353 files changed, 23161 insertions, 8335 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d46f1da18a3c..0c55582a49c3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -716,7 +716,6 @@ config CAVIUM_OCTEON_SIMULATOR
         select DMA_COHERENT
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_HIGHMEM
         select SYS_SUPPORTS_HOTPLUG_CPU
         select SYS_HAS_CPU_CAVIUM_OCTEON
         select HOLES_IN_ZONE
@@ -732,7 +731,6 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
         select DMA_COHERENT
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
-        select SYS_SUPPORTS_HIGHMEM
         select SYS_SUPPORTS_HOTPLUG_CPU
         select SYS_HAS_EARLY_PRINTK
         select SYS_HAS_CPU_CAVIUM_OCTEON
@@ -761,7 +759,6 @@ config NLM_XLR_BOARD
         depends on EXPERIMENTAL
         select BOOT_ELF32
         select NLM_COMMON
-        select NLM_XLR
         select SYS_HAS_CPU_XLR
         select SYS_SUPPORTS_SMP
         select HW_HAS_PCI
@@ -776,6 +773,7 @@ config NLM_XLR_BOARD
         select CEVT_R4K
         select CSRC_R4K
         select IRQ_CPU
+        select ARCH_SUPPORTS_MSI
         select ZONE_DMA if 64BIT
         select SYNC_R4K
         select SYS_HAS_EARLY_PRINTK
@@ -783,6 +781,33 @@ config NLM_XLR_BOARD
           Support for systems based on Netlogic XLR and XLS processors.
           Say Y here if you have a XLR or XLS based board.
 
+config NLM_XLP_BOARD
+        bool "Netlogic XLP based systems"
+        depends on EXPERIMENTAL
+        select BOOT_ELF32
+        select NLM_COMMON
+        select SYS_HAS_CPU_XLP
+        select SYS_SUPPORTS_SMP
+        select HW_HAS_PCI
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_64BIT_KERNEL
+        select 64BIT_PHYS_ADDR
+        select SYS_SUPPORTS_BIG_ENDIAN
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_HIGHMEM
+        select DMA_COHERENT
+        select NR_CPUS_DEFAULT_32
+        select CEVT_R4K
+        select CSRC_R4K
+        select IRQ_CPU
+        select ZONE_DMA if 64BIT
+        select SYNC_R4K
+        select SYS_HAS_EARLY_PRINTK
+        help
+          This board is based on Netlogic XLP Processor.
+          Say Y here if you have a XLP based board.
+
 endchoice
 
 source "arch/mips/alchemy/Kconfig"
@@ -1413,51 +1438,36 @@ config CPU_CAVIUM_OCTEON
 config CPU_BMIPS3300
         bool "BMIPS3300"
         depends on SYS_HAS_CPU_BMIPS3300
-        select DMA_NONCOHERENT
-        select IRQ_CPU
-        select SWAP_IO_SPACE
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select WEAK_ORDERING
+        select CPU_BMIPS
         help
           Broadcom BMIPS3300 processors.
 
 config CPU_BMIPS4350
         bool "BMIPS4350"
         depends on SYS_HAS_CPU_BMIPS4350
-        select CPU_SUPPORTS_32BIT_KERNEL
-        select DMA_NONCOHERENT
-        select IRQ_CPU
-        select SWAP_IO_SPACE
+        select CPU_BMIPS
         select SYS_SUPPORTS_SMP
         select SYS_SUPPORTS_HOTPLUG_CPU
-        select WEAK_ORDERING
         help
           Broadcom BMIPS4350 ("VIPER") processors.
 
 config CPU_BMIPS4380
         bool "BMIPS4380"
         depends on SYS_HAS_CPU_BMIPS4380
-        select CPU_SUPPORTS_32BIT_KERNEL
-        select DMA_NONCOHERENT
-        select IRQ_CPU
-        select SWAP_IO_SPACE
+        select CPU_BMIPS
         select SYS_SUPPORTS_SMP
         select SYS_SUPPORTS_HOTPLUG_CPU
-        select WEAK_ORDERING
         help
           Broadcom BMIPS4380 processors.
 
 config CPU_BMIPS5000
         bool "BMIPS5000"
         depends on SYS_HAS_CPU_BMIPS5000
-        select CPU_SUPPORTS_32BIT_KERNEL
+        select CPU_BMIPS
         select CPU_SUPPORTS_HIGHMEM
-        select DMA_NONCOHERENT
-        select IRQ_CPU
-        select SWAP_IO_SPACE
+        select MIPS_CPU_SCACHE
         select SYS_SUPPORTS_SMP
         select SYS_SUPPORTS_HOTPLUG_CPU
-        select WEAK_ORDERING
         help
           Broadcom BMIPS5000 processors.
 
@@ -1472,6 +1482,19 @@ config CPU_XLR
         select CPU_SUPPORTS_HUGEPAGES
         help
           Netlogic Microsystems XLR/XLS processors.
+
+config CPU_XLP
+        bool "Netlogic XLP SoC"
+        depends on SYS_HAS_CPU_XLP
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
+        select CPU_HAS_LLSC
+        select WEAK_ORDERING
+        select WEAK_REORDERING_BEYOND_LLSC
+        select CPU_HAS_PREFETCH
+        help
+          Netlogic Microsystems XLP processors.
 endchoice
 
 if CPU_LOONGSON2F
@@ -1518,6 +1541,15 @@ config CPU_LOONGSON2
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
 
+config CPU_BMIPS
+        bool
+        select CPU_MIPS32
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select WEAK_ORDERING
+
 config SYS_HAS_CPU_LOONGSON2E
         bool
 
@@ -1605,6 +1637,9 @@ config SYS_HAS_CPU_BMIPS5000
 config SYS_HAS_CPU_XLR
         bool
 
+config SYS_HAS_CPU_XLP
+        bool
+
 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -1992,6 +2027,9 @@ config CPU_HAS_SMARTMIPS
 config CPU_HAS_WB
         bool
 
+config XKS01
+        bool
+
 #
 # Vectored interrupt mode is an R2 feature
 #
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 0be318609fc6..4fedf5a51d96 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -157,6 +157,7 @@ ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
 cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
 endif
 cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
+cflags-$(CONFIG_CPU_BMIPS)      += -march=mips32 -Wa,-mips32 -Wa,--trap
 
 cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)  += $(call cc-option,-mfix-r4000,)
 cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)  += $(call cc-option,-mfix-r4400,)
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 2a68be6a1b97..0faaab24376e 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -2,6 +2,10 @@
 config ALCHEMY_GPIOINT_AU1000
         bool
 
+# au1300-style GPIO/INT controller
+config ALCHEMY_GPIOINT_AU1300
+        bool
+
 # select this in your board config if you don't want to use the gpio
 # namespace as documented in the manuals.  In this case however you need
 # to create the necessary gpio_* functions in your board code/headers!
@@ -22,43 +26,29 @@ config MIPS_MTX1
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
 
-config MIPS_BOSPORUS
-        bool "Alchemy Bosporus board"
-        select ALCHEMY_GPIOINT_AU1000
-        select DMA_NONCOHERENT
-        select SYS_SUPPORTS_LITTLE_ENDIAN
-        select SYS_HAS_EARLY_PRINTK
-
 config MIPS_DB1000
-        bool "Alchemy DB1000 board"
+        bool "Alchemy DB1000/DB1500/DB1100 boards"
         select ALCHEMY_GPIOINT_AU1000
         select DMA_NONCOHERENT
         select HW_HAS_PCI
-        select SYS_SUPPORTS_LITTLE_ENDIAN
-        select SYS_HAS_EARLY_PRINTK
-
-config MIPS_DB1100
-        bool "Alchemy DB1100 board"
-        select ALCHEMY_GPIOINT_AU1000
-        select DMA_NONCOHERENT
+        select MIPS_DISABLE_OBSOLETE_IDE
+        select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
 
 config MIPS_DB1200
-        bool "Alchemy DB1200 board"
+        bool "Alchemy DB1200/PB1200 board"
         select ALCHEMY_GPIOINT_AU1000
         select DMA_COHERENT
         select MIPS_DISABLE_OBSOLETE_IDE
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
 
-config MIPS_DB1500
-        bool "Alchemy DB1500 board"
-        select ALCHEMY_GPIOINT_AU1000
-        select DMA_NONCOHERENT
-        select HW_HAS_PCI
+config MIPS_DB1300
+        bool "NetLogic DB1300 board"
+        select ALCHEMY_GPIOINT_AU1300
+        select DMA_COHERENT
         select MIPS_DISABLE_OBSOLETE_IDE
-        select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
 
@@ -66,27 +56,11 @@ config MIPS_DB1550
         bool "Alchemy DB1550 board"
         select ALCHEMY_GPIOINT_AU1000
         select HW_HAS_PCI
-        select DMA_NONCOHERENT
+        select DMA_COHERENT
         select MIPS_DISABLE_OBSOLETE_IDE
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
 
-config MIPS_MIRAGE
-        bool "Alchemy Mirage board"
-        select DMA_NONCOHERENT
-        select ALCHEMY_GPIOINT_AU1000
-        select SYS_SUPPORTS_LITTLE_ENDIAN
-        select SYS_HAS_EARLY_PRINTK
-
-config MIPS_PB1000
-        bool "Alchemy PB1000 board"
-        select ALCHEMY_GPIOINT_AU1000
-        select DMA_NONCOHERENT
-        select HW_HAS_PCI
-        select SWAP_IO_SPACE
-        select SYS_SUPPORTS_LITTLE_ENDIAN
-        select SYS_HAS_EARLY_PRINTK
-
 config MIPS_PB1100
         bool "Alchemy PB1100 board"
         select ALCHEMY_GPIOINT_AU1000
@@ -96,14 +70,6 @@ config MIPS_PB1100
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
 
-config MIPS_PB1200
-        bool "Alchemy PB1200 board"
-        select ALCHEMY_GPIOINT_AU1000
-        select DMA_NONCOHERENT
-        select MIPS_DISABLE_OBSOLETE_IDE
-        select SYS_SUPPORTS_LITTLE_ENDIAN
-        select SYS_HAS_EARLY_PRINTK
-
 config MIPS_PB1500
         bool "Alchemy PB1500 board"
         select ALCHEMY_GPIOINT_AU1000
diff --git a/arch/mips/alchemy/Makefile b/arch/mips/alchemy/Makefile
new file mode 100644
index 000000000000..aac3b179bbc0
--- /dev/null
+++ b/arch/mips/alchemy/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_MIPS_GPR) += board-gpr.o
+obj-$(CONFIG_MIPS_MTX1) += board-mtx1.o
+obj-$(CONFIG_MIPS_XXS1500) += board-xxs1500.o
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index 96e9e41f1b2a..7956274de15f 100644
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -5,62 +5,31 @@ platform-$(CONFIG_MIPS_ALCHEMY)	+= alchemy/common/
 
 
 #
-# AMD Alchemy Pb1000 eval board
-#
-platform-$(CONFIG_MIPS_PB1000)  += alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1000)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1000)      += 0xffffffff80100000
-
-#
 # AMD Alchemy Pb1100 eval board
 #
 platform-$(CONFIG_MIPS_PB1100)  += alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1100)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1100)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Pb1500 eval board
 #
 platform-$(CONFIG_MIPS_PB1500)  += alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1500)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1500)      += 0xffffffff80100000
 
 #
 # AMD Alchemy Pb1550 eval board
 #
 platform-$(CONFIG_MIPS_PB1550)  += alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1550)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
 load-$(CONFIG_MIPS_PB1550)      += 0xffffffff80100000
 
 #
-# AMD Alchemy Pb1200 eval board
-#
-platform-$(CONFIG_MIPS_PB1200)  += alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1200)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1200)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1000 eval board
+# AMD Alchemy Db1000/Db1500/Db1100 eval boards
 #
 platform-$(CONFIG_MIPS_DB1000)  += alchemy/devboards/
 cflags-$(CONFIG_MIPS_DB1000)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
 load-$(CONFIG_MIPS_DB1000)      += 0xffffffff80100000
 
 #
-# AMD Alchemy Db1100 eval board
-#
-platform-$(CONFIG_MIPS_DB1100)  += alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1100)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1100)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1500 eval board
-#
-platform-$(CONFIG_MIPS_DB1500)  += alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1500)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1500)      += 0xffffffff80100000
-
-#
 # AMD Alchemy Db1550 eval board
 #
 platform-$(CONFIG_MIPS_DB1550)  += alchemy/devboards/
@@ -68,42 +37,35 @@ cflags-$(CONFIG_MIPS_DB1550)	+= -I$(srctree)/arch/mips/include/asm/mach-db1x00
 load-$(CONFIG_MIPS_DB1550)      += 0xffffffff80100000
 
 #
-# AMD Alchemy Db1200 eval board
+# AMD Alchemy Db1200/Pb1200 eval boards
 #
 platform-$(CONFIG_MIPS_DB1200)  += alchemy/devboards/
 cflags-$(CONFIG_MIPS_DB1200)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
 load-$(CONFIG_MIPS_DB1200)      += 0xffffffff80100000
 
 #
-# AMD Alchemy Bosporus eval board
-#
-platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/
-cflags-$(CONFIG_MIPS_BOSPORUS)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_BOSPORUS)     += 0xffffffff80100000
-
-#
-# AMD Alchemy Mirage eval board
+# NetLogic DBAu1300 development platform
 #
-platform-$(CONFIG_MIPS_MIRAGE)  += alchemy/devboards/
-cflags-$(CONFIG_MIPS_MIRAGE)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_MIRAGE)      += 0xffffffff80100000
+platform-$(CONFIG_MIPS_DB1300)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1300)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1300)      += 0xffffffff80100000
 
 #
-# 4G-Systems eval board
+# 4G-Systems MTX-1 "MeshCube" wireless router
 #
-platform-$(CONFIG_MIPS_MTX1)    += alchemy/mtx-1/
+platform-$(CONFIG_MIPS_MTX1)    += alchemy/
 load-$(CONFIG_MIPS_MTX1)        += 0xffffffff80100000
 
 #
 # MyCable eval board
 #
-platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/
+platform-$(CONFIG_MIPS_XXS1500) += alchemy/
 load-$(CONFIG_MIPS_XXS1500)     += 0xffffffff80100000
 
 #
 # Trapeze ITS GRP board
 #
-platform-$(CONFIG_MIPS_GPR)     += alchemy/gpr/
+platform-$(CONFIG_MIPS_GPR)     += alchemy/
 load-$(CONFIG_MIPS_GPR)         += 0xffffffff80100000
 
 # boards can specify their own <gpio.h> in one of their include dirs.
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/board-gpr.c
index 982ce85db60d..ba3259086b9d 100644
--- a/arch/mips/alchemy/gpr/platform.c
+++ b/arch/mips/alchemy/board-gpr.c
@@ -1,5 +1,5 @@
 /*
- * GPR board platform device registration
+ * GPR board platform device registration (Au1550)
  *
  * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
  *
@@ -18,16 +18,89 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/pm.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/leds.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
-
+#include <asm/bootinfo.h>
+#include <asm/reboot.h>
 #include <asm/mach-au1x00/au1000.h>
+#include <prom.h>
+
+const char *get_system_type(void)
+{
+        return "GPR";
+}
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str)
+                memsize = 0x04000000;
+        else
+                strict_strtoul(memsize_str, 0, &memsize);
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+}
+
+static void gpr_reset(char *c)
+{
+        /* switch System-LED to orange (red# and green# on) */
+        alchemy_gpio_direction_output(4, 0);
+        alchemy_gpio_direction_output(5, 0);
+
+        /* trigger watchdog to reset board in 200ms */
+        printk(KERN_EMERG "Triggering watchdog soft reset...\n");
+        raw_local_irq_disable();
+        alchemy_gpio_direction_output(1, 0);
+        udelay(1);
+        alchemy_gpio_set_value(1, 1);
+        while (1)
+                cpu_wait();
+}
+
+static void gpr_power_off(void)
+{
+        while (1)
+                cpu_wait();
+}
+
+void __init board_setup(void)
+{
+        printk(KERN_INFO "Trapeze ITS GPR board\n");
+
+        pm_power_off = gpr_power_off;
+        _machine_halt = gpr_power_off;
+        _machine_restart = gpr_reset;
+
+        /* Enable UART1/3 */
+        alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
+        alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
+
+        /* Take away Reset of UMTS-card */
+        alchemy_gpio_direction_output(215, 1);
+}
 
 /*
  * Watchdog
@@ -152,7 +225,7 @@ static struct i2c_gpio_platform_data gpr_i2c_data = {
         .scl_is_open_drain      = 1,
         .udelay                 = 2,            /* ~100 kHz */
         .timeout                = HZ,
- };
+};
 
 static struct platform_device gpr_i2c_device = {
         .name                   = "i2c-gpio",
@@ -184,7 +257,7 @@ static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
         else if ((slot == 0) && (pin == 2))
                 return AU1550_PCI_INTB;
 
-        return -1;
+        return 0xff;
 }
 
 static struct alchemy_pci_platdata gpr_pci_pd = {
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/board-mtx1.c
index cc47b6868ca3..295f1a95f745 100644
--- a/arch/mips/alchemy/mtx-1/platform.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -1,5 +1,5 @@
 /*
- * MTX-1 platform devices registration
+ * MTX-1 platform devices registration (Au1500)
  *
  * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org>
  *
@@ -19,6 +19,8 @@
  */
 
 #include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/gpio.h>
@@ -27,8 +29,85 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <mtd/mtd-abi.h>
-
+#include <asm/bootinfo.h>
+#include <asm/reboot.h>
+#include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/au1xxx_eth.h>
+#include <prom.h>
+
+const char *get_system_type(void)
+{
+        return "MTX-1";
+}
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str)
+                memsize = 0x04000000;
+        else
+                strict_strtoul(memsize_str, 0, &memsize);
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+}
+
+static void mtx1_reset(char *c)
+{
+        /* Jump to the reset vector */
+        __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000));
+}
+
+static void mtx1_power_off(void)
+{
+        while (1)
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
+}
+
+void __init board_setup(void)
+{
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+        /* Enable USB power switch */
+        alchemy_gpio_direction_output(204, 0);
+#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
+
+        /* Initialize sys_pinfunc */
+        au_writel(SYS_PF_NI2, SYS_PINFUNC);
+
+        /* Initialize GPIO */
+        au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
+        alchemy_gpio_direction_output(0, 0);    /* Disable M66EN (PCI 66MHz) */
+        alchemy_gpio_direction_output(3, 1);    /* Disable PCI CLKRUN# */
+        alchemy_gpio_direction_output(1, 1);    /* Enable EXT_IO3 */
+        alchemy_gpio_direction_output(5, 0);    /* Disable eth PHY TX_ER */
+
+        /* Enable LED and set it to green */
+        alchemy_gpio_direction_output(211, 1);  /* green on */
+        alchemy_gpio_direction_output(212, 0);  /* red off */
+
+        pm_power_off = mtx1_power_off;
+        _machine_halt = mtx1_power_off;
+        _machine_restart = mtx1_reset;
+
+        printk(KERN_INFO "4G Systems MTX-1 Board\n");
+}
+
+/******************************************************************************/
 
 static struct gpio_keys_button mtx1_gpio_button[] = {
         {
@@ -195,7 +274,6 @@ static struct platform_device mtx1_pci_host = {
         .resource       = alchemy_pci_host_res,
 };
 
-
 static struct __initdata platform_device * mtx1_devs[] = {
         &mtx1_pci_host,
         &mtx1_gpio_leds,
@@ -206,13 +284,19 @@ static struct __initdata platform_device * mtx1_devs[] = {
 
 static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = {
         .phy_search_highest_addr        = 1,
-        .phy1_search_mac0               = 1,
+        .phy1_search_mac0               = 1,
 };
 
 static int __init mtx1_register_devices(void)
 {
         int rc;
 
+        irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH);
+        irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
+
         au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata);
 
         rc = gpio_request(mtx1_gpio_button[0].gpio,
@@ -226,5 +310,4 @@ static int __init mtx1_register_devices(void)
 out:
         return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
 }
-
 arch_initcall(mtx1_register_devices);
diff --git a/arch/mips/alchemy/board-xxs1500.c b/arch/mips/alchemy/board-xxs1500.c
new file mode 100644
index 000000000000..bd5513650293
--- /dev/null
+++ b/arch/mips/alchemy/board-xxs1500.c
@@ -0,0 +1,154 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      MyCable XXS1500 board support
+ *
+ * Copyright 2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <asm/bootinfo.h>
+#include <asm/reboot.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <prom.h>
+
+const char *get_system_type(void)
+{
+        return "XXS1500";
+}
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
+                memsize = 0x04000000;
+
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+}
+
+static void xxs1500_reset(char *c)
+{
+        /* Jump to the reset vector */
+        __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000));
+}
+
+static void xxs1500_power_off(void)
+{
+        while (1)
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
+}
+
+void __init board_setup(void)
+{
+        u32 pin_func;
+
+        pm_power_off = xxs1500_power_off;
+        _machine_halt = xxs1500_power_off;
+        _machine_restart = xxs1500_reset;
+
+        alchemy_gpio1_input_enable();
+        alchemy_gpio2_enable();
+
+        /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
+        pin_func  = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
+        pin_func |= SYS_PF_UR3;
+        au_writel(pin_func, SYS_PINFUNC);
+
+        /* Enable UART */
+        alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
+        /* Enable DTR (MCR bit 0) = USB power up */
+        __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
+        wmb();
+}
+
+/******************************************************************************/
+
+static struct resource xxs1500_pcmcia_res[] = {
+        {
+                .name   = "pcmcia-io",
+                .flags  = IORESOURCE_MEM,
+                .start  = AU1000_PCMCIA_IO_PHYS_ADDR,
+                .end    = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
+        },
+        {
+                .name   = "pcmcia-attr",
+                .flags  = IORESOURCE_MEM,
+                .start  = AU1000_PCMCIA_ATTR_PHYS_ADDR,
+                .end    = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+        },
+        {
+                .name   = "pcmcia-mem",
+                .flags  = IORESOURCE_MEM,
+                .start  = AU1000_PCMCIA_MEM_PHYS_ADDR,
+                .end    = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+        },
+};
+
+static struct platform_device xxs1500_pcmcia_dev = {
+        .name           = "xxs1500_pcmcia",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(xxs1500_pcmcia_res),
+        .resource       = xxs1500_pcmcia_res,
+};
+
+static struct platform_device *xxs1500_devs[] __initdata = {
+        &xxs1500_pcmcia_dev,
+};
+
+static int __init xxs1500_dev_init(void)
+{
+        irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_HIGH);
+        irq_set_irq_type(AU1500_GPIO201_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO202_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO203_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO207_INT, IRQ_TYPE_LEVEL_LOW);
+
+        irq_set_irq_type(AU1500_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO2_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(AU1500_GPIO4_INT, IRQ_TYPE_LEVEL_LOW); /* CF irq */
+        irq_set_irq_type(AU1500_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);
+
+        return platform_add_devices(xxs1500_devs,
+                                    ARRAY_SIZE(xxs1500_devs));
+}
+device_initcall(xxs1500_dev_init);
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 811ece7b22e3..407ebc00e661 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -6,9 +6,7 @@
 #
 
 obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
-        sleeper.o dma.o dbdma.o
-
-obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
+        sleeper.o dma.o dbdma.o vss.o irq.o
 
 # optional gpiolib support
 ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 0e63ee487d6d..cf02d7dc2df0 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -148,6 +148,50 @@ static dbdev_tab_t au1200_dbdev_tab[] __initdata = {
         { DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
 };
 
+static dbdev_tab_t au1300_dbdev_tab[] __initdata = {
+        { AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8,  0x10100004, 0, 0 },
+        { AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN,  0, 8,  0x10100000, 0, 0 },
+        { AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8,  0x10101004, 0, 0 },
+        { AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN,  0, 8,  0x10101000, 0, 0 },
+        { AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8,  0x10102004, 0, 0 },
+        { AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN,  0, 8,  0x10102000, 0, 0 },
+        { AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8,  0x10103004, 0, 0 },
+        { AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN,  0, 8,  0x10103000, 0, 0 },
+
+        { AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8,  0x10600000, 0, 0 },
+        { AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN,  4, 8,  0x10600004, 0, 0 },
+        { AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8,  0x10601000, 0, 0 },
+        { AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN,  8, 8,  0x10601004, 0, 0 },
+
+        { AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN ,   4, 32, 0x10300008, 0, 0 },
+        { AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT,   4, 32, 0x10300004, 0, 0 },
+
+        { AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0001c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN,   0, 16, 0x10a0001c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0101c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN,   0, 16, 0x10a0101c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0201c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN,   0, 16, 0x10a0201c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0301c, 0, 0 },
+        { AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN,   0, 16, 0x10a0301c, 0, 0 },
+
+        { AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE,   0, 0,  0x00000000, 0, 0 },
+        { AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+
+        { AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8,  0x10602000, 0, 0 },
+        { AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN,  4, 8,  0x10602004, 0, 0 },
+
+        { AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+
+        { AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE,  0, 32, 0x14001810, 0, 0 },
+
+        { AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
+        { AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
+
+        { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+        { DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+};
+
 /* 32 predefined plus 32 custom */
 #define DBDEV_TAB_SIZE          64
 
@@ -1019,8 +1063,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
         dbdma_gptr->ddma_inten = 0xffff;
         au_sync();
 
-        ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma",
-                          (void *)dbdma_gptr);
+        ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);
         if (ret)
                 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
         else {
@@ -1038,6 +1081,8 @@ static int __init alchemy_dbdma_init(void)
                 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
         case ALCHEMY_CPU_AU1200:
                 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
+        case ALCHEMY_CPU_AU1300:
+                return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab);
         }
         return 0;
 }
diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c
index 91fb4d9e30fd..f1b50f0c01db 100644
--- a/arch/mips/alchemy/common/gpiolib.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -27,6 +27,7 @@
  *       CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail!
  *      au1000 SoC have only one GPIO block : GPIO1
  *      Au1100, Au15x0, Au12x0 have a second one : GPIO2
+ *      Au1300 is totally different: 1 block with up to 128 GPIOs
  */
 
 #include <linux/init.h>
@@ -35,6 +36,7 @@
 #include <linux/types.h>
 #include <linux/gpio.h>
 #include <asm/mach-au1x00/gpio-au1000.h>
+#include <asm/mach-au1x00/gpio-au1300.h>
 
 static int gpio2_get(struct gpio_chip *chip, unsigned offset)
 {
@@ -115,6 +117,43 @@ struct gpio_chip alchemy_gpio_chip[] = {
         },
 };
 
+static int alchemy_gpic_get(struct gpio_chip *chip, unsigned int off)
+{
+        return au1300_gpio_get_value(off + AU1300_GPIO_BASE);
+}
+
+static void alchemy_gpic_set(struct gpio_chip *chip, unsigned int off, int v)
+{
+        au1300_gpio_set_value(off + AU1300_GPIO_BASE, v);
+}
+
+static int alchemy_gpic_dir_input(struct gpio_chip *chip, unsigned int off)
+{
+        return au1300_gpio_direction_input(off + AU1300_GPIO_BASE);
+}
+
+static int alchemy_gpic_dir_output(struct gpio_chip *chip, unsigned int off,
+                                   int v)
+{
+        return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v);
+}
+
+static int alchemy_gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off)
+{
+        return au1300_gpio_to_irq(off + AU1300_GPIO_BASE);
+}
+
+static struct gpio_chip au1300_gpiochip = {
+        .label                  = "alchemy-gpic",
+        .direction_input        = alchemy_gpic_dir_input,
+        .direction_output       = alchemy_gpic_dir_output,
+        .get                    = alchemy_gpic_get,
+        .set                    = alchemy_gpic_set,
+        .to_irq                 = alchemy_gpic_gpio_to_irq,
+        .base                   = AU1300_GPIO_BASE,
+        .ngpio                  = AU1300_GPIO_NUM,
+};
+
 static int __init alchemy_gpiochip_init(void)
 {
         int ret = 0;
@@ -127,6 +166,9 @@ static int __init alchemy_gpiochip_init(void)
                 ret = gpiochip_add(&alchemy_gpio_chip[0]);
                 ret |= gpiochip_add(&alchemy_gpio_chip[1]);
                 break;
+        case ALCHEMY_CPU_AU1300:
+                ret = gpiochip_add(&au1300_gpiochip);
+                break;
         }
         return ret;
 }
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 8b60ba0675e2..94fbcd19eb9c 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -25,19 +25,15 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/bitops.h>
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/irq.h>
 #include <linux/slab.h>
 #include <linux/syscore_ops.h>
 
 #include <asm/irq_cpu.h>
-#include <asm/mipsregs.h>
 #include <asm/mach-au1x00/au1000.h>
-#ifdef CONFIG_MIPS_PB1000
-#include <asm/mach-pb1x00/pb1000.h>
-#endif
+#include <asm/mach-au1x00/gpio-au1300.h>
 
 /* Interrupt Controller register offsets */
 #define IC_CFG0RD       0x40
@@ -69,7 +65,17 @@
 #define IC_FALLINGCLR   0x7C
 #define IC_TESTBIT      0x80
 
-static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type);
+/* per-processor fixed function irqs */
+struct alchemy_irqmap {
+        int irq;        /* linux IRQ number */
+        int type;       /* IRQ_TYPE_ */
+        int prio;       /* irq priority, 0 highest, 3 lowest */
+        int internal;   /* GPIC: internal source (no ext. pin)? */
+};
+
+static int au1x_ic_settype(struct irq_data *d, unsigned int type);
+static int au1300_gpic_settype(struct irq_data *d, unsigned int type);
+
 
 /* NOTE on interrupt priorities: The original writers of this code said:
  *
@@ -77,176 +83,207 @@ static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type);
  * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT)
  * needs the highest priority.
  */
-
-/* per-processor fixed function irqs */
-struct au1xxx_irqmap {
-        int im_irq;
-        int im_type;
-        int im_request;         /* set 1 to get higher priority */
+struct alchemy_irqmap au1000_irqmap[] __initdata = {
+        { AU1000_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_UART2_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1000_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1000_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1000_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1000_RTC_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1000_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1000_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1000_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
+        { AU1000_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
+        { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1000_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1000_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1000_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1000_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { -1, },
 };
 
-struct au1xxx_irqmap au1000_irqmap[] __initdata = {
-        { AU1000_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_UART2_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
-        { AU1000_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
-        { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1000_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1000_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
+struct alchemy_irqmap au1500_irqmap[] __initdata = {
+        { AU1500_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1500_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1500_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1500_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1500_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1500_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1500_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1500_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1500_RTC_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1500_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1500_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1500_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
+        { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
+        { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1500_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1500_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1500_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1500_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 1, 0 },
         { -1, },
 };
 
-struct au1xxx_irqmap au1500_irqmap[] __initdata = {
-        { AU1500_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1500_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1500_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1500_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1500_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1500_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1500_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1500_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1500_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1500_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1500_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1500_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
-        { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
-        { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1500_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1500_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1500_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1500_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
+struct alchemy_irqmap au1100_irqmap[] __initdata = {
+        { AU1100_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1100_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1100_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1100_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1100_RTC_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1100_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1100_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1100_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
+        { AU1100_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
+        { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1100_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1100_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1100_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1100_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 1, 0 },
         { -1, },
 };
 
-struct au1xxx_irqmap au1100_irqmap[] __initdata = {
-        { AU1100_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1100_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1100_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1100_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1100_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1100_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1100_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1100_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
-        { AU1100_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
-        { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1100_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1100_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1100_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1100_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
+struct alchemy_irqmap au1550_irqmap[] __initdata = {
+        { AU1550_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1550_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1550_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1550_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1550_CRYPTO_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1550_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1550_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1550_PCI_RST_INT,     IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1550_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1550_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1550_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1550_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1550_PSC2_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1550_PSC3_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1550_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1550_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1550_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1550_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1550_RTC_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1550_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1550_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1550_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
+        { AU1550_NAND_INT,        IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
+        { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1550_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
+        { AU1550_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1550_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
         { -1, },
 };
 
-struct au1xxx_irqmap au1550_irqmap[] __initdata = {
-        { AU1550_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1550_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1550_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1550_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1550_CRYPTO_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1550_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1550_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1550_PCI_RST_INT,     IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1550_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1550_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1550_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1550_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1550_PSC2_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1550_PSC3_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1550_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
-        { AU1550_NAND_INT,        IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
-        { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
-        { AU1550_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1550_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
+struct alchemy_irqmap au1200_irqmap[] __initdata = {
+        { AU1200_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_SWT_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1200_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_MAE_BE_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_MAE_FE_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_AES_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_CAMERA_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1200_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1200_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1200_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1200_RTC_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1200_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1200_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1200_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
+        { AU1200_NAND_INT,        IRQ_TYPE_EDGE_RISING, 1, 0 },
+        { AU1200_USB_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+        { AU1200_MAE_BOTH_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
         { -1, },
 };
 
-struct au1xxx_irqmap au1200_irqmap[] __initdata = {
-        { AU1200_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_SWT_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_MAE_BE_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_MAE_FE_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_AES_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_CAMERA_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
-        { AU1200_NAND_INT,        IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_USB_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
-        { AU1200_MAE_BOTH_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
-        { -1, },
+static struct alchemy_irqmap au1300_irqmap[] __initdata = {
+        /* multifunction: gpio pin or device */
+        { AU1300_UART1_INT,      IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_UART2_INT,      IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_UART3_INT,      IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_SD1_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_SD2_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_PSC0_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_PSC1_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_PSC2_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_PSC3_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        { AU1300_NAND_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 0, },
+        /* au1300 internal */
+        { AU1300_DDMA_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_MMU_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_MPU_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_GPU_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_UDMA_INT,       IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_TOY_INT,        IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_RTC_INT,        IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING,  0, 1, },
+        { AU1300_UART0_INT,      IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_SD0_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_USB_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_LCD_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_BSA_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_MPE_INT,        IRQ_TYPE_EDGE_RISING,  1, 1, },
+        { AU1300_ITE_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_AES_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { AU1300_CIM_INT,        IRQ_TYPE_LEVEL_HIGH,   1, 1, },
+        { -1, },        /* terminator */
 };
 
+/******************************************************************************/
 
 static void au1x_ic0_unmask(struct irq_data *d)
 {
@@ -265,14 +302,6 @@ static void au1x_ic1_unmask(struct irq_data *d)
 
         __raw_writel(1 << bit, base + IC_MASKSET);
         __raw_writel(1 << bit, base + IC_WAKESET);
-
-/* very hacky. does the pb1000 cpld auto-disable this int?
- * nowhere in the current kernel sources is it disabled.        --mlau
- */
-#if defined(CONFIG_MIPS_PB1000)
-        if (d->irq == AU1000_GPIO15_INT)
-                __raw_writel(0x4000, (void __iomem *)PB1000_MDR); /* enable int */
-#endif
         wmb();
 }
 
@@ -470,40 +499,219 @@ static int au1x_ic_settype(struct irq_data *d, unsigned int flow_type)
         return ret;
 }
 
-asmlinkage void plat_irq_dispatch(void)
+/******************************************************************************/
+
+/*
+ * au1300_gpic_chgcfg - change PIN configuration.
+ * @gpio:       pin to change (0-based GPIO number from datasheet).
+ * @clr:        clear all bits set in 'clr'.
+ * @set:        set these bits.
+ *
+ * modifies a pins' configuration register, bits set in @clr will
+ * be cleared in the register, bits in @set will be set.
+ */
+static inline void au1300_gpic_chgcfg(unsigned int gpio,
+                                      unsigned long clr,
+                                      unsigned long set)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long l;
+
+        r += gpio * 4;  /* offset into pin config array */
+        l = __raw_readl(r + AU1300_GPIC_PINCFG);
+        l &= ~clr;
+        l |= set;
+        __raw_writel(l, r + AU1300_GPIC_PINCFG);
+        wmb();
+}
+
+/*
+ * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl).
+ * @pin:        pin (0-based GPIO number from datasheet).
+ *
+ * Assigns a GPIO pin to the GPIO controller, so its level can either
+ * be read or set through the generic GPIO functions.
+ * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1).
+ * REVISIT: is this function really necessary?
+ */
+void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio)
+{
+        au1300_gpio_direction_input(gpio + AU1300_GPIO_BASE);
+}
+EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio);
+
+/*
+ * au1300_pinfunc_to_dev - assign a pin to the device function.
+ * @pin:        pin (0-based GPIO number from datasheet).
+ *
+ * Assigns a GPIO pin to its associated device function; the pin will be
+ * driven by the device and not through GPIO functions.
+ */
+void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long bit;
+
+        r += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        __raw_writel(bit, r + AU1300_GPIC_DEVSEL);
+        wmb();
+}
+EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev);
+
+/*
+ * au1300_set_irq_priority -  set internal priority of IRQ.
+ * @irq:        irq to set priority (linux irq number).
+ * @p:          priority (0 = highest, 3 = lowest).
+ */
+void au1300_set_irq_priority(unsigned int irq, int p)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
-        unsigned long s, off;
-
-        if (pending & CAUSEF_IP7) {
-                off = MIPS_CPU_IRQ_BASE + 7;
-                goto handle;
-        } else if (pending & CAUSEF_IP2) {
-                s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ0INT;
-                off = AU1000_INTC0_INT_BASE;
-        } else if (pending & CAUSEF_IP3) {
-                s = KSEG1ADDR(AU1000_IC0_PHYS_ADDR) + IC_REQ1INT;
-                off = AU1000_INTC0_INT_BASE;
-        } else if (pending & CAUSEF_IP4) {
-                s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ0INT;
-                off = AU1000_INTC1_INT_BASE;
-        } else if (pending & CAUSEF_IP5) {
-                s = KSEG1ADDR(AU1000_IC1_PHYS_ADDR) + IC_REQ1INT;
-                off = AU1000_INTC1_INT_BASE;
-        } else
-                goto spurious;
-
-        s = __raw_readl((void __iomem *)s);
-        if (unlikely(!s)) {
-spurious:
-                spurious_interrupt();
-                return;
+        irq -= ALCHEMY_GPIC_INT_BASE;
+        au1300_gpic_chgcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p));
+}
+EXPORT_SYMBOL_GPL(au1300_set_irq_priority);
+
+/*
+ * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers.
+ * @dchan:      dbdma trigger select (0, 1).
+ * @gpio:       pin to assign as trigger.
+ *
+ * DBDMA controller has 2 external trigger sources; this function
+ * assigns a GPIO to the selected trigger.
+ */
+void au1300_set_dbdma_gpio(int dchan, unsigned int gpio)
+{
+        unsigned long r;
+
+        if ((dchan >= 0) && (dchan <= 1)) {
+                r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
+                r &= ~(0xff << (8 * dchan));
+                r |= (gpio & 0x7f) << (8 * dchan);
+                __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL);
+                wmb();
         }
-        off += __ffs(s);
-handle:
-        do_IRQ(off);
 }
 
+static inline void gpic_pin_set_idlewake(unsigned int gpio, int allow)
+{
+        au1300_gpic_chgcfg(gpio, GPIC_CFG_IDLEWAKE,
+                           allow ? GPIC_CFG_IDLEWAKE : 0);
+}
+
+static void au1300_gpic_mask(struct irq_data *d)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long bit, irq = d->irq;
+
+        irq -= ALCHEMY_GPIC_INT_BASE;
+        r += GPIC_GPIO_BANKOFF(irq);
+        bit = GPIC_GPIO_TO_BIT(irq);
+        __raw_writel(bit, r + AU1300_GPIC_IDIS);
+        wmb();
+
+        gpic_pin_set_idlewake(irq, 0);
+}
+
+static void au1300_gpic_unmask(struct irq_data *d)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long bit, irq = d->irq;
+
+        irq -= ALCHEMY_GPIC_INT_BASE;
+
+        gpic_pin_set_idlewake(irq, 1);
+
+        r += GPIC_GPIO_BANKOFF(irq);
+        bit = GPIC_GPIO_TO_BIT(irq);
+        __raw_writel(bit, r + AU1300_GPIC_IEN);
+        wmb();
+}
+
+static void au1300_gpic_maskack(struct irq_data *d)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long bit, irq = d->irq;
+
+        irq -= ALCHEMY_GPIC_INT_BASE;
+        r += GPIC_GPIO_BANKOFF(irq);
+        bit = GPIC_GPIO_TO_BIT(irq);
+        __raw_writel(bit, r + AU1300_GPIC_IPEND);       /* ack */
+        __raw_writel(bit, r + AU1300_GPIC_IDIS);        /* mask */
+        wmb();
+
+        gpic_pin_set_idlewake(irq, 0);
+}
+
+static void au1300_gpic_ack(struct irq_data *d)
+{
+        void __iomem *r = AU1300_GPIC_ADDR;
+        unsigned long bit, irq = d->irq;
+
+        irq -= ALCHEMY_GPIC_INT_BASE;
+        r += GPIC_GPIO_BANKOFF(irq);
+        bit = GPIC_GPIO_TO_BIT(irq);
+        __raw_writel(bit, r + AU1300_GPIC_IPEND);       /* ack */
+        wmb();
+}
+
+static struct irq_chip au1300_gpic = {
+        .name           = "GPIOINT",
+        .irq_ack        = au1300_gpic_ack,
+        .irq_mask       = au1300_gpic_mask,
+        .irq_mask_ack   = au1300_gpic_maskack,
+        .irq_unmask     = au1300_gpic_unmask,
+        .irq_set_type   = au1300_gpic_settype,
+};
+
+static int au1300_gpic_settype(struct irq_data *d, unsigned int type)
+{
+        unsigned long s;
+        unsigned char *name = NULL;
+        irq_flow_handler_t hdl = NULL;
+
+        switch (type) {
+        case IRQ_TYPE_LEVEL_HIGH:
+                s = GPIC_CFG_IC_LEVEL_HIGH;
+                name = "high";
+                hdl = handle_level_irq;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                s = GPIC_CFG_IC_LEVEL_LOW;
+                name = "low";
+                hdl = handle_level_irq;
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                s = GPIC_CFG_IC_EDGE_RISE;
+                name = "posedge";
+                hdl = handle_edge_irq;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                s = GPIC_CFG_IC_EDGE_FALL;
+                name = "negedge";
+                hdl = handle_edge_irq;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                s = GPIC_CFG_IC_EDGE_BOTH;
+                name = "bothedge";
+                hdl = handle_edge_irq;
+                break;
+        case IRQ_TYPE_NONE:
+                s = GPIC_CFG_IC_OFF;
+                name = "disabled";
+                hdl = handle_level_irq;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        __irq_set_chip_handler_name_locked(d->irq, &au1300_gpic, hdl, name);
+
+        au1300_gpic_chgcfg(d->irq - ALCHEMY_GPIC_INT_BASE, GPIC_CFG_IC_MASK, s);
+
+        return 0;
+}
+
+/******************************************************************************/
 
 static inline void ic_init(void __iomem *base)
 {
@@ -521,13 +729,159 @@ static inline void ic_init(void __iomem *base)
         wmb();
 }
 
-static void __init au1000_init_irq(struct au1xxx_irqmap *map)
+static unsigned long alchemy_gpic_pmdata[ALCHEMY_GPIC_INT_NUM + 6];
+
+static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d)
+{
+        d[0] = __raw_readl(base + IC_CFG0RD);
+        d[1] = __raw_readl(base + IC_CFG1RD);
+        d[2] = __raw_readl(base + IC_CFG2RD);
+        d[3] = __raw_readl(base + IC_SRCRD);
+        d[4] = __raw_readl(base + IC_ASSIGNRD);
+        d[5] = __raw_readl(base + IC_WAKERD);
+        d[6] = __raw_readl(base + IC_MASKRD);
+        ic_init(base);          /* shut it up too while at it */
+}
+
+static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)
+{
+        ic_init(base);
+
+        __raw_writel(d[0], base + IC_CFG0SET);
+        __raw_writel(d[1], base + IC_CFG1SET);
+        __raw_writel(d[2], base + IC_CFG2SET);
+        __raw_writel(d[3], base + IC_SRCSET);
+        __raw_writel(d[4], base + IC_ASSIGNSET);
+        __raw_writel(d[5], base + IC_WAKESET);
+        wmb();
+
+        __raw_writel(d[6], base + IC_MASKSET);
+        wmb();
+}
+
+static int alchemy_ic_suspend(void)
+{
+        alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
+                               alchemy_gpic_pmdata);
+        alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
+                               &alchemy_gpic_pmdata[7]);
+        return 0;
+}
+
+static void alchemy_ic_resume(void)
+{
+        alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
+                              &alchemy_gpic_pmdata[7]);
+        alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
+                              alchemy_gpic_pmdata);
+}
+
+static int alchemy_gpic_suspend(void)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
+        int i;
+
+        /* save 4 interrupt mask status registers */
+        alchemy_gpic_pmdata[0] = __raw_readl(base + AU1300_GPIC_IEN + 0x0);
+        alchemy_gpic_pmdata[1] = __raw_readl(base + AU1300_GPIC_IEN + 0x4);
+        alchemy_gpic_pmdata[2] = __raw_readl(base + AU1300_GPIC_IEN + 0x8);
+        alchemy_gpic_pmdata[3] = __raw_readl(base + AU1300_GPIC_IEN + 0xc);
+
+        /* save misc register(s) */
+        alchemy_gpic_pmdata[4] = __raw_readl(base + AU1300_GPIC_DMASEL);
+
+        /* molto silenzioso */
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
+        wmb();
+
+        /* save pin/int-type configuration */
+        base += AU1300_GPIC_PINCFG;
+        for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
+                alchemy_gpic_pmdata[i + 5] = __raw_readl(base + (i << 2));
+
+        wmb();
+
+        return 0;
+}
+
+static void alchemy_gpic_resume(void)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
+        int i;
+
+        /* disable all first */
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x0);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x4);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0x8);
+        __raw_writel(~0UL, base + AU1300_GPIC_IDIS + 0xc);
+        wmb();
+
+        /* restore pin/int-type configurations */
+        base += AU1300_GPIC_PINCFG;
+        for (i = 0; i < ALCHEMY_GPIC_INT_NUM; i++)
+                __raw_writel(alchemy_gpic_pmdata[i + 5], base + (i << 2));
+        wmb();
+
+        /* restore misc register(s) */
+        base = (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR);
+        __raw_writel(alchemy_gpic_pmdata[4], base + AU1300_GPIC_DMASEL);
+        wmb();
+
+        /* finally restore masks */
+        __raw_writel(alchemy_gpic_pmdata[0], base + AU1300_GPIC_IEN + 0x0);
+        __raw_writel(alchemy_gpic_pmdata[1], base + AU1300_GPIC_IEN + 0x4);
+        __raw_writel(alchemy_gpic_pmdata[2], base + AU1300_GPIC_IEN + 0x8);
+        __raw_writel(alchemy_gpic_pmdata[3], base + AU1300_GPIC_IEN + 0xc);
+        wmb();
+}
+
+static struct syscore_ops alchemy_ic_pmops = {
+        .suspend        = alchemy_ic_suspend,
+        .resume         = alchemy_ic_resume,
+};
+
+static struct syscore_ops alchemy_gpic_pmops = {
+        .suspend        = alchemy_gpic_suspend,
+        .resume         = alchemy_gpic_resume,
+};
+
+/******************************************************************************/
+
+/* create chained handlers for the 4 IC requests to the MIPS IRQ ctrl */
+#define DISP(name, base, addr)                                                \
+static void au1000_##name##_dispatch(unsigned int irq, struct irq_desc *d)    \
+{                                                                             \
+        unsigned long r = __raw_readl((void __iomem *)KSEG1ADDR(addr));       \
+        if (likely(r))                                                        \
+                generic_handle_irq(base + __ffs(r));                          \
+        else                                                                  \
+                spurious_interrupt();                                         \
+}
+
+DISP(ic0r0, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ0INT)
+DISP(ic0r1, AU1000_INTC0_INT_BASE, AU1000_IC0_PHYS_ADDR + IC_REQ1INT)
+DISP(ic1r0, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ0INT)
+DISP(ic1r1, AU1000_INTC1_INT_BASE, AU1000_IC1_PHYS_ADDR + IC_REQ1INT)
+
+static void alchemy_gpic_dispatch(unsigned int irq, struct irq_desc *d)
+{
+        int i = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC);
+        generic_handle_irq(ALCHEMY_GPIC_INT_BASE + i);
+}
+
+/******************************************************************************/
+
+static void __init au1000_init_irq(struct alchemy_irqmap *map)
 {
         unsigned int bit, irq_nr;
         void __iomem *base;
 
         ic_init((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR));
         ic_init((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR));
+        register_syscore_ops(&alchemy_ic_pmops);
         mips_cpu_irq_init();
 
         /* register all 64 possible IC0+IC1 irq sources as type "none".
@@ -544,8 +898,8 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
         /*
          * Initialize IC0, which is fixed per processor.
          */
-        while (map->im_irq != -1) {
-                irq_nr = map->im_irq;
+        while (map->irq != -1) {
+                irq_nr = map->irq;
 
                 if (irq_nr >= AU1000_INTC1_INT_BASE) {
                         bit = irq_nr - AU1000_INTC1_INT_BASE;
@@ -554,16 +908,61 @@ static void __init au1000_init_irq(struct au1xxx_irqmap *map)
                         bit = irq_nr - AU1000_INTC0_INT_BASE;
                         base = (void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR);
                 }
-                if (map->im_request)
+                if (map->prio == 0)
                         __raw_writel(1 << bit, base + IC_ASSIGNSET);
 
-                au1x_ic_settype(irq_get_irq_data(irq_nr), map->im_type);
+                au1x_ic_settype(irq_get_irq_data(irq_nr), map->type);
                 ++map;
         }
 
-        set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, au1000_ic0r0_dispatch);
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, au1000_ic0r1_dispatch);
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, au1000_ic1r0_dispatch);
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, au1000_ic1r1_dispatch);
+}
+
+static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints)
+{
+        int i;
+        void __iomem *bank_base;
+
+        register_syscore_ops(&alchemy_gpic_pmops);
+        mips_cpu_irq_init();
+
+        /* disable & ack all possible interrupt sources */
+        for (i = 0; i < 4; i++) {
+                bank_base = AU1300_GPIC_ADDR + (i * 4);
+                __raw_writel(~0UL, bank_base + AU1300_GPIC_IDIS);
+                wmb();
+                __raw_writel(~0UL, bank_base + AU1300_GPIC_IPEND);
+                wmb();
+        }
+
+        /* register an irq_chip for them, with 2nd highest priority */
+        for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) {
+                au1300_set_irq_priority(i, 1);
+                au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE);
+        }
+
+        /* setup known on-chip sources */
+        while ((i = dints->irq) != -1) {
+                au1300_gpic_settype(irq_get_irq_data(i), dints->type);
+                au1300_set_irq_priority(i, dints->prio);
+
+                if (dints->internal)
+                        au1300_pinfunc_to_dev(i - ALCHEMY_GPIC_INT_BASE);
+
+                dints++;
+        }
+
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, alchemy_gpic_dispatch);
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, alchemy_gpic_dispatch);
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, alchemy_gpic_dispatch);
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, alchemy_gpic_dispatch);
 }
 
+/******************************************************************************/
+
 void __init arch_init_irq(void)
 {
         switch (alchemy_get_cputype()) {
@@ -582,65 +981,17 @@ void __init arch_init_irq(void)
         case ALCHEMY_CPU_AU1200:
                 au1000_init_irq(au1200_irqmap);
                 break;
+        case ALCHEMY_CPU_AU1300:
+                alchemy_gpic_init_irq(au1300_irqmap);
+                break;
+        default:
+                pr_err("unknown Alchemy IRQ core\n");
+                break;
         }
 }
 
-
-static unsigned long alchemy_ic_pmdata[7 * 2];
-
-static inline void alchemy_ic_suspend_one(void __iomem *base, unsigned long *d)
-{
-        d[0] = __raw_readl(base + IC_CFG0RD);
-        d[1] = __raw_readl(base + IC_CFG1RD);
-        d[2] = __raw_readl(base + IC_CFG2RD);
-        d[3] = __raw_readl(base + IC_SRCRD);
-        d[4] = __raw_readl(base + IC_ASSIGNRD);
-        d[5] = __raw_readl(base + IC_WAKERD);
-        d[6] = __raw_readl(base + IC_MASKRD);
-        ic_init(base);          /* shut it up too while at it */
-}
-
-static inline void alchemy_ic_resume_one(void __iomem *base, unsigned long *d)
-{
-        ic_init(base);
-
-        __raw_writel(d[0], base + IC_CFG0SET);
-        __raw_writel(d[1], base + IC_CFG1SET);
-        __raw_writel(d[2], base + IC_CFG2SET);
-        __raw_writel(d[3], base + IC_SRCSET);
-        __raw_writel(d[4], base + IC_ASSIGNSET);
-        __raw_writel(d[5], base + IC_WAKESET);
-        wmb();
-
-        __raw_writel(d[6], base + IC_MASKSET);
-        wmb();
-}
-
-static int alchemy_ic_suspend(void)
-{
-        alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
-                               alchemy_ic_pmdata);
-        alchemy_ic_suspend_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
-                               &alchemy_ic_pmdata[7]);
-        return 0;
-}
-
-static void alchemy_ic_resume(void)
-{
-        alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC1_PHYS_ADDR),
-                              &alchemy_ic_pmdata[7]);
-        alchemy_ic_resume_one((void __iomem *)KSEG1ADDR(AU1000_IC0_PHYS_ADDR),
-                              alchemy_ic_pmdata);
-}
-
-static struct syscore_ops alchemy_ic_syscore_ops = {
-        .suspend        = alchemy_ic_suspend,
-        .resume         = alchemy_ic_resume,
-};
-
-static int __init alchemy_ic_pm_init(void)
+asmlinkage void plat_irq_dispatch(void)
 {
-        register_syscore_ops(&alchemy_ic_syscore_ops);
-        return 0;
+        unsigned long r = (read_c0_status() & read_c0_cause()) >> 8;
+        do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(r & 0xff));
 }
-device_initcall(alchemy_ic_pm_init);
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index c8e5d72a5826..95cb9113b12c 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -82,6 +82,12 @@ static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
                 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
                 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
         },
+        [ALCHEMY_CPU_AU1300] = {
+                PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT),
+                PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT),
+                PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT),
+                PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT),
+        },
 };
 
 static struct platform_device au1xx0_uart_device = {
@@ -122,10 +128,12 @@ static unsigned long alchemy_ohci_data[][2] __initdata = {
         [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
         [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
         [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
+        [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT },
 };
 
 static unsigned long alchemy_ehci_data[][2] __initdata = {
         [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
+        [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT },
 };
 
 static int __init _new_usbres(struct resource **r, struct platform_device **d)
@@ -169,8 +177,8 @@ static void __init alchemy_setup_usb(int ctype)
                 printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
 
 
-        /* setup EHCI0: Au1200 */
-        if (ctype == ALCHEMY_CPU_AU1200) {
+        /* setup EHCI0: Au1200/Au1300 */
+        if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) {
                 if (_new_usbres(&res, &pdev))
                         return;
 
@@ -187,6 +195,25 @@ static void __init alchemy_setup_usb(int ctype)
                 if (platform_device_register(pdev))
                         printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
         }
+
+        /* Au1300: OHCI1 */
+        if (ctype == ALCHEMY_CPU_AU1300) {
+                if (_new_usbres(&res, &pdev))
+                        return;
+
+                res[0].start = AU1300_USB_OHCI1_PHYS_ADDR;
+                res[0].end = res[0].start + 0x100 - 1;
+                res[0].flags = IORESOURCE_MEM;
+                res[1].start = AU1300_USB_INT;
+                res[1].end = res[1].start;
+                res[1].flags = IORESOURCE_IRQ;
+                pdev->name = "au1xxx-ohci";
+                pdev->id = 1;
+                pdev->dev.dma_mask = &alchemy_ohci_dmamask;
+
+                if (platform_device_register(pdev))
+                        printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n");
+        }
 }
 
 /* Macro to help defining the Ethernet MAC resources */
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index bdd6651e9a4f..0c7fce2a3c12 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -126,6 +126,9 @@ void au_sleep(void)
         case ALCHEMY_CPU_AU1200:
                 alchemy_sleep_au1550();
                 break;
+        case ALCHEMY_CPU_AU1300:
+                alchemy_sleep_au1300();
+                break;
         }
 
         restore_core_regs();
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 77f3c743b716..c7bcc7e5c822 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -153,6 +153,79 @@ LEAF(alchemy_sleep_au1550)
 
 END(alchemy_sleep_au1550)
 
+/* sleepcode for Au1300 memory controller type */
+LEAF(alchemy_sleep_au1300)
+
+        SETUP_SLEEP
+
+        /* cache following instructions, as memory gets put to sleep */
+        la      t0, 2f
+        la      t1, 4f
+        subu    t2, t1, t0
+
+        .set    mips3
+
+1:      cache   0x14, 0(t0)
+        subu    t2, t2, 32
+        bgez    t2, 1b
+         addu   t0, t0, 32
+
+        .set    mips0
+
+2:      lui     a0, 0xb400              /* mem_xxx */
+
+        /* disable all ports in mem_sdportcfga */
+        sw      zero, 0x868(a0)         /* mem_sdportcfga */
+        sync
+
+        /* disable ODT */
+        li      t0, 0x03010000
+        sw      t0, 0x08d8(a0)          /* mem_sdcmd0 */
+        sw      t0, 0x08dc(a0)          /* mem_sdcmd1 */
+        sync
+
+        /* precharge */
+        li      t0, 0x23000400
+        sw      t0, 0x08dc(a0)          /* mem_sdcmd1 */
+        sw      t0, 0x08d8(a0)          /* mem_sdcmd0 */
+        sync
+
+        /* auto refresh */
+        sw      zero, 0x08c8(a0)        /* mem_sdautoref */
+        sync
+
+        /* block access to the DDR */
+        lw      t0, 0x0848(a0)          /* mem_sdconfigb */
+        li      t1, (1 << 7 | 0x3F)
+        or      t0, t0, t1
+        sw      t0, 0x0848(a0)          /* mem_sdconfigb */
+        sync
+
+        /* issue the Self Refresh command */
+        li      t0, 0x10000000
+        sw      t0, 0x08dc(a0)          /* mem_sdcmd1 */
+        sw      t0, 0x08d8(a0)          /* mem_sdcmd0 */
+        sync
+
+        /* wait for sdram to enter self-refresh mode */
+        lui     t0, 0x0300
+3:      lw      t1, 0x0850(a0)          /* mem_sdstat */
+        and     t2, t1, t0
+        bne     t2, t0, 3b
+         nop
+
+        /* disable SDRAM clocks */
+        li      t0, ~(3<<28)
+        lw      t1, 0x0840(a0)          /* mem_sdconfiga */
+        and     t1, t1, t0              /* clear CE[1:0] */
+        sw      t1, 0x0840(a0)          /* mem_sdconfiga */
+        sync
+
+        DO_SLEEP
+4:
+
+END(alchemy_sleep_au1300)
+
 
         /* This is where we return upon wakeup.
          * Reload all of the registers and return.
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index d5da6adbf634..7da4d0081487 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -92,7 +92,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
 
 static struct irqaction au1x_rtcmatch2_irqaction = {
         .handler        = au1x_rtcmatch2_irq,
-        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .flags          = IRQF_TIMER,
         .name           = "timer",
         .dev_id         = &au1x_rtcmatch2_clockdev,
 };
@@ -178,6 +178,7 @@ static int alchemy_m2inttab[] __initdata = {
         AU1100_RTC_MATCH2_INT,
         AU1550_RTC_MATCH2_INT,
         AU1200_RTC_MATCH2_INT,
+        AU1300_RTC_MATCH2_INT,
 };
 
 void __init plat_time_init(void)
diff --git a/arch/mips/alchemy/common/vss.c b/arch/mips/alchemy/common/vss.c
new file mode 100644
index 000000000000..d23b1444d365
--- /dev/null
+++ b/arch/mips/alchemy/common/vss.c
@@ -0,0 +1,84 @@
+/*
+ * Au1300 media block power gating (VSS)
+ *
+ * This is a stop-gap solution until I have the clock framework integration
+ * ready. This stuff here really must be handled transparently when clocks
+ * for various media blocks are enabled/disabled.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#define VSS_GATE        0x00    /* gate wait timers */
+#define VSS_CLKRST      0x04    /* clock/block control */
+#define VSS_FTR         0x08    /* footers */
+
+#define VSS_ADDR(blk)   (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
+
+static DEFINE_SPINLOCK(au1300_vss_lock);
+
+/* enable a block as outlined in the databook */
+static inline void __enable_block(int block)
+{
+        void __iomem *base = (void __iomem *)VSS_ADDR(block);
+
+        __raw_writel(3, base + VSS_CLKRST);     /* enable clock, assert reset */
+        wmb();
+
+        __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */
+        wmb();
+
+        /* enable footers in sequence */
+        __raw_writel(0x01, base + VSS_FTR);
+        wmb();
+        __raw_writel(0x03, base + VSS_FTR);
+        wmb();
+        __raw_writel(0x07, base + VSS_FTR);
+        wmb();
+        __raw_writel(0x0f, base + VSS_FTR);
+        wmb();
+
+        __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */
+        wmb();
+
+        __raw_writel(2, base + VSS_CLKRST);     /* deassert reset */
+        wmb();
+
+        __raw_writel(0x1f, base + VSS_FTR);     /* enable isolation cells */
+        wmb();
+}
+
+/* disable a block as outlined in the databook */
+static inline void __disable_block(int block)
+{
+        void __iomem *base = (void __iomem *)VSS_ADDR(block);
+
+        __raw_writel(0x0f, base + VSS_FTR);     /* disable isolation cells */
+        wmb();
+        __raw_writel(0, base + VSS_GATE);       /* disable FSM */
+        wmb();
+        __raw_writel(3, base + VSS_CLKRST);     /* assert reset */
+        wmb();
+        __raw_writel(1, base + VSS_CLKRST);     /* disable clock */
+        wmb();
+        __raw_writel(0, base + VSS_FTR);        /* disable all footers */
+        wmb();
+}
+
+void au1300_vss_block_control(int block, int enable)
+{
+        unsigned long flags;
+
+        if (alchemy_get_cputype() != ALCHEMY_CPU_AU1300)
+                return;
+
+        /* only one block at a time */
+        spin_lock_irqsave(&au1300_vss_lock, flags);
+        if (enable)
+                __enable_block(block);
+        else
+                __disable_block(block);
+        spin_unlock_irqrestore(&au1300_vss_lock, flags);
+}
+EXPORT_SYMBOL_GPL(au1300_vss_block_control);
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 826449c817c3..3c37fb303364 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -4,15 +4,10 @@
 
 obj-y += prom.o bcsr.o platform.o
 obj-$(CONFIG_PM)                += pm.o
-obj-$(CONFIG_MIPS_PB1000)       += pb1000/
-obj-$(CONFIG_MIPS_PB1100)       += pb1100/
-obj-$(CONFIG_MIPS_PB1200)       += pb1200/
-obj-$(CONFIG_MIPS_PB1500)       += pb1500/
-obj-$(CONFIG_MIPS_PB1550)       += pb1550/
-obj-$(CONFIG_MIPS_DB1000)       += db1x00/
-obj-$(CONFIG_MIPS_DB1100)       += db1x00/
-obj-$(CONFIG_MIPS_DB1200)       += db1200/
-obj-$(CONFIG_MIPS_DB1500)       += db1x00/
-obj-$(CONFIG_MIPS_DB1550)       += db1x00/
-obj-$(CONFIG_MIPS_BOSPORUS)     += db1x00/
-obj-$(CONFIG_MIPS_MIRAGE)       += db1x00/
+obj-$(CONFIG_MIPS_PB1100)       += pb1100.o
+obj-$(CONFIG_MIPS_PB1500)       += pb1500.o
+obj-$(CONFIG_MIPS_PB1550)       += pb1550.o
+obj-$(CONFIG_MIPS_DB1000)       += db1000.o
+obj-$(CONFIG_MIPS_DB1200)       += db1200.o
+obj-$(CONFIG_MIPS_DB1300)       += db1300.o
+obj-$(CONFIG_MIPS_DB1550)       += db1550.o
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index 463d2c4d9441..1e83ce2e1147 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -97,14 +97,9 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
         enable_irq(irq);
 }
 
-/* NOTE: both the enable and mask bits must be cleared, otherwise the
- * CPLD generates tons of spurious interrupts (at least on my DB1200).
- *      -- mlau
- */
 static void bcsr_irq_mask(struct irq_data *d)
 {
         unsigned short v = 1 << (d->irq - bcsr_csc_base);
-        __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
         __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
         wmb();
 }
@@ -112,7 +107,6 @@ static void bcsr_irq_mask(struct irq_data *d)
 static void bcsr_irq_maskack(struct irq_data *d)
 {
         unsigned short v = 1 << (d->irq - bcsr_csc_base);
-        __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
         __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
         __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT);  /* ack */
         wmb();
@@ -121,7 +115,6 @@ static void bcsr_irq_maskack(struct irq_data *d)
 static void bcsr_irq_unmask(struct irq_data *d)
 {
         unsigned short v = 1 << (d->irq - bcsr_csc_base);
-        __raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
         __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
         wmb();
 }
@@ -137,9 +130,9 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
 {
         unsigned int irq;
 
-        /* mask & disable & ack all */
-        __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTCLR);
+        /* mask & enable & ack all */
         __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
+        __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET);
         __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
         wmb();
 
diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
new file mode 100644
index 000000000000..1b81dbf6b804
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -0,0 +1,565 @@
+/*
+ * DBAu1000/1500/1100 board support
+ *
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/mmc/host.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/spi/ads7846.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1000_dma.h>
+#include <asm/mach-au1x00/au1100_mmc.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <asm/reboot.h>
+#include <prom.h>
+#include "platform.h"
+
+#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
+
+struct pci_dev;
+
+static const char *board_type_str(void)
+{
+        switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
+        case BCSR_WHOAMI_DB1000:
+                return "DB1000";
+        case BCSR_WHOAMI_DB1500:
+                return "DB1500";
+        case BCSR_WHOAMI_DB1100:
+                return "DB1100";
+        default:
+                return "(unknown)";
+        }
+}
+
+const char *get_system_type(void)
+{
+        return board_type_str();
+}
+
+void __init board_setup(void)
+{
+        /* initialize board register space */
+        bcsr_init(DB1000_BCSR_PHYS_ADDR,
+                  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
+
+        printk(KERN_INFO "AMD Alchemy %s Board\n", board_type_str());
+}
+
+
+static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+        if ((slot < 12) || (slot > 13) || pin == 0)
+                return -1;
+        if (slot == 12)
+                return (pin == 1) ? AU1500_PCI_INTA : 0xff;
+        if (slot == 13) {
+                switch (pin) {
+                case 1: return AU1500_PCI_INTA;
+                case 2: return AU1500_PCI_INTB;
+                case 3: return AU1500_PCI_INTC;
+                case 4: return AU1500_PCI_INTD;
+                }
+        }
+        return -1;
+}
+
+static struct resource alchemy_pci_host_res[] = {
+        [0] = {
+                .start  = AU1500_PCI_PHYS_ADDR,
+                .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct alchemy_pci_platdata db1500_pci_pd = {
+        .board_map_irq  = db1500_map_pci_irq,
+};
+
+static struct platform_device db1500_pci_host_dev = {
+        .dev.platform_data = &db1500_pci_pd,
+        .name           = "alchemy-pci",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
+        .resource       = alchemy_pci_host_res,
+};
+
+static int __init db1500_pci_init(void)
+{
+        if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1500)
+                return platform_device_register(&db1500_pci_host_dev);
+        return 0;
+}
+/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
+arch_initcall(db1500_pci_init);
+
+
+static struct resource au1100_lcd_resources[] = {
+        [0] = {
+                .start  = AU1100_LCD_PHYS_ADDR,
+                .end    = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1100_LCD_INT,
+                .end    = AU1100_LCD_INT,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device au1100_lcd_device = {
+        .name           = "au1100-lcd",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = &au1100_lcd_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(au1100_lcd_resources),
+        .resource       = au1100_lcd_resources,
+};
+
+static struct resource alchemy_ac97c_res[] = {
+        [0] = {
+                .start  = AU1000_AC97_PHYS_ADDR,
+                .end    = AU1000_AC97_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMA_ID_AC97C_TX,
+                .end    = DMA_ID_AC97C_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start  = DMA_ID_AC97C_RX,
+                .end    = DMA_ID_AC97C_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device alchemy_ac97c_dev = {
+        .name           = "alchemy-ac97c",
+        .id             = -1,
+        .resource       = alchemy_ac97c_res,
+        .num_resources  = ARRAY_SIZE(alchemy_ac97c_res),
+};
+
+static struct platform_device alchemy_ac97c_dma_dev = {
+        .name           = "alchemy-pcm-dma",
+        .id             = 0,
+};
+
+static struct platform_device db1x00_codec_dev = {
+        .name           = "ac97-codec",
+        .id             = -1,
+};
+
+static struct platform_device db1x00_audio_dev = {
+        .name           = "db1000-audio",
+};
+
+/******************************************************************************/
+
+static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
+{
+        void (*mmc_cd)(struct mmc_host *, unsigned long);
+        /* link against CONFIG_MMC=m */
+        mmc_cd = symbol_get(mmc_detect_change);
+        mmc_cd(ptr, msecs_to_jiffies(500));
+        symbol_put(mmc_detect_change);
+
+        return IRQ_HANDLED;
+}
+
+static int db1100_mmc_cd_setup(void *mmc_host, int en)
+{
+        int ret = 0;
+
+        if (en) {
+                irq_set_irq_type(AU1100_GPIO19_INT, IRQ_TYPE_EDGE_BOTH);
+                ret = request_irq(AU1100_GPIO19_INT, db1100_mmc_cd, 0,
+                                  "sd0_cd", mmc_host);
+        } else
+                free_irq(AU1100_GPIO19_INT, mmc_host);
+        return ret;
+}
+
+static int db1100_mmc1_cd_setup(void *mmc_host, int en)
+{
+        int ret = 0;
+
+        if (en) {
+                irq_set_irq_type(AU1100_GPIO20_INT, IRQ_TYPE_EDGE_BOTH);
+                ret = request_irq(AU1100_GPIO20_INT, db1100_mmc_cd, 0,
+                                  "sd1_cd", mmc_host);
+        } else
+                free_irq(AU1100_GPIO20_INT, mmc_host);
+        return ret;
+}
+
+static int db1100_mmc_card_readonly(void *mmc_host)
+{
+        /* testing suggests that this bit is inverted */
+        return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1;
+}
+
+static int db1100_mmc_card_inserted(void *mmc_host)
+{
+        return !alchemy_gpio_get_value(19);
+}
+
+static void db1100_mmc_set_power(void *mmc_host, int state)
+{
+        if (state) {
+                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
+                msleep(400);    /* stabilization time */
+        } else
+                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
+}
+
+static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
+{
+        if (b != LED_OFF)
+                bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
+        else
+                bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
+}
+
+static struct led_classdev db1100_mmc_led = {
+        .brightness_set = db1100_mmcled_set,
+};
+
+static int db1100_mmc1_card_readonly(void *mmc_host)
+{
+        return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0;
+}
+
+static int db1100_mmc1_card_inserted(void *mmc_host)
+{
+        return !alchemy_gpio_get_value(20);
+}
+
+static void db1100_mmc1_set_power(void *mmc_host, int state)
+{
+        if (state) {
+                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
+                msleep(400);    /* stabilization time */
+        } else
+                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
+}
+
+static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
+{
+        if (b != LED_OFF)
+                bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
+        else
+                bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
+}
+
+static struct led_classdev db1100_mmc1_led = {
+        .brightness_set = db1100_mmc1led_set,
+};
+
+static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
+        [0] = {
+                .cd_setup       = db1100_mmc_cd_setup,
+                .set_power      = db1100_mmc_set_power,
+                .card_inserted  = db1100_mmc_card_inserted,
+                .card_readonly  = db1100_mmc_card_readonly,
+                .led            = &db1100_mmc_led,
+        },
+        [1] = {
+                .cd_setup       = db1100_mmc1_cd_setup,
+                .set_power      = db1100_mmc1_set_power,
+                .card_inserted  = db1100_mmc1_card_inserted,
+                .card_readonly  = db1100_mmc1_card_readonly,
+                .led            = &db1100_mmc1_led,
+        },
+};
+
+static struct resource au1100_mmc0_resources[] = {
+        [0] = {
+                .start  = AU1100_SD0_PHYS_ADDR,
+                .end    = AU1100_SD0_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1100_SD_INT,
+                .end    = AU1100_SD_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = DMA_ID_SD0_TX,
+                .end    = DMA_ID_SD0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = DMA_ID_SD0_RX,
+                .end    = DMA_ID_SD0_RX,
+                .flags  = IORESOURCE_DMA,
+        }
+};
+
+static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
+
+static struct platform_device db1100_mmc0_dev = {
+        .name           = "au1xxx-mmc",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = &au1xxx_mmc_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &db1100_mmc_platdata[0],
+        },
+        .num_resources  = ARRAY_SIZE(au1100_mmc0_resources),
+        .resource       = au1100_mmc0_resources,
+};
+
+static struct resource au1100_mmc1_res[] = {
+        [0] = {
+                .start  = AU1100_SD1_PHYS_ADDR,
+                .end    = AU1100_SD1_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1100_SD_INT,
+                .end    = AU1100_SD_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = DMA_ID_SD1_TX,
+                .end    = DMA_ID_SD1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = DMA_ID_SD1_RX,
+                .end    = DMA_ID_SD1_RX,
+                .flags  = IORESOURCE_DMA,
+        }
+};
+
+static struct platform_device db1100_mmc1_dev = {
+        .name           = "au1xxx-mmc",
+        .id             = 1,
+        .dev = {
+                .dma_mask               = &au1xxx_mmc_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &db1100_mmc_platdata[1],
+        },
+        .num_resources  = ARRAY_SIZE(au1100_mmc1_res),
+        .resource       = au1100_mmc1_res,
+};
+
+/******************************************************************************/
+
+static void db1000_irda_set_phy_mode(int mode)
+{
+        unsigned short mask = BCSR_RESETS_IRDA_MODE_MASK | BCSR_RESETS_FIR_SEL;
+
+        switch (mode) {
+        case AU1000_IRDA_PHY_MODE_OFF:
+                bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_OFF);
+                break;
+        case AU1000_IRDA_PHY_MODE_SIR:
+                bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL);
+                break;
+        case AU1000_IRDA_PHY_MODE_FIR:
+                bcsr_mod(BCSR_RESETS, mask, BCSR_RESETS_IRDA_MODE_FULL |
+                                            BCSR_RESETS_FIR_SEL);
+                break;
+        }
+}
+
+static struct au1k_irda_platform_data db1000_irda_platdata = {
+        .set_phy_mode   = db1000_irda_set_phy_mode,
+};
+
+static struct resource au1000_irda_res[] = {
+        [0] = {
+                .start  = AU1000_IRDA_PHYS_ADDR,
+                .end    = AU1000_IRDA_PHYS_ADDR + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1000_IRDA_TX_INT,
+                .end    = AU1000_IRDA_TX_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1000_IRDA_RX_INT,
+                .end    = AU1000_IRDA_RX_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device db1000_irda_dev = {
+        .name   = "au1000-irda",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &db1000_irda_platdata,
+        },
+        .resource       = au1000_irda_res,
+        .num_resources  = ARRAY_SIZE(au1000_irda_res),
+};
+
+/******************************************************************************/
+
+static struct ads7846_platform_data db1100_touch_pd = {
+        .model          = 7846,
+        .vref_mv        = 3300,
+        .gpio_pendown   = 21,
+};
+
+static struct spi_gpio_platform_data db1100_spictl_pd = {
+        .sck            = 209,
+        .mosi           = 208,
+        .miso           = 207,
+        .num_chipselect = 1,
+};
+
+static struct spi_board_info db1100_spi_info[] __initdata = {
+        [0] = {
+                .modalias        = "ads7846",
+                .max_speed_hz    = 3250000,
+                .bus_num         = 0,
+                .chip_select     = 0,
+                .mode            = 0,
+                .irq             = AU1100_GPIO21_INT,
+                .platform_data   = &db1100_touch_pd,
+                .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */
+        },
+};
+
+static struct platform_device db1100_spi_dev = {
+        .name           = "spi_gpio",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &db1100_spictl_pd,
+        },
+};
+
+
+static struct platform_device *db1x00_devs[] = {
+        &db1x00_codec_dev,
+        &alchemy_ac97c_dma_dev,
+        &alchemy_ac97c_dev,
+        &db1x00_audio_dev,
+};
+
+static struct platform_device *db1000_devs[] = {
+        &db1000_irda_dev,
+};
+
+static struct platform_device *db1100_devs[] = {
+        &au1100_lcd_device,
+        &db1100_mmc0_dev,
+        &db1100_mmc1_dev,
+        &db1000_irda_dev,
+        &db1100_spi_dev,
+};
+
+static int __init db1000_dev_init(void)
+{
+        int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
+        int c0, c1, d0, d1, s0, s1;
+        unsigned long pfc;
+
+        if (board == BCSR_WHOAMI_DB1500) {
+                c0 = AU1500_GPIO2_INT;
+                c1 = AU1500_GPIO5_INT;
+                d0 = AU1500_GPIO0_INT;
+                d1 = AU1500_GPIO3_INT;
+                s0 = AU1500_GPIO1_INT;
+                s1 = AU1500_GPIO4_INT;
+        } else if (board == BCSR_WHOAMI_DB1100) {
+                c0 = AU1100_GPIO2_INT;
+                c1 = AU1100_GPIO5_INT;
+                d0 = AU1100_GPIO0_INT;
+                d1 = AU1100_GPIO3_INT;
+                s0 = AU1100_GPIO1_INT;
+                s1 = AU1100_GPIO4_INT;
+
+                gpio_direction_input(19);       /* sd0 cd# */
+                gpio_direction_input(20);       /* sd1 cd# */
+                gpio_direction_input(21);       /* touch pendown# */
+                gpio_direction_input(207);      /* SPI MISO */
+                gpio_direction_output(208, 0);  /* SPI MOSI */
+                gpio_direction_output(209, 1);  /* SPI SCK */
+                gpio_direction_output(210, 1);  /* SPI CS# */
+
+                /* spi_gpio on SSI0 pins */
+                pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
+                pfc |= (1 << 0);        /* SSI0 pins as GPIOs */
+                __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
+                wmb();
+
+                spi_register_board_info(db1100_spi_info,
+                                        ARRAY_SIZE(db1100_spi_info));
+
+                platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
+        } else if (board == BCSR_WHOAMI_DB1000) {
+                c0 = AU1000_GPIO2_INT;
+                c1 = AU1000_GPIO5_INT;
+                d0 = AU1000_GPIO0_INT;
+                d1 = AU1000_GPIO3_INT;
+                s0 = AU1000_GPIO1_INT;
+                s1 = AU1000_GPIO4_INT;
+                platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs));
+        } else
+                return 0; /* unknown board, no further dev setup to do */
+
+        irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH);
+        irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);
+        irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
+
+        db1x_register_pcmcia_socket(
+                AU1000_PCMCIA_ATTR_PHYS_ADDR,
+                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                AU1000_PCMCIA_MEM_PHYS_ADDR,
+                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                AU1000_PCMCIA_IO_PHYS_ADDR,
+                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                c0, d0, /*s0*/0, 0, 0);
+
+        db1x_register_pcmcia_socket(
+                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
+                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
+                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
+                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
+                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
+                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
+                c1, d1, /*s1*/0, 0, 1);
+
+        platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
+        db1x_register_norflash(32 << 20, 4 /* 32bit */, F_SWAPPED);
+        return 0;
+}
+device_initcall(db1000_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200.c
index c61867c93c4a..a83302b96c01 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -1,7 +1,7 @@
 /*
- * DBAu1200 board platform device registration
+ * DBAu1200/PBAu1200 board platform device registration
  *
- * Copyright (C) 2008-2009 Manuel Lauss
+ * Copyright (C) 2008-2011 Manuel Lauss
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,6 +22,7 @@
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/leds.h>
 #include <linux/mmc/host.h>
@@ -33,18 +34,116 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/smc91x.h>
-
+#include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/au1100_mmc.h>
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
+#include <asm/mach-au1x00/au1200fb.h>
 #include <asm/mach-au1x00/au1550_spi.h>
 #include <asm/mach-db1x00/bcsr.h>
 #include <asm/mach-db1x00/db1200.h>
 
-#include "../platform.h"
+#include "platform.h"
+
+static const char *board_type_str(void)
+{
+        switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
+        case BCSR_WHOAMI_PB1200_DDR1:
+        case BCSR_WHOAMI_PB1200_DDR2:
+                return "PB1200";
+        case BCSR_WHOAMI_DB1200:
+                return "DB1200";
+        default:
+                return "(unknown)";
+        }
+}
+
+const char *get_system_type(void)
+{
+        return board_type_str();
+}
+
+static int __init detect_board(void)
+{
+        int bid;
+
+        /* try the DB1200 first */
+        bcsr_init(DB1200_BCSR_PHYS_ADDR,
+                  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
+        if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
+                unsigned short t = bcsr_read(BCSR_HEXLEDS);
+                bcsr_write(BCSR_HEXLEDS, ~t);
+                if (bcsr_read(BCSR_HEXLEDS) != t) {
+                        bcsr_write(BCSR_HEXLEDS, t);
+                        return 0;
+                }
+        }
+
+        /* okay, try the PB1200 then */
+        bcsr_init(PB1200_BCSR_PHYS_ADDR,
+                  PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
+        bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
+        if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
+            (bid == BCSR_WHOAMI_PB1200_DDR2)) {
+                unsigned short t = bcsr_read(BCSR_HEXLEDS);
+                bcsr_write(BCSR_HEXLEDS, ~t);
+                if (bcsr_read(BCSR_HEXLEDS) != t) {
+                        bcsr_write(BCSR_HEXLEDS, t);
+                        return 0;
+                }
+        }
+
+        return 1;       /* it's neither */
+}
+
+void __init board_setup(void)
+{
+        unsigned long freq0, clksrc, div, pfc;
+        unsigned short whoami;
+
+        if (detect_board()) {
+                printk(KERN_ERR "NOT running on a DB1200/PB1200 board!\n");
+                return;
+        }
+
+        whoami = bcsr_read(BCSR_WHOAMI);
+        printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
+                "  Board-ID %d  Daughtercard ID %d\n", board_type_str(),
+                (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
+
+        /* SMBus/SPI on PSC0, Audio on PSC1 */
+        pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
+        pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
+        pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
+        pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
+        __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
+        wmb();
+
+        /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
+         * CPU clock; all other clock generators off/unused.
+         */
+        div = (get_au1x00_speed() + 25000000) / 50000000;
+        if (div & 1)
+                div++;
+        div = ((div >> 1) - 1) & 0xff;
+
+        freq0 = div << SYS_FC_FRDIV0_BIT;
+        __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
+        wmb();
+        freq0 |= SYS_FC_FE0;    /* enable F0 */
+        __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
+        wmb();
+
+        /* psc0_intclk comes 1:1 from F0 */
+        clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
+        __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
+        wmb();
+}
+
+/******************************************************************************/
 
 static struct mtd_partition db1200_spiflash_parts[] = {
         {
-                .name   = "DB1200 SPI flash",
+                .name   = "spi_flash",
                 .offset = 0,
                 .size   = MTDPART_SIZ_FULL,
         },
@@ -78,18 +177,9 @@ static struct spi_board_info db1200_spi_devs[] __initdata = {
 };
 
 static struct i2c_board_info db1200_i2c_devs[] __initdata = {
-        {
-                /* AT24C04-10 I2C eeprom */
-                I2C_BOARD_INFO("24c04", 0x52),
-        },
-        {
-                /* Philips NE1619 temp/voltage sensor (adm1025 drv) */
-                I2C_BOARD_INFO("ne1619", 0x2d),
-        },
-        {
-                /* I2S audio codec WM8731 */
-                I2C_BOARD_INFO("wm8731", 0x1b),
-        },
+        { I2C_BOARD_INFO("24c04", 0x52),  }, /* AT24C04-10 I2C eeprom */
+        { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
+        { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
 };
 
 /**********************************************************************/
@@ -206,7 +296,7 @@ static struct platform_device db1200_eth_dev = {
 static struct resource db1200_ide_res[] = {
         [0] = {
                 .start  = DB1200_IDE_PHYS_ADDR,
-                .end    = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
+                .end    = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -221,13 +311,13 @@ static struct resource db1200_ide_res[] = {
         },
 };
 
-static u64 ide_dmamask = DMA_BIT_MASK(32);
+static u64 au1200_ide_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device db1200_ide_dev = {
         .name           = "au1200-ide",
         .id             = 0,
         .dev = {
-                .dma_mask               = &ide_dmamask,
+                .dma_mask               = &au1200_ide_dmamask,
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
         .num_resources  = ARRAY_SIZE(db1200_ide_res),
@@ -236,13 +326,6 @@ static struct platform_device db1200_ide_dev = {
 
 /**********************************************************************/
 
-static struct platform_device db1200_rtc_dev = {
-        .name   = "rtc-au1xxx",
-        .id     = -1,
-};
-
-/**********************************************************************/
-
 /* SD carddetects:  they're supposed to be edge-triggered, but ack
  * doesn't seem to work (CPLD Rev 2).  Instead, the screaming one
  * is disabled and its counterpart enabled.  The 500ms timeout is
@@ -276,12 +359,12 @@ static int db1200_mmc_cd_setup(void *mmc_host, int en)
 
         if (en) {
                 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
-                                  IRQF_DISABLED, "sd_insert", mmc_host);
+                                  0, "sd_insert", mmc_host);
                 if (ret)
                         goto out;
 
                 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
-                                  IRQF_DISABLED, "sd_eject", mmc_host);
+                                  0, "sd_eject", mmc_host);
                 if (ret) {
                         free_irq(DB1200_SD0_INSERT_INT, mmc_host);
                         goto out;
@@ -333,12 +416,109 @@ static struct led_classdev db1200_mmc_led = {
         .brightness_set = db1200_mmcled_set,
 };
 
-static struct au1xmmc_platform_data db1200mmc_platdata = {
-        .cd_setup       = db1200_mmc_cd_setup,
-        .set_power      = db1200_mmc_set_power,
-        .card_inserted  = db1200_mmc_card_inserted,
-        .card_readonly  = db1200_mmc_card_readonly,
-        .led            = &db1200_mmc_led,
+/* -- */
+
+static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
+{
+        void(*mmc_cd)(struct mmc_host *, unsigned long);
+
+        if (irq == PB1200_SD1_INSERT_INT) {
+                disable_irq_nosync(PB1200_SD1_INSERT_INT);
+                enable_irq(PB1200_SD1_EJECT_INT);
+        } else {
+                disable_irq_nosync(PB1200_SD1_EJECT_INT);
+                enable_irq(PB1200_SD1_INSERT_INT);
+        }
+
+        /* link against CONFIG_MMC=m */
+        mmc_cd = symbol_get(mmc_detect_change);
+        if (mmc_cd) {
+                mmc_cd(ptr, msecs_to_jiffies(500));
+                symbol_put(mmc_detect_change);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
+{
+        int ret;
+
+        if (en) {
+                ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0,
+                                  "sd1_insert", mmc_host);
+                if (ret)
+                        goto out;
+
+                ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0,
+                                  "sd1_eject", mmc_host);
+                if (ret) {
+                        free_irq(PB1200_SD1_INSERT_INT, mmc_host);
+                        goto out;
+                }
+
+                if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
+                        enable_irq(PB1200_SD1_EJECT_INT);
+                else
+                        enable_irq(PB1200_SD1_INSERT_INT);
+
+        } else {
+                free_irq(PB1200_SD1_INSERT_INT, mmc_host);
+                free_irq(PB1200_SD1_EJECT_INT, mmc_host);
+        }
+        ret = 0;
+out:
+        return ret;
+}
+
+static void pb1200_mmc1led_set(struct led_classdev *led,
+                        enum led_brightness brightness)
+{
+        if (brightness != LED_OFF)
+                        bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
+        else
+                        bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
+}
+
+static struct led_classdev pb1200_mmc1_led = {
+        .brightness_set = pb1200_mmc1led_set,
+};
+
+static void pb1200_mmc1_set_power(void *mmc_host, int state)
+{
+        if (state) {
+                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
+                msleep(400);    /* stabilization time */
+        } else
+                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
+}
+
+static int pb1200_mmc1_card_readonly(void *mmc_host)
+{
+        return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
+}
+
+static int pb1200_mmc1_card_inserted(void *mmc_host)
+{
+        return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
+}
+
+
+static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
+        [0] = {
+                .cd_setup       = db1200_mmc_cd_setup,
+                .set_power      = db1200_mmc_set_power,
+                .card_inserted  = db1200_mmc_card_inserted,
+                .card_readonly  = db1200_mmc_card_readonly,
+                .led            = &db1200_mmc_led,
+        },
+        [1] = {
+                .cd_setup       = pb1200_mmc1_cd_setup,
+                .set_power      = pb1200_mmc1_set_power,
+                .card_inserted  = pb1200_mmc1_card_inserted,
+                .card_readonly  = pb1200_mmc1_card_readonly,
+                .led            = &pb1200_mmc1_led,
+        },
 };
 
 static struct resource au1200_mmc0_resources[] = {
@@ -372,14 +552,76 @@ static struct platform_device db1200_mmc0_dev = {
         .dev = {
                 .dma_mask               = &au1xxx_mmc_dmamask,
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &db1200mmc_platdata,
+                .platform_data          = &db1200_mmc_platdata[0],
         },
         .num_resources  = ARRAY_SIZE(au1200_mmc0_resources),
         .resource       = au1200_mmc0_resources,
 };
 
+static struct resource au1200_mmc1_res[] = {
+        [0] = {
+                .start  = AU1100_SD1_PHYS_ADDR,
+                .end    = AU1100_SD1_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1200_SD_INT,
+                .end    = AU1200_SD_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1200_DSCR_CMD0_SDMS_TX1,
+                .end    = AU1200_DSCR_CMD0_SDMS_TX1,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = AU1200_DSCR_CMD0_SDMS_RX1,
+                .end    = AU1200_DSCR_CMD0_SDMS_RX1,
+                .flags  = IORESOURCE_DMA,
+        }
+};
+
+static struct platform_device pb1200_mmc1_dev = {
+        .name           = "au1xxx-mmc",
+        .id             = 1,
+        .dev = {
+                .dma_mask               = &au1xxx_mmc_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &db1200_mmc_platdata[1],
+        },
+        .num_resources  = ARRAY_SIZE(au1200_mmc1_res),
+        .resource       = au1200_mmc1_res,
+};
+
 /**********************************************************************/
 
+static int db1200fb_panel_index(void)
+{
+        return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
+}
+
+static int db1200fb_panel_init(void)
+{
+        /* Apply power */
+        bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
+                                BCSR_BOARD_LCDBL);
+        return 0;
+}
+
+static int db1200fb_panel_shutdown(void)
+{
+        /* Remove power */
+        bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
+                             BCSR_BOARD_LCDBL, 0);
+        return 0;
+}
+
+static struct au1200fb_platdata db1200fb_pd = {
+        .panel_index    = db1200fb_panel_index,
+        .panel_init     = db1200fb_panel_init,
+        .panel_shutdown = db1200fb_panel_shutdown,
+};
+
 static struct resource au1200_lcd_res[] = {
         [0] = {
                 .start  = AU1200_LCD_PHYS_ADDR,
@@ -401,6 +643,7 @@ static struct platform_device au1200_lcd_dev = {
         .dev = {
                 .dma_mask               = &au1200_lcd_dmamask,
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &db1200fb_pd,
         },
         .num_resources  = ARRAY_SIZE(au1200_lcd_res),
         .resource       = au1200_lcd_res,
@@ -519,7 +762,6 @@ static struct platform_device *db1200_devs[] __initdata = {
         &db1200_mmc0_dev,
         &au1200_lcd_dev,
         &db1200_eth_dev,
-        &db1200_rtc_dev,
         &db1200_nand_dev,
         &db1200_audiodma_dev,
         &db1200_audio_dev,
@@ -527,11 +769,62 @@ static struct platform_device *db1200_devs[] __initdata = {
         &db1200_sound_dev,
 };
 
+static struct platform_device *pb1200_devs[] __initdata = {
+        &pb1200_mmc1_dev,
+};
+
+/* Some peripheral base addresses differ on the PB1200 */
+static int __init pb1200_res_fixup(void)
+{
+        /* CPLD Revs earlier than 4 cause problems */
+        if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
+                printk(KERN_ERR "the board updated to latest revisions.\n");
+                printk(KERN_ERR "This software will not work reliably\n");
+                printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                return 1;
+        }
+
+        db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
+        db1200_nand_res[0].end   = PB1200_NAND_PHYS_ADDR + 0xff;
+        db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
+        db1200_ide_res[0].end   = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
+        db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
+        db1200_eth_res[0].end   = PB1200_ETH_PHYS_ADDR + 0xff;
+        return 0;
+}
+
 static int __init db1200_dev_init(void)
 {
         unsigned long pfc;
         unsigned short sw;
-        int swapped;
+        int swapped, bid;
+
+        bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
+        if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
+            (bid == BCSR_WHOAMI_PB1200_DDR2)) {
+                if (pb1200_res_fixup())
+                        return -ENODEV;
+        }
+
+        /* GPIO7 is low-level triggered CPLD cascade */
+        irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
+        bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
+
+        /* insert/eject pairs: one of both is always screaming.  To avoid
+         * issues they must not be automatically enabled when initially
+         * requested.
+         */
+        irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
 
         i2c_register_board_info(0, db1200_i2c_devs,
                                 ARRAY_SIZE(db1200_i2c_devs));
@@ -540,6 +833,7 @@ static int __init db1200_dev_init(void)
 
         /* SWITCHES:    S6.8 I2C/SPI selector  (OFF=I2C  ON=SPI)
          *              S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
+         *              or S12 on the PB1200.
          */
 
         /* NOTE: GPIO215 controls OTG VBUS supply.  In SPI mode however
@@ -554,7 +848,7 @@ static int __init db1200_dev_init(void)
         gpio_request(215, "otg-vbus");
         gpio_direction_output(215, 1);
 
-        printk(KERN_INFO "DB1200 device configuration:\n");
+        printk(KERN_INFO "%s device configuration:\n", board_type_str());
 
         sw = bcsr_read(BCSR_SWITCHES);
         if (sw & BCSR_SWITCHES_DIP_8) {
@@ -595,7 +889,7 @@ static int __init db1200_dev_init(void)
 
         /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
         __raw_writel(PSC_SEL_CLK_SERCLK,
-                (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
+            (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
         wmb();
 
         db1x_register_pcmcia_socket(
@@ -621,28 +915,13 @@ static int __init db1200_dev_init(void)
         swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
         db1x_register_norflash(64 << 20, 2, swapped);
 
-        return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
-}
-device_initcall(db1200_dev_init);
-
-/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
-int board_au1200fb_panel(void)
-{
-        return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
-}
+        platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
 
-int board_au1200fb_panel_init(void)
-{
-        /* Apply power */
-        bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
-                                BCSR_BOARD_LCDBL);
-        return 0;
-}
+        /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
+        if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
+            (bid == BCSR_WHOAMI_PB1200_DDR2))
+                platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
 
-int board_au1200fb_panel_shutdown(void)
-{
-        /* Remove power */
-        bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
-                             BCSR_BOARD_LCDBL, 0);
         return 0;
 }
+device_initcall(db1200_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile
deleted file mode 100644
index 17840a5e2738..000000000000
--- a/arch/mips/alchemy/devboards/db1200/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
deleted file mode 100644
index 4a8980027ecf..000000000000
--- a/arch/mips/alchemy/devboards/db1200/setup.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Alchemy/AMD/RMI DB1200 board setup.
- *
- * Licensed under the terms outlined in the file COPYING in the root of
- * this source archive.
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-db1x00/bcsr.h>
-#include <asm/mach-db1x00/db1200.h>
-
-const char *get_system_type(void)
-{
-        return "Alchemy Db1200";
-}
-
-void __init board_setup(void)
-{
-        unsigned long freq0, clksrc, div, pfc;
-        unsigned short whoami;
-
-        bcsr_init(DB1200_BCSR_PHYS_ADDR,
-                  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
-
-        whoami = bcsr_read(BCSR_WHOAMI);
-        printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
-                "  Board-ID %d  Daughtercard ID %d\n",
-                (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
-
-        /* SMBus/SPI on PSC0, Audio on PSC1 */
-        pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
-        pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
-        pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
-        pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
-        __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
-        wmb();
-
-        /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
-         * CPU clock; all other clock generators off/unused.
-         */
-        div = (get_au1x00_speed() + 25000000) / 50000000;
-        if (div & 1)
-                div++;
-        div = ((div >> 1) - 1) & 0xff;
-
-        freq0 = div << SYS_FC_FRDIV0_BIT;
-        __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
-        wmb();
-        freq0 |= SYS_FC_FE0;    /* enable F0 */
-        __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
-        wmb();
-
-        /* psc0_intclk comes 1:1 from F0 */
-        clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
-        __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
-        wmb();
-}
-
-static int __init db1200_arch_init(void)
-{
-        /* GPIO7 is low-level triggered CPLD cascade */
-        irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
-        bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
-
-        /* insert/eject pairs: one of both is always screaming.  To avoid
-         * issues they must not be automatically enabled when initially
-         * requested.
-         */
-        irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
-        irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
-        irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
-        irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
-        irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
-        irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
-        return 0;
-}
-arch_initcall(db1200_arch_init);
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
new file mode 100644
index 000000000000..0893f2af0d01
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -0,0 +1,785 @@
+/*
+ * DBAu1300 init and platform device setup.
+ *
+ * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com>
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/init.h>
+#include <linux/input.h>        /* KEY_* codes */
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+#include <linux/ata_platform.h>
+#include <linux/mmc/host.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1100_mmc.h>
+#include <asm/mach-au1x00/au1200fb.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
+#include <asm/mach-au1x00/au1xxx_psc.h>
+#include <asm/mach-db1x00/db1300.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <asm/mach-au1x00/prom.h>
+
+#include "platform.h"
+
+static struct i2c_board_info db1300_i2c_devs[] __initdata = {
+        { I2C_BOARD_INFO("wm8731", 0x1b), },    /* I2S audio codec */
+        { I2C_BOARD_INFO("ne1619", 0x2d), },    /* adm1025-compat hwmon */
+};
+
+/* multifunction pins to assign to GPIO controller */
+static int db1300_gpio_pins[] __initdata = {
+        AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1,
+        AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX,
+        AU1300_PIN_EXTCLK1,
+        -1,     /* terminator */
+};
+
+/* multifunction pins to assign to device functions */
+static int db1300_dev_pins[] __initdata = {
+        /* wake-from-str pins 0-3 */
+        AU1300_PIN_WAKE0,
+        /* external clock sources for PSC0 */
+        AU1300_PIN_EXTCLK0,
+        /* 8bit MMC interface on SD0: 6-9 */
+        AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
+        AU1300_PIN_SD0DAT7,
+        /* UART1 pins: 11-18 */
+        AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
+        AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
+        AU1300_PIN_U1RX, AU1300_PIN_U1TX,
+        /* UART0 pins: 19-24 */
+        AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
+        AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
+        /* UART2: 25-26 */
+        AU1300_PIN_U2RX, AU1300_PIN_U2TX,
+        /* UART3: 27-28 */
+        AU1300_PIN_U3RX, AU1300_PIN_U3TX,
+        /* LCD controller PWMs, ext pixclock: 30-31 */
+        AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
+        /* SD1 interface: 32-37 */
+        AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
+        AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
+        /* SD2 interface: 38-43 */
+        AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
+        AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
+        /* PSC0/1 clocks: 44-45 */
+        AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
+        /* PSCs: 46-49/50-53/54-57/58-61 */
+        AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
+        AU1300_PIN_PSC0D1,
+        AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
+        AU1300_PIN_PSC1D1,
+        AU1300_PIN_PSC2SYNC0,                       AU1300_PIN_PSC2D0,
+        AU1300_PIN_PSC2D1,
+        AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
+        AU1300_PIN_PSC3D1,
+        /* PCMCIA interface: 62-70 */
+        AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
+        AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
+        AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
+        /* camera interface H/V sync inputs: 71-72 */
+        AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
+        /* PSC2/3 clocks: 73-74 */
+        AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
+        -1,     /* terminator */
+};
+
+static void __init db1300_gpio_config(void)
+{
+        int *i;
+
+        i = &db1300_dev_pins[0];
+        while (*i != -1)
+                au1300_pinfunc_to_dev(*i++);
+
+        i = &db1300_gpio_pins[0];
+        while (*i != -1)
+                au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */
+
+        au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX);
+}
+
+char *get_system_type(void)
+{
+        return "DB1300";
+}
+
+/**********************************************************************/
+
+static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+                                 unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
+
+        ioaddr &= 0xffffff00;
+
+        if (ctrl & NAND_CLE) {
+                ioaddr += MEM_STNAND_CMD;
+        } else if (ctrl & NAND_ALE) {
+                ioaddr += MEM_STNAND_ADDR;
+        } else {
+                /* assume we want to r/w real data  by default */
+                ioaddr += MEM_STNAND_DATA;
+        }
+        this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
+        if (cmd != NAND_CMD_NONE) {
+                __raw_writeb(cmd, this->IO_ADDR_W);
+                wmb();
+        }
+}
+
+static int au1300_nand_device_ready(struct mtd_info *mtd)
+{
+        return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
+}
+
+static const char *db1300_part_probes[] = { "cmdlinepart", NULL };
+
+static struct mtd_partition db1300_nand_parts[] = {
+        {
+                .name   = "NAND FS 0",
+                .offset = 0,
+                .size   = 8 * 1024 * 1024,
+        },
+        {
+                .name   = "NAND FS 1",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL
+        },
+};
+
+struct platform_nand_data db1300_nand_platdata = {
+        .chip = {
+                .nr_chips       = 1,
+                .chip_offset    = 0,
+                .nr_partitions  = ARRAY_SIZE(db1300_nand_parts),
+                .partitions     = db1300_nand_parts,
+                .chip_delay     = 20,
+                .part_probe_types = db1300_part_probes,
+        },
+        .ctrl = {
+                .dev_ready      = au1300_nand_device_ready,
+                .cmd_ctrl       = au1300_nand_cmd_ctrl,
+        },
+};
+
+static struct resource db1300_nand_res[] = {
+        [0] = {
+                .start  = DB1300_NAND_PHYS_ADDR,
+                .end    = DB1300_NAND_PHYS_ADDR + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device db1300_nand_dev = {
+        .name           = "gen_nand",
+        .num_resources  = ARRAY_SIZE(db1300_nand_res),
+        .resource       = db1300_nand_res,
+        .id             = -1,
+        .dev            = {
+                .platform_data = &db1300_nand_platdata,
+        }
+};
+
+/**********************************************************************/
+
+static struct resource db1300_eth_res[] = {
+        [0] = {
+                .start          = DB1300_ETH_PHYS_ADDR,
+                .end            = DB1300_ETH_PHYS_END,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = DB1300_ETH_INT,
+                .end            = DB1300_ETH_INT,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct smsc911x_platform_config db1300_eth_config = {
+        .phy_interface          = PHY_INTERFACE_MODE_MII,
+        .irq_polarity           = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type               = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .flags                  = SMSC911X_USE_32BIT,
+};
+
+static struct platform_device db1300_eth_dev = {
+        .name                   = "smsc911x",
+        .id                     = -1,
+        .num_resources          = ARRAY_SIZE(db1300_eth_res),
+        .resource               = db1300_eth_res,
+        .dev = {
+                .platform_data  = &db1300_eth_config,
+        },
+};
+
+/**********************************************************************/
+
+static struct resource au1300_psc1_res[] = {
+        [0] = {
+                .start  = AU1300_PSC1_PHYS_ADDR,
+                .end    = AU1300_PSC1_PHYS_ADDR + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1300_PSC1_INT,
+                .end    = AU1300_PSC1_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1300_DSCR_CMD0_PSC1_TX,
+                .end    = AU1300_DSCR_CMD0_PSC1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = AU1300_DSCR_CMD0_PSC1_RX,
+                .end    = AU1300_DSCR_CMD0_PSC1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1300_ac97_dev = {
+        .name           = "au1xpsc_ac97",
+        .id             = 1,    /* PSC ID. match with AC97 codec ID! */
+        .num_resources  = ARRAY_SIZE(au1300_psc1_res),
+        .resource       = au1300_psc1_res,
+};
+
+/**********************************************************************/
+
+static struct resource au1300_psc2_res[] = {
+        [0] = {
+                .start  = AU1300_PSC2_PHYS_ADDR,
+                .end    = AU1300_PSC2_PHYS_ADDR + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1300_PSC2_INT,
+                .end    = AU1300_PSC2_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1300_DSCR_CMD0_PSC2_TX,
+                .end    = AU1300_DSCR_CMD0_PSC2_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = AU1300_DSCR_CMD0_PSC2_RX,
+                .end    = AU1300_DSCR_CMD0_PSC2_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1300_i2s_dev = {
+        .name           = "au1xpsc_i2s",
+        .id             = 2,    /* PSC ID */
+        .num_resources  = ARRAY_SIZE(au1300_psc2_res),
+        .resource       = au1300_psc2_res,
+};
+
+/**********************************************************************/
+
+static struct resource au1300_psc3_res[] = {
+        [0] = {
+                .start  = AU1300_PSC3_PHYS_ADDR,
+                .end    = AU1300_PSC3_PHYS_ADDR + 0x0fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1300_PSC3_INT,
+                .end    = AU1300_PSC3_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1300_DSCR_CMD0_PSC3_TX,
+                .end    = AU1300_DSCR_CMD0_PSC3_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = AU1300_DSCR_CMD0_PSC3_RX,
+                .end    = AU1300_DSCR_CMD0_PSC3_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1300_i2c_dev = {
+        .name           = "au1xpsc_smbus",
+        .id             = 0,    /* bus number */
+        .num_resources  = ARRAY_SIZE(au1300_psc3_res),
+        .resource       = au1300_psc3_res,
+};
+
+/**********************************************************************/
+
+/* proper key assignments when facing the LCD panel.  For key assignments
+ * according to the schematics swap up with down and left with right.
+ * I chose to use it to emulate the arrow keys of a keyboard.
+ */
+static struct gpio_keys_button db1300_5waysw_arrowkeys[] = {
+        {
+                .code                   = KEY_DOWN,
+                .gpio                   = AU1300_PIN_LCDPWM0,
+                .type                   = EV_KEY,
+                .debounce_interval      = 1,
+                .active_low             = 1,
+                .desc                   = "5waysw-down",
+        },
+        {
+                .code                   = KEY_UP,
+                .gpio                   = AU1300_PIN_PSC2SYNC1,
+                .type                   = EV_KEY,
+                .debounce_interval      = 1,
+                .active_low             = 1,
+                .desc                   = "5waysw-up",
+        },
+        {
+                .code                   = KEY_RIGHT,
+                .gpio                   = AU1300_PIN_WAKE3,
+                .type                   = EV_KEY,
+                .debounce_interval      = 1,
+                .active_low             = 1,
+                .desc                   = "5waysw-right",
+        },
+        {
+                .code                   = KEY_LEFT,
+                .gpio                   = AU1300_PIN_WAKE2,
+                .type                   = EV_KEY,
+                .debounce_interval      = 1,
+                .active_low             = 1,
+                .desc                   = "5waysw-left",
+        },
+        {
+                .code                   = KEY_ENTER,
+                .gpio                   = AU1300_PIN_WAKE1,
+                .type                   = EV_KEY,
+                .debounce_interval      = 1,
+                .active_low             = 1,
+                .desc                   = "5waysw-push",
+        },
+};
+
+static struct gpio_keys_platform_data db1300_5waysw_data = {
+        .buttons        = db1300_5waysw_arrowkeys,
+        .nbuttons       = ARRAY_SIZE(db1300_5waysw_arrowkeys),
+        .rep            = 1,
+        .name           = "db1300-5wayswitch",
+};
+
+static struct platform_device db1300_5waysw_dev = {
+        .name           = "gpio-keys",
+        .dev    = {
+                .platform_data  = &db1300_5waysw_data,
+        },
+};
+
+/**********************************************************************/
+
+static struct pata_platform_info db1300_ide_info = {
+        .ioport_shift   = DB1300_IDE_REG_SHIFT,
+};
+
+#define IDE_ALT_START   (14 << DB1300_IDE_REG_SHIFT)
+static struct resource db1300_ide_res[] = {
+        [0] = {
+                .start  = DB1300_IDE_PHYS_ADDR,
+                .end    = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DB1300_IDE_PHYS_ADDR + IDE_ALT_START,
+                .end    = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = DB1300_IDE_INT,
+                .end    = DB1300_IDE_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device db1300_ide_dev = {
+        .dev    = {
+                .platform_data  = &db1300_ide_info,
+        },
+        .name           = "pata_platform",
+        .resource       = db1300_ide_res,
+        .num_resources  = ARRAY_SIZE(db1300_ide_res),
+};
+
+/**********************************************************************/
+
+static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
+{
+        void(*mmc_cd)(struct mmc_host *, unsigned long);
+
+        /* disable the one currently screaming. No other way to shut it up */
+        if (irq == DB1300_SD1_INSERT_INT) {
+                disable_irq_nosync(DB1300_SD1_INSERT_INT);
+                enable_irq(DB1300_SD1_EJECT_INT);
+        } else {
+                disable_irq_nosync(DB1300_SD1_EJECT_INT);
+                enable_irq(DB1300_SD1_INSERT_INT);
+        }
+
+        /* link against CONFIG_MMC=m.  We can only be called once MMC core has
+         * initialized the controller, so symbol_get() should always succeed.
+         */
+        mmc_cd = symbol_get(mmc_detect_change);
+        mmc_cd(ptr, msecs_to_jiffies(500));
+        symbol_put(mmc_detect_change);
+
+        return IRQ_HANDLED;
+}
+
+static int db1300_mmc_card_readonly(void *mmc_host)
+{
+        /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */
+        return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP;
+}
+
+static int db1300_mmc_card_inserted(void *mmc_host)
+{
+        return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */
+}
+
+static int db1300_mmc_cd_setup(void *mmc_host, int en)
+{
+        int ret;
+
+        if (en) {
+                ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0,
+                                  "sd_insert", mmc_host);
+                if (ret)
+                        goto out;
+
+                ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0,
+                                  "sd_eject", mmc_host);
+                if (ret) {
+                        free_irq(DB1300_SD1_INSERT_INT, mmc_host);
+                        goto out;
+                }
+
+                if (db1300_mmc_card_inserted(mmc_host))
+                        enable_irq(DB1300_SD1_EJECT_INT);
+                else
+                        enable_irq(DB1300_SD1_INSERT_INT);
+
+        } else {
+                free_irq(DB1300_SD1_INSERT_INT, mmc_host);
+                free_irq(DB1300_SD1_EJECT_INT, mmc_host);
+        }
+        ret = 0;
+out:
+        return ret;
+}
+
+static void db1300_mmcled_set(struct led_classdev *led,
+                              enum led_brightness brightness)
+{
+        if (brightness != LED_OFF)
+                bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
+        else
+                bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
+}
+
+static struct led_classdev db1300_mmc_led = {
+        .brightness_set = db1300_mmcled_set,
+};
+
+struct au1xmmc_platform_data db1300_sd1_platdata = {
+        .cd_setup       = db1300_mmc_cd_setup,
+        .card_inserted  = db1300_mmc_card_inserted,
+        .card_readonly  = db1300_mmc_card_readonly,
+        .led            = &db1300_mmc_led,
+};
+
+static struct resource au1300_sd1_res[] = {
+        [0] = {
+                .start  = AU1300_SD1_PHYS_ADDR,
+                .end    = AU1300_SD1_PHYS_ADDR,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1300_SD1_INT,
+                .end    = AU1300_SD1_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1300_DSCR_CMD0_SDMS_TX1,
+                .end    = AU1300_DSCR_CMD0_SDMS_TX1,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = AU1300_DSCR_CMD0_SDMS_RX1,
+                .end    = AU1300_DSCR_CMD0_SDMS_RX1,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1300_sd1_dev = {
+        .dev = {
+                .platform_data  = &db1300_sd1_platdata,
+        },
+        .name           = "au1xxx-mmc",
+        .id             = 1,
+        .resource       = au1300_sd1_res,
+        .num_resources  = ARRAY_SIZE(au1300_sd1_res),
+};
+
+/**********************************************************************/
+
+static int db1300_movinand_inserted(void *mmc_host)
+{
+        return 0; /* disable for now, it doesn't work yet */
+}
+
+static int db1300_movinand_readonly(void *mmc_host)
+{
+        return 0;
+}
+
+static void db1300_movinand_led_set(struct led_classdev *led,
+                                    enum led_brightness brightness)
+{
+        if (brightness != LED_OFF)
+                bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
+        else
+                bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
+}
+
+static struct led_classdev db1300_movinand_led = {
+        .brightness_set         = db1300_movinand_led_set,
+};
+
+struct au1xmmc_platform_data db1300_sd0_platdata = {
+        .card_inserted          = db1300_movinand_inserted,
+        .card_readonly          = db1300_movinand_readonly,
+        .led                    = &db1300_movinand_led,
+        .mask_host_caps         = MMC_CAP_NEEDS_POLL,
+};
+
+static struct resource au1300_sd0_res[] = {
+        [0] = {
+                .start  = AU1100_SD0_PHYS_ADDR,
+                .end    = AU1100_SD0_PHYS_ADDR,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1300_SD0_INT,
+                .end    = AU1300_SD0_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1300_DSCR_CMD0_SDMS_TX0,
+                .end    = AU1300_DSCR_CMD0_SDMS_TX0,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = AU1300_DSCR_CMD0_SDMS_RX0,
+                .end    = AU1300_DSCR_CMD0_SDMS_RX0,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1300_sd0_dev = {
+        .dev = {
+                .platform_data  = &db1300_sd0_platdata,
+        },
+        .name           = "au1xxx-mmc",
+        .id             = 0,
+        .resource       = au1300_sd0_res,
+        .num_resources  = ARRAY_SIZE(au1300_sd0_res),
+};
+
+/**********************************************************************/
+
+static struct platform_device db1300_wm9715_dev = {
+        .name           = "wm9712-codec",
+        .id             = 1,    /* ID of PSC for AC97 audio, see asoc glue! */
+};
+
+static struct platform_device db1300_ac97dma_dev = {
+        .name           = "au1xpsc-pcm",
+        .id             = 1,    /* PSC ID */
+};
+
+static struct platform_device db1300_i2sdma_dev = {
+        .name           = "au1xpsc-pcm",
+        .id             = 2,    /* PSC ID */
+};
+
+static struct platform_device db1300_sndac97_dev = {
+        .name           = "db1300-ac97",
+};
+
+static struct platform_device db1300_sndi2s_dev = {
+        .name           = "db1300-i2s",
+};
+
+/**********************************************************************/
+
+static int db1300fb_panel_index(void)
+{
+        return 9;       /* DB1300_800x480 */
+}
+
+static int db1300fb_panel_init(void)
+{
+        /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
+        bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD,
+                             BCSR_BOARD_LCDBL);
+        return 0;
+}
+
+static int db1300fb_panel_shutdown(void)
+{
+        /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */
+        bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL,
+                             BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD);
+        return 0;
+}
+
+static struct au1200fb_platdata db1300fb_pd = {
+        .panel_index    = db1300fb_panel_index,
+        .panel_init     = db1300fb_panel_init,
+        .panel_shutdown = db1300fb_panel_shutdown,
+};
+
+static struct resource au1300_lcd_res[] = {
+        [0] = {
+                .start  = AU1200_LCD_PHYS_ADDR,
+                .end    = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1300_LCD_INT,
+                .end    = AU1300_LCD_INT,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device db1300_lcd_dev = {
+        .name           = "au1200-lcd",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = &au1300_lcd_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &db1300fb_pd,
+        },
+        .num_resources  = ARRAY_SIZE(au1300_lcd_res),
+        .resource       = au1300_lcd_res,
+};
+
+/**********************************************************************/
+
+static struct platform_device *db1300_dev[] __initdata = {
+        &db1300_eth_dev,
+        &db1300_i2c_dev,
+        &db1300_5waysw_dev,
+        &db1300_nand_dev,
+        &db1300_ide_dev,
+        &db1300_sd0_dev,
+        &db1300_sd1_dev,
+        &db1300_lcd_dev,
+        &db1300_ac97_dev,
+        &db1300_i2s_dev,
+        &db1300_wm9715_dev,
+        &db1300_ac97dma_dev,
+        &db1300_i2sdma_dev,
+        &db1300_sndac97_dev,
+        &db1300_sndi2s_dev,
+};
+
+static int __init db1300_device_init(void)
+{
+        int swapped, cpldirq;
+
+        /* setup CPLD IRQ muxer */
+        cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1);
+        irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH);
+        bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq);
+
+        /* insert/eject IRQs: one always triggers so don't enable them
+         * when doing request_irq() on them.  DB1200 has this bug too.
+         */
+        irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN);
+
+        /*
+         * setup board
+         */
+        prom_get_ethernet_addr(&db1300_eth_config.mac[0]);
+
+        i2c_register_board_info(0, db1300_i2c_devs,
+                                ARRAY_SIZE(db1300_i2c_devs));
+
+        /* Audio PSC clock is supplied by codecs (PSC1, 2) */
+        __raw_writel(PSC_SEL_CLK_SERCLK,
+            (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
+        wmb();
+        __raw_writel(PSC_SEL_CLK_SERCLK,
+            (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
+        wmb();
+        /* I2C uses internal 48MHz EXTCLK1 */
+        __raw_writel(PSC_SEL_CLK_INTCLK,
+            (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
+        wmb();
+
+        /* enable power to USB ports */
+        bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR);
+
+        /* although it is socket #0, it uses the CPLD bits which previous boards
+         * have used for socket #1.
+         */
+        db1x_register_pcmcia_socket(
+                AU1000_PCMCIA_ATTR_PHYS_ADDR,
+                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1,
+                AU1000_PCMCIA_MEM_PHYS_ADDR,
+                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x00400000 - 1,
+                AU1000_PCMCIA_IO_PHYS_ADDR,
+                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x00010000 - 1,
+                DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1);
+
+        swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
+        db1x_register_norflash(64 << 20, 2, swapped);
+
+        return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev));
+}
+device_initcall(db1300_device_init);
+
+
+void __init board_setup(void)
+{
+        unsigned short whoami;
+
+        db1300_gpio_config();
+        bcsr_init(DB1300_BCSR_PHYS_ADDR,
+                  DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS);
+
+        whoami = bcsr_read(BCSR_WHOAMI);
+        printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t"
+                "BoardID %d   CPLD Rev %d   DaughtercardID %d\n",
+                BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami),
+                BCSR_WHOAMI_DCID(whoami));
+
+        /* enable UARTs, YAMON only enables #2 */
+        alchemy_uart_enable(AU1300_UART0_PHYS_ADDR);
+        alchemy_uart_enable(AU1300_UART1_PHYS_ADDR);
+        alchemy_uart_enable(AU1300_UART3_PHYS_ADDR);
+}
diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c
new file mode 100644
index 000000000000..6815d0783cd8
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1550.c
@@ -0,0 +1,498 @@
+/*
+ * Alchemy Db1550 board support
+ *
+ * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_eth.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
+#include <asm/mach-au1x00/au1xxx_psc.h>
+#include <asm/mach-au1x00/au1550_spi.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <prom.h>
+#include "platform.h"
+
+
+const char *get_system_type(void)
+{
+        return "DB1550";
+}
+
+static void __init db1550_hw_setup(void)
+{
+        void __iomem *base;
+
+        alchemy_gpio_direction_output(203, 0);  /* red led on */
+
+        /* complete SPI setup: link psc0_intclk to a 48MHz source,
+         * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
+         */
+        base = (void __iomem *)SYS_CLKSRC;
+        __raw_writel(__raw_readl(base) | 0x000001e0, base);
+        base = (void __iomem *)SYS_PINFUNC;
+        __raw_writel(__raw_readl(base) | 1, base);
+        wmb();
+
+        /* reset the AC97 codec now, the reset time in the psc-ac97 driver
+         * is apparently too short although it's ridiculous as it is.
+         */
+        base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
+        __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
+                     base + PSC_SEL_OFFSET);
+        __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
+        wmb();
+        __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
+        wmb();
+
+        alchemy_gpio_direction_output(202, 0);  /* green led on */
+}
+
+void __init board_setup(void)
+{
+        unsigned short whoami;
+
+        bcsr_init(DB1550_BCSR_PHYS_ADDR,
+                  DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
+
+        whoami = bcsr_read(BCSR_WHOAMI);
+        printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d"
+                "  Board-ID %d  Daughtercard ID %d\n",
+                (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
+
+        db1550_hw_setup();
+}
+
+/*****************************************************************************/
+
+static struct mtd_partition db1550_spiflash_parts[] = {
+        {
+                .name   = "spi_flash",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct flash_platform_data db1550_spiflash_data = {
+        .name           = "s25fl010",
+        .parts          = db1550_spiflash_parts,
+        .nr_parts       = ARRAY_SIZE(db1550_spiflash_parts),
+        .type           = "m25p10",
+};
+
+static struct spi_board_info db1550_spi_devs[] __initdata = {
+        {
+                /* TI TMP121AIDBVR temp sensor */
+                .modalias       = "tmp121",
+                .max_speed_hz   = 2400000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,
+        },
+        {
+                /* Spansion S25FL001D0FMA SPI flash */
+                .modalias       = "m25p80",
+                .max_speed_hz   = 2400000,
+                .bus_num        = 0,
+                .chip_select    = 1,
+                .mode           = SPI_MODE_0,
+                .platform_data  = &db1550_spiflash_data,
+        },
+};
+
+static struct i2c_board_info db1550_i2c_devs[] __initdata = {
+        { I2C_BOARD_INFO("24c04",  0x52),}, /* AT24C04-10 I2C eeprom */
+        { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
+        { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
+};
+
+/**********************************************************************/
+
+static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+                                 unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
+
+        ioaddr &= 0xffffff00;
+
+        if (ctrl & NAND_CLE) {
+                ioaddr += MEM_STNAND_CMD;
+        } else if (ctrl & NAND_ALE) {
+                ioaddr += MEM_STNAND_ADDR;
+        } else {
+                /* assume we want to r/w real data  by default */
+                ioaddr += MEM_STNAND_DATA;
+        }
+        this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
+        if (cmd != NAND_CMD_NONE) {
+                __raw_writeb(cmd, this->IO_ADDR_W);
+                wmb();
+        }
+}
+
+static int au1550_nand_device_ready(struct mtd_info *mtd)
+{
+        return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
+}
+
+static const char *db1550_part_probes[] = { "cmdlinepart", NULL };
+
+static struct mtd_partition db1550_nand_parts[] = {
+        {
+                .name   = "NAND FS 0",
+                .offset = 0,
+                .size   = 8 * 1024 * 1024,
+        },
+        {
+                .name   = "NAND FS 1",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL
+        },
+};
+
+struct platform_nand_data db1550_nand_platdata = {
+        .chip = {
+                .nr_chips       = 1,
+                .chip_offset    = 0,
+                .nr_partitions  = ARRAY_SIZE(db1550_nand_parts),
+                .partitions     = db1550_nand_parts,
+                .chip_delay     = 20,
+                .part_probe_types = db1550_part_probes,
+        },
+        .ctrl = {
+                .dev_ready      = au1550_nand_device_ready,
+                .cmd_ctrl       = au1550_nand_cmd_ctrl,
+        },
+};
+
+static struct resource db1550_nand_res[] = {
+        [0] = {
+                .start  = 0x20000000,
+                .end    = 0x200000ff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device db1550_nand_dev = {
+        .name           = "gen_nand",
+        .num_resources  = ARRAY_SIZE(db1550_nand_res),
+        .resource       = db1550_nand_res,
+        .id             = -1,
+        .dev            = {
+                .platform_data = &db1550_nand_platdata,
+        }
+};
+
+/**********************************************************************/
+
+static struct resource au1550_psc0_res[] = {
+        [0] = {
+                .start  = AU1550_PSC0_PHYS_ADDR,
+                .end    = AU1550_PSC0_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1550_PSC0_INT,
+                .end    = AU1550_PSC0_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1550_DSCR_CMD0_PSC0_TX,
+                .end    = AU1550_DSCR_CMD0_PSC0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = AU1550_DSCR_CMD0_PSC0_RX,
+                .end    = AU1550_DSCR_CMD0_PSC0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
+{
+        if (cs)
+                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
+        else
+                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
+}
+
+static struct au1550_spi_info db1550_spi_platdata = {
+        .mainclk_hz     = 48000000,     /* PSC0 clock: max. 2.4MHz SPI clk */
+        .num_chipselect = 2,
+        .activate_cs    = db1550_spi_cs_en,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device db1550_spi_dev = {
+        .dev    = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &db1550_spi_platdata,
+        },
+        .name           = "au1550-spi",
+        .id             = 0,    /* bus number */
+        .num_resources  = ARRAY_SIZE(au1550_psc0_res),
+        .resource       = au1550_psc0_res,
+};
+
+/**********************************************************************/
+
+static struct resource au1550_psc1_res[] = {
+        [0] = {
+                .start  = AU1550_PSC1_PHYS_ADDR,
+                .end    = AU1550_PSC1_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1550_PSC1_INT,
+                .end    = AU1550_PSC1_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1550_DSCR_CMD0_PSC1_TX,
+                .end    = AU1550_DSCR_CMD0_PSC1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = AU1550_DSCR_CMD0_PSC1_RX,
+                .end    = AU1550_DSCR_CMD0_PSC1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1550_ac97_dev = {
+        .name           = "au1xpsc_ac97",
+        .id             = 1,    /* PSC ID */
+        .num_resources  = ARRAY_SIZE(au1550_psc1_res),
+        .resource       = au1550_psc1_res,
+};
+
+
+static struct resource au1550_psc2_res[] = {
+        [0] = {
+                .start  = AU1550_PSC2_PHYS_ADDR,
+                .end    = AU1550_PSC2_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1550_PSC2_INT,
+                .end    = AU1550_PSC2_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1550_DSCR_CMD0_PSC2_TX,
+                .end    = AU1550_DSCR_CMD0_PSC2_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = AU1550_DSCR_CMD0_PSC2_RX,
+                .end    = AU1550_DSCR_CMD0_PSC2_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1550_i2c_dev = {
+        .name           = "au1xpsc_smbus",
+        .id             = 0,    /* bus number */
+        .num_resources  = ARRAY_SIZE(au1550_psc2_res),
+        .resource       = au1550_psc2_res,
+};
+
+/**********************************************************************/
+
+static struct resource au1550_psc3_res[] = {
+        [0] = {
+                .start  = AU1550_PSC3_PHYS_ADDR,
+                .end    = AU1550_PSC3_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1550_PSC3_INT,
+                .end    = AU1550_PSC3_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AU1550_DSCR_CMD0_PSC3_TX,
+                .end    = AU1550_DSCR_CMD0_PSC3_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = AU1550_DSCR_CMD0_PSC3_RX,
+                .end    = AU1550_DSCR_CMD0_PSC3_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1550_i2s_dev = {
+        .name           = "au1xpsc_i2s",
+        .id             = 3,    /* PSC ID */
+        .num_resources  = ARRAY_SIZE(au1550_psc3_res),
+        .resource       = au1550_psc3_res,
+};
+
+/**********************************************************************/
+
+static struct platform_device db1550_stac_dev = {
+        .name           = "ac97-codec",
+        .id             = 1,    /* on PSC1 */
+};
+
+static struct platform_device db1550_ac97dma_dev = {
+        .name           = "au1xpsc-pcm",
+        .id             = 1,    /* on PSC3 */
+};
+
+static struct platform_device db1550_i2sdma_dev = {
+        .name           = "au1xpsc-pcm",
+        .id             = 3,    /* on PSC3 */
+};
+
+static struct platform_device db1550_sndac97_dev = {
+        .name           = "db1550-ac97",
+};
+
+static struct platform_device db1550_sndi2s_dev = {
+        .name           = "db1550-i2s",
+};
+
+/**********************************************************************/
+
+static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
+{
+        if ((slot < 11) || (slot > 13) || pin == 0)
+                return -1;
+        if (slot == 11)
+                return (pin == 1) ? AU1550_PCI_INTC : 0xff;
+        if (slot == 12) {
+                switch (pin) {
+                case 1: return AU1550_PCI_INTB;
+                case 2: return AU1550_PCI_INTC;
+                case 3: return AU1550_PCI_INTD;
+                case 4: return AU1550_PCI_INTA;
+                }
+        }
+        if (slot == 13) {
+                switch (pin) {
+                case 1: return AU1550_PCI_INTA;
+                case 2: return AU1550_PCI_INTB;
+                case 3: return AU1550_PCI_INTC;
+                case 4: return AU1550_PCI_INTD;
+                }
+        }
+        return -1;
+}
+
+static struct resource alchemy_pci_host_res[] = {
+        [0] = {
+                .start  = AU1500_PCI_PHYS_ADDR,
+                .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct alchemy_pci_platdata db1550_pci_pd = {
+        .board_map_irq  = db1550_map_pci_irq,
+};
+
+static struct platform_device db1550_pci_host_dev = {
+        .dev.platform_data = &db1550_pci_pd,
+        .name           = "alchemy-pci",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
+        .resource       = alchemy_pci_host_res,
+};
+
+/**********************************************************************/
+
+static struct platform_device *db1550_devs[] __initdata = {
+        &db1550_nand_dev,
+        &db1550_i2c_dev,
+        &db1550_ac97_dev,
+        &db1550_spi_dev,
+        &db1550_i2s_dev,
+        &db1550_stac_dev,
+        &db1550_ac97dma_dev,
+        &db1550_i2sdma_dev,
+        &db1550_sndac97_dev,
+        &db1550_sndi2s_dev,
+};
+
+/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
+static int __init db1550_pci_init(void)
+{
+        return platform_device_register(&db1550_pci_host_dev);
+}
+arch_initcall(db1550_pci_init);
+
+static int __init db1550_dev_init(void)
+{
+        int swapped;
+
+        irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH);  /* CD0# */
+        irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH);  /* CD1# */
+        irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD0# */
+        irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD1# */
+        irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
+        irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
+
+        i2c_register_board_info(0, db1550_i2c_devs,
+                                ARRAY_SIZE(db1550_i2c_devs));
+        spi_register_board_info(db1550_spi_devs,
+                                ARRAY_SIZE(db1550_i2c_devs));
+
+        /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
+        __raw_writel(PSC_SEL_CLK_SERCLK,
+            (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
+        wmb();
+        __raw_writel(PSC_SEL_CLK_SERCLK,
+            (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
+        wmb();
+        /* SPI/I2C use internally supplied 50MHz source */
+        __raw_writel(PSC_SEL_CLK_INTCLK,
+            (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
+        wmb();
+        __raw_writel(PSC_SEL_CLK_INTCLK,
+            (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
+        wmb();
+
+        db1x_register_pcmcia_socket(
+                AU1000_PCMCIA_ATTR_PHYS_ADDR,
+                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                AU1000_PCMCIA_MEM_PHYS_ADDR,
+                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                AU1000_PCMCIA_IO_PHYS_ADDR,
+                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                AU1550_GPIO3_INT, AU1550_GPIO0_INT,
+                /*AU1550_GPIO21_INT*/0, 0, 0);
+
+        db1x_register_pcmcia_socket(
+                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
+                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
+                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
+                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
+                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
+                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
+                AU1550_GPIO5_INT, AU1550_GPIO1_INT,
+                /*AU1550_GPIO22_INT*/0, 0, 1);
+
+        swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT;
+        db1x_register_norflash(128 << 20, 4, swapped);
+
+        return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
+}
+device_initcall(db1550_dev_init);
diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile
deleted file mode 100644
index 613c0c0c8be9..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-#  Copyright 2000, 2008 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc. <source@mvista.com>
-#
-# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
-#
-
-obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
deleted file mode 100644
index 7cd36e631f6c..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      Alchemy Db1x00 board setup.
- *
- * Copyright 2000, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/pm.h>
-
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-au1x00/au1xxx_eth.h>
-#include <asm/mach-db1x00/db1x00.h>
-#include <asm/mach-db1x00/bcsr.h>
-#include <asm/reboot.h>
-
-#include <prom.h>
-
-#ifdef CONFIG_MIPS_BOSPORUS
-char irq_tab_alchemy[][5] __initdata = {
-        [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI  */
-        [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741   */
-        [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
-};
-
-/*
- * Micrel/Kendin 5 port switch attached to MAC0,
- * MAC0 is associated with PHY address 5 (== WAN port)
- * MAC1 is not associated with any PHY, since it's connected directly
- * to the switch.
- * no interrupts are used
- */
-static struct au1000_eth_platform_data eth0_pdata = {
-        .phy_static_config      = 1,
-        .phy_addr               = 5,
-};
-
-static void bosporus_power_off(void)
-{
-        while (1)
-                asm volatile (".set mips3 ; wait ; .set mips0");
-}
-
-const char *get_system_type(void)
-{
-        return "Alchemy Bosporus Gateway Reference";
-}
-#endif
-
-
-#ifdef CONFIG_MIPS_MIRAGE
-static void mirage_power_off(void)
-{
-        alchemy_gpio_direction_output(210, 1);
-}
-
-const char *get_system_type(void)
-{
-        return "Alchemy Mirage";
-}
-#endif
-
-
-#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
-static void mips_softreset(void)
-{
-        asm volatile ("jr\t%0" : : "r"(0xbfc00000));
-}
-
-#else
-
-const char *get_system_type(void)
-{
-        return "Alchemy Db1x00";
-}
-#endif
-
-
-void __init board_setup(void)
-{
-        unsigned long bcsr1, bcsr2;
-
-        bcsr1 = DB1000_BCSR_PHYS_ADDR;
-        bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
-
-#ifdef CONFIG_MIPS_DB1000
-        printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
-#endif
-#ifdef CONFIG_MIPS_DB1500
-        printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
-#endif
-#ifdef CONFIG_MIPS_DB1100
-        printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
-#endif
-#ifdef CONFIG_MIPS_BOSPORUS
-        au1xxx_override_eth_cfg(0, &eth0_pdata);
-
-        printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
-#endif
-#ifdef CONFIG_MIPS_MIRAGE
-        printk(KERN_INFO "AMD Alchemy Mirage Board\n");
-#endif
-#ifdef CONFIG_MIPS_DB1550
-        printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
-
-        bcsr1 = DB1550_BCSR_PHYS_ADDR;
-        bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
-#endif
-
-        /* initialize board register space */
-        bcsr_init(bcsr1, bcsr2);
-
-#if defined(CONFIG_IRDA) && defined(CONFIG_AU1000_FIR)
-        {
-                u32 pin_func;
-
-                /* Set IRFIRSEL instead of GPIO15 */
-                pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
-                au_writel(pin_func, SYS_PINFUNC);
-                /* Power off until the driver is in use */
-                bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
-                         BCSR_RESETS_IRDA_MODE_OFF);
-        }
-#endif
-        bcsr_write(BCSR_PCMCIA, 0);     /* turn off PCMCIA power */
-
-        /* Enable GPIO[31:0] inputs */
-        alchemy_gpio1_input_enable();
-
-#ifdef CONFIG_MIPS_MIRAGE
-        {
-                u32 pin_func;
-
-                /* GPIO[20] is output */
-                alchemy_gpio_direction_output(20, 0);
-
-                /* Set GPIO[210:208] instead of SSI_0 */
-                pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
-
-                /* Set GPIO[215:211] for LEDs */
-                pin_func |= 5 << 2;
-
-                /* Set GPIO[214:213] for more LEDs */
-                pin_func |= 5 << 12;
-
-                /* Set GPIO[207:200] instead of PCMCIA/LCD */
-                pin_func |= SYS_PF_LCD | SYS_PF_PC;
-                au_writel(pin_func, SYS_PINFUNC);
-
-                /*
-                 * Enable speaker amplifier.  This should
-                 * be part of the audio driver.
-                 */
-                alchemy_gpio_direction_output(209, 1);
-
-                pm_power_off = mirage_power_off;
-                _machine_halt = mirage_power_off;
-                _machine_restart = (void(*)(char *))mips_softreset;
-        }
-#endif
-
-#ifdef CONFIG_MIPS_BOSPORUS
-        pm_power_off = bosporus_power_off;
-        _machine_halt = bosporus_power_off;
-        _machine_restart = (void(*)(char *))mips_softreset;
-#endif
-        au_sync();
-}
-
-static int __init db1x00_init_irq(void)
-{
-#if defined(CONFIG_MIPS_MIRAGE)
-        irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
-#elif defined(CONFIG_MIPS_DB1550)
-        irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);  /* CD0# */
-        irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);  /* CD1# */
-        irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW);  /* CARD0# */
-        irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW);  /* CARD1# */
-        irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
-        irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
-#elif defined(CONFIG_MIPS_DB1500)
-        irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
-        irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
-        irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
-        irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
-        irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
-        irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
-#elif defined(CONFIG_MIPS_DB1100)
-        irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
-        irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
-        irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
-        irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
-        irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
-        irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
-#elif defined(CONFIG_MIPS_DB1000)
-        irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
-        irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
-        irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
-        irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
-        irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
-        irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
-#endif
-        return 0;
-}
-arch_initcall(db1x00_init_irq);
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
deleted file mode 100644
index 9e6b3d442acd..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/platform.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * DBAu1xxx board platform device registration
- *
- * Copyright (C) 2009 Manuel Lauss
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-au1x00/au1000_dma.h>
-#include <asm/mach-db1x00/bcsr.h>
-#include "../platform.h"
-
-struct pci_dev;
-
-/* DB1xxx PCMCIA interrupt sources:
- * CD0/1        GPIO0/3
- * STSCHG0/1    GPIO1/4
- * CARD0/1      GPIO2/5
- * Db1550:      0/1, 21/22, 3/5
- */
-
-#define DB1XXX_HAS_PCMCIA
-#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
-
-#if defined(CONFIG_MIPS_DB1000)
-#define DB1XXX_PCMCIA_CD0       AU1000_GPIO0_INT
-#define DB1XXX_PCMCIA_STSCHG0   AU1000_GPIO1_INT
-#define DB1XXX_PCMCIA_CARD0     AU1000_GPIO2_INT
-#define DB1XXX_PCMCIA_CD1       AU1000_GPIO3_INT
-#define DB1XXX_PCMCIA_STSCHG1   AU1000_GPIO4_INT
-#define DB1XXX_PCMCIA_CARD1     AU1000_GPIO5_INT
-#define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
-#define BOARD_FLASH_WIDTH       4 /* 32-bits */
-#elif defined(CONFIG_MIPS_DB1100)
-#define DB1XXX_PCMCIA_CD0       AU1100_GPIO0_INT
-#define DB1XXX_PCMCIA_STSCHG0   AU1100_GPIO1_INT
-#define DB1XXX_PCMCIA_CARD0     AU1100_GPIO2_INT
-#define DB1XXX_PCMCIA_CD1       AU1100_GPIO3_INT
-#define DB1XXX_PCMCIA_STSCHG1   AU1100_GPIO4_INT
-#define DB1XXX_PCMCIA_CARD1     AU1100_GPIO5_INT
-#define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
-#define BOARD_FLASH_WIDTH       4 /* 32-bits */
-#elif defined(CONFIG_MIPS_DB1500)
-#define DB1XXX_PCMCIA_CD0       AU1500_GPIO0_INT
-#define DB1XXX_PCMCIA_STSCHG0   AU1500_GPIO1_INT
-#define DB1XXX_PCMCIA_CARD0     AU1500_GPIO2_INT
-#define DB1XXX_PCMCIA_CD1       AU1500_GPIO3_INT
-#define DB1XXX_PCMCIA_STSCHG1   AU1500_GPIO4_INT
-#define DB1XXX_PCMCIA_CARD1     AU1500_GPIO5_INT
-#define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
-#define BOARD_FLASH_WIDTH       4 /* 32-bits */
-#elif defined(CONFIG_MIPS_DB1550)
-#define DB1XXX_PCMCIA_CD0       AU1550_GPIO0_INT
-#define DB1XXX_PCMCIA_STSCHG0   AU1550_GPIO21_INT
-#define DB1XXX_PCMCIA_CARD0     AU1550_GPIO3_INT
-#define DB1XXX_PCMCIA_CD1       AU1550_GPIO1_INT
-#define DB1XXX_PCMCIA_STSCHG1   AU1550_GPIO22_INT
-#define DB1XXX_PCMCIA_CARD1     AU1550_GPIO5_INT
-#define BOARD_FLASH_SIZE        0x08000000 /* 128MB */
-#define BOARD_FLASH_WIDTH       4 /* 32-bits */
-#else
-/* other board: no PCMCIA */
-#undef DB1XXX_HAS_PCMCIA
-#undef F_SWAPPED
-#define F_SWAPPED 0
-#if defined(CONFIG_MIPS_BOSPORUS)
-#define BOARD_FLASH_SIZE        0x01000000 /* 16MB */
-#define BOARD_FLASH_WIDTH       2 /* 16-bits */
-#elif defined(CONFIG_MIPS_MIRAGE)
-#define BOARD_FLASH_SIZE        0x04000000 /* 64MB */
-#define BOARD_FLASH_WIDTH       4 /* 32-bits */
-#endif
-#endif
-
-#ifdef CONFIG_PCI
-#ifdef CONFIG_MIPS_DB1500
-static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
-{
-        if ((slot < 12) || (slot > 13) || pin == 0)
-                return -1;
-        if (slot == 12)
-                return (pin == 1) ? AU1500_PCI_INTA : 0xff;
-        if (slot == 13) {
-                switch (pin) {
-                case 1: return AU1500_PCI_INTA;
-                case 2: return AU1500_PCI_INTB;
-                case 3: return AU1500_PCI_INTC;
-                case 4: return AU1500_PCI_INTD;
-                }
-        }
-        return -1;
-}
-#endif
-
-#ifdef CONFIG_MIPS_DB1550
-static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
-{
-        if ((slot < 11) || (slot > 13) || pin == 0)
-                return -1;
-        if (slot == 11)
-                return (pin == 1) ? AU1550_PCI_INTC : 0xff;
-        if (slot == 12) {
-                switch (pin) {
-                case 1: return AU1550_PCI_INTB;
-                case 2: return AU1550_PCI_INTC;
-                case 3: return AU1550_PCI_INTD;
-                case 4: return AU1550_PCI_INTA;
-                }
-        }
-        if (slot == 13) {
-                switch (pin) {
-                case 1: return AU1550_PCI_INTA;
-                case 2: return AU1550_PCI_INTB;
-                case 3: return AU1550_PCI_INTC;
-                case 4: return AU1550_PCI_INTD;
-                }
-        }
-        return -1;
-}
-#endif
-
-#ifdef CONFIG_MIPS_BOSPORUS
-static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
-{
-        if ((slot < 11) || (slot > 13) || pin == 0)
-                return -1;
-        if (slot == 12)
-                return (pin == 1) ? AU1500_PCI_INTA : 0xff;
-        if (slot == 11) {
-                switch (pin) {
-                case 1: return AU1500_PCI_INTA;
-                case 2: return AU1500_PCI_INTB;
-                default: return 0xff;
-                }
-        }
-        if (slot == 13) {
-                switch (pin) {
-                case 1: return AU1500_PCI_INTA;
-                case 2: return AU1500_PCI_INTB;
-                case 3: return AU1500_PCI_INTC;
-                case 4: return AU1500_PCI_INTD;
-                }
-        }
-        return -1;
-}
-#endif
-
-#ifdef CONFIG_MIPS_MIRAGE
-static int db1xxx_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
-{
-        if ((slot < 11) || (slot > 13) || pin == 0)
-                return -1;
-        if (slot == 11)
-                return (pin == 1) ? AU1500_PCI_INTD : 0xff;
-        if (slot == 12)
-                return (pin == 3) ? AU1500_PCI_INTC : 0xff;
-        if (slot == 13) {
-                switch (pin) {
-                case 1: return AU1500_PCI_INTA;
-                case 2: return AU1500_PCI_INTB;
-                default: return 0xff;
-                }
-        }
-        return -1;
-}
-#endif
-
-static struct resource alchemy_pci_host_res[] = {
-        [0] = {
-                .start  = AU1500_PCI_PHYS_ADDR,
-                .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct alchemy_pci_platdata db1xxx_pci_pd = {
-        .board_map_irq  = db1xxx_map_pci_irq,
-};
-
-static struct platform_device db1xxx_pci_host_dev = {
-        .dev.platform_data = &db1xxx_pci_pd,
-        .name           = "alchemy-pci",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
-        .resource       = alchemy_pci_host_res,
-};
-
-static int __init db15x0_pci_init(void)
-{
-        return platform_device_register(&db1xxx_pci_host_dev);
-}
-/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
-arch_initcall(db15x0_pci_init);
-#endif
-
-#ifdef CONFIG_MIPS_DB1100
-static struct resource au1100_lcd_resources[] = {
-        [0] = {
-                .start  = AU1100_LCD_PHYS_ADDR,
-                .end    = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AU1100_LCD_INT,
-                .end    = AU1100_LCD_INT,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1100_lcd_device = {
-        .name           = "au1100-lcd",
-        .id             = 0,
-        .dev = {
-                .dma_mask               = &au1100_lcd_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .num_resources  = ARRAY_SIZE(au1100_lcd_resources),
-        .resource       = au1100_lcd_resources,
-};
-#endif
-
-static struct resource alchemy_ac97c_res[] = {
-        [0] = {
-                .start  = AU1000_AC97_PHYS_ADDR,
-                .end    = AU1000_AC97_PHYS_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMA_ID_AC97C_TX,
-                .end    = DMA_ID_AC97C_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMA_ID_AC97C_RX,
-                .end    = DMA_ID_AC97C_RX,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-
-static struct platform_device alchemy_ac97c_dev = {
-        .name           = "alchemy-ac97c",
-        .id             = -1,
-        .resource       = alchemy_ac97c_res,
-        .num_resources  = ARRAY_SIZE(alchemy_ac97c_res),
-};
-
-static struct platform_device alchemy_ac97c_dma_dev = {
-        .name           = "alchemy-pcm-dma",
-        .id             = 0,
-};
-
-static struct platform_device db1x00_codec_dev = {
-        .name           = "ac97-codec",
-        .id             = -1,
-};
-
-static struct platform_device db1x00_audio_dev = {
-        .name           = "db1000-audio",
-};
-
-static int __init db1xxx_dev_init(void)
-{
-#ifdef DB1XXX_HAS_PCMCIA
-        db1x_register_pcmcia_socket(
-                AU1000_PCMCIA_ATTR_PHYS_ADDR,
-                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
-                AU1000_PCMCIA_MEM_PHYS_ADDR,
-                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
-                AU1000_PCMCIA_IO_PHYS_ADDR,
-                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
-                DB1XXX_PCMCIA_CARD0, DB1XXX_PCMCIA_CD0,
-                /*DB1XXX_PCMCIA_STSCHG0*/0, 0, 0);
-
-        db1x_register_pcmcia_socket(
-                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
-                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
-                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
-                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
-                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
-                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
-                DB1XXX_PCMCIA_CARD1, DB1XXX_PCMCIA_CD1,
-                /*DB1XXX_PCMCIA_STSCHG1*/0, 0, 1);
-#endif
-#ifdef CONFIG_MIPS_DB1100
-        platform_device_register(&au1100_lcd_device);
-#endif
-        db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
-
-        platform_device_register(&db1x00_codec_dev);
-        platform_device_register(&alchemy_ac97c_dma_dev);
-        platform_device_register(&alchemy_ac97c_dev);
-        platform_device_register(&db1x00_audio_dev);
-
-        return 0;
-}
-device_initcall(db1xxx_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile
deleted file mode 100644
index 97c6615ba2bb..000000000000
--- a/arch/mips/alchemy/devboards/pb1000/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-#  Copyright 2000, 2008 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc. <source@mvista.com>
-#
-# Makefile for the Alchemy Semiconductor Pb1000 board.
-#
-
-obj-y := board_setup.o
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
deleted file mode 100644
index e64fdcbf75d0..000000000000
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * Copyright 2000, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/pm.h>
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-pb1x00/pb1000.h>
-#include <asm/reboot.h>
-#include <prom.h>
-
-#include "../platform.h"
-
-const char *get_system_type(void)
-{
-        return "Alchemy Pb1000";
-}
-
-static void board_reset(char *c)
-{
-        asm volatile ("jr %0" : : "r" (0xbfc00000));
-}
-
-static void board_power_off(void)
-{
-        while (1)
-                asm volatile (
-                "       .set    mips32                                  \n"
-                "       wait                                            \n"
-                "       .set    mips0                                   \n");
-}
-
-void __init board_setup(void)
-{
-        u32 pin_func, static_cfg0;
-        u32 sys_freqctrl, sys_clksrc;
-        u32 prid = read_c0_prid();
-
-        sys_freqctrl = 0;
-        sys_clksrc = 0;
-
-        /* Set AUX clock to 12 MHz * 8 = 96 MHz */
-        au_writel(8, SYS_AUXPLL);
-        alchemy_gpio1_input_enable();
-        udelay(100);
-
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-        /* Zero and disable FREQ2 */
-        sys_freqctrl = au_readl(SYS_FREQCTRL0);
-        sys_freqctrl &= ~0xFFF00000;
-        au_writel(sys_freqctrl, SYS_FREQCTRL0);
-
-        /* Zero and disable USBH/USBD clocks */
-        sys_clksrc = au_readl(SYS_CLKSRC);
-        sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
-                        SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
-        au_writel(sys_clksrc, SYS_CLKSRC);
-
-        sys_freqctrl = au_readl(SYS_FREQCTRL0);
-        sys_freqctrl &= ~0xFFF00000;
-
-        sys_clksrc = au_readl(SYS_CLKSRC);
-        sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
-                        SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
-
-        switch (prid & 0x000000FF) {
-        case 0x00: /* DA */
-        case 0x01: /* HA */
-        case 0x02: /* HB */
-                /* CPU core freq to 48 MHz to slow it way down... */
-                au_writel(4, SYS_CPUPLL);
-
-                /*
-                 * Setup 48 MHz FREQ2 from CPUPLL for USB Host
-                 * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
-                 */
-                sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
-                au_writel(sys_freqctrl, SYS_FREQCTRL0);
-
-                /* CPU core freq to 384 MHz */
-                au_writel(0x20, SYS_CPUPLL);
-
-                printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
-                break;
-
-        default: /* HC and newer */
-                /* FREQ2 = aux / 2 = 48 MHz */
-                sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
-                                 SYS_FC_FE2 | SYS_FC_FS2;
-                au_writel(sys_freqctrl, SYS_FREQCTRL0);
-                break;
-        }
-
-        /*
-         * Route 48 MHz FREQ2 into USB Host and/or Device
-         */
-        sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
-        au_writel(sys_clksrc, SYS_CLKSRC);
-
-        /* Configure pins GPIO[14:9] as GPIO */
-        pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
-
-        /* 2nd USB port is USB host */
-        pin_func |= SYS_PF_USB;
-
-        au_writel(pin_func, SYS_PINFUNC);
-
-        alchemy_gpio_direction_input(11);
-        alchemy_gpio_direction_input(13);
-        alchemy_gpio_direction_output(4, 0);
-        alchemy_gpio_direction_output(5, 0);
-#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
-
-        /* Make GPIO 15 an input (for interrupt line) */
-        pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
-        /* We don't need I2S, so make it available for GPIO[31:29] */
-        pin_func |= SYS_PF_I2S;
-        au_writel(pin_func, SYS_PINFUNC);
-
-        alchemy_gpio_direction_input(15);
-
-        static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
-        au_writel(static_cfg0, MEM_STCFG0);
-
-        /* configure RCE2* for LCD */
-        au_writel(0x00000004, MEM_STCFG2);
-
-        /* MEM_STTIME2 */
-        au_writel(0x09000000, MEM_STTIME2);
-
-        /* Set 32-bit base address decoding for RCE2* */
-        au_writel(0x10003ff0, MEM_STADDR2);
-
-        /*
-         * PCI CPLD setup
-         * Expand CE0 to cover PCI
-         */
-        au_writel(0x11803e40, MEM_STADDR1);
-
-        /* Burst visibility on */
-        au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
-
-        au_writel(0x83, MEM_STCFG1);         /* ewait enabled, flash timing */
-        au_writel(0x33030a10, MEM_STTIME1);  /* slower timing for FPGA */
-
-        /* Setup the static bus controller */
-        au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
-        au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
-        au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
-
-        /*
-         * Enable Au1000 BCLK switching - note: sed1356 must not use
-         * its BCLK (Au1000 LCLK) for any timings
-         */
-        switch (prid & 0x000000FF) {
-        case 0x00: /* DA */
-        case 0x01: /* HA */
-        case 0x02: /* HB */
-                break;
-        default:  /* HC and newer */
-                /*
-                 * Enable sys bus clock divider when IDLE state or no bus
-                 * activity.
-                 */
-                au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
-                break;
-        }
-
-        pm_power_off = board_power_off;
-        _machine_halt = board_power_off;
-        _machine_restart = board_reset;
-}
-
-static int __init pb1000_init_irq(void)
-{
-        irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
-        return 0;
-}
-arch_initcall(pb1000_init_irq);
-
-static int __init pb1000_device_init(void)
-{
-        return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
-}
-device_initcall(pb1000_device_init);
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100.c
index d108fd573aaf..cff50d05ddd4 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100.c
@@ -1,42 +1,37 @@
 /*
- * Copyright 2002, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
+ * Pb1100 board platform device registration
  *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
+ * Copyright (C) 2009 Manuel Lauss
  *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/delay.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
-#include <linux/delay.h>
 #include <linux/interrupt.h>
-
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-db1x00/bcsr.h>
-
 #include <prom.h>
-
+#include "platform.h"
 
 const char *get_system_type(void)
 {
-        return "Alchemy Pb1100";
+        return "PB1100";
 }
 
 void __init board_setup(void)
@@ -115,13 +110,58 @@ void __init board_setup(void)
         }
 }
 
-static int __init pb1100_init_irq(void)
+/******************************************************************************/
+
+static struct resource au1100_lcd_resources[] = {
+        [0] = {
+                .start  = AU1100_LCD_PHYS_ADDR,
+                .end    = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1100_LCD_INT,
+                .end    = AU1100_LCD_INT,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device au1100_lcd_device = {
+        .name           = "au1100-lcd",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = &au1100_lcd_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(au1100_lcd_resources),
+        .resource       = au1100_lcd_resources,
+};
+
+static int __init pb1100_dev_init(void)
 {
+        int swapped;
+
         irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
         irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
         irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
         irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
 
+        /* PCMCIA. single socket, identical to Pb1500 */
+        db1x_register_pcmcia_socket(
+                AU1000_PCMCIA_ATTR_PHYS_ADDR,
+                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                AU1000_PCMCIA_MEM_PHYS_ADDR,
+                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                AU1000_PCMCIA_IO_PHYS_ADDR,
+                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                AU1100_GPIO11_INT, AU1100_GPIO9_INT,     /* card / insert */
+                /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
+
+        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1000_SWAPBOOT;
+        db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
+        platform_device_register(&au1100_lcd_device);
+
         return 0;
 }
-arch_initcall(pb1100_init_irq);
+device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile
deleted file mode 100644
index 7e3756c83fe5..000000000000
--- a/arch/mips/alchemy/devboards/pb1100/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-#  Copyright 2000, 2001, 2008 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc. <source@mvista.com>
-#
-# Makefile for the Alchemy Semiconductor Pb1100 board.
-#
-
-obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
deleted file mode 100644
index 9c57c01a68c4..000000000000
--- a/arch/mips/alchemy/devboards/pb1100/platform.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Pb1100 board platform device registration
- *
- * Copyright (C) 2009 Manuel Lauss
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/init.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-db1x00/bcsr.h>
-
-#include "../platform.h"
-
-static struct resource au1100_lcd_resources[] = {
-        [0] = {
-                .start  = AU1100_LCD_PHYS_ADDR,
-                .end    = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AU1100_LCD_INT,
-                .end    = AU1100_LCD_INT,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1100_lcd_device = {
-        .name           = "au1100-lcd",
-        .id             = 0,
-        .dev = {
-                .dma_mask               = &au1100_lcd_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .num_resources  = ARRAY_SIZE(au1100_lcd_resources),
-        .resource       = au1100_lcd_resources,
-};
-
-static int __init pb1100_dev_init(void)
-{
-        int swapped;
-
-        /* PCMCIA. single socket, identical to Pb1500 */
-        db1x_register_pcmcia_socket(
-                AU1000_PCMCIA_ATTR_PHYS_ADDR,
-                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
-                AU1000_PCMCIA_MEM_PHYS_ADDR,
-                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
-                AU1000_PCMCIA_IO_PHYS_ADDR,
-                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
-                AU1100_GPIO11_INT, AU1100_GPIO9_INT,     /* card / insert */
-                /*AU1100_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
-
-        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1000_SWAPBOOT;
-        db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
-        platform_device_register(&au1100_lcd_device);
-
-        return 0;
-}
-device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
deleted file mode 100644
index 18c1bd53e4c0..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
-#
-
-obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
deleted file mode 100644
index 6d06b07c2381..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/board_setup.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      Alchemy Pb1200/Db1200 board setup.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-db1x00/bcsr.h>
-
-#ifdef CONFIG_MIPS_PB1200
-#include <asm/mach-pb1x00/pb1200.h>
-#endif
-
-#ifdef CONFIG_MIPS_DB1200
-#include <asm/mach-db1x00/db1200.h>
-#define PB1200_INT_BEGIN DB1200_INT_BEGIN
-#define PB1200_INT_END DB1200_INT_END
-#endif
-
-#include <prom.h>
-
-const char *get_system_type(void)
-{
-        return "Alchemy Pb1200";
-}
-
-void __init board_setup(void)
-{
-        printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
-        bcsr_init(PB1200_BCSR_PHYS_ADDR,
-                  PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
-
-#if 0
-        {
-                u32 pin_func;
-
-                /*
-                 * Enable PSC1 SYNC for AC97.  Normaly done in audio driver,
-                 * but it is board specific code, so put it here.
-                 */
-                pin_func = au_readl(SYS_PINFUNC);
-                au_sync();
-                pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
-                au_writel(pin_func, SYS_PINFUNC);
-
-                au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
-                au_sync();
-        }
-#endif
-
-#if defined(CONFIG_I2C_AU1550)
-        {
-                u32 freq0, clksrc;
-                u32 pin_func;
-
-                /* Select SMBus in CPLD */
-                bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
-
-                pin_func = au_readl(SYS_PINFUNC);
-                au_sync();
-                pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
-                /* Set GPIOs correctly */
-                pin_func |= 2 << 17;
-                au_writel(pin_func, SYS_PINFUNC);
-                au_sync();
-
-                /* The I2C driver depends on 50 MHz clock */
-                freq0 = au_readl(SYS_FREQCTRL0);
-                au_sync();
-                freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
-                freq0 |= 3 << SYS_FC_FRDIV1_BIT;
-                /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
-                au_writel(freq0, SYS_FREQCTRL0);
-                au_sync();
-                freq0 |= SYS_FC_FE1;
-                au_writel(freq0, SYS_FREQCTRL0);
-                au_sync();
-
-                clksrc = au_readl(SYS_CLKSRC);
-                au_sync();
-                clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
-                /* Bit 22 is EXTCLK0 for PSC0 */
-                clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
-                au_writel(clksrc, SYS_CLKSRC);
-                au_sync();
-        }
-#endif
-
-        /*
-         * The Pb1200 development board uses external MUX for PSC0 to
-         * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
-         */
-#ifdef CONFIG_I2C_AU1550
-        bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
-#endif
-        au_sync();
-}
-
-static int __init pb1200_init_irq(void)
-{
-        /* We have a problem with CPLD rev 3. */
-        if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
-                printk(KERN_ERR "updated to latest revision. This software will\n");
-                printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                panic("Game over.  Your score is 0.");
-        }
-
-        irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
-        bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
-
-        return 0;
-}
-arch_initcall(pb1200_init_irq);
-
-
-int board_au1200fb_panel(void)
-{
-        return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
-}
-
-int board_au1200fb_panel_init(void)
-{
-        /* Apply power */
-        bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
-                                BCSR_BOARD_LCDBL);
-        /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
-        return 0;
-}
-
-int board_au1200fb_panel_shutdown(void)
-{
-        /* Remove power */
-        bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
-                             BCSR_BOARD_LCDBL, 0);
-        /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
-        return 0;
-}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
deleted file mode 100644
index 54f7f7b0676e..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * Pb1200/DBAu1200 board platform device registration
- *
- * Copyright (C) 2008 MontaVista Software Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/init.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/smc91x.h>
-
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-au1x00/au1100_mmc.h>
-#include <asm/mach-au1x00/au1xxx_dbdma.h>
-#include <asm/mach-db1x00/bcsr.h>
-#include <asm/mach-pb1x00/pb1200.h>
-
-#include "../platform.h"
-
-static int mmc_activity;
-
-static void pb1200mmc0_set_power(void *mmc_host, int state)
-{
-        if (state)
-                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
-        else
-                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
-
-        msleep(1);
-}
-
-static int pb1200mmc0_card_readonly(void *mmc_host)
-{
-        return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
-}
-
-static int pb1200mmc0_card_inserted(void *mmc_host)
-{
-        return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
-}
-
-static void pb1200_mmcled_set(struct led_classdev *led,
-                        enum led_brightness brightness)
-{
-        if (brightness != LED_OFF) {
-                if (++mmc_activity == 1)
-                        bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
-        } else {
-                if (--mmc_activity == 0)
-                        bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
-        }
-}
-
-static struct led_classdev pb1200mmc_led = {
-        .brightness_set = pb1200_mmcled_set,
-};
-
-static void pb1200mmc1_set_power(void *mmc_host, int state)
-{
-        if (state)
-                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
-        else
-                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
-
-        msleep(1);
-}
-
-static int pb1200mmc1_card_readonly(void *mmc_host)
-{
-        return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
-}
-
-static int pb1200mmc1_card_inserted(void *mmc_host)
-{
-        return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
-}
-
-static struct au1xmmc_platform_data pb1200mmc_platdata[2] = {
-        [0] = {
-                .set_power      = pb1200mmc0_set_power,
-                .card_inserted  = pb1200mmc0_card_inserted,
-                .card_readonly  = pb1200mmc0_card_readonly,
-                .cd_setup       = NULL,         /* use poll-timer in driver */
-                .led            = &pb1200mmc_led,
-        },
-        [1] = {
-                .set_power      = pb1200mmc1_set_power,
-                .card_inserted  = pb1200mmc1_card_inserted,
-                .card_readonly  = pb1200mmc1_card_readonly,
-                .cd_setup       = NULL,         /* use poll-timer in driver */
-                .led            = &pb1200mmc_led,
-        },
-};
-
-static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
-
-static struct resource au1200_mmc0_res[] = {
-        [0] = {
-                .start  = AU1100_SD0_PHYS_ADDR,
-                .end    = AU1100_SD0_PHYS_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AU1200_SD_INT,
-                .end    = AU1200_SD_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = AU1200_DSCR_CMD0_SDMS_TX0,
-                .end    = AU1200_DSCR_CMD0_SDMS_TX0,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start  = AU1200_DSCR_CMD0_SDMS_RX0,
-                .end    = AU1200_DSCR_CMD0_SDMS_RX0,
-                .flags  = IORESOURCE_DMA,
-        }
-};
-
-static struct platform_device pb1200_mmc0_dev = {
-        .name           = "au1xxx-mmc",
-        .id             = 0,
-        .dev = {
-                .dma_mask               = &au1xxx_mmc_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &pb1200mmc_platdata[0],
-        },
-        .num_resources  = ARRAY_SIZE(au1200_mmc0_res),
-        .resource       = au1200_mmc0_res,
-};
-
-static struct resource au1200_mmc1_res[] = {
-        [0] = {
-                .start  = AU1100_SD1_PHYS_ADDR,
-                .end    = AU1100_SD1_PHYS_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AU1200_SD_INT,
-                .end    = AU1200_SD_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = AU1200_DSCR_CMD0_SDMS_TX1,
-                .end    = AU1200_DSCR_CMD0_SDMS_TX1,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start  = AU1200_DSCR_CMD0_SDMS_RX1,
-                .end    = AU1200_DSCR_CMD0_SDMS_RX1,
-                .flags  = IORESOURCE_DMA,
-        }
-};
-
-static struct platform_device pb1200_mmc1_dev = {
-        .name           = "au1xxx-mmc",
-        .id             = 1,
-        .dev = {
-                .dma_mask               = &au1xxx_mmc_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &pb1200mmc_platdata[1],
-        },
-        .num_resources  = ARRAY_SIZE(au1200_mmc1_res),
-        .resource       = au1200_mmc1_res,
-};
-
-
-static struct resource ide_resources[] = {
-        [0] = {
-                .start  = IDE_PHYS_ADDR,
-                .end    = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
-                .start  = IDE_INT,
-                .end    = IDE_INT,
-                .flags  = IORESOURCE_IRQ
-        },
-        [2] = {
-                .start  = AU1200_DSCR_CMD0_DMA_REQ1,
-                .end    = AU1200_DSCR_CMD0_DMA_REQ1,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-
-static u64 ide_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device ide_device = {
-        .name           = "au1200-ide",
-        .id             = 0,
-        .dev = {
-                .dma_mask               = &ide_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .num_resources  = ARRAY_SIZE(ide_resources),
-        .resource       = ide_resources
-};
-
-static struct smc91x_platdata smc_data = {
-        .flags  = SMC91X_NOWAIT | SMC91X_USE_16BIT,
-        .leda   = RPC_LED_100_10,
-        .ledb   = RPC_LED_TX_RX,
-};
-
-static struct resource smc91c111_resources[] = {
-        [0] = {
-                .name   = "smc91x-regs",
-                .start  = SMC91C111_PHYS_ADDR,
-                .end    = SMC91C111_PHYS_ADDR + 0xf,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
-                .start  = SMC91C111_INT,
-                .end    = SMC91C111_INT,
-                .flags  = IORESOURCE_IRQ
-        },
-};
-
-static struct platform_device smc91c111_device = {
-        .dev    = {
-                .platform_data  = &smc_data,
-        },
-        .name           = "smc91x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smc91c111_resources),
-        .resource       = smc91c111_resources
-};
-
-static struct resource au1200_psc0_res[] = {
-        [0] = {
-                .start  = AU1550_PSC0_PHYS_ADDR,
-                .end    = AU1550_PSC0_PHYS_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AU1200_PSC0_INT,
-                .end    = AU1200_PSC0_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = AU1200_DSCR_CMD0_PSC0_TX,
-                .end    = AU1200_DSCR_CMD0_PSC0_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start  = AU1200_DSCR_CMD0_PSC0_RX,
-                .end    = AU1200_DSCR_CMD0_PSC0_RX,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-
-static struct platform_device pb1200_i2c_dev = {
-        .name           = "au1xpsc_smbus",
-        .id             = 0,    /* bus number */
-        .num_resources  = ARRAY_SIZE(au1200_psc0_res),
-        .resource       = au1200_psc0_res,
-};
-
-static struct resource au1200_lcd_res[] = {
-        [0] = {
-                .start  = AU1200_LCD_PHYS_ADDR,
-                .end    = AU1200_LCD_PHYS_ADDR + 0x800 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AU1200_LCD_INT,
-                .end    = AU1200_LCD_INT,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device au1200_lcd_dev = {
-        .name           = "au1200-lcd",
-        .id             = 0,
-        .dev = {
-                .dma_mask               = &au1200_lcd_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .num_resources  = ARRAY_SIZE(au1200_lcd_res),
-        .resource       = au1200_lcd_res,
-};
-
-static struct platform_device *board_platform_devices[] __initdata = {
-        &ide_device,
-        &smc91c111_device,
-        &pb1200_i2c_dev,
-        &pb1200_mmc0_dev,
-        &pb1200_mmc1_dev,
-        &au1200_lcd_dev,
-};
-
-static int __init board_register_devices(void)
-{
-        int swapped;
-
-        db1x_register_pcmcia_socket(
-                AU1000_PCMCIA_ATTR_PHYS_ADDR,
-                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
-                AU1000_PCMCIA_MEM_PHYS_ADDR,
-                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
-                AU1000_PCMCIA_IO_PHYS_ADDR,
-                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
-                PB1200_PC0_INT, PB1200_PC0_INSERT_INT,
-                /*PB1200_PC0_STSCHG_INT*/0, PB1200_PC0_EJECT_INT, 0);
-
-        db1x_register_pcmcia_socket(
-                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
-                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
-                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x008000000,
-                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x008400000 - 1,
-                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x008000000,
-                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x008010000 - 1,
-                PB1200_PC1_INT, PB1200_PC1_INSERT_INT,
-                /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1);
-
-        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1200_SWAPBOOT;
-        db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
-
-        return platform_add_devices(board_platform_devices,
-                                    ARRAY_SIZE(board_platform_devices));
-}
-device_initcall(board_register_devices);
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500.c
index 37c1883b5ea9..e7b807b3ec51 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500.c
@@ -1,41 +1,37 @@
 /*
- * Copyright 2000, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
+ * Pb1500 board support.
  *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
+ * Copyright (C) 2009 Manuel Lauss
  *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
-
+#include <linux/platform_device.h>
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-db1x00/bcsr.h>
-
 #include <prom.h>
+#include "platform.h"
 
 const char *get_system_type(void)
 {
-        return "Alchemy Pb1500";
+        return "PB1500";
 }
 
 void __init board_setup(void)
@@ -123,17 +119,80 @@ void __init board_setup(void)
         }
 }
 
-static int __init pb1500_init_irq(void)
+/******************************************************************************/
+
+static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 {
-        irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW);   /* CD0# */
-        irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW);  /* CARD0 */
-        irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW);  /* STSCHG0# */
+        if ((slot < 12) || (slot > 13) || pin == 0)
+                return -1;
+        if (slot == 12)
+                return (pin == 1) ? AU1500_PCI_INTA : 0xff;
+        if (slot == 13) {
+                switch (pin) {
+                case 1: return AU1500_PCI_INTA;
+                case 2: return AU1500_PCI_INTB;
+                case 3: return AU1500_PCI_INTC;
+                case 4: return AU1500_PCI_INTD;
+                }
+        }
+        return -1;
+}
+
+static struct resource alchemy_pci_host_res[] = {
+        [0] = {
+                .start  = AU1500_PCI_PHYS_ADDR,
+                .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct alchemy_pci_platdata pb1500_pci_pd = {
+        .board_map_irq  = pb1500_map_pci_irq,
+        .pci_cfg_set    = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
+                          PCI_CONFIG_CH |
+#if defined(__MIPSEB__)
+                          PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
+#else
+                          0,
+#endif
+};
+
+static struct platform_device pb1500_pci_host = {
+        .dev.platform_data = &pb1500_pci_pd,
+        .name           = "alchemy-pci",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
+        .resource       = alchemy_pci_host_res,
+};
+
+static int __init pb1500_dev_init(void)
+{
+        int swapped;
+
+        irq_set_irq_type(AU1500_GPIO9_INT,   IRQF_TRIGGER_LOW);   /* CD0# */
+        irq_set_irq_type(AU1500_GPIO10_INT,  IRQF_TRIGGER_LOW);  /* CARD0 */
+        irq_set_irq_type(AU1500_GPIO11_INT,  IRQF_TRIGGER_LOW);  /* STSCHG0# */
         irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
         irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
         irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
         irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
         irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
 
+        /* PCMCIA. single socket, identical to Pb1100 */
+        db1x_register_pcmcia_socket(
+                AU1000_PCMCIA_ATTR_PHYS_ADDR,
+                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                AU1000_PCMCIA_MEM_PHYS_ADDR,
+                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                AU1000_PCMCIA_IO_PHYS_ADDR,
+                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                AU1500_GPIO11_INT, AU1500_GPIO9_INT,     /* card / insert */
+                /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
+
+        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1000_SWAPBOOT;
+        db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
+        platform_device_register(&pb1500_pci_host);
+
         return 0;
 }
-arch_initcall(pb1500_init_irq);
+arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile
deleted file mode 100644
index e83b151b5b63..000000000000
--- a/arch/mips/alchemy/devboards/pb1500/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-#  Copyright 2000, 2001, 2008 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc. <source@mvista.com>
-#
-# Makefile for the Alchemy Semiconductor Pb1500 board.
-#
-
-obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
deleted file mode 100644
index 1e52a01bac00..000000000000
--- a/arch/mips/alchemy/devboards/pb1500/platform.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Pb1500 board platform device registration
- *
- * Copyright (C) 2009 Manuel Lauss
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-db1x00/bcsr.h>
-
-#include "../platform.h"
-
-static int pb1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
-{
-        if ((slot < 12) || (slot > 13) || pin == 0)
-                return -1;
-        if (slot == 12)
-                return (pin == 1) ? AU1500_PCI_INTA : 0xff;
-        if (slot == 13) {
-                switch (pin) {
-                case 1: return AU1500_PCI_INTA;
-                case 2: return AU1500_PCI_INTB;
-                case 3: return AU1500_PCI_INTC;
-                case 4: return AU1500_PCI_INTD;
-                }
-        }
-        return -1;
-}
-
-static struct resource alchemy_pci_host_res[] = {
-        [0] = {
-                .start  = AU1500_PCI_PHYS_ADDR,
-                .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct alchemy_pci_platdata pb1500_pci_pd = {
-        .board_map_irq  = pb1500_map_pci_irq,
-        .pci_cfg_set    = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
-                          PCI_CONFIG_CH |
-#if defined(__MIPSEB__)
-                          PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
-#else
-                          0,
-#endif
-};
-
-static struct platform_device pb1500_pci_host = {
-        .dev.platform_data = &pb1500_pci_pd,
-        .name           = "alchemy-pci",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
-        .resource       = alchemy_pci_host_res,
-};
-
-static int __init pb1500_dev_init(void)
-{
-        int swapped;
-
-        /* PCMCIA. single socket, identical to Pb1100 */
-        db1x_register_pcmcia_socket(
-                AU1000_PCMCIA_ATTR_PHYS_ADDR,
-                AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
-                AU1000_PCMCIA_MEM_PHYS_ADDR,
-                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
-                AU1000_PCMCIA_IO_PHYS_ADDR,
-                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
-                AU1500_GPIO11_INT, AU1500_GPIO9_INT,     /* card / insert */
-                /*AU1500_GPIO10_INT*/0, 0, 0); /* stschg / eject / id */
-
-        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1000_SWAPBOOT;
-        db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
-        platform_device_register(&pb1500_pci_host);
-
-        return 0;
-}
-arch_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550.c
index a4604b8a349e..b37e7de8d920 100644
--- a/arch/mips/alchemy/devboards/pb1550/platform.c
+++ b/arch/mips/alchemy/devboards/pb1550.c
@@ -1,7 +1,7 @@
 /*
- * Pb1550 board platform device registration
+ * Pb1550 board support.
  *
- * Copyright (C) 2009 Manuel Lauss
+ * Copyright (C) 2009-2011 Manuel Lauss
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,13 +20,44 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
-#include <asm/mach-pb1x00/pb1550.h>
+#include <asm/mach-au1x00/au1550nd.h>
+#include <asm/mach-au1x00/gpio.h>
 #include <asm/mach-db1x00/bcsr.h>
+#include "platform.h"
 
-#include "../platform.h"
+const char *get_system_type(void)
+{
+        return "PB1550";
+}
+
+void __init board_setup(void)
+{
+        u32 pin_func;
+
+        bcsr_init(PB1550_BCSR_PHYS_ADDR,
+                  PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
+
+        alchemy_gpio2_enable();
+
+        /*
+         * Enable PSC1 SYNC for AC'97.  Normaly done in audio driver,
+         * but it is board specific code, so put it here.
+         */
+        pin_func = au_readl(SYS_PINFUNC);
+        au_sync();
+        pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
+        au_writel(pin_func, SYS_PINFUNC);
+
+        bcsr_write(BCSR_PCMCIA, 0);     /* turn off PCMCIA power */
+
+        printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
+}
+
+/******************************************************************************/
 
 static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 {
@@ -101,10 +132,79 @@ static struct platform_device pb1550_i2c_dev = {
         .resource       = au1550_psc2_res,
 };
 
+static struct mtd_partition pb1550_nand_parts[] = {
+        [0] = {
+                .name   = "NAND FS 0",
+                .offset = 0,
+                .size   = 8 * 1024 * 1024,
+        },
+        [1] = {
+                .name   = "NAND FS 1",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct au1550nd_platdata pb1550_nand_pd = {
+        .parts          = pb1550_nand_parts,
+        .num_parts      = ARRAY_SIZE(pb1550_nand_parts),
+        .devwidth       = 0,    /* x8 NAND default, needs fixing up */
+};
+
+static struct resource pb1550_nand_res[] = {
+        [0] = {
+                .start  = 0x20000000,
+                .end    = 0x20000fff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device pb1550_nand_dev = {
+        .name           = "au1550-nand",
+        .id             = -1,
+        .resource       = pb1550_nand_res,
+        .num_resources  = ARRAY_SIZE(pb1550_nand_res),
+        .dev            = {
+                .platform_data  = &pb1550_nand_pd,
+        },
+};
+
+static void __init pb1550_nand_setup(void)
+{
+        int boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) |
+                            ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
+
+        switch (boot_swapboot) {
+        case 0:
+        case 2:
+        case 8:
+        case 0xC:
+        case 0xD:
+                /* x16 NAND Flash */
+                pb1550_nand_pd.devwidth = 1;
+                /* fallthrough */
+        case 1:
+        case 9:
+        case 3:
+        case 0xE:
+        case 0xF:
+                /* x8 NAND, already set up */
+                platform_device_register(&pb1550_nand_dev);
+        }
+}
+
 static int __init pb1550_dev_init(void)
 {
         int swapped;
 
+        irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
+
+        /* enable both PCMCIA card irqs in the shared line */
+        alchemy_gpio2_enable_int(201);
+        alchemy_gpio2_enable_int(202);
+
         /* Pb1550, like all others, also has statuschange irqs; however they're
         * wired up on one of the Au1550's shared GPIO201_205 line, which also
         * services the PCMCIA card interrupts.  So we ignore statuschange and
@@ -130,6 +230,10 @@ static int __init pb1550_dev_init(void)
                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x008010000 - 1,
                 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
 
+        /* NAND setup */
+        gpio_direction_input(206);      /* GPIO206 high */
+        pb1550_nand_setup();
+
         swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
         db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
         platform_device_register(&pb1550_pci_host);
diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile
deleted file mode 100644
index 9661b6ec5dd3..000000000000
--- a/arch/mips/alchemy/devboards/pb1550/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-#  Copyright 2000, 2008 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc. <source@mvista.com>
-#
-# Makefile for the Alchemy Semiconductor Pb1550 board.
-#
-
-obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
deleted file mode 100644
index 0f62d1e3df24..000000000000
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      Alchemy Pb1550 board setup.
- *
- * Copyright 2000, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-pb1x00/pb1550.h>
-#include <asm/mach-db1x00/bcsr.h>
-#include <asm/mach-au1x00/gpio.h>
-
-#include <prom.h>
-
-const char *get_system_type(void)
-{
-        return "Alchemy Pb1550";
-}
-
-void __init board_setup(void)
-{
-        u32 pin_func;
-
-        bcsr_init(PB1550_BCSR_PHYS_ADDR,
-                  PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
-
-        alchemy_gpio2_enable();
-
-        /*
-         * Enable PSC1 SYNC for AC'97.  Normaly done in audio driver,
-         * but it is board specific code, so put it here.
-         */
-        pin_func = au_readl(SYS_PINFUNC);
-        au_sync();
-        pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
-        au_writel(pin_func, SYS_PINFUNC);
-
-        bcsr_write(BCSR_PCMCIA, 0);     /* turn off PCMCIA power */
-
-        printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
-}
-
-static int __init pb1550_init_irq(void)
-{
-        irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
-
-        /* enable both PCMCIA card irqs in the shared line */
-        alchemy_gpio2_enable_int(201);
-        alchemy_gpio2_enable_int(202);
-
-        return 0;
-}
-arch_initcall(pb1550_init_irq);
diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c
index 49a4b3244d8e..621f70afb63a 100644
--- a/arch/mips/alchemy/devboards/platform.c
+++ b/arch/mips/alchemy/devboards/platform.c
@@ -13,6 +13,13 @@
 #include <asm/reboot.h>
 #include <asm/mach-db1x00/bcsr.h>
 
+
+static struct platform_device db1x00_rtc_dev = {
+        .name   = "rtc-au1xxx",
+        .id     = -1,
+};
+
+
 static void db1x_power_off(void)
 {
         bcsr_write(BCSR_RESETS, 0);
@@ -25,7 +32,7 @@ static void db1x_reset(char *c)
         bcsr_write(BCSR_SYSTEM, 0);
 }
 
-static int __init db1x_poweroff_setup(void)
+static int __init db1x_late_setup(void)
 {
         if (!pm_power_off)
                 pm_power_off = db1x_power_off;
@@ -34,9 +41,11 @@ static int __init db1x_poweroff_setup(void)
         if (!_machine_restart)
                 _machine_restart = db1x_reset;
 
+        platform_device_register(&db1x00_rtc_dev);
+
         return 0;
 }
-late_initcall(db1x_poweroff_setup);
+device_initcall(db1x_late_setup);
 
 /* register a pcmcia socket */
 int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start,
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
index e5306b56da6d..93a22107cc41 100644
--- a/arch/mips/alchemy/devboards/prom.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -33,10 +33,9 @@
 #include <asm/mach-au1x00/au1000.h>
 #include <prom.h>
 
-#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \
-    defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \
-    defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \
-    defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
+#if defined(CONFIG_MIPS_DB1000) || \
+    defined(CONFIG_MIPS_PB1100) || \
+    defined(CONFIG_MIPS_PB1500)
 #define ALCHEMY_BOARD_DEFAULT_MEMSIZE   0x04000000
 
 #else   /* Au1550/Au1200-based develboards */
@@ -62,5 +61,9 @@ void __init prom_init(void)
 
 void prom_putchar(unsigned char c)
 {
+#ifdef CONFIG_MIPS_DB1300
+        alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
+#else
         alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+#endif
 }
diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile
deleted file mode 100644
index cb73fe256dce..000000000000
--- a/arch/mips/alchemy/gpr/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-#  Copyright 2003 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc. <source@mvista.com>
-#
-# Makefile for Trapeze ITS GPR board.
-#
-
-obj-y += board_setup.o init.o platform.o
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
deleted file mode 100644
index dea45c78fdcd..000000000000
--- a/arch/mips/alchemy/gpr/board_setup.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
- *
- * Copyright 2000-2003, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/pm.h>
-
-#include <asm/reboot.h>
-#include <asm/mach-au1x00/au1000.h>
-
-#include <prom.h>
-
-static void gpr_reset(char *c)
-{
-        /* switch System-LED to orange (red# and green# on) */
-        alchemy_gpio_direction_output(4, 0);
-        alchemy_gpio_direction_output(5, 0);
-
-        /* trigger watchdog to reset board in 200ms */
-        printk(KERN_EMERG "Triggering watchdog soft reset...\n");
-        raw_local_irq_disable();
-        alchemy_gpio_direction_output(1, 0);
-        udelay(1);
-        alchemy_gpio_set_value(1, 1);
-        while (1)
-                cpu_wait();
-}
-
-static void gpr_power_off(void)
-{
-        while (1)
-                cpu_wait();
-}
-
-void __init board_setup(void)
-{
-        printk(KERN_INFO "Trapeze ITS GPR board\n");
-
-        pm_power_off = gpr_power_off;
-        _machine_halt = gpr_power_off;
-        _machine_restart = gpr_reset;
-
-        /* Enable UART1/3 */
-        alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
-        alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
-
-        /* Take away Reset of UMTS-card */
-        alchemy_gpio_direction_output(215, 1);
-}
diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c
deleted file mode 100644
index 229aafae680c..000000000000
--- a/arch/mips/alchemy/gpr/init.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
- *
- * Copyright 2003, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-
-#include <asm/bootinfo.h>
-#include <asm/mach-au1x00/au1000.h>
-
-#include <prom.h>
-
-const char *get_system_type(void)
-{
-        return "GPR";
-}
-
-void __init prom_init(void)
-{
-        unsigned char *memsize_str;
-        unsigned long memsize;
-
-        prom_argc = fw_arg0;
-        prom_argv = (char **)fw_arg1;
-        prom_envp = (char **)fw_arg2;
-
-        prom_init_cmdline();
-
-        memsize_str = prom_getenv("memsize");
-        if (!memsize_str)
-                memsize = 0x04000000;
-        else
-                strict_strtoul(memsize_str, 0, &memsize);
-        add_memory_region(0, memsize, BOOT_MEM_RAM);
-}
-
-void prom_putchar(unsigned char c)
-{
-        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
-}
diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
deleted file mode 100644
index 81b540ceaf88..000000000000
--- a/arch/mips/alchemy/mtx-1/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-#  Copyright 2003 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc. <source@mvista.com>
-#       Bruno Randolf <bruno.randolf@4g-systems.biz>
-#
-# Makefile for 4G Systems MTX-1 board.
-#
-
-obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
deleted file mode 100644
index 851a5ab4c8f2..000000000000
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      4G Systems MTX-1 board setup.
- *
- * Copyright 2003, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *         Bruno Randolf <bruno.randolf@4g-systems.biz>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/pm.h>
-
-#include <asm/reboot.h>
-#include <asm/mach-au1x00/au1000.h>
-
-#include <prom.h>
-
-static void mtx1_reset(char *c)
-{
-        /* Jump to the reset vector */
-        __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
-}
-
-static void mtx1_power_off(void)
-{
-        while (1)
-                asm volatile (
-                "       .set    mips32                                  \n"
-                "       wait                                            \n"
-                "       .set    mips0                                   \n");
-}
-
-void __init board_setup(void)
-{
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-        /* Enable USB power switch */
-        alchemy_gpio_direction_output(204, 0);
-#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
-
-        /* Initialize sys_pinfunc */
-        au_writel(SYS_PF_NI2, SYS_PINFUNC);
-
-        /* Initialize GPIO */
-        au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
-        alchemy_gpio_direction_output(0, 0);    /* Disable M66EN (PCI 66MHz) */
-        alchemy_gpio_direction_output(3, 1);    /* Disable PCI CLKRUN# */
-        alchemy_gpio_direction_output(1, 1);    /* Enable EXT_IO3 */
-        alchemy_gpio_direction_output(5, 0);    /* Disable eth PHY TX_ER */
-
-        /* Enable LED and set it to green */
-        alchemy_gpio_direction_output(211, 1);  /* green on */
-        alchemy_gpio_direction_output(212, 0);  /* red off */
-
-        pm_power_off = mtx1_power_off;
-        _machine_halt = mtx1_power_off;
-        _machine_restart = mtx1_reset;
-
-        printk(KERN_INFO "4G Systems MTX-1 Board\n");
-}
-
-static int __init mtx1_init_irq(void)
-{
-        irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
-        irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
-
-        return 0;
-}
-arch_initcall(mtx1_init_irq);
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
deleted file mode 100644
index 2e81cc7f3422..000000000000
--- a/arch/mips/alchemy/mtx-1/init.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      4G Systems MTX-1 board setup
- *
- * Copyright 2003, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *         Bruno Randolf <bruno.randolf@4g-systems.biz>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/bootinfo.h>
-#include <asm/mach-au1x00/au1000.h>
-
-#include <prom.h>
-
-const char *get_system_type(void)
-{
-        return "MTX-1";
-}
-
-void __init prom_init(void)
-{
-        unsigned char *memsize_str;
-        unsigned long memsize;
-
-        prom_argc = fw_arg0;
-        prom_argv = (char **)fw_arg1;
-        prom_envp = (char **)fw_arg2;
-
-        prom_init_cmdline();
-
-        memsize_str = prom_getenv("memsize");
-        if (!memsize_str)
-                memsize = 0x04000000;
-        else
-                strict_strtoul(memsize_str, 0, &memsize);
-        add_memory_region(0, memsize, BOOT_MEM_RAM);
-}
-
-void prom_putchar(unsigned char c)
-{
-        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
-}
diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
deleted file mode 100644
index 91defcf4f335..000000000000
--- a/arch/mips/alchemy/xxs1500/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-#  Copyright 2003 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc. <source@mvista.com>
-#
-# Makefile for MyCable XXS1500 board.
-#
-
-obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
deleted file mode 100644
index 3fa83f72e014..000000000000
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2000-2003, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/pm.h>
-
-#include <asm/reboot.h>
-#include <asm/mach-au1x00/au1000.h>
-
-#include <prom.h>
-
-static void xxs1500_reset(char *c)
-{
-        /* Jump to the reset vector */
-        __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
-}
-
-static void xxs1500_power_off(void)
-{
-        while (1)
-                asm volatile (
-                "       .set    mips32                                  \n"
-                "       wait                                            \n"
-                "       .set    mips0                                   \n");
-}
-
-void __init board_setup(void)
-{
-        u32 pin_func;
-
-        pm_power_off = xxs1500_power_off;
-        _machine_halt = xxs1500_power_off;
-        _machine_restart = xxs1500_reset;
-
-        alchemy_gpio1_input_enable();
-        alchemy_gpio2_enable();
-
-        /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
-        pin_func  = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
-        pin_func |= SYS_PF_UR3;
-        au_writel(pin_func, SYS_PINFUNC);
-
-        /* Enable UART */
-        alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
-        /* Enable DTR (MCR bit 0) = USB power up */
-        __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
-        wmb();
-}
-
-static int __init xxs1500_init_irq(void)
-{
-        irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
-        irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
-
-        irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
-        irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
-        irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
-
-        return 0;
-}
-arch_initcall(xxs1500_init_irq);
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
deleted file mode 100644
index 0ee02cfa989d..000000000000
--- a/arch/mips/alchemy/xxs1500/init.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      XXS1500 board setup
- *
- * Copyright 2003, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-
-#include <asm/bootinfo.h>
-#include <asm/mach-au1x00/au1000.h>
-
-#include <prom.h>
-
-const char *get_system_type(void)
-{
-        return "XXS1500";
-}
-
-void __init prom_init(void)
-{
-        unsigned char *memsize_str;
-        unsigned long memsize;
-
-        prom_argc = fw_arg0;
-        prom_argv = (char **)fw_arg1;
-        prom_envp = (char **)fw_arg2;
-
-        prom_init_cmdline();
-
-        memsize_str = prom_getenv("memsize");
-        if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
-                memsize = 0x04000000;
-
-        add_memory_region(0, memsize, BOOT_MEM_RAM);
-}
-
-void prom_putchar(unsigned char c)
-{
-        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
-}
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
deleted file mode 100644
index 06a3a459b8aa..000000000000
--- a/arch/mips/alchemy/xxs1500/platform.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * XXS1500 board platform device registration
- *
- * Copyright (C) 2009 Manuel Lauss
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-au1x00/au1000.h>
-
-static struct resource xxs1500_pcmcia_res[] = {
-        {
-                .name   = "pcmcia-io",
-                .flags  = IORESOURCE_MEM,
-                .start  = AU1000_PCMCIA_IO_PHYS_ADDR,
-                .end    = AU1000_PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
-        },
-        {
-                .name   = "pcmcia-attr",
-                .flags  = IORESOURCE_MEM,
-                .start  = AU1000_PCMCIA_ATTR_PHYS_ADDR,
-                .end    = AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
-        },
-        {
-                .name   = "pcmcia-mem",
-                .flags  = IORESOURCE_MEM,
-                .start  = AU1000_PCMCIA_MEM_PHYS_ADDR,
-                .end    = AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
-        },
-};
-
-static struct platform_device xxs1500_pcmcia_dev = {
-        .name           = "xxs1500_pcmcia",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(xxs1500_pcmcia_res),
-        .resource       = xxs1500_pcmcia_res,
-};
-
-static struct platform_device *xxs1500_devs[] __initdata = {
-        &xxs1500_pcmcia_dev,
-};
-
-static int __init xxs1500_dev_init(void)
-{
-        return platform_add_devices(xxs1500_devs,
-                                    ARRAY_SIZE(xxs1500_devs));
-}
-device_initcall(xxs1500_dev_init);
diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c
index bb571bcdb8f2..d8dbd8f0c1d2 100644
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -217,7 +217,7 @@ struct titan_gpio_cfg {
         u32 func;
 };
 
-static struct titan_gpio_cfg titan_gpio_table[] = {
+static const struct titan_gpio_cfg titan_gpio_table[] = {
         /* reg, start bit, mux value */
         {4, 24, 1},
         {4, 26, 1},
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 33ffecf6a6d6..1a24d317e7a3 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -462,6 +462,40 @@ static struct gpio_led fb_fon_leds[] = {
         },
 };
 
+static struct gpio_led gt701_leds[] = {
+        {
+                .name                   = "inet:green",
+                .gpio                   = 13,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "usb",
+                .gpio                   = 12,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "inet:red",
+                .gpio                   = 9,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "power:red",
+                .gpio                   = 7,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "power:green",
+                .gpio                   = 8,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
+        },
+        {
+                .name                   = "ethernet",
+                .gpio                   = 10,
+                .active_low             = 1,
+        },
+};
+
 static struct gpio_led_platform_data ar7_led_data;
 
 static struct platform_device ar7_gpio_leds = {
@@ -503,6 +537,9 @@ static void __init detect_leds(void)
         } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
                 ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
                 ar7_led_data.leds = titan_leds;
+        } else if (strstr(prid, "GT701")) {
+                ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds);
+                ar7_led_data.leds = gt701_leds;
         }
 }
 
@@ -536,7 +573,7 @@ static int __init ar7_register_uarts(void)
 
         bus_clk = clk_get(NULL, "bus");
         if (IS_ERR(bus_clk))
-                panic("unable to get bus clk\n");
+                panic("unable to get bus clk");
 
         uart_port.type          = PORT_AR7;
         uart_port.uartclk       = clk_get_rate(bus_clk) / 2;
diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c
index 8088c6fdb83e..a23adc49d50f 100644
--- a/arch/mips/ar7/prom.c
+++ b/arch/mips/ar7/prom.c
@@ -69,7 +69,7 @@ struct psbl_rec {
         u32     ffs_size;
 };
 
-static __initdata char psp_env_version[] = "TIENV0.8";
+static const char psp_env_version[] __initconst = "TIENV0.8";
 
 struct psp_env_chunk {
         u8      num;
@@ -84,7 +84,7 @@ struct psp_var_map_entry {
         char    *value;
 };
 
-static struct psp_var_map_entry psp_var_map[] = {
+static const struct psp_var_map_entry psp_var_map[] = {
         {  1,   "cpufrequency" },
         {  2,   "memsize" },
         {  3,   "flashsize" },
diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c
index f20b53e597c4..9a357fffcfbe 100644
--- a/arch/mips/ar7/setup.c
+++ b/arch/mips/ar7/setup.c
@@ -96,7 +96,7 @@ void __init plat_mem_setup(void)
 
         io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
         if (!io_base)
-                panic("Can't remap IO base!\n");
+                panic("Can't remap IO base!");
         set_io_port_base(io_base);
 
         prom_meminit();
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index 47707410582c..e0fae8f4442b 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -2,13 +2,26 @@ if ATH79
 
 menu "Atheros AR71XX/AR724X/AR913X machine selection"
 
+config ATH79_MACH_AP121
+        bool "Atheros AP121 reference board"
+        select SOC_AR933X
+        select ATH79_DEV_GPIO_BUTTONS
+        select ATH79_DEV_LEDS_GPIO
+        select ATH79_DEV_SPI
+        select ATH79_DEV_USB
+        select ATH79_DEV_WMAC
+        help
+          Say 'Y' here if you want your kernel to support the
+          Atheros AP121 reference board.
+
 config ATH79_MACH_AP81
         bool "Atheros AP81 reference board"
         select SOC_AR913X
-        select ATH79_DEV_AR913X_WMAC
         select ATH79_DEV_GPIO_BUTTONS
         select ATH79_DEV_LEDS_GPIO
         select ATH79_DEV_SPI
+        select ATH79_DEV_USB
+        select ATH79_DEV_WMAC
         help
           Say 'Y' here if you want your kernel to support the
           Atheros AP81 reference board.
@@ -19,10 +32,21 @@ config ATH79_MACH_PB44
         select ATH79_DEV_GPIO_BUTTONS
         select ATH79_DEV_LEDS_GPIO
         select ATH79_DEV_SPI
+        select ATH79_DEV_USB
         help
           Say 'Y' here if you want your kernel to support the
           Atheros PB44 reference board.
 
+config ATH79_MACH_UBNT_XM
+        bool "Ubiquiti Networks XM (rev 1.0) board"
+        select SOC_AR724X
+        select ATH79_DEV_GPIO_BUTTONS
+        select ATH79_DEV_LEDS_GPIO
+        select ATH79_DEV_SPI
+        help
+          Say 'Y' here if you want your kernel to support the
+          Ubiquiti Networks XM (rev 1.0) board.
+
 endmenu
 
 config SOC_AR71XX
@@ -33,14 +57,15 @@ config SOC_AR71XX
 config SOC_AR724X
         select USB_ARCH_HAS_EHCI
         select USB_ARCH_HAS_OHCI
+        select HW_HAS_PCI
         def_bool n
 
 config SOC_AR913X
         select USB_ARCH_HAS_EHCI
         def_bool n
 
-config ATH79_DEV_AR913X_WMAC
-        depends on SOC_AR913X
+config SOC_AR933X
+        select USB_ARCH_HAS_EHCI
         def_bool n
 
 config ATH79_DEV_GPIO_BUTTONS
@@ -52,4 +77,11 @@ config ATH79_DEV_LEDS_GPIO
 config ATH79_DEV_SPI
         def_bool n
 
+config ATH79_DEV_USB
+        def_bool n
+
+config ATH79_DEV_WMAC
+        depends on (SOC_AR913X || SOC_AR933X)
+        def_bool n
+
 endif
diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile
index c33d4653007c..3b911e09dbec 100644
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -16,13 +16,16 @@ obj-$(CONFIG_EARLY_PRINTK)		+= early_printk.o
 # Devices
 #
 obj-y                                   += dev-common.o
-obj-$(CONFIG_ATH79_DEV_AR913X_WMAC)     += dev-ar913x-wmac.o
 obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS)    += dev-gpio-buttons.o
 obj-$(CONFIG_ATH79_DEV_LEDS_GPIO)       += dev-leds-gpio.o
 obj-$(CONFIG_ATH79_DEV_SPI)             += dev-spi.o
+obj-$(CONFIG_ATH79_DEV_USB)             += dev-usb.o
+obj-$(CONFIG_ATH79_DEV_WMAC)            += dev-wmac.o
 
 #
 # Machines
 #
+obj-$(CONFIG_ATH79_MACH_AP121)          += mach-ap121.o
 obj-$(CONFIG_ATH79_MACH_AP81)           += mach-ap81.o
 obj-$(CONFIG_ATH79_MACH_PB44)           += mach-pb44.o
+obj-$(CONFIG_ATH79_MACH_UBNT_XM)        += mach-ubnt-xm.o
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 680bde99a26c..54d0eb4db987 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -110,6 +110,59 @@ static void __init ar913x_clocks_init(void)
         ath79_uart_clk.rate = ath79_ahb_clk.rate;
 }
 
+static void __init ar933x_clocks_init(void)
+{
+        u32 clock_ctrl;
+        u32 cpu_config;
+        u32 freq;
+        u32 t;
+
+        t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+        if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+                ath79_ref_clk.rate = (40 * 1000 * 1000);
+        else
+                ath79_ref_clk.rate = (25 * 1000 * 1000);
+
+        clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
+        if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
+                ath79_cpu_clk.rate = ath79_ref_clk.rate;
+                ath79_ahb_clk.rate = ath79_ref_clk.rate;
+                ath79_ddr_clk.rate = ath79_ref_clk.rate;
+        } else {
+                cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
+
+                t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+                    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+                freq = ath79_ref_clk.rate / t;
+
+                t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
+                    AR933X_PLL_CPU_CONFIG_NINT_MASK;
+                freq *= t;
+
+                t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+                    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+                if (t == 0)
+                        t = 1;
+
+                freq >>= t;
+
+                t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
+                     AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
+                ath79_cpu_clk.rate = freq / t;
+
+                t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
+                      AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
+                ath79_ddr_clk.rate = freq / t;
+
+                t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
+                     AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
+                ath79_ahb_clk.rate = freq / t;
+        }
+
+        ath79_wdt_clk.rate = ath79_ref_clk.rate;
+        ath79_uart_clk.rate = ath79_ref_clk.rate;
+}
+
 void __init ath79_clocks_init(void)
 {
         if (soc_is_ar71xx())
@@ -118,6 +171,8 @@ void __init ath79_clocks_init(void)
                 ar724x_clocks_init();
         else if (soc_is_ar913x())
                 ar913x_clocks_init();
+        else if (soc_is_ar933x())
+                ar933x_clocks_init();
         else
                 BUG();
 
diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
index 58f60e722a03..f0fda982b965 100644
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -30,6 +30,7 @@ u32 ath79_ddr_freq;
 EXPORT_SYMBOL_GPL(ath79_ddr_freq);
 
 enum ath79_soc_type ath79_soc;
+unsigned int ath79_soc_rev;
 
 void __iomem *ath79_pll_base;
 void __iomem *ath79_reset_base;
@@ -64,6 +65,8 @@ void ath79_device_reset_set(u32 mask)
                 reg = AR724X_RESET_REG_RESET_MODULE;
         else if (soc_is_ar913x())
                 reg = AR913X_RESET_REG_RESET_MODULE;
+        else if (soc_is_ar933x())
+                reg = AR933X_RESET_REG_RESET_MODULE;
         else
                 BUG();
 
@@ -86,6 +89,8 @@ void ath79_device_reset_clear(u32 mask)
                 reg = AR724X_RESET_REG_RESET_MODULE;
         else if (soc_is_ar913x())
                 reg = AR913X_RESET_REG_RESET_MODULE;
+        else if (soc_is_ar933x())
+                reg = AR933X_RESET_REG_RESET_MODULE;
         else
                 BUG();
 
diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c
deleted file mode 100644
index 48f425a5ba28..000000000000
--- a/arch/mips/ath79/dev-ar913x-wmac.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *  Atheros AR913X SoC built-in WMAC device support
- *
- *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/ath9k_platform.h>
-
-#include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include "dev-ar913x-wmac.h"
-
-static struct ath9k_platform_data ar913x_wmac_data;
-
-static struct resource ar913x_wmac_resources[] = {
-        {
-                .start  = AR913X_WMAC_BASE,
-                .end    = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = ATH79_CPU_IRQ_IP2,
-                .end    = ATH79_CPU_IRQ_IP2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ar913x_wmac_device = {
-        .name           = "ath9k",
-        .id             = -1,
-        .resource       = ar913x_wmac_resources,
-        .num_resources  = ARRAY_SIZE(ar913x_wmac_resources),
-        .dev = {
-                .platform_data = &ar913x_wmac_data,
-        },
-};
-
-void __init ath79_register_ar913x_wmac(u8 *cal_data)
-{
-        if (cal_data)
-                memcpy(ar913x_wmac_data.eeprom_data, cal_data,
-                       sizeof(ar913x_wmac_data.eeprom_data));
-
-        /* reset the WMAC */
-        ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
-        mdelay(10);
-
-        ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
-        mdelay(10);
-
-        platform_device_register(&ar913x_wmac_device);
-}
diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
index 3b82e325bebf..f4956f809072 100644
--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
@@ -20,6 +20,7 @@
 
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ar933x_uart_platform.h>
 #include "common.h"
 #include "dev-common.h"
 
@@ -54,6 +55,30 @@ static struct platform_device ath79_uart_device = {
         },
 };
 
+static struct resource ar933x_uart_resources[] = {
+        {
+                .start  = AR933X_UART_BASE,
+                .end    = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = ATH79_MISC_IRQ_UART,
+                .end    = ATH79_MISC_IRQ_UART,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct ar933x_uart_platform_data ar933x_uart_data;
+static struct platform_device ar933x_uart_device = {
+        .name           = "ar933x-uart",
+        .id             = -1,
+        .resource       = ar933x_uart_resources,
+        .num_resources  = ARRAY_SIZE(ar933x_uart_resources),
+        .dev = {
+                .platform_data  = &ar933x_uart_data,
+        },
+};
+
 void __init ath79_register_uart(void)
 {
         struct clk *clk;
@@ -62,8 +87,17 @@ void __init ath79_register_uart(void)
         if (IS_ERR(clk))
                 panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
 
-        ath79_uart_data[0].uartclk = clk_get_rate(clk);
-        platform_device_register(&ath79_uart_device);
+        if (soc_is_ar71xx() ||
+            soc_is_ar724x() ||
+            soc_is_ar913x()) {
+                ath79_uart_data[0].uartclk = clk_get_rate(clk);
+                platform_device_register(&ath79_uart_device);
+        } else if (soc_is_ar933x()) {
+                ar933x_uart_data.uartclk = clk_get_rate(clk);
+                platform_device_register(&ar933x_uart_device);
+        } else {
+                BUG();
+        }
 }
 
 static struct platform_device ath79_wdt_device = {
diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c
new file mode 100644
index 000000000000..002d6d2afe04
--- /dev/null
+++ b/arch/mips/ath79/dev-usb.c
@@ -0,0 +1,197 @@
+/*
+ *  Atheros AR7XXX/AR9XXX USB Host Controller device
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include "common.h"
+#include "dev-usb.h"
+
+static struct resource ath79_ohci_resources[] = {
+        [0] = {
+                /* .start and .end fields are filled dynamically */
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = ATH79_MISC_IRQ_OHCI,
+                .end    = ATH79_MISC_IRQ_OHCI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
+static struct platform_device ath79_ohci_device = {
+        .name           = "ath79-ohci",
+        .id             = -1,
+        .resource       = ath79_ohci_resources,
+        .num_resources  = ARRAY_SIZE(ath79_ohci_resources),
+        .dev = {
+                .dma_mask               = &ath79_ohci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource ath79_ehci_resources[] = {
+        [0] = {
+                /* .start and .end fields are filled dynamically */
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = ATH79_CPU_IRQ_USB,
+                .end    = ATH79_CPU_IRQ_USB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
+static struct platform_device ath79_ehci_device = {
+        .name           = "ath79-ehci",
+        .id             = -1,
+        .resource       = ath79_ehci_resources,
+        .num_resources  = ARRAY_SIZE(ath79_ehci_resources),
+        .dev = {
+                .dma_mask               = &ath79_ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+#define AR71XX_USB_RESET_MASK   (AR71XX_RESET_USB_HOST | \
+                                 AR71XX_RESET_USB_PHY | \
+                                 AR71XX_RESET_USB_OHCI_DLL)
+
+static void __init ath79_usb_setup(void)
+{
+        void __iomem *usb_ctrl_base;
+
+        ath79_device_reset_set(AR71XX_USB_RESET_MASK);
+        mdelay(1000);
+        ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
+
+        usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
+
+        /* Turning on the Buff and Desc swap bits */
+        __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
+
+        /* WAR for HW bug. Here it adjusts the duration between two SOFS */
+        __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
+
+        iounmap(usb_ctrl_base);
+
+        mdelay(900);
+
+        ath79_ohci_resources[0].start = AR71XX_OHCI_BASE;
+        ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1;
+        platform_device_register(&ath79_ohci_device);
+
+        ath79_ehci_resources[0].start = AR71XX_EHCI_BASE;
+        ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1;
+        ath79_ehci_device.name = "ar71xx-ehci";
+        platform_device_register(&ath79_ehci_device);
+}
+
+static void __init ar7240_usb_setup(void)
+{
+        void __iomem *usb_ctrl_base;
+
+        ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
+        ath79_device_reset_set(AR7240_RESET_USB_HOST);
+
+        mdelay(1000);
+
+        ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
+        ath79_device_reset_clear(AR7240_RESET_USB_HOST);
+
+        usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
+
+        /* WAR for HW bug. Here it adjusts the duration between two SOFS */
+        __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
+
+        iounmap(usb_ctrl_base);
+
+        ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
+        ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
+        platform_device_register(&ath79_ohci_device);
+}
+
+static void __init ar724x_usb_setup(void)
+{
+        ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR724X_RESET_USB_HOST);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR724X_RESET_USB_PHY);
+        mdelay(10);
+
+        ath79_ehci_resources[0].start = AR724X_EHCI_BASE;
+        ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1;
+        ath79_ehci_device.name = "ar724x-ehci";
+        platform_device_register(&ath79_ehci_device);
+}
+
+static void __init ar913x_usb_setup(void)
+{
+        ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR913X_RESET_USB_HOST);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR913X_RESET_USB_PHY);
+        mdelay(10);
+
+        ath79_ehci_resources[0].start = AR913X_EHCI_BASE;
+        ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1;
+        ath79_ehci_device.name = "ar913x-ehci";
+        platform_device_register(&ath79_ehci_device);
+}
+
+static void __init ar933x_usb_setup(void)
+{
+        ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR933X_RESET_USB_HOST);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR933X_RESET_USB_PHY);
+        mdelay(10);
+
+        ath79_ehci_resources[0].start = AR933X_EHCI_BASE;
+        ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1;
+        ath79_ehci_device.name = "ar933x-ehci";
+        platform_device_register(&ath79_ehci_device);
+}
+
+void __init ath79_register_usb(void)
+{
+        if (soc_is_ar71xx())
+                ath79_usb_setup();
+        else if (soc_is_ar7240())
+                ar7240_usb_setup();
+        else if (soc_is_ar7241() || soc_is_ar7242())
+                ar724x_usb_setup();
+        else if (soc_is_ar913x())
+                ar913x_usb_setup();
+        else if (soc_is_ar933x())
+                ar933x_usb_setup();
+        else
+                BUG();
+}
diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-usb.h
index 579d562bbda8..4b86a69ca080 100644
--- a/arch/mips/ath79/dev-ar913x-wmac.h
+++ b/arch/mips/ath79/dev-usb.h
@@ -1,5 +1,5 @@
 /*
- *  Atheros AR913X SoC built-in WMAC device support
+ *  Atheros AR71XX/AR724X/AR913X USB Host Controller support
  *
  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
@@ -9,9 +9,9 @@
  *  by the Free Software Foundation.
  */
 
-#ifndef _ATH79_DEV_AR913X_WMAC_H
-#define _ATH79_DEV_AR913X_WMAC_H
+#ifndef _ATH79_DEV_USB_H
+#define _ATH79_DEV_USB_H
 
-void ath79_register_ar913x_wmac(u8 *cal_data);
+void ath79_register_usb(void);
 
-#endif /* _ATH79_DEV_AR913X_WMAC_H */
+#endif /* _ATH79_DEV_USB_H */
diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
new file mode 100644
index 000000000000..24f546985b69
--- /dev/null
+++ b/arch/mips/ath79/dev-wmac.c
@@ -0,0 +1,109 @@
+/*
+ *  Atheros AR913X/AR933X SoC built-in WMAC device support
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/ath9k_platform.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include "dev-wmac.h"
+
+static struct ath9k_platform_data ath79_wmac_data;
+
+static struct resource ath79_wmac_resources[] = {
+        {
+                /* .start and .end fields are filled dynamically */
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = ATH79_CPU_IRQ_IP2,
+                .end    = ATH79_CPU_IRQ_IP2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ath79_wmac_device = {
+        .name           = "ath9k",
+        .id             = -1,
+        .resource       = ath79_wmac_resources,
+        .num_resources  = ARRAY_SIZE(ath79_wmac_resources),
+        .dev = {
+                .platform_data = &ath79_wmac_data,
+        },
+};
+
+static void __init ar913x_wmac_setup(void)
+{
+        /* reset the WMAC */
+        ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
+        mdelay(10);
+
+        ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
+        ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
+}
+
+
+static int ar933x_wmac_reset(void)
+{
+        ath79_device_reset_clear(AR933X_RESET_WMAC);
+        ath79_device_reset_set(AR933X_RESET_WMAC);
+
+        return 0;
+}
+
+static int ar933x_r1_get_wmac_revision(void)
+{
+        return ath79_soc_rev;
+}
+
+static void __init ar933x_wmac_setup(void)
+{
+        u32 t;
+
+        ar933x_wmac_reset();
+
+        ath79_wmac_device.name = "ar933x_wmac";
+
+        ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
+        ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
+
+        t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+        if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+                ath79_wmac_data.is_clk_25mhz = false;
+        else
+                ath79_wmac_data.is_clk_25mhz = true;
+
+        if (ath79_soc_rev == 1)
+                ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
+
+        ath79_wmac_data.external_reset = ar933x_wmac_reset;
+}
+
+void __init ath79_register_wmac(u8 *cal_data)
+{
+        if (soc_is_ar913x())
+                ar913x_wmac_setup();
+        if (soc_is_ar933x())
+                ar933x_wmac_setup();
+        else
+                BUG();
+
+        if (cal_data)
+                memcpy(ath79_wmac_data.eeprom_data, cal_data,
+                       sizeof(ath79_wmac_data.eeprom_data));
+
+        platform_device_register(&ath79_wmac_device);
+}
diff --git a/arch/mips/ath79/dev-wmac.h b/arch/mips/ath79/dev-wmac.h
new file mode 100644
index 000000000000..c9cd8709f090
--- /dev/null
+++ b/arch/mips/ath79/dev-wmac.h
@@ -0,0 +1,17 @@
+/*
+ *  Atheros AR913X/AR933X SoC built-in WMAC device support
+ *
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _ATH79_DEV_WMAC_H
+#define _ATH79_DEV_WMAC_H
+
+void ath79_register_wmac(u8 *cal_data);
+
+#endif /* _ATH79_DEV_WMAC_H */
diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
index 7499b0e9df26..6a51ced7a293 100644
--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
@@ -1,7 +1,7 @@
 /*
- *  Atheros AR71XX/AR724X/AR913X SoC early printk support
+ *  Atheros AR7XXX/AR9XXX SoC early printk support
  *
- *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  This program is free software; you can redistribute it and/or modify it
@@ -10,27 +10,85 @@
  */
 
 #include <linux/io.h>
+#include <linux/errno.h>
 #include <linux/serial_reg.h>
 #include <asm/addrspace.h>
 
+#include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ar933x_uart.h>
 
-static inline void prom_wait_thre(void __iomem *base)
+static void (*_prom_putchar) (unsigned char);
+
+static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
 {
-        u32 lsr;
+        u32 t;
 
         do {
-                lsr = __raw_readl(base + UART_LSR * 4);
-                if (lsr & UART_LSR_THRE)
+                t = __raw_readl(reg);
+                if ((t & mask) == val)
                         break;
         } while (1);
 }
 
-void prom_putchar(unsigned char ch)
+static void prom_putchar_ar71xx(unsigned char ch)
 {
         void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
 
-        prom_wait_thre(base);
+        prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
         __raw_writel(ch, base + UART_TX * 4);
-        prom_wait_thre(base);
+        prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
+}
+
+static void prom_putchar_ar933x(unsigned char ch)
+{
+        void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
+
+        prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
+                          AR933X_UART_DATA_TX_CSR);
+        __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
+        prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
+                          AR933X_UART_DATA_TX_CSR);
+}
+
+static void prom_putchar_dummy(unsigned char ch)
+{
+        /* nothing to do */
+}
+
+static void prom_putchar_init(void)
+{
+        void __iomem *base;
+        u32 id;
+
+        base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
+        id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
+        id &= REV_ID_MAJOR_MASK;
+
+        switch (id) {
+        case REV_ID_MAJOR_AR71XX:
+        case REV_ID_MAJOR_AR7240:
+        case REV_ID_MAJOR_AR7241:
+        case REV_ID_MAJOR_AR7242:
+        case REV_ID_MAJOR_AR913X:
+                _prom_putchar = prom_putchar_ar71xx;
+                break;
+
+        case REV_ID_MAJOR_AR9330:
+        case REV_ID_MAJOR_AR9331:
+                _prom_putchar = prom_putchar_ar933x;
+                break;
+
+        default:
+                _prom_putchar = prom_putchar_dummy;
+                break;
+        }
+}
+
+void prom_putchar(unsigned char ch)
+{
+        if (!_prom_putchar)
+                prom_putchar_init();
+
+        _prom_putchar(ch);
 }
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c
index a0c426b82123..a2f8ca630ed6 100644
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -153,6 +153,8 @@ void __init ath79_gpio_init(void)
                 ath79_gpio_count = AR724X_GPIO_COUNT;
         else if (soc_is_ar913x())
                 ath79_gpio_count = AR913X_GPIO_COUNT;
+        else if (soc_is_ar933x())
+                ath79_gpio_count = AR933X_GPIO_COUNT;
         else
                 BUG();
 
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index ac610d5fe3ba..1b073de44680 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
         else if (pending & MISC_INT_TIMER)
                 generic_handle_irq(ATH79_MISC_IRQ_TIMER);
 
+        else if (pending & MISC_INT_TIMER2)
+                generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
+
+        else if (pending & MISC_INT_TIMER3)
+                generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
+
+        else if (pending & MISC_INT_TIMER4)
+                generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
+
         else if (pending & MISC_INT_OHCI)
                 generic_handle_irq(ATH79_MISC_IRQ_OHCI);
 
@@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
         else if (pending & MISC_INT_WDOG)
                 generic_handle_irq(ATH79_MISC_IRQ_WDOG);
 
+        else if (pending & MISC_INT_ETHSW)
+                generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
+
         else
                 spurious_interrupt();
 }
@@ -117,7 +129,7 @@ static void __init ath79_misc_irq_init(void)
 
         if (soc_is_ar71xx() || soc_is_ar913x())
                 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
-        else if (soc_is_ar724x())
+        else if (soc_is_ar724x() || soc_is_ar933x())
                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
         else
                 BUG();
@@ -174,6 +186,9 @@ void __init arch_init_irq(void)
         } else if (soc_is_ar913x()) {
                 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
                 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
+        } else if (soc_is_ar933x()) {
+                ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
+                ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
         } else
                 BUG();
 
diff --git a/arch/mips/ath79/mach-ap121.c b/arch/mips/ath79/mach-ap121.c
new file mode 100644
index 000000000000..4c20200d7c72
--- /dev/null
+++ b/arch/mips/ath79/mach-ap121.c
@@ -0,0 +1,92 @@
+/*
+ *  Atheros AP121 board support
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include "machtypes.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-spi.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+
+#define AP121_GPIO_LED_WLAN             0
+#define AP121_GPIO_LED_USB              1
+
+#define AP121_GPIO_BTN_JUMPSTART        11
+#define AP121_GPIO_BTN_RESET            12
+
+#define AP121_KEYS_POLL_INTERVAL        20      /* msecs */
+#define AP121_KEYS_DEBOUNCE_INTERVAL    (3 * AP121_KEYS_POLL_INTERVAL)
+
+#define AP121_CAL_DATA_ADDR     0x1fff1000
+
+static struct gpio_led ap121_leds_gpio[] __initdata = {
+        {
+                .name           = "ap121:green:usb",
+                .gpio           = AP121_GPIO_LED_USB,
+                .active_low     = 0,
+        },
+        {
+                .name           = "ap121:green:wlan",
+                .gpio           = AP121_GPIO_LED_WLAN,
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
+        {
+                .desc           = "jumpstart button",
+                .type           = EV_KEY,
+                .code           = KEY_WPS_BUTTON,
+                .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
+                .gpio           = AP121_GPIO_BTN_JUMPSTART,
+                .active_low     = 1,
+        },
+        {
+                .desc           = "reset button",
+                .type           = EV_KEY,
+                .code           = KEY_RESTART,
+                .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
+                .gpio           = AP121_GPIO_BTN_RESET,
+                .active_low     = 1,
+        }
+};
+
+static struct spi_board_info ap121_spi_info[] = {
+        {
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .max_speed_hz   = 25000000,
+                .modalias       = "mx25l1606e",
+        }
+};
+
+static struct ath79_spi_platform_data ap121_spi_data = {
+        .bus_num        = 0,
+        .num_chipselect = 1,
+};
+
+static void __init ap121_setup(void)
+{
+        u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
+
+        ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
+                                 ap121_leds_gpio);
+        ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(ap121_gpio_keys),
+                                        ap121_gpio_keys);
+
+        ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+                           ARRAY_SIZE(ap121_spi_info));
+        ath79_register_usb();
+        ath79_register_wmac(cal_data);
+}
+
+MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
+             ap121_setup);
diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c
index eee4c121deb4..abe19836331c 100644
--- a/arch/mips/ath79/mach-ap81.c
+++ b/arch/mips/ath79/mach-ap81.c
@@ -10,10 +10,11 @@
  */
 
 #include "machtypes.h"
-#include "dev-ar913x-wmac.h"
+#include "dev-wmac.h"
 #include "dev-gpio-buttons.h"
 #include "dev-leds-gpio.h"
 #include "dev-spi.h"
+#include "dev-usb.h"
 
 #define AP81_GPIO_LED_STATUS    1
 #define AP81_GPIO_LED_AOSS      3
@@ -91,7 +92,8 @@ static void __init ap81_setup(void)
                                         ap81_gpio_keys);
         ath79_register_spi(&ap81_spi_data, ap81_spi_info,
                            ARRAY_SIZE(ap81_spi_info));
-        ath79_register_ar913x_wmac(cal_data);
+        ath79_register_wmac(cal_data);
+        ath79_register_usb();
 }
 
 MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c
index ec7b7a135d53..fe9701a32291 100644
--- a/arch/mips/ath79/mach-pb44.c
+++ b/arch/mips/ath79/mach-pb44.c
@@ -18,6 +18,7 @@
 #include "dev-gpio-buttons.h"
 #include "dev-leds-gpio.h"
 #include "dev-spi.h"
+#include "dev-usb.h"
 
 #define PB44_GPIO_I2C_SCL       0
 #define PB44_GPIO_I2C_SDA       1
@@ -112,6 +113,7 @@ static void __init pb44_init(void)
                                         pb44_gpio_keys);
         ath79_register_spi(&pb44_spi_data, pb44_spi_info,
                            ARRAY_SIZE(pb44_spi_info));
+        ath79_register_usb();
 }
 
 MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c
new file mode 100644
index 000000000000..3c311a539347
--- /dev/null
+++ b/arch/mips/ath79/mach-ubnt-xm.c
@@ -0,0 +1,119 @@
+/*
+ *  Ubiquiti Networks XM (rev 1.0) board support
+ *
+ *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+ *
+ *  Derived from: mach-pb44.c
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/pci.h>
+
+#ifdef CONFIG_PCI
+#include <linux/ath9k_platform.h>
+#include <asm/mach-ath79/pci-ath724x.h>
+#endif /* CONFIG_PCI */
+
+#include "machtypes.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-spi.h"
+
+#define UBNT_XM_GPIO_LED_L1             0
+#define UBNT_XM_GPIO_LED_L2             1
+#define UBNT_XM_GPIO_LED_L3             11
+#define UBNT_XM_GPIO_LED_L4             7
+
+#define UBNT_XM_GPIO_BTN_RESET          12
+
+#define UBNT_XM_KEYS_POLL_INTERVAL      20
+#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL  (3 * UBNT_XM_KEYS_POLL_INTERVAL)
+
+#define UBNT_XM_PCI_IRQ                 48
+#define UBNT_XM_EEPROM_ADDR             (u8 *) KSEG1ADDR(0x1fff1000)
+
+static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+        {
+                .name           = "ubnt-xm:red:link1",
+                .gpio           = UBNT_XM_GPIO_LED_L1,
+                .active_low     = 0,
+        }, {
+                .name           = "ubnt-xm:orange:link2",
+                .gpio           = UBNT_XM_GPIO_LED_L2,
+                .active_low     = 0,
+        }, {
+                .name           = "ubnt-xm:green:link3",
+                .gpio           = UBNT_XM_GPIO_LED_L3,
+                .active_low     = 0,
+        }, {
+                .name           = "ubnt-xm:green:link4",
+                .gpio           = UBNT_XM_GPIO_LED_L4,
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = {
+        {
+                .desc                   = "reset",
+                .type                   = EV_KEY,
+                .code                   = KEY_RESTART,
+                .debounce_interval      = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
+                .gpio                   = UBNT_XM_GPIO_BTN_RESET,
+                .active_low             = 1,
+        }
+};
+
+static struct spi_board_info ubnt_xm_spi_info[] = {
+        {
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .max_speed_hz   = 25000000,
+                .modalias       = "mx25l6405d",
+        }
+};
+
+static struct ath79_spi_platform_data ubnt_xm_spi_data = {
+        .bus_num                = 0,
+        .num_chipselect         = 1,
+};
+
+#ifdef CONFIG_PCI
+static struct ath9k_platform_data ubnt_xm_eeprom_data;
+
+static struct ath724x_pci_data ubnt_xm_pci_data[] = {
+        {
+                .irq    = UBNT_XM_PCI_IRQ,
+                .pdata  = &ubnt_xm_eeprom_data,
+        },
+};
+#endif /* CONFIG_PCI */
+
+static void __init ubnt_xm_init(void)
+{
+        ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+                                 ubnt_xm_leds_gpio);
+
+        ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
+                                        ARRAY_SIZE(ubnt_xm_gpio_keys),
+                                        ubnt_xm_gpio_keys);
+
+        ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
+                           ARRAY_SIZE(ubnt_xm_spi_info));
+
+#ifdef CONFIG_PCI
+        memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+               sizeof(ubnt_xm_eeprom_data.eeprom_data));
+
+        ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
+#endif /* CONFIG_PCI */
+
+}
+
+MIPS_MACHINE(ATH79_MACH_UBNT_XM,
+             "UBNT-XM",
+             "Ubiquiti Networks XM (rev 1.0) board",
+             ubnt_xm_init);
diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h
index 3940fe470b2d..9a1f3826626e 100644
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -16,8 +16,10 @@
 
 enum ath79_mach_type {
         ATH79_MACH_GENERIC = 0,
+        ATH79_MACH_AP121,               /* Atheros AP121 reference board */
         ATH79_MACH_AP81,                /* Atheros AP81 reference board */
         ATH79_MACH_PB44,                /* Atheros PB44 reference board */
+        ATH79_MACH_UBNT_XM,             /* Ubiquiti Networks XM board rev 1.0 */
 };
 
 #endif /* _ATH79_MACHTYPE_H */
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 159b42f106b0..80a7d4023d7f 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -101,19 +101,31 @@ static void __init ath79_detect_sys_type(void)
         case REV_ID_MAJOR_AR7240:
                 ath79_soc = ATH79_SOC_AR7240;
                 chip = "7240";
-                rev = (id & AR724X_REV_ID_REVISION_MASK);
+                rev = id & AR724X_REV_ID_REVISION_MASK;
                 break;
 
         case REV_ID_MAJOR_AR7241:
                 ath79_soc = ATH79_SOC_AR7241;
                 chip = "7241";
-                rev = (id & AR724X_REV_ID_REVISION_MASK);
+                rev = id & AR724X_REV_ID_REVISION_MASK;
                 break;
 
         case REV_ID_MAJOR_AR7242:
                 ath79_soc = ATH79_SOC_AR7242;
                 chip = "7242";
-                rev = (id & AR724X_REV_ID_REVISION_MASK);
+                rev = id & AR724X_REV_ID_REVISION_MASK;
+                break;
+
+        case REV_ID_MAJOR_AR9330:
+                ath79_soc = ATH79_SOC_AR9330;
+                chip = "9330";
+                rev = id & AR933X_REV_ID_REVISION_MASK;
+                break;
+
+        case REV_ID_MAJOR_AR9331:
+                ath79_soc = ATH79_SOC_AR9331;
+                chip = "9331";
+                rev = id & AR933X_REV_ID_REVISION_MASK;
                 break;
 
         case REV_ID_MAJOR_AR913X:
@@ -134,9 +146,11 @@ static void __init ath79_detect_sys_type(void)
                 break;
 
         default:
-                panic("ath79: unknown SoC, id:0x%08x\n", id);
+                panic("ath79: unknown SoC, id:0x%08x", id);
         }
 
+        ath79_soc_rev = rev;
+
         sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
         pr_info("SoC: %s\n", ath79_sys_type);
 }
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 1cfdda03546a..aab6b0c40a75 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -289,7 +289,7 @@ static void __init bcm47xx_register_ssb(void)
         err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE,
                                       bcm47xx_get_invariants);
         if (err)
-                panic("Failed to initialize SSB bus (err %d)\n", err);
+                panic("Failed to initialize SSB bus (err %d)", err);
 
         mcore = &bcm47xx_bus.ssb.mipscore;
         if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
@@ -314,7 +314,7 @@ static void __init bcm47xx_register_bcma(void)
 
         err = bcma_host_soc_register(&bcm47xx_bus.bcma);
         if (err)
-                panic("Failed to initialize BCMA bus (err %d)\n", err);
+                panic("Failed to initialize BCMA bus (err %d)", err);
 }
 #endif
 
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index fb177d6df066..6b1b9ad8d857 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
 config BCM63XX_CPU_6358
         bool "support 6358 CPU"
         select HW_HAS_PCI
+
+config BCM63XX_CPU_6368
+        bool "support 6368 CPU"
+        select HW_HAS_PCI
 endmenu
 
 source "arch/mips/bcm63xx/boards/Kconfig"
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 40b223b603be..e62461f817d7 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -709,15 +709,9 @@ void __init board_prom_init(void)
         char cfe_version[32];
         u32 val;
 
-        /* read base address of boot chip select (0)
-         * 6345 does not have MPI but boots from standard
-         * MIPS Flash address */
-        if (BCMCPU_IS_6345())
-                val = 0x1fc00000;
-        else {
-                val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-                val &= MPI_CSBASE_BASE_MASK;
-        }
+        /* read base address of boot chip select (0) */
+        val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+        val &= MPI_CSBASE_BASE_MASK;
         boot_addr = (u8 *)KSEG1ADDR(val);
 
         /* dump cfe version */
@@ -797,18 +791,6 @@ void __init board_prom_init(void)
         }
 
         bcm_gpio_writel(val, GPIO_MODE_REG);
-
-        /* Generate MAC address for WLAN and
-         * register our SPROM */
-#ifdef CONFIG_SSB_PCIHOST
-        if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
-                memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
-                memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
-                if (ssb_arch_register_fallback_sprom(
-                                &bcm63xx_get_fallback_sprom) < 0)
-                        printk(KERN_ERR PFX "failed to register fallback SPROM\n");
-        }
-#endif
 }
 
 /*
@@ -892,13 +874,23 @@ int __init board_register_devices(void)
         if (board.has_dsp)
                 bcm63xx_dsp_register(&board.dsp);
 
-        /* read base address of boot chip select (0) */
-        if (BCMCPU_IS_6345())
-                val = 0x1fc00000;
-        else {
-                val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-                val &= MPI_CSBASE_BASE_MASK;
+        /* Generate MAC address for WLAN and register our SPROM,
+         * do this after registering enet devices
+         */
+#ifdef CONFIG_SSB_PCIHOST
+        if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
+                memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+                memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+                if (ssb_arch_register_fallback_sprom(
+                                &bcm63xx_get_fallback_sprom) < 0)
+                        pr_err(PFX "failed to register fallback SPROM\n");
         }
+#endif
+
+        /* read base address of boot chip select (0) */
+        val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+        val &= MPI_CSBASE_BASE_MASK;
+
         mtd_resources[0].start = val;
         mtd_resources[0].end = 0x1FFFFFFF;
 
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 2c68ee9ccee2..9d57c71b7b58 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -10,6 +10,7 @@
 #include <linux/mutex.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <bcm63xx_cpu.h>
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
@@ -113,6 +114,34 @@ static struct clk clk_ephy = {
 };
 
 /*
+ * Ethernet switch clock
+ */
+static void enetsw_set(struct clk *clk, int enable)
+{
+        if (!BCMCPU_IS_6368())
+                return;
+        bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
+                        CKCTL_6368_SWPKT_USB_EN |
+                        CKCTL_6368_SWPKT_SAR_EN, enable);
+        if (enable) {
+                u32 val;
+
+                /* reset switch core afer clock change */
+                val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
+                val &= ~SOFTRESET_6368_ENETSW_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                msleep(10);
+                val |= SOFTRESET_6368_ENETSW_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                msleep(10);
+        }
+}
+
+static struct clk clk_enetsw = {
+        .set    = enetsw_set,
+};
+
+/*
  * PCM clock
  */
 static void pcm_set(struct clk *clk, int enable)
@@ -131,9 +160,10 @@ static struct clk clk_pcm = {
  */
 static void usbh_set(struct clk *clk, int enable)
 {
-        if (!BCMCPU_IS_6348())
-                return;
-        bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+        if (BCMCPU_IS_6348())
+                bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+        else if (BCMCPU_IS_6368())
+                bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
 }
 
 static struct clk clk_usbh = {
@@ -162,6 +192,36 @@ static struct clk clk_spi = {
 };
 
 /*
+ * XTM clock
+ */
+static void xtm_set(struct clk *clk, int enable)
+{
+        if (!BCMCPU_IS_6368())
+                return;
+
+        bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
+                        CKCTL_6368_SWPKT_SAR_EN, enable);
+
+        if (enable) {
+                u32 val;
+
+                /* reset sar core afer clock change */
+                val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
+                val &= ~SOFTRESET_6368_SAR_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                mdelay(1);
+                val |= SOFTRESET_6368_SAR_MASK;
+                bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+                mdelay(1);
+        }
+}
+
+
+static struct clk clk_xtm = {
+        .set    = xtm_set,
+};
+
+/*
  * Internal peripheral clock
  */
 static struct clk clk_periph = {
@@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
                 return &clk_enet0;
         if (!strcmp(id, "enet1"))
                 return &clk_enet1;
+        if (!strcmp(id, "enetsw"))
+                return &clk_enetsw;
         if (!strcmp(id, "ephy"))
                 return &clk_ephy;
         if (!strcmp(id, "usbh"))
                 return &clk_usbh;
         if (!strcmp(id, "spi"))
                 return &clk_spi;
+        if (!strcmp(id, "xtm"))
+                return &clk_xtm;
         if (!strcmp(id, "periph"))
                 return &clk_periph;
         if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 7c7e4d4486ce..8f0d6c7725ea 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,166 +29,47 @@ static u16 bcm63xx_cpu_rev;
 static unsigned int bcm63xx_cpu_freq;
 static unsigned int bcm63xx_memory_size;
 
-/*
- * 6338 register sets and irqs
- */
-static const unsigned long bcm96338_regs_base[] = {
-        [RSET_DSL_LMEM]         = BCM_6338_DSL_LMEM_BASE,
-        [RSET_PERF]             = BCM_6338_PERF_BASE,
-        [RSET_TIMER]            = BCM_6338_TIMER_BASE,
-        [RSET_WDT]              = BCM_6338_WDT_BASE,
-        [RSET_UART0]            = BCM_6338_UART0_BASE,
-        [RSET_UART1]            = BCM_6338_UART1_BASE,
-        [RSET_GPIO]             = BCM_6338_GPIO_BASE,
-        [RSET_SPI]              = BCM_6338_SPI_BASE,
-        [RSET_OHCI0]            = BCM_6338_OHCI0_BASE,
-        [RSET_OHCI_PRIV]        = BCM_6338_OHCI_PRIV_BASE,
-        [RSET_USBH_PRIV]        = BCM_6338_USBH_PRIV_BASE,
-        [RSET_UDC0]             = BCM_6338_UDC0_BASE,
-        [RSET_MPI]              = BCM_6338_MPI_BASE,
-        [RSET_PCMCIA]           = BCM_6338_PCMCIA_BASE,
-        [RSET_SDRAM]            = BCM_6338_SDRAM_BASE,
-        [RSET_DSL]              = BCM_6338_DSL_BASE,
-        [RSET_ENET0]            = BCM_6338_ENET0_BASE,
-        [RSET_ENET1]            = BCM_6338_ENET1_BASE,
-        [RSET_ENETDMA]          = BCM_6338_ENETDMA_BASE,
-        [RSET_MEMC]             = BCM_6338_MEMC_BASE,
-        [RSET_DDR]              = BCM_6338_DDR_BASE,
+static const unsigned long bcm6338_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6338)
 };
 
-static const int bcm96338_irqs[] = {
-        [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
-        [IRQ_UART0]             = BCM_6338_UART0_IRQ,
-        [IRQ_DSL]               = BCM_6338_DSL_IRQ,
-        [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
-        [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
-        [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
-        [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
+static const int bcm6338_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6338)
 };
 
-/*
- * 6345 register sets and irqs
- */
-static const unsigned long bcm96345_regs_base[] = {
-        [RSET_DSL_LMEM]         = BCM_6345_DSL_LMEM_BASE,
-        [RSET_PERF]             = BCM_6345_PERF_BASE,
-        [RSET_TIMER]            = BCM_6345_TIMER_BASE,
-        [RSET_WDT]              = BCM_6345_WDT_BASE,
-        [RSET_UART0]            = BCM_6345_UART0_BASE,
-        [RSET_UART1]            = BCM_6345_UART1_BASE,
-        [RSET_GPIO]             = BCM_6345_GPIO_BASE,
-        [RSET_SPI]              = BCM_6345_SPI_BASE,
-        [RSET_UDC0]             = BCM_6345_UDC0_BASE,
-        [RSET_OHCI0]            = BCM_6345_OHCI0_BASE,
-        [RSET_OHCI_PRIV]        = BCM_6345_OHCI_PRIV_BASE,
-        [RSET_USBH_PRIV]        = BCM_6345_USBH_PRIV_BASE,
-        [RSET_MPI]              = BCM_6345_MPI_BASE,
-        [RSET_PCMCIA]           = BCM_6345_PCMCIA_BASE,
-        [RSET_DSL]              = BCM_6345_DSL_BASE,
-        [RSET_ENET0]            = BCM_6345_ENET0_BASE,
-        [RSET_ENET1]            = BCM_6345_ENET1_BASE,
-        [RSET_ENETDMA]          = BCM_6345_ENETDMA_BASE,
-        [RSET_EHCI0]            = BCM_6345_EHCI0_BASE,
-        [RSET_SDRAM]            = BCM_6345_SDRAM_BASE,
-        [RSET_MEMC]             = BCM_6345_MEMC_BASE,
-        [RSET_DDR]              = BCM_6345_DDR_BASE,
+static const unsigned long bcm6345_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6345)
 };
 
-static const int bcm96345_irqs[] = {
-        [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
-        [IRQ_UART0]             = BCM_6345_UART0_IRQ,
-        [IRQ_DSL]               = BCM_6345_DSL_IRQ,
-        [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
-        [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
-        [IRQ_ENET0_RXDMA]       = BCM_6345_ENET0_RXDMA_IRQ,
-        [IRQ_ENET0_TXDMA]       = BCM_6345_ENET0_TXDMA_IRQ,
+static const int bcm6345_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6345)
 };
 
-/*
- * 6348 register sets and irqs
- */
-static const unsigned long bcm96348_regs_base[] = {
-        [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
-        [RSET_PERF]             = BCM_6348_PERF_BASE,
-        [RSET_TIMER]            = BCM_6348_TIMER_BASE,
-        [RSET_WDT]              = BCM_6348_WDT_BASE,
-        [RSET_UART0]            = BCM_6348_UART0_BASE,
-        [RSET_UART1]            = BCM_6348_UART1_BASE,
-        [RSET_GPIO]             = BCM_6348_GPIO_BASE,
-        [RSET_SPI]              = BCM_6348_SPI_BASE,
-        [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
-        [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
-        [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
-        [RSET_MPI]              = BCM_6348_MPI_BASE,
-        [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
-        [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
-        [RSET_DSL]              = BCM_6348_DSL_BASE,
-        [RSET_ENET0]            = BCM_6348_ENET0_BASE,
-        [RSET_ENET1]            = BCM_6348_ENET1_BASE,
-        [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
-        [RSET_MEMC]             = BCM_6348_MEMC_BASE,
-        [RSET_DDR]              = BCM_6348_DDR_BASE,
+static const unsigned long bcm6348_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6348)
 };
 
-static const int bcm96348_irqs[] = {
-        [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
-        [IRQ_UART0]             = BCM_6348_UART0_IRQ,
-        [IRQ_DSL]               = BCM_6348_DSL_IRQ,
-        [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
-        [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
-        [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
-        [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
-        [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
-        [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
-        [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
-        [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
-        [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
-        [IRQ_PCI]               = BCM_6348_PCI_IRQ,
+static const int bcm6348_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6348)
+
 };
 
-/*
- * 6358 register sets and irqs
- */
-static const unsigned long bcm96358_regs_base[] = {
-        [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
-        [RSET_PERF]             = BCM_6358_PERF_BASE,
-        [RSET_TIMER]            = BCM_6358_TIMER_BASE,
-        [RSET_WDT]              = BCM_6358_WDT_BASE,
-        [RSET_UART0]            = BCM_6358_UART0_BASE,
-        [RSET_UART1]            = BCM_6358_UART1_BASE,
-        [RSET_GPIO]             = BCM_6358_GPIO_BASE,
-        [RSET_SPI]              = BCM_6358_SPI_BASE,
-        [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
-        [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
-        [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
-        [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
-        [RSET_MPI]              = BCM_6358_MPI_BASE,
-        [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
-        [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
-        [RSET_DSL]              = BCM_6358_DSL_BASE,
-        [RSET_ENET0]            = BCM_6358_ENET0_BASE,
-        [RSET_ENET1]            = BCM_6358_ENET1_BASE,
-        [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
-        [RSET_MEMC]             = BCM_6358_MEMC_BASE,
-        [RSET_DDR]              = BCM_6358_DDR_BASE,
+static const unsigned long bcm6358_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6358)
+};
+
+static const int bcm6358_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6358)
+
 };
 
-static const int bcm96358_irqs[] = {
-        [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
-        [IRQ_UART0]             = BCM_6358_UART0_IRQ,
-        [IRQ_UART1]             = BCM_6358_UART1_IRQ,
-        [IRQ_DSL]               = BCM_6358_DSL_IRQ,
-        [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
-        [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
-        [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
-        [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
-        [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
-        [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
-        [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
-        [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
-        [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
-        [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
-        [IRQ_PCI]               = BCM_6358_PCI_IRQ,
+static const unsigned long bcm6368_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6368)
+};
+
+static const int bcm6368_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6368)
+
 };
 
 u16 __bcm63xx_get_cpu_id(void)
@@ -217,20 +98,19 @@ unsigned int bcm63xx_get_memory_size(void)
 
 static unsigned int detect_cpu_clock(void)
 {
-        unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
-
-        /* BCM6338 has a fixed 240 Mhz frequency */
-        if (BCMCPU_IS_6338())
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6338_CPU_ID:
+                /* BCM6338 has a fixed 240 Mhz frequency */
                 return 240000000;
 
-        /* BCM6345 has a fixed 140Mhz frequency */
-        if (BCMCPU_IS_6345())
+        case BCM6345_CPU_ID:
+                /* BCM6345 has a fixed 140Mhz frequency */
                 return 140000000;
 
-        /*
-         * frequency depends on PLL configuration:
-         */
-        if (BCMCPU_IS_6348()) {
+        case BCM6348_CPU_ID:
+        {
+                unsigned int tmp, n1, n2, m1;
+
                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
@@ -239,17 +119,47 @@ static unsigned int detect_cpu_clock(void)
                 n1 += 1;
                 n2 += 2;
                 m1 += 1;
+                return (16 * 1000000 * n1 * n2) / m1;
         }
 
-        if (BCMCPU_IS_6358()) {
+        case BCM6358_CPU_ID:
+        {
+                unsigned int tmp, n1, n2, m1;
+
                 /* 16MHz * N1 * N2 / M1_CPU */
                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
+                return (16 * 1000000 * n1 * n2) / m1;
         }
 
-        return (16 * 1000000 * n1 * n2) / m1;
+        case BCM6368_CPU_ID:
+        {
+                unsigned int tmp, p1, p2, ndiv, m1;
+
+                /* (64MHz / P1) * P2 * NDIV / M1_CPU */
+                tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
+
+                p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
+                        DMIPSPLLCFG_6368_P1_SHIFT;
+
+                p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
+                        DMIPSPLLCFG_6368_P2_SHIFT;
+
+                ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
+                        DMIPSPLLCFG_6368_NDIV_SHIFT;
+
+                tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
+                m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
+                        DMIPSPLLDIV_6368_MDIV_SHIFT;
+
+                return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
+        }
+
+        default:
+                BUG();
+        }
 }
 
 /*
@@ -260,8 +170,10 @@ static unsigned int detect_memory_size(void)
         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
         u32 val;
 
-        if (BCMCPU_IS_6345())
-                return (8 * 1024 * 1024);
+        if (BCMCPU_IS_6345()) {
+                val = bcm_sdram_readl(SDRAM_MBASE_REG);
+                return (val * 8 * 1024 * 1024);
+        }
 
         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
                 val = bcm_sdram_readl(SDRAM_CFG_REG);
@@ -271,7 +183,7 @@ static unsigned int detect_memory_size(void)
                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
         }
 
-        if (BCMCPU_IS_6358()) {
+        if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
                 val = bcm_memc_readl(MEMC_CFG_REG);
                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -301,24 +213,33 @@ void __init bcm63xx_cpu_init(void)
         case CPU_BMIPS3300:
                 if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
                         expected_cpu_id = BCM6348_CPU_ID;
-                        bcm63xx_regs_base = bcm96348_regs_base;
-                        bcm63xx_irqs = bcm96348_irqs;
+                        bcm63xx_regs_base = bcm6348_regs_base;
+                        bcm63xx_irqs = bcm6348_irqs;
                 } else {
                         __cpu_name[cpu] = "Broadcom BCM6338";
                         expected_cpu_id = BCM6338_CPU_ID;
-                        bcm63xx_regs_base = bcm96338_regs_base;
-                        bcm63xx_irqs = bcm96338_irqs;
+                        bcm63xx_regs_base = bcm6338_regs_base;
+                        bcm63xx_irqs = bcm6338_irqs;
                 }
                 break;
         case CPU_BMIPS32:
                 expected_cpu_id = BCM6345_CPU_ID;
-                bcm63xx_regs_base = bcm96345_regs_base;
-                bcm63xx_irqs = bcm96345_irqs;
+                bcm63xx_regs_base = bcm6345_regs_base;
+                bcm63xx_irqs = bcm6345_irqs;
                 break;
         case CPU_BMIPS4350:
-                expected_cpu_id = BCM6358_CPU_ID;
-                bcm63xx_regs_base = bcm96358_regs_base;
-                bcm63xx_irqs = bcm96358_irqs;
+                switch (read_c0_prid() & 0xf0) {
+                case 0x10:
+                        expected_cpu_id = BCM6358_CPU_ID;
+                        bcm63xx_regs_base = bcm6358_regs_base;
+                        bcm63xx_irqs = bcm6358_irqs;
+                        break;
+                case 0x30:
+                        expected_cpu_id = BCM6368_CPU_ID;
+                        bcm63xx_regs_base = bcm6368_regs_base;
+                        bcm63xx_irqs = bcm6368_irqs;
+                        break;
+                }
                 break;
         }
 
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
index c2963da0253e..d6e42c608325 100644
--- a/arch/mips/bcm63xx/dev-uart.c
+++ b/arch/mips/bcm63xx/dev-uart.c
@@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
         if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
                 return -ENODEV;
 
-        if (id == 1 && !BCMCPU_IS_6358())
+        if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
                 return -ENODEV;
 
         if (id == 0) {
diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c
index f560fe7d38dd..a6c2135dbf38 100644
--- a/arch/mips/bcm63xx/gpio.c
+++ b/arch/mips/bcm63xx/gpio.c
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
- * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>
  */
 
 #include <linux/kernel.h>
@@ -18,6 +18,34 @@
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
 
+#ifndef BCMCPU_RUNTIME_DETECT
+#define gpio_out_low_reg        GPIO_DATA_LO_REG
+#ifdef CONFIG_BCM63XX_CPU_6345
+#ifdef gpio_out_low_reg
+#undef gpio_out_low_reg
+#define gpio_out_low_reg        GPIO_DATA_LO_REG_6345
+#endif /* gpio_out_low_reg */
+#endif /* CONFIG_BCM63XX_CPU_6345 */
+
+static inline void bcm63xx_gpio_out_low_reg_init(void)
+{
+}
+#else /* ! BCMCPU_RUNTIME_DETECT */
+static u32 gpio_out_low_reg;
+
+static void bcm63xx_gpio_out_low_reg_init(void)
+{
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6345_CPU_ID:
+                gpio_out_low_reg = GPIO_DATA_LO_REG_6345;
+                break;
+        default:
+                gpio_out_low_reg = GPIO_DATA_LO_REG;
+                break;
+        }
+}
+#endif /* ! BCMCPU_RUNTIME_DETECT */
+
 static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
 static u32 gpio_out_low, gpio_out_high;
 
@@ -33,7 +61,7 @@ static void bcm63xx_gpio_set(struct gpio_chip *chip,
                 BUG();
 
         if (gpio < 32) {
-                reg = GPIO_DATA_LO_REG;
+                reg = gpio_out_low_reg;
                 mask = 1 << gpio;
                 v = &gpio_out_low;
         } else {
@@ -60,7 +88,7 @@ static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
                 BUG();
 
         if (gpio < 32) {
-                reg = GPIO_DATA_LO_REG;
+                reg = gpio_out_low_reg;
                 mask = 1 << gpio;
         } else {
                 reg = GPIO_DATA_HI_REG;
@@ -125,8 +153,11 @@ static struct gpio_chip bcm63xx_gpio_chip = {
 
 int __init bcm63xx_gpio_init(void)
 {
-        gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG);
-        gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
+        bcm63xx_gpio_out_low_reg_init();
+
+        gpio_out_low = bcm_gpio_readl(gpio_out_low_reg);
+        if (!BCMCPU_IS_6345())
+                gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
         bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
         pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
 
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 162e11b4ed75..9a216a451d92 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -19,19 +19,187 @@
 #include <bcm63xx_io.h>
 #include <bcm63xx_irq.h>
 
+static void __dispatch_internal(void) __maybe_unused;
+static void __dispatch_internal_64(void) __maybe_unused;
+static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
+static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
+static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
+static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
+
+#ifndef BCMCPU_RUNTIME_DETECT
+#ifdef CONFIG_BCM63XX_CPU_6338
+#define irq_stat_reg            PERF_IRQSTAT_6338_REG
+#define irq_mask_reg            PERF_IRQMASK_6338_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     0
+#define ext_irq_start           0
+#define ext_irq_end             0
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6338
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6345
+#define irq_stat_reg            PERF_IRQSTAT_6345_REG
+#define irq_mask_reg            PERF_IRQMASK_6345_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     0
+#define ext_irq_start           0
+#define ext_irq_end             0
+#define ext_irq_count           0
+#define ext_irq_cfg_reg1        0
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6348
+#define irq_stat_reg            PERF_IRQSTAT_6348_REG
+#define irq_mask_reg            PERF_IRQMASK_6348_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     0
+#define ext_irq_start           0
+#define ext_irq_end             0
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6348
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6358
+#define irq_stat_reg            PERF_IRQSTAT_6358_REG
+#define irq_mask_reg            PERF_IRQMASK_6358_REG
+#define irq_bits                32
+#define is_ext_irq_cascaded     1
+#define ext_irq_start           (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end             (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6358
+#define ext_irq_cfg_reg2        0
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6368
+#define irq_stat_reg            PERF_IRQSTAT_6368_REG
+#define irq_mask_reg            PERF_IRQMASK_6368_REG
+#define irq_bits                64
+#define is_ext_irq_cascaded     1
+#define ext_irq_start           (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end             (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
+#define ext_irq_count           6
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6368
+#define ext_irq_cfg_reg2        PERF_EXTIRQ_CFG_REG2_6368
+#endif
+
+#if irq_bits == 32
+#define dispatch_internal                       __dispatch_internal
+#define internal_irq_mask                       __internal_irq_mask_32
+#define internal_irq_unmask                     __internal_irq_unmask_32
+#else
+#define dispatch_internal                       __dispatch_internal_64
+#define internal_irq_mask                       __internal_irq_mask_64
+#define internal_irq_unmask                     __internal_irq_unmask_64
+#endif
+
+#define irq_stat_addr   (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
+#define irq_mask_addr   (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
+
+static inline void bcm63xx_init_irq(void)
+{
+}
+#else /* ! BCMCPU_RUNTIME_DETECT */
+
+static u32 irq_stat_addr, irq_mask_addr;
+static void (*dispatch_internal)(void);
+static int is_ext_irq_cascaded;
+static unsigned int ext_irq_count;
+static unsigned int ext_irq_start, ext_irq_end;
+static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
+static void (*internal_irq_mask)(unsigned int irq);
+static void (*internal_irq_unmask)(unsigned int irq);
+
+static void bcm63xx_init_irq(void)
+{
+        int irq_bits;
+
+        irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
+        irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
+
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6338_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6338_REG;
+                irq_mask_addr += PERF_IRQMASK_6338_REG;
+                irq_bits = 32;
+                break;
+        case BCM6345_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6345_REG;
+                irq_mask_addr += PERF_IRQMASK_6345_REG;
+                irq_bits = 32;
+                break;
+        case BCM6348_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6348_REG;
+                irq_mask_addr += PERF_IRQMASK_6348_REG;
+                irq_bits = 32;
+                ext_irq_count = 4;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
+                break;
+        case BCM6358_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6358_REG;
+                irq_mask_addr += PERF_IRQMASK_6358_REG;
+                irq_bits = 32;
+                ext_irq_count = 4;
+                is_ext_irq_cascaded = 1;
+                ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+                ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
+                break;
+        case BCM6368_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6368_REG;
+                irq_mask_addr += PERF_IRQMASK_6368_REG;
+                irq_bits = 64;
+                ext_irq_count = 6;
+                is_ext_irq_cascaded = 1;
+                ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+                ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
+                ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
+                break;
+        default:
+                BUG();
+        }
+
+        if (irq_bits == 32) {
+                dispatch_internal = __dispatch_internal;
+                internal_irq_mask = __internal_irq_mask_32;
+                internal_irq_unmask = __internal_irq_unmask_32;
+        } else {
+                dispatch_internal = __dispatch_internal_64;
+                internal_irq_mask = __internal_irq_mask_64;
+                internal_irq_unmask = __internal_irq_unmask_64;
+        }
+}
+#endif /* ! BCMCPU_RUNTIME_DETECT */
+
+static inline u32 get_ext_irq_perf_reg(int irq)
+{
+        if (irq < 4)
+                return ext_irq_cfg_reg1;
+        return ext_irq_cfg_reg2;
+}
+
+static inline void handle_internal(int intbit)
+{
+        if (is_ext_irq_cascaded &&
+            intbit >= ext_irq_start && intbit <= ext_irq_end)
+                do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
+        else
+                do_IRQ(intbit + IRQ_INTERNAL_BASE);
+}
+
 /*
  * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
  * prioritize any interrupt relatively to another. the static counter
  * will resume the loop where it ended the last time we left this
  * function.
  */
-static void bcm63xx_irq_dispatch_internal(void)
+static void __dispatch_internal(void)
 {
         u32 pending;
         static int i;
 
-        pending = bcm_perf_readl(PERF_IRQMASK_REG) &
-                bcm_perf_readl(PERF_IRQSTAT_REG);
+        pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
 
         if (!pending)
                 return ;
@@ -41,7 +209,28 @@ static void bcm63xx_irq_dispatch_internal(void)
 
                 i = (i + 1) & 0x1f;
                 if (pending & (1 << to_call)) {
-                        do_IRQ(to_call + IRQ_INTERNAL_BASE);
+                        handle_internal(to_call);
+                        break;
+                }
+        }
+}
+
+static void __dispatch_internal_64(void)
+{
+        u64 pending;
+        static int i;
+
+        pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);
+
+        if (!pending)
+                return ;
+
+        while (1) {
+                int to_call = i;
+
+                i = (i + 1) & 0x3f;
+                if (pending & (1ull << to_call)) {
+                        handle_internal(to_call);
                         break;
                 }
         }
@@ -60,15 +249,17 @@ asmlinkage void plat_irq_dispatch(void)
                 if (cause & CAUSEF_IP7)
                         do_IRQ(7);
                 if (cause & CAUSEF_IP2)
-                        bcm63xx_irq_dispatch_internal();
-                if (cause & CAUSEF_IP3)
-                        do_IRQ(IRQ_EXT_0);
-                if (cause & CAUSEF_IP4)
-                        do_IRQ(IRQ_EXT_1);
-                if (cause & CAUSEF_IP5)
-                        do_IRQ(IRQ_EXT_2);
-                if (cause & CAUSEF_IP6)
-                        do_IRQ(IRQ_EXT_3);
+                        dispatch_internal();
+                if (!is_ext_irq_cascaded) {
+                        if (cause & CAUSEF_IP3)
+                                do_IRQ(IRQ_EXT_0);
+                        if (cause & CAUSEF_IP4)
+                                do_IRQ(IRQ_EXT_1);
+                        if (cause & CAUSEF_IP5)
+                                do_IRQ(IRQ_EXT_2);
+                        if (cause & CAUSEF_IP6)
+                                do_IRQ(IRQ_EXT_3);
+                }
         } while (1);
 }
 
@@ -76,24 +267,50 @@ asmlinkage void plat_irq_dispatch(void)
  * internal IRQs operations: only mask/unmask on PERF irq mask
  * register.
  */
-static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
+static void __internal_irq_mask_32(unsigned int irq)
 {
-        unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
         u32 mask;
 
-        mask = bcm_perf_readl(PERF_IRQMASK_REG);
+        mask = bcm_readl(irq_mask_addr);
         mask &= ~(1 << irq);
-        bcm_perf_writel(mask, PERF_IRQMASK_REG);
+        bcm_writel(mask, irq_mask_addr);
 }
 
-static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+static void __internal_irq_mask_64(unsigned int irq)
+{
+        u64 mask;
+
+        mask = bcm_readq(irq_mask_addr);
+        mask &= ~(1ull << irq);
+        bcm_writeq(mask, irq_mask_addr);
+}
+
+static void __internal_irq_unmask_32(unsigned int irq)
 {
-        unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
         u32 mask;
 
-        mask = bcm_perf_readl(PERF_IRQMASK_REG);
+        mask = bcm_readl(irq_mask_addr);
         mask |= (1 << irq);
-        bcm_perf_writel(mask, PERF_IRQMASK_REG);
+        bcm_writel(mask, irq_mask_addr);
+}
+
+static void __internal_irq_unmask_64(unsigned int irq)
+{
+        u64 mask;
+
+        mask = bcm_readq(irq_mask_addr);
+        mask |= (1ull << irq);
+        bcm_writeq(mask, irq_mask_addr);
+}
+
+static void bcm63xx_internal_irq_mask(struct irq_data *d)
+{
+        internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
+}
+
+static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+{
+        internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
 }
 
 /*
@@ -102,94 +319,131 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
  */
 static void bcm63xx_external_irq_mask(struct irq_data *d)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg &= ~EXTIRQ_CFG_MASK(irq);
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
+
+        if (BCMCPU_IS_6348())
+                reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
+        else
+                reg &= ~EXTIRQ_CFG_MASK(irq % 4);
+
+        bcm_perf_writel(reg, regaddr);
+        if (is_ext_irq_cascaded)
+                internal_irq_mask(irq + ext_irq_start);
 }
 
 static void bcm63xx_external_irq_unmask(struct irq_data *d)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg |= EXTIRQ_CFG_MASK(irq);
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
+
+        if (BCMCPU_IS_6348())
+                reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
+        else
+                reg |= EXTIRQ_CFG_MASK(irq % 4);
+
+        bcm_perf_writel(reg, regaddr);
+
+        if (is_ext_irq_cascaded)
+                internal_irq_unmask(irq + ext_irq_start);
 }
 
 static void bcm63xx_external_irq_clear(struct irq_data *d)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg |= EXTIRQ_CFG_CLEAR(irq);
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
-}
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
 
-static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
-{
-        set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
-        irq_enable_hazard();
-        bcm63xx_external_irq_unmask(d);
-        return 0;
-}
+        if (BCMCPU_IS_6348())
+                reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
+        else
+                reg |= EXTIRQ_CFG_CLEAR(irq % 4);
 
-static void bcm63xx_external_irq_shutdown(struct irq_data *d)
-{
-        bcm63xx_external_irq_mask(d);
-        clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
-        irq_disable_hazard();
+        bcm_perf_writel(reg, regaddr);
 }
 
 static int bcm63xx_external_irq_set_type(struct irq_data *d,
                                          unsigned int flow_type)
 {
-        unsigned int irq = d->irq - IRQ_EXT_BASE;
-        u32 reg;
+        unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+        u32 reg, regaddr;
+        int levelsense, sense, bothedge;
 
         flow_type &= IRQ_TYPE_SENSE_MASK;
 
         if (flow_type == IRQ_TYPE_NONE)
                 flow_type = IRQ_TYPE_LEVEL_LOW;
 
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
+        levelsense = sense = bothedge = 0;
         switch (flow_type) {
         case IRQ_TYPE_EDGE_BOTH:
-                reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-                reg |= EXTIRQ_CFG_BOTHEDGE(irq);
+                bothedge = 1;
                 break;
 
         case IRQ_TYPE_EDGE_RISING:
-                reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-                reg |= EXTIRQ_CFG_SENSE(irq);
-                reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
+                sense = 1;
                 break;
 
         case IRQ_TYPE_EDGE_FALLING:
-                reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-                reg &= ~EXTIRQ_CFG_SENSE(irq);
-                reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
                 break;
 
         case IRQ_TYPE_LEVEL_HIGH:
-                reg |= EXTIRQ_CFG_LEVELSENSE(irq);
-                reg |= EXTIRQ_CFG_SENSE(irq);
+                levelsense = 1;
+                sense = 1;
                 break;
 
         case IRQ_TYPE_LEVEL_LOW:
-                reg |= EXTIRQ_CFG_LEVELSENSE(irq);
-                reg &= ~EXTIRQ_CFG_SENSE(irq);
+                levelsense = 1;
                 break;
 
         default:
                 printk(KERN_ERR "bogus flow type combination given !\n");
                 return -EINVAL;
         }
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+
+        regaddr = get_ext_irq_perf_reg(irq);
+        reg = bcm_perf_readl(regaddr);
+        irq %= 4;
+
+        if (BCMCPU_IS_6348()) {
+                if (levelsense)
+                        reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
+                if (sense)
+                        reg |= EXTIRQ_CFG_SENSE_6348(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
+                if (bothedge)
+                        reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
+        }
+
+        if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+                if (levelsense)
+                        reg |= EXTIRQ_CFG_LEVELSENSE(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
+                if (sense)
+                        reg |= EXTIRQ_CFG_SENSE(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_SENSE(irq);
+                if (bothedge)
+                        reg |= EXTIRQ_CFG_BOTHEDGE(irq);
+                else
+                        reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
+        }
+
+        bcm_perf_writel(reg, regaddr);
 
         irqd_set_trigger_type(d, flow_type);
         if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -208,9 +462,6 @@ static struct irq_chip bcm63xx_internal_irq_chip = {
 
 static struct irq_chip bcm63xx_external_irq_chip = {
         .name           = "bcm63xx_epic",
-        .irq_startup    = bcm63xx_external_irq_startup,
-        .irq_shutdown   = bcm63xx_external_irq_shutdown,
-
         .irq_ack        = bcm63xx_external_irq_clear,
 
         .irq_mask       = bcm63xx_external_irq_mask,
@@ -225,18 +476,30 @@ static struct irqaction cpu_ip2_cascade_action = {
         .flags          = IRQF_NO_THREAD,
 };
 
+static struct irqaction cpu_ext_cascade_action = {
+        .handler        = no_action,
+        .name           = "cascade_extirq",
+        .flags          = IRQF_NO_THREAD,
+};
+
 void __init arch_init_irq(void)
 {
         int i;
 
+        bcm63xx_init_irq();
         mips_cpu_irq_init();
         for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
                 irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
                                          handle_level_irq);
 
-        for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
+        for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
                 irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
                                          handle_edge_irq);
 
-        setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
+        if (!is_ext_irq_cascaded) {
+                for (i = 3; i < 3 + ext_irq_count; ++i)
+                        setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
+        }
+
+        setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
 }
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index be252efa0757..99d7f405cbeb 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -32,9 +32,12 @@ void __init prom_init(void)
                 mask = CKCTL_6345_ALL_SAFE_EN;
         else if (BCMCPU_IS_6348())
                 mask = CKCTL_6348_ALL_SAFE_EN;
-        else
-                /* BCMCPU_IS_6358() */
+        else if (BCMCPU_IS_6358())
                 mask = CKCTL_6358_ALL_SAFE_EN;
+        else if (BCMCPU_IS_6368())
+                mask = CKCTL_6368_ALL_SAFE_EN;
+        else
+                mask = 0;
 
         reg = bcm_perf_readl(PERF_CKCTL_REG);
         reg &= ~mask;
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index d0056598fbfc..d209f85d87bb 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -63,13 +63,33 @@ static void bcm6348_a1_reboot(void)
 
 void bcm63xx_machine_reboot(void)
 {
-        u32 reg;
+        u32 reg, perf_regs[2] = { 0, 0 };
+        unsigned int i;
 
         /* mask and clear all external irq */
-        reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-        reg &= ~EXTIRQ_CFG_MASK_ALL;
-        reg |= EXTIRQ_CFG_CLEAR_ALL;
-        bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6338_CPU_ID:
+                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
+                break;
+        case BCM6348_CPU_ID:
+                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
+                break;
+        case BCM6358_CPU_ID:
+                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
+                break;
+        }
+
+        for (i = 0; i < 2; i++) {
+                reg = bcm_perf_readl(perf_regs[i]);
+                if (BCMCPU_IS_6348()) {
+                        reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
+                        reg |= EXTIRQ_CFG_CLEAR_ALL_6348;
+                } else {
+                        reg &= ~EXTIRQ_CFG_MASK_ALL;
+                        reg |= EXTIRQ_CFG_CLEAR_ALL;
+                }
+                bcm_perf_writel(reg, perf_regs[i]);
+        }
 
         if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
                 bcm6348_a1_reboot();
@@ -124,4 +144,4 @@ int __init bcm63xx_register_devices(void)
         return board_register_devices();
 }
 
-arch_initcall(bcm63xx_register_devices);
+device_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c
index eb063e6dead9..3112df8f90db 100644
--- a/arch/mips/boot/compressed/uart-alchemy.c
+++ b/arch/mips/boot/compressed/uart-alchemy.c
@@ -2,6 +2,9 @@
 
 void putc(char c)
 {
-        /* all current (Jan. 2010) in-kernel boards */
+#ifdef CONFIG_MIPS_DB1300
+        alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
+#else
         alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+#endif
 }
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index cad555ebeca3..f9e275a50d98 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -86,10 +86,6 @@ config ARCH_SPARSEMEM_ENABLE
         def_bool y
         select SPARSEMEM_STATIC
 
-config CAVIUM_OCTEON_HELPER
-        def_bool y
-        depends on OCTEON_ETHERNET || PCI
-
 config IOMMU_HELPER
         bool
 
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index ea4febaa4bb1..b6bb92c16a47 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -61,6 +61,16 @@ static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
         return daddr;
 }
 
+static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        return octeon_hole_phys_to_dma(paddr);
+}
+
+static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        return octeon_hole_dma_to_phys(daddr);
+}
+
 static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
         if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
@@ -262,11 +272,11 @@ void __init plat_swiotlb_setup(void)
 
         for (i = 0 ; i < boot_mem_map.nr_map; i++) {
                 struct boot_mem_map_entry *e = &boot_mem_map.map[i];
-                if (e->type != BOOT_MEM_RAM)
+                if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM)
                         continue;
 
                 /* These addresses map low for PCI. */
-                if (e->addr > 0x410000000ull)
+                if (e->addr > 0x410000000ull && !OCTEON_IS_MODEL(OCTEON_CN6XXX))
                         continue;
 
                 addr_size += e->size;
@@ -296,6 +306,11 @@ void __init plat_swiotlb_setup(void)
                 swiotlbsize = 64 * (1<<20);
         }
 #endif
+#ifdef CONFIG_USB_OCTEON_OHCI
+        /* OCTEON II ohci is only 32-bit. */
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && max_addr >= 0x100000000ul)
+                swiotlbsize = 64 * (1<<20);
+#endif
         swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
         swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
         swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
@@ -330,6 +345,10 @@ struct dma_map_ops *octeon_pci_dma_map_ops;
 void __init octeon_pci_dma_init(void)
 {
         switch (octeon_dma_bar_type) {
+        case OCTEON_DMA_BAR_TYPE_PCIE2:
+                _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma;
+                _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys;
+                break;
         case OCTEON_DMA_BAR_TYPE_PCIE:
                 _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
                 _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
index 7f41c5be2190..b6d6e841a984 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -10,5 +10,10 @@
 #
 
 obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
+obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
+        cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
+        cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
+        cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
+        cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
 
-obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o
+obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/drivers/staging/octeon/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
index e9809d375162..132bccc66a93 100644
--- a/drivers/staging/octeon/cvmx-cmd-queue.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
@@ -34,13 +34,13 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
-#include "cvmx-fpa.h"
-#include "cvmx-cmd-queue.h"
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-cmd-queue.h>
 
 #include <asm/octeon/cvmx-npei-defs.h>
 #include <asm/octeon/cvmx-pexp-defs.h>
-#include "cvmx-pko-defs.h"
+#include <asm/octeon/cvmx-pko-defs.h>
 
 /**
  * This application uses this pointer to access the global queue
diff --git a/drivers/staging/octeon/cvmx-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-fpa.c
index ad44b8bd8057..ad44b8bd8057 100644
--- a/drivers/staging/octeon/cvmx-fpa.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-fpa.c
diff --git a/drivers/staging/octeon/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index 57d35dc63ddb..fd2015331a20 100644
--- a/drivers/staging/octeon/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -34,16 +34,16 @@
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/cvmx-bootinfo.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-mdio.h"
+#include <asm/octeon/cvmx-mdio.h>
 
-#include "cvmx-helper.h"
-#include "cvmx-helper-util.h"
-#include "cvmx-helper-board.h"
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-util.h>
+#include <asm/octeon/cvmx-helper-board.h>
 
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-asxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-asxx-defs.h>
 
 /**
  * cvmx_override_board_link_get(int ipd_port) is a function
@@ -117,6 +117,10 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
         case CVMX_BOARD_TYPE_EBH5200:
         case CVMX_BOARD_TYPE_EBH5201:
         case CVMX_BOARD_TYPE_EBT5200:
+                /* Board has 2 management ports */
+                if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
+                    (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
+                        return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
                 /*
                  * Board has 4 SGMII ports. The PHYs start right after the MII
                  * ports MII0 = 0, MII1 = 1, SGMII = 2-5.
@@ -128,6 +132,9 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
         case CVMX_BOARD_TYPE_EBH5600:
         case CVMX_BOARD_TYPE_EBH5601:
         case CVMX_BOARD_TYPE_EBH5610:
+                /* Board has 1 management port */
+                if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
+                        return 0;
                 /*
                  * Board has 8 SGMII ports. 4 connect out, two connect
                  * to a switch, and 2 loop to each other
@@ -147,6 +154,19 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
                         return ipd_port - 16 + 1;
                 else
                         return -1;
+        case CVMX_BOARD_TYPE_NIC_XLE_10G:
+        case CVMX_BOARD_TYPE_NIC10E:
+                return -1;
+        case CVMX_BOARD_TYPE_NIC4E:
+                if (ipd_port >= 0 && ipd_port <= 3)
+                        return (ipd_port + 0x1f) & 0x1f;
+                else
+                        return -1;
+        case CVMX_BOARD_TYPE_NIC2E:
+                if (ipd_port >= 0 && ipd_port <= 1)
+                        return ipd_port + 1;
+                else
+                        return -1;
         case CVMX_BOARD_TYPE_BBGW_REF:
                 /*
                  * No PHYs are connected to Octeon, everything is
@@ -493,7 +513,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr,
                 cvmx_mdio_phy_reg_control_t reg_control;
                 cvmx_mdio_phy_reg_status_t reg_status;
                 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
-                cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
                 cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
 
                 reg_status.u16 =
@@ -508,9 +527,6 @@ int cvmx_helper_board_link_set_phy(int phy_addr,
                 reg_autoneg_adver.s.advert_100base_tx_full = 0;
                 reg_autoneg_adver.s.advert_100base_tx_half = 0;
                 if (reg_status.s.capable_extended_status) {
-                        reg_extended_status.u16 =
-                            cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
-                                           CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
                         reg_control_1000.u16 =
                             cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
                                            CVMX_MDIO_PHY_REG_CONTROL_1000);
diff --git a/drivers/staging/octeon/cvmx-helper-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
index c239e5f4ab9a..c239e5f4ab9a 100644
--- a/drivers/staging/octeon/cvmx-helper-fpa.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
diff --git a/drivers/staging/octeon/cvmx-helper-loop.c b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c
index 55a571a69529..bfbd46115e71 100644
--- a/drivers/staging/octeon/cvmx-helper-loop.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c
@@ -31,10 +31,10 @@
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-helper.h"
-#include "cvmx-pip-defs.h"
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-pip-defs.h>
 
 /**
  * Probe a LOOP interface and determine the number of ports
diff --git a/drivers/staging/octeon/cvmx-helper-npi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
index 7388a1e72b38..cc94cfa545b4 100644
--- a/drivers/staging/octeon/cvmx-helper-npi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
@@ -31,11 +31,11 @@
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-pip-defs.h"
+#include <asm/octeon/cvmx-pip-defs.h>
 
 /**
  * Probe a NPI interface and determine the number of ports
diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
index aa2d5d7fee2b..82b21843421c 100644
--- a/drivers/staging/octeon/cvmx-helper-rgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
@@ -31,18 +31,18 @@
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
 
-#include "cvmx-mdio.h"
-#include "cvmx-pko.h"
-#include "cvmx-helper.h"
-#include "cvmx-helper-board.h"
+#include <asm/octeon/cvmx-mdio.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
 
 #include <asm/octeon/cvmx-npi-defs.h>
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-asxx-defs.h"
-#include "cvmx-dbg-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-asxx-defs.h>
+#include <asm/octeon/cvmx-dbg-defs.h>
 
 void __cvmx_interrupt_gmxx_enable(int interface);
 void __cvmx_interrupt_asxx_enable(int block);
@@ -326,6 +326,7 @@ int __cvmx_helper_rgmii_link_set(int ipd_port,
                        cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) &
                                      ~(1 << index));
 
+        memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save));
         /* Disable all queues so that TX should become idle */
         for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
                 int queue = cvmx_pko_get_base_queue(ipd_port) + i;
diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
index 6214e3b6d975..0c0bf5d30e70 100644
--- a/drivers/staging/octeon/cvmx-helper-sgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
@@ -32,14 +32,14 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-mdio.h"
-#include "cvmx-helper.h"
-#include "cvmx-helper-board.h"
+#include <asm/octeon/cvmx-mdio.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
 
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-pcsx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-pcsx-defs.h>
 
 void __cvmx_interrupt_gmxx_enable(int interface);
 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
@@ -326,6 +326,10 @@ static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
         return 0;
 }
 
+int __cvmx_helper_sgmii_enumerate(int interface)
+{
+        return 4;
+}
 /**
  * Probe a SGMII interface and determine the number of ports
  * connected to it. The SGMII interface should still be down after
@@ -347,7 +351,7 @@ int __cvmx_helper_sgmii_probe(int interface)
         mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
         mode.s.en = 1;
         cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
-        return 4;
+        return __cvmx_helper_sgmii_enumerate(interface);
 }
 
 /**
diff --git a/drivers/staging/octeon/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
index 8ba6c832471e..2830e4bdf7f3 100644
--- a/drivers/staging/octeon/cvmx-helper-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
@@ -35,12 +35,12 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index);
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
-#include "cvmx-spi.h"
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-spi.h>
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-pip-defs.h"
-#include "cvmx-pko-defs.h"
+#include <asm/octeon/cvmx-pip-defs.h>
+#include <asm/octeon/cvmx-pko-defs.h>
 
 /*
  * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI
@@ -51,6 +51,16 @@ void __cvmx_interrupt_stxx_int_msk_enable(int index);
 #define CVMX_HELPER_SPI_TIMEOUT 10
 #endif
 
+int __cvmx_helper_spi_enumerate(int interface)
+{
+        if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
+            cvmx_spi4000_is_present(interface)) {
+                return 10;
+        } else {
+                return 16;
+        }
+}
+
 /**
  * Probe a SPI interface and determine the number of ports
  * connected to it. The SPI interface should still be down after
diff --git a/drivers/staging/octeon/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
index 131182bf5abb..116dea17acf5 100644
--- a/drivers/staging/octeon/cvmx-helper-util.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
@@ -32,16 +32,16 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-fpa.h"
-#include "cvmx-pip.h"
-#include "cvmx-pko.h"
-#include "cvmx-ipd.h"
-#include "cvmx-spi.h"
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-ipd.h>
+#include <asm/octeon/cvmx-spi.h>
 
-#include "cvmx-helper.h"
-#include "cvmx-helper-util.h"
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-util.h>
 
 #include <asm/octeon/cvmx-ipd-defs.h>
 
diff --git a/drivers/staging/octeon/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
index a11e6769e234..1723248e987d 100644
--- a/drivers/staging/octeon/cvmx-helper-xaui.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
@@ -33,17 +33,30 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-pko-defs.h"
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-pcsxx-defs.h"
+#include <asm/octeon/cvmx-pko-defs.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-pcsxx-defs.h>
 
 void __cvmx_interrupt_gmxx_enable(int interface);
 void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
 void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
+
+int __cvmx_helper_xaui_enumerate(int interface)
+{
+        union cvmx_gmxx_hg2_control gmx_hg2_control;
+
+        /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
+        gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
+        if (gmx_hg2_control.s.hg2tx_en)
+                return 16;
+        else
+                return 1;
+}
+
 /**
  * Probe a XAUI interface and determine the number of ports
  * connected to it. The XAUI interface should still be down
@@ -56,7 +69,6 @@ void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
 int __cvmx_helper_xaui_probe(int interface)
 {
         int i;
-        union cvmx_gmxx_hg2_control gmx_hg2_control;
         union cvmx_gmxx_inf_mode mode;
 
         /*
@@ -90,13 +102,7 @@ int __cvmx_helper_xaui_probe(int interface)
                 pko_mem_port_ptrs.s.pid = interface * 16 + i;
                 cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
         }
-
-        /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
-        gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
-        if (gmx_hg2_control.s.hg2tx_en)
-                return 16;
-        else
-                return 1;
+        return __cvmx_helper_xaui_enumerate(interface);
 }
 
 /**
diff --git a/drivers/staging/octeon/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index e9c5c836ceff..fa4963856353 100644
--- a/drivers/staging/octeon/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -32,19 +32,19 @@
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-fpa.h"
-#include "cvmx-pip.h"
-#include "cvmx-pko.h"
-#include "cvmx-ipd.h"
-#include "cvmx-spi.h"
-#include "cvmx-helper.h"
-#include "cvmx-helper-board.h"
+#include <asm/octeon/cvmx-fpa.h>
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-ipd.h>
+#include <asm/octeon/cvmx-spi.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
 
-#include "cvmx-pip-defs.h"
-#include "cvmx-smix-defs.h"
-#include "cvmx-asxx-defs.h"
+#include <asm/octeon/cvmx-pip-defs.h>
+#include <asm/octeon/cvmx-smix-defs.h>
+#include <asm/octeon/cvmx-asxx-defs.h>
 
 /**
  * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
@@ -234,21 +234,16 @@ static int __cvmx_helper_port_setup_ipd(int ipd_port)
 }
 
 /**
- * This function probes an interface to determine the actual
- * number of hardware ports connected to it. It doesn't setup the
- * ports or enable them. The main goal here is to set the global
- * interface_port_count[interface] correctly. Hardware setup of the
- * ports will be performed later.
+ * This function sets the interface_port_count[interface] correctly,
+ * without modifying any hardware configuration.  Hardware setup of
+ * the ports will be performed later.
  *
  * @interface: Interface to probe
  *
  * Returns Zero on success, negative on failure
  */
-int cvmx_helper_interface_probe(int interface)
+int cvmx_helper_interface_enumerate(int interface)
 {
-        /* At this stage in the game we don't want packets to be moving yet.
-           The following probe calls should perform hardware setup
-           needed to determine port counts. Receive must still be disabled */
         switch (cvmx_helper_interface_get_mode(interface)) {
                 /* These types don't support ports to IPD/PKO */
         case CVMX_HELPER_INTERFACE_MODE_DISABLED:
@@ -258,7 +253,7 @@ int cvmx_helper_interface_probe(int interface)
                 /* XAUI is a single high speed port */
         case CVMX_HELPER_INTERFACE_MODE_XAUI:
                 interface_port_count[interface] =
-                    __cvmx_helper_xaui_probe(interface);
+                    __cvmx_helper_xaui_enumerate(interface);
                 break;
                 /*
                  * RGMII/GMII/MII are all treated about the same. Most
@@ -267,7 +262,7 @@ int cvmx_helper_interface_probe(int interface)
         case CVMX_HELPER_INTERFACE_MODE_RGMII:
         case CVMX_HELPER_INTERFACE_MODE_GMII:
                 interface_port_count[interface] =
-                    __cvmx_helper_rgmii_probe(interface);
+                    __cvmx_helper_rgmii_enumerate(interface);
                 break;
                 /*
                  * SPI4 can have 1-16 ports depending on the device at
@@ -275,7 +270,7 @@ int cvmx_helper_interface_probe(int interface)
                  */
         case CVMX_HELPER_INTERFACE_MODE_SPI:
                 interface_port_count[interface] =
-                    __cvmx_helper_spi_probe(interface);
+                    __cvmx_helper_spi_enumerate(interface);
                 break;
                 /*
                  * SGMII can have 1-4 ports depending on how many are
@@ -284,12 +279,12 @@ int cvmx_helper_interface_probe(int interface)
         case CVMX_HELPER_INTERFACE_MODE_SGMII:
         case CVMX_HELPER_INTERFACE_MODE_PICMG:
                 interface_port_count[interface] =
-                    __cvmx_helper_sgmii_probe(interface);
+                    __cvmx_helper_sgmii_enumerate(interface);
                 break;
                 /* PCI target Network Packet Interface */
         case CVMX_HELPER_INTERFACE_MODE_NPI:
                 interface_port_count[interface] =
-                    __cvmx_helper_npi_probe(interface);
+                    __cvmx_helper_npi_enumerate(interface);
                 break;
                 /*
                  * Special loopback only ports. These are not the same
@@ -297,7 +292,7 @@ int cvmx_helper_interface_probe(int interface)
                  */
         case CVMX_HELPER_INTERFACE_MODE_LOOP:
                 interface_port_count[interface] =
-                    __cvmx_helper_loop_probe(interface);
+                    __cvmx_helper_loop_enumerate(interface);
                 break;
         }
 
@@ -313,6 +308,74 @@ int cvmx_helper_interface_probe(int interface)
 }
 
 /**
+ * This function probes an interface to determine the actual
+ * number of hardware ports connected to it. It doesn't setup the
+ * ports or enable them. The main goal here is to set the global
+ * interface_port_count[interface] correctly. Hardware setup of the
+ * ports will be performed later.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Zero on success, negative on failure
+ */
+int cvmx_helper_interface_probe(int interface)
+{
+        cvmx_helper_interface_enumerate(interface);
+        /* At this stage in the game we don't want packets to be moving yet.
+           The following probe calls should perform hardware setup
+           needed to determine port counts. Receive must still be disabled */
+        switch (cvmx_helper_interface_get_mode(interface)) {
+                /* These types don't support ports to IPD/PKO */
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+                break;
+                /* XAUI is a single high speed port */
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                __cvmx_helper_xaui_probe(interface);
+                break;
+                /*
+                 * RGMII/GMII/MII are all treated about the same. Most
+                 * functions refer to these ports as RGMII.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+                __cvmx_helper_rgmii_probe(interface);
+                break;
+                /*
+                 * SPI4 can have 1-16 ports depending on the device at
+                 * the other end.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+                __cvmx_helper_spi_probe(interface);
+                break;
+                /*
+                 * SGMII can have 1-4 ports depending on how many are
+                 * hooked up.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                __cvmx_helper_sgmii_probe(interface);
+                break;
+                /* PCI target Network Packet Interface */
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+                __cvmx_helper_npi_probe(interface);
+                break;
+                /*
+                 * Special loopback only ports. These are not the same
+                 * as other ports in loopback mode.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                __cvmx_helper_loop_probe(interface);
+                break;
+        }
+
+        /* Make sure all global variables propagate to other cores */
+        CVMX_SYNCWS;
+
+        return 0;
+}
+
+/**
  * Setup the IPD/PIP for the ports on an interface. Packet
  * classification and tagging are set for every port on the
  * interface. The number of ports on the interface must already
@@ -548,7 +611,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
         union cvmx_gmxx_prtx_cfg gmx_cfg;
         int retry_cnt;
         int retry_loop_cnt;
-        int mtu;
         int i;
         cvmx_helper_link_info_t link_info;
 
@@ -662,10 +724,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
                 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
                                1 << INDEX(FIX_IPD_OUTPORT));
 
-                mtu =
-                    cvmx_read_csr(CVMX_GMXX_RXX_JABBER
-                                  (INDEX(FIX_IPD_OUTPORT),
-                                   INTERFACE(FIX_IPD_OUTPORT)));
                 cvmx_write_csr(CVMX_GMXX_RXX_JABBER
                                (INDEX(FIX_IPD_OUTPORT),
                                 INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
diff --git a/drivers/staging/octeon/cvmx-interrupt-decodes.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
index a3337e382ee9..e59d1b79f24c 100644
--- a/drivers/staging/octeon/cvmx-interrupt-decodes.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
@@ -34,11 +34,11 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-pcsx-defs.h"
-#include "cvmx-pcsxx-defs.h"
-#include "cvmx-spxx-defs.h"
-#include "cvmx-stxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-pcsx-defs.h>
+#include <asm/octeon/cvmx-pcsxx-defs.h>
+#include <asm/octeon/cvmx-spxx-defs.h>
+#include <asm/octeon/cvmx-stxx-defs.h>
 
 #ifndef PRINT_ERROR
 #define PRINT_ERROR(format, ...)
diff --git a/drivers/staging/octeon/cvmx-interrupt-rsl.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
index df50048cfbc0..bea7538ea4e9 100644
--- a/drivers/staging/octeon/cvmx-interrupt-rsl.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
@@ -32,8 +32,8 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-asxx-defs.h"
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-asxx-defs.h>
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 #ifndef PRINT_ERROR
 #define PRINT_ERROR(format, ...)
diff --git a/drivers/staging/octeon/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c
index 50a2c9bd5a55..f557084b1092 100644
--- a/drivers/staging/octeon/cvmx-pko.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c
@@ -31,9 +31,9 @@
 
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
-#include "cvmx-pko.h"
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-config.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-helper.h>
 
 /**
  * Internal state of packet output
@@ -54,7 +54,7 @@ void cvmx_pko_initialize_global(void)
         /*
          * Set the size of the PKO command buffers to an odd number of
          * 64bit words. This allows the normal two word send to stay
-         * aligned and never span a command word buffer.
+         * aligned and never span a comamnd word buffer.
          */
         config.u64 = 0;
         config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
diff --git a/drivers/staging/octeon/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c
index 82794d920cec..74afb1710cd9 100644
--- a/drivers/staging/octeon/cvmx-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c
@@ -31,14 +31,14 @@
  */
 #include <asm/octeon/octeon.h>
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
-#include "cvmx-pko.h"
-#include "cvmx-spi.h"
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-spi.h>
 
-#include "cvmx-spxx-defs.h"
-#include "cvmx-stxx-defs.h"
-#include "cvmx-srxx-defs.h"
+#include <asm/octeon/cvmx-spxx-defs.h>
+#include <asm/octeon/cvmx-stxx-defs.h>
+#include <asm/octeon/cvmx-srxx-defs.h>
 
 #define INVOKE_CB(function_p, args...)          \
         do {                                    \
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c
index c8d35684504e..f4c1b36fdf65 100644
--- a/arch/mips/cavium-octeon/executive/octeon-model.c
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -25,10 +25,6 @@
  * Contact Cavium Networks for more information
  ***********************license end**************************************/
 
-/*
- * File defining functions for working with different Octeon
- * models.
- */
 #include <asm/octeon/octeon.h>
 
 /**
@@ -69,11 +65,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
         char fuse_model[10];
         uint32_t fuse_data = 0;
 
-        fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
+        fus3.u64 = 0;
+        if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
+                fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
         fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
         fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
-
-        num_cores = cvmx_octeon_num_cores();
+        num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE));
 
         /* Make sure the non existent devices look disabled */
         switch ((chip_id >> 8) & 0xff) {
@@ -108,7 +105,7 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
          * Assume pass number is encoded using <5:3><2:0>. Exceptions
          * will be fixed later.
          */
-        sprintf(pass, "%u.%u", ((chip_id >> 3) & 7) + 1, chip_id & 7);
+        sprintf(pass, "%d.%d", (int)((chip_id >> 3) & 7) + 1, (int)chip_id & 7);
 
         /*
          * Use the number of cores to determine the last 2 digits of
@@ -116,6 +113,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
          * later.
          */
         switch (num_cores) {
+        case 32:
+                core_model = "80";
+                break;
+        case 24:
+                core_model = "70";
+                break;
         case 16:
                 core_model = "60";
                 break;
@@ -246,8 +249,8 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
                 break;
         case 3:         /* CN58XX */
                 family = "58";
-                /* Special case. 4 core, no crypto */
-                if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto)
+                /* Special case. 4 core, half cache (CP with half cache) */
+                if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2))
                         core_model = "29";
 
                 /* Pass 1 uses different encodings for pass numbers */
@@ -285,6 +288,9 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
                                 suffix = "NSP";
                                 if (fus_dat3.s.nozip)
                                         suffix = "SCP";
+
+                                if (fus_dat3.s.bar2_en)
+                                        suffix = "NSPB2";
                         }
                         if (fus3.cn56xx.crip_1024k)
                                 family = "54";
@@ -301,6 +307,60 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
                 else
                         family = "52";
                 break;
+        case 0x93:              /* CN61XX */
+                family = "61";
+                if (fus_dat2.cn61xx.nocrypto && fus_dat2.cn61xx.dorm_crypto)
+                        suffix = "AP";
+                if (fus_dat2.cn61xx.nocrypto)
+                        suffix = "CP";
+                else if (fus_dat2.cn61xx.dorm_crypto)
+                        suffix = "DAP";
+                else if (fus_dat3.cn61xx.nozip)
+                        suffix = "SCP";
+                break;
+        case 0x90:              /* CN63XX */
+                family = "63";
+                if (fus_dat3.s.l2c_crip == 2)
+                        family = "62";
+                if (num_cores == 6)     /* Other core counts match generic */
+                        core_model = "35";
+                if (fus_dat2.cn63xx.nocrypto)
+                        suffix = "CP";
+                else if (fus_dat2.cn63xx.dorm_crypto)
+                        suffix = "DAP";
+                else if (fus_dat3.cn63xx.nozip)
+                        suffix = "SCP";
+                else
+                        suffix = "AAP";
+                break;
+        case 0x92:              /* CN66XX */
+                family = "66";
+                if (num_cores == 6)     /* Other core counts match generic */
+                        core_model = "35";
+                if (fus_dat2.cn66xx.nocrypto && fus_dat2.cn66xx.dorm_crypto)
+                        suffix = "AP";
+                if (fus_dat2.cn66xx.nocrypto)
+                        suffix = "CP";
+                else if (fus_dat2.cn66xx.dorm_crypto)
+                        suffix = "DAP";
+                else if (fus_dat3.cn66xx.nozip)
+                        suffix = "SCP";
+                else
+                        suffix = "AAP";
+                break;
+        case 0x91:              /* CN68XX */
+                family = "68";
+                if (fus_dat2.cn68xx.nocrypto && fus_dat3.cn68xx.nozip)
+                        suffix = "CP";
+                else if (fus_dat2.cn68xx.dorm_crypto)
+                        suffix = "DAP";
+                else if (fus_dat3.cn68xx.nozip)
+                        suffix = "SCP";
+                else if (fus_dat2.cn68xx.nocrypto)
+                        suffix = "SP";
+                else
+                        suffix = "AAP";
+                break;
         default:
                 family = "XX";
                 core_model = "XX";
@@ -310,49 +370,40 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
         }
 
         clock_mhz = octeon_get_clock_rate() / 1000000;
-
         if (family[0] != '3') {
+                int fuse_base = 384 / 8;
+                if (family[0] == '6')
+                        fuse_base = 832 / 8;
+
                 /* Check for model in fuses, overrides normal decode */
                 /* This is _not_ valid for Octeon CN3XXX models */
-                fuse_data |= cvmx_fuse_read_byte(51);
+                fuse_data |= cvmx_fuse_read_byte(fuse_base + 3);
                 fuse_data = fuse_data << 8;
-                fuse_data |= cvmx_fuse_read_byte(50);
+                fuse_data |= cvmx_fuse_read_byte(fuse_base + 2);
                 fuse_data = fuse_data << 8;
-                fuse_data |= cvmx_fuse_read_byte(49);
+                fuse_data |= cvmx_fuse_read_byte(fuse_base + 1);
                 fuse_data = fuse_data << 8;
-                fuse_data |= cvmx_fuse_read_byte(48);
+                fuse_data |= cvmx_fuse_read_byte(fuse_base);
                 if (fuse_data & 0x7ffff) {
                         int model = fuse_data & 0x3fff;
                         int suffix = (fuse_data >> 14) & 0x1f;
                         if (suffix && model) {
-                                /*
-                                 * Have both number and suffix in
-                                 * fuses, so both
-                                 */
-                                sprintf(fuse_model, "%d%c",
-                                        model, 'A' + suffix - 1);
+                                /* Have both number and suffix in fuses, so both */
+                                sprintf(fuse_model, "%d%c", model, 'A' + suffix - 1);
                                 core_model = "";
                                 family = fuse_model;
                         } else if (suffix && !model) {
-                                /*
-                                 * Only have suffix, so add suffix to
-                                 * 'normal' model number.
-                                 */
-                                sprintf(fuse_model, "%s%c", core_model,
-                                        'A' + suffix - 1);
+                                /* Only have suffix, so add suffix to 'normal' model number */
+                                sprintf(fuse_model, "%s%c", core_model, 'A' + suffix - 1);
                                 core_model = fuse_model;
                         } else {
-                                /*
-                                 * Don't have suffix, so just use
-                                 * model from fuses.
-                                 */
+                                /* Don't have suffix, so just use model from fuses */
                                 sprintf(fuse_model, "%d", model);
                                 core_model = "";
                                 family = fuse_model;
                         }
                 }
         }
-        sprintf(buffer, "CN%s%sp%s-%d-%s",
-                family, core_model, pass, clock_mhz, suffix);
+        sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz, suffix);
         return buffer;
 }
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 2d9028f1474c..260b27367347 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -642,14 +642,6 @@ void __init plat_mem_setup(void)
 
         total = 0;
 
-        /* First add the init memory we will be returning.  */
-        memory = __pa_symbol(&__init_begin) & PAGE_MASK;
-        mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory;
-        if (mem_alloc_size > 0) {
-                add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
-                total += mem_alloc_size;
-        }
-
         /*
          * The Mips memory init uses the first memory location for
          * some memory vectors. When SPARSEMEM is in use, it doesn't
@@ -767,11 +759,11 @@ void prom_free_prom_memory(void)
                         : "=r" (insn) : : "$31", "memory");
 
                 if ((insn >> 26) != 0x33)
-                        panic("No PREF instruction at Core-14449 probe point.\n");
+                        panic("No PREF instruction at Core-14449 probe point.");
 
                 if (((insn >> 16) & 0x1f) != 28)
                         panic("Core-14449 WAR not in place (%04x).\n"
-                              "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);
+                              "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
         }
 #ifdef CONFIG_CAVIUM_DECODE_RSL
         cvmx_interrupt_rsl_enable();
@@ -779,7 +771,7 @@ void prom_free_prom_memory(void)
         /* Add an interrupt handler for general failures. */
         if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
                         "RML/RSL", octeon_rlm_interrupt)) {
-                panic("Unable to request_irq(OCTEON_IRQ_RML)\n");
+                panic("Unable to request_irq(OCTEON_IRQ_RML)");
         }
 #endif
 }
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index efcfff4d4627..b1535fe409d4 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -210,7 +210,7 @@ void octeon_prepare_cpus(unsigned int max_cpus)
         if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
                         IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
                         mailbox_interrupt)) {
-                panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
+                panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
         }
 }
 
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 4044c9e0fb73..17a36c125172 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -1,118 +1,359 @@
+CONFIG_MIPS=y
 CONFIG_MIPS_ALCHEMY=y
+CONFIG_MIPS_DB1000=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_HZ_100=y
-# CONFIG_SECCOMP is not set
+CONFIG_HZ=100
+CONFIG_PREEMPT_NONE=y
 CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="-db1000"
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION="-db1x00"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_KERNEL_LZMA=y
+CONFIG_DEFAULT_HOSTNAME="db1x00"
+CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_FHANDLE=y
+CONFIG_AUDIT=y
 CONFIG_TINY_RCU=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_SYSCTL=y
 CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_PCSPKR_PLATFORM is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PCI_QUIRKS=y
 CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
+CONFIG_SLABINFO=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_FREEZER=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
 CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
 CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
-CONFIG_PM=y
+CONFIG_BINFMT_ELF=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
 CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
+CONFIG_XFRM=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_NET_IPIP=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_LRO=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_STP=y
+CONFIG_GARP=y
+CONFIG_BRIDGE=y
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_VLAN_8021Q=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_LLC=y
+CONFIG_LLC2=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HCIBTUSB=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_I4=y
+CONFIG_MTD_CFI_I8=y
+CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_PHYSMAP=y
-# CONFIG_MISC_DEVICES is not set
+CONFIG_SCSI_MOD=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_PROC_FS=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_ATA=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATA_SFF=y
+CONFIG_ATA_BMDMA=y
+CONFIG_PATA_HPT37X=y
+CONFIG_PATA_PCMCIA=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_FIREWIRE=y
+CONFIG_FIREWIRE_OHCI=y
+CONFIG_FIREWIRE_OHCI_DEBUG=y
+CONFIG_FIREWIRE_NET=y
 CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_REALTEK_PHY=y
-CONFIG_NATIONAL_PHY=y
-CONFIG_STE10XP=y
-CONFIG_LSI_ET1011C_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+CONFIG_PHYLIB=y
+CONFIG_NET_ETHERNET=y
 CONFIG_MIPS_AU1X00_ENET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_NET_PCMCIA=y
+CONFIG_PCMCIA_3C589=y
+CONFIG_PCMCIA_PCNET=y
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPPOE=y
+CONFIG_INPUT=y
 CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+CONFIG_DEVKMEM=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_TTY_PRINTK=y
+CONFIG_DEVPORT=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_FB=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_AU1100=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x16=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_HRTIMER=y
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AU1XAUDIO=y
+CONFIG_SND_SOC_AU1XAC97C=y
+CONFIG_SND_SOC_DB1000=y
+CONFIG_SND_SOC_AC97_CODEC=y
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+CONFIG_USB_HID=y
+CONFIG_USB_SUPPORT=y
 CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_DYNAMIC_MINORS=y
 CONFIG_USB_SUSPEND=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
 CONFIG_RTC_DRV_AU1XXX=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-# CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT23=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_GENERIC_ACL=y
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
 CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_JFFS2_CMODE_PRIORITY=y
 CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_PNFS_FILE_LAYOUT=y
+CONFIG_PNFS_BLOCK=y
 CONFIG_ROOT_NFS=y
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFS_USE_NEW_IDMAPPER=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_FTRACE is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="noirqdebug rootwait root=/dev/sda1 rootfstype=ext4 console=ttyS0,115200 video=au1100fb:panel:CRT_800x600_16"
 CONFIG_DEBUG_ZBOOT=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITYFS=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
deleted file mode 100644
index c6b49938ee84..000000000000
--- a/arch/mips/configs/db1100_defconfig
+++ /dev/null
@@ -1,122 +0,0 @@
-CONFIG_MIPS_ALCHEMY=y
-CONFIG_MIPS_DB1100=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_HZ_100=y
-# CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="-db1100"
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_TINY_RCU=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_KALLSYMS is not set
-# CONFIG_PCSPKR_PLATFORM is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_IDE=y
-CONFIG_IDE_TASK_IOCTL=y
-CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_REALTEK_PHY=y
-CONFIG_NATIONAL_PHY=y
-CONFIG_STE10XP=y
-CONFIG_LSI_ET1011C_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MIPS_AU1X00_ENET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_AU1100=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x16=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_SUSPEND=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AU1XXX=y
-CONFIG_EXT2_FS=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_SQUASHFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_ZBOOT=y
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig
new file mode 100644
index 000000000000..c38b190151c4
--- /dev/null
+++ b/arch/mips/configs/db1300_defconfig
@@ -0,0 +1,391 @@
+CONFIG_MIPS=y
+CONFIG_MIPS_ALCHEMY=y
+CONFIG_ALCHEMY_GPIOINT_AU1300=y
+CONFIG_MIPS_DB1300=y
+CONFIG_SOC_AU1300=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
+CONFIG_DMA_COHERENT=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_CPU_MIPS32_R1=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_32BIT=y
+CONFIG_PAGE_SIZE_4KB=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HZ_100=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=100
+CONFIG_PREEMPT_NONE=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION="-db1300"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_LZMA=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_FHANDLE=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_TINY_RCU=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_SLAB=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_INLINE_SPIN_UNLOCK=y
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_MMU=y
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+CONFIG_BINFMT_ELF=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_TRAD_SIGNALS=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_INET_TUNNEL=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_BLK_DEV=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_UB=y
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_IDE_TASK_IOCTL=y
+CONFIG_IDE_PROC_FS=y
+CONFIG_BLK_DEV_PLATFORM=y
+CONFIG_SCSI_MOD=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+CONFIG_SMSC_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMSC911X=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_WM97XX=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_SMBUS=y
+CONFIG_I2C_AU1550=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_AU1550=y
+CONFIG_SPI_BITBANG=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_HWMON=y
+CONFIG_HWMON_VID=y
+CONFIG_SENSORS_ADM1025=y
+CONFIG_FB=y
+CONFIG_FB_AU1200=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_FONT_ACORN_8x8=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_HRTIMER=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_CACHE_LZO=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AU1XPSC=y
+CONFIG_SND_SOC_AU1XPSC_I2S=y
+CONFIG_SND_SOC_AU1XPSC_AC97=y
+CONFIG_SND_SOC_DB1300=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_WM8731=y
+CONFIG_SND_SOC_WM9712=y
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+CONFIG_USB_HID=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_AU1XXX=y
+CONFIG_EXT2_FS=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_GENERIC_ACL=y
+CONFIG_FAT_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_JFFS2_CMODE_PRIORITY=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="video=au1200fb:panel:bs console=tty console=ttyS2,115200"
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+CONFIG_BITREVERSE=y
+CONFIG_CRC32=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
deleted file mode 100644
index b6e21c7cb6bd..000000000000
--- a/arch/mips/configs/db1500_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
-CONFIG_MIPS_ALCHEMY=y
-CONFIG_MIPS_DB1500=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_HZ_100=y
-# CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="-db1500"
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_PCSPKR_PLATFORM is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PCI=y
-CONFIG_PCCARD=y
-# CONFIG_CARDBUS is not set
-CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=y
-# CONFIG_IDEPCI_PCIBUS_ORDER is not set
-CONFIG_BLK_DEV_HPT366=y
-CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_REALTEK_PHY=y
-CONFIG_NATIONAL_PHY=y
-CONFIG_STE10XP=y
-CONFIG_LSI_ET1011C_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MIPS_AU1X00_ENET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_SERIAL_8250_PCI is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_ARB is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_SUSPEND=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AU1XXX=y
-CONFIG_EXT2_FS=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_SQUASHFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_1250=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_ZBOOT=y
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 798a553c9e80..36cda27725e7 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -1,145 +1,262 @@
+CONFIG_MIPS=y
 CONFIG_MIPS_ALCHEMY=y
 CONFIG_MIPS_DB1550=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_HZ_100=y
-# CONFIG_SECCOMP is not set
+CONFIG_HZ=100
 CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION="-db1550"
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_KERNEL_LZMA=y
+CONFIG_DEFAULT_HOSTNAME="db1550"
+CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_FHANDLE=y
+CONFIG_AUDIT=y
 CONFIG_TINY_RCU=y
-CONFIG_LOG_BUF_SHIFT=14
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_KALLSYMS is not set
-# CONFIG_PCSPKR_PLATFORM is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+CONFIG_PCI_QUIRKS=y
 CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_IOSCHED_NOOP=y
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
 CONFIG_PCI=y
 CONFIG_PCCARD=y
-# CONFIG_CARDBUS is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
 CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
-CONFIG_PM=y
+CONFIG_BINFMT_ELF=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_BINFMT_MISC=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
 CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
+CONFIG_XFRM=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_LRO=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_IPV6=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_AU1550=y
-CONFIG_BLK_DEV_UB=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=y
-CONFIG_BLK_DEV_IDECD=y
-# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set
-CONFIG_IDE_TASK_IOCTL=y
-# CONFIG_IDEPCI_PCIBUS_ORDER is not set
-CONFIG_BLK_DEV_HPT366=y
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI_MOD=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_ATA=y
+CONFIG_ATA_SFF=y
+CONFIG_ATA_BMDMA=y
+CONFIG_PATA_HPT37X=y
+CONFIG_PATA_PCMCIA=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
 CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_REALTEK_PHY=y
-CONFIG_NATIONAL_PHY=y
-CONFIG_STE10XP=y
-CONFIG_LSI_ET1011C_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+CONFIG_PHYLIB=y
+CONFIG_NET_ETHERNET=y
 CONFIG_MIPS_AU1X00_ENET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_NET_PCMCIA=y
+CONFIG_PCMCIA_3C589=y
+CONFIG_PCMCIA_PCNET=y
+CONFIG_INPUT=y
 CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+CONFIG_DEVKMEM=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_DEVPORT=y
 CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
 CONFIG_I2C_AU1550=y
 CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
 CONFIG_SPI_AU1550=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_ARB is not set
-# CONFIG_VGA_CONSOLE is not set
+CONFIG_SPI_BITBANG=y
+CONFIG_HWMON=y
+CONFIG_SENSORS_ADM1025=y
+CONFIG_SENSORS_LM70=y
+CONFIG_DUMMY_CONSOLE=y
 CONFIG_SOUND=y
 CONFIG_SND=y
-CONFIG_SND_HRTIMER=y
-CONFIG_SND_DYNAMIC_MINORS=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_PCI is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_MIPS is not set
-# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
 CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
 CONFIG_SND_SOC_AU1XPSC=y
-# CONFIG_HID_SUPPORT is not set
+CONFIG_SND_SOC_AU1XPSC_I2S=y
+CONFIG_SND_SOC_AU1XPSC_AC97=y
+CONFIG_SND_SOC_DB1200=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_AC97_CODEC=y
+CONFIG_SND_SOC_WM8731=y
+CONFIG_SND_SOC_WM9712=y
+CONFIG_AC97_BUS=y
 CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_SUSPEND=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
 CONFIG_RTC_DRV_AU1XXX=y
-CONFIG_EXT2_FS=y
-# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT23=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_JBD2=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 CONFIG_CONFIGFS_FS=y
+CONFIG_MISC_FILESYSTEMS=y
 CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
 CONFIG_JFFS2_SUMMARY=y
 CONFIG_JFFS2_FS_XATTR=y
-# CONFIG_JFFS2_FS_POSIX_ACL is not set
-# CONFIG_JFFS2_FS_SECURITY is not set
 CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
 CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
 CONFIG_JFFS2_RUBIN=y
+CONFIG_JFFS2_CMODE_PRIORITY=y
 CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_PNFS_FILE_LAYOUT=y
+CONFIG_PNFS_BLOCK=y
 CONFIG_ROOT_NFS=y
+CONFIG_NFS_USE_KERNEL_DNS=y
+CONFIG_NFS_USE_NEW_IDMAPPER=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUNRPC_BACKCHANNEL=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_CODEPAGE_852=y
@@ -148,10 +265,21 @@ CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_ZBOOT=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_FRAME_WARN=1024
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="noirqdebug console=ttyS0,115200 root=/dev/sda1 rootfstype=ext4"
 CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
 CONFIG_SECURITYFS=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_BITREVERSE=y
+CONFIG_CRC16=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_BCH=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig
new file mode 100644
index 000000000000..4479fd669ac1
--- /dev/null
+++ b/arch/mips/configs/nlm_xlp_defconfig
@@ -0,0 +1,570 @@
+CONFIG_NLM_XLP_BOARD=y
+CONFIG_64BIT=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_SMP=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+# CONFIG_SECCOMP is not set
+CONFIG_USE_OF=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_CROSS_COMPILE="mips-linux-gnu-"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+CONFIG_CGROUPS=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlp"
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_INITRAMFS_COMPRESSION_LZMA=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLK_DEV_INTEGRITY=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_MISC=y
+CONFIG_MIPS32_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_NET_IPIP=m
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_NETLABEL=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+CONFIG_IP_VS_FTP=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_SECURITY=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_SECURITY=m
+CONFIG_DECNET_NF_GRABULATOR=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_IP_DCCP=m
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_TIPC=m
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_DECNET=m
+CONFIG_LLC2=m
+CONFIG_IPX=m
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_IPDDP_DECAP=y
+CONFIG_X25=m
+CONFIG_LAPB=m
+CONFIG_ECONET=m
+CONFIG_ECONET_AUNUDP=y
+CONFIG_ECONET_NATIVE=y
+CONFIG_WAN_ROUTER=m
+CONFIG_PHONET=m
+CONFIG_IEEE802154=m
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_DCB=y
+CONFIG_NET_PKTGEN=m
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_CONNECTOR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_OSD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_CDROM_PKTCDVD=y
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=m
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_TGT_ATTRS=y
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_ISCSI_TCP=m
+CONFIG_LIBFCOE=m
+CONFIG_SCSI_DEBUG=m
+CONFIG_SCSI_DH=y
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DH_HP_SW=m
+CONFIG_SCSI_DH_EMC=m
+CONFIG_SCSI_DH_ALUA=m
+CONFIG_SCSI_OSD_INITIATOR=m
+CONFIG_SCSI_OSD_ULD=m
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+CONFIG_LEGACY_PTY_COUNT=0
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_N_HDLC=m
+# CONFIG_DEVKMEM is not set
+CONFIG_STALDRV=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=48
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+CONFIG_RAW_DRIVER=m
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_UIO=y
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
+CONFIG_OCFS2_FS=m
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_NILFS2_FS=m
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_QFMT_V1=m
+CONFIG_QFMT_V2=m
+CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=m
+CONFIG_FSCACHE=m
+CONFIG_FSCACHE_STATS=y
+CONFIG_FSCACHE_HISTOGRAM=y
+CONFIG_CACHEFILES=m
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_NTFS_FS=m
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_ADFS_FS=m
+CONFIG_AFFS_FS=m
+CONFIG_ECRYPT_FS=y
+CONFIG_HFS_FS=m
+CONFIG_HFSPLUS_FS=m
+CONFIG_BEFS_FS=m
+CONFIG_BFS_FS=m
+CONFIG_EFS_FS=m
+CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=m
+CONFIG_VXFS_FS=m
+CONFIG_MINIX_FS=m
+CONFIG_OMFS_FS=m
+CONFIG_HPFS_FS=m
+CONFIG_QNX4FS_FS=m
+CONFIG_ROMFS_FS=m
+CONFIG_SYSV_FS=m
+CONFIG_UFS_FS=m
+CONFIG_EXOFS_FS=m
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_FSCACHE=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_CIFS=m
+CONFIG_CIFS_WEAK_PW_HASH=y
+CONFIG_CIFS_UPCALL=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_CIFS_DFS_UPCALL=y
+CONFIG_NCP_FS=m
+CONFIG_NCPFS_PACKET_SIGNING=y
+CONFIG_NCPFS_IOCTL_LOCKING=y
+CONFIG_NCPFS_STRONG=y
+CONFIG_NCPFS_NFS_NS=y
+CONFIG_NCPFS_OS2_NS=y
+CONFIG_NCPFS_NLS=y
+CONFIG_NCPFS_EXTRAS=y
+CONFIG_CODA_FS=m
+CONFIG_AFS_FS=m
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ACORN_PARTITION=y
+CONFIG_ACORN_PARTITION_ICS=y
+CONFIG_ACORN_PARTITION_RISCIX=y
+CONFIG_OSF_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
+CONFIG_ATARI_PARTITION=y
+CONFIG_MAC_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_SGI_PARTITION=y
+CONFIG_ULTRIX_PARTITION=y
+CONFIG_SUN_PARTITION=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SYSV68_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_SCHED_TRACER=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_KGDB=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_LSM_MMAP_MIN_ADDR=0
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
+CONFIG_SECURITY_SELINUX_DISABLE=y
+CONFIG_SECURITY_SMACK=y
+CONFIG_SECURITY_TOMOYO=y
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=m
+CONFIG_CRC_CCITT=m
+CONFIG_CRC7=m
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
index e4b399fdaa61..7c68666fdd64 100644
--- a/arch/mips/configs/nlm_xlr_defconfig
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -8,7 +8,7 @@ CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_KEXEC=y
 CONFIG_EXPERIMENTAL=y
-CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-"
+CONFIG_CROSS_COMPILE="mips-linux-gnu-"
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -22,15 +22,13 @@ CONFIG_AUDIT=y
 CONFIG_NAMESPACES=y
 CONFIG_SCHED_AUTOGROUP=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs"
+CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlr"
 CONFIG_RD_BZIP2=y
 CONFIG_RD_LZMA=y
 CONFIG_INITRAMFS_COMPRESSION_GZIP=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
 CONFIG_KALLSYMS_ALL=y
 # CONFIG_ELF_CORE is not set
-# CONFIG_PCSPKR_PLATFORM is not set
 # CONFIG_PERF_EVENTS is not set
 # CONFIG_COMPAT_BRK is not set
 CONFIG_PROFILING=y
@@ -39,6 +37,9 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_DEBUG=y
 CONFIG_BINFMT_MISC=m
 CONFIG_PM_RUNTIME=y
 CONFIG_PM_DEBUG=y
@@ -297,12 +298,10 @@ CONFIG_NET_ACT_SIMP=m
 CONFIG_NET_ACT_SKBEDIT=m
 CONFIG_DCB=y
 CONFIG_NET_PKTGEN=m
-# CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 CONFIG_CONNECTOR=y
-CONFIG_MTD=m
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_NBD=m
@@ -339,6 +338,9 @@ CONFIG_SCSI_DH_EMC=m
 CONFIG_SCSI_DH_ALUA=m
 CONFIG_SCSI_OSD_INITIATOR=m
 CONFIG_SCSI_OSD_ULD=m
+CONFIG_NETDEVICES=y
+CONFIG_E1000E=y
+CONFIG_SKY2=y
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_EVBUG=m
@@ -443,7 +445,6 @@ CONFIG_CIFS_UPCALL=y
 CONFIG_CIFS_XATTR=y
 CONFIG_CIFS_POSIX=y
 CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_EXPERIMENTAL=y
 CONFIG_NCP_FS=m
 CONFIG_NCPFS_PACKET_SIGNING=y
 CONFIG_NCPFS_IOCTL_LOCKING=y
@@ -516,7 +517,6 @@ CONFIG_PRINTK_TIME=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_UNUSED_SYMBOLS=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig
deleted file mode 100644
index dcbe2704e5ed..000000000000
--- a/arch/mips/configs/pb1200_defconfig
+++ /dev/null
@@ -1,170 +0,0 @@
-CONFIG_MIPS_ALCHEMY=y
-CONFIG_MIPS_PB1200=y
-CONFIG_KSM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_HZ_100=y
-# CONFIG_SECCOMP is not set
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="-pb1200"
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_TINY_RCU=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_KALLSYMS is not set
-# CONFIG_PCSPKR_PLATFORM is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PCCARD=y
-CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_UB=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=y
-CONFIG_BLK_DEV_IDECD=y
-CONFIG_IDE_TASK_IOCTL=y
-# CONFIG_IDE_PROC_FS is not set
-CONFIG_BLK_DEV_IDE_AU1XXX=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=2
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_AU1550=y
-CONFIG_SPI=y
-CONFIG_SPI_AU1550=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_SENSORS_ADM1025=y
-CONFIG_SENSORS_LM70=y
-CONFIG_FB=y
-CONFIG_FB_AU1200=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x16=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_DYNAMIC_MINORS=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_MIPS is not set
-# CONFIG_SND_USB is not set
-# CONFIG_SND_PCMCIA is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_AU1XPSC=y
-CONFIG_SND_SOC_DB1200=y
-CONFIG_HIDRAW=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_AU1X=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AU1XXX=y
-CONFIG_EXT2_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=y
-CONFIG_VFAT_FS=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_SQUASHFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_CODEPAGE_1250=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_FTRACE is not set
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=ttyS0,115200"
-CONFIG_DEBUG_ZBOOT=y
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_SECURITYFS=y
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index f7b7ba6d5c45..b874accd878a 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -110,7 +110,6 @@ static struct irqaction fpuirq = {
 };
 
 static struct irqaction busirq = {
-        .flags = IRQF_DISABLED,
         .name = "bus error",
         .flags = IRQF_NO_THREAD,
 };
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
new file mode 100644
index 000000000000..552a65a0cf2b
--- /dev/null
+++ b/arch/mips/include/asm/bmips.h
@@ -0,0 +1,110 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
+ *
+ * Definitions for BMIPS processors
+ */
+#ifndef _ASM_BMIPS_H
+#define _ASM_BMIPS_H
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <asm/addrspace.h>
+#include <asm/mipsregs.h>
+#include <asm/hazards.h>
+
+/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
+#define BMIPS_GET_CBR()                 ((void __iomem *)(CKSEG1 | \
+                                         (unsigned long) \
+                                         ((read_c0_brcm_cbr() >> 18) << 18)))
+
+#define BMIPS_RAC_CONFIG                0x00000000
+#define BMIPS_RAC_ADDRESS_RANGE         0x00000004
+#define BMIPS_RAC_CONFIG_1              0x00000008
+#define BMIPS_L2_CONFIG                 0x0000000c
+#define BMIPS_LMB_CONTROL               0x0000001c
+#define BMIPS_SYSTEM_BASE               0x00000020
+#define BMIPS_PERF_GLOBAL_CONTROL       0x00020000
+#define BMIPS_PERF_CONTROL_0            0x00020004
+#define BMIPS_PERF_CONTROL_1            0x00020008
+#define BMIPS_PERF_COUNTER_0            0x00020010
+#define BMIPS_PERF_COUNTER_1            0x00020014
+#define BMIPS_PERF_COUNTER_2            0x00020018
+#define BMIPS_PERF_COUNTER_3            0x0002001c
+#define BMIPS_RELO_VECTOR_CONTROL_0     0x00030000
+#define BMIPS_RELO_VECTOR_CONTROL_1     0x00038000
+
+#define BMIPS_NMI_RESET_VEC             0x80000000
+#define BMIPS_WARM_RESTART_VEC          0x80000380
+
+#define ZSCM_REG_BASE                   0x97000000
+
+#if !defined(__ASSEMBLY__)
+
+#include <linux/cpumask.h>
+#include <asm/r4kcache.h>
+
+extern struct plat_smp_ops bmips_smp_ops;
+extern char bmips_reset_nmi_vec;
+extern char bmips_reset_nmi_vec_end;
+extern char bmips_smp_movevec;
+extern char bmips_smp_int_vec;
+extern char bmips_smp_int_vec_end;
+
+extern int bmips_smp_enabled;
+extern int bmips_cpu_offset;
+extern cpumask_t bmips_booted_mask;
+
+extern void bmips_ebase_setup(void);
+extern asmlinkage void plat_wired_tlb_setup(void);
+
+static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
+{
+        unsigned long ret;
+
+        __asm__ __volatile__(
+                ".set push\n"
+                ".set noreorder\n"
+                "cache %1, 0(%2)\n"
+                "sync\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "mfc0 %0, $28, 3\n"
+                "_ssnop\n"
+                ".set pop\n"
+                : "=&r" (ret)
+                : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
+                : "memory");
+        return ret;
+}
+
+static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
+{
+        __asm__ __volatile__(
+                ".set push\n"
+                ".set noreorder\n"
+                "mtc0 %0, $28, 3\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "cache %1, 0(%2)\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                "_ssnop\n"
+                : /* no outputs */
+                : "r" (data),
+                  "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
+                : "memory");
+}
+
+#endif /* !defined(__ASSEMBLY__) */
+
+#endif /* _ASM_BMIPS_H */
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 35cd1bab69c3..7a51d879e6ca 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -86,6 +86,7 @@ extern unsigned long mips_machtype;
 #define BOOT_MEM_RAM            1
 #define BOOT_MEM_ROM_DATA       2
 #define BOOT_MEM_RESERVED       3
+#define BOOT_MEM_INIT_RAM       4
 
 /*
  * A memory map that's built upon what was determined
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index 37c6857c8d4a..888766ae1f85 100644
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -9,6 +9,7 @@
 #define _ASM_BRANCH_H
 
 #include <asm/ptrace.h>
+#include <asm/inst.h>
 
 static inline int delay_slot(struct pt_regs *regs)
 {
@@ -23,7 +24,11 @@ static inline unsigned long exception_epc(struct pt_regs *regs)
         return regs->cp0_epc + 4;
 }
 
+#define BRANCH_LIKELY_TAKEN 0x0001
+
 extern int __compute_return_epc(struct pt_regs *regs);
+extern int __compute_return_epc_for_insn(struct pt_regs *regs,
+                                         union mips_instruction insn);
 
 static inline int compute_return_epc(struct pt_regs *regs)
 {
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 2f7f41873f24..f9fa2a479dd0 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -169,6 +169,10 @@
 #define PRID_IMP_NETLOGIC_XLS412B       0x4c00
 #define PRID_IMP_NETLOGIC_XLS408B       0x4e00
 #define PRID_IMP_NETLOGIC_XLS404B       0x4f00
+#define PRID_IMP_NETLOGIC_AU13XX        0x8000
+
+#define PRID_IMP_NETLOGIC_XLP8XX        0x1000
+#define PRID_IMP_NETLOGIC_XLP3XX        0x1100
 
 /*
  * Definitions for 7:0 on legacy processors
@@ -263,7 +267,7 @@ enum cpu_type_enum {
          */
         CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
         CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
-        CPU_XLR,
+        CPU_XLR, CPU_XLP,
 
         CPU_LAST
 };
diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h
new file mode 100644
index 000000000000..5437c84664bf
--- /dev/null
+++ b/arch/mips/include/asm/gio_device.h
@@ -0,0 +1,56 @@
+#include <linux/device.h>
+#include <linux/mod_devicetable.h>
+
+struct gio_device_id {
+        __u8 id;
+};
+
+struct gio_device {
+        struct device   dev;
+        struct resource resource;
+        unsigned int    irq;
+        unsigned int    slotno;
+
+        const char      *name;
+        struct gio_device_id id;
+        unsigned        id32:1;
+        unsigned        gio64:1;
+};
+#define to_gio_device(d) container_of(d, struct gio_device, dev)
+
+struct gio_driver {
+        const char    *name;
+        struct module *owner;
+        const struct gio_device_id *id_table;
+
+        int  (*probe)(struct gio_device *, const struct gio_device_id *);
+        void (*remove)(struct gio_device *);
+        int  (*suspend)(struct gio_device *, pm_message_t);
+        int  (*resume)(struct gio_device *);
+        void (*shutdown)(struct gio_device *);
+
+        struct device_driver driver;
+};
+#define to_gio_driver(drv) container_of(drv, struct gio_driver, driver)
+
+extern const struct gio_device_id *gio_match_device(const struct gio_device_id *,
+                                                    const struct gio_device *);
+extern struct gio_device *gio_dev_get(struct gio_device *);
+extern void gio_dev_put(struct gio_device *);
+
+extern int gio_device_register(struct gio_device *);
+extern void gio_device_unregister(struct gio_device *);
+extern void gio_release_dev(struct device *);
+
+static inline void gio_device_free(struct gio_device *dev)
+{
+        gio_release_dev(&dev->dev);
+}
+
+extern int gio_register_driver(struct gio_driver *);
+extern void gio_unregister_driver(struct gio_driver *);
+
+#define gio_get_drvdata(_dev)        drv_get_drvdata(&(_dev)->dev)
+#define gio_set_drvdata(_dev, data)  drv_set_drvdata(&(_dev)->dev, (data))
+
+extern void gio_set_master(struct gio_device *);
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 4e332165d7b7..b4c20e4f87cd 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,8 @@ do {									\
         : "=r" (tmp));                                                  \
 } while (0)
 
-#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
+#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
+        defined(CONFIG_CPU_BMIPS)
 
 /*
  * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -139,8 +140,8 @@ do {									\
 } while (0)
 
 #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
-      defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
-      defined(CONFIG_CPU_R5500)
+        defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
+        defined(CONFIG_CPU_R5500)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index c565b7c3f0b5..58d36889f09b 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -70,7 +70,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
 static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
                                          unsigned long addr, pte_t *ptep)
 {
-        flush_tlb_mm(vma->vm_mm);
+        flush_tlb_page(vma, addr & huge_page_mask(hstate_vma(vma)));
 }
 
 static inline int huge_pte_none(pte_t pte)
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
index e6ea4d4d7205..1fbbca01e681 100644
--- a/arch/mips/include/asm/kprobes.h
+++ b/arch/mips/include/asm/kprobes.h
@@ -74,6 +74,8 @@ struct prev_kprobe {
                 : MAX_JPROBES_STACK_SIZE)
 
 
+#define SKIP_DELAYSLOT 0x0001
+
 /* per-cpu kprobe control block */
 struct kprobe_ctlblk {
         unsigned long kprobe_status;
@@ -82,6 +84,9 @@ struct kprobe_ctlblk {
         unsigned long kprobe_saved_epc;
         unsigned long jprobe_saved_sp;
         struct pt_regs jprobe_saved_regs;
+        /* Per-thread fields, used while emulating branches */
+        unsigned long flags;
+        unsigned long target_epc;
         u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
         struct prev_kprobe prev_kprobe;
 };
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index cda1c8070b27..2f0becb4ec8f 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -20,6 +20,10 @@
 #include <linux/bitops.h>
 
 #define AR71XX_APB_BASE         0x18000000
+#define AR71XX_EHCI_BASE        0x1b000000
+#define AR71XX_EHCI_SIZE        0x1000
+#define AR71XX_OHCI_BASE        0x1c000000
+#define AR71XX_OHCI_SIZE        0x1000
 #define AR71XX_SPI_BASE         0x1f000000
 #define AR71XX_SPI_SIZE         0x01000000
 
@@ -27,6 +31,8 @@
 #define AR71XX_DDR_CTRL_SIZE    0x100
 #define AR71XX_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
 #define AR71XX_UART_SIZE        0x100
+#define AR71XX_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE    0x100
 #define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
 #define AR71XX_GPIO_SIZE        0x100
 #define AR71XX_PLL_BASE         (AR71XX_APB_BASE + 0x00050000)
@@ -34,9 +40,26 @@
 #define AR71XX_RESET_BASE       (AR71XX_APB_BASE + 0x00060000)
 #define AR71XX_RESET_SIZE       0x100
 
+#define AR7240_USB_CTRL_BASE    (AR71XX_APB_BASE + 0x00030000)
+#define AR7240_USB_CTRL_SIZE    0x100
+#define AR7240_OHCI_BASE        0x1b000000
+#define AR7240_OHCI_SIZE        0x1000
+
+#define AR724X_EHCI_BASE        0x1b000000
+#define AR724X_EHCI_SIZE        0x1000
+
+#define AR913X_EHCI_BASE        0x1b000000
+#define AR913X_EHCI_SIZE        0x1000
 #define AR913X_WMAC_BASE        (AR71XX_APB_BASE + 0x000C0000)
 #define AR913X_WMAC_SIZE        0x30000
 
+#define AR933X_UART_BASE        (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE        0x14
+#define AR933X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE        0x20000
+#define AR933X_EHCI_BASE        0x1b000000
+#define AR933X_EHCI_SIZE        0x1000
+
 /*
  * DDR_CTRL block
  */
@@ -63,6 +86,11 @@
 #define AR913X_DDR_REG_FLUSH_USB        0x84
 #define AR913X_DDR_REG_FLUSH_WMAC       0x88
 
+#define AR933X_DDR_REG_FLUSH_GE0        0x7c
+#define AR933X_DDR_REG_FLUSH_GE1        0x80
+#define AR933X_DDR_REG_FLUSH_USB        0x84
+#define AR933X_DDR_REG_FLUSH_WMAC       0x88
+
 /*
  * PLL block
  */
@@ -104,6 +132,30 @@
 #define AR913X_AHB_DIV_SHIFT            19
 #define AR913X_AHB_DIV_MASK             0x1
 
+#define AR933X_PLL_CPU_CONFIG_REG       0x00
+#define AR933X_PLL_CLOCK_CTRL_REG       0x08
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT        10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK         0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT      16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT      23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK       0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS            BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT     5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK      0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT     10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK      0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT     15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK      0x7
+
+/*
+ * USB_CONFIG block
+ */
+#define AR71XX_USB_CTRL_REG_FLADJ       0x00
+#define AR71XX_USB_CTRL_REG_CONFIG      0x04
+
 /*
  * RESET block
  */
@@ -130,6 +182,13 @@
 
 #define AR724X_RESET_REG_RESET_MODULE           0x1c
 
+#define AR933X_RESET_REG_RESET_MODULE           0x1c
+#define AR933X_RESET_REG_BOOTSTRAP              0xac
+
+#define MISC_INT_ETHSW                  BIT(12)
+#define MISC_INT_TIMER4                 BIT(10)
+#define MISC_INT_TIMER3                 BIT(9)
+#define MISC_INT_TIMER2                 BIT(8)
 #define MISC_INT_DMA                    BIT(7)
 #define MISC_INT_OHCI                   BIT(6)
 #define MISC_INT_PERFC                  BIT(5)
@@ -158,14 +217,29 @@
 #define AR71XX_RESET_PCI_BUS            BIT(1)
 #define AR71XX_RESET_PCI_CORE           BIT(0)
 
+#define AR7240_RESET_USB_HOST           BIT(5)
+#define AR7240_RESET_OHCI_DLL           BIT(3)
+
 #define AR724X_RESET_GE1_MDIO           BIT(23)
 #define AR724X_RESET_GE0_MDIO           BIT(22)
 #define AR724X_RESET_PCIE_PHY_SERIAL    BIT(10)
 #define AR724X_RESET_PCIE_PHY           BIT(7)
 #define AR724X_RESET_PCIE               BIT(6)
-#define AR724X_RESET_OHCI_DLL           BIT(3)
+#define AR724X_RESET_USB_HOST           BIT(5)
+#define AR724X_RESET_USB_PHY            BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE    BIT(3)
 
 #define AR913X_RESET_AMBA2WMAC          BIT(22)
+#define AR913X_RESET_USBSUS_OVERRIDE    BIT(10)
+#define AR913X_RESET_USB_HOST           BIT(5)
+#define AR913X_RESET_USB_PHY            BIT(4)
+
+#define AR933X_RESET_WMAC               BIT(11)
+#define AR933X_RESET_USB_HOST           BIT(5)
+#define AR933X_RESET_USB_PHY            BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE    BIT(3)
+
+#define AR933X_BOOTSTRAP_REF_CLK_40     BIT(0)
 
 #define REV_ID_MAJOR_MASK               0xfff0
 #define REV_ID_MAJOR_AR71XX             0x00a0
@@ -173,6 +247,8 @@
 #define REV_ID_MAJOR_AR7240             0x00c0
 #define REV_ID_MAJOR_AR7241             0x0100
 #define REV_ID_MAJOR_AR7242             0x1100
+#define REV_ID_MAJOR_AR9330             0x0110
+#define REV_ID_MAJOR_AR9331             0x1110
 
 #define AR71XX_REV_ID_MINOR_MASK        0x3
 #define AR71XX_REV_ID_MINOR_AR7130      0x0
@@ -187,6 +263,8 @@
 #define AR913X_REV_ID_REVISION_MASK     0x3
 #define AR913X_REV_ID_REVISION_SHIFT    2
 
+#define AR933X_REV_ID_REVISION_MASK     0x3
+
 #define AR724X_REV_ID_REVISION_MASK     0x3
 
 /*
@@ -229,5 +307,6 @@
 #define AR71XX_GPIO_COUNT               16
 #define AR724X_GPIO_COUNT               18
 #define AR913X_GPIO_COUNT               22
+#define AR933X_GPIO_COUNT               30
 
 #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
new file mode 100644
index 000000000000..52730555937f
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
@@ -0,0 +1,67 @@
+/*
+ *  Atheros AR933X UART defines
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __AR933X_UART_H
+#define __AR933X_UART_H
+
+#define AR933X_UART_REGS_SIZE           20
+#define AR933X_UART_FIFO_SIZE           16
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLOCK_REG           0x08
+#define AR933X_UART_INT_REG             0x0c
+#define AR933X_UART_INT_EN_REG          0x10
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+
+#define AR933X_UART_CS_PARITY_S         0
+#define AR933X_UART_CS_PARITY_M         0x3
+#define   AR933X_UART_CS_PARITY_NONE    0
+#define   AR933X_UART_CS_PARITY_ODD     1
+#define   AR933X_UART_CS_PARITY_EVEN    2
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define   AR933X_UART_CS_IF_MODE_NONE   0
+#define   AR933X_UART_CS_IF_MODE_DTE    1
+#define   AR933X_UART_CS_IF_MODE_DCE    2
+#define AR933X_UART_CS_FLOW_CTRL_S      4
+#define AR933X_UART_CS_FLOW_CTRL_M      0x3
+#define AR933X_UART_CS_DMA_EN           BIT(6)
+#define AR933X_UART_CS_TX_READY_ORIDE   BIT(7)
+#define AR933X_UART_CS_RX_READY_ORIDE   BIT(8)
+#define AR933X_UART_CS_TX_READY         BIT(9)
+#define AR933X_UART_CS_RX_BREAK         BIT(10)
+#define AR933X_UART_CS_TX_BREAK         BIT(11)
+#define AR933X_UART_CS_HOST_INT         BIT(12)
+#define AR933X_UART_CS_HOST_INT_EN      BIT(13)
+#define AR933X_UART_CS_TX_BUSY          BIT(14)
+#define AR933X_UART_CS_RX_BUSY          BIT(15)
+
+#define AR933X_UART_CLOCK_STEP_M        0xffff
+#define AR933X_UART_CLOCK_SCALE_M       0xfff
+#define AR933X_UART_CLOCK_SCALE_S       16
+#define AR933X_UART_CLOCK_STEP_M        0xffff
+
+#define AR933X_UART_INT_RX_VALID        BIT(0)
+#define AR933X_UART_INT_TX_READY        BIT(1)
+#define AR933X_UART_INT_RX_FRAMING_ERR  BIT(2)
+#define AR933X_UART_INT_RX_OFLOW_ERR    BIT(3)
+#define AR933X_UART_INT_TX_OFLOW_ERR    BIT(4)
+#define AR933X_UART_INT_RX_PARITY_ERR   BIT(5)
+#define AR933X_UART_INT_RX_BREAK_ON     BIT(6)
+#define AR933X_UART_INT_RX_BREAK_OFF    BIT(7)
+#define AR933X_UART_INT_RX_FULL         BIT(8)
+#define AR933X_UART_INT_TX_EMPTY        BIT(9)
+#define AR933X_UART_INT_ALLINTS         0x3ff
+
+#endif /* __AR933X_UART_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
new file mode 100644
index 000000000000..6cb30f2b7198
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
@@ -0,0 +1,18 @@
+/*
+ *  Platform data definition for Atheros AR933X UART
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _AR933X_UART_PLATFORM_H
+#define _AR933X_UART_PLATFORM_H
+
+struct ar933x_uart_platform_data {
+        unsigned        uartclk;
+};
+
+#endif /* _AR933X_UART_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 6a9f168506fe..6d0c6c9d5622 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -26,10 +26,13 @@ enum ath79_soc_type {
         ATH79_SOC_AR7241,
         ATH79_SOC_AR7242,
         ATH79_SOC_AR9130,
-        ATH79_SOC_AR9132
+        ATH79_SOC_AR9132,
+        ATH79_SOC_AR9330,
+        ATH79_SOC_AR9331,
 };
 
 extern enum ath79_soc_type ath79_soc;
+extern unsigned int ath79_soc_rev;
 
 static inline int soc_is_ar71xx(void)
 {
@@ -66,6 +69,12 @@ static inline int soc_is_ar913x(void)
                 ath79_soc == ATH79_SOC_AR9132);
 }
 
+static inline int soc_is_ar933x(void)
+{
+        return (ath79_soc == ATH79_SOC_AR9330 ||
+                ath79_soc == ATH79_SOC_AR9331);
+}
+
 extern void __iomem *ath79_ddr_base;
 extern void __iomem *ath79_pll_base;
 extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 189bc6eb9c10..519958fe4e3c 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,10 +10,10 @@
 #define __ASM_MACH_ATH79_IRQ_H
 
 #define MIPS_CPU_IRQ_BASE       0
-#define NR_IRQS                 16
+#define NR_IRQS                 40
 
 #define ATH79_MISC_IRQ_BASE     8
-#define ATH79_MISC_IRQ_COUNT    8
+#define ATH79_MISC_IRQ_COUNT    32
 
 #define ATH79_CPU_IRQ_IP2       (MIPS_CPU_IRQ_BASE + 2)
 #define ATH79_CPU_IRQ_USB       (MIPS_CPU_IRQ_BASE + 3)
@@ -30,6 +30,10 @@
 #define ATH79_MISC_IRQ_PERFC    (ATH79_MISC_IRQ_BASE + 5)
 #define ATH79_MISC_IRQ_OHCI     (ATH79_MISC_IRQ_BASE + 6)
 #define ATH79_MISC_IRQ_DMA      (ATH79_MISC_IRQ_BASE + 7)
+#define ATH79_MISC_IRQ_TIMER2   (ATH79_MISC_IRQ_BASE + 8)
+#define ATH79_MISC_IRQ_TIMER3   (ATH79_MISC_IRQ_BASE + 9)
+#define ATH79_MISC_IRQ_TIMER4   (ATH79_MISC_IRQ_BASE + 10)
+#define ATH79_MISC_IRQ_ETHSW    (ATH79_MISC_IRQ_BASE + 12)
 
 #include_next <irq.h>
 
diff --git a/arch/mips/include/asm/mach-ath79/pci-ath724x.h b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
new file mode 100644
index 000000000000..454885fa30c3
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
@@ -0,0 +1,21 @@
+/*
+ *  Atheros 724x PCI support
+ *
+ *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
+#define __ASM_MACH_ATH79_PCI_ATH724X_H
+
+struct ath724x_pci_data {
+        int irq;
+        void *pdata;
+};
+
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
+
+#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index de24ec57dd2f..569828d3ccab 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
 #define ALCHEMY_CPU_AU1100      2
 #define ALCHEMY_CPU_AU1550      3
 #define ALCHEMY_CPU_AU1200      4
+#define ALCHEMY_CPU_AU1300      5
 
 static inline int alchemy_get_cputype(void)
 {
@@ -156,6 +157,9 @@ static inline int alchemy_get_cputype(void)
         case 0x05030000:
                 return ALCHEMY_CPU_AU1200;
                 break;
+        case 0x800c0000:
+                return ALCHEMY_CPU_AU1300;
+                break;
         }
 
         return ALCHEMY_CPU_UNKNOWN;
@@ -166,6 +170,7 @@ static inline int alchemy_get_uarts(int type)
 {
         switch (type) {
         case ALCHEMY_CPU_AU1000:
+        case ALCHEMY_CPU_AU1300:
                 return 4;
         case ALCHEMY_CPU_AU1500:
         case ALCHEMY_CPU_AU1200:
@@ -243,6 +248,7 @@ extern unsigned long au1xxx_calc_clock(void);
 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
 void alchemy_sleep_au1000(void);
 void alchemy_sleep_au1550(void);
+void alchemy_sleep_au1300(void);
 void au_sleep(void);
 
 /* USB: drivers/usb/host/alchemy-common.c */
@@ -251,6 +257,7 @@ enum alchemy_usb_block {
         ALCHEMY_USB_UDC0,
         ALCHEMY_USB_EHCI0,
         ALCHEMY_USB_OTG0,
+        ALCHEMY_USB_OHCI1,
 };
 int alchemy_usb_control(int block, int enable);
 
@@ -263,14 +270,92 @@ struct alchemy_pci_platdata {
         unsigned long pci_cfg_clr;
 };
 
-/* SOC Interrupt numbers */
+/* Multifunction pins: Each of these pins can either be assigned to the
+ * GPIO controller or a on-chip peripheral.
+ * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
+ * assign one of these to either the GPIO controller or the device.
+ */
+enum au1300_multifunc_pins {
+        /* wake-from-str pins 0-3 */
+        AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
+        AU1300_PIN_WAKE3,
+        /* external clock sources for PSCs: 4-5 */
+        AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
+        /* 8bit MMC interface on SD0: 6-9 */
+        AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
+        AU1300_PIN_SD0DAT7,
+        /* aux clk input for freqgen 3: 10 */
+        AU1300_PIN_FG3AUX,
+        /* UART1 pins: 11-18 */
+        AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
+        AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
+        AU1300_PIN_U1RX, AU1300_PIN_U1TX,
+        /* UART0 pins: 19-24 */
+        AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
+        AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
+        /* UART2: 25-26 */
+        AU1300_PIN_U2RX, AU1300_PIN_U2TX,
+        /* UART3: 27-28 */
+        AU1300_PIN_U3RX, AU1300_PIN_U3TX,
+        /* LCD controller PWMs, ext pixclock: 29-31 */
+        AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
+        /* SD1 interface: 32-37 */
+        AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
+        AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
+        /* SD2 interface: 38-43 */
+        AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
+        AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
+        /* PSC0/1 clocks: 44-45 */
+        AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
+        /* PSCs: 46-49/50-53/54-57/58-61 */
+        AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
+        AU1300_PIN_PSC0D1,
+        AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
+        AU1300_PIN_PSC1D1,
+        AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
+        AU1300_PIN_PSC2D1,
+        AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
+        AU1300_PIN_PSC3D1,
+        /* PCMCIA interface: 62-70 */
+        AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
+        AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
+        AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
+        /* camera interface H/V sync inputs: 71-72 */
+        AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
+        /* PSC2/3 clocks: 73-74 */
+        AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
+};
+
+/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
+extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
+extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
+extern void au1300_set_irq_priority(unsigned int irq, int p);
+extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
+
+/* Au1300 allows to disconnect certain blocks from internal power supply */
+enum au1300_vss_block {
+        AU1300_VSS_MPE = 0,
+        AU1300_VSS_BSA,
+        AU1300_VSS_GPE,
+        AU1300_VSS_MGP,
+};
 
+extern void au1300_vss_block_control(int block, int enable);
+
+
+/* SOC Interrupt numbers */
+/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
 #define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
 #define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)
 #define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_LAST + 1)
 #define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)
 #define AU1000_MAX_INTR         AU1000_INTC1_INT_LAST
 
+/* Au1300-style (GPIC): 1 controller with up to 128 sources */
+#define ALCHEMY_GPIC_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
+#define ALCHEMY_GPIC_INT_NUM    128
+#define ALCHEMY_GPIC_INT_LAST   (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
+
 enum soc_au1000_ints {
         AU1000_FIRST_INT        = AU1000_INTC0_INT_BASE,
         AU1000_UART0_INT        = AU1000_FIRST_INT,
@@ -591,24 +676,77 @@ enum soc_au1200_ints {
 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
+/* Au1300 peripheral interrupt numbers */
+#define AU1300_FIRST_INT        (ALCHEMY_GPIC_INT_BASE)
+#define AU1300_UART1_INT        (AU1300_FIRST_INT + 17)
+#define AU1300_UART2_INT        (AU1300_FIRST_INT + 25)
+#define AU1300_UART3_INT        (AU1300_FIRST_INT + 27)
+#define AU1300_SD1_INT          (AU1300_FIRST_INT + 32)
+#define AU1300_SD2_INT          (AU1300_FIRST_INT + 38)
+#define AU1300_PSC0_INT         (AU1300_FIRST_INT + 48)
+#define AU1300_PSC1_INT         (AU1300_FIRST_INT + 52)
+#define AU1300_PSC2_INT         (AU1300_FIRST_INT + 56)
+#define AU1300_PSC3_INT         (AU1300_FIRST_INT + 60)
+#define AU1300_NAND_INT         (AU1300_FIRST_INT + 62)
+#define AU1300_DDMA_INT         (AU1300_FIRST_INT + 75)
+#define AU1300_MMU_INT          (AU1300_FIRST_INT + 76)
+#define AU1300_MPU_INT          (AU1300_FIRST_INT + 77)
+#define AU1300_GPU_INT          (AU1300_FIRST_INT + 78)
+#define AU1300_UDMA_INT         (AU1300_FIRST_INT + 79)
+#define AU1300_TOY_INT          (AU1300_FIRST_INT + 80)
+#define AU1300_TOY_MATCH0_INT   (AU1300_FIRST_INT + 81)
+#define AU1300_TOY_MATCH1_INT   (AU1300_FIRST_INT + 82)
+#define AU1300_TOY_MATCH2_INT   (AU1300_FIRST_INT + 83)
+#define AU1300_RTC_INT          (AU1300_FIRST_INT + 84)
+#define AU1300_RTC_MATCH0_INT   (AU1300_FIRST_INT + 85)
+#define AU1300_RTC_MATCH1_INT   (AU1300_FIRST_INT + 86)
+#define AU1300_RTC_MATCH2_INT   (AU1300_FIRST_INT + 87)
+#define AU1300_UART0_INT        (AU1300_FIRST_INT + 88)
+#define AU1300_SD0_INT          (AU1300_FIRST_INT + 89)
+#define AU1300_USB_INT          (AU1300_FIRST_INT + 90)
+#define AU1300_LCD_INT          (AU1300_FIRST_INT + 91)
+#define AU1300_BSA_INT          (AU1300_FIRST_INT + 92)
+#define AU1300_MPE_INT          (AU1300_FIRST_INT + 93)
+#define AU1300_ITE_INT          (AU1300_FIRST_INT + 94)
+#define AU1300_AES_INT          (AU1300_FIRST_INT + 95)
+#define AU1300_CIM_INT          (AU1300_FIRST_INT + 96)
+
+/**********************************************************************/
+
 /*
  * Physical base addresses for integrated peripherals
- * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
+ * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
  */
 
 #define AU1000_AC97_PHYS_ADDR           0x10000000 /* 012 */
+#define AU1300_ROM_PHYS_ADDR            0x10000000 /* 5 */
+#define AU1300_OTP_PHYS_ADDR            0x10002000 /* 5 */
+#define AU1300_VSS_PHYS_ADDR            0x10003000 /* 5 */
+#define AU1300_UART0_PHYS_ADDR          0x10100000 /* 5 */
+#define AU1300_UART1_PHYS_ADDR          0x10101000 /* 5 */
+#define AU1300_UART2_PHYS_ADDR          0x10102000 /* 5 */
+#define AU1300_UART3_PHYS_ADDR          0x10103000 /* 5 */
 #define AU1000_USB_OHCI_PHYS_ADDR       0x10100000 /* 012 */
 #define AU1000_USB_UDC_PHYS_ADDR        0x10200000 /* 0123 */
+#define AU1300_GPIC_PHYS_ADDR           0x10200000 /* 5 */
 #define AU1000_IRDA_PHYS_ADDR           0x10300000 /* 02 */
-#define AU1200_AES_PHYS_ADDR            0x10300000 /* 4 */
+#define AU1200_AES_PHYS_ADDR            0x10300000 /* 45 */
 #define AU1000_IC0_PHYS_ADDR            0x10400000 /* 01234 */
+#define AU1300_GPU_PHYS_ADDR            0x10500000 /* 5 */
 #define AU1000_MAC0_PHYS_ADDR           0x10500000 /* 023 */
 #define AU1000_MAC1_PHYS_ADDR           0x10510000 /* 023 */
 #define AU1000_MACEN_PHYS_ADDR          0x10520000 /* 023 */
-#define AU1100_SD0_PHYS_ADDR            0x10600000 /* 24 */
+#define AU1100_SD0_PHYS_ADDR            0x10600000 /* 245 */
+#define AU1300_SD1_PHYS_ADDR            0x10601000 /* 5 */
+#define AU1300_SD2_PHYS_ADDR            0x10602000 /* 5 */
 #define AU1100_SD1_PHYS_ADDR            0x10680000 /* 24 */
+#define AU1300_SYS_PHYS_ADDR            0x10900000 /* 5 */
 #define AU1550_PSC2_PHYS_ADDR           0x10A00000 /* 3 */
 #define AU1550_PSC3_PHYS_ADDR           0x10B00000 /* 3 */
+#define AU1300_PSC0_PHYS_ADDR           0x10A00000 /* 5 */
+#define AU1300_PSC1_PHYS_ADDR           0x10A01000 /* 5 */
+#define AU1300_PSC2_PHYS_ADDR           0x10A02000 /* 5 */
+#define AU1300_PSC3_PHYS_ADDR           0x10A03000 /* 5 */
 #define AU1000_I2S_PHYS_ADDR            0x11000000 /* 02 */
 #define AU1500_MAC0_PHYS_ADDR           0x11500000 /* 1 */
 #define AU1500_MAC1_PHYS_ADDR           0x11510000 /* 1 */
@@ -622,37 +760,96 @@ enum soc_au1200_ints {
 #define AU1000_SSI1_PHYS_ADDR           0x11680000 /* 02 */
 #define AU1500_GPIO2_PHYS_ADDR          0x11700000 /* 1234 */
 #define AU1000_IC1_PHYS_ADDR            0x11800000 /* 01234 */
-#define AU1000_SYS_PHYS_ADDR            0x11900000 /* 01234 */
+#define AU1000_SYS_PHYS_ADDR            0x11900000 /* 012345 */
 #define AU1550_PSC0_PHYS_ADDR           0x11A00000 /* 34 */
 #define AU1550_PSC1_PHYS_ADDR           0x11B00000 /* 34 */
 #define AU1000_MEM_PHYS_ADDR            0x14000000 /* 01234 */
 #define AU1000_STATIC_MEM_PHYS_ADDR     0x14001000 /* 01234 */
+#define AU1300_UDMA_PHYS_ADDR           0x14001800 /* 5 */
 #define AU1000_DMA_PHYS_ADDR            0x14002000 /* 012 */
-#define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 34 */
-#define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 34 */
+#define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 345 */
+#define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 345 */
 #define AU1000_MACDMA0_PHYS_ADDR        0x14004000 /* 0123 */
 #define AU1000_MACDMA1_PHYS_ADDR        0x14004200 /* 0123 */
-#define AU1200_CIM_PHYS_ADDR            0x14004000 /* 4 */
+#define AU1200_CIM_PHYS_ADDR            0x14004000 /* 45 */
 #define AU1500_PCI_PHYS_ADDR            0x14005000 /* 13 */
 #define AU1550_PE_PHYS_ADDR             0x14008000 /* 3 */
 #define AU1200_MAEBE_PHYS_ADDR          0x14010000 /* 4 */
 #define AU1200_MAEFE_PHYS_ADDR          0x14012000 /* 4 */
+#define AU1300_MAEITE_PHYS_ADDR         0x14010000 /* 5 */
+#define AU1300_MAEMPE_PHYS_ADDR         0x14014000 /* 5 */
 #define AU1550_USB_OHCI_PHYS_ADDR       0x14020000 /* 3 */
 #define AU1200_USB_CTL_PHYS_ADDR        0x14020000 /* 4 */
 #define AU1200_USB_OTG_PHYS_ADDR        0x14020020 /* 4 */
 #define AU1200_USB_OHCI_PHYS_ADDR       0x14020100 /* 4 */
 #define AU1200_USB_EHCI_PHYS_ADDR       0x14020200 /* 4 */
 #define AU1200_USB_UDC_PHYS_ADDR        0x14022000 /* 4 */
+#define AU1300_USB_EHCI_PHYS_ADDR       0x14020000 /* 5 */
+#define AU1300_USB_OHCI0_PHYS_ADDR      0x14020400 /* 5 */
+#define AU1300_USB_OHCI1_PHYS_ADDR      0x14020800 /* 5 */
+#define AU1300_USB_CTL_PHYS_ADDR        0x14021000 /* 5 */
+#define AU1300_USB_OTG_PHYS_ADDR        0x14022000 /* 5 */
+#define AU1300_MAEBSA_PHYS_ADDR         0x14030000 /* 5 */
 #define AU1100_LCD_PHYS_ADDR            0x15000000 /* 2 */
-#define AU1200_LCD_PHYS_ADDR            0x15000000 /* 4 */
+#define AU1200_LCD_PHYS_ADDR            0x15000000 /* 45 */
 #define AU1500_PCI_MEM_PHYS_ADDR        0x400000000ULL /* 13 */
 #define AU1500_PCI_IO_PHYS_ADDR         0x500000000ULL /* 13 */
 #define AU1500_PCI_CONFIG0_PHYS_ADDR    0x600000000ULL /* 13 */
 #define AU1500_PCI_CONFIG1_PHYS_ADDR    0x680000000ULL /* 13 */
-#define AU1000_PCMCIA_IO_PHYS_ADDR      0xF00000000ULL /* 01234 */
-#define AU1000_PCMCIA_ATTR_PHYS_ADDR    0xF40000000ULL /* 01234 */
-#define AU1000_PCMCIA_MEM_PHYS_ADDR     0xF80000000ULL /* 01234 */
+#define AU1000_PCMCIA_IO_PHYS_ADDR      0xF00000000ULL /* 012345 */
+#define AU1000_PCMCIA_ATTR_PHYS_ADDR    0xF40000000ULL /* 012345 */
+#define AU1000_PCMCIA_MEM_PHYS_ADDR     0xF80000000ULL /* 012345 */
 
+/**********************************************************************/
+
+
+/*
+ * Au1300 GPIO+INT controller (GPIC) register offsets and bits
+ * Registers are 128bits (0x10 bytes), divided into 4 "banks".
+ */
+#define AU1300_GPIC_PINVAL      0x0000
+#define AU1300_GPIC_PINVALCLR   0x0010
+#define AU1300_GPIC_IPEND       0x0020
+#define AU1300_GPIC_PRIENC      0x0030
+#define AU1300_GPIC_IEN         0x0040  /* int_mask in manual */
+#define AU1300_GPIC_IDIS        0x0050  /* int_maskclr in manual */
+#define AU1300_GPIC_DMASEL      0x0060
+#define AU1300_GPIC_DEVSEL      0x0080
+#define AU1300_GPIC_DEVCLR      0x0090
+#define AU1300_GPIC_RSTVAL      0x00a0
+/* pin configuration space. one 32bit register for up to 128 IRQs */
+#define AU1300_GPIC_PINCFG      0x1000
+
+#define GPIC_GPIO_TO_BIT(gpio)  \
+        (1 << ((gpio) & 0x1f))
+
+#define GPIC_GPIO_BANKOFF(gpio) \
+        (((gpio) >> 5) * 4)
+
+/* Pin Control bits: who owns the pin, what does it do */
+#define GPIC_CFG_PC_GPIN                0
+#define GPIC_CFG_PC_DEV                 1
+#define GPIC_CFG_PC_GPOLOW              2
+#define GPIC_CFG_PC_GPOHIGH             3
+#define GPIC_CFG_PC_MASK                3
+
+/* assign pin to MIPS IRQ line */
+#define GPIC_CFG_IL_SET(x)      (((x) & 3) << 2)
+#define GPIC_CFG_IL_MASK        (3 << 2)
+
+/* pin interrupt type setup */
+#define GPIC_CFG_IC_OFF         (0 << 4)
+#define GPIC_CFG_IC_LEVEL_LOW   (1 << 4)
+#define GPIC_CFG_IC_LEVEL_HIGH  (2 << 4)
+#define GPIC_CFG_IC_EDGE_FALL   (5 << 4)
+#define GPIC_CFG_IC_EDGE_RISE   (6 << 4)
+#define GPIC_CFG_IC_EDGE_BOTH   (7 << 4)
+#define GPIC_CFG_IC_MASK        (7 << 4)
+
+/* allow interrupt to wake cpu from 'wait' */
+#define GPIC_CFG_IDLEWAKE       (1 << 7)
+
+/***********************************************************************/
 
 /* Au1000 SDRAM memory controller register offsets */
 #define AU1000_MEM_SDMODE0              0x0000
@@ -1068,44 +1265,20 @@ enum soc_au1200_ints {
 #define SSI_ENABLE_CD           (1 << 1)
 #define SSI_ENABLE_E            (1 << 0)
 
-/* IrDA Controller */
-#define IRDA_BASE               0xB0300000
-#define IR_RING_PTR_STATUS      (IRDA_BASE + 0x00)
-#define IR_RING_BASE_ADDR_H     (IRDA_BASE + 0x04)
-#define IR_RING_BASE_ADDR_L     (IRDA_BASE + 0x08)
-#define IR_RING_SIZE            (IRDA_BASE + 0x0C)
-#define IR_RING_PROMPT          (IRDA_BASE + 0x10)
-#define IR_RING_ADDR_CMPR       (IRDA_BASE + 0x14)
-#define IR_INT_CLEAR            (IRDA_BASE + 0x18)
-#define IR_CONFIG_1             (IRDA_BASE + 0x20)
-#  define IR_RX_INVERT_LED      (1 << 0)
-#  define IR_TX_INVERT_LED      (1 << 1)
-#  define IR_ST                 (1 << 2)
-#  define IR_SF                 (1 << 3)
-#  define IR_SIR                (1 << 4)
-#  define IR_MIR                (1 << 5)
-#  define IR_FIR                (1 << 6)
-#  define IR_16CRC              (1 << 7)
-#  define IR_TD                 (1 << 8)
-#  define IR_RX_ALL             (1 << 9)
-#  define IR_DMA_ENABLE         (1 << 10)
-#  define IR_RX_ENABLE          (1 << 11)
-#  define IR_TX_ENABLE          (1 << 12)
-#  define IR_LOOPBACK           (1 << 14)
-#  define IR_SIR_MODE           (IR_SIR | IR_DMA_ENABLE | \
-                                 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
-#define IR_SIR_FLAGS            (IRDA_BASE + 0x24)
-#define IR_ENABLE               (IRDA_BASE + 0x28)
-#  define IR_RX_STATUS          (1 << 9)
-#  define IR_TX_STATUS          (1 << 10)
-#define IR_READ_PHY_CONFIG      (IRDA_BASE + 0x2C)
-#define IR_WRITE_PHY_CONFIG     (IRDA_BASE + 0x30)
-#define IR_MAX_PKT_LEN          (IRDA_BASE + 0x34)
-#define IR_RX_BYTE_CNT          (IRDA_BASE + 0x38)
-#define IR_CONFIG_2             (IRDA_BASE + 0x3C)
-#  define IR_MODE_INV           (1 << 0)
-#  define IR_ONE_PIN            (1 << 1)
-#define IR_INTERFACE_CONFIG     (IRDA_BASE + 0x40)
+
+/*
+ * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not
+ * used to select FIR/SIR mode on the transceiver but as a GPIO.  Instead a
+ * CPLD has to be told about the mode.
+ */
+#define AU1000_IRDA_PHY_MODE_OFF        0
+#define AU1000_IRDA_PHY_MODE_SIR        1
+#define AU1000_IRDA_PHY_MODE_FIR        2
+
+struct au1k_irda_platform_data {
+        void(*set_phy_mode)(int mode);
+};
+
 
 /* GPIO */
 #define SYS_PINFUNC             0xB190002C
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index 94000a3b6f0b..e221659f1bca 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -130,8 +130,10 @@ struct au1xmmc_platform_data {
 #define SD_CONFIG2_DF   (0x00000008)
 #define SD_CONFIG2_DC   (0x00000010)
 #define SD_CONFIG2_xx2  (0x000000e0)
+#define SD_CONFIG2_BB   (0x00000080)
 #define SD_CONFIG2_WB   (0x00000100)
 #define SD_CONFIG2_RW   (0x00000200)
+#define SD_CONFIG2_DP   (0x00000400)
 
 
 /*
diff --git a/arch/mips/include/asm/mach-au1x00/au1200fb.h b/arch/mips/include/asm/mach-au1x00/au1200fb.h
new file mode 100644
index 000000000000..b3c87cc64bb9
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1200fb.h
@@ -0,0 +1,14 @@
+/*
+ * platform data for au1200fb driver.
+ */
+
+#ifndef _AU1200FB_PLAT_H_
+#define _AU1200FB_PLAT_H_
+
+struct au1200fb_platdata {
+        int (*panel_index)(void);
+        int (*panel_init)(void);
+        int (*panel_shutdown)(void);
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1550nd.h b/arch/mips/include/asm/mach-au1x00/au1550nd.h
new file mode 100644
index 000000000000..ad4c0a03afef
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1550nd.h
@@ -0,0 +1,16 @@
+/*
+ * platform data for the Au1550 NAND driver
+ */
+
+#ifndef _AU1550ND_H_
+#define _AU1550ND_H_
+
+#include <linux/mtd/partitions.h>
+
+struct au1550nd_platdata {
+        struct mtd_partition *parts;
+        int num_parts;
+        int devwidth;   /* 0 = 8bit device, 1 = 16bit device */
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 323ce2d145f2..217810e18361 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -183,6 +183,37 @@ typedef volatile struct au1xxx_ddma_desc {
 #define AU1200_DSCR_CMD0_PSC1_SYNC      25
 #define AU1200_DSCR_CMD0_CIM_SYNC       26
 
+#define AU1300_DSCR_CMD0_UART0_TX      0
+#define AU1300_DSCR_CMD0_UART0_RX      1
+#define AU1300_DSCR_CMD0_UART1_TX      2
+#define AU1300_DSCR_CMD0_UART1_RX      3
+#define AU1300_DSCR_CMD0_UART2_TX      4
+#define AU1300_DSCR_CMD0_UART2_RX      5
+#define AU1300_DSCR_CMD0_UART3_TX      6
+#define AU1300_DSCR_CMD0_UART3_RX      7
+#define AU1300_DSCR_CMD0_SDMS_TX0      8
+#define AU1300_DSCR_CMD0_SDMS_RX0      9
+#define AU1300_DSCR_CMD0_SDMS_TX1      10
+#define AU1300_DSCR_CMD0_SDMS_RX1      11
+#define AU1300_DSCR_CMD0_AES_TX        12
+#define AU1300_DSCR_CMD0_AES_RX        13
+#define AU1300_DSCR_CMD0_PSC0_TX       14
+#define AU1300_DSCR_CMD0_PSC0_RX       15
+#define AU1300_DSCR_CMD0_PSC1_TX       16
+#define AU1300_DSCR_CMD0_PSC1_RX       17
+#define AU1300_DSCR_CMD0_PSC2_TX       18
+#define AU1300_DSCR_CMD0_PSC2_RX       19
+#define AU1300_DSCR_CMD0_PSC3_TX       20
+#define AU1300_DSCR_CMD0_PSC3_RX       21
+#define AU1300_DSCR_CMD0_LCD           22
+#define AU1300_DSCR_CMD0_NAND_FLASH    23
+#define AU1300_DSCR_CMD0_SDMS_TX2      24
+#define AU1300_DSCR_CMD0_SDMS_RX2      25
+#define AU1300_DSCR_CMD0_CIM_SYNC      26
+#define AU1300_DSCR_CMD0_UDMA          27
+#define AU1300_DSCR_CMD0_DMA_REQ0      28
+#define AU1300_DSCR_CMD0_DMA_REQ1      29
+
 #define DSCR_CMD0_THROTTLE      30
 #define DSCR_CMD0_ALWAYS        31
 #define DSCR_NDEV_IDS           32
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index d5df0cab9b87..3f741af37d47 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -13,12 +13,14 @@
 #define cpu_has_4k_cache                1
 #define cpu_has_tx39_cache              0
 #define cpu_has_fpu                     0
+#define cpu_has_32fpr                   0
 #define cpu_has_counter                 1
 #define cpu_has_watch                   1
 #define cpu_has_divec                   1
 #define cpu_has_vce                     0
 #define cpu_has_cache_cdex_p            0
 #define cpu_has_cache_cdex_s            0
+#define cpu_has_prefetch                1
 #define cpu_has_mcheck                  1
 #define cpu_has_ejtag                   1
 #define cpu_has_llsc                    1
@@ -29,6 +31,7 @@
 #define cpu_has_vtag_icache             0
 #define cpu_has_dc_aliases              0
 #define cpu_has_ic_fills_f_dc           1
+#define cpu_has_pindexed_dcache         0
 #define cpu_has_mips32r1                1
 #define cpu_has_mips32r2                0
 #define cpu_has_mips64r1                0
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
new file mode 100644
index 000000000000..556e1be20bf6
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
@@ -0,0 +1,241 @@
+/*
+ * gpio-au1300.h -- GPIO control for Au1300 GPIC and compatibles.
+ *
+ * Copyright (c) 2009-2011 Manuel Lauss <manuel.lauss@googlemail.com>
+ */
+
+#ifndef _GPIO_AU1300_H_
+#define _GPIO_AU1300_H_
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/mach-au1x00/au1000.h>
+
+/* with the current GPIC design, up to 128 GPIOs are possible.
+ * The only implementation so far is in the Au1300, which has 75 externally
+ * available GPIOs.
+ */
+#define AU1300_GPIO_BASE        0
+#define AU1300_GPIO_NUM         75
+#define AU1300_GPIO_MAX         (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1)
+
+#define AU1300_GPIC_ADDR        \
+        (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR)
+
+static inline int au1300_gpio_get_value(unsigned int gpio)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        int bit;
+
+        gpio -= AU1300_GPIO_BASE;
+        roff += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit;
+}
+
+static inline int au1300_gpio_direction_input(unsigned int gpio)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        unsigned long bit;
+
+        gpio -= AU1300_GPIO_BASE;
+
+        roff += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        __raw_writel(bit, roff + AU1300_GPIC_DEVCLR);
+        wmb();
+
+        return 0;
+}
+
+static inline int au1300_gpio_set_value(unsigned int gpio, int v)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        unsigned long bit;
+
+        gpio -= AU1300_GPIO_BASE;
+
+        roff += GPIC_GPIO_BANKOFF(gpio);
+        bit = GPIC_GPIO_TO_BIT(gpio);
+        __raw_writel(bit, roff + (v ? AU1300_GPIC_PINVAL
+                                    : AU1300_GPIC_PINVALCLR));
+        wmb();
+
+        return 0;
+}
+
+static inline int au1300_gpio_direction_output(unsigned int gpio, int v)
+{
+        /* hw switches to output automatically */
+        return au1300_gpio_set_value(gpio, v);
+}
+
+static inline int au1300_gpio_to_irq(unsigned int gpio)
+{
+        return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE);
+}
+
+static inline int au1300_irq_to_gpio(unsigned int irq)
+{
+        return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE;
+}
+
+static inline int au1300_gpio_is_valid(unsigned int gpio)
+{
+        int ret;
+
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1300:
+                ret = ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX));
+                break;
+        default:
+                ret = 0;
+        }
+        return ret;
+}
+
+static inline int au1300_gpio_cansleep(unsigned int gpio)
+{
+        return 0;
+}
+
+/* hardware remembers gpio 0-63 levels on powerup */
+static inline int au1300_gpio_getinitlvl(unsigned int gpio)
+{
+        void __iomem *roff = AU1300_GPIC_ADDR;
+        unsigned long v;
+
+        if (unlikely(gpio > 63))
+                return 0;
+        else if (gpio > 31) {
+                gpio -= 32;
+                roff += 4;
+        }
+
+        v = __raw_readl(roff + AU1300_GPIC_RSTVAL);
+        return (v >> gpio) & 1;
+}
+
+/**********************************************************************/
+
+/* Linux gpio framework integration.
+*
+* 4 use cases of Alchemy GPIOS:
+*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
+*       Board must register gpiochips.
+*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
+*       A gpiochip for the 75 GPIOs is registered.
+*
+*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
+*       the boards' gpio.h must provide the linux gpio wrapper functions,
+*
+*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
+*       inlinable gpio functions are provided which enable access to the
+*       Au1300 gpios only by using the numbers straight out of the data-
+*       sheets.
+
+* Cases 1 and 3 are intended for boards which want to provide their own
+* GPIO namespace and -operations (i.e. for example you have 8 GPIOs
+* which are in part provided by spare Au1300 GPIO pins and in part by
+* an external FPGA but you still want them to be accssible in linux
+* as gpio0-7. The board can of course use the alchemy_gpioX_* functions
+* as required).
+*/
+
+#ifndef CONFIG_GPIOLIB
+
+#ifdef CONFIG_ALCHEMY_GPIOINT_AU1300
+
+#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT    /* case (4) */
+
+static inline int gpio_direction_input(unsigned int gpio)
+{
+        return au1300_gpio_direction_input(gpio);
+}
+
+static inline int gpio_direction_output(unsigned int gpio, int v)
+{
+        return au1300_gpio_direction_output(gpio, v);
+}
+
+static inline int gpio_get_value(unsigned int gpio)
+{
+        return au1300_gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int v)
+{
+        au1300_gpio_set_value(gpio, v);
+}
+
+static inline int gpio_get_value_cansleep(unsigned gpio)
+{
+        return gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value_cansleep(unsigned gpio, int value)
+{
+        gpio_set_value(gpio, value);
+}
+
+static inline int gpio_is_valid(unsigned int gpio)
+{
+        return au1300_gpio_is_valid(gpio);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+        return au1300_gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned int gpio)
+{
+        return au1300_gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+        return au1300_irq_to_gpio(irq);
+}
+
+static inline int gpio_request(unsigned int gpio, const char *label)
+{
+        return 0;
+}
+
+static inline void gpio_free(unsigned int gpio)
+{
+}
+
+static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
+{
+        return -ENOSYS;
+}
+
+static inline void gpio_unexport(unsigned gpio)
+{
+}
+
+static inline int gpio_export(unsigned gpio, bool direction_may_change)
+{
+        return -ENOSYS;
+}
+
+static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
+{
+        return -ENOSYS;
+}
+
+static inline int gpio_export_link(struct device *dev, const char *name,
+                                   unsigned gpio)
+{
+        return -ENOSYS;
+}
+
+#endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
+
+#endif  /* CONFIG_ALCHEMY_GPIOINT_AU1300 */
+
+#endif  /* CONFIG GPIOLIB */
+
+#endif /* _GPIO_AU1300_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index fcdc8c4809db..22e7ff17fc48 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -12,6 +12,7 @@
 
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/gpio-au1000.h>
+#include <asm/mach-au1x00/gpio-au1300.h>
 
 /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
  * SYS_PININPUTEN is written to at least once.  On Au1550/Au1200/Au1300 this
@@ -58,6 +59,8 @@ static inline int __au_irq_to_gpio(unsigned int irq)
         switch (alchemy_get_cputype()) {
         case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
                 return alchemy_irq_to_gpio(irq);
+        case ALCHEMY_CPU_AU1300:
+                return au1300_irq_to_gpio(irq);
         }
         return -EINVAL;
 }
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 96a2391ad85b..5b8d15bb5fe8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,6 +13,7 @@
 #define BCM6345_CPU_ID          0x6345
 #define BCM6348_CPU_ID          0x6348
 #define BCM6358_CPU_ID          0x6358
+#define BCM6368_CPU_ID          0x6368
 
 void __init bcm63xx_cpu_init(void);
 u16 __bcm63xx_get_cpu_id(void);
@@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
 # define BCMCPU_IS_6358()       (0)
 #endif
 
+#ifdef CONFIG_BCM63XX_CPU_6368
+# ifdef bcm63xx_get_cpu_id
+#  undef bcm63xx_get_cpu_id
+#  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
+#  define BCMCPU_RUNTIME_DETECT
+# else
+#  define bcm63xx_get_cpu_id()  BCM6368_CPU_ID
+# endif
+# define BCMCPU_IS_6368()       (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
+#else
+# define BCMCPU_IS_6368()       (0)
+#endif
+
 #ifndef bcm63xx_get_cpu_id
 #error "No CPU support configured"
 #endif
@@ -88,6 +102,7 @@ enum bcm63xx_regs_set {
         RSET_UART1,
         RSET_GPIO,
         RSET_SPI,
+        RSET_SPI2,
         RSET_UDC0,
         RSET_OHCI0,
         RSET_OHCI_PRIV,
@@ -98,10 +113,23 @@ enum bcm63xx_regs_set {
         RSET_ENET0,
         RSET_ENET1,
         RSET_ENETDMA,
+        RSET_ENETDMAC,
+        RSET_ENETDMAS,
+        RSET_ENETSW,
         RSET_EHCI0,
         RSET_SDRAM,
         RSET_MEMC,
         RSET_DDR,
+        RSET_M2M,
+        RSET_ATM,
+        RSET_XTM,
+        RSET_XTMDMA,
+        RSET_XTMDMAC,
+        RSET_XTMDMAS,
+        RSET_PCM,
+        RSET_PCMDMA,
+        RSET_PCMDMAC,
+        RSET_PCMDMAS,
 };
 
 #define RSET_DSL_LMEM_SIZE              (64 * 1024 * 4)
@@ -109,11 +137,18 @@ enum bcm63xx_regs_set {
 #define RSET_WDT_SIZE                   12
 #define RSET_ENET_SIZE                  2048
 #define RSET_ENETDMA_SIZE               2048
+#define RSET_ENETSW_SIZE                65536
 #define RSET_UART_SIZE                  24
 #define RSET_UDC_SIZE                   256
 #define RSET_OHCI_SIZE                  256
 #define RSET_EHCI_SIZE                  256
 #define RSET_PCMCIA_SIZE                12
+#define RSET_M2M_SIZE                   256
+#define RSET_ATM_SIZE                   4096
+#define RSET_XTM_SIZE                   10240
+#define RSET_XTMDMA_SIZE                256
+#define RSET_XTMDMAC_SIZE(chans)        (16 * (chans))
+#define RSET_XTMDMAS_SIZE(chans)        (16 * (chans))
 
 /*
  * 6338 register sets base address
@@ -127,6 +162,7 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UART1_BASE             (0xdeadbeef)
 #define BCM_6338_GPIO_BASE              (0xfffe0400)
 #define BCM_6338_SPI_BASE               (0xfffe0c00)
+#define BCM_6338_SPI2_BASE              (0xdeadbeef)
 #define BCM_6338_UDC0_BASE              (0xdeadbeef)
 #define BCM_6338_USBDMA_BASE            (0xfffe2400)
 #define BCM_6338_OHCI0_BASE             (0xdeadbeef)
@@ -136,15 +172,27 @@ enum bcm63xx_regs_set {
 #define BCM_6338_PCMCIA_BASE            (0xdeadbeef)
 #define BCM_6338_SDRAM_REGS_BASE        (0xfffe3100)
 #define BCM_6338_DSL_BASE               (0xfffe1000)
-#define BCM_6338_SAR_BASE               (0xfffe2000)
 #define BCM_6338_UBUS_BASE              (0xdeadbeef)
 #define BCM_6338_ENET0_BASE             (0xfffe2800)
 #define BCM_6338_ENET1_BASE             (0xdeadbeef)
 #define BCM_6338_ENETDMA_BASE           (0xfffe2400)
+#define BCM_6338_ENETDMAC_BASE          (0xfffe2500)
+#define BCM_6338_ENETDMAS_BASE          (0xfffe2600)
+#define BCM_6338_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6338_EHCI0_BASE             (0xdeadbeef)
 #define BCM_6338_SDRAM_BASE             (0xfffe3100)
 #define BCM_6338_MEMC_BASE              (0xdeadbeef)
 #define BCM_6338_DDR_BASE               (0xdeadbeef)
+#define BCM_6338_M2M_BASE               (0xdeadbeef)
+#define BCM_6338_ATM_BASE               (0xfffe2000)
+#define BCM_6338_XTM_BASE               (0xdeadbeef)
+#define BCM_6338_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6338_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6338_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6338_PCM_BASE               (0xdeadbeef)
+#define BCM_6338_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6338_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6338_PCMDMAS_BASE           (0xdeadbeef)
 
 /*
  * 6345 register sets base address
@@ -158,24 +206,37 @@ enum bcm63xx_regs_set {
 #define BCM_6345_UART1_BASE             (0xdeadbeef)
 #define BCM_6345_GPIO_BASE              (0xfffe0400)
 #define BCM_6345_SPI_BASE               (0xdeadbeef)
+#define BCM_6345_SPI2_BASE              (0xdeadbeef)
 #define BCM_6345_UDC0_BASE              (0xdeadbeef)
 #define BCM_6345_USBDMA_BASE            (0xfffe2800)
 #define BCM_6345_ENET0_BASE             (0xfffe1800)
 #define BCM_6345_ENETDMA_BASE           (0xfffe2800)
+#define BCM_6345_ENETDMAC_BASE          (0xfffe2900)
+#define BCM_6345_ENETDMAS_BASE          (0xfffe2a00)
+#define BCM_6345_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6345_PCMCIA_BASE            (0xfffe2028)
-#define BCM_6345_MPI_BASE               (0xdeadbeef)
+#define BCM_6345_MPI_BASE               (0xfffe2000)
 #define BCM_6345_OHCI0_BASE             (0xfffe2100)
 #define BCM_6345_OHCI_PRIV_BASE         (0xfffe2200)
 #define BCM_6345_USBH_PRIV_BASE         (0xdeadbeef)
 #define BCM_6345_SDRAM_REGS_BASE        (0xfffe2300)
 #define BCM_6345_DSL_BASE               (0xdeadbeef)
-#define BCM_6345_SAR_BASE               (0xdeadbeef)
 #define BCM_6345_UBUS_BASE              (0xdeadbeef)
 #define BCM_6345_ENET1_BASE             (0xdeadbeef)
 #define BCM_6345_EHCI0_BASE             (0xdeadbeef)
 #define BCM_6345_SDRAM_BASE             (0xfffe2300)
 #define BCM_6345_MEMC_BASE              (0xdeadbeef)
 #define BCM_6345_DDR_BASE               (0xdeadbeef)
+#define BCM_6345_M2M_BASE               (0xdeadbeef)
+#define BCM_6345_ATM_BASE               (0xfffe4000)
+#define BCM_6345_XTM_BASE               (0xdeadbeef)
+#define BCM_6345_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6345_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6345_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6345_PCM_BASE               (0xdeadbeef)
+#define BCM_6345_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6345_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6345_PCMDMAS_BASE           (0xdeadbeef)
 
 /*
  * 6348 register sets base address
@@ -188,6 +249,7 @@ enum bcm63xx_regs_set {
 #define BCM_6348_UART1_BASE             (0xdeadbeef)
 #define BCM_6348_GPIO_BASE              (0xfffe0400)
 #define BCM_6348_SPI_BASE               (0xfffe0c00)
+#define BCM_6348_SPI2_BASE              (0xdeadbeef)
 #define BCM_6348_UDC0_BASE              (0xfffe1000)
 #define BCM_6348_OHCI0_BASE             (0xfffe1b00)
 #define BCM_6348_OHCI_PRIV_BASE         (0xfffe1c00)
@@ -195,14 +257,27 @@ enum bcm63xx_regs_set {
 #define BCM_6348_MPI_BASE               (0xfffe2000)
 #define BCM_6348_PCMCIA_BASE            (0xfffe2054)
 #define BCM_6348_SDRAM_REGS_BASE        (0xfffe2300)
+#define BCM_6348_M2M_BASE               (0xfffe2800)
 #define BCM_6348_DSL_BASE               (0xfffe3000)
 #define BCM_6348_ENET0_BASE             (0xfffe6000)
 #define BCM_6348_ENET1_BASE             (0xfffe6800)
 #define BCM_6348_ENETDMA_BASE           (0xfffe7000)
+#define BCM_6348_ENETDMAC_BASE          (0xfffe7100)
+#define BCM_6348_ENETDMAS_BASE          (0xfffe7200)
+#define BCM_6348_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6348_EHCI0_BASE             (0xdeadbeef)
 #define BCM_6348_SDRAM_BASE             (0xfffe2300)
 #define BCM_6348_MEMC_BASE              (0xdeadbeef)
 #define BCM_6348_DDR_BASE               (0xdeadbeef)
+#define BCM_6348_ATM_BASE               (0xfffe4000)
+#define BCM_6348_XTM_BASE               (0xdeadbeef)
+#define BCM_6348_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6348_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6348_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6348_PCM_BASE               (0xdeadbeef)
+#define BCM_6348_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6348_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6348_PCMDMAS_BASE           (0xdeadbeef)
 
 /*
  * 6358 register sets base address
@@ -215,6 +290,7 @@ enum bcm63xx_regs_set {
 #define BCM_6358_UART1_BASE             (0xfffe0120)
 #define BCM_6358_GPIO_BASE              (0xfffe0080)
 #define BCM_6358_SPI_BASE               (0xdeadbeef)
+#define BCM_6358_SPI2_BASE              (0xfffe0800)
 #define BCM_6358_UDC0_BASE              (0xfffe0800)
 #define BCM_6358_OHCI0_BASE             (0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE         (0xdeadbeef)
@@ -222,214 +298,175 @@ enum bcm63xx_regs_set {
 #define BCM_6358_MPI_BASE               (0xfffe1000)
 #define BCM_6358_PCMCIA_BASE            (0xfffe1054)
 #define BCM_6358_SDRAM_REGS_BASE        (0xfffe2300)
+#define BCM_6358_M2M_BASE               (0xdeadbeef)
 #define BCM_6358_DSL_BASE               (0xfffe3000)
 #define BCM_6358_ENET0_BASE             (0xfffe4000)
 #define BCM_6358_ENET1_BASE             (0xfffe4800)
 #define BCM_6358_ENETDMA_BASE           (0xfffe5000)
+#define BCM_6358_ENETDMAC_BASE          (0xfffe5100)
+#define BCM_6358_ENETDMAS_BASE          (0xfffe5200)
+#define BCM_6358_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6358_EHCI0_BASE             (0xfffe1300)
 #define BCM_6358_SDRAM_BASE             (0xdeadbeef)
 #define BCM_6358_MEMC_BASE              (0xfffe1200)
 #define BCM_6358_DDR_BASE               (0xfffe12a0)
+#define BCM_6358_ATM_BASE               (0xfffe2000)
+#define BCM_6358_XTM_BASE               (0xdeadbeef)
+#define BCM_6358_XTMDMA_BASE            (0xdeadbeef)
+#define BCM_6358_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6358_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6358_PCM_BASE               (0xfffe1600)
+#define BCM_6358_PCMDMA_BASE            (0xfffe1800)
+#define BCM_6358_PCMDMAC_BASE           (0xfffe1900)
+#define BCM_6358_PCMDMAS_BASE           (0xfffe1a00)
+
+
+/*
+ * 6368 register sets base address
+ */
+#define BCM_6368_DSL_LMEM_BASE          (0xdeadbeef)
+#define BCM_6368_PERF_BASE              (0xb0000000)
+#define BCM_6368_TIMER_BASE             (0xb0000040)
+#define BCM_6368_WDT_BASE               (0xb000005c)
+#define BCM_6368_UART0_BASE             (0xb0000100)
+#define BCM_6368_UART1_BASE             (0xb0000120)
+#define BCM_6368_GPIO_BASE              (0xb0000080)
+#define BCM_6368_SPI_BASE               (0xdeadbeef)
+#define BCM_6368_SPI2_BASE              (0xb0000800)
+#define BCM_6368_UDC0_BASE              (0xdeadbeef)
+#define BCM_6368_OHCI0_BASE             (0xb0001600)
+#define BCM_6368_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_6368_USBH_PRIV_BASE         (0xb0001700)
+#define BCM_6368_MPI_BASE               (0xb0001000)
+#define BCM_6368_PCMCIA_BASE            (0xb0001054)
+#define BCM_6368_SDRAM_REGS_BASE        (0xdeadbeef)
+#define BCM_6368_M2M_BASE               (0xdeadbeef)
+#define BCM_6368_DSL_BASE               (0xdeadbeef)
+#define BCM_6368_ENET0_BASE             (0xdeadbeef)
+#define BCM_6368_ENET1_BASE             (0xdeadbeef)
+#define BCM_6368_ENETDMA_BASE           (0xb0006800)
+#define BCM_6368_ENETDMAC_BASE          (0xb0006a00)
+#define BCM_6368_ENETDMAS_BASE          (0xb0006c00)
+#define BCM_6368_ENETSW_BASE            (0xb0f00000)
+#define BCM_6368_EHCI0_BASE             (0xb0001500)
+#define BCM_6368_SDRAM_BASE             (0xdeadbeef)
+#define BCM_6368_MEMC_BASE              (0xb0001200)
+#define BCM_6368_DDR_BASE               (0xb0001280)
+#define BCM_6368_ATM_BASE               (0xdeadbeef)
+#define BCM_6368_XTM_BASE               (0xb0001800)
+#define BCM_6368_XTMDMA_BASE            (0xb0005000)
+#define BCM_6368_XTMDMAC_BASE           (0xb0005200)
+#define BCM_6368_XTMDMAS_BASE           (0xb0005400)
+#define BCM_6368_PCM_BASE               (0xb0004000)
+#define BCM_6368_PCMDMA_BASE            (0xb0005800)
+#define BCM_6368_PCMDMAC_BASE           (0xb0005a00)
+#define BCM_6368_PCMDMAS_BASE           (0xb0005c00)
 
 
 extern const unsigned long *bcm63xx_regs_base;
 
+#define __GEN_RSET_BASE(__cpu, __rset)                                  \
+        case RSET_## __rset :                                           \
+                return BCM_## __cpu ##_## __rset ##_BASE;
+
+#define __GEN_RSET(__cpu)                                               \
+        switch (set) {                                                  \
+        __GEN_RSET_BASE(__cpu, DSL_LMEM)                                \
+        __GEN_RSET_BASE(__cpu, PERF)                                    \
+        __GEN_RSET_BASE(__cpu, TIMER)                                   \
+        __GEN_RSET_BASE(__cpu, WDT)                                     \
+        __GEN_RSET_BASE(__cpu, UART0)                                   \
+        __GEN_RSET_BASE(__cpu, UART1)                                   \
+        __GEN_RSET_BASE(__cpu, GPIO)                                    \
+        __GEN_RSET_BASE(__cpu, SPI)                                     \
+        __GEN_RSET_BASE(__cpu, SPI2)                                    \
+        __GEN_RSET_BASE(__cpu, UDC0)                                    \
+        __GEN_RSET_BASE(__cpu, OHCI0)                                   \
+        __GEN_RSET_BASE(__cpu, OHCI_PRIV)                               \
+        __GEN_RSET_BASE(__cpu, USBH_PRIV)                               \
+        __GEN_RSET_BASE(__cpu, MPI)                                     \
+        __GEN_RSET_BASE(__cpu, PCMCIA)                                  \
+        __GEN_RSET_BASE(__cpu, DSL)                                     \
+        __GEN_RSET_BASE(__cpu, ENET0)                                   \
+        __GEN_RSET_BASE(__cpu, ENET1)                                   \
+        __GEN_RSET_BASE(__cpu, ENETDMA)                                 \
+        __GEN_RSET_BASE(__cpu, ENETDMAC)                                \
+        __GEN_RSET_BASE(__cpu, ENETDMAS)                                \
+        __GEN_RSET_BASE(__cpu, ENETSW)                                  \
+        __GEN_RSET_BASE(__cpu, EHCI0)                                   \
+        __GEN_RSET_BASE(__cpu, SDRAM)                                   \
+        __GEN_RSET_BASE(__cpu, MEMC)                                    \
+        __GEN_RSET_BASE(__cpu, DDR)                                     \
+        __GEN_RSET_BASE(__cpu, M2M)                                     \
+        __GEN_RSET_BASE(__cpu, ATM)                                     \
+        __GEN_RSET_BASE(__cpu, XTM)                                     \
+        __GEN_RSET_BASE(__cpu, XTMDMA)                                  \
+        __GEN_RSET_BASE(__cpu, XTMDMAC)                                 \
+        __GEN_RSET_BASE(__cpu, XTMDMAS)                                 \
+        __GEN_RSET_BASE(__cpu, PCM)                                     \
+        __GEN_RSET_BASE(__cpu, PCMDMA)                                  \
+        __GEN_RSET_BASE(__cpu, PCMDMAC)                                 \
+        __GEN_RSET_BASE(__cpu, PCMDMAS)                                 \
+        }
+
+#define __GEN_CPU_REGS_TABLE(__cpu)                                     \
+        [RSET_DSL_LMEM]         = BCM_## __cpu ##_DSL_LMEM_BASE,        \
+        [RSET_PERF]             = BCM_## __cpu ##_PERF_BASE,            \
+        [RSET_TIMER]            = BCM_## __cpu ##_TIMER_BASE,           \
+        [RSET_WDT]              = BCM_## __cpu ##_WDT_BASE,             \
+        [RSET_UART0]            = BCM_## __cpu ##_UART0_BASE,           \
+        [RSET_UART1]            = BCM_## __cpu ##_UART1_BASE,           \
+        [RSET_GPIO]             = BCM_## __cpu ##_GPIO_BASE,            \
+        [RSET_SPI]              = BCM_## __cpu ##_SPI_BASE,             \
+        [RSET_SPI2]             = BCM_## __cpu ##_SPI2_BASE,            \
+        [RSET_UDC0]             = BCM_## __cpu ##_UDC0_BASE,            \
+        [RSET_OHCI0]            = BCM_## __cpu ##_OHCI0_BASE,           \
+        [RSET_OHCI_PRIV]        = BCM_## __cpu ##_OHCI_PRIV_BASE,       \
+        [RSET_USBH_PRIV]        = BCM_## __cpu ##_USBH_PRIV_BASE,       \
+        [RSET_MPI]              = BCM_## __cpu ##_MPI_BASE,             \
+        [RSET_PCMCIA]           = BCM_## __cpu ##_PCMCIA_BASE,          \
+        [RSET_DSL]              = BCM_## __cpu ##_DSL_BASE,             \
+        [RSET_ENET0]            = BCM_## __cpu ##_ENET0_BASE,           \
+        [RSET_ENET1]            = BCM_## __cpu ##_ENET1_BASE,           \
+        [RSET_ENETDMA]          = BCM_## __cpu ##_ENETDMA_BASE,         \
+        [RSET_ENETDMAC]         = BCM_## __cpu ##_ENETDMAC_BASE,        \
+        [RSET_ENETDMAS]         = BCM_## __cpu ##_ENETDMAS_BASE,        \
+        [RSET_ENETSW]           = BCM_## __cpu ##_ENETSW_BASE,          \
+        [RSET_EHCI0]            = BCM_## __cpu ##_EHCI0_BASE,           \
+        [RSET_SDRAM]            = BCM_## __cpu ##_SDRAM_BASE,           \
+        [RSET_MEMC]             = BCM_## __cpu ##_MEMC_BASE,            \
+        [RSET_DDR]              = BCM_## __cpu ##_DDR_BASE,             \
+        [RSET_M2M]              = BCM_## __cpu ##_M2M_BASE,             \
+        [RSET_ATM]              = BCM_## __cpu ##_ATM_BASE,             \
+        [RSET_XTM]              = BCM_## __cpu ##_XTM_BASE,             \
+        [RSET_XTMDMA]           = BCM_## __cpu ##_XTMDMA_BASE,          \
+        [RSET_XTMDMAC]          = BCM_## __cpu ##_XTMDMAC_BASE,         \
+        [RSET_XTMDMAS]          = BCM_## __cpu ##_XTMDMAS_BASE,         \
+        [RSET_PCM]              = BCM_## __cpu ##_PCM_BASE,             \
+        [RSET_PCMDMA]           = BCM_## __cpu ##_PCMDMA_BASE,          \
+        [RSET_PCMDMAC]          = BCM_## __cpu ##_PCMDMAC_BASE,         \
+        [RSET_PCMDMAS]          = BCM_## __cpu ##_PCMDMAS_BASE,         \
+
+
 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 {
 #ifdef BCMCPU_RUNTIME_DETECT
         return bcm63xx_regs_base[set];
 #else
 #ifdef CONFIG_BCM63XX_CPU_6338
-        switch (set) {
-        case RSET_DSL_LMEM:
-                return BCM_6338_DSL_LMEM_BASE;
-        case RSET_PERF:
-                return BCM_6338_PERF_BASE;
-        case RSET_TIMER:
-                return BCM_6338_TIMER_BASE;
-        case RSET_WDT:
-                return BCM_6338_WDT_BASE;
-        case RSET_UART0:
-                return BCM_6338_UART0_BASE;
-        case RSET_UART1:
-                return BCM_6338_UART1_BASE;
-        case RSET_GPIO:
-                return BCM_6338_GPIO_BASE;
-        case RSET_SPI:
-                return BCM_6338_SPI_BASE;
-        case RSET_UDC0:
-                return BCM_6338_UDC0_BASE;
-        case RSET_OHCI0:
-                return BCM_6338_OHCI0_BASE;
-        case RSET_OHCI_PRIV:
-                return BCM_6338_OHCI_PRIV_BASE;
-        case RSET_USBH_PRIV:
-                return BCM_6338_USBH_PRIV_BASE;
-        case RSET_MPI:
-                return BCM_6338_MPI_BASE;
-        case RSET_PCMCIA:
-                return BCM_6338_PCMCIA_BASE;
-        case RSET_DSL:
-                return BCM_6338_DSL_BASE;
-        case RSET_ENET0:
-                return BCM_6338_ENET0_BASE;
-        case RSET_ENET1:
-                return BCM_6338_ENET1_BASE;
-        case RSET_ENETDMA:
-                return BCM_6338_ENETDMA_BASE;
-        case RSET_EHCI0:
-                return BCM_6338_EHCI0_BASE;
-        case RSET_SDRAM:
-                return BCM_6338_SDRAM_BASE;
-        case RSET_MEMC:
-                return BCM_6338_MEMC_BASE;
-        case RSET_DDR:
-                return BCM_6338_DDR_BASE;
-        }
+        __GEN_RSET(6338)
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6345
-        switch (set) {
-        case RSET_DSL_LMEM:
-                return BCM_6345_DSL_LMEM_BASE;
-        case RSET_PERF:
-                return BCM_6345_PERF_BASE;
-        case RSET_TIMER:
-                return BCM_6345_TIMER_BASE;
-        case RSET_WDT:
-                return BCM_6345_WDT_BASE;
-        case RSET_UART0:
-                return BCM_6345_UART0_BASE;
-        case RSET_UART1:
-                return BCM_6345_UART1_BASE;
-        case RSET_GPIO:
-                return BCM_6345_GPIO_BASE;
-        case RSET_SPI:
-                return BCM_6345_SPI_BASE;
-        case RSET_UDC0:
-                return BCM_6345_UDC0_BASE;
-        case RSET_OHCI0:
-                return BCM_6345_OHCI0_BASE;
-        case RSET_OHCI_PRIV:
-                return BCM_6345_OHCI_PRIV_BASE;
-        case RSET_USBH_PRIV:
-                return BCM_6345_USBH_PRIV_BASE;
-        case RSET_MPI:
-                return BCM_6345_MPI_BASE;
-        case RSET_PCMCIA:
-                return BCM_6345_PCMCIA_BASE;
-        case RSET_DSL:
-                return BCM_6345_DSL_BASE;
-        case RSET_ENET0:
-                return BCM_6345_ENET0_BASE;
-        case RSET_ENET1:
-                return BCM_6345_ENET1_BASE;
-        case RSET_ENETDMA:
-                return BCM_6345_ENETDMA_BASE;
-        case RSET_EHCI0:
-                return BCM_6345_EHCI0_BASE;
-        case RSET_SDRAM:
-                return BCM_6345_SDRAM_BASE;
-        case RSET_MEMC:
-                return BCM_6345_MEMC_BASE;
-        case RSET_DDR:
-                return BCM_6345_DDR_BASE;
-        }
+        __GEN_RSET(6345)
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6348
-        switch (set) {
-        case RSET_DSL_LMEM:
-                return BCM_6348_DSL_LMEM_BASE;
-        case RSET_PERF:
-                return BCM_6348_PERF_BASE;
-        case RSET_TIMER:
-                return BCM_6348_TIMER_BASE;
-        case RSET_WDT:
-                return BCM_6348_WDT_BASE;
-        case RSET_UART0:
-                return BCM_6348_UART0_BASE;
-        case RSET_UART1:
-                return BCM_6348_UART1_BASE;
-        case RSET_GPIO:
-                return BCM_6348_GPIO_BASE;
-        case RSET_SPI:
-                return BCM_6348_SPI_BASE;
-        case RSET_UDC0:
-                return BCM_6348_UDC0_BASE;
-        case RSET_OHCI0:
-                return BCM_6348_OHCI0_BASE;
-        case RSET_OHCI_PRIV:
-                return BCM_6348_OHCI_PRIV_BASE;
-        case RSET_USBH_PRIV:
-                return BCM_6348_USBH_PRIV_BASE;
-        case RSET_MPI:
-                return BCM_6348_MPI_BASE;
-        case RSET_PCMCIA:
-                return BCM_6348_PCMCIA_BASE;
-        case RSET_DSL:
-                return BCM_6348_DSL_BASE;
-        case RSET_ENET0:
-                return BCM_6348_ENET0_BASE;
-        case RSET_ENET1:
-                return BCM_6348_ENET1_BASE;
-        case RSET_ENETDMA:
-                return BCM_6348_ENETDMA_BASE;
-        case RSET_EHCI0:
-                return BCM_6348_EHCI0_BASE;
-        case RSET_SDRAM:
-                return BCM_6348_SDRAM_BASE;
-        case RSET_MEMC:
-                return BCM_6348_MEMC_BASE;
-        case RSET_DDR:
-                return BCM_6348_DDR_BASE;
-        }
+        __GEN_RSET(6348)
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6358
-        switch (set) {
-        case RSET_DSL_LMEM:
-                return BCM_6358_DSL_LMEM_BASE;
-        case RSET_PERF:
-                return BCM_6358_PERF_BASE;
-        case RSET_TIMER:
-                return BCM_6358_TIMER_BASE;
-        case RSET_WDT:
-                return BCM_6358_WDT_BASE;
-        case RSET_UART0:
-                return BCM_6358_UART0_BASE;
-        case RSET_UART1:
-                return BCM_6358_UART1_BASE;
-        case RSET_GPIO:
-                return BCM_6358_GPIO_BASE;
-        case RSET_SPI:
-                return BCM_6358_SPI_BASE;
-        case RSET_UDC0:
-                return BCM_6358_UDC0_BASE;
-        case RSET_OHCI0:
-                return BCM_6358_OHCI0_BASE;
-        case RSET_OHCI_PRIV:
-                return BCM_6358_OHCI_PRIV_BASE;
-        case RSET_USBH_PRIV:
-                return BCM_6358_USBH_PRIV_BASE;
-        case RSET_MPI:
-                return BCM_6358_MPI_BASE;
-        case RSET_PCMCIA:
-                return BCM_6358_PCMCIA_BASE;
-        case RSET_ENET0:
-                return BCM_6358_ENET0_BASE;
-        case RSET_ENET1:
-                return BCM_6358_ENET1_BASE;
-        case RSET_ENETDMA:
-                return BCM_6358_ENETDMA_BASE;
-        case RSET_DSL:
-                return BCM_6358_DSL_BASE;
-        case RSET_EHCI0:
-                return BCM_6358_EHCI0_BASE;
-        case RSET_SDRAM:
-                return BCM_6358_SDRAM_BASE;
-        case RSET_MEMC:
-                return BCM_6358_MEMC_BASE;
-        case RSET_DDR:
-                return BCM_6358_DDR_BASE;
-        }
+        __GEN_RSET(6358)
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6368
+        __GEN_RSET(6368)
 #endif
 #endif
         /* unreached */
@@ -449,75 +486,114 @@ enum bcm63xx_irq {
         IRQ_ENET_PHY,
         IRQ_OHCI0,
         IRQ_EHCI0,
-        IRQ_PCMCIA0,
         IRQ_ENET0_RXDMA,
         IRQ_ENET0_TXDMA,
         IRQ_ENET1_RXDMA,
         IRQ_ENET1_TXDMA,
         IRQ_PCI,
         IRQ_PCMCIA,
+        IRQ_ATM,
+        IRQ_ENETSW_RXDMA0,
+        IRQ_ENETSW_RXDMA1,
+        IRQ_ENETSW_RXDMA2,
+        IRQ_ENETSW_RXDMA3,
+        IRQ_ENETSW_TXDMA0,
+        IRQ_ENETSW_TXDMA1,
+        IRQ_ENETSW_TXDMA2,
+        IRQ_ENETSW_TXDMA3,
+        IRQ_XTM,
+        IRQ_XTM_DMA0,
 };
 
 /*
  * 6338 irqs
  */
 #define BCM_6338_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
-#define BCM_6338_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 #define BCM_6338_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
-#define BCM_6338_DG_IRQ                 (IRQ_INTERNAL_BASE + 4)
+#define BCM_6338_UART1_IRQ              0
 #define BCM_6338_DSL_IRQ                (IRQ_INTERNAL_BASE + 5)
-#define BCM_6338_ATM_IRQ                (IRQ_INTERNAL_BASE + 6)
-#define BCM_6338_UDC0_IRQ               (IRQ_INTERNAL_BASE + 7)
 #define BCM_6338_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6338_ENET1_IRQ              0
 #define BCM_6338_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
-#define BCM_6338_SDRAM_IRQ              (IRQ_INTERNAL_BASE + 10)
-#define BCM_6338_USB_CNTL_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 11)
-#define BCM_6338_USB_CNTL_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 12)
-#define BCM_6338_USB_BULK_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13)
-#define BCM_6338_USB_BULK_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 14)
+#define BCM_6338_OHCI0_IRQ              0
+#define BCM_6338_EHCI0_IRQ              0
 #define BCM_6338_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 #define BCM_6338_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
-#define BCM_6338_SDIO_IRQ               (IRQ_INTERNAL_BASE + 17)
+#define BCM_6338_ENET1_RXDMA_IRQ        0
+#define BCM_6338_ENET1_TXDMA_IRQ        0
+#define BCM_6338_PCI_IRQ                0
+#define BCM_6338_PCMCIA_IRQ             0
+#define BCM_6338_ATM_IRQ                0
+#define BCM_6338_ENETSW_RXDMA0_IRQ      0
+#define BCM_6338_ENETSW_RXDMA1_IRQ      0
+#define BCM_6338_ENETSW_RXDMA2_IRQ      0
+#define BCM_6338_ENETSW_RXDMA3_IRQ      0
+#define BCM_6338_ENETSW_TXDMA0_IRQ      0
+#define BCM_6338_ENETSW_TXDMA1_IRQ      0
+#define BCM_6338_ENETSW_TXDMA2_IRQ      0
+#define BCM_6338_ENETSW_TXDMA3_IRQ      0
+#define BCM_6338_XTM_IRQ                0
+#define BCM_6338_XTM_DMA0_IRQ           0
 
 /*
  * 6345 irqs
  */
 #define BCM_6345_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 #define BCM_6345_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6345_UART1_IRQ              0
 #define BCM_6345_DSL_IRQ                (IRQ_INTERNAL_BASE + 3)
-#define BCM_6345_ATM_IRQ                (IRQ_INTERNAL_BASE + 4)
-#define BCM_6345_USB_IRQ                (IRQ_INTERNAL_BASE + 5)
 #define BCM_6345_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6345_ENET1_IRQ              0
 #define BCM_6345_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
+#define BCM_6345_OHCI0_IRQ              0
+#define BCM_6345_EHCI0_IRQ              0
 #define BCM_6345_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 1)
 #define BCM_6345_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 2)
-#define BCM_6345_EBI_RX_IRQ             (IRQ_INTERNAL_BASE + 13 + 5)
-#define BCM_6345_EBI_TX_IRQ             (IRQ_INTERNAL_BASE + 13 + 6)
-#define BCM_6345_RESERVED_RX_IRQ        (IRQ_INTERNAL_BASE + 13 + 9)
-#define BCM_6345_RESERVED_TX_IRQ        (IRQ_INTERNAL_BASE + 13 + 10)
-#define BCM_6345_USB_BULK_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 13)
-#define BCM_6345_USB_BULK_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 14)
-#define BCM_6345_USB_CNTL_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 15)
-#define BCM_6345_USB_CNTL_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13 + 16)
-#define BCM_6345_USB_ISO_RX_DMA_IRQ     (IRQ_INTERNAL_BASE + 13 + 17)
-#define BCM_6345_USB_ISO_TX_DMA_IRQ     (IRQ_INTERNAL_BASE + 13 + 18)
+#define BCM_6345_ENET1_RXDMA_IRQ        0
+#define BCM_6345_ENET1_TXDMA_IRQ        0
+#define BCM_6345_PCI_IRQ                0
+#define BCM_6345_PCMCIA_IRQ             0
+#define BCM_6345_ATM_IRQ                0
+#define BCM_6345_ENETSW_RXDMA0_IRQ      0
+#define BCM_6345_ENETSW_RXDMA1_IRQ      0
+#define BCM_6345_ENETSW_RXDMA2_IRQ      0
+#define BCM_6345_ENETSW_RXDMA3_IRQ      0
+#define BCM_6345_ENETSW_TXDMA0_IRQ      0
+#define BCM_6345_ENETSW_TXDMA1_IRQ      0
+#define BCM_6345_ENETSW_TXDMA2_IRQ      0
+#define BCM_6345_ENETSW_TXDMA3_IRQ      0
+#define BCM_6345_XTM_IRQ                0
+#define BCM_6345_XTM_DMA0_IRQ           0
 
 /*
  * 6348 irqs
  */
 #define BCM_6348_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 #define BCM_6348_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6348_UART1_IRQ              0
 #define BCM_6348_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
-#define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
 #define BCM_6348_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
 #define BCM_6348_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 #define BCM_6348_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 12)
+#define BCM_6348_EHCI0_IRQ              0
 #define BCM_6348_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 20)
 #define BCM_6348_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 21)
 #define BCM_6348_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 22)
 #define BCM_6348_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 23)
-#define BCM_6348_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
 #define BCM_6348_PCI_IRQ                (IRQ_INTERNAL_BASE + 24)
+#define BCM_6348_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
+#define BCM_6348_ATM_IRQ                (IRQ_INTERNAL_BASE + 5)
+#define BCM_6348_ENETSW_RXDMA0_IRQ      0
+#define BCM_6348_ENETSW_RXDMA1_IRQ      0
+#define BCM_6348_ENETSW_RXDMA2_IRQ      0
+#define BCM_6348_ENETSW_RXDMA3_IRQ      0
+#define BCM_6348_ENETSW_TXDMA0_IRQ      0
+#define BCM_6348_ENETSW_TXDMA1_IRQ      0
+#define BCM_6348_ENETSW_TXDMA2_IRQ      0
+#define BCM_6348_ENETSW_TXDMA3_IRQ      0
+#define BCM_6348_XTM_IRQ                0
+#define BCM_6348_XTM_DMA0_IRQ           0
 
 /*
  * 6358 irqs
@@ -525,21 +601,108 @@ enum bcm63xx_irq {
 #define BCM_6358_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 #define BCM_6358_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 #define BCM_6358_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
-#define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
-#define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
+#define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
 #define BCM_6358_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
+#define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
 #define BCM_6358_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
+#define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
 #define BCM_6358_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 #define BCM_6358_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 #define BCM_6358_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
 #define BCM_6358_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
-#define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
 #define BCM_6358_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
 #define BCM_6358_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
+#define BCM_6358_ATM_IRQ                (IRQ_INTERNAL_BASE + 19)
+#define BCM_6358_ENETSW_RXDMA0_IRQ      0
+#define BCM_6358_ENETSW_RXDMA1_IRQ      0
+#define BCM_6358_ENETSW_RXDMA2_IRQ      0
+#define BCM_6358_ENETSW_RXDMA3_IRQ      0
+#define BCM_6358_ENETSW_TXDMA0_IRQ      0
+#define BCM_6358_ENETSW_TXDMA1_IRQ      0
+#define BCM_6358_ENETSW_TXDMA2_IRQ      0
+#define BCM_6358_ENETSW_TXDMA3_IRQ      0
+#define BCM_6358_XTM_IRQ                0
+#define BCM_6358_XTM_DMA0_IRQ           0
+
+#define BCM_6358_PCM_DMA0_IRQ           (IRQ_INTERNAL_BASE + 23)
+#define BCM_6358_PCM_DMA1_IRQ           (IRQ_INTERNAL_BASE + 24)
+#define BCM_6358_EXT_IRQ0               (IRQ_INTERNAL_BASE + 25)
+#define BCM_6358_EXT_IRQ1               (IRQ_INTERNAL_BASE + 26)
+#define BCM_6358_EXT_IRQ2               (IRQ_INTERNAL_BASE + 27)
+#define BCM_6358_EXT_IRQ3               (IRQ_INTERNAL_BASE + 28)
+
+/*
+ * 6368 irqs
+ */
+#define BCM_6368_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
+
+#define BCM_6368_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6368_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
+#define BCM_6368_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
+#define BCM_6368_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
+#define BCM_6368_ENET0_IRQ              0
+#define BCM_6368_ENET1_IRQ              0
+#define BCM_6368_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 15)
+#define BCM_6368_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
+#define BCM_6368_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 7)
+#define BCM_6368_PCMCIA_IRQ             0
+#define BCM_6368_ENET0_RXDMA_IRQ        0
+#define BCM_6368_ENET0_TXDMA_IRQ        0
+#define BCM_6368_ENET1_RXDMA_IRQ        0
+#define BCM_6368_ENET1_TXDMA_IRQ        0
+#define BCM_6368_PCI_IRQ                (IRQ_INTERNAL_BASE + 13)
+#define BCM_6368_ATM_IRQ                0
+#define BCM_6368_ENETSW_RXDMA0_IRQ      (BCM_6368_HIGH_IRQ_BASE + 0)
+#define BCM_6368_ENETSW_RXDMA1_IRQ      (BCM_6368_HIGH_IRQ_BASE + 1)
+#define BCM_6368_ENETSW_RXDMA2_IRQ      (BCM_6368_HIGH_IRQ_BASE + 2)
+#define BCM_6368_ENETSW_RXDMA3_IRQ      (BCM_6368_HIGH_IRQ_BASE + 3)
+#define BCM_6368_ENETSW_TXDMA0_IRQ      (BCM_6368_HIGH_IRQ_BASE + 4)
+#define BCM_6368_ENETSW_TXDMA1_IRQ      (BCM_6368_HIGH_IRQ_BASE + 5)
+#define BCM_6368_ENETSW_TXDMA2_IRQ      (BCM_6368_HIGH_IRQ_BASE + 6)
+#define BCM_6368_ENETSW_TXDMA3_IRQ      (BCM_6368_HIGH_IRQ_BASE + 7)
+#define BCM_6368_XTM_IRQ                (IRQ_INTERNAL_BASE + 11)
+#define BCM_6368_XTM_DMA0_IRQ           (BCM_6368_HIGH_IRQ_BASE + 8)
+
+#define BCM_6368_PCM_DMA0_IRQ           (BCM_6368_HIGH_IRQ_BASE + 30)
+#define BCM_6368_PCM_DMA1_IRQ           (BCM_6368_HIGH_IRQ_BASE + 31)
+#define BCM_6368_EXT_IRQ0               (IRQ_INTERNAL_BASE + 20)
+#define BCM_6368_EXT_IRQ1               (IRQ_INTERNAL_BASE + 21)
+#define BCM_6368_EXT_IRQ2               (IRQ_INTERNAL_BASE + 22)
+#define BCM_6368_EXT_IRQ3               (IRQ_INTERNAL_BASE + 23)
+#define BCM_6368_EXT_IRQ4               (IRQ_INTERNAL_BASE + 24)
+#define BCM_6368_EXT_IRQ5               (IRQ_INTERNAL_BASE + 25)
 
 extern const int *bcm63xx_irqs;
 
+#define __GEN_CPU_IRQ_TABLE(__cpu)                                      \
+        [IRQ_TIMER]             = BCM_## __cpu ##_TIMER_IRQ,            \
+        [IRQ_UART0]             = BCM_## __cpu ##_UART0_IRQ,            \
+        [IRQ_UART1]             = BCM_## __cpu ##_UART1_IRQ,            \
+        [IRQ_DSL]               = BCM_## __cpu ##_DSL_IRQ,              \
+        [IRQ_ENET0]             = BCM_## __cpu ##_ENET0_IRQ,            \
+        [IRQ_ENET1]             = BCM_## __cpu ##_ENET1_IRQ,            \
+        [IRQ_ENET_PHY]          = BCM_## __cpu ##_ENET_PHY_IRQ,         \
+        [IRQ_OHCI0]             = BCM_## __cpu ##_OHCI0_IRQ,            \
+        [IRQ_EHCI0]             = BCM_## __cpu ##_EHCI0_IRQ,            \
+        [IRQ_ENET0_RXDMA]       = BCM_## __cpu ##_ENET0_RXDMA_IRQ,      \
+        [IRQ_ENET0_TXDMA]       = BCM_## __cpu ##_ENET0_TXDMA_IRQ,      \
+        [IRQ_ENET1_RXDMA]       = BCM_## __cpu ##_ENET1_RXDMA_IRQ,      \
+        [IRQ_ENET1_TXDMA]       = BCM_## __cpu ##_ENET1_TXDMA_IRQ,      \
+        [IRQ_PCI]               = BCM_## __cpu ##_PCI_IRQ,              \
+        [IRQ_PCMCIA]            = BCM_## __cpu ##_PCMCIA_IRQ,           \
+        [IRQ_ATM]               = BCM_## __cpu ##_ATM_IRQ,              \
+        [IRQ_ENETSW_RXDMA0]     = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ,    \
+        [IRQ_ENETSW_RXDMA1]     = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ,    \
+        [IRQ_ENETSW_RXDMA2]     = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ,    \
+        [IRQ_ENETSW_RXDMA3]     = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ,    \
+        [IRQ_ENETSW_TXDMA0]     = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ,    \
+        [IRQ_ENETSW_TXDMA1]     = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ,    \
+        [IRQ_ENETSW_TXDMA2]     = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ,    \
+        [IRQ_ENETSW_TXDMA3]     = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ,    \
+        [IRQ_XTM]               = BCM_## __cpu ##_XTM_IRQ,              \
+        [IRQ_XTM_DMA0]          = BCM_## __cpu ##_XTM_DMA0_IRQ,         \
+
 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
 {
         return bcm63xx_irqs[irq];
@@ -550,4 +713,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
  */
 unsigned int bcm63xx_get_memory_size(void);
 
+void bcm63xx_machine_halt(void);
+
+void bcm63xx_machine_reboot(void);
+
 #endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 3999ec0aa7f5..3d5de96d4036 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
                 return 8;
         case BCM6345_CPU_ID:
                 return 16;
+        case BCM6368_CPU_ID:
+                return 38;
         case BCM6348_CPU_ID:
         default:
                 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 91180fac6ed9..72477a6441dd 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -49,9 +49,11 @@
 #define bcm_readb(a)    (*(volatile unsigned char *)    BCM_REGS_VA(a))
 #define bcm_readw(a)    (*(volatile unsigned short *)   BCM_REGS_VA(a))
 #define bcm_readl(a)    (*(volatile unsigned int *)     BCM_REGS_VA(a))
+#define bcm_readq(a)    (*(volatile u64 *)              BCM_REGS_VA(a))
 #define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
 #define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
 #define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
+#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
 
 /*
  * IO helpers to access register set for current CPU
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
index 5f95577c8213..0c3074b871b8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -3,13 +3,11 @@
 
 #include <bcm63xx_cpu.h>
 
-#define IRQ_MIPS_BASE                   0
 #define IRQ_INTERNAL_BASE               8
-
-#define IRQ_EXT_BASE                    (IRQ_MIPS_BASE + 3)
-#define IRQ_EXT_0                       (IRQ_EXT_BASE + 0)
-#define IRQ_EXT_1                       (IRQ_EXT_BASE + 1)
-#define IRQ_EXT_2                       (IRQ_EXT_BASE + 2)
-#define IRQ_EXT_3                       (IRQ_EXT_BASE + 3)
+#define IRQ_EXTERNAL_BASE               100
+#define IRQ_EXT_0                       (IRQ_EXTERNAL_BASE + 0)
+#define IRQ_EXT_1                       (IRQ_EXTERNAL_BASE + 1)
+#define IRQ_EXT_2                       (IRQ_EXTERNAL_BASE + 2)
+#define IRQ_EXT_3                       (IRQ_EXTERNAL_BASE + 3)
 
 #endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 0ed5230243c9..94d4faad29a1 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -83,30 +83,86 @@
                                         CKCTL_6358_USBSU_EN |           \
                                         CKCTL_6358_EPHY_EN)
 
+#define CKCTL_6368_VDSL_QPROC_EN        (1 << 2)
+#define CKCTL_6368_VDSL_AFE_EN          (1 << 3)
+#define CKCTL_6368_VDSL_BONDING_EN      (1 << 4)
+#define CKCTL_6368_VDSL_EN              (1 << 5)
+#define CKCTL_6368_PHYMIPS_EN           (1 << 6)
+#define CKCTL_6368_SWPKT_USB_EN         (1 << 7)
+#define CKCTL_6368_SWPKT_SAR_EN         (1 << 8)
+#define CKCTL_6368_SPI_CLK_EN           (1 << 9)
+#define CKCTL_6368_USBD_CLK_EN          (1 << 10)
+#define CKCTL_6368_SAR_CLK_EN           (1 << 11)
+#define CKCTL_6368_ROBOSW_CLK_EN        (1 << 12)
+#define CKCTL_6368_UTOPIA_CLK_EN        (1 << 13)
+#define CKCTL_6368_PCM_CLK_EN           (1 << 14)
+#define CKCTL_6368_USBH_CLK_EN          (1 << 15)
+#define CKCTL_6368_DISABLE_GLESS_EN     (1 << 16)
+#define CKCTL_6368_NAND_CLK_EN          (1 << 17)
+#define CKCTL_6368_IPSEC_CLK_EN         (1 << 17)
+
+#define CKCTL_6368_ALL_SAFE_EN          (CKCTL_6368_SWPKT_USB_EN |      \
+                                        CKCTL_6368_SWPKT_SAR_EN |       \
+                                        CKCTL_6368_SPI_CLK_EN |         \
+                                        CKCTL_6368_USBD_CLK_EN |        \
+                                        CKCTL_6368_SAR_CLK_EN |         \
+                                        CKCTL_6368_ROBOSW_CLK_EN |      \
+                                        CKCTL_6368_UTOPIA_CLK_EN |      \
+                                        CKCTL_6368_PCM_CLK_EN |         \
+                                        CKCTL_6368_USBH_CLK_EN |        \
+                                        CKCTL_6368_DISABLE_GLESS_EN |   \
+                                        CKCTL_6368_NAND_CLK_EN |        \
+                                        CKCTL_6368_IPSEC_CLK_EN)
+
 /* System PLL Control register  */
 #define PERF_SYS_PLL_CTL_REG            0x8
 #define SYS_PLL_SOFT_RESET              0x1
 
 /* Interrupt Mask register */
-#define PERF_IRQMASK_REG                0xc
+#define PERF_IRQMASK_6338_REG           0xc
+#define PERF_IRQMASK_6345_REG           0xc
+#define PERF_IRQMASK_6348_REG           0xc
+#define PERF_IRQMASK_6358_REG           0xc
+#define PERF_IRQMASK_6368_REG           0x20
 
 /* Interrupt Status register */
-#define PERF_IRQSTAT_REG                0x10
+#define PERF_IRQSTAT_6338_REG           0x10
+#define PERF_IRQSTAT_6345_REG           0x10
+#define PERF_IRQSTAT_6348_REG           0x10
+#define PERF_IRQSTAT_6358_REG           0x10
+#define PERF_IRQSTAT_6368_REG           0x28
 
 /* External Interrupt Configuration register */
-#define PERF_EXTIRQ_CFG_REG             0x14
+#define PERF_EXTIRQ_CFG_REG_6338        0x14
+#define PERF_EXTIRQ_CFG_REG_6348        0x14
+#define PERF_EXTIRQ_CFG_REG_6358        0x14
+#define PERF_EXTIRQ_CFG_REG_6368        0x18
+
+#define PERF_EXTIRQ_CFG_REG2_6368       0x1c
+
+/* for 6348 only */
+#define EXTIRQ_CFG_SENSE_6348(x)        (1 << (x))
+#define EXTIRQ_CFG_STAT_6348(x)         (1 << (x + 5))
+#define EXTIRQ_CFG_CLEAR_6348(x)        (1 << (x + 10))
+#define EXTIRQ_CFG_MASK_6348(x)         (1 << (x + 15))
+#define EXTIRQ_CFG_BOTHEDGE_6348(x)     (1 << (x + 20))
+#define EXTIRQ_CFG_LEVELSENSE_6348(x)   (1 << (x + 25))
+#define EXTIRQ_CFG_CLEAR_ALL_6348       (0xf << 10)
+#define EXTIRQ_CFG_MASK_ALL_6348        (0xf << 15)
+
+/* for all others */
 #define EXTIRQ_CFG_SENSE(x)             (1 << (x))
-#define EXTIRQ_CFG_STAT(x)              (1 << (x + 5))
-#define EXTIRQ_CFG_CLEAR(x)             (1 << (x + 10))
-#define EXTIRQ_CFG_MASK(x)              (1 << (x + 15))
-#define EXTIRQ_CFG_BOTHEDGE(x)          (1 << (x + 20))
-#define EXTIRQ_CFG_LEVELSENSE(x)        (1 << (x + 25))
-
-#define EXTIRQ_CFG_CLEAR_ALL            (0xf << 10)
-#define EXTIRQ_CFG_MASK_ALL             (0xf << 15)
+#define EXTIRQ_CFG_STAT(x)              (1 << (x + 4))
+#define EXTIRQ_CFG_CLEAR(x)             (1 << (x + 8))
+#define EXTIRQ_CFG_MASK(x)              (1 << (x + 12))
+#define EXTIRQ_CFG_BOTHEDGE(x)          (1 << (x + 16))
+#define EXTIRQ_CFG_LEVELSENSE(x)        (1 << (x + 20))
+#define EXTIRQ_CFG_CLEAR_ALL            (0xf << 8)
+#define EXTIRQ_CFG_MASK_ALL             (0xf << 12)
 
 /* Soft Reset register */
 #define PERF_SOFTRESET_REG              0x28
+#define PERF_SOFTRESET_6368_REG         0x10
 
 #define SOFTRESET_6338_SPI_MASK         (1 << 0)
 #define SOFTRESET_6338_ENET_MASK        (1 << 2)
@@ -147,6 +203,15 @@
                                   SOFTRESET_6348_ACLC_MASK |            \
                                   SOFTRESET_6348_ADSLMIPSPLL_MASK)
 
+#define SOFTRESET_6368_SPI_MASK         (1 << 0)
+#define SOFTRESET_6368_MPI_MASK         (1 << 3)
+#define SOFTRESET_6368_EPHY_MASK        (1 << 6)
+#define SOFTRESET_6368_SAR_MASK         (1 << 7)
+#define SOFTRESET_6368_ENETSW_MASK      (1 << 10)
+#define SOFTRESET_6368_USBS_MASK        (1 << 11)
+#define SOFTRESET_6368_USBH_MASK        (1 << 12)
+#define SOFTRESET_6368_PCM_MASK         (1 << 13)
+
 /* MIPS PLL control register */
 #define PERF_MIPSPLLCTL_REG             0x34
 #define MIPSPLLCTL_N1_SHIFT             20
@@ -372,6 +437,7 @@
 #define GPIO_CTL_LO_REG                 0x4
 #define GPIO_DATA_HI_REG                0x8
 #define GPIO_DATA_LO_REG                0xC
+#define GPIO_DATA_LO_REG_6345           0x8
 
 /* GPIO mux registers and constants */
 #define GPIO_MODE_REG                   0x18
@@ -402,6 +468,44 @@
 #define GPIO_MODE_6358_SERIAL_LED       (1 << 10)
 #define GPIO_MODE_6358_UTOPIA           (1 << 12)
 
+#define GPIO_MODE_6368_ANALOG_AFE_0     (1 << 0)
+#define GPIO_MODE_6368_ANALOG_AFE_1     (1 << 1)
+#define GPIO_MODE_6368_SYS_IRQ          (1 << 2)
+#define GPIO_MODE_6368_SERIAL_LED_DATA  (1 << 3)
+#define GPIO_MODE_6368_SERIAL_LED_CLK   (1 << 4)
+#define GPIO_MODE_6368_INET_LED         (1 << 5)
+#define GPIO_MODE_6368_EPHY0_LED        (1 << 6)
+#define GPIO_MODE_6368_EPHY1_LED        (1 << 7)
+#define GPIO_MODE_6368_EPHY2_LED        (1 << 8)
+#define GPIO_MODE_6368_EPHY3_LED        (1 << 9)
+#define GPIO_MODE_6368_ROBOSW_LED_DAT   (1 << 10)
+#define GPIO_MODE_6368_ROBOSW_LED_CLK   (1 << 11)
+#define GPIO_MODE_6368_ROBOSW_LED0      (1 << 12)
+#define GPIO_MODE_6368_ROBOSW_LED1      (1 << 13)
+#define GPIO_MODE_6368_USBD_LED         (1 << 14)
+#define GPIO_MODE_6368_NTR_PULSE        (1 << 15)
+#define GPIO_MODE_6368_PCI_REQ1         (1 << 16)
+#define GPIO_MODE_6368_PCI_GNT1         (1 << 17)
+#define GPIO_MODE_6368_PCI_INTB         (1 << 18)
+#define GPIO_MODE_6368_PCI_REQ0         (1 << 19)
+#define GPIO_MODE_6368_PCI_GNT0         (1 << 20)
+#define GPIO_MODE_6368_PCMCIA_CD1       (1 << 22)
+#define GPIO_MODE_6368_PCMCIA_CD2       (1 << 23)
+#define GPIO_MODE_6368_PCMCIA_VS1       (1 << 24)
+#define GPIO_MODE_6368_PCMCIA_VS2       (1 << 25)
+#define GPIO_MODE_6368_EBI_CS2          (1 << 26)
+#define GPIO_MODE_6368_EBI_CS3          (1 << 27)
+#define GPIO_MODE_6368_SPI_SSN2         (1 << 28)
+#define GPIO_MODE_6368_SPI_SSN3         (1 << 29)
+#define GPIO_MODE_6368_SPI_SSN4         (1 << 30)
+#define GPIO_MODE_6368_SPI_SSN5         (1 << 31)
+
+
+#define GPIO_BASEMODE_6368_REG          0x38
+#define GPIO_BASEMODE_6368_UART2        0x1
+#define GPIO_BASEMODE_6368_GPIO         0x0
+#define GPIO_BASEMODE_6368_MASK         0x7
+/* those bits must be kept as read in gpio basemode register*/
 
 /*************************************************************************
  * _REG relative to RSET_ENET
@@ -548,6 +652,56 @@
 
 
 /*************************************************************************
+ * _REG relative to RSET_ENETDMAC
+ *************************************************************************/
+
+/* Channel Configuration register */
+#define ENETDMAC_CHANCFG_REG(x)         ((x) * 0x10)
+#define ENETDMAC_CHANCFG_EN_SHIFT       0
+#define ENETDMAC_CHANCFG_EN_MASK        (1 << ENETDMA_CHANCFG_EN_SHIFT)
+#define ENETDMAC_CHANCFG_PKTHALT_SHIFT  1
+#define ENETDMAC_CHANCFG_PKTHALT_MASK   (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
+
+/* Interrupt Control/Status register */
+#define ENETDMAC_IR_REG(x)              (0x4 + (x) * 0x10)
+#define ENETDMAC_IR_BUFDONE_MASK        (1 << 0)
+#define ENETDMAC_IR_PKTDONE_MASK        (1 << 1)
+#define ENETDMAC_IR_NOTOWNER_MASK       (1 << 2)
+
+/* Interrupt Mask register */
+#define ENETDMAC_IRMASK_REG(x)          (0x8 + (x) * 0x10)
+
+/* Maximum Burst Length */
+#define ENETDMAC_MAXBURST_REG(x)        (0xc + (x) * 0x10)
+
+
+/*************************************************************************
+ * _REG relative to RSET_ENETDMAS
+ *************************************************************************/
+
+/* Ring Start Address register */
+#define ENETDMAS_RSTART_REG(x)          ((x) * 0x10)
+
+/* State Ram Word 2 */
+#define ENETDMAS_SRAM2_REG(x)           (0x4 + (x) * 0x10)
+
+/* State Ram Word 3 */
+#define ENETDMAS_SRAM3_REG(x)           (0x8 + (x) * 0x10)
+
+/* State Ram Word 4 */
+#define ENETDMAS_SRAM4_REG(x)           (0xc + (x) * 0x10)
+
+
+/*************************************************************************
+ * _REG relative to RSET_ENETSW
+ *************************************************************************/
+
+/* MIB register */
+#define ENETSW_MIB_REG(x)               (0x2800 + (x) * 4)
+#define ENETSW_MIB_REG_COUNT            47
+
+
+/*************************************************************************
  * _REG relative to RSET_OHCI_PRIV
  *************************************************************************/
 
@@ -562,7 +716,9 @@
  * _REG relative to RSET_USBH_PRIV
  *************************************************************************/
 
-#define USBH_PRIV_SWAP_REG              0x0
+#define USBH_PRIV_SWAP_6358_REG         0x0
+#define USBH_PRIV_SWAP_6368_REG         0x1c
+
 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT  4
 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK   (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT  3
@@ -572,7 +728,13 @@
 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT  0
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK   (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
-#define USBH_PRIV_TEST_REG              0x24
+#define USBH_PRIV_TEST_6358_REG         0x24
+#define USBH_PRIV_TEST_6368_REG         0x14
+
+#define USBH_PRIV_SETUP_6368_REG        0x28
+#define USBH_PRIV_SETUP_IOC_SHIFT       4
+#define USBH_PRIV_SETUP_IOC_MASK        (1 << USBH_PRIV_SETUP_IOC_SHIFT)
+
 
 
 /*************************************************************************
@@ -734,6 +896,8 @@
 #define SDRAM_CFG_BANK_SHIFT            13
 #define SDRAM_CFG_BANK_MASK             (1 << SDRAM_CFG_BANK_SHIFT)
 
+#define SDRAM_MBASE_REG                 0xc
+
 #define SDRAM_PRIO_REG                  0x2C
 #define SDRAM_PRIO_MIPS_SHIFT           29
 #define SDRAM_PRIO_MIPS_MASK            (1 << SDRAM_PRIO_MIPS_SHIFT)
@@ -768,4 +932,45 @@
 #define DMIPSPLLCFG_N2_SHIFT            29
 #define DMIPSPLLCFG_N2_MASK             (0x7 << DMIPSPLLCFG_N2_SHIFT)
 
+#define DDR_DMIPSPLLCFG_6368_REG        0x20
+#define DMIPSPLLCFG_6368_P1_SHIFT       0
+#define DMIPSPLLCFG_6368_P1_MASK        (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
+#define DMIPSPLLCFG_6368_P2_SHIFT       4
+#define DMIPSPLLCFG_6368_P2_MASK        (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
+#define DMIPSPLLCFG_6368_NDIV_SHIFT     16
+#define DMIPSPLLCFG_6368_NDIV_MASK      (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
+
+#define DDR_DMIPSPLLDIV_6368_REG        0x24
+#define DMIPSPLLDIV_6368_MDIV_SHIFT     0
+#define DMIPSPLLDIV_6368_MDIV_MASK      (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
+
+
+/*************************************************************************
+ * _REG relative to RSET_M2M
+ *************************************************************************/
+
+#define M2M_RX                          0
+#define M2M_TX                          1
+
+#define M2M_SRC_REG(x)                  ((x) * 0x40 + 0x00)
+#define M2M_DST_REG(x)                  ((x) * 0x40 + 0x04)
+#define M2M_SIZE_REG(x)                 ((x) * 0x40 + 0x08)
+
+#define M2M_CTRL_REG(x)                 ((x) * 0x40 + 0x0c)
+#define M2M_CTRL_ENABLE_MASK            (1 << 0)
+#define M2M_CTRL_IRQEN_MASK             (1 << 1)
+#define M2M_CTRL_ERROR_CLR_MASK         (1 << 6)
+#define M2M_CTRL_DONE_CLR_MASK          (1 << 7)
+#define M2M_CTRL_NOINC_MASK             (1 << 8)
+#define M2M_CTRL_PCMCIASWAP_MASK        (1 << 9)
+#define M2M_CTRL_SWAPBYTE_MASK          (1 << 10)
+#define M2M_CTRL_ENDIAN_MASK            (1 << 11)
+
+#define M2M_STAT_REG(x)                 ((x) * 0x40 + 0x10)
+#define M2M_STAT_DONE                   (1 << 0)
+#define M2M_STAT_ERROR                  (1 << 1)
+
+#define M2M_SRCID_REG(x)                ((x) * 0x40 + 0x14)
+#define M2M_DSTID_REG(x)                ((x) * 0x40 + 0x18)
+
 #endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
new file mode 100644
index 000000000000..ef94ba73646e
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -0,0 +1,42 @@
+#ifndef BCM63XX_IOREMAP_H_
+#define BCM63XX_IOREMAP_H_
+
+#include <bcm63xx_cpu.h>
+
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+        return phys_addr;
+}
+
+static inline int is_bcm63xx_internal_registers(phys_t offset)
+{
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6338_CPU_ID:
+        case BCM6345_CPU_ID:
+        case BCM6348_CPU_ID:
+        case BCM6358_CPU_ID:
+                if (offset >= 0xfff00000)
+                        return 1;
+                break;
+        case BCM6368_CPU_ID:
+                if (offset >= 0xb0000000 && offset < 0xb1000000)
+                        return 1;
+                break;
+        }
+        return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+                                         unsigned long flags)
+{
+        if (is_bcm63xx_internal_registers(offset))
+                return (void __iomem *)offset;
+        return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+        return is_bcm63xx_internal_registers((unsigned long)addr);
+}
+
+#endif /* BCM63XX_IOREMAP_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h
new file mode 100644
index 000000000000..9332e788a5c9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_BCM63XX_IRQ_H
+#define __ASM_MACH_BCM63XX_IRQ_H
+
+#define NR_IRQS 128
+#define MIPS_CPU_IRQ_BASE 0
+
+#endif
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
index 618d2de02ed3..bb9fc23d853a 100644
--- a/arch/mips/include/asm/mach-db1x00/bcsr.h
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -34,6 +34,8 @@
 #define PB1200_BCSR_PHYS_ADDR   0x0D800000
 #define PB1200_BCSR_HEXLED_OFS  0x00400000
 
+#define DB1300_BCSR_PHYS_ADDR   0x19800000
+#define DB1300_BCSR_HEXLED_OFS  0x00400000
 
 enum bcsr_id {
         /* BCSR base 1 */
@@ -105,6 +107,7 @@ enum bcsr_whoami_boards {
         BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
         BCSR_WHOAMI_PB1200_DDR2,
         BCSR_WHOAMI_DB1200,
+        BCSR_WHOAMI_DB1300,
 };
 
 /* STATUS reg.  Unless otherwise noted, they're valid on all boards.
@@ -118,12 +121,12 @@ enum bcsr_whoami_boards {
 #define BCSR_STATUS_SRAMWIDTH           0x0080
 #define BCSR_STATUS_FLASHBUSY           0x0100
 #define BCSR_STATUS_ROMBUSY             0x0400
-#define BCSR_STATUS_SD0WP               0x0400  /* DB1200 */
+#define BCSR_STATUS_SD0WP               0x0400  /* DB1200/DB1300:SD1 */
 #define BCSR_STATUS_SD1WP               0x0800
 #define BCSR_STATUS_USBOTGID            0x0800  /* PB/DB1550 */
 #define BCSR_STATUS_DB1000_SWAPBOOT     0x2000
-#define BCSR_STATUS_DB1200_SWAPBOOT     0x0040  /* DB1200 */
-#define BCSR_STATUS_IDECBLID            0x0200  /* DB1200 */
+#define BCSR_STATUS_DB1200_SWAPBOOT     0x0040  /* DB1200/1300 */
+#define BCSR_STATUS_IDECBLID            0x0200  /* DB1200/1300 */
 #define BCSR_STATUS_DB1200_U0RXD        0x1000  /* DB1200 */
 #define BCSR_STATUS_DB1200_U1RXD        0x2000  /* DB1200 */
 #define BCSR_STATUS_FLASHDEN            0xC000
@@ -133,6 +136,11 @@ enum bcsr_whoami_boards {
 #define BCSR_STATUS_PB1550_U1RXD        0x2000  /* PB1550 */
 #define BCSR_STATUS_PB1550_U3RXD        0x8000  /* PB1550 */
 
+#define BCSR_STATUS_CFWP                0x4000  /* DB1300 */
+#define BCSR_STATUS_USBOCn              0x2000  /* DB1300 */
+#define BCSR_STATUS_OTGOCn              0x1000  /* DB1300 */
+#define BCSR_STATUS_DCDMARQ             0x0010  /* DB1300 */
+#define BCSR_STATUS_IDEDMARQ            0x0020  /* DB1300 */
 
 /* DB/PB1000,1100,1500,1550 */
 #define BCSR_RESETS_PHY0                0x0001
@@ -155,17 +163,17 @@ enum bcsr_whoami_boards {
 #define BCSR_BOARD_GPIO200RST           0x0400
 #define BCSR_BOARD_PCICLKOUT            0x0800
 #define BCSR_BOARD_PCICFG               0x1000
-#define BCSR_BOARD_SPISEL               0x4000  /* PB/DB1550 */
+#define BCSR_BOARD_SPISEL               0x2000  /* PB/DB1550 */
 #define BCSR_BOARD_SD0WP                0x4000  /* DB1100 */
 #define BCSR_BOARD_SD1WP                0x8000  /* DB1100 */
 
 
-/* DB/PB1200 */
+/* DB/PB1200/1300 */
 #define BCSR_RESETS_ETH                 0x0001
 #define BCSR_RESETS_CAMERA              0x0002
 #define BCSR_RESETS_DC                  0x0004
 #define BCSR_RESETS_IDE                 0x0008
-#define BCSR_RESETS_TV                  0x0010  /* DB1200 */
+#define BCSR_RESETS_TV                  0x0010  /* DB1200/1300 */
 /* Not resets but in the same register */
 #define BCSR_RESETS_PWMR1MUX            0x0800  /* DB1200 */
 #define BCSR_RESETS_PB1200_WSCFSM       0x0800  /* PB1200 */
@@ -174,13 +182,22 @@ enum bcsr_whoami_boards {
 #define BCSR_RESETS_SPISEL              0x4000
 #define BCSR_RESETS_SD1MUX              0x8000  /* PB1200 */
 
+#define BCSR_RESETS_VDDQSHDN            0x0200  /* DB1300 */
+#define BCSR_RESETS_OTPPGM              0x0400  /* DB1300 */
+#define BCSR_RESETS_OTPSCLK             0x0800  /* DB1300 */
+#define BCSR_RESETS_OTPWRPROT           0x1000  /* DB1300 */
+#define BCSR_RESETS_OTPCSB              0x2000  /* DB1300 */
+#define BCSR_RESETS_OTGPWR              0x4000  /* DB1300 */
+#define BCSR_RESETS_USBHPWR             0x8000  /* DB1300 */
+
 #define BCSR_BOARD_LCDVEE               0x0001
 #define BCSR_BOARD_LCDVDD               0x0002
 #define BCSR_BOARD_LCDBL                0x0004
 #define BCSR_BOARD_CAMSNAP              0x0010
 #define BCSR_BOARD_CAMPWR               0x0020
 #define BCSR_BOARD_SD0PWR               0x0040
-
+#define BCSR_BOARD_CAMCS                0x0010  /* DB1300 */
+#define BCSR_BOARD_HDMI_DE              0x0040  /* DB1300 */
 
 #define BCSR_SWITCHES_DIP               0x00FF
 #define BCSR_SWITCHES_DIP_1             0x0080
@@ -214,7 +231,10 @@ enum bcsr_whoami_boards {
 #define BCSR_SYSTEM_RESET               0x8000  /* clear to reset */
 #define BCSR_SYSTEM_PWROFF              0x4000  /* set to power off */
 #define BCSR_SYSTEM_VDDI                0x001F  /* PB1xxx boards */
-
+#define BCSR_SYSTEM_DEBUGCSMASK         0x003F  /* DB1300 */
+#define BCSR_SYSTEM_UDMAMODE            0x0100  /* DB1300 */
+#define BCSR_SYSTEM_WAKEONIRQ           0x0200  /* DB1300 */
+#define BCSR_SYSTEM_VDDI1300            0x3C00  /* DB1300 */
 
 
 
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 7a39657108c4..b2a8319521e5 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -43,15 +43,20 @@
 #define BCSR_INT_PC1EJECT       0x0800
 #define BCSR_INT_SD0INSERT      0x1000
 #define BCSR_INT_SD0EJECT       0x2000
+#define BCSR_INT_SD1INSERT      0x4000
+#define BCSR_INT_SD1EJECT       0x8000
 
-#define IDE_PHYS_ADDR           0x18800000
 #define IDE_REG_SHIFT           5
 
-#define DB1200_IDE_PHYS_ADDR    IDE_PHYS_ADDR
+#define DB1200_IDE_PHYS_ADDR    0x18800000
 #define DB1200_IDE_PHYS_LEN     (16 << IDE_REG_SHIFT)
 #define DB1200_ETH_PHYS_ADDR    0x19000300
 #define DB1200_NAND_PHYS_ADDR   0x20000000
 
+#define PB1200_IDE_PHYS_ADDR    0x0C800000
+#define PB1200_ETH_PHYS_ADDR    0x0D000300
+#define PB1200_NAND_PHYS_ADDR   0x1C000000
+
 /*
  * External Interrupts for DBAu1200 as of 8/6/2004.
  * Bit positions in the CPLD registers can be calculated by taking
@@ -77,6 +82,8 @@ enum external_db1200_ints {
         DB1200_PC1_EJECT_INT,
         DB1200_SD0_INSERT_INT,
         DB1200_SD0_EJECT_INT,
+        PB1200_SD1_INSERT_INT,
+        PB1200_SD1_EJECT_INT,
 
         DB1200_INT_END          = DB1200_INT_BEGIN + 15,
 };
diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h
new file mode 100644
index 000000000000..7fe5fb3ba877
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1300.h
@@ -0,0 +1,40 @@
+/*
+ * NetLogic DB1300 board constants
+ */
+
+#ifndef _DB1300_H_
+#define _DB1300_H_
+
+/* FPGA (external mux) interrupt sources */
+#define DB1300_FIRST_INT        (ALCHEMY_GPIC_INT_LAST + 1)
+#define DB1300_IDE_INT          (DB1300_FIRST_INT + 0)
+#define DB1300_ETH_INT          (DB1300_FIRST_INT + 1)
+#define DB1300_CF_INT           (DB1300_FIRST_INT + 2)
+#define DB1300_VIDEO_INT        (DB1300_FIRST_INT + 4)
+#define DB1300_HDMI_INT         (DB1300_FIRST_INT + 5)
+#define DB1300_DC_INT           (DB1300_FIRST_INT + 6)
+#define DB1300_FLASH_INT        (DB1300_FIRST_INT + 7)
+#define DB1300_CF_INSERT_INT    (DB1300_FIRST_INT + 8)
+#define DB1300_CF_EJECT_INT     (DB1300_FIRST_INT + 9)
+#define DB1300_AC97_INT         (DB1300_FIRST_INT + 10)
+#define DB1300_AC97_PEN_INT     (DB1300_FIRST_INT + 11)
+#define DB1300_SD1_INSERT_INT   (DB1300_FIRST_INT + 12)
+#define DB1300_SD1_EJECT_INT    (DB1300_FIRST_INT + 13)
+#define DB1300_OTG_VBUS_OC_INT  (DB1300_FIRST_INT + 14)
+#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
+#define DB1300_LAST_INT         (DB1300_FIRST_INT + 15)
+
+/* SMSC9210 CS */
+#define DB1300_ETH_PHYS_ADDR    0x19000000
+#define DB1300_ETH_PHYS_END     0x197fffff
+
+/* ATA CS */
+#define DB1300_IDE_PHYS_ADDR    0x18800000
+#define DB1300_IDE_REG_SHIFT    5
+#define DB1300_IDE_PHYS_LEN     (16 << DB1300_IDE_REG_SHIFT)
+
+/* NAND CS */
+#define DB1300_NAND_PHYS_ADDR   0x20000000
+#define DB1300_NAND_PHYS_END    0x20000fff
+
+#endif  /* _DB1300_H_ */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
deleted file mode 100644
index a5affb0568ef..000000000000
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * AMD Alchemy DBAu1x00 Reference Boards
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_DB1X00_H
-#define __ASM_DB1X00_H
-
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#ifdef CONFIG_MIPS_DB1550
-
-#define DBDMA_AC97_TX_CHAN      AU1550_DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      AU1550_DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       AU1550_DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN       AU1550_DSCR_CMD0_PSC3_RX
-
-#define SPI_PSC_BASE            AU1550_PSC0_PHYS_ADDR
-#define AC97_PSC_BASE           AU1550_PSC1_PHYS_ADDR
-#define SMBUS_PSC_BASE          AU1550_PSC2_PHYS_ADDR
-#define I2S_PSC_BASE            AU1550_PSC3_PHYS_ADDR
-
-#define NAND_PHYS_ADDR          0x20000000
-
-#endif
-
-/*
- * NAND defines
- *
- * Timing values as described in databook, * ns value stripped of the
- * lower 2 bits.
- * These defines are here rather than an Au1550 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H                (18 >> 2)
-#define NAND_T_PUL              (30 >> 2)
-#define NAND_T_SU               (30 >> 2)
-#define NAND_T_WH               (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT          0
-#define NAND_T_PUL_SHIFT        4
-#define NAND_T_SU_SHIFT         8
-#define NAND_T_WH_SHIFT         12
-
-#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-#define NAND_CS         1
-
-/* Should be done by YAMON */
-#define NAND_STCFG      0x00400005 /* 8-bit NAND */
-#define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
-#define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
-
-#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-db1x00/irq.h b/arch/mips/include/asm/mach-db1x00/irq.h
new file mode 100644
index 000000000000..15b26693238f
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/irq.h
@@ -0,0 +1,23 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_IRQ_H
+#define __ASM_MACH_GENERIC_IRQ_H
+
+
+#ifdef NR_IRQS
+#undef NR_IRQS
+#endif
+
+#ifndef MIPS_CPU_IRQ_BASE
+#define MIPS_CPU_IRQ_BASE 0
+#endif
+
+/* 8 (MIPS) + 128 (au1300) + 16 (cpld) */
+#define NR_IRQS 152
+
+#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index 001a8ce17c17..a38f4d43e5e5 100644
--- a/arch/mips/include/asm/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -98,7 +98,7 @@ static inline void fd_disable_irq(void)
 static inline int fd_request_irq(void)
 {
         return request_irq(FLOPPY_IRQ, floppy_interrupt,
-                           IRQF_DISABLED, "floppy", NULL);
+                           0, "floppy", NULL);
 }
 
 static inline void fd_free_irq(void)
diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
index 56e9ca6ae426..88b5acb75145 100644
--- a/arch/mips/include/asm/mach-jazz/floppy.h
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -90,7 +90,7 @@ static inline void fd_disable_irq(void)
 static inline int fd_request_irq(void)
 {
         return request_irq(FLOPPY_IRQ, floppy_interrupt,
-                           IRQF_DISABLED, "floppy", NULL);
+                           0, "floppy", NULL);
 }
 
 static inline void fd_free_irq(void)
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3b728275b9b0..d193fb68cf27 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,24 +24,33 @@
 
 #define cpu_has_llsc            1
 #define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_ic_fills_f_dc   1
 #define cpu_has_dsp             0
 #define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-#define cpu_icache_snoops_remote_store  0
+#define cpu_icache_snoops_remote_store  1
 
-#define cpu_has_nofpuex         0
 #define cpu_has_64bits          1
 
 #define cpu_has_mips32r1        1
-#define cpu_has_mips32r2        0
 #define cpu_has_mips64r1        1
-#define cpu_has_mips64r2        0
 
 #define cpu_has_inclusive_pcaches       0
 
 #define cpu_dcache_line_size()  32
 #define cpu_icache_line_size()  32
 
+#if defined(CONFIG_CPU_XLR)
+#define cpu_has_userlocal       0
+#define cpu_has_dc_aliases      0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r2        0
+#elif defined(CONFIG_CPU_XLP)
+#define cpu_has_userlocal       1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r2        1
+#define cpu_has_dc_aliases      1
+#else
+#error "Unknown Netlogic CPU"
+#endif
+
 #endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
deleted file mode 100644
index 622c58710e5b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2001, 03 by Ralf Baechle
- *
- * RTC routines for PC style attached Dallas chip.
- */
-#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
-#define __ASM_MACH_AU1XX_MC146818RTC_H
-
-#include <asm/io.h>
-#include <asm/mach-au1x00/au1000.h>
-
-#define RTC_PORT(x)     (0x0c000000 + (x))
-#define RTC_IRQ         8
-#define PB1500_RTC_ADDR 0x0c000000
-
-static inline unsigned char CMOS_READ(unsigned long offset)
-{
-        offset <<= 2;
-        return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
-{
-        offset <<= 2;
-        au_writel(data, offset + PB1500_RTC_ADDR);
-}
-
-#define RTC_ALWAYS_BCD  1
-
-#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
deleted file mode 100644
index 65059255dc1e..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1000.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Alchemy Semi Pb1000 Reference Board
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1000_H
-#define __ASM_PB1000_H
-
-/* PCMCIA PB1000 specific defines */
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-#define PB1000_PCR              0xBE000000
-#  define PCR_SLOT_0_VPP0       (1 << 0)
-#  define PCR_SLOT_0_VPP1       (1 << 1)
-#  define PCR_SLOT_0_VCC0       (1 << 2)
-#  define PCR_SLOT_0_VCC1       (1 << 3)
-#  define PCR_SLOT_0_RST        (1 << 4)
-#  define PCR_SLOT_1_VPP0       (1 << 8)
-#  define PCR_SLOT_1_VPP1       (1 << 9)
-#  define PCR_SLOT_1_VCC0       (1 << 10)
-#  define PCR_SLOT_1_VCC1       (1 << 11)
-#  define PCR_SLOT_1_RST        (1 << 12)
-
-#define PB1000_MDR              0xBE000004
-#  define MDR_PI                (1 << 5)        /* PCMCIA int latch  */
-#  define MDR_EPI               (1 << 14)       /* enable PCMCIA int */
-#  define MDR_CPI               (1 << 15)       /* clear  PCMCIA int  */
-
-#define PB1000_ACR1             0xBE000008
-#  define ACR1_SLOT_0_CD1       (1 << 0)        /* card detect 1        */
-#  define ACR1_SLOT_0_CD2       (1 << 1)        /* card detect 2        */
-#  define ACR1_SLOT_0_READY     (1 << 2)        /* ready                */
-#  define ACR1_SLOT_0_STATUS    (1 << 3)        /* status change        */
-#  define ACR1_SLOT_0_VS1       (1 << 4)        /* voltage sense 1      */
-#  define ACR1_SLOT_0_VS2       (1 << 5)        /* voltage sense 2      */
-#  define ACR1_SLOT_0_INPACK    (1 << 6)        /* inpack pin status    */
-#  define ACR1_SLOT_1_CD1       (1 << 8)        /* card detect 1        */
-#  define ACR1_SLOT_1_CD2       (1 << 9)        /* card detect 2        */
-#  define ACR1_SLOT_1_READY     (1 << 10)       /* ready                */
-#  define ACR1_SLOT_1_STATUS    (1 << 11)       /* status change        */
-#  define ACR1_SLOT_1_VS1       (1 << 12)       /* voltage sense 1      */
-#  define ACR1_SLOT_1_VS2       (1 << 13)       /* voltage sense 2      */
-#  define ACR1_SLOT_1_INPACK    (1 << 14)       /* inpack pin status    */
-
-#define CPLD_AUX0               0xBE00000C
-#define CPLD_AUX1               0xBE000010
-#define CPLD_AUX2               0xBE000014
-
-/* Voltage levels */
-
-/* VPPEN1 - VPPEN0 */
-#define VPP_GND ((0 << 1) | (0 << 0))
-#define VPP_5V  ((1 << 1) | (0 << 0))
-#define VPP_3V  ((0 << 1) | (1 << 0))
-#define VPP_12V ((0 << 1) | (1 << 0))
-#define VPP_HIZ ((1 << 1) | (1 << 0))
-
-/* VCCEN1 - VCCEN0 */
-#define VCC_3V  ((0 << 1) | (1 << 0))
-#define VCC_5V  ((1 << 1) | (0 << 0))
-#define VCC_HIZ ((0 << 1) | (0 << 0))
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT) \
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-#endif /* __ASM_PB1000_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
deleted file mode 100644
index 374416adb65b..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * AMD Alchemy Pb1200 Reference Board
- * Board Registers defines.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1200_H
-#define __ASM_PB1200_H
-
-#include <linux/types.h>
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#define DBDMA_AC97_TX_CHAN      AU1200_DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      AU1200_DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       AU1200_DSCR_CMD0_PSC1_TX
-#define DBDMA_I2S_RX_CHAN       AU1200_DSCR_CMD0_PSC1_RX
-
-/*
- * SPI and SMB are muxed on the Pb1200 board.
- * Refer to board documentation.
- */
-#define SPI_PSC_BASE            AU1550_PSC0_PHYS_ADDR
-#define SMBUS_PSC_BASE          AU1550_PSC0_PHYS_ADDR
-/*
- * AC97 and I2S are muxed on the Pb1200 board.
- * Refer to board documentation.
- */
-#define AC97_PSC_BASE       AU1550_PSC1_PHYS_ADDR
-#define I2S_PSC_BASE    AU1550_PSC1_PHYS_ADDR
-
-
-#define BCSR_SYSTEM_VDDI        0x001F
-#define BCSR_SYSTEM_POWEROFF    0x4000
-#define BCSR_SYSTEM_RESET       0x8000
-
-/* Bit positions for the different interrupt sources */
-#define BCSR_INT_IDE            0x0001
-#define BCSR_INT_ETH            0x0002
-#define BCSR_INT_PC0            0x0004
-#define BCSR_INT_PC0STSCHG      0x0008
-#define BCSR_INT_PC1            0x0010
-#define BCSR_INT_PC1STSCHG      0x0020
-#define BCSR_INT_DC             0x0040
-#define BCSR_INT_FLASHBUSY      0x0080
-#define BCSR_INT_PC0INSERT      0x0100
-#define BCSR_INT_PC0EJECT       0x0200
-#define BCSR_INT_PC1INSERT      0x0400
-#define BCSR_INT_PC1EJECT       0x0800
-#define BCSR_INT_SD0INSERT      0x1000
-#define BCSR_INT_SD0EJECT       0x2000
-#define BCSR_INT_SD1INSERT      0x4000
-#define BCSR_INT_SD1EJECT       0x8000
-
-#define SMC91C111_PHYS_ADDR     0x0D000300
-#define SMC91C111_INT           PB1200_ETH_INT
-
-#define IDE_PHYS_ADDR           0x0C800000
-#define IDE_REG_SHIFT           5
-#define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
-#define IDE_INT                 PB1200_IDE_INT
-
-#define NAND_PHYS_ADDR  0x1C000000
-
-/*
- * Timing values as described in databook, * ns value stripped of
- * lower 2 bits.
- * These defines are here rather than an Au1200 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H                (18 >> 2)
-#define NAND_T_PUL              (30 >> 2)
-#define NAND_T_SU               (30 >> 2)
-#define NAND_T_WH               (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT          0
-#define NAND_T_PUL_SHIFT        4
-#define NAND_T_SU_SHIFT         8
-#define NAND_T_WH_SHIFT         12
-
-#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-
-/*
- * External Interrupts for Pb1200 as of 8/6/2004.
- * Bit positions in the CPLD registers can be calculated by taking
- * the interrupt define and subtracting the PB1200_INT_BEGIN value.
- *
- *   Example: IDE bis pos is  = 64 - 64
- *            ETH bit pos is  = 65 - 64
- */
-enum external_pb1200_ints {
-        PB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
-
-        PB1200_IDE_INT          = PB1200_INT_BEGIN,
-        PB1200_ETH_INT,
-        PB1200_PC0_INT,
-        PB1200_PC0_STSCHG_INT,
-        PB1200_PC1_INT,
-        PB1200_PC1_STSCHG_INT,
-        PB1200_DC_INT,
-        PB1200_FLASHBUSY_INT,
-        PB1200_PC0_INSERT_INT,
-        PB1200_PC0_EJECT_INT,
-        PB1200_PC1_INSERT_INT,
-        PB1200_PC1_EJECT_INT,
-        PB1200_SD0_INSERT_INT,
-        PB1200_SD0_EJECT_INT,
-        PB1200_SD1_INSERT_INT,
-        PB1200_SD1_EJECT_INT,
-
-        PB1200_INT_END          = PB1200_INT_BEGIN + 15
-};
-
-/* NAND chip select */
-#define NAND_CS 1
-
-#endif /* __ASM_PB1200_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
deleted file mode 100644
index 443b88adebf1..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * AMD Alchemy Semi PB1550 Reference Board
- * Board Registers defines.
- *
- * Copyright 2004 Embedded Edge LLC.
- * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1550_H
-#define __ASM_PB1550_H
-
-#include <linux/types.h>
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#define DBDMA_AC97_TX_CHAN      AU1550_DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      AU1550_DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       AU1550_DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN       AU1550_DSCR_CMD0_PSC3_RX
-
-#define SPI_PSC_BASE            AU1550_PSC0_PHYS_ADDR
-#define AC97_PSC_BASE           AU1550_PSC1_PHYS_ADDR
-#define SMBUS_PSC_BASE          AU1550_PSC2_PHYS_ADDR
-#define I2S_PSC_BASE            AU1550_PSC3_PHYS_ADDR
-
-/*
- * Timing values as described in databook, * ns value stripped of
- * lower 2 bits.
- * These defines are here rather than an SOC1550 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H                (18 >> 2)
-#define NAND_T_PUL              (30 >> 2)
-#define NAND_T_SU               (30 >> 2)
-#define NAND_T_WH               (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT          0
-#define NAND_T_PUL_SHIFT        4
-#define NAND_T_SU_SHIFT         8
-#define NAND_T_WH_SHIFT         12
-
-#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-
-#define NAND_CS 1
-
-/* Should be done by YAMON */
-#define NAND_STCFG      0x00400005 /* 8-bit NAND */
-#define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
-#define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
-
-#endif /* __ASM_PB1550_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2ea7b817feb8..7f87d824eeb0 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1106,7 +1106,7 @@ do {									\
 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
 
-/* BMIPS4380 */
+/* BMIPS43xx */
 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
 
@@ -1667,6 +1667,13 @@ __BUILD_SET_C0(config)
 __BUILD_SET_C0(intcontrol)
 __BUILD_SET_C0(intctl)
 __BUILD_SET_C0(srsmap)
+__BUILD_SET_C0(brcm_config_0)
+__BUILD_SET_C0(brcm_bus_pll)
+__BUILD_SET_C0(brcm_reset)
+__BUILD_SET_C0(brcm_cmt_intr)
+__BUILD_SET_C0(brcm_cmt_ctrl)
+__BUILD_SET_C0(brcm_config)
+__BUILD_SET_C0(brcm_mode)
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02cacd8..7467d1d933d5 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -74,7 +74,9 @@ search_module_dbetables(unsigned long addr)
 }
 #endif
 
-#ifdef CONFIG_CPU_MIPS32_R1
+#ifdef CONFIG_CPU_BMIPS
+#define MODULE_PROC_FAMILY "BMIPS "
+#elif defined CONFIG_CPU_MIPS32_R1
 #define MODULE_PROC_FAMILY "MIPS32_R1 "
 #elif defined CONFIG_CPU_MIPS32_R2
 #define MODULE_PROC_FAMILY "MIPS32_R2 "
@@ -120,6 +122,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "OCTEON "
 #elif defined CONFIG_CPU_XLR
 #define MODULE_PROC_FAMILY "XLR "
+#elif defined CONFIG_CPU_XLP
+#define MODULE_PROC_FAMILY "XLP "
 #else
 #error MODULE_PROC_FAMILY undefined for your processor configuration
 #endif
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
new file mode 100644
index 000000000000..fdd2f44c7b59
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _NETLOGIC_COMMON_H_
+#define _NETLOGIC_COMMON_H_
+
+/*
+ * Common SMP definitions
+ */
+#define RESET_VEC_PHYS          0x1fc00000
+#define RESET_DATA_PHYS         (RESET_VEC_PHYS + (1<<10))
+#define BOOT_THREAD_MODE        0
+#define BOOT_NMI_LOCK           4
+#define BOOT_NMI_HANDLER        8
+
+#ifndef __ASSEMBLY__
+struct irq_desc;
+extern struct plat_smp_ops nlm_smp_ops;
+extern char nlm_reset_entry[], nlm_reset_entry_end[];
+void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
+void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
+void nlm_smp_irq_init(void);
+void nlm_boot_secondary_cpus(void);
+int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
+void nlm_rmiboot_preboot(void);
+
+static inline void
+nlm_set_nmi_handler(void *handler)
+{
+        char *reset_data;
+
+        reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
+        *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
+}
+
+/*
+ * Misc.
+ */
+unsigned int nlm_get_cpu_frequency(void);
+
+extern unsigned long nlm_common_ebase;
+extern int nlm_threads_per_core;
+extern uint32_t nlm_cpumask, nlm_coremask;
+#endif
+#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
new file mode 100644
index 000000000000..72a0c788b472
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_HALDEFS_H__
+#define __NLM_HAL_HALDEFS_H__
+
+/*
+ * This file contains platform specific memory mapped IO implementation
+ * and will provide a way to read 32/64 bit memory mapped registers in
+ * all ABIs
+ */
+#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
+#error "o32 compile not supported on XLP yet"
+#endif
+/*
+ * For o32 compilation, we have to disable interrupts and enable KX bit to
+ * access 64 bit addresses or data.
+ *
+ * We need to disable interrupts because we save just the lower 32 bits of
+ * registers in  interrupt handling. So if we get hit by an interrupt while
+ * using the upper 32 bits of a register, we lose.
+ */
+static inline uint32_t nlm_save_flags_kx(void)
+{
+        return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
+}
+
+static inline uint32_t nlm_save_flags_cop2(void)
+{
+        return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
+}
+
+static inline void nlm_restore_flags(uint32_t sr)
+{
+        write_c0_status(sr);
+}
+
+/*
+ * The n64 implementations are simple, the o32 implementations when they
+ * are added, will have to disable interrupts and enable KX before doing
+ * 64 bit ops.
+ */
+static inline uint32_t
+nlm_read_reg(uint64_t base, uint32_t reg)
+{
+        volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
+
+        return *addr;
+}
+
+static inline void
+nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
+{
+        volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
+
+        *addr = val;
+}
+
+static inline uint64_t
+nlm_read_reg64(uint64_t base, uint32_t reg)
+{
+        uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
+        volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
+
+        return *ptr;
+}
+
+static inline void
+nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
+{
+        uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
+        volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
+
+        *ptr = val;
+}
+
+/*
+ * Routines to store 32/64 bit values to 64 bit addresses,
+ * used when going thru XKPHYS to access registers
+ */
+static inline uint32_t
+nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
+{
+        return nlm_read_reg(base, reg);
+}
+
+static inline void
+nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
+{
+        nlm_write_reg(base, reg, val);
+}
+
+static inline uint64_t
+nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
+{
+        return nlm_read_reg64(base, reg);
+}
+
+static inline void
+nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
+{
+        nlm_write_reg64(base, reg, val);
+}
+
+/* Location where IO base is mapped */
+extern uint64_t nlm_io_base;
+
+#if defined(CONFIG_CPU_XLP)
+static inline uint64_t
+nlm_pcicfg_base(uint32_t devoffset)
+{
+        return nlm_io_base + devoffset;
+}
+
+static inline uint64_t
+nlm_xkphys_map_pcibar0(uint64_t pcibase)
+{
+        uint64_t paddr;
+
+        paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
+        return (uint64_t)0x9000000000000000 | paddr;
+}
+#elif defined(CONFIG_CPU_XLR)
+
+static inline uint64_t
+nlm_mmio_base(uint32_t devoffset)
+{
+        return nlm_io_base + devoffset;
+}
+#endif
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
new file mode 100644
index 000000000000..ca95133f1ad1
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_BRIDGE_H__
+#define __NLM_HAL_BRIDGE_H__
+
+/**
+* @file_name mio.h
+* @author Netlogic Microsystems
+* @brief Basic definitions of XLP memory and io subsystem
+*/
+
+/*
+ * BRIDGE specific registers
+ *
+ * These registers start after the PCIe header, which has 0x40
+ * standard entries
+ */
+#define BRIDGE_MODE                     0x00
+#define BRIDGE_PCI_CFG_BASE             0x01
+#define BRIDGE_PCI_CFG_LIMIT            0x02
+#define BRIDGE_PCIE_CFG_BASE            0x03
+#define BRIDGE_PCIE_CFG_LIMIT           0x04
+#define BRIDGE_BUSNUM_BAR0              0x05
+#define BRIDGE_BUSNUM_BAR1              0x06
+#define BRIDGE_BUSNUM_BAR2              0x07
+#define BRIDGE_BUSNUM_BAR3              0x08
+#define BRIDGE_BUSNUM_BAR4              0x09
+#define BRIDGE_BUSNUM_BAR5              0x0a
+#define BRIDGE_BUSNUM_BAR6              0x0b
+#define BRIDGE_FLASH_BAR0               0x0c
+#define BRIDGE_FLASH_BAR1               0x0d
+#define BRIDGE_FLASH_BAR2               0x0e
+#define BRIDGE_FLASH_BAR3               0x0f
+#define BRIDGE_FLASH_LIMIT0             0x10
+#define BRIDGE_FLASH_LIMIT1             0x11
+#define BRIDGE_FLASH_LIMIT2             0x12
+#define BRIDGE_FLASH_LIMIT3             0x13
+
+#define BRIDGE_DRAM_BAR(i)              (0x14 + (i))
+#define BRIDGE_DRAM_BAR0                0x14
+#define BRIDGE_DRAM_BAR1                0x15
+#define BRIDGE_DRAM_BAR2                0x16
+#define BRIDGE_DRAM_BAR3                0x17
+#define BRIDGE_DRAM_BAR4                0x18
+#define BRIDGE_DRAM_BAR5                0x19
+#define BRIDGE_DRAM_BAR6                0x1a
+#define BRIDGE_DRAM_BAR7                0x1b
+
+#define BRIDGE_DRAM_LIMIT(i)            (0x1c + (i))
+#define BRIDGE_DRAM_LIMIT0              0x1c
+#define BRIDGE_DRAM_LIMIT1              0x1d
+#define BRIDGE_DRAM_LIMIT2              0x1e
+#define BRIDGE_DRAM_LIMIT3              0x1f
+#define BRIDGE_DRAM_LIMIT4              0x20
+#define BRIDGE_DRAM_LIMIT5              0x21
+#define BRIDGE_DRAM_LIMIT6              0x22
+#define BRIDGE_DRAM_LIMIT7              0x23
+
+#define BRIDGE_DRAM_NODE_TRANSLN0       0x24
+#define BRIDGE_DRAM_NODE_TRANSLN1       0x25
+#define BRIDGE_DRAM_NODE_TRANSLN2       0x26
+#define BRIDGE_DRAM_NODE_TRANSLN3       0x27
+#define BRIDGE_DRAM_NODE_TRANSLN4       0x28
+#define BRIDGE_DRAM_NODE_TRANSLN5       0x29
+#define BRIDGE_DRAM_NODE_TRANSLN6       0x2a
+#define BRIDGE_DRAM_NODE_TRANSLN7       0x2b
+#define BRIDGE_DRAM_CHNL_TRANSLN0       0x2c
+#define BRIDGE_DRAM_CHNL_TRANSLN1       0x2d
+#define BRIDGE_DRAM_CHNL_TRANSLN2       0x2e
+#define BRIDGE_DRAM_CHNL_TRANSLN3       0x2f
+#define BRIDGE_DRAM_CHNL_TRANSLN4       0x30
+#define BRIDGE_DRAM_CHNL_TRANSLN5       0x31
+#define BRIDGE_DRAM_CHNL_TRANSLN6       0x32
+#define BRIDGE_DRAM_CHNL_TRANSLN7       0x33
+#define BRIDGE_PCIEMEM_BASE0            0x34
+#define BRIDGE_PCIEMEM_BASE1            0x35
+#define BRIDGE_PCIEMEM_BASE2            0x36
+#define BRIDGE_PCIEMEM_BASE3            0x37
+#define BRIDGE_PCIEMEM_LIMIT0           0x38
+#define BRIDGE_PCIEMEM_LIMIT1           0x39
+#define BRIDGE_PCIEMEM_LIMIT2           0x3a
+#define BRIDGE_PCIEMEM_LIMIT3           0x3b
+#define BRIDGE_PCIEIO_BASE0             0x3c
+#define BRIDGE_PCIEIO_BASE1             0x3d
+#define BRIDGE_PCIEIO_BASE2             0x3e
+#define BRIDGE_PCIEIO_BASE3             0x3f
+#define BRIDGE_PCIEIO_LIMIT0            0x40
+#define BRIDGE_PCIEIO_LIMIT1            0x41
+#define BRIDGE_PCIEIO_LIMIT2            0x42
+#define BRIDGE_PCIEIO_LIMIT3            0x43
+#define BRIDGE_PCIEMEM_BASE4            0x44
+#define BRIDGE_PCIEMEM_BASE5            0x45
+#define BRIDGE_PCIEMEM_BASE6            0x46
+#define BRIDGE_PCIEMEM_LIMIT4           0x47
+#define BRIDGE_PCIEMEM_LIMIT5           0x48
+#define BRIDGE_PCIEMEM_LIMIT6           0x49
+#define BRIDGE_PCIEIO_BASE4             0x4a
+#define BRIDGE_PCIEIO_BASE5             0x4b
+#define BRIDGE_PCIEIO_BASE6             0x4c
+#define BRIDGE_PCIEIO_LIMIT4            0x4d
+#define BRIDGE_PCIEIO_LIMIT5            0x4e
+#define BRIDGE_PCIEIO_LIMIT6            0x4f
+#define BRIDGE_NBU_EVENT_CNT_CTL        0x50
+#define BRIDGE_EVNTCTR1_LOW             0x51
+#define BRIDGE_EVNTCTR1_HI              0x52
+#define BRIDGE_EVNT_CNT_CTL2            0x53
+#define BRIDGE_EVNTCTR2_LOW             0x54
+#define BRIDGE_EVNTCTR2_HI              0x55
+#define BRIDGE_TRACEBUF_MATCH0          0x56
+#define BRIDGE_TRACEBUF_MATCH1          0x57
+#define BRIDGE_TRACEBUF_MATCH_LOW       0x58
+#define BRIDGE_TRACEBUF_MATCH_HI        0x59
+#define BRIDGE_TRACEBUF_CTRL            0x5a
+#define BRIDGE_TRACEBUF_INIT            0x5b
+#define BRIDGE_TRACEBUF_ACCESS          0x5c
+#define BRIDGE_TRACEBUF_READ_DATA0      0x5d
+#define BRIDGE_TRACEBUF_READ_DATA1      0x5d
+#define BRIDGE_TRACEBUF_READ_DATA2      0x5f
+#define BRIDGE_TRACEBUF_READ_DATA3      0x60
+#define BRIDGE_TRACEBUF_STATUS          0x61
+#define BRIDGE_ADDRESS_ERROR0           0x62
+#define BRIDGE_ADDRESS_ERROR1           0x63
+#define BRIDGE_ADDRESS_ERROR2           0x64
+#define BRIDGE_TAG_ECC_ADDR_ERROR0      0x65
+#define BRIDGE_TAG_ECC_ADDR_ERROR1      0x66
+#define BRIDGE_TAG_ECC_ADDR_ERROR2      0x67
+#define BRIDGE_LINE_FLUSH0              0x68
+#define BRIDGE_LINE_FLUSH1              0x69
+#define BRIDGE_NODE_ID                  0x6a
+#define BRIDGE_ERROR_INTERRUPT_EN       0x6b
+#define BRIDGE_PCIE0_WEIGHT             0x2c0
+#define BRIDGE_PCIE1_WEIGHT             0x2c1
+#define BRIDGE_PCIE2_WEIGHT             0x2c2
+#define BRIDGE_PCIE3_WEIGHT             0x2c3
+#define BRIDGE_USB_WEIGHT               0x2c4
+#define BRIDGE_NET_WEIGHT               0x2c5
+#define BRIDGE_POE_WEIGHT               0x2c6
+#define BRIDGE_CMS_WEIGHT               0x2c7
+#define BRIDGE_DMAENG_WEIGHT            0x2c8
+#define BRIDGE_SEC_WEIGHT               0x2c9
+#define BRIDGE_COMP_WEIGHT              0x2ca
+#define BRIDGE_GIO_WEIGHT               0x2cb
+#define BRIDGE_FLASH_WEIGHT             0x2cc
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_bridge_reg(b, r)       nlm_read_reg(b, r)
+#define nlm_write_bridge_reg(b, r, v)   nlm_write_reg(b, r, v)
+#define nlm_get_bridge_pcibase(node)    \
+                        nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
+#define nlm_get_bridge_regbase(node)    \
+                        (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+#endif /* __ASSEMBLY__ */
+#endif /* __NLM_HAL_BRIDGE_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
new file mode 100644
index 000000000000..bf7d41deb9be
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_CPUCONTROL_H__
+#define __NLM_HAL_CPUCONTROL_H__
+
+#define CPU_BLOCKID_IFU         0
+#define CPU_BLOCKID_ICU         1
+#define CPU_BLOCKID_IEU         2
+#define CPU_BLOCKID_LSU         3
+#define CPU_BLOCKID_MMU         4
+#define CPU_BLOCKID_PRF         5
+#define CPU_BLOCKID_SCH         7
+#define CPU_BLOCKID_SCU         8
+#define CPU_BLOCKID_FPU         9
+#define CPU_BLOCKID_MAP         10
+
+#define LSU_DEFEATURE           0x304
+#define LSU_CERRLOG_REGID       0x09
+#define SCHED_DEFEATURE         0x700
+
+/* Offsets of interest from the 'MAP' Block */
+#define MAP_THREADMODE                  0x00
+#define MAP_EXT_EBASE_ENABLE            0x04
+#define MAP_CCDI_CONFIG                 0x08
+#define MAP_THRD0_CCDI_STATUS           0x0c
+#define MAP_THRD1_CCDI_STATUS           0x10
+#define MAP_THRD2_CCDI_STATUS           0x14
+#define MAP_THRD3_CCDI_STATUS           0x18
+#define MAP_THRD0_DEBUG_MODE            0x1c
+#define MAP_THRD1_DEBUG_MODE            0x20
+#define MAP_THRD2_DEBUG_MODE            0x24
+#define MAP_THRD3_DEBUG_MODE            0x28
+#define MAP_MISC_STATE                  0x60
+#define MAP_DEBUG_READ_CTL              0x64
+#define MAP_DEBUG_READ_REG0             0x68
+#define MAP_DEBUG_READ_REG1             0x6c
+
+#define MMU_SETUP               0x400
+#define MMU_LFSRSEED            0x401
+#define MMU_HPW_NUM_PAGE_LVL    0x410
+#define MMU_PGWKR_PGDBASE       0x411
+#define MMU_PGWKR_PGDSHFT       0x412
+#define MMU_PGWKR_PGDMASK       0x413
+#define MMU_PGWKR_PUDSHFT       0x414
+#define MMU_PGWKR_PUDMASK       0x415
+#define MMU_PGWKR_PMDSHFT       0x416
+#define MMU_PGWKR_PMDMASK       0x417
+#define MMU_PGWKR_PTESHFT       0x418
+#define MMU_PGWKR_PTEMASK       0x419
+
+#endif /* __NLM_CPUCONTROL_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
new file mode 100644
index 000000000000..86cc3391e50c
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_IOMAP_H__
+#define __NLM_HAL_IOMAP_H__
+
+#define XLP_DEFAULT_IO_BASE             0x18000000
+#define NMI_BASE                        0xbfc00000
+#define XLP_IO_CLK                      133333333
+
+#define XLP_PCIE_CFG_SIZE               0x1000          /* 4K */
+#define XLP_PCIE_DEV_BLK_SIZE           (8 * XLP_PCIE_CFG_SIZE)
+#define XLP_PCIE_BUS_BLK_SIZE           (256 * XLP_PCIE_DEV_BLK_SIZE)
+#define XLP_IO_SIZE                     (64 << 20)      /* ECFG space size */
+#define XLP_IO_PCI_HDRSZ                0x100
+#define XLP_IO_DEV(node, dev)           ((dev) + (node) * 8)
+#define XLP_HDR_OFFSET(node, bus, dev, fn)      (((bus) << 20) | \
+                                ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
+
+#define XLP_IO_BRIDGE_OFFSET(node)      XLP_HDR_OFFSET(node, 0, 0, 0)
+/* coherent inter chip */
+#define XLP_IO_CIC0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 1)
+#define XLP_IO_CIC1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 2)
+#define XLP_IO_CIC2_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 0, 3)
+#define XLP_IO_PIC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 0, 4)
+
+#define XLP_IO_PCIE_OFFSET(node, i)     XLP_HDR_OFFSET(node, 0, 1, i)
+#define XLP_IO_PCIE0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 0)
+#define XLP_IO_PCIE1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 1)
+#define XLP_IO_PCIE2_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 2)
+#define XLP_IO_PCIE3_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 1, 3)
+
+#define XLP_IO_USB_OFFSET(node, i)      XLP_HDR_OFFSET(node, 0, 2, i)
+#define XLP_IO_USB_EHCI0_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 0)
+#define XLP_IO_USB_OHCI0_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 1)
+#define XLP_IO_USB_OHCI1_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 2)
+#define XLP_IO_USB_EHCI1_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 3)
+#define XLP_IO_USB_OHCI2_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 4)
+#define XLP_IO_USB_OHCI3_OFFSET(node)   XLP_HDR_OFFSET(node, 0, 2, 5)
+
+#define XLP_IO_NAE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 0)
+#define XLP_IO_POE_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 3, 1)
+
+#define XLP_IO_CMS_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 4, 0)
+
+#define XLP_IO_DMA_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 1)
+#define XLP_IO_SEC_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 2)
+#define XLP_IO_CMP_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 5, 3)
+
+#define XLP_IO_UART_OFFSET(node, i)     XLP_HDR_OFFSET(node, 0, 6, i)
+#define XLP_IO_UART0_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 0)
+#define XLP_IO_UART1_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 6, 1)
+#define XLP_IO_I2C_OFFSET(node, i)      XLP_HDR_OFFSET(node, 0, 6, 2 + i)
+#define XLP_IO_I2C0_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 2)
+#define XLP_IO_I2C1_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 3)
+#define XLP_IO_GPIO_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 4)
+/* system management */
+#define XLP_IO_SYS_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 6, 5)
+#define XLP_IO_JTAG_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 6, 6)
+
+#define XLP_IO_NOR_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 0)
+#define XLP_IO_NAND_OFFSET(node)        XLP_HDR_OFFSET(node, 0, 7, 1)
+#define XLP_IO_SPI_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 2)
+/* SD flash */
+#define XLP_IO_SD_OFFSET(node)          XLP_HDR_OFFSET(node, 0, 7, 3)
+#define XLP_IO_MMC_OFFSET(node, slot)   \
+                ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
+
+/* PCI config header register id's */
+#define XLP_PCI_CFGREG0                 0x00
+#define XLP_PCI_CFGREG1                 0x01
+#define XLP_PCI_CFGREG2                 0x02
+#define XLP_PCI_CFGREG3                 0x03
+#define XLP_PCI_CFGREG4                 0x04
+#define XLP_PCI_CFGREG5                 0x05
+#define XLP_PCI_DEVINFO_REG0            0x30
+#define XLP_PCI_DEVINFO_REG1            0x31
+#define XLP_PCI_DEVINFO_REG2            0x32
+#define XLP_PCI_DEVINFO_REG3            0x33
+#define XLP_PCI_DEVINFO_REG4            0x34
+#define XLP_PCI_DEVINFO_REG5            0x35
+#define XLP_PCI_DEVINFO_REG6            0x36
+#define XLP_PCI_DEVINFO_REG7            0x37
+#define XLP_PCI_DEVSCRATCH_REG0         0x38
+#define XLP_PCI_DEVSCRATCH_REG1         0x39
+#define XLP_PCI_DEVSCRATCH_REG2         0x3a
+#define XLP_PCI_DEVSCRATCH_REG3         0x3b
+#define XLP_PCI_MSGSTN_REG              0x3c
+#define XLP_PCI_IRTINFO_REG             0x3d
+#define XLP_PCI_UCODEINFO_REG           0x3e
+#define XLP_PCI_SBB_WT_REG              0x3f
+
+/* PCI IDs for SoC device */
+#define PCI_VENDOR_NETLOGIC             0x184e
+
+#define PCI_DEVICE_ID_NLM_ROOT          0x1001
+#define PCI_DEVICE_ID_NLM_ICI           0x1002
+#define PCI_DEVICE_ID_NLM_PIC           0x1003
+#define PCI_DEVICE_ID_NLM_PCIE          0x1004
+#define PCI_DEVICE_ID_NLM_EHCI          0x1007
+#define PCI_DEVICE_ID_NLM_ILK           0x1008
+#define PCI_DEVICE_ID_NLM_NAE           0x1009
+#define PCI_DEVICE_ID_NLM_POE           0x100A
+#define PCI_DEVICE_ID_NLM_FMN           0x100B
+#define PCI_DEVICE_ID_NLM_RAID          0x100D
+#define PCI_DEVICE_ID_NLM_SAE           0x100D
+#define PCI_DEVICE_ID_NLM_RSA           0x100E
+#define PCI_DEVICE_ID_NLM_CMP           0x100F
+#define PCI_DEVICE_ID_NLM_UART          0x1010
+#define PCI_DEVICE_ID_NLM_I2C           0x1011
+#define PCI_DEVICE_ID_NLM_NOR           0x1015
+#define PCI_DEVICE_ID_NLM_NAND          0x1016
+#define PCI_DEVICE_ID_NLM_MMC           0x1018
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_pci_reg(b, r)          nlm_read_reg(b, r)
+#define nlm_write_pci_reg(b, r, v)      nlm_write_reg(b, r, v)
+
+#endif /* !__ASSEMBLY */
+
+#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
new file mode 100644
index 000000000000..b6628f7ccf74
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _NLM_HAL_PIC_H
+#define _NLM_HAL_PIC_H
+
+/* PIC Specific registers */
+#define PIC_CTRL                0x00
+
+/* PIC control register defines */
+#define PIC_CTRL_ITV            32 /* interrupt timeout value */
+#define PIC_CTRL_ICI            19 /* ICI interrupt timeout enable */
+#define PIC_CTRL_ITE            18 /* interrupt timeout enable */
+#define PIC_CTRL_STE            10 /* system timer interrupt enable */
+#define PIC_CTRL_WWR1           8  /* watchdog 1 wraparound count for reset */
+#define PIC_CTRL_WWR0           6  /* watchdog 0 wraparound count for reset */
+#define PIC_CTRL_WWN1           4  /* watchdog 1 wraparound count for NMI */
+#define PIC_CTRL_WWN0           2  /* watchdog 0 wraparound count for NMI */
+#define PIC_CTRL_WTE            0  /* watchdog timer enable */
+
+/* PIC Status register defines */
+#define PIC_ICI_STATUS          33 /* ICI interrupt timeout status */
+#define PIC_ITE_STATUS          32 /* interrupt timeout status */
+#define PIC_STS_STATUS          4  /* System timer interrupt status */
+#define PIC_WNS_STATUS          2  /* NMI status for watchdog timers */
+#define PIC_WIS_STATUS          0  /* Interrupt status for watchdog timers */
+
+/* PIC IPI control register offsets */
+#define PIC_IPICTRL_NMI         32
+#define PIC_IPICTRL_RIV         20 /* received interrupt vector */
+#define PIC_IPICTRL_IDB         16 /* interrupt destination base */
+#define PIC_IPICTRL_DTE          0 /* interrupt destination thread enables */
+
+/* PIC IRT register offsets */
+#define PIC_IRT_ENABLE          31
+#define PIC_IRT_NMI             29
+#define PIC_IRT_SCH             28 /* Scheduling scheme */
+#define PIC_IRT_RVEC            20 /* Interrupt receive vectors */
+#define PIC_IRT_DT              19 /* Destination type */
+#define PIC_IRT_DB              16 /* Destination base */
+#define PIC_IRT_DTE             0  /* Destination thread enables */
+
+#define PIC_BYTESWAP            0x02
+#define PIC_STATUS              0x04
+#define PIC_INTR_TIMEOUT        0x06
+#define PIC_ICI0_INTR_TIMEOUT   0x08
+#define PIC_ICI1_INTR_TIMEOUT   0x0a
+#define PIC_ICI2_INTR_TIMEOUT   0x0c
+#define PIC_IPI_CTL             0x0e
+#define PIC_INT_ACK             0x10
+#define PIC_INT_PENDING0        0x12
+#define PIC_INT_PENDING1        0x14
+#define PIC_INT_PENDING2        0x16
+
+#define PIC_WDOG0_MAXVAL        0x18
+#define PIC_WDOG0_COUNT         0x1a
+#define PIC_WDOG0_ENABLE0       0x1c
+#define PIC_WDOG0_ENABLE1       0x1e
+#define PIC_WDOG0_BEATCMD       0x20
+#define PIC_WDOG0_BEAT0         0x22
+#define PIC_WDOG0_BEAT1         0x24
+
+#define PIC_WDOG1_MAXVAL        0x26
+#define PIC_WDOG1_COUNT         0x28
+#define PIC_WDOG1_ENABLE0       0x2a
+#define PIC_WDOG1_ENABLE1       0x2c
+#define PIC_WDOG1_BEATCMD       0x2e
+#define PIC_WDOG1_BEAT0         0x30
+#define PIC_WDOG1_BEAT1         0x32
+
+#define PIC_WDOG_MAXVAL(i)      (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
+#define PIC_WDOG_COUNT(i)       (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
+#define PIC_WDOG_ENABLE0(i)     (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
+#define PIC_WDOG_ENABLE1(i)     (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
+#define PIC_WDOG_BEATCMD(i)     (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
+#define PIC_WDOG_BEAT0(i)       (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
+#define PIC_WDOG_BEAT1(i)       (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
+
+#define PIC_TIMER0_MAXVAL    0x34
+#define PIC_TIMER1_MAXVAL    0x36
+#define PIC_TIMER2_MAXVAL    0x38
+#define PIC_TIMER3_MAXVAL    0x3a
+#define PIC_TIMER4_MAXVAL    0x3c
+#define PIC_TIMER5_MAXVAL    0x3e
+#define PIC_TIMER6_MAXVAL    0x40
+#define PIC_TIMER7_MAXVAL    0x42
+#define PIC_TIMER_MAXVAL(i)  (PIC_TIMER0_MAXVAL + ((i) * 2))
+
+#define PIC_TIMER0_COUNT     0x44
+#define PIC_TIMER1_COUNT     0x46
+#define PIC_TIMER2_COUNT     0x48
+#define PIC_TIMER3_COUNT     0x4a
+#define PIC_TIMER4_COUNT     0x4c
+#define PIC_TIMER5_COUNT     0x4e
+#define PIC_TIMER6_COUNT     0x50
+#define PIC_TIMER7_COUNT     0x52
+#define PIC_TIMER_COUNT(i)   (PIC_TIMER0_COUNT + ((i) * 2))
+
+#define PIC_ITE0_N0_N1          0x54
+#define PIC_ITE1_N0_N1          0x58
+#define PIC_ITE2_N0_N1          0x5c
+#define PIC_ITE3_N0_N1          0x60
+#define PIC_ITE4_N0_N1          0x64
+#define PIC_ITE5_N0_N1          0x68
+#define PIC_ITE6_N0_N1          0x6c
+#define PIC_ITE7_N0_N1          0x70
+#define PIC_ITE_N0_N1(i)        (PIC_ITE0_N0_N1 + ((i) * 4))
+
+#define PIC_ITE0_N2_N3          0x56
+#define PIC_ITE1_N2_N3          0x5a
+#define PIC_ITE2_N2_N3          0x5e
+#define PIC_ITE3_N2_N3          0x62
+#define PIC_ITE4_N2_N3          0x66
+#define PIC_ITE5_N2_N3          0x6a
+#define PIC_ITE6_N2_N3          0x6e
+#define PIC_ITE7_N2_N3          0x72
+#define PIC_ITE_N2_N3(i)        (PIC_ITE0_N2_N3 + ((i) * 4))
+
+#define PIC_IRT0                0x74
+#define PIC_IRT(i)              (PIC_IRT0 + ((i) * 2))
+
+#define TIMER_CYCLES_MAXVAL     0xffffffffffffffffULL
+
+/*
+ *    IRT Map
+ */
+#define PIC_NUM_IRTS            160
+
+#define PIC_IRT_WD_0_INDEX      0
+#define PIC_IRT_WD_1_INDEX      1
+#define PIC_IRT_WD_NMI_0_INDEX  2
+#define PIC_IRT_WD_NMI_1_INDEX  3
+#define PIC_IRT_TIMER_0_INDEX   4
+#define PIC_IRT_TIMER_1_INDEX   5
+#define PIC_IRT_TIMER_2_INDEX   6
+#define PIC_IRT_TIMER_3_INDEX   7
+#define PIC_IRT_TIMER_4_INDEX   8
+#define PIC_IRT_TIMER_5_INDEX   9
+#define PIC_IRT_TIMER_6_INDEX   10
+#define PIC_IRT_TIMER_7_INDEX   11
+#define PIC_IRT_CLOCK_INDEX     PIC_IRT_TIMER_7_INDEX
+#define PIC_IRT_TIMER_INDEX(num)        ((num) + PIC_IRT_TIMER_0_INDEX)
+
+
+/* 11 and 12 */
+#define PIC_NUM_MSG_Q_IRTS      32
+#define PIC_IRT_MSG_Q0_INDEX    12
+#define PIC_IRT_MSG_Q_INDEX(qid)        ((qid) + PIC_IRT_MSG_Q0_INDEX)
+/* 12 to 43 */
+#define PIC_IRT_MSG_0_INDEX     44
+#define PIC_IRT_MSG_1_INDEX     45
+/* 44 and 45 */
+#define PIC_NUM_PCIE_MSIX_IRTS  32
+#define PIC_IRT_PCIE_MSIX_0_INDEX       46
+#define PIC_IRT_PCIE_MSIX_INDEX(num)    ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
+/* 46 to 77 */
+#define PIC_NUM_PCIE_LINK_IRTS          4
+#define PIC_IRT_PCIE_LINK_0_INDEX       78
+#define PIC_IRT_PCIE_LINK_1_INDEX       79
+#define PIC_IRT_PCIE_LINK_2_INDEX       80
+#define PIC_IRT_PCIE_LINK_3_INDEX       81
+#define PIC_IRT_PCIE_LINK_INDEX(num)    ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
+/* 78 to 81 */
+#define PIC_NUM_NA_IRTS                 32
+/* 82 to 113 */
+#define PIC_IRT_NA_0_INDEX              82
+#define PIC_IRT_NA_INDEX(num)           ((num) + PIC_IRT_NA_0_INDEX)
+#define PIC_IRT_POE_INDEX               114
+
+#define PIC_NUM_USB_IRTS                6
+#define PIC_IRT_USB_0_INDEX             115
+#define PIC_IRT_EHCI_0_INDEX            115
+#define PIC_IRT_EHCI_1_INDEX            118
+#define PIC_IRT_USB_INDEX(num)          ((num) + PIC_IRT_USB_0_INDEX)
+/* 115 to 120 */
+#define PIC_IRT_GDX_INDEX               121
+#define PIC_IRT_SEC_INDEX               122
+#define PIC_IRT_RSA_INDEX               123
+
+#define PIC_NUM_COMP_IRTS               4
+#define PIC_IRT_COMP_0_INDEX            124
+#define PIC_IRT_COMP_INDEX(num)         ((num) + PIC_IRT_COMP_0_INDEX)
+/* 124 to 127 */
+#define PIC_IRT_GBU_INDEX               128
+#define PIC_IRT_ICC_0_INDEX             129 /* ICC - Inter Chip Coherency */
+#define PIC_IRT_ICC_1_INDEX             130
+#define PIC_IRT_ICC_2_INDEX             131
+#define PIC_IRT_CAM_INDEX               132
+#define PIC_IRT_UART_0_INDEX            133
+#define PIC_IRT_UART_1_INDEX            134
+#define PIC_IRT_I2C_0_INDEX             135
+#define PIC_IRT_I2C_1_INDEX             136
+#define PIC_IRT_SYS_0_INDEX             137
+#define PIC_IRT_SYS_1_INDEX             138
+#define PIC_IRT_JTAG_INDEX              139
+#define PIC_IRT_PIC_INDEX               140
+#define PIC_IRT_NBU_INDEX               141
+#define PIC_IRT_TCU_INDEX               142
+#define PIC_IRT_GCU_INDEX               143 /* GBC - Global Coherency */
+#define PIC_IRT_DMC_0_INDEX             144
+#define PIC_IRT_DMC_1_INDEX             145
+
+#define PIC_NUM_GPIO_IRTS               4
+#define PIC_IRT_GPIO_0_INDEX            146
+#define PIC_IRT_GPIO_INDEX(num)         ((num) + PIC_IRT_GPIO_0_INDEX)
+
+/* 146 to 149 */
+#define PIC_IRT_NOR_INDEX               150
+#define PIC_IRT_NAND_INDEX              151
+#define PIC_IRT_SPI_INDEX               152
+#define PIC_IRT_MMC_INDEX               153
+
+#define PIC_CLOCK_TIMER                 7
+#define PIC_IRQ_BASE                    8
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define PIC_IRT_FIRST_IRQ               (PIC_IRQ_BASE)
+#define PIC_IRT_LAST_IRQ                63
+#define PIC_IRQ_IS_IRT(irq)             ((irq) >= PIC_IRT_FIRST_IRQ)
+
+/*
+ *   Misc
+ */
+#define PIC_IRT_VALID                   1
+#define PIC_LOCAL_SCHEDULING            1
+#define PIC_GLOBAL_SCHEDULING           0
+
+#define nlm_read_pic_reg(b, r)  nlm_read_reg64(b, r)
+#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
+#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
+#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+/* IRT and h/w interrupt routines */
+static inline int
+nlm_pic_read_irt(uint64_t base, int irt_index)
+{
+        return nlm_read_pic_reg(base, PIC_IRT(irt_index));
+}
+
+static inline uint64_t
+nlm_pic_read_control(uint64_t base)
+{
+        return nlm_read_pic_reg(base, PIC_CTRL);
+}
+
+static inline void
+nlm_pic_write_control(uint64_t base, uint64_t control)
+{
+        nlm_write_pic_reg(base, PIC_CTRL, control);
+}
+
+static inline void
+nlm_pic_update_control(uint64_t base, uint64_t control)
+{
+        uint64_t val;
+
+        val = nlm_read_pic_reg(base, PIC_CTRL);
+        nlm_write_pic_reg(base, PIC_CTRL, control | val);
+}
+
+static inline void
+nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
+{
+        uint64_t val;
+
+        val = nlm_read_pic_reg(base, PIC_IRT(irt));
+        val |= cpu & 0xf;
+        if (cpu > 15)
+                val |= 1 << 16;
+        nlm_write_pic_reg(base, PIC_IRT(irt), val);
+}
+
+static inline void
+nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
+        int sch, int vec, int dt, int db, int dte)
+{
+        uint64_t val;
+
+        val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
+                        ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
+                        ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
+                        (dte & 0xffff);
+
+        nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
+}
+
+static inline void
+nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
+        int sch, int vec, int cpu)
+{
+        nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
+                (cpu >> 4),             /* thread group */
+                1 << (cpu & 0xf));      /* thread mask */
+}
+
+static inline uint64_t
+nlm_pic_read_timer(uint64_t base, int timer)
+{
+        return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
+}
+
+static inline void
+nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
+{
+        nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
+}
+
+static inline void
+nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
+{
+        uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
+        int en;
+
+        en = (irq > 0);
+        nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
+        nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
+                en, 0, 0, irq, cpu);
+
+        /* enable the timer */
+        pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
+        nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
+}
+
+static inline void
+nlm_pic_enable_irt(uint64_t base, int irt)
+{
+        uint64_t reg;
+
+        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+        nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
+}
+
+static inline void
+nlm_pic_disable_irt(uint64_t base, int irt)
+{
+        uint32_t reg;
+
+        reg = nlm_read_pic_reg(base, PIC_IRT(irt));
+        nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
+}
+
+static inline void
+nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
+{
+        uint64_t ipi;
+        int     node, ncpu;
+
+        node = hwt / 32;
+        ncpu = hwt & 0x1f;
+        ipi = ((uint64_t)nmi << 31) | (irq << 20) | (node << 17) |
+                (1 << (ncpu & 0xf));
+        if (ncpu > 15)
+                ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
+
+        nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
+}
+
+static inline void
+nlm_pic_ack(uint64_t base, int irt_num)
+{
+        nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
+
+        /* Ack the Status register for Watchdog & System timers */
+        if (irt_num < 12)
+                nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
+}
+
+static inline void
+nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
+{
+        nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, 0);
+}
+
+extern uint64_t nlm_pic_base;
+int nlm_irq_to_irt(int irq);
+int nlm_irt_to_irq(int irt);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
new file mode 100644
index 000000000000..21432f7d89b9
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_SYS_H__
+#define __NLM_HAL_SYS_H__
+
+/**
+* @file_name sys.h
+* @author Netlogic Microsystems
+* @brief HAL for System configuration registers
+*/
+#define SYS_CHIP_RESET                          0x00
+#define SYS_POWER_ON_RESET_CFG                  0x01
+#define SYS_EFUSE_DEVICE_CFG_STATUS0            0x02
+#define SYS_EFUSE_DEVICE_CFG_STATUS1            0x03
+#define SYS_EFUSE_DEVICE_CFG_STATUS2            0x04
+#define SYS_EFUSE_DEVICE_CFG3                   0x05
+#define SYS_EFUSE_DEVICE_CFG4                   0x06
+#define SYS_EFUSE_DEVICE_CFG5                   0x07
+#define SYS_EFUSE_DEVICE_CFG6                   0x08
+#define SYS_EFUSE_DEVICE_CFG7                   0x09
+#define SYS_PLL_CTRL                            0x0a
+#define SYS_CPU_RESET                           0x0b
+#define SYS_CPU_NONCOHERENT_MODE                0x0d
+#define SYS_CORE_DFS_DIS_CTRL                   0x0e
+#define SYS_CORE_DFS_RST_CTRL                   0x0f
+#define SYS_CORE_DFS_BYP_CTRL                   0x10
+#define SYS_CORE_DFS_PHA_CTRL                   0x11
+#define SYS_CORE_DFS_DIV_INC_CTRL               0x12
+#define SYS_CORE_DFS_DIV_DEC_CTRL               0x13
+#define SYS_CORE_DFS_DIV_VALUE                  0x14
+#define SYS_RESET                               0x15
+#define SYS_DFS_DIS_CTRL                        0x16
+#define SYS_DFS_RST_CTRL                        0x17
+#define SYS_DFS_BYP_CTRL                        0x18
+#define SYS_DFS_DIV_INC_CTRL                    0x19
+#define SYS_DFS_DIV_DEC_CTRL                    0x1a
+#define SYS_DFS_DIV_VALUE0                      0x1b
+#define SYS_DFS_DIV_VALUE1                      0x1c
+#define SYS_SENSE_AMP_DLY                       0x1d
+#define SYS_SOC_SENSE_AMP_DLY                   0x1e
+#define SYS_CTRL0                               0x1f
+#define SYS_CTRL1                               0x20
+#define SYS_TIMEOUT_BS1                         0x21
+#define SYS_BYTE_SWAP                           0x22
+#define SYS_VRM_VID                             0x23
+#define SYS_PWR_RAM_CMD                         0x24
+#define SYS_PWR_RAM_ADDR                        0x25
+#define SYS_PWR_RAM_DATA0                       0x26
+#define SYS_PWR_RAM_DATA1                       0x27
+#define SYS_PWR_RAM_DATA2                       0x28
+#define SYS_PWR_UCODE                           0x29
+#define SYS_CPU0_PWR_STATUS                     0x2a
+#define SYS_CPU1_PWR_STATUS                     0x2b
+#define SYS_CPU2_PWR_STATUS                     0x2c
+#define SYS_CPU3_PWR_STATUS                     0x2d
+#define SYS_CPU4_PWR_STATUS                     0x2e
+#define SYS_CPU5_PWR_STATUS                     0x2f
+#define SYS_CPU6_PWR_STATUS                     0x30
+#define SYS_CPU7_PWR_STATUS                     0x31
+#define SYS_STATUS                              0x32
+#define SYS_INT_POL                             0x33
+#define SYS_INT_TYPE                            0x34
+#define SYS_INT_STATUS                          0x35
+#define SYS_INT_MASK0                           0x36
+#define SYS_INT_MASK1                           0x37
+#define SYS_UCO_S_ECC                           0x38
+#define SYS_UCO_M_ECC                           0x39
+#define SYS_UCO_ADDR                            0x3a
+#define SYS_UCO_INSTR                           0x3b
+#define SYS_MEM_BIST0                           0x3c
+#define SYS_MEM_BIST1                           0x3d
+#define SYS_MEM_BIST2                           0x3e
+#define SYS_MEM_BIST3                           0x3f
+#define SYS_MEM_BIST4                           0x40
+#define SYS_MEM_BIST5                           0x41
+#define SYS_MEM_BIST6                           0x42
+#define SYS_MEM_BIST7                           0x43
+#define SYS_MEM_BIST8                           0x44
+#define SYS_MEM_BIST9                           0x45
+#define SYS_MEM_BIST10                          0x46
+#define SYS_MEM_BIST11                          0x47
+#define SYS_MEM_BIST12                          0x48
+#define SYS_SCRTCH0                             0x49
+#define SYS_SCRTCH1                             0x4a
+#define SYS_SCRTCH2                             0x4b
+#define SYS_SCRTCH3                             0x4c
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_sys_reg(b, r)          nlm_read_reg(b, r)
+#define nlm_write_sys_reg(b, r, v)      nlm_write_reg(b, r, v)
+#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
+#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
+
+extern uint64_t nlm_sys_base;
+#endif
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
new file mode 100644
index 000000000000..6a7046ca094d
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __XLP_HAL_UART_H__
+#define __XLP_HAL_UART_H__
+
+/* UART Specific registers */
+#define UART_RX_DATA            0x00
+#define UART_TX_DATA            0x00
+
+#define UART_INT_EN             0x01
+#define UART_INT_ID             0x02
+#define UART_FIFO_CTL           0x02
+#define UART_LINE_CTL           0x03
+#define UART_MODEM_CTL          0x04
+#define UART_LINE_STS           0x05
+#define UART_MODEM_STS          0x06
+
+#define UART_DIVISOR0           0x00
+#define UART_DIVISOR1           0x01
+
+#define BASE_BAUD               (XLP_IO_CLK/16)
+#define BAUD_DIVISOR(baud)      (BASE_BAUD / baud)
+
+/* LCR mask values */
+#define LCR_5BITS               0x00
+#define LCR_6BITS               0x01
+#define LCR_7BITS               0x02
+#define LCR_8BITS               0x03
+#define LCR_STOPB               0x04
+#define LCR_PENAB               0x08
+#define LCR_PODD                0x00
+#define LCR_PEVEN               0x10
+#define LCR_PONE                0x20
+#define LCR_PZERO               0x30
+#define LCR_SBREAK              0x40
+#define LCR_EFR_ENABLE          0xbf
+#define LCR_DLAB                0x80
+
+/* MCR mask values */
+#define MCR_DTR                 0x01
+#define MCR_RTS                 0x02
+#define MCR_DRS                 0x04
+#define MCR_IE                  0x08
+#define MCR_LOOPBACK            0x10
+
+/* FCR mask values */
+#define FCR_RCV_RST             0x02
+#define FCR_XMT_RST             0x04
+#define FCR_RX_LOW              0x00
+#define FCR_RX_MEDL             0x40
+#define FCR_RX_MEDH             0x80
+#define FCR_RX_HIGH             0xc0
+
+/* IER mask values */
+#define IER_ERXRDY              0x1
+#define IER_ETXRDY              0x2
+#define IER_ERLS                0x4
+#define IER_EMSC                0x8
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+
+#define nlm_read_uart_reg(b, r)         nlm_read_reg(b, r)
+#define nlm_write_uart_reg(b, r, v)     nlm_write_reg(b, r, v)
+#define nlm_get_uart_pcibase(node, inst)        \
+                nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
+#define nlm_get_uart_regbase(node, inst)        \
+                        (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
+
+static inline void
+nlm_uart_set_baudrate(uint64_t base, int baud)
+{
+        uint32_t lcr;
+
+        lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
+
+        /* enable divisor register, and write baud values */
+        nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
+        nlm_write_uart_reg(base, UART_DIVISOR0,
+                        (BAUD_DIVISOR(baud) & 0xff));
+        nlm_write_uart_reg(base, UART_DIVISOR1,
+                        ((BAUD_DIVISOR(baud) >> 8) & 0xff));
+
+        /* restore default lcr */
+        nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
+}
+
+static inline void
+nlm_uart_outbyte(uint64_t base, char c)
+{
+        uint32_t lsr;
+
+        for (;;) {
+                lsr = nlm_read_uart_reg(base, UART_LINE_STS);
+                if (lsr & 0x20)
+                        break;
+        }
+
+        nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
+}
+
+static inline char
+nlm_uart_inbyte(uint64_t base)
+{
+        int data, lsr;
+
+        for (;;) {
+                lsr = nlm_read_uart_reg(base, UART_LINE_STS);
+                if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
+                        data = 0;
+                        break;
+                }
+                if (lsr & 0x01) {       /* Rx data */
+                        data = nlm_read_uart_reg(base, UART_RX_DATA);
+                        break;
+                }
+        }
+
+        return (char)data;
+}
+
+static inline int
+nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
+        int parity, int int_en, int loopback)
+{
+        uint32_t lcr;
+
+        lcr = 0;
+        if (databits >= 8)
+                lcr |= LCR_8BITS;
+        else if (databits == 7)
+                lcr |= LCR_7BITS;
+        else if (databits == 6)
+                lcr |= LCR_6BITS;
+        else
+                lcr |= LCR_5BITS;
+
+        if (stopbits > 1)
+                lcr |= LCR_STOPB;
+
+        lcr |= parity << 3;
+
+        /* setup default lcr */
+        nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
+
+        /* Reset the FIFOs */
+        nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
+
+        nlm_uart_set_baudrate(base, baud);
+
+        if (loopback)
+                nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
+
+        if (int_en)
+                nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
+
+        return 0;
+}
+#endif /* !LOCORE && !__ASSEMBLY__ */
+#endif /* __XLP_HAL_UART_H__ */
diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 759df0692201..1540588e396d 100644
--- a/arch/mips/netlogic/xlr/xlr_console.c
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -32,15 +32,20 @@
  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <linux/types.h>
-#include <asm/netlogic/xlr/iomap.h>
+#ifndef _NLM_HAL_XLP_H
+#define _NLM_HAL_XLP_H
 
-void prom_putchar(char c)
-{
-        nlm_reg_t *mmio;
+#define PIC_UART_0_IRQ           17
+#define PIC_UART_1_IRQ           18
 
-        mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
-        while (netlogic_read_reg(mmio, 0x5) == 0)
-                ;
-        netlogic_write_reg(mmio, 0x0, c);
-}
+#ifndef __ASSEMBLY__
+
+/* SMP support functions */
+void xlp_boot_core0_siblings(void);
+void xlp_wakeup_secondary_cpus(void);
+
+void xlp_mmu_init(void);
+void nlm_hal_init(void);
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
index 2e3a4dd53045..2e768f032e83 100644
--- a/arch/mips/include/asm/netlogic/xlr/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -106,26 +106,4 @@
 #define DEFAULT_HT_TYPE0_CFG_BASE       0x16000000
 #define DEFAULT_HT_TYPE1_CFG_BASE       0x17000000
 
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#include <asm/byteorder.h>
-
-typedef volatile __u32 nlm_reg_t;
-extern unsigned long netlogic_io_base;
-
-/* FIXME read once in write_reg */
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-#define netlogic_read_reg(base, offset)         ((base)[(offset)])
-#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
-#else
-#define netlogic_read_reg(base, offset)         (be32_to_cpu((base)[(offset)]))
-#define netlogic_write_reg(base, offset, value) \
-                                ((base)[(offset)] = cpu_to_be32((value)))
-#endif
-
-#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
-#define netlogic_write_reg_le32(base, offset, value) \
-                                ((base)[(offset)] = cpu_to_le32((value)))
-#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
-#endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
new file mode 100644
index 000000000000..7e39d40be4f5
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/msidef.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ASM_RMI_MSIDEF_H
+#define ASM_RMI_MSIDEF_H
+
+/*
+ * Constants for Intel APIC based MSI messages.
+ * Adapted for the RMI XLR using identical defines
+ */
+
+/*
+ * Shifts for MSI data
+ */
+
+#define MSI_DATA_VECTOR_SHIFT           0
+#define  MSI_DATA_VECTOR_MASK           0x000000ff
+#define  MSI_DATA_VECTOR(v)             (((v) << MSI_DATA_VECTOR_SHIFT) & \
+                                                MSI_DATA_VECTOR_MASK)
+
+#define MSI_DATA_DELIVERY_MODE_SHIFT    8
+#define  MSI_DATA_DELIVERY_FIXED        (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
+#define  MSI_DATA_DELIVERY_LOWPRI       (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
+
+#define MSI_DATA_LEVEL_SHIFT            14
+#define  MSI_DATA_LEVEL_DEASSERT        (0 << MSI_DATA_LEVEL_SHIFT)
+#define  MSI_DATA_LEVEL_ASSERT          (1 << MSI_DATA_LEVEL_SHIFT)
+
+#define MSI_DATA_TRIGGER_SHIFT          15
+#define  MSI_DATA_TRIGGER_EDGE          (0 << MSI_DATA_TRIGGER_SHIFT)
+#define  MSI_DATA_TRIGGER_LEVEL         (1 << MSI_DATA_TRIGGER_SHIFT)
+
+/*
+ * Shift/mask fields for msi address
+ */
+
+#define MSI_ADDR_BASE_HI                0
+#define MSI_ADDR_BASE_LO                0xfee00000
+
+#define MSI_ADDR_DEST_MODE_SHIFT        2
+#define  MSI_ADDR_DEST_MODE_PHYSICAL    (0 << MSI_ADDR_DEST_MODE_SHIFT)
+#define  MSI_ADDR_DEST_MODE_LOGICAL     (1 << MSI_ADDR_DEST_MODE_SHIFT)
+
+#define MSI_ADDR_REDIRECTION_SHIFT      3
+#define  MSI_ADDR_REDIRECTION_CPU       (0 << MSI_ADDR_REDIRECTION_SHIFT)
+#define  MSI_ADDR_REDIRECTION_LOWPRI    (1 << MSI_ADDR_REDIRECTION_SHIFT)
+
+#define MSI_ADDR_DEST_ID_SHIFT          12
+#define  MSI_ADDR_DEST_ID_MASK          0x00ffff0
+#define  MSI_ADDR_DEST_ID(dest)         (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
+                                                 MSI_ADDR_DEST_ID_MASK)
+
+#endif /* ASM_RMI_MSIDEF_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 5cceb746f080..868013e62f32 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -193,39 +193,72 @@
 /* end XLS */
 
 #ifndef __ASSEMBLY__
-static inline void pic_send_ipi(u32 ipi)
+
+#define PIC_IRQ_IS_EDGE_TRIGGERED(irq)  (((irq) >= PIC_TIMER_0_IRQ) && \
+                                        ((irq) <= PIC_TIMER_7_IRQ))
+#define PIC_IRQ_IS_IRT(irq)             (((irq) >= PIC_IRT_FIRST_IRQ) && \
+                                        ((irq) <= PIC_IRT_LAST_IRQ))
+
+static inline int
+nlm_irq_to_irt(int irq)
 {
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        if (PIC_IRQ_IS_IRT(irq) == 0)
+                return -1;
 
-        netlogic_write_reg(mmio, PIC_IPI, ipi);
+        return PIC_IRQ_TO_INTR(irq);
 }
 
-static inline u32 pic_read_control(void)
+static inline int
+nlm_irt_to_irq(int irt)
 {
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
 
-        return netlogic_read_reg(mmio, PIC_CTRL);
+        return PIC_INTR_TO_IRQ(irt);
 }
 
-static inline void pic_write_control(u32 control)
+static inline void
+nlm_pic_enable_irt(uint64_t base, int irt)
 {
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        uint32_t reg;
 
-        netlogic_write_reg(mmio, PIC_CTRL, control);
+        reg = nlm_read_reg(base, PIC_IRT_1(irt));
+        nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
 }
 
-static inline void pic_update_control(u32 control)
+static inline void
+nlm_pic_disable_irt(uint64_t base, int irt)
 {
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        uint32_t reg;
 
-        netlogic_write_reg(mmio, PIC_CTRL,
-                (control | netlogic_read_reg(mmio, PIC_CTRL)));
+        reg = nlm_read_reg(base, PIC_IRT_1(irt));
+        nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
 }
 
-#define PIC_IRQ_IS_EDGE_TRIGGERED(irq)  (((irq) >= PIC_TIMER_0_IRQ) && \
-                                        ((irq) <= PIC_TIMER_7_IRQ))
-#define PIC_IRQ_IS_IRT(irq)             (((irq) >= PIC_IRT_FIRST_IRQ) && \
-                                        ((irq) <= PIC_IRT_LAST_IRQ))
-#endif
+static inline void
+nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
+{
+        unsigned int tid, pid;
+
+        tid = hwt & 0x3;
+        pid = (hwt >> 2) & 0x07;
+        nlm_write_reg(base, PIC_IPI,
+                (pid << 20) | (tid << 16) | (nmi << 8) | irq);
+}
+
+static inline void
+nlm_pic_ack(uint64_t base, int irt)
+{
+        nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
+}
 
+static inline void
+nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
+{
+        nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
+        /* local scheduling, invalid, level by default */
+        nlm_write_reg(base, PIC_IRT_1(irt),
+                (1 << 30) | (1 << 6) | irq);
+}
+
+extern uint64_t nlm_pic_base;
+#endif
 #endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index 3e6372692a04..ff4a17b0bf78 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -40,17 +40,8 @@ struct uart_port;
 unsigned int nlm_xlr_uart_in(struct uart_port *, int);
 void nlm_xlr_uart_out(struct uart_port *, int, int);
 
-/* SMP support functions */
-struct irq_desc;
-void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
-void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
-int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
-void nlm_smp_irq_init(void);
-void nlm_boot_smp_nmi(void);
-void prom_pre_boot_secondary_cpus(void);
-
-extern struct plat_smp_ops nlm_smp_ops;
-extern unsigned long nlm_common_ebase;
+/* SMP helpers */
+void xlr_wakeup_secondary_cpus(void);
 
 /* XLS B silicon "Rook" */
 static inline unsigned int nlm_chip_is_xls_b(void)
diff --git a/drivers/staging/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h
index 3c74d826e2e6..3c74d826e2e6 100644
--- a/drivers/staging/octeon/cvmx-address.h
+++ b/arch/mips/include/asm/octeon/cvmx-address.h
diff --git a/drivers/staging/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
index 91415a85e8d2..91415a85e8d2 100644
--- a/drivers/staging/octeon/cvmx-asxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 4e4c3a8282d6..1db1dc2724cb 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -39,7 +39,7 @@
  * versions.
  */
 #define CVMX_BOOTINFO_MAJ_VER 1
-#define CVMX_BOOTINFO_MIN_VER 2
+#define CVMX_BOOTINFO_MIN_VER 3
 
 #if (CVMX_BOOTINFO_MAJ_VER == 1)
 #define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
@@ -116,7 +116,13 @@ struct cvmx_bootinfo {
          */
         uint32_t config_flags;
 #endif
-
+#if (CVMX_BOOTINFO_MIN_VER >= 3)
+        /*
+         * Address of the OF Flattened Device Tree structure
+         * describing the board.
+         */
+        uint64_t fdt_addr;
+#endif
 };
 
 #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST                 (1ull << 0)
@@ -164,6 +170,22 @@ enum cvmx_board_types_enum {
         /* Special 'generic' board type, supports many boards */
         CVMX_BOARD_TYPE_GENERIC = 28,
         CVMX_BOARD_TYPE_EBH5610 = 29,
+        CVMX_BOARD_TYPE_LANAI2_A = 30,
+        CVMX_BOARD_TYPE_LANAI2_U = 31,
+        CVMX_BOARD_TYPE_EBB5600 = 32,
+        CVMX_BOARD_TYPE_EBB6300 = 33,
+        CVMX_BOARD_TYPE_NIC_XLE_10G = 34,
+        CVMX_BOARD_TYPE_LANAI2_G = 35,
+        CVMX_BOARD_TYPE_EBT5810 = 36,
+        CVMX_BOARD_TYPE_NIC10E = 37,
+        CVMX_BOARD_TYPE_EP6300C = 38,
+        CVMX_BOARD_TYPE_EBB6800 = 39,
+        CVMX_BOARD_TYPE_NIC4E = 40,
+        CVMX_BOARD_TYPE_NIC2E = 41,
+        CVMX_BOARD_TYPE_EBB6600 = 42,
+        CVMX_BOARD_TYPE_REDWING = 43,
+        CVMX_BOARD_TYPE_NIC68_4 = 44,
+        CVMX_BOARD_TYPE_NIC10E_66 = 45,
         CVMX_BOARD_TYPE_MAX,
 
         /*
@@ -181,6 +203,23 @@ enum cvmx_board_types_enum {
         CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
         CVMX_BOARD_TYPE_CUST_NB5 = 10003,
         CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
+        CVMX_BOARD_TYPE_CUST_ITB101 = 10005,
+        CVMX_BOARD_TYPE_CUST_NTE102 = 10006,
+        CVMX_BOARD_TYPE_CUST_AGS103 = 10007,
+        CVMX_BOARD_TYPE_CUST_GST104 = 10008,
+        CVMX_BOARD_TYPE_CUST_GCT105 = 10009,
+        CVMX_BOARD_TYPE_CUST_AGS106 = 10010,
+        CVMX_BOARD_TYPE_CUST_SGM107 = 10011,
+        CVMX_BOARD_TYPE_CUST_GCT108 = 10012,
+        CVMX_BOARD_TYPE_CUST_AGS109 = 10013,
+        CVMX_BOARD_TYPE_CUST_GCT110 = 10014,
+        CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015,
+        CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016,
+        CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017,
+        CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018,
+        CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019,
+        CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020,
+        CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021,
         CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
 
         /*
@@ -241,6 +280,22 @@ static inline const char *cvmx_board_type_to_string(enum
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
 
                         /* Customer boards listed here */
@@ -249,6 +304,23 @@ static inline const char *cvmx_board_type_to_string(enum
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
 
                     /* Customer private range */
@@ -265,9 +337,9 @@ static inline const char *cvmx_chip_type_to_string(enum
 {
         switch (type) {
                 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
-                    ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
-                    ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
-                    ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
+                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
+                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
+                ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
         }
         return "Unsupported Chip";
 }
diff --git a/drivers/staging/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
index 614653b686a0..614653b686a0 100644
--- a/drivers/staging/octeon/cvmx-cmd-queue.h
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
diff --git a/drivers/staging/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h
index 078a520481cf..26835d1b43b8 100644
--- a/drivers/staging/octeon/cvmx-config.h
+++ b/arch/mips/include/asm/octeon/cvmx-config.h
@@ -166,4 +166,3 @@ typedef enum {
 #define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
 
 #endif /* __CVMX_CONFIG_H__ */
-
diff --git a/drivers/staging/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
index abbf42d05e5a..abbf42d05e5a 100644
--- a/drivers/staging/octeon/cvmx-dbg-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
new file mode 100644
index 000000000000..c34ad04789ce
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
@@ -0,0 +1,643 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_DPI_DEFS_H__
+#define __CVMX_DPI_DEFS_H__
+
+#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
+#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
+#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
+#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
+#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
+#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
+#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
+#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
+#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
+#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
+#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
+#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
+#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
+#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
+#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
+#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
+#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
+#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
+
+union cvmx_dpi_bist_status {
+        uint64_t u64;
+        struct cvmx_dpi_bist_status_s {
+                uint64_t reserved_47_63:17;
+                uint64_t bist:47;
+        } s;
+        struct cvmx_dpi_bist_status_s cn61xx;
+        struct cvmx_dpi_bist_status_cn63xx {
+                uint64_t reserved_45_63:19;
+                uint64_t bist:45;
+        } cn63xx;
+        struct cvmx_dpi_bist_status_cn63xxp1 {
+                uint64_t reserved_37_63:27;
+                uint64_t bist:37;
+        } cn63xxp1;
+        struct cvmx_dpi_bist_status_s cn66xx;
+        struct cvmx_dpi_bist_status_cn63xx cn68xx;
+        struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_ctl {
+        uint64_t u64;
+        struct cvmx_dpi_ctl_s {
+                uint64_t reserved_2_63:62;
+                uint64_t clk:1;
+                uint64_t en:1;
+        } s;
+        struct cvmx_dpi_ctl_cn61xx {
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+        } cn61xx;
+        struct cvmx_dpi_ctl_s cn63xx;
+        struct cvmx_dpi_ctl_s cn63xxp1;
+        struct cvmx_dpi_ctl_s cn66xx;
+        struct cvmx_dpi_ctl_s cn68xx;
+        struct cvmx_dpi_ctl_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_counts {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_counts_s {
+                uint64_t reserved_39_63:25;
+                uint64_t fcnt:7;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_dpi_dmax_counts_s cn61xx;
+        struct cvmx_dpi_dmax_counts_s cn63xx;
+        struct cvmx_dpi_dmax_counts_s cn63xxp1;
+        struct cvmx_dpi_dmax_counts_s cn66xx;
+        struct cvmx_dpi_dmax_counts_s cn68xx;
+        struct cvmx_dpi_dmax_counts_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_dbell {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_dbell_s {
+                uint64_t reserved_16_63:48;
+                uint64_t dbell:16;
+        } s;
+        struct cvmx_dpi_dmax_dbell_s cn61xx;
+        struct cvmx_dpi_dmax_dbell_s cn63xx;
+        struct cvmx_dpi_dmax_dbell_s cn63xxp1;
+        struct cvmx_dpi_dmax_dbell_s cn66xx;
+        struct cvmx_dpi_dmax_dbell_s cn68xx;
+        struct cvmx_dpi_dmax_dbell_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_err_rsp_status {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_err_rsp_status_s {
+                uint64_t reserved_6_63:58;
+                uint64_t status:6;
+        } s;
+        struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
+        struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
+        struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
+        struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_ibuff_saddr {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_ibuff_saddr_s {
+                uint64_t reserved_62_63:2;
+                uint64_t csize:14;
+                uint64_t reserved_41_47:7;
+                uint64_t idle:1;
+                uint64_t saddr:33;
+                uint64_t reserved_0_6:7;
+        } s;
+        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
+                uint64_t reserved_62_63:2;
+                uint64_t csize:14;
+                uint64_t reserved_41_47:7;
+                uint64_t idle:1;
+                uint64_t reserved_36_39:4;
+                uint64_t saddr:29;
+                uint64_t reserved_0_6:7;
+        } cn61xx;
+        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
+        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
+        struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
+        struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
+        struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_iflight {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_iflight_s {
+                uint64_t reserved_3_63:61;
+                uint64_t cnt:3;
+        } s;
+        struct cvmx_dpi_dmax_iflight_s cn61xx;
+        struct cvmx_dpi_dmax_iflight_s cn66xx;
+        struct cvmx_dpi_dmax_iflight_s cn68xx;
+        struct cvmx_dpi_dmax_iflight_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_naddr {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_naddr_s {
+                uint64_t reserved_40_63:24;
+                uint64_t addr:40;
+        } s;
+        struct cvmx_dpi_dmax_naddr_cn61xx {
+                uint64_t reserved_36_63:28;
+                uint64_t addr:36;
+        } cn61xx;
+        struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
+        struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
+        struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
+        struct cvmx_dpi_dmax_naddr_s cn68xx;
+        struct cvmx_dpi_dmax_naddr_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_reqbnk0 {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_reqbnk0_s {
+                uint64_t state:64;
+        } s;
+        struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
+        struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
+        struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
+        struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
+        struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
+        struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_reqbnk1 {
+        uint64_t u64;
+        struct cvmx_dpi_dmax_reqbnk1_s {
+                uint64_t state:64;
+        } s;
+        struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
+        struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
+        struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
+        struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
+        struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
+        struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
+};
+
+union cvmx_dpi_dma_control {
+        uint64_t u64;
+        struct cvmx_dpi_dma_control_s {
+                uint64_t reserved_62_63:2;
+                uint64_t dici_mode:1;
+                uint64_t pkt_en1:1;
+                uint64_t ffp_dis:1;
+                uint64_t commit_mode:1;
+                uint64_t pkt_hp:1;
+                uint64_t pkt_en:1;
+                uint64_t reserved_54_55:2;
+                uint64_t dma_enb:6;
+                uint64_t reserved_34_47:14;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t reserved_0_13:14;
+        } s;
+        struct cvmx_dpi_dma_control_s cn61xx;
+        struct cvmx_dpi_dma_control_cn63xx {
+                uint64_t reserved_61_63:3;
+                uint64_t pkt_en1:1;
+                uint64_t ffp_dis:1;
+                uint64_t commit_mode:1;
+                uint64_t pkt_hp:1;
+                uint64_t pkt_en:1;
+                uint64_t reserved_54_55:2;
+                uint64_t dma_enb:6;
+                uint64_t reserved_34_47:14;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t reserved_0_13:14;
+        } cn63xx;
+        struct cvmx_dpi_dma_control_cn63xxp1 {
+                uint64_t reserved_59_63:5;
+                uint64_t commit_mode:1;
+                uint64_t pkt_hp:1;
+                uint64_t pkt_en:1;
+                uint64_t reserved_54_55:2;
+                uint64_t dma_enb:6;
+                uint64_t reserved_34_47:14;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t reserved_0_13:14;
+        } cn63xxp1;
+        struct cvmx_dpi_dma_control_cn63xx cn66xx;
+        struct cvmx_dpi_dma_control_s cn68xx;
+        struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_dma_engx_en {
+        uint64_t u64;
+        struct cvmx_dpi_dma_engx_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t qen:8;
+        } s;
+        struct cvmx_dpi_dma_engx_en_s cn61xx;
+        struct cvmx_dpi_dma_engx_en_s cn63xx;
+        struct cvmx_dpi_dma_engx_en_s cn63xxp1;
+        struct cvmx_dpi_dma_engx_en_s cn66xx;
+        struct cvmx_dpi_dma_engx_en_s cn68xx;
+        struct cvmx_dpi_dma_engx_en_s cn68xxp1;
+};
+
+union cvmx_dpi_dma_ppx_cnt {
+        uint64_t u64;
+        struct cvmx_dpi_dma_ppx_cnt_s {
+                uint64_t reserved_16_63:48;
+                uint64_t cnt:16;
+        } s;
+        struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
+        struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
+};
+
+union cvmx_dpi_engx_buf {
+        uint64_t u64;
+        struct cvmx_dpi_engx_buf_s {
+                uint64_t reserved_37_63:27;
+                uint64_t compblks:5;
+                uint64_t reserved_9_31:23;
+                uint64_t base:5;
+                uint64_t blks:4;
+        } s;
+        struct cvmx_dpi_engx_buf_s cn61xx;
+        struct cvmx_dpi_engx_buf_cn63xx {
+                uint64_t reserved_8_63:56;
+                uint64_t base:4;
+                uint64_t blks:4;
+        } cn63xx;
+        struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
+        struct cvmx_dpi_engx_buf_s cn66xx;
+        struct cvmx_dpi_engx_buf_s cn68xx;
+        struct cvmx_dpi_engx_buf_s cn68xxp1;
+};
+
+union cvmx_dpi_info_reg {
+        uint64_t u64;
+        struct cvmx_dpi_info_reg_s {
+                uint64_t reserved_8_63:56;
+                uint64_t ffp:4;
+                uint64_t reserved_2_3:2;
+                uint64_t ncb:1;
+                uint64_t rsl:1;
+        } s;
+        struct cvmx_dpi_info_reg_s cn61xx;
+        struct cvmx_dpi_info_reg_s cn63xx;
+        struct cvmx_dpi_info_reg_cn63xxp1 {
+                uint64_t reserved_2_63:62;
+                uint64_t ncb:1;
+                uint64_t rsl:1;
+        } cn63xxp1;
+        struct cvmx_dpi_info_reg_s cn66xx;
+        struct cvmx_dpi_info_reg_s cn68xx;
+        struct cvmx_dpi_info_reg_s cn68xxp1;
+};
+
+union cvmx_dpi_int_en {
+        uint64_t u64;
+        struct cvmx_dpi_int_en_s {
+                uint64_t reserved_28_63:36;
+                uint64_t sprt3_rst:1;
+                uint64_t sprt2_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+        } s;
+        struct cvmx_dpi_int_en_s cn61xx;
+        struct cvmx_dpi_int_en_cn63xx {
+                uint64_t reserved_26_63:38;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+        } cn63xx;
+        struct cvmx_dpi_int_en_cn63xx cn63xxp1;
+        struct cvmx_dpi_int_en_s cn66xx;
+        struct cvmx_dpi_int_en_cn63xx cn68xx;
+        struct cvmx_dpi_int_en_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_int_reg {
+        uint64_t u64;
+        struct cvmx_dpi_int_reg_s {
+                uint64_t reserved_28_63:36;
+                uint64_t sprt3_rst:1;
+                uint64_t sprt2_rst:1;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+        } s;
+        struct cvmx_dpi_int_reg_s cn61xx;
+        struct cvmx_dpi_int_reg_cn63xx {
+                uint64_t reserved_26_63:38;
+                uint64_t sprt1_rst:1;
+                uint64_t sprt0_rst:1;
+                uint64_t reserved_23_23:1;
+                uint64_t req_badfil:1;
+                uint64_t req_inull:1;
+                uint64_t req_anull:1;
+                uint64_t req_undflw:1;
+                uint64_t req_ovrflw:1;
+                uint64_t req_badlen:1;
+                uint64_t req_badadr:1;
+                uint64_t dmadbo:8;
+                uint64_t reserved_2_7:6;
+                uint64_t nfovr:1;
+                uint64_t nderr:1;
+        } cn63xx;
+        struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
+        struct cvmx_dpi_int_reg_s cn66xx;
+        struct cvmx_dpi_int_reg_cn63xx cn68xx;
+        struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_ncbx_cfg {
+        uint64_t u64;
+        struct cvmx_dpi_ncbx_cfg_s {
+                uint64_t reserved_6_63:58;
+                uint64_t molr:6;
+        } s;
+        struct cvmx_dpi_ncbx_cfg_s cn61xx;
+        struct cvmx_dpi_ncbx_cfg_s cn66xx;
+        struct cvmx_dpi_ncbx_cfg_s cn68xx;
+};
+
+union cvmx_dpi_pint_info {
+        uint64_t u64;
+        struct cvmx_dpi_pint_info_s {
+                uint64_t reserved_14_63:50;
+                uint64_t iinfo:6;
+                uint64_t reserved_6_7:2;
+                uint64_t sinfo:6;
+        } s;
+        struct cvmx_dpi_pint_info_s cn61xx;
+        struct cvmx_dpi_pint_info_s cn63xx;
+        struct cvmx_dpi_pint_info_s cn63xxp1;
+        struct cvmx_dpi_pint_info_s cn66xx;
+        struct cvmx_dpi_pint_info_s cn68xx;
+        struct cvmx_dpi_pint_info_s cn68xxp1;
+};
+
+union cvmx_dpi_pkt_err_rsp {
+        uint64_t u64;
+        struct cvmx_dpi_pkt_err_rsp_s {
+                uint64_t reserved_1_63:63;
+                uint64_t pkterr:1;
+        } s;
+        struct cvmx_dpi_pkt_err_rsp_s cn61xx;
+        struct cvmx_dpi_pkt_err_rsp_s cn63xx;
+        struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
+        struct cvmx_dpi_pkt_err_rsp_s cn66xx;
+        struct cvmx_dpi_pkt_err_rsp_s cn68xx;
+        struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rsp {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rsp_s {
+                uint64_t reserved_8_63:56;
+                uint64_t qerr:8;
+        } s;
+        struct cvmx_dpi_req_err_rsp_s cn61xx;
+        struct cvmx_dpi_req_err_rsp_s cn63xx;
+        struct cvmx_dpi_req_err_rsp_s cn63xxp1;
+        struct cvmx_dpi_req_err_rsp_s cn66xx;
+        struct cvmx_dpi_req_err_rsp_s cn68xx;
+        struct cvmx_dpi_req_err_rsp_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rsp_en {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rsp_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+        } s;
+        struct cvmx_dpi_req_err_rsp_en_s cn61xx;
+        struct cvmx_dpi_req_err_rsp_en_s cn63xx;
+        struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
+        struct cvmx_dpi_req_err_rsp_en_s cn66xx;
+        struct cvmx_dpi_req_err_rsp_en_s cn68xx;
+        struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rst {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rst_s {
+                uint64_t reserved_8_63:56;
+                uint64_t qerr:8;
+        } s;
+        struct cvmx_dpi_req_err_rst_s cn61xx;
+        struct cvmx_dpi_req_err_rst_s cn63xx;
+        struct cvmx_dpi_req_err_rst_s cn63xxp1;
+        struct cvmx_dpi_req_err_rst_s cn66xx;
+        struct cvmx_dpi_req_err_rst_s cn68xx;
+        struct cvmx_dpi_req_err_rst_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rst_en {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_rst_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+        } s;
+        struct cvmx_dpi_req_err_rst_en_s cn61xx;
+        struct cvmx_dpi_req_err_rst_en_s cn63xx;
+        struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
+        struct cvmx_dpi_req_err_rst_en_s cn66xx;
+        struct cvmx_dpi_req_err_rst_en_s cn68xx;
+        struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_skip_comp {
+        uint64_t u64;
+        struct cvmx_dpi_req_err_skip_comp_s {
+                uint64_t reserved_24_63:40;
+                uint64_t en_rst:8;
+                uint64_t reserved_8_15:8;
+                uint64_t en_rsp:8;
+        } s;
+        struct cvmx_dpi_req_err_skip_comp_s cn61xx;
+        struct cvmx_dpi_req_err_skip_comp_s cn66xx;
+        struct cvmx_dpi_req_err_skip_comp_s cn68xx;
+        struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
+};
+
+union cvmx_dpi_req_gbl_en {
+        uint64_t u64;
+        struct cvmx_dpi_req_gbl_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t qen:8;
+        } s;
+        struct cvmx_dpi_req_gbl_en_s cn61xx;
+        struct cvmx_dpi_req_gbl_en_s cn63xx;
+        struct cvmx_dpi_req_gbl_en_s cn63xxp1;
+        struct cvmx_dpi_req_gbl_en_s cn66xx;
+        struct cvmx_dpi_req_gbl_en_s cn68xx;
+        struct cvmx_dpi_req_gbl_en_s cn68xxp1;
+};
+
+union cvmx_dpi_sli_prtx_cfg {
+        uint64_t u64;
+        struct cvmx_dpi_sli_prtx_cfg_s {
+                uint64_t reserved_25_63:39;
+                uint64_t halt:1;
+                uint64_t qlm_cfg:4;
+                uint64_t reserved_17_19:3;
+                uint64_t rd_mode:1;
+                uint64_t reserved_14_15:2;
+                uint64_t molr:6;
+                uint64_t mps_lim:1;
+                uint64_t reserved_5_6:2;
+                uint64_t mps:1;
+                uint64_t mrrs_lim:1;
+                uint64_t reserved_2_2:1;
+                uint64_t mrrs:2;
+        } s;
+        struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
+        struct cvmx_dpi_sli_prtx_cfg_cn63xx {
+                uint64_t reserved_25_63:39;
+                uint64_t halt:1;
+                uint64_t reserved_21_23:3;
+                uint64_t qlm_cfg:1;
+                uint64_t reserved_17_19:3;
+                uint64_t rd_mode:1;
+                uint64_t reserved_14_15:2;
+                uint64_t molr:6;
+                uint64_t mps_lim:1;
+                uint64_t reserved_5_6:2;
+                uint64_t mps:1;
+                uint64_t mrrs_lim:1;
+                uint64_t reserved_2_2:1;
+                uint64_t mrrs:2;
+        } cn63xx;
+        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
+        struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
+        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
+        struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_sli_prtx_err {
+        uint64_t u64;
+        struct cvmx_dpi_sli_prtx_err_s {
+                uint64_t addr:61;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_dpi_sli_prtx_err_s cn61xx;
+        struct cvmx_dpi_sli_prtx_err_s cn63xx;
+        struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
+        struct cvmx_dpi_sli_prtx_err_s cn66xx;
+        struct cvmx_dpi_sli_prtx_err_s cn68xx;
+        struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
+};
+
+union cvmx_dpi_sli_prtx_err_info {
+        uint64_t u64;
+        struct cvmx_dpi_sli_prtx_err_info_s {
+                uint64_t reserved_9_63:55;
+                uint64_t lock:1;
+                uint64_t reserved_5_7:3;
+                uint64_t type:1;
+                uint64_t reserved_3_3:1;
+                uint64_t reqq:3;
+        } s;
+        struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
+        struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
+        struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
+        struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
+        struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
+        struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h
index a6939fc8ba18..a6939fc8ba18 100644
--- a/drivers/staging/octeon/cvmx-fau.h
+++ b/arch/mips/include/asm/octeon/cvmx-fau.h
diff --git a/drivers/staging/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
index bf5546b90110..bf5546b90110 100644
--- a/drivers/staging/octeon/cvmx-fpa-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
diff --git a/drivers/staging/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
index 1f04f9658736..1f04f9658736 100644
--- a/drivers/staging/octeon/cvmx-fpa.h
+++ b/arch/mips/include/asm/octeon/cvmx-fpa.h
diff --git a/drivers/staging/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
index 946a43a73fd7..946a43a73fd7 100644
--- a/drivers/staging/octeon/cvmx-gmxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
diff --git a/drivers/staging/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
index b465bec43553..88527fa835c9 100644
--- a/drivers/staging/octeon/cvmx-helper-board.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -44,6 +44,12 @@ typedef enum {
         set_phy_link_flags_flow_control_mask = 0x3 << 1,        /* Mask for 2 bit wide flow control field */
 } cvmx_helper_board_set_phy_link_flags_types_t;
 
+/*
+ * Fake IPD port, the RGMII/MII interface may use different PHY, use
+ * this macro to return appropriate MIX address to read the PHY.
+ */
+#define CVMX_HELPER_BOARD_MGMT_IPD_PORT     -10
+
 /**
  * cvmx_override_board_link_get(int ipd_port) is a function
  * pointer. It is meant to allow customization of the process of
diff --git a/drivers/staging/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
index 5ff8c93198de..5ff8c93198de 100644
--- a/drivers/staging/octeon/cvmx-helper-fpa.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
diff --git a/drivers/staging/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
index e646a6ccce75..077f0e9d3b2d 100644
--- a/drivers/staging/octeon/cvmx-helper-loop.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
@@ -44,6 +44,7 @@
  * Returns Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_loop_probe(int interface);
+static inline int __cvmx_helper_loop_enumerate(int interface) {return 4; }
 
 /**
  * Bringup and enable a LOOP interface. After this call packet
diff --git a/drivers/staging/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
index 908e7b08c214..8df4c7fafdba 100644
--- a/drivers/staging/octeon/cvmx-helper-npi.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
@@ -45,6 +45,7 @@
  * Returns Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_npi_probe(int interface);
+#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe
 
 /**
  * Bringup and enable a NPI interface. After this call packet
diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
index ea2652604a57..78295ba0050f 100644
--- a/drivers/staging/octeon/cvmx-helper-rgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
@@ -43,6 +43,7 @@
  * Returns Number of RGMII/GMII/MII ports (0-4).
  */
 extern int __cvmx_helper_rgmii_probe(int interface);
+#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe
 
 /**
  * Put an RGMII interface in loopback mode. Internal packets sent
diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
index 19b48d60857f..9a9b6c103ede 100644
--- a/drivers/staging/octeon/cvmx-helper-sgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
@@ -45,6 +45,7 @@
  * Returns Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_sgmii_probe(int interface);
+extern int __cvmx_helper_sgmii_enumerate(int interface);
 
 /**
  * Bringup and enable a SGMII interface. After this call packet
diff --git a/drivers/staging/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
index 69bac036d10e..9f1c6b968f91 100644
--- a/drivers/staging/octeon/cvmx-helper-spi.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
@@ -42,6 +42,7 @@
  * Returns Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_spi_probe(int interface);
+extern int __cvmx_helper_spi_enumerate(int interface);
 
 /**
  * Bringup and enable a SPI interface. After this call packet I/O
diff --git a/drivers/staging/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h
index 6a6e52fc22c1..6a6e52fc22c1 100644
--- a/drivers/staging/octeon/cvmx-helper-util.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
diff --git a/drivers/staging/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
index 4b4db2f93cd4..f6fbc4f45b56 100644
--- a/drivers/staging/octeon/cvmx-helper-xaui.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
@@ -45,6 +45,7 @@
  * Returns Number of ports on the interface. Zero to disable.
  */
 extern int __cvmx_helper_xaui_probe(int interface);
+extern int __cvmx_helper_xaui_enumerate(int interface);
 
 /**
  * Bringup and enable a XAUI interface. After this call packet
diff --git a/drivers/staging/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
index 51916f3cc40c..3169cd79f2ac 100644
--- a/drivers/staging/octeon/cvmx-helper.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper.h
@@ -207,6 +207,7 @@ extern int cvmx_helper_link_set(int ipd_port,
  * Returns Zero on success, negative on failure
  */
 extern int cvmx_helper_interface_probe(int interface);
+extern int cvmx_helper_interface_enumerate(int interface);
 
 /**
  * Configure a port for internal and/or external loopback. Internal loopback
diff --git a/drivers/staging/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h
index 115a552c5c7f..115a552c5c7f 100644
--- a/drivers/staging/octeon/cvmx-ipd.h
+++ b/arch/mips/include/asm/octeon/cvmx-ipd.h
diff --git a/drivers/staging/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h
index d88ab8d8e37d..d88ab8d8e37d 100644
--- a/drivers/staging/octeon/cvmx-mdio.h
+++ b/arch/mips/include/asm/octeon/cvmx-mdio.h
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index 52b14a333ad4..b1774126736d 100644
--- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -43,6 +43,22 @@
 #define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
 #define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
 #define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
+#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
+#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
+#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
+#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
+#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
+#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
+#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
+#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
+#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
+#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
+#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
+#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
+#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
+#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
+#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
 #define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
 #define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
 #define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
@@ -60,6 +76,7 @@
 #define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
 #define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
 #define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
+#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
 #define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
 #define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
 #define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
@@ -68,14 +85,25 @@
 #define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
 #define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
 #define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
+#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
+#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
+#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
+#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
 #define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
 #define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
 #define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
 #define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
 #define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
+#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
+#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
+#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
+#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
 #define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
+#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
 #define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
 #define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
+#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
+#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
 #define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
 #define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
 #define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
@@ -183,11 +211,21 @@ union cvmx_mio_boot_bist_stat {
         struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
         struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
         struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
+        struct cvmx_mio_boot_bist_stat_cn61xx {
+                uint64_t reserved_12_63:52;
+                uint64_t stat:12;
+        } cn61xx;
         struct cvmx_mio_boot_bist_stat_cn63xx {
                 uint64_t reserved_9_63:55;
                 uint64_t stat:9;
         } cn63xx;
         struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
+        struct cvmx_mio_boot_bist_stat_cn66xx {
+                uint64_t reserved_10_63:54;
+                uint64_t stat:10;
+        } cn66xx;
+        struct cvmx_mio_boot_bist_stat_cn66xx cn68xx;
+        struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1;
 };
 
 union cvmx_mio_boot_comp {
@@ -204,12 +242,16 @@ union cvmx_mio_boot_comp {
         struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
         struct cvmx_mio_boot_comp_cn50xx cn56xx;
         struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
-        struct cvmx_mio_boot_comp_cn63xx {
+        struct cvmx_mio_boot_comp_cn61xx {
                 uint64_t reserved_12_63:52;
                 uint64_t pctl:6;
                 uint64_t nctl:6;
-        } cn63xx;
-        struct cvmx_mio_boot_comp_cn63xx cn63xxp1;
+        } cn61xx;
+        struct cvmx_mio_boot_comp_cn61xx cn63xx;
+        struct cvmx_mio_boot_comp_cn61xx cn63xxp1;
+        struct cvmx_mio_boot_comp_cn61xx cn66xx;
+        struct cvmx_mio_boot_comp_cn61xx cn68xx;
+        struct cvmx_mio_boot_comp_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_boot_dma_cfgx {
@@ -230,8 +272,12 @@ union cvmx_mio_boot_dma_cfgx {
         struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
         struct cvmx_mio_boot_dma_cfgx_s cn56xx;
         struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_cfgx_s cn61xx;
         struct cvmx_mio_boot_dma_cfgx_s cn63xx;
         struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
+        struct cvmx_mio_boot_dma_cfgx_s cn66xx;
+        struct cvmx_mio_boot_dma_cfgx_s cn68xx;
+        struct cvmx_mio_boot_dma_cfgx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_dma_intx {
@@ -245,8 +291,12 @@ union cvmx_mio_boot_dma_intx {
         struct cvmx_mio_boot_dma_intx_s cn52xxp1;
         struct cvmx_mio_boot_dma_intx_s cn56xx;
         struct cvmx_mio_boot_dma_intx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_intx_s cn61xx;
         struct cvmx_mio_boot_dma_intx_s cn63xx;
         struct cvmx_mio_boot_dma_intx_s cn63xxp1;
+        struct cvmx_mio_boot_dma_intx_s cn66xx;
+        struct cvmx_mio_boot_dma_intx_s cn68xx;
+        struct cvmx_mio_boot_dma_intx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_dma_int_enx {
@@ -260,8 +310,12 @@ union cvmx_mio_boot_dma_int_enx {
         struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
         struct cvmx_mio_boot_dma_int_enx_s cn56xx;
         struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_int_enx_s cn61xx;
         struct cvmx_mio_boot_dma_int_enx_s cn63xx;
         struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
+        struct cvmx_mio_boot_dma_int_enx_s cn66xx;
+        struct cvmx_mio_boot_dma_int_enx_s cn68xx;
+        struct cvmx_mio_boot_dma_int_enx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_dma_timx {
@@ -287,8 +341,12 @@ union cvmx_mio_boot_dma_timx {
         struct cvmx_mio_boot_dma_timx_s cn52xxp1;
         struct cvmx_mio_boot_dma_timx_s cn56xx;
         struct cvmx_mio_boot_dma_timx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_timx_s cn61xx;
         struct cvmx_mio_boot_dma_timx_s cn63xx;
         struct cvmx_mio_boot_dma_timx_s cn63xxp1;
+        struct cvmx_mio_boot_dma_timx_s cn66xx;
+        struct cvmx_mio_boot_dma_timx_s cn68xx;
+        struct cvmx_mio_boot_dma_timx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_err {
@@ -309,8 +367,12 @@ union cvmx_mio_boot_err {
         struct cvmx_mio_boot_err_s cn56xxp1;
         struct cvmx_mio_boot_err_s cn58xx;
         struct cvmx_mio_boot_err_s cn58xxp1;
+        struct cvmx_mio_boot_err_s cn61xx;
         struct cvmx_mio_boot_err_s cn63xx;
         struct cvmx_mio_boot_err_s cn63xxp1;
+        struct cvmx_mio_boot_err_s cn66xx;
+        struct cvmx_mio_boot_err_s cn68xx;
+        struct cvmx_mio_boot_err_s cn68xxp1;
 };
 
 union cvmx_mio_boot_int {
@@ -331,8 +393,12 @@ union cvmx_mio_boot_int {
         struct cvmx_mio_boot_int_s cn56xxp1;
         struct cvmx_mio_boot_int_s cn58xx;
         struct cvmx_mio_boot_int_s cn58xxp1;
+        struct cvmx_mio_boot_int_s cn61xx;
         struct cvmx_mio_boot_int_s cn63xx;
         struct cvmx_mio_boot_int_s cn63xxp1;
+        struct cvmx_mio_boot_int_s cn66xx;
+        struct cvmx_mio_boot_int_s cn68xx;
+        struct cvmx_mio_boot_int_s cn68xxp1;
 };
 
 union cvmx_mio_boot_loc_adr {
@@ -353,8 +419,12 @@ union cvmx_mio_boot_loc_adr {
         struct cvmx_mio_boot_loc_adr_s cn56xxp1;
         struct cvmx_mio_boot_loc_adr_s cn58xx;
         struct cvmx_mio_boot_loc_adr_s cn58xxp1;
+        struct cvmx_mio_boot_loc_adr_s cn61xx;
         struct cvmx_mio_boot_loc_adr_s cn63xx;
         struct cvmx_mio_boot_loc_adr_s cn63xxp1;
+        struct cvmx_mio_boot_loc_adr_s cn66xx;
+        struct cvmx_mio_boot_loc_adr_s cn68xx;
+        struct cvmx_mio_boot_loc_adr_s cn68xxp1;
 };
 
 union cvmx_mio_boot_loc_cfgx {
@@ -377,8 +447,12 @@ union cvmx_mio_boot_loc_cfgx {
         struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
         struct cvmx_mio_boot_loc_cfgx_s cn58xx;
         struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
+        struct cvmx_mio_boot_loc_cfgx_s cn61xx;
         struct cvmx_mio_boot_loc_cfgx_s cn63xx;
         struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
+        struct cvmx_mio_boot_loc_cfgx_s cn66xx;
+        struct cvmx_mio_boot_loc_cfgx_s cn68xx;
+        struct cvmx_mio_boot_loc_cfgx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_loc_dat {
@@ -397,14 +471,19 @@ union cvmx_mio_boot_loc_dat {
         struct cvmx_mio_boot_loc_dat_s cn56xxp1;
         struct cvmx_mio_boot_loc_dat_s cn58xx;
         struct cvmx_mio_boot_loc_dat_s cn58xxp1;
+        struct cvmx_mio_boot_loc_dat_s cn61xx;
         struct cvmx_mio_boot_loc_dat_s cn63xx;
         struct cvmx_mio_boot_loc_dat_s cn63xxp1;
+        struct cvmx_mio_boot_loc_dat_s cn66xx;
+        struct cvmx_mio_boot_loc_dat_s cn68xx;
+        struct cvmx_mio_boot_loc_dat_s cn68xxp1;
 };
 
 union cvmx_mio_boot_pin_defs {
         uint64_t u64;
         struct cvmx_mio_boot_pin_defs_s {
-                uint64_t reserved_16_63:48;
+                uint64_t reserved_32_63:32;
+                uint64_t user1:16;
                 uint64_t ale:1;
                 uint64_t width:1;
                 uint64_t dmack_p2:1;
@@ -412,7 +491,7 @@ union cvmx_mio_boot_pin_defs {
                 uint64_t dmack_p0:1;
                 uint64_t term:2;
                 uint64_t nand:1;
-                uint64_t reserved_0_7:8;
+                uint64_t user0:8;
         } s;
         struct cvmx_mio_boot_pin_defs_cn52xx {
                 uint64_t reserved_16_63:48;
@@ -435,8 +514,23 @@ union cvmx_mio_boot_pin_defs {
                 uint64_t term:2;
                 uint64_t reserved_0_8:9;
         } cn56xx;
+        struct cvmx_mio_boot_pin_defs_cn61xx {
+                uint64_t reserved_32_63:32;
+                uint64_t user1:16;
+                uint64_t ale:1;
+                uint64_t width:1;
+                uint64_t reserved_13_13:1;
+                uint64_t dmack_p1:1;
+                uint64_t dmack_p0:1;
+                uint64_t term:2;
+                uint64_t nand:1;
+                uint64_t user0:8;
+        } cn61xx;
         struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
         struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
+        struct cvmx_mio_boot_pin_defs_cn52xx cn66xx;
+        struct cvmx_mio_boot_pin_defs_cn52xx cn68xx;
+        struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1;
 };
 
 union cvmx_mio_boot_reg_cfgx {
@@ -498,8 +592,12 @@ union cvmx_mio_boot_reg_cfgx {
         struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
+        struct cvmx_mio_boot_reg_cfgx_s cn61xx;
         struct cvmx_mio_boot_reg_cfgx_s cn63xx;
         struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
+        struct cvmx_mio_boot_reg_cfgx_s cn66xx;
+        struct cvmx_mio_boot_reg_cfgx_s cn68xx;
+        struct cvmx_mio_boot_reg_cfgx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_reg_timx {
@@ -544,8 +642,12 @@ union cvmx_mio_boot_reg_timx {
         struct cvmx_mio_boot_reg_timx_s cn56xxp1;
         struct cvmx_mio_boot_reg_timx_s cn58xx;
         struct cvmx_mio_boot_reg_timx_s cn58xxp1;
+        struct cvmx_mio_boot_reg_timx_s cn61xx;
         struct cvmx_mio_boot_reg_timx_s cn63xx;
         struct cvmx_mio_boot_reg_timx_s cn63xxp1;
+        struct cvmx_mio_boot_reg_timx_s cn66xx;
+        struct cvmx_mio_boot_reg_timx_s cn68xx;
+        struct cvmx_mio_boot_reg_timx_s cn68xxp1;
 };
 
 union cvmx_mio_boot_thr {
@@ -574,8 +676,231 @@ union cvmx_mio_boot_thr {
         struct cvmx_mio_boot_thr_s cn56xxp1;
         struct cvmx_mio_boot_thr_cn30xx cn58xx;
         struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
+        struct cvmx_mio_boot_thr_s cn61xx;
         struct cvmx_mio_boot_thr_s cn63xx;
         struct cvmx_mio_boot_thr_s cn63xxp1;
+        struct cvmx_mio_boot_thr_s cn66xx;
+        struct cvmx_mio_boot_thr_s cn68xx;
+        struct cvmx_mio_boot_thr_s cn68xxp1;
+};
+
+union cvmx_mio_emm_buf_dat {
+        uint64_t u64;
+        struct cvmx_mio_emm_buf_dat_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_mio_emm_buf_dat_s cn61xx;
+};
+
+union cvmx_mio_emm_buf_idx {
+        uint64_t u64;
+        struct cvmx_mio_emm_buf_idx_s {
+                uint64_t reserved_17_63:47;
+                uint64_t inc:1;
+                uint64_t reserved_7_15:9;
+                uint64_t buf_num:1;
+                uint64_t offset:6;
+        } s;
+        struct cvmx_mio_emm_buf_idx_s cn61xx;
+};
+
+union cvmx_mio_emm_cfg {
+        uint64_t u64;
+        struct cvmx_mio_emm_cfg_s {
+                uint64_t reserved_17_63:47;
+                uint64_t boot_fail:1;
+                uint64_t reserved_4_15:12;
+                uint64_t bus_ena:4;
+        } s;
+        struct cvmx_mio_emm_cfg_s cn61xx;
+};
+
+union cvmx_mio_emm_cmd {
+        uint64_t u64;
+        struct cvmx_mio_emm_cmd_s {
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t cmd_val:1;
+                uint64_t reserved_56_58:3;
+                uint64_t dbuf:1;
+                uint64_t offset:6;
+                uint64_t reserved_43_48:6;
+                uint64_t ctype_xor:2;
+                uint64_t rtype_xor:3;
+                uint64_t cmd_idx:6;
+                uint64_t arg:32;
+        } s;
+        struct cvmx_mio_emm_cmd_s cn61xx;
+};
+
+union cvmx_mio_emm_dma {
+        uint64_t u64;
+        struct cvmx_mio_emm_dma_s {
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t dma_val:1;
+                uint64_t sector:1;
+                uint64_t dat_null:1;
+                uint64_t thres:6;
+                uint64_t rel_wr:1;
+                uint64_t rw:1;
+                uint64_t multi:1;
+                uint64_t block_cnt:16;
+                uint64_t card_addr:32;
+        } s;
+        struct cvmx_mio_emm_dma_s cn61xx;
+};
+
+union cvmx_mio_emm_int {
+        uint64_t u64;
+        struct cvmx_mio_emm_int_s {
+                uint64_t reserved_7_63:57;
+                uint64_t switch_err:1;
+                uint64_t switch_done:1;
+                uint64_t dma_err:1;
+                uint64_t cmd_err:1;
+                uint64_t dma_done:1;
+                uint64_t cmd_done:1;
+                uint64_t buf_done:1;
+        } s;
+        struct cvmx_mio_emm_int_s cn61xx;
+};
+
+union cvmx_mio_emm_int_en {
+        uint64_t u64;
+        struct cvmx_mio_emm_int_en_s {
+                uint64_t reserved_7_63:57;
+                uint64_t switch_err:1;
+                uint64_t switch_done:1;
+                uint64_t dma_err:1;
+                uint64_t cmd_err:1;
+                uint64_t dma_done:1;
+                uint64_t cmd_done:1;
+                uint64_t buf_done:1;
+        } s;
+        struct cvmx_mio_emm_int_en_s cn61xx;
+};
+
+union cvmx_mio_emm_modex {
+        uint64_t u64;
+        struct cvmx_mio_emm_modex_s {
+                uint64_t reserved_49_63:15;
+                uint64_t hs_timing:1;
+                uint64_t reserved_43_47:5;
+                uint64_t bus_width:3;
+                uint64_t reserved_36_39:4;
+                uint64_t power_class:4;
+                uint64_t clk_hi:16;
+                uint64_t clk_lo:16;
+        } s;
+        struct cvmx_mio_emm_modex_s cn61xx;
+};
+
+union cvmx_mio_emm_rca {
+        uint64_t u64;
+        struct cvmx_mio_emm_rca_s {
+                uint64_t reserved_16_63:48;
+                uint64_t card_rca:16;
+        } s;
+        struct cvmx_mio_emm_rca_s cn61xx;
+};
+
+union cvmx_mio_emm_rsp_hi {
+        uint64_t u64;
+        struct cvmx_mio_emm_rsp_hi_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_mio_emm_rsp_hi_s cn61xx;
+};
+
+union cvmx_mio_emm_rsp_lo {
+        uint64_t u64;
+        struct cvmx_mio_emm_rsp_lo_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_mio_emm_rsp_lo_s cn61xx;
+};
+
+union cvmx_mio_emm_rsp_sts {
+        uint64_t u64;
+        struct cvmx_mio_emm_rsp_sts_s {
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t cmd_val:1;
+                uint64_t switch_val:1;
+                uint64_t dma_val:1;
+                uint64_t dma_pend:1;
+                uint64_t reserved_29_55:27;
+                uint64_t dbuf_err:1;
+                uint64_t reserved_24_27:4;
+                uint64_t dbuf:1;
+                uint64_t blk_timeout:1;
+                uint64_t blk_crc_err:1;
+                uint64_t rsp_busybit:1;
+                uint64_t stp_timeout:1;
+                uint64_t stp_crc_err:1;
+                uint64_t stp_bad_sts:1;
+                uint64_t stp_val:1;
+                uint64_t rsp_timeout:1;
+                uint64_t rsp_crc_err:1;
+                uint64_t rsp_bad_sts:1;
+                uint64_t rsp_val:1;
+                uint64_t rsp_type:3;
+                uint64_t cmd_type:2;
+                uint64_t cmd_idx:6;
+                uint64_t cmd_done:1;
+        } s;
+        struct cvmx_mio_emm_rsp_sts_s cn61xx;
+};
+
+union cvmx_mio_emm_sample {
+        uint64_t u64;
+        struct cvmx_mio_emm_sample_s {
+                uint64_t reserved_26_63:38;
+                uint64_t cmd_cnt:10;
+                uint64_t reserved_10_15:6;
+                uint64_t dat_cnt:10;
+        } s;
+        struct cvmx_mio_emm_sample_s cn61xx;
+};
+
+union cvmx_mio_emm_sts_mask {
+        uint64_t u64;
+        struct cvmx_mio_emm_sts_mask_s {
+                uint64_t reserved_32_63:32;
+                uint64_t sts_msk:32;
+        } s;
+        struct cvmx_mio_emm_sts_mask_s cn61xx;
+};
+
+union cvmx_mio_emm_switch {
+        uint64_t u64;
+        struct cvmx_mio_emm_switch_s {
+                uint64_t reserved_62_63:2;
+                uint64_t bus_id:2;
+                uint64_t switch_exe:1;
+                uint64_t switch_err0:1;
+                uint64_t switch_err1:1;
+                uint64_t switch_err2:1;
+                uint64_t reserved_49_55:7;
+                uint64_t hs_timing:1;
+                uint64_t reserved_43_47:5;
+                uint64_t bus_width:3;
+                uint64_t reserved_36_39:4;
+                uint64_t power_class:4;
+                uint64_t clk_hi:16;
+                uint64_t clk_lo:16;
+        } s;
+        struct cvmx_mio_emm_switch_s cn61xx;
+};
+
+union cvmx_mio_emm_wdog {
+        uint64_t u64;
+        struct cvmx_mio_emm_wdog_s {
+                uint64_t reserved_26_63:38;
+                uint64_t clk_cnt:26;
+        } s;
+        struct cvmx_mio_emm_wdog_s cn61xx;
 };
 
 union cvmx_mio_fus_bnk_datx {
@@ -590,8 +915,12 @@ union cvmx_mio_fus_bnk_datx {
         struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
         struct cvmx_mio_fus_bnk_datx_s cn58xx;
         struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
+        struct cvmx_mio_fus_bnk_datx_s cn61xx;
         struct cvmx_mio_fus_bnk_datx_s cn63xx;
         struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
+        struct cvmx_mio_fus_bnk_datx_s cn66xx;
+        struct cvmx_mio_fus_bnk_datx_s cn68xx;
+        struct cvmx_mio_fus_bnk_datx_s cn68xxp1;
 };
 
 union cvmx_mio_fus_dat0 {
@@ -611,8 +940,12 @@ union cvmx_mio_fus_dat0 {
         struct cvmx_mio_fus_dat0_s cn56xxp1;
         struct cvmx_mio_fus_dat0_s cn58xx;
         struct cvmx_mio_fus_dat0_s cn58xxp1;
+        struct cvmx_mio_fus_dat0_s cn61xx;
         struct cvmx_mio_fus_dat0_s cn63xx;
         struct cvmx_mio_fus_dat0_s cn63xxp1;
+        struct cvmx_mio_fus_dat0_s cn66xx;
+        struct cvmx_mio_fus_dat0_s cn68xx;
+        struct cvmx_mio_fus_dat0_s cn68xxp1;
 };
 
 union cvmx_mio_fus_dat1 {
@@ -632,14 +965,21 @@ union cvmx_mio_fus_dat1 {
         struct cvmx_mio_fus_dat1_s cn56xxp1;
         struct cvmx_mio_fus_dat1_s cn58xx;
         struct cvmx_mio_fus_dat1_s cn58xxp1;
+        struct cvmx_mio_fus_dat1_s cn61xx;
         struct cvmx_mio_fus_dat1_s cn63xx;
         struct cvmx_mio_fus_dat1_s cn63xxp1;
+        struct cvmx_mio_fus_dat1_s cn66xx;
+        struct cvmx_mio_fus_dat1_s cn68xx;
+        struct cvmx_mio_fus_dat1_s cn68xxp1;
 };
 
 union cvmx_mio_fus_dat2 {
         uint64_t u64;
         struct cvmx_mio_fus_dat2_s {
-                uint64_t reserved_35_63:29;
+                uint64_t reserved_48_63:16;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
                 uint64_t dorm_crypto:1;
                 uint64_t fus318:1;
                 uint64_t raid_en:1;
@@ -747,6 +1087,23 @@ union cvmx_mio_fus_dat2 {
                 uint64_t pp_dis:16;
         } cn58xx;
         struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
+        struct cvmx_mio_fus_dat2_cn61xx {
+                uint64_t reserved_48_63:16;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_4_15:12;
+                uint64_t pp_dis:4;
+        } cn61xx;
         struct cvmx_mio_fus_dat2_cn63xx {
                 uint64_t reserved_35_63:29;
                 uint64_t dorm_crypto:1;
@@ -762,6 +1119,38 @@ union cvmx_mio_fus_dat2 {
                 uint64_t pp_dis:6;
         } cn63xx;
         struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
+        struct cvmx_mio_fus_dat2_cn66xx {
+                uint64_t reserved_48_63:16;
+                uint64_t fus118:1;
+                uint64_t rom_info:10;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_10_15:6;
+                uint64_t pp_dis:10;
+        } cn66xx;
+        struct cvmx_mio_fus_dat2_cn68xx {
+                uint64_t reserved_37_63:27;
+                uint64_t power_limit:2;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_0_15:16;
+        } cn68xx;
+        struct cvmx_mio_fus_dat2_cn68xx cn68xxp1;
 };
 
 union cvmx_mio_fus_dat3 {
@@ -834,7 +1223,7 @@ union cvmx_mio_fus_dat3 {
         struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
         struct cvmx_mio_fus_dat3_cn38xx cn58xx;
         struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
-        struct cvmx_mio_fus_dat3_cn63xx {
+        struct cvmx_mio_fus_dat3_cn61xx {
                 uint64_t reserved_58_63:6;
                 uint64_t pll_ctl:10;
                 uint64_t dfa_info_dte:3;
@@ -853,8 +1242,12 @@ union cvmx_mio_fus_dat3 {
                 uint64_t nozip:1;
                 uint64_t nodfa_dte:1;
                 uint64_t reserved_0_23:24;
-        } cn63xx;
-        struct cvmx_mio_fus_dat3_cn63xx cn63xxp1;
+        } cn61xx;
+        struct cvmx_mio_fus_dat3_cn61xx cn63xx;
+        struct cvmx_mio_fus_dat3_cn61xx cn63xxp1;
+        struct cvmx_mio_fus_dat3_cn61xx cn66xx;
+        struct cvmx_mio_fus_dat3_cn61xx cn68xx;
+        struct cvmx_mio_fus_dat3_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_fus_ema {
@@ -875,8 +1268,12 @@ union cvmx_mio_fus_ema {
                 uint64_t ema:2;
         } cn58xx;
         struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
+        struct cvmx_mio_fus_ema_s cn61xx;
         struct cvmx_mio_fus_ema_s cn63xx;
         struct cvmx_mio_fus_ema_s cn63xxp1;
+        struct cvmx_mio_fus_ema_s cn66xx;
+        struct cvmx_mio_fus_ema_s cn68xx;
+        struct cvmx_mio_fus_ema_s cn68xxp1;
 };
 
 union cvmx_mio_fus_pdf {
@@ -890,14 +1287,21 @@ union cvmx_mio_fus_pdf {
         struct cvmx_mio_fus_pdf_s cn56xx;
         struct cvmx_mio_fus_pdf_s cn56xxp1;
         struct cvmx_mio_fus_pdf_s cn58xx;
+        struct cvmx_mio_fus_pdf_s cn61xx;
         struct cvmx_mio_fus_pdf_s cn63xx;
         struct cvmx_mio_fus_pdf_s cn63xxp1;
+        struct cvmx_mio_fus_pdf_s cn66xx;
+        struct cvmx_mio_fus_pdf_s cn68xx;
+        struct cvmx_mio_fus_pdf_s cn68xxp1;
 };
 
 union cvmx_mio_fus_pll {
         uint64_t u64;
         struct cvmx_mio_fus_pll_s {
-                uint64_t reserved_8_63:56;
+                uint64_t reserved_48_63:16;
+                uint64_t rclk_align_r:8;
+                uint64_t rclk_align_l:8;
+                uint64_t reserved_8_31:24;
                 uint64_t c_cout_rst:1;
                 uint64_t c_cout_sel:2;
                 uint64_t pnr_cout_rst:1;
@@ -916,8 +1320,20 @@ union cvmx_mio_fus_pll {
         struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
         struct cvmx_mio_fus_pll_cn50xx cn58xx;
         struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
-        struct cvmx_mio_fus_pll_s cn63xx;
-        struct cvmx_mio_fus_pll_s cn63xxp1;
+        struct cvmx_mio_fus_pll_cn61xx {
+                uint64_t reserved_8_63:56;
+                uint64_t c_cout_rst:1;
+                uint64_t c_cout_sel:2;
+                uint64_t pnr_cout_rst:1;
+                uint64_t pnr_cout_sel:2;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+        } cn61xx;
+        struct cvmx_mio_fus_pll_cn61xx cn63xx;
+        struct cvmx_mio_fus_pll_cn61xx cn63xxp1;
+        struct cvmx_mio_fus_pll_cn61xx cn66xx;
+        struct cvmx_mio_fus_pll_s cn68xx;
+        struct cvmx_mio_fus_pll_s cn68xxp1;
 };
 
 union cvmx_mio_fus_prog {
@@ -941,8 +1357,12 @@ union cvmx_mio_fus_prog {
         struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
         struct cvmx_mio_fus_prog_cn30xx cn58xx;
         struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
+        struct cvmx_mio_fus_prog_s cn61xx;
         struct cvmx_mio_fus_prog_s cn63xx;
         struct cvmx_mio_fus_prog_s cn63xxp1;
+        struct cvmx_mio_fus_prog_s cn66xx;
+        struct cvmx_mio_fus_prog_s cn68xx;
+        struct cvmx_mio_fus_prog_s cn68xxp1;
 };
 
 union cvmx_mio_fus_prog_times {
@@ -969,7 +1389,7 @@ union cvmx_mio_fus_prog_times {
         struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
         struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
         struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
-        struct cvmx_mio_fus_prog_times_cn63xx {
+        struct cvmx_mio_fus_prog_times_cn61xx {
                 uint64_t reserved_35_63:29;
                 uint64_t vgate_pin:1;
                 uint64_t fsrc_pin:1;
@@ -978,8 +1398,12 @@ union cvmx_mio_fus_prog_times {
                 uint64_t sclk_lo:4;
                 uint64_t sclk_hi:15;
                 uint64_t setup:6;
-        } cn63xx;
-        struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
+        } cn61xx;
+        struct cvmx_mio_fus_prog_times_cn61xx cn63xx;
+        struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1;
+        struct cvmx_mio_fus_prog_times_cn61xx cn66xx;
+        struct cvmx_mio_fus_prog_times_cn61xx cn68xx;
+        struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_fus_rcmd {
@@ -1013,8 +1437,12 @@ union cvmx_mio_fus_rcmd {
         struct cvmx_mio_fus_rcmd_s cn56xxp1;
         struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
         struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
+        struct cvmx_mio_fus_rcmd_s cn61xx;
         struct cvmx_mio_fus_rcmd_s cn63xx;
         struct cvmx_mio_fus_rcmd_s cn63xxp1;
+        struct cvmx_mio_fus_rcmd_s cn66xx;
+        struct cvmx_mio_fus_rcmd_s cn68xx;
+        struct cvmx_mio_fus_rcmd_s cn68xxp1;
 };
 
 union cvmx_mio_fus_read_times {
@@ -1027,8 +1455,12 @@ union cvmx_mio_fus_read_times {
                 uint64_t sdh:4;
                 uint64_t setup:10;
         } s;
+        struct cvmx_mio_fus_read_times_s cn61xx;
         struct cvmx_mio_fus_read_times_s cn63xx;
         struct cvmx_mio_fus_read_times_s cn63xxp1;
+        struct cvmx_mio_fus_read_times_s cn66xx;
+        struct cvmx_mio_fus_read_times_s cn68xx;
+        struct cvmx_mio_fus_read_times_s cn68xxp1;
 };
 
 union cvmx_mio_fus_repair_res0 {
@@ -1040,8 +1472,12 @@ union cvmx_mio_fus_repair_res0 {
                 uint64_t repair1:18;
                 uint64_t repair0:18;
         } s;
+        struct cvmx_mio_fus_repair_res0_s cn61xx;
         struct cvmx_mio_fus_repair_res0_s cn63xx;
         struct cvmx_mio_fus_repair_res0_s cn63xxp1;
+        struct cvmx_mio_fus_repair_res0_s cn66xx;
+        struct cvmx_mio_fus_repair_res0_s cn68xx;
+        struct cvmx_mio_fus_repair_res0_s cn68xxp1;
 };
 
 union cvmx_mio_fus_repair_res1 {
@@ -1052,8 +1488,12 @@ union cvmx_mio_fus_repair_res1 {
                 uint64_t repair4:18;
                 uint64_t repair3:18;
         } s;
+        struct cvmx_mio_fus_repair_res1_s cn61xx;
         struct cvmx_mio_fus_repair_res1_s cn63xx;
         struct cvmx_mio_fus_repair_res1_s cn63xxp1;
+        struct cvmx_mio_fus_repair_res1_s cn66xx;
+        struct cvmx_mio_fus_repair_res1_s cn68xx;
+        struct cvmx_mio_fus_repair_res1_s cn68xxp1;
 };
 
 union cvmx_mio_fus_repair_res2 {
@@ -1062,8 +1502,12 @@ union cvmx_mio_fus_repair_res2 {
                 uint64_t reserved_18_63:46;
                 uint64_t repair6:18;
         } s;
+        struct cvmx_mio_fus_repair_res2_s cn61xx;
         struct cvmx_mio_fus_repair_res2_s cn63xx;
         struct cvmx_mio_fus_repair_res2_s cn63xxp1;
+        struct cvmx_mio_fus_repair_res2_s cn66xx;
+        struct cvmx_mio_fus_repair_res2_s cn68xx;
+        struct cvmx_mio_fus_repair_res2_s cn68xxp1;
 };
 
 union cvmx_mio_fus_spr_repair_res {
@@ -1084,8 +1528,12 @@ union cvmx_mio_fus_spr_repair_res {
         struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
         struct cvmx_mio_fus_spr_repair_res_s cn58xx;
         struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
+        struct cvmx_mio_fus_spr_repair_res_s cn61xx;
         struct cvmx_mio_fus_spr_repair_res_s cn63xx;
         struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
+        struct cvmx_mio_fus_spr_repair_res_s cn66xx;
+        struct cvmx_mio_fus_spr_repair_res_s cn68xx;
+        struct cvmx_mio_fus_spr_repair_res_s cn68xxp1;
 };
 
 union cvmx_mio_fus_spr_repair_sum {
@@ -1104,8 +1552,22 @@ union cvmx_mio_fus_spr_repair_sum {
         struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
         struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
+        struct cvmx_mio_fus_spr_repair_sum_s cn61xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
+        struct cvmx_mio_fus_spr_repair_sum_s cn66xx;
+        struct cvmx_mio_fus_spr_repair_sum_s cn68xx;
+        struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1;
+};
+
+union cvmx_mio_fus_tgg {
+        uint64_t u64;
+        struct cvmx_mio_fus_tgg_s {
+                uint64_t val:1;
+                uint64_t dat:63;
+        } s;
+        struct cvmx_mio_fus_tgg_s cn61xx;
+        struct cvmx_mio_fus_tgg_s cn66xx;
 };
 
 union cvmx_mio_fus_unlock {
@@ -1141,11 +1603,15 @@ union cvmx_mio_fus_wadr {
         struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
         struct cvmx_mio_fus_wadr_cn50xx cn58xx;
         struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
-        struct cvmx_mio_fus_wadr_cn63xx {
+        struct cvmx_mio_fus_wadr_cn61xx {
                 uint64_t reserved_4_63:60;
                 uint64_t addr:4;
-        } cn63xx;
-        struct cvmx_mio_fus_wadr_cn63xx cn63xxp1;
+        } cn61xx;
+        struct cvmx_mio_fus_wadr_cn61xx cn63xx;
+        struct cvmx_mio_fus_wadr_cn61xx cn63xxp1;
+        struct cvmx_mio_fus_wadr_cn61xx cn66xx;
+        struct cvmx_mio_fus_wadr_cn61xx cn68xx;
+        struct cvmx_mio_fus_wadr_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_gpio_comp {
@@ -1155,8 +1621,12 @@ union cvmx_mio_gpio_comp {
                 uint64_t pctl:6;
                 uint64_t nctl:6;
         } s;
+        struct cvmx_mio_gpio_comp_s cn61xx;
         struct cvmx_mio_gpio_comp_s cn63xx;
         struct cvmx_mio_gpio_comp_s cn63xxp1;
+        struct cvmx_mio_gpio_comp_s cn66xx;
+        struct cvmx_mio_gpio_comp_s cn68xx;
+        struct cvmx_mio_gpio_comp_s cn68xxp1;
 };
 
 union cvmx_mio_ndf_dma_cfg {
@@ -1174,8 +1644,12 @@ union cvmx_mio_ndf_dma_cfg {
                 uint64_t adr:36;
         } s;
         struct cvmx_mio_ndf_dma_cfg_s cn52xx;
+        struct cvmx_mio_ndf_dma_cfg_s cn61xx;
         struct cvmx_mio_ndf_dma_cfg_s cn63xx;
         struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
+        struct cvmx_mio_ndf_dma_cfg_s cn66xx;
+        struct cvmx_mio_ndf_dma_cfg_s cn68xx;
+        struct cvmx_mio_ndf_dma_cfg_s cn68xxp1;
 };
 
 union cvmx_mio_ndf_dma_int {
@@ -1185,8 +1659,12 @@ union cvmx_mio_ndf_dma_int {
                 uint64_t done:1;
         } s;
         struct cvmx_mio_ndf_dma_int_s cn52xx;
+        struct cvmx_mio_ndf_dma_int_s cn61xx;
         struct cvmx_mio_ndf_dma_int_s cn63xx;
         struct cvmx_mio_ndf_dma_int_s cn63xxp1;
+        struct cvmx_mio_ndf_dma_int_s cn66xx;
+        struct cvmx_mio_ndf_dma_int_s cn68xx;
+        struct cvmx_mio_ndf_dma_int_s cn68xxp1;
 };
 
 union cvmx_mio_ndf_dma_int_en {
@@ -1196,8 +1674,12 @@ union cvmx_mio_ndf_dma_int_en {
                 uint64_t done:1;
         } s;
         struct cvmx_mio_ndf_dma_int_en_s cn52xx;
+        struct cvmx_mio_ndf_dma_int_en_s cn61xx;
         struct cvmx_mio_ndf_dma_int_en_s cn63xx;
         struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
+        struct cvmx_mio_ndf_dma_int_en_s cn66xx;
+        struct cvmx_mio_ndf_dma_int_en_s cn68xx;
+        struct cvmx_mio_ndf_dma_int_en_s cn68xxp1;
 };
 
 union cvmx_mio_pll_ctl {
@@ -1220,10 +1702,63 @@ union cvmx_mio_pll_setting {
         struct cvmx_mio_pll_setting_s cn31xx;
 };
 
+union cvmx_mio_ptp_ckout_hi_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_hi_incr_s {
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx;
+        struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx;
+        struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx;
+};
+
+union cvmx_mio_ptp_ckout_lo_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_lo_incr_s {
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx;
+        struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx;
+        struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx;
+};
+
+union cvmx_mio_ptp_ckout_thresh_hi {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_thresh_hi_s {
+                uint64_t nanosec:64;
+        } s;
+        struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx;
+        struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx;
+        struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx;
+};
+
+union cvmx_mio_ptp_ckout_thresh_lo {
+        uint64_t u64;
+        struct cvmx_mio_ptp_ckout_thresh_lo_s {
+                uint64_t reserved_32_63:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx;
+        struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx;
+        struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx;
+};
+
 union cvmx_mio_ptp_clock_cfg {
         uint64_t u64;
         struct cvmx_mio_ptp_clock_cfg_s {
-                uint64_t reserved_24_63:40;
+                uint64_t reserved_42_63:22;
+                uint64_t pps:1;
+                uint64_t ckout:1;
+                uint64_t ext_clk_edge:2;
+                uint64_t ckout_out4:1;
+                uint64_t pps_out:5;
+                uint64_t pps_inv:1;
+                uint64_t pps_en:1;
+                uint64_t ckout_out:4;
+                uint64_t ckout_inv:1;
+                uint64_t ckout_en:1;
                 uint64_t evcnt_in:6;
                 uint64_t evcnt_edge:1;
                 uint64_t evcnt_en:1;
@@ -1234,8 +1769,42 @@ union cvmx_mio_ptp_clock_cfg {
                 uint64_t ext_clk_en:1;
                 uint64_t ptp_en:1;
         } s;
-        struct cvmx_mio_ptp_clock_cfg_s cn63xx;
-        struct cvmx_mio_ptp_clock_cfg_s cn63xxp1;
+        struct cvmx_mio_ptp_clock_cfg_s cn61xx;
+        struct cvmx_mio_ptp_clock_cfg_cn63xx {
+                uint64_t reserved_24_63:40;
+                uint64_t evcnt_in:6;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_en:1;
+                uint64_t tstmp_in:6;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t ext_clk_en:1;
+                uint64_t ptp_en:1;
+        } cn63xx;
+        struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;
+        struct cvmx_mio_ptp_clock_cfg_cn66xx {
+                uint64_t reserved_40_63:24;
+                uint64_t ext_clk_edge:2;
+                uint64_t ckout_out4:1;
+                uint64_t pps_out:5;
+                uint64_t pps_inv:1;
+                uint64_t pps_en:1;
+                uint64_t ckout_out:4;
+                uint64_t ckout_inv:1;
+                uint64_t ckout_en:1;
+                uint64_t evcnt_in:6;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_en:1;
+                uint64_t tstmp_in:6;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t ext_clk_en:1;
+                uint64_t ptp_en:1;
+        } cn66xx;
+        struct cvmx_mio_ptp_clock_cfg_s cn68xx;
+        struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;
 };
 
 union cvmx_mio_ptp_clock_comp {
@@ -1244,8 +1813,12 @@ union cvmx_mio_ptp_clock_comp {
                 uint64_t nanosec:32;
                 uint64_t frnanosec:32;
         } s;
+        struct cvmx_mio_ptp_clock_comp_s cn61xx;
         struct cvmx_mio_ptp_clock_comp_s cn63xx;
         struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
+        struct cvmx_mio_ptp_clock_comp_s cn66xx;
+        struct cvmx_mio_ptp_clock_comp_s cn68xx;
+        struct cvmx_mio_ptp_clock_comp_s cn68xxp1;
 };
 
 union cvmx_mio_ptp_clock_hi {
@@ -1253,8 +1826,12 @@ union cvmx_mio_ptp_clock_hi {
         struct cvmx_mio_ptp_clock_hi_s {
                 uint64_t nanosec:64;
         } s;
+        struct cvmx_mio_ptp_clock_hi_s cn61xx;
         struct cvmx_mio_ptp_clock_hi_s cn63xx;
         struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
+        struct cvmx_mio_ptp_clock_hi_s cn66xx;
+        struct cvmx_mio_ptp_clock_hi_s cn68xx;
+        struct cvmx_mio_ptp_clock_hi_s cn68xxp1;
 };
 
 union cvmx_mio_ptp_clock_lo {
@@ -1263,8 +1840,12 @@ union cvmx_mio_ptp_clock_lo {
                 uint64_t reserved_32_63:32;
                 uint64_t frnanosec:32;
         } s;
+        struct cvmx_mio_ptp_clock_lo_s cn61xx;
         struct cvmx_mio_ptp_clock_lo_s cn63xx;
         struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
+        struct cvmx_mio_ptp_clock_lo_s cn66xx;
+        struct cvmx_mio_ptp_clock_lo_s cn68xx;
+        struct cvmx_mio_ptp_clock_lo_s cn68xxp1;
 };
 
 union cvmx_mio_ptp_evt_cnt {
@@ -1272,8 +1853,55 @@ union cvmx_mio_ptp_evt_cnt {
         struct cvmx_mio_ptp_evt_cnt_s {
                 uint64_t cntr:64;
         } s;
+        struct cvmx_mio_ptp_evt_cnt_s cn61xx;
         struct cvmx_mio_ptp_evt_cnt_s cn63xx;
         struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
+        struct cvmx_mio_ptp_evt_cnt_s cn66xx;
+        struct cvmx_mio_ptp_evt_cnt_s cn68xx;
+        struct cvmx_mio_ptp_evt_cnt_s cn68xxp1;
+};
+
+union cvmx_mio_ptp_pps_hi_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_hi_incr_s {
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_pps_hi_incr_s cn61xx;
+        struct cvmx_mio_ptp_pps_hi_incr_s cn66xx;
+        struct cvmx_mio_ptp_pps_hi_incr_s cn68xx;
+};
+
+union cvmx_mio_ptp_pps_lo_incr {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_lo_incr_s {
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_pps_lo_incr_s cn61xx;
+        struct cvmx_mio_ptp_pps_lo_incr_s cn66xx;
+        struct cvmx_mio_ptp_pps_lo_incr_s cn68xx;
+};
+
+union cvmx_mio_ptp_pps_thresh_hi {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_thresh_hi_s {
+                uint64_t nanosec:64;
+        } s;
+        struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx;
+        struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx;
+        struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx;
+};
+
+union cvmx_mio_ptp_pps_thresh_lo {
+        uint64_t u64;
+        struct cvmx_mio_ptp_pps_thresh_lo_s {
+                uint64_t reserved_32_63:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx;
+        struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx;
+        struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx;
 };
 
 union cvmx_mio_ptp_timestamp {
@@ -1281,14 +1909,52 @@ union cvmx_mio_ptp_timestamp {
         struct cvmx_mio_ptp_timestamp_s {
                 uint64_t nanosec:64;
         } s;
+        struct cvmx_mio_ptp_timestamp_s cn61xx;
         struct cvmx_mio_ptp_timestamp_s cn63xx;
         struct cvmx_mio_ptp_timestamp_s cn63xxp1;
+        struct cvmx_mio_ptp_timestamp_s cn66xx;
+        struct cvmx_mio_ptp_timestamp_s cn68xx;
+        struct cvmx_mio_ptp_timestamp_s cn68xxp1;
+};
+
+union cvmx_mio_qlmx_cfg {
+        uint64_t u64;
+        struct cvmx_mio_qlmx_cfg_s {
+                uint64_t reserved_12_63:52;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_4_7:4;
+                uint64_t qlm_cfg:4;
+        } s;
+        struct cvmx_mio_qlmx_cfg_cn61xx {
+                uint64_t reserved_12_63:52;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_2_7:6;
+                uint64_t qlm_cfg:2;
+        } cn61xx;
+        struct cvmx_mio_qlmx_cfg_s cn66xx;
+        struct cvmx_mio_qlmx_cfg_cn68xx {
+                uint64_t reserved_12_63:52;
+                uint64_t qlm_spd:4;
+                uint64_t reserved_3_7:5;
+                uint64_t qlm_cfg:3;
+        } cn68xx;
+        struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1;
 };
 
 union cvmx_mio_rst_boot {
         uint64_t u64;
         struct cvmx_mio_rst_boot_s {
-                uint64_t reserved_36_63:28;
+                uint64_t chipkill:1;
+                uint64_t jtcsrdis:1;
+                uint64_t ejtagdis:1;
+                uint64_t romen:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t jt_tstmode:1;
+                uint64_t reserved_50_57:8;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_44_47:4;
+                uint64_t qlm4_spd:4;
+                uint64_t qlm3_spd:4;
                 uint64_t c_mul:6;
                 uint64_t pnr_mul:6;
                 uint64_t qlm2_spd:4;
@@ -1298,32 +1964,168 @@ union cvmx_mio_rst_boot {
                 uint64_t rboot:1;
                 uint64_t rboot_pin:1;
         } s;
-        struct cvmx_mio_rst_boot_s cn63xx;
-        struct cvmx_mio_rst_boot_s cn63xxp1;
+        struct cvmx_mio_rst_boot_cn61xx {
+                uint64_t chipkill:1;
+                uint64_t jtcsrdis:1;
+                uint64_t ejtagdis:1;
+                uint64_t romen:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t jt_tstmode:1;
+                uint64_t reserved_50_57:8;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_36_47:12;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } cn61xx;
+        struct cvmx_mio_rst_boot_cn63xx {
+                uint64_t reserved_36_63:28;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } cn63xx;
+        struct cvmx_mio_rst_boot_cn63xx cn63xxp1;
+        struct cvmx_mio_rst_boot_cn66xx {
+                uint64_t chipkill:1;
+                uint64_t jtcsrdis:1;
+                uint64_t ejtagdis:1;
+                uint64_t romen:1;
+                uint64_t ckill_ppdis:1;
+                uint64_t reserved_50_58:9;
+                uint64_t lboot_ext:2;
+                uint64_t reserved_36_47:12;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } cn66xx;
+        struct cvmx_mio_rst_boot_cn68xx {
+                uint64_t reserved_59_63:5;
+                uint64_t jt_tstmode:1;
+                uint64_t reserved_44_57:14;
+                uint64_t qlm4_spd:4;
+                uint64_t qlm3_spd:4;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } cn68xx;
+        struct cvmx_mio_rst_boot_cn68xxp1 {
+                uint64_t reserved_44_63:20;
+                uint64_t qlm4_spd:4;
+                uint64_t qlm3_spd:4;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } cn68xxp1;
 };
 
 union cvmx_mio_rst_cfg {
         uint64_t u64;
         struct cvmx_mio_rst_cfg_s {
+                uint64_t reserved_3_63:61;
+                uint64_t cntl_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+        } s;
+        struct cvmx_mio_rst_cfg_cn61xx {
                 uint64_t bist_delay:58;
                 uint64_t reserved_3_5:3;
                 uint64_t cntl_clr_bist:1;
                 uint64_t warm_clr_bist:1;
                 uint64_t soft_clr_bist:1;
-        } s;
-        struct cvmx_mio_rst_cfg_s cn63xx;
+        } cn61xx;
+        struct cvmx_mio_rst_cfg_cn61xx cn63xx;
         struct cvmx_mio_rst_cfg_cn63xxp1 {
                 uint64_t bist_delay:58;
                 uint64_t reserved_2_5:4;
                 uint64_t warm_clr_bist:1;
                 uint64_t soft_clr_bist:1;
         } cn63xxp1;
+        struct cvmx_mio_rst_cfg_cn61xx cn66xx;
+        struct cvmx_mio_rst_cfg_cn68xx {
+                uint64_t bist_delay:56;
+                uint64_t reserved_3_7:5;
+                uint64_t cntl_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+        } cn68xx;
+        struct cvmx_mio_rst_cfg_cn68xx cn68xxp1;
+};
+
+union cvmx_mio_rst_ckill {
+        uint64_t u64;
+        struct cvmx_mio_rst_ckill_s {
+                uint64_t reserved_47_63:17;
+                uint64_t timer:47;
+        } s;
+        struct cvmx_mio_rst_ckill_s cn61xx;
+        struct cvmx_mio_rst_ckill_s cn66xx;
+};
+
+union cvmx_mio_rst_cntlx {
+        uint64_t u64;
+        struct cvmx_mio_rst_cntlx_s {
+                uint64_t reserved_13_63:51;
+                uint64_t in_rev_ln:1;
+                uint64_t rev_lanes:1;
+                uint64_t gen1_only:1;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+        } s;
+        struct cvmx_mio_rst_cntlx_s cn61xx;
+        struct cvmx_mio_rst_cntlx_cn66xx {
+                uint64_t reserved_10_63:54;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+        } cn66xx;
+        struct cvmx_mio_rst_cntlx_cn66xx cn68xx;
 };
 
 union cvmx_mio_rst_ctlx {
         uint64_t u64;
         struct cvmx_mio_rst_ctlx_s {
-                uint64_t reserved_10_63:54;
+                uint64_t reserved_13_63:51;
+                uint64_t in_rev_ln:1;
+                uint64_t rev_lanes:1;
+                uint64_t gen1_only:1;
                 uint64_t prst_link:1;
                 uint64_t rst_done:1;
                 uint64_t rst_link:1;
@@ -1334,7 +2136,19 @@ union cvmx_mio_rst_ctlx {
                 uint64_t rst_chip:1;
                 uint64_t rst_val:1;
         } s;
-        struct cvmx_mio_rst_ctlx_s cn63xx;
+        struct cvmx_mio_rst_ctlx_s cn61xx;
+        struct cvmx_mio_rst_ctlx_cn63xx {
+                uint64_t reserved_10_63:54;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+        } cn63xx;
         struct cvmx_mio_rst_ctlx_cn63xxp1 {
                 uint64_t reserved_9_63:55;
                 uint64_t rst_done:1;
@@ -1346,17 +2160,24 @@ union cvmx_mio_rst_ctlx {
                 uint64_t rst_chip:1;
                 uint64_t rst_val:1;
         } cn63xxp1;
+        struct cvmx_mio_rst_ctlx_cn63xx cn66xx;
+        struct cvmx_mio_rst_ctlx_cn63xx cn68xx;
+        struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1;
 };
 
 union cvmx_mio_rst_delay {
         uint64_t u64;
         struct cvmx_mio_rst_delay_s {
                 uint64_t reserved_32_63:32;
-                uint64_t soft_rst_dly:16;
                 uint64_t warm_rst_dly:16;
+                uint64_t soft_rst_dly:16;
         } s;
+        struct cvmx_mio_rst_delay_s cn61xx;
         struct cvmx_mio_rst_delay_s cn63xx;
         struct cvmx_mio_rst_delay_s cn63xxp1;
+        struct cvmx_mio_rst_delay_s cn66xx;
+        struct cvmx_mio_rst_delay_s cn68xx;
+        struct cvmx_mio_rst_delay_s cn68xxp1;
 };
 
 union cvmx_mio_rst_int {
@@ -1365,12 +2186,25 @@ union cvmx_mio_rst_int {
                 uint64_t reserved_10_63:54;
                 uint64_t perst1:1;
                 uint64_t perst0:1;
-                uint64_t reserved_2_7:6;
+                uint64_t reserved_4_7:4;
+                uint64_t rst_link3:1;
+                uint64_t rst_link2:1;
                 uint64_t rst_link1:1;
                 uint64_t rst_link0:1;
         } s;
-        struct cvmx_mio_rst_int_s cn63xx;
-        struct cvmx_mio_rst_int_s cn63xxp1;
+        struct cvmx_mio_rst_int_cn61xx {
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_2_7:6;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+        } cn61xx;
+        struct cvmx_mio_rst_int_cn61xx cn63xx;
+        struct cvmx_mio_rst_int_cn61xx cn63xxp1;
+        struct cvmx_mio_rst_int_s cn66xx;
+        struct cvmx_mio_rst_int_cn61xx cn68xx;
+        struct cvmx_mio_rst_int_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_rst_int_en {
@@ -1379,12 +2213,25 @@ union cvmx_mio_rst_int_en {
                 uint64_t reserved_10_63:54;
                 uint64_t perst1:1;
                 uint64_t perst0:1;
-                uint64_t reserved_2_7:6;
+                uint64_t reserved_4_7:4;
+                uint64_t rst_link3:1;
+                uint64_t rst_link2:1;
                 uint64_t rst_link1:1;
                 uint64_t rst_link0:1;
         } s;
-        struct cvmx_mio_rst_int_en_s cn63xx;
-        struct cvmx_mio_rst_int_en_s cn63xxp1;
+        struct cvmx_mio_rst_int_en_cn61xx {
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_2_7:6;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+        } cn61xx;
+        struct cvmx_mio_rst_int_en_cn61xx cn63xx;
+        struct cvmx_mio_rst_int_en_cn61xx cn63xxp1;
+        struct cvmx_mio_rst_int_en_s cn66xx;
+        struct cvmx_mio_rst_int_en_cn61xx cn68xx;
+        struct cvmx_mio_rst_int_en_cn61xx cn68xxp1;
 };
 
 union cvmx_mio_twsx_int {
@@ -1424,8 +2271,12 @@ union cvmx_mio_twsx_int {
         struct cvmx_mio_twsx_int_s cn56xxp1;
         struct cvmx_mio_twsx_int_s cn58xx;
         struct cvmx_mio_twsx_int_s cn58xxp1;
+        struct cvmx_mio_twsx_int_s cn61xx;
         struct cvmx_mio_twsx_int_s cn63xx;
         struct cvmx_mio_twsx_int_s cn63xxp1;
+        struct cvmx_mio_twsx_int_s cn66xx;
+        struct cvmx_mio_twsx_int_s cn68xx;
+        struct cvmx_mio_twsx_int_s cn68xxp1;
 };
 
 union cvmx_mio_twsx_sw_twsi {
@@ -1455,8 +2306,12 @@ union cvmx_mio_twsx_sw_twsi {
         struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
         struct cvmx_mio_twsx_sw_twsi_s cn58xx;
         struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
+        struct cvmx_mio_twsx_sw_twsi_s cn61xx;
         struct cvmx_mio_twsx_sw_twsi_s cn63xx;
         struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
+        struct cvmx_mio_twsx_sw_twsi_s cn66xx;
+        struct cvmx_mio_twsx_sw_twsi_s cn68xx;
+        struct cvmx_mio_twsx_sw_twsi_s cn68xxp1;
 };
 
 union cvmx_mio_twsx_sw_twsi_ext {
@@ -1477,8 +2332,12 @@ union cvmx_mio_twsx_sw_twsi_ext {
         struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1;
 };
 
 union cvmx_mio_twsx_twsi_sw {
@@ -1499,8 +2358,12 @@ union cvmx_mio_twsx_twsi_sw {
         struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
         struct cvmx_mio_twsx_twsi_sw_s cn58xx;
         struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
+        struct cvmx_mio_twsx_twsi_sw_s cn61xx;
         struct cvmx_mio_twsx_twsi_sw_s cn63xx;
         struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
+        struct cvmx_mio_twsx_twsi_sw_s cn66xx;
+        struct cvmx_mio_twsx_twsi_sw_s cn68xx;
+        struct cvmx_mio_twsx_twsi_sw_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_dlh {
@@ -1520,8 +2383,12 @@ union cvmx_mio_uartx_dlh {
         struct cvmx_mio_uartx_dlh_s cn56xxp1;
         struct cvmx_mio_uartx_dlh_s cn58xx;
         struct cvmx_mio_uartx_dlh_s cn58xxp1;
+        struct cvmx_mio_uartx_dlh_s cn61xx;
         struct cvmx_mio_uartx_dlh_s cn63xx;
         struct cvmx_mio_uartx_dlh_s cn63xxp1;
+        struct cvmx_mio_uartx_dlh_s cn66xx;
+        struct cvmx_mio_uartx_dlh_s cn68xx;
+        struct cvmx_mio_uartx_dlh_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_dll {
@@ -1541,8 +2408,12 @@ union cvmx_mio_uartx_dll {
         struct cvmx_mio_uartx_dll_s cn56xxp1;
         struct cvmx_mio_uartx_dll_s cn58xx;
         struct cvmx_mio_uartx_dll_s cn58xxp1;
+        struct cvmx_mio_uartx_dll_s cn61xx;
         struct cvmx_mio_uartx_dll_s cn63xx;
         struct cvmx_mio_uartx_dll_s cn63xxp1;
+        struct cvmx_mio_uartx_dll_s cn66xx;
+        struct cvmx_mio_uartx_dll_s cn68xx;
+        struct cvmx_mio_uartx_dll_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_far {
@@ -1562,8 +2433,12 @@ union cvmx_mio_uartx_far {
         struct cvmx_mio_uartx_far_s cn56xxp1;
         struct cvmx_mio_uartx_far_s cn58xx;
         struct cvmx_mio_uartx_far_s cn58xxp1;
+        struct cvmx_mio_uartx_far_s cn61xx;
         struct cvmx_mio_uartx_far_s cn63xx;
         struct cvmx_mio_uartx_far_s cn63xxp1;
+        struct cvmx_mio_uartx_far_s cn66xx;
+        struct cvmx_mio_uartx_far_s cn68xx;
+        struct cvmx_mio_uartx_far_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_fcr {
@@ -1588,8 +2463,12 @@ union cvmx_mio_uartx_fcr {
         struct cvmx_mio_uartx_fcr_s cn56xxp1;
         struct cvmx_mio_uartx_fcr_s cn58xx;
         struct cvmx_mio_uartx_fcr_s cn58xxp1;
+        struct cvmx_mio_uartx_fcr_s cn61xx;
         struct cvmx_mio_uartx_fcr_s cn63xx;
         struct cvmx_mio_uartx_fcr_s cn63xxp1;
+        struct cvmx_mio_uartx_fcr_s cn66xx;
+        struct cvmx_mio_uartx_fcr_s cn68xx;
+        struct cvmx_mio_uartx_fcr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_htx {
@@ -1609,8 +2488,12 @@ union cvmx_mio_uartx_htx {
         struct cvmx_mio_uartx_htx_s cn56xxp1;
         struct cvmx_mio_uartx_htx_s cn58xx;
         struct cvmx_mio_uartx_htx_s cn58xxp1;
+        struct cvmx_mio_uartx_htx_s cn61xx;
         struct cvmx_mio_uartx_htx_s cn63xx;
         struct cvmx_mio_uartx_htx_s cn63xxp1;
+        struct cvmx_mio_uartx_htx_s cn66xx;
+        struct cvmx_mio_uartx_htx_s cn68xx;
+        struct cvmx_mio_uartx_htx_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_ier {
@@ -1635,8 +2518,12 @@ union cvmx_mio_uartx_ier {
         struct cvmx_mio_uartx_ier_s cn56xxp1;
         struct cvmx_mio_uartx_ier_s cn58xx;
         struct cvmx_mio_uartx_ier_s cn58xxp1;
+        struct cvmx_mio_uartx_ier_s cn61xx;
         struct cvmx_mio_uartx_ier_s cn63xx;
         struct cvmx_mio_uartx_ier_s cn63xxp1;
+        struct cvmx_mio_uartx_ier_s cn66xx;
+        struct cvmx_mio_uartx_ier_s cn68xx;
+        struct cvmx_mio_uartx_ier_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_iir {
@@ -1658,8 +2545,12 @@ union cvmx_mio_uartx_iir {
         struct cvmx_mio_uartx_iir_s cn56xxp1;
         struct cvmx_mio_uartx_iir_s cn58xx;
         struct cvmx_mio_uartx_iir_s cn58xxp1;
+        struct cvmx_mio_uartx_iir_s cn61xx;
         struct cvmx_mio_uartx_iir_s cn63xx;
         struct cvmx_mio_uartx_iir_s cn63xxp1;
+        struct cvmx_mio_uartx_iir_s cn66xx;
+        struct cvmx_mio_uartx_iir_s cn68xx;
+        struct cvmx_mio_uartx_iir_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_lcr {
@@ -1685,8 +2576,12 @@ union cvmx_mio_uartx_lcr {
         struct cvmx_mio_uartx_lcr_s cn56xxp1;
         struct cvmx_mio_uartx_lcr_s cn58xx;
         struct cvmx_mio_uartx_lcr_s cn58xxp1;
+        struct cvmx_mio_uartx_lcr_s cn61xx;
         struct cvmx_mio_uartx_lcr_s cn63xx;
         struct cvmx_mio_uartx_lcr_s cn63xxp1;
+        struct cvmx_mio_uartx_lcr_s cn66xx;
+        struct cvmx_mio_uartx_lcr_s cn68xx;
+        struct cvmx_mio_uartx_lcr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_lsr {
@@ -1713,8 +2608,12 @@ union cvmx_mio_uartx_lsr {
         struct cvmx_mio_uartx_lsr_s cn56xxp1;
         struct cvmx_mio_uartx_lsr_s cn58xx;
         struct cvmx_mio_uartx_lsr_s cn58xxp1;
+        struct cvmx_mio_uartx_lsr_s cn61xx;
         struct cvmx_mio_uartx_lsr_s cn63xx;
         struct cvmx_mio_uartx_lsr_s cn63xxp1;
+        struct cvmx_mio_uartx_lsr_s cn66xx;
+        struct cvmx_mio_uartx_lsr_s cn68xx;
+        struct cvmx_mio_uartx_lsr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_mcr {
@@ -1739,8 +2638,12 @@ union cvmx_mio_uartx_mcr {
         struct cvmx_mio_uartx_mcr_s cn56xxp1;
         struct cvmx_mio_uartx_mcr_s cn58xx;
         struct cvmx_mio_uartx_mcr_s cn58xxp1;
+        struct cvmx_mio_uartx_mcr_s cn61xx;
         struct cvmx_mio_uartx_mcr_s cn63xx;
         struct cvmx_mio_uartx_mcr_s cn63xxp1;
+        struct cvmx_mio_uartx_mcr_s cn66xx;
+        struct cvmx_mio_uartx_mcr_s cn68xx;
+        struct cvmx_mio_uartx_mcr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_msr {
@@ -1767,8 +2670,12 @@ union cvmx_mio_uartx_msr {
         struct cvmx_mio_uartx_msr_s cn56xxp1;
         struct cvmx_mio_uartx_msr_s cn58xx;
         struct cvmx_mio_uartx_msr_s cn58xxp1;
+        struct cvmx_mio_uartx_msr_s cn61xx;
         struct cvmx_mio_uartx_msr_s cn63xx;
         struct cvmx_mio_uartx_msr_s cn63xxp1;
+        struct cvmx_mio_uartx_msr_s cn66xx;
+        struct cvmx_mio_uartx_msr_s cn68xx;
+        struct cvmx_mio_uartx_msr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_rbr {
@@ -1788,8 +2695,12 @@ union cvmx_mio_uartx_rbr {
         struct cvmx_mio_uartx_rbr_s cn56xxp1;
         struct cvmx_mio_uartx_rbr_s cn58xx;
         struct cvmx_mio_uartx_rbr_s cn58xxp1;
+        struct cvmx_mio_uartx_rbr_s cn61xx;
         struct cvmx_mio_uartx_rbr_s cn63xx;
         struct cvmx_mio_uartx_rbr_s cn63xxp1;
+        struct cvmx_mio_uartx_rbr_s cn66xx;
+        struct cvmx_mio_uartx_rbr_s cn68xx;
+        struct cvmx_mio_uartx_rbr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_rfl {
@@ -1809,8 +2720,12 @@ union cvmx_mio_uartx_rfl {
         struct cvmx_mio_uartx_rfl_s cn56xxp1;
         struct cvmx_mio_uartx_rfl_s cn58xx;
         struct cvmx_mio_uartx_rfl_s cn58xxp1;
+        struct cvmx_mio_uartx_rfl_s cn61xx;
         struct cvmx_mio_uartx_rfl_s cn63xx;
         struct cvmx_mio_uartx_rfl_s cn63xxp1;
+        struct cvmx_mio_uartx_rfl_s cn66xx;
+        struct cvmx_mio_uartx_rfl_s cn68xx;
+        struct cvmx_mio_uartx_rfl_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_rfw {
@@ -1832,8 +2747,12 @@ union cvmx_mio_uartx_rfw {
         struct cvmx_mio_uartx_rfw_s cn56xxp1;
         struct cvmx_mio_uartx_rfw_s cn58xx;
         struct cvmx_mio_uartx_rfw_s cn58xxp1;
+        struct cvmx_mio_uartx_rfw_s cn61xx;
         struct cvmx_mio_uartx_rfw_s cn63xx;
         struct cvmx_mio_uartx_rfw_s cn63xxp1;
+        struct cvmx_mio_uartx_rfw_s cn66xx;
+        struct cvmx_mio_uartx_rfw_s cn68xx;
+        struct cvmx_mio_uartx_rfw_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_sbcr {
@@ -1853,8 +2772,12 @@ union cvmx_mio_uartx_sbcr {
         struct cvmx_mio_uartx_sbcr_s cn56xxp1;
         struct cvmx_mio_uartx_sbcr_s cn58xx;
         struct cvmx_mio_uartx_sbcr_s cn58xxp1;
+        struct cvmx_mio_uartx_sbcr_s cn61xx;
         struct cvmx_mio_uartx_sbcr_s cn63xx;
         struct cvmx_mio_uartx_sbcr_s cn63xxp1;
+        struct cvmx_mio_uartx_sbcr_s cn66xx;
+        struct cvmx_mio_uartx_sbcr_s cn68xx;
+        struct cvmx_mio_uartx_sbcr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_scr {
@@ -1874,8 +2797,12 @@ union cvmx_mio_uartx_scr {
         struct cvmx_mio_uartx_scr_s cn56xxp1;
         struct cvmx_mio_uartx_scr_s cn58xx;
         struct cvmx_mio_uartx_scr_s cn58xxp1;
+        struct cvmx_mio_uartx_scr_s cn61xx;
         struct cvmx_mio_uartx_scr_s cn63xx;
         struct cvmx_mio_uartx_scr_s cn63xxp1;
+        struct cvmx_mio_uartx_scr_s cn66xx;
+        struct cvmx_mio_uartx_scr_s cn68xx;
+        struct cvmx_mio_uartx_scr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_sfe {
@@ -1895,8 +2822,12 @@ union cvmx_mio_uartx_sfe {
         struct cvmx_mio_uartx_sfe_s cn56xxp1;
         struct cvmx_mio_uartx_sfe_s cn58xx;
         struct cvmx_mio_uartx_sfe_s cn58xxp1;
+        struct cvmx_mio_uartx_sfe_s cn61xx;
         struct cvmx_mio_uartx_sfe_s cn63xx;
         struct cvmx_mio_uartx_sfe_s cn63xxp1;
+        struct cvmx_mio_uartx_sfe_s cn66xx;
+        struct cvmx_mio_uartx_sfe_s cn68xx;
+        struct cvmx_mio_uartx_sfe_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_srr {
@@ -1918,8 +2849,12 @@ union cvmx_mio_uartx_srr {
         struct cvmx_mio_uartx_srr_s cn56xxp1;
         struct cvmx_mio_uartx_srr_s cn58xx;
         struct cvmx_mio_uartx_srr_s cn58xxp1;
+        struct cvmx_mio_uartx_srr_s cn61xx;
         struct cvmx_mio_uartx_srr_s cn63xx;
         struct cvmx_mio_uartx_srr_s cn63xxp1;
+        struct cvmx_mio_uartx_srr_s cn66xx;
+        struct cvmx_mio_uartx_srr_s cn68xx;
+        struct cvmx_mio_uartx_srr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_srt {
@@ -1939,8 +2874,12 @@ union cvmx_mio_uartx_srt {
         struct cvmx_mio_uartx_srt_s cn56xxp1;
         struct cvmx_mio_uartx_srt_s cn58xx;
         struct cvmx_mio_uartx_srt_s cn58xxp1;
+        struct cvmx_mio_uartx_srt_s cn61xx;
         struct cvmx_mio_uartx_srt_s cn63xx;
         struct cvmx_mio_uartx_srt_s cn63xxp1;
+        struct cvmx_mio_uartx_srt_s cn66xx;
+        struct cvmx_mio_uartx_srt_s cn68xx;
+        struct cvmx_mio_uartx_srt_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_srts {
@@ -1960,8 +2899,12 @@ union cvmx_mio_uartx_srts {
         struct cvmx_mio_uartx_srts_s cn56xxp1;
         struct cvmx_mio_uartx_srts_s cn58xx;
         struct cvmx_mio_uartx_srts_s cn58xxp1;
+        struct cvmx_mio_uartx_srts_s cn61xx;
         struct cvmx_mio_uartx_srts_s cn63xx;
         struct cvmx_mio_uartx_srts_s cn63xxp1;
+        struct cvmx_mio_uartx_srts_s cn66xx;
+        struct cvmx_mio_uartx_srts_s cn68xx;
+        struct cvmx_mio_uartx_srts_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_stt {
@@ -1981,8 +2924,12 @@ union cvmx_mio_uartx_stt {
         struct cvmx_mio_uartx_stt_s cn56xxp1;
         struct cvmx_mio_uartx_stt_s cn58xx;
         struct cvmx_mio_uartx_stt_s cn58xxp1;
+        struct cvmx_mio_uartx_stt_s cn61xx;
         struct cvmx_mio_uartx_stt_s cn63xx;
         struct cvmx_mio_uartx_stt_s cn63xxp1;
+        struct cvmx_mio_uartx_stt_s cn66xx;
+        struct cvmx_mio_uartx_stt_s cn68xx;
+        struct cvmx_mio_uartx_stt_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_tfl {
@@ -2002,8 +2949,12 @@ union cvmx_mio_uartx_tfl {
         struct cvmx_mio_uartx_tfl_s cn56xxp1;
         struct cvmx_mio_uartx_tfl_s cn58xx;
         struct cvmx_mio_uartx_tfl_s cn58xxp1;
+        struct cvmx_mio_uartx_tfl_s cn61xx;
         struct cvmx_mio_uartx_tfl_s cn63xx;
         struct cvmx_mio_uartx_tfl_s cn63xxp1;
+        struct cvmx_mio_uartx_tfl_s cn66xx;
+        struct cvmx_mio_uartx_tfl_s cn68xx;
+        struct cvmx_mio_uartx_tfl_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_tfr {
@@ -2023,8 +2974,12 @@ union cvmx_mio_uartx_tfr {
         struct cvmx_mio_uartx_tfr_s cn56xxp1;
         struct cvmx_mio_uartx_tfr_s cn58xx;
         struct cvmx_mio_uartx_tfr_s cn58xxp1;
+        struct cvmx_mio_uartx_tfr_s cn61xx;
         struct cvmx_mio_uartx_tfr_s cn63xx;
         struct cvmx_mio_uartx_tfr_s cn63xxp1;
+        struct cvmx_mio_uartx_tfr_s cn66xx;
+        struct cvmx_mio_uartx_tfr_s cn68xx;
+        struct cvmx_mio_uartx_tfr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_thr {
@@ -2044,8 +2999,12 @@ union cvmx_mio_uartx_thr {
         struct cvmx_mio_uartx_thr_s cn56xxp1;
         struct cvmx_mio_uartx_thr_s cn58xx;
         struct cvmx_mio_uartx_thr_s cn58xxp1;
+        struct cvmx_mio_uartx_thr_s cn61xx;
         struct cvmx_mio_uartx_thr_s cn63xx;
         struct cvmx_mio_uartx_thr_s cn63xxp1;
+        struct cvmx_mio_uartx_thr_s cn66xx;
+        struct cvmx_mio_uartx_thr_s cn68xx;
+        struct cvmx_mio_uartx_thr_s cn68xxp1;
 };
 
 union cvmx_mio_uartx_usr {
@@ -2069,8 +3028,12 @@ union cvmx_mio_uartx_usr {
         struct cvmx_mio_uartx_usr_s cn56xxp1;
         struct cvmx_mio_uartx_usr_s cn58xx;
         struct cvmx_mio_uartx_usr_s cn58xxp1;
+        struct cvmx_mio_uartx_usr_s cn61xx;
         struct cvmx_mio_uartx_usr_s cn63xx;
         struct cvmx_mio_uartx_usr_s cn63xxp1;
+        struct cvmx_mio_uartx_usr_s cn66xx;
+        struct cvmx_mio_uartx_usr_s cn68xx;
+        struct cvmx_mio_uartx_usr_s cn68xxp1;
 };
 
 union cvmx_mio_uart2_dlh {
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 9899a9d2ba72..a3075f733ca5 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2011 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -65,7 +65,7 @@
 #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
 #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
 #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
-#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
 #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
 #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
 #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index f8cb88902efb..7b1dc8b74e5b 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2011 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -116,8 +116,12 @@ union cvmx_pciercx_cfg000 {
         struct cvmx_pciercx_cfg000_s cn52xxp1;
         struct cvmx_pciercx_cfg000_s cn56xx;
         struct cvmx_pciercx_cfg000_s cn56xxp1;
+        struct cvmx_pciercx_cfg000_s cn61xx;
         struct cvmx_pciercx_cfg000_s cn63xx;
         struct cvmx_pciercx_cfg000_s cn63xxp1;
+        struct cvmx_pciercx_cfg000_s cn66xx;
+        struct cvmx_pciercx_cfg000_s cn68xx;
+        struct cvmx_pciercx_cfg000_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg001 {
@@ -152,8 +156,12 @@ union cvmx_pciercx_cfg001 {
         struct cvmx_pciercx_cfg001_s cn52xxp1;
         struct cvmx_pciercx_cfg001_s cn56xx;
         struct cvmx_pciercx_cfg001_s cn56xxp1;
+        struct cvmx_pciercx_cfg001_s cn61xx;
         struct cvmx_pciercx_cfg001_s cn63xx;
         struct cvmx_pciercx_cfg001_s cn63xxp1;
+        struct cvmx_pciercx_cfg001_s cn66xx;
+        struct cvmx_pciercx_cfg001_s cn68xx;
+        struct cvmx_pciercx_cfg001_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg002 {
@@ -168,8 +176,12 @@ union cvmx_pciercx_cfg002 {
         struct cvmx_pciercx_cfg002_s cn52xxp1;
         struct cvmx_pciercx_cfg002_s cn56xx;
         struct cvmx_pciercx_cfg002_s cn56xxp1;
+        struct cvmx_pciercx_cfg002_s cn61xx;
         struct cvmx_pciercx_cfg002_s cn63xx;
         struct cvmx_pciercx_cfg002_s cn63xxp1;
+        struct cvmx_pciercx_cfg002_s cn66xx;
+        struct cvmx_pciercx_cfg002_s cn68xx;
+        struct cvmx_pciercx_cfg002_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg003 {
@@ -185,8 +197,12 @@ union cvmx_pciercx_cfg003 {
         struct cvmx_pciercx_cfg003_s cn52xxp1;
         struct cvmx_pciercx_cfg003_s cn56xx;
         struct cvmx_pciercx_cfg003_s cn56xxp1;
+        struct cvmx_pciercx_cfg003_s cn61xx;
         struct cvmx_pciercx_cfg003_s cn63xx;
         struct cvmx_pciercx_cfg003_s cn63xxp1;
+        struct cvmx_pciercx_cfg003_s cn66xx;
+        struct cvmx_pciercx_cfg003_s cn68xx;
+        struct cvmx_pciercx_cfg003_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg004 {
@@ -198,8 +214,12 @@ union cvmx_pciercx_cfg004 {
         struct cvmx_pciercx_cfg004_s cn52xxp1;
         struct cvmx_pciercx_cfg004_s cn56xx;
         struct cvmx_pciercx_cfg004_s cn56xxp1;
+        struct cvmx_pciercx_cfg004_s cn61xx;
         struct cvmx_pciercx_cfg004_s cn63xx;
         struct cvmx_pciercx_cfg004_s cn63xxp1;
+        struct cvmx_pciercx_cfg004_s cn66xx;
+        struct cvmx_pciercx_cfg004_s cn68xx;
+        struct cvmx_pciercx_cfg004_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg005 {
@@ -211,8 +231,12 @@ union cvmx_pciercx_cfg005 {
         struct cvmx_pciercx_cfg005_s cn52xxp1;
         struct cvmx_pciercx_cfg005_s cn56xx;
         struct cvmx_pciercx_cfg005_s cn56xxp1;
+        struct cvmx_pciercx_cfg005_s cn61xx;
         struct cvmx_pciercx_cfg005_s cn63xx;
         struct cvmx_pciercx_cfg005_s cn63xxp1;
+        struct cvmx_pciercx_cfg005_s cn66xx;
+        struct cvmx_pciercx_cfg005_s cn68xx;
+        struct cvmx_pciercx_cfg005_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg006 {
@@ -227,8 +251,12 @@ union cvmx_pciercx_cfg006 {
         struct cvmx_pciercx_cfg006_s cn52xxp1;
         struct cvmx_pciercx_cfg006_s cn56xx;
         struct cvmx_pciercx_cfg006_s cn56xxp1;
+        struct cvmx_pciercx_cfg006_s cn61xx;
         struct cvmx_pciercx_cfg006_s cn63xx;
         struct cvmx_pciercx_cfg006_s cn63xxp1;
+        struct cvmx_pciercx_cfg006_s cn66xx;
+        struct cvmx_pciercx_cfg006_s cn68xx;
+        struct cvmx_pciercx_cfg006_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg007 {
@@ -256,8 +284,12 @@ union cvmx_pciercx_cfg007 {
         struct cvmx_pciercx_cfg007_s cn52xxp1;
         struct cvmx_pciercx_cfg007_s cn56xx;
         struct cvmx_pciercx_cfg007_s cn56xxp1;
+        struct cvmx_pciercx_cfg007_s cn61xx;
         struct cvmx_pciercx_cfg007_s cn63xx;
         struct cvmx_pciercx_cfg007_s cn63xxp1;
+        struct cvmx_pciercx_cfg007_s cn66xx;
+        struct cvmx_pciercx_cfg007_s cn68xx;
+        struct cvmx_pciercx_cfg007_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg008 {
@@ -272,8 +304,12 @@ union cvmx_pciercx_cfg008 {
         struct cvmx_pciercx_cfg008_s cn52xxp1;
         struct cvmx_pciercx_cfg008_s cn56xx;
         struct cvmx_pciercx_cfg008_s cn56xxp1;
+        struct cvmx_pciercx_cfg008_s cn61xx;
         struct cvmx_pciercx_cfg008_s cn63xx;
         struct cvmx_pciercx_cfg008_s cn63xxp1;
+        struct cvmx_pciercx_cfg008_s cn66xx;
+        struct cvmx_pciercx_cfg008_s cn68xx;
+        struct cvmx_pciercx_cfg008_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg009 {
@@ -290,8 +326,12 @@ union cvmx_pciercx_cfg009 {
         struct cvmx_pciercx_cfg009_s cn52xxp1;
         struct cvmx_pciercx_cfg009_s cn56xx;
         struct cvmx_pciercx_cfg009_s cn56xxp1;
+        struct cvmx_pciercx_cfg009_s cn61xx;
         struct cvmx_pciercx_cfg009_s cn63xx;
         struct cvmx_pciercx_cfg009_s cn63xxp1;
+        struct cvmx_pciercx_cfg009_s cn66xx;
+        struct cvmx_pciercx_cfg009_s cn68xx;
+        struct cvmx_pciercx_cfg009_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg010 {
@@ -303,8 +343,12 @@ union cvmx_pciercx_cfg010 {
         struct cvmx_pciercx_cfg010_s cn52xxp1;
         struct cvmx_pciercx_cfg010_s cn56xx;
         struct cvmx_pciercx_cfg010_s cn56xxp1;
+        struct cvmx_pciercx_cfg010_s cn61xx;
         struct cvmx_pciercx_cfg010_s cn63xx;
         struct cvmx_pciercx_cfg010_s cn63xxp1;
+        struct cvmx_pciercx_cfg010_s cn66xx;
+        struct cvmx_pciercx_cfg010_s cn68xx;
+        struct cvmx_pciercx_cfg010_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg011 {
@@ -316,8 +360,12 @@ union cvmx_pciercx_cfg011 {
         struct cvmx_pciercx_cfg011_s cn52xxp1;
         struct cvmx_pciercx_cfg011_s cn56xx;
         struct cvmx_pciercx_cfg011_s cn56xxp1;
+        struct cvmx_pciercx_cfg011_s cn61xx;
         struct cvmx_pciercx_cfg011_s cn63xx;
         struct cvmx_pciercx_cfg011_s cn63xxp1;
+        struct cvmx_pciercx_cfg011_s cn66xx;
+        struct cvmx_pciercx_cfg011_s cn68xx;
+        struct cvmx_pciercx_cfg011_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg012 {
@@ -330,8 +378,12 @@ union cvmx_pciercx_cfg012 {
         struct cvmx_pciercx_cfg012_s cn52xxp1;
         struct cvmx_pciercx_cfg012_s cn56xx;
         struct cvmx_pciercx_cfg012_s cn56xxp1;
+        struct cvmx_pciercx_cfg012_s cn61xx;
         struct cvmx_pciercx_cfg012_s cn63xx;
         struct cvmx_pciercx_cfg012_s cn63xxp1;
+        struct cvmx_pciercx_cfg012_s cn66xx;
+        struct cvmx_pciercx_cfg012_s cn68xx;
+        struct cvmx_pciercx_cfg012_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg013 {
@@ -344,8 +396,12 @@ union cvmx_pciercx_cfg013 {
         struct cvmx_pciercx_cfg013_s cn52xxp1;
         struct cvmx_pciercx_cfg013_s cn56xx;
         struct cvmx_pciercx_cfg013_s cn56xxp1;
+        struct cvmx_pciercx_cfg013_s cn61xx;
         struct cvmx_pciercx_cfg013_s cn63xx;
         struct cvmx_pciercx_cfg013_s cn63xxp1;
+        struct cvmx_pciercx_cfg013_s cn66xx;
+        struct cvmx_pciercx_cfg013_s cn68xx;
+        struct cvmx_pciercx_cfg013_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg014 {
@@ -357,8 +413,12 @@ union cvmx_pciercx_cfg014 {
         struct cvmx_pciercx_cfg014_s cn52xxp1;
         struct cvmx_pciercx_cfg014_s cn56xx;
         struct cvmx_pciercx_cfg014_s cn56xxp1;
+        struct cvmx_pciercx_cfg014_s cn61xx;
         struct cvmx_pciercx_cfg014_s cn63xx;
         struct cvmx_pciercx_cfg014_s cn63xxp1;
+        struct cvmx_pciercx_cfg014_s cn66xx;
+        struct cvmx_pciercx_cfg014_s cn68xx;
+        struct cvmx_pciercx_cfg014_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg015 {
@@ -384,8 +444,12 @@ union cvmx_pciercx_cfg015 {
         struct cvmx_pciercx_cfg015_s cn52xxp1;
         struct cvmx_pciercx_cfg015_s cn56xx;
         struct cvmx_pciercx_cfg015_s cn56xxp1;
+        struct cvmx_pciercx_cfg015_s cn61xx;
         struct cvmx_pciercx_cfg015_s cn63xx;
         struct cvmx_pciercx_cfg015_s cn63xxp1;
+        struct cvmx_pciercx_cfg015_s cn66xx;
+        struct cvmx_pciercx_cfg015_s cn68xx;
+        struct cvmx_pciercx_cfg015_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg016 {
@@ -406,8 +470,12 @@ union cvmx_pciercx_cfg016 {
         struct cvmx_pciercx_cfg016_s cn52xxp1;
         struct cvmx_pciercx_cfg016_s cn56xx;
         struct cvmx_pciercx_cfg016_s cn56xxp1;
+        struct cvmx_pciercx_cfg016_s cn61xx;
         struct cvmx_pciercx_cfg016_s cn63xx;
         struct cvmx_pciercx_cfg016_s cn63xxp1;
+        struct cvmx_pciercx_cfg016_s cn66xx;
+        struct cvmx_pciercx_cfg016_s cn68xx;
+        struct cvmx_pciercx_cfg016_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg017 {
@@ -430,14 +498,19 @@ union cvmx_pciercx_cfg017 {
         struct cvmx_pciercx_cfg017_s cn52xxp1;
         struct cvmx_pciercx_cfg017_s cn56xx;
         struct cvmx_pciercx_cfg017_s cn56xxp1;
+        struct cvmx_pciercx_cfg017_s cn61xx;
         struct cvmx_pciercx_cfg017_s cn63xx;
         struct cvmx_pciercx_cfg017_s cn63xxp1;
+        struct cvmx_pciercx_cfg017_s cn66xx;
+        struct cvmx_pciercx_cfg017_s cn68xx;
+        struct cvmx_pciercx_cfg017_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg020 {
         uint32_t u32;
         struct cvmx_pciercx_cfg020_s {
-                uint32_t reserved_24_31:8;
+                uint32_t reserved_25_31:7;
+                uint32_t pvm:1;
                 uint32_t m64:1;
                 uint32_t mme:3;
                 uint32_t mmc:3;
@@ -445,12 +518,24 @@ union cvmx_pciercx_cfg020 {
                 uint32_t ncp:8;
                 uint32_t msicid:8;
         } s;
-        struct cvmx_pciercx_cfg020_s cn52xx;
-        struct cvmx_pciercx_cfg020_s cn52xxp1;
-        struct cvmx_pciercx_cfg020_s cn56xx;
-        struct cvmx_pciercx_cfg020_s cn56xxp1;
-        struct cvmx_pciercx_cfg020_s cn63xx;
-        struct cvmx_pciercx_cfg020_s cn63xxp1;
+        struct cvmx_pciercx_cfg020_cn52xx {
+                uint32_t reserved_24_31:8;
+                uint32_t m64:1;
+                uint32_t mme:3;
+                uint32_t mmc:3;
+                uint32_t msien:1;
+                uint32_t ncp:8;
+                uint32_t msicid:8;
+        } cn52xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg020_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg020_s cn61xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg020_cn52xx cn66xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn68xx;
+        struct cvmx_pciercx_cfg020_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg021 {
@@ -463,8 +548,12 @@ union cvmx_pciercx_cfg021 {
         struct cvmx_pciercx_cfg021_s cn52xxp1;
         struct cvmx_pciercx_cfg021_s cn56xx;
         struct cvmx_pciercx_cfg021_s cn56xxp1;
+        struct cvmx_pciercx_cfg021_s cn61xx;
         struct cvmx_pciercx_cfg021_s cn63xx;
         struct cvmx_pciercx_cfg021_s cn63xxp1;
+        struct cvmx_pciercx_cfg021_s cn66xx;
+        struct cvmx_pciercx_cfg021_s cn68xx;
+        struct cvmx_pciercx_cfg021_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg022 {
@@ -476,8 +565,12 @@ union cvmx_pciercx_cfg022 {
         struct cvmx_pciercx_cfg022_s cn52xxp1;
         struct cvmx_pciercx_cfg022_s cn56xx;
         struct cvmx_pciercx_cfg022_s cn56xxp1;
+        struct cvmx_pciercx_cfg022_s cn61xx;
         struct cvmx_pciercx_cfg022_s cn63xx;
         struct cvmx_pciercx_cfg022_s cn63xxp1;
+        struct cvmx_pciercx_cfg022_s cn66xx;
+        struct cvmx_pciercx_cfg022_s cn68xx;
+        struct cvmx_pciercx_cfg022_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg023 {
@@ -490,8 +583,12 @@ union cvmx_pciercx_cfg023 {
         struct cvmx_pciercx_cfg023_s cn52xxp1;
         struct cvmx_pciercx_cfg023_s cn56xx;
         struct cvmx_pciercx_cfg023_s cn56xxp1;
+        struct cvmx_pciercx_cfg023_s cn61xx;
         struct cvmx_pciercx_cfg023_s cn63xx;
         struct cvmx_pciercx_cfg023_s cn63xxp1;
+        struct cvmx_pciercx_cfg023_s cn66xx;
+        struct cvmx_pciercx_cfg023_s cn68xx;
+        struct cvmx_pciercx_cfg023_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg028 {
@@ -509,8 +606,12 @@ union cvmx_pciercx_cfg028 {
         struct cvmx_pciercx_cfg028_s cn52xxp1;
         struct cvmx_pciercx_cfg028_s cn56xx;
         struct cvmx_pciercx_cfg028_s cn56xxp1;
+        struct cvmx_pciercx_cfg028_s cn61xx;
         struct cvmx_pciercx_cfg028_s cn63xx;
         struct cvmx_pciercx_cfg028_s cn63xxp1;
+        struct cvmx_pciercx_cfg028_s cn66xx;
+        struct cvmx_pciercx_cfg028_s cn68xx;
+        struct cvmx_pciercx_cfg028_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg029 {
@@ -532,8 +633,12 @@ union cvmx_pciercx_cfg029 {
         struct cvmx_pciercx_cfg029_s cn52xxp1;
         struct cvmx_pciercx_cfg029_s cn56xx;
         struct cvmx_pciercx_cfg029_s cn56xxp1;
+        struct cvmx_pciercx_cfg029_s cn61xx;
         struct cvmx_pciercx_cfg029_s cn63xx;
         struct cvmx_pciercx_cfg029_s cn63xxp1;
+        struct cvmx_pciercx_cfg029_s cn66xx;
+        struct cvmx_pciercx_cfg029_s cn68xx;
+        struct cvmx_pciercx_cfg029_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg030 {
@@ -563,15 +668,20 @@ union cvmx_pciercx_cfg030 {
         struct cvmx_pciercx_cfg030_s cn52xxp1;
         struct cvmx_pciercx_cfg030_s cn56xx;
         struct cvmx_pciercx_cfg030_s cn56xxp1;
+        struct cvmx_pciercx_cfg030_s cn61xx;
         struct cvmx_pciercx_cfg030_s cn63xx;
         struct cvmx_pciercx_cfg030_s cn63xxp1;
+        struct cvmx_pciercx_cfg030_s cn66xx;
+        struct cvmx_pciercx_cfg030_s cn68xx;
+        struct cvmx_pciercx_cfg030_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg031 {
         uint32_t u32;
         struct cvmx_pciercx_cfg031_s {
                 uint32_t pnum:8;
-                uint32_t reserved_22_23:2;
+                uint32_t reserved_23_23:1;
+                uint32_t aspm:1;
                 uint32_t lbnc:1;
                 uint32_t dllarc:1;
                 uint32_t sderc:1;
@@ -582,12 +692,28 @@ union cvmx_pciercx_cfg031 {
                 uint32_t mlw:6;
                 uint32_t mls:4;
         } s;
-        struct cvmx_pciercx_cfg031_s cn52xx;
-        struct cvmx_pciercx_cfg031_s cn52xxp1;
-        struct cvmx_pciercx_cfg031_s cn56xx;
-        struct cvmx_pciercx_cfg031_s cn56xxp1;
-        struct cvmx_pciercx_cfg031_s cn63xx;
-        struct cvmx_pciercx_cfg031_s cn63xxp1;
+        struct cvmx_pciercx_cfg031_cn52xx {
+                uint32_t pnum:8;
+                uint32_t reserved_22_23:2;
+                uint32_t lbnc:1;
+                uint32_t dllarc:1;
+                uint32_t sderc:1;
+                uint32_t cpm:1;
+                uint32_t l1el:3;
+                uint32_t l0el:3;
+                uint32_t aslpms:2;
+                uint32_t mlw:6;
+                uint32_t mls:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg031_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg031_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg031_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg031_s cn61xx;
+        struct cvmx_pciercx_cfg031_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg031_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg031_s cn66xx;
+        struct cvmx_pciercx_cfg031_s cn68xx;
+        struct cvmx_pciercx_cfg031_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg032 {
@@ -618,8 +744,12 @@ union cvmx_pciercx_cfg032 {
         struct cvmx_pciercx_cfg032_s cn52xxp1;
         struct cvmx_pciercx_cfg032_s cn56xx;
         struct cvmx_pciercx_cfg032_s cn56xxp1;
+        struct cvmx_pciercx_cfg032_s cn61xx;
         struct cvmx_pciercx_cfg032_s cn63xx;
         struct cvmx_pciercx_cfg032_s cn63xxp1;
+        struct cvmx_pciercx_cfg032_s cn66xx;
+        struct cvmx_pciercx_cfg032_s cn68xx;
+        struct cvmx_pciercx_cfg032_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg033 {
@@ -642,8 +772,12 @@ union cvmx_pciercx_cfg033 {
         struct cvmx_pciercx_cfg033_s cn52xxp1;
         struct cvmx_pciercx_cfg033_s cn56xx;
         struct cvmx_pciercx_cfg033_s cn56xxp1;
+        struct cvmx_pciercx_cfg033_s cn61xx;
         struct cvmx_pciercx_cfg033_s cn63xx;
         struct cvmx_pciercx_cfg033_s cn63xxp1;
+        struct cvmx_pciercx_cfg033_s cn66xx;
+        struct cvmx_pciercx_cfg033_s cn68xx;
+        struct cvmx_pciercx_cfg033_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg034 {
@@ -676,8 +810,12 @@ union cvmx_pciercx_cfg034 {
         struct cvmx_pciercx_cfg034_s cn52xxp1;
         struct cvmx_pciercx_cfg034_s cn56xx;
         struct cvmx_pciercx_cfg034_s cn56xxp1;
+        struct cvmx_pciercx_cfg034_s cn61xx;
         struct cvmx_pciercx_cfg034_s cn63xx;
         struct cvmx_pciercx_cfg034_s cn63xxp1;
+        struct cvmx_pciercx_cfg034_s cn66xx;
+        struct cvmx_pciercx_cfg034_s cn68xx;
+        struct cvmx_pciercx_cfg034_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg035 {
@@ -696,8 +834,12 @@ union cvmx_pciercx_cfg035 {
         struct cvmx_pciercx_cfg035_s cn52xxp1;
         struct cvmx_pciercx_cfg035_s cn56xx;
         struct cvmx_pciercx_cfg035_s cn56xxp1;
+        struct cvmx_pciercx_cfg035_s cn61xx;
         struct cvmx_pciercx_cfg035_s cn63xx;
         struct cvmx_pciercx_cfg035_s cn63xxp1;
+        struct cvmx_pciercx_cfg035_s cn66xx;
+        struct cvmx_pciercx_cfg035_s cn68xx;
+        struct cvmx_pciercx_cfg035_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg036 {
@@ -712,38 +854,95 @@ union cvmx_pciercx_cfg036 {
         struct cvmx_pciercx_cfg036_s cn52xxp1;
         struct cvmx_pciercx_cfg036_s cn56xx;
         struct cvmx_pciercx_cfg036_s cn56xxp1;
+        struct cvmx_pciercx_cfg036_s cn61xx;
         struct cvmx_pciercx_cfg036_s cn63xx;
         struct cvmx_pciercx_cfg036_s cn63xxp1;
+        struct cvmx_pciercx_cfg036_s cn66xx;
+        struct cvmx_pciercx_cfg036_s cn68xx;
+        struct cvmx_pciercx_cfg036_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg037 {
         uint32_t u32;
         struct cvmx_pciercx_cfg037_s {
-                uint32_t reserved_5_31:27;
+                uint32_t reserved_14_31:18;
+                uint32_t tph:2;
+                uint32_t reserved_11_11:1;
+                uint32_t noroprpr:1;
+                uint32_t atom128s:1;
+                uint32_t atom64s:1;
+                uint32_t atom32s:1;
+                uint32_t atom_ops:1;
+                uint32_t reserved_5_5:1;
                 uint32_t ctds:1;
                 uint32_t ctrs:4;
         } s;
-        struct cvmx_pciercx_cfg037_s cn52xx;
-        struct cvmx_pciercx_cfg037_s cn52xxp1;
-        struct cvmx_pciercx_cfg037_s cn56xx;
-        struct cvmx_pciercx_cfg037_s cn56xxp1;
-        struct cvmx_pciercx_cfg037_s cn63xx;
-        struct cvmx_pciercx_cfg037_s cn63xxp1;
+        struct cvmx_pciercx_cfg037_cn52xx {
+                uint32_t reserved_5_31:27;
+                uint32_t ctds:1;
+                uint32_t ctrs:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg037_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg037_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg037_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg037_cn61xx {
+                uint32_t reserved_14_31:18;
+                uint32_t tph:2;
+                uint32_t reserved_11_11:1;
+                uint32_t noroprpr:1;
+                uint32_t atom128s:1;
+                uint32_t atom64s:1;
+                uint32_t atom32s:1;
+                uint32_t atom_ops:1;
+                uint32_t ari_fw:1;
+                uint32_t ctds:1;
+                uint32_t ctrs:4;
+        } cn61xx;
+        struct cvmx_pciercx_cfg037_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg037_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg037_cn66xx {
+                uint32_t reserved_14_31:18;
+                uint32_t tph:2;
+                uint32_t reserved_11_11:1;
+                uint32_t noroprpr:1;
+                uint32_t atom128s:1;
+                uint32_t atom64s:1;
+                uint32_t atom32s:1;
+                uint32_t atom_ops:1;
+                uint32_t ari:1;
+                uint32_t ctds:1;
+                uint32_t ctrs:4;
+        } cn66xx;
+        struct cvmx_pciercx_cfg037_cn66xx cn68xx;
+        struct cvmx_pciercx_cfg037_cn66xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg038 {
         uint32_t u32;
         struct cvmx_pciercx_cfg038_s {
-                uint32_t reserved_5_31:27;
+                uint32_t reserved_10_31:22;
+                uint32_t id0_cp:1;
+                uint32_t id0_rq:1;
+                uint32_t atom_op_eb:1;
+                uint32_t atom_op:1;
+                uint32_t ari:1;
                 uint32_t ctd:1;
                 uint32_t ctv:4;
         } s;
-        struct cvmx_pciercx_cfg038_s cn52xx;
-        struct cvmx_pciercx_cfg038_s cn52xxp1;
-        struct cvmx_pciercx_cfg038_s cn56xx;
-        struct cvmx_pciercx_cfg038_s cn56xxp1;
-        struct cvmx_pciercx_cfg038_s cn63xx;
-        struct cvmx_pciercx_cfg038_s cn63xxp1;
+        struct cvmx_pciercx_cfg038_cn52xx {
+                uint32_t reserved_5_31:27;
+                uint32_t ctd:1;
+                uint32_t ctv:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg038_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg038_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg038_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg038_s cn61xx;
+        struct cvmx_pciercx_cfg038_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg038_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg038_s cn66xx;
+        struct cvmx_pciercx_cfg038_s cn68xx;
+        struct cvmx_pciercx_cfg038_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg039 {
@@ -760,8 +959,12 @@ union cvmx_pciercx_cfg039 {
         struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
         struct cvmx_pciercx_cfg039_cn52xx cn56xx;
         struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg039_s cn61xx;
         struct cvmx_pciercx_cfg039_s cn63xx;
         struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg039_s cn66xx;
+        struct cvmx_pciercx_cfg039_s cn68xx;
+        struct cvmx_pciercx_cfg039_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg040 {
@@ -785,8 +988,12 @@ union cvmx_pciercx_cfg040 {
         struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
         struct cvmx_pciercx_cfg040_cn52xx cn56xx;
         struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg040_s cn61xx;
         struct cvmx_pciercx_cfg040_s cn63xx;
         struct cvmx_pciercx_cfg040_s cn63xxp1;
+        struct cvmx_pciercx_cfg040_s cn66xx;
+        struct cvmx_pciercx_cfg040_s cn68xx;
+        struct cvmx_pciercx_cfg040_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg041 {
@@ -798,8 +1005,12 @@ union cvmx_pciercx_cfg041 {
         struct cvmx_pciercx_cfg041_s cn52xxp1;
         struct cvmx_pciercx_cfg041_s cn56xx;
         struct cvmx_pciercx_cfg041_s cn56xxp1;
+        struct cvmx_pciercx_cfg041_s cn61xx;
         struct cvmx_pciercx_cfg041_s cn63xx;
         struct cvmx_pciercx_cfg041_s cn63xxp1;
+        struct cvmx_pciercx_cfg041_s cn66xx;
+        struct cvmx_pciercx_cfg041_s cn68xx;
+        struct cvmx_pciercx_cfg041_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg042 {
@@ -811,8 +1022,12 @@ union cvmx_pciercx_cfg042 {
         struct cvmx_pciercx_cfg042_s cn52xxp1;
         struct cvmx_pciercx_cfg042_s cn56xx;
         struct cvmx_pciercx_cfg042_s cn56xxp1;
+        struct cvmx_pciercx_cfg042_s cn61xx;
         struct cvmx_pciercx_cfg042_s cn63xx;
         struct cvmx_pciercx_cfg042_s cn63xxp1;
+        struct cvmx_pciercx_cfg042_s cn66xx;
+        struct cvmx_pciercx_cfg042_s cn68xx;
+        struct cvmx_pciercx_cfg042_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg064 {
@@ -826,14 +1041,20 @@ union cvmx_pciercx_cfg064 {
         struct cvmx_pciercx_cfg064_s cn52xxp1;
         struct cvmx_pciercx_cfg064_s cn56xx;
         struct cvmx_pciercx_cfg064_s cn56xxp1;
+        struct cvmx_pciercx_cfg064_s cn61xx;
         struct cvmx_pciercx_cfg064_s cn63xx;
         struct cvmx_pciercx_cfg064_s cn63xxp1;
+        struct cvmx_pciercx_cfg064_s cn66xx;
+        struct cvmx_pciercx_cfg064_s cn68xx;
+        struct cvmx_pciercx_cfg064_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg065 {
         uint32_t u32;
         struct cvmx_pciercx_cfg065_s {
-                uint32_t reserved_21_31:11;
+                uint32_t reserved_25_31:7;
+                uint32_t uatombs:1;
+                uint32_t reserved_21_23:3;
                 uint32_t ures:1;
                 uint32_t ecrces:1;
                 uint32_t mtlps:1;
@@ -848,18 +1069,39 @@ union cvmx_pciercx_cfg065 {
                 uint32_t dlpes:1;
                 uint32_t reserved_0_3:4;
         } s;
-        struct cvmx_pciercx_cfg065_s cn52xx;
-        struct cvmx_pciercx_cfg065_s cn52xxp1;
-        struct cvmx_pciercx_cfg065_s cn56xx;
-        struct cvmx_pciercx_cfg065_s cn56xxp1;
-        struct cvmx_pciercx_cfg065_s cn63xx;
-        struct cvmx_pciercx_cfg065_s cn63xxp1;
+        struct cvmx_pciercx_cfg065_cn52xx {
+                uint32_t reserved_21_31:11;
+                uint32_t ures:1;
+                uint32_t ecrces:1;
+                uint32_t mtlps:1;
+                uint32_t ros:1;
+                uint32_t ucs:1;
+                uint32_t cas:1;
+                uint32_t cts:1;
+                uint32_t fcpes:1;
+                uint32_t ptlps:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdes:1;
+                uint32_t dlpes:1;
+                uint32_t reserved_0_3:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg065_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg065_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg065_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg065_s cn61xx;
+        struct cvmx_pciercx_cfg065_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg065_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg065_s cn66xx;
+        struct cvmx_pciercx_cfg065_s cn68xx;
+        struct cvmx_pciercx_cfg065_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg066 {
         uint32_t u32;
         struct cvmx_pciercx_cfg066_s {
-                uint32_t reserved_21_31:11;
+                uint32_t reserved_25_31:7;
+                uint32_t uatombm:1;
+                uint32_t reserved_21_23:3;
                 uint32_t urem:1;
                 uint32_t ecrcem:1;
                 uint32_t mtlpm:1;
@@ -874,18 +1116,39 @@ union cvmx_pciercx_cfg066 {
                 uint32_t dlpem:1;
                 uint32_t reserved_0_3:4;
         } s;
-        struct cvmx_pciercx_cfg066_s cn52xx;
-        struct cvmx_pciercx_cfg066_s cn52xxp1;
-        struct cvmx_pciercx_cfg066_s cn56xx;
-        struct cvmx_pciercx_cfg066_s cn56xxp1;
-        struct cvmx_pciercx_cfg066_s cn63xx;
-        struct cvmx_pciercx_cfg066_s cn63xxp1;
+        struct cvmx_pciercx_cfg066_cn52xx {
+                uint32_t reserved_21_31:11;
+                uint32_t urem:1;
+                uint32_t ecrcem:1;
+                uint32_t mtlpm:1;
+                uint32_t rom:1;
+                uint32_t ucm:1;
+                uint32_t cam:1;
+                uint32_t ctm:1;
+                uint32_t fcpem:1;
+                uint32_t ptlpm:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdem:1;
+                uint32_t dlpem:1;
+                uint32_t reserved_0_3:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg066_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg066_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg066_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg066_s cn61xx;
+        struct cvmx_pciercx_cfg066_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg066_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg066_s cn66xx;
+        struct cvmx_pciercx_cfg066_s cn68xx;
+        struct cvmx_pciercx_cfg066_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg067 {
         uint32_t u32;
         struct cvmx_pciercx_cfg067_s {
-                uint32_t reserved_21_31:11;
+                uint32_t reserved_25_31:7;
+                uint32_t uatombs:1;
+                uint32_t reserved_21_23:3;
                 uint32_t ures:1;
                 uint32_t ecrces:1;
                 uint32_t mtlps:1;
@@ -900,12 +1163,31 @@ union cvmx_pciercx_cfg067 {
                 uint32_t dlpes:1;
                 uint32_t reserved_0_3:4;
         } s;
-        struct cvmx_pciercx_cfg067_s cn52xx;
-        struct cvmx_pciercx_cfg067_s cn52xxp1;
-        struct cvmx_pciercx_cfg067_s cn56xx;
-        struct cvmx_pciercx_cfg067_s cn56xxp1;
-        struct cvmx_pciercx_cfg067_s cn63xx;
-        struct cvmx_pciercx_cfg067_s cn63xxp1;
+        struct cvmx_pciercx_cfg067_cn52xx {
+                uint32_t reserved_21_31:11;
+                uint32_t ures:1;
+                uint32_t ecrces:1;
+                uint32_t mtlps:1;
+                uint32_t ros:1;
+                uint32_t ucs:1;
+                uint32_t cas:1;
+                uint32_t cts:1;
+                uint32_t fcpes:1;
+                uint32_t ptlps:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdes:1;
+                uint32_t dlpes:1;
+                uint32_t reserved_0_3:4;
+        } cn52xx;
+        struct cvmx_pciercx_cfg067_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg067_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg067_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg067_s cn61xx;
+        struct cvmx_pciercx_cfg067_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg067_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg067_s cn66xx;
+        struct cvmx_pciercx_cfg067_s cn68xx;
+        struct cvmx_pciercx_cfg067_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg068 {
@@ -925,8 +1207,12 @@ union cvmx_pciercx_cfg068 {
         struct cvmx_pciercx_cfg068_s cn52xxp1;
         struct cvmx_pciercx_cfg068_s cn56xx;
         struct cvmx_pciercx_cfg068_s cn56xxp1;
+        struct cvmx_pciercx_cfg068_s cn61xx;
         struct cvmx_pciercx_cfg068_s cn63xx;
         struct cvmx_pciercx_cfg068_s cn63xxp1;
+        struct cvmx_pciercx_cfg068_s cn66xx;
+        struct cvmx_pciercx_cfg068_s cn68xx;
+        struct cvmx_pciercx_cfg068_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg069 {
@@ -946,8 +1232,12 @@ union cvmx_pciercx_cfg069 {
         struct cvmx_pciercx_cfg069_s cn52xxp1;
         struct cvmx_pciercx_cfg069_s cn56xx;
         struct cvmx_pciercx_cfg069_s cn56xxp1;
+        struct cvmx_pciercx_cfg069_s cn61xx;
         struct cvmx_pciercx_cfg069_s cn63xx;
         struct cvmx_pciercx_cfg069_s cn63xxp1;
+        struct cvmx_pciercx_cfg069_s cn66xx;
+        struct cvmx_pciercx_cfg069_s cn68xx;
+        struct cvmx_pciercx_cfg069_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg070 {
@@ -964,8 +1254,12 @@ union cvmx_pciercx_cfg070 {
         struct cvmx_pciercx_cfg070_s cn52xxp1;
         struct cvmx_pciercx_cfg070_s cn56xx;
         struct cvmx_pciercx_cfg070_s cn56xxp1;
+        struct cvmx_pciercx_cfg070_s cn61xx;
         struct cvmx_pciercx_cfg070_s cn63xx;
         struct cvmx_pciercx_cfg070_s cn63xxp1;
+        struct cvmx_pciercx_cfg070_s cn66xx;
+        struct cvmx_pciercx_cfg070_s cn68xx;
+        struct cvmx_pciercx_cfg070_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg071 {
@@ -977,8 +1271,12 @@ union cvmx_pciercx_cfg071 {
         struct cvmx_pciercx_cfg071_s cn52xxp1;
         struct cvmx_pciercx_cfg071_s cn56xx;
         struct cvmx_pciercx_cfg071_s cn56xxp1;
+        struct cvmx_pciercx_cfg071_s cn61xx;
         struct cvmx_pciercx_cfg071_s cn63xx;
         struct cvmx_pciercx_cfg071_s cn63xxp1;
+        struct cvmx_pciercx_cfg071_s cn66xx;
+        struct cvmx_pciercx_cfg071_s cn68xx;
+        struct cvmx_pciercx_cfg071_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg072 {
@@ -990,8 +1288,12 @@ union cvmx_pciercx_cfg072 {
         struct cvmx_pciercx_cfg072_s cn52xxp1;
         struct cvmx_pciercx_cfg072_s cn56xx;
         struct cvmx_pciercx_cfg072_s cn56xxp1;
+        struct cvmx_pciercx_cfg072_s cn61xx;
         struct cvmx_pciercx_cfg072_s cn63xx;
         struct cvmx_pciercx_cfg072_s cn63xxp1;
+        struct cvmx_pciercx_cfg072_s cn66xx;
+        struct cvmx_pciercx_cfg072_s cn68xx;
+        struct cvmx_pciercx_cfg072_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg073 {
@@ -1003,8 +1305,12 @@ union cvmx_pciercx_cfg073 {
         struct cvmx_pciercx_cfg073_s cn52xxp1;
         struct cvmx_pciercx_cfg073_s cn56xx;
         struct cvmx_pciercx_cfg073_s cn56xxp1;
+        struct cvmx_pciercx_cfg073_s cn61xx;
         struct cvmx_pciercx_cfg073_s cn63xx;
         struct cvmx_pciercx_cfg073_s cn63xxp1;
+        struct cvmx_pciercx_cfg073_s cn66xx;
+        struct cvmx_pciercx_cfg073_s cn68xx;
+        struct cvmx_pciercx_cfg073_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg074 {
@@ -1016,8 +1322,12 @@ union cvmx_pciercx_cfg074 {
         struct cvmx_pciercx_cfg074_s cn52xxp1;
         struct cvmx_pciercx_cfg074_s cn56xx;
         struct cvmx_pciercx_cfg074_s cn56xxp1;
+        struct cvmx_pciercx_cfg074_s cn61xx;
         struct cvmx_pciercx_cfg074_s cn63xx;
         struct cvmx_pciercx_cfg074_s cn63xxp1;
+        struct cvmx_pciercx_cfg074_s cn66xx;
+        struct cvmx_pciercx_cfg074_s cn68xx;
+        struct cvmx_pciercx_cfg074_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg075 {
@@ -1032,8 +1342,12 @@ union cvmx_pciercx_cfg075 {
         struct cvmx_pciercx_cfg075_s cn52xxp1;
         struct cvmx_pciercx_cfg075_s cn56xx;
         struct cvmx_pciercx_cfg075_s cn56xxp1;
+        struct cvmx_pciercx_cfg075_s cn61xx;
         struct cvmx_pciercx_cfg075_s cn63xx;
         struct cvmx_pciercx_cfg075_s cn63xxp1;
+        struct cvmx_pciercx_cfg075_s cn66xx;
+        struct cvmx_pciercx_cfg075_s cn68xx;
+        struct cvmx_pciercx_cfg075_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg076 {
@@ -1053,8 +1367,12 @@ union cvmx_pciercx_cfg076 {
         struct cvmx_pciercx_cfg076_s cn52xxp1;
         struct cvmx_pciercx_cfg076_s cn56xx;
         struct cvmx_pciercx_cfg076_s cn56xxp1;
+        struct cvmx_pciercx_cfg076_s cn61xx;
         struct cvmx_pciercx_cfg076_s cn63xx;
         struct cvmx_pciercx_cfg076_s cn63xxp1;
+        struct cvmx_pciercx_cfg076_s cn66xx;
+        struct cvmx_pciercx_cfg076_s cn68xx;
+        struct cvmx_pciercx_cfg076_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg077 {
@@ -1067,8 +1385,12 @@ union cvmx_pciercx_cfg077 {
         struct cvmx_pciercx_cfg077_s cn52xxp1;
         struct cvmx_pciercx_cfg077_s cn56xx;
         struct cvmx_pciercx_cfg077_s cn56xxp1;
+        struct cvmx_pciercx_cfg077_s cn61xx;
         struct cvmx_pciercx_cfg077_s cn63xx;
         struct cvmx_pciercx_cfg077_s cn63xxp1;
+        struct cvmx_pciercx_cfg077_s cn66xx;
+        struct cvmx_pciercx_cfg077_s cn68xx;
+        struct cvmx_pciercx_cfg077_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg448 {
@@ -1081,8 +1403,12 @@ union cvmx_pciercx_cfg448 {
         struct cvmx_pciercx_cfg448_s cn52xxp1;
         struct cvmx_pciercx_cfg448_s cn56xx;
         struct cvmx_pciercx_cfg448_s cn56xxp1;
+        struct cvmx_pciercx_cfg448_s cn61xx;
         struct cvmx_pciercx_cfg448_s cn63xx;
         struct cvmx_pciercx_cfg448_s cn63xxp1;
+        struct cvmx_pciercx_cfg448_s cn66xx;
+        struct cvmx_pciercx_cfg448_s cn68xx;
+        struct cvmx_pciercx_cfg448_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg449 {
@@ -1094,8 +1420,12 @@ union cvmx_pciercx_cfg449 {
         struct cvmx_pciercx_cfg449_s cn52xxp1;
         struct cvmx_pciercx_cfg449_s cn56xx;
         struct cvmx_pciercx_cfg449_s cn56xxp1;
+        struct cvmx_pciercx_cfg449_s cn61xx;
         struct cvmx_pciercx_cfg449_s cn63xx;
         struct cvmx_pciercx_cfg449_s cn63xxp1;
+        struct cvmx_pciercx_cfg449_s cn66xx;
+        struct cvmx_pciercx_cfg449_s cn68xx;
+        struct cvmx_pciercx_cfg449_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg450 {
@@ -1112,26 +1442,42 @@ union cvmx_pciercx_cfg450 {
         struct cvmx_pciercx_cfg450_s cn52xxp1;
         struct cvmx_pciercx_cfg450_s cn56xx;
         struct cvmx_pciercx_cfg450_s cn56xxp1;
+        struct cvmx_pciercx_cfg450_s cn61xx;
         struct cvmx_pciercx_cfg450_s cn63xx;
         struct cvmx_pciercx_cfg450_s cn63xxp1;
+        struct cvmx_pciercx_cfg450_s cn66xx;
+        struct cvmx_pciercx_cfg450_s cn68xx;
+        struct cvmx_pciercx_cfg450_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg451 {
         uint32_t u32;
         struct cvmx_pciercx_cfg451_s {
-                uint32_t reserved_30_31:2;
+                uint32_t reserved_31_31:1;
+                uint32_t easpml1:1;
                 uint32_t l1el:3;
                 uint32_t l0el:3;
                 uint32_t n_fts_cc:8;
                 uint32_t n_fts:8;
                 uint32_t ack_freq:8;
         } s;
-        struct cvmx_pciercx_cfg451_s cn52xx;
-        struct cvmx_pciercx_cfg451_s cn52xxp1;
-        struct cvmx_pciercx_cfg451_s cn56xx;
-        struct cvmx_pciercx_cfg451_s cn56xxp1;
-        struct cvmx_pciercx_cfg451_s cn63xx;
-        struct cvmx_pciercx_cfg451_s cn63xxp1;
+        struct cvmx_pciercx_cfg451_cn52xx {
+                uint32_t reserved_30_31:2;
+                uint32_t l1el:3;
+                uint32_t l0el:3;
+                uint32_t n_fts_cc:8;
+                uint32_t n_fts:8;
+                uint32_t ack_freq:8;
+        } cn52xx;
+        struct cvmx_pciercx_cfg451_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg451_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg451_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg451_s cn61xx;
+        struct cvmx_pciercx_cfg451_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg451_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg451_s cn66xx;
+        struct cvmx_pciercx_cfg451_s cn68xx;
+        struct cvmx_pciercx_cfg451_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg452 {
@@ -1155,8 +1501,24 @@ union cvmx_pciercx_cfg452 {
         struct cvmx_pciercx_cfg452_s cn52xxp1;
         struct cvmx_pciercx_cfg452_s cn56xx;
         struct cvmx_pciercx_cfg452_s cn56xxp1;
+        struct cvmx_pciercx_cfg452_cn61xx {
+                uint32_t reserved_22_31:10;
+                uint32_t lme:6;
+                uint32_t reserved_8_15:8;
+                uint32_t flm:1;
+                uint32_t reserved_6_6:1;
+                uint32_t dllle:1;
+                uint32_t reserved_4_4:1;
+                uint32_t ra:1;
+                uint32_t le:1;
+                uint32_t sd:1;
+                uint32_t omr:1;
+        } cn61xx;
         struct cvmx_pciercx_cfg452_s cn63xx;
         struct cvmx_pciercx_cfg452_s cn63xxp1;
+        struct cvmx_pciercx_cfg452_cn61xx cn66xx;
+        struct cvmx_pciercx_cfg452_cn61xx cn68xx;
+        struct cvmx_pciercx_cfg452_cn61xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg453 {
@@ -1172,13 +1534,26 @@ union cvmx_pciercx_cfg453 {
         struct cvmx_pciercx_cfg453_s cn52xxp1;
         struct cvmx_pciercx_cfg453_s cn56xx;
         struct cvmx_pciercx_cfg453_s cn56xxp1;
+        struct cvmx_pciercx_cfg453_s cn61xx;
         struct cvmx_pciercx_cfg453_s cn63xx;
         struct cvmx_pciercx_cfg453_s cn63xxp1;
+        struct cvmx_pciercx_cfg453_s cn66xx;
+        struct cvmx_pciercx_cfg453_s cn68xx;
+        struct cvmx_pciercx_cfg453_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg454 {
         uint32_t u32;
         struct cvmx_pciercx_cfg454_s {
+                uint32_t cx_nfunc:3;
+                uint32_t tmfcwt:5;
+                uint32_t tmanlt:5;
+                uint32_t tmrt:5;
+                uint32_t reserved_11_13:3;
+                uint32_t nskps:3;
+                uint32_t reserved_0_7:8;
+        } s;
+        struct cvmx_pciercx_cfg454_cn52xx {
                 uint32_t reserved_29_31:3;
                 uint32_t tmfcwt:5;
                 uint32_t tmanlt:5;
@@ -1187,13 +1562,23 @@ union cvmx_pciercx_cfg454 {
                 uint32_t nskps:3;
                 uint32_t reserved_4_7:4;
                 uint32_t ntss:4;
-        } s;
-        struct cvmx_pciercx_cfg454_s cn52xx;
-        struct cvmx_pciercx_cfg454_s cn52xxp1;
-        struct cvmx_pciercx_cfg454_s cn56xx;
-        struct cvmx_pciercx_cfg454_s cn56xxp1;
-        struct cvmx_pciercx_cfg454_s cn63xx;
-        struct cvmx_pciercx_cfg454_s cn63xxp1;
+        } cn52xx;
+        struct cvmx_pciercx_cfg454_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg454_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg454_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg454_cn61xx {
+                uint32_t cx_nfunc:3;
+                uint32_t tmfcwt:5;
+                uint32_t tmanlt:5;
+                uint32_t tmrt:5;
+                uint32_t reserved_8_13:6;
+                uint32_t mfuncn:8;
+        } cn61xx;
+        struct cvmx_pciercx_cfg454_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg454_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg454_cn61xx cn66xx;
+        struct cvmx_pciercx_cfg454_cn61xx cn68xx;
+        struct cvmx_pciercx_cfg454_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg455 {
@@ -1223,23 +1608,37 @@ union cvmx_pciercx_cfg455 {
         struct cvmx_pciercx_cfg455_s cn52xxp1;
         struct cvmx_pciercx_cfg455_s cn56xx;
         struct cvmx_pciercx_cfg455_s cn56xxp1;
+        struct cvmx_pciercx_cfg455_s cn61xx;
         struct cvmx_pciercx_cfg455_s cn63xx;
         struct cvmx_pciercx_cfg455_s cn63xxp1;
+        struct cvmx_pciercx_cfg455_s cn66xx;
+        struct cvmx_pciercx_cfg455_s cn68xx;
+        struct cvmx_pciercx_cfg455_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg456 {
         uint32_t u32;
         struct cvmx_pciercx_cfg456_s {
-                uint32_t reserved_2_31:30;
+                uint32_t reserved_4_31:28;
+                uint32_t m_handle_flush:1;
+                uint32_t m_dabort_4ucpl:1;
                 uint32_t m_vend1_drp:1;
                 uint32_t m_vend0_drp:1;
         } s;
-        struct cvmx_pciercx_cfg456_s cn52xx;
-        struct cvmx_pciercx_cfg456_s cn52xxp1;
-        struct cvmx_pciercx_cfg456_s cn56xx;
-        struct cvmx_pciercx_cfg456_s cn56xxp1;
-        struct cvmx_pciercx_cfg456_s cn63xx;
-        struct cvmx_pciercx_cfg456_s cn63xxp1;
+        struct cvmx_pciercx_cfg456_cn52xx {
+                uint32_t reserved_2_31:30;
+                uint32_t m_vend1_drp:1;
+                uint32_t m_vend0_drp:1;
+        } cn52xx;
+        struct cvmx_pciercx_cfg456_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg456_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg456_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg456_s cn61xx;
+        struct cvmx_pciercx_cfg456_cn52xx cn63xx;
+        struct cvmx_pciercx_cfg456_cn52xx cn63xxp1;
+        struct cvmx_pciercx_cfg456_s cn66xx;
+        struct cvmx_pciercx_cfg456_s cn68xx;
+        struct cvmx_pciercx_cfg456_cn52xx cn68xxp1;
 };
 
 union cvmx_pciercx_cfg458 {
@@ -1251,8 +1650,12 @@ union cvmx_pciercx_cfg458 {
         struct cvmx_pciercx_cfg458_s cn52xxp1;
         struct cvmx_pciercx_cfg458_s cn56xx;
         struct cvmx_pciercx_cfg458_s cn56xxp1;
+        struct cvmx_pciercx_cfg458_s cn61xx;
         struct cvmx_pciercx_cfg458_s cn63xx;
         struct cvmx_pciercx_cfg458_s cn63xxp1;
+        struct cvmx_pciercx_cfg458_s cn66xx;
+        struct cvmx_pciercx_cfg458_s cn68xx;
+        struct cvmx_pciercx_cfg458_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg459 {
@@ -1264,8 +1667,12 @@ union cvmx_pciercx_cfg459 {
         struct cvmx_pciercx_cfg459_s cn52xxp1;
         struct cvmx_pciercx_cfg459_s cn56xx;
         struct cvmx_pciercx_cfg459_s cn56xxp1;
+        struct cvmx_pciercx_cfg459_s cn61xx;
         struct cvmx_pciercx_cfg459_s cn63xx;
         struct cvmx_pciercx_cfg459_s cn63xxp1;
+        struct cvmx_pciercx_cfg459_s cn66xx;
+        struct cvmx_pciercx_cfg459_s cn68xx;
+        struct cvmx_pciercx_cfg459_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg460 {
@@ -1279,8 +1686,12 @@ union cvmx_pciercx_cfg460 {
         struct cvmx_pciercx_cfg460_s cn52xxp1;
         struct cvmx_pciercx_cfg460_s cn56xx;
         struct cvmx_pciercx_cfg460_s cn56xxp1;
+        struct cvmx_pciercx_cfg460_s cn61xx;
         struct cvmx_pciercx_cfg460_s cn63xx;
         struct cvmx_pciercx_cfg460_s cn63xxp1;
+        struct cvmx_pciercx_cfg460_s cn66xx;
+        struct cvmx_pciercx_cfg460_s cn68xx;
+        struct cvmx_pciercx_cfg460_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg461 {
@@ -1294,8 +1705,12 @@ union cvmx_pciercx_cfg461 {
         struct cvmx_pciercx_cfg461_s cn52xxp1;
         struct cvmx_pciercx_cfg461_s cn56xx;
         struct cvmx_pciercx_cfg461_s cn56xxp1;
+        struct cvmx_pciercx_cfg461_s cn61xx;
         struct cvmx_pciercx_cfg461_s cn63xx;
         struct cvmx_pciercx_cfg461_s cn63xxp1;
+        struct cvmx_pciercx_cfg461_s cn66xx;
+        struct cvmx_pciercx_cfg461_s cn68xx;
+        struct cvmx_pciercx_cfg461_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg462 {
@@ -1309,8 +1724,12 @@ union cvmx_pciercx_cfg462 {
         struct cvmx_pciercx_cfg462_s cn52xxp1;
         struct cvmx_pciercx_cfg462_s cn56xx;
         struct cvmx_pciercx_cfg462_s cn56xxp1;
+        struct cvmx_pciercx_cfg462_s cn61xx;
         struct cvmx_pciercx_cfg462_s cn63xx;
         struct cvmx_pciercx_cfg462_s cn63xxp1;
+        struct cvmx_pciercx_cfg462_s cn66xx;
+        struct cvmx_pciercx_cfg462_s cn68xx;
+        struct cvmx_pciercx_cfg462_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg463 {
@@ -1325,8 +1744,12 @@ union cvmx_pciercx_cfg463 {
         struct cvmx_pciercx_cfg463_s cn52xxp1;
         struct cvmx_pciercx_cfg463_s cn56xx;
         struct cvmx_pciercx_cfg463_s cn56xxp1;
+        struct cvmx_pciercx_cfg463_s cn61xx;
         struct cvmx_pciercx_cfg463_s cn63xx;
         struct cvmx_pciercx_cfg463_s cn63xxp1;
+        struct cvmx_pciercx_cfg463_s cn66xx;
+        struct cvmx_pciercx_cfg463_s cn68xx;
+        struct cvmx_pciercx_cfg463_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg464 {
@@ -1341,8 +1764,12 @@ union cvmx_pciercx_cfg464 {
         struct cvmx_pciercx_cfg464_s cn52xxp1;
         struct cvmx_pciercx_cfg464_s cn56xx;
         struct cvmx_pciercx_cfg464_s cn56xxp1;
+        struct cvmx_pciercx_cfg464_s cn61xx;
         struct cvmx_pciercx_cfg464_s cn63xx;
         struct cvmx_pciercx_cfg464_s cn63xxp1;
+        struct cvmx_pciercx_cfg464_s cn66xx;
+        struct cvmx_pciercx_cfg464_s cn68xx;
+        struct cvmx_pciercx_cfg464_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg465 {
@@ -1357,8 +1784,12 @@ union cvmx_pciercx_cfg465 {
         struct cvmx_pciercx_cfg465_s cn52xxp1;
         struct cvmx_pciercx_cfg465_s cn56xx;
         struct cvmx_pciercx_cfg465_s cn56xxp1;
+        struct cvmx_pciercx_cfg465_s cn61xx;
         struct cvmx_pciercx_cfg465_s cn63xx;
         struct cvmx_pciercx_cfg465_s cn63xxp1;
+        struct cvmx_pciercx_cfg465_s cn66xx;
+        struct cvmx_pciercx_cfg465_s cn68xx;
+        struct cvmx_pciercx_cfg465_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg466 {
@@ -1376,8 +1807,12 @@ union cvmx_pciercx_cfg466 {
         struct cvmx_pciercx_cfg466_s cn52xxp1;
         struct cvmx_pciercx_cfg466_s cn56xx;
         struct cvmx_pciercx_cfg466_s cn56xxp1;
+        struct cvmx_pciercx_cfg466_s cn61xx;
         struct cvmx_pciercx_cfg466_s cn63xx;
         struct cvmx_pciercx_cfg466_s cn63xxp1;
+        struct cvmx_pciercx_cfg466_s cn66xx;
+        struct cvmx_pciercx_cfg466_s cn68xx;
+        struct cvmx_pciercx_cfg466_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg467 {
@@ -1393,8 +1828,12 @@ union cvmx_pciercx_cfg467 {
         struct cvmx_pciercx_cfg467_s cn52xxp1;
         struct cvmx_pciercx_cfg467_s cn56xx;
         struct cvmx_pciercx_cfg467_s cn56xxp1;
+        struct cvmx_pciercx_cfg467_s cn61xx;
         struct cvmx_pciercx_cfg467_s cn63xx;
         struct cvmx_pciercx_cfg467_s cn63xxp1;
+        struct cvmx_pciercx_cfg467_s cn66xx;
+        struct cvmx_pciercx_cfg467_s cn68xx;
+        struct cvmx_pciercx_cfg467_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg468 {
@@ -1410,8 +1849,12 @@ union cvmx_pciercx_cfg468 {
         struct cvmx_pciercx_cfg468_s cn52xxp1;
         struct cvmx_pciercx_cfg468_s cn56xx;
         struct cvmx_pciercx_cfg468_s cn56xxp1;
+        struct cvmx_pciercx_cfg468_s cn61xx;
         struct cvmx_pciercx_cfg468_s cn63xx;
         struct cvmx_pciercx_cfg468_s cn63xxp1;
+        struct cvmx_pciercx_cfg468_s cn66xx;
+        struct cvmx_pciercx_cfg468_s cn68xx;
+        struct cvmx_pciercx_cfg468_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg490 {
@@ -1426,8 +1869,12 @@ union cvmx_pciercx_cfg490 {
         struct cvmx_pciercx_cfg490_s cn52xxp1;
         struct cvmx_pciercx_cfg490_s cn56xx;
         struct cvmx_pciercx_cfg490_s cn56xxp1;
+        struct cvmx_pciercx_cfg490_s cn61xx;
         struct cvmx_pciercx_cfg490_s cn63xx;
         struct cvmx_pciercx_cfg490_s cn63xxp1;
+        struct cvmx_pciercx_cfg490_s cn66xx;
+        struct cvmx_pciercx_cfg490_s cn68xx;
+        struct cvmx_pciercx_cfg490_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg491 {
@@ -1442,8 +1889,12 @@ union cvmx_pciercx_cfg491 {
         struct cvmx_pciercx_cfg491_s cn52xxp1;
         struct cvmx_pciercx_cfg491_s cn56xx;
         struct cvmx_pciercx_cfg491_s cn56xxp1;
+        struct cvmx_pciercx_cfg491_s cn61xx;
         struct cvmx_pciercx_cfg491_s cn63xx;
         struct cvmx_pciercx_cfg491_s cn63xxp1;
+        struct cvmx_pciercx_cfg491_s cn66xx;
+        struct cvmx_pciercx_cfg491_s cn68xx;
+        struct cvmx_pciercx_cfg491_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg492 {
@@ -1458,8 +1909,12 @@ union cvmx_pciercx_cfg492 {
         struct cvmx_pciercx_cfg492_s cn52xxp1;
         struct cvmx_pciercx_cfg492_s cn56xx;
         struct cvmx_pciercx_cfg492_s cn56xxp1;
+        struct cvmx_pciercx_cfg492_s cn61xx;
         struct cvmx_pciercx_cfg492_s cn63xx;
         struct cvmx_pciercx_cfg492_s cn63xxp1;
+        struct cvmx_pciercx_cfg492_s cn66xx;
+        struct cvmx_pciercx_cfg492_s cn68xx;
+        struct cvmx_pciercx_cfg492_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg515 {
@@ -1473,8 +1928,12 @@ union cvmx_pciercx_cfg515 {
                 uint32_t le:9;
                 uint32_t n_fts:8;
         } s;
+        struct cvmx_pciercx_cfg515_s cn61xx;
         struct cvmx_pciercx_cfg515_s cn63xx;
         struct cvmx_pciercx_cfg515_s cn63xxp1;
+        struct cvmx_pciercx_cfg515_s cn66xx;
+        struct cvmx_pciercx_cfg515_s cn68xx;
+        struct cvmx_pciercx_cfg515_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg516 {
@@ -1486,8 +1945,12 @@ union cvmx_pciercx_cfg516 {
         struct cvmx_pciercx_cfg516_s cn52xxp1;
         struct cvmx_pciercx_cfg516_s cn56xx;
         struct cvmx_pciercx_cfg516_s cn56xxp1;
+        struct cvmx_pciercx_cfg516_s cn61xx;
         struct cvmx_pciercx_cfg516_s cn63xx;
         struct cvmx_pciercx_cfg516_s cn63xxp1;
+        struct cvmx_pciercx_cfg516_s cn66xx;
+        struct cvmx_pciercx_cfg516_s cn68xx;
+        struct cvmx_pciercx_cfg516_s cn68xxp1;
 };
 
 union cvmx_pciercx_cfg517 {
@@ -1499,8 +1962,12 @@ union cvmx_pciercx_cfg517 {
         struct cvmx_pciercx_cfg517_s cn52xxp1;
         struct cvmx_pciercx_cfg517_s cn56xx;
         struct cvmx_pciercx_cfg517_s cn56xxp1;
+        struct cvmx_pciercx_cfg517_s cn61xx;
         struct cvmx_pciercx_cfg517_s cn63xx;
         struct cvmx_pciercx_cfg517_s cn63xxp1;
+        struct cvmx_pciercx_cfg517_s cn66xx;
+        struct cvmx_pciercx_cfg517_s cn68xx;
+        struct cvmx_pciercx_cfg517_s cn68xxp1;
 };
 
 #endif
diff --git a/drivers/staging/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
index d45952df5f5b..d45952df5f5b 100644
--- a/drivers/staging/octeon/cvmx-pcsx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
index 55d120fe8aed..55d120fe8aed 100644
--- a/drivers/staging/octeon/cvmx-pcsxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
new file mode 100644
index 000000000000..be189a2585e0
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
@@ -0,0 +1,509 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PEMX_DEFS_H__
+#define __CVMX_PEMX_DEFS_H__
+
+#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
+#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
+#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
+#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
+
+union cvmx_pemx_bar1_indexx {
+        uint64_t u64;
+        struct cvmx_pemx_bar1_indexx_s {
+                uint64_t reserved_20_63:44;
+                uint64_t addr_idx:16;
+                uint64_t ca:1;
+                uint64_t end_swp:2;
+                uint64_t addr_v:1;
+        } s;
+        struct cvmx_pemx_bar1_indexx_s cn61xx;
+        struct cvmx_pemx_bar1_indexx_s cn63xx;
+        struct cvmx_pemx_bar1_indexx_s cn63xxp1;
+        struct cvmx_pemx_bar1_indexx_s cn66xx;
+        struct cvmx_pemx_bar1_indexx_s cn68xx;
+        struct cvmx_pemx_bar1_indexx_s cn68xxp1;
+};
+
+union cvmx_pemx_bar2_mask {
+        uint64_t u64;
+        struct cvmx_pemx_bar2_mask_s {
+                uint64_t reserved_38_63:26;
+                uint64_t mask:35;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_pemx_bar2_mask_s cn61xx;
+        struct cvmx_pemx_bar2_mask_s cn66xx;
+        struct cvmx_pemx_bar2_mask_s cn68xx;
+        struct cvmx_pemx_bar2_mask_s cn68xxp1;
+};
+
+union cvmx_pemx_bar_ctl {
+        uint64_t u64;
+        struct cvmx_pemx_bar_ctl_s {
+                uint64_t reserved_7_63:57;
+                uint64_t bar1_siz:3;
+                uint64_t bar2_enb:1;
+                uint64_t bar2_esx:2;
+                uint64_t bar2_cax:1;
+        } s;
+        struct cvmx_pemx_bar_ctl_s cn61xx;
+        struct cvmx_pemx_bar_ctl_s cn63xx;
+        struct cvmx_pemx_bar_ctl_s cn63xxp1;
+        struct cvmx_pemx_bar_ctl_s cn66xx;
+        struct cvmx_pemx_bar_ctl_s cn68xx;
+        struct cvmx_pemx_bar_ctl_s cn68xxp1;
+};
+
+union cvmx_pemx_bist_status {
+        uint64_t u64;
+        struct cvmx_pemx_bist_status_s {
+                uint64_t reserved_8_63:56;
+                uint64_t retry:1;
+                uint64_t rqdata0:1;
+                uint64_t rqdata1:1;
+                uint64_t rqdata2:1;
+                uint64_t rqdata3:1;
+                uint64_t rqhdr1:1;
+                uint64_t rqhdr0:1;
+                uint64_t sot:1;
+        } s;
+        struct cvmx_pemx_bist_status_s cn61xx;
+        struct cvmx_pemx_bist_status_s cn63xx;
+        struct cvmx_pemx_bist_status_s cn63xxp1;
+        struct cvmx_pemx_bist_status_s cn66xx;
+        struct cvmx_pemx_bist_status_s cn68xx;
+        struct cvmx_pemx_bist_status_s cn68xxp1;
+};
+
+union cvmx_pemx_bist_status2 {
+        uint64_t u64;
+        struct cvmx_pemx_bist_status2_s {
+                uint64_t reserved_10_63:54;
+                uint64_t e2p_cpl:1;
+                uint64_t e2p_n:1;
+                uint64_t e2p_p:1;
+                uint64_t peai_p2e:1;
+                uint64_t pef_tpf1:1;
+                uint64_t pef_tpf0:1;
+                uint64_t pef_tnf:1;
+                uint64_t pef_tcf1:1;
+                uint64_t pef_tc0:1;
+                uint64_t ppf:1;
+        } s;
+        struct cvmx_pemx_bist_status2_s cn61xx;
+        struct cvmx_pemx_bist_status2_s cn63xx;
+        struct cvmx_pemx_bist_status2_s cn63xxp1;
+        struct cvmx_pemx_bist_status2_s cn66xx;
+        struct cvmx_pemx_bist_status2_s cn68xx;
+        struct cvmx_pemx_bist_status2_s cn68xxp1;
+};
+
+union cvmx_pemx_cfg_rd {
+        uint64_t u64;
+        struct cvmx_pemx_cfg_rd_s {
+                uint64_t data:32;
+                uint64_t addr:32;
+        } s;
+        struct cvmx_pemx_cfg_rd_s cn61xx;
+        struct cvmx_pemx_cfg_rd_s cn63xx;
+        struct cvmx_pemx_cfg_rd_s cn63xxp1;
+        struct cvmx_pemx_cfg_rd_s cn66xx;
+        struct cvmx_pemx_cfg_rd_s cn68xx;
+        struct cvmx_pemx_cfg_rd_s cn68xxp1;
+};
+
+union cvmx_pemx_cfg_wr {
+        uint64_t u64;
+        struct cvmx_pemx_cfg_wr_s {
+                uint64_t data:32;
+                uint64_t addr:32;
+        } s;
+        struct cvmx_pemx_cfg_wr_s cn61xx;
+        struct cvmx_pemx_cfg_wr_s cn63xx;
+        struct cvmx_pemx_cfg_wr_s cn63xxp1;
+        struct cvmx_pemx_cfg_wr_s cn66xx;
+        struct cvmx_pemx_cfg_wr_s cn68xx;
+        struct cvmx_pemx_cfg_wr_s cn68xxp1;
+};
+
+union cvmx_pemx_cpl_lut_valid {
+        uint64_t u64;
+        struct cvmx_pemx_cpl_lut_valid_s {
+                uint64_t reserved_32_63:32;
+                uint64_t tag:32;
+        } s;
+        struct cvmx_pemx_cpl_lut_valid_s cn61xx;
+        struct cvmx_pemx_cpl_lut_valid_s cn63xx;
+        struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
+        struct cvmx_pemx_cpl_lut_valid_s cn66xx;
+        struct cvmx_pemx_cpl_lut_valid_s cn68xx;
+        struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
+};
+
+union cvmx_pemx_ctl_status {
+        uint64_t u64;
+        struct cvmx_pemx_ctl_status_s {
+                uint64_t reserved_48_63:16;
+                uint64_t auto_sd:1;
+                uint64_t dnum:5;
+                uint64_t pbus:8;
+                uint64_t reserved_32_33:2;
+                uint64_t cfg_rtry:16;
+                uint64_t reserved_12_15:4;
+                uint64_t pm_xtoff:1;
+                uint64_t pm_xpme:1;
+                uint64_t ob_p_cmd:1;
+                uint64_t reserved_7_8:2;
+                uint64_t nf_ecrc:1;
+                uint64_t dly_one:1;
+                uint64_t lnk_enb:1;
+                uint64_t ro_ctlp:1;
+                uint64_t fast_lm:1;
+                uint64_t inv_ecrc:1;
+                uint64_t inv_lcrc:1;
+        } s;
+        struct cvmx_pemx_ctl_status_s cn61xx;
+        struct cvmx_pemx_ctl_status_s cn63xx;
+        struct cvmx_pemx_ctl_status_s cn63xxp1;
+        struct cvmx_pemx_ctl_status_s cn66xx;
+        struct cvmx_pemx_ctl_status_s cn68xx;
+        struct cvmx_pemx_ctl_status_s cn68xxp1;
+};
+
+union cvmx_pemx_dbg_info {
+        uint64_t u64;
+        struct cvmx_pemx_dbg_info_s {
+                uint64_t reserved_31_63:33;
+                uint64_t ecrc_e:1;
+                uint64_t rawwpp:1;
+                uint64_t racpp:1;
+                uint64_t ramtlp:1;
+                uint64_t rarwdns:1;
+                uint64_t caar:1;
+                uint64_t racca:1;
+                uint64_t racur:1;
+                uint64_t rauc:1;
+                uint64_t rqo:1;
+                uint64_t fcuv:1;
+                uint64_t rpe:1;
+                uint64_t fcpvwt:1;
+                uint64_t dpeoosd:1;
+                uint64_t rtwdle:1;
+                uint64_t rdwdle:1;
+                uint64_t mre:1;
+                uint64_t rte:1;
+                uint64_t acto:1;
+                uint64_t rvdm:1;
+                uint64_t rumep:1;
+                uint64_t rptamrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rfemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rcemrc:1;
+                uint64_t rpoison:1;
+                uint64_t recrce:1;
+                uint64_t rtlplle:1;
+                uint64_t rtlpmal:1;
+                uint64_t spoison:1;
+        } s;
+        struct cvmx_pemx_dbg_info_s cn61xx;
+        struct cvmx_pemx_dbg_info_s cn63xx;
+        struct cvmx_pemx_dbg_info_s cn63xxp1;
+        struct cvmx_pemx_dbg_info_s cn66xx;
+        struct cvmx_pemx_dbg_info_s cn68xx;
+        struct cvmx_pemx_dbg_info_s cn68xxp1;
+};
+
+union cvmx_pemx_dbg_info_en {
+        uint64_t u64;
+        struct cvmx_pemx_dbg_info_en_s {
+                uint64_t reserved_31_63:33;
+                uint64_t ecrc_e:1;
+                uint64_t rawwpp:1;
+                uint64_t racpp:1;
+                uint64_t ramtlp:1;
+                uint64_t rarwdns:1;
+                uint64_t caar:1;
+                uint64_t racca:1;
+                uint64_t racur:1;
+                uint64_t rauc:1;
+                uint64_t rqo:1;
+                uint64_t fcuv:1;
+                uint64_t rpe:1;
+                uint64_t fcpvwt:1;
+                uint64_t dpeoosd:1;
+                uint64_t rtwdle:1;
+                uint64_t rdwdle:1;
+                uint64_t mre:1;
+                uint64_t rte:1;
+                uint64_t acto:1;
+                uint64_t rvdm:1;
+                uint64_t rumep:1;
+                uint64_t rptamrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rfemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rcemrc:1;
+                uint64_t rpoison:1;
+                uint64_t recrce:1;
+                uint64_t rtlplle:1;
+                uint64_t rtlpmal:1;
+                uint64_t spoison:1;
+        } s;
+        struct cvmx_pemx_dbg_info_en_s cn61xx;
+        struct cvmx_pemx_dbg_info_en_s cn63xx;
+        struct cvmx_pemx_dbg_info_en_s cn63xxp1;
+        struct cvmx_pemx_dbg_info_en_s cn66xx;
+        struct cvmx_pemx_dbg_info_en_s cn68xx;
+        struct cvmx_pemx_dbg_info_en_s cn68xxp1;
+};
+
+union cvmx_pemx_diag_status {
+        uint64_t u64;
+        struct cvmx_pemx_diag_status_s {
+                uint64_t reserved_4_63:60;
+                uint64_t pm_dst:1;
+                uint64_t pm_stat:1;
+                uint64_t pm_en:1;
+                uint64_t aux_en:1;
+        } s;
+        struct cvmx_pemx_diag_status_s cn61xx;
+        struct cvmx_pemx_diag_status_s cn63xx;
+        struct cvmx_pemx_diag_status_s cn63xxp1;
+        struct cvmx_pemx_diag_status_s cn66xx;
+        struct cvmx_pemx_diag_status_s cn68xx;
+        struct cvmx_pemx_diag_status_s cn68xxp1;
+};
+
+union cvmx_pemx_inb_read_credits {
+        uint64_t u64;
+        struct cvmx_pemx_inb_read_credits_s {
+                uint64_t reserved_6_63:58;
+                uint64_t num:6;
+        } s;
+        struct cvmx_pemx_inb_read_credits_s cn61xx;
+        struct cvmx_pemx_inb_read_credits_s cn66xx;
+        struct cvmx_pemx_inb_read_credits_s cn68xx;
+};
+
+union cvmx_pemx_int_enb {
+        uint64_t u64;
+        struct cvmx_pemx_int_enb_s {
+                uint64_t reserved_14_63:50;
+                uint64_t crs_dr:1;
+                uint64_t crs_er:1;
+                uint64_t rdlk:1;
+                uint64_t exc:1;
+                uint64_t un_bx:1;
+                uint64_t un_b2:1;
+                uint64_t un_b1:1;
+                uint64_t up_bx:1;
+                uint64_t up_b2:1;
+                uint64_t up_b1:1;
+                uint64_t pmem:1;
+                uint64_t pmei:1;
+                uint64_t se:1;
+                uint64_t aeri:1;
+        } s;
+        struct cvmx_pemx_int_enb_s cn61xx;
+        struct cvmx_pemx_int_enb_s cn63xx;
+        struct cvmx_pemx_int_enb_s cn63xxp1;
+        struct cvmx_pemx_int_enb_s cn66xx;
+        struct cvmx_pemx_int_enb_s cn68xx;
+        struct cvmx_pemx_int_enb_s cn68xxp1;
+};
+
+union cvmx_pemx_int_enb_int {
+        uint64_t u64;
+        struct cvmx_pemx_int_enb_int_s {
+                uint64_t reserved_14_63:50;
+                uint64_t crs_dr:1;
+                uint64_t crs_er:1;
+                uint64_t rdlk:1;
+                uint64_t exc:1;
+                uint64_t un_bx:1;
+                uint64_t un_b2:1;
+                uint64_t un_b1:1;
+                uint64_t up_bx:1;
+                uint64_t up_b2:1;
+                uint64_t up_b1:1;
+                uint64_t pmem:1;
+                uint64_t pmei:1;
+                uint64_t se:1;
+                uint64_t aeri:1;
+        } s;
+        struct cvmx_pemx_int_enb_int_s cn61xx;
+        struct cvmx_pemx_int_enb_int_s cn63xx;
+        struct cvmx_pemx_int_enb_int_s cn63xxp1;
+        struct cvmx_pemx_int_enb_int_s cn66xx;
+        struct cvmx_pemx_int_enb_int_s cn68xx;
+        struct cvmx_pemx_int_enb_int_s cn68xxp1;
+};
+
+union cvmx_pemx_int_sum {
+        uint64_t u64;
+        struct cvmx_pemx_int_sum_s {
+                uint64_t reserved_14_63:50;
+                uint64_t crs_dr:1;
+                uint64_t crs_er:1;
+                uint64_t rdlk:1;
+                uint64_t exc:1;
+                uint64_t un_bx:1;
+                uint64_t un_b2:1;
+                uint64_t un_b1:1;
+                uint64_t up_bx:1;
+                uint64_t up_b2:1;
+                uint64_t up_b1:1;
+                uint64_t pmem:1;
+                uint64_t pmei:1;
+                uint64_t se:1;
+                uint64_t aeri:1;
+        } s;
+        struct cvmx_pemx_int_sum_s cn61xx;
+        struct cvmx_pemx_int_sum_s cn63xx;
+        struct cvmx_pemx_int_sum_s cn63xxp1;
+        struct cvmx_pemx_int_sum_s cn66xx;
+        struct cvmx_pemx_int_sum_s cn68xx;
+        struct cvmx_pemx_int_sum_s cn68xxp1;
+};
+
+union cvmx_pemx_p2n_bar0_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2n_bar0_start_s {
+                uint64_t addr:50;
+                uint64_t reserved_0_13:14;
+        } s;
+        struct cvmx_pemx_p2n_bar0_start_s cn61xx;
+        struct cvmx_pemx_p2n_bar0_start_s cn63xx;
+        struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
+        struct cvmx_pemx_p2n_bar0_start_s cn66xx;
+        struct cvmx_pemx_p2n_bar0_start_s cn68xx;
+        struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
+};
+
+union cvmx_pemx_p2n_bar1_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2n_bar1_start_s {
+                uint64_t addr:38;
+                uint64_t reserved_0_25:26;
+        } s;
+        struct cvmx_pemx_p2n_bar1_start_s cn61xx;
+        struct cvmx_pemx_p2n_bar1_start_s cn63xx;
+        struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
+        struct cvmx_pemx_p2n_bar1_start_s cn66xx;
+        struct cvmx_pemx_p2n_bar1_start_s cn68xx;
+        struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
+};
+
+union cvmx_pemx_p2n_bar2_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2n_bar2_start_s {
+                uint64_t addr:23;
+                uint64_t reserved_0_40:41;
+        } s;
+        struct cvmx_pemx_p2n_bar2_start_s cn61xx;
+        struct cvmx_pemx_p2n_bar2_start_s cn63xx;
+        struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
+        struct cvmx_pemx_p2n_bar2_start_s cn66xx;
+        struct cvmx_pemx_p2n_bar2_start_s cn68xx;
+        struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
+};
+
+union cvmx_pemx_p2p_barx_end {
+        uint64_t u64;
+        struct cvmx_pemx_p2p_barx_end_s {
+                uint64_t addr:52;
+                uint64_t reserved_0_11:12;
+        } s;
+        struct cvmx_pemx_p2p_barx_end_s cn63xx;
+        struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
+        struct cvmx_pemx_p2p_barx_end_s cn66xx;
+        struct cvmx_pemx_p2p_barx_end_s cn68xx;
+        struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
+};
+
+union cvmx_pemx_p2p_barx_start {
+        uint64_t u64;
+        struct cvmx_pemx_p2p_barx_start_s {
+                uint64_t addr:52;
+                uint64_t reserved_0_11:12;
+        } s;
+        struct cvmx_pemx_p2p_barx_start_s cn63xx;
+        struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
+        struct cvmx_pemx_p2p_barx_start_s cn66xx;
+        struct cvmx_pemx_p2p_barx_start_s cn68xx;
+        struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
+};
+
+union cvmx_pemx_tlp_credits {
+        uint64_t u64;
+        struct cvmx_pemx_tlp_credits_s {
+                uint64_t reserved_56_63:8;
+                uint64_t peai_ppf:8;
+                uint64_t pem_cpl:8;
+                uint64_t pem_np:8;
+                uint64_t pem_p:8;
+                uint64_t sli_cpl:8;
+                uint64_t sli_np:8;
+                uint64_t sli_p:8;
+        } s;
+        struct cvmx_pemx_tlp_credits_cn61xx {
+                uint64_t reserved_56_63:8;
+                uint64_t peai_ppf:8;
+                uint64_t reserved_24_47:24;
+                uint64_t sli_cpl:8;
+                uint64_t sli_np:8;
+                uint64_t sli_p:8;
+        } cn61xx;
+        struct cvmx_pemx_tlp_credits_s cn63xx;
+        struct cvmx_pemx_tlp_credits_s cn63xxp1;
+        struct cvmx_pemx_tlp_credits_s cn66xx;
+        struct cvmx_pemx_tlp_credits_s cn68xx;
+        struct cvmx_pemx_tlp_credits_s cn68xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ab8679d89af..4438d211988b 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2011 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -25,13 +25,6 @@
  * Contact Cavium Networks for more information
  ***********************license end**************************************/
 
-/**
- * cvmx-pexp-defs.h
- *
- * Configuration and status register (CSR) definitions for
- * OCTEON PEXP.
- *
- */
 #ifndef __CVMX_PEXP_DEFS_H__
 #define __CVMX_PEXP_DEFS_H__
 
@@ -139,7 +132,7 @@
 #define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
 #define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
 #define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
-#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
 #define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
 #define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
 #define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
@@ -152,7 +145,10 @@
 #define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
 #define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
 #define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
@@ -206,6 +202,7 @@
 #define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
 #define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
+#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
 #define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
 #define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
@@ -214,12 +211,14 @@
 #define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
 #define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
-#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
 #define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
 #define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
 #define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
 #define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
 #define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
+#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
 #define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
 
 #endif
diff --git a/drivers/staging/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
index 5a369100ca68..5a369100ca68 100644
--- a/drivers/staging/octeon/cvmx-pip-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
diff --git a/drivers/staging/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h
index 78dbce8f2c5e..78dbce8f2c5e 100644
--- a/drivers/staging/octeon/cvmx-pip.h
+++ b/arch/mips/include/asm/octeon/cvmx-pip.h
diff --git a/drivers/staging/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
index 50e779cf1ad8..50e779cf1ad8 100644
--- a/drivers/staging/octeon/cvmx-pko-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
diff --git a/drivers/staging/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
index de3412aada5d..de3412aada5d 100644
--- a/drivers/staging/octeon/cvmx-pko.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
diff --git a/drivers/staging/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
index 999aefe3274c..999aefe3274c 100644
--- a/drivers/staging/octeon/cvmx-pow.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
diff --git a/drivers/staging/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h
index 96b70cfd6245..96b70cfd6245 100644
--- a/drivers/staging/octeon/cvmx-scratch.h
+++ b/arch/mips/include/asm/octeon/cvmx-scratch.h
diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
new file mode 100644
index 000000000000..7c6c901d3d28
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -0,0 +1,2172 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SLI_DEFS_H__
+#define __CVMX_SLI_DEFS_H__
+
+#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
+#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
+#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
+#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
+#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
+#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
+#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
+#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
+#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
+#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
+#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
+#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
+#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
+#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
+#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
+#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
+#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
+#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
+#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
+#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
+#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
+#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
+#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
+#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
+#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
+#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
+#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
+#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
+#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
+#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
+#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
+#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
+#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
+#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
+#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
+#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
+#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
+#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
+#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
+#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
+#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
+#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
+#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
+#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
+#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
+#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
+#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
+#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
+#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
+#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
+#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
+#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
+#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
+#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
+#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
+#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
+#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
+#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
+#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
+#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
+#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
+#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
+#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
+#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
+#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
+#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
+#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
+#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
+#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
+#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
+#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
+#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
+#define CVMX_SLI_STATE1 (0x0000000000000620ull)
+#define CVMX_SLI_STATE2 (0x0000000000000630ull)
+#define CVMX_SLI_STATE3 (0x0000000000000640ull)
+#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
+#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
+#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
+#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
+#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
+#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
+#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
+
+union cvmx_sli_bist_status {
+        uint64_t u64;
+        struct cvmx_sli_bist_status_s {
+                uint64_t reserved_32_63:32;
+                uint64_t ncb_req:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t reserved_19_24:6;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t reserved_6_8:3;
+                uint64_t dsi1_1:1;
+                uint64_t dsi1_0:1;
+                uint64_t dsi0_1:1;
+                uint64_t dsi0_0:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } s;
+        struct cvmx_sli_bist_status_cn61xx {
+                uint64_t reserved_31_63:33;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t reserved_27_28:2;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t reserved_19_24:6;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t reserved_6_8:3;
+                uint64_t dsi1_1:1;
+                uint64_t dsi1_0:1;
+                uint64_t dsi0_1:1;
+                uint64_t dsi0_0:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } cn61xx;
+        struct cvmx_sli_bist_status_cn63xx {
+                uint64_t reserved_31_63:33;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t reserved_19_24:6;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t reserved_6_8:3;
+                uint64_t dsi1_1:1;
+                uint64_t dsi1_0:1;
+                uint64_t dsi0_1:1;
+                uint64_t dsi0_0:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } cn63xx;
+        struct cvmx_sli_bist_status_cn63xx cn63xxp1;
+        struct cvmx_sli_bist_status_cn61xx cn66xx;
+        struct cvmx_sli_bist_status_s cn68xx;
+        struct cvmx_sli_bist_status_s cn68xxp1;
+};
+
+union cvmx_sli_ctl_portx {
+        uint64_t u64;
+        struct cvmx_sli_ctl_portx_s {
+                uint64_t reserved_22_63:42;
+                uint64_t intd:1;
+                uint64_t intc:1;
+                uint64_t intb:1;
+                uint64_t inta:1;
+                uint64_t dis_port:1;
+                uint64_t waitl_com:1;
+                uint64_t intd_map:2;
+                uint64_t intc_map:2;
+                uint64_t intb_map:2;
+                uint64_t inta_map:2;
+                uint64_t ctlp_ro:1;
+                uint64_t reserved_6_6:1;
+                uint64_t ptlp_ro:1;
+                uint64_t reserved_1_4:4;
+                uint64_t wait_com:1;
+        } s;
+        struct cvmx_sli_ctl_portx_s cn61xx;
+        struct cvmx_sli_ctl_portx_s cn63xx;
+        struct cvmx_sli_ctl_portx_s cn63xxp1;
+        struct cvmx_sli_ctl_portx_s cn66xx;
+        struct cvmx_sli_ctl_portx_s cn68xx;
+        struct cvmx_sli_ctl_portx_s cn68xxp1;
+};
+
+union cvmx_sli_ctl_status {
+        uint64_t u64;
+        struct cvmx_sli_ctl_status_s {
+                uint64_t reserved_20_63:44;
+                uint64_t p1_ntags:6;
+                uint64_t p0_ntags:6;
+                uint64_t chip_rev:8;
+        } s;
+        struct cvmx_sli_ctl_status_cn61xx {
+                uint64_t reserved_14_63:50;
+                uint64_t p0_ntags:6;
+                uint64_t chip_rev:8;
+        } cn61xx;
+        struct cvmx_sli_ctl_status_s cn63xx;
+        struct cvmx_sli_ctl_status_s cn63xxp1;
+        struct cvmx_sli_ctl_status_cn61xx cn66xx;
+        struct cvmx_sli_ctl_status_s cn68xx;
+        struct cvmx_sli_ctl_status_s cn68xxp1;
+};
+
+union cvmx_sli_data_out_cnt {
+        uint64_t u64;
+        struct cvmx_sli_data_out_cnt_s {
+                uint64_t reserved_44_63:20;
+                uint64_t p1_ucnt:16;
+                uint64_t p1_fcnt:6;
+                uint64_t p0_ucnt:16;
+                uint64_t p0_fcnt:6;
+        } s;
+        struct cvmx_sli_data_out_cnt_s cn61xx;
+        struct cvmx_sli_data_out_cnt_s cn63xx;
+        struct cvmx_sli_data_out_cnt_s cn63xxp1;
+        struct cvmx_sli_data_out_cnt_s cn66xx;
+        struct cvmx_sli_data_out_cnt_s cn68xx;
+        struct cvmx_sli_data_out_cnt_s cn68xxp1;
+};
+
+union cvmx_sli_dbg_data {
+        uint64_t u64;
+        struct cvmx_sli_dbg_data_s {
+                uint64_t reserved_18_63:46;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+        } s;
+        struct cvmx_sli_dbg_data_s cn61xx;
+        struct cvmx_sli_dbg_data_s cn63xx;
+        struct cvmx_sli_dbg_data_s cn63xxp1;
+        struct cvmx_sli_dbg_data_s cn66xx;
+        struct cvmx_sli_dbg_data_s cn68xx;
+        struct cvmx_sli_dbg_data_s cn68xxp1;
+};
+
+union cvmx_sli_dbg_select {
+        uint64_t u64;
+        struct cvmx_sli_dbg_select_s {
+                uint64_t reserved_33_63:31;
+                uint64_t adbg_sel:1;
+                uint64_t dbg_sel:32;
+        } s;
+        struct cvmx_sli_dbg_select_s cn61xx;
+        struct cvmx_sli_dbg_select_s cn63xx;
+        struct cvmx_sli_dbg_select_s cn63xxp1;
+        struct cvmx_sli_dbg_select_s cn66xx;
+        struct cvmx_sli_dbg_select_s cn68xx;
+        struct cvmx_sli_dbg_select_s cn68xxp1;
+};
+
+union cvmx_sli_dmax_cnt {
+        uint64_t u64;
+        struct cvmx_sli_dmax_cnt_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_dmax_cnt_s cn61xx;
+        struct cvmx_sli_dmax_cnt_s cn63xx;
+        struct cvmx_sli_dmax_cnt_s cn63xxp1;
+        struct cvmx_sli_dmax_cnt_s cn66xx;
+        struct cvmx_sli_dmax_cnt_s cn68xx;
+        struct cvmx_sli_dmax_cnt_s cn68xxp1;
+};
+
+union cvmx_sli_dmax_int_level {
+        uint64_t u64;
+        struct cvmx_sli_dmax_int_level_s {
+                uint64_t time:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_dmax_int_level_s cn61xx;
+        struct cvmx_sli_dmax_int_level_s cn63xx;
+        struct cvmx_sli_dmax_int_level_s cn63xxp1;
+        struct cvmx_sli_dmax_int_level_s cn66xx;
+        struct cvmx_sli_dmax_int_level_s cn68xx;
+        struct cvmx_sli_dmax_int_level_s cn68xxp1;
+};
+
+union cvmx_sli_dmax_tim {
+        uint64_t u64;
+        struct cvmx_sli_dmax_tim_s {
+                uint64_t reserved_32_63:32;
+                uint64_t tim:32;
+        } s;
+        struct cvmx_sli_dmax_tim_s cn61xx;
+        struct cvmx_sli_dmax_tim_s cn63xx;
+        struct cvmx_sli_dmax_tim_s cn63xxp1;
+        struct cvmx_sli_dmax_tim_s cn66xx;
+        struct cvmx_sli_dmax_tim_s cn68xx;
+        struct cvmx_sli_dmax_tim_s cn68xxp1;
+};
+
+union cvmx_sli_int_enb_ciu {
+        uint64_t u64;
+        struct cvmx_sli_int_enb_ciu_s {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t reserved_18_19:2;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } s;
+        struct cvmx_sli_int_enb_ciu_cn61xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t reserved_18_19:2;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn61xx;
+        struct cvmx_sli_int_enb_ciu_cn63xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_18_31:14;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn63xx;
+        struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
+        struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
+        struct cvmx_sli_int_enb_ciu_cn68xx {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t reserved_51_51:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_18_31:14;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn68xx;
+        struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_int_enb_portx {
+        uint64_t u64;
+        struct cvmx_sli_int_enb_portx_s {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } s;
+        struct cvmx_sli_int_enb_portx_cn61xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn61xx;
+        struct cvmx_sli_int_enb_portx_cn63xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_20_31:12;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn63xx;
+        struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
+        struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
+        struct cvmx_sli_int_enb_portx_cn68xx {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t reserved_51_51:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_20_31:12;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn68xx;
+        struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_int_sum {
+        uint64_t u64;
+        struct cvmx_sli_int_sum_s {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } s;
+        struct cvmx_sli_int_sum_cn61xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t sprt3_err:1;
+                uint64_t sprt2_err:1;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_28_31:4;
+                uint64_t m3_un_wi:1;
+                uint64_t m3_un_b0:1;
+                uint64_t m3_up_wi:1;
+                uint64_t m3_up_b0:1;
+                uint64_t m2_un_wi:1;
+                uint64_t m2_un_b0:1;
+                uint64_t m2_up_wi:1;
+                uint64_t m2_up_b0:1;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn61xx;
+        struct cvmx_sli_int_sum_cn63xx {
+                uint64_t reserved_61_63:3;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t pin_bp:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_20_31:12;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn63xx;
+        struct cvmx_sli_int_sum_cn63xx cn63xxp1;
+        struct cvmx_sli_int_sum_cn61xx cn66xx;
+        struct cvmx_sli_int_sum_cn68xx {
+                uint64_t reserved_62_63:2;
+                uint64_t pipe_err:1;
+                uint64_t ill_pad:1;
+                uint64_t reserved_58_59:2;
+                uint64_t sprt1_err:1;
+                uint64_t sprt0_err:1;
+                uint64_t pins_err:1;
+                uint64_t pop_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pgl_err:1;
+                uint64_t reserved_51_51:1;
+                uint64_t pout_err:1;
+                uint64_t psldbof:1;
+                uint64_t pidbof:1;
+                uint64_t reserved_38_47:10;
+                uint64_t dtime:2;
+                uint64_t dcnt:2;
+                uint64_t dmafi:2;
+                uint64_t reserved_20_31:12;
+                uint64_t mac1_int:1;
+                uint64_t mac0_int:1;
+                uint64_t mio_int1:1;
+                uint64_t mio_int0:1;
+                uint64_t m1_un_wi:1;
+                uint64_t m1_un_b0:1;
+                uint64_t m1_up_wi:1;
+                uint64_t m1_up_b0:1;
+                uint64_t m0_un_wi:1;
+                uint64_t m0_un_b0:1;
+                uint64_t m0_up_wi:1;
+                uint64_t m0_up_b0:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t reserved_1_1:1;
+                uint64_t rml_to:1;
+        } cn68xx;
+        struct cvmx_sli_int_sum_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_last_win_rdata0 {
+        uint64_t u64;
+        struct cvmx_sli_last_win_rdata0_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_last_win_rdata0_s cn61xx;
+        struct cvmx_sli_last_win_rdata0_s cn63xx;
+        struct cvmx_sli_last_win_rdata0_s cn63xxp1;
+        struct cvmx_sli_last_win_rdata0_s cn66xx;
+        struct cvmx_sli_last_win_rdata0_s cn68xx;
+        struct cvmx_sli_last_win_rdata0_s cn68xxp1;
+};
+
+union cvmx_sli_last_win_rdata1 {
+        uint64_t u64;
+        struct cvmx_sli_last_win_rdata1_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_last_win_rdata1_s cn61xx;
+        struct cvmx_sli_last_win_rdata1_s cn63xx;
+        struct cvmx_sli_last_win_rdata1_s cn63xxp1;
+        struct cvmx_sli_last_win_rdata1_s cn66xx;
+        struct cvmx_sli_last_win_rdata1_s cn68xx;
+        struct cvmx_sli_last_win_rdata1_s cn68xxp1;
+};
+
+union cvmx_sli_last_win_rdata2 {
+        uint64_t u64;
+        struct cvmx_sli_last_win_rdata2_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_last_win_rdata2_s cn61xx;
+        struct cvmx_sli_last_win_rdata2_s cn66xx;
+};
+
+union cvmx_sli_last_win_rdata3 {
+        uint64_t u64;
+        struct cvmx_sli_last_win_rdata3_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_last_win_rdata3_s cn61xx;
+        struct cvmx_sli_last_win_rdata3_s cn66xx;
+};
+
+union cvmx_sli_mac_credit_cnt {
+        uint64_t u64;
+        struct cvmx_sli_mac_credit_cnt_s {
+                uint64_t reserved_54_63:10;
+                uint64_t p1_c_d:1;
+                uint64_t p1_n_d:1;
+                uint64_t p1_p_d:1;
+                uint64_t p0_c_d:1;
+                uint64_t p0_n_d:1;
+                uint64_t p0_p_d:1;
+                uint64_t p1_ccnt:8;
+                uint64_t p1_ncnt:8;
+                uint64_t p1_pcnt:8;
+                uint64_t p0_ccnt:8;
+                uint64_t p0_ncnt:8;
+                uint64_t p0_pcnt:8;
+        } s;
+        struct cvmx_sli_mac_credit_cnt_s cn61xx;
+        struct cvmx_sli_mac_credit_cnt_s cn63xx;
+        struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
+                uint64_t reserved_48_63:16;
+                uint64_t p1_ccnt:8;
+                uint64_t p1_ncnt:8;
+                uint64_t p1_pcnt:8;
+                uint64_t p0_ccnt:8;
+                uint64_t p0_ncnt:8;
+                uint64_t p0_pcnt:8;
+        } cn63xxp1;
+        struct cvmx_sli_mac_credit_cnt_s cn66xx;
+        struct cvmx_sli_mac_credit_cnt_s cn68xx;
+        struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
+};
+
+union cvmx_sli_mac_credit_cnt2 {
+        uint64_t u64;
+        struct cvmx_sli_mac_credit_cnt2_s {
+                uint64_t reserved_54_63:10;
+                uint64_t p3_c_d:1;
+                uint64_t p3_n_d:1;
+                uint64_t p3_p_d:1;
+                uint64_t p2_c_d:1;
+                uint64_t p2_n_d:1;
+                uint64_t p2_p_d:1;
+                uint64_t p3_ccnt:8;
+                uint64_t p3_ncnt:8;
+                uint64_t p3_pcnt:8;
+                uint64_t p2_ccnt:8;
+                uint64_t p2_ncnt:8;
+                uint64_t p2_pcnt:8;
+        } s;
+        struct cvmx_sli_mac_credit_cnt2_s cn61xx;
+        struct cvmx_sli_mac_credit_cnt2_s cn66xx;
+};
+
+union cvmx_sli_mac_number {
+        uint64_t u64;
+        struct cvmx_sli_mac_number_s {
+                uint64_t reserved_9_63:55;
+                uint64_t a_mode:1;
+                uint64_t num:8;
+        } s;
+        struct cvmx_sli_mac_number_s cn61xx;
+        struct cvmx_sli_mac_number_cn63xx {
+                uint64_t reserved_8_63:56;
+                uint64_t num:8;
+        } cn63xx;
+        struct cvmx_sli_mac_number_s cn66xx;
+        struct cvmx_sli_mac_number_cn63xx cn68xx;
+        struct cvmx_sli_mac_number_cn63xx cn68xxp1;
+};
+
+union cvmx_sli_mem_access_ctl {
+        uint64_t u64;
+        struct cvmx_sli_mem_access_ctl_s {
+                uint64_t reserved_14_63:50;
+                uint64_t max_word:4;
+                uint64_t timer:10;
+        } s;
+        struct cvmx_sli_mem_access_ctl_s cn61xx;
+        struct cvmx_sli_mem_access_ctl_s cn63xx;
+        struct cvmx_sli_mem_access_ctl_s cn63xxp1;
+        struct cvmx_sli_mem_access_ctl_s cn66xx;
+        struct cvmx_sli_mem_access_ctl_s cn68xx;
+        struct cvmx_sli_mem_access_ctl_s cn68xxp1;
+};
+
+union cvmx_sli_mem_access_subidx {
+        uint64_t u64;
+        struct cvmx_sli_mem_access_subidx_s {
+                uint64_t reserved_43_63:21;
+                uint64_t zero:1;
+                uint64_t port:3;
+                uint64_t nmerge:1;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t wtype:2;
+                uint64_t rtype:2;
+                uint64_t reserved_0_29:30;
+        } s;
+        struct cvmx_sli_mem_access_subidx_cn61xx {
+                uint64_t reserved_43_63:21;
+                uint64_t zero:1;
+                uint64_t port:3;
+                uint64_t nmerge:1;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t wtype:2;
+                uint64_t rtype:2;
+                uint64_t ba:30;
+        } cn61xx;
+        struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
+        struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
+        struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
+        struct cvmx_sli_mem_access_subidx_cn68xx {
+                uint64_t reserved_43_63:21;
+                uint64_t zero:1;
+                uint64_t port:3;
+                uint64_t nmerge:1;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t wtype:2;
+                uint64_t rtype:2;
+                uint64_t ba:28;
+                uint64_t reserved_0_1:2;
+        } cn68xx;
+        struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_msi_enb0 {
+        uint64_t u64;
+        struct cvmx_sli_msi_enb0_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_sli_msi_enb0_s cn61xx;
+        struct cvmx_sli_msi_enb0_s cn63xx;
+        struct cvmx_sli_msi_enb0_s cn63xxp1;
+        struct cvmx_sli_msi_enb0_s cn66xx;
+        struct cvmx_sli_msi_enb0_s cn68xx;
+        struct cvmx_sli_msi_enb0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_enb1 {
+        uint64_t u64;
+        struct cvmx_sli_msi_enb1_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_sli_msi_enb1_s cn61xx;
+        struct cvmx_sli_msi_enb1_s cn63xx;
+        struct cvmx_sli_msi_enb1_s cn63xxp1;
+        struct cvmx_sli_msi_enb1_s cn66xx;
+        struct cvmx_sli_msi_enb1_s cn68xx;
+        struct cvmx_sli_msi_enb1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_enb2 {
+        uint64_t u64;
+        struct cvmx_sli_msi_enb2_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_sli_msi_enb2_s cn61xx;
+        struct cvmx_sli_msi_enb2_s cn63xx;
+        struct cvmx_sli_msi_enb2_s cn63xxp1;
+        struct cvmx_sli_msi_enb2_s cn66xx;
+        struct cvmx_sli_msi_enb2_s cn68xx;
+        struct cvmx_sli_msi_enb2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_enb3 {
+        uint64_t u64;
+        struct cvmx_sli_msi_enb3_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_sli_msi_enb3_s cn61xx;
+        struct cvmx_sli_msi_enb3_s cn63xx;
+        struct cvmx_sli_msi_enb3_s cn63xxp1;
+        struct cvmx_sli_msi_enb3_s cn66xx;
+        struct cvmx_sli_msi_enb3_s cn68xx;
+        struct cvmx_sli_msi_enb3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv0 {
+        uint64_t u64;
+        struct cvmx_sli_msi_rcv0_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_sli_msi_rcv0_s cn61xx;
+        struct cvmx_sli_msi_rcv0_s cn63xx;
+        struct cvmx_sli_msi_rcv0_s cn63xxp1;
+        struct cvmx_sli_msi_rcv0_s cn66xx;
+        struct cvmx_sli_msi_rcv0_s cn68xx;
+        struct cvmx_sli_msi_rcv0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv1 {
+        uint64_t u64;
+        struct cvmx_sli_msi_rcv1_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_sli_msi_rcv1_s cn61xx;
+        struct cvmx_sli_msi_rcv1_s cn63xx;
+        struct cvmx_sli_msi_rcv1_s cn63xxp1;
+        struct cvmx_sli_msi_rcv1_s cn66xx;
+        struct cvmx_sli_msi_rcv1_s cn68xx;
+        struct cvmx_sli_msi_rcv1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv2 {
+        uint64_t u64;
+        struct cvmx_sli_msi_rcv2_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_sli_msi_rcv2_s cn61xx;
+        struct cvmx_sli_msi_rcv2_s cn63xx;
+        struct cvmx_sli_msi_rcv2_s cn63xxp1;
+        struct cvmx_sli_msi_rcv2_s cn66xx;
+        struct cvmx_sli_msi_rcv2_s cn68xx;
+        struct cvmx_sli_msi_rcv2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv3 {
+        uint64_t u64;
+        struct cvmx_sli_msi_rcv3_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_sli_msi_rcv3_s cn61xx;
+        struct cvmx_sli_msi_rcv3_s cn63xx;
+        struct cvmx_sli_msi_rcv3_s cn63xxp1;
+        struct cvmx_sli_msi_rcv3_s cn66xx;
+        struct cvmx_sli_msi_rcv3_s cn68xx;
+        struct cvmx_sli_msi_rcv3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rd_map {
+        uint64_t u64;
+        struct cvmx_sli_msi_rd_map_s {
+                uint64_t reserved_16_63:48;
+                uint64_t rd_int:8;
+                uint64_t msi_int:8;
+        } s;
+        struct cvmx_sli_msi_rd_map_s cn61xx;
+        struct cvmx_sli_msi_rd_map_s cn63xx;
+        struct cvmx_sli_msi_rd_map_s cn63xxp1;
+        struct cvmx_sli_msi_rd_map_s cn66xx;
+        struct cvmx_sli_msi_rd_map_s cn68xx;
+        struct cvmx_sli_msi_rd_map_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb0 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1c_enb0_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_sli_msi_w1c_enb0_s cn61xx;
+        struct cvmx_sli_msi_w1c_enb0_s cn63xx;
+        struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
+        struct cvmx_sli_msi_w1c_enb0_s cn66xx;
+        struct cvmx_sli_msi_w1c_enb0_s cn68xx;
+        struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb1 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1c_enb1_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_sli_msi_w1c_enb1_s cn61xx;
+        struct cvmx_sli_msi_w1c_enb1_s cn63xx;
+        struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
+        struct cvmx_sli_msi_w1c_enb1_s cn66xx;
+        struct cvmx_sli_msi_w1c_enb1_s cn68xx;
+        struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb2 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1c_enb2_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_sli_msi_w1c_enb2_s cn61xx;
+        struct cvmx_sli_msi_w1c_enb2_s cn63xx;
+        struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
+        struct cvmx_sli_msi_w1c_enb2_s cn66xx;
+        struct cvmx_sli_msi_w1c_enb2_s cn68xx;
+        struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb3 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1c_enb3_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_sli_msi_w1c_enb3_s cn61xx;
+        struct cvmx_sli_msi_w1c_enb3_s cn63xx;
+        struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
+        struct cvmx_sli_msi_w1c_enb3_s cn66xx;
+        struct cvmx_sli_msi_w1c_enb3_s cn68xx;
+        struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb0 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1s_enb0_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_sli_msi_w1s_enb0_s cn61xx;
+        struct cvmx_sli_msi_w1s_enb0_s cn63xx;
+        struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
+        struct cvmx_sli_msi_w1s_enb0_s cn66xx;
+        struct cvmx_sli_msi_w1s_enb0_s cn68xx;
+        struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb1 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1s_enb1_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_sli_msi_w1s_enb1_s cn61xx;
+        struct cvmx_sli_msi_w1s_enb1_s cn63xx;
+        struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
+        struct cvmx_sli_msi_w1s_enb1_s cn66xx;
+        struct cvmx_sli_msi_w1s_enb1_s cn68xx;
+        struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb2 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1s_enb2_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_sli_msi_w1s_enb2_s cn61xx;
+        struct cvmx_sli_msi_w1s_enb2_s cn63xx;
+        struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
+        struct cvmx_sli_msi_w1s_enb2_s cn66xx;
+        struct cvmx_sli_msi_w1s_enb2_s cn68xx;
+        struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb3 {
+        uint64_t u64;
+        struct cvmx_sli_msi_w1s_enb3_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_sli_msi_w1s_enb3_s cn61xx;
+        struct cvmx_sli_msi_w1s_enb3_s cn63xx;
+        struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
+        struct cvmx_sli_msi_w1s_enb3_s cn66xx;
+        struct cvmx_sli_msi_w1s_enb3_s cn68xx;
+        struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_wr_map {
+        uint64_t u64;
+        struct cvmx_sli_msi_wr_map_s {
+                uint64_t reserved_16_63:48;
+                uint64_t ciu_int:8;
+                uint64_t msi_int:8;
+        } s;
+        struct cvmx_sli_msi_wr_map_s cn61xx;
+        struct cvmx_sli_msi_wr_map_s cn63xx;
+        struct cvmx_sli_msi_wr_map_s cn63xxp1;
+        struct cvmx_sli_msi_wr_map_s cn66xx;
+        struct cvmx_sli_msi_wr_map_s cn68xx;
+        struct cvmx_sli_msi_wr_map_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv {
+        uint64_t u64;
+        struct cvmx_sli_pcie_msi_rcv_s {
+                uint64_t reserved_8_63:56;
+                uint64_t intr:8;
+        } s;
+        struct cvmx_sli_pcie_msi_rcv_s cn61xx;
+        struct cvmx_sli_pcie_msi_rcv_s cn63xx;
+        struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
+        struct cvmx_sli_pcie_msi_rcv_s cn66xx;
+        struct cvmx_sli_pcie_msi_rcv_s cn68xx;
+        struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv_b1 {
+        uint64_t u64;
+        struct cvmx_sli_pcie_msi_rcv_b1_s {
+                uint64_t reserved_16_63:48;
+                uint64_t intr:8;
+                uint64_t reserved_0_7:8;
+        } s;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
+        struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv_b2 {
+        uint64_t u64;
+        struct cvmx_sli_pcie_msi_rcv_b2_s {
+                uint64_t reserved_24_63:40;
+                uint64_t intr:8;
+                uint64_t reserved_0_15:16;
+        } s;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
+        struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv_b3 {
+        uint64_t u64;
+        struct cvmx_sli_pcie_msi_rcv_b3_s {
+                uint64_t reserved_32_63:32;
+                uint64_t intr:8;
+                uint64_t reserved_0_23:24;
+        } s;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
+        struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_cnts {
+        uint64_t u64;
+        struct cvmx_sli_pktx_cnts_s {
+                uint64_t reserved_54_63:10;
+                uint64_t timer:22;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_pktx_cnts_s cn61xx;
+        struct cvmx_sli_pktx_cnts_s cn63xx;
+        struct cvmx_sli_pktx_cnts_s cn63xxp1;
+        struct cvmx_sli_pktx_cnts_s cn66xx;
+        struct cvmx_sli_pktx_cnts_s cn68xx;
+        struct cvmx_sli_pktx_cnts_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_in_bp {
+        uint64_t u64;
+        struct cvmx_sli_pktx_in_bp_s {
+                uint64_t wmark:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_pktx_in_bp_s cn61xx;
+        struct cvmx_sli_pktx_in_bp_s cn63xx;
+        struct cvmx_sli_pktx_in_bp_s cn63xxp1;
+        struct cvmx_sli_pktx_in_bp_s cn66xx;
+};
+
+union cvmx_sli_pktx_instr_baddr {
+        uint64_t u64;
+        struct cvmx_sli_pktx_instr_baddr_s {
+                uint64_t addr:61;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_sli_pktx_instr_baddr_s cn61xx;
+        struct cvmx_sli_pktx_instr_baddr_s cn63xx;
+        struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
+        struct cvmx_sli_pktx_instr_baddr_s cn66xx;
+        struct cvmx_sli_pktx_instr_baddr_s cn68xx;
+        struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_instr_baoff_dbell {
+        uint64_t u64;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s {
+                uint64_t aoff:32;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
+        struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_instr_fifo_rsize {
+        uint64_t u64;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s {
+                uint64_t max:9;
+                uint64_t rrp:9;
+                uint64_t wrp:9;
+                uint64_t fcnt:5;
+                uint64_t rsize:32;
+        } s;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
+        struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_instr_header {
+        uint64_t u64;
+        struct cvmx_sli_pktx_instr_header_s {
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t reserved_38_42:5;
+                uint64_t rparmode:2;
+                uint64_t reserved_35_35:1;
+                uint64_t rskp_len:7;
+                uint64_t rngrpext:2;
+                uint64_t rnqos:1;
+                uint64_t rngrp:1;
+                uint64_t rntt:1;
+                uint64_t rntag:1;
+                uint64_t use_ihdr:1;
+                uint64_t reserved_16_20:5;
+                uint64_t par_mode:2;
+                uint64_t reserved_13_13:1;
+                uint64_t skp_len:7;
+                uint64_t ngrpext:2;
+                uint64_t nqos:1;
+                uint64_t ngrp:1;
+                uint64_t ntt:1;
+                uint64_t ntag:1;
+        } s;
+        struct cvmx_sli_pktx_instr_header_cn61xx {
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t reserved_38_42:5;
+                uint64_t rparmode:2;
+                uint64_t reserved_35_35:1;
+                uint64_t rskp_len:7;
+                uint64_t reserved_26_27:2;
+                uint64_t rnqos:1;
+                uint64_t rngrp:1;
+                uint64_t rntt:1;
+                uint64_t rntag:1;
+                uint64_t use_ihdr:1;
+                uint64_t reserved_16_20:5;
+                uint64_t par_mode:2;
+                uint64_t reserved_13_13:1;
+                uint64_t skp_len:7;
+                uint64_t reserved_4_5:2;
+                uint64_t nqos:1;
+                uint64_t ngrp:1;
+                uint64_t ntt:1;
+                uint64_t ntag:1;
+        } cn61xx;
+        struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
+        struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
+        struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
+        struct cvmx_sli_pktx_instr_header_s cn68xx;
+        struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
+};
+
+union cvmx_sli_pktx_out_size {
+        uint64_t u64;
+        struct cvmx_sli_pktx_out_size_s {
+                uint64_t reserved_23_63:41;
+                uint64_t isize:7;
+                uint64_t bsize:16;
+        } s;
+        struct cvmx_sli_pktx_out_size_s cn61xx;
+        struct cvmx_sli_pktx_out_size_s cn63xx;
+        struct cvmx_sli_pktx_out_size_s cn63xxp1;
+        struct cvmx_sli_pktx_out_size_s cn66xx;
+        struct cvmx_sli_pktx_out_size_s cn68xx;
+        struct cvmx_sli_pktx_out_size_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_slist_baddr {
+        uint64_t u64;
+        struct cvmx_sli_pktx_slist_baddr_s {
+                uint64_t addr:60;
+                uint64_t reserved_0_3:4;
+        } s;
+        struct cvmx_sli_pktx_slist_baddr_s cn61xx;
+        struct cvmx_sli_pktx_slist_baddr_s cn63xx;
+        struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
+        struct cvmx_sli_pktx_slist_baddr_s cn66xx;
+        struct cvmx_sli_pktx_slist_baddr_s cn68xx;
+        struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_slist_baoff_dbell {
+        uint64_t u64;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s {
+                uint64_t aoff:32;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
+        struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_slist_fifo_rsize {
+        uint64_t u64;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s {
+                uint64_t reserved_32_63:32;
+                uint64_t rsize:32;
+        } s;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
+        struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_cnt_int {
+        uint64_t u64;
+        struct cvmx_sli_pkt_cnt_int_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_sli_pkt_cnt_int_s cn61xx;
+        struct cvmx_sli_pkt_cnt_int_s cn63xx;
+        struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
+        struct cvmx_sli_pkt_cnt_int_s cn66xx;
+        struct cvmx_sli_pkt_cnt_int_s cn68xx;
+        struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_cnt_int_enb {
+        uint64_t u64;
+        struct cvmx_sli_pkt_cnt_int_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
+        struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_ctl {
+        uint64_t u64;
+        struct cvmx_sli_pkt_ctl_s {
+                uint64_t reserved_5_63:59;
+                uint64_t ring_en:1;
+                uint64_t pkt_bp:4;
+        } s;
+        struct cvmx_sli_pkt_ctl_s cn61xx;
+        struct cvmx_sli_pkt_ctl_s cn63xx;
+        struct cvmx_sli_pkt_ctl_s cn63xxp1;
+        struct cvmx_sli_pkt_ctl_s cn66xx;
+        struct cvmx_sli_pkt_ctl_s cn68xx;
+        struct cvmx_sli_pkt_ctl_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_data_out_es {
+        uint64_t u64;
+        struct cvmx_sli_pkt_data_out_es_s {
+                uint64_t es:64;
+        } s;
+        struct cvmx_sli_pkt_data_out_es_s cn61xx;
+        struct cvmx_sli_pkt_data_out_es_s cn63xx;
+        struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
+        struct cvmx_sli_pkt_data_out_es_s cn66xx;
+        struct cvmx_sli_pkt_data_out_es_s cn68xx;
+        struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_data_out_ns {
+        uint64_t u64;
+        struct cvmx_sli_pkt_data_out_ns_s {
+                uint64_t reserved_32_63:32;
+                uint64_t nsr:32;
+        } s;
+        struct cvmx_sli_pkt_data_out_ns_s cn61xx;
+        struct cvmx_sli_pkt_data_out_ns_s cn63xx;
+        struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
+        struct cvmx_sli_pkt_data_out_ns_s cn66xx;
+        struct cvmx_sli_pkt_data_out_ns_s cn68xx;
+        struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_data_out_ror {
+        uint64_t u64;
+        struct cvmx_sli_pkt_data_out_ror_s {
+                uint64_t reserved_32_63:32;
+                uint64_t ror:32;
+        } s;
+        struct cvmx_sli_pkt_data_out_ror_s cn61xx;
+        struct cvmx_sli_pkt_data_out_ror_s cn63xx;
+        struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
+        struct cvmx_sli_pkt_data_out_ror_s cn66xx;
+        struct cvmx_sli_pkt_data_out_ror_s cn68xx;
+        struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_dpaddr {
+        uint64_t u64;
+        struct cvmx_sli_pkt_dpaddr_s {
+                uint64_t reserved_32_63:32;
+                uint64_t dptr:32;
+        } s;
+        struct cvmx_sli_pkt_dpaddr_s cn61xx;
+        struct cvmx_sli_pkt_dpaddr_s cn63xx;
+        struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
+        struct cvmx_sli_pkt_dpaddr_s cn66xx;
+        struct cvmx_sli_pkt_dpaddr_s cn68xx;
+        struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_in_bp {
+        uint64_t u64;
+        struct cvmx_sli_pkt_in_bp_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bp:32;
+        } s;
+        struct cvmx_sli_pkt_in_bp_s cn61xx;
+        struct cvmx_sli_pkt_in_bp_s cn63xx;
+        struct cvmx_sli_pkt_in_bp_s cn63xxp1;
+        struct cvmx_sli_pkt_in_bp_s cn66xx;
+};
+
+union cvmx_sli_pkt_in_donex_cnts {
+        uint64_t u64;
+        struct cvmx_sli_pkt_in_donex_cnts_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
+        struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_in_instr_counts {
+        uint64_t u64;
+        struct cvmx_sli_pkt_in_instr_counts_s {
+                uint64_t wr_cnt:32;
+                uint64_t rd_cnt:32;
+        } s;
+        struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
+        struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
+        struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
+        struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
+        struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
+        struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_in_pcie_port {
+        uint64_t u64;
+        struct cvmx_sli_pkt_in_pcie_port_s {
+                uint64_t pp:64;
+        } s;
+        struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
+        struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
+        struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
+        struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
+        struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
+        struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_input_control {
+        uint64_t u64;
+        struct cvmx_sli_pkt_input_control_s {
+                uint64_t prd_erst:1;
+                uint64_t prd_rds:7;
+                uint64_t gii_erst:1;
+                uint64_t gii_rds:7;
+                uint64_t reserved_41_47:7;
+                uint64_t prc_idle:1;
+                uint64_t reserved_24_39:16;
+                uint64_t pin_rst:1;
+                uint64_t pkt_rr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t d_nsr:1;
+                uint64_t d_esr:2;
+                uint64_t d_ror:1;
+                uint64_t use_csr:1;
+                uint64_t nsr:1;
+                uint64_t esr:2;
+                uint64_t ror:1;
+        } s;
+        struct cvmx_sli_pkt_input_control_s cn61xx;
+        struct cvmx_sli_pkt_input_control_cn63xx {
+                uint64_t reserved_23_63:41;
+                uint64_t pkt_rr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t d_nsr:1;
+                uint64_t d_esr:2;
+                uint64_t d_ror:1;
+                uint64_t use_csr:1;
+                uint64_t nsr:1;
+                uint64_t esr:2;
+                uint64_t ror:1;
+        } cn63xx;
+        struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
+        struct cvmx_sli_pkt_input_control_s cn66xx;
+        struct cvmx_sli_pkt_input_control_s cn68xx;
+        struct cvmx_sli_pkt_input_control_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_instr_enb {
+        uint64_t u64;
+        struct cvmx_sli_pkt_instr_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t enb:32;
+        } s;
+        struct cvmx_sli_pkt_instr_enb_s cn61xx;
+        struct cvmx_sli_pkt_instr_enb_s cn63xx;
+        struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
+        struct cvmx_sli_pkt_instr_enb_s cn66xx;
+        struct cvmx_sli_pkt_instr_enb_s cn68xx;
+        struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_instr_rd_size {
+        uint64_t u64;
+        struct cvmx_sli_pkt_instr_rd_size_s {
+                uint64_t rdsize:64;
+        } s;
+        struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
+        struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
+        struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
+        struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
+        struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
+        struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_instr_size {
+        uint64_t u64;
+        struct cvmx_sli_pkt_instr_size_s {
+                uint64_t reserved_32_63:32;
+                uint64_t is_64b:32;
+        } s;
+        struct cvmx_sli_pkt_instr_size_s cn61xx;
+        struct cvmx_sli_pkt_instr_size_s cn63xx;
+        struct cvmx_sli_pkt_instr_size_s cn63xxp1;
+        struct cvmx_sli_pkt_instr_size_s cn66xx;
+        struct cvmx_sli_pkt_instr_size_s cn68xx;
+        struct cvmx_sli_pkt_instr_size_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_int_levels {
+        uint64_t u64;
+        struct cvmx_sli_pkt_int_levels_s {
+                uint64_t reserved_54_63:10;
+                uint64_t time:22;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_sli_pkt_int_levels_s cn61xx;
+        struct cvmx_sli_pkt_int_levels_s cn63xx;
+        struct cvmx_sli_pkt_int_levels_s cn63xxp1;
+        struct cvmx_sli_pkt_int_levels_s cn66xx;
+        struct cvmx_sli_pkt_int_levels_s cn68xx;
+        struct cvmx_sli_pkt_int_levels_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_iptr {
+        uint64_t u64;
+        struct cvmx_sli_pkt_iptr_s {
+                uint64_t reserved_32_63:32;
+                uint64_t iptr:32;
+        } s;
+        struct cvmx_sli_pkt_iptr_s cn61xx;
+        struct cvmx_sli_pkt_iptr_s cn63xx;
+        struct cvmx_sli_pkt_iptr_s cn63xxp1;
+        struct cvmx_sli_pkt_iptr_s cn66xx;
+        struct cvmx_sli_pkt_iptr_s cn68xx;
+        struct cvmx_sli_pkt_iptr_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_out_bmode {
+        uint64_t u64;
+        struct cvmx_sli_pkt_out_bmode_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bmode:32;
+        } s;
+        struct cvmx_sli_pkt_out_bmode_s cn61xx;
+        struct cvmx_sli_pkt_out_bmode_s cn63xx;
+        struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
+        struct cvmx_sli_pkt_out_bmode_s cn66xx;
+        struct cvmx_sli_pkt_out_bmode_s cn68xx;
+        struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_out_bp_en {
+        uint64_t u64;
+        struct cvmx_sli_pkt_out_bp_en_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bp_en:32;
+        } s;
+        struct cvmx_sli_pkt_out_bp_en_s cn68xx;
+        struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_out_enb {
+        uint64_t u64;
+        struct cvmx_sli_pkt_out_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t enb:32;
+        } s;
+        struct cvmx_sli_pkt_out_enb_s cn61xx;
+        struct cvmx_sli_pkt_out_enb_s cn63xx;
+        struct cvmx_sli_pkt_out_enb_s cn63xxp1;
+        struct cvmx_sli_pkt_out_enb_s cn66xx;
+        struct cvmx_sli_pkt_out_enb_s cn68xx;
+        struct cvmx_sli_pkt_out_enb_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_output_wmark {
+        uint64_t u64;
+        struct cvmx_sli_pkt_output_wmark_s {
+                uint64_t reserved_32_63:32;
+                uint64_t wmark:32;
+        } s;
+        struct cvmx_sli_pkt_output_wmark_s cn61xx;
+        struct cvmx_sli_pkt_output_wmark_s cn63xx;
+        struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
+        struct cvmx_sli_pkt_output_wmark_s cn66xx;
+        struct cvmx_sli_pkt_output_wmark_s cn68xx;
+        struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_pcie_port {
+        uint64_t u64;
+        struct cvmx_sli_pkt_pcie_port_s {
+                uint64_t pp:64;
+        } s;
+        struct cvmx_sli_pkt_pcie_port_s cn61xx;
+        struct cvmx_sli_pkt_pcie_port_s cn63xx;
+        struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
+        struct cvmx_sli_pkt_pcie_port_s cn66xx;
+        struct cvmx_sli_pkt_pcie_port_s cn68xx;
+        struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_port_in_rst {
+        uint64_t u64;
+        struct cvmx_sli_pkt_port_in_rst_s {
+                uint64_t in_rst:32;
+                uint64_t out_rst:32;
+        } s;
+        struct cvmx_sli_pkt_port_in_rst_s cn61xx;
+        struct cvmx_sli_pkt_port_in_rst_s cn63xx;
+        struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
+        struct cvmx_sli_pkt_port_in_rst_s cn66xx;
+        struct cvmx_sli_pkt_port_in_rst_s cn68xx;
+        struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_slist_es {
+        uint64_t u64;
+        struct cvmx_sli_pkt_slist_es_s {
+                uint64_t es:64;
+        } s;
+        struct cvmx_sli_pkt_slist_es_s cn61xx;
+        struct cvmx_sli_pkt_slist_es_s cn63xx;
+        struct cvmx_sli_pkt_slist_es_s cn63xxp1;
+        struct cvmx_sli_pkt_slist_es_s cn66xx;
+        struct cvmx_sli_pkt_slist_es_s cn68xx;
+        struct cvmx_sli_pkt_slist_es_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_slist_ns {
+        uint64_t u64;
+        struct cvmx_sli_pkt_slist_ns_s {
+                uint64_t reserved_32_63:32;
+                uint64_t nsr:32;
+        } s;
+        struct cvmx_sli_pkt_slist_ns_s cn61xx;
+        struct cvmx_sli_pkt_slist_ns_s cn63xx;
+        struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
+        struct cvmx_sli_pkt_slist_ns_s cn66xx;
+        struct cvmx_sli_pkt_slist_ns_s cn68xx;
+        struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_slist_ror {
+        uint64_t u64;
+        struct cvmx_sli_pkt_slist_ror_s {
+                uint64_t reserved_32_63:32;
+                uint64_t ror:32;
+        } s;
+        struct cvmx_sli_pkt_slist_ror_s cn61xx;
+        struct cvmx_sli_pkt_slist_ror_s cn63xx;
+        struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
+        struct cvmx_sli_pkt_slist_ror_s cn66xx;
+        struct cvmx_sli_pkt_slist_ror_s cn68xx;
+        struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_time_int {
+        uint64_t u64;
+        struct cvmx_sli_pkt_time_int_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_sli_pkt_time_int_s cn61xx;
+        struct cvmx_sli_pkt_time_int_s cn63xx;
+        struct cvmx_sli_pkt_time_int_s cn63xxp1;
+        struct cvmx_sli_pkt_time_int_s cn66xx;
+        struct cvmx_sli_pkt_time_int_s cn68xx;
+        struct cvmx_sli_pkt_time_int_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_time_int_enb {
+        uint64_t u64;
+        struct cvmx_sli_pkt_time_int_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_sli_pkt_time_int_enb_s cn61xx;
+        struct cvmx_sli_pkt_time_int_enb_s cn63xx;
+        struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
+        struct cvmx_sli_pkt_time_int_enb_s cn66xx;
+        struct cvmx_sli_pkt_time_int_enb_s cn68xx;
+        struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
+};
+
+union cvmx_sli_portx_pkind {
+        uint64_t u64;
+        struct cvmx_sli_portx_pkind_s {
+                uint64_t reserved_25_63:39;
+                uint64_t rpk_enb:1;
+                uint64_t reserved_22_23:2;
+                uint64_t pkindr:6;
+                uint64_t reserved_14_15:2;
+                uint64_t bpkind:6;
+                uint64_t reserved_6_7:2;
+                uint64_t pkind:6;
+        } s;
+        struct cvmx_sli_portx_pkind_s cn68xx;
+        struct cvmx_sli_portx_pkind_cn68xxp1 {
+                uint64_t reserved_14_63:50;
+                uint64_t bpkind:6;
+                uint64_t reserved_6_7:2;
+                uint64_t pkind:6;
+        } cn68xxp1;
+};
+
+union cvmx_sli_s2m_portx_ctl {
+        uint64_t u64;
+        struct cvmx_sli_s2m_portx_ctl_s {
+                uint64_t reserved_5_63:59;
+                uint64_t wind_d:1;
+                uint64_t bar0_d:1;
+                uint64_t mrrs:3;
+        } s;
+        struct cvmx_sli_s2m_portx_ctl_s cn61xx;
+        struct cvmx_sli_s2m_portx_ctl_s cn63xx;
+        struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
+        struct cvmx_sli_s2m_portx_ctl_s cn66xx;
+        struct cvmx_sli_s2m_portx_ctl_s cn68xx;
+        struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
+};
+
+union cvmx_sli_scratch_1 {
+        uint64_t u64;
+        struct cvmx_sli_scratch_1_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_scratch_1_s cn61xx;
+        struct cvmx_sli_scratch_1_s cn63xx;
+        struct cvmx_sli_scratch_1_s cn63xxp1;
+        struct cvmx_sli_scratch_1_s cn66xx;
+        struct cvmx_sli_scratch_1_s cn68xx;
+        struct cvmx_sli_scratch_1_s cn68xxp1;
+};
+
+union cvmx_sli_scratch_2 {
+        uint64_t u64;
+        struct cvmx_sli_scratch_2_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_sli_scratch_2_s cn61xx;
+        struct cvmx_sli_scratch_2_s cn63xx;
+        struct cvmx_sli_scratch_2_s cn63xxp1;
+        struct cvmx_sli_scratch_2_s cn66xx;
+        struct cvmx_sli_scratch_2_s cn68xx;
+        struct cvmx_sli_scratch_2_s cn68xxp1;
+};
+
+union cvmx_sli_state1 {
+        uint64_t u64;
+        struct cvmx_sli_state1_s {
+                uint64_t cpl1:12;
+                uint64_t cpl0:12;
+                uint64_t arb:1;
+                uint64_t csr:39;
+        } s;
+        struct cvmx_sli_state1_s cn61xx;
+        struct cvmx_sli_state1_s cn63xx;
+        struct cvmx_sli_state1_s cn63xxp1;
+        struct cvmx_sli_state1_s cn66xx;
+        struct cvmx_sli_state1_s cn68xx;
+        struct cvmx_sli_state1_s cn68xxp1;
+};
+
+union cvmx_sli_state2 {
+        uint64_t u64;
+        struct cvmx_sli_state2_s {
+                uint64_t reserved_56_63:8;
+                uint64_t nnp1:8;
+                uint64_t reserved_47_47:1;
+                uint64_t rac:1;
+                uint64_t csm1:15;
+                uint64_t csm0:15;
+                uint64_t nnp0:8;
+                uint64_t nnd:8;
+        } s;
+        struct cvmx_sli_state2_s cn61xx;
+        struct cvmx_sli_state2_s cn63xx;
+        struct cvmx_sli_state2_s cn63xxp1;
+        struct cvmx_sli_state2_s cn66xx;
+        struct cvmx_sli_state2_s cn68xx;
+        struct cvmx_sli_state2_s cn68xxp1;
+};
+
+union cvmx_sli_state3 {
+        uint64_t u64;
+        struct cvmx_sli_state3_s {
+                uint64_t reserved_56_63:8;
+                uint64_t psm1:15;
+                uint64_t psm0:15;
+                uint64_t nsm1:13;
+                uint64_t nsm0:13;
+        } s;
+        struct cvmx_sli_state3_s cn61xx;
+        struct cvmx_sli_state3_s cn63xx;
+        struct cvmx_sli_state3_s cn63xxp1;
+        struct cvmx_sli_state3_s cn66xx;
+        struct cvmx_sli_state3_s cn68xx;
+        struct cvmx_sli_state3_s cn68xxp1;
+};
+
+union cvmx_sli_tx_pipe {
+        uint64_t u64;
+        struct cvmx_sli_tx_pipe_s {
+                uint64_t reserved_24_63:40;
+                uint64_t nump:8;
+                uint64_t reserved_7_15:9;
+                uint64_t base:7;
+        } s;
+        struct cvmx_sli_tx_pipe_s cn68xx;
+        struct cvmx_sli_tx_pipe_s cn68xxp1;
+};
+
+union cvmx_sli_win_rd_addr {
+        uint64_t u64;
+        struct cvmx_sli_win_rd_addr_s {
+                uint64_t reserved_51_63:13;
+                uint64_t ld_cmd:2;
+                uint64_t iobit:1;
+                uint64_t rd_addr:48;
+        } s;
+        struct cvmx_sli_win_rd_addr_s cn61xx;
+        struct cvmx_sli_win_rd_addr_s cn63xx;
+        struct cvmx_sli_win_rd_addr_s cn63xxp1;
+        struct cvmx_sli_win_rd_addr_s cn66xx;
+        struct cvmx_sli_win_rd_addr_s cn68xx;
+        struct cvmx_sli_win_rd_addr_s cn68xxp1;
+};
+
+union cvmx_sli_win_rd_data {
+        uint64_t u64;
+        struct cvmx_sli_win_rd_data_s {
+                uint64_t rd_data:64;
+        } s;
+        struct cvmx_sli_win_rd_data_s cn61xx;
+        struct cvmx_sli_win_rd_data_s cn63xx;
+        struct cvmx_sli_win_rd_data_s cn63xxp1;
+        struct cvmx_sli_win_rd_data_s cn66xx;
+        struct cvmx_sli_win_rd_data_s cn68xx;
+        struct cvmx_sli_win_rd_data_s cn68xxp1;
+};
+
+union cvmx_sli_win_wr_addr {
+        uint64_t u64;
+        struct cvmx_sli_win_wr_addr_s {
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t wr_addr:45;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_sli_win_wr_addr_s cn61xx;
+        struct cvmx_sli_win_wr_addr_s cn63xx;
+        struct cvmx_sli_win_wr_addr_s cn63xxp1;
+        struct cvmx_sli_win_wr_addr_s cn66xx;
+        struct cvmx_sli_win_wr_addr_s cn68xx;
+        struct cvmx_sli_win_wr_addr_s cn68xxp1;
+};
+
+union cvmx_sli_win_wr_data {
+        uint64_t u64;
+        struct cvmx_sli_win_wr_data_s {
+                uint64_t wr_data:64;
+        } s;
+        struct cvmx_sli_win_wr_data_s cn61xx;
+        struct cvmx_sli_win_wr_data_s cn63xx;
+        struct cvmx_sli_win_wr_data_s cn63xxp1;
+        struct cvmx_sli_win_wr_data_s cn66xx;
+        struct cvmx_sli_win_wr_data_s cn68xx;
+        struct cvmx_sli_win_wr_data_s cn68xxp1;
+};
+
+union cvmx_sli_win_wr_mask {
+        uint64_t u64;
+        struct cvmx_sli_win_wr_mask_s {
+                uint64_t reserved_8_63:56;
+                uint64_t wr_mask:8;
+        } s;
+        struct cvmx_sli_win_wr_mask_s cn61xx;
+        struct cvmx_sli_win_wr_mask_s cn63xx;
+        struct cvmx_sli_win_wr_mask_s cn63xxp1;
+        struct cvmx_sli_win_wr_mask_s cn66xx;
+        struct cvmx_sli_win_wr_mask_s cn68xx;
+        struct cvmx_sli_win_wr_mask_s cn68xxp1;
+};
+
+union cvmx_sli_window_ctl {
+        uint64_t u64;
+        struct cvmx_sli_window_ctl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t time:32;
+        } s;
+        struct cvmx_sli_window_ctl_s cn61xx;
+        struct cvmx_sli_window_ctl_s cn63xx;
+        struct cvmx_sli_window_ctl_s cn63xxp1;
+        struct cvmx_sli_window_ctl_s cn66xx;
+        struct cvmx_sli_window_ctl_s cn68xx;
+        struct cvmx_sli_window_ctl_s cn68xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h
index e814648953a5..e814648953a5 100644
--- a/drivers/staging/octeon/cvmx-spi.h
+++ b/arch/mips/include/asm/octeon/cvmx-spi.h
diff --git a/drivers/staging/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
index b16940e32c83..b16940e32c83 100644
--- a/drivers/staging/octeon/cvmx-spxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
new file mode 100644
index 000000000000..7be7e9ed7465
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
@@ -0,0 +1,1036 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SRIOX_DEFS_H__
+#define __CVMX_SRIOX_DEFS_H__
+
+#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
+
+union cvmx_sriox_acc_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_acc_ctrl_s {
+                uint64_t reserved_7_63:57;
+                uint64_t deny_adr2:1;
+                uint64_t deny_adr1:1;
+                uint64_t deny_adr0:1;
+                uint64_t reserved_3_3:1;
+                uint64_t deny_bar2:1;
+                uint64_t deny_bar1:1;
+                uint64_t deny_bar0:1;
+        } s;
+        struct cvmx_sriox_acc_ctrl_cn63xx {
+                uint64_t reserved_3_63:61;
+                uint64_t deny_bar2:1;
+                uint64_t deny_bar1:1;
+                uint64_t deny_bar0:1;
+        } cn63xx;
+        struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
+        struct cvmx_sriox_acc_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_asmbly_id {
+        uint64_t u64;
+        struct cvmx_sriox_asmbly_id_s {
+                uint64_t reserved_32_63:32;
+                uint64_t assy_id:16;
+                uint64_t assy_ven:16;
+        } s;
+        struct cvmx_sriox_asmbly_id_s cn63xx;
+        struct cvmx_sriox_asmbly_id_s cn63xxp1;
+        struct cvmx_sriox_asmbly_id_s cn66xx;
+};
+
+union cvmx_sriox_asmbly_info {
+        uint64_t u64;
+        struct cvmx_sriox_asmbly_info_s {
+                uint64_t reserved_32_63:32;
+                uint64_t assy_rev:16;
+                uint64_t reserved_0_15:16;
+        } s;
+        struct cvmx_sriox_asmbly_info_s cn63xx;
+        struct cvmx_sriox_asmbly_info_s cn63xxp1;
+        struct cvmx_sriox_asmbly_info_s cn66xx;
+};
+
+union cvmx_sriox_bell_resp_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_bell_resp_ctrl_s {
+                uint64_t reserved_6_63:58;
+                uint64_t rp1_sid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_pid:2;
+        } s;
+        struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
+        struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
+        struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_bist_status {
+        uint64_t u64;
+        struct cvmx_sriox_bist_status_s {
+                uint64_t reserved_45_63:19;
+                uint64_t lram:1;
+                uint64_t mram:2;
+                uint64_t cram:2;
+                uint64_t bell:2;
+                uint64_t otag:2;
+                uint64_t itag:1;
+                uint64_t ofree:1;
+                uint64_t rtn:2;
+                uint64_t obulk:4;
+                uint64_t optrs:4;
+                uint64_t oarb2:2;
+                uint64_t rxbuf2:2;
+                uint64_t oarb:2;
+                uint64_t ispf:1;
+                uint64_t ospf:1;
+                uint64_t txbuf:2;
+                uint64_t rxbuf:2;
+                uint64_t imsg:5;
+                uint64_t omsg:7;
+        } s;
+        struct cvmx_sriox_bist_status_cn63xx {
+                uint64_t reserved_44_63:20;
+                uint64_t mram:2;
+                uint64_t cram:2;
+                uint64_t bell:2;
+                uint64_t otag:2;
+                uint64_t itag:1;
+                uint64_t ofree:1;
+                uint64_t rtn:2;
+                uint64_t obulk:4;
+                uint64_t optrs:4;
+                uint64_t oarb2:2;
+                uint64_t rxbuf2:2;
+                uint64_t oarb:2;
+                uint64_t ispf:1;
+                uint64_t ospf:1;
+                uint64_t txbuf:2;
+                uint64_t rxbuf:2;
+                uint64_t imsg:5;
+                uint64_t omsg:7;
+        } cn63xx;
+        struct cvmx_sriox_bist_status_cn63xxp1 {
+                uint64_t reserved_44_63:20;
+                uint64_t mram:2;
+                uint64_t cram:2;
+                uint64_t bell:2;
+                uint64_t otag:2;
+                uint64_t itag:1;
+                uint64_t ofree:1;
+                uint64_t rtn:2;
+                uint64_t obulk:4;
+                uint64_t optrs:4;
+                uint64_t reserved_20_23:4;
+                uint64_t oarb:2;
+                uint64_t ispf:1;
+                uint64_t ospf:1;
+                uint64_t txbuf:2;
+                uint64_t rxbuf:2;
+                uint64_t imsg:5;
+                uint64_t omsg:7;
+        } cn63xxp1;
+        struct cvmx_sriox_bist_status_s cn66xx;
+};
+
+union cvmx_sriox_imsg_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_ctrl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t to_mode:1;
+                uint64_t reserved_30_30:1;
+                uint64_t rsp_thr:6;
+                uint64_t reserved_22_23:2;
+                uint64_t rp1_sid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_pid:2;
+                uint64_t reserved_15_15:1;
+                uint64_t prt_sel:3;
+                uint64_t lttr:4;
+                uint64_t prio:4;
+                uint64_t mbox:4;
+        } s;
+        struct cvmx_sriox_imsg_ctrl_s cn63xx;
+        struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
+        struct cvmx_sriox_imsg_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_imsg_inst_hdrx {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_inst_hdrx_s {
+                uint64_t r:1;
+                uint64_t reserved_58_62:5;
+                uint64_t pm:2;
+                uint64_t reserved_55_55:1;
+                uint64_t sl:7;
+                uint64_t reserved_46_47:2;
+                uint64_t nqos:1;
+                uint64_t ngrp:1;
+                uint64_t ntt:1;
+                uint64_t ntag:1;
+                uint64_t reserved_35_41:7;
+                uint64_t rs:1;
+                uint64_t tt:2;
+                uint64_t tag:32;
+        } s;
+        struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
+        struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
+        struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
+};
+
+union cvmx_sriox_imsg_qos_grpx {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_qos_grpx_s {
+                uint64_t reserved_63_63:1;
+                uint64_t qos7:3;
+                uint64_t grp7:4;
+                uint64_t reserved_55_55:1;
+                uint64_t qos6:3;
+                uint64_t grp6:4;
+                uint64_t reserved_47_47:1;
+                uint64_t qos5:3;
+                uint64_t grp5:4;
+                uint64_t reserved_39_39:1;
+                uint64_t qos4:3;
+                uint64_t grp4:4;
+                uint64_t reserved_31_31:1;
+                uint64_t qos3:3;
+                uint64_t grp3:4;
+                uint64_t reserved_23_23:1;
+                uint64_t qos2:3;
+                uint64_t grp2:4;
+                uint64_t reserved_15_15:1;
+                uint64_t qos1:3;
+                uint64_t grp1:4;
+                uint64_t reserved_7_7:1;
+                uint64_t qos0:3;
+                uint64_t grp0:4;
+        } s;
+        struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
+        struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
+        struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
+};
+
+union cvmx_sriox_imsg_statusx {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_statusx_s {
+                uint64_t val1:1;
+                uint64_t err1:1;
+                uint64_t toe1:1;
+                uint64_t toc1:1;
+                uint64_t prt1:1;
+                uint64_t reserved_58_58:1;
+                uint64_t tt1:1;
+                uint64_t dis1:1;
+                uint64_t seg1:4;
+                uint64_t mbox1:2;
+                uint64_t lttr1:2;
+                uint64_t sid1:16;
+                uint64_t val0:1;
+                uint64_t err0:1;
+                uint64_t toe0:1;
+                uint64_t toc0:1;
+                uint64_t prt0:1;
+                uint64_t reserved_26_26:1;
+                uint64_t tt0:1;
+                uint64_t dis0:1;
+                uint64_t seg0:4;
+                uint64_t mbox0:2;
+                uint64_t lttr0:2;
+                uint64_t sid0:16;
+        } s;
+        struct cvmx_sriox_imsg_statusx_s cn63xx;
+        struct cvmx_sriox_imsg_statusx_s cn63xxp1;
+        struct cvmx_sriox_imsg_statusx_s cn66xx;
+};
+
+union cvmx_sriox_imsg_vport_thr {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_vport_thr_s {
+                uint64_t reserved_54_63:10;
+                uint64_t max_tot:6;
+                uint64_t reserved_46_47:2;
+                uint64_t max_s1:6;
+                uint64_t reserved_38_39:2;
+                uint64_t max_s0:6;
+                uint64_t sp_vport:1;
+                uint64_t reserved_20_30:11;
+                uint64_t buf_thr:4;
+                uint64_t reserved_14_15:2;
+                uint64_t max_p1:6;
+                uint64_t reserved_6_7:2;
+                uint64_t max_p0:6;
+        } s;
+        struct cvmx_sriox_imsg_vport_thr_s cn63xx;
+        struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
+        struct cvmx_sriox_imsg_vport_thr_s cn66xx;
+};
+
+union cvmx_sriox_imsg_vport_thr2 {
+        uint64_t u64;
+        struct cvmx_sriox_imsg_vport_thr2_s {
+                uint64_t reserved_46_63:18;
+                uint64_t max_s3:6;
+                uint64_t reserved_38_39:2;
+                uint64_t max_s2:6;
+                uint64_t reserved_0_31:32;
+        } s;
+        struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
+};
+
+union cvmx_sriox_int2_enable {
+        uint64_t u64;
+        struct cvmx_sriox_int2_enable_s {
+                uint64_t reserved_1_63:63;
+                uint64_t pko_rst:1;
+        } s;
+        struct cvmx_sriox_int2_enable_s cn63xx;
+        struct cvmx_sriox_int2_enable_s cn66xx;
+};
+
+union cvmx_sriox_int2_reg {
+        uint64_t u64;
+        struct cvmx_sriox_int2_reg_s {
+                uint64_t reserved_32_63:32;
+                uint64_t int_sum:1;
+                uint64_t reserved_1_30:30;
+                uint64_t pko_rst:1;
+        } s;
+        struct cvmx_sriox_int2_reg_s cn63xx;
+        struct cvmx_sriox_int2_reg_s cn66xx;
+};
+
+union cvmx_sriox_int_enable {
+        uint64_t u64;
+        struct cvmx_sriox_int_enable_s {
+                uint64_t reserved_27_63:37;
+                uint64_t zero_pkt:1;
+                uint64_t ttl_tout:1;
+                uint64_t fail:1;
+                uint64_t degrade:1;
+                uint64_t mac_buf:1;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+        } s;
+        struct cvmx_sriox_int_enable_s cn63xx;
+        struct cvmx_sriox_int_enable_cn63xxp1 {
+                uint64_t reserved_22_63:42;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+        } cn63xxp1;
+        struct cvmx_sriox_int_enable_s cn66xx;
+};
+
+union cvmx_sriox_int_info0 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info0_s {
+                uint64_t cmd:4;
+                uint64_t type:4;
+                uint64_t tag:8;
+                uint64_t reserved_42_47:6;
+                uint64_t length:10;
+                uint64_t status:3;
+                uint64_t reserved_16_28:13;
+                uint64_t be0:8;
+                uint64_t be1:8;
+        } s;
+        struct cvmx_sriox_int_info0_s cn63xx;
+        struct cvmx_sriox_int_info0_s cn63xxp1;
+        struct cvmx_sriox_int_info0_s cn66xx;
+};
+
+union cvmx_sriox_int_info1 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info1_s {
+                uint64_t info1:64;
+        } s;
+        struct cvmx_sriox_int_info1_s cn63xx;
+        struct cvmx_sriox_int_info1_s cn63xxp1;
+        struct cvmx_sriox_int_info1_s cn66xx;
+};
+
+union cvmx_sriox_int_info2 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info2_s {
+                uint64_t prio:2;
+                uint64_t tt:1;
+                uint64_t sis:1;
+                uint64_t ssize:4;
+                uint64_t did:16;
+                uint64_t xmbox:4;
+                uint64_t mbox:2;
+                uint64_t letter:2;
+                uint64_t rsrvd:30;
+                uint64_t lns:1;
+                uint64_t intr:1;
+        } s;
+        struct cvmx_sriox_int_info2_s cn63xx;
+        struct cvmx_sriox_int_info2_s cn63xxp1;
+        struct cvmx_sriox_int_info2_s cn66xx;
+};
+
+union cvmx_sriox_int_info3 {
+        uint64_t u64;
+        struct cvmx_sriox_int_info3_s {
+                uint64_t prio:2;
+                uint64_t tt:2;
+                uint64_t type:4;
+                uint64_t other:48;
+                uint64_t reserved_0_7:8;
+        } s;
+        struct cvmx_sriox_int_info3_s cn63xx;
+        struct cvmx_sriox_int_info3_s cn63xxp1;
+        struct cvmx_sriox_int_info3_s cn66xx;
+};
+
+union cvmx_sriox_int_reg {
+        uint64_t u64;
+        struct cvmx_sriox_int_reg_s {
+                uint64_t reserved_32_63:32;
+                uint64_t int2_sum:1;
+                uint64_t reserved_27_30:4;
+                uint64_t zero_pkt:1;
+                uint64_t ttl_tout:1;
+                uint64_t fail:1;
+                uint64_t degrad:1;
+                uint64_t mac_buf:1;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+        } s;
+        struct cvmx_sriox_int_reg_s cn63xx;
+        struct cvmx_sriox_int_reg_cn63xxp1 {
+                uint64_t reserved_22_63:42;
+                uint64_t f_error:1;
+                uint64_t rtry_err:1;
+                uint64_t pko_err:1;
+                uint64_t omsg_err:1;
+                uint64_t omsg1:1;
+                uint64_t omsg0:1;
+                uint64_t link_up:1;
+                uint64_t link_dwn:1;
+                uint64_t phy_erb:1;
+                uint64_t log_erb:1;
+                uint64_t soft_rx:1;
+                uint64_t soft_tx:1;
+                uint64_t mce_rx:1;
+                uint64_t mce_tx:1;
+                uint64_t wr_done:1;
+                uint64_t sli_err:1;
+                uint64_t deny_wr:1;
+                uint64_t bar_err:1;
+                uint64_t maint_op:1;
+                uint64_t rxbell:1;
+                uint64_t bell_err:1;
+                uint64_t txbell:1;
+        } cn63xxp1;
+        struct cvmx_sriox_int_reg_s cn66xx;
+};
+
+union cvmx_sriox_ip_feature {
+        uint64_t u64;
+        struct cvmx_sriox_ip_feature_s {
+                uint64_t ops:32;
+                uint64_t reserved_15_31:17;
+                uint64_t no_vmin:1;
+                uint64_t a66:1;
+                uint64_t a50:1;
+                uint64_t reserved_11_11:1;
+                uint64_t tx_flow:1;
+                uint64_t pt_width:2;
+                uint64_t tx_pol:4;
+                uint64_t rx_pol:4;
+        } s;
+        struct cvmx_sriox_ip_feature_cn63xx {
+                uint64_t ops:32;
+                uint64_t reserved_14_31:18;
+                uint64_t a66:1;
+                uint64_t a50:1;
+                uint64_t reserved_11_11:1;
+                uint64_t tx_flow:1;
+                uint64_t pt_width:2;
+                uint64_t tx_pol:4;
+                uint64_t rx_pol:4;
+        } cn63xx;
+        struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
+        struct cvmx_sriox_ip_feature_s cn66xx;
+};
+
+union cvmx_sriox_mac_buffers {
+        uint64_t u64;
+        struct cvmx_sriox_mac_buffers_s {
+                uint64_t reserved_56_63:8;
+                uint64_t tx_enb:8;
+                uint64_t reserved_44_47:4;
+                uint64_t tx_inuse:4;
+                uint64_t tx_stat:8;
+                uint64_t reserved_24_31:8;
+                uint64_t rx_enb:8;
+                uint64_t reserved_12_15:4;
+                uint64_t rx_inuse:4;
+                uint64_t rx_stat:8;
+        } s;
+        struct cvmx_sriox_mac_buffers_s cn63xx;
+        struct cvmx_sriox_mac_buffers_s cn66xx;
+};
+
+union cvmx_sriox_maint_op {
+        uint64_t u64;
+        struct cvmx_sriox_maint_op_s {
+                uint64_t wr_data:32;
+                uint64_t reserved_27_31:5;
+                uint64_t fail:1;
+                uint64_t pending:1;
+                uint64_t op:1;
+                uint64_t addr:24;
+        } s;
+        struct cvmx_sriox_maint_op_s cn63xx;
+        struct cvmx_sriox_maint_op_s cn63xxp1;
+        struct cvmx_sriox_maint_op_s cn66xx;
+};
+
+union cvmx_sriox_maint_rd_data {
+        uint64_t u64;
+        struct cvmx_sriox_maint_rd_data_s {
+                uint64_t reserved_33_63:31;
+                uint64_t valid:1;
+                uint64_t rd_data:32;
+        } s;
+        struct cvmx_sriox_maint_rd_data_s cn63xx;
+        struct cvmx_sriox_maint_rd_data_s cn63xxp1;
+        struct cvmx_sriox_maint_rd_data_s cn66xx;
+};
+
+union cvmx_sriox_mce_tx_ctl {
+        uint64_t u64;
+        struct cvmx_sriox_mce_tx_ctl_s {
+                uint64_t reserved_1_63:63;
+                uint64_t mce:1;
+        } s;
+        struct cvmx_sriox_mce_tx_ctl_s cn63xx;
+        struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
+        struct cvmx_sriox_mce_tx_ctl_s cn66xx;
+};
+
+union cvmx_sriox_mem_op_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_mem_op_ctrl_s {
+                uint64_t reserved_10_63:54;
+                uint64_t rr_ro:1;
+                uint64_t w_ro:1;
+                uint64_t reserved_6_7:2;
+                uint64_t rp1_sid:1;
+                uint64_t rp0_sid:2;
+                uint64_t rp1_pid:1;
+                uint64_t rp0_pid:2;
+        } s;
+        struct cvmx_sriox_mem_op_ctrl_s cn63xx;
+        struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
+        struct cvmx_sriox_mem_op_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_omsg_ctrlx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_ctrlx_s {
+                uint64_t testmode:1;
+                uint64_t reserved_37_62:26;
+                uint64_t silo_max:5;
+                uint64_t rtry_thr:16;
+                uint64_t rtry_en:1;
+                uint64_t reserved_11_14:4;
+                uint64_t idm_tt:1;
+                uint64_t idm_sis:1;
+                uint64_t idm_did:1;
+                uint64_t lttr_sp:4;
+                uint64_t lttr_mp:4;
+        } s;
+        struct cvmx_sriox_omsg_ctrlx_s cn63xx;
+        struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
+                uint64_t testmode:1;
+                uint64_t reserved_32_62:31;
+                uint64_t rtry_thr:16;
+                uint64_t rtry_en:1;
+                uint64_t reserved_11_14:4;
+                uint64_t idm_tt:1;
+                uint64_t idm_sis:1;
+                uint64_t idm_did:1;
+                uint64_t lttr_sp:4;
+                uint64_t lttr_mp:4;
+        } cn63xxp1;
+        struct cvmx_sriox_omsg_ctrlx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_done_countsx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_done_countsx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bad:16;
+                uint64_t good:16;
+        } s;
+        struct cvmx_sriox_omsg_done_countsx_s cn63xx;
+        struct cvmx_sriox_omsg_done_countsx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_fmp_mrx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_fmp_mrx_s {
+                uint64_t reserved_15_63:49;
+                uint64_t ctlr_sp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t id_sp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_nmp:1;
+                uint64_t id_psd:1;
+                uint64_t mbox_sp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_nmp:1;
+                uint64_t mbox_psd:1;
+                uint64_t all_sp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_nmp:1;
+                uint64_t all_psd:1;
+        } s;
+        struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
+        struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
+        struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_nmp_mrx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_nmp_mrx_s {
+                uint64_t reserved_15_63:49;
+                uint64_t ctlr_sp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t id_sp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_nmp:1;
+                uint64_t reserved_8_8:1;
+                uint64_t mbox_sp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_nmp:1;
+                uint64_t reserved_4_4:1;
+                uint64_t all_sp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_nmp:1;
+                uint64_t reserved_0_0:1;
+        } s;
+        struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
+        struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
+        struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_portx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_portx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t enable:1;
+                uint64_t reserved_3_30:28;
+                uint64_t port:3;
+        } s;
+        struct cvmx_sriox_omsg_portx_cn63xx {
+                uint64_t reserved_32_63:32;
+                uint64_t enable:1;
+                uint64_t reserved_2_30:29;
+                uint64_t port:2;
+        } cn63xx;
+        struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
+        struct cvmx_sriox_omsg_portx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_silo_thr {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_silo_thr_s {
+                uint64_t reserved_5_63:59;
+                uint64_t tot_silo:5;
+        } s;
+        struct cvmx_sriox_omsg_silo_thr_s cn63xx;
+        struct cvmx_sriox_omsg_silo_thr_s cn66xx;
+};
+
+union cvmx_sriox_omsg_sp_mrx {
+        uint64_t u64;
+        struct cvmx_sriox_omsg_sp_mrx_s {
+                uint64_t reserved_16_63:48;
+                uint64_t xmbox_sp:1;
+                uint64_t ctlr_sp:1;
+                uint64_t ctlr_fmp:1;
+                uint64_t ctlr_nmp:1;
+                uint64_t id_sp:1;
+                uint64_t id_fmp:1;
+                uint64_t id_nmp:1;
+                uint64_t id_psd:1;
+                uint64_t mbox_sp:1;
+                uint64_t mbox_fmp:1;
+                uint64_t mbox_nmp:1;
+                uint64_t mbox_psd:1;
+                uint64_t all_sp:1;
+                uint64_t all_fmp:1;
+                uint64_t all_nmp:1;
+                uint64_t all_psd:1;
+        } s;
+        struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
+        struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
+        struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
+};
+
+union cvmx_sriox_priox_in_use {
+        uint64_t u64;
+        struct cvmx_sriox_priox_in_use_s {
+                uint64_t reserved_32_63:32;
+                uint64_t end_cnt:16;
+                uint64_t start_cnt:16;
+        } s;
+        struct cvmx_sriox_priox_in_use_s cn63xx;
+        struct cvmx_sriox_priox_in_use_s cn66xx;
+};
+
+union cvmx_sriox_rx_bell {
+        uint64_t u64;
+        struct cvmx_sriox_rx_bell_s {
+                uint64_t reserved_48_63:16;
+                uint64_t data:16;
+                uint64_t src_id:16;
+                uint64_t count:8;
+                uint64_t reserved_5_7:3;
+                uint64_t dest_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_2:1;
+                uint64_t priority:2;
+        } s;
+        struct cvmx_sriox_rx_bell_s cn63xx;
+        struct cvmx_sriox_rx_bell_s cn63xxp1;
+        struct cvmx_sriox_rx_bell_s cn66xx;
+};
+
+union cvmx_sriox_rx_bell_seq {
+        uint64_t u64;
+        struct cvmx_sriox_rx_bell_seq_s {
+                uint64_t reserved_40_63:24;
+                uint64_t count:8;
+                uint64_t seq:32;
+        } s;
+        struct cvmx_sriox_rx_bell_seq_s cn63xx;
+        struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
+        struct cvmx_sriox_rx_bell_seq_s cn66xx;
+};
+
+union cvmx_sriox_rx_status {
+        uint64_t u64;
+        struct cvmx_sriox_rx_status_s {
+                uint64_t rtn_pr3:8;
+                uint64_t rtn_pr2:8;
+                uint64_t rtn_pr1:8;
+                uint64_t reserved_28_39:12;
+                uint64_t mbox:4;
+                uint64_t comp:8;
+                uint64_t reserved_13_15:3;
+                uint64_t n_post:5;
+                uint64_t post:8;
+        } s;
+        struct cvmx_sriox_rx_status_s cn63xx;
+        struct cvmx_sriox_rx_status_s cn63xxp1;
+        struct cvmx_sriox_rx_status_s cn66xx;
+};
+
+union cvmx_sriox_s2m_typex {
+        uint64_t u64;
+        struct cvmx_sriox_s2m_typex_s {
+                uint64_t reserved_19_63:45;
+                uint64_t wr_op:3;
+                uint64_t reserved_15_15:1;
+                uint64_t rd_op:3;
+                uint64_t wr_prior:2;
+                uint64_t rd_prior:2;
+                uint64_t reserved_6_7:2;
+                uint64_t src_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_3:2;
+                uint64_t iaow_sel:2;
+        } s;
+        struct cvmx_sriox_s2m_typex_s cn63xx;
+        struct cvmx_sriox_s2m_typex_s cn63xxp1;
+        struct cvmx_sriox_s2m_typex_s cn66xx;
+};
+
+union cvmx_sriox_seq {
+        uint64_t u64;
+        struct cvmx_sriox_seq_s {
+                uint64_t reserved_32_63:32;
+                uint64_t seq:32;
+        } s;
+        struct cvmx_sriox_seq_s cn63xx;
+        struct cvmx_sriox_seq_s cn63xxp1;
+        struct cvmx_sriox_seq_s cn66xx;
+};
+
+union cvmx_sriox_status_reg {
+        uint64_t u64;
+        struct cvmx_sriox_status_reg_s {
+                uint64_t reserved_2_63:62;
+                uint64_t access:1;
+                uint64_t srio:1;
+        } s;
+        struct cvmx_sriox_status_reg_s cn63xx;
+        struct cvmx_sriox_status_reg_s cn63xxp1;
+        struct cvmx_sriox_status_reg_s cn66xx;
+};
+
+union cvmx_sriox_tag_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_tag_ctrl_s {
+                uint64_t reserved_17_63:47;
+                uint64_t o_clr:1;
+                uint64_t reserved_13_15:3;
+                uint64_t otag:5;
+                uint64_t reserved_5_7:3;
+                uint64_t itag:5;
+        } s;
+        struct cvmx_sriox_tag_ctrl_s cn63xx;
+        struct cvmx_sriox_tag_ctrl_s cn63xxp1;
+        struct cvmx_sriox_tag_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_tlp_credits {
+        uint64_t u64;
+        struct cvmx_sriox_tlp_credits_s {
+                uint64_t reserved_28_63:36;
+                uint64_t mbox:4;
+                uint64_t comp:8;
+                uint64_t reserved_13_15:3;
+                uint64_t n_post:5;
+                uint64_t post:8;
+        } s;
+        struct cvmx_sriox_tlp_credits_s cn63xx;
+        struct cvmx_sriox_tlp_credits_s cn63xxp1;
+        struct cvmx_sriox_tlp_credits_s cn66xx;
+};
+
+union cvmx_sriox_tx_bell {
+        uint64_t u64;
+        struct cvmx_sriox_tx_bell_s {
+                uint64_t reserved_48_63:16;
+                uint64_t data:16;
+                uint64_t dest_id:16;
+                uint64_t reserved_9_15:7;
+                uint64_t pending:1;
+                uint64_t reserved_5_7:3;
+                uint64_t src_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_2:1;
+                uint64_t priority:2;
+        } s;
+        struct cvmx_sriox_tx_bell_s cn63xx;
+        struct cvmx_sriox_tx_bell_s cn63xxp1;
+        struct cvmx_sriox_tx_bell_s cn66xx;
+};
+
+union cvmx_sriox_tx_bell_info {
+        uint64_t u64;
+        struct cvmx_sriox_tx_bell_info_s {
+                uint64_t reserved_48_63:16;
+                uint64_t data:16;
+                uint64_t dest_id:16;
+                uint64_t reserved_8_15:8;
+                uint64_t timeout:1;
+                uint64_t error:1;
+                uint64_t retry:1;
+                uint64_t src_id:1;
+                uint64_t id16:1;
+                uint64_t reserved_2_2:1;
+                uint64_t priority:2;
+        } s;
+        struct cvmx_sriox_tx_bell_info_s cn63xx;
+        struct cvmx_sriox_tx_bell_info_s cn63xxp1;
+        struct cvmx_sriox_tx_bell_info_s cn66xx;
+};
+
+union cvmx_sriox_tx_ctrl {
+        uint64_t u64;
+        struct cvmx_sriox_tx_ctrl_s {
+                uint64_t reserved_53_63:11;
+                uint64_t tag_th2:5;
+                uint64_t reserved_45_47:3;
+                uint64_t tag_th1:5;
+                uint64_t reserved_37_39:3;
+                uint64_t tag_th0:5;
+                uint64_t reserved_20_31:12;
+                uint64_t tx_th2:4;
+                uint64_t reserved_12_15:4;
+                uint64_t tx_th1:4;
+                uint64_t reserved_4_7:4;
+                uint64_t tx_th0:4;
+        } s;
+        struct cvmx_sriox_tx_ctrl_s cn63xx;
+        struct cvmx_sriox_tx_ctrl_s cn63xxp1;
+        struct cvmx_sriox_tx_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_tx_emphasis {
+        uint64_t u64;
+        struct cvmx_sriox_tx_emphasis_s {
+                uint64_t reserved_4_63:60;
+                uint64_t emph:4;
+        } s;
+        struct cvmx_sriox_tx_emphasis_s cn63xx;
+        struct cvmx_sriox_tx_emphasis_s cn66xx;
+};
+
+union cvmx_sriox_tx_status {
+        uint64_t u64;
+        struct cvmx_sriox_tx_status_s {
+                uint64_t reserved_32_63:32;
+                uint64_t s2m_pr3:8;
+                uint64_t s2m_pr2:8;
+                uint64_t s2m_pr1:8;
+                uint64_t s2m_pr0:8;
+        } s;
+        struct cvmx_sriox_tx_status_s cn63xx;
+        struct cvmx_sriox_tx_status_s cn63xxp1;
+        struct cvmx_sriox_tx_status_s cn66xx;
+};
+
+union cvmx_sriox_wr_done_counts {
+        uint64_t u64;
+        struct cvmx_sriox_wr_done_counts_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bad:16;
+                uint64_t good:16;
+        } s;
+        struct cvmx_sriox_wr_done_counts_s cn63xx;
+        struct cvmx_sriox_wr_done_counts_s cn66xx;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
index d82b366c279f..d82b366c279f 100644
--- a/drivers/staging/octeon/cvmx-srxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
diff --git a/drivers/staging/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
index 4f209b62cae1..4f209b62cae1 100644
--- a/drivers/staging/octeon/cvmx-stxx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
diff --git a/drivers/staging/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
index 653610953d28..653610953d28 100644
--- a/drivers/staging/octeon/cvmx-wqe.h
+++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 7e1286706d46..740be97a3251 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -31,6 +31,27 @@
 #include <linux/kernel.h>
 #include <linux/string.h>
 
+enum cvmx_mips_space {
+        CVMX_MIPS_SPACE_XKSEG = 3LL,
+        CVMX_MIPS_SPACE_XKPHYS = 2LL,
+        CVMX_MIPS_SPACE_XSSEG = 1LL,
+        CVMX_MIPS_SPACE_XUSEG = 0LL
+};
+
+/* These macros for use when using 32 bit pointers. */
+#define CVMX_MIPS32_SPACE_KSEG0 1l
+#define CVMX_ADD_SEG32(segment, add) \
+        (((int32_t)segment << 31) | (int32_t)(add))
+
+#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
+
+/* These macros simplify the process of creating common IO addresses */
+#define CVMX_ADD_SEG(segment, add) \
+        ((((uint64_t)segment) << 62) | (add))
+#ifndef CVMX_ADD_IO_SEG
+#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
+#endif
+
 #include "cvmx-asm.h"
 #include "cvmx-packet.h"
 #include "cvmx-sysinfo.h"
@@ -129,27 +150,6 @@ static inline uint64_t cvmx_build_bits(uint64_t high_bit,
         return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
 }
 
-enum cvmx_mips_space {
-        CVMX_MIPS_SPACE_XKSEG = 3LL,
-        CVMX_MIPS_SPACE_XKPHYS = 2LL,
-        CVMX_MIPS_SPACE_XSSEG = 1LL,
-        CVMX_MIPS_SPACE_XUSEG = 0LL
-};
-
-/* These macros for use when using 32 bit pointers. */
-#define CVMX_MIPS32_SPACE_KSEG0 1l
-#define CVMX_ADD_SEG32(segment, add) \
-        (((int32_t)segment << 31) | (int32_t)(add))
-
-#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
-
-/* These macros simplify the process of creating common IO addresses */
-#define CVMX_ADD_SEG(segment, add) \
-        ((((uint64_t)segment) << 62) | (add))
-#ifndef CVMX_ADD_IO_SEG
-#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
-#endif
-
 /**
  * Convert a memory pointer (void*) into a hardware compatible
  * memory address (uint64_t). Octeon hardware widgets don't
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index cba6fbed9f43..8008da2f8779 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -31,8 +31,14 @@
 
 #ifndef __OCTEON_FEATURE_H__
 #define __OCTEON_FEATURE_H__
+#include <asm/octeon/cvmx-mio-defs.h>
+#include <asm/octeon/cvmx-rnm-defs.h>
 
 enum octeon_feature {
+        /* CN68XX uses port kinds for packet interface */
+        OCTEON_FEATURE_PKND,
+        /* CN68XX has different fields in word0 - word2 */
+        OCTEON_FEATURE_CN68XX_WQE,
         /*
          * Octeon models in the CN5XXX family and higher support
          * atomic add instructions to memory (saa/saad).
@@ -42,8 +48,13 @@ enum octeon_feature {
         OCTEON_FEATURE_ZIP,
         /* Does this Octeon support crypto acceleration using COP2? */
         OCTEON_FEATURE_CRYPTO,
+        OCTEON_FEATURE_DORM_CRYPTO,
         /* Does this Octeon support PCI express? */
         OCTEON_FEATURE_PCIE,
+        /* Does this Octeon support SRIOs */
+        OCTEON_FEATURE_SRIO,
+        /*  Does this Octeon support Interlaken */
+        OCTEON_FEATURE_ILK,
         /* Some Octeon models support internal memory for storing
          * cryptographic keys */
         OCTEON_FEATURE_KEY_MEMORY,
@@ -64,6 +75,15 @@ enum octeon_feature {
         /* Octeon MDIO block supports clause 45 transactions for 10
          * Gig support */
         OCTEON_FEATURE_MDIO_CLAUSE_45,
+        /*
+         *  CN52XX and CN56XX used a block named NPEI for PCIe
+         *  access. Newer chips replaced this with SLI+DPI.
+         */
+        OCTEON_FEATURE_NPEI,
+        OCTEON_FEATURE_HFA,
+        OCTEON_FEATURE_DFM,
+        OCTEON_FEATURE_CIU2,
+        OCTEON_MAX_FEATURE
 };
 
 static inline int cvmx_fuse_read(int fuse);
@@ -96,30 +116,78 @@ static inline int octeon_has_feature(enum octeon_feature feature)
                         return !cvmx_fuse_read(121);
 
         case OCTEON_FEATURE_CRYPTO:
-                return !cvmx_fuse_read(90);
+                if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                        union cvmx_mio_fus_dat2 fus_2;
+                        fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+                        if (fus_2.s.nocrypto || fus_2.s.nomul) {
+                                return 0;
+                        } else if (!fus_2.s.dorm_crypto) {
+                                return 1;
+                        } else {
+                                union cvmx_rnm_ctl_status st;
+                                st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
+                                return st.s.eer_val;
+                        }
+                } else {
+                        return !cvmx_fuse_read(90);
+                }
+
+        case OCTEON_FEATURE_DORM_CRYPTO:
+                if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                        union cvmx_mio_fus_dat2 fus_2;
+                        fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+                        return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
+                } else {
+                        return 0;
+                }
 
         case OCTEON_FEATURE_PCIE:
-        case OCTEON_FEATURE_MGMT_PORT:
-        case OCTEON_FEATURE_RAID:
                 return OCTEON_IS_MODEL(OCTEON_CN56XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN52XX);
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
+        case OCTEON_FEATURE_SRIO:
+                return OCTEON_IS_MODEL(OCTEON_CN63XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN66XX);
+
+        case OCTEON_FEATURE_ILK:
+                return (OCTEON_IS_MODEL(OCTEON_CN68XX));
 
         case OCTEON_FEATURE_KEY_MEMORY:
+                return OCTEON_IS_MODEL(OCTEON_CN38XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN58XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
         case OCTEON_FEATURE_LED_CONTROLLER:
                 return OCTEON_IS_MODEL(OCTEON_CN38XX)
                         || OCTEON_IS_MODEL(OCTEON_CN58XX)
                         || OCTEON_IS_MODEL(OCTEON_CN56XX);
+
         case OCTEON_FEATURE_TRA:
                 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
                          || OCTEON_IS_MODEL(OCTEON_CN50XX));
+        case OCTEON_FEATURE_MGMT_PORT:
+                return OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
+        case OCTEON_FEATURE_RAID:
+                return OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
         case OCTEON_FEATURE_USB:
                 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
                          || OCTEON_IS_MODEL(OCTEON_CN58XX));
+
         case OCTEON_FEATURE_NO_WPTR:
                 return (OCTEON_IS_MODEL(OCTEON_CN56XX)
-                         || OCTEON_IS_MODEL(OCTEON_CN52XX))
-                        && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
-                        && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN6XXX))
+                          && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
+                          && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+
         case OCTEON_FEATURE_DFA:
                 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
                     && !OCTEON_IS_MODEL(OCTEON_CN31XX)
@@ -127,14 +195,42 @@ static inline int octeon_has_feature(enum octeon_feature feature)
                         return 0;
                 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
                         return 0;
-                else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
-                        return 1;
                 else
                         return !cvmx_fuse_read(120);
+
+        case OCTEON_FEATURE_HFA:
+                if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
+                        return 0;
+                else
+                        return !cvmx_fuse_read(90);
+
+        case OCTEON_FEATURE_DFM:
+                if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)
+                      || OCTEON_IS_MODEL(OCTEON_CN66XX)))
+                        return 0;
+                else
+                        return !cvmx_fuse_read(90);
+
         case OCTEON_FEATURE_MDIO_CLAUSE_45:
                 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
                          || OCTEON_IS_MODEL(OCTEON_CN58XX)
                          || OCTEON_IS_MODEL(OCTEON_CN50XX));
+
+        case OCTEON_FEATURE_NPEI:
+                return OCTEON_IS_MODEL(OCTEON_CN56XX)
+                        || OCTEON_IS_MODEL(OCTEON_CN52XX);
+
+        case OCTEON_FEATURE_PKND:
+                return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+        case OCTEON_FEATURE_CN68XX_WQE:
+                return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+        case OCTEON_FEATURE_CIU2:
+                return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+        default:
+                break;
         }
         return 0;
 }
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index 700f88e31cad..4e338a4d9424 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -24,14 +24,6 @@
  * This file may also be available under a different license from Cavium.
  * Contact Cavium Networks for more information
  ***********************license end**************************************/
-
-/*
- *
- * File defining different Octeon model IDs and macros to
- * compare them.
- *
- */
-
 #ifndef __OCTEON_MODEL_H__
 #define __OCTEON_MODEL_H__
 
@@ -52,6 +44,8 @@
  * for internal use only, and may change without notice.
  */
 
+#define OCTEON_FAMILY_MASK      0x00ffff00
+
 /* Flag bits in top byte */
 /* Ignores revision in model checks */
 #define OM_IGNORE_REVISION        0x01000000
@@ -63,21 +57,48 @@
 #define OM_IGNORE_MINOR_REVISION  0x08000000
 #define OM_FLAG_MASK              0xff000000
 
-#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000 /* Match all cn5XXX Octeon models. */
-#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000 /* Match all cn6XXX Octeon models. */
+/* Match all cn5XXX Octeon models. */
+#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000
+/* Match all cn6XXX Octeon models. */
+#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000
 
 /*
  * CN6XXX models with new revision encoding
  */
+#define OCTEON_CN68XX_PASS1_0   0x000d9100
+#define OCTEON_CN68XX_PASS1_1   0x000d9101
+#define OCTEON_CN68XX_PASS1_2   0x000d9102
+#define OCTEON_CN68XX_PASS2_0   0x000d9108
+
+#define OCTEON_CN68XX           (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN68XX_PASS1_X   (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN68XX_PASS2_X   (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+
+#define OCTEON_CN68XX_PASS1     OCTEON_CN68XX_PASS1_X
+#define OCTEON_CN68XX_PASS2     OCTEON_CN68XX_PASS2_X
+
+#define OCTEON_CN66XX_PASS1_0   0x000d9200
+#define OCTEON_CN66XX_PASS1_2   0x000d9202
+
+#define OCTEON_CN66XX           (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN66XX_PASS1_X   (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+
 #define OCTEON_CN63XX_PASS1_0   0x000d9000
 #define OCTEON_CN63XX_PASS1_1   0x000d9001
 #define OCTEON_CN63XX_PASS1_2   0x000d9002
 #define OCTEON_CN63XX_PASS2_0   0x000d9008
+#define OCTEON_CN63XX_PASS2_1   0x000d9009
+#define OCTEON_CN63XX_PASS2_2   0x000d900a
 
 #define OCTEON_CN63XX           (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
 #define OCTEON_CN63XX_PASS1_X   (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN63XX_PASS2_X   (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
 
+#define OCTEON_CN61XX_PASS1_0   0x000d9300
+
+#define OCTEON_CN61XX           (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN61XX_PASS1_X   (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+
 /*
  * CN5XXX models with new revision encoding
  */
@@ -90,10 +111,8 @@
 #define OCTEON_CN58XX_PASS2_3   0x000d030b
 
 #define OCTEON_CN58XX           (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN58XX_PASS1_X   (OCTEON_CN58XX_PASS1_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN58XX_PASS2_X   (OCTEON_CN58XX_PASS2_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS1_X   (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS2_X   (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN58XX_PASS1     OCTEON_CN58XX_PASS1_X
 #define OCTEON_CN58XX_PASS2     OCTEON_CN58XX_PASS2_X
 
@@ -103,10 +122,8 @@
 #define OCTEON_CN56XX_PASS2_1   0x000d0409
 
 #define OCTEON_CN56XX           (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN56XX_PASS1_X   (OCTEON_CN56XX_PASS1_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN56XX_PASS2_X   (OCTEON_CN56XX_PASS2_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS1_X   (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS2_X   (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN56XX_PASS1     OCTEON_CN56XX_PASS1_X
 #define OCTEON_CN56XX_PASS2     OCTEON_CN56XX_PASS2_X
 
@@ -125,8 +142,7 @@
 #define OCTEON_CN50XX_PASS1_0   0x000d0600
 
 #define OCTEON_CN50XX           (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN50XX_PASS1_X   (OCTEON_CN50XX_PASS1_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN50XX_PASS1_X   (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN50XX_PASS1     OCTEON_CN50XX_PASS1_X
 
 /*
@@ -138,10 +154,8 @@
 #define OCTEON_CN52XX_PASS2_0   0x000d0708
 
 #define OCTEON_CN52XX           (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN52XX_PASS1_X   (OCTEON_CN52XX_PASS1_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN52XX_PASS2_X   (OCTEON_CN52XX_PASS2_0 \
-                                 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS1_X   (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS2_X   (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
 #define OCTEON_CN52XX_PASS1     OCTEON_CN52XX_PASS1_X
 #define OCTEON_CN52XX_PASS2     OCTEON_CN52XX_PASS2_X
 
@@ -174,28 +188,23 @@
 #define OCTEON_CN3005_PASS1     (0x000d0210 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3005_PASS1_0   (0x000d0210 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3005_PASS1_1   (0x000d0212 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3005           (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \
-                                 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005           (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
 
 #define OCTEON_CN3010_PASS1     (0x000d0200 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3010_PASS1_0   (0x000d0200 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3010_PASS1_1   (0x000d0202 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3010           (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \
-                                 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010           (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
 
 #define OCTEON_CN3020_PASS1     (0x000d0110 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3020_PASS1_0   (0x000d0110 | OM_CHECK_SUBMODEL)
 #define OCTEON_CN3020_PASS1_1   (0x000d0112 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3020           (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \
-                                 | OM_CHECK_SUBMODEL)
-
-
-
-/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
-#define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 \
-                                 | OM_MATCH_PREVIOUS_MODELS \
-                                 | OM_IGNORE_REVISION)
+#define OCTEON_CN3020           (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
 
+/*
+ * This matches the complete family of CN3xxx CPUs, and not subsequent
+ * models
+ */
+#define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
 #define OCTEON_CN5XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
 #define OCTEON_CN6XXX           (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
 
@@ -221,90 +230,55 @@
 #define OCTEON_38XX_FAMILY_MASK      0x00ffff00
 #define OCTEON_38XX_FAMILY_REV_MASK  0x00ffff0f
 #define OCTEON_38XX_MODEL_MASK       0x00ffff10
-#define OCTEON_38XX_MODEL_REV_MASK   (OCTEON_38XX_FAMILY_REV_MASK \
-                                      | OCTEON_38XX_MODEL_MASK)
+#define OCTEON_38XX_MODEL_REV_MASK   (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK)
 
 /* CN5XXX and later use different layout of bits in the revision ID field */
 #define OCTEON_58XX_FAMILY_MASK      OCTEON_38XX_FAMILY_MASK
 #define OCTEON_58XX_FAMILY_REV_MASK  0x00ffff3f
 #define OCTEON_58XX_MODEL_MASK       0x00ffffc0
-#define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK \
-                                      | OCTEON_58XX_MODEL_MASK)
-#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
-                                          & 0x00fffff8)
+#define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
+#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)
 #define OCTEON_5XXX_MODEL_MASK       0x00ff0fc0
 
-#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
-
-/* NOTE: This is for internal (to this file) use only. */
-static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
-                                              uint32_t chip_model)
-{
-        uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
-
-        if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
-                if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
-                    __OCTEON_MATCH_MASK__(chip_model, arg_model,
-                                          OCTEON_38XX_MODEL_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == 0) &&
-                    __OCTEON_MATCH_MASK__(chip_model, arg_model,
-                                          OCTEON_38XX_FAMILY_REV_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
-                    __OCTEON_MATCH_MASK__(chip_model, arg_model,
-                                          OCTEON_38XX_FAMILY_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_38XX_MODEL_REV_MASK))
-                        return 1;
-                if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
-                    ((chip_model & OCTEON_38XX_MODEL_MASK) <
-                            (arg_model & OCTEON_38XX_MODEL_MASK)))
-                        return 1;
-        } else {
-                if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_58XX_MODEL_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == 0) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_58XX_FAMILY_REV_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_58XX_MODEL_MINOR_REV_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_58XX_FAMILY_MASK))
-                        return 1;
-                if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
-                    __OCTEON_MATCH_MASK__((chip_model), (arg_model),
-                                          OCTEON_58XX_MODEL_REV_MASK))
-                        return 1;
-
-                if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) &&
-                    ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0))
-                        return 1;
-
-                if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) &&
-                    ((chip_model) >= OCTEON_CN63XX_PASS1_0))
-                        return 1;
-
-                if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
-                    ((chip_model & OCTEON_58XX_MODEL_MASK) <
-                            (arg_model & OCTEON_58XX_MODEL_MASK)))
-                        return 1;
-        }
-        return 0;
-}
-
 /* forward declarations */
 static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
 static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
 
+#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
+
+/* NOTE: This for internal use only! */
+#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model)              \
+((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0)  && ( \
+                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL)  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \
+                ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
+                        && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
+                )) ||                                                   \
+        (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0)  && ( \
+                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_MINOR_REVISION) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MINOR_REV_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
+                ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL)  \
+                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
+                ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
+                        && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
+                ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
+                        && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) ||  \
+                ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
+                        && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
+                )))
+
 /* NOTE: This for internal use only!!!!! */
 static inline int __octeon_is_model_runtime__(uint32_t model)
 {
@@ -312,22 +286,25 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
 
         /*
          * Check for special case of mismarked 3005 samples. We only
-         * need to check if the sub model isn't being ignored.
+         * need to check if the sub model isn't being ignored
          */
         if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
-                if (cpuid == OCTEON_CN3010_PASS1 \
-                    && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
+                if (cpuid == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
                         cpuid |= 0x10;
         }
         return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
 }
 
 /*
- * The OCTEON_IS_MODEL macro should be used for all Octeon model
- * checking done in a program.  This should be kept runtime if at all
- * possible.  Any compile time (#if OCTEON_IS_MODEL) usage must be
- * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking
- * support is required.
+ * The OCTEON_IS_MODEL macro should be used for all Octeon model checking done
+ * in a program.
+ * This should be kept runtime if at all possible  and must be conditionalized
+ * with OCTEON_IS_COMMON_BINARY() if runtime checking support is required.
+ *
+ * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) )
+ * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR()
+ * I.e.:
+ *  #if OCTEON_IS_MODEL(OCTEON_CN56XX)  ->  #if CVMX_COMPILED_FOR(OCTEON_CN56XX)
  */
 #define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
 #define OCTEON_IS_COMMON_BINARY() 1
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index fba2ba200f58..c66734bd3382 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -56,7 +56,8 @@ enum octeon_dma_bar_type {
         OCTEON_DMA_BAR_TYPE_INVALID,
         OCTEON_DMA_BAR_TYPE_SMALL,
         OCTEON_DMA_BAR_TYPE_BIG,
-        OCTEON_DMA_BAR_TYPE_PCIE
+        OCTEON_DMA_BAR_TYPE_PCIE,
+        OCTEON_DMA_BAR_TYPE_PCIE2
 };
 
 /*
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index e59cd1ac09c2..d41790928c64 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -38,6 +38,14 @@
 #define HPAGE_SIZE      (_AC(1,UL) << HPAGE_SHIFT)
 #define HPAGE_MASK      (~(HPAGE_SIZE - 1))
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+#else /* !CONFIG_HUGETLB_PAGE */
+# ifndef BUILD_BUG
+#  define BUILD_BUG() do { extern void __build_bug(void); __build_bug(); } while (0)
+# endif
+#define HPAGE_SHIFT     ({BUILD_BUG(); 0; })
+#define HPAGE_SIZE      ({BUILD_BUG(); 0; })
+#define HPAGE_MASK      ({BUILD_BUG(); 0; })
+#define HUGETLB_PAGE_ORDER      ({BUILD_BUG(); 0; })
 #endif /* CONFIG_HUGETLB_PAGE */
 
 #ifndef __ASSEMBLY__
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 8a153d2fa62a..5d56bb230345 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -19,23 +19,7 @@
 #include <asm-generic/pgtable-nopmd.h>
 
 /*
- * - add_wired_entry() add a fixed TLB entry, and move wired register
- */
-extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
-                               unsigned long entryhi, unsigned long pagemask);
-
-/*
- * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
- *      starting at the top and working down. This is for populating the
- *      TLB before trap_init() puts the TLB miss handler in place. It
- *      should be used only for entries matching the actual page tables,
- *      to prevent inconsistencies.
- */
-extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
-                               unsigned long entryhi, unsigned long pagemask);
-
-
-/* Basically we have the same two-level (which is the logical three level
+ * Basically we have the same two-level (which is the logical three level
  * Linux page table layout folded) page tables as the i386.  Some day
  * when we have proper page coloring support we can have a 1% quicker
  * tlb refill handling mechanism, but for now it is a bit slower but
diff --git a/arch/mips/include/asm/tlbmisc.h b/arch/mips/include/asm/tlbmisc.h
new file mode 100644
index 000000000000..3a452282cba0
--- /dev/null
+++ b/arch/mips/include/asm/tlbmisc.h
@@ -0,0 +1,10 @@
+#ifndef __ASM_TLBMISC_H
+#define __ASM_TLBMISC_H
+
+/*
+ * - add_wired_entry() add a fixed TLB entry, and move wired register
+ */
+extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
+        unsigned long entryhi, unsigned long pagemask);
+
+#endif /* __ASM_TLBMISC_H */
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index 90ff2f497c50..ff74aec3561a 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -24,5 +24,18 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 extern void (*board_nmi_handler_setup)(void);
 extern void (*board_ejtag_handler_setup)(void);
 extern void (*board_bind_eic_interrupt)(int irq, int regset);
+extern void (*board_ebase_setup)(void);
+
+extern int register_nmi_notifier(struct notifier_block *nb);
+
+#define nmi_notifier(fn, pri)                                           \
+({                                                                      \
+        static struct notifier_block fn##_nb = {                        \
+                .notifier_call = fn,                                    \
+                .priority = pri                                         \
+        };                                                              \
+                                                                        \
+        register_nmi_notifier(&fn##_nb);                                \
+})
 
 #endif /* _ASM_TRAPS_H */
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index ca9bd2069142..f21868b28b24 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -20,6 +20,7 @@
 #include <asm/io.h>
 #include <asm/jazz.h>
 #include <asm/pgtable.h>
+#include <asm/tlbmisc.h>
 
 static DEFINE_RAW_SPINLOCK(r4030_lock);
 
@@ -133,7 +134,7 @@ static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction r4030_timer_irqaction = {
         .handler        = r4030_timer_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .flags          = IRQF_TIMER,
         .name           = "R4030 timer",
 };
 
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index 0d0f054a02f4..820e926dacbc 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -21,6 +21,7 @@
 #include <asm/jazzdma.h>
 #include <asm/reboot.h>
 #include <asm/pgtable.h>
+#include <asm/tlbmisc.h>
 
 extern asmlinkage void jazz_handle_int(void);
 
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index c3b04be3fb2b..639e3ce6c264 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -488,7 +488,7 @@ static int __init qi_lb60_board_setup(void)
         board_gpio_setup();
 
         if (qi_lb60_init_platform_devices())
-                panic("Failed to initialize platform devices\n");
+                panic("Failed to initialize platform devices");
 
         return 0;
 }
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 1a966183e353..0c6877ea9004 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -55,9 +55,11 @@ obj-$(CONFIG_CPU_TX49XX)	+= r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_VR41XX)        += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
 obj-$(CONFIG_CPU_XLR)           += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_XLP)           += r4k_fpu.o r4k_switch.o
 
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_SMP_UP)            += smp-up.o
+obj-$(CONFIG_CPU_BMIPS)         += smp-bmips.o bmips_vec.o
 
 obj-$(CONFIG_MIPS_MT)           += mips-mt.o
 obj-$(CONFIG_MIPS_MT_FPAFF)     += mips-mt-fpaff.o
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
new file mode 100644
index 000000000000..e908e81330b1
--- /dev/null
+++ b/arch/mips/kernel/bmips_vec.S
@@ -0,0 +1,255 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
+ *
+ * Reset/NMI/re-entry vectors for BMIPS processors
+ */
+
+#include <linux/init.h>
+
+#include <asm/asm.h>
+#include <asm/asmmacro.h>
+#include <asm/cacheops.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/stackframe.h>
+#include <asm/addrspace.h>
+#include <asm/hazards.h>
+#include <asm/bmips.h>
+
+        .macro  BARRIER
+        .set    mips32
+        _ssnop
+        _ssnop
+        _ssnop
+        .set    mips0
+        .endm
+
+        __CPUINIT
+
+/***********************************************************************
+ * Alternate CPU1 startup vector for BMIPS4350
+ *
+ * On some systems the bootloader has already started CPU1 and configured
+ * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
+ * triggered by the SW1 interrupt.  If that is the case we try to move
+ * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
+ ***********************************************************************/
+
+LEAF(bmips_smp_movevec)
+        la      k0, 1f
+        li      k1, CKSEG1
+        or      k0, k1
+        jr      k0
+
+1:
+        /* clear IV, pending IPIs */
+        mtc0    zero, CP0_CAUSE
+
+        /* re-enable IRQs to wait for SW1 */
+        li      k0, ST0_IE | ST0_BEV | STATUSF_IP1
+        mtc0    k0, CP0_STATUS
+
+        /* set up CPU1 CBR; move BASE to 0xa000_0000 */
+        li      k0, 0xff400000
+        mtc0    k0, $22, 6
+        li      k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_1
+        or      k0, k1
+        li      k1, 0xa0080000
+        sw      k1, 0(k0)
+
+        /* wait here for SW1 interrupt from bmips_boot_secondary() */
+        wait
+
+        la      k0, bmips_reset_nmi_vec
+        li      k1, CKSEG1
+        or      k0, k1
+        jr      k0
+END(bmips_smp_movevec)
+
+/***********************************************************************
+ * Reset/NMI vector
+ * For BMIPS processors that can relocate their exception vectors, this
+ * entire function gets copied to 0x8000_0000.
+ ***********************************************************************/
+
+NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
+        .set    push
+        .set    noat
+        .align  4
+
+#ifdef CONFIG_SMP
+        /* if the NMI bit is clear, assume this is a CPU1 reset instead */
+        li      k1, (1 << 19)
+        mfc0    k0, CP0_STATUS
+        and     k0, k1
+        beqz    k0, bmips_smp_entry
+
+#if defined(CONFIG_CPU_BMIPS5000)
+        /* if we're not on core 0, this must be the SMP boot signal */
+        li      k1, (3 << 25)
+        mfc0    k0, $22
+        and     k0, k1
+        bnez    k0, bmips_smp_entry
+#endif
+#endif /* CONFIG_SMP */
+
+        /* nope, it's just a regular NMI */
+        SAVE_ALL
+        move    a0, sp
+
+        /* clear EXL, ERL, BEV so that TLB refills still work */
+        mfc0    k0, CP0_STATUS
+        li      k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
+        or      k0, k1
+        xor     k0, k1
+        mtc0    k0, CP0_STATUS
+        BARRIER
+
+        /* jump to the NMI handler function */
+        la      k0, nmi_handler
+        jr      k0
+
+        RESTORE_ALL
+        .set    mips3
+        eret
+
+/***********************************************************************
+ * CPU1 reset vector (used for the initial boot only)
+ * This is still part of bmips_reset_nmi_vec().
+ ***********************************************************************/
+
+#ifdef CONFIG_SMP
+
+bmips_smp_entry:
+
+        /* set up CP0 STATUS; enable FPU */
+        li      k0, 0x30000000
+        mtc0    k0, CP0_STATUS
+        BARRIER
+
+        /* set local CP0 CONFIG to make kseg0 cacheable, write-back */
+        mfc0    k0, CP0_CONFIG
+        ori     k0, 0x07
+        xori    k0, 0x04
+        mtc0    k0, CP0_CONFIG
+
+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+        /* initialize CPU1's local I-cache */
+        li      k0, 0x80000000
+        li      k1, 0x80010000
+        mtc0    zero, $28
+        mtc0    zero, $28, 1
+        BARRIER
+
+1:      cache   Index_Store_Tag_I, 0(k0)
+        addiu   k0, 16
+        bne     k0, k1, 1b
+#elif defined(CONFIG_CPU_BMIPS5000)
+        /* set exception vector base */
+        la      k0, ebase
+        lw      k0, 0(k0)
+        mtc0    k0, $15, 1
+        BARRIER
+#endif
+
+        /* jump back to kseg0 in case we need to remap the kseg1 area */
+        la      k0, 1f
+        jr      k0
+1:
+        la      k0, bmips_enable_xks01
+        jalr    k0
+
+        /* use temporary stack to set up upper memory TLB */
+        li      sp, BMIPS_WARM_RESTART_VEC
+        la      k0, plat_wired_tlb_setup
+        jalr    k0
+
+        /* switch to permanent stack and continue booting */
+
+        .global bmips_secondary_reentry
+bmips_secondary_reentry:
+        la      k0, bmips_smp_boot_sp
+        lw      sp, 0(k0)
+        la      k0, bmips_smp_boot_gp
+        lw      gp, 0(k0)
+        la      k0, start_secondary
+        jr      k0
+
+#endif /* CONFIG_SMP */
+
+        .align  4
+        .global bmips_reset_nmi_vec_end
+bmips_reset_nmi_vec_end:
+
+END(bmips_reset_nmi_vec)
+
+        .set    pop
+        .previous
+
+/***********************************************************************
+ * CPU1 warm restart vector (used for second and subsequent boots).
+ * Also used for S2 standby recovery (PM).
+ * This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
+ ***********************************************************************/
+
+LEAF(bmips_smp_int_vec)
+
+        .align  4
+        mfc0    k0, CP0_STATUS
+        ori     k0, 0x01
+        xori    k0, 0x01
+        mtc0    k0, CP0_STATUS
+        eret
+
+        .align  4
+        .global bmips_smp_int_vec_end
+bmips_smp_int_vec_end:
+
+END(bmips_smp_int_vec)
+
+/***********************************************************************
+ * XKS01 support
+ * Certain CPUs support extending kseg0 to 1024MB.
+ ***********************************************************************/
+
+        __CPUINIT
+
+LEAF(bmips_enable_xks01)
+
+#if defined(CONFIG_XKS01)
+
+#if defined(CONFIG_CPU_BMIPS4380)
+        mfc0    t0, $22, 3
+        li      t1, 0x1ff0
+        li      t2, (1 << 12) | (1 << 9)
+        or      t0, t1
+        xor     t0, t1
+        or      t0, t2
+        mtc0    t0, $22, 3
+        BARRIER
+#elif defined(CONFIG_CPU_BMIPS5000)
+        mfc0    t0, $22, 5
+        li      t1, 0x01ff
+        li      t2, (1 << 8) | (1 << 5)
+        or      t0, t1
+        xor     t0, t1
+        or      t0, t2
+        mtc0    t0, $22, 5
+        BARRIER
+#else
+
+#error Missing XKS01 setup
+
+#endif
+
+#endif /* defined(CONFIG_XKS01) */
+
+        jr      ra
+
+END(bmips_enable_xks01)
+
+        .previous
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 32103cc2a257..4d735d0e58f5 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -9,6 +9,7 @@
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/signal.h>
+#include <linux/module.h>
 #include <asm/branch.h>
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
@@ -17,28 +18,22 @@
 #include <asm/ptrace.h>
 #include <asm/uaccess.h>
 
-/*
- * Compute the return address and do emulate branch simulation, if required.
+/**
+ * __compute_return_epc_for_insn - Computes the return address and do emulate
+ *                                  branch simulation, if required.
+ *
+ * @regs:       Pointer to pt_regs
+ * @insn:       branch instruction to decode
+ * @returns:    -EFAULT on error and forces SIGBUS, and on success
+ *              returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
+ *              evaluating the branch.
  */
-int __compute_return_epc(struct pt_regs *regs)
+int __compute_return_epc_for_insn(struct pt_regs *regs,
+                                   union mips_instruction insn)
 {
-        unsigned int __user *addr;
         unsigned int bit, fcr31, dspcontrol;
-        long epc;
-        union mips_instruction insn;
-
-        epc = regs->cp0_epc;
-        if (epc & 3)
-                goto unaligned;
-
-        /*
-         * Read the instruction
-         */
-        addr = (unsigned int __user *) epc;
-        if (__get_user(insn.word, addr)) {
-                force_sig(SIGSEGV, current);
-                return -EFAULT;
-        }
+        long epc = regs->cp0_epc;
+        int ret = 0;
 
         switch (insn.i_format.opcode) {
         /*
@@ -64,18 +59,22 @@ int __compute_return_epc(struct pt_regs *regs)
                 switch (insn.i_format.rt) {
                 case bltz_op:
                 case bltzl_op:
-                        if ((long)regs->regs[insn.i_format.rs] < 0)
+                        if ((long)regs->regs[insn.i_format.rs] < 0) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == bltzl_op)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
 
                 case bgez_op:
                 case bgezl_op:
-                        if ((long)regs->regs[insn.i_format.rs] >= 0)
+                        if ((long)regs->regs[insn.i_format.rs] >= 0) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == bgezl_op)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
@@ -83,9 +82,11 @@ int __compute_return_epc(struct pt_regs *regs)
                 case bltzal_op:
                 case bltzall_op:
                         regs->regs[31] = epc + 8;
-                        if ((long)regs->regs[insn.i_format.rs] < 0)
+                        if ((long)regs->regs[insn.i_format.rs] < 0) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == bltzall_op)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
@@ -93,12 +94,15 @@ int __compute_return_epc(struct pt_regs *regs)
                 case bgezal_op:
                 case bgezall_op:
                         regs->regs[31] = epc + 8;
-                        if ((long)regs->regs[insn.i_format.rs] >= 0)
+                        if ((long)regs->regs[insn.i_format.rs] >= 0) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == bgezall_op)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
+
                 case bposge32_op:
                         if (!cpu_has_dsp)
                                 goto sigill;
@@ -133,9 +137,11 @@ int __compute_return_epc(struct pt_regs *regs)
         case beq_op:
         case beql_op:
                 if (regs->regs[insn.i_format.rs] ==
-                    regs->regs[insn.i_format.rt])
+                    regs->regs[insn.i_format.rt]) {
                         epc = epc + 4 + (insn.i_format.simmediate << 2);
-                else
+                        if (insn.i_format.rt == beql_op)
+                                ret = BRANCH_LIKELY_TAKEN;
+                } else
                         epc += 8;
                 regs->cp0_epc = epc;
                 break;
@@ -143,9 +149,11 @@ int __compute_return_epc(struct pt_regs *regs)
         case bne_op:
         case bnel_op:
                 if (regs->regs[insn.i_format.rs] !=
-                    regs->regs[insn.i_format.rt])
+                    regs->regs[insn.i_format.rt]) {
                         epc = epc + 4 + (insn.i_format.simmediate << 2);
-                else
+                        if (insn.i_format.rt == bnel_op)
+                                ret = BRANCH_LIKELY_TAKEN;
+                } else
                         epc += 8;
                 regs->cp0_epc = epc;
                 break;
@@ -153,9 +161,11 @@ int __compute_return_epc(struct pt_regs *regs)
         case blez_op: /* not really i_format */
         case blezl_op:
                 /* rt field assumed to be zero */
-                if ((long)regs->regs[insn.i_format.rs] <= 0)
+                if ((long)regs->regs[insn.i_format.rs] <= 0) {
                         epc = epc + 4 + (insn.i_format.simmediate << 2);
-                else
+                        if (insn.i_format.rt == bnel_op)
+                                ret = BRANCH_LIKELY_TAKEN;
+                } else
                         epc += 8;
                 regs->cp0_epc = epc;
                 break;
@@ -163,9 +173,11 @@ int __compute_return_epc(struct pt_regs *regs)
         case bgtz_op:
         case bgtzl_op:
                 /* rt field assumed to be zero */
-                if ((long)regs->regs[insn.i_format.rs] > 0)
+                if ((long)regs->regs[insn.i_format.rs] > 0) {
                         epc = epc + 4 + (insn.i_format.simmediate << 2);
-                else
+                        if (insn.i_format.rt == bnel_op)
+                                ret = BRANCH_LIKELY_TAKEN;
+                } else
                         epc += 8;
                 regs->cp0_epc = epc;
                 break;
@@ -187,18 +199,22 @@ int __compute_return_epc(struct pt_regs *regs)
                 switch (insn.i_format.rt & 3) {
                 case 0: /* bc1f */
                 case 2: /* bc1fl */
-                        if (~fcr31 & (1 << bit))
+                        if (~fcr31 & (1 << bit)) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == 2)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
 
                 case 1: /* bc1t */
                 case 3: /* bc1tl */
-                        if (fcr31 & (1 << bit))
+                        if (fcr31 & (1 << bit)) {
                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
-                        else
+                                if (insn.i_format.rt == 3)
+                                        ret = BRANCH_LIKELY_TAKEN;
+                        } else
                                 epc += 8;
                         regs->cp0_epc = epc;
                         break;
@@ -239,15 +255,39 @@ int __compute_return_epc(struct pt_regs *regs)
 #endif
         }
 
-        return 0;
+        return ret;
 
-unaligned:
-        printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
+sigill:
+        printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
         force_sig(SIGBUS, current);
         return -EFAULT;
+}
+EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
 
-sigill:
-        printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
+int __compute_return_epc(struct pt_regs *regs)
+{
+        unsigned int __user *addr;
+        long epc;
+        union mips_instruction insn;
+
+        epc = regs->cp0_epc;
+        if (epc & 3)
+                goto unaligned;
+
+        /*
+         * Read the instruction
+         */
+        addr = (unsigned int __user *) epc;
+        if (__get_user(insn.word, addr)) {
+                force_sig(SIGSEGV, current);
+                return -EFAULT;
+        }
+
+        return __compute_return_epc_for_insn(regs, insn);
+
+unaligned:
+        printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
         force_sig(SIGBUS, current);
         return -EFAULT;
+
 }
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index 36c3898b76db..69bbfae183bc 100644
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -145,7 +145,7 @@ void __cpuinit sb1480_clockevent_init(void)
         bcm1480_unmask_irq(cpu, irq);
 
         action->handler = sibyte_counter_handler;
-        action->flags   = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER;
+        action->flags   = IRQF_PERCPU | IRQF_TIMER;
         action->name    = name;
         action->dev_id  = cd;
 
diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c
index 939157e397b9..ed648cb5a69f 100644
--- a/arch/mips/kernel/cevt-ds1287.c
+++ b/arch/mips/kernel/cevt-ds1287.c
@@ -108,7 +108,7 @@ static irqreturn_t ds1287_interrupt(int irq, void *dev_id)
 
 static struct irqaction ds1287_irqaction = {
         .handler        = ds1287_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
+        .flags          = IRQF_PERCPU | IRQF_TIMER,
         .name           = "ds1287",
 };
 
diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c
index 339f3639b90e..831b47585b7c 100644
--- a/arch/mips/kernel/cevt-gt641xx.c
+++ b/arch/mips/kernel/cevt-gt641xx.c
@@ -114,7 +114,7 @@ static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
 
 static struct irqaction gt641xx_timer0_irqaction = {
         .handler        = gt641xx_timer0_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
+        .flags          = IRQF_PERCPU | IRQF_TIMER,
         .name           = "gt641xx_timer0",
 };
 
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index e2d8e199be32..51095dd9599d 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -84,7 +84,7 @@ out:
 
 struct irqaction c0_compare_irqaction = {
         .handler = c0_compare_interrupt,
-        .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
+        .flags = IRQF_PERCPU | IRQF_TIMER,
         .name = "timer",
 };
 
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index 590c54f28a81..e73439fd6850 100644
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -144,7 +144,7 @@ void __cpuinit sb1250_clockevent_init(void)
         sb1250_unmask_irq(cpu, irq);
 
         action->handler = sibyte_counter_handler;
-        action->flags   = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER;
+        action->flags   = IRQF_PERCPU | IRQF_TIMER;
         action->name    = name;
         action->dev_id  = cd;
 
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index f0ab92a1b057..e5c30b1d0860 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -146,7 +146,7 @@ static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
 
 static struct irqaction txx9tmr_irq = {
         .handler        = txx9tmr_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
+        .flags          = IRQF_PERCPU | IRQF_TIMER,
         .name           = "txx9tmr",
         .dev_id         = &txx9_clock_event_device,
 };
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c7d3cf1ce46e..0bab464b8e33 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -191,6 +191,8 @@ void __init check_wait(void)
         case CPU_CAVIUM_OCTEON_PLUS:
         case CPU_CAVIUM_OCTEON2:
         case CPU_JZRISC:
+        case CPU_XLR:
+        case CPU_XLP:
                 cpu_wait = r4k_wait;
                 break;
 
@@ -1014,6 +1016,13 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
 {
         decode_configs(c);
 
+        if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
+                c->cputype = CPU_ALCHEMY;
+                __cpu_name[cpu] = "Au1300";
+                /* following stuff is not for Alchemy */
+                return;
+        }
+
         c->options = (MIPS_CPU_TLB       |
                         MIPS_CPU_4KEX    |
                         MIPS_CPU_COUNTER |
@@ -1023,6 +1032,12 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
                         MIPS_CPU_LLSC);
 
         switch (c->processor_id & 0xff00) {
+        case PRID_IMP_NETLOGIC_XLP8XX:
+        case PRID_IMP_NETLOGIC_XLP3XX:
+                c->cputype = CPU_XLP;
+                __cpu_name[cpu] = "Netlogic XLP";
+                break;
+
         case PRID_IMP_NETLOGIC_XLR732:
         case PRID_IMP_NETLOGIC_XLR716:
         case PRID_IMP_NETLOGIC_XLR532:
@@ -1053,14 +1068,21 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
                 break;
 
         default:
-                printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
+                pr_info("Unknown Netlogic chip id [%02x]!\n",
                        c->processor_id);
                 c->cputype = CPU_XLR;
                 break;
         }
 
-        c->isa_level = MIPS_CPU_ISA_M64R1;
-        c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+        if (c->cputype == CPU_XLP) {
+                c->isa_level = MIPS_CPU_ISA_M64R2;
+                c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
+                /* This will be updated again after all threads are woken up */
+                c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+        } else {
+                c->isa_level = MIPS_CPU_ISA_M64R1;
+                c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+        }
 }
 
 #ifdef CONFIG_64BIT
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index 7047bff35ea5..c5bc344fc745 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -19,7 +19,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction irq0  = {
         .handler = timer_interrupt,
-        .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
+        .flags = IRQF_NOBALANCING | IRQF_TIMER,
         .name = "timer"
 };
 
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
index ee28683fc2ac..158467da9bc1 100644
--- a/arch/mips/kernel/kprobes.c
+++ b/arch/mips/kernel/kprobes.c
@@ -25,10 +25,12 @@
 
 #include <linux/kprobes.h>
 #include <linux/preempt.h>
+#include <linux/uaccess.h>
 #include <linux/kdebug.h>
 #include <linux/slab.h>
 
 #include <asm/ptrace.h>
+#include <asm/branch.h>
 #include <asm/break.h>
 #include <asm/inst.h>
 
@@ -112,17 +114,49 @@ insn_ok:
         return 0;
 }
 
+/*
+ * insn_has_ll_or_sc function checks whether instruction is ll or sc
+ * one; putting breakpoint on top of atomic ll/sc pair is bad idea;
+ * so we need to prevent it and refuse kprobes insertion for such
+ * instructions; cannot do much about breakpoint in the middle of
+ * ll/sc pair; it is upto user to avoid those places
+ */
+static int __kprobes insn_has_ll_or_sc(union mips_instruction insn)
+{
+        int ret = 0;
+
+        switch (insn.i_format.opcode) {
+        case ll_op:
+        case lld_op:
+        case sc_op:
+        case scd_op:
+                ret = 1;
+                break;
+        default:
+                break;
+        }
+        return ret;
+}
+
 int __kprobes arch_prepare_kprobe(struct kprobe *p)
 {
         union mips_instruction insn;
         union mips_instruction prev_insn;
         int ret = 0;
 
-        prev_insn = p->addr[-1];
         insn = p->addr[0];
 
-        if (insn_has_delayslot(insn) || insn_has_delayslot(prev_insn)) {
-                pr_notice("Kprobes for branch and jump instructions are not supported\n");
+        if (insn_has_ll_or_sc(insn)) {
+                pr_notice("Kprobes for ll and sc instructions are not"
+                          "supported\n");
+                ret = -EINVAL;
+                goto out;
+        }
+
+        if ((probe_kernel_read(&prev_insn, p->addr - 1,
+                                sizeof(mips_instruction)) == 0) &&
+                                insn_has_delayslot(prev_insn)) {
+                pr_notice("Kprobes for branch delayslot are not supported\n");
                 ret = -EINVAL;
                 goto out;
         }
@@ -138,9 +172,20 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
          * In the kprobe->ainsn.insn[] array we store the original
          * instruction at index zero and a break trap instruction at
          * index one.
+         *
+         * On MIPS arch if the instruction at probed address is a
+         * branch instruction, we need to execute the instruction at
+         * Branch Delayslot (BD) at the time of probe hit. As MIPS also
+         * doesn't have single stepping support, the BD instruction can
+         * not be executed in-line and it would be executed on SSOL slot
+         * using a normal breakpoint instruction in the next slot.
+         * So, read the instruction and save it for later execution.
          */
+        if (insn_has_delayslot(insn))
+                memcpy(&p->ainsn.insn[0], p->addr + 1, sizeof(kprobe_opcode_t));
+        else
+                memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
 
-        memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
         p->ainsn.insn[1] = breakpoint2_insn;
         p->opcode = *p->addr;
 
@@ -191,16 +236,96 @@ static void set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
         kcb->kprobe_saved_epc = regs->cp0_epc;
 }
 
-static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
+/**
+ * evaluate_branch_instrucion -
+ *
+ * Evaluate the branch instruction at probed address during probe hit. The
+ * result of evaluation would be the updated epc. The insturction in delayslot
+ * would actually be single stepped using a normal breakpoint) on SSOL slot.
+ *
+ * The result is also saved in the kprobe control block for later use,
+ * in case we need to execute the delayslot instruction. The latter will be
+ * false for NOP instruction in dealyslot and the branch-likely instructions
+ * when the branch is taken. And for those cases we set a flag as
+ * SKIP_DELAYSLOT in the kprobe control block
+ */
+static int evaluate_branch_instruction(struct kprobe *p, struct pt_regs *regs,
+                                        struct kprobe_ctlblk *kcb)
 {
+        union mips_instruction insn = p->opcode;
+        long epc;
+        int ret = 0;
+
+        epc = regs->cp0_epc;
+        if (epc & 3)
+                goto unaligned;
+
+        if (p->ainsn.insn->word == 0)
+                kcb->flags |= SKIP_DELAYSLOT;
+        else
+                kcb->flags &= ~SKIP_DELAYSLOT;
+
+        ret = __compute_return_epc_for_insn(regs, insn);
+        if (ret < 0)
+                return ret;
+
+        if (ret == BRANCH_LIKELY_TAKEN)
+                kcb->flags |= SKIP_DELAYSLOT;
+
+        kcb->target_epc = regs->cp0_epc;
+
+        return 0;
+
+unaligned:
+        pr_notice("%s: unaligned epc - sending SIGBUS.\n", current->comm);
+        force_sig(SIGBUS, current);
+        return -EFAULT;
+
+}
+
+static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs,
+                                                struct kprobe_ctlblk *kcb)
+{
+        int ret = 0;
+
         regs->cp0_status &= ~ST0_IE;
 
         /* single step inline if the instruction is a break */
         if (p->opcode.word == breakpoint_insn.word ||
             p->opcode.word == breakpoint2_insn.word)
                 regs->cp0_epc = (unsigned long)p->addr;
-        else
-                regs->cp0_epc = (unsigned long)&p->ainsn.insn[0];
+        else if (insn_has_delayslot(p->opcode)) {
+                ret = evaluate_branch_instruction(p, regs, kcb);
+                if (ret < 0) {
+                        pr_notice("Kprobes: Error in evaluating branch\n");
+                        return;
+                }
+        }
+        regs->cp0_epc = (unsigned long)&p->ainsn.insn[0];
+}
+
+/*
+ * Called after single-stepping.  p->addr is the address of the
+ * instruction whose first byte has been replaced by the "break 0"
+ * instruction.  To avoid the SMP problems that can occur when we
+ * temporarily put back the original opcode to single-step, we
+ * single-stepped a copy of the instruction.  The address of this
+ * copy is p->ainsn.insn.
+ *
+ * This function prepares to return from the post-single-step
+ * breakpoint trap. In case of branch instructions, the target
+ * epc to be restored.
+ */
+static void __kprobes resume_execution(struct kprobe *p,
+                                       struct pt_regs *regs,
+                                       struct kprobe_ctlblk *kcb)
+{
+        if (insn_has_delayslot(p->opcode))
+                regs->cp0_epc = kcb->target_epc;
+        else {
+                unsigned long orig_epc = kcb->kprobe_saved_epc;
+                regs->cp0_epc = orig_epc + 4;
+        }
 }
 
 static int __kprobes kprobe_handler(struct pt_regs *regs)
@@ -239,8 +364,13 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
                         save_previous_kprobe(kcb);
                         set_current_kprobe(p, regs, kcb);
                         kprobes_inc_nmissed_count(p);
-                        prepare_singlestep(p, regs);
+                        prepare_singlestep(p, regs, kcb);
                         kcb->kprobe_status = KPROBE_REENTER;
+                        if (kcb->flags & SKIP_DELAYSLOT) {
+                                resume_execution(p, regs, kcb);
+                                restore_previous_kprobe(kcb);
+                                preempt_enable_no_resched();
+                        }
                         return 1;
                 } else {
                         if (addr->word != breakpoint_insn.word) {
@@ -284,8 +414,16 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
         }
 
 ss_probe:
-        prepare_singlestep(p, regs);
-        kcb->kprobe_status = KPROBE_HIT_SS;
+        prepare_singlestep(p, regs, kcb);
+        if (kcb->flags & SKIP_DELAYSLOT) {
+                kcb->kprobe_status = KPROBE_HIT_SSDONE;
+                if (p->post_handler)
+                        p->post_handler(p, regs, 0);
+                resume_execution(p, regs, kcb);
+                preempt_enable_no_resched();
+        } else
+                kcb->kprobe_status = KPROBE_HIT_SS;
+
         return 1;
 
 no_kprobe:
@@ -294,25 +432,6 @@ no_kprobe:
 
 }
 
-/*
- * Called after single-stepping.  p->addr is the address of the
- * instruction whose first byte has been replaced by the "break 0"
- * instruction.  To avoid the SMP problems that can occur when we
- * temporarily put back the original opcode to single-step, we
- * single-stepped a copy of the instruction.  The address of this
- * copy is p->ainsn.insn.
- *
- * This function prepares to return from the post-single-step
- * breakpoint trap.
- */
-static void __kprobes resume_execution(struct kprobe *p,
-                                       struct pt_regs *regs,
-                                       struct kprobe_ctlblk *kcb)
-{
-        unsigned long orig_epc = kcb->kprobe_saved_epc;
-        regs->cp0_epc = orig_epc + 4;
-}
-
 static inline int post_kprobe_handler(struct pt_regs *regs)
 {
         struct kprobe *cur = kprobe_running();
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 933166f44a6d..a9d801dec6b0 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -473,7 +473,6 @@ static const struct file_operations rtlx_fops = {
 
 static struct irqaction rtlx_irq = {
         .handler        = rtlx_interrupt,
-        .flags          = IRQF_DISABLED,
         .name           = "RTLX",
 };
 
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 84af26ab2212..e86c2cf554aa 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -121,6 +121,9 @@ static void __init print_memory_map(void)
                 case BOOT_MEM_RAM:
                         printk(KERN_CONT "(usable)\n");
                         break;
+                case BOOT_MEM_INIT_RAM:
+                        printk(KERN_CONT "(usable after init)\n");
+                        break;
                 case BOOT_MEM_ROM_DATA:
                         printk(KERN_CONT "(ROM data)\n");
                         break;
@@ -361,15 +364,24 @@ static void __init bootmem_init(void)
         for (i = 0; i < boot_mem_map.nr_map; i++) {
                 unsigned long start, end, size;
 
+                start = PFN_UP(boot_mem_map.map[i].addr);
+                end   = PFN_DOWN(boot_mem_map.map[i].addr
+                                    + boot_mem_map.map[i].size);
+
                 /*
                  * Reserve usable memory.
                  */
-                if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
+                switch (boot_mem_map.map[i].type) {
+                case BOOT_MEM_RAM:
+                        break;
+                case BOOT_MEM_INIT_RAM:
+                        memory_present(0, start, end);
                         continue;
+                default:
+                        /* Not usable memory */
+                        continue;
+                }
 
-                start = PFN_UP(boot_mem_map.map[i].addr);
-                end   = PFN_DOWN(boot_mem_map.map[i].addr
-                                    + boot_mem_map.map[i].size);
                 /*
                  * We are rounding up the start address of usable memory
                  * and at the end of the usable range downwards.
@@ -455,11 +467,33 @@ early_param("mem", early_parse_mem);
 
 static void __init arch_mem_init(char **cmdline_p)
 {
+        phys_t init_mem, init_end, init_size;
+
         extern void plat_mem_setup(void);
 
         /* call board setup routine */
         plat_mem_setup();
 
+        init_mem = PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT;
+        init_end = PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT;
+        init_size = init_end - init_mem;
+        if (init_size) {
+                /* Make sure it is in the boot_mem_map */
+                int i, found;
+                found = 0;
+                for (i = 0; i < boot_mem_map.nr_map; i++) {
+                        if (init_mem >= boot_mem_map.map[i].addr &&
+                            init_mem < (boot_mem_map.map[i].addr +
+                                        boot_mem_map.map[i].size)) {
+                                found = 1;
+                                break;
+                        }
+                }
+                if (!found)
+                        add_memory_region(init_mem, init_size,
+                                          BOOT_MEM_INIT_RAM);
+        }
+
         pr_info("Determined physical RAM map:\n");
         print_memory_map();
 
@@ -523,6 +557,7 @@ static void __init resource_init(void)
                 res = alloc_bootmem(sizeof(struct resource));
                 switch (boot_mem_map.map[i].type) {
                 case BOOT_MEM_RAM:
+                case BOOT_MEM_INIT_RAM:
                 case BOOT_MEM_ROM_DATA:
                         res->name = "System RAM";
                         break;
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
new file mode 100644
index 000000000000..58fe71afd879
--- /dev/null
+++ b/arch/mips/kernel/smp-bmips.c
@@ -0,0 +1,458 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
+ *
+ * SMP support for BMIPS
+ */
+
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/init.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+#include <linux/reboot.h>
+#include <linux/io.h>
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/bug.h>
+#include <linux/kernel.h>
+
+#include <asm/time.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/bootinfo.h>
+#include <asm/pmon.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/mipsregs.h>
+#include <asm/bmips.h>
+#include <asm/traps.h>
+#include <asm/barrier.h>
+
+static int __maybe_unused max_cpus = 1;
+
+/* these may be configured by the platform code */
+int bmips_smp_enabled = 1;
+int bmips_cpu_offset;
+cpumask_t bmips_booted_mask;
+
+#ifdef CONFIG_SMP
+
+/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
+unsigned long bmips_smp_boot_sp;
+unsigned long bmips_smp_boot_gp;
+
+static void bmips_send_ipi_single(int cpu, unsigned int action);
+static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
+
+/* SW interrupts 0,1 are used for interprocessor signaling */
+#define IPI0_IRQ                        (MIPS_CPU_IRQ_BASE + 0)
+#define IPI1_IRQ                        (MIPS_CPU_IRQ_BASE + 1)
+
+#define CPUNUM(cpu, shift)              (((cpu) + bmips_cpu_offset) << (shift))
+#define ACTION_CLR_IPI(cpu, ipi)        (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
+#define ACTION_SET_IPI(cpu, ipi)        (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
+#define ACTION_BOOT_THREAD(cpu)         (0x08 | CPUNUM(cpu, 0))
+
+static void __init bmips_smp_setup(void)
+{
+        int i;
+
+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+        /* arbitration priority */
+        clear_c0_brcm_cmt_ctrl(0x30);
+
+        /* NBK and weak order flags */
+        set_c0_brcm_config_0(0x30000);
+
+        /*
+         * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
+         * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
+         * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
+         */
+        change_c0_brcm_cmt_intr(0xf8018000,
+                (0x02 << 27) | (0x03 << 15));
+
+        /* single core, 2 threads (2 pipelines) */
+        max_cpus = 2;
+#elif defined(CONFIG_CPU_BMIPS5000)
+        /* enable raceless SW interrupts */
+        set_c0_brcm_config(0x03 << 22);
+
+        /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
+        change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
+
+        /* N cores, 2 threads per core */
+        max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
+
+        /* clear any pending SW interrupts */
+        for (i = 0; i < max_cpus; i++) {
+                write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
+                write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
+        }
+#endif
+
+        if (!bmips_smp_enabled)
+                max_cpus = 1;
+
+        /* this can be overridden by the BSP */
+        if (!board_ebase_setup)
+                board_ebase_setup = &bmips_ebase_setup;
+
+        for (i = 0; i < max_cpus; i++) {
+                __cpu_number_map[i] = 1;
+                __cpu_logical_map[i] = 1;
+                set_cpu_possible(i, 1);
+                set_cpu_present(i, 1);
+        }
+}
+
+/*
+ * IPI IRQ setup - runs on CPU0
+ */
+static void bmips_prepare_cpus(unsigned int max_cpus)
+{
+        if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
+                        "smp_ipi0", NULL))
+                panic("Can't request IPI0 interrupt\n");
+        if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
+                        "smp_ipi1", NULL))
+                panic("Can't request IPI1 interrupt\n");
+}
+
+/*
+ * Tell the hardware to boot CPUx - runs on CPU0
+ */
+static void bmips_boot_secondary(int cpu, struct task_struct *idle)
+{
+        bmips_smp_boot_sp = __KSTK_TOS(idle);
+        bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
+        mb();
+
+        /*
+         * Initial boot sequence for secondary CPU:
+         *   bmips_reset_nmi_vec @ a000_0000 ->
+         *   bmips_smp_entry ->
+         *   plat_wired_tlb_setup (cached function call; optional) ->
+         *   start_secondary (cached jump)
+         *
+         * Warm restart sequence:
+         *   play_dead WAIT loop ->
+         *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
+         *   eret to play_dead ->
+         *   bmips_secondary_reentry ->
+         *   start_secondary
+         */
+
+        pr_info("SMP: Booting CPU%d...\n", cpu);
+
+        if (cpumask_test_cpu(cpu, &bmips_booted_mask))
+                bmips_send_ipi_single(cpu, 0);
+        else {
+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+                set_c0_brcm_cmt_ctrl(0x01);
+#elif defined(CONFIG_CPU_BMIPS5000)
+                if (cpu & 0x01)
+                        write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
+                else {
+                        /*
+                         * core N thread 0 was already booted; just
+                         * pulse the NMI line
+                         */
+                        bmips_write_zscm_reg(0x210, 0xc0000000);
+                        udelay(10);
+                        bmips_write_zscm_reg(0x210, 0x00);
+                }
+#endif
+                cpumask_set_cpu(cpu, &bmips_booted_mask);
+        }
+}
+
+/*
+ * Early setup - runs on secondary CPU after cache probe
+ */
+static void bmips_init_secondary(void)
+{
+        /* move NMI vector to kseg0, in case XKS01 is enabled */
+
+#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+        void __iomem *cbr = BMIPS_GET_CBR();
+        unsigned long old_vec;
+
+        old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+        __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+
+        clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
+#elif defined(CONFIG_CPU_BMIPS5000)
+        write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
+                (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
+
+        write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
+#endif
+
+        /* make sure there won't be a timer interrupt for a little while */
+        write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
+
+        irq_enable_hazard();
+        set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
+        irq_enable_hazard();
+}
+
+/*
+ * Late setup - runs on secondary CPU before entering the idle loop
+ */
+static void bmips_smp_finish(void)
+{
+        pr_info("SMP: CPU%d is running\n", smp_processor_id());
+}
+
+/*
+ * Runs on CPU0 after all CPUs have been booted
+ */
+static void bmips_cpus_done(void)
+{
+}
+
+#if defined(CONFIG_CPU_BMIPS5000)
+
+/*
+ * BMIPS5000 raceless IPIs
+ *
+ * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
+ * IPI0 is used for SMP_RESCHEDULE_YOURSELF
+ * IPI1 is used for SMP_CALL_FUNCTION
+ */
+
+static void bmips_send_ipi_single(int cpu, unsigned int action)
+{
+        write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
+}
+
+static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
+{
+        int action = irq - IPI0_IRQ;
+
+        write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
+
+        if (action == 0)
+                scheduler_ipi();
+        else
+                smp_call_function_interrupt();
+
+        return IRQ_HANDLED;
+}
+
+#else
+
+/*
+ * BMIPS43xx racey IPIs
+ *
+ * We use one inbound SW IRQ for each CPU.
+ *
+ * A spinlock must be held in order to keep CPUx from accidentally clearing
+ * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy.  The
+ * same spinlock is used to protect the action masks.
+ */
+
+static DEFINE_SPINLOCK(ipi_lock);
+static DEFINE_PER_CPU(int, ipi_action_mask);
+
+static void bmips_send_ipi_single(int cpu, unsigned int action)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&ipi_lock, flags);
+        set_c0_cause(cpu ? C_SW1 : C_SW0);
+        per_cpu(ipi_action_mask, cpu) |= action;
+        irq_enable_hazard();
+        spin_unlock_irqrestore(&ipi_lock, flags);
+}
+
+static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
+{
+        unsigned long flags;
+        int action, cpu = irq - IPI0_IRQ;
+
+        spin_lock_irqsave(&ipi_lock, flags);
+        action = __get_cpu_var(ipi_action_mask);
+        per_cpu(ipi_action_mask, cpu) = 0;
+        clear_c0_cause(cpu ? C_SW1 : C_SW0);
+        spin_unlock_irqrestore(&ipi_lock, flags);
+
+        if (action & SMP_RESCHEDULE_YOURSELF)
+                scheduler_ipi();
+        if (action & SMP_CALL_FUNCTION)
+                smp_call_function_interrupt();
+
+        return IRQ_HANDLED;
+}
+
+#endif /* BMIPS type */
+
+static void bmips_send_ipi_mask(const struct cpumask *mask,
+        unsigned int action)
+{
+        unsigned int i;
+
+        for_each_cpu(i, mask)
+                bmips_send_ipi_single(i, action);
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+
+static int bmips_cpu_disable(void)
+{
+        unsigned int cpu = smp_processor_id();
+
+        if (cpu == 0)
+                return -EBUSY;
+
+        pr_info("SMP: CPU%d is offline\n", cpu);
+
+        cpu_clear(cpu, cpu_online_map);
+        cpu_clear(cpu, cpu_callin_map);
+
+        local_flush_tlb_all();
+        local_flush_icache_range(0, ~0);
+
+        return 0;
+}
+
+static void bmips_cpu_die(unsigned int cpu)
+{
+}
+
+void __ref play_dead(void)
+{
+        idle_task_exit();
+
+        /* flush data cache */
+        _dma_cache_wback_inv(0, ~0);
+
+        /*
+         * Wakeup is on SW0 or SW1; disable everything else
+         * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
+         * IRQ handlers; this clears ST0_IE and returns immediately.
+         */
+        clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
+        change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
+                IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
+        irq_disable_hazard();
+
+        /*
+         * wait for SW interrupt from bmips_boot_secondary(), then jump
+         * back to start_secondary()
+         */
+        __asm__ __volatile__(
+        "       wait\n"
+        "       j       bmips_secondary_reentry\n"
+        : : : "memory");
+}
+
+#endif /* CONFIG_HOTPLUG_CPU */
+
+struct plat_smp_ops bmips_smp_ops = {
+        .smp_setup              = bmips_smp_setup,
+        .prepare_cpus           = bmips_prepare_cpus,
+        .boot_secondary         = bmips_boot_secondary,
+        .smp_finish             = bmips_smp_finish,
+        .init_secondary         = bmips_init_secondary,
+        .cpus_done              = bmips_cpus_done,
+        .send_ipi_single        = bmips_send_ipi_single,
+        .send_ipi_mask          = bmips_send_ipi_mask,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_disable            = bmips_cpu_disable,
+        .cpu_die                = bmips_cpu_die,
+#endif
+};
+
+#endif /* CONFIG_SMP */
+
+/***********************************************************************
+ * BMIPS vector relocation
+ * This is primarily used for SMP boot, but it is applicable to some
+ * UP BMIPS systems as well.
+ ***********************************************************************/
+
+static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end)
+{
+        memcpy((void *)dst, start, end - start);
+        dma_cache_wback((unsigned long)start, end - start);
+        local_flush_icache_range(dst, dst + (end - start));
+        instruction_hazard();
+}
+
+static inline void __cpuinit bmips_nmi_handler_setup(void)
+{
+        bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
+                &bmips_reset_nmi_vec_end);
+        bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
+                &bmips_smp_int_vec_end);
+}
+
+void __cpuinit bmips_ebase_setup(void)
+{
+        unsigned long new_ebase = ebase;
+        void __iomem __maybe_unused *cbr;
+
+        BUG_ON(ebase != CKSEG0);
+
+#if defined(CONFIG_CPU_BMIPS4350)
+        /*
+         * BMIPS4350 cannot relocate the normal vectors, but it
+         * can relocate the BEV=1 vectors.  So CPU1 starts up at
+         * the relocated BEV=1, IV=0 general exception vector @
+         * 0xa000_0380.
+         *
+         * set_uncached_handler() is used here because:
+         *  - CPU1 will run this from uncached space
+         *  - None of the cacheflush functions are set up yet
+         */
+        set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
+                &bmips_smp_int_vec, 0x80);
+        __sync();
+        return;
+#elif defined(CONFIG_CPU_BMIPS4380)
+        /*
+         * 0x8000_0000: reset/NMI (initially in kseg1)
+         * 0x8000_0400: normal vectors
+         */
+        new_ebase = 0x80000400;
+        cbr = BMIPS_GET_CBR();
+        __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+        __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+#elif defined(CONFIG_CPU_BMIPS5000)
+        /*
+         * 0x8000_0000: reset/NMI (initially in kseg1)
+         * 0x8000_1000: normal vectors
+         */
+        new_ebase = 0x80001000;
+        write_c0_brcm_bootvec(0xa0088008);
+        write_c0_ebase(new_ebase);
+        if (max_cpus > 2)
+                bmips_write_zscm_reg(0xa0, 0xa008a008);
+#else
+        return;
+#endif
+        board_nmi_handler_setup = &bmips_nmi_handler_setup;
+        ebase = new_ebase;
+}
+
+asmlinkage void __weak plat_wired_tlb_setup(void)
+{
+        /*
+         * Called when starting/restarting a secondary CPU.
+         * Kernel stacks and other important data might only be accessible
+         * once the wired entries are present.
+         */
+}
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f0895e70e283..0a42ff3ff6a1 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -559,7 +559,7 @@ void smtc_prepare_cpus(int cpus)
 
         pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL);
         if (pipi == NULL)
-                panic("kmalloc of IPI message buffers failed\n");
+                panic("kmalloc of IPI message buffers failed");
         else
                 printk("IPI buffer pool of %d buffers\n", nipi);
         for (i = 0; i < nipi; i++) {
@@ -813,7 +813,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
         if (pipi == NULL) {
                 bust_spinlocks(1);
                 mips_mt_regdump(dvpe());
-                panic("IPI Msg. Buffers Depleted\n");
+                panic("IPI Msg. Buffers Depleted");
         }
         pipi->type = type;
         pipi->arg = (void *)action;
@@ -1130,7 +1130,7 @@ static void ipi_irq_dispatch(void)
 
 static struct irqaction irq_ipi = {
         .handler        = ipi_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_PERCPU,
+        .flags          = IRQF_PERCPU,
         .name           = "SMTC_IPI"
 };
 
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 5c8a49d55054..48240fd8c297 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -91,6 +91,7 @@ int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
 void (*board_nmi_handler_setup)(void);
 void (*board_ejtag_handler_setup)(void);
 void (*board_bind_eic_interrupt)(int irq, int regset);
+void (*board_ebase_setup)(void);
 
 
 static void show_raw_backtrace(unsigned long reg29)
@@ -400,7 +401,7 @@ void __noreturn die(const char *str, struct pt_regs *regs)
                 panic("Fatal exception in interrupt");
 
         if (panic_on_oops) {
-                printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
+                printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
                 ssleep(5);
                 panic("Fatal exception");
         }
@@ -1150,7 +1151,7 @@ asmlinkage void do_mt(struct pt_regs *regs)
 asmlinkage void do_dsp(struct pt_regs *regs)
 {
         if (cpu_has_dsp)
-                panic("Unexpected DSP exception\n");
+                panic("Unexpected DSP exception");
 
         force_sig(SIGILL, current);
 }
@@ -1339,9 +1340,18 @@ void ejtag_exception_handler(struct pt_regs *regs)
 
 /*
  * NMI exception handler.
+ * No lock; only written during early bootup by CPU 0.
  */
+static RAW_NOTIFIER_HEAD(nmi_chain);
+
+int register_nmi_notifier(struct notifier_block *nb)
+{
+        return raw_notifier_chain_register(&nmi_chain, nb);
+}
+
 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
 {
+        raw_notifier_call_chain(&nmi_chain, 0, regs);
         bust_spinlocks(1);
         printk("NMI taken!!!!\n");
         die("NMI", regs);
@@ -1682,6 +1692,8 @@ void __init trap_init(void)
                         ebase += (read_c0_ebase() & 0x3ffff000);
         }
 
+        if (board_ebase_setup)
+                board_ebase_setup();
         per_cpu_trap_init();
 
         /*
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index 77ed70fc2fe5..412814fdd3ee 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -134,11 +134,11 @@ void __init plat_time_init(void)
         struct clk *clk;
 
         if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
-                panic("Failed to insert cgu memory\n");
+                panic("Failed to insert cgu memory");
 
         if (request_mem_region(ltq_cgu_resource.start,
                         resource_size(&ltq_cgu_resource), "cgu") < 0)
-                panic("Failed to request cgu memory\n");
+                panic("Failed to request cgu memory");
 
         ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
                                 resource_size(&ltq_cgu_resource));
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index f9737bb3c5ab..d673731c538a 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -240,7 +240,6 @@ out:
 
 static struct irqaction cascade = {
         .handler = no_action,
-        .flags = IRQF_DISABLED,
         .name = "cascade",
 };
 
@@ -249,28 +248,28 @@ void __init arch_init_irq(void)
         int i;
 
         if (insert_resource(&iomem_resource, &ltq_icu_resource) < 0)
-                panic("Failed to insert icu memory\n");
+                panic("Failed to insert icu memory");
 
         if (request_mem_region(ltq_icu_resource.start,
                         resource_size(&ltq_icu_resource), "icu") < 0)
-                panic("Failed to request icu memory\n");
+                panic("Failed to request icu memory");
 
         ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start,
                                 resource_size(&ltq_icu_resource));
         if (!ltq_icu_membase)
-                panic("Failed to remap icu memory\n");
+                panic("Failed to remap icu memory");
 
         if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
-                panic("Failed to insert eiu memory\n");
+                panic("Failed to insert eiu memory");
 
         if (request_mem_region(ltq_eiu_resource.start,
                         resource_size(&ltq_eiu_resource), "eiu") < 0)
-                panic("Failed to request eiu memory\n");
+                panic("Failed to request eiu memory");
 
         ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
                                 resource_size(&ltq_eiu_resource));
         if (!ltq_eiu_membase)
-                panic("Failed to remap eiu memory\n");
+                panic("Failed to remap eiu memory");
 
         /* make sure all irqs are turned off by default */
         for (i = 0; i < 5; i++)
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index cbb6ae5747b9..b210e936c7c3 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -222,17 +222,17 @@ ltq_dma_init(void)
 
         /* insert and request the memory region */
         if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0)
-                panic("Failed to insert dma memory\n");
+                panic("Failed to insert dma memory");
 
         if (request_mem_region(ltq_dma_resource.start,
                         resource_size(&ltq_dma_resource), "dma") < 0)
-                panic("Failed to request dma memory\n");
+                panic("Failed to request dma memory");
 
         /* remap dma register range */
         ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
                                 resource_size(&ltq_dma_resource));
         if (!ltq_dma_membase)
-                panic("Failed to remap dma memory\n");
+                panic("Failed to remap dma memory");
 
         /* power up and reset the dma engine */
         ltq_pmu_enable(PMU_DMA);
diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c
index 033b3184c7a7..862e3e830680 100644
--- a/arch/mips/lantiq/xway/ebu.c
+++ b/arch/mips/lantiq/xway/ebu.c
@@ -32,17 +32,17 @@ static int __init lantiq_ebu_init(void)
 {
         /* insert and request the memory region */
         if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0)
-                panic("Failed to insert ebu memory\n");
+                panic("Failed to insert ebu memory");
 
         if (request_mem_region(ltq_ebu_resource.start,
                         resource_size(&ltq_ebu_resource), "ebu") < 0)
-                panic("Failed to request ebu memory\n");
+                panic("Failed to request ebu memory");
 
         /* remap ebu register range */
         ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
                                 resource_size(&ltq_ebu_resource));
         if (!ltq_ebu_membase)
-                panic("Failed to remap ebu memory\n");
+                panic("Failed to remap ebu memory");
 
         /* make sure to unprotect the memory region where flash is located */
         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c
index 39f0d2641cbf..fe85361e032e 100644
--- a/arch/mips/lantiq/xway/pmu.c
+++ b/arch/mips/lantiq/xway/pmu.c
@@ -40,7 +40,7 @@ void ltq_pmu_enable(unsigned int module)
         do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
 
         if (!err)
-                panic("activating PMU module failed!\n");
+                panic("activating PMU module failed!");
 }
 EXPORT_SYMBOL(ltq_pmu_enable);
 
@@ -53,16 +53,16 @@ EXPORT_SYMBOL(ltq_pmu_disable);
 int __init ltq_pmu_init(void)
 {
         if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0)
-                panic("Failed to insert pmu memory\n");
+                panic("Failed to insert pmu memory");
 
         if (request_mem_region(ltq_pmu_resource.start,
                         resource_size(&ltq_pmu_resource), "pmu") < 0)
-                panic("Failed to request pmu memory\n");
+                panic("Failed to request pmu memory");
 
         ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
                                 resource_size(&ltq_pmu_resource));
         if (!ltq_pmu_membase)
-                panic("Failed to remap pmu memory\n");
+                panic("Failed to remap pmu memory");
         return 0;
 }
 
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 3d41f0bb5bf7..8b66bd87f0c1 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -69,17 +69,17 @@ static int __init mips_reboot_setup(void)
 {
         /* insert and request the memory region */
         if (insert_resource(&iomem_resource, &ltq_rcu_resource) < 0)
-                panic("Failed to insert rcu memory\n");
+                panic("Failed to insert rcu memory");
 
         if (request_mem_region(ltq_rcu_resource.start,
                         resource_size(&ltq_rcu_resource), "rcu") < 0)
-                panic("Failed to request rcu memory\n");
+                panic("Failed to request rcu memory");
 
         /* remap rcu register range */
         ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
                                 resource_size(&ltq_rcu_resource));
         if (!ltq_rcu_membase)
-                panic("Failed to remap rcu memory\n");
+                panic("Failed to remap rcu memory");
 
         _machine_restart = ltq_machine_restart;
         _machine_halt = ltq_machine_halt;
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index b2cad4fd5fc4..2a7c74fc15fc 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX49XX)	+= dump_tlb.o
 obj-$(CONFIG_CPU_VR41XX)        += dump_tlb.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o
 obj-$(CONFIG_CPU_XLR)           += dump_tlb.o
+obj-$(CONFIG_CPU_XLP)           += dump_tlb.o
 
 # libgcc-style stuff needed in the kernel
 obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
index 0cb1b9760e34..5d1f48fa1a52 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -111,7 +111,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction irq5 = {
         .handler = timer_interrupt,
-        .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
+        .flags = IRQF_NOBALANCING | IRQF_TIMER,
         .name = "timer"
 };
 
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index dbf2f93a5091..a03bf00a1a9c 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -245,7 +245,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                  */
                 emulpc = xcp->cp0_epc + 4;      /* Snapshot emulation target */
 
-                if (__compute_return_epc(xcp)) {
+                if (__compute_return_epc(xcp) < 0) {
 #ifdef CP1DBG
                         printk("failed to emulate branch at %p\n",
                                 (void *) (xcp->cp0_epc));
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 4d8c1623eee2..4aa20280613e 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -3,8 +3,8 @@
 #
 
 obj-y                           += cache.o dma-default.o extable.o fault.o \
-                                   init.o mmap.o tlbex.o tlbex-fault.o uasm.o \
-                                   page.o
+                                   gup.o init.o mmap.o page.o tlbex.o \
+                                   tlbex-fault.o uasm.o
 
 obj-$(CONFIG_32BIT)             += ioremap.o pgtable-32.o
 obj-$(CONFIG_64BIT)             += pgtable-64.o
@@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_TX49XX)	+= c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_VR41XX)        += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
 obj-$(CONFIG_CPU_XLR)           += c-r4k.o tlb-r4k.o cex-gen.o
+obj-$(CONFIG_CPU_XLP)           += c-r4k.o tlb-r4k.o cex-gen.o
 
 obj-$(CONFIG_IP22_CPU_SCACHE)   += sc-ip22.o
 obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index daa81f7284ac..cf7895db0739 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -223,7 +223,7 @@ static void __cpuinit probe_octeon(void)
                 break;
 
         default:
-                panic("Unsupported Cavium Networks CPU type\n");
+                panic("Unsupported Cavium Networks CPU type");
                 break;
         }
 
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a79fe9aa7721..4f9eb0b23036 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void)
                 loongson2_sc_init();
                 return;
 #endif
+        case CPU_XLP:
+                /* don't need to worry about L2, fully coherent */
+                return;
 
         default:
                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c
new file mode 100644
index 000000000000..33aadbcf170b
--- /dev/null
+++ b/arch/mips/mm/gup.c
@@ -0,0 +1,315 @@
+/*
+ * Lockless get_user_pages_fast for MIPS
+ *
+ * Copyright (C) 2008 Nick Piggin
+ * Copyright (C) 2008 Novell Inc.
+ * Copyright (C) 2011 Ralf Baechle
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/vmstat.h>
+#include <linux/highmem.h>
+#include <linux/swap.h>
+#include <linux/hugetlb.h>
+
+#include <asm/pgtable.h>
+
+static inline pte_t gup_get_pte(pte_t *ptep)
+{
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+        pte_t pte;
+
+retry:
+        pte.pte_low = ptep->pte_low;
+        smp_rmb();
+        pte.pte_high = ptep->pte_high;
+        smp_rmb();
+        if (unlikely(pte.pte_low != ptep->pte_low))
+                goto retry;
+
+        return pte;
+#else
+        return ACCESS_ONCE(*ptep);
+#endif
+}
+
+static int gup_pte_range(pmd_t pmd, unsigned long addr, unsigned long end,
+                        int write, struct page **pages, int *nr)
+{
+        pte_t *ptep = pte_offset_map(&pmd, addr);
+        do {
+                pte_t pte = gup_get_pte(ptep);
+                struct page *page;
+
+                if (!pte_present(pte) ||
+                    pte_special(pte) || (write && !pte_write(pte))) {
+                        pte_unmap(ptep);
+                        return 0;
+                }
+                VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
+                page = pte_page(pte);
+                get_page(page);
+                SetPageReferenced(page);
+                pages[*nr] = page;
+                (*nr)++;
+
+        } while (ptep++, addr += PAGE_SIZE, addr != end);
+
+        pte_unmap(ptep - 1);
+        return 1;
+}
+
+static inline void get_head_page_multiple(struct page *page, int nr)
+{
+        VM_BUG_ON(page != compound_head(page));
+        VM_BUG_ON(page_count(page) == 0);
+        atomic_add(nr, &page->_count);
+        SetPageReferenced(page);
+}
+
+static int gup_huge_pmd(pmd_t pmd, unsigned long addr, unsigned long end,
+                        int write, struct page **pages, int *nr)
+{
+        pte_t pte = *(pte_t *)&pmd;
+        struct page *head, *page;
+        int refs;
+
+        if (write && !pte_write(pte))
+                return 0;
+        /* hugepages are never "special" */
+        VM_BUG_ON(pte_special(pte));
+        VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
+
+        refs = 0;
+        head = pte_page(pte);
+        page = head + ((addr & ~PMD_MASK) >> PAGE_SHIFT);
+        do {
+                VM_BUG_ON(compound_head(page) != head);
+                pages[*nr] = page;
+                if (PageTail(page))
+                        get_huge_page_tail(page);
+                (*nr)++;
+                page++;
+                refs++;
+        } while (addr += PAGE_SIZE, addr != end);
+
+        get_head_page_multiple(head, refs);
+        return 1;
+}
+
+static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
+                        int write, struct page **pages, int *nr)
+{
+        unsigned long next;
+        pmd_t *pmdp;
+
+        pmdp = pmd_offset(&pud, addr);
+        do {
+                pmd_t pmd = *pmdp;
+
+                next = pmd_addr_end(addr, end);
+                /*
+                 * The pmd_trans_splitting() check below explains why
+                 * pmdp_splitting_flush has to flush the tlb, to stop
+                 * this gup-fast code from running while we set the
+                 * splitting bit in the pmd. Returning zero will take
+                 * the slow path that will call wait_split_huge_page()
+                 * if the pmd is still in splitting state. gup-fast
+                 * can't because it has irq disabled and
+                 * wait_split_huge_page() would never return as the
+                 * tlb flush IPI wouldn't run.
+                 */
+                if (pmd_none(pmd) || pmd_trans_splitting(pmd))
+                        return 0;
+                if (unlikely(pmd_huge(pmd))) {
+                        if (!gup_huge_pmd(pmd, addr, next, write, pages,nr))
+                                return 0;
+                } else {
+                        if (!gup_pte_range(pmd, addr, next, write, pages,nr))
+                                return 0;
+                }
+        } while (pmdp++, addr = next, addr != end);
+
+        return 1;
+}
+
+static int gup_huge_pud(pud_t pud, unsigned long addr, unsigned long end,
+                        int write, struct page **pages, int *nr)
+{
+        pte_t pte = *(pte_t *)&pud;
+        struct page *head, *page;
+        int refs;
+
+        if (write && !pte_write(pte))
+                return 0;
+        /* hugepages are never "special" */
+        VM_BUG_ON(pte_special(pte));
+        VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
+
+        refs = 0;
+        head = pte_page(pte);
+        page = head + ((addr & ~PUD_MASK) >> PAGE_SHIFT);
+        do {
+                VM_BUG_ON(compound_head(page) != head);
+                pages[*nr] = page;
+                (*nr)++;
+                page++;
+                refs++;
+        } while (addr += PAGE_SIZE, addr != end);
+
+        get_head_page_multiple(head, refs);
+        return 1;
+}
+
+static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
+                        int write, struct page **pages, int *nr)
+{
+        unsigned long next;
+        pud_t *pudp;
+
+        pudp = pud_offset(&pgd, addr);
+        do {
+                pud_t pud = *pudp;
+
+                next = pud_addr_end(addr, end);
+                if (pud_none(pud))
+                        return 0;
+                if (unlikely(pud_huge(pud))) {
+                        if (!gup_huge_pud(pud, addr, next, write, pages,nr))
+                                return 0;
+                } else {
+                        if (!gup_pmd_range(pud, addr, next, write, pages,nr))
+                                return 0;
+                }
+        } while (pudp++, addr = next, addr != end);
+
+        return 1;
+}
+
+/*
+ * Like get_user_pages_fast() except its IRQ-safe in that it won't fall
+ * back to the regular GUP.
+ */
+int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
+                          struct page **pages)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long addr, len, end;
+        unsigned long next;
+        unsigned long flags;
+        pgd_t *pgdp;
+        int nr = 0;
+
+        start &= PAGE_MASK;
+        addr = start;
+        len = (unsigned long) nr_pages << PAGE_SHIFT;
+        end = start + len;
+        if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ,
+                                        (void __user *)start, len)))
+                return 0;
+
+        /*
+         * XXX: batch / limit 'nr', to avoid large irq off latency
+         * needs some instrumenting to determine the common sizes used by
+         * important workloads (eg. DB2), and whether limiting the batch
+         * size will decrease performance.
+         *
+         * It seems like we're in the clear for the moment. Direct-IO is
+         * the main guy that batches up lots of get_user_pages, and even
+         * they are limited to 64-at-a-time which is not so many.
+         */
+        /*
+         * This doesn't prevent pagetable teardown, but does prevent
+         * the pagetables and pages from being freed.
+         *
+         * So long as we atomically load page table pointers versus teardown,
+         * we can follow the address down to the page and take a ref on it.
+         */
+        local_irq_save(flags);
+        pgdp = pgd_offset(mm, addr);
+        do {
+                pgd_t pgd = *pgdp;
+
+                next = pgd_addr_end(addr, end);
+                if (pgd_none(pgd))
+                        break;
+                if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
+                        break;
+        } while (pgdp++, addr = next, addr != end);
+        local_irq_restore(flags);
+
+        return nr;
+}
+
+/**
+ * get_user_pages_fast() - pin user pages in memory
+ * @start:      starting user address
+ * @nr_pages:   number of pages from start to pin
+ * @write:      whether pages will be written to
+ * @pages:      array that receives pointers to the pages pinned.
+ *              Should be at least nr_pages long.
+ *
+ * Attempt to pin user pages in memory without taking mm->mmap_sem.
+ * If not successful, it will fall back to taking the lock and
+ * calling get_user_pages().
+ *
+ * Returns number of pages pinned. This may be fewer than the number
+ * requested. If nr_pages is 0 or negative, returns 0. If no pages
+ * were pinned, returns -errno.
+ */
+int get_user_pages_fast(unsigned long start, int nr_pages, int write,
+                        struct page **pages)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long addr, len, end;
+        unsigned long next;
+        pgd_t *pgdp;
+        int ret, nr = 0;
+
+        start &= PAGE_MASK;
+        addr = start;
+        len = (unsigned long) nr_pages << PAGE_SHIFT;
+
+        end = start + len;
+        if (end < start)
+                goto slow_irqon;
+
+        /* XXX: batch / limit 'nr' */
+        local_irq_disable();
+        pgdp = pgd_offset(mm, addr);
+        do {
+                pgd_t pgd = *pgdp;
+
+                next = pgd_addr_end(addr, end);
+                if (pgd_none(pgd))
+                        goto slow;
+                if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
+                        goto slow;
+        } while (pgdp++, addr = next, addr != end);
+        local_irq_enable();
+
+        VM_BUG_ON(nr != (end - start) >> PAGE_SHIFT);
+        return nr;
+slow:
+        local_irq_enable();
+
+slow_irqon:
+        /* Try to get the remaining pages with get_user_pages */
+        start += nr << PAGE_SHIFT;
+        pages += nr;
+
+        down_read(&mm->mmap_sem);
+        ret = get_user_pages(current, mm, start,
+                                (end - start) >> PAGE_SHIFT,
+                                write, 0, pages, NULL);
+        up_read(&mm->mmap_sem);
+
+        /* Have to be a bit careful with return values */
+        if (nr > 0) {
+                if (ret < 0)
+                        ret = nr;
+                else
+                        ret += nr;
+        }
+        return ret;
+}
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index b7ebc4fa89bc..3b3ffd439cd7 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -304,9 +304,14 @@ int page_is_ram(unsigned long pagenr)
         for (i = 0; i < boot_mem_map.nr_map; i++) {
                 unsigned long addr, end;
 
-                if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
+                switch (boot_mem_map.map[i].type) {
+                case BOOT_MEM_RAM:
+                case BOOT_MEM_INIT_RAM:
+                        break;
+                default:
                         /* not usable memory */
                         continue;
+                }
 
                 addr = PFN_UP(boot_mem_map.map[i].addr);
                 end = PFN_DOWN(boot_mem_map.map[i].addr +
@@ -379,7 +384,7 @@ void __init mem_init(void)
 
         reservedpages = ram = 0;
         for (tmp = 0; tmp < max_low_pfn; tmp++)
-                if (page_is_ram(tmp)) {
+                if (page_is_ram(tmp) && pfn_valid(tmp)) {
                         ram++;
                         if (PageReserved(pfn_to_page(tmp)))
                                 reservedpages++;
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index 87bb85d8d537..ed1fa460f84e 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -20,6 +20,7 @@
 #include <asm/pgtable.h>
 #include <asm/mmu_context.h>
 #include <asm/system.h>
+#include <asm/tlbmisc.h>
 #include <asm/isadep.h>
 #include <asm/io.h>
 #include <asm/bootinfo.h>
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 0d394e0e8837..2dc625346c40 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -19,6 +19,7 @@
 #include <asm/mmu_context.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
+#include <asm/tlbmisc.h>
 
 extern void build_tlb_refill_handler(void);
 
@@ -120,22 +121,30 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 
         if (cpu_context(cpu, mm) != 0) {
                 unsigned long size, flags;
+                int huge = is_vm_hugetlb_page(vma);
 
                 ENTER_CRITICAL(flags);
-                size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-                size = (size + 1) >> 1;
+                if (huge) {
+                        start = round_down(start, HPAGE_SIZE);
+                        end = round_up(end, HPAGE_SIZE);
+                        size = (end - start) >> HPAGE_SHIFT;
+                } else {
+                        start = round_down(start, PAGE_SIZE << 1);
+                        end = round_up(end, PAGE_SIZE << 1);
+                        size = (end - start) >> (PAGE_SHIFT + 1);
+                }
                 if (size <= current_cpu_data.tlbsize/2) {
                         int oldpid = read_c0_entryhi();
                         int newpid = cpu_asid(cpu, mm);
 
-                        start &= (PAGE_MASK << 1);
-                        end += ((PAGE_SIZE << 1) - 1);
-                        end &= (PAGE_MASK << 1);
                         while (start < end) {
                                 int idx;
 
                                 write_c0_entryhi(start | newpid);
-                                start += (PAGE_SIZE << 1);
+                                if (huge)
+                                        start += HPAGE_SIZE;
+                                else
+                                        start += (PAGE_SIZE << 1);
                                 mtc0_tlbw_hazard();
                                 tlb_probe();
                                 tlb_probe_hazard();
@@ -368,51 +377,6 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
         EXIT_CRITICAL(flags);
 }
 
-/*
- * Used for loading TLB entries before trap_init() has started, when we
- * don't actually want to add a wired entry which remains throughout the
- * lifetime of the system
- */
-
-static int temp_tlb_entry __cpuinitdata;
-
-__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
-                               unsigned long entryhi, unsigned long pagemask)
-{
-        int ret = 0;
-        unsigned long flags;
-        unsigned long wired;
-        unsigned long old_pagemask;
-        unsigned long old_ctx;
-
-        ENTER_CRITICAL(flags);
-        /* Save old context and create impossible VPN2 value */
-        old_ctx = read_c0_entryhi();
-        old_pagemask = read_c0_pagemask();
-        wired = read_c0_wired();
-        if (--temp_tlb_entry < wired) {
-                printk(KERN_WARNING
-                       "No TLB space left for add_temporary_entry\n");
-                ret = -ENOSPC;
-                goto out;
-        }
-
-        write_c0_index(temp_tlb_entry);
-        write_c0_pagemask(pagemask);
-        write_c0_entryhi(entryhi);
-        write_c0_entrylo0(entrylo0);
-        write_c0_entrylo1(entrylo1);
-        mtc0_tlbw_hazard();
-        tlb_write_indexed();
-        tlbw_use_hazard();
-
-        write_c0_entryhi(old_ctx);
-        write_c0_pagemask(old_pagemask);
-out:
-        EXIT_CRITICAL(flags);
-        return ret;
-}
-
 static int __cpuinitdata ntlb;
 static int __init set_ntlb(char *str)
 {
@@ -450,8 +414,6 @@ void __cpuinit tlb_init(void)
                 write_c0_pagegrain(pg);
         }
 
-        temp_tlb_entry = current_cpu_data.tlbsize - 1;
-
         /* From this point on the ARC firmware is dead.  */
         local_flush_tlb_all();
 
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index d53ff91b277c..a588b5cef8d2 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -322,13 +322,13 @@ static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
 
 static struct irqaction irq_resched = {
         .handler        = ipi_resched_interrupt,
-        .flags          = IRQF_DISABLED|IRQF_PERCPU,
+        .flags          = IRQF_PERCPU,
         .name           = "IPI_resched"
 };
 
 static struct irqaction irq_call = {
         .handler        = ipi_call_interrupt,
-        .flags          = IRQF_DISABLED|IRQF_PERCPU,
+        .flags          = IRQF_PERCPU,
         .name           = "IPI_call"
 };
 #endif /* CONFIG_MIPS_MT_SMP */
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index a5ca743613f2..75bec44b5856 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -1,5 +1,2 @@
 config NLM_COMMON
         bool
-
-config NLM_XLR
-        bool
diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile
new file mode 100644
index 000000000000..36d169b2ca6d
--- /dev/null
+++ b/arch/mips/netlogic/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_NLM_COMMON)        +=      common/
+obj-$(CONFIG_CPU_XLR)           +=      xlr/
+obj-$(CONFIG_CPU_XLP)           +=      xlp/
diff --git a/arch/mips/netlogic/Platform b/arch/mips/netlogic/Platform
index b648b487fd66..cdfc9abbbb7b 100644
--- a/arch/mips/netlogic/Platform
+++ b/arch/mips/netlogic/Platform
@@ -1,16 +1,17 @@
 #
 # NETLOGIC includes
 #
-cflags-$(CONFIG_NLM_COMMON)  += -I$(srctree)/arch/mips/include/asm/mach-netlogic
-cflags-$(CONFIG_NLM_COMMON)  += -I$(srctree)/arch/mips/include/asm/netlogic
+cflags-$(CONFIG_NLM_COMMON)     += -I$(srctree)/arch/mips/include/asm/mach-netlogic
+cflags-$(CONFIG_NLM_COMMON)     += -I$(srctree)/arch/mips/include/asm/netlogic
 
 #
 # use mips64 if xlr is not available
 #
-cflags-$(CONFIG_NLM_XLR)        += $(call cc-option,-march=xlr,-march=mips64)
+cflags-$(CONFIG_CPU_XLR)        += $(call cc-option,-march=xlr,-march=mips64)
+cflags-$(CONFIG_CPU_XLP)        += $(call cc-option,-march=xlp,-march=mips64r2)
 
 #
-# NETLOGIC XLR/XLS SoC, Simulator and boards
+# NETLOGIC processor support
 #
-core-$(CONFIG_NLM_XLR)        += arch/mips/netlogic/xlr/
-load-$(CONFIG_NLM_XLR_BOARD)  += 0xffffffff84000000
+platform-$(CONFIG_NLM_COMMON)   += netlogic/
+load-$(CONFIG_NLM_COMMON)       += 0xffffffff80100000
diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile
new file mode 100644
index 000000000000..291372a086f5
--- /dev/null
+++ b/arch/mips/netlogic/common/Makefile
@@ -0,0 +1,3 @@
+obj-y                           += irq.o time.o
+obj-$(CONFIG_SMP)               += smp.o smpboot.o
+obj-$(CONFIG_EARLY_PRINTK)      += earlycons.o
diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c
new file mode 100644
index 000000000000..f193f7b3bd81
--- /dev/null
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+
+#include <asm/mipsregs.h>
+#include <asm/netlogic/haldefs.h>
+
+#if defined(CONFIG_CPU_XLP)
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/uart.h>
+#elif defined(CONFIG_CPU_XLR)
+#include <asm/netlogic/xlr/iomap.h>
+#endif
+
+void prom_putchar(char c)
+{
+        uint64_t uartbase;
+
+#if defined(CONFIG_CPU_XLP)
+        uartbase = nlm_get_uart_regbase(0, 0);
+#elif defined(CONFIG_CPU_XLR)
+        uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
+#endif
+        while (nlm_read_reg(uartbase, UART_LSR) == 0)
+                ;
+        nlm_write_reg(uartbase, UART_TX, c);
+}
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
new file mode 100644
index 000000000000..49a4f6cf71e5
--- /dev/null
+++ b/arch/mips/netlogic/common/irq.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+
+#include <asm/errno.h>
+#include <asm/signal.h>
+#include <asm/system.h>
+#include <asm/ptrace.h>
+#include <asm/mipsregs.h>
+#include <asm/thread_info.h>
+
+#include <asm/netlogic/mips-extns.h>
+#include <asm/netlogic/interrupt.h>
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+
+#if defined(CONFIG_CPU_XLP)
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#elif defined(CONFIG_CPU_XLR)
+#include <asm/netlogic/xlr/iomap.h>
+#include <asm/netlogic/xlr/pic.h>
+#else
+#error "Unknown CPU"
+#endif
+/*
+ * These are the routines that handle all the low level interrupt stuff.
+ * Actions handled here are: initialization of the interrupt map, requesting of
+ * interrupt lines by handlers, dispatching if interrupts to handlers, probing
+ * for interrupt lines
+ */
+
+/* Globals */
+static uint64_t nlm_irq_mask;
+static DEFINE_SPINLOCK(nlm_pic_lock);
+
+static void xlp_pic_enable(struct irq_data *d)
+{
+        unsigned long flags;
+        int irt;
+
+        irt = nlm_irq_to_irt(d->irq);
+        if (irt == -1)
+                return;
+        spin_lock_irqsave(&nlm_pic_lock, flags);
+        nlm_pic_enable_irt(nlm_pic_base, irt);
+        spin_unlock_irqrestore(&nlm_pic_lock, flags);
+}
+
+static void xlp_pic_disable(struct irq_data *d)
+{
+        unsigned long flags;
+        int irt;
+
+        irt = nlm_irq_to_irt(d->irq);
+        if (irt == -1)
+                return;
+        spin_lock_irqsave(&nlm_pic_lock, flags);
+        nlm_pic_disable_irt(nlm_pic_base, irt);
+        spin_unlock_irqrestore(&nlm_pic_lock, flags);
+}
+
+static void xlp_pic_mask_ack(struct irq_data *d)
+{
+        uint64_t mask = 1ull << d->irq;
+
+        write_c0_eirr(mask);            /* ack by writing EIRR */
+}
+
+static void xlp_pic_unmask(struct irq_data *d)
+{
+        void *hd = irq_data_get_irq_handler_data(d);
+        int irt;
+
+        irt = nlm_irq_to_irt(d->irq);
+        if (irt == -1)
+                return;
+
+        if (hd) {
+                void (*extra_ack)(void *) = hd;
+                extra_ack(d);
+        }
+        /* Ack is a single write, no need to lock */
+        nlm_pic_ack(nlm_pic_base, irt);
+}
+
+static struct irq_chip xlp_pic = {
+        .name           = "XLP-PIC",
+        .irq_enable     = xlp_pic_enable,
+        .irq_disable    = xlp_pic_disable,
+        .irq_mask_ack   = xlp_pic_mask_ack,
+        .irq_unmask     = xlp_pic_unmask,
+};
+
+static void cpuintr_disable(struct irq_data *d)
+{
+        uint64_t eimr;
+        uint64_t mask = 1ull << d->irq;
+
+        eimr = read_c0_eimr();
+        write_c0_eimr(eimr & ~mask);
+}
+
+static void cpuintr_enable(struct irq_data *d)
+{
+        uint64_t eimr;
+        uint64_t mask = 1ull << d->irq;
+
+        eimr = read_c0_eimr();
+        write_c0_eimr(eimr | mask);
+}
+
+static void cpuintr_ack(struct irq_data *d)
+{
+        uint64_t mask = 1ull << d->irq;
+
+        write_c0_eirr(mask);
+}
+
+static void cpuintr_nop(struct irq_data *d)
+{
+        WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
+}
+
+/*
+ * Chip definition for CPU originated interrupts(timer, msg) and
+ * IPIs
+ */
+struct irq_chip nlm_cpu_intr = {
+        .name           = "XLP-CPU-INTR",
+        .irq_enable     = cpuintr_enable,
+        .irq_disable    = cpuintr_disable,
+        .irq_mask       = cpuintr_nop,
+        .irq_ack        = cpuintr_nop,
+        .irq_eoi        = cpuintr_ack,
+};
+
+void __init init_nlm_common_irqs(void)
+{
+        int i, irq, irt;
+
+        for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
+                irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
+
+        for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ ; i++)
+                irq_set_chip_and_handler(i, &xlp_pic, handle_level_irq);
+
+#ifdef CONFIG_SMP
+        irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
+                         nlm_smp_function_ipi_handler);
+        irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
+                         nlm_smp_resched_ipi_handler);
+        nlm_irq_mask |=
+            ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
+#endif
+
+        for (irq = PIC_IRT_FIRST_IRQ; irq <= PIC_IRT_LAST_IRQ; irq++) {
+                irt = nlm_irq_to_irt(irq);
+                if (irt == -1)
+                        continue;
+                nlm_irq_mask |= (1ULL << irq);
+                nlm_pic_init_irt(nlm_pic_base, irt, irq, 0);
+        }
+
+        nlm_irq_mask |= (1ULL << IRQ_TIMER);
+}
+
+void __init arch_init_irq(void)
+{
+        /* Initialize the irq descriptors */
+        init_nlm_common_irqs();
+
+        write_c0_eimr(nlm_irq_mask);
+}
+
+void __cpuinit nlm_smp_irq_init(void)
+{
+        /* set interrupt mask for non-zero cpus */
+        write_c0_eimr(nlm_irq_mask);
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        uint64_t eirr;
+        int i;
+
+        eirr = read_c0_eirr() & read_c0_eimr();
+        if (eirr & (1 << IRQ_TIMER)) {
+                do_IRQ(IRQ_TIMER);
+                return;
+        }
+
+        i = __ilog2_u64(eirr);
+        if (i == -1)
+                return;
+
+        do_IRQ(i);
+}
diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/common/smp.c
index 080284ded508..db17f49886c2 100644
--- a/arch/mips/netlogic/xlr/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -42,31 +42,29 @@
 
 #include <asm/netlogic/interrupt.h>
 #include <asm/netlogic/mips-extns.h>
-
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+
+#if defined(CONFIG_CPU_XLP)
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#elif defined(CONFIG_CPU_XLR)
 #include <asm/netlogic/xlr/iomap.h>
 #include <asm/netlogic/xlr/pic.h>
 #include <asm/netlogic/xlr/xlr.h>
+#else
+#error "Unknown CPU"
+#endif
 
-void core_send_ipi(int logical_cpu, unsigned int action)
+void nlm_send_ipi_single(int logical_cpu, unsigned int action)
 {
         int cpu = cpu_logical_map(logical_cpu);
-        u32 tid = cpu & 0x3;
-        u32 pid = (cpu >> 2) & 0x07;
-        u32 ipi = (tid << 16) | (pid << 20);
 
         if (action & SMP_CALL_FUNCTION)
-                ipi |= IRQ_IPI_SMP_FUNCTION;
-        else if (action & SMP_RESCHEDULE_YOURSELF)
-                ipi |= IRQ_IPI_SMP_RESCHEDULE;
-        else
-                return;
-
-        pic_send_ipi(ipi);
-}
-
-void nlm_send_ipi_single(int cpu, unsigned int action)
-{
-        core_send_ipi(cpu, action);
+                nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_FUNCTION, 0);
+        if (action & SMP_RESCHEDULE_YOURSELF)
+                nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
 }
 
 void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
@@ -74,29 +72,35 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
         int cpu;
 
         for_each_cpu(cpu, mask) {
-                core_send_ipi(cpu, action);
+                nlm_send_ipi_single(cpu, action);
         }
 }
 
 /* IRQ_IPI_SMP_FUNCTION Handler */
 void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
 {
+        write_c0_eirr(1ull << irq);
         smp_call_function_interrupt();
 }
 
 /* IRQ_IPI_SMP_RESCHEDULE  handler */
 void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
 {
+        write_c0_eirr(1ull << irq);
         scheduler_ipi();
 }
 
 /*
  * Called before going into mips code, early cpu init
  */
-void nlm_early_init_secondary(void)
+void nlm_early_init_secondary(int cpu)
 {
+        change_c0_config(CONF_CM_CMASK, 0x3);
         write_c0_ebase((uint32_t)nlm_common_ebase);
-        /* TLB partition here later */
+#ifdef CONFIG_CPU_XLP
+        if (hard_smp_processor_id() % 4 == 0)
+                xlp_mmu_init();
+#endif
 }
 
 /*
@@ -104,9 +108,16 @@ void nlm_early_init_secondary(void)
  */
 static void __cpuinit nlm_init_secondary(void)
 {
+        current_cpu_data.core = hard_smp_processor_id() / 4;
         nlm_smp_irq_init();
 }
 
+void nlm_prepare_cpus(unsigned int max_cpus)
+{
+        /* declare we are SMT capable */
+        smp_num_siblings = nlm_threads_per_core;
+}
+
 void nlm_smp_finish(void)
 {
 #ifdef notyet
@@ -123,10 +134,10 @@ void nlm_cpus_done(void)
  * Boot all other cpus in the system, initialize them, and bring them into
  * the boot function
  */
-int nlm_cpu_unblock[NR_CPUS];
 int nlm_cpu_ready[NR_CPUS];
 unsigned long nlm_next_gp;
 unsigned long nlm_next_sp;
+
 cpumask_t phys_cpu_present_map;
 
 void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
@@ -140,7 +151,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
 
         /* barrier */
         __sync();
-        nlm_cpu_unblock[cpu] = 1;
+        nlm_pic_send_ipi(nlm_pic_base, cpu, 1, 1);
 }
 
 void __init nlm_smp_setup(void)
@@ -159,8 +170,8 @@ void __init nlm_smp_setup(void)
         num_cpus = 1;
         for (i = 0; i < NR_CPUS; i++) {
                 /*
-                 * BSP is not set in nlm_cpu_ready array, it is only for
-                 * ASPs (goto see smpboot.S)
+                 * nlm_cpu_ready array is not set for the boot_cpu,
+                 * it is only set for ASPs (see smpboot.S)
                  */
                 if (nlm_cpu_ready[i]) {
                         cpu_set(i, phys_cpu_present_map);
@@ -176,10 +187,75 @@ void __init nlm_smp_setup(void)
                 (unsigned long)cpu_possible_map.bits[0]);
 
         pr_info("Detected %i Slave CPU(s)\n", num_cpus);
+        nlm_set_nmi_handler(nlm_boot_secondary_cpus);
 }
 
-void nlm_prepare_cpus(unsigned int max_cpus)
+static int nlm_parse_cpumask(u32 cpu_mask)
+{
+        uint32_t core0_thr_mask, core_thr_mask;
+        int threadmode, i;
+
+        core0_thr_mask = cpu_mask & 0xf;
+        switch (core0_thr_mask) {
+        case 1:
+                nlm_threads_per_core = 1;
+                threadmode = 0;
+                break;
+        case 3:
+                nlm_threads_per_core = 2;
+                threadmode = 2;
+                break;
+        case 0xf:
+                nlm_threads_per_core = 4;
+                threadmode = 3;
+                break;
+        default:
+                goto unsupp;
+        }
+
+        /* Verify other cores CPU masks */
+        nlm_coremask = 1;
+        nlm_cpumask = core0_thr_mask;
+        for (i = 1; i < 8; i++) {
+                core_thr_mask = (cpu_mask >> (i * 4)) & 0xf;
+                if (core_thr_mask) {
+                        if (core_thr_mask != core0_thr_mask)
+                                goto unsupp;
+                        nlm_coremask |= 1 << i;
+                        nlm_cpumask |= core0_thr_mask << (4 * i);
+                }
+        }
+        return threadmode;
+
+unsupp:
+        panic("Unsupported CPU mask %x\n", cpu_mask);
+        return 0;
+}
+
+int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
 {
+        unsigned long reset_vec;
+        char *reset_data;
+        int threadmode;
+
+        /* Update reset entry point with CPU init code */
+        reset_vec = CKSEG1ADDR(RESET_VEC_PHYS);
+        memcpy((void *)reset_vec, (void *)nlm_reset_entry,
+                        (nlm_reset_entry_end - nlm_reset_entry));
+
+        /* verify the mask and setup core config variables */
+        threadmode = nlm_parse_cpumask(wakeup_mask);
+
+        /* Setup CPU init parameters */
+        reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
+        *(int *)(reset_data + BOOT_THREAD_MODE) = threadmode;
+
+#ifdef CONFIG_CPU_XLP
+        xlp_wakeup_secondary_cpus();
+#else
+        xlr_wakeup_secondary_cpus();
+#endif
+        return 0;
 }
 
 struct plat_smp_ops nlm_smp_ops = {
@@ -192,29 +268,3 @@ struct plat_smp_ops nlm_smp_ops = {
         .smp_setup              = nlm_smp_setup,
         .prepare_cpus           = nlm_prepare_cpus,
 };
-
-unsigned long secondary_entry_point;
-
-int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
-{
-        unsigned int tid, pid, ipi, i, boot_cpu;
-        void *reset_vec;
-
-        secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
-        reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
-        memcpy(reset_vec, nlm_boot_smp_nmi, 0x80);
-        boot_cpu = hard_smp_processor_id();
-
-        for (i = 0; i < NR_CPUS; i++) {
-                if (i == boot_cpu)
-                        continue;
-                if (wakeup_mask & (1u << i)) {
-                        tid = i & 0x3;
-                        pid = (i >> 2) & 0x7;
-                        ipi = (tid << 16) | (pid << 20) | (1 << 8);
-                        pic_send_ipi(ipi);
-                }
-        }
-
-        return 0;
-}
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
new file mode 100644
index 000000000000..c138b1a6dec3
--- /dev/null
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -0,0 +1,272 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/init.h>
+
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/stackframe.h>
+#include <asm/asmmacro.h>
+#include <asm/addrspace.h>
+
+#include <asm/netlogic/common.h>
+
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/sys.h>
+#include <asm/netlogic/xlp-hal/cpucontrol.h>
+
+#define CP0_EBASE       $15
+#define SYS_CPU_COHERENT_BASE(node)     CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
+                        XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
+                        SYS_CPU_NONCOHERENT_MODE * 4
+
+.macro __config_lsu
+        li      t0, LSU_DEFEATURE
+        mfcr    t1, t0
+
+        lui     t2, 0x4080  /* Enable Unaligned Access, L2HPE */
+        or      t1, t1, t2
+        li      t2, ~0xe    /* S1RCM */
+        and     t1, t1, t2
+        mtcr    t1, t0
+
+        li      t0, SCHED_DEFEATURE
+        lui     t1, 0x0100  /* Experimental: Disable BRU accepting ALU ops */
+        mtcr    t1, t0
+.endm
+
+/*
+ * The cores can come start when they are woken up. This is also the NMI
+ * entry, so check that first.
+ *
+ * The data corresponding to reset is stored at RESET_DATA_PHYS location,
+ * this will have the thread mask (used when core is woken up) and the
+ * current NMI handler in case we reached here for an NMI.
+ *
+ * When a core or thread is newly woken up, it loops in a 'wait'. When
+ * the CPU really needs waking up, we send an NMI to it, with the NMI
+ * handler set to prom_boot_secondary_cpus
+ */
+
+        .set    noreorder
+        .set    noat
+        .set    arch=xlr        /* for mfcr/mtcr, XLR is sufficient */
+
+FEXPORT(nlm_reset_entry)
+        dmtc0   k0, $22, 6
+        dmtc0   k1, $22, 7
+        mfc0    k0, CP0_STATUS
+        li      k1, 0x80000
+        and     k1, k0, k1
+        beqz    k1, 1f         /* go to real reset entry */
+        nop
+        li      k1, CKSEG1ADDR(RESET_DATA_PHYS)   /* NMI */
+        ld      k0, BOOT_NMI_HANDLER(k1)
+        jr      k0
+        nop
+
+1:      /* Entry point on core wakeup */
+        mfc0    t0, CP0_EBASE, 1
+        mfc0    t1, CP0_EBASE, 1
+        srl     t1, 5
+        andi    t1, 0x3                 /* t1 <- node */
+        li      t2, 0x40000
+        mul     t3, t2, t1              /* t3 = node * 0x40000 */
+        srl     t0, t0, 2
+        and     t0, t0, 0x7             /* t0 <- core */
+        li      t1, 0x1
+        sll     t0, t1, t0
+        nor     t0, t0, zero            /* t0 <- ~(1 << core) */
+        li      t2, SYS_CPU_COHERENT_BASE(0)
+        add     t2, t2, t3              /* t2 <- SYS offset for node */
+        lw      t1, 0(t2)
+        and     t1, t1, t0
+        sw      t1, 0(t2)
+
+        /* read back to ensure complete */
+        lw      t1, 0(t2)
+        sync
+
+        /* Configure LSU on Non-0 Cores. */
+        __config_lsu
+
+/*
+ * Wake up sibling threads from the initial thread in
+ * a core.
+ */
+EXPORT(nlm_boot_siblings)
+        li      t0, CKSEG1ADDR(RESET_DATA_PHYS)
+        lw      t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
+        li      t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
+        mfcr    t2, t0
+        or      t2, t2, t1
+        mtcr    t2, t0
+
+        /*
+         * The new hardware thread starts at the next instruction
+         * For all the cases other than core 0 thread 0, we will
+         * jump to the secondary wait function.
+         */
+        mfc0    v0, CP0_EBASE, 1
+        andi    v0, 0x7f                /* v0 <- node/core */
+
+#if 1
+        /* A0 errata - Write MMU_SETUP after changing thread mode register. */
+        andi    v1, v0, 0x3             /* v1 <- thread id */
+        bnez    v1, 2f
+        nop
+
+        li      t0, MMU_SETUP
+        li      t1, 0
+        mtcr    t1, t0
+        ehb
+#endif
+
+2:      beqz    v0, 4f
+        nop
+
+        /* setup status reg */
+        mfc0    t1, CP0_STATUS
+        li      t0, ST0_BEV
+        or      t1, t0
+        xor     t1, t0
+#ifdef CONFIG_64BIT
+        ori     t1, ST0_KX
+#endif
+        mtc0    t1, CP0_STATUS
+        /* mark CPU ready */
+        PTR_LA  t1, nlm_cpu_ready
+        sll     v1, v0, 2
+        PTR_ADDU t1, v1
+        li      t2, 1
+        sw      t2, 0(t1)
+        /* Wait until NMI hits */
+3:      wait
+        j       3b
+        nop
+
+        /*
+         * For the boot CPU, we have to restore registers and
+         * return
+         */
+4:      dmfc0   t0, $4, 2       /* restore SP from UserLocal */
+        li      t1, 0xfadebeef
+        dmtc0   t1, $4, 2       /* restore SP from UserLocal */
+        PTR_SUBU sp, t0, PT_SIZE
+        RESTORE_ALL
+        jr   ra
+        nop
+EXPORT(nlm_reset_entry_end)
+
+FEXPORT(xlp_boot_core0_siblings)        /* "Master" cpu starts from here */
+        __config_lsu
+        dmtc0   sp, $4, 2               /* SP saved in UserLocal */
+        SAVE_ALL
+        sync
+        /* find the location to which nlm_boot_siblings was relocated */
+        li      t0, CKSEG1ADDR(RESET_VEC_PHYS)
+        dla     t1, nlm_reset_entry
+        dla     t2, nlm_boot_siblings
+        dsubu   t2, t1
+        daddu   t2, t0
+        /* call it */
+        jr      t2
+        nop
+        /* not reached */
+
+        __CPUINIT
+NESTED(nlm_boot_secondary_cpus, 16, sp)
+        PTR_LA  t1, nlm_next_sp
+        PTR_L   sp, 0(t1)
+        PTR_LA  t1, nlm_next_gp
+        PTR_L   gp, 0(t1)
+
+        /* a0 has the processor id */
+        PTR_LA  t0, nlm_early_init_secondary
+        jalr    t0
+        nop
+
+        PTR_LA  t0, smp_bootstrap
+        jr      t0
+        nop
+END(nlm_boot_secondary_cpus)
+        __FINIT
+
+/*
+ * In case of RMIboot bootloader which is used on XLR boards, the CPUs
+ * be already woken up and waiting in bootloader code.
+ * This will get them out of the bootloader code and into linux. Needed
+ *  because the bootloader area will be taken and initialized by linux.
+ */
+        __CPUINIT
+NESTED(nlm_rmiboot_preboot, 16, sp)
+        mfc0    t0, $15, 1      # read ebase
+        andi    t0, 0x1f        # t0 has the processor_id()
+        andi    t2, t0, 0x3     # thread no
+        sll     t0, 2           # offset in cpu array
+
+        PTR_LA  t1, nlm_cpu_ready # mark CPU ready
+        PTR_ADDU t1, t0
+        li      t3, 1
+        sw      t3, 0(t1)
+
+        bnez    t2, 1f          # skip thread programming
+        nop                     # for non zero hw threads
+
+        /*
+         * MMU setup only for first thread in core
+         */
+        li      t0, 0x400
+        mfcr    t1, t0
+        li      t2, 6           # XLR thread mode mask
+        nor     t3, t2, zero
+        and     t2, t1, t2      # t2 - current thread mode
+        li      v0, CKSEG1ADDR(RESET_DATA_PHYS)
+        lw      v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode
+        sll     v1, 1
+        beq     v1, t2, 1f      # same as request value
+        nop                     # nothing to do */
+
+        and     t2, t1, t3      # mask out old thread mode
+        or      t1, t2, v1      # put in new value
+        mtcr    t1, t0          # update core control
+
+1:      wait
+        j       1b
+        nop
+END(nlm_rmiboot_preboot)
+        __FINIT
diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/common/time.c
index 0d81b262593c..bd3e498157ff 100644
--- a/arch/mips/netlogic/xlr/time.c
+++ b/arch/mips/netlogic/common/time.c
@@ -36,7 +36,7 @@
 
 #include <asm/time.h>
 #include <asm/netlogic/interrupt.h>
-#include <asm/netlogic/psb-bootinfo.h>
+#include <asm/netlogic/common.h>
 
 unsigned int __cpuinit get_c0_compare_int(void)
 {
@@ -45,7 +45,7 @@ unsigned int __cpuinit get_c0_compare_int(void)
 
 void __init plat_time_init(void)
 {
-        mips_hpt_frequency = nlm_prom_info.cpu_frequency;
+        mips_hpt_frequency = nlm_get_cpu_frequency();
         pr_info("MIPS counter frequency [%ld]\n",
-                (unsigned long)mips_hpt_frequency);
+                        (unsigned long)mips_hpt_frequency);
 }
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
new file mode 100644
index 000000000000..b93ed83474ec
--- /dev/null
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -0,0 +1,2 @@
+obj-y                           += setup.o platform.o nlm_hal.o
+obj-$(CONFIG_SMP)               += wakeup.o
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
new file mode 100644
index 000000000000..9428e7125fed
--- /dev/null
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+
+#include <asm/mipsregs.h>
+#include <asm/time.h>
+
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#include <asm/netlogic/xlp-hal/sys.h>
+
+/* These addresses are computed by the nlm_hal_init() */
+uint64_t nlm_io_base;
+uint64_t nlm_sys_base;
+uint64_t nlm_pic_base;
+
+/* Main initialization */
+void nlm_hal_init(void)
+{
+        nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
+        nlm_sys_base = nlm_get_sys_regbase(0);  /* node 0 */
+        nlm_pic_base = nlm_get_pic_regbase(0);  /* node 0 */
+}
+
+int nlm_irq_to_irt(int irq)
+{
+        if (!PIC_IRQ_IS_IRT(irq))
+                return -1;
+
+        switch (irq) {
+        case PIC_UART_0_IRQ:
+                return PIC_IRT_UART_0_INDEX;
+        case PIC_UART_1_IRQ:
+                return PIC_IRT_UART_1_INDEX;
+        default:
+                return -1;
+        }
+}
+
+int nlm_irt_to_irq(int irt)
+{
+        switch (irt) {
+        case PIC_IRT_UART_0_INDEX:
+                return PIC_UART_0_IRQ;
+        case PIC_IRT_UART_1_INDEX:
+                return PIC_UART_1_IRQ;
+        default:
+                return -1;
+        }
+}
+
+unsigned int nlm_get_core_frequency(int core)
+{
+        unsigned int pll_divf, pll_divr, dfs_div, ext_div;
+        unsigned int rstval, dfsval, denom;
+        uint64_t num;
+
+        rstval = nlm_read_sys_reg(nlm_sys_base, SYS_POWER_ON_RESET_CFG);
+        dfsval = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIV_VALUE);
+        pll_divf = ((rstval >> 10) & 0x7f) + 1;
+        pll_divr = ((rstval >> 8)  & 0x3) + 1;
+        ext_div  = ((rstval >> 30) & 0x3) + 1;
+        dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;
+
+        num = 800000000ULL * pll_divf;
+        denom = 3 * pll_divr * ext_div * dfs_div;
+        do_div(num, denom);
+        return (unsigned int)num;
+}
+
+unsigned int nlm_get_cpu_frequency(void)
+{
+        return nlm_get_core_frequency(0);
+}
diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c
new file mode 100644
index 000000000000..1f5e4cba891d
--- /dev/null
+++ b/arch/mips/netlogic/xlp/platform.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/pci.h>
+#include <linux/serial_reg.h>
+#include <linux/spinlock.h>
+
+#include <asm/time.h>
+#include <asm/addrspace.h>
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#include <asm/netlogic/xlp-hal/uart.h>
+
+static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
+{
+         return nlm_read_reg(p->iobase, offset);
+}
+
+static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
+{
+        nlm_write_reg(p->iobase, offset, value);
+}
+
+#define PORT(_irq)                                      \
+        {                                               \
+                .irq            = _irq,                 \
+                .regshift       = 2,                    \
+                .iotype         = UPIO_MEM32,           \
+                .flags          = (UPF_SKIP_TEST|UPF_FIXED_TYPE|\
+                                        UPF_BOOT_AUTOCONF),     \
+                .uartclk        = XLP_IO_CLK,           \
+                .type           = PORT_16550A,          \
+                .serial_in      = nlm_xlp_uart_in,      \
+                .serial_out     = nlm_xlp_uart_out,     \
+        }
+
+static struct plat_serial8250_port xlp_uart_data[] = {
+        PORT(PIC_UART_0_IRQ),
+        PORT(PIC_UART_1_IRQ),
+        {},
+};
+
+static struct platform_device uart_device = {
+        .name           = "serial8250",
+        .id             = PLAT8250_DEV_PLATFORM,
+        .dev = {
+                .platform_data = xlp_uart_data,
+        },
+};
+
+static int __init nlm_platform_uart_init(void)
+{
+        unsigned long mmio;
+
+        mmio = (unsigned long)nlm_get_uart_regbase(0, 0);
+        xlp_uart_data[0].iobase = mmio;
+        xlp_uart_data[0].membase = (void __iomem *)mmio;
+        xlp_uart_data[0].mapbase = mmio;
+
+        mmio = (unsigned long)nlm_get_uart_regbase(0, 1);
+        xlp_uart_data[1].iobase = mmio;
+        xlp_uart_data[1].membase = (void __iomem *)mmio;
+        xlp_uart_data[1].mapbase = mmio;
+
+        return platform_device_register(&uart_device);
+}
+
+arch_initcall(nlm_platform_uart_init);
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
new file mode 100644
index 000000000000..acb677a1227c
--- /dev/null
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/serial_8250.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+#include <asm/time.h>
+#include <asm/bootinfo.h>
+
+#include <linux/of_fdt.h>
+
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/sys.h>
+
+unsigned long nlm_common_ebase = 0x0;
+
+/* default to uniprocessor */
+uint32_t nlm_coremask = 1, nlm_cpumask  = 1;
+int  nlm_threads_per_core = 1;
+
+static void nlm_linux_exit(void)
+{
+        nlm_write_sys_reg(nlm_sys_base, SYS_CHIP_RESET, 1);
+        for ( ; ; )
+                cpu_wait();
+}
+
+void __init plat_mem_setup(void)
+{
+        panic_timeout   = 5;
+        _machine_restart = (void (*)(char *))nlm_linux_exit;
+        _machine_halt   = nlm_linux_exit;
+        pm_power_off    = nlm_linux_exit;
+}
+
+const char *get_system_type(void)
+{
+        return "Netlogic XLP Series";
+}
+
+void __init prom_free_prom_memory(void)
+{
+        /* Nothing yet */
+}
+
+void xlp_mmu_init(void)
+{
+        write_c0_config6(read_c0_config6() | 0x24);
+        current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+        write_c0_config7(PM_DEFAULT_MASK >>
+                (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
+}
+
+void __init prom_init(void)
+{
+        void *fdtp;
+
+        fdtp = (void *)(long)fw_arg0;
+        xlp_mmu_init();
+        nlm_hal_init();
+        early_init_devtree(fdtp);
+
+        nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
+#ifdef CONFIG_SMP
+        nlm_wakeup_secondary_cpus(0xffffffff);
+        register_smp_ops(&nlm_smp_ops);
+#endif
+}
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
new file mode 100644
index 000000000000..44d923ff3846
--- /dev/null
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/threads.h>
+
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/string.h>
+
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+#include <asm/netlogic/mips-extns.h>
+
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/sys.h>
+
+static void xlp_enable_secondary_cores(void)
+{
+        uint32_t core, value, coremask, syscoremask;
+        int count;
+
+        /* read cores in reset from SYS block */
+        syscoremask = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
+
+        /* update user specified */
+        nlm_coremask = nlm_coremask & (syscoremask | 1);
+
+        for (core = 1; core < 8; core++) {
+                coremask = 1 << core;
+                if ((nlm_coremask & coremask) == 0)
+                        continue;
+
+                /* Enable CPU clock */
+                value = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL);
+                value &= ~coremask;
+                nlm_write_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL, value);
+
+                /* Remove CPU Reset */
+                value = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
+                value &= ~coremask;
+                nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value);
+
+                /* Poll for CPU to mark itself coherent */
+                count = 100000;
+                do {
+                        value = nlm_read_sys_reg(nlm_sys_base,
+                            SYS_CPU_NONCOHERENT_MODE);
+                } while ((value & coremask) != 0 && count-- > 0);
+
+                if (count == 0)
+                        pr_err("Failed to enable core %d\n", core);
+        }
+}
+
+void xlp_wakeup_secondary_cpus(void)
+{
+        /*
+         * In case of u-boot, the secondaries are in reset
+         * first wakeup core 0 threads
+         */
+        xlp_boot_core0_siblings();
+
+        /* now get other cores out of reset */
+        xlp_enable_secondary_cores();
+}
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index 2dca585dd2f7..f01e4d7a0600 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,5 +1,2 @@
-obj-y                           += setup.o platform.o irq.o setup.o time.o
-obj-$(CONFIG_SMP)               += smp.o smpboot.o
-obj-$(CONFIG_EARLY_PRINTK)      += xlr_console.o
-
-ccflags-y                       += -Werror
+obj-y                           += setup.o platform.o
+obj-$(CONFIG_SMP)               += wakeup.o
diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
deleted file mode 100644
index 521bb7377eb0..000000000000
--- a/arch/mips/netlogic/xlr/irq.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
- * reserved.
- *
- * This software is available to you under a choice of one of two
- * licenses.  You may choose to be licensed under the terms of the GNU
- * General Public License (GPL) Version 2, available from the file
- * COPYING in the main directory of this source tree, or the NetLogic
- * license below:
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/linkage.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/mm.h>
-
-#include <asm/mipsregs.h>
-
-#include <asm/netlogic/xlr/iomap.h>
-#include <asm/netlogic/xlr/pic.h>
-#include <asm/netlogic/xlr/xlr.h>
-
-#include <asm/netlogic/interrupt.h>
-#include <asm/netlogic/mips-extns.h>
-
-static u64 nlm_irq_mask;
-static DEFINE_SPINLOCK(nlm_pic_lock);
-
-static void xlr_pic_enable(struct irq_data *d)
-{
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
-        unsigned long flags;
-        nlm_reg_t reg;
-        int irq = d->irq;
-
-        WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
-
-        spin_lock_irqsave(&nlm_pic_lock, flags);
-        reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
-        netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
-                          reg | (1 << 6) | (1 << 30) | (1 << 31));
-        spin_unlock_irqrestore(&nlm_pic_lock, flags);
-}
-
-static void xlr_pic_mask(struct irq_data *d)
-{
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
-        unsigned long flags;
-        nlm_reg_t reg;
-        int irq = d->irq;
-
-        WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
-
-        spin_lock_irqsave(&nlm_pic_lock, flags);
-        reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
-        netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
-                          reg | (1 << 6) | (1 << 30) | (0 << 31));
-        spin_unlock_irqrestore(&nlm_pic_lock, flags);
-}
-
-#ifdef CONFIG_PCI
-/* Extra ACK needed for XLR on chip PCI controller */
-static void xlr_pci_ack(struct irq_data *d)
-{
-        nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
-
-        netlogic_read_reg(pci_mmio, (0x140 >> 2));
-}
-
-/* Extra ACK needed for XLS on chip PCIe controller */
-static void xls_pcie_ack(struct irq_data *d)
-{
-        nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
-
-        switch (d->irq) {
-        case PIC_PCIE_LINK0_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_LINK1_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_LINK2_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_LINK3_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
-                break;
-        }
-}
-
-/* For XLS B silicon, the 3,4 PCI interrupts are different */
-static void xls_pcie_ack_b(struct irq_data *d)
-{
-        nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
-
-        switch (d->irq) {
-        case PIC_PCIE_LINK0_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_LINK1_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_XLSB0_LINK2_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
-                break;
-        case PIC_PCIE_XLSB0_LINK3_IRQ:
-                netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
-                break;
-        }
-}
-#endif
-
-static void xlr_pic_ack(struct irq_data *d)
-{
-        unsigned long flags;
-        nlm_reg_t *mmio;
-        int irq = d->irq;
-        void *hd = irq_data_get_irq_handler_data(d);
-
-        WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
-
-        if (hd) {
-                void (*extra_ack)(void *) = hd;
-                extra_ack(d);
-        }
-        mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
-        spin_lock_irqsave(&nlm_pic_lock, flags);
-        netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
-        spin_unlock_irqrestore(&nlm_pic_lock, flags);
-}
-
-/*
- * This chip definition handles interrupts routed thru the XLR
- * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
- * 0-31 wired the XLR PIC
- */
-static struct irq_chip xlr_pic = {
-        .name           = "XLR-PIC",
-        .irq_enable     = xlr_pic_enable,
-        .irq_mask       = xlr_pic_mask,
-        .irq_ack        = xlr_pic_ack,
-};
-
-static void rsvd_irq_handler(struct irq_data *d)
-{
-        WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
-}
-
-/*
- * Chip definition for CPU originated interrupts(timer, msg) and
- * IPIs
- */
-struct irq_chip nlm_cpu_intr = {
-        .name           = "XLR-CPU-INTR",
-        .irq_enable     = rsvd_irq_handler,
-        .irq_mask       = rsvd_irq_handler,
-        .irq_ack        = rsvd_irq_handler,
-};
-
-void __init init_xlr_irqs(void)
-{
-        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
-        uint32_t thread_mask = 1;
-        int level, i;
-
-        pr_info("Interrupt thread mask [%x]\n", thread_mask);
-        for (i = 0; i < PIC_NUM_IRTS; i++) {
-                level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
-
-                /* Bind all PIC irqs to boot cpu */
-                netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
-
-                /*
-                 * Use local scheduling and high polarity for all IRTs
-                 * Invalidate all IRTs, by default
-                 */
-                netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
-                                (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
-        }
-
-        /* Make all IRQs as level triggered by default */
-        for (i = 0; i < NR_IRQS; i++) {
-                if (PIC_IRQ_IS_IRT(i))
-                        irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
-                else
-                        irq_set_chip_and_handler(i, &nlm_cpu_intr,
-                                                handle_percpu_irq);
-        }
-#ifdef CONFIG_SMP
-        irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
-                         nlm_smp_function_ipi_handler);
-        irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
-                         nlm_smp_resched_ipi_handler);
-        nlm_irq_mask |=
-            ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
-#endif
-
-#ifdef CONFIG_PCI
-        /*
-         * For PCI interrupts, we need to ack the PIC controller too, overload
-         * irq handler data to do this
-         */
-        if (nlm_chip_is_xls()) {
-                if (nlm_chip_is_xls_b()) {
-                        irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
-                                                        xls_pcie_ack_b);
-                        irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
-                                                        xls_pcie_ack_b);
-                        irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
-                                                        xls_pcie_ack_b);
-                        irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
-                                                        xls_pcie_ack_b);
-                } else {
-                        irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
-                        irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
-                        irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
-                        irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
-                }
-        } else {
-                /* XLR PCI controller ACK */
-                irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
-        }
-#endif
-        /* unmask all PIC related interrupts. If no handler is installed by the
-         * drivers, it'll just ack the interrupt and return
-         */
-        for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
-                nlm_irq_mask |= (1ULL << i);
-
-        nlm_irq_mask |= (1ULL << IRQ_TIMER);
-}
-
-void __init arch_init_irq(void)
-{
-        /* Initialize the irq descriptors */
-        init_xlr_irqs();
-        write_c0_eimr(nlm_irq_mask);
-}
-
-void __cpuinit nlm_smp_irq_init(void)
-{
-        /* set interrupt mask for non-zero cpus */
-        write_c0_eimr(nlm_irq_mask);
-}
-
-asmlinkage void plat_irq_dispatch(void)
-{
-        uint64_t eirr;
-        int i;
-
-        eirr = read_c0_eirr() & read_c0_eimr();
-        if (!eirr)
-                return;
-
-        /* no need of EIRR here, writing compare clears interrupt */
-        if (eirr & (1 << IRQ_TIMER)) {
-                do_IRQ(IRQ_TIMER);
-                return;
-        }
-
-        /* use dcltz: optimize below code */
-        for (i = 63; i != -1; i--) {
-                if (eirr & (1ULL << i))
-                        break;
-        }
-        if (i == -1) {
-                pr_err("no interrupt !!\n");
-                return;
-        }
-
-        /* Ack eirr */
-        write_c0_eirr(1ULL << i);
-
-        do_IRQ(i);
-}
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 609ec2534642..eab64b45dffd 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -15,18 +15,19 @@
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
 
+#include <asm/netlogic/haldefs.h>
 #include <asm/netlogic/xlr/iomap.h>
 #include <asm/netlogic/xlr/pic.h>
 #include <asm/netlogic/xlr/xlr.h>
 
 unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
 {
-        nlm_reg_t *mmio;
+        uint64_t uartbase;
         unsigned int value;
 
-        /* XLR uart does not need any mapping of regs */
-        mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift));
-        value = netlogic_read_reg(mmio, 0);
+        /* sign extend to 64 bits, if needed */
+        uartbase = (uint64_t)(long)p->membase;
+        value = nlm_read_reg(uartbase, offset);
 
         /* See XLR/XLS errata */
         if (offset == UART_MSR)
@@ -39,10 +40,10 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
 
 void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
 {
-        nlm_reg_t *mmio;
+        uint64_t uartbase;
 
-        /* XLR uart does not need any mapping of regs */
-        mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift));
+        /* sign extend to 64 bits, if needed */
+        uartbase = (uint64_t)(long)p->membase;
 
         /* See XLR/XLS errata */
         if (offset == UART_MSR)
@@ -50,7 +51,7 @@ void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
         else if (offset == UART_MCR)
                 value ^= 0x3;
 
-        netlogic_write_reg(mmio, 0, value);
+        nlm_write_reg(uartbase, offset, value);
 }
 
 #define PORT(_irq)                                      \
@@ -82,15 +83,15 @@ static struct platform_device uart_device = {
 
 static int __init nlm_uart_init(void)
 {
-        nlm_reg_t *mmio;
+        unsigned long uartbase;
 
-        mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
-        xlr_uart_data[0].membase = (void __iomem *)mmio;
-        xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio);
+        uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
+        xlr_uart_data[0].membase = (void __iomem *)uartbase;
+        xlr_uart_data[0].mapbase = CPHYSADDR(uartbase);
 
-        mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET);
-        xlr_uart_data[1].membase = (void __iomem *)mmio;
-        xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio);
+        uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_1_OFFSET);
+        xlr_uart_data[1].membase = (void __iomem *)uartbase;
+        xlr_uart_data[1].mapbase = CPHYSADDR(uartbase);
 
         return platform_device_register(&uart_device);
 }
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index cee25ddd0887..c9d066dedc4e 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -39,26 +39,33 @@
 #include <asm/reboot.h>
 #include <asm/time.h>
 #include <asm/bootinfo.h>
-#include <asm/smp-ops.h>
 
 #include <asm/netlogic/interrupt.h>
 #include <asm/netlogic/psb-bootinfo.h>
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
 
 #include <asm/netlogic/xlr/xlr.h>
 #include <asm/netlogic/xlr/iomap.h>
 #include <asm/netlogic/xlr/pic.h>
 #include <asm/netlogic/xlr/gpio.h>
 
-unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE);
-unsigned long nlm_common_ebase = 0x0;
+uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
+uint64_t nlm_pic_base;
 struct psb_info nlm_prom_info;
 
+unsigned long nlm_common_ebase = 0x0;
+
+/* default to uniprocessor */
+uint32_t nlm_coremask = 1, nlm_cpumask  = 1;
+int  nlm_threads_per_core = 1;
+
 static void __init nlm_early_serial_setup(void)
 {
         struct uart_port s;
-        nlm_reg_t *uart_base;
+        unsigned long uart_base;
 
-        uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
+        uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
         memset(&s, 0, sizeof(s));
         s.flags         = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
         s.iotype        = UPIO_MEM32;
@@ -67,18 +74,18 @@ static void __init nlm_early_serial_setup(void)
         s.uartclk       = PIC_CLKS_PER_SEC;
         s.serial_in     = nlm_xlr_uart_in;
         s.serial_out    = nlm_xlr_uart_out;
-        s.mapbase       = (unsigned long)uart_base;
+        s.mapbase       = uart_base;
         s.membase       = (unsigned char __iomem *)uart_base;
         early_serial_setup(&s);
 }
 
 static void nlm_linux_exit(void)
 {
-        nlm_reg_t *mmio;
+        uint64_t gpiobase;
 
-        mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET);
+        gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
         /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
-        netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1);
+        nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1);
         for ( ; ; )
                 cpu_wait();
 }
@@ -96,6 +103,11 @@ const char *get_system_type(void)
         return "Netlogic XLR/XLS Series";
 }
 
+unsigned int nlm_get_cpu_frequency(void)
+{
+        return (unsigned int)nlm_prom_info.cpu_frequency;
+}
+
 void __init prom_free_prom_memory(void)
 {
         /* Nothing yet */
@@ -175,6 +187,7 @@ void __init prom_init(void)
         prom_infop = (struct psb_info *)(long)(int)fw_arg3;
 
         nlm_prom_info = *prom_infop;
+        nlm_pic_base = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
 
         nlm_early_serial_setup();
         build_arcs_cmdline(argv);
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/wakeup.c
index 8cb7889ce0cc..db5d987d4881 100644
--- a/arch/mips/netlogic/xlr/smpboot.S
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -33,68 +33,36 @@
  */
 
 #include <linux/init.h>
+#include <linux/threads.h>
 
 #include <asm/asm.h>
 #include <asm/asm-offsets.h>
-#include <asm/regdef.h>
 #include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/string.h>
 
-/*
- * Early code for secondary CPUs. This will get them out of the bootloader
- * code and into linux. Needed because the bootloader area will be taken
- * and initialized by linux.
- */
-        __CPUINIT
-NESTED(prom_pre_boot_secondary_cpus, 16, sp)
-        .set    mips64
-        mfc0    t0, $15, 1      # read ebase
-        andi    t0, 0x1f        # t0 has the processor_id()
-        sll     t0, 2           # offset in cpu array
-
-        PTR_LA  t1, nlm_cpu_ready # mark CPU ready
-        PTR_ADDU t1, t0
-        li      t2, 1
-        sw      t2, 0(t1)
-
-        PTR_LA  t1, nlm_cpu_unblock
-        PTR_ADDU t1, t0
-1:      lw      t2, 0(t1)       # wait till unblocked
-        beqz    t2, 1b
-        nop
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/common.h>
+#include <asm/netlogic/mips-extns.h>
 
-        PTR_LA  t1, nlm_next_sp
-        PTR_L   sp, 0(t1)
-        PTR_LA  t1, nlm_next_gp
-        PTR_L   gp, 0(t1)
+#include <asm/netlogic/xlr/iomap.h>
+#include <asm/netlogic/xlr/pic.h>
 
-        PTR_LA  t0, nlm_early_init_secondary
-        jalr    t0
-        nop
-
-        PTR_LA  t0, smp_bootstrap
-        jr      t0
-        nop
-END(prom_pre_boot_secondary_cpus)
-        __FINIT
-
-/*
- * NMI code, used for CPU wakeup, copied to reset entry
- */
-NESTED(nlm_boot_smp_nmi, 0, sp)
-        .set push
-        .set noat
-        .set mips64
-        .set noreorder
+int __cpuinit xlr_wakeup_secondary_cpus(void)
+{
+        unsigned int i, boot_cpu;
 
-        /* Clear the  NMI and BEV bits */
-        MFC0    k0, CP0_STATUS
-        li      k1, 0xffb7ffff
-        and     k0, k0, k1
-        MTC0    k0, CP0_STATUS
+        /*
+         *  In case of RMI boot, hit with NMI to get the cores
+         *  from bootloader to linux code.
+         */
+        boot_cpu = hard_smp_processor_id();
+        nlm_set_nmi_handler(nlm_rmiboot_preboot);
+        for (i = 0; i < NR_CPUS; i++) {
+                if (i == boot_cpu || (nlm_cpumask & (1u << i)) == 0)
+                        continue;
+                nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
+        }
 
-        PTR_LA  k1, secondary_entry_point
-        PTR_L   k0, 0(k1)
-        jr      k0
-        nop
-        .set pop
-END(nlm_boot_smp_nmi)
+        return 0;
+}
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index bb82cbdbc62a..c3ac4b086eb2 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX)		+= pci-bcm47xx.o
 obj-$(CONFIG_BCM63XX)           += pci-bcm63xx.o fixup-bcm63xx.o \
                                         ops-bcm63xx.o
 obj-$(CONFIG_MIPS_ALCHEMY)      += pci-alchemy.o
+obj-$(CONFIG_SOC_AR724X)        += pci-ath724x.o
 
 #
 # These are still pretty much in the old state, watch, go blind.
@@ -55,7 +56,7 @@ obj-$(CONFIG_ZAO_CAPCELLA)	+= fixup-capcella.o
 obj-$(CONFIG_WR_PPMC)           += fixup-wrppmc.o
 obj-$(CONFIG_MIKROTIK_RB532)    += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
-obj-$(CONFIG_NLM_XLR)           += pci-xlr.o
+obj-$(CONFIG_CPU_XLR)           += pci-xlr.o
 
 ifdef CONFIG_PCI_MSI
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index 5d530f89d872..d37be36dc659 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -162,7 +162,7 @@ msi_irq_allocated:
                 msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
                 break;
         default:
-                panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
+                panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
         }
         msg.data = irq - OCTEON_IRQ_MSI_BIT0;
 
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 8fbfbf2b931c..389bf669d56e 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -405,7 +405,7 @@ int msp_pcibios_config_access(unsigned char access_type,
         if (pciirqflag == 0) {
                 ret = request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */
                                 bpci_interrupt,
-                                IRQF_SHARED | IRQF_DISABLED,
+                                IRQF_SHARED,
                                 "PMC MSP PCI Host",
                                 preg);
                 if (ret != 0)
diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c
index 6a3bdb5ffa80..02d64f77e967 100644
--- a/arch/mips/pci/ops-tx3927.c
+++ b/arch/mips/pci/ops-tx3927.c
@@ -225,7 +225,7 @@ void __init tx3927_setup_pcierr_irq(void)
 {
         if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI,
                         tx3927_pcierr_interrupt,
-                        IRQF_DISABLED, "PCI error",
+                        0, "PCI error",
                         (void *)TX3927_PCIC_REG))
                 printk(KERN_WARNING "Failed to request irq for PCIERR\n");
 }
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index b5ce041cdafb..ec125bed721c 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -13,9 +13,11 @@
 #include <linux/platform_device.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/syscore_ops.h>
 #include <linux/vmalloc.h>
 
 #include <asm/mach-au1x00/au1000.h>
+#include <asm/tlbmisc.h>
 
 #ifdef CONFIG_DEBUG_PCI
 #define DBG(x...) printk(KERN_DEBUG x)
@@ -41,6 +43,12 @@ struct alchemy_pci_context {
         int (*board_pci_idsel)(unsigned int devsel, int assert);
 };
 
+/* for syscore_ops. There's only one PCI controller on Alchemy chips, so this
+ * should suffice for now.
+ */
+static struct alchemy_pci_context *__alchemy_pci_ctx;
+
+
 /* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
  * in arch/mips/alchemy/common/setup.c
  */
@@ -99,18 +107,6 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
                 return -1;
         }
 
-        /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
-         * on resume, clearing our wired entry.  Unfortunately the ->resume()
-         * callback is called way way way too late (and ->suspend() too early)
-         * to have them destroy and recreate it.  Instead just test if c0_wired
-         * is now lower than the index we retrieved before suspending and then
-         * recreate the entry if necessary.  Of course this is totally bonkers
-         * and breaks as soon as someone else adds another wired entry somewhere
-         * else.  Anyone have any ideas how to handle this better?
-         */
-        if (unlikely(read_c0_wired() < ctx->wired_entry))
-                alchemy_pci_wired_entry(ctx);
-
         local_irq_save(flags);
         r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff;
         r |= PCI_STATCMD_STATUS(0x2000);
@@ -304,6 +300,62 @@ static int alchemy_pci_def_idsel(unsigned int devsel, int assert)
         return 1;       /* success */
 }
 
+/* save PCI controller register contents. */
+static int alchemy_pci_suspend(void)
+{
+        struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
+        if (!ctx)
+                return 0;
+
+        ctx->pm[0]  = __raw_readl(ctx->regs + PCI_REG_CMEM);
+        ctx->pm[1]  = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
+        ctx->pm[2]  = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
+        ctx->pm[3]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
+        ctx->pm[4]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
+        ctx->pm[5]  = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
+        ctx->pm[6]  = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
+        ctx->pm[7]  = __raw_readl(ctx->regs + PCI_REG_ID);
+        ctx->pm[8]  = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
+        ctx->pm[9]  = __raw_readl(ctx->regs + PCI_REG_PARAM);
+        ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
+        ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
+
+        return 0;
+}
+
+static void alchemy_pci_resume(void)
+{
+        struct alchemy_pci_context *ctx = __alchemy_pci_ctx;
+        if (!ctx)
+                return;
+
+        __raw_writel(ctx->pm[0],  ctx->regs + PCI_REG_CMEM);
+        __raw_writel(ctx->pm[2],  ctx->regs + PCI_REG_B2BMASK_CCH);
+        __raw_writel(ctx->pm[3],  ctx->regs + PCI_REG_B2BBASE0_VID);
+        __raw_writel(ctx->pm[4],  ctx->regs + PCI_REG_B2BBASE1_SID);
+        __raw_writel(ctx->pm[5],  ctx->regs + PCI_REG_MWMASK_DEV);
+        __raw_writel(ctx->pm[6],  ctx->regs + PCI_REG_MWBASE_REV_CCL);
+        __raw_writel(ctx->pm[7],  ctx->regs + PCI_REG_ID);
+        __raw_writel(ctx->pm[8],  ctx->regs + PCI_REG_CLASSREV);
+        __raw_writel(ctx->pm[9],  ctx->regs + PCI_REG_PARAM);
+        __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
+        __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
+        wmb();
+        __raw_writel(ctx->pm[1],  ctx->regs + PCI_REG_CONFIG);
+        wmb();
+
+        /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
+         * on resume, making it necessary to recreate it as soon as possible.
+         */
+        ctx->wired_entry = 8191;        /* impossibly high value */
+        alchemy_pci_wired_entry(ctx);   /* install it */
+}
+
+static struct syscore_ops alchemy_pci_pmops = {
+        .suspend        = alchemy_pci_suspend,
+        .resume         = alchemy_pci_resume,
+};
+
 static int __devinit alchemy_pci_probe(struct platform_device *pdev)
 {
         struct alchemy_pci_platdata *pd = pdev->dev.platform_data;
@@ -396,7 +448,8 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev)
                 ret = -ENOMEM;
                 goto out4;
         }
-        ctx->wired_entry = 8192;        /* impossibly high value */
+        ctx->wired_entry = 8191;        /* impossibly high value */
+        alchemy_pci_wired_entry(ctx);   /* install it */
 
         set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base);
 
@@ -408,7 +461,9 @@ static int __devinit alchemy_pci_probe(struct platform_device *pdev)
         __raw_writel(val, ctx->regs + PCI_REG_CONFIG);
         wmb();
 
+        __alchemy_pci_ctx = ctx;
         platform_set_drvdata(pdev, ctx);
+        register_syscore_ops(&alchemy_pci_pmops);
         register_pci_controller(&ctx->alchemy_pci_ctrl);
 
         return 0;
@@ -425,68 +480,11 @@ out:
         return ret;
 }
 
-
-#ifdef CONFIG_PM
-/* save PCI controller register contents. */
-static int alchemy_pci_suspend(struct device *dev)
-{
-        struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
-
-        ctx->pm[0]  = __raw_readl(ctx->regs + PCI_REG_CMEM);
-        ctx->pm[1]  = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff;
-        ctx->pm[2]  = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH);
-        ctx->pm[3]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID);
-        ctx->pm[4]  = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID);
-        ctx->pm[5]  = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV);
-        ctx->pm[6]  = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL);
-        ctx->pm[7]  = __raw_readl(ctx->regs + PCI_REG_ID);
-        ctx->pm[8]  = __raw_readl(ctx->regs + PCI_REG_CLASSREV);
-        ctx->pm[9]  = __raw_readl(ctx->regs + PCI_REG_PARAM);
-        ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR);
-        ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT);
-
-        return 0;
-}
-
-static int alchemy_pci_resume(struct device *dev)
-{
-        struct alchemy_pci_context *ctx = dev_get_drvdata(dev);
-
-        __raw_writel(ctx->pm[0],  ctx->regs + PCI_REG_CMEM);
-        __raw_writel(ctx->pm[2],  ctx->regs + PCI_REG_B2BMASK_CCH);
-        __raw_writel(ctx->pm[3],  ctx->regs + PCI_REG_B2BBASE0_VID);
-        __raw_writel(ctx->pm[4],  ctx->regs + PCI_REG_B2BBASE1_SID);
-        __raw_writel(ctx->pm[5],  ctx->regs + PCI_REG_MWMASK_DEV);
-        __raw_writel(ctx->pm[6],  ctx->regs + PCI_REG_MWBASE_REV_CCL);
-        __raw_writel(ctx->pm[7],  ctx->regs + PCI_REG_ID);
-        __raw_writel(ctx->pm[8],  ctx->regs + PCI_REG_CLASSREV);
-        __raw_writel(ctx->pm[9],  ctx->regs + PCI_REG_PARAM);
-        __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR);
-        __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT);
-        wmb();
-        __raw_writel(ctx->pm[1],  ctx->regs + PCI_REG_CONFIG);
-        wmb();
-
-        return 0;
-}
-
-static const struct dev_pm_ops alchemy_pci_pmops = {
-        .suspend        = alchemy_pci_suspend,
-        .resume         = alchemy_pci_resume,
-};
-
-#define ALCHEMY_PCICTL_PM       (&alchemy_pci_pmops)
-
-#else
-#define ALCHEMY_PCICTL_PM       NULL
-#endif
-
 static struct platform_driver alchemy_pcictl_driver = {
         .probe          = alchemy_pci_probe,
         .driver = {
                 .name   = "alchemy-pci",
                 .owner  = THIS_MODULE,
-                .pm     = ALCHEMY_PCICTL_PM,
         },
 };
 
diff --git a/arch/mips/pci/pci-ath724x.c b/arch/mips/pci/pci-ath724x.c
new file mode 100644
index 000000000000..a4dd24a4130b
--- /dev/null
+++ b/arch/mips/pci/pci-ath724x.c
@@ -0,0 +1,174 @@
+/*
+ *  Atheros 724x PCI support
+ *
+ *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <asm/mach-ath79/pci-ath724x.h>
+
+#define reg_read(_phys)         (*(unsigned int *) KSEG1ADDR(_phys))
+#define reg_write(_phys, _val)  ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
+
+#define ATH724X_PCI_DEV_BASE    0x14000000
+#define ATH724X_PCI_MEM_BASE    0x10000000
+#define ATH724X_PCI_MEM_SIZE    0x08000000
+
+static DEFINE_SPINLOCK(ath724x_pci_lock);
+static struct ath724x_pci_data *pci_data;
+static int pci_data_size;
+
+static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+                            int size, uint32_t *value)
+{
+        unsigned long flags, addr, tval, mask;
+
+        if (devfn)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (where & (size - 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        spin_lock_irqsave(&ath724x_pci_lock, flags);
+
+        switch (size) {
+        case 1:
+                addr = where & ~3;
+                mask = 0xff000000 >> ((where % 4) * 8);
+                tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
+                tval = tval & ~mask;
+                *value = (tval >> ((4 - (where % 4))*8));
+                break;
+        case 2:
+                addr = where & ~3;
+                mask = 0xffff0000 >> ((where % 4)*8);
+                tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
+                tval = tval & ~mask;
+                *value = (tval >> ((4 - (where % 4))*8));
+                break;
+        case 4:
+                *value = reg_read(ATH724X_PCI_DEV_BASE + where);
+                break;
+        default:
+                spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+                             int size, uint32_t value)
+{
+        unsigned long flags, tval, addr, mask;
+
+        if (devfn)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (where & (size - 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        spin_lock_irqsave(&ath724x_pci_lock, flags);
+
+        switch (size) {
+        case 1:
+                addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
+                mask = 0xff000000 >> ((where % 4)*8);
+                tval = reg_read(addr);
+                tval = tval & ~mask;
+                tval |= (value << ((4 - (where % 4))*8)) & mask;
+                reg_write(addr, tval);
+                break;
+        case 2:
+                addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
+                mask = 0xffff0000 >> ((where % 4)*8);
+                tval = reg_read(addr);
+                tval = tval & ~mask;
+                tval |= (value << ((4 - (where % 4))*8)) & mask;
+                reg_write(addr, tval);
+                break;
+        case 4:
+                reg_write((ATH724X_PCI_DEV_BASE + where), value);
+                break;
+        default:
+                spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops ath724x_pci_ops = {
+        .read   = ath724x_pci_read,
+        .write  = ath724x_pci_write,
+};
+
+static struct resource ath724x_io_resource = {
+        .name   = "PCI IO space",
+        .start  = 0,
+        .end    = 0,
+        .flags  = IORESOURCE_IO,
+};
+
+static struct resource ath724x_mem_resource = {
+        .name   = "PCI memory space",
+        .start  = ATH724X_PCI_MEM_BASE,
+        .end    = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct pci_controller ath724x_pci_controller = {
+        .pci_ops        = &ath724x_pci_ops,
+        .io_resource    = &ath724x_io_resource,
+        .mem_resource   = &ath724x_mem_resource,
+};
+
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
+{
+        pci_data        = data;
+        pci_data_size   = size;
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+{
+        unsigned int devfn = dev->devfn;
+        int irq = -1;
+
+        if (devfn > pci_data_size - 1)
+                return irq;
+
+        irq = pci_data[devfn].irq;
+
+        return irq;
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        unsigned int devfn = dev->devfn;
+
+        if (devfn > pci_data_size - 1)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        dev->dev.platform_data = pci_data[devfn].pdata;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int __init ath724x_pcibios_init(void)
+{
+        register_pci_controller(&ath724x_pci_controller);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+arch_initcall(ath724x_pcibios_init);
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 82e0fde1dba0..39eb7c417e2f 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -99,7 +99,7 @@ static int __init bcm63xx_pci_init(void)
         unsigned int mem_size;
         u32 val;
 
-        if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
+        if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
                 return -ENODEV;
 
         if (!bcm63xx_pci_enabled)
@@ -159,7 +159,7 @@ static int __init bcm63xx_pci_init(void)
         /* setup PCI to local bus access, used by PCI device to target
          * local RAM while bus mastering */
         bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
-        if (BCMCPU_IS_6358())
+        if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
                 val = MPI_SP0_REMAP_ENABLE_MASK;
         else
                 val = 0;
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index ed1c54284b8f..52a1ba70b3b6 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -99,7 +99,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
          */
         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
         /* Set latency timers for all devices */
-        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
+        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 
         /* Enable reporting System errors and parity errors on all devices */
         /* Enable parity checking and error reporting */
@@ -109,7 +109,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 
         if (dev->subordinate) {
                 /* Set latency timers on sub bridges */
-                pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
+                pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
                 /* More bridge error detection */
                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
                 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
@@ -121,14 +121,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
         if (pos) {
                 /* Update Device Control */
                 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
-                /* Correctable Error Reporting */
-                config |= PCI_EXP_DEVCTL_CERE;
-                /* Non-Fatal Error Reporting */
-                config |= PCI_EXP_DEVCTL_NFERE;
-                /* Fatal Error Reporting */
-                config |= PCI_EXP_DEVCTL_FERE;
-                /* Unsupported Request */
-                config |= PCI_EXP_DEVCTL_URRE;
+                config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
+                config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
+                config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
+                config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
                 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
         }
 
diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c
index a5807406a7f1..a032ae0a533d 100644
--- a/arch/mips/pci/pci-tx4927.c
+++ b/arch/mips/pci/pci-tx4927.c
@@ -85,7 +85,7 @@ void __init tx4927_setup_pcierr_irq(void)
 {
         if (request_irq(TXX9_IRQ_BASE + TX4927_IR_PCIERR,
                         tx4927_pcierr_interrupt,
-                        IRQF_DISABLED, "PCI error",
+                        0, "PCI error",
                         (void *)TX4927_PCIC_REG))
                 printk(KERN_WARNING "Failed to request irq for PCIERR\n");
 }
diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c
index 20e45f30b2ef..141bba562488 100644
--- a/arch/mips/pci/pci-tx4938.c
+++ b/arch/mips/pci/pci-tx4938.c
@@ -136,7 +136,7 @@ void __init tx4938_setup_pcierr_irq(void)
 {
         if (request_irq(TXX9_IRQ_BASE + TX4938_IR_PCIERR,
                         tx4927_pcierr_interrupt,
-                        IRQF_DISABLED, "PCI error",
+                        0, "PCI error",
                         (void *)TX4927_PCIC_REG))
                 printk(KERN_WARNING "Failed to request irq for PCIERR\n");
 }
diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c
index 9ef840693baf..c10fbf2a19dc 100644
--- a/arch/mips/pci/pci-tx4939.c
+++ b/arch/mips/pci/pci-tx4939.c
@@ -101,7 +101,7 @@ void __init tx4939_setup_pcierr_irq(void)
 {
         if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR,
                         tx4927_pcierr_interrupt,
-                        IRQF_DISABLED, "PCI error",
+                        0, "PCI error",
                         (void *)TX4939_PCIC_REG))
                 pr_warning("Failed to request irq for PCIERR\n");
 }
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 38fece16c435..3d701a962ef4 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -36,12 +36,18 @@
 #include <linux/pci.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/msi.h>
 #include <linux/mm.h>
+#include <linux/irq.h>
+#include <linux/irqdesc.h>
 #include <linux/console.h>
 
 #include <asm/io.h>
 
 #include <asm/netlogic/interrupt.h>
+#include <asm/netlogic/haldefs.h>
+
+#include <asm/netlogic/xlr/msidef.h>
 #include <asm/netlogic/xlr/iomap.h>
 #include <asm/netlogic/xlr/pic.h>
 #include <asm/netlogic/xlr/xlr.h>
@@ -150,7 +156,7 @@ struct pci_controller nlm_pci_controller = {
         .io_offset      = 0x00000000UL,
 };
 
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+static int get_irq_vector(const struct pci_dev *dev)
 {
         if (!nlm_chip_is_xls())
                 return  PIC_PCIX_IRQ;   /* for XLR just one IRQ*/
@@ -182,6 +188,101 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
         return 0;
 }
 
+#ifdef CONFIG_PCI_MSI
+void destroy_irq(unsigned int irq)
+{
+            /* nothing to do yet */
+}
+
+void arch_teardown_msi_irq(unsigned int irq)
+{
+        destroy_irq(irq);
+}
+
+int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
+{
+        struct msi_msg msg;
+        int irq, ret;
+
+        irq = get_irq_vector(dev);
+        if (irq <= 0)
+                return 1;
+
+        msg.address_hi = MSI_ADDR_BASE_HI;
+        msg.address_lo = MSI_ADDR_BASE_LO   |
+                MSI_ADDR_DEST_MODE_PHYSICAL |
+                MSI_ADDR_REDIRECTION_CPU;
+
+        msg.data = MSI_DATA_TRIGGER_EDGE |
+                MSI_DATA_LEVEL_ASSERT    |
+                MSI_DATA_DELIVERY_FIXED;
+
+        ret = irq_set_msi_desc(irq, desc);
+        if (ret < 0) {
+                destroy_irq(irq);
+                return ret;
+        }
+
+        write_msi_msg(irq, &msg);
+        return 0;
+}
+#endif
+
+/* Extra ACK needed for XLR on chip PCI controller */
+static void xlr_pci_ack(struct irq_data *d)
+{
+        uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET);
+
+        nlm_read_reg(pcibase, (0x140 >> 2));
+}
+
+/* Extra ACK needed for XLS on chip PCIe controller */
+static void xls_pcie_ack(struct irq_data *d)
+{
+        uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
+
+        switch (d->irq) {
+        case PIC_PCIE_LINK0_IRQ:
+                nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK1_IRQ:
+                nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK2_IRQ:
+                nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK3_IRQ:
+                nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
+                break;
+        }
+}
+
+/* For XLS B silicon, the 3,4 PCI interrupts are different */
+static void xls_pcie_ack_b(struct irq_data *d)
+{
+        uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
+
+        switch (d->irq) {
+        case PIC_PCIE_LINK0_IRQ:
+                nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK1_IRQ:
+                nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_XLSB0_LINK2_IRQ:
+                nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_XLSB0_LINK3_IRQ:
+                nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
+                break;
+        }
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return get_irq_vector(dev);
+}
+
 /* Do platform specific device initialization at pci_enable_device() time */
 int pcibios_plat_dev_init(struct pci_dev *dev)
 {
@@ -204,6 +305,31 @@ static int __init pcibios_init(void)
         pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
         register_pci_controller(&nlm_pci_controller);
 
+        /*
+         * For PCI interrupts, we need to ack the PCI controller too, overload
+         * irq handler data to do this
+         */
+        if (nlm_chip_is_xls()) {
+                if (nlm_chip_is_xls_b()) {
+                        irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
+                                                        xls_pcie_ack_b);
+                        irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
+                                                        xls_pcie_ack_b);
+                        irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
+                                                        xls_pcie_ack_b);
+                        irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
+                                                        xls_pcie_ack_b);
+                } else {
+                        irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
+                        irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
+                        irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
+                        irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
+                }
+        } else {
+                /* XLR PCI controller ACK */
+                irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
+        }
+
         return 0;
 }
 
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 41af7fa2887b..8ac0d4841852 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -4,8 +4,11 @@
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
- * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2011 Wind River Systems,
+ *   written by Ralf Baechle (ralf@linux-mips.org)
  */
+#include <linux/bug.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/bootmem.h>
@@ -14,6 +17,8 @@
 #include <linux/types.h>
 #include <linux/pci.h>
 
+#include <asm/cpu-info.h>
+
 /*
  * Indicate whether we respect the PCI setup left by the firmware.
  *
@@ -150,10 +155,32 @@ out:
                "Skipping PCI bus scan due to resource conflict\n");
 }
 
+static void __init pcibios_set_cache_line_size(void)
+{
+        struct cpuinfo_mips *c = &current_cpu_data;
+        unsigned int lsize;
+
+        /*
+         * Set PCI cacheline size to that of the highest level in the
+         * cache hierarchy.
+         */
+        lsize = c->dcache.linesz;
+        lsize = c->scache.linesz ? : lsize;
+        lsize = c->tcache.linesz ? : lsize;
+
+        BUG_ON(!lsize);
+
+        pci_dfl_cache_line_size = lsize >> 2;
+
+        pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
+}
+
 static int __init pcibios_init(void)
 {
         struct pci_controller *hose;
 
+        pcibios_set_cache_line_size();
+
         /* Scan all of the recorded PCI controllers.  */
         for (hose = hose_head; hose; hose = hose->next)
                 pcibios_scanbus(hose);
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 0583c463e5f1..fdb4d558c0cc 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2007, 2008 Cavium Networks
+ * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -11,15 +11,32 @@
 #include <linux/interrupt.h>
 #include <linux/time.h>
 #include <linux/delay.h>
+#include <linux/module.h>
 
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/cvmx-npei-defs.h>
 #include <asm/octeon/cvmx-pciercx-defs.h>
 #include <asm/octeon/cvmx-pescx-defs.h>
 #include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-pemx-defs.h>
+#include <asm/octeon/cvmx-dpi-defs.h>
+#include <asm/octeon/cvmx-sli-defs.h>
+#include <asm/octeon/cvmx-sriox-defs.h>
 #include <asm/octeon/cvmx-helper-errata.h>
 #include <asm/octeon/pci-octeon.h>
 
+#define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
+#define MPS_CN5XXX  0 /* 128 byte Max Packet Size (Limit of most PCs) */
+#define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
+#define MPS_CN6XXX  0 /* 128 byte Max Packet Size (Limit of most PCs) */
+
+/* Module parameter to disable PCI probing */
+static int pcie_disable;
+module_param(pcie_disable, int, S_IRUGO);
+
+static int enable_pcie_14459_war;
+static int enable_pcie_bus_num_war[2];
+
 union cvmx_pcie_address {
         uint64_t u64;
         struct {
@@ -75,6 +92,8 @@ union cvmx_pcie_address {
         } mem;
 };
 
+static int cvmx_pcie_rc_initialize(int pcie_port);
+
 #include <dma-coherence.h>
 
 /**
@@ -154,12 +173,21 @@ static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
  */
 static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
 {
-        union cvmx_pescx_cfg_rd pescx_cfg_rd;
-        pescx_cfg_rd.u64 = 0;
-        pescx_cfg_rd.s.addr = cfg_offset;
-        cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
-        pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
-        return pescx_cfg_rd.s.data;
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+                union cvmx_pescx_cfg_rd pescx_cfg_rd;
+                pescx_cfg_rd.u64 = 0;
+                pescx_cfg_rd.s.addr = cfg_offset;
+                cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
+                pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
+                return pescx_cfg_rd.s.data;
+        } else {
+                union cvmx_pemx_cfg_rd pemx_cfg_rd;
+                pemx_cfg_rd.u64 = 0;
+                pemx_cfg_rd.s.addr = cfg_offset;
+                cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
+                pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));
+                return pemx_cfg_rd.s.data;
+        }
 }
 
 /**
@@ -173,11 +201,19 @@ static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
 static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
                                  uint32_t val)
 {
-        union cvmx_pescx_cfg_wr pescx_cfg_wr;
-        pescx_cfg_wr.u64 = 0;
-        pescx_cfg_wr.s.addr = cfg_offset;
-        pescx_cfg_wr.s.data = val;
-        cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+                union cvmx_pescx_cfg_wr pescx_cfg_wr;
+                pescx_cfg_wr.u64 = 0;
+                pescx_cfg_wr.s.addr = cfg_offset;
+                pescx_cfg_wr.s.data = val;
+                cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
+        } else {
+                union cvmx_pemx_cfg_wr pemx_cfg_wr;
+                pemx_cfg_wr.u64 = 0;
+                pemx_cfg_wr.s.addr = cfg_offset;
+                pemx_cfg_wr.s.data = val;
+                cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
+        }
 }
 
 /**
@@ -348,7 +384,6 @@ static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
 static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
 {
         union cvmx_pciercx_cfg030 pciercx_cfg030;
-        union cvmx_npei_ctl_status2 npei_ctl_status2;
         union cvmx_pciercx_cfg070 pciercx_cfg070;
         union cvmx_pciercx_cfg001 pciercx_cfg001;
         union cvmx_pciercx_cfg032 pciercx_cfg032;
@@ -365,21 +400,21 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
         /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
         /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
-        pciercx_cfg030.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
-        /*
-         * Max payload size = 128 bytes for best Octeon DMA
-         * performance.
-         */
-        pciercx_cfg030.s.mps = 0;
+
+        pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
+                pciercx_cfg030.s.mps = MPS_CN5XXX;
+                pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
+        } else {
+                pciercx_cfg030.s.mps = MPS_CN6XXX;
+                pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
+        }
         /*
-         * Max read request size = 128 bytes for best Octeon DMA
-         * performance.
+         * Enable relaxed order processing. This will allow devices to
+         * affect read response ordering.
          */
-        pciercx_cfg030.s.mrrs = 0;
-        /* Enable relaxed ordering. */
         pciercx_cfg030.s.ro_en = 1;
-        /* Enable no snoop. */
+        /* Enable no snoop processing. Not used by Octeon */
         pciercx_cfg030.s.ns_en = 1;
         /* Correctable error reporting enable. */
         pciercx_cfg030.s.ce_en = 1;
@@ -389,50 +424,67 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         pciercx_cfg030.s.fe_en = 1;
         /* Unsupported request reporting enable. */
         pciercx_cfg030.s.ur_en = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
-                             pciercx_cfg030.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
 
-        /*
-         * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
-         * PCIE*_CFG030[MPS]
-         *
-         * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
-         * exceed PCIE*_CFG030[MRRS].
-         */
-        npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
-        /* Max payload size = 128 bytes for best Octeon DMA performance */
-        npei_ctl_status2.s.mps = 0;
-        /* Max read request size = 128 bytes for best Octeon DMA performance */
-        npei_ctl_status2.s.mrrs = 0;
-        if (pcie_port)
-                npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
-        else
-                npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
-        cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
+
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+                union cvmx_npei_ctl_status2 npei_ctl_status2;
+                /*
+                 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
+                 * PCIE*_CFG030[MPS].  Max Read Request Size
+                 * (NPEI_CTL_STATUS2[MRRS]) must not exceed
+                 * PCIE*_CFG030[MRRS]
+                 */
+                npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
+                /* Max payload size = 128 bytes for best Octeon DMA performance */
+                npei_ctl_status2.s.mps = MPS_CN5XXX;
+                /* Max read request size = 128 bytes for best Octeon DMA performance */
+                npei_ctl_status2.s.mrrs = MRRS_CN5XXX;
+                if (pcie_port)
+                        npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
+                else
+                        npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
+
+                cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
+        } else {
+                /*
+                 * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
+                 * PCIE*_CFG030[MPS].  Max Read Request Size
+                 * (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
+                 * PCIE*_CFG030[MRRS].
+                 */
+                union cvmx_dpi_sli_prtx_cfg prt_cfg;
+                union cvmx_sli_s2m_portx_ctl sli_s2m_portx_ctl;
+                prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
+                prt_cfg.s.mps = MPS_CN6XXX;
+                prt_cfg.s.mrrs = MRRS_CN6XXX;
+                /* Max outstanding load request. */
+                prt_cfg.s.molr = 32;
+                cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
+
+                sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
+                sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
+                cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
+        }
 
         /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
-        pciercx_cfg070.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
+        pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
         pciercx_cfg070.s.ge = 1;        /* ECRC generation enable. */
         pciercx_cfg070.s.ce = 1;        /* ECRC check enable. */
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
-                             pciercx_cfg070.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
 
         /*
-         * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
-         * always be set.
-         *
-         * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
-         * Message Enable (PCIE*_CFG001[SEE])
+         * Access Enables (PCIE*_CFG001[MSAE,ME])
+         * ME and MSAE should always be set.
+         * Interrupt Disable (PCIE*_CFG001[I_DIS])
+         * System Error Message Enable (PCIE*_CFG001[SEE])
          */
-        pciercx_cfg001.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
+        pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
         pciercx_cfg001.s.msae = 1;      /* Memory space enable. */
         pciercx_cfg001.s.me = 1;        /* Bus master enable. */
         pciercx_cfg001.s.i_dis = 1;     /* INTx assertion disable. */
         pciercx_cfg001.s.see = 1;       /* SERR# enable */
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
-                        pciercx_cfg001.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
 
         /* Advanced Error Recovery Message Enables */
         /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
@@ -440,14 +492,11 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         /* Use CVMX_PCIERCX_CFG067 hardware default */
         cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
 
-        /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
-        pciercx_cfg032.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
-        pciercx_cfg032.s.aslpc = 0;     /* Active state Link PM control. */
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
-                             pciercx_cfg032.u32);
 
-        /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
+        /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
+        pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+        pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
 
         /*
          * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
@@ -462,8 +511,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         pciercx_cfg006.s.pbnum = 1;
         pciercx_cfg006.s.sbnum = 1;
         pciercx_cfg006.s.subbnum = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
-                             pciercx_cfg006.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
+
 
         /*
          * Memory-mapped I/O BAR (PCIERCn_CFG008)
@@ -473,8 +522,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         pciercx_cfg008.u32 = 0;
         pciercx_cfg008.s.mb_addr = 0x100;
         pciercx_cfg008.s.ml_addr = 0;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
-                             pciercx_cfg008.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
+
 
         /*
          * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
@@ -482,72 +531,51 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
          * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
          * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
          */
-        pciercx_cfg009.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
-        pciercx_cfg010.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
-        pciercx_cfg011.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
+        pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
+        pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
+        pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
         pciercx_cfg009.s.lmem_base = 0x100;
         pciercx_cfg009.s.lmem_limit = 0;
         pciercx_cfg010.s.umem_base = 0x100;
         pciercx_cfg011.s.umem_limit = 0;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
-                             pciercx_cfg009.u32);
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
-                             pciercx_cfg010.u32);
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
-                             pciercx_cfg011.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
 
         /*
          * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
          * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
-         */
-        pciercx_cfg035.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
-        /* System error on correctable error enable. */
-        pciercx_cfg035.s.secee = 1;
-        /* System error on fatal error enable. */
-        pciercx_cfg035.s.sefee = 1;
-        /* System error on non-fatal error enable. */
-        pciercx_cfg035.s.senfee = 1;
-        /* PME interrupt enable. */
-        pciercx_cfg035.s.pmeie = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
-                             pciercx_cfg035.u32);
+        */
+        pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
+        pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
+        pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
+        pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
+        pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
 
         /*
          * Advanced Error Recovery Interrupt Enables
          * (PCIERCn_CFG075[CERE,NFERE,FERE])
          */
-        pciercx_cfg075.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
-        /* Correctable error reporting enable. */
-        pciercx_cfg075.s.cere = 1;
-        /* Non-fatal error reporting enable. */
-        pciercx_cfg075.s.nfere = 1;
-        /* Fatal error reporting enable. */
-        pciercx_cfg075.s.fere = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
-                             pciercx_cfg075.u32);
+        pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
+        pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
+        pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
+        pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
 
-        /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
+        /*
+         * HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
          * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
          */
-        pciercx_cfg034.u32 =
-                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
-        /* Hot-plug interrupt enable. */
-        pciercx_cfg034.s.hpint_en = 1;
-        /* Data Link Layer state changed enable */
-        pciercx_cfg034.s.dlls_en = 1;
-        /* Command completed interrupt enable. */
-        pciercx_cfg034.s.ccint_en = 1;
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
-                             pciercx_cfg034.u32);
+        pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
+        pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
+        pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
+        pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
 }
 
 /**
- * Initialize a host mode PCIe link. This function takes a PCIe
+ * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
  * port from reset to a link up state. Software can then begin
  * configuring the rest of the link.
  *
@@ -555,7 +583,7 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
  *
  * Returns Zero on success
  */
-static int __cvmx_pcie_rc_initialize_link(int pcie_port)
+static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
 {
         uint64_t start_cycle;
         union cvmx_pescx_ctl_status pescx_ctl_status;
@@ -564,18 +592,15 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
         union cvmx_pciercx_cfg448 pciercx_cfg448;
 
         /* Set the lane width */
-        pciercx_cfg452.u32 =
-            cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
+        pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
         pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
-        if (pescx_ctl_status.s.qlm_cfg == 0) {
+        if (pescx_ctl_status.s.qlm_cfg == 0)
                 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
                 pciercx_cfg452.s.lme = 0xf;
-        } else {
+        else
                 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
                 pciercx_cfg452.s.lme = 0x7;
-        }
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
-                             pciercx_cfg452.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);
 
         /*
          * CN52XX pass 1.x has an errata where length mismatches on UR
@@ -584,19 +609,15 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
          */
         if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
                 union cvmx_pciercx_cfg455 pciercx_cfg455;
-                pciercx_cfg455.u32 =
-                    cvmx_pcie_cfgx_read(pcie_port,
-                                        CVMX_PCIERCX_CFG455(pcie_port));
+                pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));
                 pciercx_cfg455.s.m_cpl_len_err = 1;
-                cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
-                                     pciercx_cfg455.u32);
+                cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);
         }
 
         /* Lane swap needs to be manually enabled for CN52XX */
         if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
                 pescx_ctl_status.s.lane_swp = 1;
-                cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
-                               pescx_ctl_status.u64);
+                cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
         }
 
         /* Bring up the link */
@@ -612,24 +633,18 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
                 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
 
         /* Wait for the link to come up */
-        cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
         start_cycle = cvmx_get_cycle();
         do {
-                if (cvmx_get_cycle() - start_cycle >
-                    2 * cvmx_sysinfo_get()->cpu_clock_hz) {
-                        cvmx_dprintf("PCIe: Port %d link timeout\n",
-                                     pcie_port);
+                if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) {
+                        cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
                         return -1;
                 }
                 cvmx_wait(10000);
-                pciercx_cfg032.u32 =
-                    cvmx_pcie_cfgx_read(pcie_port,
-                                        CVMX_PCIERCX_CFG032(pcie_port));
+                pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
         } while (pciercx_cfg032.s.dlla == 0);
 
-        /* Display the link status */
-        cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
-                     pciercx_cfg032.s.nlw);
+        /* Clear all pending errors */
+        cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
 
         /*
          * Update the Replay Time Limit. Empirically, some PCIe
@@ -639,8 +654,7 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
          * our actual 256 byte MPS. The numbers below are directly
          * from the PCIe spec table 3-4.
          */
-        pciercx_cfg448.u32 =
-            cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
+        pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
         switch (pciercx_cfg032.s.nlw) {
         case 1:         /* 1 lane */
                 pciercx_cfg448.s.rtl = 1677;
@@ -655,21 +669,28 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
                 pciercx_cfg448.s.rtl = 258;
                 break;
         }
-        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
-                             pciercx_cfg448.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
 
         return 0;
 }
 
+static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas)
+{
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                pmas->cn68xx.ba++;
+        else
+                pmas->cn63xx.ba++;
+}
+
 /**
- * Initialize a PCIe port for use in host(RC) mode. It doesn't
+ * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't
  * enumerate the bus.
  *
  * @pcie_port: PCIe port to initialize
  *
  * Returns Zero on success
  */
-static int cvmx_pcie_rc_initialize(int pcie_port)
+static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
 {
         int i;
         int base;
@@ -682,16 +703,17 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         union cvmx_npei_mem_access_subidx mem_access_subid;
         union cvmx_npei_dbg_data npei_dbg_data;
         union cvmx_pescx_ctl_status2 pescx_ctl_status2;
+        union cvmx_pciercx_cfg032 pciercx_cfg032;
         union cvmx_npei_bar1_indexx bar1_index;
 
+retry:
         /*
          * Make sure we aren't trying to setup a target mode interface
          * in host mode.
          */
         npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
         if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
-                cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
-                             "on port0, but port0 is not in host mode\n");
+                cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);
                 return -1;
         }
 
@@ -702,9 +724,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
                 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
                 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
-                        cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
-                                     "called on port1, but port1 is "
-                                     "disabled\n");
+                        cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n");
                         return -1;
                 }
         }
@@ -733,7 +753,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
                  * the board. As a workaround for this bug, we bring
                  * both PCIe ports out of reset at the same time
                  * instead of on separate calls. So for port 0, we
-                 * bring both out of reset and do nothing on port 1.
+                 * bring both out of reset and do nothing on port 1
                  */
                 if (pcie_port == 0) {
                         ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
@@ -746,13 +766,10 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
                         if (ciu_soft_prst.s.soft_prst == 0) {
                                 /* Reset the ports */
                                 ciu_soft_prst.s.soft_prst = 1;
-                                cvmx_write_csr(CVMX_CIU_SOFT_PRST,
-                                               ciu_soft_prst.u64);
-                                ciu_soft_prst.u64 =
-                                    cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+                                ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
                                 ciu_soft_prst.s.soft_prst = 1;
-                                cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
-                                               ciu_soft_prst.u64);
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
                                 /* Wait until pcie resets the ports. */
                                 udelay(2000);
                         }
@@ -782,11 +799,9 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
                         /* Reset the port */
                         ciu_soft_prst.s.soft_prst = 1;
                         if (pcie_port)
-                                cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
-                                               ciu_soft_prst.u64);
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
                         else
-                                cvmx_write_csr(CVMX_CIU_SOFT_PRST,
-                                               ciu_soft_prst.u64);
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
                         /* Wait until pcie resets the ports. */
                         udelay(2000);
                 }
@@ -808,25 +823,21 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
          */
         cvmx_wait(400000);
 
-        /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
-           CN52XX, so we only probe it on newer chips */
-        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
-            && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
+        /*
+         * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
+         * CN56XX and CN52XX, so we only probe it on newer chips
+         */
+        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
                 /* Clear PCLK_RUN so we can check if the clock is running */
-                pescx_ctl_status2.u64 =
-                    cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
+                pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
                 pescx_ctl_status2.s.pclk_run = 1;
-                cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
-                               pescx_ctl_status2.u64);
-                /*
-                 * Now that we cleared PCLK_RUN, wait for it to be set
-                 * again telling us the clock is running.
+                cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);
+                /* Now that we cleared PCLK_RUN, wait for it to be set
+                 * again telling us the clock is running
                  */
                 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
-                                          union cvmx_pescx_ctl_status2,
-                                          pclk_run, ==, 1, 10000)) {
-                        cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
-                                     pcie_port);
+                                          union cvmx_pescx_ctl_status2, pclk_run, ==, 1, 10000)) {
+                        cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);
                         return -1;
                 }
         }
@@ -836,30 +847,26 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
          * the board probably hasn't wired the clocks up and the
          * interface should be skipped.
          */
-        pescx_ctl_status2.u64 =
-            cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
+        pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
         if (pescx_ctl_status2.s.pcierst) {
-                cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
-                             pcie_port);
+                cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
                 return -1;
         }
 
         /*
-         * Check BIST2 status. If any bits are set skip this interface. This
-         * is an attempt to catch PCIE-813 on pass 1 parts.
+         * Check BIST2 status. If any bits are set skip this
+         * interface. This is an attempt to catch PCIE-813 on pass 1
+         * parts.
          */
-        pescx_bist_status2.u64 =
-            cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
+        pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
         if (pescx_bist_status2.u64) {
-                cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
-                             "port isn't hooked up, skipping.\n",
+                cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n",
                              pcie_port);
                 return -1;
         }
 
         /* Check BIST status */
-        pescx_bist_status.u64 =
-            cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
+        pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
         if (pescx_bist_status.u64)
                 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
                              pcie_port, CAST64(pescx_bist_status.u64));
@@ -868,50 +875,37 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         __cvmx_pcie_rc_initialize_config_space(pcie_port);
 
         /* Bring the link up */
-        if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
-                cvmx_dprintf
-                    ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
+        if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) {
+                cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n",
+                             pcie_port);
                 return -1;
         }
 
         /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
         npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
-        /* Allow 16 words to combine */
-        npei_mem_access_ctl.s.max_word = 0;
-        /* Wait up to 127 cycles for more data */
-        npei_mem_access_ctl.s.timer = 127;
+        npei_mem_access_ctl.s.max_word = 0;     /* Allow 16 words to combine */
+        npei_mem_access_ctl.s.timer = 127;      /* Wait up to 127 cycles for more data */
         cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
 
         /* Setup Mem access SubDIDs */
         mem_access_subid.u64 = 0;
-        /* Port the request is sent to. */
-        mem_access_subid.s.port = pcie_port;
-        /* Due to an errata on pass 1 chips, no merging is allowed. */
-        mem_access_subid.s.nmerge = 1;
-        /* Endian-swap for Reads. */
-        mem_access_subid.s.esr = 1;
-        /* Endian-swap for Writes. */
-        mem_access_subid.s.esw = 1;
-        /* No Snoop for Reads. */
-        mem_access_subid.s.nsr = 1;
-        /* No Snoop for Writes. */
-        mem_access_subid.s.nsw = 1;
-        /* Disable Relaxed Ordering for Reads. */
-        mem_access_subid.s.ror = 0;
-        /* Disable Relaxed Ordering for Writes. */
-        mem_access_subid.s.row = 0;
-        /* PCIe Address Bits <63:34>. */
-        mem_access_subid.s.ba = 0;
+        mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
+        mem_access_subid.s.nmerge = 1;  /* Due to an errata on pass 1 chips, no merging is allowed. */
+        mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
+        mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
+        mem_access_subid.s.nsr = 0;     /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
+        mem_access_subid.s.nsw = 0;     /* Enable Snoop for Writes. */
+        mem_access_subid.s.ror = 0;     /* Disable Relaxed Ordering for Reads. */
+        mem_access_subid.s.row = 0;     /* Disable Relaxed Ordering for Writes. */
+        mem_access_subid.s.ba = 0;      /* PCIe Adddress Bits <63:34>. */
 
         /*
          * Setup mem access 12-15 for port 0, 16-19 for port 1,
          * supplying 36 bits of address space.
          */
         for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
-                cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
-                               mem_access_subid.u64);
-                /* Set each SUBID to extend the addressable range */
-                mem_access_subid.s.ba += 1;
+                cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
+                mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
         }
 
         /*
@@ -927,7 +921,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
         cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
 
-        /* BAR1 follows BAR2 with a gap. */
+        /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */
         cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
 
         bar1_index.u32 = 0;
@@ -992,14 +986,474 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
                 npei_ctl_port.s.waitl_com = 0;
                 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
         }
+
+        /*
+         * Both pass 1 and pass 2 of CN52XX and CN56XX have an errata
+         * that causes TLP ordering to not be preserved after multiple
+         * PCIe port resets. This code detects this fault and corrects
+         * it by aligning the TLP counters properly. Another link
+         * reset is then performed. See PCIE-13340
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
+            OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
+            OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) ||
+            OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
+                union cvmx_npei_dbg_data dbg_data;
+                int old_in_fif_p_count;
+                int in_fif_p_count;
+                int out_p_count;
+                int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1;
+                int i;
+
+                /*
+                 * Choose a write address of 1MB. It should be
+                 * harmless as all bars haven't been setup.
+                 */
+                uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);
+
+                /*
+                 * Make sure at least in_p_offset have been executed before we try and
+                 * read in_fif_p_count
+                 */
+                i = in_p_offset;
+                while (i--) {
+                        cvmx_write64_uint32(write_address, 0);
+                        cvmx_wait(10000);
+                }
+
+                /*
+                 * Read the IN_FIF_P_COUNT from the debug
+                 * select. IN_FIF_P_COUNT can be unstable sometimes so
+                 * read it twice with a write between the reads.  This
+                 * way we can tell the value is good as it will
+                 * increment by one due to the write
+                 */
+                cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);
+                cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
+                do {
+                        dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+                        old_in_fif_p_count = dbg_data.s.data & 0xff;
+                        cvmx_write64_uint32(write_address, 0);
+                        cvmx_wait(10000);
+                        dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+                        in_fif_p_count = dbg_data.s.data & 0xff;
+                } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
+
+                /* Update in_fif_p_count for it's offset with respect to out_p_count */
+                in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
+
+                /* Read the OUT_P_COUNT from the debug select */
+                cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);
+                cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
+                dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+                out_p_count = (dbg_data.s.data>>1) & 0xff;
+
+                /* Check that the two counters are aligned */
+                if (out_p_count != in_fif_p_count) {
+                        cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
+                        while (in_fif_p_count != 0) {
+                                cvmx_write64_uint32(write_address, 0);
+                                cvmx_wait(10000);
+                                in_fif_p_count = (in_fif_p_count + 1) & 0xff;
+                        }
+                        /*
+                         * The EBH5200 board swapped the PCIe reset
+                         * lines on the board. This means we must
+                         * bring both links down and up, which will
+                         * cause the PCIe0 to need alignment
+                         * again. Lots of messages will be displayed,
+                         * but everything should work
+                         */
+                        if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
+                                (pcie_port == 1))
+                                cvmx_pcie_rc_initialize(0);
+                        /* Rety bringing this port up */
+                        goto retry;
+                }
+        }
+
+        /* Display the link status */
+        pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+        cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
+
         return 0;
 }
 
+/**
+  * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
+ * port from reset to a link up state. Software can then begin
+ * configuring the rest of the link.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Return Zero on success.
+ */
+static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
+{
+        uint64_t start_cycle;
+        union cvmx_pemx_ctl_status pem_ctl_status;
+        union cvmx_pciercx_cfg032 pciercx_cfg032;
+        union cvmx_pciercx_cfg448 pciercx_cfg448;
 
-/* Above was cvmx-pcie.c, below original pcie.c */
+        /* Bring up the link */
+        pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
+        pem_ctl_status.s.lnk_enb = 1;
+        cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
+
+        /* Wait for the link to come up */
+        start_cycle = cvmx_get_cycle();
+        do {
+                if (cvmx_get_cycle() - start_cycle >  octeon_get_clock_rate())
+                        return -1;
+                cvmx_wait(10000);
+                pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+        } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
+
+        /*
+         * Update the Replay Time Limit. Empirically, some PCIe
+         * devices take a little longer to respond than expected under
+         * load. As a workaround for this we configure the Replay Time
+         * Limit to the value expected for a 512 byte MPS instead of
+         * our actual 256 byte MPS. The numbers below are directly
+         * from the PCIe spec table 3-4
+         */
+        pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
+        switch (pciercx_cfg032.s.nlw) {
+        case 1: /* 1 lane */
+                pciercx_cfg448.s.rtl = 1677;
+                break;
+        case 2: /* 2 lanes */
+                pciercx_cfg448.s.rtl = 867;
+                break;
+        case 4: /* 4 lanes */
+                pciercx_cfg448.s.rtl = 462;
+                break;
+        case 8: /* 8 lanes */
+                pciercx_cfg448.s.rtl = 258;
+                break;
+        }
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
+
+        return 0;
+}
 
 
 /**
+ * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
+ * the bus.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Returns Zero on success.
+ */
+static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
+{
+        int i;
+        union cvmx_ciu_soft_prst ciu_soft_prst;
+        union cvmx_mio_rst_ctlx mio_rst_ctl;
+        union cvmx_pemx_bar_ctl pemx_bar_ctl;
+        union cvmx_pemx_ctl_status pemx_ctl_status;
+        union cvmx_pemx_bist_status pemx_bist_status;
+        union cvmx_pemx_bist_status2 pemx_bist_status2;
+        union cvmx_pciercx_cfg032 pciercx_cfg032;
+        union cvmx_pciercx_cfg515 pciercx_cfg515;
+        union cvmx_sli_ctl_portx sli_ctl_portx;
+        union cvmx_sli_mem_access_ctl sli_mem_access_ctl;
+        union cvmx_sli_mem_access_subidx mem_access_subid;
+        union cvmx_sriox_status_reg sriox_status_reg;
+        union cvmx_pemx_bar1_indexx bar1_index;
+
+        if (octeon_has_feature(OCTEON_FEATURE_SRIO)) {
+                /* Make sure this interface isn't SRIO */
+                if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
+                        /*
+                         * The CN66XX requires reading the
+                         * MIO_QLMX_CFG register to figure out the
+                         * port type.
+                         */
+                        union cvmx_mio_qlmx_cfg qlmx_cfg;
+                        qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));
+
+                        if (qlmx_cfg.s.qlm_spd == 15) {
+                                pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port);
+                                return -1;
+                        }
+
+                        switch (qlmx_cfg.s.qlm_spd) {
+                        case 0x1: /* SRIO 1x4 short */
+                        case 0x3: /* SRIO 1x4 long */
+                        case 0x4: /* SRIO 2x2 short */
+                        case 0x6: /* SRIO 2x2 long */
+                                pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
+                                return -1;
+                        case 0x9: /* SGMII */
+                                pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port);
+                                return -1;
+                        case 0xb: /* XAUI */
+                                pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port);
+                                return -1;
+                        case 0x0: /* PCIE gen2 */
+                        case 0x8: /* PCIE gen2 (alias) */
+                        case 0x2: /* PCIE gen1 */
+                        case 0xa: /* PCIE gen1 (alias) */
+                                break;
+                        default:
+                                pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port);
+                                return -1;
+                        }
+                } else {
+                        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
+                        if (sriox_status_reg.s.srio) {
+                                pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
+                                return -1;
+                        }
+                }
+        }
+
+#if 0
+    /* This code is so that the PCIe analyzer is able to see 63XX traffic */
+        pr_notice("PCIE : init for pcie analyzer.\n");
+        cvmx_helper_qlm_jtag_init();
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+        cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+        cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+        cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+        cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+        cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+        cvmx_helper_qlm_jtag_update(pcie_port);
+#endif
+
+        /* Make sure we aren't trying to setup a target mode interface in host mode */
+        mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
+        if (!mio_rst_ctl.s.host_mode) {
+                pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port);
+                return -1;
+        }
+
+        /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
+                if (pcie_port) {
+                        union cvmx_ciu_qlm1 ciu_qlm;
+                        ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
+                        ciu_qlm.s.txbypass = 1;
+                        ciu_qlm.s.txdeemph = 5;
+                        ciu_qlm.s.txmargin = 0x17;
+                        cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
+                } else {
+                        union cvmx_ciu_qlm0 ciu_qlm;
+                        ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
+                        ciu_qlm.s.txbypass = 1;
+                        ciu_qlm.s.txdeemph = 5;
+                        ciu_qlm.s.txmargin = 0x17;
+                        cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
+                }
+        }
+        /* Bring the PCIe out of reset */
+        if (pcie_port)
+                ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+        else
+                ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+        /*
+         * After a chip reset the PCIe will also be in reset. If it
+         * isn't, most likely someone is trying to init it again
+         * without a proper PCIe reset
+         */
+        if (ciu_soft_prst.s.soft_prst == 0) {
+                /* Reset the port */
+                ciu_soft_prst.s.soft_prst = 1;
+                if (pcie_port)
+                        cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+                else
+                        cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+                /* Wait until pcie resets the ports. */
+                udelay(2000);
+        }
+        if (pcie_port) {
+                ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+                ciu_soft_prst.s.soft_prst = 0;
+                cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+        } else {
+                ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+                ciu_soft_prst.s.soft_prst = 0;
+                cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+        }
+
+        /* Wait for PCIe reset to complete */
+        udelay(1000);
+
+        /*
+         * Check and make sure PCIe came out of reset. If it doesn't
+         * the board probably hasn't wired the clocks up and the
+         * interface should be skipped.
+         */
+        if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {
+                pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
+                return -1;
+        }
+
+        /* Check BIST status */
+        pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));
+        if (pemx_bist_status.u64)
+                pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
+        pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
+        /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+                pemx_bist_status2.u64 &= ~0x3full;
+        if (pemx_bist_status2.u64)
+                pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
+
+        /* Initialize the config space CSRs */
+        __cvmx_pcie_rc_initialize_config_space(pcie_port);
+
+        /* Enable gen2 speed selection */
+        pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
+        pciercx_cfg515.s.dsc = 1;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
+
+        /* Bring the link up */
+        if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
+                /*
+                 * Some gen1 devices don't handle the gen 2 training
+                 * correctly. Disable gen2 and try again with only
+                 * gen1
+                 */
+                union cvmx_pciercx_cfg031 pciercx_cfg031;
+                pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
+                pciercx_cfg031.s.mls = 1;
+                cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
+                if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
+                        pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
+                        return -1;
+                }
+        }
+
+        /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
+        sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
+        sli_mem_access_ctl.s.max_word = 0;      /* Allow 16 words to combine */
+        sli_mem_access_ctl.s.timer = 127;       /* Wait up to 127 cycles for more data */
+        cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
+
+        /* Setup Mem access SubDIDs */
+        mem_access_subid.u64 = 0;
+        mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
+        mem_access_subid.s.nmerge = 0;  /* Allow merging as it works on CN6XXX. */
+        mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
+        mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
+        mem_access_subid.s.wtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
+        mem_access_subid.s.rtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
+        /* PCIe Adddress Bits <63:34>. */
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                mem_access_subid.cn68xx.ba = 0;
+        else
+                mem_access_subid.cn63xx.ba = 0;
+
+        /*
+         * Setup mem access 12-15 for port 0, 16-19 for port 1,
+         * supplying 36 bits of address space.
+         */
+        for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
+                cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
+                /* Set each SUBID to extend the addressable range */
+                __cvmx_increment_ba(&mem_access_subid);
+        }
+
+        /*
+         * Disable the peer to peer forwarding register. This must be
+         * setup by the OS after it enumerates the bus and assigns
+         * addresses to the PCIe busses.
+         */
+        for (i = 0; i < 4; i++) {
+                cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
+                cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
+        }
+
+        /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
+        cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
+
+        /*
+         * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take
+         * precedence where they overlap. It also overlaps with the
+         * device addresses, so make sure the peer to peer forwarding
+         * is set right.
+         */
+        cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
+
+        /*
+         * Setup BAR2 attributes
+         * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
+         * - PTLP_RO,CTLP_RO should normally be set (except for debug).
+         * - WAIT_COM=0 will likely work for all applications.
+         * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM])
+         */
+        pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
+        pemx_bar_ctl.s.bar1_siz = 3;  /* 256MB BAR1*/
+        pemx_bar_ctl.s.bar2_enb = 1;
+        pemx_bar_ctl.s.bar2_esx = 1;
+        pemx_bar_ctl.s.bar2_cax = 0;
+        cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
+        sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
+        sli_ctl_portx.s.ptlp_ro = 1;
+        sli_ctl_portx.s.ctlp_ro = 1;
+        sli_ctl_portx.s.wait_com = 0;
+        sli_ctl_portx.s.waitl_com = 0;
+        cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
+
+        /* BAR1 follows BAR2 */
+        cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
+
+        bar1_index.u64 = 0;
+        bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
+        bar1_index.s.ca = 1;       /* Not Cached */
+        bar1_index.s.end_swp = 1;  /* Endian Swap mode */
+        bar1_index.s.addr_v = 1;   /* Valid entry */
+
+        for (i = 0; i < 16; i++) {
+                cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
+                /* 256MB / 16 >> 22 == 4 */
+                bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
+        }
+
+        /*
+         * Allow config retries for 250ms. Count is based off the 5Ghz
+         * SERDES clock.
+         */
+        pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
+        pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000;
+        cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
+
+        /* Display the link status */
+        pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+        pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
+
+        return 0;
+}
+
+/**
+ * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Returns Zero on success
+ */
+static int cvmx_pcie_rc_initialize(int pcie_port)
+{
+        int result;
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+                result = __cvmx_pcie_rc_initialize_gen1(pcie_port);
+        else
+                result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
+        return result;
+}
+
+/* Above was cvmx-pcie.c, below original pcie.c */
+
+/**
  * Map a PCI device to the appropriate interrupt line
  *
  * @dev:    The Linux PCI device structure for the device to map
@@ -1027,11 +1481,12 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
                  */
                 while (dev->bus && dev->bus->parent)
                         dev = to_pci_dev(dev->bus->bridge);
-                /* If the root bus is number 0 and the PEX 8114 is the
+                /*
+                 * If the root bus is number 0 and the PEX 8114 is the
                  * root, assume we are behind the miswired bus. We
                  * need to correct the swizzle level by two. Yuck.
                  */
-                if ((dev->bus->number == 0) &&
+                if ((dev->bus->number == 1) &&
                     (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
                         /*
                          * The pin field is one based, not zero. We
@@ -1048,39 +1503,73 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
         return pin - 1 + OCTEON_IRQ_PCI_INT0;
 }
 
-/**
+static  void set_cfg_read_retry(u32 retry_cnt)
+{
+        union cvmx_pemx_ctl_status pemx_ctl;
+        pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
+        pemx_ctl.s.cfg_rtry = retry_cnt;
+        cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
+}
+
+
+static u32 disable_cfg_read_retry(void)
+{
+        u32 retry_cnt;
+
+        union cvmx_pemx_ctl_status pemx_ctl;
+        pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
+        retry_cnt =  pemx_ctl.s.cfg_rtry;
+        pemx_ctl.s.cfg_rtry = 0;
+        cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
+        return retry_cnt;
+}
+
+static int is_cfg_retry(void)
+{
+        union cvmx_pemx_int_sum pemx_int_sum;
+        pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1));
+        if (pemx_int_sum.s.crs_dr)
+                return 1;
+        return 0;
+}
+
+/*
  * Read a value from configuration space
  *
- * @bus:
- * @devfn:
- * @reg:
- * @size:
- * @val:
- * Returns
  */
-static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
-                                          unsigned int devfn, int reg, int size,
-                                          u32 *val)
+static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus,
+                                   unsigned int devfn, int reg, int size,
+                                   u32 *val)
 {
         union octeon_cvmemctl cvmmemctl;
         union octeon_cvmemctl cvmmemctl_save;
         int bus_number = bus->number;
+        int cfg_retry = 0;
+        int retry_cnt = 0;
+        int max_retry_cnt = 10;
+        u32 cfg_retry_cnt = 0;
 
+        cvmmemctl_save.u64 = 0;
+        BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
         /*
          * For the top level bus make sure our hardware bus number
-         * matches the software one.
+         * matches the software one
          */
         if (bus->parent == NULL) {
-                union cvmx_pciercx_cfg006 pciercx_cfg006;
-                pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
-                        CVMX_PCIERCX_CFG006(pcie_port));
-                if (pciercx_cfg006.s.pbnum != bus_number) {
-                        pciercx_cfg006.s.pbnum = bus_number;
-                        pciercx_cfg006.s.sbnum = bus_number;
-                        pciercx_cfg006.s.subbnum = bus_number;
-                        cvmx_pcie_cfgx_write(pcie_port,
-                                CVMX_PCIERCX_CFG006(pcie_port),
-                                pciercx_cfg006.u32);
+                if (enable_pcie_bus_num_war[pcie_port])
+                        bus_number = 0;
+                else {
+                        union cvmx_pciercx_cfg006 pciercx_cfg006;
+                        pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
+                                             CVMX_PCIERCX_CFG006(pcie_port));
+                        if (pciercx_cfg006.s.pbnum != bus_number) {
+                                pciercx_cfg006.s.pbnum = bus_number;
+                                pciercx_cfg006.s.sbnum = bus_number;
+                                pciercx_cfg006.s.subbnum = bus_number;
+                                cvmx_pcie_cfgx_write(pcie_port,
+                                            CVMX_PCIERCX_CFG006(pcie_port),
+                                            pciercx_cfg006.u32);
+                        }
                 }
         }
 
@@ -1116,29 +1605,52 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
                  */
 #if 1
                 /* Use this option if you aren't using either slot */
-                if (bus_number == 1)
+                if (bus_number == 2)
                         return PCIBIOS_FUNC_NOT_SUPPORTED;
 #elif 0
                 /*
                  * Use this option if you are using the first slot but
                  * not the second.
                  */
-                if ((bus_number == 1) && (devfn >> 3 != 2))
+                if ((bus_number == 2) && (devfn >> 3 != 2))
                         return PCIBIOS_FUNC_NOT_SUPPORTED;
 #elif 0
                 /*
                  * Use this option if you are using the second slot
                  * but not the first.
                  */
-                if ((bus_number == 1) && (devfn >> 3 != 3))
+                if ((bus_number == 2) && (devfn >> 3 != 3))
                         return PCIBIOS_FUNC_NOT_SUPPORTED;
 #elif 0
                 /* Use this opion if you are using both slots */
-                if ((bus_number == 1) &&
+                if ((bus_number == 2) &&
                     !((devfn == (2 << 3)) || (devfn == (3 << 3))))
                         return PCIBIOS_FUNC_NOT_SUPPORTED;
 #endif
 
+                /* The following #if gives a more complicated example. This is
+                   the required checks for running a Nitrox CN16XX-NHBX in the
+                   slot of the EBH5600. This card has a PLX PCIe bridge with
+                   four Nitrox PLX parts behind it */
+#if 0
+                /* PLX bridge with 4 ports */
+                if ((bus_number == 4) &&
+                    !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                /* Nitrox behind PLX 1 */
+                if ((bus_number == 5) && (devfn >> 3 != 0))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                /* Nitrox behind PLX 2 */
+                if ((bus_number == 6) && (devfn >> 3 != 0))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                /* Nitrox behind PLX 3 */
+                if ((bus_number == 7) && (devfn >> 3 != 0))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                /* Nitrox behind PLX 4 */
+                if ((bus_number == 8) && (devfn >> 3 != 0))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+#endif
+
                 /*
                  * Shorten the DID timeout so bus errors for PCIe
                  * config reads from non existent devices happen
@@ -1152,26 +1664,48 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
                 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
         }
 
-        switch (size) {
-        case 4:
-                *val = cvmx_pcie_config_read32(pcie_port, bus_number,
-                                               devfn >> 3, devfn & 0x7, reg);
+        if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
+                cfg_retry_cnt = disable_cfg_read_retry();
+
+        pr_debug("pcie_cfg_rd port=%d b=%d devfn=0x%03x reg=0x%03x"
+                 " size=%d ", pcie_port, bus_number, devfn, reg, size);
+        do {
+                switch (size) {
+                case 4:
+                        *val = cvmx_pcie_config_read32(pcie_port, bus_number,
+                                devfn >> 3, devfn & 0x7, reg);
                 break;
-        case 2:
-                *val = cvmx_pcie_config_read16(pcie_port, bus_number,
-                                               devfn >> 3, devfn & 0x7, reg);
+                case 2:
+                        *val = cvmx_pcie_config_read16(pcie_port, bus_number,
+                                devfn >> 3, devfn & 0x7, reg);
                 break;
-        case 1:
-                *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
-                                              devfn & 0x7, reg);
+                case 1:
+                        *val = cvmx_pcie_config_read8(pcie_port, bus_number,
+                                devfn >> 3, devfn & 0x7, reg);
                 break;
-        default:
-                return PCIBIOS_FUNC_NOT_SUPPORTED;
-        }
+                default:
+                        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+                                set_cfg_read_retry(cfg_retry_cnt);
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                }
+                if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) &&
+                        (enable_pcie_14459_war)) {
+                        cfg_retry = is_cfg_retry();
+                        retry_cnt++;
+                        if (retry_cnt > max_retry_cnt) {
+                                pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n",
+                                       retry_cnt);
+                                cfg_retry = 0;
+                        }
+                }
+        } while (cfg_retry);
 
+        if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
+                set_cfg_read_retry(cfg_retry_cnt);
+        pr_debug("val=%08x  : tries=%02d\n", *val, retry_cnt);
         if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
             OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
-                __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
+                write_c0_cvmmemctl(cvmmemctl_save.u64);
         return PCIBIOS_SUCCESSFUL;
 }
 
@@ -1187,42 +1721,56 @@ static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
         return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
 }
 
+static int octeon_dummy_read_config(struct pci_bus *bus, unsigned int devfn,
+                                    int reg, int size, u32 *val)
+{
+        return PCIBIOS_FUNC_NOT_SUPPORTED;
+}
 
-
-/**
+/*
  * Write a value to PCI configuration space
- *
- * @bus:
- * @devfn:
- * @reg:
- * @size:
- * @val:
- * Returns
  */
-static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
-                                           unsigned int devfn, int reg,
-                                           int size, u32 val)
+static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
+                                    unsigned int devfn, int reg,
+                                    int size, u32 val)
 {
         int bus_number = bus->number;
 
+        BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
+
+        if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))
+                bus_number = 0;
+
+        pr_debug("pcie_cfg_wr port=%d b=%d devfn=0x%03x"
+                 " reg=0x%03x size=%d val=%08x\n", pcie_port, bus_number, devfn,
+                 reg, size, val);
+
+
         switch (size) {
         case 4:
                 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
                                          devfn & 0x7, reg, val);
-                return PCIBIOS_SUCCESSFUL;
+                break;
         case 2:
                 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
                                          devfn & 0x7, reg, val);
-                return PCIBIOS_SUCCESSFUL;
+                break;
         case 1:
                 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
                                         devfn & 0x7, reg, val);
-                return PCIBIOS_SUCCESSFUL;
+                break;
+        default:
+                return PCIBIOS_FUNC_NOT_SUPPORTED;
         }
 #if PCI_CONFIG_SPACE_DELAY
+        /*
+         * Delay on writes so that devices have time to come up. Some
+         * bridges need this to allow time for the secondary busses to
+         * work
+         */
         udelay(PCI_CONFIG_SPACE_DELAY);
 #endif
-        return PCIBIOS_FUNC_NOT_SUPPORTED;
+        return PCIBIOS_SUCCESSFUL;
 }
 
 static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -1237,6 +1785,12 @@ static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
         return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
 }
 
+static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn,
+                                     int reg, int size, u32 val)
+{
+        return PCIBIOS_FUNC_NOT_SUPPORTED;
+}
+
 static struct pci_ops octeon_pcie0_ops = {
         octeon_pcie0_read_config,
         octeon_pcie0_write_config,
@@ -1279,6 +1833,35 @@ static struct pci_controller octeon_pcie1_controller = {
         .io_resource = &octeon_pcie1_io_resource,
 };
 
+static struct pci_ops octeon_dummy_ops = {
+        octeon_dummy_read_config,
+        octeon_dummy_write_config,
+};
+
+static struct resource octeon_dummy_mem_resource = {
+        .name = "Virtual PCIe MEM",
+        .flags = IORESOURCE_MEM,
+};
+
+static struct resource octeon_dummy_io_resource = {
+        .name = "Virtual PCIe IO",
+        .flags = IORESOURCE_IO,
+};
+
+static struct pci_controller octeon_dummy_controller = {
+        .pci_ops = &octeon_dummy_ops,
+        .mem_resource = &octeon_dummy_mem_resource,
+        .io_resource = &octeon_dummy_io_resource,
+};
+
+static int device_needs_bus_num_war(uint32_t deviceid)
+{
+#define IDT_VENDOR_ID 0x111d
+
+        if ((deviceid  & 0xffff) == IDT_VENDOR_ID)
+                return 1;
+        return 0;
+}
 
 /**
  * Initialize the Octeon PCIe controllers
@@ -1287,19 +1870,27 @@ static struct pci_controller octeon_pcie1_controller = {
  */
 static int __init octeon_pcie_setup(void)
 {
-        union cvmx_npei_ctl_status npei_ctl_status;
         int result;
+        int host_mode;
+        int srio_war15205 = 0, port;
+        union cvmx_sli_ctl_portx sli_ctl_portx;
+        union cvmx_sriox_status_reg sriox_status_reg;
 
         /* These chips don't have PCIe */
         if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
                 return 0;
 
+        /* No PCIe simulation */
+        if (octeon_is_simulation())
+                return 0;
+
+        /* Disable PCI if instructed on the command line */
+        if (pcie_disable)
+                return 0;
+
         /* Point pcibios_map_irq() to the PCIe version of it */
         octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
 
-        /* Use the PCIe based DMA mappings */
-        octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
-
         /*
          * PCIe I/O range. It is based on port 0 but includes up until
          * port 1's end.
@@ -1310,11 +1901,43 @@ static int __init octeon_pcie_setup(void)
                 cvmx_pcie_get_io_base_address(1) -
                 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
 
-        npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
-        if (npei_ctl_status.s.host_mode) {
+        /*
+         * Create a dummy PCIe controller to swallow up bus 0. IDT bridges
+         * don't work if the primary bus number is zero. Here we add a fake
+         * PCIe controller that the kernel will give bus 0. This allows
+         * us to not change the normal kernel bus enumeration
+         */
+        octeon_dummy_controller.io_map_base = -1;
+        octeon_dummy_controller.mem_resource->start = (1ull<<48);
+        octeon_dummy_controller.mem_resource->end = (1ull<<48);
+        register_pci_controller(&octeon_dummy_controller);
+
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+                union cvmx_npei_ctl_status npei_ctl_status;
+                npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
+                host_mode = npei_ctl_status.s.host_mode;
+                octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
+        } else {
+                union cvmx_mio_rst_ctlx mio_rst_ctl;
+                mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0));
+                host_mode = mio_rst_ctl.s.host_mode;
+                octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE2;
+        }
+
+        if (host_mode) {
                 pr_notice("PCIe: Initializing port 0\n");
+                /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
+                if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+                        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
+                        if (sriox_status_reg.s.srio) {
+                                srio_war15205 += 1;      /* Port is SRIO */
+                                port = 0;
+                        }
+                }
                 result = cvmx_pcie_rc_initialize(0);
                 if (result == 0) {
+                        uint32_t device0;
                         /* Memory offsets are physical addresses */
                         octeon_pcie0_controller.mem_offset =
                                 cvmx_pcie_get_mem_base_address(0);
@@ -1343,60 +1966,134 @@ static int __init octeon_pcie_setup(void)
                         octeon_pcie0_controller.io_resource->start = 4 << 10;
                         octeon_pcie0_controller.io_resource->end =
                                 cvmx_pcie_get_io_size(0) - 1;
+                        msleep(100); /* Some devices need extra time */
                         register_pci_controller(&octeon_pcie0_controller);
+                        device0 = cvmx_pcie_config_read32(0, 0, 0, 0, 0);
+                        enable_pcie_bus_num_war[0] =
+                                device_needs_bus_num_war(device0);
                 }
         } else {
                 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
+                /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
+                if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+                        srio_war15205 += 1;
+                        port = 0;
+                }
         }
 
-        /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
-        if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
-                union cvmx_npei_dbg_data npei_dbg_data;
-                npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
-                if (npei_dbg_data.cn52xx.qlm0_link_width)
-                        return 0;
+        if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+                host_mode = 1;
+                /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
+                if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                        union cvmx_npei_dbg_data dbg_data;
+                        dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+                        if (dbg_data.cn52xx.qlm0_link_width)
+                                host_mode = 0;
+                }
+        } else {
+                union cvmx_mio_rst_ctlx mio_rst_ctl;
+                mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1));
+                host_mode = mio_rst_ctl.s.host_mode;
         }
 
-        pr_notice("PCIe: Initializing port 1\n");
-        result = cvmx_pcie_rc_initialize(1);
-        if (result == 0) {
-                /* Memory offsets are physical addresses */
-                octeon_pcie1_controller.mem_offset =
-                        cvmx_pcie_get_mem_base_address(1);
-                /* IO offsets are Mips virtual addresses */
-                octeon_pcie1_controller.io_map_base =
-                        CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
-                octeon_pcie1_controller.io_offset =
-                        cvmx_pcie_get_io_base_address(1) -
-                        cvmx_pcie_get_io_base_address(0);
-                /*
-                 * To keep things similar to PCI, we start device
-                 * addresses at the same place as PCI uisng big bar
-                 * support. This normally translates to 4GB-256MB,
-                 * which is the same as most x86 PCs.
-                 */
-                octeon_pcie1_controller.mem_resource->start =
-                        cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
-                        (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
-                octeon_pcie1_controller.mem_resource->end =
-                        cvmx_pcie_get_mem_base_address(1) +
-                        cvmx_pcie_get_mem_size(1) - 1;
-                /*
-                 * Ports must be above 16KB for the ISA bus filtering
-                 * in the PCI-X to PCI bridge.
-                 */
-                octeon_pcie1_controller.io_resource->start =
-                        cvmx_pcie_get_io_base_address(1) -
-                        cvmx_pcie_get_io_base_address(0);
-                octeon_pcie1_controller.io_resource->end =
-                        octeon_pcie1_controller.io_resource->start +
-                        cvmx_pcie_get_io_size(1) - 1;
-                register_pci_controller(&octeon_pcie1_controller);
+        if (host_mode) {
+                pr_notice("PCIe: Initializing port 1\n");
+                /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
+                if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+                        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
+                        if (sriox_status_reg.s.srio) {
+                                srio_war15205 += 1;      /* Port is SRIO */
+                                port = 1;
+                        }
+                }
+                result = cvmx_pcie_rc_initialize(1);
+                if (result == 0) {
+                        uint32_t device0;
+                        /* Memory offsets are physical addresses */
+                        octeon_pcie1_controller.mem_offset =
+                                cvmx_pcie_get_mem_base_address(1);
+                        /*
+                         * To calculate the address for accessing the 2nd PCIe device,
+                         * either 'io_map_base' (pci_iomap()), or 'mips_io_port_base'
+                         * (ioport_map()) value is added to
+                         * pci_resource_start(dev,bar)). The 'mips_io_port_base' is set
+                         * only once based on first PCIe. Also changing 'io_map_base'
+                         * based on first slot's value so that both the routines will
+                         * work properly.
+                         */
+                        octeon_pcie1_controller.io_map_base =
+                                CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0));
+                        /* IO offsets are Mips virtual addresses */
+                        octeon_pcie1_controller.io_offset =
+                                cvmx_pcie_get_io_base_address(1) -
+                                cvmx_pcie_get_io_base_address(0);
+                        /*
+                         * To keep things similar to PCI, we start device
+                         * addresses at the same place as PCI uisng big bar
+                         * support. This normally translates to 4GB-256MB,
+                         * which is the same as most x86 PCs.
+                         */
+                        octeon_pcie1_controller.mem_resource->start =
+                                cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
+                                (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
+                        octeon_pcie1_controller.mem_resource->end =
+                                cvmx_pcie_get_mem_base_address(1) +
+                                cvmx_pcie_get_mem_size(1) - 1;
+                        /*
+                         * Ports must be above 16KB for the ISA bus filtering
+                         * in the PCI-X to PCI bridge.
+                         */
+                        octeon_pcie1_controller.io_resource->start =
+                                cvmx_pcie_get_io_base_address(1) -
+                                cvmx_pcie_get_io_base_address(0);
+                        octeon_pcie1_controller.io_resource->end =
+                                octeon_pcie1_controller.io_resource->start +
+                                cvmx_pcie_get_io_size(1) - 1;
+                        msleep(100); /* Some devices need extra time */
+                        register_pci_controller(&octeon_pcie1_controller);
+                        device0 = cvmx_pcie_config_read32(1, 0, 0, 0, 0);
+                        enable_pcie_bus_num_war[1] =
+                                device_needs_bus_num_war(device0);
+                }
+        } else {
+                pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n");
+                /* CN63XX pass 1_x/2.0 errata PCIe-15205  */
+                if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+                        srio_war15205 += 1;
+                        port = 1;
+                }
+        }
+
+        /*
+         * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all
+         * of SRIO MACs SLI_CTL_PORT*[INT*_MAP] to similar value and
+         * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value
+         * from the previous set values
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+                OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+                if (srio_war15205 == 1) {
+                        sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port));
+                        sli_ctl_portx.s.inta_map = 1;
+                        sli_ctl_portx.s.intb_map = 1;
+                        sli_ctl_portx.s.intc_map = 1;
+                        sli_ctl_portx.s.intd_map = 1;
+                        cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64);
+
+                        sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port));
+                        sli_ctl_portx.s.inta_map = 0;
+                        sli_ctl_portx.s.intb_map = 0;
+                        sli_ctl_portx.s.intc_map = 0;
+                        sli_ctl_portx.s.intd_map = 0;
+                        cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64);
+                }
         }
 
         octeon_pci_dma_init();
 
         return 0;
 }
-
 arch_initcall(octeon_pcie_setup);
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
index c841f083a7f5..bb57ed9ea2bd 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
@@ -149,7 +149,7 @@ static int msp_hwbutton_register(struct hwbutton_interrupt *hirq)
                 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
         *CIC_EXT_CFG_REG = cic_ext;
 
-        return request_irq(hirq->irq, hwbutton_handler, IRQF_DISABLED,
+        return request_irq(hirq->irq, hwbutton_handler, 0,
                            hirq->name, hirq);
 }
 
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
index 655308a4e1cd..7a834b2f8a5f 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
@@ -209,7 +209,7 @@ void __init prom_init(void)
         default:
                 /* we don't recognize the machine */
                 mips_machtype  = MACH_UNKNOWN;
-                panic("***Bogosity factor five***, exiting\n");
+                panic("***Bogosity factor five***, exiting");
                 break;
         }
 
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
index bec17901ff03..10170580a2de 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_smp.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
@@ -51,13 +51,13 @@ static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
 
 static struct irqaction irq_resched = {
         .handler        = ipi_resched_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_PERCPU,
+        .flags          = IRQF_PERCPU,
         .name           = "IPI_resched"
 };
 
 static struct irqaction irq_call = {
         .handler        = ipi_call_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_PERCPU,
+        .flags          = IRQF_PERCPU,
         .name           = "IPI_call"
 };
 
diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
index 1ebe22bdadc8..ec684b8c3f79 100644
--- a/arch/mips/pnx8550/common/int.c
+++ b/arch/mips/pnx8550/common/int.c
@@ -167,13 +167,13 @@ static struct irq_chip level_irq_type = {
 
 static struct irqaction gic_action = {
         .handler =      no_action,
-        .flags =        IRQF_DISABLED | IRQF_NO_THREAD,
+        .flags =        IRQF_NO_THREAD,
         .name =         "GIC",
 };
 
 static struct irqaction timer_action = {
         .handler =      no_action,
-        .flags =        IRQF_DISABLED | IRQF_TIMER,
+        .flags =        IRQF_TIMER,
         .name =         "Timer",
 };
 
diff --git a/arch/mips/pnx8550/common/time.c b/arch/mips/pnx8550/common/time.c
index 8836c6203df0..831d6b369e9c 100644
--- a/arch/mips/pnx8550/common/time.c
+++ b/arch/mips/pnx8550/common/time.c
@@ -59,7 +59,7 @@ static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id)
 
 static struct irqaction pnx8xxx_timer_irq = {
         .handler        = pnx8xxx_timer_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
+        .flags          = IRQF_PERCPU | IRQF_TIMER,
         .name           = "pnx8xxx_timer",
 };
 
@@ -72,7 +72,7 @@ static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
 
 static struct irqaction monotonic_irqaction = {
         .handler = monotonic_interrupt,
-        .flags = IRQF_DISABLED | IRQF_TIMER,
+        .flags = IRQF_TIMER,
         .name = "Monotonic timer",
 };
 
diff --git a/arch/mips/sgi-ip22/Makefile b/arch/mips/sgi-ip22/Makefile
index cc538493cae1..411cda9ee030 100644
--- a/arch/mips/sgi-ip22/Makefile
+++ b/arch/mips/sgi-ip22/Makefile
@@ -4,7 +4,7 @@
 #
 
 obj-y   += ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \
-           ip22-platform.o ip22-reset.o ip22-setup.o
+           ip22-platform.o ip22-reset.o ip22-setup.o ip22-gio.o
 
 obj-$(CONFIG_SGI_IP22) += ip22-berr.o
 obj-$(CONFIG_SGI_IP28) += ip28-berr.o
diff --git a/arch/mips/sgi-ip22/ip22-gio.c b/arch/mips/sgi-ip22/ip22-gio.c
new file mode 100644
index 000000000000..f5ebc092aed5
--- /dev/null
+++ b/arch/mips/sgi-ip22/ip22-gio.c
@@ -0,0 +1,428 @@
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+
+#include <asm/addrspace.h>
+#include <asm/paccess.h>
+#include <asm/gio_device.h>
+#include <asm/sgi/gio.h>
+#include <asm/sgi/hpc3.h>
+#include <asm/sgi/mc.h>
+#include <asm/sgi/ip22.h>
+
+static struct bus_type gio_bus_type;
+
+static struct {
+        const char *name;
+        __u8       id;
+} gio_name_table[] = {
+        { .name = "SGI Impact", .id = 0x10 },
+        { .name = "Phobos G160", .id = 0x35 },
+        /* fake IDs */
+        { .name = "SGI Newport", .id = 0x7e },
+        { .name = "SGI GR2/GR3", .id = 0x7f },
+};
+
+static struct device gio_bus = {
+        .init_name = "gio",
+};
+
+/**
+ * gio_match_device - Tell if an of_device structure has a matching
+ * gio_match structure
+ * @ids: array of of device match structures to search in
+ * @dev: the of device structure to match against
+ *
+ * Used by a driver to check whether an of_device present in the
+ * system is in its list of supported devices.
+ */
+const struct gio_device_id *gio_match_device(const struct gio_device_id *match,
+                     const struct gio_device *dev)
+{
+        const struct gio_device_id *ids;
+
+        for (ids = match; ids->id != 0xff; ids++)
+                if (ids->id == dev->id.id)
+                        return ids;
+
+        return NULL;
+}
+EXPORT_SYMBOL_GPL(gio_match_device);
+
+struct gio_device *gio_dev_get(struct gio_device *dev)
+{
+        struct device *tmp;
+
+        if (!dev)
+                return NULL;
+        tmp = get_device(&dev->dev);
+        if (tmp)
+                return to_gio_device(tmp);
+        else
+                return NULL;
+}
+EXPORT_SYMBOL_GPL(gio_dev_get);
+
+void gio_dev_put(struct gio_device *dev)
+{
+        if (dev)
+                put_device(&dev->dev);
+}
+EXPORT_SYMBOL_GPL(gio_dev_put);
+
+/**
+ * gio_release_dev - free an gio device structure when all users of it are finished.
+ * @dev: device that's been disconnected
+ *
+ * Will be called only by the device core when all users of this gio device are
+ * done.
+ */
+void gio_release_dev(struct device *dev)
+{
+        struct gio_device *giodev;
+
+        giodev = to_gio_device(dev);
+        kfree(giodev);
+}
+EXPORT_SYMBOL_GPL(gio_release_dev);
+
+int gio_device_register(struct gio_device *giodev)
+{
+        giodev->dev.bus = &gio_bus_type;
+        giodev->dev.parent = &gio_bus;
+        return device_register(&giodev->dev);
+}
+EXPORT_SYMBOL_GPL(gio_device_register);
+
+void gio_device_unregister(struct gio_device *giodev)
+{
+        device_unregister(&giodev->dev);
+}
+EXPORT_SYMBOL_GPL(gio_device_unregister);
+
+static int gio_bus_match(struct device *dev, struct device_driver *drv)
+{
+        struct gio_device *gio_dev = to_gio_device(dev);
+        struct gio_driver *gio_drv = to_gio_driver(drv);
+
+        return gio_match_device(gio_drv->id_table, gio_dev) != NULL;
+}
+
+static int gio_device_probe(struct device *dev)
+{
+        int error = -ENODEV;
+        struct gio_driver *drv;
+        struct gio_device *gio_dev;
+        const struct gio_device_id *match;
+
+        drv = to_gio_driver(dev->driver);
+        gio_dev = to_gio_device(dev);
+
+        if (!drv->probe)
+                return error;
+
+        gio_dev_get(gio_dev);
+
+        match = gio_match_device(drv->id_table, gio_dev);
+        if (match)
+                error = drv->probe(gio_dev, match);
+        if (error)
+                gio_dev_put(gio_dev);
+
+        return error;
+}
+
+static int gio_device_remove(struct device *dev)
+{
+        struct gio_device *gio_dev = to_gio_device(dev);
+        struct gio_driver *drv = to_gio_driver(dev->driver);
+
+        if (dev->driver && drv->remove)
+                drv->remove(gio_dev);
+        return 0;
+}
+
+static int gio_device_suspend(struct device *dev, pm_message_t state)
+{
+        struct gio_device *gio_dev = to_gio_device(dev);
+        struct gio_driver *drv = to_gio_driver(dev->driver);
+        int error = 0;
+
+        if (dev->driver && drv->suspend)
+                error = drv->suspend(gio_dev, state);
+        return error;
+}
+
+static int gio_device_resume(struct device *dev)
+{
+        struct gio_device *gio_dev = to_gio_device(dev);
+        struct gio_driver *drv = to_gio_driver(dev->driver);
+        int error = 0;
+
+        if (dev->driver && drv->resume)
+                error = drv->resume(gio_dev);
+        return error;
+}
+
+static void gio_device_shutdown(struct device *dev)
+{
+        struct gio_device *gio_dev = to_gio_device(dev);
+        struct gio_driver *drv = to_gio_driver(dev->driver);
+
+        if (dev->driver && drv->shutdown)
+                drv->shutdown(gio_dev);
+}
+
+static ssize_t modalias_show(struct device *dev, struct device_attribute *a,
+                             char *buf)
+{
+        struct gio_device *gio_dev = to_gio_device(dev);
+        int len = snprintf(buf, PAGE_SIZE, "gio:%x\n", gio_dev->id.id);
+
+        return (len >= PAGE_SIZE) ? (PAGE_SIZE - 1) : len;
+}
+
+static ssize_t name_show(struct device *dev,
+                         struct device_attribute *attr, char *buf)
+{
+        struct gio_device *giodev;
+
+        giodev = to_gio_device(dev);
+        return sprintf(buf, "%s", giodev->name);
+}
+
+static ssize_t id_show(struct device *dev,
+                       struct device_attribute *attr, char *buf)
+{
+        struct gio_device *giodev;
+
+        giodev = to_gio_device(dev);
+        return sprintf(buf, "%x", giodev->id.id);
+}
+
+static struct device_attribute gio_dev_attrs[] = {
+        __ATTR_RO(modalias),
+        __ATTR_RO(name),
+        __ATTR_RO(id),
+        __ATTR_NULL,
+};
+
+static int gio_device_uevent(struct device *dev, struct kobj_uevent_env *env)
+{
+        struct gio_device *gio_dev = to_gio_device(dev);
+
+        add_uevent_var(env, "MODALIAS=gio:%x", gio_dev->id.id);
+        return 0;
+}
+
+int gio_register_driver(struct gio_driver *drv)
+{
+        /* initialize common driver fields */
+        if (!drv->driver.name)
+                drv->driver.name = drv->name;
+        if (!drv->driver.owner)
+                drv->driver.owner = drv->owner;
+        drv->driver.bus = &gio_bus_type;
+
+        /* register with core */
+        return driver_register(&drv->driver);
+}
+EXPORT_SYMBOL_GPL(gio_register_driver);
+
+void gio_unregister_driver(struct gio_driver *drv)
+{
+        driver_unregister(&drv->driver);
+}
+EXPORT_SYMBOL_GPL(gio_unregister_driver);
+
+void gio_set_master(struct gio_device *dev)
+{
+        u32 tmp = sgimc->giopar;
+
+        switch (dev->slotno) {
+        case 0:
+                tmp |= SGIMC_GIOPAR_MASTERGFX;
+                break;
+        case 1:
+                tmp |= SGIMC_GIOPAR_MASTEREXP0;
+                break;
+        case 2:
+                tmp |= SGIMC_GIOPAR_MASTEREXP1;
+                break;
+        }
+        sgimc->giopar = tmp;
+}
+EXPORT_SYMBOL_GPL(gio_set_master);
+
+void ip22_gio_set_64bit(int slotno)
+{
+        u32 tmp = sgimc->giopar;
+
+        switch (slotno) {
+        case 0:
+                tmp |= SGIMC_GIOPAR_GFX64;
+                break;
+        case 1:
+                tmp |= SGIMC_GIOPAR_EXP064;
+                break;
+        case 2:
+                tmp |= SGIMC_GIOPAR_EXP164;
+                break;
+        }
+        sgimc->giopar = tmp;
+}
+
+static int ip22_gio_id(unsigned long addr, u32 *res)
+{
+        u8 tmp8;
+        u8 tmp16;
+        u32 tmp32;
+        u8 *ptr8;
+        u16 *ptr16;
+        u32 *ptr32;
+
+        ptr32 = (void *)CKSEG1ADDR(addr);
+        if (!get_dbe(tmp32, ptr32)) {
+                /*
+                 * We got no DBE, but this doesn't mean anything.
+                 * If GIO is pipelined (which can't be disabled
+                 * for GFX slot) we don't get a DBE, but we see
+                 * the transfer size as data. So we do an 8bit
+                 * and a 16bit access and check whether the common
+                 * data matches
+                 */
+                ptr8 = (void *)CKSEG1ADDR(addr + 3);
+                get_dbe(tmp8, ptr8);
+                ptr16 = (void *)CKSEG1ADDR(addr + 2);
+                get_dbe(tmp16, ptr16);
+                if (tmp8 == (tmp16 & 0xff) &&
+                    tmp8 == (tmp32 & 0xff) &&
+                    tmp16 == (tmp32 & 0xffff)) {
+                        *res = tmp32;
+                        return 1;
+                }
+        }
+        return 0; /* nothing here */
+}
+
+#define HQ2_MYSTERY_OFFS       0x6A07C
+#define NEWPORT_USTATUS_OFFS   0xF133C
+
+static int ip22_is_gr2(unsigned long addr)
+{
+        u32 tmp;
+        u32 *ptr;
+
+        /* HQ2 only allows 32bit accesses */
+        ptr = (void *)CKSEG1ADDR(addr + HQ2_MYSTERY_OFFS);
+        if (!get_dbe(tmp, ptr)) {
+                if (tmp == 0xdeadbeef)
+                        return 1;
+        }
+        return 0;
+}
+
+
+static void ip22_check_gio(int slotno, unsigned long addr)
+{
+        const char *name = "Unknown";
+        struct gio_device *gio_dev;
+        u32 tmp;
+        __u8 id;
+        int i;
+
+        /* first look for GR2/GR3 by checking mystery register */
+        if (ip22_is_gr2(addr))
+                tmp = 0x7f;
+        else {
+                if (!ip22_gio_id(addr, &tmp)) {
+                        /*
+                         * no GIO signature at start address of slot, but
+                         * Newport doesn't have one, so let's check usea
+                         * status register
+                         */
+                        if (ip22_gio_id(addr + NEWPORT_USTATUS_OFFS, &tmp))
+                                tmp = 0x7e;
+                        else
+                                tmp = 0;
+                }
+        }
+        if (tmp) {
+                id = GIO_ID(tmp);
+                if (tmp & GIO_32BIT_ID) {
+                        if (tmp & GIO_64BIT_IFACE)
+                                ip22_gio_set_64bit(slotno);
+                }
+                for (i = 0; i < ARRAY_SIZE(gio_name_table); i++) {
+                        if (id == gio_name_table[i].id) {
+                                name = gio_name_table[i].name;
+                                break;
+                        }
+                }
+                printk(KERN_INFO "GIO: slot %d : %s (id %x)\n",
+                       slotno, name, id);
+                gio_dev = kzalloc(sizeof *gio_dev, GFP_KERNEL);
+                gio_dev->name = name;
+                gio_dev->slotno = slotno;
+                gio_dev->id.id = id;
+                gio_dev->resource.start = addr;
+                gio_dev->resource.end = addr + 0x3fffff;
+                gio_dev->resource.flags = IORESOURCE_MEM;
+                dev_set_name(&gio_dev->dev, "%d", slotno);
+                gio_device_register(gio_dev);
+        } else
+                printk(KERN_INFO "GIO: slot %d : Empty\n", slotno);
+}
+
+static struct bus_type gio_bus_type = {
+        .name      = "gio",
+        .dev_attrs = gio_dev_attrs,
+        .match     = gio_bus_match,
+        .probe     = gio_device_probe,
+        .remove    = gio_device_remove,
+        .suspend   = gio_device_suspend,
+        .resume    = gio_device_resume,
+        .shutdown  = gio_device_shutdown,
+        .uevent    = gio_device_uevent,
+};
+
+static struct resource gio_bus_resource = {
+        .start = GIO_SLOT_GFX_BASE,
+        .end   = GIO_SLOT_GFX_BASE + 0x9fffff,
+        .name  = "GIO Bus",
+        .flags = IORESOURCE_MEM,
+};
+
+int __init ip22_gio_init(void)
+{
+        unsigned int pbdma __maybe_unused;
+        int ret;
+
+        ret = device_register(&gio_bus);
+        if (ret)
+                return ret;
+
+        ret = bus_register(&gio_bus_type);
+        if (!ret) {
+                request_resource(&iomem_resource, &gio_bus_resource);
+                printk(KERN_INFO "GIO: Probing bus...\n");
+
+                if (ip22_is_fullhouse() ||
+                    !get_dbe(pbdma, (unsigned int *)&hpc3c1->pbdma[1])) {
+                        /* Indigo2 and ChallengeS */
+                        ip22_check_gio(0, GIO_SLOT_GFX_BASE);
+                        ip22_check_gio(1, GIO_SLOT_EXP0_BASE);
+                } else {
+                        /* Indy */
+                        ip22_check_gio(0, GIO_SLOT_GFX_BASE);
+                        ip22_check_gio(1, GIO_SLOT_EXP0_BASE);
+                        ip22_check_gio(2, GIO_SLOT_EXP1_BASE);
+                }
+        } else
+                device_unregister(&gio_bus);
+
+        return ret;
+}
+
+subsys_initcall(ip22_gio_init);
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index f72c336ea27b..3f2b7633f946 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -155,32 +155,32 @@ static void __irq_entry indy_buserror_irq(void)
 
 static struct irqaction local0_cascade = {
         .handler        = no_action,
-        .flags          = IRQF_DISABLED | IRQF_NO_THREAD,
+        .flags          = IRQF_NO_THREAD,
         .name           = "local0 cascade",
 };
 
 static struct irqaction local1_cascade = {
         .handler        = no_action,
-        .flags          = IRQF_DISABLED | IRQF_NO_THREAD,
+        .flags          = IRQF_NO_THREAD,
         .name           = "local1 cascade",
 };
 
 static struct irqaction buserr = {
         .handler        = no_action,
-        .flags          = IRQF_DISABLED | IRQF_NO_THREAD,
+        .flags          = IRQF_NO_THREAD,
         .name           = "Bus Error",
 };
 
 static struct irqaction map0_cascade = {
         .handler        = no_action,
-        .flags          = IRQF_DISABLED | IRQF_NO_THREAD,
+        .flags          = IRQF_NO_THREAD,
         .name           = "mapable0 cascade",
 };
 
 #ifdef USE_LIO3_IRQ
 static struct irqaction map1_cascade = {
         .handler        = no_action,
-        .flags          = IRQF_DISABLED | IRQF_NO_THREAD,
+        .flags          = IRQF_NO_THREAD,
         .name           = "mapable1 cascade",
 };
 #define SGI_INTERRUPTS  SGINT_END
diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c
index d22262ee6853..75ada8a9713b 100644
--- a/arch/mips/sgi-ip22/ip22-mc.c
+++ b/arch/mips/sgi-ip22/ip22-mc.c
@@ -139,11 +139,11 @@ void __init sgimc_init(void)
          *         zero.
          */
         /* don't touch parity settings for IP28 */
-#ifndef CONFIG_SGI_IP28
         tmp = sgimc->cpuctrl0;
-        tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM |
-                SGIMC_CCTRL0_R4KNOCHKPARR);
+#ifndef CONFIG_SGI_IP28
+        tmp |= SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM;
 #endif
+        tmp |= SGIMC_CCTRL0_R4KNOCHKPARR;
         sgimc->cpuctrl0 = tmp;
 
         /* Step 3: Setup the MC write buffer depth, this is controlled
@@ -178,7 +178,8 @@ void __init sgimc_init(void)
          */
 
         /* First the basic invariants across all GIO64 implementations. */
-        tmp = SGIMC_GIOPAR_HPC64;       /* All 1st HPC's interface at 64bits */
+        tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */
+        tmp |= SGIMC_GIOPAR_HPC64;      /* All 1st HPC's interface at 64bits */
         tmp |= SGIMC_GIOPAR_ONEBUS;     /* Only one physical GIO bus exists */
 
         if (ip22_is_fullhouse()) {
@@ -193,7 +194,6 @@ void __init sgimc_init(void)
                         tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp[01] pipelined */
                         tmp |= SGIMC_GIOPAR_PLINEEXP1;
                         tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
-                        tmp |= SGIMC_GIOPAR_GFX64;      /* GFX at 64 bits */
                 }
         } else {
                 /* Guiness specific settings. */
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index 5e6621349471..c7bdfe43df5b 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -26,9 +26,6 @@
 #include <asm/sgi/hpc3.h>
 #include <asm/sgi/ip22.h>
 
-unsigned long sgi_gfxaddr;
-EXPORT_SYMBOL_GPL(sgi_gfxaddr);
-
 extern void ip22_be_init(void) __init;
 
 void __init plat_mem_setup(void)
@@ -78,22 +75,4 @@ void __init plat_mem_setup(void)
                 prom_flags |= PROM_FLAG_USE_AS_CONSOLE;
                 add_preferred_console("arc", 0, NULL);
         }
-
-#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE)
-        {
-                ULONG *gfxinfo;
-                ULONG * (*__vec)(void) = (void *) (long)
-                        *((_PULONG *)(long)((PROMBLOCK)->pvector + 0x20));
-
-                gfxinfo = __vec();
-                sgi_gfxaddr = ((gfxinfo[1] >= 0xa0000000
-                               && gfxinfo[1] <= 0xc0000000)
-                               ? gfxinfo[1] - 0xa0000000 : 0);
-
-                /* newport addresses? */
-                if (sgi_gfxaddr == 0x1f0f0000 || sgi_gfxaddr == 0x1f4f0000) {
-                        conswitchp = &newport_con;
-                }
-        }
-#endif
 }
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index f90dce315e04..23642238c689 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -73,7 +73,7 @@ static inline int alloc_level(int cpu, int irq)
 
         level = find_first_zero_bit(hub->irq_alloc_mask, LEVELS_PER_SLICE);
         if (level >= LEVELS_PER_SLICE)
-                panic("Cpu %d flooded with devices\n", cpu);
+                panic("Cpu %d flooded with devices", cpu);
 
         __set_bit(level, hub->irq_alloc_mask);
         si->level_to_irq[level] = irq;
@@ -96,7 +96,7 @@ static inline int find_level(cpuid_t *cpunum, int irq)
                         }
         }
 
-        panic("Could not identify cpu/level for irq %d\n", irq);
+        panic("Could not identify cpu/level for irq %d", irq);
 }
 
 /*
@@ -116,7 +116,7 @@ static int ms1bit(unsigned long x)
 }
 
 /*
- * This code is unnecessarily complex, because we do IRQF_DISABLED
+ * This code is unnecessarily complex, because we do
  * intr enabling. Basically, once we grab the set of intrs we need
  * to service, we must mask _all_ these interrupts; firstly, to make
  * sure the same intr does not intr again, causing recursion that
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index ef74f3267f91..13cfeab50528 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -91,7 +91,7 @@ static irqreturn_t hub_rt_counter_handler(int irq, void *dev_id)
 
 struct irqaction hub_rt_irqaction = {
         .handler        = hub_rt_counter_handler,
-        .flags          = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
+        .flags          = IRQF_PERCPU | IRQF_TIMER,
         .name           = "hub-rt",
 };
 
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index c65ea76d56c7..a092860d5196 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -113,13 +113,11 @@ extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
 
 static struct irqaction memerr_irq = {
         .handler = crime_memerr_intr,
-        .flags = IRQF_DISABLED,
         .name = "CRIME memory error",
 };
 
 static struct irqaction cpuerr_irq = {
         .handler = crime_cpuerr_intr,
-        .flags = IRQF_DISABLED,
         .name = "CRIME CPU error",
 };
 
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index e8e72bb3a9af..5a4ec75382e2 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -42,7 +42,7 @@ static irqreturn_t sni_isa_irq_handler(int dummy, void *p)
 struct irqaction sni_isa_irq = {
         .handler = sni_isa_irq_handler,
         .name = "ISA",
-        .flags = IRQF_SHARED | IRQF_DISABLED
+        .flags = IRQF_SHARED
 };
 
 /*
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index ec0be14996a4..494c9e7847aa 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -68,7 +68,7 @@ static irqreturn_t a20r_interrupt(int irq, void *dev_id)
 
 static struct irqaction a20r_irqaction = {
         .handler        = a20r_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
+        .flags          = IRQF_PERCPU | IRQF_TIMER,
         .name           = "a20r-timer",
 };
 
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 85a87de17eb4..682efb0c108d 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -262,7 +262,7 @@ txx9_i8259_irq_setup(int irq)
         int err;
 
         init_i8259_irqs();
-        err = request_irq(irq, &i8259_interrupt, IRQF_DISABLED|IRQF_SHARED,
+        err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
                           "cascade(i8259)", (void *)(long)irq);
         if (!err)
                 printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq);
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a3afac4be734..cbe7a2fb779f 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -299,11 +299,11 @@ config I2C_AT91
           unless your system can cope with those limitations.
 
 config I2C_AU1550
-        tristate "Au1550/Au1200 SMBus interface"
+        tristate "Au1550/Au1200/Au1300 SMBus interface"
         depends on MIPS_ALCHEMY
         help
           If you say yes to this option, support will be included for the
-          Au1550 and Au1200 SMBus interface.
+          Au1550/Au1200/Au1300 SMBus interface.
 
           This driver can also be built as a module.  If so, the module
           will be called i2c-au1550.
diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c
index 5d3b9ae64523..dbd0c8a4e98a 100644
--- a/drivers/mmc/host/au1xmmc.c
+++ b/drivers/mmc/host/au1xmmc.c
@@ -153,6 +153,7 @@ static inline int has_dbdma(void)
 {
         switch (alchemy_get_cputype()) {
         case ALCHEMY_CPU_AU1200:
+        case ALCHEMY_CPU_AU1300:
                 return 1;
         default:
                 return 0;
@@ -768,11 +769,15 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
         config2 = au_readl(HOST_CONFIG2(host));
         switch (ios->bus_width) {
+        case MMC_BUS_WIDTH_8:
+                config2 |= SD_CONFIG2_BB;
+                break;
         case MMC_BUS_WIDTH_4:
+                config2 &= ~SD_CONFIG2_BB;
                 config2 |= SD_CONFIG2_WB;
                 break;
         case MMC_BUS_WIDTH_1:
-                config2 &= ~SD_CONFIG2_WB;
+                config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
                 break;
         }
         au_writel(config2, HOST_CONFIG2(host));
@@ -943,7 +948,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
         struct mmc_host *mmc;
         struct au1xmmc_host *host;
         struct resource *r;
-        int ret;
+        int ret, iflag;
 
         mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
         if (!mmc) {
@@ -982,37 +987,43 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
                 dev_err(&pdev->dev, "no IRQ defined\n");
                 goto out3;
         }
-
         host->irq = r->start;
-        /* IRQ is shared among both SD controllers */
-        ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
-                          DRIVER_NAME, host);
-        if (ret) {
-                dev_err(&pdev->dev, "cannot grab IRQ\n");
-                goto out3;
-        }
 
         mmc->ops = &au1xmmc_ops;
 
         mmc->f_min =   450000;
         mmc->f_max = 24000000;
 
+        mmc->max_blk_size = 2048;
+        mmc->max_blk_count = 512;
+
+        mmc->ocr_avail = AU1XMMC_OCR;
+        mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
+        mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
+
+        iflag = IRQF_SHARED;    /* Au1100/Au1200: one int for both ctrls */
+
         switch (alchemy_get_cputype()) {
         case ALCHEMY_CPU_AU1100:
                 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
-                mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
                 break;
         case ALCHEMY_CPU_AU1200:
                 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
-                mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
+                break;
+        case ALCHEMY_CPU_AU1300:
+                iflag = 0;      /* nothing is shared */
+                mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
+                mmc->f_max = 52000000;
+                if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
+                        mmc->caps |= MMC_CAP_8_BIT_DATA;
                 break;
         }
 
-        mmc->max_blk_size = 2048;
-        mmc->max_blk_count = 512;
-
-        mmc->ocr_avail = AU1XMMC_OCR;
-        mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
+        ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
+        if (ret) {
+                dev_err(&pdev->dev, "cannot grab IRQ\n");
+                goto out3;
+        }
 
         host->status = HOST_S_IDLE;
 
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c
index 7dd3700f2303..73abbc3e093e 100644
--- a/drivers/mtd/nand/au1550nd.c
+++ b/drivers/mtd/nand/au1550nd.c
@@ -17,35 +17,19 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
 #include <asm/io.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1550nd.h>
 
-#ifdef CONFIG_MIPS_PB1550
-#include <asm/mach-pb1x00/pb1550.h>
-#elif defined(CONFIG_MIPS_DB1550)
-#include <asm/mach-db1x00/db1x00.h>
-#endif
-#include <asm/mach-db1x00/bcsr.h>
 
-/*
- * MTD structure for NAND controller
- */
-static struct mtd_info *au1550_mtd = NULL;
-static void __iomem *p_nand;
-static int nand_width = 1;      /* default x8 */
-static void (*au1550_write_byte)(struct mtd_info *, u_char);
+struct au1550nd_ctx {
+        struct mtd_info info;
+        struct nand_chip chip;
 
-/*
- * Define partitions for flash device
- */
-static const struct mtd_partition partition_info[] = {
-        {
-         .name = "NAND FS 0",
-         .offset = 0,
-         .size = 8 * 1024 * 1024},
-        {
-         .name = "NAND FS 1",
-         .offset = MTDPART_OFS_APPEND,
-         .size = MTDPART_SIZ_FULL}
+        int cs;
+        void __iomem *base;
+        void (*write_byte)(struct mtd_info *, u_char);
 };
 
 /**
@@ -259,24 +243,25 @@ static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
 
 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
 {
-        register struct nand_chip *this = mtd->priv;
+        struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
+        struct nand_chip *this = mtd->priv;
 
         switch (cmd) {
 
         case NAND_CTL_SETCLE:
-                this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
+                this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
                 break;
 
         case NAND_CTL_CLRCLE:
-                this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
+                this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
                 break;
 
         case NAND_CTL_SETALE:
-                this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
+                this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
                 break;
 
         case NAND_CTL_CLRALE:
-                this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
+                this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
                 /* FIXME: Nobody knows why this is necessary,
                  * but it works only that way */
                 udelay(1);
@@ -284,7 +269,7 @@ static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
 
         case NAND_CTL_SETNCE:
                 /* assert (force assert) chip enable */
-                au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
+                au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL);
                 break;
 
         case NAND_CTL_CLRNCE:
@@ -331,9 +316,10 @@ static void au1550_select_chip(struct mtd_info *mtd, int chip)
  */
 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
 {
-        register struct nand_chip *this = mtd->priv;
+        struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
+        struct nand_chip *this = mtd->priv;
         int ce_override = 0, i;
-        ulong flags;
+        unsigned long flags = 0;
 
         /* Begin command latch cycle */
         au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
@@ -354,9 +340,9 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
                         column -= 256;
                         readcmd = NAND_CMD_READ1;
                 }
-                au1550_write_byte(mtd, readcmd);
+                ctx->write_byte(mtd, readcmd);
         }
-        au1550_write_byte(mtd, command);
+        ctx->write_byte(mtd, command);
 
         /* Set ALE and clear CLE to start address cycle */
         au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
@@ -369,10 +355,10 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
                         /* Adjust columns for 16 bit buswidth */
                         if (this->options & NAND_BUSWIDTH_16)
                                 column >>= 1;
-                        au1550_write_byte(mtd, column);
+                        ctx->write_byte(mtd, column);
                 }
                 if (page_addr != -1) {
-                        au1550_write_byte(mtd, (u8)(page_addr & 0xff));
+                        ctx->write_byte(mtd, (u8)(page_addr & 0xff));
 
                         if (command == NAND_CMD_READ0 ||
                             command == NAND_CMD_READ1 ||
@@ -390,11 +376,12 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
                                 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
                         }
 
-                        au1550_write_byte(mtd, (u8)(page_addr >> 8));
+                        ctx->write_byte(mtd, (u8)(page_addr >> 8));
 
                         /* One more address cycle for devices > 32MiB */
                         if (this->chipsize > (32 << 20))
-                                au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
+                                ctx->write_byte(mtd,
+                                                ((page_addr >> 16) & 0x0f));
                 }
                 /* Latch in address */
                 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
@@ -440,121 +427,79 @@ static void au1550_command(struct mtd_info *mtd, unsigned command, int column, i
         while(!this->dev_ready(mtd));
 }
 
-
-/*
- * Main initialization routine
- */
-static int __init au1xxx_nand_init(void)
+static int __devinit find_nand_cs(unsigned long nand_base)
 {
-        struct nand_chip *this;
-        u16 boot_swapboot = 0;  /* default value */
-        int retval;
-        u32 mem_staddr;
-        u32 nand_phys;
-
-        /* Allocate memory for MTD device structure and private data */
-        au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
-        if (!au1550_mtd) {
-                printk("Unable to allocate NAND MTD dev structure.\n");
-                return -ENOMEM;
-        }
-
-        /* Get pointer to private data */
-        this = (struct nand_chip *)(&au1550_mtd[1]);
-
-        /* Link the private data with the MTD structure */
-        au1550_mtd->priv = this;
-        au1550_mtd->owner = THIS_MODULE;
-
+        void __iomem *base =
+                        (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
+        unsigned long addr, staddr, start, mask, end;
+        int i;
 
-        /* MEM_STNDCTL: disable ints, disable nand boot */
-        au_writel(0, MEM_STNDCTL);
+        for (i = 0; i < 4; i++) {
+                addr = 0x1000 + (i * 0x10);                     /* CSx */
+                staddr = __raw_readl(base + addr + 0x08);       /* STADDRx */
+                /* figure out the decoded range of this CS */
+                start = (staddr << 4) & 0xfffc0000;
+                mask = (staddr << 18) & 0xfffc0000;
+                end = (start | (start - 1)) & ~(start ^ mask);
+                if ((nand_base >= start) && (nand_base < end))
+                        return i;
+        }
 
-#ifdef CONFIG_MIPS_PB1550
-        /* set gpio206 high */
-        gpio_direction_input(206);
+        return -ENODEV;
+}
 
-        boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
+static int __devinit au1550nd_probe(struct platform_device *pdev)
+{
+        struct au1550nd_platdata *pd;
+        struct au1550nd_ctx *ctx;
+        struct nand_chip *this;
+        struct resource *r;
+        int ret, cs;
 
-        switch (boot_swapboot) {
-        case 0:
-        case 2:
-        case 8:
-        case 0xC:
-        case 0xD:
-                /* x16 NAND Flash */
-                nand_width = 0;
-                break;
-        case 1:
-        case 9:
-        case 3:
-        case 0xE:
-        case 0xF:
-                /* x8 NAND Flash */
-                nand_width = 1;
-                break;
-        default:
-                printk("Pb1550 NAND: bad boot:swap\n");
-                retval = -EINVAL;
-                goto outmem;
+        pd = pdev->dev.platform_data;
+        if (!pd) {
+                dev_err(&pdev->dev, "missing platform data\n");
+                return -ENODEV;
         }
-#endif
-
-        /* Configure chip-select; normally done by boot code, e.g. YAMON */
-#ifdef NAND_STCFG
-        if (NAND_CS == 0) {
-                au_writel(NAND_STCFG,  MEM_STCFG0);
-                au_writel(NAND_STTIME, MEM_STTIME0);
-                au_writel(NAND_STADDR, MEM_STADDR0);
-        }
-        if (NAND_CS == 1) {
-                au_writel(NAND_STCFG,  MEM_STCFG1);
-                au_writel(NAND_STTIME, MEM_STTIME1);
-                au_writel(NAND_STADDR, MEM_STADDR1);
+
+        ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+        if (!ctx) {
+                dev_err(&pdev->dev, "no memory for NAND context\n");
+                return -ENOMEM;
         }
-        if (NAND_CS == 2) {
-                au_writel(NAND_STCFG,  MEM_STCFG2);
-                au_writel(NAND_STTIME, MEM_STTIME2);
-                au_writel(NAND_STADDR, MEM_STADDR2);
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!r) {
+                dev_err(&pdev->dev, "no NAND memory resource\n");
+                ret = -ENODEV;
+                goto out1;
         }
-        if (NAND_CS == 3) {
-                au_writel(NAND_STCFG,  MEM_STCFG3);
-                au_writel(NAND_STTIME, MEM_STTIME3);
-                au_writel(NAND_STADDR, MEM_STADDR3);
+        if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
+                dev_err(&pdev->dev, "cannot claim NAND memory area\n");
+                ret = -ENOMEM;
+                goto out1;
         }
-#endif
-
-        /* Locate NAND chip-select in order to determine NAND phys address */
-        mem_staddr = 0x00000000;
-        if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
-                mem_staddr = au_readl(MEM_STADDR0);
-        else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
-                mem_staddr = au_readl(MEM_STADDR1);
-        else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
-                mem_staddr = au_readl(MEM_STADDR2);
-        else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
-                mem_staddr = au_readl(MEM_STADDR3);
-
-        if (mem_staddr == 0x00000000) {
-                printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
-                kfree(au1550_mtd);
-                return 1;
+
+        ctx->base = ioremap_nocache(r->start, 0x1000);
+        if (!ctx->base) {
+                dev_err(&pdev->dev, "cannot remap NAND memory area\n");
+                ret = -ENODEV;
+                goto out2;
         }
-        nand_phys = (mem_staddr << 4) & 0xFFFC0000;
 
-        p_nand = ioremap(nand_phys, 0x1000);
+        this = &ctx->chip;
+        ctx->info.priv = this;
+        ctx->info.owner = THIS_MODULE;
 
-        /* make controller and MTD agree */
-        if (NAND_CS == 0)
-                nand_width = au_readl(MEM_STCFG0) & (1 << 22);
-        if (NAND_CS == 1)
-                nand_width = au_readl(MEM_STCFG1) & (1 << 22);
-        if (NAND_CS == 2)
-                nand_width = au_readl(MEM_STCFG2) & (1 << 22);
-        if (NAND_CS == 3)
-                nand_width = au_readl(MEM_STCFG3) & (1 << 22);
+        /* figure out which CS# r->start belongs to */
+        cs = find_nand_cs(r->start);
+        if (cs < 0) {
+                dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
+                ret = -ENODEV;
+                goto out3;
+        }
+        ctx->cs = cs;
 
-        /* Set address of hardware control function */
         this->dev_ready = au1550_device_ready;
         this->select_chip = au1550_select_chip;
         this->cmdfunc = au1550_command;
@@ -565,54 +510,57 @@ static int __init au1xxx_nand_init(void)
 
         this->options = NAND_NO_AUTOINCR;
 
-        if (!nand_width)
+        if (pd->devwidth)
                 this->options |= NAND_BUSWIDTH_16;
 
-        this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
-        au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
+        this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
+        ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
         this->read_word = au_read_word;
-        this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
-        this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
-        this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
-
-        /* Scan to find existence of the device */
-        if (nand_scan(au1550_mtd, 1)) {
-                retval = -ENXIO;
-                goto outio;
+        this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
+        this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
+        this->verify_buf = (pd->devwidth) ? au_verify_buf16 : au_verify_buf;
+
+        ret = nand_scan(&ctx->info, 1);
+        if (ret) {
+                dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
+                goto out3;
         }
 
-        /* Register the partitions */
-        mtd_device_register(au1550_mtd, partition_info,
-                            ARRAY_SIZE(partition_info));
+        mtd_device_register(&ctx->info, pd->parts, pd->num_parts);
 
         return 0;
 
- outio:
-        iounmap(p_nand);
-
- outmem:
-        kfree(au1550_mtd);
-        return retval;
+out3:
+        iounmap(ctx->base);
+out2:
+        release_mem_region(r->start, resource_size(r));
+out1:
+        kfree(ctx);
+        return ret;
 }
 
-module_init(au1xxx_nand_init);
-
-/*
- * Clean up routine
- */
-static void __exit au1550_cleanup(void)
+static int __devexit au1550nd_remove(struct platform_device *pdev)
 {
-        /* Release resources, unregister device */
-        nand_release(au1550_mtd);
+        struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
+        struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
-        /* Free the MTD device structure */
-        kfree(au1550_mtd);
-
-        /* Unmap */
-        iounmap(p_nand);
+        nand_release(&ctx->info);
+        iounmap(ctx->base);
+        release_mem_region(r->start, 0x1000);
+        kfree(ctx);
+        return 0;
 }
 
-module_exit(au1550_cleanup);
+static struct platform_driver au1550nd_driver = {
+        .driver = {
+                .name   = "au1550-nand",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = au1550nd_probe,
+        .remove         = __devexit_p(au1550nd_remove),
+};
+
+module_platform_driver(au1550nd_driver);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Embedded Edge, LLC");
diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig
index d423d18b4ad6..e535137eb2d0 100644
--- a/drivers/net/irda/Kconfig
+++ b/drivers/net/irda/Kconfig
@@ -313,8 +313,12 @@ config TOSHIBA_FIR
           donauboe.
 
 config AU1000_FIR
-        tristate "Alchemy Au1000 SIR/FIR"
+        tristate "Alchemy IrDA SIR/FIR"
         depends on IRDA && MIPS_ALCHEMY
+        help
+          Say Y/M here to build suppor the the IrDA peripheral on the
+          Alchemy Au1000 and Au1100 SoCs.
+          Say M to build a module; it will be called au1k_ir.ko
 
 config SMC_IRCC_FIR
         tristate "SMSC IrCC (EXPERIMENTAL)"
diff --git a/drivers/net/irda/au1000_ircc.h b/drivers/net/irda/au1000_ircc.h
deleted file mode 100644
index c072c09a8d91..000000000000
--- a/drivers/net/irda/au1000_ircc.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      Au1000 IrDA driver.
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef AU1000_IRCC_H
-#define AU1000_IRCC_H
-
-#include <linux/time.h>
-
-#include <linux/spinlock.h>
-#include <linux/pm.h>
-#include <asm/io.h>
-
-#define NUM_IR_IFF          1
-#define NUM_IR_DESC        64
-#define RING_SIZE_4       0x0
-#define RING_SIZE_16      0x3
-#define RING_SIZE_64      0xF
-#define MAX_NUM_IR_DESC    64
-#define MAX_BUF_SIZE     2048
-
-#define BPS_115200          0
-#define BPS_57600           1
-#define BPS_38400           2
-#define BPS_19200           5
-#define BPS_9600           11
-#define BPS_2400           47
-
-/* Ring descriptor flags */
-#define AU_OWN           (1<<7) /* tx,rx */
-
-#define IR_DIS_CRC       (1<<6) /* tx */
-#define IR_BAD_CRC       (1<<5) /* tx */
-#define IR_NEED_PULSE    (1<<4) /* tx */
-#define IR_FORCE_UNDER   (1<<3) /* tx */
-#define IR_DISABLE_TX    (1<<2) /* tx */
-#define IR_HW_UNDER      (1<<0) /* tx */
-#define IR_TX_ERROR      (IR_DIS_CRC|IR_BAD_CRC|IR_HW_UNDER)
-
-#define IR_PHY_ERROR     (1<<6) /* rx */
-#define IR_CRC_ERROR     (1<<5) /* rx */
-#define IR_MAX_LEN       (1<<4) /* rx */
-#define IR_FIFO_OVER     (1<<3) /* rx */
-#define IR_SIR_ERROR     (1<<2) /* rx */
-#define IR_RX_ERROR      (IR_PHY_ERROR|IR_CRC_ERROR| \
-                IR_MAX_LEN|IR_FIFO_OVER|IR_SIR_ERROR)
-
-typedef struct db_dest {
-        struct db_dest *pnext;
-        volatile u32 *vaddr;
-        dma_addr_t dma_addr;
-} db_dest_t;
-
-
-typedef struct ring_desc {
-        u8 count_0;               /* 7:0  */
-        u8 count_1;               /* 12:8 */
-        u8 reserved;
-        u8 flags;
-        u8 addr_0;                /* 7:0   */
-        u8 addr_1;                /* 15:8  */
-        u8 addr_2;                /* 23:16 */
-        u8 addr_3;                /* 31:24 */
-} ring_dest_t;
-
-
-/* Private data for each instance */
-struct au1k_private {
-
-        db_dest_t *pDBfree;
-        db_dest_t db[2*NUM_IR_DESC];
-        volatile ring_dest_t *rx_ring[NUM_IR_DESC];
-        volatile ring_dest_t *tx_ring[NUM_IR_DESC];
-        db_dest_t *rx_db_inuse[NUM_IR_DESC];
-        db_dest_t *tx_db_inuse[NUM_IR_DESC];
-        u32 rx_head;
-        u32 tx_head;
-        u32 tx_tail;
-        u32 tx_full;
-
-        iobuff_t rx_buff;
-
-        struct net_device *netdev;
-        
-        struct timeval stamp;
-        struct timeval now;
-        struct qos_info         qos;
-        struct irlap_cb         *irlap;
-        
-        u8 open;
-        u32 speed;
-        u32 newspeed;
-        
-        u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */
-        struct timer_list timer;
-
-        spinlock_t lock;           /* For serializing operations */
-};
-#endif /* AU1000_IRCC_H */
diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c
index a3d696a9456a..fc503aa5288e 100644
--- a/drivers/net/irda/au1k_ir.c
+++ b/drivers/net/irda/au1k_ir.c
@@ -18,104 +18,220 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  */
-#include <linux/module.h>
-#include <linux/types.h>
+
 #include <linux/init.h>
-#include <linux/errno.h>
+#include <linux/module.h>
 #include <linux/netdevice.h>
-#include <linux/slab.h>
-#include <linux/rtnetlink.h>
 #include <linux/interrupt.h>
-#include <linux/pm.h>
-#include <linux/bitops.h>
-
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/au1000.h>
-#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100)
-#include <asm/pb1000.h>
-#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
-#include <asm/db1x00.h>
-#include <asm/mach-db1x00/bcsr.h>
-#else 
-#error au1k_ir: unsupported board
-#endif
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/time.h>
+#include <linux/types.h>
 
 #include <net/irda/irda.h>
 #include <net/irda/irmod.h>
 #include <net/irda/wrapper.h>
 #include <net/irda/irda_device.h>
-#include "au1000_ircc.h"
+#include <asm/mach-au1x00/au1000.h>
+
+/* registers */
+#define IR_RING_PTR_STATUS      0x00
+#define IR_RING_BASE_ADDR_H     0x04
+#define IR_RING_BASE_ADDR_L     0x08
+#define IR_RING_SIZE            0x0C
+#define IR_RING_PROMPT          0x10
+#define IR_RING_ADDR_CMPR       0x14
+#define IR_INT_CLEAR            0x18
+#define IR_CONFIG_1             0x20
+#define IR_SIR_FLAGS            0x24
+#define IR_STATUS               0x28
+#define IR_READ_PHY_CONFIG      0x2C
+#define IR_WRITE_PHY_CONFIG     0x30
+#define IR_MAX_PKT_LEN          0x34
+#define IR_RX_BYTE_CNT          0x38
+#define IR_CONFIG_2             0x3C
+#define IR_ENABLE               0x40
+
+/* Config1 */
+#define IR_RX_INVERT_LED        (1 << 0)
+#define IR_TX_INVERT_LED        (1 << 1)
+#define IR_ST                   (1 << 2)
+#define IR_SF                   (1 << 3)
+#define IR_SIR                  (1 << 4)
+#define IR_MIR                  (1 << 5)
+#define IR_FIR                  (1 << 6)
+#define IR_16CRC                (1 << 7)
+#define IR_TD                   (1 << 8)
+#define IR_RX_ALL               (1 << 9)
+#define IR_DMA_ENABLE           (1 << 10)
+#define IR_RX_ENABLE            (1 << 11)
+#define IR_TX_ENABLE            (1 << 12)
+#define IR_LOOPBACK             (1 << 14)
+#define IR_SIR_MODE             (IR_SIR | IR_DMA_ENABLE | \
+                                 IR_RX_ALL | IR_RX_ENABLE | IR_SF | \
+                                 IR_16CRC)
+
+/* ir_status */
+#define IR_RX_STATUS            (1 << 9)
+#define IR_TX_STATUS            (1 << 10)
+#define IR_PHYEN                (1 << 15)
+
+/* ir_write_phy_config */
+#define IR_BR(x)                (((x) & 0x3f) << 10)    /* baud rate */
+#define IR_PW(x)                (((x) & 0x1f) << 5)     /* pulse width */
+#define IR_P(x)                 ((x) & 0x1f)            /* preamble bits */
+
+/* Config2 */
+#define IR_MODE_INV             (1 << 0)
+#define IR_ONE_PIN              (1 << 1)
+#define IR_PHYCLK_40MHZ         (0 << 2)
+#define IR_PHYCLK_48MHZ         (1 << 2)
+#define IR_PHYCLK_56MHZ         (2 << 2)
+#define IR_PHYCLK_64MHZ         (3 << 2)
+#define IR_DP                   (1 << 4)
+#define IR_DA                   (1 << 5)
+#define IR_FLT_HIGH             (0 << 6)
+#define IR_FLT_MEDHI            (1 << 6)
+#define IR_FLT_MEDLO            (2 << 6)
+#define IR_FLT_LO               (3 << 6)
+#define IR_IEN                  (1 << 8)
+
+/* ir_enable */
+#define IR_HC                   (1 << 3)        /* divide SBUS clock by 2 */
+#define IR_CE                   (1 << 2)        /* clock enable */
+#define IR_C                    (1 << 1)        /* coherency bit */
+#define IR_BE                   (1 << 0)        /* set in big endian mode */
+
+#define NUM_IR_DESC     64
+#define RING_SIZE_4     0x0
+#define RING_SIZE_16    0x3
+#define RING_SIZE_64    0xF
+#define MAX_NUM_IR_DESC 64
+#define MAX_BUF_SIZE    2048
+
+/* Ring descriptor flags */
+#define AU_OWN          (1 << 7) /* tx,rx */
+#define IR_DIS_CRC      (1 << 6) /* tx */
+#define IR_BAD_CRC      (1 << 5) /* tx */
+#define IR_NEED_PULSE   (1 << 4) /* tx */
+#define IR_FORCE_UNDER  (1 << 3) /* tx */
+#define IR_DISABLE_TX   (1 << 2) /* tx */
+#define IR_HW_UNDER     (1 << 0) /* tx */
+#define IR_TX_ERROR     (IR_DIS_CRC | IR_BAD_CRC | IR_HW_UNDER)
+
+#define IR_PHY_ERROR    (1 << 6) /* rx */
+#define IR_CRC_ERROR    (1 << 5) /* rx */
+#define IR_MAX_LEN      (1 << 4) /* rx */
+#define IR_FIFO_OVER    (1 << 3) /* rx */
+#define IR_SIR_ERROR    (1 << 2) /* rx */
+#define IR_RX_ERROR     (IR_PHY_ERROR | IR_CRC_ERROR | \
+                         IR_MAX_LEN | IR_FIFO_OVER | IR_SIR_ERROR)
+
+struct db_dest {
+        struct db_dest *pnext;
+        volatile u32 *vaddr;
+        dma_addr_t dma_addr;
+};
 
-static int au1k_irda_net_init(struct net_device *);
-static int au1k_irda_start(struct net_device *);
-static int au1k_irda_stop(struct net_device *dev);
-static int au1k_irda_hard_xmit(struct sk_buff *, struct net_device *);
-static int au1k_irda_rx(struct net_device *);
-static void au1k_irda_interrupt(int, void *);
-static void au1k_tx_timeout(struct net_device *);
-static int au1k_irda_ioctl(struct net_device *, struct ifreq *, int);
-static int au1k_irda_set_speed(struct net_device *dev, int speed);
+struct ring_dest {
+        u8 count_0;     /* 7:0  */
+        u8 count_1;     /* 12:8 */
+        u8 reserved;
+        u8 flags;
+        u8 addr_0;      /* 7:0   */
+        u8 addr_1;      /* 15:8  */
+        u8 addr_2;      /* 23:16 */
+        u8 addr_3;      /* 31:24 */
+};
 
-static void *dma_alloc(size_t, dma_addr_t *);
-static void dma_free(void *, size_t);
+/* Private data for each instance */
+struct au1k_private {
+        void __iomem *iobase;
+        int irq_rx, irq_tx;
+
+        struct db_dest *pDBfree;
+        struct db_dest db[2 * NUM_IR_DESC];
+        volatile struct ring_dest *rx_ring[NUM_IR_DESC];
+        volatile struct ring_dest *tx_ring[NUM_IR_DESC];
+        struct db_dest *rx_db_inuse[NUM_IR_DESC];
+        struct db_dest *tx_db_inuse[NUM_IR_DESC];
+        u32 rx_head;
+        u32 tx_head;
+        u32 tx_tail;
+        u32 tx_full;
+
+        iobuff_t rx_buff;
+
+        struct net_device *netdev;
+        struct timeval stamp;
+        struct timeval now;
+        struct qos_info qos;
+        struct irlap_cb *irlap;
+
+        u8 open;
+        u32 speed;
+        u32 newspeed;
+
+        struct timer_list timer;
+
+        struct resource *ioarea;
+        struct au1k_irda_platform_data *platdata;
+};
 
 static int qos_mtt_bits = 0x07;  /* 1 ms or more */
-static struct net_device *ir_devs[NUM_IR_IFF];
-static char version[] __devinitdata =
-    "au1k_ircc:1.2 ppopov@mvista.com\n";
 
 #define RUN_AT(x) (jiffies + (x))
 
-static DEFINE_SPINLOCK(ir_lock);
+static void au1k_irda_plat_set_phy_mode(struct au1k_private *p, int mode)
+{
+        if (p->platdata && p->platdata->set_phy_mode)
+                p->platdata->set_phy_mode(mode);
+}
 
-/*
- * IrDA peripheral bug. You have to read the register
- * twice to get the right value.
- */
-u32 read_ir_reg(u32 addr) 
-{ 
-        readl(addr);
-        return readl(addr);
+static inline unsigned long irda_read(struct au1k_private *p,
+                                      unsigned long ofs)
+{
+        /*
+        * IrDA peripheral bug. You have to read the register
+        * twice to get the right value.
+        */
+        (void)__raw_readl(p->iobase + ofs);
+        return __raw_readl(p->iobase + ofs);
 }
 
+static inline void irda_write(struct au1k_private *p, unsigned long ofs,
+                              unsigned long val)
+{
+        __raw_writel(val, p->iobase + ofs);
+        wmb();
+}
 
 /*
  * Buffer allocation/deallocation routines. The buffer descriptor returned
- * has the virtual and dma address of a buffer suitable for 
+ * has the virtual and dma address of a buffer suitable for
  * both, receive and transmit operations.
  */
-static db_dest_t *GetFreeDB(struct au1k_private *aup)
+static struct db_dest *GetFreeDB(struct au1k_private *aup)
 {
-        db_dest_t *pDB;
-        pDB = aup->pDBfree;
-
-        if (pDB) {
-                aup->pDBfree = pDB->pnext;
-        }
-        return pDB;
-}
+        struct db_dest *db;
+        db = aup->pDBfree;
 
-static void ReleaseDB(struct au1k_private *aup, db_dest_t *pDB)
-{
-        db_dest_t *pDBfree = aup->pDBfree;
-        if (pDBfree)
-                pDBfree->pnext = pDB;
-        aup->pDBfree = pDB;
+        if (db)
+                aup->pDBfree = db->pnext;
+        return db;
 }
 
-
 /*
   DMA memory allocation, derived from pci_alloc_consistent.
   However, the Au1000 data cache is coherent (when programmed
   so), therefore we return KSEG0 address, not KSEG1.
 */
-static void *dma_alloc(size_t size, dma_addr_t * dma_handle)
+static void *dma_alloc(size_t size, dma_addr_t *dma_handle)
 {
         void *ret;
         int gfp = GFP_ATOMIC | GFP_DMA;
 
-        ret = (void *) __get_free_pages(gfp, get_order(size));
+        ret = (void *)__get_free_pages(gfp, get_order(size));
 
         if (ret != NULL) {
                 memset(ret, 0, size);
@@ -125,7 +241,6 @@ static void *dma_alloc(size_t size, dma_addr_t * dma_handle)
         return ret;
 }
 
-
 static void dma_free(void *vaddr, size_t size)
 {
         vaddr = (void *)KSEG0ADDR(vaddr);
@@ -133,206 +248,306 @@ static void dma_free(void *vaddr, size_t size)
 }
 
 
-static void 
-setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base)
+static void setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base)
 {
         int i;
-        for (i=0; i<NUM_IR_DESC; i++) {
-                aup->rx_ring[i] = (volatile ring_dest_t *) 
-                        (rx_base + sizeof(ring_dest_t)*i);
+        for (i = 0; i < NUM_IR_DESC; i++) {
+                aup->rx_ring[i] = (volatile struct ring_dest *)
+                        (rx_base + sizeof(struct ring_dest) * i);
         }
-        for (i=0; i<NUM_IR_DESC; i++) {
-                aup->tx_ring[i] = (volatile ring_dest_t *) 
-                        (tx_base + sizeof(ring_dest_t)*i);
+        for (i = 0; i < NUM_IR_DESC; i++) {
+                aup->tx_ring[i] = (volatile struct ring_dest *)
+                        (tx_base + sizeof(struct ring_dest) * i);
         }
 }
 
-static int au1k_irda_init(void)
-{
-        static unsigned version_printed = 0;
-        struct au1k_private *aup;
-        struct net_device *dev;
-        int err;
-
-        if (version_printed++ == 0) printk(version);
-
-        dev = alloc_irdadev(sizeof(struct au1k_private));
-        if (!dev)
-                return -ENOMEM;
-
-        dev->irq = AU1000_IRDA_RX_INT; /* TX has its own interrupt */
-        err = au1k_irda_net_init(dev);
-        if (err)
-                goto out;
-        err = register_netdev(dev);
-        if (err)
-                goto out1;
-        ir_devs[0] = dev;
-        printk(KERN_INFO "IrDA: Registered device %s\n", dev->name);
-        return 0;
-
-out1:
-        aup = netdev_priv(dev);
-        dma_free((void *)aup->db[0].vaddr,
-                MAX_BUF_SIZE * 2*NUM_IR_DESC);
-        dma_free((void *)aup->rx_ring[0],
-                2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t)));
-        kfree(aup->rx_buff.head);
-out:
-        free_netdev(dev);
-        return err;
-}
-
 static int au1k_irda_init_iobuf(iobuff_t *io, int size)
 {
         io->head = kmalloc(size, GFP_KERNEL);
         if (io->head != NULL) {
-                io->truesize = size;
-                io->in_frame = FALSE;
-                io->state    = OUTSIDE_FRAME;
-                io->data     = io->head;
+                io->truesize    = size;
+                io->in_frame    = FALSE;
+                io->state       = OUTSIDE_FRAME;
+                io->data        = io->head;
         }
         return io->head ? 0 : -ENOMEM;
 }
 
-static const struct net_device_ops au1k_irda_netdev_ops = {
-        .ndo_open               = au1k_irda_start,
-        .ndo_stop               = au1k_irda_stop,
-        .ndo_start_xmit         = au1k_irda_hard_xmit,
-        .ndo_tx_timeout         = au1k_tx_timeout,
-        .ndo_do_ioctl           = au1k_irda_ioctl,
-};
-
-static int au1k_irda_net_init(struct net_device *dev)
+/*
+ * Set the IrDA communications speed.
+ */
+static int au1k_irda_set_speed(struct net_device *dev, int speed)
 {
         struct au1k_private *aup = netdev_priv(dev);
-        int i, retval = 0, err;
-        db_dest_t *pDB, *pDBfree;
-        dma_addr_t temp;
+        volatile struct ring_dest *ptxd;
+        unsigned long control;
+        int ret = 0, timeout = 10, i;
 
-        err = au1k_irda_init_iobuf(&aup->rx_buff, 14384);
-        if (err)
-                goto out1;
+        if (speed == aup->speed)
+                return ret;
 
-        dev->netdev_ops = &au1k_irda_netdev_ops;
+        /* disable PHY first */
+        au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
+        irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN);
 
-        irda_init_max_qos_capabilies(&aup->qos);
+        /* disable RX/TX */
+        irda_write(aup, IR_CONFIG_1,
+            irda_read(aup, IR_CONFIG_1) & ~(IR_RX_ENABLE | IR_TX_ENABLE));
+        msleep(20);
+        while (irda_read(aup, IR_STATUS) & (IR_RX_STATUS | IR_TX_STATUS)) {
+                msleep(20);
+                if (!timeout--) {
+                        printk(KERN_ERR "%s: rx/tx disable timeout\n",
+                                        dev->name);
+                        break;
+                }
+        }
 
-        /* The only value we must override it the baudrate */
-        aup->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
-                IR_115200|IR_576000 |(IR_4000000 << 8);
-        
-        aup->qos.min_turn_time.bits = qos_mtt_bits;
-        irda_qos_bits_to_value(&aup->qos);
+        /* disable DMA */
+        irda_write(aup, IR_CONFIG_1,
+                   irda_read(aup, IR_CONFIG_1) & ~IR_DMA_ENABLE);
+        msleep(20);
 
-        retval = -ENOMEM;
+        /* After we disable tx/rx. the index pointers go back to zero. */
+        aup->tx_head = aup->tx_tail = aup->rx_head = 0;
+        for (i = 0; i < NUM_IR_DESC; i++) {
+                ptxd = aup->tx_ring[i];
+                ptxd->flags = 0;
+                ptxd->count_0 = 0;
+                ptxd->count_1 = 0;
+        }
 
-        /* Tx ring follows rx ring + 512 bytes */
-        /* we need a 1k aligned buffer */
-        aup->rx_ring[0] = (ring_dest_t *)
-                dma_alloc(2*MAX_NUM_IR_DESC*(sizeof(ring_dest_t)), &temp);
-        if (!aup->rx_ring[0])
-                goto out2;
+        for (i = 0; i < NUM_IR_DESC; i++) {
+                ptxd = aup->rx_ring[i];
+                ptxd->count_0 = 0;
+                ptxd->count_1 = 0;
+                ptxd->flags = AU_OWN;
+        }
 
-        /* allocate the data buffers */
-        aup->db[0].vaddr = 
-                (void *)dma_alloc(MAX_BUF_SIZE * 2*NUM_IR_DESC, &temp);
-        if (!aup->db[0].vaddr)
-                goto out3;
+        if (speed == 4000000)
+                au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_FIR);
+        else
+                au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR);
 
-        setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512);
+        switch (speed) {
+        case 9600:
+                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(11) | IR_PW(12));
+                irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
+                break;
+        case 19200:
+                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(5) | IR_PW(12));
+                irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
+                break;
+        case 38400:
+                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(2) | IR_PW(12));
+                irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
+                break;
+        case 57600:
+                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(1) | IR_PW(12));
+                irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
+                break;
+        case 115200:
+                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_PW(12));
+                irda_write(aup, IR_CONFIG_1, IR_SIR_MODE);
+                break;
+        case 4000000:
+                irda_write(aup, IR_WRITE_PHY_CONFIG, IR_P(15));
+                irda_write(aup, IR_CONFIG_1, IR_FIR | IR_DMA_ENABLE |
+                                IR_RX_ENABLE);
+                break;
+        default:
+                printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed);
+                ret = -EINVAL;
+                break;
+        }
 
-        pDBfree = NULL;
-        pDB = aup->db;
-        for (i=0; i<(2*NUM_IR_DESC); i++) {
-                pDB->pnext = pDBfree;
-                pDBfree = pDB;
-                pDB->vaddr = 
-                        (u32 *)((unsigned)aup->db[0].vaddr + MAX_BUF_SIZE*i);
-                pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
-                pDB++;
+        aup->speed = speed;
+        irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) | IR_PHYEN);
+
+        control = irda_read(aup, IR_STATUS);
+        irda_write(aup, IR_RING_PROMPT, 0);
+
+        if (control & (1 << 14)) {
+                printk(KERN_ERR "%s: configuration error\n", dev->name);
+        } else {
+                if (control & (1 << 11))
+                        printk(KERN_DEBUG "%s Valid SIR config\n", dev->name);
+                if (control & (1 << 12))
+                        printk(KERN_DEBUG "%s Valid MIR config\n", dev->name);
+                if (control & (1 << 13))
+                        printk(KERN_DEBUG "%s Valid FIR config\n", dev->name);
+                if (control & (1 << 10))
+                        printk(KERN_DEBUG "%s TX enabled\n", dev->name);
+                if (control & (1 << 9))
+                        printk(KERN_DEBUG "%s RX enabled\n", dev->name);
         }
-        aup->pDBfree = pDBfree;
 
-        /* attach a data buffer to each descriptor */
-        for (i=0; i<NUM_IR_DESC; i++) {
-                pDB = GetFreeDB(aup);
-                if (!pDB) goto out;
-                aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff);
-                aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff);
-                aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff);
-                aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff);
-                aup->rx_db_inuse[i] = pDB;
+        return ret;
+}
+
+static void update_rx_stats(struct net_device *dev, u32 status, u32 count)
+{
+        struct net_device_stats *ps = &dev->stats;
+
+        ps->rx_packets++;
+
+        if (status & IR_RX_ERROR) {
+                ps->rx_errors++;
+                if (status & (IR_PHY_ERROR | IR_FIFO_OVER))
+                        ps->rx_missed_errors++;
+                if (status & IR_MAX_LEN)
+                        ps->rx_length_errors++;
+                if (status & IR_CRC_ERROR)
+                        ps->rx_crc_errors++;
+        } else
+                ps->rx_bytes += count;
+}
+
+static void update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
+{
+        struct net_device_stats *ps = &dev->stats;
+
+        ps->tx_packets++;
+        ps->tx_bytes += pkt_len;
+
+        if (status & IR_TX_ERROR) {
+                ps->tx_errors++;
+                ps->tx_aborted_errors++;
         }
-        for (i=0; i<NUM_IR_DESC; i++) {
-                pDB = GetFreeDB(aup);
-                if (!pDB) goto out;
-                aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff);
-                aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff);
-                aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff);
-                aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff);
-                aup->tx_ring[i]->count_0 = 0;
-                aup->tx_ring[i]->count_1 = 0;
-                aup->tx_ring[i]->flags = 0;
-                aup->tx_db_inuse[i] = pDB;
+}
+
+static void au1k_tx_ack(struct net_device *dev)
+{
+        struct au1k_private *aup = netdev_priv(dev);
+        volatile struct ring_dest *ptxd;
+
+        ptxd = aup->tx_ring[aup->tx_tail];
+        while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) {
+                update_tx_stats(dev, ptxd->flags,
+                                (ptxd->count_1 << 8) | ptxd->count_0);
+                ptxd->count_0 = 0;
+                ptxd->count_1 = 0;
+                wmb();
+                aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1);
+                ptxd = aup->tx_ring[aup->tx_tail];
+
+                if (aup->tx_full) {
+                        aup->tx_full = 0;
+                        netif_wake_queue(dev);
+                }
         }
 
-#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
-        /* power on */
-        bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
-                              BCSR_RESETS_IRDA_MODE_FULL);
-#endif
+        if (aup->tx_tail == aup->tx_head) {
+                if (aup->newspeed) {
+                        au1k_irda_set_speed(dev, aup->newspeed);
+                        aup->newspeed = 0;
+                } else {
+                        irda_write(aup, IR_CONFIG_1,
+                            irda_read(aup, IR_CONFIG_1) & ~IR_TX_ENABLE);
+                        irda_write(aup, IR_CONFIG_1,
+                            irda_read(aup, IR_CONFIG_1) | IR_RX_ENABLE);
+                        irda_write(aup, IR_RING_PROMPT, 0);
+                }
+        }
+}
 
-        return 0;
+static int au1k_irda_rx(struct net_device *dev)
+{
+        struct au1k_private *aup = netdev_priv(dev);
+        volatile struct ring_dest *prxd;
+        struct sk_buff *skb;
+        struct db_dest *pDB;
+        u32 flags, count;
 
-out3:
-        dma_free((void *)aup->rx_ring[0],
-                2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t)));
-out2:
-        kfree(aup->rx_buff.head);
-out1:
-        printk(KERN_ERR "au1k_init_module failed.  Returns %d\n", retval);
-        return retval;
+        prxd = aup->rx_ring[aup->rx_head];
+        flags = prxd->flags;
+
+        while (!(flags & AU_OWN))  {
+                pDB = aup->rx_db_inuse[aup->rx_head];
+                count = (prxd->count_1 << 8) | prxd->count_0;
+                if (!(flags & IR_RX_ERROR)) {
+                        /* good frame */
+                        update_rx_stats(dev, flags, count);
+                        skb = alloc_skb(count + 1, GFP_ATOMIC);
+                        if (skb == NULL) {
+                                dev->stats.rx_dropped++;
+                                continue;
+                        }
+                        skb_reserve(skb, 1);
+                        if (aup->speed == 4000000)
+                                skb_put(skb, count);
+                        else
+                                skb_put(skb, count - 2);
+                        skb_copy_to_linear_data(skb, (void *)pDB->vaddr,
+                                                count - 2);
+                        skb->dev = dev;
+                        skb_reset_mac_header(skb);
+                        skb->protocol = htons(ETH_P_IRDA);
+                        netif_rx(skb);
+                        prxd->count_0 = 0;
+                        prxd->count_1 = 0;
+                }
+                prxd->flags |= AU_OWN;
+                aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1);
+                irda_write(aup, IR_RING_PROMPT, 0);
+
+                /* next descriptor */
+                prxd = aup->rx_ring[aup->rx_head];
+                flags = prxd->flags;
+
+        }
+        return 0;
 }
 
+static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id)
+{
+        struct net_device *dev = dev_id;
+        struct au1k_private *aup = netdev_priv(dev);
+
+        irda_write(aup, IR_INT_CLEAR, 0); /* ack irda interrupts */
+
+        au1k_irda_rx(dev);
+        au1k_tx_ack(dev);
+
+        return IRQ_HANDLED;
+}
 
 static int au1k_init(struct net_device *dev)
 {
         struct au1k_private *aup = netdev_priv(dev);
+        u32 enable, ring_address;
         int i;
-        u32 control;
-        u32 ring_address;
 
-        /* bring the device out of reset */
-        control = 0xe; /* coherent, clock enable, one half system clock */
-                          
+        enable = IR_HC | IR_CE | IR_C;
 #ifndef CONFIG_CPU_LITTLE_ENDIAN
-        control |= 1;
+        enable |= IR_BE;
 #endif
         aup->tx_head = 0;
         aup->tx_tail = 0;
         aup->rx_head = 0;
 
-        for (i=0; i<NUM_IR_DESC; i++) {
+        for (i = 0; i < NUM_IR_DESC; i++)
                 aup->rx_ring[i]->flags = AU_OWN;
-        }
 
-        writel(control, IR_INTERFACE_CONFIG);
-        au_sync_delay(10);
+        irda_write(aup, IR_ENABLE, enable);
+        msleep(20);
 
-        writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); /* disable PHY */
-        au_sync_delay(1);
+        /* disable PHY */
+        au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
+        irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN);
+        msleep(20);
 
-        writel(MAX_BUF_SIZE, IR_MAX_PKT_LEN);
+        irda_write(aup, IR_MAX_PKT_LEN, MAX_BUF_SIZE);
 
         ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]);
-        writel(ring_address >> 26, IR_RING_BASE_ADDR_H);
-        writel((ring_address >> 10) & 0xffff, IR_RING_BASE_ADDR_L);
+        irda_write(aup, IR_RING_BASE_ADDR_H, ring_address >> 26);
+        irda_write(aup, IR_RING_BASE_ADDR_L, (ring_address >> 10) & 0xffff);
 
-        writel(RING_SIZE_64<<8 | RING_SIZE_64<<12, IR_RING_SIZE);
+        irda_write(aup, IR_RING_SIZE,
+                                (RING_SIZE_64 << 8) | (RING_SIZE_64 << 12));
 
-        writel(1<<2 | IR_ONE_PIN, IR_CONFIG_2); /* 48MHz */
-        writel(0, IR_RING_ADDR_CMPR);
+        irda_write(aup, IR_CONFIG_2, IR_PHYCLK_48MHZ | IR_ONE_PIN);
+        irda_write(aup, IR_RING_ADDR_CMPR, 0);
 
         au1k_irda_set_speed(dev, 9600);
         return 0;
@@ -340,25 +555,28 @@ static int au1k_init(struct net_device *dev)
 
 static int au1k_irda_start(struct net_device *dev)
 {
-        int retval;
-        char hwname[32];
         struct au1k_private *aup = netdev_priv(dev);
+        char hwname[32];
+        int retval;
 
-        if ((retval = au1k_init(dev))) {
+        retval = au1k_init(dev);
+        if (retval) {
                 printk(KERN_ERR "%s: error in au1k_init\n", dev->name);
                 return retval;
         }
 
-        if ((retval = request_irq(AU1000_IRDA_TX_INT, au1k_irda_interrupt, 
-                                        0, dev->name, dev))) {
-                printk(KERN_ERR "%s: unable to get IRQ %d\n", 
+        retval = request_irq(aup->irq_tx, &au1k_irda_interrupt, 0,
+                             dev->name, dev);
+        if (retval) {
+                printk(KERN_ERR "%s: unable to get IRQ %d\n",
                                 dev->name, dev->irq);
                 return retval;
         }
-        if ((retval = request_irq(AU1000_IRDA_RX_INT, au1k_irda_interrupt, 
-                                        0, dev->name, dev))) {
-                free_irq(AU1000_IRDA_TX_INT, dev);
-                printk(KERN_ERR "%s: unable to get IRQ %d\n", 
+        retval = request_irq(aup->irq_rx, &au1k_irda_interrupt, 0,
+                             dev->name, dev);
+        if (retval) {
+                free_irq(aup->irq_tx, dev);
+                printk(KERN_ERR "%s: unable to get IRQ %d\n",
                                 dev->name, dev->irq);
                 return retval;
         }
@@ -368,9 +586,13 @@ static int au1k_irda_start(struct net_device *dev)
         aup->irlap = irlap_open(dev, &aup->qos, hwname);
         netif_start_queue(dev);
 
-        writel(read_ir_reg(IR_CONFIG_2) | 1<<8, IR_CONFIG_2); /* int enable */
+        /* int enable */
+        irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) | IR_IEN);
+
+        /* power up */
+        au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR);
 
-        aup->timer.expires = RUN_AT((3*HZ)); 
+        aup->timer.expires = RUN_AT((3 * HZ));
         aup->timer.data = (unsigned long)dev;
         return 0;
 }
@@ -379,11 +601,12 @@ static int au1k_irda_stop(struct net_device *dev)
 {
         struct au1k_private *aup = netdev_priv(dev);
 
+        au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF);
+
         /* disable interrupts */
-        writel(read_ir_reg(IR_CONFIG_2) & ~(1<<8), IR_CONFIG_2);
-        writel(0, IR_CONFIG_1); 
-        writel(0, IR_INTERFACE_CONFIG); /* disable clock */
-        au_sync();
+        irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) & ~IR_IEN);
+        irda_write(aup, IR_CONFIG_1, 0);
+        irda_write(aup, IR_ENABLE, 0); /* disable clock */
 
         if (aup->irlap) {
                 irlap_close(aup->irlap);
@@ -394,83 +617,12 @@ static int au1k_irda_stop(struct net_device *dev)
         del_timer(&aup->timer);
 
         /* disable the interrupt */
-        free_irq(AU1000_IRDA_TX_INT, dev);
-        free_irq(AU1000_IRDA_RX_INT, dev);
-        return 0;
-}
-
-static void __exit au1k_irda_exit(void)
-{
-        struct net_device *dev = ir_devs[0];
-        struct au1k_private *aup = netdev_priv(dev);
+        free_irq(aup->irq_tx, dev);
+        free_irq(aup->irq_rx, dev);
 
-        unregister_netdev(dev);
-
-        dma_free((void *)aup->db[0].vaddr,
-                MAX_BUF_SIZE * 2*NUM_IR_DESC);
-        dma_free((void *)aup->rx_ring[0],
-                2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t)));
-        kfree(aup->rx_buff.head);
-        free_netdev(dev);
-}
-
-
-static inline void 
-update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len)
-{
-        struct au1k_private *aup = netdev_priv(dev);
-        struct net_device_stats *ps = &aup->stats;
-
-        ps->tx_packets++;
-        ps->tx_bytes += pkt_len;
-
-        if (status & IR_TX_ERROR) {
-                ps->tx_errors++;
-                ps->tx_aborted_errors++;
-        }
-}
-
-
-static void au1k_tx_ack(struct net_device *dev)
-{
-        struct au1k_private *aup = netdev_priv(dev);
-        volatile ring_dest_t *ptxd;
-
-        ptxd = aup->tx_ring[aup->tx_tail];
-        while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) {
-                update_tx_stats(dev, ptxd->flags, 
-                                ptxd->count_1<<8 | ptxd->count_0);
-                ptxd->count_0 = 0;
-                ptxd->count_1 = 0;
-                au_sync();
-
-                aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1);
-                ptxd = aup->tx_ring[aup->tx_tail];
-
-                if (aup->tx_full) {
-                        aup->tx_full = 0;
-                        netif_wake_queue(dev);
-                }
-        }
-
-        if (aup->tx_tail == aup->tx_head) {
-                if (aup->newspeed) {
-                        au1k_irda_set_speed(dev, aup->newspeed);
-                        aup->newspeed = 0;
-                }
-                else {
-                        writel(read_ir_reg(IR_CONFIG_1) & ~IR_TX_ENABLE, 
-                                        IR_CONFIG_1); 
-                        au_sync();
-                        writel(read_ir_reg(IR_CONFIG_1) | IR_RX_ENABLE, 
-                                        IR_CONFIG_1); 
-                        writel(0, IR_RING_PROMPT);
-                        au_sync();
-                }
-        }
+        return 0;
 }
 
-
 /*
  * Au1000 transmit routine.
  */
@@ -478,15 +630,12 @@ static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
 {
         struct au1k_private *aup = netdev_priv(dev);
         int speed = irda_get_next_speed(skb);
-        volatile ring_dest_t *ptxd;
-        u32 len;
-
-        u32 flags;
-        db_dest_t *pDB;
+        volatile struct ring_dest *ptxd;
+        struct db_dest *pDB;
+        u32 len, flags;
 
-        if (speed != aup->speed && speed != -1) {
+        if (speed != aup->speed && speed != -1)
                 aup->newspeed = speed;
-        }
 
         if ((skb->len == 0) && (aup->newspeed)) {
                 if (aup->tx_tail == aup->tx_head) {
@@ -504,138 +653,47 @@ static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
                 printk(KERN_DEBUG "%s: tx_full\n", dev->name);
                 netif_stop_queue(dev);
                 aup->tx_full = 1;
-                return NETDEV_TX_BUSY;
-        }
-        else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) {
+                return 1;
+        } else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) {
                 printk(KERN_DEBUG "%s: tx_full\n", dev->name);
                 netif_stop_queue(dev);
                 aup->tx_full = 1;
-                return NETDEV_TX_BUSY;
+                return 1;
         }
 
         pDB = aup->tx_db_inuse[aup->tx_head];
 
 #if 0
-        if (read_ir_reg(IR_RX_BYTE_CNT) != 0) {
-                printk("tx warning: rx byte cnt %x\n", 
-                                read_ir_reg(IR_RX_BYTE_CNT));
+        if (irda_read(aup, IR_RX_BYTE_CNT) != 0) {
+                printk(KERN_DEBUG "tx warning: rx byte cnt %x\n",
+                                irda_read(aup, IR_RX_BYTE_CNT));
         }
 #endif
-        
+
         if (aup->speed == 4000000) {
                 /* FIR */
-                skb_copy_from_linear_data(skb, pDB->vaddr, skb->len);
+                skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
                 ptxd->count_0 = skb->len & 0xff;
                 ptxd->count_1 = (skb->len >> 8) & 0xff;
-
-        }
-        else {
+        } else {
                 /* SIR */
                 len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE);
                 ptxd->count_0 = len & 0xff;
                 ptxd->count_1 = (len >> 8) & 0xff;
                 ptxd->flags |= IR_DIS_CRC;
-                au_writel(au_readl(0xae00000c) & ~(1<<13), 0xae00000c);
         }
         ptxd->flags |= AU_OWN;
-        au_sync();
+        wmb();
 
-        writel(read_ir_reg(IR_CONFIG_1) | IR_TX_ENABLE, IR_CONFIG_1); 
-        writel(0, IR_RING_PROMPT);
-        au_sync();
+        irda_write(aup, IR_CONFIG_1,
+                   irda_read(aup, IR_CONFIG_1) | IR_TX_ENABLE);
+        irda_write(aup, IR_RING_PROMPT, 0);
 
         dev_kfree_skb(skb);
         aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1);
         return NETDEV_TX_OK;
 }
 
-
-static inline void 
-update_rx_stats(struct net_device *dev, u32 status, u32 count)
-{
-        struct au1k_private *aup = netdev_priv(dev);
-        struct net_device_stats *ps = &aup->stats;
-
-        ps->rx_packets++;
-
-        if (status & IR_RX_ERROR) {
-                ps->rx_errors++;
-                if (status & (IR_PHY_ERROR|IR_FIFO_OVER))
-                        ps->rx_missed_errors++;
-                if (status & IR_MAX_LEN)
-                        ps->rx_length_errors++;
-                if (status & IR_CRC_ERROR)
-                        ps->rx_crc_errors++;
-        }
-        else 
-                ps->rx_bytes += count;
-}
-
-/*
- * Au1000 receive routine.
- */
-static int au1k_irda_rx(struct net_device *dev)
-{
-        struct au1k_private *aup = netdev_priv(dev);
-        struct sk_buff *skb;
-        volatile ring_dest_t *prxd;
-        u32 flags, count;
-        db_dest_t *pDB;
-
-        prxd = aup->rx_ring[aup->rx_head];
-        flags = prxd->flags;
-
-        while (!(flags & AU_OWN))  {
-                pDB = aup->rx_db_inuse[aup->rx_head];
-                count = prxd->count_1<<8 | prxd->count_0;
-                if (!(flags & IR_RX_ERROR))  {
-                        /* good frame */
-                        update_rx_stats(dev, flags, count);
-                        skb=alloc_skb(count+1,GFP_ATOMIC);
-                        if (skb == NULL) {
-                                aup->netdev->stats.rx_dropped++;
-                                continue;
-                        }
-                        skb_reserve(skb, 1);
-                        if (aup->speed == 4000000)
-                                skb_put(skb, count);
-                        else
-                                skb_put(skb, count-2);
-                        skb_copy_to_linear_data(skb, pDB->vaddr, count - 2);
-                        skb->dev = dev;
-                        skb_reset_mac_header(skb);
-                        skb->protocol = htons(ETH_P_IRDA);
-                        netif_rx(skb);
-                        prxd->count_0 = 0;
-                        prxd->count_1 = 0;
-                }
-                prxd->flags |= AU_OWN;
-                aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1);
-                writel(0, IR_RING_PROMPT);
-                au_sync();
-
-                /* next descriptor */
-                prxd = aup->rx_ring[aup->rx_head];
-                flags = prxd->flags;
-
-        }
-        return 0;
-}
-
-
-static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id)
-{
-        struct net_device *dev = dev_id;
-
-        writel(0, IR_INT_CLEAR); /* ack irda interrupts */
-
-        au1k_irda_rx(dev);
-        au1k_tx_ack(dev);
-
-        return IRQ_HANDLED;
-}
-
-
 /*
  * The Tx ring has been full longer than the watchdog timeout
  * value. The transmitter must be hung?
@@ -653,142 +711,7 @@ static void au1k_tx_timeout(struct net_device *dev)
         netif_wake_queue(dev);
 }
 
-
-/*
- * Set the IrDA communications speed.
- */
-static int 
-au1k_irda_set_speed(struct net_device *dev, int speed)
-{
-        unsigned long flags;
-        struct au1k_private *aup = netdev_priv(dev);
-        u32 control;
-        int ret = 0, timeout = 10, i;
-        volatile ring_dest_t *ptxd;
-#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
-        unsigned long irda_resets;
-#endif
-
-        if (speed == aup->speed)
-                return ret;
-
-        spin_lock_irqsave(&ir_lock, flags);
-
-        /* disable PHY first */
-        writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE);
-
-        /* disable RX/TX */
-        writel(read_ir_reg(IR_CONFIG_1) & ~(IR_RX_ENABLE|IR_TX_ENABLE), 
-                        IR_CONFIG_1);
-        au_sync_delay(1);
-        while (read_ir_reg(IR_ENABLE) & (IR_RX_STATUS | IR_TX_STATUS)) {
-                mdelay(1);
-                if (!timeout--) {
-                        printk(KERN_ERR "%s: rx/tx disable timeout\n",
-                                        dev->name);
-                        break;
-                }
-        }
-
-        /* disable DMA */
-        writel(read_ir_reg(IR_CONFIG_1) & ~IR_DMA_ENABLE, IR_CONFIG_1);
-        au_sync_delay(1);
-
-        /* 
-         *  After we disable tx/rx. the index pointers
-         * go back to zero.
-         */
-        aup->tx_head = aup->tx_tail = aup->rx_head = 0;
-        for (i=0; i<NUM_IR_DESC; i++) {
-                ptxd = aup->tx_ring[i];
-                ptxd->flags = 0;
-                ptxd->count_0 = 0;
-                ptxd->count_1 = 0;
-        }
-
-        for (i=0; i<NUM_IR_DESC; i++) {
-                ptxd = aup->rx_ring[i];
-                ptxd->count_0 = 0;
-                ptxd->count_1 = 0;
-                ptxd->flags = AU_OWN;
-        }
-
-        if (speed == 4000000) {
-#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
-                bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_FIR_SEL);
-#else /* Pb1000 and Pb1100 */
-                writel(1<<13, CPLD_AUX1);
-#endif
-        }
-        else {
-#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100)
-                bcsr_mod(BCSR_RESETS, BCSR_RESETS_FIR_SEL, 0);
-#else /* Pb1000 and Pb1100 */
-                writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1);
-#endif
-        }
-
-        switch (speed) {
-        case 9600:      
-                writel(11<<10 | 12<<5, IR_WRITE_PHY_CONFIG); 
-                writel(IR_SIR_MODE, IR_CONFIG_1); 
-                break;
-        case 19200:     
-                writel(5<<10 | 12<<5, IR_WRITE_PHY_CONFIG); 
-                writel(IR_SIR_MODE, IR_CONFIG_1); 
-                break;
-        case 38400:
-                writel(2<<10 | 12<<5, IR_WRITE_PHY_CONFIG); 
-                writel(IR_SIR_MODE, IR_CONFIG_1); 
-                break;
-        case 57600:     
-                writel(1<<10 | 12<<5, IR_WRITE_PHY_CONFIG); 
-                writel(IR_SIR_MODE, IR_CONFIG_1); 
-                break;
-        case 115200: 
-                writel(12<<5, IR_WRITE_PHY_CONFIG); 
-                writel(IR_SIR_MODE, IR_CONFIG_1); 
-                break;
-        case 4000000:
-                writel(0xF, IR_WRITE_PHY_CONFIG);
-                writel(IR_FIR|IR_DMA_ENABLE|IR_RX_ENABLE, IR_CONFIG_1); 
-                break;
-        default:
-                printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed);
-                ret = -EINVAL;
-                break;
-        }
-
-        aup->speed = speed;
-        writel(read_ir_reg(IR_ENABLE) | 0x8000, IR_ENABLE);
-        au_sync();
-
-        control = read_ir_reg(IR_ENABLE);
-        writel(0, IR_RING_PROMPT);
-        au_sync();
-
-        if (control & (1<<14)) {
-                printk(KERN_ERR "%s: configuration error\n", dev->name);
-        }
-        else {
-                if (control & (1<<11))
-                        printk(KERN_DEBUG "%s Valid SIR config\n", dev->name);
-                if (control & (1<<12))
-                        printk(KERN_DEBUG "%s Valid MIR config\n", dev->name);
-                if (control & (1<<13))
-                        printk(KERN_DEBUG "%s Valid FIR config\n", dev->name);
-                if (control & (1<<10))
-                        printk(KERN_DEBUG "%s TX enabled\n", dev->name);
-                if (control & (1<<9))
-                        printk(KERN_DEBUG "%s RX enabled\n", dev->name);
-        }
-
-        spin_unlock_irqrestore(&ir_lock, flags);
-        return ret;
-}
-
-static int 
-au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
+static int au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
 {
         struct if_irda_req *rq = (struct if_irda_req *)ifreq;
         struct au1k_private *aup = netdev_priv(dev);
@@ -829,8 +752,218 @@ au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
         return ret;
 }
 
+static const struct net_device_ops au1k_irda_netdev_ops = {
+        .ndo_open               = au1k_irda_start,
+        .ndo_stop               = au1k_irda_stop,
+        .ndo_start_xmit         = au1k_irda_hard_xmit,
+        .ndo_tx_timeout         = au1k_tx_timeout,
+        .ndo_do_ioctl           = au1k_irda_ioctl,
+};
+
+static int __devinit au1k_irda_net_init(struct net_device *dev)
+{
+        struct au1k_private *aup = netdev_priv(dev);
+        struct db_dest *pDB, *pDBfree;
+        int i, err, retval = 0;
+        dma_addr_t temp;
+
+        err = au1k_irda_init_iobuf(&aup->rx_buff, 14384);
+        if (err)
+                goto out1;
+
+        dev->netdev_ops = &au1k_irda_netdev_ops;
+
+        irda_init_max_qos_capabilies(&aup->qos);
+
+        /* The only value we must override it the baudrate */
+        aup->qos.baud_rate.bits = IR_9600 | IR_19200 | IR_38400 |
+                IR_57600 | IR_115200 | IR_576000 | (IR_4000000 << 8);
+
+        aup->qos.min_turn_time.bits = qos_mtt_bits;
+        irda_qos_bits_to_value(&aup->qos);
+
+        retval = -ENOMEM;
+
+        /* Tx ring follows rx ring + 512 bytes */
+        /* we need a 1k aligned buffer */
+        aup->rx_ring[0] = (struct ring_dest *)
+                dma_alloc(2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)),
+                          &temp);
+        if (!aup->rx_ring[0])
+                goto out2;
+
+        /* allocate the data buffers */
+        aup->db[0].vaddr =
+                (void *)dma_alloc(MAX_BUF_SIZE * 2 * NUM_IR_DESC, &temp);
+        if (!aup->db[0].vaddr)
+                goto out3;
+
+        setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512);
+
+        pDBfree = NULL;
+        pDB = aup->db;
+        for (i = 0; i < (2 * NUM_IR_DESC); i++) {
+                pDB->pnext = pDBfree;
+                pDBfree = pDB;
+                pDB->vaddr =
+                       (u32 *)((unsigned)aup->db[0].vaddr + (MAX_BUF_SIZE * i));
+                pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
+                pDB++;
+        }
+        aup->pDBfree = pDBfree;
+
+        /* attach a data buffer to each descriptor */
+        for (i = 0; i < NUM_IR_DESC; i++) {
+                pDB = GetFreeDB(aup);
+                if (!pDB)
+                        goto out3;
+                aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff);
+                aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr >>  8) & 0xff);
+                aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff);
+                aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff);
+                aup->rx_db_inuse[i] = pDB;
+        }
+        for (i = 0; i < NUM_IR_DESC; i++) {
+                pDB = GetFreeDB(aup);
+                if (!pDB)
+                        goto out3;
+                aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff);
+                aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr >>  8) & 0xff);
+                aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff);
+                aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff);
+                aup->tx_ring[i]->count_0 = 0;
+                aup->tx_ring[i]->count_1 = 0;
+                aup->tx_ring[i]->flags = 0;
+                aup->tx_db_inuse[i] = pDB;
+        }
+
+        return 0;
+
+out3:
+        dma_free((void *)aup->rx_ring[0],
+                2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
+out2:
+        kfree(aup->rx_buff.head);
+out1:
+        printk(KERN_ERR "au1k_irda_net_init() failed.  Returns %d\n", retval);
+        return retval;
+}
+
+static int __devinit au1k_irda_probe(struct platform_device *pdev)
+{
+        struct au1k_private *aup;
+        struct net_device *dev;
+        struct resource *r;
+        int err;
+
+        dev = alloc_irdadev(sizeof(struct au1k_private));
+        if (!dev)
+                return -ENOMEM;
+
+        aup = netdev_priv(dev);
+
+        aup->platdata = pdev->dev.platform_data;
+
+        err = -EINVAL;
+        r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (!r)
+                goto out;
+
+        aup->irq_tx = r->start;
+
+        r = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
+        if (!r)
+                goto out;
+
+        aup->irq_rx = r->start;
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!r)
+                goto out;
+
+        err = -EBUSY;
+        aup->ioarea = request_mem_region(r->start, r->end - r->start + 1,
+                                         pdev->name);
+        if (!aup->ioarea)
+                goto out;
+
+        aup->iobase = ioremap_nocache(r->start, r->end - r->start + 1);
+        if (!aup->iobase)
+                goto out2;
+
+        dev->irq = aup->irq_rx;
+
+        err = au1k_irda_net_init(dev);
+        if (err)
+                goto out3;
+        err = register_netdev(dev);
+        if (err)
+                goto out4;
+
+        platform_set_drvdata(pdev, dev);
+
+        printk(KERN_INFO "IrDA: Registered device %s\n", dev->name);
+        return 0;
+
+out4:
+        dma_free((void *)aup->db[0].vaddr,
+                MAX_BUF_SIZE * 2 * NUM_IR_DESC);
+        dma_free((void *)aup->rx_ring[0],
+                2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
+        kfree(aup->rx_buff.head);
+out3:
+        iounmap(aup->iobase);
+out2:
+        release_resource(aup->ioarea);
+        kfree(aup->ioarea);
+out:
+        free_netdev(dev);
+        return err;
+}
+
+static int __devexit au1k_irda_remove(struct platform_device *pdev)
+{
+        struct net_device *dev = platform_get_drvdata(pdev);
+        struct au1k_private *aup = netdev_priv(dev);
+
+        unregister_netdev(dev);
+
+        dma_free((void *)aup->db[0].vaddr,
+                MAX_BUF_SIZE * 2 * NUM_IR_DESC);
+        dma_free((void *)aup->rx_ring[0],
+                2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)));
+        kfree(aup->rx_buff.head);
+
+        iounmap(aup->iobase);
+        release_resource(aup->ioarea);
+        kfree(aup->ioarea);
+
+        free_netdev(dev);
+
+        return 0;
+}
+
+static struct platform_driver au1k_irda_driver = {
+        .driver = {
+                .name   = "au1000-irda",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = au1k_irda_probe,
+        .remove         = __devexit_p(au1k_irda_remove),
+};
+
+static int __init au1k_irda_load(void)
+{
+        return platform_driver_register(&au1k_irda_driver);
+}
+
+static void __exit au1k_irda_unload(void)
+{
+        return platform_driver_unregister(&au1k_irda_driver);
+}
+
 MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>");
 MODULE_DESCRIPTION("Au1000 IrDA Device Driver");
 
-module_init(au1k_irda_init);
-module_exit(au1k_irda_exit);
+module_init(au1k_irda_load);
+module_exit(au1k_irda_unload);
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index 6e318ce41136..f9e3fb3a285b 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -155,18 +155,14 @@ config PCMCIA_M8XX
 
           This driver is also available as a module called m8xx_pcmcia.
 
-config PCMCIA_AU1X00
-        tristate "Au1x00 pcmcia support"
-        depends on MIPS_ALCHEMY && PCMCIA
-
 config PCMCIA_ALCHEMY_DEVBOARD
         tristate "Alchemy Db/Pb1xxx PCMCIA socket services"
         depends on MIPS_ALCHEMY && PCMCIA
         select 64BIT_PHYS_ADDR
         help
           Enable this driver of you want PCMCIA support on your Alchemy
-          Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200 board.
-          NOT suitable for the PB1000!
+          Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200, DB1300
+          board.  NOT suitable for the PB1000!
 
           This driver is also available as a module called db1xxx_ss.ko
 
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 29935ea921df..ec543a4ff2e4 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_PCMCIA_SA1100)			+= sa11xx_base.o sa1100_cs.o
 obj-$(CONFIG_PCMCIA_SA1111)                     += sa11xx_base.o sa1111_cs.o
 obj-$(CONFIG_M32R_PCC)                          += m32r_pcc.o
 obj-$(CONFIG_M32R_CFC)                          += m32r_cfc.o
-obj-$(CONFIG_PCMCIA_AU1X00)                     += au1x00_ss.o
 obj-$(CONFIG_PCMCIA_BCM63XX)                    += bcm63xx_pcmcia.o
 obj-$(CONFIG_PCMCIA_VRC4171)                    += vrc4171_card.o
 obj-$(CONFIG_PCMCIA_VRC4173)                    += vrc4173_cardu.o
@@ -39,9 +38,6 @@ obj-$(CONFIG_AT91_CF)				+= at91_cf.o
 obj-$(CONFIG_ELECTRA_CF)                        += electra_cf.o
 obj-$(CONFIG_PCMCIA_ALCHEMY_DEVBOARD)           += db1xxx_ss.o
 
-au1x00_ss-y                                     += au1000_generic.o
-au1x00_ss-$(CONFIG_MIPS_PB1000)                 += au1000_pb1x00.o
-
 sa1111_cs-y                                     += sa1111_generic.o
 sa1111_cs-$(CONFIG_ASSABET_NEPONSET)            += sa1100_neponset.o
 sa1111_cs-$(CONFIG_SA1100_BADGE4)               += sa1100_badge4.o
diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c
deleted file mode 100644
index 95dd7c62741f..000000000000
--- a/drivers/pcmcia/au1000_generic.c
+++ /dev/null
@@ -1,545 +0,0 @@
-/*
- *
- * Alchemy Semi Au1000 pcmcia driver
- *
- * Copyright 2001-2003 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@embeddedalley.com or source@mvista.com
- *
- * Copyright 2004 Pete Popov, Embedded Alley Solutions, Inc.
- * Updated the driver to 2.6. Followed the sa11xx API and largely
- * copied many of the hardware independent functions.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * 
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
-#include <linux/ioport.h>
-#include <linux/kernel.h>
-#include <linux/timer.h>
-#include <linux/mm.h>
-#include <linux/notifier.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/system.h>
-
-#include <asm/mach-au1x00/au1000.h>
-#include "au1000_generic.h"
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Pete Popov <ppopov@embeddedalley.com>");
-MODULE_DESCRIPTION("Linux PCMCIA Card Services: Au1x00 Socket Controller");
-
-#if 0
-#define debug(x,args...) printk(KERN_DEBUG "%s: " x, __func__ , ##args)
-#else
-#define debug(x,args...)
-#endif
-
-#define MAP_SIZE 0x100000
-extern struct au1000_pcmcia_socket au1000_pcmcia_socket[];
-#define PCMCIA_SOCKET(x)        (au1000_pcmcia_socket + (x))
-#define to_au1000_socket(x)     container_of(x, struct au1000_pcmcia_socket, socket)
-
-/* Some boards like to support CF cards as IDE root devices, so they
- * grab pcmcia sockets directly.
- */
-u32 *pcmcia_base_vaddrs[2];
-extern const unsigned long mips_io_port_base;
-
-static DEFINE_MUTEX(pcmcia_sockets_lock);
-
-static int (*au1x00_pcmcia_hw_init[])(struct device *dev) = {
-        au1x_board_init,
-};
-
-static int
-au1x00_pcmcia_skt_state(struct au1000_pcmcia_socket *skt)
-{
-        struct pcmcia_state state;
-        unsigned int stat;
-
-        memset(&state, 0, sizeof(struct pcmcia_state));
-
-        skt->ops->socket_state(skt, &state);
-
-        stat = state.detect  ? SS_DETECT : 0;
-        stat |= state.ready  ? SS_READY  : 0;
-        stat |= state.wrprot ? SS_WRPROT : 0;
-        stat |= state.vs_3v  ? SS_3VCARD : 0;
-        stat |= state.vs_Xv  ? SS_XVCARD : 0;
-        stat |= skt->cs_state.Vcc ? SS_POWERON : 0;
-
-        if (skt->cs_state.flags & SS_IOCARD)
-                stat |= state.bvd1 ? SS_STSCHG : 0;
-        else {
-                if (state.bvd1 == 0)
-                        stat |= SS_BATDEAD;
-                else if (state.bvd2 == 0)
-                        stat |= SS_BATWARN;
-        }
-        return stat;
-}
-
-/*
- * au100_pcmcia_config_skt
- *
- * Convert PCMCIA socket state to our socket configure structure.
- */
-static int
-au1x00_pcmcia_config_skt(struct au1000_pcmcia_socket *skt, socket_state_t *state)
-{
-        int ret;
-
-        ret = skt->ops->configure_socket(skt, state);
-        if (ret == 0) {
-                skt->cs_state = *state;
-        }
-
-        if (ret < 0)
-                debug("unable to configure socket %d\n", skt->nr);
-
-        return ret;
-}
-
-/* au1x00_pcmcia_sock_init()
- *
- * (Re-)Initialise the socket, turning on status interrupts
- * and PCMCIA bus.  This must wait for power to stabilise
- * so that the card status signals report correctly.
- *
- * Returns: 0
- */
-static int au1x00_pcmcia_sock_init(struct pcmcia_socket *sock)
-{
-        struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
-
-        debug("initializing socket %u\n", skt->nr);
-
-        skt->ops->socket_init(skt);
-        return 0;
-}
-
-/*
- * au1x00_pcmcia_suspend()
- *
- * Remove power on the socket, disable IRQs from the card.
- * Turn off status interrupts, and disable the PCMCIA bus.
- *
- * Returns: 0
- */
-static int au1x00_pcmcia_suspend(struct pcmcia_socket *sock)
-{
-        struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
-
-        debug("suspending socket %u\n", skt->nr);
-
-        skt->ops->socket_suspend(skt);
-
-        return 0;
-}
-
-static DEFINE_SPINLOCK(status_lock);
-
-/*
- * au1x00_check_status()
- */
-static void au1x00_check_status(struct au1000_pcmcia_socket *skt)
-{
-        unsigned int events;
-
-        debug("entering PCMCIA monitoring thread\n");
-
-        do {
-                unsigned int status;
-                unsigned long flags;
-
-                status = au1x00_pcmcia_skt_state(skt);
-
-                spin_lock_irqsave(&status_lock, flags);
-                events = (status ^ skt->status) & skt->cs_state.csc_mask;
-                skt->status = status;
-                spin_unlock_irqrestore(&status_lock, flags);
-
-                debug("events: %s%s%s%s%s%s\n",
-                        events == 0         ? "<NONE>"   : "",
-                        events & SS_DETECT  ? "DETECT "  : "",
-                        events & SS_READY   ? "READY "   : "",
-                        events & SS_BATDEAD ? "BATDEAD " : "",
-                        events & SS_BATWARN ? "BATWARN " : "",
-                        events & SS_STSCHG  ? "STSCHG "  : "");
-
-                if (events)
-                        pcmcia_parse_events(&skt->socket, events);
-        } while (events);
-}
-
-/* 
- * au1x00_pcmcia_poll_event()
- * Let's poll for events in addition to IRQs since IRQ only is unreliable...
- */
-static void au1x00_pcmcia_poll_event(unsigned long dummy)
-{
-        struct au1000_pcmcia_socket *skt = (struct au1000_pcmcia_socket *)dummy;
-        debug("polling for events\n");
-
-        mod_timer(&skt->poll_timer, jiffies + AU1000_PCMCIA_POLL_PERIOD);
-
-        au1x00_check_status(skt);
-}
-
-/* au1x00_pcmcia_get_status()
- *
- * From the sa11xx_core.c:
- * Implements the get_status() operation for the in-kernel PCMCIA
- * service (formerly SS_GetStatus in Card Services). Essentially just
- * fills in bits in `status' according to internal driver state or
- * the value of the voltage detect chipselect register.
- *
- * As a debugging note, during card startup, the PCMCIA core issues
- * three set_socket() commands in a row the first with RESET deasserted,
- * the second with RESET asserted, and the last with RESET deasserted
- * again. Following the third set_socket(), a get_status() command will
- * be issued. The kernel is looking for the SS_READY flag (see
- * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
- *
- * Returns: 0
- */
-static int
-au1x00_pcmcia_get_status(struct pcmcia_socket *sock, unsigned int *status)
-{
-        struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
-
-        skt->status = au1x00_pcmcia_skt_state(skt);
-        *status = skt->status;
-
-        return 0;
-}
-
-/* au1x00_pcmcia_set_socket()
- * Implements the set_socket() operation for the in-kernel PCMCIA
- * service (formerly SS_SetSocket in Card Services). We more or
- * less punt all of this work and let the kernel handle the details
- * of power configuration, reset, &c. We also record the value of
- * `state' in order to regurgitate it to the PCMCIA core later.
- *
- * Returns: 0
- */
-static int
-au1x00_pcmcia_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
-{
-  struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
-
-  debug("for sock %u\n", skt->nr);
-
-  debug("\tmask:  %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n",
-        (state->csc_mask==0)?"<NONE>":"",
-        (state->csc_mask&SS_DETECT)?"DETECT ":"",
-        (state->csc_mask&SS_READY)?"READY ":"",
-        (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"",
-        (state->csc_mask&SS_BATWARN)?"BATWARN ":"",
-        (state->csc_mask&SS_STSCHG)?"STSCHG ":"",
-        (state->flags==0)?"<NONE>":"",
-        (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"",
-        (state->flags&SS_IOCARD)?"IOCARD ":"",
-        (state->flags&SS_RESET)?"RESET ":"",
-        (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"",
-        (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"");
-  debug("\tVcc %d  Vpp %d  irq %d\n",
-        state->Vcc, state->Vpp, state->io_irq);
-
-  return au1x00_pcmcia_config_skt(skt, state);
-}
-
-int 
-au1x00_pcmcia_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *map)
-{
-        struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
-        unsigned int speed;
-
-        if(map->map>=MAX_IO_WIN){
-                debug("map (%d) out of range\n", map->map);
-                return -1;
-        }
-
-        if(map->flags&MAP_ACTIVE){
-                speed=(map->speed>0)?map->speed:AU1000_PCMCIA_IO_SPEED;
-                skt->spd_io[map->map] = speed;
-        }
-
-        map->start=(unsigned int)(u32)skt->virt_io;
-        map->stop=map->start+MAP_SIZE;
-        return 0;
-
-}  /* au1x00_pcmcia_set_io_map() */
-
-
-static int 
-au1x00_pcmcia_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map)
-{
-        struct au1000_pcmcia_socket *skt = to_au1000_socket(sock);
-        unsigned short speed = map->speed;
-
-        if(map->map>=MAX_WIN){
-                debug("map (%d) out of range\n", map->map);
-                return -1;
-        }
-
-        if (map->flags & MAP_ATTRIB) {
-                skt->spd_attr[map->map] = speed;
-                skt->spd_mem[map->map] = 0;
-        } else {
-                skt->spd_attr[map->map] = 0;
-                skt->spd_mem[map->map] = speed;
-        }
-
-        if (map->flags & MAP_ATTRIB) {
-                map->static_start = skt->phys_attr + map->card_start;
-        }
-        else {
-                map->static_start = skt->phys_mem + map->card_start;
-        }
-
-        debug("set_mem_map %d start %08lx card_start %08x\n",
-                        map->map, map->static_start, map->card_start);
-        return 0;
-
-}  /* au1x00_pcmcia_set_mem_map() */
-
-static struct pccard_operations au1x00_pcmcia_operations = {
-        .init                   = au1x00_pcmcia_sock_init,
-        .suspend                = au1x00_pcmcia_suspend,
-        .get_status             = au1x00_pcmcia_get_status,
-        .set_socket             = au1x00_pcmcia_set_socket,
-        .set_io_map             = au1x00_pcmcia_set_io_map,
-        .set_mem_map            = au1x00_pcmcia_set_mem_map,
-};
-
-static const char *skt_names[] = {
-        "PCMCIA socket 0",
-        "PCMCIA socket 1",
-};
-
-struct skt_dev_info {
-        int nskt;
-};
-
-int au1x00_pcmcia_socket_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr)
-{
-        struct skt_dev_info *sinfo;
-        struct au1000_pcmcia_socket *skt;
-        int ret, i;
-
-        sinfo = kzalloc(sizeof(struct skt_dev_info), GFP_KERNEL);
-        if (!sinfo) {
-                ret = -ENOMEM;
-                goto out;
-        }
-
-        sinfo->nskt = nr;
-
-        /*
-         * Initialise the per-socket structure.
-         */
-        for (i = 0; i < nr; i++) {
-                skt = PCMCIA_SOCKET(i);
-                memset(skt, 0, sizeof(*skt));
-
-                skt->socket.resource_ops = &pccard_static_ops;
-                skt->socket.ops = &au1x00_pcmcia_operations;
-                skt->socket.owner = ops->owner;
-                skt->socket.dev.parent = dev;
-
-                init_timer(&skt->poll_timer);
-                skt->poll_timer.function = au1x00_pcmcia_poll_event;
-                skt->poll_timer.data = (unsigned long)skt;
-                skt->poll_timer.expires = jiffies + AU1000_PCMCIA_POLL_PERIOD;
-
-                skt->nr         = first + i;
-                skt->irq        = 255;
-                skt->dev        = dev;
-                skt->ops        = ops;
-
-                skt->res_skt.name       = skt_names[skt->nr];
-                skt->res_io.name        = "io";
-                skt->res_io.flags       = IORESOURCE_MEM | IORESOURCE_BUSY;
-                skt->res_mem.name       = "memory";
-                skt->res_mem.flags      = IORESOURCE_MEM;
-                skt->res_attr.name      = "attribute";
-                skt->res_attr.flags     = IORESOURCE_MEM;
-
-                /*
-                 * PCMCIA client drivers use the inb/outb macros to access the
-                 * IO registers. Since mips_io_port_base is added to the
-                 * access address of the mips implementation of inb/outb,
-                 * we need to subtract it here because we want to access the
-                 * I/O or MEM address directly, without going through this
-                 * "mips_io_port_base" mechanism.
-                 */
-                if (i == 0) {
-                        skt->virt_io = (void *)
-                                (ioremap((phys_t)AU1X_SOCK0_IO, 0x1000) -
-                                (u32)mips_io_port_base);
-                        skt->phys_attr = AU1X_SOCK0_PHYS_ATTR;
-                        skt->phys_mem = AU1X_SOCK0_PHYS_MEM;
-                }
-                else  {
-                        skt->virt_io = (void *)
-                                (ioremap((phys_t)AU1X_SOCK1_IO, 0x1000) -
-                                (u32)mips_io_port_base);
-                        skt->phys_attr = AU1X_SOCK1_PHYS_ATTR;
-                        skt->phys_mem = AU1X_SOCK1_PHYS_MEM;
-                }
-                pcmcia_base_vaddrs[i] = (u32 *)skt->virt_io;
-                ret = ops->hw_init(skt);
-
-                skt->socket.features = SS_CAP_STATIC_MAP|SS_CAP_PCCARD;
-                skt->socket.irq_mask = 0;
-                skt->socket.map_size = MAP_SIZE;
-                skt->socket.pci_irq = skt->irq;
-                skt->socket.io_offset = (unsigned long)skt->virt_io;
-
-                skt->status = au1x00_pcmcia_skt_state(skt);
-
-                ret = pcmcia_register_socket(&skt->socket);
-                if (ret)
-                        goto out_err;
-
-                WARN_ON(skt->socket.sock != i);
-
-                add_timer(&skt->poll_timer);
-        }
-
-        dev_set_drvdata(dev, sinfo);
-        return 0;
-
-
-out_err:
-        ops->hw_shutdown(skt);
-        while (i-- > 0) {
-                skt = PCMCIA_SOCKET(i);
-
-                del_timer_sync(&skt->poll_timer);
-                pcmcia_unregister_socket(&skt->socket);
-                if (i == 0) {
-                        iounmap(skt->virt_io + (u32)mips_io_port_base);
-                        skt->virt_io = NULL;
-                }
-#ifndef CONFIG_MIPS_XXS1500
-                else {
-                        iounmap(skt->virt_io + (u32)mips_io_port_base);
-                        skt->virt_io = NULL;
-                }
-#endif
-                ops->hw_shutdown(skt);
-
-        }
-        kfree(sinfo);
-out:
-        return ret;
-}
-
-int au1x00_drv_pcmcia_remove(struct platform_device *dev)
-{
-        struct skt_dev_info *sinfo = platform_get_drvdata(dev);
-        int i;
-
-        mutex_lock(&pcmcia_sockets_lock);
-        platform_set_drvdata(dev, NULL);
-
-        for (i = 0; i < sinfo->nskt; i++) {
-                struct au1000_pcmcia_socket *skt = PCMCIA_SOCKET(i);
-
-                del_timer_sync(&skt->poll_timer);
-                pcmcia_unregister_socket(&skt->socket);
-                skt->ops->hw_shutdown(skt);
-                au1x00_pcmcia_config_skt(skt, &dead_socket);
-                iounmap(skt->virt_io + (u32)mips_io_port_base);
-                skt->virt_io = NULL;
-        }
-
-        kfree(sinfo);
-        mutex_unlock(&pcmcia_sockets_lock);
-        return 0;
-}
-
-
-/*
- * PCMCIA "Driver" API
- */
-
-static int au1x00_drv_pcmcia_probe(struct platform_device *dev)
-{
-        int i, ret = -ENODEV;
-
-        mutex_lock(&pcmcia_sockets_lock);
-        for (i=0; i < ARRAY_SIZE(au1x00_pcmcia_hw_init); i++) {
-                ret = au1x00_pcmcia_hw_init[i](&dev->dev);
-                if (ret == 0)
-                        break;
-        }
-        mutex_unlock(&pcmcia_sockets_lock);
-        return ret;
-}
-
-static struct platform_driver au1x00_pcmcia_driver = {
-        .driver = {
-                .name           = "au1x00-pcmcia",
-                .owner          = THIS_MODULE,
-        },
-        .probe          = au1x00_drv_pcmcia_probe,
-        .remove         = au1x00_drv_pcmcia_remove,
-};
-
-
-/* au1x00_pcmcia_init()
- *
- * This routine performs low-level PCMCIA initialization and then
- * registers this socket driver with Card Services.
- *
- * Returns: 0 on success, -ve error code on failure
- */
-static int __init au1x00_pcmcia_init(void)
-{
-        int error = 0;
-        error = platform_driver_register(&au1x00_pcmcia_driver);
-        return error;
-}
-
-/* au1x00_pcmcia_exit()
- * Invokes the low-level kernel service to free IRQs associated with this
- * socket controller and reset GPIO edge detection.
- */
-static void __exit au1x00_pcmcia_exit(void)
-{
-        platform_driver_unregister(&au1x00_pcmcia_driver);
-}
-
-module_init(au1x00_pcmcia_init);
-module_exit(au1x00_pcmcia_exit);
diff --git a/drivers/pcmcia/au1000_generic.h b/drivers/pcmcia/au1000_generic.h
deleted file mode 100644
index 5c36bda2963b..000000000000
--- a/drivers/pcmcia/au1000_generic.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Alchemy Semi Au1000 pcmcia driver include file
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-#ifndef __ASM_AU1000_PCMCIA_H
-#define __ASM_AU1000_PCMCIA_H
-
-/* include the world */
-
-#include <pcmcia/ss.h>
-#include <pcmcia/cistpl.h>
-#include "cs_internal.h"
-
-#define AU1000_PCMCIA_POLL_PERIOD    (2*HZ)
-#define AU1000_PCMCIA_IO_SPEED       (255)
-#define AU1000_PCMCIA_MEM_SPEED      (300)
-
-#define AU1X_SOCK0_IO        0xF00000000ULL
-#define AU1X_SOCK0_PHYS_ATTR 0xF40000000ULL
-#define AU1X_SOCK0_PHYS_MEM  0xF80000000ULL
-
-/* pcmcia socket 1 needs external glue logic so the memory map
- * differs from board to board.
- */
-#if defined(CONFIG_MIPS_PB1000)
-#define AU1X_SOCK1_IO        0xF08000000ULL
-#define AU1X_SOCK1_PHYS_ATTR 0xF48000000ULL
-#define AU1X_SOCK1_PHYS_MEM  0xF88000000ULL
-#endif
-
-struct pcmcia_state {
-  unsigned detect: 1,
-            ready: 1,
-           wrprot: 1,
-             bvd1: 1,
-             bvd2: 1,
-            vs_3v: 1,
-            vs_Xv: 1;
-};
-
-struct pcmcia_configure {
-  unsigned sock: 8,
-            vcc: 8,
-            vpp: 8,
-         output: 1,
-        speaker: 1,
-          reset: 1;
-};
-
-struct pcmcia_irqs {
-        int sock;
-        int irq;
-        const char *str;
-};
-
-
-struct au1000_pcmcia_socket {
-        struct pcmcia_socket socket;
-
-        /*
-         * Info from low level handler
-         */
-        struct device           *dev;
-        unsigned int            nr;
-        unsigned int            irq;
-
-        /*
-         * Core PCMCIA state
-         */
-        struct pcmcia_low_level *ops;
-
-        unsigned int            status;
-        socket_state_t          cs_state;
-
-        unsigned short          spd_io[MAX_IO_WIN];
-        unsigned short          spd_mem[MAX_WIN];
-        unsigned short          spd_attr[MAX_WIN];
-
-        struct resource         res_skt;
-        struct resource         res_io;
-        struct resource         res_mem;
-        struct resource         res_attr;
-
-        void *                  virt_io;
-        unsigned int            phys_io;
-        unsigned int            phys_attr;
-        unsigned int            phys_mem;
-        unsigned short          speed_io, speed_attr, speed_mem;
-
-        unsigned int            irq_state;
-
-        struct timer_list       poll_timer;
-};
-
-struct pcmcia_low_level {
-        struct module *owner;
-
-        int (*hw_init)(struct au1000_pcmcia_socket *);
-        void (*hw_shutdown)(struct au1000_pcmcia_socket *);
-
-        void (*socket_state)(struct au1000_pcmcia_socket *, struct pcmcia_state *);
-        int (*configure_socket)(struct au1000_pcmcia_socket *, struct socket_state_t *);
-
-        /*
-         * Enable card status IRQs on (re-)initialisation.  This can
-         * be called at initialisation, power management event, or
-         * pcmcia event.
-         */
-        void (*socket_init)(struct au1000_pcmcia_socket *);
-
-        /*
-         * Disable card status IRQs and PCMCIA bus on suspend.
-         */
-        void (*socket_suspend)(struct au1000_pcmcia_socket *);
-};
-
-extern int au1x_board_init(struct device *dev);
-
-#endif /* __ASM_AU1000_PCMCIA_H */
diff --git a/drivers/pcmcia/au1000_pb1x00.c b/drivers/pcmcia/au1000_pb1x00.c
deleted file mode 100644
index b2396647a165..000000000000
--- a/drivers/pcmcia/au1000_pb1x00.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- *
- * Alchemy Semi Pb1000 boards specific pcmcia routines.
- *
- * Copyright 2002 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/ioport.h>
-#include <linux/kernel.h>
-#include <linux/timer.h>
-#include <linux/mm.h>
-#include <linux/proc_fs.h>
-#include <linux/types.h>
-
-#include <pcmcia/ss.h>
-#include <pcmcia/cistpl.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/system.h>
-
-#include <asm/au1000.h>
-#include <asm/au1000_pcmcia.h>
-
-#define debug(fmt, arg...) do { } while (0)
-
-#include <asm/pb1000.h>
-#define PCMCIA_IRQ AU1000_GPIO_15
-
-static int pb1x00_pcmcia_init(struct pcmcia_init *init)
-{
-        u16 pcr;
-        pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
-
-        au_writel(0x8000, PB1000_MDR); /* clear pcmcia interrupt */
-        au_sync_delay(100);
-        au_writel(0x4000, PB1000_MDR); /* enable pcmcia interrupt */
-        au_sync();
-
-        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
-        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1);
-        au_writel(pcr, PB1000_PCR);
-        au_sync_delay(20);
-          
-        return PCMCIA_NUM_SOCKS;
-}
-
-static int pb1x00_pcmcia_shutdown(void)
-{
-        u16 pcr;
-        pcr = PCR_SLOT_0_RST | PCR_SLOT_1_RST;
-        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,0);
-        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,1);
-        au_writel(pcr, PB1000_PCR);
-        au_sync_delay(20);
-        return 0;
-}
-
-static int 
-pb1x00_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
-{
-        u32 inserted0, inserted1;
-        u16 vs0, vs1;
-
-        vs0 = vs1 = (u16)au_readl(PB1000_ACR1);
-        inserted0 = !(vs0 & (ACR1_SLOT_0_CD1 | ACR1_SLOT_0_CD2));
-        inserted1 = !(vs1 & (ACR1_SLOT_1_CD1 | ACR1_SLOT_1_CD2));
-        vs0 = (vs0 >> 4) & 0x3;
-        vs1 = (vs1 >> 12) & 0x3;
-
-        state->ready = 0;
-        state->vs_Xv = 0;
-        state->vs_3v = 0;
-        state->detect = 0;
-
-        if (sock == 0) {
-                if (inserted0) {
-                        switch (vs0) {
-                                case 0:
-                                case 2:
-                                        state->vs_3v=1;
-                                        break;
-                                case 3: /* 5V */
-                                        break;
-                                default:
-                                        /* return without setting 'detect' */
-                                        printk(KERN_ERR "pb1x00 bad VS (%d)\n",
-                                                        vs0);
-                                        return 0;
-                        }
-                        state->detect = 1;
-                }
-        }
-        else  {
-                if (inserted1) {
-                        switch (vs1) {
-                                case 0:
-                                case 2:
-                                        state->vs_3v=1;
-                                        break;
-                                case 3: /* 5V */
-                                        break;
-                                default:
-                                        /* return without setting 'detect' */
-                                        printk(KERN_ERR "pb1x00 bad VS (%d)\n",
-                                                        vs1);
-                                        return 0;
-                        }
-                        state->detect = 1;
-                }
-        }
-
-        if (state->detect) {
-                state->ready = 1;
-        }
-
-        state->bvd1=1;
-        state->bvd2=1;
-        state->wrprot=0; 
-        return 1;
-}
-
-
-static int pb1x00_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
-{
-
-        if(info->sock > PCMCIA_MAX_SOCK) return -1;
-
-        /*
-         * Even in the case of the Pb1000, both sockets are connected
-         * to the same irq line.
-         */
-        info->irq = PCMCIA_IRQ;
-
-        return 0;
-}
-
-
-static int 
-pb1x00_pcmcia_configure_socket(const struct pcmcia_configure *configure)
-{
-        u16 pcr;
-
-        if(configure->sock > PCMCIA_MAX_SOCK) return -1;
-
-        pcr = au_readl(PB1000_PCR);
-
-        if (configure->sock == 0) {
-                pcr &= ~(PCR_SLOT_0_VCC0 | PCR_SLOT_0_VCC1 | 
-                                PCR_SLOT_0_VPP0 | PCR_SLOT_0_VPP1);
-        }
-        else  {
-                pcr &= ~(PCR_SLOT_1_VCC0 | PCR_SLOT_1_VCC1 | 
-                                PCR_SLOT_1_VPP0 | PCR_SLOT_1_VPP1);
-        }
-
-        pcr &= ~PCR_SLOT_0_RST;
-        debug("Vcc %dV Vpp %dV, pcr %x\n", 
-                        configure->vcc, configure->vpp, pcr);
-        switch(configure->vcc){
-                case 0:  /* Vcc 0 */
-                        switch(configure->vpp) {
-                                case 0:
-                                        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_GND,
-                                                        configure->sock);
-                                        break;
-                                case 12:
-                                        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_12V,
-                                                        configure->sock);
-                                        break;
-                                case 50:
-                                        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_5V,
-                                                        configure->sock);
-                                        break;
-                                case 33:
-                                        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_3V,
-                                                        configure->sock);
-                                        break;
-                                default:
-                                        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
-                                                        configure->sock);
-                                        printk("%s: bad Vcc/Vpp (%d:%d)\n", 
-                                                        __func__,
-                                                        configure->vcc, 
-                                                        configure->vpp);
-                                        break;
-                        }
-                        break;
-                case 50: /* Vcc 5V */
-                        switch(configure->vpp) {
-                                case 0:
-                                        pcr |= SET_VCC_VPP(VCC_5V,VPP_GND,
-                                                        configure->sock);
-                                        break;
-                                case 50:
-                                        pcr |= SET_VCC_VPP(VCC_5V,VPP_5V,
-                                                        configure->sock);
-                                        break;
-                                case 12:
-                                        pcr |= SET_VCC_VPP(VCC_5V,VPP_12V,
-                                                        configure->sock);
-                                        break;
-                                case 33:
-                                        pcr |= SET_VCC_VPP(VCC_5V,VPP_3V,
-                                                        configure->sock);
-                                        break;
-                                default:
-                                        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
-                                                        configure->sock);
-                                        printk("%s: bad Vcc/Vpp (%d:%d)\n", 
-                                                        __func__,
-                                                        configure->vcc, 
-                                                        configure->vpp);
-                                        break;
-                        }
-                        break;
-                case 33: /* Vcc 3.3V */
-                        switch(configure->vpp) {
-                                case 0:
-                                        pcr |= SET_VCC_VPP(VCC_3V,VPP_GND,
-                                                        configure->sock);
-                                        break;
-                                case 50:
-                                        pcr |= SET_VCC_VPP(VCC_3V,VPP_5V,
-                                                        configure->sock);
-                                        break;
-                                case 12:
-                                        pcr |= SET_VCC_VPP(VCC_3V,VPP_12V,
-                                                        configure->sock);
-                                        break;
-                                case 33:
-                                        pcr |= SET_VCC_VPP(VCC_3V,VPP_3V,
-                                                        configure->sock);
-                                        break;
-                                default:
-                                        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,
-                                                        configure->sock);
-                                        printk("%s: bad Vcc/Vpp (%d:%d)\n", 
-                                                        __func__,
-                                                        configure->vcc, 
-                                                        configure->vpp);
-                                        break;
-                        }
-                        break;
-                default: /* what's this ? */
-                        pcr |= SET_VCC_VPP(VCC_HIZ,VPP_HIZ,configure->sock);
-                        printk(KERN_ERR "%s: bad Vcc %d\n", 
-                                        __func__, configure->vcc);
-                        break;
-        }
-
-        if (configure->sock == 0) {
-        pcr &= ~(PCR_SLOT_0_RST);
-                if (configure->reset)
-                pcr |= PCR_SLOT_0_RST;
-        }
-        else {
-                pcr &= ~(PCR_SLOT_1_RST);
-                if (configure->reset)
-                        pcr |= PCR_SLOT_1_RST;
-        }
-        au_writel(pcr, PB1000_PCR);
-        au_sync_delay(300);
-
-        return 0;
-}
-
-
-struct pcmcia_low_level pb1x00_pcmcia_ops = { 
-        pb1x00_pcmcia_init,
-        pb1x00_pcmcia_shutdown,
-        pb1x00_pcmcia_socket_state,
-        pb1x00_pcmcia_get_irq_info,
-        pb1x00_pcmcia_configure_socket
-};
diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c
index 3e49df6d5e3b..5b7c22784aff 100644
--- a/drivers/pcmcia/db1xxx_ss.c
+++ b/drivers/pcmcia/db1xxx_ss.c
@@ -7,7 +7,7 @@
 
 /* This is a fairly generic PCMCIA socket driver suitable for the
  * following Alchemy Development boards:
- *  Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200.
+ *  Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200, Db1300
  *
  * The Db1000 is used as a reference:  Per-socket card-, carddetect- and
  *  statuschange IRQs connected to SoC GPIOs, control and status register
@@ -18,6 +18,7 @@
  *      - Pb1100/Pb1500:  single socket only; voltage key bits VS are
  *                        at STATUS[5:4] (instead of STATUS[1:0]).
  *      - Au1200-based:   additional card-eject irqs, irqs not gpios!
+ *      - Db1300:         Db1200-like, no pwr ctrl, single socket (#1).
  */
 
 #include <linux/delay.h>
@@ -59,11 +60,17 @@ struct db1x_pcmcia_sock {
 #define BOARD_TYPE_DEFAULT      0       /* most boards */
 #define BOARD_TYPE_DB1200       1       /* IRQs aren't gpios */
 #define BOARD_TYPE_PB1100       2       /* VS bits slightly different */
+#define BOARD_TYPE_DB1300       3       /* no power control */
         int     board_type;
 };
 
 #define to_db1x_socket(x) container_of(x, struct db1x_pcmcia_sock, socket)
 
+static int db1300_card_inserted(struct db1x_pcmcia_sock *sock)
+{
+        return bcsr_read(BCSR_SIGSTAT) & (1 << 8);
+}
+
 /* DB/PB1200: check CPLD SIGSTATUS register bit 10/12 */
 static int db1200_card_inserted(struct db1x_pcmcia_sock *sock)
 {
@@ -84,6 +91,8 @@ static int db1x_card_inserted(struct db1x_pcmcia_sock *sock)
         switch (sock->board_type) {
         case BOARD_TYPE_DB1200:
                 return db1200_card_inserted(sock);
+        case BOARD_TYPE_DB1300:
+                return db1300_card_inserted(sock);
         default:
                 return db1000_card_inserted(sock);
         }
@@ -160,7 +169,8 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock)
          * ejection handler have been registered and the currently
          * active one disabled.
          */
-        if (sock->board_type == BOARD_TYPE_DB1200) {
+        if ((sock->board_type == BOARD_TYPE_DB1200) ||
+            (sock->board_type == BOARD_TYPE_DB1300)) {
                 ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq,
                                   IRQF_DISABLED, "pcmcia_insert", sock);
                 if (ret)
@@ -174,7 +184,7 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock)
                 }
 
                 /* enable the currently silent one */
-                if (db1200_card_inserted(sock))
+                if (db1x_card_inserted(sock))
                         enable_irq(sock->eject_irq);
                 else
                         enable_irq(sock->insert_irq);
@@ -270,7 +280,8 @@ static int db1x_pcmcia_configure(struct pcmcia_socket *skt,
         }
 
         /* create new voltage code */
-        cr_set |= ((v << 2) | p) << (sock->nr * 8);
+        if (sock->board_type != BOARD_TYPE_DB1300)
+                cr_set |= ((v << 2) | p) << (sock->nr * 8);
 
         changed = state->flags ^ sock->old_flags;
 
@@ -343,6 +354,10 @@ static int db1x_pcmcia_get_status(struct pcmcia_socket *skt,
         /* if Vcc is not zero, we have applied power to a card */
         status |= GET_VCC(cr, sock->nr) ? SS_POWERON : 0;
 
+        /* DB1300: power always on, but don't tell when no card present */
+        if ((sock->board_type == BOARD_TYPE_DB1300) && (status & SS_DETECT))
+                status = SS_POWERON | SS_3VCARD | SS_DETECT;
+
         /* reset de-asserted? then we're ready */
         status |= (GET_RESET(cr, sock->nr)) ? SS_READY : SS_RESET;
 
@@ -419,6 +434,9 @@ static int __devinit db1x_pcmcia_socket_probe(struct platform_device *pdev)
         case BCSR_WHOAMI_PB1200 ... BCSR_WHOAMI_DB1200:
                 sock->board_type = BOARD_TYPE_DB1200;
                 break;
+        case BCSR_WHOAMI_DB1300:
+                sock->board_type = BOARD_TYPE_DB1300;
+                break;
         default:
                 printk(KERN_INFO "db1xxx-ss: unknown board %d!\n", bid);
                 ret = -ENODEV;
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a1fd73df5416..369e092bf3d5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -87,12 +87,12 @@ config SPI_BFIN_SPORT
           Enable support for a SPI bus via the Blackfin SPORT peripheral.
 
 config SPI_AU1550
-        tristate "Au1550/Au12x0 SPI Controller"
+        tristate "Au1550/Au1200/Au1300 SPI Controller"
         depends on MIPS_ALCHEMY && EXPERIMENTAL
         select SPI_BITBANG
         help
           If you say yes to this option, support will be included for the
-          Au1550 SPI controller (may also work with Au1200,Au1210,Au1250).
+          PSC SPI controller found on Au1550, Au1200 and Au1300 series.
 
 config SPI_BITBANG
         tristate "Utilities for Bitbanging SPI masters"
diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile
index fc850bac88c1..9012dee0c348 100644
--- a/drivers/staging/octeon/Makefile
+++ b/drivers/staging/octeon/Makefile
@@ -20,9 +20,4 @@ octeon-ethernet-y += ethernet-sgmii.o
 octeon-ethernet-y += ethernet-spi.o
 octeon-ethernet-y += ethernet-tx.o
 octeon-ethernet-y += ethernet-xaui.o
-octeon-ethernet-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
-        cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
-        cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
-        cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
-        cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
 
diff --git a/drivers/staging/octeon/cvmx-packet.h b/drivers/staging/octeon/cvmx-packet.h
deleted file mode 100644
index 62ffe78a8c81..000000000000
--- a/drivers/staging/octeon/cvmx-packet.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- *
- * Packet buffer defines.
- */
-
-#ifndef __CVMX_PACKET_H__
-#define __CVMX_PACKET_H__
-
-/**
- * This structure defines a buffer pointer on Octeon
- */
-union cvmx_buf_ptr {
-        void *ptr;
-        uint64_t u64;
-        struct {
-                /*
-                 * if set, invert the "free" pick of the overall
-                 * packet. HW always sets this bit to 0 on inbound
-                 * packet
-                 */
-                uint64_t i:1;
-                /*
-                 * Indicates the amount to back up to get to the
-                 * buffer start in cache lines. In most cases this is
-                 * less than one complete cache line, so the value is
-                 * zero.
-                 */
-                uint64_t back:4;
-                /* The pool that the buffer came from / goes to */
-                uint64_t pool:3;
-                /* The size of the segment pointed to by addr (in bytes) */
-                uint64_t size:16;
-                /* Pointer to the first byte of the data, NOT buffer */
-                uint64_t addr:40;
-        } s;
-};
-
-#endif /*  __CVMX_PACKET_H__ */
diff --git a/drivers/staging/octeon/cvmx-smix-defs.h b/drivers/staging/octeon/cvmx-smix-defs.h
deleted file mode 100644
index 9ae45fcbe3e3..000000000000
--- a/drivers/staging/octeon/cvmx-smix-defs.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-#ifndef __CVMX_SMIX_DEFS_H__
-#define __CVMX_SMIX_DEFS_H__
-
-#define CVMX_SMIX_CLK(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_CMD(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_EN(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_RD_DAT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_WR_DAT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
-
-union cvmx_smix_clk {
-        uint64_t u64;
-        struct cvmx_smix_clk_s {
-                uint64_t reserved_25_63:39;
-                uint64_t mode:1;
-                uint64_t reserved_21_23:3;
-                uint64_t sample_hi:5;
-                uint64_t sample_mode:1;
-                uint64_t reserved_14_14:1;
-                uint64_t clk_idle:1;
-                uint64_t preamble:1;
-                uint64_t sample:4;
-                uint64_t phase:8;
-        } s;
-        struct cvmx_smix_clk_cn30xx {
-                uint64_t reserved_21_63:43;
-                uint64_t sample_hi:5;
-                uint64_t reserved_14_15:2;
-                uint64_t clk_idle:1;
-                uint64_t preamble:1;
-                uint64_t sample:4;
-                uint64_t phase:8;
-        } cn30xx;
-        struct cvmx_smix_clk_cn30xx cn31xx;
-        struct cvmx_smix_clk_cn30xx cn38xx;
-        struct cvmx_smix_clk_cn30xx cn38xxp2;
-        struct cvmx_smix_clk_cn50xx {
-                uint64_t reserved_25_63:39;
-                uint64_t mode:1;
-                uint64_t reserved_21_23:3;
-                uint64_t sample_hi:5;
-                uint64_t reserved_14_15:2;
-                uint64_t clk_idle:1;
-                uint64_t preamble:1;
-                uint64_t sample:4;
-                uint64_t phase:8;
-        } cn50xx;
-        struct cvmx_smix_clk_s cn52xx;
-        struct cvmx_smix_clk_cn50xx cn52xxp1;
-        struct cvmx_smix_clk_s cn56xx;
-        struct cvmx_smix_clk_cn50xx cn56xxp1;
-        struct cvmx_smix_clk_cn30xx cn58xx;
-        struct cvmx_smix_clk_cn30xx cn58xxp1;
-};
-
-union cvmx_smix_cmd {
-        uint64_t u64;
-        struct cvmx_smix_cmd_s {
-                uint64_t reserved_18_63:46;
-                uint64_t phy_op:2;
-                uint64_t reserved_13_15:3;
-                uint64_t phy_adr:5;
-                uint64_t reserved_5_7:3;
-                uint64_t reg_adr:5;
-        } s;
-        struct cvmx_smix_cmd_cn30xx {
-                uint64_t reserved_17_63:47;
-                uint64_t phy_op:1;
-                uint64_t reserved_13_15:3;
-                uint64_t phy_adr:5;
-                uint64_t reserved_5_7:3;
-                uint64_t reg_adr:5;
-        } cn30xx;
-        struct cvmx_smix_cmd_cn30xx cn31xx;
-        struct cvmx_smix_cmd_cn30xx cn38xx;
-        struct cvmx_smix_cmd_cn30xx cn38xxp2;
-        struct cvmx_smix_cmd_s cn50xx;
-        struct cvmx_smix_cmd_s cn52xx;
-        struct cvmx_smix_cmd_s cn52xxp1;
-        struct cvmx_smix_cmd_s cn56xx;
-        struct cvmx_smix_cmd_s cn56xxp1;
-        struct cvmx_smix_cmd_cn30xx cn58xx;
-        struct cvmx_smix_cmd_cn30xx cn58xxp1;
-};
-
-union cvmx_smix_en {
-        uint64_t u64;
-        struct cvmx_smix_en_s {
-                uint64_t reserved_1_63:63;
-                uint64_t en:1;
-        } s;
-        struct cvmx_smix_en_s cn30xx;
-        struct cvmx_smix_en_s cn31xx;
-        struct cvmx_smix_en_s cn38xx;
-        struct cvmx_smix_en_s cn38xxp2;
-        struct cvmx_smix_en_s cn50xx;
-        struct cvmx_smix_en_s cn52xx;
-        struct cvmx_smix_en_s cn52xxp1;
-        struct cvmx_smix_en_s cn56xx;
-        struct cvmx_smix_en_s cn56xxp1;
-        struct cvmx_smix_en_s cn58xx;
-        struct cvmx_smix_en_s cn58xxp1;
-};
-
-union cvmx_smix_rd_dat {
-        uint64_t u64;
-        struct cvmx_smix_rd_dat_s {
-                uint64_t reserved_18_63:46;
-                uint64_t pending:1;
-                uint64_t val:1;
-                uint64_t dat:16;
-        } s;
-        struct cvmx_smix_rd_dat_s cn30xx;
-        struct cvmx_smix_rd_dat_s cn31xx;
-        struct cvmx_smix_rd_dat_s cn38xx;
-        struct cvmx_smix_rd_dat_s cn38xxp2;
-        struct cvmx_smix_rd_dat_s cn50xx;
-        struct cvmx_smix_rd_dat_s cn52xx;
-        struct cvmx_smix_rd_dat_s cn52xxp1;
-        struct cvmx_smix_rd_dat_s cn56xx;
-        struct cvmx_smix_rd_dat_s cn56xxp1;
-        struct cvmx_smix_rd_dat_s cn58xx;
-        struct cvmx_smix_rd_dat_s cn58xxp1;
-};
-
-union cvmx_smix_wr_dat {
-        uint64_t u64;
-        struct cvmx_smix_wr_dat_s {
-                uint64_t reserved_18_63:46;
-                uint64_t pending:1;
-                uint64_t val:1;
-                uint64_t dat:16;
-        } s;
-        struct cvmx_smix_wr_dat_s cn30xx;
-        struct cvmx_smix_wr_dat_s cn31xx;
-        struct cvmx_smix_wr_dat_s cn38xx;
-        struct cvmx_smix_wr_dat_s cn38xxp2;
-        struct cvmx_smix_wr_dat_s cn50xx;
-        struct cvmx_smix_wr_dat_s cn52xx;
-        struct cvmx_smix_wr_dat_s cn52xxp1;
-        struct cvmx_smix_wr_dat_s cn56xx;
-        struct cvmx_smix_wr_dat_s cn56xxp1;
-        struct cvmx_smix_wr_dat_s cn58xx;
-        struct cvmx_smix_wr_dat_s cn58xxp1;
-};
-
-#endif
diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h
index 6a2cd50a17df..bdaec8d2ca0c 100644
--- a/drivers/staging/octeon/ethernet-defines.h
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -59,7 +59,7 @@
 #ifndef __ETHERNET_DEFINES_H__
 #define __ETHERNET_DEFINES_H__
 
-#include "cvmx-config.h"
+#include <asm/octeon/cvmx-config.h>
 
 
 #define OCTEON_ETHERNET_VERSION "1.9"
diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c
index f18e3e140413..63800ba71d06 100644
--- a/drivers/staging/octeon/ethernet-mdio.c
+++ b/drivers/staging/octeon/ethernet-mdio.c
@@ -38,9 +38,9 @@
 #include "ethernet-mdio.h"
 #include "ethernet-util.h"
 
-#include "cvmx-helper-board.h"
+#include <asm/octeon/cvmx-helper-board.h>
 
-#include "cvmx-smix-defs.h"
+#include <asm/octeon/cvmx-smix-defs.h>
 
 static void cvm_oct_get_drvinfo(struct net_device *dev,
                                 struct ethtool_drvinfo *info)
diff --git a/drivers/staging/octeon/ethernet-mem.c b/drivers/staging/octeon/ethernet-mem.c
index 635bb86cdcff..78b6cb743769 100644
--- a/drivers/staging/octeon/ethernet-mem.c
+++ b/drivers/staging/octeon/ethernet-mem.c
@@ -32,7 +32,7 @@
 
 #include "ethernet-defines.h"
 
-#include "cvmx-fpa.h"
+#include <asm/octeon/cvmx-fpa.h>
 
 /**
  * cvm_oct_fill_hw_skbuff - fill the supplied hardware pool with skbuffs
diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c
index c3d73f8431ae..d8f5f694ec35 100644
--- a/drivers/staging/octeon/ethernet-rgmii.c
+++ b/drivers/staging/octeon/ethernet-rgmii.c
@@ -37,11 +37,11 @@
 #include "octeon-ethernet.h"
 #include "ethernet-util.h"
 
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-helper.h>
 
 #include <asm/octeon/cvmx-ipd-defs.h>
 #include <asm/octeon/cvmx-npi-defs.h>
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 DEFINE_SPINLOCK(global_register_lock);
 
diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c
index 8b307b428791..400df8cbee53 100644
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -52,14 +52,14 @@
 #include "octeon-ethernet.h"
 #include "ethernet-util.h"
 
-#include "cvmx-helper.h"
-#include "cvmx-wqe.h"
-#include "cvmx-fau.h"
-#include "cvmx-pow.h"
-#include "cvmx-pip.h"
-#include "cvmx-scratch.h"
-
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-wqe.h>
+#include <asm/octeon/cvmx-fau.h>
+#include <asm/octeon/cvmx-pow.h>
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-scratch.h>
+
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 struct cvm_napi_wrapper {
         struct napi_struct napi;
diff --git a/drivers/staging/octeon/ethernet-rx.h b/drivers/staging/octeon/ethernet-rx.h
index a0743b85d54e..9240c85ce241 100644
--- a/drivers/staging/octeon/ethernet-rx.h
+++ b/drivers/staging/octeon/ethernet-rx.h
@@ -24,7 +24,7 @@
  * This file may also be available under a different license from Cavium.
  * Contact Cavium Networks for more information
 *********************************************************************/
-#include "cvmx-fau.h"
+#include <asm/octeon/cvmx-fau.h>
 
 void cvm_oct_poll_controller(struct net_device *dev);
 void cvm_oct_rx_initialize(void);
diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c
index 5e148b512c97..d3e82430eba6 100644
--- a/drivers/staging/octeon/ethernet-sgmii.c
+++ b/drivers/staging/octeon/ethernet-sgmii.c
@@ -35,9 +35,9 @@
 #include "octeon-ethernet.h"
 #include "ethernet-util.h"
 
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 int cvm_oct_sgmii_open(struct net_device *dev)
 {
diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c
index d0e2d514968a..af8d62818f13 100644
--- a/drivers/staging/octeon/ethernet-spi.c
+++ b/drivers/staging/octeon/ethernet-spi.c
@@ -35,11 +35,11 @@
 #include "octeon-ethernet.h"
 #include "ethernet-util.h"
 
-#include "cvmx-spi.h"
+#include <asm/octeon/cvmx-spi.h>
 
 #include <asm/octeon/cvmx-npi-defs.h>
-#include "cvmx-spxx-defs.h"
-#include "cvmx-stxx-defs.h"
+#include <asm/octeon/cvmx-spxx-defs.h>
+#include <asm/octeon/cvmx-stxx-defs.h>
 
 static int number_spi_ports;
 static int need_retrain[2] = { 0, 0 };
diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c
index 2542c3743904..56d74dc2fbd5 100644
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -47,13 +47,13 @@
 #include "ethernet-tx.h"
 #include "ethernet-util.h"
 
-#include "cvmx-wqe.h"
-#include "cvmx-fau.h"
-#include "cvmx-pip.h"
-#include "cvmx-pko.h"
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-wqe.h>
+#include <asm/octeon/cvmx-fau.h>
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 #define CVM_OCT_SKB_CB(skb)     ((u64 *)((skb)->cb))
 
diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c
index 861a4b3fe857..419f8c34ecdf 100644
--- a/drivers/staging/octeon/ethernet-xaui.c
+++ b/drivers/staging/octeon/ethernet-xaui.c
@@ -35,9 +35,9 @@
 #include "octeon-ethernet.h"
 #include "ethernet-util.h"
 
-#include "cvmx-helper.h"
+#include <asm/octeon/cvmx-helper.h>
 
-#include "cvmx-gmxx-defs.h"
+#include <asm/octeon/cvmx-gmxx-defs.h>
 
 int cvm_oct_xaui_open(struct net_device *dev)
 {
diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c
index 076f86675ce6..9112cd882154 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -44,14 +44,14 @@
 #include "ethernet-mdio.h"
 #include "ethernet-util.h"
 
-#include "cvmx-pip.h"
-#include "cvmx-pko.h"
-#include "cvmx-fau.h"
-#include "cvmx-ipd.h"
-#include "cvmx-helper.h"
-
-#include "cvmx-gmxx-defs.h"
-#include "cvmx-smix-defs.h"
+#include <asm/octeon/cvmx-pip.h>
+#include <asm/octeon/cvmx-pko.h>
+#include <asm/octeon/cvmx-fau.h>
+#include <asm/octeon/cvmx-ipd.h>
+#include <asm/octeon/cvmx-helper.h>
+
+#include <asm/octeon/cvmx-gmxx-defs.h>
+#include <asm/octeon/cvmx-smix-defs.h>
 
 #if defined(CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS) \
         && CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 925a1e547a83..95a0f5fe7d42 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1610,4 +1610,27 @@ config SERIAL_XILINX_PS_UART_CONSOLE
         help
           Enable a Xilinx PS UART port to be the system console.
 
+config SERIAL_AR933X
+        bool "AR933X serial port support"
+        depends on SOC_AR933X
+        select SERIAL_CORE
+        help
+          If you have an Atheros AR933X SOC based board and want to use the
+          built-in UART of the SoC, say Y to this option.
+
+config SERIAL_AR933X_CONSOLE
+        bool "Console on AR933X serial port"
+        depends on SERIAL_AR933X=y
+        select SERIAL_CORE_CONSOLE
+        help
+          Enable a built-in UART port of the AR933X to be the system console.
+
+config SERIAL_AR933X_NR_UARTS
+        int "Maximum number of AR933X serial ports"
+        depends on SERIAL_AR933X
+        default "2"
+        help
+          Set this to the number of serial ports you want the driver
+          to support.
+
 endmenu
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index e10cf5b54b6d..76811cc58591 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -94,3 +94,4 @@ obj-$(CONFIG_SERIAL_MSM_SMD)	+= msm_smd_tty.o
 obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
 obj-$(CONFIG_SERIAL_LANTIQ)     += lantiq.o
 obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
+obj-$(CONFIG_SERIAL_AR933X)   += ar933x_uart.o
diff --git a/drivers/tty/serial/ar933x_uart.c b/drivers/tty/serial/ar933x_uart.c
new file mode 100644
index 000000000000..e4f60e2b87f3
--- /dev/null
+++ b/drivers/tty/serial/ar933x_uart.c
@@ -0,0 +1,688 @@
+/*
+ *  Atheros AR933X SoC built-in UART driver
+ *
+ *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/mach-ath79/ar933x_uart.h>
+#include <asm/mach-ath79/ar933x_uart_platform.h>
+
+#define DRIVER_NAME "ar933x-uart"
+
+#define AR933X_DUMMY_STATUS_RD  0x01
+
+static struct uart_driver ar933x_uart_driver;
+
+struct ar933x_uart_port {
+        struct uart_port        port;
+        unsigned int            ier;    /* shadow Interrupt Enable Register */
+};
+
+static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up,
+                                            int offset)
+{
+        return readl(up->port.membase + offset);
+}
+
+static inline void ar933x_uart_write(struct ar933x_uart_port *up,
+                                     int offset, unsigned int value)
+{
+        writel(value, up->port.membase + offset);
+}
+
+static inline void ar933x_uart_rmw(struct ar933x_uart_port *up,
+                                  unsigned int offset,
+                                  unsigned int mask,
+                                  unsigned int val)
+{
+        unsigned int t;
+
+        t = ar933x_uart_read(up, offset);
+        t &= ~mask;
+        t |= val;
+        ar933x_uart_write(up, offset, t);
+}
+
+static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up,
+                                       unsigned int offset,
+                                       unsigned int val)
+{
+        ar933x_uart_rmw(up, offset, 0, val);
+}
+
+static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up,
+                                         unsigned int offset,
+                                         unsigned int val)
+{
+        ar933x_uart_rmw(up, offset, val, 0);
+}
+
+static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up)
+{
+        up->ier |= AR933X_UART_INT_TX_EMPTY;
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+}
+
+static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up)
+{
+        up->ier &= ~AR933X_UART_INT_TX_EMPTY;
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+}
+
+static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch)
+{
+        unsigned int rdata;
+
+        rdata = ch & AR933X_UART_DATA_TX_RX_MASK;
+        rdata |= AR933X_UART_DATA_TX_CSR;
+        ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata);
+}
+
+static unsigned int ar933x_uart_tx_empty(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+        unsigned long flags;
+        unsigned int rdata;
+
+        spin_lock_irqsave(&up->port.lock, flags);
+        rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+        spin_unlock_irqrestore(&up->port.lock, flags);
+
+        return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT;
+}
+
+static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
+{
+        return TIOCM_CAR;
+}
+
+static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+static void ar933x_uart_start_tx(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+
+        ar933x_uart_start_tx_interrupt(up);
+}
+
+static void ar933x_uart_stop_tx(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+
+        ar933x_uart_stop_tx_interrupt(up);
+}
+
+static void ar933x_uart_stop_rx(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+
+        up->ier &= ~AR933X_UART_INT_RX_VALID;
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+}
+
+static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+        unsigned long flags;
+
+        spin_lock_irqsave(&up->port.lock, flags);
+        if (break_state == -1)
+                ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+                                    AR933X_UART_CS_TX_BREAK);
+        else
+                ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
+                                      AR933X_UART_CS_TX_BREAK);
+        spin_unlock_irqrestore(&up->port.lock, flags);
+}
+
+static void ar933x_uart_enable_ms(struct uart_port *port)
+{
+}
+
+static void ar933x_uart_set_termios(struct uart_port *port,
+                                    struct ktermios *new,
+                                    struct ktermios *old)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+        unsigned int cs;
+        unsigned long flags;
+        unsigned int baud, scale;
+
+        /* Only CS8 is supported */
+        new->c_cflag &= ~CSIZE;
+        new->c_cflag |= CS8;
+
+        /* Only one stop bit is supported */
+        new->c_cflag &= ~CSTOPB;
+
+        cs = 0;
+        if (new->c_cflag & PARENB) {
+                if (!(new->c_cflag & PARODD))
+                        cs |= AR933X_UART_CS_PARITY_EVEN;
+                else
+                        cs |= AR933X_UART_CS_PARITY_ODD;
+        } else {
+                cs |= AR933X_UART_CS_PARITY_NONE;
+        }
+
+        /* Mark/space parity is not supported */
+        new->c_cflag &= ~CMSPAR;
+
+        baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
+        scale = (port->uartclk / (16 * baud)) - 1;
+
+        /*
+         * Ok, we're now changing the port state. Do it with
+         * interrupts disabled.
+         */
+        spin_lock_irqsave(&up->port.lock, flags);
+
+        /* Update the per-port timeout. */
+        uart_update_timeout(port, new->c_cflag, baud);
+
+        up->port.ignore_status_mask = 0;
+
+        /* ignore all characters if CREAD is not set */
+        if ((new->c_cflag & CREAD) == 0)
+                up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD;
+
+        ar933x_uart_write(up, AR933X_UART_CLOCK_REG,
+                          scale << AR933X_UART_CLOCK_SCALE_S | 8192);
+
+        /* setup configuration register */
+        ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs);
+
+        /* enable host interrupt */
+        ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+                            AR933X_UART_CS_HOST_INT_EN);
+
+        spin_unlock_irqrestore(&up->port.lock, flags);
+
+        if (tty_termios_baud_rate(new))
+                tty_termios_encode_baud_rate(new, baud, baud);
+}
+
+static void ar933x_uart_rx_chars(struct ar933x_uart_port *up)
+{
+        struct tty_struct *tty;
+        int max_count = 256;
+
+        tty = tty_port_tty_get(&up->port.state->port);
+        do {
+                unsigned int rdata;
+                unsigned char ch;
+
+                rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+                if ((rdata & AR933X_UART_DATA_RX_CSR) == 0)
+                        break;
+
+                /* remove the character from the FIFO */
+                ar933x_uart_write(up, AR933X_UART_DATA_REG,
+                                  AR933X_UART_DATA_RX_CSR);
+
+                if (!tty) {
+                        /* discard the data if no tty available */
+                        continue;
+                }
+
+                up->port.icount.rx++;
+                ch = rdata & AR933X_UART_DATA_TX_RX_MASK;
+
+                if (uart_handle_sysrq_char(&up->port, ch))
+                        continue;
+
+                if ((up->port.ignore_status_mask & AR933X_DUMMY_STATUS_RD) == 0)
+                        tty_insert_flip_char(tty, ch, TTY_NORMAL);
+        } while (max_count-- > 0);
+
+        if (tty) {
+                tty_flip_buffer_push(tty);
+                tty_kref_put(tty);
+        }
+}
+
+static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
+{
+        struct circ_buf *xmit = &up->port.state->xmit;
+        int count;
+
+        if (uart_tx_stopped(&up->port))
+                return;
+
+        count = up->port.fifosize;
+        do {
+                unsigned int rdata;
+
+                rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+                if ((rdata & AR933X_UART_DATA_TX_CSR) == 0)
+                        break;
+
+                if (up->port.x_char) {
+                        ar933x_uart_putc(up, up->port.x_char);
+                        up->port.icount.tx++;
+                        up->port.x_char = 0;
+                        continue;
+                }
+
+                if (uart_circ_empty(xmit))
+                        break;
+
+                ar933x_uart_putc(up, xmit->buf[xmit->tail]);
+
+                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+                up->port.icount.tx++;
+        } while (--count > 0);
+
+        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                uart_write_wakeup(&up->port);
+
+        if (!uart_circ_empty(xmit))
+                ar933x_uart_start_tx_interrupt(up);
+}
+
+static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
+{
+        struct ar933x_uart_port *up = dev_id;
+        unsigned int status;
+
+        status = ar933x_uart_read(up, AR933X_UART_CS_REG);
+        if ((status & AR933X_UART_CS_HOST_INT) == 0)
+                return IRQ_NONE;
+
+        spin_lock(&up->port.lock);
+
+        status = ar933x_uart_read(up, AR933X_UART_INT_REG);
+        status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
+
+        if (status & AR933X_UART_INT_RX_VALID) {
+                ar933x_uart_write(up, AR933X_UART_INT_REG,
+                                  AR933X_UART_INT_RX_VALID);
+                ar933x_uart_rx_chars(up);
+        }
+
+        if (status & AR933X_UART_INT_TX_EMPTY) {
+                ar933x_uart_write(up, AR933X_UART_INT_REG,
+                                  AR933X_UART_INT_TX_EMPTY);
+                ar933x_uart_stop_tx_interrupt(up);
+                ar933x_uart_tx_chars(up);
+        }
+
+        spin_unlock(&up->port.lock);
+
+        return IRQ_HANDLED;
+}
+
+static int ar933x_uart_startup(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+        unsigned long flags;
+        int ret;
+
+        ret = request_irq(up->port.irq, ar933x_uart_interrupt,
+                          up->port.irqflags, dev_name(up->port.dev), up);
+        if (ret)
+                return ret;
+
+        spin_lock_irqsave(&up->port.lock, flags);
+
+        /* Enable HOST interrupts */
+        ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+                            AR933X_UART_CS_HOST_INT_EN);
+
+        /* Enable RX interrupts */
+        up->ier = AR933X_UART_INT_RX_VALID;
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+
+        spin_unlock_irqrestore(&up->port.lock, flags);
+
+        return 0;
+}
+
+static void ar933x_uart_shutdown(struct uart_port *port)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+
+        /* Disable all interrupts */
+        up->ier = 0;
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+
+        /* Disable break condition */
+        ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
+                              AR933X_UART_CS_TX_BREAK);
+
+        free_irq(up->port.irq, up);
+}
+
+static const char *ar933x_uart_type(struct uart_port *port)
+{
+        return (port->type == PORT_AR933X) ? "AR933X UART" : NULL;
+}
+
+static void ar933x_uart_release_port(struct uart_port *port)
+{
+        /* Nothing to release ... */
+}
+
+static int ar933x_uart_request_port(struct uart_port *port)
+{
+        /* UARTs always present */
+        return 0;
+}
+
+static void ar933x_uart_config_port(struct uart_port *port, int flags)
+{
+        if (flags & UART_CONFIG_TYPE)
+                port->type = PORT_AR933X;
+}
+
+static int ar933x_uart_verify_port(struct uart_port *port,
+                                   struct serial_struct *ser)
+{
+        if (ser->type != PORT_UNKNOWN &&
+            ser->type != PORT_AR933X)
+                return -EINVAL;
+
+        if (ser->irq < 0 || ser->irq >= NR_IRQS)
+                return -EINVAL;
+
+        if (ser->baud_base < 28800)
+                return -EINVAL;
+
+        return 0;
+}
+
+static struct uart_ops ar933x_uart_ops = {
+        .tx_empty       = ar933x_uart_tx_empty,
+        .set_mctrl      = ar933x_uart_set_mctrl,
+        .get_mctrl      = ar933x_uart_get_mctrl,
+        .stop_tx        = ar933x_uart_stop_tx,
+        .start_tx       = ar933x_uart_start_tx,
+        .stop_rx        = ar933x_uart_stop_rx,
+        .enable_ms      = ar933x_uart_enable_ms,
+        .break_ctl      = ar933x_uart_break_ctl,
+        .startup        = ar933x_uart_startup,
+        .shutdown       = ar933x_uart_shutdown,
+        .set_termios    = ar933x_uart_set_termios,
+        .type           = ar933x_uart_type,
+        .release_port   = ar933x_uart_release_port,
+        .request_port   = ar933x_uart_request_port,
+        .config_port    = ar933x_uart_config_port,
+        .verify_port    = ar933x_uart_verify_port,
+};
+
+#ifdef CONFIG_SERIAL_AR933X_CONSOLE
+
+static struct ar933x_uart_port *
+ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS];
+
+static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up)
+{
+        unsigned int status;
+        unsigned int timeout = 60000;
+
+        /* Wait up to 60ms for the character(s) to be sent. */
+        do {
+                status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
+                if (--timeout == 0)
+                        break;
+                udelay(1);
+        } while ((status & AR933X_UART_DATA_TX_CSR) == 0);
+}
+
+static void ar933x_uart_console_putchar(struct uart_port *port, int ch)
+{
+        struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
+
+        ar933x_uart_wait_xmitr(up);
+        ar933x_uart_putc(up, ch);
+}
+
+static void ar933x_uart_console_write(struct console *co, const char *s,
+                                      unsigned int count)
+{
+        struct ar933x_uart_port *up = ar933x_console_ports[co->index];
+        unsigned long flags;
+        unsigned int int_en;
+        int locked = 1;
+
+        local_irq_save(flags);
+
+        if (up->port.sysrq)
+                locked = 0;
+        else if (oops_in_progress)
+                locked = spin_trylock(&up->port.lock);
+        else
+                spin_lock(&up->port.lock);
+
+        /*
+         * First save the IER then disable the interrupts
+         */
+        int_en = ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0);
+
+        uart_console_write(&up->port, s, count, ar933x_uart_console_putchar);
+
+        /*
+         * Finally, wait for transmitter to become empty
+         * and restore the IER
+         */
+        ar933x_uart_wait_xmitr(up);
+        ar933x_uart_write(up, AR933X_UART_INT_EN_REG, int_en);
+
+        ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS);
+
+        if (locked)
+                spin_unlock(&up->port.lock);
+
+        local_irq_restore(flags);
+}
+
+static int ar933x_uart_console_setup(struct console *co, char *options)
+{
+        struct ar933x_uart_port *up;
+        int baud = 115200;
+        int bits = 8;
+        int parity = 'n';
+        int flow = 'n';
+
+        if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS)
+                return -EINVAL;
+
+        up = ar933x_console_ports[co->index];
+        if (!up)
+                return -ENODEV;
+
+        if (options)
+                uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+        return uart_set_options(&up->port, co, baud, parity, bits, flow);
+}
+
+static struct console ar933x_uart_console = {
+        .name           = "ttyATH",
+        .write          = ar933x_uart_console_write,
+        .device         = uart_console_device,
+        .setup          = ar933x_uart_console_setup,
+        .flags          = CON_PRINTBUFFER,
+        .index          = -1,
+        .data           = &ar933x_uart_driver,
+};
+
+static void ar933x_uart_add_console_port(struct ar933x_uart_port *up)
+{
+        ar933x_console_ports[up->port.line] = up;
+}
+
+#define AR933X_SERIAL_CONSOLE   (&ar933x_uart_console)
+
+#else
+
+static inline void ar933x_uart_add_console_port(struct ar933x_uart_port *up) {}
+
+#define AR933X_SERIAL_CONSOLE   NULL
+
+#endif /* CONFIG_SERIAL_AR933X_CONSOLE */
+
+static struct uart_driver ar933x_uart_driver = {
+        .owner          = THIS_MODULE,
+        .driver_name    = DRIVER_NAME,
+        .dev_name       = "ttyATH",
+        .nr             = CONFIG_SERIAL_AR933X_NR_UARTS,
+        .cons           = AR933X_SERIAL_CONSOLE,
+};
+
+static int __devinit ar933x_uart_probe(struct platform_device *pdev)
+{
+        struct ar933x_uart_platform_data *pdata;
+        struct ar933x_uart_port *up;
+        struct uart_port *port;
+        struct resource *mem_res;
+        struct resource *irq_res;
+        int id;
+        int ret;
+
+        pdata = pdev->dev.platform_data;
+        if (!pdata)
+                return -EINVAL;
+
+        id = pdev->id;
+        if (id == -1)
+                id = 0;
+
+        if (id > CONFIG_SERIAL_AR933X_NR_UARTS)
+                return -EINVAL;
+
+        mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!mem_res) {
+                dev_err(&pdev->dev, "no MEM resource\n");
+                return -EINVAL;
+        }
+
+        irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (!irq_res) {
+                dev_err(&pdev->dev, "no IRQ resource\n");
+                return -EINVAL;
+        }
+
+        up = kzalloc(sizeof(struct ar933x_uart_port), GFP_KERNEL);
+        if (!up)
+                return -ENOMEM;
+
+        port = &up->port;
+        port->mapbase = mem_res->start;
+
+        port->membase = ioremap(mem_res->start, AR933X_UART_REGS_SIZE);
+        if (!port->membase) {
+                ret = -ENOMEM;
+                goto err_free_up;
+        }
+
+        port->line = id;
+        port->irq = irq_res->start;
+        port->dev = &pdev->dev;
+        port->type = PORT_AR933X;
+        port->iotype = UPIO_MEM32;
+        port->uartclk = pdata->uartclk;
+
+        port->regshift = 2;
+        port->fifosize = AR933X_UART_FIFO_SIZE;
+        port->ops = &ar933x_uart_ops;
+
+        ar933x_uart_add_console_port(up);
+
+        ret = uart_add_one_port(&ar933x_uart_driver, &up->port);
+        if (ret)
+                goto err_unmap;
+
+        platform_set_drvdata(pdev, up);
+        return 0;
+
+err_unmap:
+        iounmap(up->port.membase);
+err_free_up:
+        kfree(up);
+        return ret;
+}
+
+static int __devexit ar933x_uart_remove(struct platform_device *pdev)
+{
+        struct ar933x_uart_port *up;
+
+        up = platform_get_drvdata(pdev);
+        platform_set_drvdata(pdev, NULL);
+
+        if (up) {
+                uart_remove_one_port(&ar933x_uart_driver, &up->port);
+                iounmap(up->port.membase);
+                kfree(up);
+        }
+
+        return 0;
+}
+
+static struct platform_driver ar933x_uart_platform_driver = {
+        .probe          = ar933x_uart_probe,
+        .remove         = __devexit_p(ar933x_uart_remove),
+        .driver         = {
+                .name           = DRIVER_NAME,
+                .owner          = THIS_MODULE,
+        },
+};
+
+static int __init ar933x_uart_init(void)
+{
+        int ret;
+
+        ar933x_uart_driver.nr = CONFIG_SERIAL_AR933X_NR_UARTS;
+        ret = uart_register_driver(&ar933x_uart_driver);
+        if (ret)
+                goto err_out;
+
+        ret = platform_driver_register(&ar933x_uart_platform_driver);
+        if (ret)
+                goto err_unregister_uart_driver;
+
+        return 0;
+
+err_unregister_uart_driver:
+        uart_unregister_driver(&ar933x_uart_driver);
+err_out:
+        return ret;
+}
+
+static void __exit ar933x_uart_exit(void)
+{
+        platform_driver_unregister(&ar933x_uart_platform_driver);
+        uart_unregister_driver(&ar933x_uart_driver);
+}
+
+module_init(ar933x_uart_init);
+module_exit(ar933x_uart_exit);
+
+MODULE_DESCRIPTION("Atheros AR933X UART driver");
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 060e0e2b1ae6..8b094b4f6531 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -210,7 +210,7 @@ config USB_CNS3XXX_EHCI
 
 config USB_EHCI_ATH79
         bool "EHCI support for AR7XXX/AR9XXX SoCs"
-        depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X)
+        depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X)
         select USB_EHCI_ROOT_HUB_TT
         default y
         ---help---
diff --git a/drivers/usb/host/alchemy-common.c b/drivers/usb/host/alchemy-common.c
index b4192c964d0d..936af8359fb2 100644
--- a/drivers/usb/host/alchemy-common.c
+++ b/drivers/usb/host/alchemy-common.c
@@ -52,9 +52,263 @@
                                  USBCFG_EBE | USBCFG_EME | USBCFG_OBE |        \
                                  USBCFG_OME)
 
+/* Au1300 USB config registers */
+#define USB_DWC_CTRL1           0x00
+#define USB_DWC_CTRL2           0x04
+#define USB_VBUS_TIMER          0x10
+#define USB_SBUS_CTRL           0x14
+#define USB_MSR_ERR             0x18
+#define USB_DWC_CTRL3           0x1C
+#define USB_DWC_CTRL4           0x20
+#define USB_OTG_STATUS          0x28
+#define USB_DWC_CTRL5           0x2C
+#define USB_DWC_CTRL6           0x30
+#define USB_DWC_CTRL7           0x34
+#define USB_PHY_STATUS          0xC0
+#define USB_INT_STATUS          0xC4
+#define USB_INT_ENABLE          0xC8
+
+#define USB_DWC_CTRL1_OTGD      0x04 /* set to DISable OTG */
+#define USB_DWC_CTRL1_HSTRS     0x02 /* set to ENable EHCI */
+#define USB_DWC_CTRL1_DCRS      0x01 /* set to ENable UDC */
+
+#define USB_DWC_CTRL2_PHY1RS    0x04 /* set to enable PHY1 */
+#define USB_DWC_CTRL2_PHY0RS    0x02 /* set to enable PHY0 */
+#define USB_DWC_CTRL2_PHYRS     0x01 /* set to enable PHY */
+
+#define USB_DWC_CTRL3_OHCI1_CKEN        (1 << 19)
+#define USB_DWC_CTRL3_OHCI0_CKEN        (1 << 18)
+#define USB_DWC_CTRL3_EHCI0_CKEN        (1 << 17)
+#define USB_DWC_CTRL3_OTG0_CKEN         (1 << 16)
+
+#define USB_SBUS_CTRL_SBCA              0x04 /* coherent access */
+
+#define USB_INTEN_FORCE                 0x20
+#define USB_INTEN_PHY                   0x10
+#define USB_INTEN_UDC                   0x08
+#define USB_INTEN_EHCI                  0x04
+#define USB_INTEN_OHCI1                 0x02
+#define USB_INTEN_OHCI0                 0x01
 
 static DEFINE_SPINLOCK(alchemy_usb_lock);
 
+static inline void __au1300_usb_phyctl(void __iomem *base, int enable)
+{
+        unsigned long r, s;
+
+        r = __raw_readl(base + USB_DWC_CTRL2);
+        s = __raw_readl(base + USB_DWC_CTRL3);
+
+        s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN |
+                USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN;
+
+        if (enable) {
+                /* simply enable all PHYs */
+                r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
+                     USB_DWC_CTRL2_PHYRS;
+                __raw_writel(r, base + USB_DWC_CTRL2);
+                wmb();
+        } else if (!s) {
+                /* no USB block active, do disable all PHYs */
+                r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
+                       USB_DWC_CTRL2_PHYRS);
+                __raw_writel(r, base + USB_DWC_CTRL2);
+                wmb();
+        }
+}
+
+static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
+{
+        unsigned long r;
+
+        if (enable) {
+                __raw_writel(1, base + USB_DWC_CTRL7);  /* start OHCI clock */
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL3);  /* enable OHCI block */
+                r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
+                               : USB_DWC_CTRL3_OHCI1_CKEN;
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);      /* power up the PHYs */
+
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1;
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+
+                /* reset the OHCI start clock bit */
+                __raw_writel(0, base + USB_DWC_CTRL7);
+                wmb();
+        } else {
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1);
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL3);
+                r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
+                                 : USB_DWC_CTRL3_OHCI1_CKEN);
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+        }
+}
+
+static inline void __au1300_ehci_control(void __iomem *base, int enable)
+{
+        unsigned long r;
+
+        if (enable) {
+                r = __raw_readl(base + USB_DWC_CTRL3);
+                r |= USB_DWC_CTRL3_EHCI0_CKEN;
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r |= USB_DWC_CTRL1_HSTRS;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r |= USB_INTEN_EHCI;
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+        } else {
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r &= ~USB_INTEN_EHCI;
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r &= ~USB_DWC_CTRL1_HSTRS;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL3);
+                r &= ~USB_DWC_CTRL3_EHCI0_CKEN;
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+        }
+}
+
+static inline void __au1300_udc_control(void __iomem *base, int enable)
+{
+        unsigned long r;
+
+        if (enable) {
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r |= USB_DWC_CTRL1_DCRS;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r |= USB_INTEN_UDC;
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+        } else {
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r &= ~USB_INTEN_UDC;
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r &= ~USB_DWC_CTRL1_DCRS;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+        }
+}
+
+static inline void __au1300_otg_control(void __iomem *base, int enable)
+{
+        unsigned long r;
+        if (enable) {
+                r = __raw_readl(base + USB_DWC_CTRL3);
+                r |= USB_DWC_CTRL3_OTG0_CKEN;
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r &= ~USB_DWC_CTRL1_OTGD;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+        } else {
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r |= USB_DWC_CTRL1_OTGD;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL3);
+                r &= ~USB_DWC_CTRL3_OTG0_CKEN;
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+        }
+}
+
+static inline int au1300_usb_control(int block, int enable)
+{
+        void __iomem *base =
+                (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
+        int ret = 0;
+
+        switch (block) {
+        case ALCHEMY_USB_OHCI0:
+                __au1300_ohci_control(base, enable, 0);
+                break;
+        case ALCHEMY_USB_OHCI1:
+                __au1300_ohci_control(base, enable, 1);
+                break;
+        case ALCHEMY_USB_EHCI0:
+                __au1300_ehci_control(base, enable);
+                break;
+        case ALCHEMY_USB_UDC0:
+                __au1300_udc_control(base, enable);
+                break;
+        case ALCHEMY_USB_OTG0:
+                __au1300_otg_control(base, enable);
+                break;
+        default:
+                ret = -ENODEV;
+        }
+        return ret;
+}
+
+static inline void au1300_usb_init(void)
+{
+        void __iomem *base =
+                (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
+
+        /* set some sane defaults.  Note: we don't fiddle with DWC_CTRL4
+         * here at all: Port 2 routing (EHCI or UDC) must be set either
+         * by boot firmware or platform init code; I can't autodetect
+         * a sane setting.
+         */
+        __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
+        wmb();
+        __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
+        wmb();
+        __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
+        wmb();
+        __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
+        wmb();
+        /* set coherent access bit */
+        __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
+        wmb();
+}
 
 static inline void __au1200_ohci_control(void __iomem *base, int enable)
 {
@@ -233,6 +487,9 @@ int alchemy_usb_control(int block, int enable)
         case ALCHEMY_CPU_AU1200:
                 ret = au1200_usb_control(block, enable);
                 break;
+        case ALCHEMY_CPU_AU1300:
+                ret = au1300_usb_control(block, enable);
+                break;
         default:
                 ret = -ENODEV;
         }
@@ -281,6 +538,20 @@ static void au1200_usb_pm(int susp)
         }
 }
 
+static void au1300_usb_pm(int susp)
+{
+        void __iomem *base =
+                        (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
+        /* remember Port2 routing */
+        if (susp) {
+                alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
+        } else {
+                au1300_usb_init();
+                __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);
+                wmb();
+        }
+}
+
 static void alchemy_usb_pm(int susp)
 {
         switch (alchemy_get_cputype()) {
@@ -295,6 +566,9 @@ static void alchemy_usb_pm(int susp)
         case ALCHEMY_CPU_AU1200:
                 au1200_usb_pm(susp);
                 break;
+        case ALCHEMY_CPU_AU1300:
+                au1300_usb_pm(susp);
+                break;
         }
 }
 
@@ -328,6 +602,9 @@ static int __init alchemy_usb_init(void)
         case ALCHEMY_CPU_AU1200:
                 au1200_usb_init();
                 break;
+        case ALCHEMY_CPU_AU1300:
+                au1300_usb_init();
+                break;
         }
 
         register_syscore_ops(&alchemy_usb_pm_ops);
diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c
index afb6743cf094..f1424f9bc363 100644
--- a/drivers/usb/host/ehci-ath79.c
+++ b/drivers/usb/host/ehci-ath79.c
@@ -33,6 +33,10 @@ static const struct platform_device_id ehci_ath79_id_table[] = {
                 .driver_data    = EHCI_ATH79_IP_V2,
         },
         {
+                .name           = "ar933x-ehci",
+                .driver_data    = EHCI_ATH79_IP_V2,
+        },
+        {
                 /* terminating entry */
         },
 };
diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c
index 9b66df8278f3..95d1a71dccad 100644
--- a/drivers/usb/host/ohci-au1xxx.c
+++ b/drivers/usb/host/ohci-au1xxx.c
@@ -89,7 +89,7 @@ static const struct hc_driver ohci_au1xxx_hc_driver = {
 
 static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
 {
-        int ret;
+        int ret, unit;
         struct usb_hcd *hcd;
 
         if (usb_disabled())
@@ -120,7 +120,9 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
                 goto err2;
         }
 
-        if (alchemy_usb_control(ALCHEMY_USB_OHCI0, 1)) {
+        unit = (hcd->rsrc_start == AU1300_USB_OHCI1_PHYS_ADDR) ?
+                        ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
+        if (alchemy_usb_control(unit, 1)) {
                 printk(KERN_INFO "%s: controller init failed!\n", pdev->name);
                 ret = -ENODEV;
                 goto err3;
@@ -135,7 +137,7 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
                 return ret;
         }
 
-        alchemy_usb_control(ALCHEMY_USB_OHCI0, 0);
+        alchemy_usb_control(unit, 0);
 err3:
         iounmap(hcd->regs);
 err2:
@@ -148,9 +150,12 @@ err1:
 static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev)
 {
         struct usb_hcd *hcd = platform_get_drvdata(pdev);
+        int unit;
 
+        unit = (hcd->rsrc_start == AU1300_USB_OHCI1_PHYS_ADDR) ?
+                        ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
         usb_remove_hcd(hcd);
-        alchemy_usb_control(ALCHEMY_USB_OHCI0, 0);
+        alchemy_usb_control(unit, 0);
         iounmap(hcd->regs);
         release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
         usb_put_hcd(hcd);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d83e967e4e15..acd4ba555e3a 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1763,16 +1763,16 @@ config FB_AU1100
           au1100fb:panel=<name>.
 
 config FB_AU1200
-        bool "Au1200 LCD Driver"
+        bool "Au1200/Au1300 LCD Driver"
         depends on (FB = y) && MIPS_ALCHEMY
         select FB_SYS_FILLRECT
         select FB_SYS_COPYAREA
         select FB_SYS_IMAGEBLIT
         select FB_SYS_FOPS
         help
-          This is the framebuffer driver for the AMD Au1200 SOC.  It can drive
-          various panels and CRTs by passing in kernel cmd line option
-          au1200fb:panel=<name>.
+          This is the framebuffer driver for the Au1200/Au1300 SOCs.
+          It can drive various panels and CRTs by passing in kernel cmd line
+          option au1200fb:panel=<name>.
 
 config FB_VT8500
         bool "VT8500 LCD Driver"
diff --git a/drivers/video/au1100fb.c b/drivers/video/au1100fb.c
index 649cb35de4ed..de9da6774fd9 100644
--- a/drivers/video/au1100fb.c
+++ b/drivers/video/au1100fb.c
@@ -60,18 +60,6 @@
 
 #include "au1100fb.h"
 
-/*
- * Sanity check. If this is a new Au1100 based board, search for
- * the PB1100 ifdefs to make sure you modify the code accordingly.
- */
-#if defined(CONFIG_MIPS_PB1100)
-  #include <asm/mach-pb1x00/pb1100.h>
-#elif defined(CONFIG_MIPS_DB1100)
-  #include <asm/mach-db1x00/db1x00.h>
-#else
-  #error "Unknown Au1100 board, Au1100 FB driver not supported"
-#endif
-
 #define DRIVER_NAME "au1100fb"
 #define DRIVER_DESC "LCD controller driver for AU1100 processors"
 
diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c
index 72005598040f..04e4479d5afd 100644
--- a/drivers/video/au1200fb.c
+++ b/drivers/video/au1200fb.c
@@ -44,6 +44,7 @@
 #include <linux/slab.h>
 
 #include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1200fb.h>   /* platform_data */
 #include "au1200fb.h"
 
 #define DRIVER_NAME "au1200fb"
@@ -143,6 +144,7 @@ struct au1200_lcd_iodata_t {
 /* Private, per-framebuffer management information (independent of the panel itself) */
 struct au1200fb_device {
         struct fb_info *fb_info;                /* FB driver info record */
+        struct au1200fb_platdata *pd;
 
         int                                     plane;
         unsigned char*          fb_mem;         /* FrameBuffer memory map */
@@ -201,9 +203,6 @@ struct window_settings {
 #define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_01
 #endif
 
-extern int board_au1200fb_panel_init (void);
-extern int board_au1200fb_panel_shutdown (void);
-
 /*
  * Default window configurations
  */
@@ -334,8 +333,6 @@ struct panel_settings
         uint32 mode_toyclksrc;
         uint32 mode_backlight;
         uint32 mode_auxpll;
-        int (*device_init)(void);
-        int (*device_shutdown)(void);
 #define Xres min_xres
 #define Yres min_yres
         u32     min_xres;               /* Minimum horizontal resolution */
@@ -385,8 +382,6 @@ static struct panel_settings known_lcd_panels[] =
                 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
                 .mode_backlight = 0x00000000,
                 .mode_auxpll            = 8, /* 96MHz AUXPLL */
-                .device_init            = NULL,
-                .device_shutdown        = NULL,
                 320, 320,
                 240, 240,
         },
@@ -415,8 +410,6 @@ static struct panel_settings known_lcd_panels[] =
                 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
                 .mode_backlight = 0x00000000,
                 .mode_auxpll            = 8, /* 96MHz AUXPLL */
-                .device_init            = NULL,
-                .device_shutdown        = NULL,
                 640, 480,
                 640, 480,
         },
@@ -445,8 +438,6 @@ static struct panel_settings known_lcd_panels[] =
                 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
                 .mode_backlight = 0x00000000,
                 .mode_auxpll            = 8, /* 96MHz AUXPLL */
-                .device_init            = NULL,
-                .device_shutdown        = NULL,
                 800, 800,
                 600, 600,
         },
@@ -475,8 +466,6 @@ static struct panel_settings known_lcd_panels[] =
                 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
                 .mode_backlight = 0x00000000,
                 .mode_auxpll            = 6, /* 72MHz AUXPLL */
-                .device_init            = NULL,
-                .device_shutdown        = NULL,
                 1024, 1024,
                 768, 768,
         },
@@ -505,8 +494,6 @@ static struct panel_settings known_lcd_panels[] =
                 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
                 .mode_backlight = 0x00000000,
                 .mode_auxpll            = 10, /* 120MHz AUXPLL */
-                .device_init            = NULL,
-                .device_shutdown        = NULL,
                 1280, 1280,
                 1024, 1024,
         },
@@ -535,8 +522,6 @@ static struct panel_settings known_lcd_panels[] =
                 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
                 .mode_backlight = 0x00000000,
                 .mode_auxpll            = 8, /* 96MHz AUXPLL */
-                .device_init            = board_au1200fb_panel_init,
-                .device_shutdown        = board_au1200fb_panel_shutdown,
                 1024, 1024,
                 768, 768,
         },
@@ -568,8 +553,6 @@ static struct panel_settings known_lcd_panels[] =
                 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
                 .mode_backlight = 0x00000000,
                 .mode_auxpll            = 8, /* 96MHz AUXPLL */
-                .device_init            = board_au1200fb_panel_init,
-                .device_shutdown        = board_au1200fb_panel_shutdown,
                 640, 480,
                 640, 480,
         },
@@ -601,8 +584,6 @@ static struct panel_settings known_lcd_panels[] =
                 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
                 .mode_backlight = 0x00000000,
                 .mode_auxpll            = 8, /* 96MHz AUXPLL */
-                .device_init            = board_au1200fb_panel_init,
-                .device_shutdown        = board_au1200fb_panel_shutdown,
                 320, 320,
                 240, 240,
         },
@@ -634,11 +615,43 @@ static struct panel_settings known_lcd_panels[] =
                 .mode_toyclksrc = 0x00000004, /* AUXPLL directly */
                 .mode_backlight = 0x00000000,
                 .mode_auxpll            = 8, /* 96MHz AUXPLL */
-                .device_init            = board_au1200fb_panel_init,
-                .device_shutdown        = board_au1200fb_panel_shutdown,
                 856, 856,
                 480, 480,
         },
+        [9] = {
+                .name = "DB1300_800x480",
+                .monspecs = {
+                        .modedb = NULL,
+                        .modedb_len = 0,
+                        .hfmin = 30000,
+                        .hfmax = 70000,
+                        .vfmin = 60,
+                        .vfmax = 60,
+                        .dclkmin = 6000000,
+                        .dclkmax = 28000000,
+                        .input = FB_DISP_RGB,
+                },
+                .mode_screen            = LCD_SCREEN_SX_N(800) |
+                                          LCD_SCREEN_SY_N(480),
+                .mode_horztiming        = LCD_HORZTIMING_HPW_N(5) |
+                                          LCD_HORZTIMING_HND1_N(16) |
+                                          LCD_HORZTIMING_HND2_N(8),
+                .mode_verttiming        = LCD_VERTTIMING_VPW_N(4) |
+                                          LCD_VERTTIMING_VND1_N(8) |
+                                          LCD_VERTTIMING_VND2_N(5),
+                .mode_clkcontrol        = LCD_CLKCONTROL_PCD_N(1) |
+                                          LCD_CLKCONTROL_IV |
+                                          LCD_CLKCONTROL_IH,
+                .mode_pwmdiv            = 0x00000000,
+                .mode_pwmhi             = 0x00000000,
+                .mode_outmask           = 0x00FFFFFF,
+                .mode_fifoctrl          = 0x2f2f2f2f,
+                .mode_toyclksrc         = 0x00000004, /* AUXPLL directly */
+                .mode_backlight         = 0x00000000,
+                .mode_auxpll            = (48/12) * 2,
+                800, 800,
+                480, 480,
+        },
 };
 
 #define NUM_PANELS (ARRAY_SIZE(known_lcd_panels))
@@ -764,7 +777,8 @@ static int au1200_setlocation (struct au1200fb_device *fbdev, int plane,
         return 0;
 }
 
-static void au1200_setpanel (struct panel_settings *newpanel)
+static void au1200_setpanel(struct panel_settings *newpanel,
+                            struct au1200fb_platdata *pd)
 {
         /*
          * Perform global setup/init of LCD controller
@@ -798,8 +812,8 @@ static void au1200_setpanel (struct panel_settings *newpanel)
                     the controller, the clock cannot be turned off before first
                         shutting down the controller.
                  */
-                if (panel->device_shutdown != NULL)
-                        panel->device_shutdown();
+                if (pd->panel_shutdown)
+                        pd->panel_shutdown();
         }
 
         /* Newpanel == NULL indicates a shutdown operation only */
@@ -852,7 +866,8 @@ static void au1200_setpanel (struct panel_settings *newpanel)
         au_sync();
 
         /* Call init of panel */
-        if (panel->device_init != NULL) panel->device_init();
+        if (pd->panel_init)
+                pd->panel_init();
 
         /* FIX!!!! not appropriate on panel change!!! Global setup/init */
         lcd->intenable = 0;
@@ -1185,6 +1200,8 @@ static int au1200fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green,
  */
 static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi)
 {
+        struct au1200fb_device *fbdev = fbi->par;
+
         /* Short-circuit screen blanking */
         if (noblanking)
                 return 0;
@@ -1194,13 +1211,13 @@ static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi)
         case FB_BLANK_UNBLANK:
         case FB_BLANK_NORMAL:
                 /* printk("turn on panel\n"); */
-                au1200_setpanel(panel);
+                au1200_setpanel(panel, fbdev->pd);
                 break;
         case FB_BLANK_VSYNC_SUSPEND:
         case FB_BLANK_HSYNC_SUSPEND:
         case FB_BLANK_POWERDOWN:
                 /* printk("turn off panel\n"); */
-                au1200_setpanel(NULL);
+                au1200_setpanel(NULL, fbdev->pd);
                 break;
         default:
                 break;
@@ -1428,6 +1445,7 @@ static void get_window(unsigned int plane,
 static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd,
                           unsigned long arg)
 {
+        struct au1200fb_device *fbdev = info->par;
         int plane;
         int val;
 
@@ -1472,7 +1490,7 @@ static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd,
                                 struct panel_settings *newpanel;
                                 panel_index = iodata.global.panel_choice;
                                 newpanel = &known_lcd_panels[panel_index];
-                                au1200_setpanel(newpanel);
+                                au1200_setpanel(newpanel, fbdev->pd);
                         }
                         break;
 
@@ -1588,22 +1606,102 @@ static int au1200fb_init_fbinfo(struct au1200fb_device *fbdev)
 
 /*-------------------------------------------------------------------------*/
 
-/* AU1200 LCD controller device driver */
 
+static int au1200fb_setup(struct au1200fb_platdata *pd)
+{
+        char *options = NULL;
+        char *this_opt, *endptr;
+        int num_panels = ARRAY_SIZE(known_lcd_panels);
+        int panel_idx = -1;
+
+        fb_get_options(DRIVER_NAME, &options);
+
+        if (!options)
+                goto out;
+
+        while ((this_opt = strsep(&options, ",")) != NULL) {
+                /* Panel option - can be panel name,
+                 * "bs" for board-switch, or number/index */
+                if (!strncmp(this_opt, "panel:", 6)) {
+                        int i;
+                        long int li;
+                        char *endptr;
+                        this_opt += 6;
+                        /* First check for index, which allows
+                         * to short circuit this mess */
+                        li = simple_strtol(this_opt, &endptr, 0);
+                        if (*endptr == '\0')
+                                panel_idx = (int)li;
+                        else if (strcmp(this_opt, "bs") == 0)
+                                panel_idx = pd->panel_index();
+                        else {
+                                for (i = 0; i < num_panels; i++) {
+                                        if (!strcmp(this_opt,
+                                                    known_lcd_panels[i].name)) {
+                                                panel_idx = i;
+                                                break;
+                                        }
+                                }
+                        }
+                        if ((panel_idx < 0) || (panel_idx >= num_panels))
+                                print_warn("Panel %s not supported!", this_opt);
+                        else
+                                panel_index = panel_idx;
+
+                } else if (strncmp(this_opt, "nohwcursor", 10) == 0)
+                        nohwcursor = 1;
+                else if (strncmp(this_opt, "devices:", 8) == 0) {
+                        this_opt += 8;
+                        device_count = simple_strtol(this_opt, &endptr, 0);
+                        if ((device_count < 0) ||
+                            (device_count > MAX_DEVICE_COUNT))
+                                device_count = MAX_DEVICE_COUNT;
+                } else if (strncmp(this_opt, "wincfg:", 7) == 0) {
+                        this_opt += 7;
+                        window_index = simple_strtol(this_opt, &endptr, 0);
+                        if ((window_index < 0) ||
+                            (window_index >= ARRAY_SIZE(windows)))
+                                window_index = DEFAULT_WINDOW_INDEX;
+                } else if (strncmp(this_opt, "off", 3) == 0)
+                        return 1;
+                else
+                        print_warn("Unsupported option \"%s\"", this_opt);
+        }
+
+out:
+        return 0;
+}
+
+/* AU1200 LCD controller device driver */
 static int __devinit au1200fb_drv_probe(struct platform_device *dev)
 {
         struct au1200fb_device *fbdev;
+        struct au1200fb_platdata *pd;
         struct fb_info *fbi = NULL;
         unsigned long page;
         int bpp, plane, ret, irq;
 
+        print_info("" DRIVER_DESC "");
+
+        pd = dev->dev.platform_data;
+        if (!pd)
+                return -ENODEV;
+
+        /* Setup driver with options */
+        if (au1200fb_setup(pd))
+                return -ENODEV;
+
+        /* Point to the panel selected */
+        panel = &known_lcd_panels[panel_index];
+        win = &windows[window_index];
+
+        printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name);
+        printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name);
+
         /* shut gcc up */
         ret = 0;
         fbdev = NULL;
 
-        /* Kickstart the panel */
-        au1200_setpanel(panel);
-
         for (plane = 0; plane < device_count; ++plane) {
                 bpp = winbpp(win->w[plane].mode_winctrl1);
                 if (win->w[plane].xres == 0)
@@ -1619,6 +1717,7 @@ static int __devinit au1200fb_drv_probe(struct platform_device *dev)
                 _au1200fb_infos[plane] = fbi;
                 fbdev = fbi->par;
                 fbdev->fb_info = fbi;
+                fbdev->pd = pd;
 
                 fbdev->plane = plane;
 
@@ -1680,6 +1779,11 @@ static int __devinit au1200fb_drv_probe(struct platform_device *dev)
                 goto failed;
         }
 
+        platform_set_drvdata(dev, pd);
+
+        /* Kickstart the panel */
+        au1200_setpanel(panel, pd);
+
         return 0;
 
 failed:
@@ -1699,12 +1803,13 @@ failed:
 
 static int __devexit au1200fb_drv_remove(struct platform_device *dev)
 {
+        struct au1200fb_platdata *pd = platform_get_drvdata(dev);
         struct au1200fb_device *fbdev;
         struct fb_info *fbi;
         int plane;
 
         /* Turn off the panel */
-        au1200_setpanel(NULL);
+        au1200_setpanel(NULL, pd);
 
         for (plane = 0; plane < device_count; ++plane)  {
                 fbi = _au1200fb_infos[plane];
@@ -1732,7 +1837,8 @@ static int __devexit au1200fb_drv_remove(struct platform_device *dev)
 #ifdef CONFIG_PM
 static int au1200fb_drv_suspend(struct device *dev)
 {
-        au1200_setpanel(NULL);
+        struct au1200fb_platdata *pd = dev_get_drvdata(dev);
+        au1200_setpanel(NULL, pd);
 
         lcd->outmask = 0;
         au_sync();
@@ -1742,11 +1848,12 @@ static int au1200fb_drv_suspend(struct device *dev)
 
 static int au1200fb_drv_resume(struct device *dev)
 {
+        struct au1200fb_platdata *pd = dev_get_drvdata(dev);
         struct fb_info *fbi;
         int i;
 
         /* Kickstart the panel */
-        au1200_setpanel(panel);
+        au1200_setpanel(panel, pd);
 
         for (i = 0; i < device_count; i++) {
                 fbi = _au1200fb_infos[i];
@@ -1781,100 +1888,8 @@ static struct platform_driver au1200fb_driver = {
 
 /*-------------------------------------------------------------------------*/
 
-/* Kernel driver */
-
-static int au1200fb_setup(void)
-{
-        char *options = NULL;
-        char *this_opt, *endptr;
-        int num_panels = ARRAY_SIZE(known_lcd_panels);
-        int panel_idx = -1;
-
-        fb_get_options(DRIVER_NAME, &options);
-
-        if (options) {
-                while ((this_opt = strsep(&options,",")) != NULL) {
-                        /* Panel option - can be panel name,
-                         * "bs" for board-switch, or number/index */
-                        if (!strncmp(this_opt, "panel:", 6)) {
-                                int i;
-                                long int li;
-                                char *endptr;
-                                this_opt += 6;
-                                /* First check for index, which allows
-                                 * to short circuit this mess */
-                                li = simple_strtol(this_opt, &endptr, 0);
-                                if (*endptr == '\0') {
-                                        panel_idx = (int)li;
-                                }
-                                else if (strcmp(this_opt, "bs") == 0) {
-                                        extern int board_au1200fb_panel(void);
-                                        panel_idx = board_au1200fb_panel();
-                                }
-
-                                else
-                                for (i = 0; i < num_panels; i++) {
-                                        if (!strcmp(this_opt, known_lcd_panels[i].name)) {
-                                                panel_idx = i;
-                                                break;
-                                        }
-                                }
-
-                                if ((panel_idx < 0) || (panel_idx >= num_panels)) {
-                                                print_warn("Panel %s not supported!", this_opt);
-                                }
-                                else
-                                        panel_index = panel_idx;
-                        }
-
-                        else if (strncmp(this_opt, "nohwcursor", 10) == 0) {
-                                nohwcursor = 1;
-                        }
-
-                        else if (strncmp(this_opt, "devices:", 8) == 0) {
-                                this_opt += 8;
-                                device_count = simple_strtol(this_opt,
-                                                             &endptr, 0);
-                                if ((device_count < 0) ||
-                                    (device_count > MAX_DEVICE_COUNT))
-                                        device_count = MAX_DEVICE_COUNT;
-                        }
-
-                        else if (strncmp(this_opt, "wincfg:", 7) == 0) {
-                                this_opt += 7;
-                                window_index = simple_strtol(this_opt,
-                                                             &endptr, 0);
-                                if ((window_index < 0) ||
-                                    (window_index >= ARRAY_SIZE(windows)))
-                                        window_index = DEFAULT_WINDOW_INDEX;
-                        }
-
-                        else if (strncmp(this_opt, "off", 3) == 0)
-                                return 1;
-                        /* Unsupported option */
-                        else {
-                                print_warn("Unsupported option \"%s\"", this_opt);
-                        }
-                }
-        }
-        return 0;
-}
-
 static int __init au1200fb_init(void)
 {
-        print_info("" DRIVER_DESC "");
-
-        /* Setup driver with options */
-        if (au1200fb_setup())
-                return -ENODEV;
-
-        /* Point to the panel selected */
-        panel = &known_lcd_panels[panel_index];
-        win = &windows[window_index];
-
-        printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name);
-        printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name);
-
         return platform_driver_register(&au1200fb_driver);
 }
 
diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c
index 93317b5b8740..a122d9287d16 100644
--- a/drivers/video/console/newport_con.c
+++ b/drivers/video/console/newport_con.c
@@ -25,14 +25,13 @@
 #include <asm/system.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
+#include <asm/gio_device.h>
+
 #include <video/newport.h>
 
 #include <linux/linux_logo.h>
 #include <linux/font.h>
 
-
-extern unsigned long sgi_gfxaddr;
-
 #define FONT_DATA ((unsigned char *)font_vga_8x16.data)
 
 /* borrowed from fbcon.c */
@@ -304,12 +303,6 @@ static const char *newport_startup(void)
 {
         int i;
 
-        if (!sgi_gfxaddr)
-                return NULL;
-
-        if (!npregs)
-                npregs = (struct newport_regs *)/* ioremap cannot fail */
-                        ioremap(sgi_gfxaddr, sizeof(struct newport_regs));
         npregs->cset.config = NPORT_CFG_GD0;
 
         if (newport_wait(npregs))
@@ -743,26 +736,58 @@ const struct consw newport_con = {
         .con_save_screen  = DUMMY
 };
 
-#ifdef MODULE
-static int __init newport_console_init(void)
+static int newport_probe(struct gio_device *dev,
+                         const struct gio_device_id *id)
 {
-        if (!sgi_gfxaddr)
-                return 0;
+        unsigned long newport_addr;
 
-        if (!npregs)
-                npregs = (struct newport_regs *)/* ioremap cannot fail */
-                        ioremap(sgi_gfxaddr, sizeof(struct newport_regs));
+        if (!dev->resource.start)
+                return -EINVAL;
+
+        if (npregs)
+                return -EBUSY; /* we only support one Newport as console */
+
+        newport_addr = dev->resource.start + 0xF0000;
+        if (!request_mem_region(newport_addr, 0x10000, "Newport"))
+                return -ENODEV;
+
+        npregs = (struct newport_regs *)/* ioremap cannot fail */
+                ioremap(newport_addr, sizeof(struct newport_regs));
 
         return take_over_console(&newport_con, 0, MAX_NR_CONSOLES - 1, 1);
 }
-module_init(newport_console_init);
 
-static void __exit newport_console_exit(void)
+static void newport_remove(struct gio_device *dev)
 {
         give_up_console(&newport_con);
         iounmap((void *)npregs);
 }
+
+static struct gio_device_id newport_ids[] = {
+        { .id = 0x7e },
+        { .id = 0xff }
+};
+
+MODULE_ALIAS("gio:7e");
+
+static struct gio_driver newport_driver = {
+        .name = "newport",
+        .id_table = newport_ids,
+        .probe = newport_probe,
+        .remove = newport_remove,
+};
+
+int __init newport_console_init(void)
+{
+        return gio_register_driver(&newport_driver);
+}
+
+void __exit newport_console_exit(void)
+{
+        gio_unregister_driver(&newport_driver);
+}
+
+module_init(newport_console_init);
 module_exit(newport_console_exit);
-#endif
 
 MODULE_LICENSE("GPL");
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index eadf33d0abba..3c35fb2f688f 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -207,6 +207,10 @@
 /* Xilinx PSS UART */
 #define PORT_XUARTPS    98
 
+/* Atheros AR933X SoC */
+#define PORT_AR933X     99
+
+
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>
diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig
index e908a8123110..a56104040e83 100644
--- a/sound/soc/au1x/Kconfig
+++ b/sound/soc/au1x/Kconfig
@@ -1,13 +1,13 @@
 ##
-## Au1200/Au1550 PSC + DBDMA
+## Au1200/Au1550/Au1300 PSC + DBDMA
 ##
 config SND_SOC_AU1XPSC
-        tristate "SoC Audio for Au1200/Au1250/Au1550"
+        tristate "SoC Audio for Au12xx/Au13xx/Au1550"
         depends on MIPS_ALCHEMY
         help
           This option enables support for the Programmable Serial
           Controllers in AC97 and I2S mode, and the Descriptor-Based DMA
-          Controller (DBDMA) as found on the Au1200/Au1250/Au1550 SoC.
+          Controller (DBDMA) as found on the Au12xx/Au13xx/Au1550 SoC.
 
 config SND_SOC_AU1XPSC_I2S
         tristate
@@ -51,12 +51,14 @@ config SND_SOC_DB1000
           of boards (DB1000/DB1500/DB1100).
 
 config SND_SOC_DB1200
-        tristate "DB1200 AC97+I2S audio support"
+        tristate "DB1200/DB1300/DB1550 Audio support"
         depends on SND_SOC_AU1XPSC
         select SND_SOC_AU1XPSC_AC97
         select SND_SOC_AC97_CODEC
+        select SND_SOC_WM9712
         select SND_SOC_AU1XPSC_I2S
         select SND_SOC_WM8731
         help
-          Select this option to enable audio (AC97 or I2S) on the
-          Alchemy/AMD/RMI DB1200 demoboard.
+          Select this option to enable audio (AC97 and I2S) on the
+          Alchemy/AMD/RMI/NetLogic Db1200, Db1550 and Db1300 evaluation boards.
+          If you need Db1300 touchscreen support, you definitely want to say Y.
diff --git a/sound/soc/au1x/db1200.c b/sound/soc/au1x/db1200.c
index 289312c14b99..44ad11827364 100644
--- a/sound/soc/au1x/db1200.c
+++ b/sound/soc/au1x/db1200.c
@@ -1,5 +1,5 @@
 /*
- * DB1200 ASoC audio fabric support code.
+ * DB1200/DB1300/DB1550 ASoC audio fabric support code.
  *
  * (c) 2008-2011 Manuel Lauss <manuel.lauss@googlemail.com>
  *
@@ -28,6 +28,18 @@ static struct platform_device_id db1200_pids[] = {
         }, {
                 .name           = "db1200-i2s",
                 .driver_data    = 1,
+        }, {
+                .name           = "db1300-ac97",
+                .driver_data    = 2,
+        }, {
+                .name           = "db1300-i2s",
+                .driver_data    = 3,
+        }, {
+                .name           = "db1550-ac97",
+                .driver_data    = 4,
+        }, {
+                .name           = "db1550-i2s",
+                .driver_data    = 5,
         },
         {},
 };
@@ -49,6 +61,27 @@ static struct snd_soc_card db1200_ac97_machine = {
         .num_links      = 1,
 };
 
+static struct snd_soc_dai_link db1300_ac97_dai = {
+        .name           = "AC97",
+        .stream_name    = "AC97 HiFi",
+        .codec_dai_name = "wm9712-hifi",
+        .cpu_dai_name   = "au1xpsc_ac97.1",
+        .platform_name  = "au1xpsc-pcm.1",
+        .codec_name     = "wm9712-codec.1",
+};
+
+static struct snd_soc_card db1300_ac97_machine = {
+        .name           = "DB1300_AC97",
+        .dai_link       = &db1300_ac97_dai,
+        .num_links      = 1,
+};
+
+static struct snd_soc_card db1550_ac97_machine = {
+        .name           = "DB1550_AC97",
+        .dai_link       = &db1200_ac97_dai,
+        .num_links      = 1,
+};
+
 /*-------------------------  I2S PART  ---------------------------*/
 
 static int db1200_i2s_startup(struct snd_pcm_substream *substream)
@@ -98,11 +131,47 @@ static struct snd_soc_card db1200_i2s_machine = {
         .num_links      = 1,
 };
 
+static struct snd_soc_dai_link db1300_i2s_dai = {
+        .name           = "WM8731",
+        .stream_name    = "WM8731 PCM",
+        .codec_dai_name = "wm8731-hifi",
+        .cpu_dai_name   = "au1xpsc_i2s.2",
+        .platform_name  = "au1xpsc-pcm.2",
+        .codec_name     = "wm8731.0-001b",
+        .ops            = &db1200_i2s_wm8731_ops,
+};
+
+static struct snd_soc_card db1300_i2s_machine = {
+        .name           = "DB1300_I2S",
+        .dai_link       = &db1300_i2s_dai,
+        .num_links      = 1,
+};
+
+static struct snd_soc_dai_link db1550_i2s_dai = {
+        .name           = "WM8731",
+        .stream_name    = "WM8731 PCM",
+        .codec_dai_name = "wm8731-hifi",
+        .cpu_dai_name   = "au1xpsc_i2s.3",
+        .platform_name  = "au1xpsc-pcm.3",
+        .codec_name     = "wm8731.0-001b",
+        .ops            = &db1200_i2s_wm8731_ops,
+};
+
+static struct snd_soc_card db1550_i2s_machine = {
+        .name           = "DB1550_I2S",
+        .dai_link       = &db1550_i2s_dai,
+        .num_links      = 1,
+};
+
 /*-------------------------  COMMON PART  ---------------------------*/
 
 static struct snd_soc_card *db1200_cards[] __devinitdata = {
         &db1200_ac97_machine,
         &db1200_i2s_machine,
+        &db1300_ac97_machine,
+        &db1300_i2s_machine,
+        &db1550_ac97_machine,
+        &db1550_i2s_machine,
 };
 
 static int __devinit db1200_audio_probe(struct platform_device *pdev)
@@ -147,5 +216,5 @@ module_init(db1200_audio_load);
 module_exit(db1200_audio_unload);
 
 MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("DB1200 ASoC audio support");
+MODULE_DESCRIPTION("DB1200/DB1300/DB1550 ASoC audio support");
 MODULE_AUTHOR("Manuel Lauss");