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-rw-r--r--arch/arm/mach-shmobile/Kconfig7
-rw-r--r--arch/arm/mach-shmobile/Makefile2
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c378
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h6
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h584
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7740.c45
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c246
-rw-r--r--drivers/tty/serial/sh-sci.h4
8 files changed, 1271 insertions, 1 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0828fab2b65c..329a3cb7f99b 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -28,6 +28,13 @@ config ARCH_SH73A0
28 select ARM_GIC 28 select ARM_GIC
29 select I2C 29 select I2C
30 30
31config ARCH_R8A7740
32 bool "R-Mobile A1 (R8A77400)"
33 select CPU_V7
34 select SH_CLK_CPG
35 select ARCH_WANT_OPTIONAL_GPIOLIB
36 select ARM_GIC
37
31comment "SH-Mobile Board Type" 38comment "SH-Mobile Board Type"
32 39
33config MACH_G3EVM 40config MACH_G3EVM
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 2aec2f732515..d61f1eca159a 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o 10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
13obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
13 14
14# SMP objects 15# SMP objects
15smp-y := platsmp.o headsmp.o 16smp-y := platsmp.o headsmp.o
@@ -29,6 +30,7 @@ obj-$(CONFIG_ARCH_SH7367) += entry-intc.o
29obj-$(CONFIG_ARCH_SH7377) += entry-intc.o 30obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
30obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 31obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
31obj-$(CONFIG_ARCH_SH73A0) += entry-gic.o 32obj-$(CONFIG_ARCH_SH73A0) += entry-gic.o
33obj-$(CONFIG_ARCH_R8A7740) += entry-gic.o
32 34
33# PM objects 35# PM objects
34obj-$(CONFIG_SUSPEND) += suspend.o 36obj-$(CONFIG_SUSPEND) += suspend.o
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
new file mode 100644
index 000000000000..5bb02f224077
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -0,0 +1,378 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26#include <mach/r8a7740.h>
27
28/*
29 * | MDx | XTAL1/EXTAL1 | System | EXTALR |
30 * Clock |-------+-----------------+ clock | 32.768 | RCLK
31 * Mode | 2/1/0 | src MHz | source | KHz | source
32 * -------+-------+-----------------+-----------+--------+----------
33 * 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
34 * 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
35 * 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
36 * 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
37 * 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
38 * 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
39 * 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
40 * 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
41 */
42
43/* CPG registers */
44#define FRQCRA 0xe6150000
45#define FRQCRB 0xe6150004
46#define FRQCRC 0xe61500e0
47#define PLLC01CR 0xe6150028
48
49#define SUBCKCR 0xe6150080
50
51#define MSTPSR0 0xe6150030
52#define MSTPSR1 0xe6150038
53#define MSTPSR2 0xe6150040
54#define MSTPSR3 0xe6150048
55#define MSTPSR4 0xe615004c
56#define SMSTPCR0 0xe6150130
57#define SMSTPCR1 0xe6150134
58#define SMSTPCR2 0xe6150138
59#define SMSTPCR3 0xe615013c
60#define SMSTPCR4 0xe6150140
61
62/* Fixed 32 KHz root clock from EXTALR pin */
63static struct clk extalr_clk = {
64 .rate = 32768,
65};
66
67/*
68 * 25MHz default rate for the EXTAL1 root input clock.
69 * If needed, reset this with clk_set_rate() from the platform code.
70 */
71static struct clk extal1_clk = {
72 .rate = 25000000,
73};
74
75/*
76 * 48MHz default rate for the EXTAL2 root input clock.
77 * If needed, reset this with clk_set_rate() from the platform code.
78 */
79static struct clk extal2_clk = {
80 .rate = 48000000,
81};
82
83/*
84 * 27MHz default rate for the DV_CLKI root input clock.
85 * If needed, reset this with clk_set_rate() from the platform code.
86 */
87static struct clk dv_clk = {
88 .rate = 27000000,
89};
90
91static unsigned long div_recalc(struct clk *clk)
92{
93 return clk->parent->rate / (int)(clk->priv);
94}
95
96static struct clk_ops div_clk_ops = {
97 .recalc = div_recalc,
98};
99
100/* extal1 / 2 */
101static struct clk extal1_div2_clk = {
102 .ops = &div_clk_ops,
103 .priv = (void *)2,
104 .parent = &extal1_clk,
105};
106
107/* extal1 / 1024 */
108static struct clk extal1_div1024_clk = {
109 .ops = &div_clk_ops,
110 .priv = (void *)1024,
111 .parent = &extal1_clk,
112};
113
114/* extal1 / 2 / 1024 */
115static struct clk extal1_div2048_clk = {
116 .ops = &div_clk_ops,
117 .priv = (void *)1024,
118 .parent = &extal1_div2_clk,
119};
120
121/* extal2 / 2 */
122static struct clk extal2_div2_clk = {
123 .ops = &div_clk_ops,
124 .priv = (void *)2,
125 .parent = &extal2_clk,
126};
127
128static struct clk_ops followparent_clk_ops = {
129 .recalc = followparent_recalc,
130};
131
132/* Main clock */
133static struct clk system_clk = {
134 .ops = &followparent_clk_ops,
135};
136
137static struct clk system_div2_clk = {
138 .ops = &div_clk_ops,
139 .priv = (void *)2,
140 .parent = &system_clk,
141};
142
143/* r_clk */
144static struct clk r_clk = {
145 .ops = &followparent_clk_ops,
146};
147
148/* PLLC0/PLLC1 */
149static unsigned long pllc01_recalc(struct clk *clk)
150{
151 unsigned long mult = 1;
152
153 if (__raw_readl(PLLC01CR) & (1 << 14))
154 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
155
156 return clk->parent->rate * mult;
157}
158
159static struct clk_ops pllc01_clk_ops = {
160 .recalc = pllc01_recalc,
161};
162
163static struct clk pllc0_clk = {
164 .ops = &pllc01_clk_ops,
165 .flags = CLK_ENABLE_ON_INIT,
166 .parent = &system_clk,
167 .enable_reg = (void __iomem *)FRQCRC,
168};
169
170static struct clk pllc1_clk = {
171 .ops = &pllc01_clk_ops,
172 .flags = CLK_ENABLE_ON_INIT,
173 .parent = &system_div2_clk,
174 .enable_reg = (void __iomem *)FRQCRA,
175};
176
177/* PLLC1 / 2 */
178static struct clk pllc1_div2_clk = {
179 .ops = &div_clk_ops,
180 .priv = (void *)2,
181 .parent = &pllc1_clk,
182};
183
184struct clk *main_clks[] = {
185 &extalr_clk,
186 &extal1_clk,
187 &extal2_clk,
188 &extal1_div2_clk,
189 &extal1_div1024_clk,
190 &extal1_div2048_clk,
191 &extal2_div2_clk,
192 &dv_clk,
193 &system_clk,
194 &system_div2_clk,
195 &r_clk,
196 &pllc0_clk,
197 &pllc1_clk,
198 &pllc1_div2_clk,
199};
200
201static void div4_kick(struct clk *clk)
202{
203 unsigned long value;
204
205 /* set KICK bit in FRQCRB to update hardware setting */
206 value = __raw_readl(FRQCRB);
207 value |= (1 << 31);
208 __raw_writel(value, FRQCRB);
209}
210
211static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
212 24, 32, 36, 48, 0, 72, 96, 0 };
213
214static struct clk_div_mult_table div4_div_mult_table = {
215 .divisors = divisors,
216 .nr_divisors = ARRAY_SIZE(divisors),
217};
218
219static struct clk_div4_table div4_table = {
220 .div_mult_table = &div4_div_mult_table,
221 .kick = div4_kick,
222};
223
224enum {
225 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
226 DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
227 DIV4_NR
228};
229
230struct clk div4_clks[DIV4_NR] = {
231 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
232 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
233 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
234 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
235 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
236 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
237 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
238 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
239 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
240 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
241};
242
243enum {
244 DIV6_SUB,
245 DIV6_NR
246};
247
248static struct clk div6_clks[DIV6_NR] = {
249 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
250};
251
252enum {
253 MSTP125,
254 MSTP116, MSTP111,
255
256 MSTP230,
257 MSTP222,
258 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
259
260 MSTP329, MSTP323,
261
262 MSTP_NR
263};
264
265static struct clk mstp_clks[MSTP_NR] = {
266 [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
267 [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
268 [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
269
270 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
271 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
272 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
273 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
274 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
275 [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
276 [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
277 [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
278 [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
279
280 [MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
281 [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
282};
283
284static struct clk_lookup lookups[] = {
285 /* main clocks */
286 CLKDEV_CON_ID("extalr", &extalr_clk),
287 CLKDEV_CON_ID("extal1", &extal1_clk),
288 CLKDEV_CON_ID("extal2", &extal2_clk),
289 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
290 CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
291 CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
292 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
293 CLKDEV_CON_ID("dv_clk", &dv_clk),
294 CLKDEV_CON_ID("system_clk", &system_clk),
295 CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
296 CLKDEV_CON_ID("r_clk", &r_clk),
297 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
298 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
299 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
300
301 /* DIV4 clocks */
302 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
303 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
304 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
305 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
306 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
307 CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
308 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
309 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
310 CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
311 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
312
313 /* DIV6 clocks */
314 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
315
316 /* MSTP32 clocks */
317 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
318 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
319 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
320
321 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
322 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
323 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
324 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
325 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
326 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
327 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
328
329 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
330 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
331
332 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
333 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
334};
335
336void __init r8a7740_clock_init(u8 md_ck)
337{
338 int k, ret = 0;
339
340 /* detect system clock parent */
341 if (md_ck & MD_CK1)
342 system_clk.parent = &extal1_div2_clk;
343 else
344 system_clk.parent = &extal1_clk;
345
346 /* detect RCLK parent */
347 switch (md_ck & (MD_CK2 | MD_CK1)) {
348 case MD_CK2 | MD_CK1:
349 r_clk.parent = &extal1_div2048_clk;
350 break;
351 case MD_CK2:
352 r_clk.parent = &extal1_div1024_clk;
353 break;
354 case MD_CK1:
355 default:
356 r_clk.parent = &extalr_clk;
357 break;
358 }
359
360 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
361 ret = clk_register(main_clks[k]);
362
363 if (!ret)
364 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
365
366 if (!ret)
367 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
368
369 if (!ret)
370 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
371
372 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
373
374 if (!ret)
375 clk_init();
376 else
377 panic("failed to setup r8a7740 clocks\n");
378}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 834bd6cd508f..5055a00a83d4 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -53,4 +53,10 @@ extern void sh73a0_secondary_init(unsigned int cpu);
53extern int sh73a0_boot_secondary(unsigned int cpu); 53extern int sh73a0_boot_secondary(unsigned int cpu);
54extern void sh73a0_smp_prepare_cpus(void); 54extern void sh73a0_smp_prepare_cpus(void);
55 55
56extern void r8a7740_init_irq(void);
57extern void r8a7740_add_early_devices(void);
58extern void r8a7740_add_standard_devices(void);
59extern void r8a7740_clock_init(u8 md_ck);
60extern void r8a7740_pinmux_init(void);
61
56#endif /* __ARCH_MACH_COMMON_H */ 62#endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
new file mode 100644
index 000000000000..9d447abb969c
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -0,0 +1,584 @@
1/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_R8A7740_H__
20#define __ASM_R8A7740_H__
21
22/*
23 * MD_CKx pin
24 */
25#define MD_CK2 (1 << 2)
26#define MD_CK1 (1 << 1)
27#define MD_CK0 (1 << 0)
28
29/*
30 * Pin Function Controller:
31 * GPIO_FN_xx - GPIO used to select pin function
32 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
33 */
34enum {
35 /* PORT */
36 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
37 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
38
39 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
40 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
41
42 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
43 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
44
45 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
46 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
47
48 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
49 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
50
51 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
52 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
53
54 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
55 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
56
57 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
58 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
59
60 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
61 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
62
63 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
64 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
65
66 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
67 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
68
69 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
70 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
71
72 GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
73 GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
74
75 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
76 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
77
78 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
79 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
80
81 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
82 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
83
84 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
85 GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
86
87 GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
88 GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
89
90 GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
91 GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
92
93 GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
94 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
95
96 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
97 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
98
99 GPIO_PORT210, GPIO_PORT211,
100
101 /* IRQ */
102 GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
103 GPIO_FN_IRQ1,
104 GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
105 GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
106 GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
107 GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
108 GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
109 GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
110 GPIO_FN_IRQ8,
111 GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
112 GPIO_FN_IRQ10,
113 GPIO_FN_IRQ11,
114 GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
115 GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
116 GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
117 GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
118 GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
119 GPIO_FN_IRQ17,
120 GPIO_FN_IRQ18,
121 GPIO_FN_IRQ19,
122 GPIO_FN_IRQ20,
123 GPIO_FN_IRQ21,
124 GPIO_FN_IRQ22,
125 GPIO_FN_IRQ23,
126 GPIO_FN_IRQ24,
127 GPIO_FN_IRQ25,
128 GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
129 GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
130 GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
131 GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
132 GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
133 GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
134
135 /* Function */
136
137 /* DBGT */
138 GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
139 GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
140 GPIO_FN_DBGMD21,
141
142 /* FSI */
143 GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
144 GPIO_FN_FSIAISLD_PORT5,
145 GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
146 GPIO_FN_FSIASPDIF_PORT18,
147 GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
148 GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
149 GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
150 GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
151 GPIO_FN_FSIAIBT,
152
153 /* FMSI */
154 GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
155 GPIO_FN_FMSISLD_PORT6,
156 GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
157 GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
158 GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
159 GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
160 GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
161 GPIO_FN_FMSOCK,
162
163 /* SCIFA0 */
164 GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
165 GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
166 GPIO_FN_SCIFA0_TXD,
167
168 /* SCIFA1 */
169 GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
170 GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
171 GPIO_FN_SCIFA1_RTS,
172
173 /* SCIFA2 */
174 GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
175 GPIO_FN_SCIFA2_SCK_PORT199,
176 GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
177 GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
178
179 /* SCIFA3 */
180 GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
181 GPIO_FN_SCIFA3_SCK_PORT116,
182 GPIO_FN_SCIFA3_CTS_PORT117,
183 GPIO_FN_SCIFA3_RXD_PORT174,
184 GPIO_FN_SCIFA3_TXD_PORT175,
185
186 GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
187 GPIO_FN_SCIFA3_SCK_PORT158,
188 GPIO_FN_SCIFA3_CTS_PORT162,
189 GPIO_FN_SCIFA3_RXD_PORT159,
190 GPIO_FN_SCIFA3_TXD_PORT160,
191
192 /* SCIFA4 */
193 GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
194 GPIO_FN_SCIFA4_TXD_PORT13,
195
196 GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
197 GPIO_FN_SCIFA4_TXD_PORT203,
198
199 GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
200 GPIO_FN_SCIFA4_TXD_PORT93,
201
202 GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
203 GPIO_FN_SCIFA4_SCK_PORT205,
204
205 /* SCIFA5 */
206 GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
207 GPIO_FN_SCIFA5_RXD_PORT10,
208
209 GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
210 GPIO_FN_SCIFA5_TXD_PORT208,
211
212 GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
213 GPIO_FN_SCIFA5_RXD_PORT92,
214
215 GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
216 GPIO_FN_SCIFA5_SCK_PORT206,
217
218 /* SCIFA6 */
219 GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
220
221 /* SCIFA7 */
222 GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
223
224 /* SCIFAB */
225 GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
226 GPIO_FN_SCIFB_RXD_PORT191,
227 GPIO_FN_SCIFB_TXD_PORT192,
228 GPIO_FN_SCIFB_RTS_PORT186,
229 GPIO_FN_SCIFB_CTS_PORT187,
230
231 GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
232 GPIO_FN_SCIFB_RXD_PORT3,
233 GPIO_FN_SCIFB_TXD_PORT4,
234 GPIO_FN_SCIFB_RTS_PORT172,
235 GPIO_FN_SCIFB_CTS_PORT173,
236
237 /* LCD0 */
238 GPIO_FN_LCDC0_SELECT,
239 GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
240 GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
241 GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
242 GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
243 GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
244 GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
245 GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
246
247 GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
248 GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
249
250 GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
251 GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
252
253 GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
254 GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
255 GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
256 GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
257
258 GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
259 GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
260 GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
261 GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
262
263 /* LCD1 */
264 GPIO_FN_LCDC1_SELECT,
265 GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
266 GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
267 GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
268 GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
269 GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
270 GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
271 GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
272 GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
273 GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
274 GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
275
276 GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
277 GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
278
279 GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
280 GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
281
282 /* RSPI */
283 GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
284 GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
285 GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
286 GPIO_FN_RSPI_CK_A,
287
288 /* VIO CKO */
289 GPIO_FN_VIO_CKO1,
290 GPIO_FN_VIO_CKO2,
291 GPIO_FN_VIO_CKO_1,
292 GPIO_FN_VIO_CKO,
293
294 /* VIO0 */
295 GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
296 GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
297 GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
298 GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
299 GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
300 GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
301
302 GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
303 GPIO_FN_VIO0_D14_PORT25,
304 GPIO_FN_VIO0_D15_PORT24,
305
306 GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
307 GPIO_FN_VIO0_D14_PORT95,
308 GPIO_FN_VIO0_D15_PORT96,
309
310 /* VIO1 */
311 GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
312 GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
313 GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
314 GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
315
316 /* TPU0 */
317 GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
318 GPIO_FN_TPU0TO3,
319 GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
320 GPIO_FN_TPU0TO2_PORT202,
321
322 /* SSP1 0 */
323 GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
324 GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
325 GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
326 GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
327
328 /* SSP1 1 */
329 GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
330 GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
331 GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
332
333 GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
334 GPIO_FN_STP1_IPEN_PORT187,
335
336 GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
337 GPIO_FN_STP1_IPEN_PORT193,
338
339 /* SIM */
340 GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
341 GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
342 GPIO_FN_SIM_D_PORT199,
343
344 /* SDHI0 */
345 GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
346 GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
347 GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
348
349 /* SDHI1 */
350 GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
351 GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
352 GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
353
354 /* SDHI2 */
355 GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
356 GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
357
358 GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
359 GPIO_FN_SDHI2_WP_PORT25,
360
361 GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
362 GPIO_FN_SDHI2_CD_PORT202,
363
364 /* MSIOF2 */
365 GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
366 GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
367 GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
368 GPIO_FN_MSIOF2_RSCK,
369
370 /* KEYSC */
371 GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
372 GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
373 GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
374 GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
375 GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
376
377 GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
378 GPIO_FN_KEYIN1_PORT44,
379 GPIO_FN_KEYIN2_PORT45,
380 GPIO_FN_KEYIN3_PORT46,
381
382 GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
383 GPIO_FN_KEYIN1_PORT57,
384 GPIO_FN_KEYIN2_PORT56,
385 GPIO_FN_KEYIN3_PORT55,
386
387 /* VOU */
388 GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
389 GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
390 GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
391 GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
392 GPIO_FN_DV_CLK,
393 GPIO_FN_DV_VSYNC,
394 GPIO_FN_DV_HSYNC,
395
396 /* MEMC */
397 GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
398 GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
399 GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
400 GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
401 GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
402 GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
403 GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
404
405 GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
406 GPIO_FN_MEMC_ADV,
407 GPIO_FN_MEMC_WAIT,
408 GPIO_FN_MEMC_BUSCLK,
409
410 GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
411 GPIO_FN_MEMC_DREQ0,
412 GPIO_FN_MEMC_DREQ1,
413 GPIO_FN_MEMC_A0,
414
415 /* MMC */
416 GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
417 GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
418 GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
419 GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
420 GPIO_FN_MMC0_CLK_PORT66,
421 GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
422
423 GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
424 GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
425 GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
426 GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
427 GPIO_FN_MMC1_CLK_PORT103,
428 GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
429
430 /* MSIOF0 */
431 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
432 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
433 GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
434 GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
435 GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
436
437 /* MSIOF1 */
438 GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
439 GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
440
441 GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
442 GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
443 GPIO_FN_MSIOF1_TSYNC_PORT120,
444 GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
445
446 GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
447 GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
448 GPIO_FN_MSIOF1_RXD_PORT75,
449 GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
450
451 /* GPIO */
452 GPIO_FN_GPO0, GPIO_FN_GPI0,
453 GPIO_FN_GPO1, GPIO_FN_GPI1,
454
455 /* USB0 */
456 GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
457
458 /* USB1 */
459 GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
460
461 /* BBIF1 */
462 GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
463 GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
464 GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
465
466 /* BBIF2 */
467 GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
468 GPIO_FN_BBIF2_RXD2_PORT60,
469 GPIO_FN_BBIF2_TSYNC2_PORT6,
470 GPIO_FN_BBIF2_TSCK2_PORT59,
471
472 GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
473 GPIO_FN_BBIF2_TXD2_PORT183,
474 GPIO_FN_BBIF2_TSCK2_PORT89,
475 GPIO_FN_BBIF2_TSYNC2_PORT184,
476
477 /* BSC / FLCTL / PCMCIA */
478 GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
479 GPIO_FN_CS5B, GPIO_FN_CS6A,
480 GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
481 GPIO_FN_CS5A_PORT19,
482 GPIO_FN_IOIS16, /* ? */
483
484 GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
485 GPIO_FN_A4_FOE, /* share with FLCTL */
486 GPIO_FN_A5_FCDE, /* share with FLCTL */
487 GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
488 GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
489 GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
490 GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
491 GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
492 GPIO_FN_A26,
493
494 GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
495 GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
496 GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
497 GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
498 GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
499 GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
500 GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
501 GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
502
503 GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
504 GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
505 GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
506 GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
507
508 GPIO_FN_WE0_FWE, /* share with FLCTL */
509 GPIO_FN_WE1,
510 GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
511 GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
512 GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
513 GPIO_FN_RD_FSC, /* share with FLCTL */
514 GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
515 GPIO_FN_WAIT_PORT90,
516
517 GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
518
519 /* IRDA */
520 GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
521
522 /* ATAPI */
523 GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
524 GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
525 GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
526 GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
527 GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
528 GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
529 GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
530 GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
531 GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
532 GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
533
534 /* RMII */
535 GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
536 GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
537 GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
538 GPIO_FN_RMII_REF50CK, /* for RMII */
539 GPIO_FN_RMII_REF125CK, /* for GMII */
540
541 /* GEther */
542 GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
543 GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
544 GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
545 GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
546 GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
547 GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
548 GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
549 GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
550 GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
551 GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
552 GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
553 GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
554 GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
555 GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
556
557 /* DMA0 */
558 GPIO_FN_DREQ0, GPIO_FN_DACK0,
559
560 /* DMA1 */
561 GPIO_FN_DREQ1, GPIO_FN_DACK1,
562
563 /* SYSC */
564 GPIO_FN_RESETOUTS,
565 GPIO_FN_RESETP_PULLUP,
566 GPIO_FN_RESETP_PLAIN,
567
568 /* SDENC */
569 GPIO_FN_SDENC_CPG,
570 GPIO_FN_SDENC_DV_CLKI,
571
572 /* IRREM */
573 GPIO_FN_IROUT,
574
575 /* DEBUG */
576 GPIO_FN_EDEBGREQ_PULLDOWN,
577 GPIO_FN_EDEBGREQ_PULLUP,
578
579 GPIO_FN_TRACEAUD_FROM_VIO,
580 GPIO_FN_TRACEAUD_FROM_LCDC0,
581 GPIO_FN_TRACEAUD_FROM_MEMC,
582};
583
584#endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
new file mode 100644
index 000000000000..c62a2059f2f7
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -0,0 +1,45 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/irq.h>
22#include <linux/io.h>
23#include <asm/hardware/gic.h>
24
25#define INTA_CTRL 0xe605807c
26
27static int r8a7740_set_wake(struct irq_data *data, unsigned int on)
28{
29 return 0; /* always allow wakeup */
30}
31
32void __init r8a7740_init_irq(void)
33{
34 void __iomem *gic_dist_base = __io(0xf0001000);
35 void __iomem *gic_cpu_base = __io(0xf0000000);
36
37 /*
38 * Change INT_SEL INTCA->GIC
39 * (on GPIO)
40 */
41 __raw_writel(__raw_readl(INTA_CTRL) & ~(1 << 1), INTA_CTRL);
42
43 gic_init(0, 29, gic_dist_base, gic_cpu_base);
44 gic_arch_extn.irq_set_wake = r8a7740_set_wake;
45}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
new file mode 100644
index 000000000000..55485187f0c7
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -0,0 +1,246 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/serial_sci.h>
24#include <linux/sh_timer.h>
25#include <mach/r8a7740.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28
29/* SCIFA0 */
30static struct plat_sci_port scif0_platform_data = {
31 .mapbase = 0xe6c40000,
32 .flags = UPF_BOOT_AUTOCONF,
33 .scscr = SCSCR_RE | SCSCR_TE,
34 .scbrr_algo_id = SCBRR_ALGO_4,
35 .type = PORT_SCIFA,
36 .irqs = SCIx_IRQ_MUXED(gic_spi(100)),
37};
38
39static struct platform_device scif0_device = {
40 .name = "sh-sci",
41 .id = 0,
42 .dev = {
43 .platform_data = &scif0_platform_data,
44 },
45};
46
47/* SCIFA1 */
48static struct plat_sci_port scif1_platform_data = {
49 .mapbase = 0xe6c50000,
50 .flags = UPF_BOOT_AUTOCONF,
51 .scscr = SCSCR_RE | SCSCR_TE,
52 .scbrr_algo_id = SCBRR_ALGO_4,
53 .type = PORT_SCIFA,
54 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
55};
56
57static struct platform_device scif1_device = {
58 .name = "sh-sci",
59 .id = 1,
60 .dev = {
61 .platform_data = &scif1_platform_data,
62 },
63};
64
65/* SCIFA2 */
66static struct plat_sci_port scif2_platform_data = {
67 .mapbase = 0xe6c60000,
68 .flags = UPF_BOOT_AUTOCONF,
69 .scscr = SCSCR_RE | SCSCR_TE,
70 .scbrr_algo_id = SCBRR_ALGO_4,
71 .type = PORT_SCIFA,
72 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
73};
74
75static struct platform_device scif2_device = {
76 .name = "sh-sci",
77 .id = 2,
78 .dev = {
79 .platform_data = &scif2_platform_data,
80 },
81};
82
83/* SCIFA3 */
84static struct plat_sci_port scif3_platform_data = {
85 .mapbase = 0xe6c70000,
86 .flags = UPF_BOOT_AUTOCONF,
87 .scscr = SCSCR_RE | SCSCR_TE,
88 .scbrr_algo_id = SCBRR_ALGO_4,
89 .type = PORT_SCIFA,
90 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
91};
92
93static struct platform_device scif3_device = {
94 .name = "sh-sci",
95 .id = 3,
96 .dev = {
97 .platform_data = &scif3_platform_data,
98 },
99};
100
101/* SCIFA4 */
102static struct plat_sci_port scif4_platform_data = {
103 .mapbase = 0xe6c80000,
104 .flags = UPF_BOOT_AUTOCONF,
105 .scscr = SCSCR_RE | SCSCR_TE,
106 .scbrr_algo_id = SCBRR_ALGO_4,
107 .type = PORT_SCIFA,
108 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
109};
110
111static struct platform_device scif4_device = {
112 .name = "sh-sci",
113 .id = 4,
114 .dev = {
115 .platform_data = &scif4_platform_data,
116 },
117};
118
119/* SCIFA5 */
120static struct plat_sci_port scif5_platform_data = {
121 .mapbase = 0xe6cb0000,
122 .flags = UPF_BOOT_AUTOCONF,
123 .scscr = SCSCR_RE | SCSCR_TE,
124 .scbrr_algo_id = SCBRR_ALGO_4,
125 .type = PORT_SCIFA,
126 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
127};
128
129static struct platform_device scif5_device = {
130 .name = "sh-sci",
131 .id = 5,
132 .dev = {
133 .platform_data = &scif5_platform_data,
134 },
135};
136
137/* SCIFA6 */
138static struct plat_sci_port scif6_platform_data = {
139 .mapbase = 0xe6cc0000,
140 .flags = UPF_BOOT_AUTOCONF,
141 .scscr = SCSCR_RE | SCSCR_TE,
142 .scbrr_algo_id = SCBRR_ALGO_4,
143 .type = PORT_SCIFA,
144 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
145};
146
147static struct platform_device scif6_device = {
148 .name = "sh-sci",
149 .id = 6,
150 .dev = {
151 .platform_data = &scif6_platform_data,
152 },
153};
154
155/* SCIFA7 */
156static struct plat_sci_port scif7_platform_data = {
157 .mapbase = 0xe6cd0000,
158 .flags = UPF_BOOT_AUTOCONF,
159 .scscr = SCSCR_RE | SCSCR_TE,
160 .scbrr_algo_id = SCBRR_ALGO_4,
161 .type = PORT_SCIFA,
162 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
163};
164
165static struct platform_device scif7_device = {
166 .name = "sh-sci",
167 .id = 7,
168 .dev = {
169 .platform_data = &scif7_platform_data,
170 },
171};
172
173/* SCIFB */
174static struct plat_sci_port scifb_platform_data = {
175 .mapbase = 0xe6c30000,
176 .flags = UPF_BOOT_AUTOCONF,
177 .scscr = SCSCR_RE | SCSCR_TE,
178 .scbrr_algo_id = SCBRR_ALGO_4,
179 .type = PORT_SCIFB,
180 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
181};
182
183static struct platform_device scifb_device = {
184 .name = "sh-sci",
185 .id = 8,
186 .dev = {
187 .platform_data = &scifb_platform_data,
188 },
189};
190
191/* CMT */
192static struct sh_timer_config cmt10_platform_data = {
193 .name = "CMT10",
194 .channel_offset = 0x10,
195 .timer_bit = 0,
196 .clockevent_rating = 125,
197 .clocksource_rating = 125,
198};
199
200static struct resource cmt10_resources[] = {
201 [0] = {
202 .name = "CMT10",
203 .start = 0xe6138010,
204 .end = 0xe613801b,
205 .flags = IORESOURCE_MEM,
206 },
207 [1] = {
208 .start = gic_spi(58),
209 .flags = IORESOURCE_IRQ,
210 },
211};
212
213static struct platform_device cmt10_device = {
214 .name = "sh_cmt",
215 .id = 10,
216 .dev = {
217 .platform_data = &cmt10_platform_data,
218 },
219 .resource = cmt10_resources,
220 .num_resources = ARRAY_SIZE(cmt10_resources),
221};
222
223static struct platform_device *r8a7740_early_devices[] __initdata = {
224 &scif0_device,
225 &scif1_device,
226 &scif2_device,
227 &scif3_device,
228 &scif4_device,
229 &scif5_device,
230 &scif6_device,
231 &scif7_device,
232 &scifb_device,
233 &cmt10_device,
234};
235
236void __init r8a7740_add_standard_devices(void)
237{
238 platform_add_devices(r8a7740_early_devices,
239 ARRAY_SIZE(r8a7740_early_devices));
240}
241
242void __init r8a7740_add_early_devices(void)
243{
244 early_platform_add_devices(r8a7740_early_devices,
245 ARRAY_SIZE(r8a7740_early_devices));
246}
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index e9bed038aa1f..a1a2d364f92b 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -17,7 +17,9 @@
17 defined(CONFIG_ARCH_SH73A0) || \ 17 defined(CONFIG_ARCH_SH73A0) || \
18 defined(CONFIG_ARCH_SH7367) || \ 18 defined(CONFIG_ARCH_SH7367) || \
19 defined(CONFIG_ARCH_SH7377) || \ 19 defined(CONFIG_ARCH_SH7377) || \
20 defined(CONFIG_ARCH_SH7372) 20 defined(CONFIG_ARCH_SH7372) || \
21 defined(CONFIG_ARCH_R8A7740)
22
21# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) 23# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
22# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) 24# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
23# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) 25# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 09:28:47 -0500