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-rw-r--r--sound/soc/Makefile3
-rw-r--r--sound/soc/soc-cache.c380
-rw-r--r--sound/soc/soc-io.c399
3 files changed, 401 insertions, 381 deletions
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index adb5719cb7d2..4f913876f332 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -1,4 +1,5 @@
1snd-soc-core-objs := soc-core.o soc-dapm.o soc-jack.o soc-cache.o soc-utils.o soc-pcm.o 1snd-soc-core-objs := soc-core.o soc-dapm.o soc-jack.o soc-cache.o soc-utils.o
2snd-soc-core-objs += soc-pcm.o soc-io.o
2 3
3obj-$(CONFIG_SND_SOC) += snd-soc-core.o 4obj-$(CONFIG_SND_SOC) += snd-soc-core.o
4obj-$(CONFIG_SND_SOC) += codecs/ 5obj-$(CONFIG_SND_SOC) += codecs/
diff --git a/sound/soc/soc-cache.c b/sound/soc/soc-cache.c
index b88a61fd6de0..d9f8aded51f3 100644
--- a/sound/soc/soc-cache.c
+++ b/sound/soc/soc-cache.c
@@ -20,386 +20,6 @@
20 20
21#include <trace/events/asoc.h> 21#include <trace/events/asoc.h>
22 22
23#ifdef CONFIG_SPI_MASTER
24static int do_spi_write(void *control, const char *data, int len)
25{
26 struct spi_device *spi = control;
27 int ret;
28
29 ret = spi_write(spi, data, len);
30 if (ret < 0)
31 return ret;
32
33 return len;
34}
35#endif
36
37static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
38 unsigned int value, const void *data, int len)
39{
40 int ret;
41
42 if (!snd_soc_codec_volatile_register(codec, reg) &&
43 reg < codec->driver->reg_cache_size &&
44 !codec->cache_bypass) {
45 ret = snd_soc_cache_write(codec, reg, value);
46 if (ret < 0)
47 return -1;
48 }
49
50 if (codec->cache_only) {
51 codec->cache_sync = 1;
52 return 0;
53 }
54
55 ret = codec->hw_write(codec->control_data, data, len);
56 if (ret == len)
57 return 0;
58 if (ret < 0)
59 return ret;
60 else
61 return -EIO;
62}
63
64static unsigned int hw_read(struct snd_soc_codec *codec, unsigned int reg)
65{
66 int ret;
67 unsigned int val;
68
69 if (reg >= codec->driver->reg_cache_size ||
70 snd_soc_codec_volatile_register(codec, reg) ||
71 codec->cache_bypass) {
72 if (codec->cache_only)
73 return -1;
74
75 BUG_ON(!codec->hw_read);
76 return codec->hw_read(codec, reg);
77 }
78
79 ret = snd_soc_cache_read(codec, reg, &val);
80 if (ret < 0)
81 return -1;
82 return val;
83}
84
85static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
86 unsigned int value)
87{
88 u16 data;
89
90 data = cpu_to_be16((reg << 12) | (value & 0xffffff));
91
92 return do_hw_write(codec, reg, value, &data, 2);
93}
94
95static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
96 unsigned int value)
97{
98 u16 data;
99
100 data = cpu_to_be16((reg << 9) | (value & 0x1ff));
101
102 return do_hw_write(codec, reg, value, &data, 2);
103}
104
105static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
106 unsigned int value)
107{
108 u8 data[2];
109
110 reg &= 0xff;
111 data[0] = reg;
112 data[1] = value & 0xff;
113
114 return do_hw_write(codec, reg, value, data, 2);
115}
116
117static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
118 unsigned int value)
119{
120 u8 data[3];
121 u16 val = cpu_to_be16(value);
122
123 data[0] = reg;
124 memcpy(&data[1], &val, sizeof(val));
125
126 return do_hw_write(codec, reg, value, data, 3);
127}
128
129#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
130static unsigned int do_i2c_read(struct snd_soc_codec *codec,
131 void *reg, int reglen,
132 void *data, int datalen)
133{
134 struct i2c_msg xfer[2];
135 int ret;
136 struct i2c_client *client = codec->control_data;
137
138 /* Write register */
139 xfer[0].addr = client->addr;
140 xfer[0].flags = 0;
141 xfer[0].len = reglen;
142 xfer[0].buf = reg;
143
144 /* Read data */
145 xfer[1].addr = client->addr;
146 xfer[1].flags = I2C_M_RD;
147 xfer[1].len = datalen;
148 xfer[1].buf = data;
149
150 ret = i2c_transfer(client->adapter, xfer, 2);
151 if (ret == 2)
152 return 0;
153 else if (ret < 0)
154 return ret;
155 else
156 return -EIO;
157}
158#endif
159
160#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
161static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
162 unsigned int r)
163{
164 u8 reg = r;
165 u8 data;
166 int ret;
167
168 ret = do_i2c_read(codec, &reg, 1, &data, 1);
169 if (ret < 0)
170 return 0;
171 return data;
172}
173#else
174#define snd_soc_8_8_read_i2c NULL
175#endif
176
177#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
178static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
179 unsigned int r)
180{
181 u8 reg = r;
182 u16 data;
183 int ret;
184
185 ret = do_i2c_read(codec, &reg, 1, &data, 2);
186 if (ret < 0)
187 return 0;
188 return (data >> 8) | ((data & 0xff) << 8);
189}
190#else
191#define snd_soc_8_16_read_i2c NULL
192#endif
193
194#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
195static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
196 unsigned int r)
197{
198 u16 reg = r;
199 u8 data;
200 int ret;
201
202 ret = do_i2c_read(codec, &reg, 2, &data, 1);
203 if (ret < 0)
204 return 0;
205 return data;
206}
207#else
208#define snd_soc_16_8_read_i2c NULL
209#endif
210
211static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
212 unsigned int value)
213{
214 u8 data[3];
215 u16 rval = cpu_to_be16(reg);
216
217 memcpy(data, &rval, sizeof(rval));
218 data[2] = value;
219
220 return do_hw_write(codec, reg, value, data, 3);
221}
222
223#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
224static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
225 unsigned int r)
226{
227 u16 reg = cpu_to_be16(r);
228 u16 data;
229 int ret;
230
231 ret = do_i2c_read(codec, &reg, 2, &data, 2);
232 if (ret < 0)
233 return 0;
234 return be16_to_cpu(data);
235}
236#else
237#define snd_soc_16_16_read_i2c NULL
238#endif
239
240static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
241 unsigned int value)
242{
243 u16 data[2];
244
245 data[0] = cpu_to_be16(reg);
246 data[1] = cpu_to_be16(value);
247
248 return do_hw_write(codec, reg, value, data, sizeof(data));
249}
250
251/* Primitive bulk write support for soc-cache. The data pointed to by
252 * `data' needs to already be in the form the hardware expects
253 * including any leading register specific data. Any data written
254 * through this function will not go through the cache as it only
255 * handles writing to volatile or out of bounds registers.
256 */
257static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec, unsigned int reg,
258 const void *data, size_t len)
259{
260 int ret;
261
262 /* To ensure that we don't get out of sync with the cache, check
263 * whether the base register is volatile or if we've directly asked
264 * to bypass the cache. Out of bounds registers are considered
265 * volatile.
266 */
267 if (!codec->cache_bypass
268 && !snd_soc_codec_volatile_register(codec, reg)
269 && reg < codec->driver->reg_cache_size)
270 return -EINVAL;
271
272 switch (codec->control_type) {
273#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
274 case SND_SOC_I2C:
275 ret = i2c_master_send(codec->control_data, data, len);
276 break;
277#endif
278#if defined(CONFIG_SPI_MASTER)
279 case SND_SOC_SPI:
280 ret = spi_write(codec->control_data, data, len);
281 break;
282#endif
283 default:
284 BUG();
285 }
286
287 if (ret == len)
288 return 0;
289 if (ret < 0)
290 return ret;
291 else
292 return -EIO;
293}
294
295static struct {
296 int addr_bits;
297 int data_bits;
298 int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
299 unsigned int (*read)(struct snd_soc_codec *, unsigned int);
300 unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
301} io_types[] = {
302 {
303 .addr_bits = 4, .data_bits = 12,
304 .write = snd_soc_4_12_write,
305 },
306 {
307 .addr_bits = 7, .data_bits = 9,
308 .write = snd_soc_7_9_write,
309 },
310 {
311 .addr_bits = 8, .data_bits = 8,
312 .write = snd_soc_8_8_write,
313 .i2c_read = snd_soc_8_8_read_i2c,
314 },
315 {
316 .addr_bits = 8, .data_bits = 16,
317 .write = snd_soc_8_16_write,
318 .i2c_read = snd_soc_8_16_read_i2c,
319 },
320 {
321 .addr_bits = 16, .data_bits = 8,
322 .write = snd_soc_16_8_write,
323 .i2c_read = snd_soc_16_8_read_i2c,
324 },
325 {
326 .addr_bits = 16, .data_bits = 16,
327 .write = snd_soc_16_16_write,
328 .i2c_read = snd_soc_16_16_read_i2c,
329 },
330};
331
332/**
333 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
334 *
335 * @codec: CODEC to configure.
336 * @addr_bits: Number of bits of register address data.
337 * @data_bits: Number of bits of data per register.
338 * @control: Control bus used.
339 *
340 * Register formats are frequently shared between many I2C and SPI
341 * devices. In order to promote code reuse the ASoC core provides
342 * some standard implementations of CODEC read and write operations
343 * which can be set up using this function.
344 *
345 * The caller is responsible for allocating and initialising the
346 * actual cache.
347 *
348 * Note that at present this code cannot be used by CODECs with
349 * volatile registers.
350 */
351int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
352 int addr_bits, int data_bits,
353 enum snd_soc_control_type control)
354{
355 int i;
356
357 for (i = 0; i < ARRAY_SIZE(io_types); i++)
358 if (io_types[i].addr_bits == addr_bits &&
359 io_types[i].data_bits == data_bits)
360 break;
361 if (i == ARRAY_SIZE(io_types)) {
362 printk(KERN_ERR
363 "No I/O functions for %d bit address %d bit data\n",
364 addr_bits, data_bits);
365 return -EINVAL;
366 }
367
368 codec->write = io_types[i].write;
369 codec->read = hw_read;
370 codec->bulk_write_raw = snd_soc_hw_bulk_write_raw;
371
372 switch (control) {
373 case SND_SOC_CUSTOM:
374 break;
375
376 case SND_SOC_I2C:
377#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
378 codec->hw_write = (hw_write_t)i2c_master_send;
379#endif
380 if (io_types[i].i2c_read)
381 codec->hw_read = io_types[i].i2c_read;
382
383 codec->control_data = container_of(codec->dev,
384 struct i2c_client,
385 dev);
386 break;
387
388 case SND_SOC_SPI:
389#ifdef CONFIG_SPI_MASTER
390 codec->hw_write = do_spi_write;
391#endif
392
393 codec->control_data = container_of(codec->dev,
394 struct spi_device,
395 dev);
396 break;
397 }
398
399 return 0;
400}
401EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
402
403static bool snd_soc_set_cache_val(void *base, unsigned int idx, 23static bool snd_soc_set_cache_val(void *base, unsigned int idx,
404 unsigned int val, unsigned int word_size) 24 unsigned int val, unsigned int word_size)
405{ 25{
diff --git a/sound/soc/soc-io.c b/sound/soc/soc-io.c
new file mode 100644
index 000000000000..855e5cde2793
--- /dev/null
+++ b/sound/soc/soc-io.c
@@ -0,0 +1,399 @@
1/*
2 * soc-io.c -- ASoC register I/O helpers
3 *
4 * Copyright 2009-2011 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/i2c.h>
15#include <linux/spi/spi.h>
16#include <sound/soc.h>
17
18#include <trace/events/asoc.h>
19
20#ifdef CONFIG_SPI_MASTER
21static int do_spi_write(void *control, const char *data, int len)
22{
23 struct spi_device *spi = control;
24 int ret;
25
26 ret = spi_write(spi, data, len);
27 if (ret < 0)
28 return ret;
29
30 return len;
31}
32#endif
33
34static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
35 unsigned int value, const void *data, int len)
36{
37 int ret;
38
39 if (!snd_soc_codec_volatile_register(codec, reg) &&
40 reg < codec->driver->reg_cache_size &&
41 !codec->cache_bypass) {
42 ret = snd_soc_cache_write(codec, reg, value);
43 if (ret < 0)
44 return -1;
45 }
46
47 if (codec->cache_only) {
48 codec->cache_sync = 1;
49 return 0;
50 }
51
52 ret = codec->hw_write(codec->control_data, data, len);
53 if (ret == len)
54 return 0;
55 if (ret < 0)
56 return ret;
57 else
58 return -EIO;
59}
60
61static unsigned int hw_read(struct snd_soc_codec *codec, unsigned int reg)
62{
63 int ret;
64 unsigned int val;
65
66 if (reg >= codec->driver->reg_cache_size ||
67 snd_soc_codec_volatile_register(codec, reg) ||
68 codec->cache_bypass) {
69 if (codec->cache_only)
70 return -1;
71
72 BUG_ON(!codec->hw_read);
73 return codec->hw_read(codec, reg);
74 }
75
76 ret = snd_soc_cache_read(codec, reg, &val);
77 if (ret < 0)
78 return -1;
79 return val;
80}
81
82static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
83 unsigned int value)
84{
85 u16 data;
86
87 data = cpu_to_be16((reg << 12) | (value & 0xffffff));
88
89 return do_hw_write(codec, reg, value, &data, 2);
90}
91
92static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
93 unsigned int value)
94{
95 u16 data;
96
97 data = cpu_to_be16((reg << 9) | (value & 0x1ff));
98
99 return do_hw_write(codec, reg, value, &data, 2);
100}
101
102static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
103 unsigned int value)
104{
105 u8 data[2];
106
107 reg &= 0xff;
108 data[0] = reg;
109 data[1] = value & 0xff;
110
111 return do_hw_write(codec, reg, value, data, 2);
112}
113
114static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
115 unsigned int value)
116{
117 u8 data[3];
118 u16 val = cpu_to_be16(value);
119
120 data[0] = reg;
121 memcpy(&data[1], &val, sizeof(val));
122
123 return do_hw_write(codec, reg, value, data, 3);
124}
125
126#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
127static unsigned int do_i2c_read(struct snd_soc_codec *codec,
128 void *reg, int reglen,
129 void *data, int datalen)
130{
131 struct i2c_msg xfer[2];
132 int ret;
133 struct i2c_client *client = codec->control_data;
134
135 /* Write register */
136 xfer[0].addr = client->addr;
137 xfer[0].flags = 0;
138 xfer[0].len = reglen;
139 xfer[0].buf = reg;
140
141 /* Read data */
142 xfer[1].addr = client->addr;
143 xfer[1].flags = I2C_M_RD;
144 xfer[1].len = datalen;
145 xfer[1].buf = data;
146
147 ret = i2c_transfer(client->adapter, xfer, 2);
148 if (ret == 2)
149 return 0;
150 else if (ret < 0)
151 return ret;
152 else
153 return -EIO;
154}
155#endif
156
157#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
158static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
159 unsigned int r)
160{
161 u8 reg = r;
162 u8 data;
163 int ret;
164
165 ret = do_i2c_read(codec, &reg, 1, &data, 1);
166 if (ret < 0)
167 return 0;
168 return data;
169}
170#else
171#define snd_soc_8_8_read_i2c NULL
172#endif
173
174#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
175static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
176 unsigned int r)
177{
178 u8 reg = r;
179 u16 data;
180 int ret;
181
182 ret = do_i2c_read(codec, &reg, 1, &data, 2);
183 if (ret < 0)
184 return 0;
185 return (data >> 8) | ((data & 0xff) << 8);
186}
187#else
188#define snd_soc_8_16_read_i2c NULL
189#endif
190
191#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
192static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
193 unsigned int r)
194{
195 u16 reg = r;
196 u8 data;
197 int ret;
198
199 ret = do_i2c_read(codec, &reg, 2, &data, 1);
200 if (ret < 0)
201 return 0;
202 return data;
203}
204#else
205#define snd_soc_16_8_read_i2c NULL
206#endif
207
208static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
209 unsigned int value)
210{
211 u8 data[3];
212 u16 rval = cpu_to_be16(reg);
213
214 memcpy(data, &rval, sizeof(rval));
215 data[2] = value;
216
217 return do_hw_write(codec, reg, value, data, 3);
218}
219
220#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
221static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
222 unsigned int r)
223{
224 u16 reg = cpu_to_be16(r);
225 u16 data;
226 int ret;
227
228 ret = do_i2c_read(codec, &reg, 2, &data, 2);
229 if (ret < 0)
230 return 0;
231 return be16_to_cpu(data);
232}
233#else
234#define snd_soc_16_16_read_i2c NULL
235#endif
236
237static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
238 unsigned int value)
239{
240 u16 data[2];
241
242 data[0] = cpu_to_be16(reg);
243 data[1] = cpu_to_be16(value);
244
245 return do_hw_write(codec, reg, value, data, sizeof(data));
246}
247
248/* Primitive bulk write support for soc-cache. The data pointed to by
249 * `data' needs to already be in the form the hardware expects
250 * including any leading register specific data. Any data written
251 * through this function will not go through the cache as it only
252 * handles writing to volatile or out of bounds registers.
253 */
254static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec, unsigned int reg,
255 const void *data, size_t len)
256{
257 int ret;
258
259 /* To ensure that we don't get out of sync with the cache, check
260 * whether the base register is volatile or if we've directly asked
261 * to bypass the cache. Out of bounds registers are considered
262 * volatile.
263 */
264 if (!codec->cache_bypass
265 && !snd_soc_codec_volatile_register(codec, reg)
266 && reg < codec->driver->reg_cache_size)
267 return -EINVAL;
268
269 switch (codec->control_type) {
270#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
271 case SND_SOC_I2C:
272 ret = i2c_master_send(codec->control_data, data, len);
273 break;
274#endif
275#if defined(CONFIG_SPI_MASTER)
276 case SND_SOC_SPI:
277 ret = spi_write(codec->control_data, data, len);
278 break;
279#endif
280 default:
281 BUG();
282 }
283
284 if (ret == len)
285 return 0;
286 if (ret < 0)
287 return ret;
288 else
289 return -EIO;
290}
291
292static struct {
293 int addr_bits;
294 int data_bits;
295 int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
296 unsigned int (*read)(struct snd_soc_codec *, unsigned int);
297 unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
298} io_types[] = {
299 {
300 .addr_bits = 4, .data_bits = 12,
301 .write = snd_soc_4_12_write,
302 },
303 {
304 .addr_bits = 7, .data_bits = 9,
305 .write = snd_soc_7_9_write,
306 },
307 {
308 .addr_bits = 8, .data_bits = 8,
309 .write = snd_soc_8_8_write,
310 .i2c_read = snd_soc_8_8_read_i2c,
311 },
312 {
313 .addr_bits = 8, .data_bits = 16,
314 .write = snd_soc_8_16_write,
315 .i2c_read = snd_soc_8_16_read_i2c,
316 },
317 {
318 .addr_bits = 16, .data_bits = 8,
319 .write = snd_soc_16_8_write,
320 .i2c_read = snd_soc_16_8_read_i2c,
321 },
322 {
323 .addr_bits = 16, .data_bits = 16,
324 .write = snd_soc_16_16_write,
325 .i2c_read = snd_soc_16_16_read_i2c,
326 },
327};
328
329/**
330 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
331 *
332 * @codec: CODEC to configure.
333 * @addr_bits: Number of bits of register address data.
334 * @data_bits: Number of bits of data per register.
335 * @control: Control bus used.
336 *
337 * Register formats are frequently shared between many I2C and SPI
338 * devices. In order to promote code reuse the ASoC core provides
339 * some standard implementations of CODEC read and write operations
340 * which can be set up using this function.
341 *
342 * The caller is responsible for allocating and initialising the
343 * actual cache.
344 *
345 * Note that at present this code cannot be used by CODECs with
346 * volatile registers.
347 */
348int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
349 int addr_bits, int data_bits,
350 enum snd_soc_control_type control)
351{
352 int i;
353
354 for (i = 0; i < ARRAY_SIZE(io_types); i++)
355 if (io_types[i].addr_bits == addr_bits &&
356 io_types[i].data_bits == data_bits)
357 break;
358 if (i == ARRAY_SIZE(io_types)) {
359 printk(KERN_ERR
360 "No I/O functions for %d bit address %d bit data\n",
361 addr_bits, data_bits);
362 return -EINVAL;
363 }
364
365 codec->write = io_types[i].write;
366 codec->read = hw_read;
367 codec->bulk_write_raw = snd_soc_hw_bulk_write_raw;
368
369 switch (control) {
370 case SND_SOC_CUSTOM:
371 break;
372
373 case SND_SOC_I2C:
374#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
375 codec->hw_write = (hw_write_t)i2c_master_send;
376#endif
377 if (io_types[i].i2c_read)
378 codec->hw_read = io_types[i].i2c_read;
379
380 codec->control_data = container_of(codec->dev,
381 struct i2c_client,
382 dev);
383 break;
384
385 case SND_SOC_SPI:
386#ifdef CONFIG_SPI_MASTER
387 codec->hw_write = do_spi_write;
388#endif
389
390 codec->control_data = container_of(codec->dev,
391 struct spi_device,
392 dev);
393 break;
394 }
395
396 return 0;
397}
398EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
399
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-22 08:26:19 -0500