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-rw-r--r--drivers/net/tg3.c7
-rw-r--r--drivers/net/tg3.h2
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 9b04954b6943..ed7a86df98cd 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -6717,6 +6717,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6717 tw32(TG3_CPMU_HST_ACC, val); 6717 tw32(TG3_CPMU_HST_ACC, val);
6718 } 6718 }
6719 6719
6720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6721 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
6722 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
6723 PCIE_PWR_MGMT_L1_THRESH_4MS;
6724 tw32(PCIE_PWR_MGMT_THRESH, val);
6725 }
6726
6720 /* This works around an issue with Athlon chipsets on 6727 /* This works around an issue with Athlon chipsets on
6721 * B3 tigon3 silicon. This bit has no effect on any 6728 * B3 tigon3 silicon. This bit has no effect on any
6722 * other revision. But do not set this on PCI Express 6729 * other revision. But do not set this on PCI Express
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index afbabf283c51..f1016cb1a89a 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1697,6 +1697,8 @@
1697 1697
1698#define PCIE_PWR_MGMT_THRESH 0x00007d28 1698#define PCIE_PWR_MGMT_THRESH 0x00007d28
1699#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 1699#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
1700#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
1701#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
1700 1702
1701 1703
1702/* OTP bit definitions */ 1704/* OTP bit definitions */