437 files changed, 14402 insertions, 8103 deletions

diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index a33628759d36..d933af370697 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example,
                 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
                 reg = <0x1460 0x18>;
                 gpio-controller;
-                gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;
+                gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
 
     }
 
@@ -107,8 +107,8 @@ where,
 
    Next values specify the base pin and number of pins for the range
    handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
-   pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled
-   by this gpio controller.
+   pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
+   pinctrl2 with gpio offset 10 is handled by this gpio controller.
 
 The pinctrl node must have "#gpio-range-cells" property to show number of
 arguments to pass with phandle from gpio controllers node.
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
index e13787498bcf..9b3f1d4a88d6 100644
--- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -1,7 +1,10 @@
 * Marvell PXA GPIO controller
 
 Required properties:
-- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
+- compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio",
+                "intel,pxa27x-gpio", "intel,pxa3xx-gpio",
+                "marvell,pxa93x-gpio", "marvell,mmp-gpio" or
+                "marvell,mmp2-gpio".
 - reg : Address and length of the register set for the device
 - interrupts : Should be the port interrupt shared by all gpio pins.
   There're three gpio interrupts in arch-pxa, and they're gpio0,
@@ -18,7 +21,7 @@ Required properties:
 Example:
 
         gpio: gpio@d4019000 {
-                compatible = "mrvl,mmp-gpio";
+                compatible = "marvell,mmp-gpio";
                 reg = <0xd4019000 0x1000>;
                 interrupts = <49>;
                 interrupt-name = "gpio_mux";
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index 2c81e45f1374..fa1746b639b9 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -1,7 +1,9 @@
 One-register-per-pin type device tree based pinctrl driver
 
 Required properties:
-- compatible : "pinctrl-single"
+- compatible : "pinctrl-single" or "pinconf-single".
+  "pinctrl-single" means that pinconf isn't supported.
+  "pinconf-single" means that generic pinconf is supported.
 
 - reg : offset and length of the register set for the mux registers
 
@@ -14,9 +16,61 @@ Optional properties:
 - pinctrl-single,function-off : function off mode for disabled state if
   available and same for all registers; if not specified, disabling of
   pin functions is ignored
+
 - pinctrl-single,bit-per-mux : boolean to indicate that one register controls
   more than one pin
 
+- pinctrl-single,drive-strength : array of value that are used to configure
+  drive strength in the pinmux register. They're value of drive strength
+  current and drive strength mask.
+
+                /* drive strength current, mask */
+                pinctrl-single,power-source = <0x30 0xf0>;
+
+- pinctrl-single,bias-pullup : array of value that are used to configure the
+  input bias pullup in the pinmux register.
+
+                /* input, enabled pullup bits, disabled pullup bits, mask */
+                pinctrl-single,bias-pullup = <0 1 0 1>;
+
+- pinctrl-single,bias-pulldown : array of value that are used to configure the
+  input bias pulldown in the pinmux register.
+
+                /* input, enabled pulldown bits, disabled pulldown bits, mask */
+                pinctrl-single,bias-pulldown = <2 2 0 2>;
+
+  * Two bits to control input bias pullup and pulldown: User should use
+    pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
+    pullup, and the other one bit means pulldown.
+  * Three bits to control input bias enable, pullup and pulldown. User should
+    use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
+    enable bit should be included in pullup or pulldown bits.
+  * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
+    pinctrl-single,bias-disable. Because pinctrl single driver could implement
+    it by calling pulldown, pullup disabled.
+
+- pinctrl-single,input-schmitt : array of value that are used to configure
+  input schmitt in the pinmux register. In some silicons, there're two input
+  schmitt value (rising-edge & falling-edge) in the pinmux register.
+
+                /* input schmitt value, mask */
+                pinctrl-single,input-schmitt = <0x30 0x70>;
+
+- pinctrl-single,input-schmitt-enable : array of value that are used to
+  configure input schmitt enable or disable in the pinmux register.
+
+                /* input, enable bits, disable bits, mask */
+                pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
+
+- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
+  range. They're value of subnode phandle, pin base in pinctrl device, pin
+  number in this range, GPIO function value of this GPIO range.
+  The number of parameters is depend on #pinctrl-single,gpio-range-cells
+  property.
+
+                /* pin base, nr pins & gpio function */
+                pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
+
 This driver assumes that there is only one register for each pin (unless the
 pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
 specified in the pinctrl-bindings.txt document in this directory.
@@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the
 device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
 be used when applying this change to the register.
 
+
+Optional sub-node: In case some pins could be configured as GPIO in the pinmux
+register, those pins could be defined as a GPIO range. This sub-node is required
+by pinctrl-single,gpio-range property.
+
+Required properties in sub-node:
+- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
+  pinctrl-single,gpio-range property.
+
+        range: gpio-range {
+                #pinctrl-single,gpio-range-cells = <3>;
+        };
+
+
 Example:
 
 /* SoC common file */
@@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 {
         pinctrl-single,function-mask = <0x5F>;
 };
 
+/* third controller instance for pins in gpio domain */
+pmx_gpio: pinmux@d401e000 {
+        compatible = "pinconf-single";
+        reg = <0xd401e000 0x0330>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        pinctrl-single,register-width = <32>;
+        pinctrl-single,function-mask = <7>;
+
+        /* sparse GPIO range could be supported */
+        pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
+                                &range 12 1 0 &range 13 29 1
+                                &range 43 1 0 &range 44 49 1
+                                &range 94 1 1 &range 96 2 1>;
+
+        range: gpio-range {
+                #pinctrl-single,gpio-range-cells = <3>;
+        };
+};
+
+
 /* board specific .dts file */
 
 &pmx_core {
@@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 {
                 >;
         };
 
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        0x208 0         /* UART0_RXD (IOCFG138) */
+                        0x20c 0         /* UART0_TXD (IOCFG139) */
+                >;
+                pinctrl-single,bias-pulldown = <0 2 2>;
+                pinctrl-single,bias-pullup = <0 1 1>;
+        };
+
         /* map uart2 pins */
         uart2_pins: pinmux_uart2_pins {
                 pinctrl-single,pins = <
@@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 {
 
 };
 
+&uart1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+};
+
 &uart2 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart2_pins>;
diff --git a/Documentation/sound/alsa/ALSA-Configuration.txt b/Documentation/sound/alsa/ALSA-Configuration.txt
index 4499bd948860..95731a08f257 100644
--- a/Documentation/sound/alsa/ALSA-Configuration.txt
+++ b/Documentation/sound/alsa/ALSA-Configuration.txt
@@ -890,9 +890,8 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed.
     enable_msi  - Enable Message Signaled Interrupt (MSI) (default = off)
     power_save  - Automatic power-saving timeout (in second, 0 =
                 disable)
-    power_save_controller - Support runtime D3 of HD-audio controller
-                (-1 = on for supported chip (default), false = off,
-                 true = force to on even for unsupported hardware)
+    power_save_controller - Reset HD-audio controller in power-saving mode
+                (default = on)
     align_buffer_size - Force rounding of buffer/period sizes to multiples
                       of 128 bytes. This is more efficient in terms of memory
                       access but isn't required by the HDA spec and prevents
diff --git a/MAINTAINERS b/MAINTAINERS
index 74e58a4d035b..836a6183c37f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5065,9 +5065,8 @@ S:	Maintained
 F:      drivers/net/ethernet/marvell/sk*
 
 MARVELL LIBERTAS WIRELESS DRIVER
-M:      Dan Williams <dcbw@redhat.com>
 L:      libertas-dev@lists.infradead.org
-S:      Maintained
+S:      Orphan
 F:      drivers/net/wireless/libertas/
 
 MARVELL MV643XX ETHERNET DRIVER
@@ -5569,6 +5568,7 @@ F:	include/uapi/linux/if_*
 F:      include/uapi/linux/netdevice.h
 
 NETXEN (1/10) GbE SUPPORT
+M:      Manish Chopra <manish.chopra@qlogic.com>
 M:      Sony Chacko <sony.chacko@qlogic.com>
 M:      Rajesh Borundia <rajesh.borundia@qlogic.com>
 L:      netdev@vger.kernel.org
diff --git a/Makefile b/Makefile
index 58a165b02af1..6db672b15bda 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 9
 SUBLEVEL = 0
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc6
 NAME = Unicycling Gorilla
 
 # *DOCUMENTATION*
diff --git a/arch/alpha/Makefile b/arch/alpha/Makefile
index 4759fe751aa1..2cc3cc519c54 100644
--- a/arch/alpha/Makefile
+++ b/arch/alpha/Makefile
@@ -12,7 +12,7 @@ NM := $(NM) -B
 
 LDFLAGS_vmlinux := -static -N #-relax
 CHECKFLAGS      += -D__alpha__ -m64
-cflags-y        := -pipe -mno-fp-regs -ffixed-8 -msmall-data
+cflags-y        := -pipe -mno-fp-regs -ffixed-8
 cflags-y        += $(call cc-option, -fno-jump-tables)
 
 cpuflags-$(CONFIG_ALPHA_EV4)            := -mcpu=ev4
diff --git a/arch/alpha/include/asm/floppy.h b/arch/alpha/include/asm/floppy.h
index 46cefbd50e73..bae97eb19d26 100644
--- a/arch/alpha/include/asm/floppy.h
+++ b/arch/alpha/include/asm/floppy.h
@@ -26,7 +26,7 @@
 #define fd_disable_irq()        disable_irq(FLOPPY_IRQ)
 #define fd_cacheflush(addr,size) /* nothing */
 #define fd_request_irq()        request_irq(FLOPPY_IRQ, floppy_interrupt,\
-                                            IRQF_DISABLED, "floppy", NULL)
+                                            0, "floppy", NULL)
 #define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL)
 
 #ifdef CONFIG_PCI
diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c
index 2872accd2215..7b2be251c30f 100644
--- a/arch/alpha/kernel/irq.c
+++ b/arch/alpha/kernel/irq.c
@@ -117,13 +117,6 @@ handle_irq(int irq)
                 return;
         }
 
-        /*
-         * From here we must proceed with IPL_MAX. Note that we do not
-         * explicitly enable interrupts afterwards - some MILO PALcode
-         * (namely LX164 one) seems to have severe problems with RTI
-         * at IPL 0.
-         */
-        local_irq_disable();
         irq_enter();
         generic_handle_irq_desc(irq, desc);
         irq_exit();
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c
index 772ddfdb71a8..f433fc11877a 100644
--- a/arch/alpha/kernel/irq_alpha.c
+++ b/arch/alpha/kernel/irq_alpha.c
@@ -45,6 +45,14 @@ do_entInt(unsigned long type, unsigned long vector,
           unsigned long la_ptr, struct pt_regs *regs)
 {
         struct pt_regs *old_regs;
+
+        /*
+         * Disable interrupts during IRQ handling.
+         * Note that there is no matching local_irq_enable() due to
+         * severe problems with RTI at IPL0 and some MILO PALcode
+         * (namely LX164).
+         */
+        local_irq_disable();
         switch (type) {
         case 0:
 #ifdef CONFIG_SMP
@@ -62,7 +70,6 @@ do_entInt(unsigned long type, unsigned long vector,
           {
                 long cpu;
 
-                local_irq_disable();
                 smp_percpu_timer_interrupt(regs);
                 cpu = smp_processor_id();
                 if (cpu != boot_cpuid) {
@@ -222,7 +229,6 @@ process_mcheck_info(unsigned long vector, unsigned long la_ptr,
 
 struct irqaction timer_irqaction = {
         .handler        = timer_interrupt,
-        .flags          = IRQF_DISABLED,
         .name           = "timer",
 };
 
diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c
index 4d4c046f708d..1383f8601a93 100644
--- a/arch/alpha/kernel/sys_nautilus.c
+++ b/arch/alpha/kernel/sys_nautilus.c
@@ -188,6 +188,10 @@ nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
 extern void free_reserved_mem(void *, void *);
 extern void pcibios_claim_one_bus(struct pci_bus *);
 
+static struct resource irongate_io = {
+        .name   = "Irongate PCI IO",
+        .flags  = IORESOURCE_IO,
+};
 static struct resource irongate_mem = {
         .name   = "Irongate PCI MEM",
         .flags  = IORESOURCE_MEM,
@@ -209,6 +213,7 @@ nautilus_init_pci(void)
 
         irongate = pci_get_bus_and_slot(0, 0);
         bus->self = irongate;
+        bus->resource[0] = &irongate_io;
         bus->resource[1] = &irongate_mem;
 
         pci_bus_size_bridges(bus);
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index 5cf4a481b8c5..a53cf03f49d5 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -280,15 +280,15 @@ titan_late_init(void)
          * all reported to the kernel as machine checks, so the handler
          * is a nop so it can be called to count the individual events.
          */
-        titan_request_irq(63+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(63+16, titan_intr_nop, 0,
                     "CChip Error", NULL);
-        titan_request_irq(62+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(62+16, titan_intr_nop, 0,
                     "PChip 0 H_Error", NULL);
-        titan_request_irq(61+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(61+16, titan_intr_nop, 0,
                     "PChip 1 H_Error", NULL);
-        titan_request_irq(60+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(60+16, titan_intr_nop, 0,
                     "PChip 0 C_Error", NULL);
-        titan_request_irq(59+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(59+16, titan_intr_nop, 0,
                     "PChip 1 C_Error", NULL);
 
         /* 
@@ -348,9 +348,9 @@ privateer_init_pci(void)
          * Hook a couple of extra err interrupts that the
          * common titan code won't.
          */
-        titan_request_irq(53+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(53+16, titan_intr_nop, 0,
                     "NMI", NULL);
-        titan_request_irq(50+16, titan_intr_nop, IRQF_DISABLED,
+        titan_request_irq(50+16, titan_intr_nop, 0,
                     "Temperature Warning", NULL);
 
         /*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 13b739469c51..1cacda426a0e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1183,9 +1183,9 @@ config ARM_NR_BANKS
         default 8
 
 config IWMMXT
-        bool "Enable iWMMXt support"
+        bool "Enable iWMMXt support" if !CPU_PJ4
         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
-        default y if PXA27x || PXA3xx || ARCH_MMP
+        default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
         help
           Enable support for iWMMXt context switching at run time if
           running on a CPU that supports it.
@@ -1439,6 +1439,16 @@ config ARM_ERRATA_775420
          to deadlock. This workaround puts DSB before executing ISB if
          an abort may occur on cache maintenance.
 
+config ARM_ERRATA_798181
+        bool "ARM errata: TLBI/DSB failure on Cortex-A15"
+        depends on CPU_V7 && SMP
+        help
+          On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
+          adequately shooting down all use of the old entries. This
+          option enables the Linux kernel workaround for this erratum
+          which sends an IPI to the CPUs that are running the same ASID
+          as the one being invalidated.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9b31f4311ea2..e5d2e6bbe76f 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -312,6 +312,13 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on PicoXcell based platforms.
 
+        config DEBUG_PXA_UART1
+                depends on ARCH_PXA
+                bool "Use PXA UART1 for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on PXA UART1.
+
         config DEBUG_REALVIEW_STD_PORT
                 bool "RealView Default UART"
                 depends on ARCH_REALVIEW
@@ -593,6 +600,8 @@ config DEBUG_LL_INCLUDE
         default "debug/mvebu.S" if DEBUG_MVEBU_UART
         default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
         default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
+        default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \
+                                 DEBUG_MMP_UART3
         default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
         default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
         default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c6255884cbb..c160215ab6d0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -51,7 +51,8 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
         integratorcp.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
-dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
+dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
+        kirkwood-dns320.dtb \
         kirkwood-dns325.dtb \
         kirkwood-dockstar.dtb \
         kirkwood-dreamplug.dtb \
@@ -65,6 +66,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
         kirkwood-lschlv2.dtb \
         kirkwood-lsxhl.dtb \
         kirkwood-mplcec4.dtb \
+        kirkwood-netgear_readynas_duo_v2.dtb \
         kirkwood-ns2.dtb \
         kirkwood-ns2lite.dtb \
         kirkwood-ns2max.dtb \
@@ -136,7 +138,9 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
         ccu9540.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
         r8a7740-armadillo800eva.dtb \
+        r8a7779-marzen-reference.dtb \
         sh73a0-kzm9g.dtb \
+        sh73a0-kzm9g-reference.dtb \
         sh7372-mackerel.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
         socfpga_vt.dtb
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index dd0c57dd9f30..3234875824dc 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -54,7 +54,7 @@
                 };
 
                 mvsdio@d00d4000 {
-                        pinctrl-0 = <&sdio_pins2>;
+                        pinctrl-0 = <&sdio_pins3>;
                         pinctrl-names = "default";
                         status = "okay";
                         /*
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 8188d138020e..a195debb67d3 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -59,6 +59,12 @@
                                              "mpp50", "mpp51", "mpp52";
                               marvell,function = "sd0";
                         };
+
+                        sdio_pins3: sdio-pins3 {
+                              marvell,pins = "mpp48", "mpp49", "mpp50",
+                                             "mpp51", "mpp52", "mpp53";
+                              marvell,function = "sd0";
+                        };
                 };
 
                 gpio0: gpio@d0018100 {
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 9de93096601a..aaa63d0a8096 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -191,8 +191,8 @@
 
                 prcmu: prcmu@80157000 {
                         compatible = "stericsson,db8500-prcmu";
-                        reg = <0x80157000 0x1000>;
-                        reg-names = "prcmu";
+                        reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
+                        reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
                         interrupts = <0 47 0x4>;
                         #address-cells = <1>;
                         #size-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
new file mode 100644
index 000000000000..5f21d4e427b0
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -0,0 +1,89 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
+
+/ {
+        model = "LaCie CloudBox";
+        compatible = "lacie,cloudbox", "marvell,kirkwood-88f6702", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_spi &pmx_uart0
+                                        &pmx_cloudbox_sata0 >;
+                        pinctrl-names = "default";
+
+                        pmx_cloudbox_sata0: pmx-cloudbox-sata0 {
+                                marvell,pins = "mpp15";
+                                marvell,function = "sata0";
+                        };
+                };
+
+                serial@12000 {
+                        clock-frequency = <166666667>;
+                        status = "okay";
+                };
+
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+
+                spi@10600 {
+                        status = "okay";
+
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "mx25l4005a";
+                                reg = <0>;
+                                spi-max-frequency = <20000000>;
+                                mode = <0>;
+
+                                partition@0 {
+                                        reg = <0x0 0x80000>;
+                                        label = "u-boot";
+                                };
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@1 {
+                        label = "Power push button";
+                        linux,code = <116>;
+                        gpios = <&gpio0 16 1>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                red-fail {
+                        label = "cloudbox:red:fail";
+                        gpios = <&gpio0 14 0>;
+                };
+                blue-sata {
+                        label = "cloudbox:blue:sata";
+                        gpios = <&gpio0 15 0>;
+                };
+        };
+
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio0 17 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index bd83b8fc7c83..c3573be7b92c 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -77,6 +77,7 @@
                 };
 
                 nand@3000000 {
+                        chip-delay = <40>;
                         status = "okay";
 
                         partition@0 {
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
new file mode 100644
index 000000000000..1ca66ab83ad6
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -0,0 +1,180 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6282.dtsi"
+
+/ {
+        model = "NETGEAR ReadyNAS Duo v2";
+        compatible = "netgear,readynas-duo-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+        memory { /* 256 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+
+                        pinctrl-0 = < &pmx_uart0
+                                      &pmx_button_power
+                                      &pmx_button_backup
+                                      &pmx_button_reset
+                                      &pmx_led_blue_power
+                                      &pmx_led_blue_activity
+                                      &pmx_led_blue_disk1
+                                      &pmx_led_blue_disk2
+                                      &pmx_led_blue_backup >;
+                        pinctrl-names = "default";
+
+                        pmx_button_power: pmx-button-power {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_backup: pmx-button-backup {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_reset: pmx-button-reset {
+                                marvell,pins = "mpp13";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue_power: pmx-led-blue-power {
+                                marvell,pins = "mpp31";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue_activity: pmx-led-blue-activity {
+                                marvell,pins = "mpp38";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue_disk1: pmx-led-blue-disk1 {
+                                marvell,pins = "mpp23";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue_disk2: pmx-led-blue-disk2 {
+                                marvell,pins = "mpp22";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue_backup: pmx-led-blue-backup {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                };
+
+                i2c@11000 {
+                        status = "okay";
+
+                        rs5c372a: rs5c372a@32 {
+                                compatible = "ricoh,rs5c372a";
+                                reg = <0x32>;
+                        };
+                };
+
+                serial@12000 {
+                        status = "okay";
+                };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x180000>;
+                                read-only;
+                        };
+
+                        partition@180000 {
+                                label = "u-boot-env";
+                                reg = <0x180000 0x20000>;
+                        };
+
+                        partition@200000 {
+                                label = "uImage";
+                                reg = <0x0200000 0x600000>;
+                        };
+
+                        partition@800000 {
+                                label = "minirootfs";
+                                reg = <0x0800000 0x1000000>;
+                        };
+
+                        partition@1800000 {
+                                label = "jffs2";
+                                reg = <0x1800000 0x6800000>;
+                        };
+                };
+
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                power_led {
+                        label = "status:blue:power_led";
+                        gpios = <&gpio0 31 1>;   /* GPIO 31 Active Low */
+                        linux,default-trigger = "default-on";
+                };
+                activity_led {
+                        label = "status:blue:activity_led";
+                        gpios = <&gpio1 6 1>;    /* GPIO 38 Active Low */
+                };
+                disk1_led {
+                        label = "status:blue:disk1_led";
+                        gpios = <&gpio0 23 1>;   /* GPIO 23 Active Low */
+                };
+                disk2_led {
+                        label = "status:blue:disk2_led";
+                        gpios = <&gpio0 22 1>;   /* GPIO 22 Active Low */
+                };
+                backup_led {
+                        label = "status:blue:backup_led";
+                        gpios = <&gpio0 29 1>;   /* GPIO 29 Active Low*/
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "Power Button";
+                        linux,code = <116>;     /* KEY_POWER */
+                        gpios = <&gpio1 15 1>;
+                };
+                button@2 {
+                        label = "Reset Button";
+                        linux,code = <0x198>;   /* KEY_RESTART */
+                        gpios = <&gpio0 13 1>;
+                };
+                button@3 {
+                        label = "Backup Button";
+                        linux,code = <133>;     /* KEY_COPY */
+                        gpios = <&gpio1 13 1>;
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                usb_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB 3.0 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 14 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index b79f5eb25589..adab1ab25733 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -3,6 +3,7 @@
 /include/ "kirkwood-ns2-common.dtsi"
 
 / {
+        /* This machine is embedded in the first LaCie CloudBox product. */
         model = "LaCie Network Space Mini v2";
         compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
 
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 1429ac05b36d..4e8b08c628c7 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -160,7 +160,7 @@
                         };
 
                         gpio@d4019000 {
-                                compatible = "mrvl,mmp-gpio";
+                                compatible = "marvell,mmp2-gpio";
                                 #address-cells = <1>;
                                 #size-cells = <1>;
                                 reg = <0xd4019000 0x1000>;
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 8aad00f81ed9..f7bec3b1ba32 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -13,6 +13,9 @@
         compatible = "marvell,orion5x";
         interrupt-parent = <&intc>;
 
+        aliases {
+                gpio0 = &gpio0;
+        };
         intc: interrupt-controller {
                 compatible = "marvell,orion-intc", "marvell,intc";
                 interrupt-controller;
@@ -32,7 +35,9 @@
                         #gpio-cells = <2>;
                         gpio-controller;
                         reg = <0x10100 0x40>;
-                        ngpio = <32>;
+                        ngpios = <32>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
                         interrupts = <6>, <7>, <8>, <9>;
                 };
 
@@ -91,7 +96,7 @@
                         reg = <0x90000 0x10000>,
                               <0xf2200000 0x800>;
                         reg-names = "regs", "sram";
-                        interrupts = <22>;
+                        interrupts = <28>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index 31a718696080..975dad21ac38 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -77,7 +77,7 @@
                         };
 
                         gpio@d4019000 {
-                                compatible = "mrvl,mmp-gpio";
+                                compatible = "marvell,mmp-gpio";
                                 #address-cells = <1>;
                                 #size-cells = <1>;
                                 reg = <0xd4019000 0x1000>;
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index 825aaca33034..0247c622f580 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -89,7 +89,7 @@
                         };
 
                         gpio@d4019000 {
-                                compatible = "mrvl,mmp-gpio";
+                                compatible = "marvell,mmp-gpio";
                                 #address-cells = <1>;
                                 #size-cells = <1>;
                                 reg = <0xd4019000 0x1000>;
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
new file mode 100644
index 000000000000..72be4c87cfb5
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -0,0 +1,47 @@
+/*
+ * Reference Device Tree Source for the Marzen board
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Simon Horman
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "r8a7779.dtsi"
+
+/ {
+        model = "marzen";
+        compatible = "renesas,marzen-reference", "renesas,r8a7779";
+
+        chosen {
+                bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x60000000 0x40000000>;
+        };
+
+        fixedregulator3v3: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        lan0@18000000 {
+                compatible = "smsc,lan9220", "smsc,lan9115";
+                reg = <0x18000000 0x100>;
+                phy-mode = "mii";
+                interrupt-parent = <&gic>;
+                interrupts = <0 28 0x4>;
+                reg-io-width = <4>;
+                vddvario-supply = <&fixedregulator3v3>;
+                vdd33a-supply = <&fixedregulator3v3>;
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
new file mode 100644
index 000000000000..fe5c6f213271
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Device Tree Source for Renesas r8a7779
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Simon Horman
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "renesas,r8a7779";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <3>;
+                };
+        };
+
+        gic: interrupt-controller@f0001000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xf0001000 0x1000>,
+                      <0xf0000100 0x100>;
+        };
+
+        i2c0: i2c@0xffc70000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc70000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 79 0x4>;
+        };
+
+        i2c1: i2c@0xffc71000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc71000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 82 0x4>;
+        };
+
+        i2c2: i2c@0xffc72000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc72000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 80 0x4>;
+        };
+
+        i2c3: i2c@0xffc73000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc73000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 81 0x4>;
+        };
+
+        thermal@ffc48000 {
+                compatible = "renesas,rcar-thermal";
+                reg = <0xffc48000 0x38>;
+        };
+
+        sata: sata@fc600000 {
+                compatible = "renesas,rcar-sata";
+                reg = <0xfc600000 0x2000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 100 0x4>;
+        };
+};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
new file mode 100644
index 000000000000..f33b5ccb7446
--- /dev/null
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -0,0 +1,66 @@
+/*
+ * Device Tree Source for the KZM-A9-GT board
+ *
+ * Copyright (C) 2012 Horms Solutions Ltd.
+ *
+ * Based on sh73a0-kzm9g.dts
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "sh73a0.dtsi"
+
+/ {
+        model = "KZM-A9-GT";
+        compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
+
+        chosen {
+                bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x41000000 0x1e800000>;
+        };
+
+        reg_1p8v: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        reg_3p3v: regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+};
+
+&mmcif {
+        bus-width = <8>;
+        vmmc-supply = <&reg_1p8v>;
+        status = "okay";
+};
+
+&sdhi0 {
+        vmmc-supply = <&reg_3p3v>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&sdhi2 {
+        vmmc-supply = <&reg_3p3v>;
+        bus-width = <4>;
+        broken-cd;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sh73a0-reference.dtsi b/arch/arm/boot/dts/sh73a0-reference.dtsi
deleted file mode 100644
index d4bb0125b2b2..000000000000
--- a/arch/arm/boot/dts/sh73a0-reference.dtsi
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Device Tree Source for the SH73A0 SoC
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/include/ "sh73a0.dtsi"
-
-/ {
-        compatible = "renesas,sh73a0";
-
-        mmcif: mmcif@0x10010000 {
-                compatible = "renesas,sh-mmcif";
-                reg = <0xe6bd0000 0x100>;
-                interrupt-parent = <&gic>;
-                interrupts = <0 140 0x4
-                              0 141 0x4>;
-                reg-io-width = <4>;
-        };
-};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 8a59465d0231..3e4d383ac6d9 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -97,4 +97,48 @@
                               0 189 0x4
                               0 190 0x4>;
         };
+
+        mmcif: mmcif@0x10010000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0xe6bd0000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 140 0x4
+                              0 141 0x4>;
+                reg-io-width = <4>;
+                status = "disabled";
+        };
+
+        sdhi0: sdhi@0xee100000 {
+                compatible = "renesas,r8a7740-sdhi";
+                reg = <0xee100000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 83 4
+                                0 84 4
+                                0 85 4>;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
+        sdhi1: sdhi@0xee120000 {
+                compatible = "renesas,r8a7740-sdhi";
+                reg = <0xee120000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 88 4
+                                0 89 4>;
+                toshiba,mmc-wrprotect-disable;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        sdhi2: sdhi@0xee140000 {
+                compatible = "renesas,r8a7740-sdhi";
+                reg = <0xee140000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 104 4
+                                0 105 4>;
+                toshiba,mmc-wrprotect-disable;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 1513c1927cc8..122ae94076c8 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -89,7 +89,7 @@
                 pinmux: pinmux@e0700000 {
                         compatible = "st,spear1310-pinmux";
                         reg = <0xe0700000 0x1000>;
-                        #gpio-range-cells = <2>;
+                        #gpio-range-cells = <3>;
                 };
 
                 apb {
@@ -212,7 +212,7 @@
                                 interrupt-controller;
                                 gpio-controller;
                                 #gpio-cells = <2>;
-                                gpio-ranges = <&pinmux 0 246>;
+                                gpio-ranges = <&pinmux 0 0 246>;
                                 status = "disabled";
 
                                 st-plgpio,ngpio = <246>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 34da11aa6795..c511c4772efd 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -63,7 +63,7 @@
                 pinmux: pinmux@e0700000 {
                         compatible = "st,spear1340-pinmux";
                         reg = <0xe0700000 0x1000>;
-                        #gpio-range-cells = <2>;
+                        #gpio-range-cells = <3>;
                 };
 
                 pwm: pwm@e0180000 {
@@ -127,7 +127,7 @@
                                 interrupt-controller;
                                 gpio-controller;
                                 #gpio-cells = <2>;
-                                gpio-ranges = <&pinmux 0 252>;
+                                gpio-ranges = <&pinmux 0 0 252>;
                                 status = "disabled";
 
                                 st-plgpio,ngpio = <250>;
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index ab45b8c81982..95372080eea6 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -25,7 +25,7 @@
                 pinmux: pinmux@b4000000 {
                         compatible = "st,spear310-pinmux";
                         reg = <0xb4000000 0x1000>;
-                        #gpio-range-cells = <2>;
+                        #gpio-range-cells = <3>;
                 };
 
                 fsmc: flash@44000000 {
@@ -102,7 +102,7 @@
                                 interrupt-controller;
                                 gpio-controller;
                                 #gpio-cells = <2>;
-                                gpio-ranges = <&pinmux 0 102>;
+                                gpio-ranges = <&pinmux 0 0 102>;
                                 status = "disabled";
 
                                 st-plgpio,ngpio = <102>;
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index caa5520b1fd4..ffea342aeec9 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -24,7 +24,7 @@
                 pinmux: pinmux@b3000000 {
                         compatible = "st,spear320-pinmux";
                         reg = <0xb3000000 0x1000>;
-                        #gpio-range-cells = <2>;
+                        #gpio-range-cells = <3>;
                 };
 
                 clcd@90000000 {
@@ -130,7 +130,7 @@
                                 interrupt-controller;
                                 gpio-controller;
                                 #gpio-cells = <2>;
-                                gpio-ranges = <&pinmux 0 102>;
+                                gpio-ranges = <&pinmux 0 0 102>;
                                 status = "disabled";
 
                                 st-plgpio,ngpio = <102>;
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
index 9aaad36a1728..7c868139bdb0 100644
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ b/arch/arm/configs/da8xx_omapl_defconfig
@@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_MODULES=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 3edc78a40b66..c86fd75e181a 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_MODULES=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 13482ea58b09..7205a7a889a5 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -10,45 +10,48 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_KIRKWOOD=y
+CONFIG_MACH_D2NET_V2=y
 CONFIG_MACH_DB88F6281_BP=y
+CONFIG_MACH_DOCKSTAR=y
+CONFIG_MACH_ESATA_SHEEVAPLUG=y
+CONFIG_MACH_GURUPLUG=y
+CONFIG_MACH_INETSPACE_V2=y
+CONFIG_MACH_MV88F6281GTW_GE=y
+CONFIG_MACH_NET2BIG_V2=y
+CONFIG_MACH_NET5BIG_V2=y
+CONFIG_MACH_NETSPACE_MAX_V2=y
+CONFIG_MACH_NETSPACE_V2=y
+CONFIG_MACH_OPENRD_BASE=y
+CONFIG_MACH_OPENRD_CLIENT=y
+CONFIG_MACH_OPENRD_ULTIMATE=y
 CONFIG_MACH_RD88F6192_NAS=y
 CONFIG_MACH_RD88F6281=y
-CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
-CONFIG_MACH_ESATA_SHEEVAPLUG=y
-CONFIG_MACH_GURUPLUG=y
-CONFIG_MACH_DREAMPLUG_DT=y
-CONFIG_MACH_ICONNECT_DT=y
+CONFIG_MACH_T5325=y
+CONFIG_MACH_TS219=y
+CONFIG_MACH_TS41X=y
+CONFIG_MACH_CLOUDBOX_DT=y
 CONFIG_MACH_DLINK_KIRKWOOD_DT=y
-CONFIG_MACH_IB62X0_DT=y
-CONFIG_MACH_TS219_DT=y
 CONFIG_MACH_DOCKSTAR_DT=y
+CONFIG_MACH_DREAMPLUG_DT=y
 CONFIG_MACH_GOFLEXNET_DT=y
-CONFIG_MACH_LSXL_DT=y
+CONFIG_MACH_GURUPLUG_DT=y
+CONFIG_MACH_IB62X0_DT=y
+CONFIG_MACH_ICONNECT_DT=y
+CONFIG_MACH_INETSPACE_V2_DT=y
 CONFIG_MACH_IOMEGA_IX2_200_DT=y
 CONFIG_MACH_KM_KIRKWOOD_DT=y
-CONFIG_MACH_INETSPACE_V2_DT=y
+CONFIG_MACH_LSXL_DT=y
 CONFIG_MACH_MPLCEC4_DT=y
-CONFIG_MACH_NETSPACE_V2_DT=y
-CONFIG_MACH_NETSPACE_MAX_V2_DT=y
 CONFIG_MACH_NETSPACE_LITE_V2_DT=y
+CONFIG_MACH_NETSPACE_MAX_V2_DT=y
 CONFIG_MACH_NETSPACE_MINI_V2_DT=y
+CONFIG_MACH_NETSPACE_V2_DT=y
+CONFIG_MACH_NSA310_DT=y
 CONFIG_MACH_OPENBLOCKS_A6_DT=y
+CONFIG_MACH_READYNAS_DT=y
 CONFIG_MACH_TOPKICK_DT=y
-CONFIG_MACH_TS219=y
-CONFIG_MACH_TS41X=y
-CONFIG_MACH_DOCKSTAR=y
-CONFIG_MACH_OPENRD_BASE=y
-CONFIG_MACH_OPENRD_CLIENT=y
-CONFIG_MACH_OPENRD_ULTIMATE=y
-CONFIG_MACH_NETSPACE_V2=y
-CONFIG_MACH_INETSPACE_V2=y
-CONFIG_MACH_NETSPACE_MAX_V2=y
-CONFIG_MACH_D2NET_V2=y
-CONFIG_MACH_NET2BIG_V2=y
-CONFIG_MACH_NET5BIG_V2=y
-CONFIG_MACH_T5325=y
-CONFIG_MACH_NSA310_DT=y
+CONFIG_MACH_TS219_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig
index 2b8f7affc1eb..44f929167d7e 100644
--- a/arch/arm/configs/msm_defconfig
+++ b/arch/arm/configs/msm_defconfig
@@ -1,72 +1,136 @@
-CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_MSM=y
-CONFIG_MACH_HALIBUT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ARCH_MSM8X60=y
+CONFIG_ARCH_MSM8960=y
+CONFIG_SMP=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyMSM,115200n8"
-CONFIG_PM=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_CLEANCACHE=y
+CONFIG_CC_STACKPROTECTOR=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_NET=y
+CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
+# CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
+CONFIG_CFG80211=y
+CONFIG_RFKILL=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_PPP=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_PHYLIB=y
+CONFIG_SLIP=y
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_ZAURUS is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_INPUT_JOYSTICK=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
-# CONFIG_HWMON is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SSBI=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_THERMAL=y
+CONFIG_REGULATOR=y
+CONFIG_MEDIA_SUPPORT=y
 CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_FB_MSM=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
 CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_INOTIFY=y
+CONFIG_RTC_CLASS=y
+CONFIG_STAGING=y
+CONFIG_MSM_IOMMU=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_CIFS=y
+CONFIG_PRINTK_TIME=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_TIMER_STATS=y
 CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
+CONFIG_DYNAMIC_DEBUG=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index bd07864f14a0..33903ca0d879 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -93,6 +93,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
 CONFIG_SENSORS_LIS3LV02D=m
 CONFIG_SENSORS_TSL2550=m
 CONFIG_SENSORS_LIS3_I2C=m
+CONFIG_BMP085_I2C=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index 720799fd3a81..dff714d886d5 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -24,7 +24,7 @@ extern struct arm_delay_ops {
         void (*delay)(unsigned long);
         void (*const_udelay)(unsigned long);
         void (*udelay)(unsigned long);
-        bool const_clock;
+        unsigned long ticks_per_jiffy;
 } arm_delay_ops;
 
 #define __delay(n)              arm_delay_ops.delay(n)
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 8c5e828f484d..91b99abe7a95 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page);
 #endif
 #endif
 
+/*
+ * Needed to be able to broadcast the TLB invalidation for kmap.
+ */
+#ifdef CONFIG_ARM_ERRATA_798181
+#undef ARCH_NEEDS_KMAP_HIGH_GET
+#endif
+
 #ifdef ARCH_NEEDS_KMAP_HIGH_GET
 extern void *kmap_high_get(struct page *page);
 #else
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 863a6611323c..a7b85e0d0cc1 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm);
 void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
 #define init_new_context(tsk,mm)        ({ atomic64_set(&mm->context.id, 0); 0; })
 
+DECLARE_PER_CPU(atomic64_t, active_asids);
+
 #else   /* !CONFIG_CPU_HAS_ASID */
 
 #ifdef CONFIG_MMU
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 4db8c8820f0d..9e9c041358ca 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void)
                 isb();
 }
 
+#ifdef CONFIG_ARM_ERRATA_798181
+static inline void dummy_flush_tlb_a15_erratum(void)
+{
+        /*
+         * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
+         */
+        asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
+        dsb();
+}
+#else
+static inline void dummy_flush_tlb_a15_erratum(void)
+{
+}
+#endif
+
 /*
  *      flush_pmd_entry
  *
diff --git a/arch/arm/include/debug/pxa.S b/arch/arm/include/debug/pxa.S
new file mode 100644
index 000000000000..e1e795aa3d7f
--- /dev/null
+++ b/arch/arm/include/debug/pxa.S
@@ -0,0 +1,33 @@
+/*
+ * Early serial output macro for Marvell PXA/MMP SoC
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * Copyright (C) 2013 Haojian Zhuang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#if defined(CONFIG_DEBUG_PXA_UART1)
+#define PXA_UART_REG_PHYS_BASE  0x40100000
+#define PXA_UART_REG_VIRT_BASE  0xf2100000
+#elif defined(CONFIG_DEBUG_MMP_UART2)
+#define PXA_UART_REG_PHYS_BASE  0xd4017000
+#define PXA_UART_REG_VIRT_BASE  0xfe017000
+#elif defined(CONFIG_DEBUG_MMP_UART3)
+#define PXA_UART_REG_PHYS_BASE  0xd4018000
+#define PXA_UART_REG_VIRT_BASE  0xfe018000
+#else
+#error "Select uart for DEBUG_LL"
+#endif
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =PXA_UART_REG_PHYS_BASE
+        ldr     \rv, =PXA_UART_REG_VIRT_BASE
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 3248cde504ed..fefd7f971437 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -276,7 +276,13 @@ ENDPROC(ftrace_graph_caller_old)
  */
 
 .macro mcount_enter
+/*
+ * This pad compensates for the push {lr} at the call site.  Note that we are
+ * unable to unwind through a function which does not otherwise save its lr.
+ */
+ UNWIND(.pad    #4)
         stmdb   sp!, {r0-r3, lr}
+ UNWIND(.save   {r0-r3, lr})
 .endm
 
 .macro mcount_get_lr reg
@@ -289,6 +295,7 @@ ENDPROC(ftrace_graph_caller_old)
 .endm
 
 ENTRY(__gnu_mcount_nc)
+UNWIND(.fnstart)
 #ifdef CONFIG_DYNAMIC_FTRACE
         mov     ip, lr
         ldmia   sp!, {lr}
@@ -296,17 +303,22 @@ ENTRY(__gnu_mcount_nc)
 #else
         __mcount
 #endif
+UNWIND(.fnend)
 ENDPROC(__gnu_mcount_nc)
 
 #ifdef CONFIG_DYNAMIC_FTRACE
 ENTRY(ftrace_caller)
+UNWIND(.fnstart)
         __ftrace_caller
+UNWIND(.fnend)
 ENDPROC(ftrace_caller)
 #endif
 
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
 ENTRY(ftrace_graph_caller)
+UNWIND(.fnstart)
         __ftrace_graph_caller
+UNWIND(.fnend)
 ENDPROC(ftrace_graph_caller)
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index e0eb9a1cae77..8bac553fe213 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -267,7 +267,7 @@ __create_page_tables:
         addne   r6, r6, #1 << SECTION_SHIFT
         strne   r6, [r3]
 
-#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
+#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
         sub     r4, r4, #4                      @ Fixup page table pointer
                                                 @ for 64-bit descriptors
 #endif
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 96093b75ab90..5dc1aa6f0f7d 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -966,7 +966,7 @@ static void reset_ctrl_regs(void *unused)
         }
 
         if (err) {
-                pr_warning("CPU %d debug is powered down!\n", cpu);
+                pr_warn_once("CPU %d debug is powered down!\n", cpu);
                 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
                 return;
         }
@@ -987,7 +987,7 @@ clear_vcr:
         isb();
 
         if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
-                pr_warning("CPU %d failed to disable vector catch\n", cpu);
+                pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
                 return;
         }
 
@@ -1007,7 +1007,7 @@ clear_vcr:
         }
 
         if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
-                pr_warning("CPU %d failed to clear debug register pairs\n", cpu);
+                pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
                 return;
         }
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 3f6cbb2e3eda..d343a6c3a6d1 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
         printk("%s", buf);
 }
 
+static void __init cpuid_init_hwcaps(void)
+{
+        unsigned int divide_instrs;
+
+        if (cpu_architecture() < CPU_ARCH_ARMv7)
+                return;
+
+        divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
+
+        switch (divide_instrs) {
+        case 2:
+                elf_hwcap |= HWCAP_IDIVA;
+        case 1:
+                elf_hwcap |= HWCAP_IDIVT;
+        }
+}
+
 static void __init feat_v6_fixup(void)
 {
         int id = read_cpuid_id();
@@ -483,8 +500,11 @@ static void __init setup_processor(void)
         snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
                  list->elf_name, ENDIANNESS);
         elf_hwcap = list->elf_hwcap;
+
+        cpuid_init_hwcaps();
+
 #ifndef CONFIG_ARM_THUMB
-        elf_hwcap &= ~HWCAP_THUMB;
+        elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
 #endif
 
         feat_v6_fixup();
@@ -524,7 +544,7 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size)
         size -= start & ~PAGE_MASK;
         bank->start = PAGE_ALIGN(start);
 
-#ifndef CONFIG_LPAE
+#ifndef CONFIG_ARM_LPAE
         if (bank->start + size < bank->start) {
                 printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
                         "32-bit physical address space\n", (long long)start);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 79078edbb9bc..1f2ccccaf009 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -673,9 +673,6 @@ static int cpufreq_callback(struct notifier_block *nb,
         if (freq->flags & CPUFREQ_CONST_LOOPS)
                 return NOTIFY_OK;
 
-        if (arm_delay_ops.const_clock)
-                return NOTIFY_OK;
-
         if (!per_cpu(l_p_j_ref, cpu)) {
                 per_cpu(l_p_j_ref, cpu) =
                         per_cpu(cpu_data, cpu).loops_per_jiffy;
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index bd0300531399..e82e1d248772 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -12,6 +12,7 @@
 
 #include <asm/smp_plat.h>
 #include <asm/tlbflush.h>
+#include <asm/mmu_context.h>
 
 /**********************************************************************/
 
@@ -69,12 +70,72 @@ static inline void ipi_flush_bp_all(void *ignored)
         local_flush_bp_all();
 }
 
+#ifdef CONFIG_ARM_ERRATA_798181
+static int erratum_a15_798181(void)
+{
+        unsigned int midr = read_cpuid_id();
+
+        /* Cortex-A15 r0p0..r3p2 affected */
+        if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2)
+                return 0;
+        return 1;
+}
+#else
+static int erratum_a15_798181(void)
+{
+        return 0;
+}
+#endif
+
+static void ipi_flush_tlb_a15_erratum(void *arg)
+{
+        dmb();
+}
+
+static void broadcast_tlb_a15_erratum(void)
+{
+        if (!erratum_a15_798181())
+                return;
+
+        dummy_flush_tlb_a15_erratum();
+        smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum,
+                               NULL, 1);
+}
+
+static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
+{
+        int cpu;
+        cpumask_t mask = { CPU_BITS_NONE };
+
+        if (!erratum_a15_798181())
+                return;
+
+        dummy_flush_tlb_a15_erratum();
+        for_each_online_cpu(cpu) {
+                if (cpu == smp_processor_id())
+                        continue;
+                /*
+                 * We only need to send an IPI if the other CPUs are running
+                 * the same ASID as the one being invalidated. There is no
+                 * need for locking around the active_asids check since the
+                 * switch_mm() function has at least one dmb() (as required by
+                 * this workaround) in case a context switch happens on
+                 * another CPU after the condition below.
+                 */
+                if (atomic64_read(&mm->context.id) ==
+                    atomic64_read(&per_cpu(active_asids, cpu)))
+                        cpumask_set_cpu(cpu, &mask);
+        }
+        smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
+}
+
 void flush_tlb_all(void)
 {
         if (tlb_ops_need_broadcast())
                 on_each_cpu(ipi_flush_tlb_all, NULL, 1);
         else
                 local_flush_tlb_all();
+        broadcast_tlb_a15_erratum();
 }
 
 void flush_tlb_mm(struct mm_struct *mm)
@@ -83,6 +144,7 @@ void flush_tlb_mm(struct mm_struct *mm)
                 on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1);
         else
                 local_flush_tlb_mm(mm);
+        broadcast_tlb_mm_a15_erratum(mm);
 }
 
 void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
@@ -95,6 +157,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
                                         &ta, 1);
         } else
                 local_flush_tlb_page(vma, uaddr);
+        broadcast_tlb_mm_a15_erratum(vma->vm_mm);
 }
 
 void flush_tlb_kernel_page(unsigned long kaddr)
@@ -105,6 +168,7 @@ void flush_tlb_kernel_page(unsigned long kaddr)
                 on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
         } else
                 local_flush_tlb_kernel_page(kaddr);
+        broadcast_tlb_a15_erratum();
 }
 
 void flush_tlb_range(struct vm_area_struct *vma,
@@ -119,6 +183,7 @@ void flush_tlb_range(struct vm_area_struct *vma,
                                         &ta, 1);
         } else
                 local_flush_tlb_range(vma, start, end);
+        broadcast_tlb_mm_a15_erratum(vma->vm_mm);
 }
 
 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
@@ -130,6 +195,7 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
                 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
         } else
                 local_flush_tlb_kernel_range(start, end);
+        broadcast_tlb_a15_erratum();
 }
 
 void flush_bp_all(void)
diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c
index c9a17316e9fe..0e4cfe123b38 100644
--- a/arch/arm/kvm/vgic.c
+++ b/arch/arm/kvm/vgic.c
@@ -883,8 +883,7 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
                           lr, irq, vgic_cpu->vgic_lr[lr]);
                 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
                 vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
-
-                goto out;
+                return true;
         }
 
         /* Try to use another LR for this interrupt */
@@ -898,7 +897,6 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
         vgic_cpu->vgic_irq_lr_map[irq] = lr;
         set_bit(lr, vgic_cpu->lr_used);
 
-out:
         if (!vgic_irq_is_edge(vcpu, irq))
                 vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
 
@@ -1018,21 +1016,6 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
 
         kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
 
-        /*
-         * We do not need to take the distributor lock here, since the only
-         * action we perform is clearing the irq_active_bit for an EOIed
-         * level interrupt.  There is a potential race with
-         * the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we
-         * check if the interrupt is already active. Two possibilities:
-         *
-         * - The queuing is occurring on the same vcpu: cannot happen,
-         *   as we're already in the context of this vcpu, and
-         *   executing the handler
-         * - The interrupt has been migrated to another vcpu, and we
-         *   ignore this interrupt for this run. Big deal. It is still
-         *   pending though, and will get considered when this vcpu
-         *   exits.
-         */
         if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
                 /*
                  * Some level interrupts have been EOIed. Clear their
@@ -1054,6 +1037,13 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
                         } else {
                                 vgic_cpu_irq_clear(vcpu, irq);
                         }
+
+                        /*
+                         * Despite being EOIed, the LR may not have
+                         * been marked as empty.
+                         */
+                        set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
+                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
                 }
         }
 
@@ -1064,9 +1054,8 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
 }
 
 /*
- * Sync back the VGIC state after a guest run. We do not really touch
- * the distributor here (the irq_pending_on_cpu bit is safe to set),
- * so there is no need for taking its lock.
+ * Sync back the VGIC state after a guest run. The distributor lock is
+ * needed so we don't get preempted in the middle of the state processing.
  */
 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
 {
@@ -1112,10 +1101,14 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
 
 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
 {
+        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
+
         if (!irqchip_in_kernel(vcpu->kvm))
                 return;
 
+        spin_lock(&dist->lock);
         __kvm_vgic_sync_hwstate(vcpu);
+        spin_unlock(&dist->lock);
 }
 
 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index 6b93f6a1a3c7..64dbfa57204a 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -58,7 +58,7 @@ static void __timer_delay(unsigned long cycles)
 static void __timer_const_udelay(unsigned long xloops)
 {
         unsigned long long loops = xloops;
-        loops *= loops_per_jiffy;
+        loops *= arm_delay_ops.ticks_per_jiffy;
         __timer_delay(loops >> UDELAY_SHIFT);
 }
 
@@ -73,11 +73,13 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
                 pr_info("Switching to timer-based delay loop\n");
                 delay_timer                     = timer;
                 lpj_fine                        = timer->freq / HZ;
-                loops_per_jiffy                 = lpj_fine;
+
+                /* cpufreq may scale loops_per_jiffy, so keep a private copy */
+                arm_delay_ops.ticks_per_jiffy   = lpj_fine;
                 arm_delay_ops.delay             = __timer_delay;
                 arm_delay_ops.const_udelay      = __timer_const_udelay;
                 arm_delay_ops.udelay            = __timer_udelay;
-                arm_delay_ops.const_clock       = true;
+
                 delay_calibrated                = true;
         } else {
                 pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index e698f26cc0cb..52e4bb5cf12d 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -22,19 +22,9 @@
 
 static struct map_desc cns3xxx_io_desc[] __initdata = {
         {
-                .virtual        = CNS3XXX_TC11MP_TWD_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
-                .length         = SZ_4K,
+                .virtual        = CNS3XXX_TC11MP_SCU_BASE_VIRT,
+                .pfn            = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
+                .length         = SZ_8K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = CNS3XXX_TIMER1_2_3_BASE_VIRT,
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 191c8e57f289..b1021aafa481 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -94,10 +94,10 @@
 #define RTC_INTR_STS_OFFSET                     0x34
 
 #define CNS3XXX_MISC_BASE                       0x76000000      /* Misc Control */
-#define CNS3XXX_MISC_BASE_VIRT                  0xFFF07000      /* Misc Control */
+#define CNS3XXX_MISC_BASE_VIRT                  0xFB000000      /* Misc Control */
 
 #define CNS3XXX_PM_BASE                         0x77000000      /* Power Management Control */
-#define CNS3XXX_PM_BASE_VIRT                    0xFFF08000
+#define CNS3XXX_PM_BASE_VIRT                    0xFB001000
 
 #define PM_CLK_GATE_OFFSET                      0x00
 #define PM_SOFT_RST_OFFSET                      0x04
@@ -109,7 +109,7 @@
 #define PM_PLL_HM_PD_OFFSET                     0x1C
 
 #define CNS3XXX_UART0_BASE                      0x78000000      /* UART 0 */
-#define CNS3XXX_UART0_BASE_VIRT                 0xFFF09000
+#define CNS3XXX_UART0_BASE_VIRT                 0xFB002000
 
 #define CNS3XXX_UART1_BASE                      0x78400000      /* UART 1 */
 #define CNS3XXX_UART1_BASE_VIRT                 0xFFF0A000
@@ -130,7 +130,7 @@
 #define CNS3XXX_I2S_BASE_VIRT                   0xFFF10000
 
 #define CNS3XXX_TIMER1_2_3_BASE                 0x7C800000      /* Timer */
-#define CNS3XXX_TIMER1_2_3_BASE_VIRT            0xFFF10800
+#define CNS3XXX_TIMER1_2_3_BASE_VIRT            0xFB003000
 
 #define TIMER1_COUNTER_OFFSET                   0x00
 #define TIMER1_AUTO_RELOAD_OFFSET               0x04
@@ -227,16 +227,16 @@
  * Testchip peripheral and fpga gic regions
  */
 #define CNS3XXX_TC11MP_SCU_BASE                 0x90000000      /* IRQ, Test chip */
-#define CNS3XXX_TC11MP_SCU_BASE_VIRT            0xFF000000
+#define CNS3XXX_TC11MP_SCU_BASE_VIRT            0xFB004000
 
 #define CNS3XXX_TC11MP_GIC_CPU_BASE             0x90000100      /* Test chip interrupt controller CPU interface */
-#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT        0xFF000100
+#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT        (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
 
 #define CNS3XXX_TC11MP_TWD_BASE                 0x90000600
-#define CNS3XXX_TC11MP_TWD_BASE_VIRT            0xFF000600
+#define CNS3XXX_TC11MP_TWD_BASE_VIRT            (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
 
 #define CNS3XXX_TC11MP_GIC_DIST_BASE            0x90001000      /* Test chip interrupt controller distributor */
-#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT       0xFF001000
+#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT       (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
 
 #define CNS3XXX_TC11MP_L220_BASE                0x92002000      /* L220 registers */
 #define CNS3XXX_TC11MP_L220_BASE_VIRT           0xFF002000
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 12e6f756361d..1332de8c52c9 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -297,11 +297,7 @@ static const short da830_evm_emif25_pins[] = {
         -1
 };
 
-#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
-#define HAS_MMC 1
-#else
-#define HAS_MMC 0
-#endif
+#define HAS_MMC         IS_ENABLED(CONFIG_MMC_DAVINCI)
 
 #ifdef CONFIG_DA830_UI_NAND
 static struct mtd_partition da830_evm_nand_partitions[] = {
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index ba739e5ac3fb..8a24b6c6339f 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -335,12 +335,7 @@ static const short da850_evm_nor_pins[] = {
         -1
 };
 
-#if defined(CONFIG_MMC_DAVINCI) || \
-    defined(CONFIG_MMC_DAVINCI_MODULE)
-#define HAS_MMC 1
-#else
-#define HAS_MMC 0
-#endif
+#define HAS_MMC         IS_ENABLED(CONFIG_MMC_DAVINCI)
 
 static inline void da850_evm_setup_nor_nand(void)
 {
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index c0206d5f2bf6..fc8e38e31b89 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -749,26 +749,11 @@ static int davinci_phy_fixup(struct phy_device *phydev)
         return 0;
 }
 
-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
-    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
-#define HAS_ATA 1
-#else
-#define HAS_ATA 0
-#endif
-
-#if defined(CONFIG_MTD_PHYSMAP) || \
-    defined(CONFIG_MTD_PHYSMAP_MODULE)
-#define HAS_NOR 1
-#else
-#define HAS_NOR 0
-#endif
-
-#if defined(CONFIG_MTD_NAND_DAVINCI) || \
-    defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
-#define HAS_NAND 1
-#else
-#define HAS_NAND 0
-#endif
+#define HAS_ATA         IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
+
+#define HAS_NOR         IS_ENABLED(CONFIG_MTD_PHYSMAP)
+
+#define HAS_NAND        IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
 
 static __init void davinci_evm_init(void)
 {
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index de7adff324dc..03785e0e9429 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -117,12 +117,7 @@ static struct platform_device davinci_nand_device = {
         },
 };
 
-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
-    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
-#define HAS_ATA 1
-#else
-#define HAS_ATA 0
-#endif
+#define HAS_ATA         IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
 
 /* CPLD Register 0 bits to control ATA */
 #define DM646X_EVM_ATA_RST              BIT(0)
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index b70e83c03bed..2bc112adf565 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -166,20 +166,9 @@ static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
         .wires          = 4,
 };
 
+#define HAS_ATA         IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
 
-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
-        defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
-#define HAS_ATA 1
-#else
-#define HAS_ATA 0
-#endif
-
-#if defined(CONFIG_MTD_NAND_DAVINCI) || \
-        defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
-#define HAS_NAND 1
-#else
-#define HAS_NAND 0
-#endif
+#define HAS_NAND        IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
 
 static __init void davinci_ntosd2_init(void)
 {
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index f6927df2dda8..a7068a3aa9d3 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -119,7 +119,7 @@ void __init davinci_init_ide(void)
         platform_device_register(&ide_device);
 }
 
-#if     defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_DAVINCI)
 
 static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
 
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 2b4c648f99b6..b0a6b522575f 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -18,7 +18,7 @@
 #define DA8XX_USB0_BASE         0x01e00000
 #define DA8XX_USB1_BASE         0x01e25000
 
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 static struct musb_hdrc_eps_bits musb_eps[] = {
         { "ep1_tx", 8, },
         { "ep1_rx", 8, },
diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
index d2afb4dd82ab..b5cc77d2380b 100644
--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
@@ -47,9 +47,13 @@ static void __raw_writel(unsigned int value, unsigned int ptr)
 
 static inline void putc(int c)
 {
-        /* Transmit fifo not full?  */
-        while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)
-                ;
+        int i;
+
+        for (i = 0; i < 10000; i++) {
+                /* Transmit fifo not full? */
+                if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
+                        break;
+        }
 
         __raw_writeb(c, PHYS_UART_DATA);
 }
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5a800bfcec5b..5bf4a97ab241 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -110,6 +110,8 @@ void tzic_handle_irq(struct pt_regs *);
 
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
+extern u32 imx_get_cpu_arg(int cpu);
+extern void imx_set_cpu_arg(int cpu, u32 arg);
 extern void v7_cpu_resume(void);
 extern u32 *pl310_get_save_ptr(void);
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 7bc5fe15dda2..361a253e2b63 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -46,11 +46,23 @@ static inline void cpu_enter_lowpower(void)
 void imx_cpu_die(unsigned int cpu)
 {
         cpu_enter_lowpower();
+        /*
+         * We use the cpu jumping argument register to sync with
+         * imx_cpu_kill() which is running on cpu0 and waiting for
+         * the register being cleared to kill the cpu.
+         */
+        imx_set_cpu_arg(cpu, ~0);
         cpu_do_idle();
 }
 
 int imx_cpu_kill(unsigned int cpu)
 {
+        unsigned long timeout = jiffies + msecs_to_jiffies(50);
+
+        while (imx_get_cpu_arg(cpu) == 0)
+                if (time_after(jiffies, timeout))
+                        return 0;
         imx_enable_cpu(cpu, false);
+        imx_set_cpu_arg(cpu, 0);
         return 1;
 }
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index e15f1555c59b..09a742f8c7ab 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -43,6 +43,18 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
                        src_base + SRC_GPR1 + cpu * 8);
 }
 
+u32 imx_get_cpu_arg(int cpu)
+{
+        cpu = cpu_logical_map(cpu);
+        return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
+}
+
+void imx_set_cpu_arg(int cpu, u32 arg)
+{
+        cpu = cpu_logical_map(cpu);
+        writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
+}
+
 void imx_src_prepare_restart(void)
 {
         u32 val;
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7b6a64bc5f40..7509a89af967 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -2,23 +2,41 @@ if ARCH_KIRKWOOD
 
 menu "Marvell Kirkwood Implementations"
 
+config MACH_D2NET_V2
+        bool "LaCie d2 Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie d2 Network v2 NAS.
+
 config MACH_DB88F6281_BP
         bool "Marvell DB-88F6281-BP Development Board"
         help
           Say 'Y' here if you want your kernel to support the
           Marvell DB-88F6281-BP Development Board.
 
-config MACH_RD88F6192_NAS
-        bool "Marvell RD-88F6192-NAS Reference Board"
+config MACH_DOCKSTAR
+        bool "Seagate FreeAgent DockStar"
         help
           Say 'Y' here if you want your kernel to support the
-          Marvell RD-88F6192-NAS Reference Board.
+          Seagate FreeAgent DockStar.
 
-config MACH_RD88F6281
-        bool "Marvell RD-88F6281 Reference Board"
+config MACH_ESATA_SHEEVAPLUG
+        bool "Marvell eSATA SheevaPlug Reference Board"
         help
           Say 'Y' here if you want your kernel to support the
-          Marvell RD-88F6281 Reference Board.
+          Marvell eSATA SheevaPlug Reference Board.
+
+config MACH_GURUPLUG
+        bool "Marvell GuruPlug Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell GuruPlug Reference Board.
+
+config MACH_INETSPACE_V2
+        bool "LaCie Internet Space v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Internet Space v2 NAS.
 
 config MACH_MV88F6281GTW_GE
         bool "Marvell 88F6281 GTW GE Board"
@@ -26,23 +44,93 @@ config MACH_MV88F6281GTW_GE
           Say 'Y' here if you want your kernel to support the
           Marvell 88F6281 GTW GE Board.
 
+config MACH_NET2BIG_V2
+        bool "LaCie 2Big Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie 2Big Network v2 NAS.
+
+config MACH_NET5BIG_V2
+        bool "LaCie 5Big Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie 5Big Network v2 NAS.
+
+config MACH_NETSPACE_MAX_V2
+        bool "LaCie Network Space Max v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Network Space Max v2 NAS.
+
+config MACH_NETSPACE_V2
+        bool "LaCie Network Space v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Network Space v2 NAS.
+
+config MACH_OPENRD
+        bool
+
+config MACH_OPENRD_BASE
+        bool "Marvell OpenRD Base Board"
+        select MACH_OPENRD
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Base Board.
+
+config MACH_OPENRD_CLIENT
+        bool "Marvell OpenRD Client Board"
+        select MACH_OPENRD
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Client Board.
+
+config MACH_OPENRD_ULTIMATE
+        bool "Marvell OpenRD Ultimate Board"
+        select MACH_OPENRD
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Ultimate Board.
+
+config MACH_RD88F6192_NAS
+        bool "Marvell RD-88F6192-NAS Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell RD-88F6192-NAS Reference Board.
+
+config MACH_RD88F6281
+        bool "Marvell RD-88F6281 Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell RD-88F6281 Reference Board.
+
 config MACH_SHEEVAPLUG
         bool "Marvell SheevaPlug Reference Board"
         help
           Say 'Y' here if you want your kernel to support the
           Marvell SheevaPlug Reference Board.
 
-config MACH_ESATA_SHEEVAPLUG
-        bool "Marvell eSATA SheevaPlug Reference Board"
+config MACH_T5325
+        bool "HP t5325 Thin Client"
         help
           Say 'Y' here if you want your kernel to support the
-          Marvell eSATA SheevaPlug Reference Board.
+          HP t5325 Thin Client.
 
-config MACH_GURUPLUG
-        bool "Marvell GuruPlug Reference Board"
+config MACH_TS219
+        bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
         help
           Say 'Y' here if you want your kernel to support the
-          Marvell GuruPlug Reference Board.
+          QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
+          TS-219P+ Turbo NAS devices.
+
+config MACH_TS41X
+        bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
+        help
+          Say 'Y' here if you want your kernel to support the
+          QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
+          NAS devices.
+
+comment "Device tree entries"
 
 config ARCH_KIRKWOOD_DT
         bool "Marvell Kirkwood Flattened Device Tree"
@@ -58,12 +146,27 @@ config ARCH_KIRKWOOD_DT
           Say 'Y' here if you want your kernel to support the
           Marvell Kirkwood using flattened device tree.
 
-config MACH_GURUPLUG_DT
-        bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
+config MACH_CLOUDBOX_DT
+        bool "LaCie CloudBox NAS (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the LaCie
+          CloudBox NAS, using Flattened Device Tree.
+
+config MACH_DLINK_KIRKWOOD_DT
+        bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the
-          Marvell GuruPlug Reference Board (Flattened Device Tree).
+          Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
+          using Flattened Device Tree.
+
+config MACH_DOCKSTAR_DT
+        bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Seagate FreeAgent Dockstar (Flattened Device Tree).
 
 config MACH_DREAMPLUG_DT
         bool "Marvell DreamPlug (Flattened Device Tree)"
@@ -72,19 +175,19 @@ config MACH_DREAMPLUG_DT
           Say 'Y' here if you want your kernel to support the
           Marvell DreamPlug (Flattened Device Tree).
 
-config MACH_ICONNECT_DT
-        bool "Iomega Iconnect (Flattened Device Tree)"
+config MACH_GOFLEXNET_DT
+        bool "Seagate GoFlex Net (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
-          Say 'Y' here to enable Iomega Iconnect support.
+          Say 'Y' here if you want your kernel to support the
+          Seagate GoFlex Net (Flattened Device Tree).
 
-config MACH_DLINK_KIRKWOOD_DT
-        bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
+config MACH_GURUPLUG_DT
+        bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the
-          Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
-          using Flattened Device Tree.
+          Marvell GuruPlug Reference Board (Flattened Device Tree).
 
 config MACH_IB62X0_DT
         bool "RaidSonic IB-NAS6210, IB-NAS6220 (Flattened Device Tree)"
@@ -94,41 +197,18 @@ config MACH_IB62X0_DT
           RaidSonic IB-NAS6210 & IB-NAS6220 devices, using
           Flattened Device Tree.
 
-config MACH_TS219_DT
-        bool "Device Tree for QNAP TS-11X, TS-21X NAS"
-        select ARCH_KIRKWOOD_DT
-        select ARM_APPENDED_DTB
-        select ARM_ATAG_DTB_COMPAT
-        help
-          Say 'Y' here if you want your kernel to support the QNAP
-          TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
-          TS-219P+ Turbo NAS devices using Fattened Device Tree.
-          There are two different Device Tree descriptions, depending
-          on if the device is based on an if the board uses the MV6281
-          or MV6282. If you have the wrong one, the buttons will not
-          work.
-
-config MACH_DOCKSTAR_DT
-        bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
-        select ARCH_KIRKWOOD_DT
-        help
-          Say 'Y' here if you want your kernel to support the
-          Seagate FreeAgent Dockstar (Flattened Device Tree).
-
-config MACH_GOFLEXNET_DT
-        bool "Seagate GoFlex Net (Flattened Device Tree)"
+config MACH_ICONNECT_DT
+        bool "Iomega Iconnect (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
-          Say 'Y' here if you want your kernel to support the
-          Seagate GoFlex Net (Flattened Device Tree).
+          Say 'Y' here to enable Iomega Iconnect support.
 
-config MACH_LSXL_DT
-        bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
+config MACH_INETSPACE_V2_DT
+        bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
-          Say 'Y' here if you want your kernel to support the
-          Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
-          Flattened Device Tree.
+          Say 'Y' here if you want your kernel to support the LaCie
+          Internet Space v2 NAS, using Flattened Device Tree.
 
 config MACH_IOMEGA_IX2_200_DT
         bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
@@ -144,12 +224,13 @@ config MACH_KM_KIRKWOOD_DT
           Say 'Y' here if you want your kernel to support the
           Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
 
-config MACH_INETSPACE_V2_DT
-        bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
+config MACH_LSXL_DT
+        bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
-          Say 'Y' here if you want your kernel to support the LaCie
-          Internet Space v2 NAS, using Flattened Device Tree.
+          Say 'Y' here if you want your kernel to support the
+          Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
+          Flattened Device Tree.
 
 config MACH_MPLCEC4_DT
         bool "MPL CEC4 (Flattened Device Tree)"
@@ -158,12 +239,12 @@ config MACH_MPLCEC4_DT
           Say 'Y' here if you want your kernel to support the
           MPL CEC4 (Flattened Device Tree).
 
-config MACH_NETSPACE_V2_DT
-        bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
+config MACH_NETSPACE_LITE_V2_DT
+        bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the LaCie
-          Network Space v2 NAS, using Flattened Device Tree.
+          Network Space Lite v2 NAS, using Flattened Device Tree.
 
 config MACH_NETSPACE_MAX_V2_DT
         bool "LaCie Network Space Max v2 NAS (Flattened Device Tree)"
@@ -172,128 +253,69 @@ config MACH_NETSPACE_MAX_V2_DT
           Say 'Y' here if you want your kernel to support the LaCie
           Network Space Max v2 NAS, using Flattened Device Tree.
 
-config MACH_NETSPACE_LITE_V2_DT
-        bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
-        select ARCH_KIRKWOOD_DT
-        help
-          Say 'Y' here if you want your kernel to support the LaCie
-          Network Space Lite v2 NAS, using Flattened Device Tree.
-
 config MACH_NETSPACE_MINI_V2_DT
         bool "LaCie Network Space Mini v2 NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the LaCie
-          Network Space Mini v2 NAS (aka SafeBox), using Flattened
-          Device Tree.
+          Network Space Mini v2 NAS using Flattened Device Tree.
 
-config MACH_OPENBLOCKS_A6_DT
-        bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
-        select ARCH_KIRKWOOD_DT
-        help
-          Say 'Y' here if you want your kernel to support the
-          Plat'Home OpenBlocks A6 (Flattened Device Tree).
+          This board is embedded in a product named CloudBox, which
+          provides automatic backup on a 100GB cloud storage. This
+          should not confused with a more recent LaCie NAS also named
+          CloudBox. For this last, the disk capacity is 1TB or above.
 
-config MACH_TOPKICK_DT
-        bool "USI Topkick (Flattened Device Tree)"
+config MACH_NETSPACE_V2_DT
+        bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
-          Say 'Y' here if you want your kernel to support the
-          USI Topkick, using Flattened Device Tree
-
-config MACH_TS219
-        bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
-        help
-          Say 'Y' here if you want your kernel to support the
-          QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
-          TS-219P+ Turbo NAS devices.
-
-config MACH_TS41X
-        bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
-        help
-          Say 'Y' here if you want your kernel to support the
-          QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
-          NAS devices.
-
-config MACH_DOCKSTAR
-        bool "Seagate FreeAgent DockStar"
-        help
-          Say 'Y' here if you want your kernel to support the
-          Seagate FreeAgent DockStar.
-
-config MACH_OPENRD
-        bool
-
-config MACH_OPENRD_BASE
-        bool "Marvell OpenRD Base Board"
-        select MACH_OPENRD
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell OpenRD Base Board.
-
-config MACH_OPENRD_CLIENT
-        bool "Marvell OpenRD Client Board"
-        select MACH_OPENRD
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell OpenRD Client Board.
-
-config MACH_OPENRD_ULTIMATE
-        bool "Marvell OpenRD Ultimate Board"
-        select MACH_OPENRD
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell OpenRD Ultimate Board.
-
-config MACH_NETSPACE_V2
-        bool "LaCie Network Space v2 NAS Board"
-        help
-          Say 'Y' here if you want your kernel to support the
-          LaCie Network Space v2 NAS.
-
-config MACH_INETSPACE_V2
-        bool "LaCie Internet Space v2 NAS Board"
-        help
-          Say 'Y' here if you want your kernel to support the
-          LaCie Internet Space v2 NAS.
-
-config MACH_NETSPACE_MAX_V2
-        bool "LaCie Network Space Max v2 NAS Board"
-        help
-          Say 'Y' here if you want your kernel to support the
-          LaCie Network Space Max v2 NAS.
+          Say 'Y' here if you want your kernel to support the LaCie
+          Network Space v2 NAS, using Flattened Device Tree.
 
-config MACH_D2NET_V2
-        bool "LaCie d2 Network v2 NAS Board"
+config MACH_NSA310_DT
+        bool "ZyXEL NSA-310 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        select ARM_ATAG_DTB_COMPAT
         help
           Say 'Y' here if you want your kernel to support the
-          LaCie d2 Network v2 NAS.
+          ZyXEL NSA-310 board (Flattened Device Tree).
 
-config MACH_NET2BIG_V2
-        bool "LaCie 2Big Network v2 NAS Board"
+config MACH_OPENBLOCKS_A6_DT
+        bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the
-          LaCie 2Big Network v2 NAS.
+          Plat'Home OpenBlocks A6 (Flattened Device Tree).
 
-config MACH_NET5BIG_V2
-        bool "LaCie 5Big Network v2 NAS Board"
+config MACH_READYNAS_DT
+        bool "NETGEAR ReadyNAS Duo v2 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        select ARM_APPENDED_DTB
+        select ARM_ATAG_DTB_COMPAT
         help
           Say 'Y' here if you want your kernel to support the
-          LaCie 5Big Network v2 NAS.
+          NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
 
-config MACH_T5325
-        bool "HP t5325 Thin Client"
+config MACH_TOPKICK_DT
+        bool "USI Topkick (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the
-          HP t5325 Thin Client.
+          USI Topkick, using Flattened Device Tree
 
-config MACH_NSA310_DT
-        bool "ZyXEL NSA-310 (Flattened Device Tree)"
+config MACH_TS219_DT
+        bool "Device Tree for QNAP TS-11X, TS-21X NAS"
         select ARCH_KIRKWOOD_DT
+        select ARM_APPENDED_DTB
         select ARM_ATAG_DTB_COMPAT
         help
-          Say 'Y' here if you want your kernel to support the
-          ZyXEL NSA-310 board (Flattened Device Tree).
+          Say 'Y' here if you want your kernel to support the QNAP
+          TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
+          TS-219P+ Turbo NAS devices using Fattened Device Tree.
+          There are two different Device Tree descriptions, depending
+          on if the device is based on an if the board uses the MV6281
+          or MV6282. If you have the wrong one, the buttons will not
+          work.
 
 endmenu
 
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 4cc4bee4d0cf..cdbca328a412 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,42 +1,44 @@
 obj-y                           += common.o addr-map.o irq.o pcie.o mpp.o
 
+obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_DB88F6281_BP)         += db88f6281-bp-setup.o
-obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6192-nas-setup.o
-obj-$(CONFIG_MACH_RD88F6281)            += rd88f6281-setup.o
-obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
-obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
+obj-$(CONFIG_MACH_DOCKSTAR)             += dockstar-setup.o
 obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG)     += sheevaplug-setup.o
 obj-$(CONFIG_MACH_GURUPLUG)             += guruplug-setup.o
-obj-$(CONFIG_MACH_DOCKSTAR)             += dockstar-setup.o
-obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
-obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
-obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
-obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
+obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6192-nas-setup.o
+obj-$(CONFIG_MACH_RD88F6281)            += rd88f6281-setup.o
+obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
 obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
+obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
+obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
-obj-$(CONFIG_MACH_DREAMPLUG_DT)         += board-dreamplug.o
-obj-$(CONFIG_MACH_GURUPLUG_DT)          += board-guruplug.o
-obj-$(CONFIG_MACH_ICONNECT_DT)          += board-iconnect.o
+obj-$(CONFIG_MACH_CLOUDBOX_DT)          += board-ns2.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
-obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
-obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
 obj-$(CONFIG_MACH_DOCKSTAR_DT)          += board-dockstar.o
+obj-$(CONFIG_MACH_DREAMPLUG_DT)         += board-dreamplug.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)         += board-goflexnet.o
-obj-$(CONFIG_MACH_LSXL_DT)              += board-lsxl.o
+obj-$(CONFIG_MACH_GURUPLUG_DT)          += board-guruplug.o
+obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
+obj-$(CONFIG_MACH_ICONNECT_DT)          += board-iconnect.o
+obj-$(CONFIG_MACH_INETSPACE_V2_DT)      += board-ns2.o
 obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)    += board-iomega_ix2_200.o
 obj-$(CONFIG_MACH_KM_KIRKWOOD_DT)       += board-km_kirkwood.o
-obj-$(CONFIG_MACH_INETSPACE_V2_DT)      += board-ns2.o
+obj-$(CONFIG_MACH_LSXL_DT)              += board-lsxl.o
 obj-$(CONFIG_MACH_MPLCEC4_DT)           += board-mplcec4.o
-obj-$(CONFIG_MACH_NETSPACE_V2_DT)       += board-ns2.o
-obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)   += board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT)  += board-ns2.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)   += board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT)  += board-ns2.o
+obj-$(CONFIG_MACH_NETSPACE_V2_DT)       += board-ns2.o
 obj-$(CONFIG_MACH_NSA310_DT)            += board-nsa310.o
 obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)     += board-openblocks_a6.o
+obj-$(CONFIG_MACH_READYNAS_DT)          += board-readynas.o
 obj-$(CONFIG_MACH_TOPKICK_DT)           += board-usi_topkick.o
+obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index d367aa6b47bb..7904758e771f 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -139,16 +139,20 @@ static void __init kirkwood_dt_init(void)
         if (of_machine_is_compatible("keymile,km_kirkwood"))
                 km_kirkwood_init();
 
-        if (of_machine_is_compatible("lacie,inetspace_v2") ||
-            of_machine_is_compatible("lacie,netspace_v2") ||
-            of_machine_is_compatible("lacie,netspace_max_v2") ||
+        if (of_machine_is_compatible("lacie,cloudbox") ||
+            of_machine_is_compatible("lacie,inetspace_v2") ||
             of_machine_is_compatible("lacie,netspace_lite_v2") ||
-            of_machine_is_compatible("lacie,netspace_mini_v2"))
+            of_machine_is_compatible("lacie,netspace_max_v2") ||
+            of_machine_is_compatible("lacie,netspace_mini_v2") ||
+            of_machine_is_compatible("lacie,netspace_v2"))
                 ns2_init();
 
         if (of_machine_is_compatible("mpl,cec4"))
                 mplcec4_init();
 
+        if (of_machine_is_compatible("netgear,readynas-duo-v2"))
+                netgear_readynas_init();
+
         if (of_machine_is_compatible("plathome,openblocks-a6"))
                 openblocks_a6_init();
 
@@ -171,12 +175,14 @@ static const char * const kirkwood_dt_board_compat[] = {
         "buffalo,lsxl",
         "iom,ix2-200",
         "keymile,km_kirkwood",
+        "lacie,cloudbox",
         "lacie,inetspace_v2",
-        "lacie,netspace_max_v2",
-        "lacie,netspace_v2",
         "lacie,netspace_lite_v2",
+        "lacie,netspace_max_v2",
         "lacie,netspace_mini_v2",
+        "lacie,netspace_v2",
         "mpl,cec4",
+        "netgear,readynas-duo-v2",
         "plathome,openblocks-a6",
         "usi,topkick",
         "zyxel,nsa310",
diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c
index f2ea3b7ad726..f8f660525ace 100644
--- a/arch/arm/mach-kirkwood/board-ns2.c
+++ b/arch/arm/mach-kirkwood/board-ns2.c
@@ -27,7 +27,8 @@ void __init ns2_init(void)
         /*
          * Basic setup. Needs to be called early.
          */
-        if (of_machine_is_compatible("lacie,netspace_lite_v2") ||
+        if (of_machine_is_compatible("lacie,cloudbox") ||
+            of_machine_is_compatible("lacie,netspace_lite_v2") ||
             of_machine_is_compatible("lacie,netspace_mini_v2"))
                 ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
         kirkwood_ge00_init(&ns2_ge00_data);
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
new file mode 100644
index 000000000000..fb42c20e273f
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-readynas.c
@@ -0,0 +1,28 @@
+/*
+ * NETGEAR ReadyNAS Duo v2 Board setup for drivers not already
+ * converted to DT.
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mv643xx_eth.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+void __init netgear_readynas_init(void)
+{
+        kirkwood_ge00_init(&netgear_readynas_ge00_data);
+        kirkwood_pcie_init(KW_PCIE0);
+}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 5ed70565c843..3147be2f34da 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -141,12 +141,24 @@ void openblocks_a6_init(void);
 static inline void openblocks_a6_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_READYNAS_DT
+void netgear_readynas_init(void);
+#else
+static inline void netgear_readynas_init(void) {};
+#endif
+
 #ifdef CONFIG_MACH_TOPKICK_DT
 void usi_topkick_init(void);
 #else
 static inline void usi_topkick_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_CLOUDBOX_DT
+void cloudbox_init(void);
+#else
+static inline void cloudbox_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 1c6e736cbbf8..08dd739aa709 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = {
 
 static struct mvsdio_platform_data guruplug_mvsdio_data = {
         /* unfortunately the CD signal has not been connected */
+        .gpio_card_detect = -1,
+        .gpio_write_protect = -1,
 };
 
 static struct gpio_led guruplug_led_pins[] = {
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 8ddd69fdc937..6a6eb548307d 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = {
 
 static struct mvsdio_platform_data openrd_mvsdio_data = {
         .gpio_card_detect = 29, /* MPP29 used as SD card detect */
+        .gpio_write_protect = -1,
 };
 
 static unsigned int openrd_mpp_config[] __initdata = {
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index c7d93b48926b..d24223166e06 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = {
 
 static struct mvsdio_platform_data rd88f6281_mvsdio_data = {
         .gpio_card_detect = 28,
+        .gpio_write_protect = -1,
 };
 
 static unsigned int rd88f6281_mpp_config[] __initdata = {
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 9f64d5632e07..fa21aac52467 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -9,6 +9,7 @@
  *  publishhed by the Free Software Foundation.
  */
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
@@ -110,6 +111,10 @@ static unsigned long common_pin_config[] __initdata = {
         GPIO121_KP_MKIN4,
 };
 
+static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct smc91x_platdata smc91x_info = {
         .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
 };
@@ -248,6 +253,8 @@ static void __init common_init(void)
         pxa168_add_nand(&aspenite_nand_info);
         pxa168_add_fb(&aspenite_lcd_info);
         pxa168_add_keypad(&aspenite_keypad_info);
+        platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&pxa168_device_gpio);
 
         /* off-chip devices */
diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c
index 1f94957b56ae..a451a0f4d512 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -12,6 +12,7 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/gpio-pxa.h>
 #include <linux/platform_device.h>
 
 #include <asm/mach-types.h>
@@ -32,12 +33,18 @@ static unsigned long avengers_lite_pin_config_V16F[] __initdata = {
         GPIO89_UART2_RXD,
 };
 
+static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static void __init avengers_lite_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(avengers_lite_pin_config_V16F));
 
         /* on-chip devices */
         pxa168_add_uart(2);
+        platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&pxa168_device_gpio);
 }
 
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index 2358011c7d8e..ac25544b8cdb 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/gpio-pxa.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/max8649.h>
 #include <linux/regulator/fixed.h>
@@ -104,6 +105,10 @@ static unsigned long brownstone_pin_config[] __initdata = {
         GPIO89_GPIO,
 };
 
+static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct regulator_consumer_supply max8649_supply[] = {
         REGULATOR_SUPPLY("vcc_core", NULL),
 };
@@ -202,6 +207,8 @@ static void __init brownstone_init(void)
         /* on-chip devices */
         mmp2_add_uart(1);
         mmp2_add_uart(3);
+        platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&mmp2_device_gpio);
         mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
         mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c
index 21d22002cd19..53d77cbd6000 100644
--- a/arch/arm/mach-mmp/clock-mmp2.c
+++ b/arch/arm/mach-mmp/clock-mmp2.c
@@ -98,7 +98,7 @@ static struct clk_lookup mmp2_clkregs[] = {
         INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
         INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_gpio, "mmp2-gpio", NULL),
         INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
         INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
         INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
index 5e6c18ccebd4..c572f219ae26 100644
--- a/arch/arm/mach-mmp/clock-pxa168.c
+++ b/arch/arm/mach-mmp/clock-pxa168.c
@@ -78,7 +78,7 @@ static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
         INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL),
         INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
         INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
         INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c
index 933ea71d0b56..379e1df61c70 100644
--- a/arch/arm/mach-mmp/clock-pxa910.c
+++ b/arch/arm/mach-mmp/clock-pxa910.c
@@ -56,7 +56,7 @@ static struct clk_lookup pxa910_clkregs[] = {
         INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
         INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL),
         INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
         INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index 754c352dd02b..6291c33d83e2 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -16,6 +16,7 @@
 #include <linux/smc91x.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
@@ -77,6 +78,10 @@ static unsigned long flint_pin_config[] __initdata = {
         GPIO160_ND_RDY1,
 };
 
+static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct smc91x_platdata flint_smc91x_info = {
         .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
 };
@@ -111,6 +116,8 @@ static void __init flint_init(void)
         /* on-chip devices */
         mmp2_add_uart(1);
         mmp2_add_uart(2);
+        platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&mmp2_device_gpio);
 
         /* off-chip devices */
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index f62b68d926f4..d81b2475e67e 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -128,6 +129,10 @@ static unsigned long gplugd_pin_config[] __initdata = {
         GPIO116_I2S_TXD
 };
 
+static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct i2c_board_info gplugd_i2c_board_info[] = {
         {
                 .type = "isl1208",
@@ -186,6 +191,8 @@ static void __init gplugd_init(void)
         pxa168_add_uart(3);
         pxa168_add_ssp(1);
         pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
+        platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&pxa168_device_gpio);
 
         pxa168_add_eth(&gplugd_eth_platform_data);
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
deleted file mode 100644
index 5c3cc29688ab..000000000000
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ /dev/null
@@ -1,30 +0,0 @@
-/* arch/arm/mach-mmp/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copied from arch/arm/mach-pxa/include/mach/debug.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#if defined(CONFIG_DEBUG_MMP_UART2)
-#define MMP_UART_OFFSET 0x00017000
-#elif defined(CONFIG_DEBUG_MMP_UART3)
-#define MMP_UART_OFFSET 0x00018000
-#else
-#error "Select uart for DEBUG_LL"
-#endif
-
-#include <mach/addr-map.h>
-
-                .macro  addruart, rp, rv, tmp
-                ldr     \rp, =APB_PHYS_BASE             @ physical
-                ldr     \rv, =APB_VIRT_BASE             @ virtual
-                orr     \rp, \rp, #MMP_UART_OFFSET
-                orr     \rv, \rv, #MMP_UART_OFFSET
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 66634fd0ecb0..0e9e5c05b37c 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -12,6 +12,7 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/gpio-pxa.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/regulator/machine.h>
@@ -99,6 +100,10 @@ static unsigned long jasper_pin_config[] __initdata = {
         GPIO151_MMC3_CLK,
 };
 
+static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct regulator_consumer_supply max8649_supply[] = {
         REGULATOR_SUPPLY("vcc_core", NULL),
 };
@@ -165,6 +170,9 @@ static void __init jasper_init(void)
         mmp2_add_uart(1);
         mmp2_add_uart(3);
         mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
+        platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
+        platform_device_register(&mmp2_device_gpio);
         mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
 
         regulator_has_full_constraints();
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index d063efa0a4f1..b37915dc4470 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -28,7 +28,7 @@ static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
         {}
 };
@@ -39,7 +39,7 @@ static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
         {}
 };
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index fad431aa6e09..4ac256720f7d 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -31,7 +31,7 @@ static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp2-gpio", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
         {}
 };
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index d94d114eef7b..c7592f168bbd 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -164,7 +164,7 @@ struct resource mmp2_resource_gpio[] = {
 };
 
 struct platform_device mmp2_device_gpio = {
-        .name           = "pxa-gpio",
+        .name           = "mmp2-gpio",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(mmp2_resource_gpio),
         .resource       = mmp2_resource_gpio,
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 9bc7b86a86a7..a30dcf3b7d9e 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -125,7 +125,7 @@ struct resource pxa168_resource_gpio[] = {
 };
 
 struct platform_device pxa168_device_gpio = {
-        .name           = "pxa-gpio",
+        .name           = "mmp-gpio",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(pxa168_resource_gpio),
         .resource       = pxa168_resource_gpio,
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 36cb321a3d70..ce6393acad86 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -152,7 +152,7 @@ struct resource pxa910_resource_gpio[] = {
 };
 
 struct platform_device pxa910_device_gpio = {
-        .name           = "pxa-gpio",
+        .name           = "mmp-gpio",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(pxa910_resource_gpio),
         .resource       = pxa910_resource_gpio,
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index 4c127d23955d..cdfc9bfee1a4 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -8,6 +8,7 @@
  *  publishhed by the Free Software Foundation.
  */
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
@@ -60,6 +61,10 @@ static unsigned long tavorevb_pin_config[] __initdata = {
         DF_RDY0_DF_RDY0,
 };
 
+static struct pxa_gpio_platform_data pxa910_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct smc91x_platdata tavorevb_smc91x_info = {
         .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
 };
@@ -93,6 +98,8 @@ static void __init tavorevb_init(void)
 
         /* on-chip devices */
         pxa910_add_uart(1);
+        platform_device_add_data(&pxa910_device_gpio, &pxa910_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&pxa910_device_gpio);
 
         /* off-chip devices */
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index 8609967975ed..e4d95b4c6bb2 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -16,6 +16,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/input.h>
 #include <linux/platform_data/keypad-pxa27x.h>
 #include <linux/i2c.h>
@@ -49,6 +50,10 @@ static unsigned long teton_bga_pin_config[] __initdata = {
         GPIO78_GPIO,
 };
 
+static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static unsigned int teton_bga_matrix_key_map[] = {
         KEY(0, 6, KEY_ESC),
         KEY(0, 7, KEY_ENTER),
@@ -79,6 +84,8 @@ static void __init teton_bga_init(void)
         pxa168_add_uart(1);
         pxa168_add_keypad(&teton_bga_keypad_info);
         pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
+        platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&pxa168_device_gpio);
 }
 
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 22a9058f9f4d..6aa788872921 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -17,6 +17,7 @@
 #include <linux/interrupt.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/mfd/88pm860x.h>
 #include <linux/platform_data/mv_usb.h>
 #include <linux/spi/spi.h>
@@ -75,6 +76,10 @@ static unsigned long ttc_dkb_pin_config[] __initdata = {
         DF_RDY0_DF_RDY0,
 };
 
+static struct pxa_gpio_platform_data pxa910_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct mtd_partition ttc_dkb_onenand_partitions[] = {
         {
                 .name           = "bootloader",
@@ -284,6 +289,8 @@ static void __init ttc_dkb_init(void)
 
         /* off-chip devices */
         pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
+        platform_device_add_data(&pxa910_device_gpio, &pxa910_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
 
 #ifdef CONFIG_USB_MV_UDC
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 2969027f02fa..f9fd77e8f1f5 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -62,7 +62,10 @@ static int msm_timer_set_next_event(unsigned long cycles,
 {
         u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
 
-        writel_relaxed(0, event_base + TIMER_CLEAR);
+        ctrl &= ~TIMER_ENABLE_EN;
+        writel_relaxed(ctrl, event_base + TIMER_ENABLE);
+
+        writel_relaxed(ctrl, event_base + TIMER_CLEAR);
         writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
         writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
         return 0;
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 274ff58271de..6a9195e10579 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -44,6 +44,8 @@
 
 #define ARMADA_370_XP_MAX_PER_CPU_IRQS          (28)
 
+#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ        (5)
+
 #define ACTIVE_DOORBELLS                        (8)
 
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
@@ -62,7 +64,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
 #ifdef CONFIG_SMP
         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
-        if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
+        if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
                 writel(hwirq, main_int_base +
                                 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
         else
@@ -79,7 +81,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
 #ifdef CONFIG_SMP
         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 
-        if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
+        if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
                 writel(hwirq, main_int_base +
                                 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
         else
@@ -147,7 +149,7 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
         writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
         irq_set_status_flags(virq, IRQ_LEVEL);
 
-        if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) {
+        if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
                 irq_set_percpu_devid(virq);
                 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
                                         handle_percpu_devid_irq);
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index cb7c6ae2e3fc..6c4f766365a2 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -543,15 +543,6 @@ static struct clk usb_dc_ck = {
         /* Direct from ULPD, no parent */
         .rate           = 48000000,
         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-        .enable_bit     = USB_REQ_EN_SHIFT,
-};
-
-static struct clk usb_dc_ck7xx = {
-        .name           = "usb_dc_ck",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 48000000,
-        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
         .enable_bit     = SOFT_USB_OTG_DPLL_REQ_SHIFT,
 };
 
@@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = {
         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
-        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
-        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
+        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX | CK_7XX),
         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h
index 753cd5ce6949..45e5ac707cbb 100644
--- a/arch/arm/mach-omap1/include/mach/usb.h
+++ b/arch/arm/mach-omap1/include/mach/usb.h
@@ -2,7 +2,7 @@
  * FIXME correct answer depends on hmc_mode,
  * as does (on omap1) any nonzero value for config->otg port number
  */
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
 #define is_usb0_device(config)  1
 #else
 #define is_usb0_device(config)  0
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index 1a1db5971cd9..4118db50d5e8 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -123,7 +123,7 @@ omap_otg_init(struct omap_usb_config *config)
         syscon = omap_readl(OTG_SYSCON_1);
         syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
 
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
         if (config->otg || config->register_dev) {
                 struct platform_device *udc_device = config->udc_device;
                 int status;
@@ -169,7 +169,7 @@ omap_otg_init(struct omap_usb_config *config)
 void omap_otg_init(struct omap_usb_config *config) {}
 #endif
 
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
 
 static struct resource udc_resources[] = {
         /* order is significant! */
@@ -600,7 +600,7 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
         while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
                 cpu_relax();
 
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
         if (config->register_dev) {
                 int status;
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b068b7fe99ef..62bb352c2d37 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -229,7 +229,6 @@ obj-$(CONFIG_MACH_DEVKIT8000)     	+= board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
 obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
 obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
-obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
 obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o
@@ -255,8 +254,6 @@ obj-$(CONFIG_MACH_TOUCHBOOK)		+= board-omap3touchbook.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
 obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o
 
-obj-$(CONFIG_MACH_PCM049)               += board-omap4pcm049.o
-
 obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o
 
 obj-$(CONFIG_MACH_CRANEBOARD)           += board-am3517crane.o
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 35f3ad0cb7c7..00d72902ef4f 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -291,6 +291,10 @@ static struct platform_device sdp4430_leds_pwm = {
         },
 };
 
+/* Dummy regulator for pwm-backlight driver */
+static struct regulator_consumer_supply backlight_supply =
+        REGULATOR_SUPPLY("enable", "pwm-backlight");
+
 static struct platform_pwm_backlight_data sdp4430_backlight_data = {
         .max_brightness = 127,
         .dft_brightness = 127,
@@ -718,6 +722,8 @@ static void __init omap_4430sdp_init(void)
 
         omap4_i2c_init();
         omap_sfh7741prox_init();
+        regulator_register_always_on(0, "backlight-enable",
+                                     &backlight_supply, 1, 0);
         platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 3a077df6b8df..1a884670a6c4 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -547,12 +547,16 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
         REGULATOR_SUPPLY("DVDD", "2-0019"),
         /* Si4713 IO supply */
         REGULATOR_SUPPLY("vio", "2-0063"),
+        /* lis3lv02d */
+        REGULATOR_SUPPLY("Vdd_IO", "3-001d"),
 };
 
 static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
         REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
         /* Si4713 supply */
         REGULATOR_SUPPLY("vdd", "2-0063"),
+        /* lis3lv02d */
+        REGULATOR_SUPPLY("Vdd", "3-001d"),
 };
 
 static struct regulator_init_data rx51_vaux1 = {
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 8cef477d6b00..9a7174faac51 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -12,7 +12,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/i2c/twl.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
@@ -49,59 +48,6 @@ static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
 }
 
-/* Register offsets in TWL4030_MODULE_INTBR */
-#define TWL_INTBR_PMBR1 0xD
-#define TWL_INTBR_GPBR1 0xC
-
-/* Register offsets in TWL_MODULE_PWM */
-#define TWL_LED_PWMON   0x3
-#define TWL_LED_PWMOFF  0x4
-
-static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
-{
-#ifdef CONFIG_TWL4030_CORE
-        unsigned char c;
-        u8 mux_pwm, enb_pwm;
-
-        if (level > 100)
-                return -1;
-
-        twl_i2c_read_u8(TWL4030_MODULE_INTBR, &mux_pwm, TWL_INTBR_PMBR1);
-        twl_i2c_read_u8(TWL4030_MODULE_INTBR, &enb_pwm, TWL_INTBR_GPBR1);
-
-        if (level == 0) {
-                /* disable pwm1 output and clock */
-                enb_pwm = enb_pwm & 0xF5;
-                /* change pwm1 pin to gpio pin */
-                mux_pwm = mux_pwm & 0xCF;
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        enb_pwm, TWL_INTBR_GPBR1);
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        mux_pwm, TWL_INTBR_PMBR1);
-                return 0;
-        }
-
-        if (!((enb_pwm & 0xA) && (mux_pwm & 0x30))) {
-                /* change gpio pin to pwm1 pin */
-                mux_pwm = mux_pwm | 0x30;
-                /* enable pwm1 output and clock*/
-                enb_pwm = enb_pwm | 0x0A;
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        mux_pwm, TWL_INTBR_PMBR1);
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        enb_pwm, TWL_INTBR_GPBR1);
-        }
-
-        c = ((50 * (100 - level)) / 100) + 1;
-        twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, TWL_LED_PWMOFF);
-        twl_i2c_write_u8(TWL_MODULE_PWM, c, TWL_LED_PWMON);
-#else
-        pr_warn("Backlight not enabled\n");
-#endif
-
-        return 0;
-}
-
 static struct omap_dss_device zoom_lcd_device = {
         .name                   = "lcd",
         .driver_name            = "NEC_8048_panel",
@@ -109,8 +55,6 @@ static struct omap_dss_device zoom_lcd_device = {
         .phy.dpi.data_lines     = 24,
         .platform_enable        = zoom_panel_enable_lcd,
         .platform_disable       = zoom_panel_disable_lcd,
-        .max_backlight_level    = 100,
-        .set_backlight          = zoom_set_bl_intensity,
 };
 
 static struct omap_dss_device *zoom_dss_devices[] = {
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index cdc0c1021863..a90375d5b2b6 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -22,6 +22,9 @@
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/omap-twl4030.h>
 #include <linux/usb/phy.h>
+#include <linux/pwm.h>
+#include <linux/leds_pwm.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -193,6 +196,53 @@ static struct platform_device omap_vwlan_device = {
         },
 };
 
+static struct pwm_lookup zoom_pwm_lookup[] = {
+        PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "zoom::keypad"),
+        PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", "backlight"),
+};
+
+static struct led_pwm zoom_pwm_leds[] = {
+        {
+                .name           = "zoom::keypad",
+                .max_brightness = 127,
+                .pwm_period_ns  = 7812500,
+        },
+};
+
+static struct led_pwm_platform_data zoom_pwm_data = {
+        .num_leds       = ARRAY_SIZE(zoom_pwm_leds),
+        .leds           = zoom_pwm_leds,
+};
+
+static struct platform_device zoom_leds_pwm = {
+        .name   = "leds_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &zoom_pwm_data,
+        },
+};
+
+static struct platform_pwm_backlight_data zoom_backlight_data = {
+        .pwm_id = 1,
+        .max_brightness = 127,
+        .dft_brightness = 127,
+        .pwm_period_ns = 7812500,
+};
+
+static struct platform_device zoom_backlight_pwm = {
+        .name   = "pwm-backlight",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &zoom_backlight_data,
+        },
+};
+
+static struct platform_device *zoom_devices[] __initdata = {
+        &omap_vwlan_device,
+        &zoom_leds_pwm,
+        &zoom_backlight_pwm,
+};
+
 static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
         .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
 };
@@ -301,7 +351,8 @@ void __init zoom_peripherals_init(void)
 
         omap_hsmmc_init(mmc);
         omap_i2c_init();
-        platform_device_register(&omap_vwlan_device);
+        pwm_add_table(zoom_pwm_lookup, ARRAY_SIZE(zoom_pwm_lookup));
+        platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices));
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
         enable_board_wakeup_source();
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 3d58f335f173..0c6834ae1fc4 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -52,6 +52,13 @@
  */
 #define OMAP4_DPLL_ABE_DEFFREQ                          98304000
 
+/*
+ * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
+ * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
+ * locked frequency for the USB DPLL is 960MHz.
+ */
+#define OMAP4_DPLL_USB_DEFFREQ                          960000000
+
 /* Root clocks */
 
 DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
@@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
                     OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
                     hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
 
+DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
+                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+                OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
+
 DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
                 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1538,6 +1549,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "per_mcbsp4_gfclk",                     &per_mcbsp4_gfclk,      CK_443X),
         CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk,   CK_443X),
         CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk,   CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
@@ -1705,5 +1717,13 @@ int __init omap4xxx_clk_init(void)
         if (rc)
                 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
+        /*
+         * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+         * domain can transition to retention state when not in use.
+         */
+        rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
+        if (rc)
+                pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
         return 0;
 }
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 40f4a03d728f..d6ba13e1c540 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -293,5 +293,8 @@ extern void omap_reserve(void);
 struct omap_hwmod;
 extern int omap_dss_reset(struct omap_hwmod *);
 
+/* SoC specific clock initializer */
+extern int (*omap_clk_init)(void);
+
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2c3fdd65387b..5c445ca1e271 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,6 +55,12 @@
 #include "prm44xx.h"
 
 /*
+ * omap_clk_init: points to a function that does the SoC-specific
+ * clock initializations
+ */
+int (*omap_clk_init)(void);
+
+/*
  * The machine specific code may provide the extra mapping besides the
  * default mapping provided here.
  */
@@ -397,7 +403,7 @@ void __init omap2420_init_early(void)
         omap242x_clockdomains_init();
         omap2420_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap2420_clk_init();
+        omap_clk_init = omap2420_clk_init;
 }
 
 void __init omap2420_init_late(void)
@@ -427,7 +433,7 @@ void __init omap2430_init_early(void)
         omap243x_clockdomains_init();
         omap2430_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap2430_clk_init();
+        omap_clk_init = omap2430_clk_init;
 }
 
 void __init omap2430_init_late(void)
@@ -462,7 +468,7 @@ void __init omap3_init_early(void)
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap3xxx_clk_init();
+        omap_clk_init = omap3xxx_clk_init;
 }
 
 void __init omap3430_init_early(void)
@@ -500,7 +506,7 @@ void __init ti81xx_init_early(void)
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap3xxx_clk_init();
+        omap_clk_init = omap3xxx_clk_init;
 }
 
 void __init omap3_init_late(void)
@@ -568,7 +574,7 @@ void __init am33xx_init_early(void)
         am33xx_clockdomains_init();
         am33xx_hwmod_init();
         omap_hwmod_init_postsetup();
-        am33xx_clk_init();
+        omap_clk_init = am33xx_clk_init;
 }
 #endif
 
@@ -593,7 +599,7 @@ void __init omap4430_init_early(void)
         omap44xx_clockdomains_init();
         omap44xx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap4xxx_clk_init();
+        omap_clk_init = omap4xxx_clk_init;
 }
 
 void __init omap4430_init_late(void)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index c2c798c08c2b..a202a4785104 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1368,7 +1368,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
         }
 
         if (sf & SYSC_HAS_MIDLEMODE) {
-                if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+                if (oh->flags & HWMOD_FORCE_MSTANDBY) {
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
                         idlemode = HWMOD_IDLEMODE_NO;
                 } else {
                         if (sf & SYSC_HAS_ENAWAKEUP)
@@ -1440,7 +1442,8 @@ static void _idle_sysc(struct omap_hwmod *oh)
         }
 
         if (sf & SYSC_HAS_MIDLEMODE) {
-                if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+                if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
+                    (oh->flags & HWMOD_FORCE_MSTANDBY)) {
                         idlemode = HWMOD_IDLEMODE_FORCE;
                 } else {
                         if (sf & SYSC_HAS_ENAWAKEUP)
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d43d9b608eda..d5dc935f6060 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm {
  *
  * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
  *     of idle, rather than relying on module smart-idle
- * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
- *     of standby, rather than relying on module smart-standby
+ * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
+ *     out of standby, rather than relying on module smart-standby
  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
  *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
  *     XXX Should be HWMOD_SETUP_NO_RESET
@@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm {
  *     correctly, or this is being abused to deal with some PM latency
  *     issues -- but we're currently suffering from a shortage of
  *     folks who are able to track these issues down properly.
+ * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
+ *     is kept in force-standby mode. Failing to do so causes PM problems
+ *     with musb on OMAP3630 at least. Note that musb has a dedicated register
+ *     to control MSTANDBY signal when MIDLEMODE is set to force-standby.
  */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
@@ -471,6 +475,7 @@ struct omap_hwmod_omap4_prcm {
 #define HWMOD_16BIT_REG                         (1 << 8)
 #define HWMOD_EXT_OPT_MAIN_CLK                  (1 << 9)
 #define HWMOD_BLOCK_WFI                         (1 << 10)
+#define HWMOD_FORCE_MSTANDBY                    (1 << 11)
 
 /*
  * omap_hwmod._int_flags definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index ac7e03ec952f..5112d04e7b79 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
          * broken when autoidle is enabled
          * workaround is to disable the autoidle bit at module level.
+         *
+         * Enabling the device in any other MIDLEMODE setting but force-idle
+         * causes core_pwrdm not enter idle states at least on OMAP3630.
+         * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
+         * signal when MIDLEMODE is set to force-idle.
          */
         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
-                                | HWMOD_SWSUP_MSTANDBY,
+                                | HWMOD_FORCE_MSTANDBY,
 };
 
 /* usb_otg_hs */
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 0e47d2e1687c..9e0576569e07 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2714,6 +2714,10 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
         { }
 };
 
+static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
+        { .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" },
+};
+
 /* ocp2scp_usb_phy */
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
         .name           = "ocp2scp_usb_phy",
@@ -2728,6 +2732,8 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                 },
         },
         .dev_attr       = ocp2scp_dev_attr,
+        .opt_clks       = ocp2scp_usb_phy_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2bdd4cf17a8f..f62b509ed08d 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -547,6 +547,8 @@ static inline void __init realtime_counter_init(void)
                                clksrc_nr, clksrc_src)                   \
 void __init omap##name##_gptimer_timer_init(void)                       \
 {                                                                       \
+        if (omap_clk_init)                                              \
+                omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
@@ -556,6 +558,8 @@ void __init omap##name##_gptimer_timer_init(void)			\
                                 clksrc_nr, clksrc_src)                  \
 void __init omap##name##_sync32k_timer_init(void)               \
 {                                                                       \
+        if (omap_clk_init)                                              \
+                omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 86eec4159cbc..9075461999c1 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -51,11 +51,13 @@ config MACH_LITTLETON
 config MACH_TAVOREVB
         bool "PXA930 Evaluation Board (aka TavorEVB)"
         select CPU_PXA930
+        select CPU_PXA935
         select PXA3xx
 
 config MACH_SAAR
         bool "PXA930 Handheld Platform (aka SAAR)"
         select CPU_PXA930
+        select CPU_PXA935
         select PXA3xx
 
 comment "Third Party Dev Platforms (sorted by vendor name)"
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index daa86d39ed9e..666094315ab1 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -1107,8 +1107,33 @@ struct resource pxa_resource_gpio[] = {
         },
 };
 
-struct platform_device pxa_device_gpio = {
-        .name           = "pxa-gpio",
+struct platform_device pxa25x_device_gpio = {
+#ifdef CONFIG_CPU_PXA26x
+        .name           = "pxa26x-gpio",
+#else
+        .name           = "pxa25x-gpio",
+#endif
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_resource_gpio),
+        .resource       = pxa_resource_gpio,
+};
+
+struct platform_device pxa27x_device_gpio = {
+        .name           = "pxa27x-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_resource_gpio),
+        .resource       = pxa_resource_gpio,
+};
+
+struct platform_device pxa3xx_device_gpio = {
+        .name           = "pxa3xx-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_resource_gpio),
+        .resource       = pxa_resource_gpio,
+};
+
+struct platform_device pxa93x_device_gpio = {
+        .name           = "pxa93x-gpio",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(pxa_resource_gpio),
         .resource       = pxa_resource_gpio,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 1475db107254..0f3fd0d65b12 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -16,7 +16,6 @@ extern struct platform_device pxa_device_ficp;
 extern struct platform_device sa1100_device_rtc;
 extern struct platform_device pxa_device_rtc;
 extern struct platform_device pxa_device_ac97;
-extern struct platform_device pxa_device_gpio;
 
 extern struct platform_device pxa27x_device_i2c_power;
 extern struct platform_device pxa27x_device_ohci;
@@ -46,4 +45,9 @@ extern struct platform_device pxa_device_asoc_ssp2;
 extern struct platform_device pxa_device_asoc_ssp3;
 extern struct platform_device pxa_device_asoc_ssp4;
 
+extern struct platform_device pxa25x_device_gpio;
+extern struct platform_device pxa27x_device_gpio;
+extern struct platform_device pxa3xx_device_gpio;
+extern struct platform_device pxa93x_device_gpio;
+
 void __init pxa_register_device(struct platform_device *dev, void *data);
diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S
deleted file mode 100644
index 70b112e8ef68..000000000000
--- a/arch/arm/mach-pxa/include/mach/debug-macro.S
+++ /dev/null
@@ -1,23 +0,0 @@
-/* arch/arm/mach-pxa/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include "hardware.h"
-
-                .macro  addruart, rp, rv, tmp
-                mov     \rp, #0x00100000
-                orr     \rv, \rp, #io_p2v(0x40000000)   @ virtual
-                orr     \rp, \rp, #0x40000000           @ physical
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 3f5171eaf67b..f2c28972084d 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -208,7 +208,11 @@ static struct clk_lookup pxa25x_clkregs[] = {
         INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
         INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
         INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
-        INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+#ifdef CONFIG_CPU_PXA26x
+        INIT_CLKREG(&clk_dummy, "pxa26x-gpio", NULL),
+#else
+        INIT_CLKREG(&clk_dummy, "pxa25x-gpio", NULL),
+#endif
         INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
@@ -340,7 +344,8 @@ void __init pxa25x_map_io(void)
 }
 
 static struct pxa_gpio_platform_data pxa25x_gpio_info __initdata = {
-        .gpio_set_wake = gpio_set_wake,
+        .irq_base       = PXA_GPIO_TO_IRQ(0),
+        .gpio_set_wake  = gpio_set_wake,
 };
 
 static struct platform_device *pxa25x_devices[] __initdata = {
@@ -375,7 +380,7 @@ static int __init pxa25x_init(void)
                 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa2xx_clock_syscore_ops);
 
-                pxa_register_device(&pxa_device_gpio, &pxa25x_gpio_info);
+                pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info);
                 ret = platform_add_devices(pxa25x_devices,
                                            ARRAY_SIZE(pxa25x_devices));
                 if (ret)
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 3203a9f5b4a2..301471a07a10 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -237,7 +237,7 @@ static struct clk_lookup pxa27x_clkregs[] = {
         INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
         INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
         INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
-        INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "pxa27x-gpio", NULL),
         INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
@@ -431,7 +431,8 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 }
 
 static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
-        .gpio_set_wake = gpio_set_wake,
+        .irq_base       = PXA_GPIO_TO_IRQ(0),
+        .gpio_set_wake  = gpio_set_wake,
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -470,7 +471,7 @@ static int __init pxa27x_init(void)
                 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa2xx_clock_syscore_ops);
 
-                pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
+                pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info);
                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
         }
 
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 656a1bb16d14..87011f3de69d 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/gpio-pxa.h>
 #include <linux/pm.h>
 #include <linux/platform_device.h>
 #include <linux/irq.h>
@@ -92,7 +93,8 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
         INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
-        INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL),
+        INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL),
         INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
@@ -435,8 +437,11 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
         pxa_register_device(&pxa3xx_device_i2c_power, info);
 }
 
+static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
+        .irq_base       = PXA_GPIO_TO_IRQ(0),
+};
+
 static struct platform_device *devices[] __initdata = {
-        &pxa_device_gpio,
         &pxa27x_device_udc,
         &pxa_device_pmu,
         &pxa_device_i2s,
@@ -482,8 +487,18 @@ static int __init pxa3xx_init(void)
                 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa3xx_clock_syscore_ops);
 
-                if (!of_have_populated_dt())
-                        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+                if (of_have_populated_dt())
+                        return 0;
+
+                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+                if (ret)
+                        return ret;
+                if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
+                        platform_device_add_data(&pxa3xx_device_gpio,
+                                                 &pxa3xx_gpio_pdata,
+                                                 sizeof(pxa3xx_gpio_pdata));
+                        ret = platform_device_register(&pxa3xx_device_gpio);
+                }
         }
 
         return ret;
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 8aeacf908784..ab624487cf39 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -12,12 +12,15 @@
 
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
 #include <linux/dma-mapping.h>
+#include <linux/irq.h>
+#include <linux/gpio-pxa.h>
+#include <linux/platform_device.h>
 
 #include <mach/pxa930.h>
 
+#include "devices.h"
+
 static struct mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
 
         MFP_ADDR(GPIO0, 0x02e0),
@@ -190,11 +193,21 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
         MFP_ADDR_END,
 };
 
+static struct pxa_gpio_platform_data pxa93x_gpio_pdata = {
+        .irq_base       = PXA_GPIO_TO_IRQ(0),
+};
+
 static int __init pxa930_init(void)
 {
+        int ret = 0;
+
         if (cpu_is_pxa93x()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa930_mfp_addr_map);
+                platform_device_add_data(&pxa93x_device_gpio,
+                                         &pxa93x_gpio_pdata,
+                                         sizeof(pxa93x_gpio_pdata));
+                ret = platform_device_register(&pxa93x_device_gpio);
         }
 
         if (cpu_is_pxa935())
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 9255546e7bf6..ab2bb71db9b2 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -102,6 +102,19 @@ config MACH_MARZEN
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
+config MACH_MARZEN_REFERENCE
+        bool "MARZEN board - Reference Device Tree Implementation"
+        depends on ARCH_R8A7779
+        select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select USE_OF
+        ---help---
+           Use reference implementation of Marzen board support
+           which makes use of device tree at the expense
+           of not supporting a number of devices.
+
+           This is intended to aid developers
+
 config MACH_KZM9D
         bool "KZM9D board"
         depends on ARCH_EMEV2
@@ -116,6 +129,20 @@ config MACH_KZM9G
         select SND_SOC_AK4642 if SND_SIMPLE_CARD
         select USE_OF
 
+config MACH_KZM9G_REFERENCE
+        bool "KZM-A9-GT board - Reference Device Tree Implementation"
+        depends on ARCH_SH73A0
+        select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select SND_SOC_AK4642 if SND_SIMPLE_CARD
+        select USE_OF
+        ---help---
+           Use reference implementation of KZM-A9-GT board support
+           which makes as greater use of device tree at the expense
+           of not supporting a number of devices.
+
+           This is intended to aid developers
+
 comment "SH-Mobile System Configuration"
 
 config CPU_HAS_INTEVT
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e1fac57514b9..c621edfa6ead 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -14,10 +14,9 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.o clock-emev2.o
 
 # SMP objects
 smp-y                           := platsmp.o headsmp.o
-smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-sh73a0.o
-smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o
-smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o
+smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-scu.o
+smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o headsmp-scu.o
+smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o headsmp-scu.o
 
 # IRQ objects
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
@@ -39,9 +38,11 @@ obj-$(CONFIG_MACH_MACKEREL)	+= board-mackerel.o
 obj-$(CONFIG_MACH_KOTA2)        += board-kota2.o
 obj-$(CONFIG_MACH_BONITO)       += board-bonito.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
+obj-$(CONFIG_MACH_MARZEN_REFERENCE)     += board-marzen-reference.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
 obj-$(CONFIG_MACH_KZM9D)        += board-kzm9d.o
 obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
+obj-$(CONFIG_MACH_KZM9G_REFERENCE)      += board-kzm9g-reference.o
 
 # Framework support
 obj-$(CONFIG_SMP)               += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 8ff53a19c48c..c7540710906f 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -23,6 +23,8 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
@@ -304,9 +306,9 @@ static int lcd_backlight_set_brightness(int brightness)
 
         if (brightness == 0) {
                 /* Reset the chip */
-                gpio_set_value(GPIO_PORT235, 0);
+                gpio_set_value(235, 0);
                 mdelay(24);
-                gpio_set_value(GPIO_PORT235, 1);
+                gpio_set_value(235, 1);
                 return 0;
         }
 
@@ -406,7 +408,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
         .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
-        .cd_gpio        = GPIO_PORT251,
+        .cd_gpio        = 251,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -461,7 +463,7 @@ static struct regulator_init_data cn4_power_init_data = {
 static struct fixed_voltage_config cn4_power_info = {
         .supply_name = "CN4 SD/MMC Vdd",
         .microvolts = 3300000,
-        .gpio = GPIO_PORT114,
+        .gpio = 114,
         .enable_high = 1,
         .init_data = &cn4_power_init_data,
 };
@@ -479,10 +481,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
         static int power_gpio = -EINVAL;
 
         if (power_gpio < 0) {
-                int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW,
+                int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW,
                                            "sdhi1_power");
                 if (!ret)
-                        power_gpio = GPIO_PORT114;
+                        power_gpio = 114;
         }
 
         /*
@@ -493,7 +495,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
          * regulator driver. We have to live with the race in case the driver
          * gets unloaded and the GPIO freed between these two steps.
          */
-        gpio_set_value(GPIO_PORT114, state);
+        gpio_set_value(114, state);
 }
 
 static struct sh_mobile_sdhi_info sh_sdhi1_info = {
@@ -550,6 +552,77 @@ static struct platform_device *ag5evm_devices[] __initdata = {
         &sdhi1_device,
 };
 
+static unsigned long pin_pullup_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map ag5evm_pinctrl_map[] = {
+        /* FSIA */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_mclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_data_out", "fsia"),
+        /* I2C2 & I2C3 */
+        PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
+                                  "i2c2_0", "i2c2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
+                                  "i2c3_0", "i2c3"),
+        /* IrDA */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0",
+                                  "irda_0", "irda"),
+        /* KEYSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_in8", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out04", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out5", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out6_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out7_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out8_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out9_2", "keysc"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                      "keysc_in8", pin_pullup_conf),
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_ctrl_0", "mmc0"),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                    "PORT279", pin_pullup_conf),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                      "mmc0_data8_0", pin_pullup_conf),
+        /* SCIFA2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+                                  "scifa2_data_0", "scifa2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+                                  "scifa2_ctrl_0", "scifa2"),
+        /* SDHI0 (CN15 [SD I/F]) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI1 (CN4 [WLAN I/F]) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                  "sdhi1_ctrl", "sdhi1"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                      "sdhi1_data4", pin_pullup_conf),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                    "PORT263", pin_pullup_conf),
+};
+
 static void __init ag5evm_init(void)
 {
         regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -558,96 +631,27 @@ static void __init ag5evm_init(void)
                                      ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
         regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+        pinctrl_register_mappings(ag5evm_pinctrl_map,
+                                  ARRAY_SIZE(ag5evm_pinctrl_map));
         sh73a0_pinmux_init();
 
-        /* enable SCIFA2 */
-        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
-        gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
-
-        /* enable KEYSC */
-        gpio_request(GPIO_FN_KEYIN0_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN1_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN2_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN3_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN4_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN5_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN6_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN7_PU, NULL);
-        gpio_request(GPIO_FN_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_KEYOUT5, NULL);
-        gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
-        gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
-        gpio_request(GPIO_FN_KEYOUT8, NULL);
-        gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
-
-        /* enable I2C channel 2 and 3 */
-        gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
-        gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
-        gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
-        gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
-
         /* enable MMCIF */
-        gpio_request(GPIO_FN_MMCCLK0, NULL);
-        gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
-        gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
+        gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
 
         /* enable SMSC911X */
-        gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
-        gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
-
-        /* FSI A */
-        gpio_request(GPIO_FN_FSIACK, NULL);
-        gpio_request(GPIO_FN_FSIAILR, NULL);
-        gpio_request(GPIO_FN_FSIAIBT, NULL);
-        gpio_request(GPIO_FN_FSIAISLD, NULL);
-        gpio_request(GPIO_FN_FSIAOSLD, NULL);
-
-        /* IrDA */
-        gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
-        gpio_request(GPIO_FN_PORT242_IRDA_IN,  NULL);
-        gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
+        gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
+        gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
 
         /* LCD panel */
-        gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
+        gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
         mdelay(1);
-        gpio_set_value(GPIO_PORT217, 1);
+        gpio_set_value(217, 1);
         mdelay(100);
 
         /* LCD backlight controller */
-        gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
+        gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
         lcd_backlight_set_brightness(0);
 
-        /* enable SDHI0 on CN15 [SD I/F] */
-        gpio_request(GPIO_FN_SDHIWP0, NULL);
-        gpio_request(GPIO_FN_SDHICMD0, NULL);
-        gpio_request(GPIO_FN_SDHICLK0, NULL);
-        gpio_request(GPIO_FN_SDHID0_3, NULL);
-        gpio_request(GPIO_FN_SDHID0_2, NULL);
-        gpio_request(GPIO_FN_SDHID0_1, NULL);
-        gpio_request(GPIO_FN_SDHID0_0, NULL);
-
-        /* enable SDHI1 on CN4 [WLAN I/F] */
-        gpio_request(GPIO_FN_SDHICLK1, NULL);
-        gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
-
 #ifdef CONFIG_CACHE_L2X0
         /* Shared attribute override enable, 64K*8way */
         l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 38f1259a0daf..45f78cadec1d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -34,6 +34,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/tsc2007.h>
 #include <linux/io.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -273,11 +274,11 @@ static struct platform_device smc911x_device = {
 
 /*
  * The card detect pin of the top SD/MMC slot (CN7) is active low and is
- * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ * connected to GPIO A22 of SH7372 (GPIO 41).
  */
 static int slot_cn7_get_cd(struct platform_device *pdev)
 {
-        return !gpio_get_value(GPIO_PORT41);
+        return !gpio_get_value(41);
 }
 /* MERAM */
 static struct sh_mobile_meram_info meram_info = {
@@ -838,22 +839,22 @@ static struct platform_device fsi_hdmi_device = {
 static struct gpio_led ap4evb_leds[] = {
         {
                 .name                   = "led4",
-                .gpio                   = GPIO_PORT185,
+                .gpio                   = 185,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name                   = "led2",
-                .gpio                   = GPIO_PORT186,
+                .gpio                   = 186,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name                   = "led3",
-                .gpio                   = GPIO_PORT187,
+                .gpio                   = 187,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name                   = "led1",
-                .gpio                   = GPIO_PORT188,
+                .gpio                   = 188,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }
 };
@@ -1026,10 +1027,10 @@ out:
 /* TouchScreen */
 #ifdef CONFIG_AP4EVB_QHD
 # define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
-# define GPIO_TSC_PORT  GPIO_PORT123
+# define GPIO_TSC_PORT  123
 #else /* WVGA */
 # define GPIO_TSC_IRQ   GPIO_FN_IRQ7_40
-# define GPIO_TSC_PORT  GPIO_PORT40
+# define GPIO_TSC_PORT  40
 #endif
 
 #define IRQ28   evt2irq(0x3380) /* IRQ28A */
@@ -1084,6 +1085,28 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 
 
+static const struct pinctrl_map ap4evb_pinctrl_map[] = {
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+                                  "mmc0_ctrl_0", "mmc0"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+                                  "sdhi1_ctrl", "sdhi1"),
+};
+
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
 #define GPIO_PORT10CR   IOMEM(0xE605100A)
 #define USCCR1          IOMEM(0xE6058144)
@@ -1110,6 +1133,8 @@ static void __init ap4evb_init(void)
         /* External clock source */
         clk_set_rate(&sh7372_dv_clki_clk, 27000000);
 
+        pinctrl_register_mappings(ap4evb_pinctrl_map,
+                                  ARRAY_SIZE(ap4evb_pinctrl_map));
         sh7372_pinmux_init();
 
         /* enable SCIFA0 */
@@ -1121,40 +1146,10 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_IRQ6_39,   NULL);
 
         /* enable Debug switch (S6) */
-        gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL);
-
-        /* SDHI0 */
-        gpio_request(GPIO_FN_SDHICD0, NULL);
-        gpio_request(GPIO_FN_SDHIWP0, NULL);
-        gpio_request(GPIO_FN_SDHICMD0, NULL);
-        gpio_request(GPIO_FN_SDHICLK0, NULL);
-        gpio_request(GPIO_FN_SDHID0_3, NULL);
-        gpio_request(GPIO_FN_SDHID0_2, NULL);
-        gpio_request(GPIO_FN_SDHID0_1, NULL);
-        gpio_request(GPIO_FN_SDHID0_0, NULL);
-
-        /* SDHI1 */
-        gpio_request(GPIO_FN_SDHICMD1, NULL);
-        gpio_request(GPIO_FN_SDHICLK1, NULL);
-        gpio_request(GPIO_FN_SDHID1_3, NULL);
-        gpio_request(GPIO_FN_SDHID1_2, NULL);
-        gpio_request(GPIO_FN_SDHID1_1, NULL);
-        gpio_request(GPIO_FN_SDHID1_0, NULL);
-
-        /* MMCIF */
-        gpio_request(GPIO_FN_MMCD0_0, NULL);
-        gpio_request(GPIO_FN_MMCD0_1, NULL);
-        gpio_request(GPIO_FN_MMCD0_2, NULL);
-        gpio_request(GPIO_FN_MMCD0_3, NULL);
-        gpio_request(GPIO_FN_MMCD0_4, NULL);
-        gpio_request(GPIO_FN_MMCD0_5, NULL);
-        gpio_request(GPIO_FN_MMCD0_6, NULL);
-        gpio_request(GPIO_FN_MMCD0_7, NULL);
-        gpio_request(GPIO_FN_MMCCMD0, NULL);
-        gpio_request(GPIO_FN_MMCCLK0, NULL);
+        gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
+        gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
+        gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
+        gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
 
         /* USB enable */
         gpio_request(GPIO_FN_VBUS0_1,    NULL);
@@ -1172,15 +1167,15 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_FSIAILR,   NULL);
         gpio_request(GPIO_FN_FSIAISLD,  NULL);
         gpio_request(GPIO_FN_FSIAOSLD,  NULL);
-        gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
+        gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
-        gpio_request(GPIO_PORT9, NULL);
-        gpio_request(GPIO_PORT10, NULL);
+        gpio_request(9, NULL);
+        gpio_request(10, NULL);
         gpio_direction_none(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
         gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
 
         /* card detect pin for MMC slot (CN7) */
-        gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
+        gpio_request_one(41, GPIOF_IN, NULL);
 
         /* setup FSI2 port B (HDMI) */
         gpio_request(GPIO_FN_FSIBCK, NULL);
@@ -1268,8 +1263,8 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_LCDDISP,  NULL);
         gpio_request(GPIO_FN_LCDDCK,   NULL);
 
-        gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
-        gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+        gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
+        gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
         lcdc_info.clock_source                  = LCDC_CLK_BUS;
         lcdc_info.ch[0].interface_type          = RGB18;
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index f2ec0777cfbe..7a78f9486684 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -28,7 +28,10 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <linux/regulator/driver.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/regulator/fixed.h>
+#include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/sh_eth.h>
 #include <linux/videodev2.h>
@@ -227,7 +230,7 @@ static void usbhsf_power_ctrl(struct platform_device *pdev,
 
 static int usbhsf_get_vbus(struct platform_device *pdev)
 {
-        return gpio_get_value(GPIO_PORT209);
+        return gpio_get_value(209);
 }
 
 static irqreturn_t usbhsf_interrupt(int irq, void *data)
@@ -535,10 +538,10 @@ static struct platform_device hdmi_lcdc_device = {
         { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
 
 static struct gpio_keys_button gpio_buttons[] = {
-        GPIO_KEY(KEY_POWER,     GPIO_PORT99,    "SW3", .wakeup = 1),
-        GPIO_KEY(KEY_BACK,      GPIO_PORT100,   "SW4"),
-        GPIO_KEY(KEY_MENU,      GPIO_PORT97,    "SW5"),
-        GPIO_KEY(KEY_HOME,      GPIO_PORT98,    "SW6"),
+        GPIO_KEY(KEY_POWER,     99,     "SW3", .wakeup = 1),
+        GPIO_KEY(KEY_BACK,      100,    "SW4"),
+        GPIO_KEY(KEY_MENU,      97,     "SW5"),
+        GPIO_KEY(KEY_HOME,      98,     "SW6"),
 };
 
 static struct gpio_keys_platform_data gpio_key_info = {
@@ -554,15 +557,119 @@ static struct platform_device gpio_keys_device = {
         },
 };
 
-/* Fixed 3.3V regulator to be used by SDHI0, SDHI1, MMCIF */
-static struct regulator_consumer_supply fixed3v3_power_consumers[] =
-{
+/* Fixed 3.3V regulator to be used by SDHI1, MMCIF */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
+};
+
+/* Fixed 3.3V regulator to be used by SDHI0 */
+static struct regulator_consumer_supply vcc_sdhi0_consumers[] = {
         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_init_data vcc_sdhi0_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(vcc_sdhi0_consumers),
+        .consumer_supplies      = vcc_sdhi0_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi0_info = {
+        .supply_name = "SDHI0 Vcc",
+        .microvolts = 3300000,
+        .gpio = GPIO_PORT75,
+        .enable_high = 1,
+        .init_data = &vcc_sdhi0_init_data,
+};
+
+static struct platform_device vcc_sdhi0 = {
+        .name = "reg-fixed-voltage",
+        .id   = 1,
+        .dev  = {
+                .platform_data = &vcc_sdhi0_info,
+        },
+};
+
+/* 1.8 / 3.3V SDHI0 VccQ regulator */
+static struct regulator_consumer_supply vccq_sdhi0_consumers[] = {
         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_init_data vccq_sdhi0_init_data = {
+        .constraints = {
+                .input_uV       = 3300000,
+                .min_uV         = 1800000,
+                .max_uV         = 3300000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(vccq_sdhi0_consumers),
+        .consumer_supplies      = vccq_sdhi0_consumers,
+};
+
+static struct gpio vccq_sdhi0_gpios[] = {
+        {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
+};
+
+static struct gpio_regulator_state vccq_sdhi0_states[] = {
+        { .value = 3300000, .gpios = (0 << 0) },
+        { .value = 1800000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config vccq_sdhi0_info = {
+        .supply_name = "vqmmc",
+
+        .enable_gpio = GPIO_PORT74,
+        .enable_high = 1,
+        .enabled_at_boot = 0,
+
+        .gpios = vccq_sdhi0_gpios,
+        .nr_gpios = ARRAY_SIZE(vccq_sdhi0_gpios),
+
+        .states = vccq_sdhi0_states,
+        .nr_states = ARRAY_SIZE(vccq_sdhi0_states),
+
+        .type = REGULATOR_VOLTAGE,
+        .init_data = &vccq_sdhi0_init_data,
+};
+
+static struct platform_device vccq_sdhi0 = {
+        .name = "gpio-regulator",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &vccq_sdhi0_info,
+        },
+};
+
+/* Fixed 3.3V regulator to be used by SDHI1 */
+static struct regulator_consumer_supply vcc_sdhi1_consumers[] = {
         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
+};
+
+static struct regulator_init_data vcc_sdhi1_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(vcc_sdhi1_consumers),
+        .consumer_supplies      = vcc_sdhi1_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi1_info = {
+        .supply_name = "SDHI1 Vcc",
+        .microvolts = 3300000,
+        .gpio = GPIO_PORT16,
+        .enable_high = 1,
+        .init_data = &vcc_sdhi1_init_data,
+};
+
+static struct platform_device vcc_sdhi1 = {
+        .name = "reg-fixed-voltage",
+        .id   = 2,
+        .dev  = {
+                .platform_data = &vcc_sdhi1_info,
+        },
 };
 
 /* SDHI0 */
@@ -578,10 +685,10 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] =
 static struct sh_mobile_sdhi_info sdhi0_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\
-                          MMC_CAP_NEEDS_POLL,
-        .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
-        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
+        .cd_gpio        = GPIO_PORT167,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -620,9 +727,11 @@ static struct platform_device sdhi0_device = {
 static struct sh_mobile_sdhi_info sdhi1_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
-        .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
-        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
+        /* Port72 cannot generate IRQs, will be used in polling mode. */
+        .cd_gpio        = GPIO_PORT72,
 };
 
 static struct resource sdhi1_resources[] = {
@@ -656,10 +765,20 @@ static struct platform_device sdhi1_device = {
         .resource       = sdhi1_resources,
 };
 
+static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = {
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+                                  "sdhi1_ctrl", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+                                  "sdhi1_cd", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+                                  "sdhi1_wp", "sdhi1"),
+};
+
 /* MMCIF */
 static struct sh_mmcif_plat_data sh_mmcif_plat = {
         .sup_pclk       = 0,
-        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
         .caps           = MMC_CAP_4_BIT_DATA |
                           MMC_CAP_8_BIT_DATA |
                           MMC_CAP_NONREMOVABLE,
@@ -708,9 +827,9 @@ static int mt9t111_power(struct device *dev, int mode)
                 /* video1 (= CON1 camera) expect 24MHz */
                 clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
                 clk_enable(mclk);
-                gpio_set_value(GPIO_PORT158, 1);
+                gpio_set_value(158, 1);
         } else {
-                gpio_set_value(GPIO_PORT158, 0);
+                gpio_set_value(158, 0);
                 clk_disable(mclk);
         }
 
@@ -864,8 +983,8 @@ static struct platform_device fsi_hdmi_device = {
 
 /* RTC: RTC connects i2c-gpio. */
 static struct i2c_gpio_platform_data i2c_gpio_data = {
-        .sda_pin        = GPIO_PORT208,
-        .scl_pin        = GPIO_PORT91,
+        .sda_pin        = 208,
+        .scl_pin        = 91,
         .udelay         = 5, /* 100 kHz */
 };
 
@@ -902,6 +1021,8 @@ static struct platform_device *eva_devices[] __initdata = {
         &lcdc0_device,
         &gpio_keys_device,
         &sh_eth_device,
+        &vcc_sdhi0,
+        &vccq_sdhi0,
         &sdhi0_device,
         &sh_mmcif_device,
         &hdmi_device,
@@ -914,6 +1035,28 @@ static struct platform_device *eva_devices[] __initdata = {
         &i2c_gpio_device,
 };
 
+static const struct pinctrl_map eva_pinctrl_map[] = {
+        /* LCD0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_data24_0", "lcd0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_lclk_1", "lcd0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_sync", "lcd0"),
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
+                                  "mmc0_data8_1", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
+                                  "mmc0_ctrl_1", "mmc0"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+                                  "sdhi0_wp", "sdhi0"),
+};
+
 static void __init eva_clock_init(void)
 {
         struct clk *system      = clk_get(NULL, "system_clk");
@@ -961,6 +1104,8 @@ static void __init eva_init(void)
         regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
                                      ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
 
+        pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
+
         r8a7740_pinmux_init();
         r8a7740_meram_workaround();
 
@@ -970,42 +1115,13 @@ static void __init eva_init(void)
 
         /* LCDC0 */
         gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
-        gpio_request(GPIO_FN_LCD0_D0,           NULL);
-        gpio_request(GPIO_FN_LCD0_D1,           NULL);
-        gpio_request(GPIO_FN_LCD0_D2,           NULL);
-        gpio_request(GPIO_FN_LCD0_D3,           NULL);
-        gpio_request(GPIO_FN_LCD0_D4,           NULL);
-        gpio_request(GPIO_FN_LCD0_D5,           NULL);
-        gpio_request(GPIO_FN_LCD0_D6,           NULL);
-        gpio_request(GPIO_FN_LCD0_D7,           NULL);
-        gpio_request(GPIO_FN_LCD0_D8,           NULL);
-        gpio_request(GPIO_FN_LCD0_D9,           NULL);
-        gpio_request(GPIO_FN_LCD0_D10,          NULL);
-        gpio_request(GPIO_FN_LCD0_D11,          NULL);
-        gpio_request(GPIO_FN_LCD0_D12,          NULL);
-        gpio_request(GPIO_FN_LCD0_D13,          NULL);
-        gpio_request(GPIO_FN_LCD0_D14,          NULL);
-        gpio_request(GPIO_FN_LCD0_D15,          NULL);
-        gpio_request(GPIO_FN_LCD0_D16,          NULL);
-        gpio_request(GPIO_FN_LCD0_D17,          NULL);
-        gpio_request(GPIO_FN_LCD0_D18_PORT40,   NULL);
-        gpio_request(GPIO_FN_LCD0_D19_PORT4,    NULL);
-        gpio_request(GPIO_FN_LCD0_D20_PORT3,    NULL);
-        gpio_request(GPIO_FN_LCD0_D21_PORT2,    NULL);
-        gpio_request(GPIO_FN_LCD0_D22_PORT0,    NULL);
-        gpio_request(GPIO_FN_LCD0_D23_PORT1,    NULL);
-        gpio_request(GPIO_FN_LCD0_DCK,          NULL);
-        gpio_request(GPIO_FN_LCD0_VSYN,         NULL);
-        gpio_request(GPIO_FN_LCD0_HSYN,         NULL);
-        gpio_request(GPIO_FN_LCD0_DISP,         NULL);
-        gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
-
-        gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
-        gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
+
+        gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+        gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
 
         /* Touchscreen */
         gpio_request(GPIO_FN_IRQ10,     NULL); /* TP_INT */
-        gpio_request_one(GPIO_PORT166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
+        gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
 
         /* GETHER */
         gpio_request(GPIO_FN_ET_CRS,            NULL);
@@ -1028,12 +1144,12 @@ static void __init eva_init(void)
         gpio_request(GPIO_FN_ET_RX_DV,          NULL);
         gpio_request(GPIO_FN_ET_RX_CLK,         NULL);
 
-        gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
+        gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
 
         /* USB */
-        gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
+        gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
 
-        if (gpio_get_value(GPIO_PORT159)) {
+        if (gpio_get_value(159)) {
                 /* USB Host */
         } else {
                 /* USB Func */
@@ -1042,47 +1158,15 @@ static void __init eva_init(void)
                  * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
                  * USB connection/disconnection (usbhsf_get_vbus()).
                  * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
-                 * and select GPIO_PORT209 here
+                 * and select GPIO 209 here
                  */
                 gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
-                gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL);
+                gpio_request_one(209, GPIOF_IN, NULL);
 
                 platform_device_register(&usbhsf_device);
                 usb = &usbhsf_device;
         }
 
-        /* SDHI0 */
-        gpio_request(GPIO_FN_SDHI0_CMD, NULL);
-        gpio_request(GPIO_FN_SDHI0_CLK, NULL);
-        gpio_request(GPIO_FN_SDHI0_D0, NULL);
-        gpio_request(GPIO_FN_SDHI0_D1, NULL);
-        gpio_request(GPIO_FN_SDHI0_D2, NULL);
-        gpio_request(GPIO_FN_SDHI0_D3, NULL);
-        gpio_request(GPIO_FN_SDHI0_WP, NULL);
-
-        gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL);  /* SDHI0_18/33_B */
-        gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
-        gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
-
-        /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
-
-        /*
-         * MMCIF
-         *
-         * Here doesn't care SW1.4 status,
-         * since CON2 is not mounted.
-         */
-        gpio_request(GPIO_FN_MMC1_CLK_PORT103,  NULL);
-        gpio_request(GPIO_FN_MMC1_CMD_PORT104,  NULL);
-        gpio_request(GPIO_FN_MMC1_D0_PORT149,   NULL);
-        gpio_request(GPIO_FN_MMC1_D1_PORT148,   NULL);
-        gpio_request(GPIO_FN_MMC1_D2_PORT147,   NULL);
-        gpio_request(GPIO_FN_MMC1_D3_PORT146,   NULL);
-        gpio_request(GPIO_FN_MMC1_D4_PORT145,   NULL);
-        gpio_request(GPIO_FN_MMC1_D5_PORT144,   NULL);
-        gpio_request(GPIO_FN_MMC1_D6_PORT143,   NULL);
-        gpio_request(GPIO_FN_MMC1_D7_PORT142,   NULL);
-
         /* CEU0 */
         gpio_request(GPIO_FN_VIO0_D7,           NULL);
         gpio_request(GPIO_FN_VIO0_D6,           NULL);
@@ -1099,10 +1183,10 @@ static void __init eva_init(void)
         gpio_request(GPIO_FN_VIO_CKO,           NULL);
 
         /* CON1/CON15 Camera */
-        gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
-        gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
+        gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
+        gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
         /* see mt9t111_power() */
-        gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
+        gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
 
         /* FSI-WM8978 */
         gpio_request(GPIO_FN_FSIAIBT,           NULL);
@@ -1111,8 +1195,8 @@ static void __init eva_init(void)
         gpio_request(GPIO_FN_FSIAOSLD,          NULL);
         gpio_request(GPIO_FN_FSIAISLD_PORT5,    NULL);
 
-        gpio_request(GPIO_PORT7, NULL);
-        gpio_request(GPIO_PORT8, NULL);
+        gpio_request(7, NULL);
+        gpio_request(8, NULL);
         gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
         gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
 
@@ -1129,29 +1213,21 @@ static void __init eva_init(void)
          * DBGMD/LCDC0/FSIA MUX
          * DBGMD_SELECT_B should be set after setting PFC Function.
          */
-        gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL);
 
         /*
          * We can switch CON8/CON14 by SW1.5,
          * but it needs after DBGMD_SELECT_B
          */
-        gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL);
-        if (gpio_get_value(GPIO_PORT6)) {
+        gpio_request_one(6, GPIOF_IN, NULL);
+        if (gpio_get_value(6)) {
                 /* CON14 enable */
         } else {
                 /* CON8 (SDHI1) enable */
-                gpio_request(GPIO_FN_SDHI1_CLK, NULL);
-                gpio_request(GPIO_FN_SDHI1_CMD, NULL);
-                gpio_request(GPIO_FN_SDHI1_D0,  NULL);
-                gpio_request(GPIO_FN_SDHI1_D1,  NULL);
-                gpio_request(GPIO_FN_SDHI1_D2,  NULL);
-                gpio_request(GPIO_FN_SDHI1_D3,  NULL);
-                gpio_request(GPIO_FN_SDHI1_CD,  NULL);
-                gpio_request(GPIO_FN_SDHI1_WP,  NULL);
-
-                /* SDSLOT2_PON */
-                gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL);
+                pinctrl_register_mappings(eva_sdhi1_pinctrl_map,
+                                          ARRAY_SIZE(eva_sdhi1_pinctrl_map));
 
+                platform_device_register(&vcc_sdhi1);
                 platform_device_register(&sdhi1_device);
         }
 
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index e50f86691539..70d992c540ae 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -24,6 +24,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/regulator/fixed.h>
@@ -288,6 +289,16 @@ static struct platform_device lcdc0_device = {
         },
 };
 
+static const struct pinctrl_map lcdc0_pinctrl_map[] = {
+        /* LCD0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_data24_1", "lcd0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_lclk_1", "lcd0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_sync", "lcd0"),
+};
+
 /*
  * SMSC 9221
  */
@@ -392,8 +403,8 @@ static void __init bonito_init(void)
         /*
          * base board settings
          */
-        gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
-        if (!gpio_get_value(GPIO_PORT176)) {
+        gpio_request_one(176, GPIOF_IN, NULL);
+        if (!gpio_get_value(176)) {
                 u16 bsw2;
                 u16 bsw3;
                 u16 bsw4;
@@ -430,38 +441,11 @@ static void __init bonito_init(void)
                  */
                 if (BIT_ON(bsw2, 3) &&  /* S38.1 = OFF */
                     BIT_ON(bsw2, 2)) {  /* S38.2 = OFF */
-                        gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
-                        gpio_request(GPIO_FN_LCD0_D0,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D1,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D2,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D3,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D4,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D5,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D6,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D7,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D8,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D9,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D10,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D11,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D12,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D13,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D14,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D15,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D16,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D17,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D18_PORT163,  NULL);
-                        gpio_request(GPIO_FN_LCD0_D19_PORT162,  NULL);
-                        gpio_request(GPIO_FN_LCD0_D20_PORT161,  NULL);
-                        gpio_request(GPIO_FN_LCD0_D21_PORT158,  NULL);
-                        gpio_request(GPIO_FN_LCD0_D22_PORT160,  NULL);
-                        gpio_request(GPIO_FN_LCD0_D23_PORT159,  NULL);
-                        gpio_request(GPIO_FN_LCD0_DCK,          NULL);
-                        gpio_request(GPIO_FN_LCD0_VSYN,         NULL);
-                        gpio_request(GPIO_FN_LCD0_HSYN,         NULL);
-                        gpio_request(GPIO_FN_LCD0_DISP,         NULL);
-                        gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
-
-                        gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
+                        pinctrl_register_mappings(lcdc0_pinctrl_map,
+                                                  ARRAY_SIZE(lcdc0_pinctrl_map));
+                        gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
+
+                        gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
                                          NULL); /* LCDDON */
 
                         /* backlight on */
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 2ccc860403ef..ef5ca0ef0cb5 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -24,6 +24,8 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
@@ -135,17 +137,17 @@ static struct platform_device keysc_device = {
 #define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
 
 static struct gpio_keys_button gpio_buttons[] = {
-        GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */
-        GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */
-        GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */
-        GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */
-        GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */
-        GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */
-        GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */
-        GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */
-        /* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */
-        GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */
-        /* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */
+        GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */
+        GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */
+        GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */
+        GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */
+        GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */
+        GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */
+        GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */
+        GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */
+        /* Omitted button "C3?": 223 - S10: CUST [IRQ8] */
+        GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */
+        /* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */
 };
 
 static struct gpio_keys_platform_data gpio_key_info = {
@@ -165,9 +167,9 @@ static struct platform_device gpio_keys_device = {
 #define GPIO_LED(n, g) { .name = n, .gpio = g }
 
 static struct gpio_led gpio_leds[] = {
-        GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */
-        GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */
-        GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */
+        GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */
+        GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */
+        GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */
 };
 
 static struct gpio_led_platform_data gpio_leds_info = {
@@ -187,7 +189,7 @@ static struct platform_device gpio_leds_device = {
 static struct led_renesas_tpu_config led_renesas_tpu12_pdata = {
         .name           = "V2513",
         .pin_gpio_fn    = GPIO_FN_TPU1TO2,
-        .pin_gpio       = GPIO_PORT153,
+        .pin_gpio       = 153,
         .channel_offset = 0x90,
         .timer_bit = 2,
         .max_brightness = 1000,
@@ -215,7 +217,7 @@ static struct platform_device leds_tpu12_device = {
 static struct led_renesas_tpu_config led_renesas_tpu41_pdata = {
         .name           = "V2514",
         .pin_gpio_fn    = GPIO_FN_TPU4TO1,
-        .pin_gpio       = GPIO_PORT199,
+        .pin_gpio       = 199,
         .channel_offset = 0x50,
         .timer_bit = 1,
         .max_brightness = 1000,
@@ -243,7 +245,7 @@ static struct platform_device leds_tpu41_device = {
 static struct led_renesas_tpu_config led_renesas_tpu21_pdata = {
         .name           = "V2515",
         .pin_gpio_fn    = GPIO_FN_TPU2TO1,
-        .pin_gpio       = GPIO_PORT197,
+        .pin_gpio       = 197,
         .channel_offset = 0x50,
         .timer_bit = 1,
         .max_brightness = 1000,
@@ -271,7 +273,7 @@ static struct platform_device leds_tpu21_device = {
 static struct led_renesas_tpu_config led_renesas_tpu30_pdata = {
         .name           = "KEYLED",
         .pin_gpio_fn    = GPIO_FN_TPU3TO0,
-        .pin_gpio       = GPIO_PORT163,
+        .pin_gpio       = 163,
         .channel_offset = 0x10,
         .timer_bit = 0,
         .max_brightness = 1000,
@@ -433,6 +435,85 @@ static struct platform_device *kota2_devices[] __initdata = {
         &sdhi1_device,
 };
 
+static unsigned long pin_pullup_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map kota2_pinctrl_map[] = {
+        /* KEYSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_in8", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out04", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out5", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out6_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out7_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out8_0", "keysc"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                      "keysc_in8", pin_pullup_conf),
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_ctrl_0", "mmc0"),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                    "PORT279", pin_pullup_conf),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                      "mmc0_data8_0", pin_pullup_conf),
+        /* SCIFA2 (UART2) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+                                  "scifa2_data_0", "scifa2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+                                  "scifa2_ctrl_0", "scifa2"),
+        /* SCIFA4 (UART1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_data", "scifa4"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_ctrl", "scifa4"),
+        /* SCIFB (BT) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+                                  "scifb_data_0", "scifb"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+                                  "scifb_clk_0", "scifb"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+                                  "scifb_ctrl_0", "scifb"),
+        /* SDHI0 (microSD) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                      "sdhi0_data4", pin_pullup_conf),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                    "PORT256", pin_pullup_conf),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                    "PORT251", pin_pullup_conf),
+        /* SDHI1 (BCM4330) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                  "sdhi1_ctrl", "sdhi1"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                      "sdhi1_data4", pin_pullup_conf),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                    "PORT263", pin_pullup_conf),
+        /* SMSC911X */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+                                  "bsc_data_0_7", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+                                  "bsc_data_8_15", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+                                  "bsc_cs5_a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+                                  "bsc_we0", "bsc"),
+};
+
 static void __init kota2_init(void)
 {
         regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -441,97 +522,16 @@ static void __init kota2_init(void)
                                      ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
         regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+        pinctrl_register_mappings(kota2_pinctrl_map,
+                                  ARRAY_SIZE(kota2_pinctrl_map));
         sh73a0_pinmux_init();
 
-        /* SCIFA2 (UART2) */
-        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
-        gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
-
-        /* SCIFA4 (UART1) */
-        gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
-        gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
-        gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
-
         /* SMSC911X */
-        gpio_request(GPIO_FN_D0_NAF0, NULL);
-        gpio_request(GPIO_FN_D1_NAF1, NULL);
-        gpio_request(GPIO_FN_D2_NAF2, NULL);
-        gpio_request(GPIO_FN_D3_NAF3, NULL);
-        gpio_request(GPIO_FN_D4_NAF4, NULL);
-        gpio_request(GPIO_FN_D5_NAF5, NULL);
-        gpio_request(GPIO_FN_D6_NAF6, NULL);
-        gpio_request(GPIO_FN_D7_NAF7, NULL);
-        gpio_request(GPIO_FN_D8_NAF8, NULL);
-        gpio_request(GPIO_FN_D9_NAF9, NULL);
-        gpio_request(GPIO_FN_D10_NAF10, NULL);
-        gpio_request(GPIO_FN_D11_NAF11, NULL);
-        gpio_request(GPIO_FN_D12_NAF12, NULL);
-        gpio_request(GPIO_FN_D13_NAF13, NULL);
-        gpio_request(GPIO_FN_D14_NAF14, NULL);
-        gpio_request(GPIO_FN_D15_NAF15, NULL);
-        gpio_request(GPIO_FN_CS5A_, NULL);
-        gpio_request(GPIO_FN_WE0__FWE, NULL);
-        gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
-        gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
-
-        /* KEYSC */
-        gpio_request(GPIO_FN_KEYIN0_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN1_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN2_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN3_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN4_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN5_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN6_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN7_PU, NULL);
-        gpio_request(GPIO_FN_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_KEYOUT5, NULL);
-        gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
-        gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
-        gpio_request(GPIO_FN_KEYOUT8, NULL);
+        gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
+        gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
 
         /* MMCIF */
-        gpio_request(GPIO_FN_MMCCLK0, NULL);
-        gpio_request(GPIO_FN_MMCD0_0, NULL);
-        gpio_request(GPIO_FN_MMCD0_1, NULL);
-        gpio_request(GPIO_FN_MMCD0_2, NULL);
-        gpio_request(GPIO_FN_MMCD0_3, NULL);
-        gpio_request(GPIO_FN_MMCD0_4, NULL);
-        gpio_request(GPIO_FN_MMCD0_5, NULL);
-        gpio_request(GPIO_FN_MMCD0_6, NULL);
-        gpio_request(GPIO_FN_MMCD0_7, NULL);
-        gpio_request(GPIO_FN_MMCCMD0, NULL);
-        gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
-
-        /* SDHI0 (microSD) */
-        gpio_request(GPIO_FN_SDHICD0_PU, NULL);
-        gpio_request(GPIO_FN_SDHICMD0_PU, NULL);
-        gpio_request(GPIO_FN_SDHICLK0, NULL);
-        gpio_request(GPIO_FN_SDHID0_3_PU, NULL);
-        gpio_request(GPIO_FN_SDHID0_2_PU, NULL);
-        gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
-        gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
-
-        /* SCIFB (BT) */
-        gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL);
-        gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL);
-        gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL);
-        gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL);
-        gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL);
-
-        /* SDHI1 (BCM4330) */
-        gpio_request(GPIO_FN_SDHICLK1, NULL);
-        gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
+        gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
 
 #ifdef CONFIG_CACHE_L2X0
         /* Early BRESP enable, Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
new file mode 100644
index 000000000000..aefa50d385b7
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -0,0 +1,107 @@
+/*
+ * KZM-A9-GT board support - Reference Device Tree Implementation
+ *
+ * Copyright (C) 2012   Horms Solutions Ltd.
+ *
+ * Based on board-kzm9g.c
+ * Copyright (C) 2012   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/input.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <mach/sh73a0.h>
+#include <mach/common.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static unsigned long pin_pullup_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map kzm_pinctrl_map[] = {
+        PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0",
+                                  "i2c3_1", "i2c3"),
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+                                  "mmc0_ctrl_0", "mmc0"),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+                                    "PORT279", pin_pullup_conf),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+                                      "mmc0_data8_0", pin_pullup_conf),
+        /* SCIFA4 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_data", "scifa4"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_ctrl", "scifa4"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
+                                  "sdhi2_data4", "sdhi2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
+                                  "sdhi2_ctrl", "sdhi2"),
+};
+
+static void __init kzm_init(void)
+{
+        sh73a0_add_standard_devices_dt();
+        pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
+        sh73a0_pinmux_init();
+
+        /* enable SD */
+        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
+        gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
+
+        gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
+
+#ifdef CONFIG_CACHE_L2X0
+        /* Early BRESP enable, Shared attribute override enable, 64K*8way */
+        l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
+#endif
+}
+
+static const char *kzm9g_boards_compat_dt[] __initdata = {
+        "renesas,kzm9g-reference",
+        NULL,
+};
+
+DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
+        .smp            = smp_ops(sh73a0_smp_ops),
+        .map_io         = sh73a0_map_io,
+        .init_early     = sh73a0_init_delay,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = irqchip_init,
+        .init_machine   = kzm_init,
+        .init_time      = shmobile_timer_init,
+        .dt_compat      = kzm9g_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 7f3a6b7e7b7c..77a66ac12417 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -30,6 +30,8 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
@@ -61,8 +63,8 @@
 
 /* Dummy supplies, where voltage doesn't matter */
 static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+        REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
 };
 
 /*
@@ -373,13 +375,64 @@ static struct platform_device mmc_device = {
         .resource       = sh_mmcif_resources,
 };
 
-/* Fixed 2.8V regulators to be used by SDHI0 and SDHI2 */
-static struct regulator_consumer_supply fixed2v8_power_consumers[] =
+/* Fixed 3.3V regulators to be used by SDHI0 */
+static struct regulator_consumer_supply vcc_sdhi0_consumers[] =
 {
         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_init_data vcc_sdhi0_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(vcc_sdhi0_consumers),
+        .consumer_supplies      = vcc_sdhi0_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi0_info = {
+        .supply_name = "SDHI0 Vcc",
+        .microvolts = 3300000,
+        .gpio = 15,
+        .enable_high = 1,
+        .init_data = &vcc_sdhi0_init_data,
+};
+
+static struct platform_device vcc_sdhi0 = {
+        .name = "reg-fixed-voltage",
+        .id   = 0,
+        .dev  = {
+                .platform_data = &vcc_sdhi0_info,
+        },
+};
+
+/* Fixed 3.3V regulators to be used by SDHI2 */
+static struct regulator_consumer_supply vcc_sdhi2_consumers[] =
+{
         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"),
+};
+
+static struct regulator_init_data vcc_sdhi2_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(vcc_sdhi2_consumers),
+        .consumer_supplies      = vcc_sdhi2_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi2_info = {
+        .supply_name = "SDHI2 Vcc",
+        .microvolts = 3300000,
+        .gpio = 14,
+        .enable_high = 1,
+        .init_data = &vcc_sdhi2_init_data,
+};
+
+static struct platform_device vcc_sdhi2 = {
+        .name = "reg-fixed-voltage",
+        .id   = 1,
+        .dev  = {
+                .platform_data = &vcc_sdhi2_info,
+        },
 };
 
 /* SDHI */
@@ -387,8 +440,8 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
-        .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -431,9 +484,8 @@ static struct sh_mobile_sdhi_info sdhi2_info = {
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT |
                           TMIO_MMC_USE_GPIO_CD |
                           TMIO_MMC_WRPROTECT_DISABLE,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
-        .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
-        .cd_gpio        = GPIO_PORT13,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD,
+        .cd_gpio        = 13,
 };
 
 static struct resource sdhi2_resources[] = {
@@ -592,6 +644,8 @@ static struct platform_device *kzm_devices[] __initdata = {
         &usbhs_device,
         &lcdc_device,
         &mmc_device,
+        &vcc_sdhi0,
+        &vcc_sdhi2,
         &sdhi0_device,
         &sdhi2_device,
         &gpio_keys_device,
@@ -599,6 +653,64 @@ static struct platform_device *kzm_devices[] __initdata = {
         &fsi_ak4648_device,
 };
 
+static unsigned long pin_pullup_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map kzm_pinctrl_map[] = {
+        /* FSIA (AK4648) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_mclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_data_out", "fsia"),
+        /* I2C3 */
+        PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
+                                  "i2c3_1", "i2c3"),
+        /* LCD */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
+                                  "lcd_data24", "lcd"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
+                                  "lcd_sync", "lcd"),
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_ctrl_0", "mmc0"),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                    "PORT279", pin_pullup_conf),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                      "mmc0_data8_0", pin_pullup_conf),
+        /* SCIFA4 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_data", "scifa4"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_ctrl", "scifa4"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
+                                  "sdhi2_data4", "sdhi2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
+                                  "sdhi2_ctrl", "sdhi2"),
+        /* SMSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+                                  "bsc_cs4", "bsc"),
+        /* USB */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0",
+                                  "usb_vbus", "usb"),
+};
+
 /*
  * FIXME
  *
@@ -654,106 +766,26 @@ device_initcall(as3711_enable_lcdc_backlight);
 
 static void __init kzm_init(void)
 {
-        regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
+        regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
                                      ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
-        regulator_register_always_on(1, "fixed-2.8V", fixed2v8_power_consumers,
-                                     ARRAY_SIZE(fixed2v8_power_consumers), 2800000);
-        regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+        regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
-        sh73a0_pinmux_init();
-
-        /* enable SCIFA4 */
-        gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
-        gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
-        gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
+        pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
 
-        /* CS4 for SMSC/USB */
-        gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
+        sh73a0_pinmux_init();
 
         /* SMSC */
-        gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */
+        gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
 
         /* LCDC */
-        gpio_request(GPIO_FN_LCDD23,    NULL);
-        gpio_request(GPIO_FN_LCDD22,    NULL);
-        gpio_request(GPIO_FN_LCDD21,    NULL);
-        gpio_request(GPIO_FN_LCDD20,    NULL);
-        gpio_request(GPIO_FN_LCDD19,    NULL);
-        gpio_request(GPIO_FN_LCDD18,    NULL);
-        gpio_request(GPIO_FN_LCDD17,    NULL);
-        gpio_request(GPIO_FN_LCDD16,    NULL);
-        gpio_request(GPIO_FN_LCDD15,    NULL);
-        gpio_request(GPIO_FN_LCDD14,    NULL);
-        gpio_request(GPIO_FN_LCDD13,    NULL);
-        gpio_request(GPIO_FN_LCDD12,    NULL);
-        gpio_request(GPIO_FN_LCDD11,    NULL);
-        gpio_request(GPIO_FN_LCDD10,    NULL);
-        gpio_request(GPIO_FN_LCDD9,     NULL);
-        gpio_request(GPIO_FN_LCDD8,     NULL);
-        gpio_request(GPIO_FN_LCDD7,     NULL);
-        gpio_request(GPIO_FN_LCDD6,     NULL);
-        gpio_request(GPIO_FN_LCDD5,     NULL);
-        gpio_request(GPIO_FN_LCDD4,     NULL);
-        gpio_request(GPIO_FN_LCDD3,     NULL);
-        gpio_request(GPIO_FN_LCDD2,     NULL);
-        gpio_request(GPIO_FN_LCDD1,     NULL);
-        gpio_request(GPIO_FN_LCDD0,     NULL);
-        gpio_request(GPIO_FN_LCDDISP,   NULL);
-        gpio_request(GPIO_FN_LCDDCK,    NULL);
-
-        gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
-        gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
+        gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
+        gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
 
         /* Touchscreen */
-        gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */
-
-        /* enable MMCIF */
-        gpio_request(GPIO_FN_MMCCLK0,           NULL);
-        gpio_request(GPIO_FN_MMCCMD0_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_0_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_1_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_2_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_3_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_4_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_5_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_6_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_7_PU,        NULL);
+        gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
 
         /* enable SD */
-        gpio_request(GPIO_FN_SDHIWP0,           NULL);
-        gpio_request(GPIO_FN_SDHICD0,           NULL);
-        gpio_request(GPIO_FN_SDHICMD0,          NULL);
-        gpio_request(GPIO_FN_SDHICLK0,          NULL);
-        gpio_request(GPIO_FN_SDHID0_3,          NULL);
-        gpio_request(GPIO_FN_SDHID0_2,          NULL);
-        gpio_request(GPIO_FN_SDHID0_1,          NULL);
-        gpio_request(GPIO_FN_SDHID0_0,          NULL);
         gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
-        gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-
-        /* enable Micro SD */
-        gpio_request(GPIO_FN_SDHID2_0,          NULL);
-        gpio_request(GPIO_FN_SDHID2_1,          NULL);
-        gpio_request(GPIO_FN_SDHID2_2,          NULL);
-        gpio_request(GPIO_FN_SDHID2_3,          NULL);
-        gpio_request(GPIO_FN_SDHICMD2,          NULL);
-        gpio_request(GPIO_FN_SDHICLK2,          NULL);
-        gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-
-        /* I2C 3 */
-        gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
-        gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
-
-        /* enable FSI2 port A (ak4648) */
-        gpio_request(GPIO_FN_FSIACK,    NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
-
-        /* enable USB */
-        gpio_request(GPIO_FN_VBUS_0,    NULL);
 
 #ifdef CONFIG_CACHE_L2X0
         /* Early BRESP enable, Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index db968a585ff0..1a9c75383ca0 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -40,6 +40,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/sh_flctl.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pm_clock.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
@@ -363,7 +364,7 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
 
 static int mackerel_set_brightness(int brightness)
 {
-        gpio_set_value(GPIO_PORT31, brightness);
+        gpio_set_value(31, brightness);
 
         return 0;
 }
@@ -819,22 +820,22 @@ static struct platform_device usbhs1_device = {
 static struct gpio_led mackerel_leds[] = {
         {
                 .name           = "led0",
-                .gpio           = GPIO_PORT0,
+                .gpio           = 0,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name           = "led1",
-                .gpio           = GPIO_PORT1,
+                .gpio           = 1,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name           = "led2",
-                .gpio           = GPIO_PORT2,
+                .gpio           = 2,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name           = "led3",
-                .gpio           = GPIO_PORT159,
+                .gpio           = 159,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }
 };
@@ -964,11 +965,11 @@ static struct platform_device nand_flash_device = {
 
 /*
  * The card detect pin of the top SD/MMC slot (CN7) is active low and is
- * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ * connected to GPIO A22 of SH7372 (GPIO 41).
  */
 static int slot_cn7_get_cd(struct platform_device *pdev)
 {
-        return !gpio_get_value(GPIO_PORT41);
+        return !gpio_get_value(41);
 }
 
 /* SDHI0 */
@@ -977,7 +978,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
         .tmio_flags     = TMIO_MMC_USE_GPIO_CD,
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
-        .cd_gpio        = GPIO_PORT172,
+        .cd_gpio        = 172,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -1060,11 +1061,11 @@ static struct platform_device sdhi1_device = {
 
 /*
  * The card detect pin of the top SD/MMC slot (CN23) is active low and is
- * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162).
+ * connected to GPIO SCIFB_SCK of SH7372 (162).
  */
 static int slot_cn23_get_cd(struct platform_device *pdev)
 {
-        return !gpio_get_value(GPIO_PORT162);
+        return !gpio_get_value(162);
 }
 
 /* SDHI2 */
@@ -1142,7 +1143,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
         .slave_id_rx    = SHDMA_SLAVE_MMCIF_RX,
 };
 
-static struct platform_device sh_mmcif_device = {
+static struct platform_device sh_mmcif_device __maybe_unused = {
         .name           = "sh_mmcif",
         .id             = 0,
         .dev            = {
@@ -1328,6 +1329,33 @@ static struct i2c_board_info i2c1_devices[] = {
         },
 };
 
+static const struct pinctrl_map mackerel_pinctrl_map[] = {
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+                                  "mmc0_ctrl_0", "mmc0"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI1 */
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+                                  "sdhi1_ctrl", "sdhi1"),
+#endif
+        /* SDHI2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
+                                  "sdhi2_data4", "sdhi2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
+                                  "sdhi2_ctrl", "sdhi2"),
+};
+
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
 #define GPIO_PORT10CR   IOMEM(0xE605100A)
 #define GPIO_PORT167CR  IOMEM(0xE60520A7)
@@ -1364,6 +1392,8 @@ static void __init mackerel_init(void)
         /* External clock source */
         clk_set_rate(&sh7372_dv_clki_clk, 27000000);
 
+        pinctrl_register_mappings(mackerel_pinctrl_map,
+                                  ARRAY_SIZE(mackerel_pinctrl_map));
         sh7372_pinmux_init();
 
         /* enable SCIFA0 */
@@ -1403,9 +1433,9 @@ static void __init mackerel_init(void)
         gpio_request(GPIO_FN_LCDDCK,   NULL);
 
         /* backlight, off by default */
-        gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL);
+        gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
 
-        gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+        gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
         /* USBHS0 */
         gpio_request(GPIO_FN_VBUS0_0, NULL);
@@ -1421,10 +1451,10 @@ static void __init mackerel_init(void)
         gpio_request(GPIO_FN_FSIAILR,   NULL);
         gpio_request(GPIO_FN_FSIAISLD,  NULL);
         gpio_request(GPIO_FN_FSIAOSLD,  NULL);
-        gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
+        gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
-        gpio_request(GPIO_PORT9,  NULL);
-        gpio_request(GPIO_PORT10, NULL);
+        gpio_request(9,  NULL);
+        gpio_request(10, NULL);
         gpio_direction_none(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
         gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
 
@@ -1453,52 +1483,14 @@ static void __init mackerel_init(void)
         gpio_request(GPIO_FN_IRQ21,     NULL);
         irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
 
-        /* enable SDHI0 */
-        gpio_request(GPIO_FN_SDHIWP0, NULL);
-        gpio_request(GPIO_FN_SDHICMD0, NULL);
-        gpio_request(GPIO_FN_SDHICLK0, NULL);
-        gpio_request(GPIO_FN_SDHID0_3, NULL);
-        gpio_request(GPIO_FN_SDHID0_2, NULL);
-        gpio_request(GPIO_FN_SDHID0_1, NULL);
-        gpio_request(GPIO_FN_SDHID0_0, NULL);
-
         /* SDHI0 PORT172 card-detect IRQ26 */
         gpio_request(GPIO_FN_IRQ26_172, NULL);
 
-#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
-        /* enable SDHI1 */
-        gpio_request(GPIO_FN_SDHICMD1, NULL);
-        gpio_request(GPIO_FN_SDHICLK1, NULL);
-        gpio_request(GPIO_FN_SDHID1_3, NULL);
-        gpio_request(GPIO_FN_SDHID1_2, NULL);
-        gpio_request(GPIO_FN_SDHID1_1, NULL);
-        gpio_request(GPIO_FN_SDHID1_0, NULL);
-#endif
         /* card detect pin for MMC slot (CN7) */
-        gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
-
-        /* enable SDHI2 */
-        gpio_request(GPIO_FN_SDHICMD2, NULL);
-        gpio_request(GPIO_FN_SDHICLK2, NULL);
-        gpio_request(GPIO_FN_SDHID2_3, NULL);
-        gpio_request(GPIO_FN_SDHID2_2, NULL);
-        gpio_request(GPIO_FN_SDHID2_1, NULL);
-        gpio_request(GPIO_FN_SDHID2_0, NULL);
+        gpio_request_one(41, GPIOF_IN, NULL);
 
         /* card detect pin for microSD slot (CN23) */
-        gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL);
-
-        /* MMCIF */
-        gpio_request(GPIO_FN_MMCD0_0, NULL);
-        gpio_request(GPIO_FN_MMCD0_1, NULL);
-        gpio_request(GPIO_FN_MMCD0_2, NULL);
-        gpio_request(GPIO_FN_MMCD0_3, NULL);
-        gpio_request(GPIO_FN_MMCD0_4, NULL);
-        gpio_request(GPIO_FN_MMCD0_5, NULL);
-        gpio_request(GPIO_FN_MMCD0_6, NULL);
-        gpio_request(GPIO_FN_MMCD0_7, NULL);
-        gpio_request(GPIO_FN_MMCCMD0, NULL);
-        gpio_request(GPIO_FN_MMCCLK0, NULL);
+        gpio_request_one(162, GPIOF_IN, NULL);
 
         /* FLCTL */
         gpio_request(GPIO_FN_D0_NAF0, NULL);
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
new file mode 100644
index 000000000000..480d882e42c7
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -0,0 +1,75 @@
+/*
+ * marzen board support - Reference DT implementation
+ *
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ * Copyright (C) 2013  Simon Horman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/pinctrl/machine.h>
+#include <mach/r8a7779.h>
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+
+static const struct pinctrl_map marzen_pinctrl_map[] = {
+        /* SCIF2 (CN18: DEBUG0) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
+                                  "scif2_data_c", "scif2"),
+        /* SCIF4 (CN19: DEBUG1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
+                                  "scif4_data", "scif4"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SMSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+                                  "intc_irq1_b", "intc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+                                  "lbsc_ex_cs0", "lbsc"),
+};
+
+static void __init marzen_init(void)
+{
+        pinctrl_register_mappings(marzen_pinctrl_map,
+                                  ARRAY_SIZE(marzen_pinctrl_map));
+        r8a7779_pinmux_init();
+
+        r8a7779_add_standard_devices_dt();
+}
+
+static const char *marzen_boards_compat_dt[] __initdata = {
+        "renesas,marzen-reference",
+        NULL,
+};
+
+DT_MACHINE_START(MARZEN, "marzen")
+        .smp            = smp_ops(r8a7779_smp_ops),
+        .map_io         = r8a7779_map_io,
+        .init_early     = r8a7779_init_delay,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = r8a7779_init_irq_dt,
+        .init_machine   = marzen_init,
+        .init_time      = shmobile_timer_init,
+        .dt_compat      = marzen_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index fec49ebc359a..2333a2d7c937 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -25,8 +25,8 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/gpio.h>
 #include <linux/dma-mapping.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -67,7 +67,7 @@ static struct resource smsc911x_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
-                .start          = gic_spi(28), /* IRQ 1 */
+                .start          = gic_iid(0x3c), /* IRQ 1 */
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -97,7 +97,7 @@ static struct resource sdhi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(104),
+                .start  = gic_iid(0x88),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -215,7 +215,7 @@ static struct resource ehci0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(44),
+                .start  = gic_iid(0x4c),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -239,7 +239,7 @@ static struct resource ehci1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(45),
+                .start  = gic_iid(0x4d),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -269,7 +269,7 @@ static struct resource ohci0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(44),
+                .start  = gic_iid(0x4c),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -293,7 +293,7 @@ static struct resource ohci1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(45),
+                .start  = gic_iid(0x4d),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -327,6 +327,41 @@ void __init marzen_init_late(void)
                              ARRAY_SIZE(marzen_late_devices));
 }
 
+static const struct pinctrl_map marzen_pinctrl_map[] = {
+        /* HSPI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
+                                  "hspi0", "hspi0"),
+        /* SCIF2 (CN18: DEBUG0) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
+                                  "scif2_data_c", "scif2"),
+        /* SCIF4 (CN19: DEBUG1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
+                                  "scif4_data", "scif4"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SMSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+                                  "intc_irq1_b", "intc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+                                  "lbsc_ex_cs0", "lbsc"),
+        /* USB0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
+                                  "usb0", "usb0"),
+        /* USB1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
+                                  "usb1", "usb1"),
+        /* USB2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
+                                  "usb2", "usb2"),
+};
+
 static void __init marzen_init(void)
 {
         regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -334,44 +369,10 @@ static void __init marzen_init(void)
         regulator_register_fixed(1, dummy_supplies,
                                 ARRAY_SIZE(dummy_supplies));
 
+        pinctrl_register_mappings(marzen_pinctrl_map,
+                                  ARRAY_SIZE(marzen_pinctrl_map));
         r8a7779_pinmux_init();
 
-        /* SCIF2 (CN18: DEBUG0) */
-        gpio_request(GPIO_FN_TX2_C, NULL);
-        gpio_request(GPIO_FN_RX2_C, NULL);
-
-        /* SCIF4 (CN19: DEBUG1) */
-        gpio_request(GPIO_FN_TX4, NULL);
-        gpio_request(GPIO_FN_RX4, NULL);
-
-        /* LAN89218 */
-        gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
-        gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
-
-        /* SD0 (CN20) */
-        gpio_request(GPIO_FN_SD0_CLK, NULL);
-        gpio_request(GPIO_FN_SD0_CMD, NULL);
-        gpio_request(GPIO_FN_SD0_DAT0, NULL);
-        gpio_request(GPIO_FN_SD0_DAT1, NULL);
-        gpio_request(GPIO_FN_SD0_DAT2, NULL);
-        gpio_request(GPIO_FN_SD0_DAT3, NULL);
-        gpio_request(GPIO_FN_SD0_CD, NULL);
-        gpio_request(GPIO_FN_SD0_WP, NULL);
-
-        /* HSPI 0 */
-        gpio_request(GPIO_FN_HSPI_CLK0, NULL);
-        gpio_request(GPIO_FN_HSPI_CS0,  NULL);
-        gpio_request(GPIO_FN_HSPI_TX0,  NULL);
-        gpio_request(GPIO_FN_HSPI_RX0,  NULL);
-
-        /* USB (CN21) */
-        gpio_request(GPIO_FN_USB_OVC0, NULL);
-        gpio_request(GPIO_FN_USB_OVC1, NULL);
-        gpio_request(GPIO_FN_USB_OVC2, NULL);
-
-        /* USB (CN22) */
-        gpio_request(GPIO_FN_USB_PENC2, NULL);
-
         r8a7779_add_standard_devices();
         platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 19ce885a3b43..1feb9a2286a8 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -593,29 +593,42 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_ceu.1",        &mstp_clks[MSTP128]),
 
         CLKDEV_DEV_ID("sh-sci.4",               &mstp_clks[MSTP200]),
+        CLKDEV_DEV_ID("e6c80000.sci",           &mstp_clks[MSTP200]),
         CLKDEV_DEV_ID("sh-sci.3",               &mstp_clks[MSTP201]),
+        CLKDEV_DEV_ID("e6c70000.sci",           &mstp_clks[MSTP201]),
         CLKDEV_DEV_ID("sh-sci.2",               &mstp_clks[MSTP202]),
+        CLKDEV_DEV_ID("e6c60000.sci",           &mstp_clks[MSTP202]),
         CLKDEV_DEV_ID("sh-sci.1",               &mstp_clks[MSTP203]),
+        CLKDEV_DEV_ID("e6c50000.sci",           &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.0",               &mstp_clks[MSTP204]),
+        CLKDEV_DEV_ID("e6c40000.sci",           &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.8",               &mstp_clks[MSTP206]),
+        CLKDEV_DEV_ID("e6c30000.sci",           &mstp_clks[MSTP206]),
         CLKDEV_DEV_ID("sh-sci.5",               &mstp_clks[MSTP207]),
+        CLKDEV_DEV_ID("e6cb0000.sci",           &mstp_clks[MSTP207]),
         CLKDEV_DEV_ID("sh-dma-engine.3",        &mstp_clks[MSTP214]),
         CLKDEV_DEV_ID("sh-dma-engine.2",        &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-dma-engine.1",        &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("sh-dma-engine.0",        &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("sh-sci.7",               &mstp_clks[MSTP222]),
+        CLKDEV_DEV_ID("e6cd0000.sci",           &mstp_clks[MSTP222]),
         CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
+        CLKDEV_DEV_ID("e6cc0000.sci",           &mstp_clks[MSTP230]),
 
         CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1",       &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("e6860000.sdhi",          &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
+        CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
 
         /* ICK */
         CLKDEV_ICK_ID("host",   "renesas_usbhs",        &mstp_clks[MSTP416]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1db36537255c..d9edeaf66007 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,7 +87,8 @@ static struct clk div4_clks[DIV4_NR] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP101, MSTP100,
+        MSTP115,
+        MSTP103, MSTP101, MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015, MSTP014,
@@ -99,6 +100,8 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */
+        [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1,  3, 0), /* DU */
         [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */
         [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  0, 0), /* USB0/1 */
         [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
@@ -156,6 +159,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
+        CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
         CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
         CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
         CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
@@ -180,6 +185,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
+        CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */
 };
 
 void __init r8a7779_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index afa5423a0f93..71843dd39e16 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -265,12 +265,12 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
-        [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
+        [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
         [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
         [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
         [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
-        [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
+        [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
         [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
         [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
         [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
@@ -581,10 +581,13 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
         CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
+        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
         CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
         CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
         CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-scu.S
index bec4c0d9b713..7d113f898e7f 100644
--- a/arch/arm/mach-shmobile/headsmp-sh73a0.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -1,5 +1,5 @@
 /*
- * SMP support for SoC sh73a0
+ * Shared SCU setup for mach-shmobile
  *
  * Copyright (C) 2012 Bastian Hecht
  *
@@ -35,11 +35,12 @@
  * the physical address as the MMU is still turned off.
  */
         .align  12
-ENTRY(sh73a0_secondary_vector)
+ENTRY(shmobile_secondary_vector_scu)
         mrc     p15, 0, r0, c0, c0, 5   @ read MIPDR
         and     r0, r0, #3              @ mask out cpu ID
         lsl     r0, r0, #3              @ we will shift by cpu_id * 8 bits
-        mov     r1, #0xf0000000         @ SCU base address
+        ldr     r1, 2f
+        ldr     r1, [r1]                @ SCU base address
         ldr     r2, [r1, #8]            @ SCU Power Status Register
         mov     r3, #3
         bic     r2, r2, r3, lsl r0      @ Clear bits of our CPU (Run Mode)
@@ -47,4 +48,10 @@ ENTRY(sh73a0_secondary_vector)
 
         ldr     pc, 1f
 1:      .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(sh73a0_secondary_vector)
+2:      .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
+ENDPROC(shmobile_secondary_vector_scu)
+
+        .text
+        .globl  shmobile_scu_base
+shmobile_scu_base:
+        .space  4
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
deleted file mode 100644
index a1524e3367b0..000000000000
--- a/arch/arm/mach-shmobile/hotplug.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * SMP support for R-Mobile / SH-Mobile
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/cpumask.h>
-#include <linux/delay.h>
-#include <linux/of.h>
-#include <mach/common.h>
-#include <mach/r8a7779.h>
-#include <mach/emev2.h>
-#include <asm/cacheflush.h>
-#include <asm/mach-types.h>
-
-static cpumask_t dead_cpus;
-
-void shmobile_cpu_die(unsigned int cpu)
-{
-        /* hardware shutdown code running on the CPU that is being offlined */
-        flush_cache_all();
-        dsb();
-
-        /* notify platform_cpu_kill() that hardware shutdown is finished */
-        cpumask_set_cpu(cpu, &dead_cpus);
-
-        /* wait for SoC code in platform_cpu_kill() to shut off CPU core
-         * power. CPU bring up starts from the reset vector.
-         */
-        while (1) {
-                /*
-                 * here's the WFI
-                 */
-                asm(".word      0xe320f003\n"
-                    :
-                    :
-                    : "memory", "cc");
-        }
-}
-
-int shmobile_cpu_disable(unsigned int cpu)
-{
-        cpumask_clear_cpu(cpu, &dead_cpus);
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
-
-int shmobile_cpu_disable_any(unsigned int cpu)
-{
-        cpumask_clear_cpu(cpu, &dead_cpus);
-        return 0;
-}
-
-int shmobile_cpu_is_dead(unsigned int cpu)
-{
-        return cpumask_test_cpu(cpu, &dead_cpus);
-}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index e48606d8a2be..86fcdf9fde1b 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -8,6 +8,7 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
+extern void shmobile_secondary_vector_scu(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
@@ -33,23 +34,23 @@ extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
 extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
+extern void sh73a0_init_delay(void);
 extern void sh73a0_init_irq(void);
 extern void sh73a0_init_irq_dt(void);
 extern void sh73a0_map_io(void);
 extern void sh73a0_earlytimer_init(void);
 extern void sh73a0_add_early_devices(void);
-extern void sh73a0_add_early_devices_dt(void);
 extern void sh73a0_add_standard_devices(void);
 extern void sh73a0_add_standard_devices_dt(void);
 extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
 extern void sh73a0_pm_init(void);
-extern void sh73a0_secondary_vector(void);
 extern struct clk sh73a0_extal1_clk;
 extern struct clk sh73a0_extal2_clk;
 extern struct clk sh73a0_extcki_clk;
 extern struct clk sh73a0_extalr_clk;
 
+extern void r8a7740_meram_workaround(void);
 extern void r8a7740_init_irq(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
@@ -58,16 +59,17 @@ extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
 
+extern void r8a7779_init_delay(void);
 extern void r8a7779_init_irq(void);
+extern void r8a7779_init_irq_dt(void);
 extern void r8a7779_map_io(void);
 extern void r8a7779_earlytimer_init(void);
 extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
+extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
-extern void r8a7740_meram_workaround(void);
-
 extern void r8a7779_register_twd(void);
 
 #ifdef CONFIG_SUSPEND
@@ -82,16 +84,7 @@ int shmobile_cpuidle_init(void);
 static inline int shmobile_cpuidle_init(void) { return 0; }
 #endif
 
-extern void shmobile_cpu_die(unsigned int cpu);
-extern int shmobile_cpu_disable(unsigned int cpu);
-extern int shmobile_cpu_disable_any(unsigned int cpu);
-
-#ifdef CONFIG_HOTPLUG_CPU
-extern int shmobile_cpu_is_dead(unsigned int cpu);
-#else
-static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
-#endif
-
+extern void __iomem *shmobile_scu_base;
 extern void shmobile_smp_init_cpus(unsigned int ncores);
 
 static inline void __init shmobile_init_late(void)
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 06a5da3c3050..992ed213cec1 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -5,6 +5,7 @@
 
 /* GIC */
 #define gic_spi(nr)             ((nr) + 32)
+#define gic_iid(nr)             (nr) /* ICCIAR / interrupt ID */
 
 /* INTCS */
 #define INTCS_VECT_BASE         0x3400
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 59d252f4cf97..c2583610ad36 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -241,48 +241,9 @@ enum {
 
         /* LCD0 */
         GPIO_FN_LCDC0_SELECT,
-        GPIO_FN_LCD0_D0,        GPIO_FN_LCD0_D1,        GPIO_FN_LCD0_D2,
-        GPIO_FN_LCD0_D3,        GPIO_FN_LCD0_D4,        GPIO_FN_LCD0_D5,
-        GPIO_FN_LCD0_D6,        GPIO_FN_LCD0_D7,        GPIO_FN_LCD0_D8,
-        GPIO_FN_LCD0_D9,        GPIO_FN_LCD0_D10,       GPIO_FN_LCD0_D11,
-        GPIO_FN_LCD0_D12,       GPIO_FN_LCD0_D13,       GPIO_FN_LCD0_D14,
-        GPIO_FN_LCD0_D15,       GPIO_FN_LCD0_D16,       GPIO_FN_LCD0_D17,
-        GPIO_FN_LCD0_DON,       GPIO_FN_LCD0_VCPWC,     GPIO_FN_LCD0_VEPWC,
-
-        GPIO_FN_LCD0_DCK,       GPIO_FN_LCD0_VSYN, /* for RGB */
-        GPIO_FN_LCD0_HSYN,      GPIO_FN_LCD0_DISP, /* for RGB */
-
-        GPIO_FN_LCD0_WR,        GPIO_FN_LCD0_RD, /* for SYS */
-        GPIO_FN_LCD0_CS,        GPIO_FN_LCD0_RS, /* for SYS */
-
-        GPIO_FN_LCD0_D18_PORT163,       GPIO_FN_LCD0_D19_PORT162,
-        GPIO_FN_LCD0_D20_PORT161,       GPIO_FN_LCD0_D21_PORT158,
-        GPIO_FN_LCD0_D22_PORT160,       GPIO_FN_LCD0_D23_PORT159,
-        GPIO_FN_LCD0_LCLK_PORT165,       /* MSEL5CR_6_1 */
-
-        GPIO_FN_LCD0_D18_PORT40,        GPIO_FN_LCD0_D19_PORT4,
-        GPIO_FN_LCD0_D20_PORT3,         GPIO_FN_LCD0_D21_PORT2,
-        GPIO_FN_LCD0_D22_PORT0,         GPIO_FN_LCD0_D23_PORT1,
-        GPIO_FN_LCD0_LCLK_PORT102,      /* MSEL5CR_6_0 */
 
         /* LCD1 */
         GPIO_FN_LCDC1_SELECT,
-        GPIO_FN_LCD1_D0,        GPIO_FN_LCD1_D1,        GPIO_FN_LCD1_D2,
-        GPIO_FN_LCD1_D3,        GPIO_FN_LCD1_D4,        GPIO_FN_LCD1_D5,
-        GPIO_FN_LCD1_D6,        GPIO_FN_LCD1_D7,        GPIO_FN_LCD1_D8,
-        GPIO_FN_LCD1_D9,        GPIO_FN_LCD1_D10,       GPIO_FN_LCD1_D11,
-        GPIO_FN_LCD1_D12,       GPIO_FN_LCD1_D13,       GPIO_FN_LCD1_D14,
-        GPIO_FN_LCD1_D15,       GPIO_FN_LCD1_D16,       GPIO_FN_LCD1_D17,
-        GPIO_FN_LCD1_D18,       GPIO_FN_LCD1_D19,       GPIO_FN_LCD1_D20,
-        GPIO_FN_LCD1_D21,       GPIO_FN_LCD1_D22,       GPIO_FN_LCD1_D23,
-        GPIO_FN_LCD1_DON,       GPIO_FN_LCD1_VCPWC,
-        GPIO_FN_LCD1_LCLK,      GPIO_FN_LCD1_VEPWC,
-
-        GPIO_FN_LCD1_DCK,       GPIO_FN_LCD1_VSYN, /* for RGB */
-        GPIO_FN_LCD1_HSYN,      GPIO_FN_LCD1_DISP, /* for RGB */
-
-        GPIO_FN_LCD1_WR,        GPIO_FN_LCD1_RD, /* for SYS */
-        GPIO_FN_LCD1_CS,        GPIO_FN_LCD1_RS, /* for SYS */
 
         /* RSPI */
         GPIO_FN_RSPI_SSL0_A,    GPIO_FN_RSPI_SSL1_A,
@@ -346,26 +307,6 @@ enum {
         GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
         GPIO_FN_SIM_D_PORT199,
 
-        /* SDHI0 */
-        GPIO_FN_SDHI0_D0,       GPIO_FN_SDHI0_D1,       GPIO_FN_SDHI0_D2,
-        GPIO_FN_SDHI0_D3,       GPIO_FN_SDHI0_CD,       GPIO_FN_SDHI0_WP,
-        GPIO_FN_SDHI0_CMD,      GPIO_FN_SDHI0_CLK,
-
-        /* SDHI1 */
-        GPIO_FN_SDHI1_D0,       GPIO_FN_SDHI1_D1,       GPIO_FN_SDHI1_D2,
-        GPIO_FN_SDHI1_D3,       GPIO_FN_SDHI1_CD,       GPIO_FN_SDHI1_WP,
-        GPIO_FN_SDHI1_CMD,      GPIO_FN_SDHI1_CLK,
-
-        /* SDHI2 */
-        GPIO_FN_SDHI2_D0,       GPIO_FN_SDHI2_D1,       GPIO_FN_SDHI2_D2,
-        GPIO_FN_SDHI2_D3,       GPIO_FN_SDHI2_CLK,      GPIO_FN_SDHI2_CMD,
-
-        GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
-        GPIO_FN_SDHI2_WP_PORT25,
-
-        GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
-        GPIO_FN_SDHI2_CD_PORT202,
-
         /* MSIOF2 */
         GPIO_FN_MSIOF2_TXD,     GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TSCK,
         GPIO_FN_MSIOF2_SS2,     GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_SS1,
@@ -417,21 +358,6 @@ enum {
         GPIO_FN_MEMC_DREQ1,
         GPIO_FN_MEMC_A0,
 
-        /* MMC */
-        GPIO_FN_MMC0_D0_PORT68,         GPIO_FN_MMC0_D1_PORT69,
-        GPIO_FN_MMC0_D2_PORT70,         GPIO_FN_MMC0_D3_PORT71,
-        GPIO_FN_MMC0_D4_PORT72,         GPIO_FN_MMC0_D5_PORT73,
-        GPIO_FN_MMC0_D6_PORT74,         GPIO_FN_MMC0_D7_PORT75,
-        GPIO_FN_MMC0_CLK_PORT66,
-        GPIO_FN_MMC0_CMD_PORT67,        /* MSEL4CR_15_0 */
-
-        GPIO_FN_MMC1_D0_PORT149,        GPIO_FN_MMC1_D1_PORT148,
-        GPIO_FN_MMC1_D2_PORT147,        GPIO_FN_MMC1_D3_PORT146,
-        GPIO_FN_MMC1_D4_PORT145,        GPIO_FN_MMC1_D5_PORT144,
-        GPIO_FN_MMC1_D6_PORT143,        GPIO_FN_MMC1_D7_PORT142,
-        GPIO_FN_MMC1_CLK_PORT103,
-        GPIO_FN_MMC1_CMD_PORT104,       /* MSEL4CR_15_1 */
-
         /* MSIOF0 */
         GPIO_FN_MSIOF0_SS1,     GPIO_FN_MSIOF0_SS2,
         GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_TXD,
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 8ab0cd6ad6b0..8ea0ad18cdff 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -71,128 +71,125 @@ enum {
         GPIO_FN_A19,
 
         /* IPSR0 */
-        GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
-        GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
-        GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
-        GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
-        GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
-        GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
-        GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
-        GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
-        GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
-        GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
-        GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
-        GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
-        GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
-        GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
+        GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+        GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS,
+        GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
+        GPIO_FN_HCTS1, GPIO_FN_A0,
+        GPIO_FN_FD3, GPIO_FN_A20,
+        GPIO_FN_A21,
+        GPIO_FN_A22, GPIO_FN_VI1_R0,
+        GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_VI1_R1,
+        GPIO_FN_A24, GPIO_FN_FD4,
+        GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
+        GPIO_FN_FD5,
+        GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B,
+        GPIO_FN_CLKOUT, GPIO_FN_PWM0_B,
         GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
-        GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
+        GPIO_FN_VI1_R7, GPIO_FN_HRTS1,
 
         /* IPSR1 */
-        GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
-        GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
-        GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
-        GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
-        GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
-        GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
-        GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
-        GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
-        GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
-        GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
-        GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
-        GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
-        GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
-        GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
-        GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
+        GPIO_FN_FD6, GPIO_FN_FD7,
+        GPIO_FN_FALE,
+        GPIO_FN_ATACS00,
+        GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4,
+        GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B,
+        GPIO_FN_SSI_SDATA9,
+        GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5,
+        GPIO_FN_HTX1, GPIO_FN_SSI_SCK9,
+        GPIO_FN_FD1,
+        GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1,
+        GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
+        GPIO_FN_MLB_SIG, GPIO_FN_PWM3,
+        GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_HTX0,
+        GPIO_FN_SDATA, GPIO_FN_SUB_TCK,
         GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
         GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
 
         /* IPSR2 */
-        GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
+        GPIO_FN_HRX0, GPIO_FN_SCKZ,
         GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
         GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
-        GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
-        GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
+        GPIO_FN_HSCK0, GPIO_FN_MTS, GPIO_FN_PWM5,
+        GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
         GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
-        GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
-        GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
+        GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0,
+        GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_SCIF_CLK_C,
         GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
-        GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
+        GPIO_FN_MDATA, GPIO_FN_SUB_TMS,
         GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
-        GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
+        GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33,
         GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
-        GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
-        GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
-        GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
-        GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
-        GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
-        GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
+        GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
+        GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1,
+        GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3,
+        GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5,
+        GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7,
+        GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
         GPIO_FN_AUDATA2,
 
         /* IPSR3 */
-        GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
-        GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
-        GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
-        GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
-        GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
-        GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
+        GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
+        GPIO_FN_AUDATA3, GPIO_FN_LCDOUT10,
+        GPIO_FN_LCDOUT11, GPIO_FN_LCDOUT12,
+        GPIO_FN_LCDOUT13, GPIO_FN_LCDOUT14,
+        GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
+        GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4,
         GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
-        GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
-        GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
-        GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
-        GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
-        GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
-        GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
-        GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
+        GPIO_FN_AUDATA5, GPIO_FN_LCDOUT18,
+        GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20,
+        GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22,
+        GPIO_FN_LCDOUT23,
+        GPIO_FN_QSTVA_QVS, GPIO_FN_SCL3_B,
+        GPIO_FN_QCLK,
+        GPIO_FN_QSTVB_QVE, GPIO_FN_SDA3_B,
         GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
-        GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
-        GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
-        GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
-        GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
+        GPIO_FN_QSTH_QHS,
+        GPIO_FN_QSTB_QHE,
+        GPIO_FN_QCPV_QDE,
+        GPIO_FN_CAN1_TX, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
 
         /* IPSR4 */
-        GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
-        GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
-        GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
-        GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
-        GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
-        GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
-        GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
-        GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
-        GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
-        GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
-        GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
-        GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
-        GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
-        GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
-        GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
-        GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
-        GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
-        GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
-        GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
+        GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C,
+        GPIO_FN_QPOLB, GPIO_FN_CAN1_RX,
+        GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B,
+        GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6,
+        GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
+        GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
+        GPIO_FN_AUDSYNC,
+        GPIO_FN_VI2_G0,
+        GPIO_FN_VI2_G1, GPIO_FN_VI2_G2,
+        GPIO_FN_VI2_G3, GPIO_FN_VI2_G4,
+        GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2,
+        GPIO_FN_SCL1_B, GPIO_FN_AUDATA6,
+        GPIO_FN_VI2_DATA3_VI2_B3,
+        GPIO_FN_SDA1_B, GPIO_FN_AUDATA7,
+        GPIO_FN_VI2_G6,
+        GPIO_FN_VI2_G7, GPIO_FN_VI2_R0,
+        GPIO_FN_VI2_R1, GPIO_FN_VI2_R2,
+        GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4,
+        GPIO_FN_SCL2_B,
 
         /* IPSR5 */
-        GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
-        GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
-        GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
-        GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
-        GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
-        GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
-        GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
-        GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
-        GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
-        GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
-        GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
-        GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
-        GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
-        GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
-        GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
-        GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
-        GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
-        GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
-        GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
+        GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
+        GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
+        GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
+        GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
+        GPIO_FN_VI2_CLKENB,
+        GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD,
+        GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
+        GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
+        GPIO_FN_VI3_VSYNC,
+        GPIO_FN_VI2_CLK,
+        GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
+        GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN,
+        GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
+        GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B,
+        GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
+        GPIO_FN_VI2_DATA7_VI2_B7,
+        GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
+        GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C,
         GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
-        GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
+        GPIO_FN_AUDIO_CLKB, GPIO_FN_CAN_DEBUGOUT0,
         GPIO_FN_MOUT0,
 
         /* IPSR6 */
@@ -208,85 +205,84 @@ enum {
         GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
         GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
         GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
-        GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
-        GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
-        GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
+        GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
+        GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
+        GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12,
         GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
 
         /* IPSR7 */
         GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
         GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
-        GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
-        GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
-        GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
-        GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
-        GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
-        GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
-        GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
-        GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
-        GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
-        GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
-        GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
-        GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
-        GPIO_FN_DREQ2,  GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
-        GPIO_FN_CTS1_B,
+        GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13,
+        GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78,
+        GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_WS9_B,
+        GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
+        GPIO_FN_TCLK1_C,
+        GPIO_FN_SSI_SDATA8, GPIO_FN_VSP,
+        GPIO_FN_ATACS01,
+        GPIO_FN_ATACS11, GPIO_FN_CC5_TDO,
+        GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST,
+        GPIO_FN_ATAG1, GPIO_FN_CC5_TMS,
+        GPIO_FN_ATARD1, GPIO_FN_CC5_TCK,
+        GPIO_FN_ATAWR1, GPIO_FN_CC5_TDI,
+        GPIO_FN_DREQ2,  GPIO_FN_DACK2,
 
         /* IPSR8 */
-        GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
+        GPIO_FN_AD_CLK,
         GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
-        GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
-        GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
+        GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36,
+        GPIO_FN_AD_DI,
         GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
-        GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
-        GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
+        GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37,
+        GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
         GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
-        GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
-        GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
+        GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38,
+        GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
         GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
         GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
         GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
-        GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
-        GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
+        GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB,
+        GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD,
         GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
-        GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
+        GPIO_FN_HSCK1_B,
         GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
-        GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
+        GPIO_FN_PWMFSW0_C,
 
         /* IPSR9 */
         GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
         GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
-        GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
-        GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
-        GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
-        GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
-        GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
-        GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
-        GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
+        GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_VI0_DATA3_VI0_B3,
+        GPIO_FN_VI0_DATA4_VI0_B4,
+        GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6,
+        GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
+        GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
+        GPIO_FN_SSI_SCK78_C, GPIO_FN_ARM_TRACEDATA_2,
+        GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C,
         GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
-        GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
-        GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
+        GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
+        GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV,
         GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
-        GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
-        GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
+        GPIO_FN_ETH_TX_EN, GPIO_FN_ARM_TRACEDATA_6,
+        GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER,
         GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
-        GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
-        GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
+        GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
+        GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9,
 
         /* IPSR10 */
-        GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
+        GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_DREQ1_B,
         GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
         GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
         GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
-        GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
-        GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
+        GPIO_FN_ARM_TRACEDATA_12,
+        GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC,
         GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
-        GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
+        GPIO_FN_ARM_TRACEDATA_14,
         GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
-        GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
+        GPIO_FN_ARM_TRACEDATA_15,
         GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
-        GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
+        GPIO_FN_DREQ2_C, GPIO_FN_TRACECLK,
         GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
-        GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
+        GPIO_FN_DACK2_C, GPIO_FN_SCIF_CLK_D,
         GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
         GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
         GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
@@ -294,35 +290,35 @@ enum {
         GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
 
         /* IPSR11 */
-        GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
+        GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SIM_RST,
         GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
-        GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
-        GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
+        GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
+        GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2,
         GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
-        GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
+        GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN,
         GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
-        GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
-        GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
-        GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
-        GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
-        GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
-        GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
-        GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
-        GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
+        GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
+        GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
+        GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
+        GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
+        GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS,
+        GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM,
+        GPIO_FN_SPA_TDI, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
+        GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B,
         GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
-        GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
+        GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B,
         GPIO_FN_HRTS0_B,
 
         /* IPSR12 */
         GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
-        GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
+        GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
         GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
         GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
         GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
-        GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
+        GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_SIM_D_B,
         GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
-        GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
-        GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
+        GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
+        GPIO_FN_GPS_MAG, GPIO_FN_FCE,
 };
 
 struct platform_device;
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index b582facc1cf6..7ded4ebaf5cc 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -294,21 +294,6 @@ enum {
         GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      GPIO_FN_D14_NAF14,
         GPIO_FN_D15_NAF15,
 
-        /*
-         * MMCIF(1)             (PORT 84, 85, 86, 87, 88, 89,
-         *                            90, 91, 92, 99)
-         */
-        GPIO_FN_MMCD0_0,        GPIO_FN_MMCD0_1,        GPIO_FN_MMCD0_2,
-        GPIO_FN_MMCD0_3,        GPIO_FN_MMCD0_4,        GPIO_FN_MMCD0_5,
-        GPIO_FN_MMCD0_6,        GPIO_FN_MMCD0_7,
-        GPIO_FN_MMCCMD0,        GPIO_FN_MMCCLK0,
-
-        /* MMCIF(2)             (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */
-        GPIO_FN_MMCD1_0,        GPIO_FN_MMCD1_1,        GPIO_FN_MMCD1_2,
-        GPIO_FN_MMCD1_3,        GPIO_FN_MMCD1_4,        GPIO_FN_MMCD1_5,
-        GPIO_FN_MMCD1_6,        GPIO_FN_MMCD1_7,
-        GPIO_FN_MMCCLK1,        GPIO_FN_MMCCMD1,
-
         /* SPU2         (PORT 65) */
         GPIO_FN_VINT_I,
 
@@ -416,20 +401,6 @@ enum {
         /* HDMI         (PORT 169, 170) */
         GPIO_FN_HDMI_HPD,       GPIO_FN_HDMI_CEC,
 
-        /* SDHI0        (PORT 171, 172, 173, 174, 175, 176, 177, 178) */
-        GPIO_FN_SDHICLK0,       GPIO_FN_SDHICD0,
-        GPIO_FN_SDHICMD0,       GPIO_FN_SDHIWP0,
-        GPIO_FN_SDHID0_0,       GPIO_FN_SDHID0_1,
-        GPIO_FN_SDHID0_2,       GPIO_FN_SDHID0_3,
-
-        /* SDHI1        (PORT 179, 180, 181, 182, 183, 184) */
-        GPIO_FN_SDHICLK1,       GPIO_FN_SDHICMD1,       GPIO_FN_SDHID1_0,
-        GPIO_FN_SDHID1_1,       GPIO_FN_SDHID1_2,       GPIO_FN_SDHID1_3,
-
-        /* SDHI2        (PORT 185, 186, 187, 188, 189, 190) */
-        GPIO_FN_SDHICLK2,       GPIO_FN_SDHICMD2,       GPIO_FN_SDHID2_0,
-        GPIO_FN_SDHID2_1,       GPIO_FN_SDHID2_2,       GPIO_FN_SDHID2_3,
-
         /* SDENC        see MSEL4CR 19 */
         GPIO_FN_SDENC_CPG,
         GPIO_FN_SDENC_DV_CLKI,
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 606d31d02a4e..fbc1584d6712 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -94,8 +94,7 @@ enum {
         GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
 
         /* Table 25-1 (Function 0-7) */
-        GPIO_FN_VBUS_0,
-        GPIO_FN_GPI0,
+        GPIO_FN_GPI0 = 310,
         GPIO_FN_GPI1,
         GPIO_FN_GPI2,
         GPIO_FN_GPI3,
@@ -103,15 +102,11 @@ enum {
         GPIO_FN_GPI5,
         GPIO_FN_GPI6,
         GPIO_FN_GPI7,
-        GPIO_FN_SCIFA7_RXD,
-        GPIO_FN_SCIFA7_CTS_,
         GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
         GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
-        GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+        GPIO_FN_GPO5,
         GPIO_FN_PORT16_VIO_CKOR,
-        GPIO_FN_SCIFA0_TXD,
-        GPIO_FN_SCIFA7_TXD,
-        GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+        GPIO_FN_PORT19_VIO_CKO2,
         GPIO_FN_GPO0,
         GPIO_FN_GPO1,
         GPIO_FN_GPO2, GPIO_FN_STATUS0,
@@ -119,83 +114,44 @@ enum {
         GPIO_FN_GPO4, GPIO_FN_STATUS2,
         GPIO_FN_VINT,
         GPIO_FN_TCKON,
-        GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+        GPIO_FN_XDVFS1,
         GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
-        GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+        GPIO_FN_XDVFS2,
         GPIO_FN_PORT28_TPU1TO1,
         GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
         GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
         GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
-        GPIO_FN_SCIFA4_TXD,
-        GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
-        GPIO_FN_SCIFA4_RTS_,
-        GPIO_FN_SCIFA4_CTS_,
-        GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
-        GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
-        GPIO_FN_FSIBOSLD,
-        GPIO_FN_FSIBISLD,
+        GPIO_FN_XWUP,
         GPIO_FN_VACK,
         GPIO_FN_XTAL1L,
-        GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
-        GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
-        GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
-        GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
-        GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
-        GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
-        GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
-        GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
-
-        GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
-        GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
-        GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
-        GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
-        GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
-        GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
-        GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+        GPIO_FN_PORT49_IROUT,
+        GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2,
+
+        GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3,
+        GPIO_FN_BBIF2_TXD2,
+        GPIO_FN_TPU3TO3,
+        GPIO_FN_TPU3TO2,
+        GPIO_FN_TPU0TO0,
         GPIO_FN_A0, GPIO_FN_BS_,
-        GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
-        GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
-        GPIO_FN_A14, GPIO_FN_KEYOUT5,
-        GPIO_FN_A15, GPIO_FN_KEYOUT4,
-        GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
-        GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
-        GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
-        GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_A26, GPIO_FN_KEYIN6,
-        GPIO_FN_KEYIN7,
-        GPIO_FN_D0_NAF0,
-        GPIO_FN_D1_NAF1,
-        GPIO_FN_D2_NAF2,
-        GPIO_FN_D3_NAF3,
-        GPIO_FN_D4_NAF4,
-        GPIO_FN_D5_NAF5,
-        GPIO_FN_D6_NAF6,
-        GPIO_FN_D7_NAF7,
-        GPIO_FN_D8_NAF8,
-        GPIO_FN_D9_NAF9,
-        GPIO_FN_D10_NAF10,
-        GPIO_FN_D11_NAF11,
-        GPIO_FN_D12_NAF12,
-        GPIO_FN_D13_NAF13,
-        GPIO_FN_D14_NAF14,
-        GPIO_FN_D15_NAF15,
-        GPIO_FN_CS4_,
-        GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
-        GPIO_FN_CS5B_, GPIO_FN_FCE1_,
-        GPIO_FN_CS6B_, GPIO_FN_DACK0,
-        GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+        GPIO_FN_A12, GPIO_FN_TPU4TO2,
+        GPIO_FN_A13, GPIO_FN_TPU0TO1,
+        GPIO_FN_A14,
+        GPIO_FN_A15,
+        GPIO_FN_A16, GPIO_FN_MSIOF0_SS1,
+        GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC,
+        GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK,
+        GPIO_FN_A19, GPIO_FN_MSIOF0_TXD,
+        GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK,
+        GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC,
+        GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0,
+        GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1,
+        GPIO_FN_A24, GPIO_FN_MSIOF0_RXD,
+        GPIO_FN_A25, GPIO_FN_MSIOF0_SS2,
+        GPIO_FN_A26,
+        GPIO_FN_FCE1_,
+        GPIO_FN_DACK0,
+        GPIO_FN_FCE0_,
         GPIO_FN_WAIT_, GPIO_FN_DREQ0,
-        GPIO_FN_RD__FSC,
-        GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
-        GPIO_FN_WE1_,
         GPIO_FN_FRB,
         GPIO_FN_CKO,
         GPIO_FN_NBRSTOUT_,
@@ -204,145 +160,118 @@ enum {
         GPIO_FN_BBIF2_RXD,
         GPIO_FN_BBIF2_SYNC,
         GPIO_FN_BBIF2_SCK,
-        GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
-        GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
-        GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
-        GPIO_FN_SCIFA3_TXD,
+        GPIO_FN_MFG3_IN2,
+        GPIO_FN_MFG3_IN1,
+        GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1,
         GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
         GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
         GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
         GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
-        GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
-        GPIO_FN_PORT115_I2C_SCL3,
-        GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
-        GPIO_FN_PORT116_I2C_SDA3,
+        GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK,
+        GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC,
         GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
         GPIO_FN_HSI_TX_FLAG,
-        GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
-        GPIO_FN_LCD2D0,
-
-        GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
-        GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
-        GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
-        GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
-        GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
-        GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
-        GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
-        GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
-        GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
-        GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
-        GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
-        GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
-        GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
-        GPIO_FN_LCD2D6,
-        GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
-        GPIO_FN_LCD2D7,
-        GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
-        GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
-        GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
-        GPIO_FN_LCD2D2,
-        GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
-        GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
-        GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
-        GPIO_FN_LCD2D4,
-        GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
-        GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
-        GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
-        GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
-        GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+        GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD,
+
+        GPIO_FN_VIO_HD,
+        GPIO_FN_VIO2_HD,
+        GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD,
+        GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1,
+        GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2,
+        GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC,
+        GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD,
+        GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK,
+        GPIO_FN_VIO_D6,
+        GPIO_FN_VIO_D7,
+        GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0,
+        GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1,
+        GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2,
+        GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3,
+        GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4,
+        GPIO_FN_VIO_D13,
+        GPIO_FN_VIO2_D5,
+        GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6,
+        GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3,
+        GPIO_FN_VIO2_D7,
+        GPIO_FN_VIO_CLK,
+        GPIO_FN_VIO2_CLK,
+        GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
         GPIO_FN_VIO_CKO,
-        GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
-        GPIO_FN_PORT149_KEYOUT9,
+        GPIO_FN_A27, GPIO_FN_MFG0_IN1,
         GPIO_FN_MFG0_IN2,
         GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
         GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
         GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
-        GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
-        GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
-        GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
-        GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
-        GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
-        GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
-        GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
-        GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
-        GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+        GPIO_FN_MSIOF2_MCK0,
+        GPIO_FN_MSIOF2_MCK1,
+        GPIO_FN_PORT156_MSIOF2_SS2,
+        GPIO_FN_PORT157_MSIOF2_RXD,
+        GPIO_FN_DINT_, GPIO_FN_TS_SCK3,
+        GPIO_FN_NMI,
         GPIO_FN_TPU3TO0,
-        GPIO_FN_LCDD0,
-        GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
-        GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
-        GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
-        GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+        GPIO_FN_BBIF2_TSYNC1,
+        GPIO_FN_BBIF2_TSCK1,
+        GPIO_FN_BBIF2_TXD1,
+        GPIO_FN_MFG2_OUT2,
         GPIO_FN_TPU2TO1,
-        GPIO_FN_LCDD6,
-        GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
-        GPIO_FN_LCDD8, GPIO_FN_D16,
-        GPIO_FN_LCDD9, GPIO_FN_D17,
-        GPIO_FN_LCDD10, GPIO_FN_D18,
-        GPIO_FN_LCDD11, GPIO_FN_D19,
-        GPIO_FN_LCDD12, GPIO_FN_D20,
-        GPIO_FN_LCDD13, GPIO_FN_D21,
-        GPIO_FN_LCDD14, GPIO_FN_D22,
-        GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
-        GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
-        GPIO_FN_LCDD17, GPIO_FN_D25,
-        GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
-        GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
-        GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
-        GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
-        GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
-        GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
-        GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
-        GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
-        GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
-        GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+        GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+        GPIO_FN_D16,
+        GPIO_FN_D17,
+        GPIO_FN_D18,
+        GPIO_FN_D19,
+        GPIO_FN_D20,
+        GPIO_FN_D21,
+        GPIO_FN_D22,
+        GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+        GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+        GPIO_FN_D25,
+        GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+        GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+        GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+        GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+        GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+        GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+        GPIO_FN_DACK2,
+        GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3,
+        GPIO_FN_DACK3,
         GPIO_FN_PORT218_VIO_CKOR,
-        GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
         GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
-        GPIO_FN_LCD2DCK_2,
-        GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
-        GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+        GPIO_FN_DREQ1,
         GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
-        GPIO_FN_PORT221_LCD2HSYN,
-        GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
-        GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
-
-        GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
-        GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
-        GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
-        GPIO_FN_SCIFA1_RXD,
-        GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
-        GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
-        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
-        GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
-        GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
-        GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
-        GPIO_FN_LCD2D20,
+        GPIO_FN_DACK1, GPIO_FN_OVCN,
+        GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3,
+
+        GPIO_FN_OVCN2,
+        GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2,
+        GPIO_FN_IDIN,
+        GPIO_FN_MFG1_IN1,
+        GPIO_FN_MSIOF1_TXD,
+        GPIO_FN_MSIOF1_TSYNC,
+        GPIO_FN_MSIOF1_TSCK,
+        GPIO_FN_MSIOF1_RXD,
+        GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2,
         GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
-        GPIO_FN_LCD2D21,
-        GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
-        GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
-        GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
-        GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
-        GPIO_FN_SCIFA6_TXD,
-        GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+        GPIO_FN_MSIOF1_MCK0,
+        GPIO_FN_MSIOF1_MCK1,
+        GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
+        GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
+        GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
         GPIO_FN_TPU4TO0,
-        GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
-        GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
-        GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
-        GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
-        GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
-        GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
-        GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
-        GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
-        GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
-        GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
-        GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
-        GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
-        GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+        GPIO_FN_MFG4_IN2,
+        GPIO_FN_PORT243_VIO_CKO2,
+        GPIO_FN_MFG2_IN1,
+        GPIO_FN_MSIOF2R_RXD,
+        GPIO_FN_MFG2_IN2,
+        GPIO_FN_MSIOF2R_TXD,
+        GPIO_FN_MFG1_OUT1,
+        GPIO_FN_TPU1TO0,
+        GPIO_FN_MFG3_OUT2,
+        GPIO_FN_TPU3TO1,
+        GPIO_FN_MFG2_OUT1,
+        GPIO_FN_TPU2TO0,
+        GPIO_FN_MSIOF2R_TSCK,
         GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
-        GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+        GPIO_FN_MSIOF2R_TSYNC,
         GPIO_FN_SDHICLK0,
         GPIO_FN_SDHICD0,
         GPIO_FN_SDHID0_0,
@@ -435,54 +364,12 @@ enum {
         GPIO_FN_IRQ9_MEM_INT,
         GPIO_FN_IRQ9_MCP_INT,
         GPIO_FN_A11,
-        GPIO_FN_KEYOUT8,
         GPIO_FN_TPU4TO3,
         GPIO_FN_RESETA_N_PU_ON,
         GPIO_FN_RESETA_N_PU_OFF,
         GPIO_FN_EDBGREQ_PD,
         GPIO_FN_EDBGREQ_PU,
 
-        /* Functions with pull-ups */
-        GPIO_FN_KEYIN0_PU,
-        GPIO_FN_KEYIN1_PU,
-        GPIO_FN_KEYIN2_PU,
-        GPIO_FN_KEYIN3_PU,
-        GPIO_FN_KEYIN4_PU,
-        GPIO_FN_KEYIN5_PU,
-        GPIO_FN_KEYIN6_PU,
-        GPIO_FN_KEYIN7_PU,
-        GPIO_FN_SDHICD0_PU,
-        GPIO_FN_SDHID0_0_PU,
-        GPIO_FN_SDHID0_1_PU,
-        GPIO_FN_SDHID0_2_PU,
-        GPIO_FN_SDHID0_3_PU,
-        GPIO_FN_SDHICMD0_PU,
-        GPIO_FN_SDHIWP0_PU,
-        GPIO_FN_SDHID1_0_PU,
-        GPIO_FN_SDHID1_1_PU,
-        GPIO_FN_SDHID1_2_PU,
-        GPIO_FN_SDHID1_3_PU,
-        GPIO_FN_SDHICMD1_PU,
-        GPIO_FN_SDHID2_0_PU,
-        GPIO_FN_SDHID2_1_PU,
-        GPIO_FN_SDHID2_2_PU,
-        GPIO_FN_SDHID2_3_PU,
-        GPIO_FN_SDHICMD2_PU,
-        GPIO_FN_MMCCMD0_PU,
-        GPIO_FN_MMCCMD1_PU,
-        GPIO_FN_MMCD0_0_PU,
-        GPIO_FN_MMCD0_1_PU,
-        GPIO_FN_MMCD0_2_PU,
-        GPIO_FN_MMCD0_3_PU,
-        GPIO_FN_MMCD0_4_PU,
-        GPIO_FN_MMCD0_5_PU,
-        GPIO_FN_MMCD0_6_PU,
-        GPIO_FN_MMCD0_7_PU,
-        GPIO_FN_FSIACK_PU,
-        GPIO_FN_FSIAILR_PU,
-        GPIO_FN_FSIAIBT_PU,
-        GPIO_FN_FSIAISLD_PU,
-
         /* end of GPIO */
         GPIO_NR,
 };
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index 8807c27f71f9..f9cc4bc9c798 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
+#include <linux/irqchip.h>
 #include <mach/intc.h>
 #include <mach/r8a7779.h>
 #include <asm/mach-types.h>
@@ -43,13 +44,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
         return 0; /* always allow wakeup */
 }
 
-void __init r8a7779_init_irq(void)
+static void __init r8a7779_init_irq_common(void)
 {
-        void __iomem *gic_dist_base = IOMEM(0xf0001000);
-        void __iomem *gic_cpu_base = IOMEM(0xf0000100);
-
-        /* use GIC to handle interrupts */
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 
         /* route all interrupts to ARM */
@@ -63,3 +59,22 @@ void __init r8a7779_init_irq(void)
         __raw_writel(0xbffffffc, INT2SMSKCR3);
         __raw_writel(0x003fee3f, INT2SMSKCR4);
 }
+
+void __init r8a7779_init_irq(void)
+{
+        void __iomem *gic_dist_base = IOMEM(0xf0001000);
+        void __iomem *gic_cpu_base = IOMEM(0xf0000100);
+
+        /* use GIC to handle interrupts */
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+
+        r8a7779_init_irq_common();
+}
+
+#ifdef CONFIG_OF
+void __init r8a7779_init_irq_dt(void)
+{
+        irqchip_init();
+        r8a7779_init_irq_common();
+}
+#endif
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 91faba666d46..a81a1d804e2e 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -460,11 +460,3 @@ void __init sh73a0_init_irq(void)
         sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
         setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
 }
-
-#ifdef CONFIG_OF
-void __init sh73a0_init_irq_dt(void)
-{
-        irqchip_init();
-        gic_arch_extn.irq_set_wake = sh73a0_set_wake;
-}
-#endif
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 47662a581c0a..e4545c152722 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void)
                              ARRAY_SIZE(emev2_late_devices));
 }
 
-void __init emev2_init_delay(void)
+static void __init emev2_init_delay(void)
 {
         shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
 }
@@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
         { }
 };
 
-void __init emev2_add_standard_devices_dt(void)
+static void __init emev2_add_standard_devices_dt(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table,
                              emev2_auxdata_lookup, NULL);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index c54ff9b29fe5..042df35e71a0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/input.h>
@@ -28,6 +29,7 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/r8a7779.h>
@@ -91,7 +93,7 @@ static struct plat_sci_port scif0_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(88)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x78)),
 };
 
 static struct platform_device scif0_device = {
@@ -108,7 +110,7 @@ static struct plat_sci_port scif1_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(89)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x79)),
 };
 
 static struct platform_device scif1_device = {
@@ -125,7 +127,7 @@ static struct plat_sci_port scif2_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(90)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7a)),
 };
 
 static struct platform_device scif2_device = {
@@ -142,7 +144,7 @@ static struct plat_sci_port scif3_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(91)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7b)),
 };
 
 static struct platform_device scif3_device = {
@@ -159,7 +161,7 @@ static struct plat_sci_port scif4_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(92)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7c)),
 };
 
 static struct platform_device scif4_device = {
@@ -176,7 +178,7 @@ static struct plat_sci_port scif5_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(93)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7d)),
 };
 
 static struct platform_device scif5_device = {
@@ -203,7 +205,7 @@ static struct resource tmu00_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(32),
+                .start  = gic_iid(0x40),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -233,7 +235,7 @@ static struct resource tmu01_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(33),
+                .start  = gic_iid(0x41),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -255,7 +257,7 @@ static struct resource rcar_i2c0_res[] = {
                 .end    = 0xffc70fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(79),
+                .start  = gic_iid(0x6f),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -273,7 +275,7 @@ static struct resource rcar_i2c1_res[] = {
                 .end    = 0xffc71fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(82),
+                .start  = gic_iid(0x72),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -291,7 +293,7 @@ static struct resource rcar_i2c2_res[] = {
                 .end    = 0xffc72fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(80),
+                .start  = gic_iid(0x70),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -309,7 +311,7 @@ static struct resource rcar_i2c3_res[] = {
                 .end    = 0xffc73fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(81),
+                .start  = gic_iid(0x71),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -321,7 +323,31 @@ static struct platform_device i2c3_device = {
         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 };
 
-static struct platform_device *r8a7779_early_devices[] __initdata = {
+static struct resource sata_resources[] = {
+        [0] = {
+                .name   = "rcar-sata",
+                .start  = 0xfc600000,
+                .end    = 0xfc601fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x84),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sata_device = {
+        .name           = "sata_rcar",
+        .id             = -1,
+        .resource       = sata_resources,
+        .num_resources  = ARRAY_SIZE(sata_resources),
+        .dev            = {
+                .dma_mask               = &sata_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct platform_device *r8a7779_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
@@ -330,13 +356,14 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
         &scif5_device,
         &tmu00_device,
         &tmu01_device,
+};
+
+static struct platform_device *r8a7779_late_devices[] __initdata = {
         &i2c0_device,
         &i2c1_device,
         &i2c2_device,
         &i2c3_device,
-};
-
-static struct platform_device *r8a7779_late_devices[] __initdata = {
+        &sata_device,
 };
 
 void __init r8a7779_add_standard_devices(void)
@@ -349,8 +376,8 @@ void __init r8a7779_add_standard_devices(void)
 
         r8a7779_init_pm_domains();
 
-        platform_add_devices(r8a7779_early_devices,
-                            ARRAY_SIZE(r8a7779_early_devices));
+        platform_add_devices(r8a7779_devices_dt,
+                            ARRAY_SIZE(r8a7779_devices_dt));
         platform_add_devices(r8a7779_late_devices,
                             ARRAY_SIZE(r8a7779_late_devices));
 }
@@ -367,8 +394,8 @@ void __init r8a7779_earlytimer_init(void)
 
 void __init r8a7779_add_early_devices(void)
 {
-        early_platform_add_devices(r8a7779_early_devices,
-                                   ARRAY_SIZE(r8a7779_early_devices));
+        early_platform_add_devices(r8a7779_devices_dt,
+                                   ARRAY_SIZE(r8a7779_devices_dt));
 
         /* Early serial console setup is not included here due to
          * memory map collisions. The SCIF serial ports in r8a7779
@@ -386,3 +413,40 @@ void __init r8a7779_add_early_devices(void)
          * command line in case of the marzen board.
          */
 }
+
+#ifdef CONFIG_USE_OF
+void __init r8a7779_init_delay(void)
+{
+        shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
+}
+
+static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
+        {},
+};
+
+void __init r8a7779_add_standard_devices_dt(void)
+{
+        /* clocks are setup late during boot in the case of DT */
+        r8a7779_clock_init();
+
+        platform_add_devices(r8a7779_devices_dt,
+                             ARRAY_SIZE(r8a7779_devices_dt));
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             r8a7779_auxdata_lookup, NULL);
+}
+
+static const char *r8a7779_compat_dt[] __initdata = {
+        "renesas,r8a7779",
+        NULL,
+};
+
+DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
+        .map_io         = r8a7779_map_io,
+        .init_early     = r8a7779_init_delay,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = r8a7779_init_irq_dt,
+        .init_machine   = r8a7779_add_standard_devices_dt,
+        .init_time      = shmobile_timer_init,
+        .dt_compat      = r8a7779_compat_dt,
+MACHINE_END
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index bdab575f88bc..2257a915746d 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/delay.h>
@@ -810,7 +811,7 @@ static struct platform_device ipmmu_device = {
         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
 
-static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
+static struct platform_device *sh73a0_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
@@ -847,8 +848,8 @@ void __init sh73a0_add_standard_devices(void)
         /* Clear software reset bit on SY-DMAC module */
         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 
-        platform_add_devices(sh73a0_early_devices_dt,
-                            ARRAY_SIZE(sh73a0_early_devices_dt));
+        platform_add_devices(sh73a0_devices_dt,
+                            ARRAY_SIZE(sh73a0_devices_dt));
         platform_add_devices(sh73a0_early_devices,
                             ARRAY_SIZE(sh73a0_early_devices));
         platform_add_devices(sh73a0_late_devices,
@@ -867,8 +868,8 @@ void __init sh73a0_earlytimer_init(void)
 
 void __init sh73a0_add_early_devices(void)
 {
-        early_platform_add_devices(sh73a0_early_devices_dt,
-                                   ARRAY_SIZE(sh73a0_early_devices_dt));
+        early_platform_add_devices(sh73a0_devices_dt,
+                                   ARRAY_SIZE(sh73a0_devices_dt));
         early_platform_add_devices(sh73a0_early_devices,
                                    ARRAY_SIZE(sh73a0_early_devices));
 
@@ -878,23 +879,9 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-/* Please note that the clock initialisation shcheme used in
- * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
- * does not work with SMP as there is a yet to be resolved lock-up in
- * workqueue initialisation.
- *
- * CONFIG_SMP should be disabled when using this code.
- */
-
-void __init sh73a0_add_early_devices_dt(void)
+void __init sh73a0_init_delay(void)
 {
         shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
-
-        early_platform_add_devices(sh73a0_early_devices_dt,
-                                   ARRAY_SIZE(sh73a0_early_devices_dt));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
 }
 
 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
@@ -906,8 +893,8 @@ void __init sh73a0_add_standard_devices_dt(void)
         /* clocks are setup late during boot in the case of DT */
         sh73a0_clock_init();
 
-        platform_add_devices(sh73a0_early_devices_dt,
-                             ARRAY_SIZE(sh73a0_early_devices_dt));
+        platform_add_devices(sh73a0_devices_dt,
+                             ARRAY_SIZE(sh73a0_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table,
                              sh73a0_auxdata_lookup, NULL);
 }
@@ -918,10 +905,11 @@ static const char *sh73a0_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
+        .smp            = smp_ops(sh73a0_smp_ops),
         .map_io         = sh73a0_map_io,
-        .init_early     = sh73a0_add_early_devices_dt,
+        .init_early     = sh73a0_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = sh73a0_init_irq_dt,
+        .init_irq       = irqchip_init,
         .init_machine   = sh73a0_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = sh73a0_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 953eb1f9388d..8225c16b371b 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -28,63 +28,9 @@
 #include <mach/emev2.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
-#include <asm/cacheflush.h>
 
 #define EMEV2_SCU_BASE 0x1e000000
 
-static DEFINE_SPINLOCK(scu_lock);
-static void __iomem *scu_base;
-
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        unsigned long tmp;
-
-        /* we assume this code is running on a different cpu
-         * than the one that is changing coherency setting */
-        spin_lock(&scu_lock);
-        tmp = readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        writel(tmp, scu_base + 8);
-        spin_unlock(&scu_lock);
-
-}
-
-static unsigned int __init emev2_get_core_count(void)
-{
-        if (!scu_base) {
-                scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
-                emev2_clock_init(); /* need ioremapped SMU */
-        }
-
-        WARN_ON_ONCE(!scu_base);
-
-        return scu_base ? scu_get_core_count(scu_base) : 1;
-}
-
-static int emev2_platform_cpu_kill(unsigned int cpu)
-{
-        return 0; /* not supported yet */
-}
-
-static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
-{
-        int k;
-
-        /* this function is running on another CPU than the offline target,
-         * here we need wait for shutdown code in platform_cpu_die() to
-         * finish before asking SoC-specific code to power off the CPU core.
-         */
-        for (k = 0; k < 1000; k++) {
-                if (shmobile_cpu_is_dead(cpu))
-                        return emev2_platform_cpu_kill(cpu);
-                mdelay(1);
-        }
-
-        return 0;
-}
-
-
 static void __cpuinit emev2_secondary_init(unsigned int cpu)
 {
         gic_secondary_init(0);
@@ -92,31 +38,30 @@ static void __cpuinit emev2_secondary_init(unsigned int cpu)
 
 static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        cpu = cpu_logical_map(cpu);
-
-        /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
-
-        /* Tell ROM loader about our vector (in headsmp.S) */
-        emev2_set_boot_vector(__pa(shmobile_secondary_vector));
-
-        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
         return 0;
 }
 
 static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
+        scu_enable(shmobile_scu_base);
 
-        scu_enable(scu_base);
+        /* Tell ROM loader about our vector (in headsmp-scu.S) */
+        emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
 
-        /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        /* enable cache coherency on booting CPU */
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
 static void __init emev2_smp_init_cpus(void)
 {
-        unsigned int ncores = emev2_get_core_count();
+        unsigned int ncores;
+
+        /* setup EMEV2 specific SCU base */
+        shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
+        emev2_clock_init(); /* need ioremapped SMU */
+
+        ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
 
         shmobile_smp_init_cpus(ncores);
 }
@@ -126,9 +71,4 @@ struct smp_operations emev2_smp_ops __initdata = {
         .smp_prepare_cpus       = emev2_smp_prepare_cpus,
         .smp_secondary_init     = emev2_secondary_init,
         .smp_boot_secondary     = emev2_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_kill               = emev2_cpu_kill,
-        .cpu_die                = shmobile_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable,
-#endif
 };
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 3a4acf23edcf..ea4535a5c4e2 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -26,11 +26,13 @@
 #include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
+#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 
 #define AVECR IOMEM(0xfe700040)
+#define R8A7779_SCU_BASE 0xf0000000
 
 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
@@ -56,44 +58,14 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
         [3] = &r8a7779_ch_cpu3,
 };
 
-static void __iomem *scu_base_addr(void)
-{
-        return (void __iomem *)0xf0000000;
-}
-
-static DEFINE_SPINLOCK(scu_lock);
-static unsigned long tmp;
-
 #ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
-
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29);
 void __init r8a7779_register_twd(void)
 {
         twd_local_timer_register(&twd_local_timer);
 }
 #endif
 
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        spin_lock(&scu_lock);
-        tmp = __raw_readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        spin_unlock(&scu_lock);
-
-        /* disable cache coherency after releasing the lock */
-        __raw_writel(tmp, scu_base + 8);
-}
-
-static unsigned int __init r8a7779_get_core_count(void)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        return scu_get_core_count(scu_base);
-}
-
 static int r8a7779_platform_cpu_kill(unsigned int cpu)
 {
         struct r8a7779_pm_ch *ch = NULL;
@@ -101,9 +73,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
 
         cpu = cpu_logical_map(cpu);
 
-        /* disable cache coherency */
-        modify_scu_cpu_psr(3 << (cpu * 8), 0);
-
         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[cpu];
 
@@ -113,25 +82,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
         return ret ? ret : 1;
 }
 
-static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
-{
-        int k;
-
-        /* this function is running on another CPU than the offline target,
-         * here we need wait for shutdown code in platform_cpu_die() to
-         * finish before asking SoC-specific code to power off the CPU core.
-         */
-        for (k = 0; k < 1000; k++) {
-                if (shmobile_cpu_is_dead(cpu))
-                        return r8a7779_platform_cpu_kill(cpu);
-
-                mdelay(1);
-        }
-
-        return 0;
-}
-
-
 static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
 {
         gic_secondary_init(0);
@@ -144,9 +94,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
 
         cpu = cpu_logical_map(cpu);
 
-        /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
-
         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[cpu];
 
@@ -158,15 +105,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
+        scu_enable(shmobile_scu_base);
 
-        scu_enable(scu_base_addr());
+        /* Map the reset vector (in headsmp-scu.S) */
+        __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
 
-        /* Map the reset vector (in headsmp.S) */
-        __raw_writel(__pa(shmobile_secondary_vector), AVECR);
-
-        /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        /* enable cache coherency on booting CPU */
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 
         r8a7779_pm_init();
 
@@ -178,10 +123,60 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 
 static void __init r8a7779_smp_init_cpus(void)
 {
-        unsigned int ncores = r8a7779_get_core_count();
+        /* setup r8a7779 specific SCU base */
+        shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
+
+        shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
+}
 
-        shmobile_smp_init_cpus(ncores);
+#ifdef CONFIG_HOTPLUG_CPU
+static int r8a7779_scu_psr_core_disabled(int cpu)
+{
+        unsigned long mask = 3 << (cpu * 8);
+
+        if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
+                return 1;
+
+        return 0;
+}
+
+static int r8a7779_cpu_kill(unsigned int cpu)
+{
+        int k;
+
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (r8a7779_scu_psr_core_disabled(cpu))
+                        return r8a7779_platform_cpu_kill(cpu);
+
+                mdelay(1);
+        }
+
+        return 0;
+}
+
+static void r8a7779_cpu_die(unsigned int cpu)
+{
+        dsb();
+        flush_cache_all();
+
+        /* disable cache coherency */
+        scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
+
+        /* Endless loop until power off from r8a7779_cpu_kill() */
+        while (1)
+                cpu_do_idle();
+}
+
+static int r8a7779_cpu_disable(unsigned int cpu)
+{
+        /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
+        return cpu == 0 ? -EPERM : 0;
 }
+#endif /* CONFIG_HOTPLUG_CPU */
 
 struct smp_operations r8a7779_smp_ops  __initdata = {
         .smp_init_cpus          = r8a7779_smp_init_cpus,
@@ -190,7 +185,7 @@ struct smp_operations r8a7779_smp_ops  __initdata = {
         .smp_boot_secondary     = r8a7779_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = r8a7779_cpu_kill,
-        .cpu_die                = shmobile_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable,
+        .cpu_die                = r8a7779_cpu_die,
+        .cpu_disable            = r8a7779_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index acb46a94ccdf..5ae502b16437 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -39,26 +39,16 @@
 
 #define PSTR_SHUTDOWN_MODE      3
 
-static void __iomem *scu_base_addr(void)
-{
-        return (void __iomem *)0xf0000000;
-}
+#define SH73A0_SCU_BASE 0xf0000000
 
 #ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
 void __init sh73a0_register_twd(void)
 {
         twd_local_timer_register(&twd_local_timer);
 }
 #endif
 
-static unsigned int __init sh73a0_get_core_count(void)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        return scu_get_core_count(scu_base);
-}
-
 static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
 {
         gic_secondary_init(0);
@@ -78,21 +68,22 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
-        scu_enable(scu_base_addr());
+        scu_enable(shmobile_scu_base);
 
-        /* Map the reset vector (in headsmp-sh73a0.S) */
+        /* Map the reset vector (in headsmp-scu.S) */
         __raw_writel(0, APARMBAREA);      /* 4k */
-        __raw_writel(__pa(sh73a0_secondary_vector), SBAR);
+        __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
 
         /* enable cache coherency on booting CPU */
-        scu_power_mode(scu_base_addr(), SCU_PM_NORMAL);
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
 static void __init sh73a0_smp_init_cpus(void)
 {
-        unsigned int ncores = sh73a0_get_core_count();
+        /* setup sh73a0 specific SCU base */
+        shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
 
-        shmobile_smp_init_cpus(ncores);
+        shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -128,11 +119,16 @@ static void sh73a0_cpu_die(unsigned int cpu)
         flush_cache_all();
 
         /* Set power off mode. This takes the CPU out of the MP cluster */
-        scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
+        scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
 
         /* Enter shutdown mode */
         cpu_do_idle();
 }
+
+static int sh73a0_cpu_disable(unsigned int cpu)
+{
+        return 0; /* CPU0 and CPU1 supported */
+}
 #endif /* CONFIG_HOTPLUG_CPU */
 
 struct smp_operations sh73a0_smp_ops __initdata = {
@@ -143,6 +139,6 @@ struct smp_operations sh73a0_smp_ops __initdata = {
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = sh73a0_cpu_kill,
         .cpu_die                = sh73a0_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable_any,
+        .cpu_disable            = sh73a0_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 051b62c27102..7f2cb6c5e2c1 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -81,7 +81,6 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 #endif
 
 struct mmci_platform_data mop500_sdi0_data = {
-        .ios_handler    = mop500_sdi0_ios_handler,
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index b03457881c4b..87d2d7b38ce9 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/platform_data/i2c-nomadik.h>
@@ -439,6 +440,15 @@ static void mop500_prox_deactivate(struct device *dev)
         regulator_put(prox_regulator);
 }
 
+void mop500_snowball_ethernet_clock_enable(void)
+{
+        struct clk *clk;
+
+        clk = clk_get_sys("fsmc", NULL);
+        if (!IS_ERR(clk))
+                clk_prepare_enable(clk);
+}
+
 static struct cryp_platform_data u8500_cryp1_platform_data = {
                 .mem_to_engine = {
                                 .dir = STEDMA40_MEM_TO_PERIPH,
@@ -683,6 +693,8 @@ static void __init snowball_init_machine(void)
         mop500_audio_init(parent);
         mop500_uart_init(parent);
 
+        mop500_snowball_ethernet_clock_enable();
+
         /* This board has full regulator constraints */
         regulator_has_full_constraints();
 }
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index eaa605f5d90d..d38951be70df 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -104,6 +104,7 @@ void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
 void mop500_audio_init(struct device *parent);
+void mop500_snowball_ethernet_clock_enable(void);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 19235cf7bbe3..f1a581844372 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -312,9 +312,10 @@ static void __init u8500_init_machine(void)
         /* Pinmaps must be in place before devices register */
         if (of_machine_is_compatible("st-ericsson,mop500"))
                 mop500_pinmaps_init();
-        else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
+        else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
                 snowball_pinmaps_init();
-        else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
+                mop500_snowball_ethernet_clock_enable();
+        } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
                 hrefv60_pinmaps_init();
         else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
                 /* TODO: Add pinmaps for ccu9540 board. */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c2f37390308a..c465faca51b0 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -299,7 +299,7 @@ static void l2x0_unlock(u32 cache_id)
         int lockregs;
         int i;
 
-        switch (cache_id) {
+        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
         case L2X0_CACHE_ID_PART_L310:
                 lockregs = 8;
                 break;
@@ -333,15 +333,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
         if (cache_id_part_number_from_dt)
                 cache_id = cache_id_part_number_from_dt;
         else
-                cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
-                        & L2X0_CACHE_ID_PART_MASK;
+                cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
         aux &= aux_mask;
         aux |= aux_val;
 
         /* Determine the number of ways */
-        switch (cache_id) {
+        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
         case L2X0_CACHE_ID_PART_L310:
                 if (aux & (1 << 16))
                         ways = 16;
@@ -725,7 +724,6 @@ static const struct l2x0_of_data pl310_data = {
                 .flush_all   = l2x0_flush_all,
                 .inv_all     = l2x0_inv_all,
                 .disable     = l2x0_disable,
-                .set_debug   = pl310_set_debug,
         },
 };
 
@@ -814,9 +812,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
                 data->save();
 
         of_init = true;
-        l2x0_init(l2x0_base, aux_val, aux_mask);
-
         memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
+        l2x0_init(l2x0_base, aux_val, aux_mask);
 
         return 0;
 }
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index a5a4b2bc42ba..2ac37372ef52 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -48,7 +48,7 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
 static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
 static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
 
-static DEFINE_PER_CPU(atomic64_t, active_asids);
+DEFINE_PER_CPU(atomic64_t, active_asids);
 static DEFINE_PER_CPU(u64, reserved_asids);
 static cpumask_t tlb_flush_pending;
 
@@ -215,6 +215,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
         if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
                 local_flush_bp_all();
                 local_flush_tlb_all();
+                dummy_flush_tlb_a15_erratum();
         }
 
         atomic64_set(&per_cpu(active_asids, cpu), asid);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e95a996ab78f..78978945492a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -598,39 +598,60 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
         } while (pte++, addr += PAGE_SIZE, addr != end);
 }
 
-static void __init alloc_init_section(pud_t *pud, unsigned long addr,
-                                      unsigned long end, phys_addr_t phys,
-                                      const struct mem_type *type)
+static void __init map_init_section(pmd_t *pmd, unsigned long addr,
+                        unsigned long end, phys_addr_t phys,
+                        const struct mem_type *type)
 {
-        pmd_t *pmd = pmd_offset(pud, addr);
-
+#ifndef CONFIG_ARM_LPAE
         /*
-         * Try a section mapping - end, addr and phys must all be aligned
-         * to a section boundary.  Note that PMDs refer to the individual
-         * L1 entries, whereas PGDs refer to a group of L1 entries making
-         * up one logical pointer to an L2 table.
+         * In classic MMU format, puds and pmds are folded in to
+         * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
+         * group of L1 entries making up one logical pointer to
+         * an L2 table (2MB), where as PMDs refer to the individual
+         * L1 entries (1MB). Hence increment to get the correct
+         * offset for odd 1MB sections.
+         * (See arch/arm/include/asm/pgtable-2level.h)
          */
-        if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
-                pmd_t *p = pmd;
-
-#ifndef CONFIG_ARM_LPAE
-                if (addr & SECTION_SIZE)
-                        pmd++;
+        if (addr & SECTION_SIZE)
+                pmd++;
 #endif
+        do {
+                *pmd = __pmd(phys | type->prot_sect);
+                phys += SECTION_SIZE;
+        } while (pmd++, addr += SECTION_SIZE, addr != end);
 
-                do {
-                        *pmd = __pmd(phys | type->prot_sect);
-                        phys += SECTION_SIZE;
-                } while (pmd++, addr += SECTION_SIZE, addr != end);
+        flush_pmd_entry(pmd);
+}
 
-                flush_pmd_entry(p);
-        } else {
+static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
+                                      unsigned long end, phys_addr_t phys,
+                                      const struct mem_type *type)
+{
+        pmd_t *pmd = pmd_offset(pud, addr);
+        unsigned long next;
+
+        do {
                 /*
-                 * No need to loop; pte's aren't interested in the
-                 * individual L1 entries.
+                 * With LPAE, we must loop over to map
+                 * all the pmds for the given range.
                  */
-                alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
-        }
+                next = pmd_addr_end(addr, end);
+
+                /*
+                 * Try a section mapping - addr, next and phys must all be
+                 * aligned to a section boundary.
+                 */
+                if (type->prot_sect &&
+                                ((addr | next | phys) & ~SECTION_MASK) == 0) {
+                        map_init_section(pmd, addr, next, phys, type);
+                } else {
+                        alloc_init_pte(pmd, addr, next,
+                                                __phys_to_pfn(phys), type);
+                }
+
+                phys += next - addr;
+
+        } while (pmd++, addr = next, addr != end);
 }
 
 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
@@ -641,7 +662,7 @@ static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
 
         do {
                 next = pud_addr_end(addr, end);
-                alloc_init_section(pud, addr, next, phys, type);
+                alloc_init_pmd(pud, addr, next, phys, type);
                 phys += next - addr;
         } while (pud++, addr = next, addr != end);
 }
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a3c015f8d5c..f584d3f5b37c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -420,7 +420,7 @@ __v7_pj4b_proc_info:
 __v7_ca7mp_proc_info:
         .long   0x410fc070
         .long   0xff0ffff0
-        __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
+        __v7_proc __v7_ca7mp_setup
         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 
         /*
@@ -430,10 +430,25 @@ __v7_ca7mp_proc_info:
 __v7_ca15mp_proc_info:
         .long   0x410fc0f0
         .long   0xff0ffff0
-        __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
+        __v7_proc __v7_ca15mp_setup
         .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 
         /*
+         * Qualcomm Inc. Krait processors.
+         */
+        .type   __krait_proc_info, #object
+__krait_proc_info:
+        .long   0x510f0400              @ Required ID value
+        .long   0xff0ffc00              @ Mask for ID
+        /*
+         * Some Krait processors don't indicate support for SDIV and UDIV
+         * instructions in the ARM instruction set, even though they actually
+         * do support them.
+         */
+        __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
+        .size   __krait_proc_info, . - __krait_proc_info
+
+        /*
          * Match any ARMv7 processor core.
          */
         .type   __v7_proc_info, #object
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cd2e21ff562a..51244bf97271 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -18,7 +18,7 @@ config MIPS
         select HAVE_KRETPROBES
         select HAVE_DEBUG_KMEMLEAK
         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
-        select HAVE_ARCH_TRANSPARENT_HUGEPAGE
+        select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
         select RTC_LIB if !MACH_LOONGSON
         select GENERIC_ATOMIC64 if !64BIT
         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
@@ -657,7 +657,7 @@ config SNI_RM
         bool "SNI RM200/300/400"
         select FW_ARC if CPU_LITTLE_ENDIAN
         select FW_ARC32 if CPU_LITTLE_ENDIAN
-        select SNIPROM if CPU_BIG_ENDIAN
+        select FW_SNIPROM if CPU_BIG_ENDIAN
         select ARCH_MAY_HAVE_PC_FDC
         select BOOT_ELF32
         select CEVT_R4K
@@ -1144,7 +1144,7 @@ config DEFAULT_SGI_PARTITION
 config FW_ARC32
         bool
 
-config SNIPROM
+config FW_SNIPROM
         bool
 
 config BOOT_ELF32
@@ -1493,7 +1493,6 @@ config CPU_XLP
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
-        select CPU_HAS_LLSC
         select WEAK_ORDERING
         select WEAK_REORDERING_BEYOND_LLSC
         select CPU_HAS_PREFETCH
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index ed1949c29508..9aa7d44898ed 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -745,10 +745,7 @@ void __init board_prom_init(void)
                 strcpy(cfe_version, "unknown");
         printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
 
-        if (bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET)) {
-                printk(KERN_ERR PFX "invalid nvram checksum\n");
-                return;
-        }
+        bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
 
         board_name = bcm63xx_nvram_get_name();
         /* find board by name */
diff --git a/arch/mips/bcm63xx/nvram.c b/arch/mips/bcm63xx/nvram.c
index 620611680839..a4b8864f9307 100644
--- a/arch/mips/bcm63xx/nvram.c
+++ b/arch/mips/bcm63xx/nvram.c
@@ -38,7 +38,7 @@ struct bcm963xx_nvram {
 static struct bcm963xx_nvram nvram;
 static int mac_addr_used;
 
-int __init bcm63xx_nvram_init(void *addr)
+void __init bcm63xx_nvram_init(void *addr)
 {
         unsigned int check_len;
         u32 crc, expected_crc;
@@ -60,9 +60,8 @@ int __init bcm63xx_nvram_init(void *addr)
         crc = crc32_le(~0, (u8 *)&nvram, check_len);
 
         if (crc != expected_crc)
-                return -EINVAL;
-
-        return 0;
+                pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
+                        expected_crc, crc);
 }
 
 u8 *bcm63xx_nvram_get_name(void)
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 314231be788c..35e18e98beb9 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -157,4 +157,4 @@ int __init bcm63xx_register_devices(void)
         return board_register_devices();
 }
 
-device_initcall(bcm63xx_register_devices);
+arch_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index c594a3d4f743..b0baa299f899 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -174,7 +174,10 @@ static int octeon_kexec_prepare(struct kimage *image)
 
 static void octeon_generic_shutdown(void)
 {
-        int cpu, i;
+        int i;
+#ifdef CONFIG_SMP
+        int cpu;
+#endif
         struct cvmx_bootmem_desc *bootmem_desc;
         void *named_block_array_ptr;
 
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
index 62d6a3b4d3b7..4e0b6bc1165e 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
@@ -9,10 +9,8 @@
  *
  * Initialized the local nvram copy from the target address and checks
  * its checksum.
- *
- * Returns 0 on success.
  */
-int __init bcm63xx_nvram_init(void *nvram);
+void bcm63xx_nvram_init(void *nvram);
 
 /**
  * bcm63xx_nvram_get_name() - returns the board name according to nvram
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
index d9c828419037..193c0912d38e 100644
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
@@ -28,11 +28,7 @@
 /* #define cpu_has_prefetch     ? */
 #define cpu_has_mcheck          1
 /* #define cpu_has_ejtag        ? */
-#ifdef CONFIG_CPU_HAS_LLSC
 #define cpu_has_llsc            1
-#else
-#define cpu_has_llsc            0
-#endif
 /* #define cpu_has_vtag_icache  ? */
 /* #define cpu_has_dc_aliases   ? */
 /* #define cpu_has_ic_fills_f_dc ? */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 12b70c25906a..0da44d422f5b 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1166,7 +1166,10 @@ do {									\
         unsigned int __dspctl;                                          \
                                                                         \
         __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
         "       rddsp   %0, %x1                                 \n"     \
+        "       .set pop                                        \n"     \
         : "=r" (__dspctl)                                               \
         : "i" (mask));                                                  \
         __dspctl;                                                       \
@@ -1175,30 +1178,198 @@ do {									\
 #define wrdsp(val, mask)                                                \
 do {                                                                    \
         __asm__ __volatile__(                                           \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
         "       wrdsp   %0, %x1                                 \n"     \
+        "       .set pop                                        \n"     \
         :                                                               \
         : "r" (val), "i" (mask));                                       \
 } while (0)
 
-#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
-#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
-#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
-#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
-
-#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
-#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
-#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
-#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
-
-#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
-#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
-#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
-#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
-
-#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
-#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
-#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
-#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
+#define mflo0()                                                         \
+({                                                                      \
+        long mflo0;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo0));                                                \
+        mflo0;                                                          \
+})
+
+#define mflo1()                                                         \
+({                                                                      \
+        long mflo1;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo1));                                                \
+        mflo1;                                                          \
+})
+
+#define mflo2()                                                         \
+({                                                                      \
+        long mflo2;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo2));                                                \
+        mflo2;                                                          \
+})
+
+#define mflo3()                                                         \
+({                                                                      \
+        long mflo3;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mflo %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mflo3));                                                \
+        mflo3;                                                          \
+})
+
+#define mfhi0()                                                         \
+({                                                                      \
+        long mfhi0;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi0));                                                \
+        mfhi0;                                                          \
+})
+
+#define mfhi1()                                                         \
+({                                                                      \
+        long mfhi1;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi1));                                                \
+        mfhi1;                                                          \
+})
+
+#define mfhi2()                                                         \
+({                                                                      \
+        long mfhi2;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi2));                                                \
+        mfhi2;                                                          \
+})
+
+#define mfhi3()                                                         \
+({                                                                      \
+        long mfhi3;                                                     \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mfhi %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        : "=r" (mfhi3));                                                \
+        mfhi3;                                                          \
+})
+
+
+#define mtlo0(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo1(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo2(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mtlo3(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mtlo %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi0(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac0                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi1(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac1                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi2(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac2                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
+
+#define mthi3(x)                                                        \
+({                                                                      \
+        __asm__(                                                        \
+        "       .set push                                       \n"     \
+        "       .set dsp                                        \n"     \
+        "       mthi %0, $ac3                                   \n"     \
+        "       .set pop                                        \n"     \
+        :                                                               \
+        : "r" (x));                                                     \
+})
 
 #else
 
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
index 197f6367c201..8efe5a9e2c3e 100644
--- a/arch/mips/include/asm/signal.h
+++ b/arch/mips/include/asm/signal.h
@@ -21,6 +21,6 @@
 #include <asm/sigcontext.h>
 #include <asm/siginfo.h>
 
-#define __ARCH_HAS_ODD_SIGACTION
+#define __ARCH_HAS_IRIX_SIGACTION
 
 #endif /* _ASM_SIGNAL_H */
diff --git a/arch/mips/include/uapi/asm/signal.h b/arch/mips/include/uapi/asm/signal.h
index d6b18b4d0f3a..addb9f556b71 100644
--- a/arch/mips/include/uapi/asm/signal.h
+++ b/arch/mips/include/uapi/asm/signal.h
@@ -72,6 +72,12 @@ typedef unsigned long old_sigset_t;		/* at least 32 bits */
  *
  * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
  * Unix names RESETHAND and NODEFER respectively.
+ *
+ * SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever
+ * supported its use and no libc was using it, so the entire sa-restorer
+ * functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48
+ * retaining only the SA_RESTORER definition as a reminder to avoid
+ * accidental reuse of the mask bit.
  */
 #define SA_ONSTACK      0x08000000
 #define SA_RESETHAND    0x80000000
@@ -84,8 +90,6 @@ typedef unsigned long old_sigset_t;		/* at least 32 bits */
 #define SA_NOMASK       SA_NODEFER
 #define SA_ONESHOT      SA_RESETHAND
 
-#define SA_RESTORER     0x04000000      /* Only for o32 */
-
 #define MINSIGSTKSZ    2048
 #define SIGSTKSZ       8192
 
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index f81d98f6184c..de75fb50562b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -100,29 +100,16 @@ obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event_mipsxx.o
 obj-$(CONFIG_JUMP_LABEL)        += jump_label.o
 
 #
-# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe
-# to enable DSP assembler support here even if the MIPS Release 2 CPU we
-# are targetting does not support DSP because all code-paths making use of
-# it properly check that the running CPU *actually does* support these
-# instructions.
+# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
+# safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
+# here because the compiler may use DSP ASE instructions (such as lwx) in
+# code paths where we cannot check that the CPU we are running on supports it.
+# Proper abstraction using HAVE_AS_DSP and macros is done in
+# arch/mips/include/asm/mipsregs.h.
 #
 ifeq ($(CONFIG_CPU_MIPSR2), y)
 CFLAGS_DSP                      = -DHAVE_AS_DSP
 
-#
-# Check if assembler supports DSP ASE
-#
-ifeq ($(call cc-option-yn,-mdsp), y)
-CFLAGS_DSP                      += -mdsp
-endif
-
-#
-# Check if assembler supports DSP ASE Rev2
-#
-ifeq ($(call cc-option-yn,-mdspr2), y)
-CFLAGS_DSP                      += -mdspr2
-endif
-
 CFLAGS_signal.o                 = $(CFLAGS_DSP)
 CFLAGS_signal32.o               = $(CFLAGS_DSP)
 CFLAGS_process.o                = $(CFLAGS_DSP)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 6bfccc227a95..5fe66a0c3224 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -580,6 +580,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                 c->tlbsize = 48;
                 break;
         case PRID_IMP_VR41XX:
+                set_isa(c, MIPS_CPU_ISA_III);
+                c->options = R4K_OPTS;
+                c->tlbsize = 32;
                 switch (c->processor_id & 0xf0) {
                 case PRID_REV_VR4111:
                         c->cputype = CPU_VR4111;
@@ -604,6 +607,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                                 __cpu_name[cpu] = "NEC VR4131";
                         } else {
                                 c->cputype = CPU_VR4133;
+                                c->options |= MIPS_CPU_LLSC;
                                 __cpu_name[cpu] = "NEC VR4133";
                         }
                         break;
@@ -613,9 +617,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                         __cpu_name[cpu] = "NEC Vr41xx";
                         break;
                 }
-                set_isa(c, MIPS_CPU_ISA_III);
-                c->options = R4K_OPTS;
-                c->tlbsize = 32;
                 break;
         case PRID_IMP_R4300:
                 c->cputype = CPU_R4300;
@@ -1226,10 +1227,8 @@ __cpuinit void cpu_probe(void)
         if (c->options & MIPS_CPU_FPU) {
                 c->fpu_id = cpu_get_fpu_id();
 
-                if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M32R2 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R2) {
+                if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
                         if (c->fpu_id & MIPS_FPIR_3D)
                                 c->ases |= MIPS_ASE_MIPS3D;
                 }
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 8eeee1c860c0..db9655f08892 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -171,7 +171,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
                 err = compat_sys_shmctl(first, second, compat_ptr(ptr));
                 break;
         default:
-                err = -EINVAL;
+                err = -ENOSYS;
                 break;
         }
 
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 165867673357..33d067148e61 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -46,10 +46,9 @@
         PTR_L   a5, PT_R9(sp)
         PTR_L   a6, PT_R10(sp)
         PTR_L   a7, PT_R11(sp)
-#else
-        PTR_ADDIU       sp, PT_SIZE
 #endif
-.endm
+        PTR_ADDIU       sp, PT_SIZE
+        .endm
 
         .macro RETURN_BACK
         jr ra
@@ -68,7 +67,11 @@ NESTED(ftrace_caller, PT_SIZE, ra)
         .globl _mcount
 _mcount:
         b       ftrace_stub
-        addiu sp,sp,8
+#ifdef CONFIG_32BIT
+         addiu sp,sp,8
+#else
+         nop
+#endif
 
         /* When tracing is activated, it calls ftrace_caller+8 (aka here) */
         lw      t1, function_trace_stop
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 135c4aadccbe..7a54f74b7818 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -67,7 +67,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         if (cpu_has_mips_r) {
                 seq_printf(m, "isa\t\t\t:");
                 if (cpu_has_mips_1)
-                        seq_printf(m, "%s", "mips1");
+                        seq_printf(m, "%s", " mips1");
                 if (cpu_has_mips_2)
                         seq_printf(m, "%s", " mips2");
                 if (cpu_has_mips_3)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index a200b5bdbb87..c3abb88170fc 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
 #ifdef CONFIG_64BIT
         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
 #endif
-        if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
+        if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
                 status_set |= ST0_XX;
         if (cpu_has_dsp)
                 status_set |= ST0_MX;
diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c
index 81f1dcfdcab8..a64daee740ee 100644
--- a/arch/mips/lib/bitops.c
+++ b/arch/mips/lib/bitops.c
@@ -90,12 +90,12 @@ int __mips_test_and_set_bit(unsigned long nr,
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a |= mask;
         raw_local_irq_restore(flags);
         return res;
@@ -116,12 +116,12 @@ int __mips_test_and_set_bit_lock(unsigned long nr,
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a |= mask;
         raw_local_irq_restore(flags);
         return res;
@@ -141,12 +141,12 @@ int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a &= ~mask;
         raw_local_irq_restore(flags);
         return res;
@@ -166,12 +166,12 @@ int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
         unsigned bit = nr & SZLONG_MASK;
         unsigned long mask;
         unsigned long flags;
-        unsigned long res;
+        int res;
 
         a += nr >> SZLONG_LOG;
         mask = 1UL << bit;
         raw_local_irq_save(flags);
-        res = (mask & *a);
+        res = (mask & *a) != 0;
         *a ^= mask;
         raw_local_irq_restore(flags);
         return res;
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 507147aebd41..a6adffbb4e5f 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -270,7 +270,7 @@ LEAF(csum_partial)
 #endif
 
         /* odd buffer alignment? */
-#ifdef CPU_MIPSR2
+#ifdef CONFIG_CPU_MIPSR2
         wsbh    v1, sum
         movn    sum, v1, t7
 #else
@@ -670,7 +670,7 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
         addu    sum, v1
 #endif
 
-#ifdef CPU_MIPSR2
+#ifdef CONFIG_CPU_MIPSR2
         wsbh    v1, sum
         movn    sum, v1, odd
 #else
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index ecca559b8d7b..2078915eacb9 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void)
                 return;
 
         default:
-                if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M32R2 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R2) {
+                if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
 #ifdef CONFIG_MIPS_CPU_SCACHE
                         if (mips_sc_init ()) {
                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 93d937b4b1ba..df96da7e939b 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void)
         c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
 
         /* Ignore anything but MIPSxx processors */
-        if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
-            c->isa_level != MIPS_CPU_ISA_M32R2 &&
-            c->isa_level != MIPS_CPU_ISA_M64R1 &&
-            c->isa_level != MIPS_CPU_ISA_M64R2)
+        if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                              MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
                 return 0;
 
         /* Does this MIPS32/MIPS64 CPU have a config2 register? */
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index 38a80c83fd67..d1faece21b6a 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -19,7 +19,7 @@
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/tlbmisc.h>
 
-#ifdef CONFIG_DEBUG_PCI
+#ifdef CONFIG_PCI_DEBUG
 #define DBG(x...) printk(KERN_DEBUG x)
 #else
 #define DBG(x...) do {} while (0)
@@ -162,7 +162,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
         if (status & (1 << 29)) {
                 *data = 0xffffffff;
                 error = -1;
-                DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d",
+                DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
                     access_type, bus->number, device);
         } else if ((status >> 28) & 0xf) {
                 DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 4a2930844d43..4a5443118cfb 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -344,6 +344,7 @@ extern unsigned long MODULES_END;
 #define _REGION3_ENTRY_CO       0x100   /* change-recording override        */
 
 /* Bits in the segment table entry */
+#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address        */
 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffUL/* segment table origin             */
 #define _SEGMENT_ENTRY_RO       0x200   /* page protection bit              */
 #define _SEGMENT_ENTRY_INV      0x20    /* invalid segment table entry      */
@@ -1531,7 +1532,8 @@ extern int s390_enable_sie(void);
 /*
  * No page table caches to initialise
  */
-#define pgtable_cache_init()    do { } while (0)
+static inline void pgtable_cache_init(void) { }
+static inline void check_pgt_cache(void) { }
 
 #include <asm-generic/pgtable.h>
 
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c
index dff631d34b45..466fb3383960 100644
--- a/arch/s390/lib/uaccess_pt.c
+++ b/arch/s390/lib/uaccess_pt.c
@@ -77,42 +77,69 @@ static size_t copy_in_kernel(size_t count, void __user *to,
  * >= -4095 (IS_ERR_VALUE(x) returns true), a fault has occured and the address
  * contains the (negative) exception code.
  */
-static __always_inline unsigned long follow_table(struct mm_struct *mm,
-                                                  unsigned long addr, int write)
+#ifdef CONFIG_64BIT
+static unsigned long follow_table(struct mm_struct *mm,
+                                  unsigned long address, int write)
 {
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        pte_t *ptep;
+        unsigned long *table = (unsigned long *)__pa(mm->pgd);
+
+        switch (mm->context.asce_bits & _ASCE_TYPE_MASK) {
+        case _ASCE_TYPE_REGION1:
+                table = table + ((address >> 53) & 0x7ff);
+                if (unlikely(*table & _REGION_ENTRY_INV))
+                        return -0x39UL;
+                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+        case _ASCE_TYPE_REGION2:
+                table = table + ((address >> 42) & 0x7ff);
+                if (unlikely(*table & _REGION_ENTRY_INV))
+                        return -0x3aUL;
+                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+        case _ASCE_TYPE_REGION3:
+                table = table + ((address >> 31) & 0x7ff);
+                if (unlikely(*table & _REGION_ENTRY_INV))
+                        return -0x3bUL;
+                table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+        case _ASCE_TYPE_SEGMENT:
+                table = table + ((address >> 20) & 0x7ff);
+                if (unlikely(*table & _SEGMENT_ENTRY_INV))
+                        return -0x10UL;
+                if (unlikely(*table & _SEGMENT_ENTRY_LARGE)) {
+                        if (write && (*table & _SEGMENT_ENTRY_RO))
+                                return -0x04UL;
+                        return (*table & _SEGMENT_ENTRY_ORIGIN_LARGE) +
+                                (address & ~_SEGMENT_ENTRY_ORIGIN_LARGE);
+                }
+                table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN);
+        }
+        table = table + ((address >> 12) & 0xff);
+        if (unlikely(*table & _PAGE_INVALID))
+                return -0x11UL;
+        if (write && (*table & _PAGE_RO))
+                return -0x04UL;
+        return (*table & PAGE_MASK) + (address & ~PAGE_MASK);
+}
 
-        pgd = pgd_offset(mm, addr);
-        if (pgd_none(*pgd) || unlikely(pgd_bad(*pgd)))
-                return -0x3aUL;
+#else /* CONFIG_64BIT */
 
-        pud = pud_offset(pgd, addr);
-        if (pud_none(*pud) || unlikely(pud_bad(*pud)))
-                return -0x3bUL;
+static unsigned long follow_table(struct mm_struct *mm,
+                                  unsigned long address, int write)
+{
+        unsigned long *table = (unsigned long *)__pa(mm->pgd);
 
-        pmd = pmd_offset(pud, addr);
-        if (pmd_none(*pmd))
+        table = table + ((address >> 20) & 0x7ff);
+        if (unlikely(*table & _SEGMENT_ENTRY_INV))
                 return -0x10UL;
-        if (pmd_large(*pmd)) {
-                if (write && (pmd_val(*pmd) & _SEGMENT_ENTRY_RO))
-                        return -0x04UL;
-                return (pmd_val(*pmd) & HPAGE_MASK) + (addr & ~HPAGE_MASK);
-        }
-        if (unlikely(pmd_bad(*pmd)))
-                return -0x10UL;
-
-        ptep = pte_offset_map(pmd, addr);
-        if (!pte_present(*ptep))
+        table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN);
+        table = table + ((address >> 12) & 0xff);
+        if (unlikely(*table & _PAGE_INVALID))
                 return -0x11UL;
-        if (write && (!pte_write(*ptep) || !pte_dirty(*ptep)))
+        if (write && (*table & _PAGE_RO))
                 return -0x04UL;
-
-        return (pte_val(*ptep) & PAGE_MASK) + (addr & ~PAGE_MASK);
+        return (*table & PAGE_MASK) + (address & ~PAGE_MASK);
 }
 
+#endif /* CONFIG_64BIT */
+
 static __always_inline size_t __user_copy_pt(unsigned long uaddr, void *kptr,
                                              size_t n, int write_user)
 {
@@ -197,7 +224,7 @@ size_t copy_to_user_pt(size_t n, void __user *to, const void *from)
 
 static size_t clear_user_pt(size_t n, void __user *to)
 {
-        void *zpage = &empty_zero_page;
+        void *zpage = (void *) empty_zero_page;
         long done, size, ret;
 
         done = 0;
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
index 96c6c2634cb4..eef17dcc3a41 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
@@ -8,12 +8,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7203_pfc_resources[] = {
+        [0] = {
+                .start  = 0xfffe3800,
+                .end    = 0xfffe3a9f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7203", NULL, 0);
+        return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources,
+                               ARRAY_SIZE(sh7203_pfc_resources));
 }
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
index b1b7c1bae127..569decbd6d93 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
@@ -8,12 +8,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7264_pfc_resources[] = {
+        [0] = {
+                .start  = 0xfffe3800,
+                .end    = 0xfffe393f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7264", NULL, 0);
+        return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources,
+                               ARRAY_SIZE(sh7264_pfc_resources));
 }
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
index dc2a86830456..1825b0bd523d 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -13,8 +13,17 @@
 #include <linux/kernel.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7269_pfc_resources[] = {
+        [0] = {
+                .start  = 0xfffe3800,
+                .end    = 0xfffe391f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7269", NULL, 0);
+        return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources,
+                               ARRAY_SIZE(sh7269_pfc_resources));
 }
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
index 7d3744ac7b08..26e90a66ebb7 100644
--- a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
@@ -8,13 +8,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7720_pfc_resources[] = {
+        [0] = {
+                .start  = 0xa4050100,
+                .end    = 0xa405016f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7720", NULL, 0);
+        return sh_pfc_register("pfc-sh7720", sh7720_pfc_resources,
+                               ARRAY_SIZE(sh7720_pfc_resources));
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
index d9bcc4290997..271bbc864929 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -1,10 +1,20 @@
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7722_pfc_resources[] = {
+        [0] = {
+                .start  = 0xa4050100,
+                .end    = 0xa405018f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7722", NULL, 0);
+        return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources,
+                               ARRAY_SIZE(sh7722_pfc_resources));
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
index bcec7ad7f783..99c637d5bf7a 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
@@ -8,13 +8,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7723_pfc_resources[] = {
+        [0] = {
+                .start  = 0xa4050100,
+                .end    = 0xa405016f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7723", NULL, 0);
+        return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources,
+                               ARRAY_SIZE(sh7723_pfc_resources));
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
index 5c3541d6aed8..63be4749e341 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
@@ -13,12 +13,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7724_pfc_resources[] = {
+        [0] = {
+                .start  = 0xa4050100,
+                .end    = 0xa405016f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7724", NULL, 0);
+        return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources,
+                               ARRAY_SIZE(sh7724_pfc_resources));
 }
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
index cda6bd177b8c..567745d44221 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -13,12 +13,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7757_pfc_resources[] = {
+        [0] = {
+                .start  = 0xffec0000,
+                .end    = 0xffec008f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7757", NULL, 0);
+        return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources,
+                               ARRAY_SIZE(sh7757_pfc_resources));
 }
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
index 01055b809f64..e336ab8b5125 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
@@ -8,13 +8,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7785_pfc_resources[] = {
+        [0] = {
+                .start  = 0xffe70000,
+                .end    = 0xffe7008f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7785", NULL, 0);
+        return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources,
+                               ARRAY_SIZE(sh7785_pfc_resources));
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
index 3061778d55da..9a459556a2f7 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
@@ -13,13 +13,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7786_pfc_resources[] = {
+        [0] = {
+                .start  = 0xffcc0000,
+                .end    = 0xffcc008f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7786", NULL, 0);
+        return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources,
+                               ARRAY_SIZE(sh7786_pfc_resources));
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
index ace84acc55ea..444bf25c60fa 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
@@ -7,12 +7,23 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
-static int __init shx3_pinmux_setup(void)
+static struct resource shx3_pfc_resources[] = {
+        [0] = {
+                .start  = 0xffc70000,
+                .end    = 0xffc7001f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-shx3", NULL, 0);
+        return sh_pfc_register("pfc-shx3", shx3_pfc_resources,
+                               ARRAY_SIZE(shx3_pfc_resources));
 }
-arch_initcall(shx3_pinmux_setup);
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index d1e15f7b59c6..7a5aa1a7864e 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -1004,15 +1004,8 @@ void __cpuinit setup_cpu(int boot)
 
 #ifdef CONFIG_BLK_DEV_INITRD
 
-/*
- * Note that the kernel can potentially support other compression
- * techniques than gz, though we don't do so by default.  If we ever
- * decide to do so we can either look for other filename extensions,
- * or just allow a file with this name to be compressed with an
- * arbitrary compressor (somewhat counterintuitively).
- */
 static int __initdata set_initramfs_file;
-static char __initdata initramfs_file[128] = "initramfs.cpio.gz";
+static char __initdata initramfs_file[128] = "initramfs";
 
 static int __init setup_initramfs_file(char *str)
 {
@@ -1026,9 +1019,9 @@ static int __init setup_initramfs_file(char *str)
 early_param("initramfs_file", setup_initramfs_file);
 
 /*
- * We look for an "initramfs.cpio.gz" file in the hvfs.
- * If there is one, we allocate some memory for it and it will be
- * unpacked to the initramfs.
+ * We look for a file called "initramfs" in the hvfs.  If there is one, we
+ * allocate some memory for it and it will be unpacked to the initramfs.
+ * If it's compressed, the initd code will uncompress it first.
  */
 static void __init load_hv_initrd(void)
 {
@@ -1038,10 +1031,16 @@ static void __init load_hv_initrd(void)
 
         fd = hv_fs_findfile((HV_VirtAddr) initramfs_file);
         if (fd == HV_ENOENT) {
-                if (set_initramfs_file)
+                if (set_initramfs_file) {
                         pr_warning("No such hvfs initramfs file '%s'\n",
                                    initramfs_file);
-                return;
+                        return;
+                } else {
+                        /* Try old backwards-compatible name. */
+                        fd = hv_fs_findfile((HV_VirtAddr)"initramfs.cpio.gz");
+                        if (fd == HV_ENOENT)
+                                return;
+                }
         }
         BUG_ON(fd < 0);
         stat = hv_fs_fstat(fd);
diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index 8a84501acb1b..5ef205c5f37b 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -4,7 +4,7 @@
 # create a compressed vmlinux image from the original vmlinux
 #
 
-targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xz vmlinux.bin.lzo head_$(BITS).o misc.o string.o cmdline.o early_serial_console.o piggy.o
+targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xz vmlinux.bin.lzo
 
 KBUILD_CFLAGS := -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2
 KBUILD_CFLAGS += -fno-strict-aliasing -fPIC
@@ -29,7 +29,6 @@ VMLINUX_OBJS = $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \
         $(obj)/piggy.o
 
 $(obj)/eboot.o: KBUILD_CFLAGS += -fshort-wchar -mno-red-zone
-$(obj)/efi_stub_$(BITS).o: KBUILD_CLFAGS += -fshort-wchar -mno-red-zone
 
 ifeq ($(CONFIG_EFI_STUB), y)
         VMLINUX_OBJS += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o
@@ -43,7 +42,7 @@ OBJCOPYFLAGS_vmlinux.bin :=  -R .comment -S
 $(obj)/vmlinux.bin: vmlinux FORCE
         $(call if_changed,objcopy)
 
-targets += vmlinux.bin.all vmlinux.relocs
+targets += $(patsubst $(obj)/%,%,$(VMLINUX_OBJS)) vmlinux.bin.all vmlinux.relocs
 
 CMD_RELOCS = arch/x86/tools/relocs
 quiet_cmd_relocs = RELOCS  $@
diff --git a/arch/x86/include/asm/syscall.h b/arch/x86/include/asm/syscall.h
index 1ace47b62592..2e188d68397c 100644
--- a/arch/x86/include/asm/syscall.h
+++ b/arch/x86/include/asm/syscall.h
@@ -29,13 +29,13 @@ extern const unsigned long sys_call_table[];
  */
 static inline int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
 {
-        return regs->orig_ax & __SYSCALL_MASK;
+        return regs->orig_ax;
 }
 
 static inline void syscall_rollback(struct task_struct *task,
                                     struct pt_regs *regs)
 {
-        regs->ax = regs->orig_ax & __SYSCALL_MASK;
+        regs->ax = regs->orig_ax;
 }
 
 static inline long syscall_get_error(struct task_struct *task,
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 02b51dd4e4ad..f77df1c5de6e 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1857,7 +1857,7 @@ int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
         if (!pv_eoi_enabled(vcpu))
                 return 0;
         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
-                                         addr);
+                                         addr, sizeof(u8));
 }
 
 void kvm_lapic_init(void)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index f19ac0aca60d..e1721324c271 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1823,7 +1823,8 @@ static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
                 return 0;
         }
 
-        if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
+        if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
+                                        sizeof(u32)))
                 return 1;
 
         vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
@@ -1952,12 +1953,9 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 
                 gpa_offset = data & ~(PAGE_MASK | 1);
 
-                /* Check that the address is 32-byte aligned. */
-                if (gpa_offset & (sizeof(struct pvclock_vcpu_time_info) - 1))
-                        break;
-
                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
-                     &vcpu->arch.pv_time, data & ~1ULL))
+                     &vcpu->arch.pv_time, data & ~1ULL,
+                     sizeof(struct pvclock_vcpu_time_info)))
                         vcpu->arch.pv_time_enabled = false;
                 else
                         vcpu->arch.pv_time_enabled = true;
@@ -1977,7 +1975,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                         return 1;
 
                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
-                                                        data & KVM_STEAL_VALID_BITS))
+                                                data & KVM_STEAL_VALID_BITS,
+                                                sizeof(struct kvm_steal_time)))
                         return 1;
 
                 vcpu->arch.st.msr_val = data;
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 92ed9692c47e..4bf68c8d4797 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -396,7 +396,7 @@ config ACPI_CUSTOM_METHOD
 
 config ACPI_BGRT
         bool "Boottime Graphics Resource Table support"
-        depends on EFI
+        depends on EFI && X86
         help
           This driver adds support for exposing the ACPI Boottime Graphics
           Resource Table, which allows the operating system to obtain
diff --git a/drivers/acpi/acpi_i2c.c b/drivers/acpi/acpi_i2c.c
index 82045e3f5cac..a82c7626aa9b 100644
--- a/drivers/acpi/acpi_i2c.c
+++ b/drivers/acpi/acpi_i2c.c
@@ -90,7 +90,7 @@ void acpi_i2c_register_devices(struct i2c_adapter *adapter)
         acpi_handle handle;
         acpi_status status;
 
-        handle = ACPI_HANDLE(&adapter->dev);
+        handle = ACPI_HANDLE(adapter->dev.parent);
         if (!handle)
                 return;
 
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index 5ff173066127..6ae5e440436e 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -415,7 +415,6 @@ static int acpi_pci_root_add(struct acpi_device *device,
         struct acpi_pci_root *root;
         struct acpi_pci_driver *driver;
         u32 flags, base_flags;
-        bool is_osc_granted = false;
 
         root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
         if (!root)
@@ -476,6 +475,30 @@ static int acpi_pci_root_add(struct acpi_device *device,
         flags = base_flags = OSC_PCI_SEGMENT_GROUPS_SUPPORT;
         acpi_pci_osc_support(root, flags);
 
+        /*
+         * TBD: Need PCI interface for enumeration/configuration of roots.
+         */
+
+        mutex_lock(&acpi_pci_root_lock);
+        list_add_tail(&root->node, &acpi_pci_roots);
+        mutex_unlock(&acpi_pci_root_lock);
+
+        /*
+         * Scan the Root Bridge
+         * --------------------
+         * Must do this prior to any attempt to bind the root device, as the
+         * PCI namespace does not get created until this call is made (and
+         * thus the root bridge's pci_dev does not exist).
+         */
+        root->bus = pci_acpi_scan_root(root);
+        if (!root->bus) {
+                printk(KERN_ERR PREFIX
+                            "Bus %04x:%02x not present in PCI namespace\n",
+                            root->segment, (unsigned int)root->secondary.start);
+                result = -ENODEV;
+                goto out_del_root;
+        }
+
         /* Indicate support for various _OSC capabilities. */
         if (pci_ext_cfg_avail())
                 flags |= OSC_EXT_PCI_CONFIG_SUPPORT;
@@ -494,6 +517,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
                         flags = base_flags;
                 }
         }
+
         if (!pcie_ports_disabled
             && (flags & ACPI_PCIE_REQ_SUPPORT) == ACPI_PCIE_REQ_SUPPORT) {
                 flags = OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL
@@ -514,54 +538,28 @@ static int acpi_pci_root_add(struct acpi_device *device,
                 status = acpi_pci_osc_control_set(device->handle, &flags,
                                        OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL);
                 if (ACPI_SUCCESS(status)) {
-                        is_osc_granted = true;
                         dev_info(&device->dev,
                                 "ACPI _OSC control (0x%02x) granted\n", flags);
+                        if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
+                                /*
+                                 * We have ASPM control, but the FADT indicates
+                                 * that it's unsupported. Clear it.
+                                 */
+                                pcie_clear_aspm(root->bus);
+                        }
                 } else {
-                        is_osc_granted = false;
                         dev_info(&device->dev,
                                 "ACPI _OSC request failed (%s), "
                                 "returned control mask: 0x%02x\n",
                                 acpi_format_exception(status), flags);
+                        pr_info("ACPI _OSC control for PCIe not granted, "
+                                "disabling ASPM\n");
+                        pcie_no_aspm();
                 }
         } else {
                 dev_info(&device->dev,
-                        "Unable to request _OSC control "
-                        "(_OSC support mask: 0x%02x)\n", flags);
-        }
-
-        /*
-         * TBD: Need PCI interface for enumeration/configuration of roots.
-         */
-
-        mutex_lock(&acpi_pci_root_lock);
-        list_add_tail(&root->node, &acpi_pci_roots);
-        mutex_unlock(&acpi_pci_root_lock);
-
-        /*
-         * Scan the Root Bridge
-         * --------------------
-         * Must do this prior to any attempt to bind the root device, as the
-         * PCI namespace does not get created until this call is made (and 
-         * thus the root bridge's pci_dev does not exist).
-         */
-        root->bus = pci_acpi_scan_root(root);
-        if (!root->bus) {
-                printk(KERN_ERR PREFIX
-                            "Bus %04x:%02x not present in PCI namespace\n",
-                            root->segment, (unsigned int)root->secondary.start);
-                result = -ENODEV;
-                goto out_del_root;
-        }
-
-        /* ASPM setting */
-        if (is_osc_granted) {
-                if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM)
-                        pcie_clear_aspm(root->bus);
-        } else {
-                pr_info("ACPI _OSC control for PCIe not granted, "
-                        "disabling ASPM\n");
-                pcie_no_aspm();
+                         "Unable to request _OSC control "
+                         "(_OSC support mask: 0x%02x)\n", flags);
         }
 
         pci_acpi_add_bus_pm_notifier(device, root->bus);
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index fc95308e9a11..ee255c60bdac 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -66,7 +66,8 @@ module_param(latency_factor, uint, 0644);
 
 static DEFINE_PER_CPU(struct cpuidle_device *, acpi_cpuidle_device);
 
-static struct acpi_processor_cx *acpi_cstate[CPUIDLE_STATE_MAX];
+static DEFINE_PER_CPU(struct acpi_processor_cx * [CPUIDLE_STATE_MAX],
+                                                                acpi_cstate);
 
 static int disabled_by_idle_boot_param(void)
 {
@@ -722,7 +723,7 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
                 struct cpuidle_driver *drv, int index)
 {
         struct acpi_processor *pr;
-        struct acpi_processor_cx *cx = acpi_cstate[index];
+        struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
 
         pr = __this_cpu_read(processors);
 
@@ -745,7 +746,7 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
  */
 static int acpi_idle_play_dead(struct cpuidle_device *dev, int index)
 {
-        struct acpi_processor_cx *cx = acpi_cstate[index];
+        struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
 
         ACPI_FLUSH_CPU_CACHE();
 
@@ -775,7 +776,7 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
                 struct cpuidle_driver *drv, int index)
 {
         struct acpi_processor *pr;
-        struct acpi_processor_cx *cx = acpi_cstate[index];
+        struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
 
         pr = __this_cpu_read(processors);
 
@@ -833,7 +834,7 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
                 struct cpuidle_driver *drv, int index)
 {
         struct acpi_processor *pr;
-        struct acpi_processor_cx *cx = acpi_cstate[index];
+        struct acpi_processor_cx *cx = per_cpu(acpi_cstate[index], dev->cpu);
 
         pr = __this_cpu_read(processors);
 
@@ -960,7 +961,7 @@ static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr,
                     !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
                         continue;
 #endif
-                acpi_cstate[count] = cx;
+                per_cpu(acpi_cstate[count], dev->cpu) = cx;
 
                 count++;
                 if (count == CPUIDLE_STATE_MAX)
diff --git a/drivers/base/power/qos.c b/drivers/base/power/qos.c
index 5f74587ef258..71671c42ef45 100644
--- a/drivers/base/power/qos.c
+++ b/drivers/base/power/qos.c
@@ -46,6 +46,7 @@
 #include "power.h"
 
 static DEFINE_MUTEX(dev_pm_qos_mtx);
+static DEFINE_MUTEX(dev_pm_qos_sysfs_mtx);
 
 static BLOCKING_NOTIFIER_HEAD(dev_pm_notifiers);
 
@@ -216,12 +217,17 @@ void dev_pm_qos_constraints_destroy(struct device *dev)
         struct pm_qos_constraints *c;
         struct pm_qos_flags *f;
 
-        mutex_lock(&dev_pm_qos_mtx);
+        mutex_lock(&dev_pm_qos_sysfs_mtx);
 
         /*
          * If the device's PM QoS resume latency limit or PM QoS flags have been
          * exposed to user space, they have to be hidden at this point.
          */
+        pm_qos_sysfs_remove_latency(dev);
+        pm_qos_sysfs_remove_flags(dev);
+
+        mutex_lock(&dev_pm_qos_mtx);
+
         __dev_pm_qos_hide_latency_limit(dev);
         __dev_pm_qos_hide_flags(dev);
 
@@ -254,6 +260,8 @@ void dev_pm_qos_constraints_destroy(struct device *dev)
 
  out:
         mutex_unlock(&dev_pm_qos_mtx);
+
+        mutex_unlock(&dev_pm_qos_sysfs_mtx);
 }
 
 /**
@@ -558,6 +566,14 @@ static void __dev_pm_qos_drop_user_request(struct device *dev,
         kfree(req);
 }
 
+static void dev_pm_qos_drop_user_request(struct device *dev,
+                                         enum dev_pm_qos_req_type type)
+{
+        mutex_lock(&dev_pm_qos_mtx);
+        __dev_pm_qos_drop_user_request(dev, type);
+        mutex_unlock(&dev_pm_qos_mtx);
+}
+
 /**
  * dev_pm_qos_expose_latency_limit - Expose PM QoS latency limit to user space.
  * @dev: Device whose PM QoS latency limit is to be exposed to user space.
@@ -581,6 +597,8 @@ int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value)
                 return ret;
         }
 
+        mutex_lock(&dev_pm_qos_sysfs_mtx);
+
         mutex_lock(&dev_pm_qos_mtx);
 
         if (IS_ERR_OR_NULL(dev->power.qos))
@@ -591,26 +609,27 @@ int dev_pm_qos_expose_latency_limit(struct device *dev, s32 value)
         if (ret < 0) {
                 __dev_pm_qos_remove_request(req);
                 kfree(req);
+                mutex_unlock(&dev_pm_qos_mtx);
                 goto out;
         }
-
         dev->power.qos->latency_req = req;
+
+        mutex_unlock(&dev_pm_qos_mtx);
+
         ret = pm_qos_sysfs_add_latency(dev);
         if (ret)
-                __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_LATENCY);
+                dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_LATENCY);
 
  out:
-        mutex_unlock(&dev_pm_qos_mtx);
+        mutex_unlock(&dev_pm_qos_sysfs_mtx);
         return ret;
 }
 EXPORT_SYMBOL_GPL(dev_pm_qos_expose_latency_limit);
 
 static void __dev_pm_qos_hide_latency_limit(struct device *dev)
 {
-        if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->latency_req) {
-                pm_qos_sysfs_remove_latency(dev);
+        if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->latency_req)
                 __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_LATENCY);
-        }
 }
 
 /**
@@ -619,9 +638,15 @@ static void __dev_pm_qos_hide_latency_limit(struct device *dev)
  */
 void dev_pm_qos_hide_latency_limit(struct device *dev)
 {
+        mutex_lock(&dev_pm_qos_sysfs_mtx);
+
+        pm_qos_sysfs_remove_latency(dev);
+
         mutex_lock(&dev_pm_qos_mtx);
         __dev_pm_qos_hide_latency_limit(dev);
         mutex_unlock(&dev_pm_qos_mtx);
+
+        mutex_unlock(&dev_pm_qos_sysfs_mtx);
 }
 EXPORT_SYMBOL_GPL(dev_pm_qos_hide_latency_limit);
 
@@ -649,6 +674,8 @@ int dev_pm_qos_expose_flags(struct device *dev, s32 val)
         }
 
         pm_runtime_get_sync(dev);
+        mutex_lock(&dev_pm_qos_sysfs_mtx);
+
         mutex_lock(&dev_pm_qos_mtx);
 
         if (IS_ERR_OR_NULL(dev->power.qos))
@@ -659,16 +686,19 @@ int dev_pm_qos_expose_flags(struct device *dev, s32 val)
         if (ret < 0) {
                 __dev_pm_qos_remove_request(req);
                 kfree(req);
+                mutex_unlock(&dev_pm_qos_mtx);
                 goto out;
         }
-
         dev->power.qos->flags_req = req;
+
+        mutex_unlock(&dev_pm_qos_mtx);
+
         ret = pm_qos_sysfs_add_flags(dev);
         if (ret)
-                __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_FLAGS);
+                dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_FLAGS);
 
  out:
-        mutex_unlock(&dev_pm_qos_mtx);
+        mutex_unlock(&dev_pm_qos_sysfs_mtx);
         pm_runtime_put(dev);
         return ret;
 }
@@ -676,10 +706,8 @@ EXPORT_SYMBOL_GPL(dev_pm_qos_expose_flags);
 
 static void __dev_pm_qos_hide_flags(struct device *dev)
 {
-        if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->flags_req) {
-                pm_qos_sysfs_remove_flags(dev);
+        if (!IS_ERR_OR_NULL(dev->power.qos) && dev->power.qos->flags_req)
                 __dev_pm_qos_drop_user_request(dev, DEV_PM_QOS_FLAGS);
-        }
 }
 
 /**
@@ -689,9 +717,15 @@ static void __dev_pm_qos_hide_flags(struct device *dev)
 void dev_pm_qos_hide_flags(struct device *dev)
 {
         pm_runtime_get_sync(dev);
+        mutex_lock(&dev_pm_qos_sysfs_mtx);
+
+        pm_qos_sysfs_remove_flags(dev);
+
         mutex_lock(&dev_pm_qos_mtx);
         __dev_pm_qos_hide_flags(dev);
         mutex_unlock(&dev_pm_qos_mtx);
+
+        mutex_unlock(&dev_pm_qos_sysfs_mtx);
         pm_runtime_put(dev);
 }
 EXPORT_SYMBOL_GPL(dev_pm_qos_hide_flags);
diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c
index e6732cf7c06e..79f4fca9877a 100644
--- a/drivers/base/regmap/regcache-rbtree.c
+++ b/drivers/base/regmap/regcache-rbtree.c
@@ -398,7 +398,7 @@ static int regcache_rbtree_sync(struct regmap *map, unsigned int min,
                         base = 0;
 
                 if (max < rbnode->base_reg + rbnode->blklen)
-                        end = rbnode->base_reg + rbnode->blklen - max;
+                        end = max - rbnode->base_reg + 1;
                 else
                         end = rbnode->blklen;
 
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 3d2367501fd0..d34adef1e63e 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -710,12 +710,12 @@ skip_format_initialization:
                 }
         }
 
+        regmap_debugfs_init(map, config->name);
+
         ret = regcache_init(map, config);
         if (ret != 0)
                 goto err_range;
 
-        regmap_debugfs_init(map, config->name);
-
         /* Add a devres resource for dev_get_regmap() */
         m = devres_alloc(dev_get_regmap_release, sizeof(*m), GFP_KERNEL);
         if (!m) {
@@ -943,8 +943,7 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg,
                 unsigned int ival;
                 int val_bytes = map->format.val_bytes;
                 for (i = 0; i < val_len / val_bytes; i++) {
-                        memcpy(map->work_buf, val + (i * val_bytes), val_bytes);
-                        ival = map->format.parse_val(map->work_buf);
+                        ival = map->format.parse_val(val + (i * val_bytes));
                         ret = regcache_write(map, reg + (i * map->reg_stride),
                                              ival);
                         if (ret) {
@@ -1036,6 +1035,8 @@ static int _regmap_raw_write(struct regmap *map, unsigned int reg,
                         kfree(async->work_buf);
                         kfree(async);
                 }
+
+                return ret;
         }
 
         trace_regmap_hw_write_start(map->dev, reg,
diff --git a/drivers/block/aoe/aoecmd.c b/drivers/block/aoe/aoecmd.c
index 25ef5c014fca..92b6d7c51e39 100644
--- a/drivers/block/aoe/aoecmd.c
+++ b/drivers/block/aoe/aoecmd.c
@@ -51,8 +51,9 @@ new_skb(ulong len)
 {
         struct sk_buff *skb;
 
-        skb = alloc_skb(len, GFP_ATOMIC);
+        skb = alloc_skb(len + MAX_HEADER, GFP_ATOMIC);
         if (skb) {
+                skb_reserve(skb, MAX_HEADER);
                 skb_reset_mac_header(skb);
                 skb_reset_network_header(skb);
                 skb->protocol = __constant_htons(ETH_P_AOE);
diff --git a/drivers/block/loop.c b/drivers/block/loop.c
index fe5f6403417f..2c127f9c3f3b 100644
--- a/drivers/block/loop.c
+++ b/drivers/block/loop.c
@@ -922,6 +922,11 @@ static int loop_set_fd(struct loop_device *lo, fmode_t mode,
                 lo->lo_flags |= LO_FLAGS_PARTSCAN;
         if (lo->lo_flags & LO_FLAGS_PARTSCAN)
                 ioctl_by_bdev(bdev, BLKRRPART, 0);
+
+        /* Grab the block_device to prevent its destruction after we
+         * put /dev/loopXX inode. Later in loop_clr_fd() we bdput(bdev).
+         */
+        bdgrab(bdev);
         return 0;
 
 out_clr:
@@ -1031,8 +1036,10 @@ static int loop_clr_fd(struct loop_device *lo)
         memset(lo->lo_encrypt_key, 0, LO_KEY_SIZE);
         memset(lo->lo_crypt_name, 0, LO_NAME_SIZE);
         memset(lo->lo_file_name, 0, LO_NAME_SIZE);
-        if (bdev)
+        if (bdev) {
+                bdput(bdev);
                 invalidate_bdev(bdev);
+        }
         set_capacity(lo->lo_disk, 0);
         loop_sysfs_exit(lo);
         if (bdev) {
diff --git a/drivers/char/hw_random/core.c b/drivers/char/hw_random/core.c
index 69ae5972713c..a0f7724852eb 100644
--- a/drivers/char/hw_random/core.c
+++ b/drivers/char/hw_random/core.c
@@ -380,6 +380,15 @@ void hwrng_unregister(struct hwrng *rng)
 }
 EXPORT_SYMBOL_GPL(hwrng_unregister);
 
+static void __exit hwrng_exit(void)
+{
+        mutex_lock(&rng_mutex);
+        BUG_ON(current_rng);
+        kfree(rng_buffer);
+        mutex_unlock(&rng_mutex);
+}
+
+module_exit(hwrng_exit);
 
 MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/char/virtio_console.c b/drivers/char/virtio_console.c
index e905d5f53051..ce5f3fc25d6d 100644
--- a/drivers/char/virtio_console.c
+++ b/drivers/char/virtio_console.c
@@ -149,7 +149,8 @@ struct ports_device {
         spinlock_t ports_lock;
 
         /* To protect the vq operations for the control channel */
-        spinlock_t cvq_lock;
+        spinlock_t c_ivq_lock;
+        spinlock_t c_ovq_lock;
 
         /* The current config space is stored here */
         struct virtio_console_config config;
@@ -569,11 +570,14 @@ static ssize_t __send_control_msg(struct ports_device *portdev, u32 port_id,
         vq = portdev->c_ovq;
 
         sg_init_one(sg, &cpkt, sizeof(cpkt));
+
+        spin_lock(&portdev->c_ovq_lock);
         if (virtqueue_add_buf(vq, sg, 1, 0, &cpkt, GFP_ATOMIC) == 0) {
                 virtqueue_kick(vq);
                 while (!virtqueue_get_buf(vq, &len))
                         cpu_relax();
         }
+        spin_unlock(&portdev->c_ovq_lock);
         return 0;
 }
 
@@ -1436,7 +1440,7 @@ static int add_port(struct ports_device *portdev, u32 id)
                  * rproc_serial does not want the console port, only
                  * the generic port implementation.
                  */
-                port->host_connected = port->guest_connected = true;
+                port->host_connected = true;
         else if (!use_multiport(port->portdev)) {
                 /*
                  * If we're not using multiport support,
@@ -1709,23 +1713,23 @@ static void control_work_handler(struct work_struct *work)
         portdev = container_of(work, struct ports_device, control_work);
         vq = portdev->c_ivq;
 
-        spin_lock(&portdev->cvq_lock);
+        spin_lock(&portdev->c_ivq_lock);
         while ((buf = virtqueue_get_buf(vq, &len))) {
-                spin_unlock(&portdev->cvq_lock);
+                spin_unlock(&portdev->c_ivq_lock);
 
                 buf->len = len;
                 buf->offset = 0;
 
                 handle_control_message(portdev, buf);
 
-                spin_lock(&portdev->cvq_lock);
+                spin_lock(&portdev->c_ivq_lock);
                 if (add_inbuf(portdev->c_ivq, buf) < 0) {
                         dev_warn(&portdev->vdev->dev,
                                  "Error adding buffer to queue\n");
                         free_buf(buf, false);
                 }
         }
-        spin_unlock(&portdev->cvq_lock);
+        spin_unlock(&portdev->c_ivq_lock);
 }
 
 static void out_intr(struct virtqueue *vq)
@@ -1752,13 +1756,23 @@ static void in_intr(struct virtqueue *vq)
         port->inbuf = get_inbuf(port);
 
         /*
-         * Don't queue up data when port is closed.  This condition
+         * Normally the port should not accept data when the port is
+         * closed. For generic serial ports, the host won't (shouldn't)
+         * send data till the guest is connected. But this condition
          * can be reached when a console port is not yet connected (no
-         * tty is spawned) and the host sends out data to console
-         * ports.  For generic serial ports, the host won't
-         * (shouldn't) send data till the guest is connected.
+         * tty is spawned) and the other side sends out data over the
+         * vring, or when a remote devices start sending data before
+         * the ports are opened.
+         *
+         * A generic serial port will discard data if not connected,
+         * while console ports and rproc-serial ports accepts data at
+         * any time. rproc-serial is initiated with guest_connected to
+         * false because port_fops_open expects this. Console ports are
+         * hooked up with an HVC console and is initialized with
+         * guest_connected to true.
          */
-        if (!port->guest_connected)
+
+        if (!port->guest_connected && !is_rproc_serial(port->portdev->vdev))
                 discard_port_data(port);
 
         spin_unlock_irqrestore(&port->inbuf_lock, flags);
@@ -1986,10 +2000,12 @@ static int virtcons_probe(struct virtio_device *vdev)
         if (multiport) {
                 unsigned int nr_added_bufs;
 
-                spin_lock_init(&portdev->cvq_lock);
+                spin_lock_init(&portdev->c_ivq_lock);
+                spin_lock_init(&portdev->c_ovq_lock);
                 INIT_WORK(&portdev->control_work, &control_work_handler);
 
-                nr_added_bufs = fill_queue(portdev->c_ivq, &portdev->cvq_lock);
+                nr_added_bufs = fill_queue(portdev->c_ivq,
+                                           &portdev->c_ivq_lock);
                 if (!nr_added_bufs) {
                         dev_err(&vdev->dev,
                                 "Error allocating buffers for control queue\n");
@@ -2140,7 +2156,7 @@ static int virtcons_restore(struct virtio_device *vdev)
                 return ret;
 
         if (use_multiport(portdev))
-                fill_queue(portdev->c_ivq, &portdev->cvq_lock);
+                fill_queue(portdev->c_ivq, &portdev->c_ivq_lock);
 
         list_for_each_entry(port, &portdev->ports, list) {
                 port->in_vq = portdev->in_vqs[port->id];
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index ade435820c7e..d1f1a19d4351 100644
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -221,7 +221,7 @@ void __init mmp2_clk_init(void)
 
         clk = mmp_clk_register_apbc("gpio", "vctcxo",
                                 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
-        clk_register_clkdev(clk, NULL, "pxa-gpio");
+        clk_register_clkdev(clk, NULL, "mmp2-gpio");
 
         clk = mmp_clk_register_apbc("kpc", "clk32",
                                 apbc_base + APBC_KPC, 10, 0, &clk_lock);
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index e8d036c12cbf..28b3b51c794b 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -172,7 +172,7 @@ void __init pxa168_clk_init(void)
 
         clk = mmp_clk_register_apbc("gpio", "vctcxo",
                                 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
-        clk_register_clkdev(clk, NULL, "pxa-gpio");
+        clk_register_clkdev(clk, NULL, "mmp-gpio");
 
         clk = mmp_clk_register_apbc("kpc", "clk32",
                                 apbc_base + APBC_KPC, 10, 0, &clk_lock);
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index 7048c31d6e7e..6ec05698ed38 100644
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -177,7 +177,7 @@ void __init pxa910_clk_init(void)
 
         clk = mmp_clk_register_apbc("gpio", "vctcxo",
                                 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
-        clk_register_clkdev(clk, NULL, "pxa-gpio");
+        clk_register_clkdev(clk, NULL, "mmp-gpio");
 
         clk = mmp_clk_register_apbc("kpc", "clk32",
                                 apbc_base + APBC_KPC, 10, 0, &clk_lock);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 1e2de7305362..f873dcefe0de 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -703,7 +703,7 @@ static void tegra20_pll_init(void)
         clks[pll_a_out0] = clk;
 
         /* PLLE */
-        clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL,
+        clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
                              0, 100000000, &pll_e_params,
                              0, pll_e_freq_table, NULL);
         clk_register_clkdev(clk, "pll_e", NULL);
diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c
index 4e5b7fb8927c..37d23a0f8c56 100644
--- a/drivers/cpufreq/cpufreq-cpu0.c
+++ b/drivers/cpufreq/cpufreq-cpu0.c
@@ -178,10 +178,16 @@ static struct cpufreq_driver cpu0_cpufreq_driver = {
 
 static int cpu0_cpufreq_probe(struct platform_device *pdev)
 {
-        struct device_node *np;
+        struct device_node *np, *parent;
         int ret;
 
-        for_each_child_of_node(of_find_node_by_path("/cpus"), np) {
+        parent = of_find_node_by_path("/cpus");
+        if (!parent) {
+                pr_err("failed to find OF /cpus\n");
+                return -ENOENT;
+        }
+
+        for_each_child_of_node(parent, np) {
                 if (of_get_property(np, "operating-points", NULL))
                         break;
         }
diff --git a/drivers/cpufreq/cpufreq_governor.h b/drivers/cpufreq/cpufreq_governor.h
index 46bde01eee62..cc4bd2f6838a 100644
--- a/drivers/cpufreq/cpufreq_governor.h
+++ b/drivers/cpufreq/cpufreq_governor.h
@@ -14,8 +14,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef _CPUFREQ_GOVERNER_H
-#define _CPUFREQ_GOVERNER_H
+#ifndef _CPUFREQ_GOVERNOR_H
+#define _CPUFREQ_GOVERNOR_H
 
 #include <linux/cpufreq.h>
 #include <linux/kobject.h>
@@ -175,4 +175,4 @@ bool need_load_eval(struct cpu_dbs_common_info *cdbs,
                 unsigned int sampling_rate);
 int cpufreq_governor_dbs(struct dbs_data *dbs_data,
                 struct cpufreq_policy *policy, unsigned int event);
-#endif /* _CPUFREQ_GOVERNER_H */
+#endif /* _CPUFREQ_GOVERNOR_H */
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 80b69971cf28..aeaea32bcfda 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -83,6 +83,7 @@ config INTEL_IOP_ADMA
 
 config DW_DMAC
         tristate "Synopsys DesignWare AHB DMA support"
+        depends on GENERIC_HARDIRQS
         select DMA_ENGINE
         default y if CPU_AT32AP7000
         help
diff --git a/drivers/eisa/pci_eisa.c b/drivers/eisa/pci_eisa.c
index cdae207028a7..6c3fca97d346 100644
--- a/drivers/eisa/pci_eisa.c
+++ b/drivers/eisa/pci_eisa.c
@@ -19,10 +19,10 @@
 /* There is only *one* pci_eisa device per machine, right ? */
 static struct eisa_root_device pci_eisa_root;
 
-static int __init pci_eisa_init(struct pci_dev *pdev,
-                                const struct pci_device_id *ent)
+static int __init pci_eisa_init(struct pci_dev *pdev)
 {
-        int rc;
+        int rc, i;
+        struct resource *res, *bus_res = NULL;
 
         if ((rc = pci_enable_device (pdev))) {
                 printk (KERN_ERR "pci_eisa : Could not enable device %s\n",
@@ -30,9 +30,30 @@ static int __init pci_eisa_init(struct pci_dev *pdev,
                 return rc;
         }
 
+        /*
+         * The Intel 82375 PCI-EISA bridge is a subtractive-decode PCI
+         * device, so the resources available on EISA are the same as those
+         * available on the 82375 bus.  This works the same as a PCI-PCI
+         * bridge in subtractive-decode mode (see pci_read_bridge_bases()).
+         * We assume other PCI-EISA bridges are similar.
+         *
+         * eisa_root_register() can only deal with a single io port resource,
+        *  so we use the first valid io port resource.
+         */
+        pci_bus_for_each_resource(pdev->bus, res, i)
+                if (res && (res->flags & IORESOURCE_IO)) {
+                        bus_res = res;
+                        break;
+                }
+
+        if (!bus_res) {
+                dev_err(&pdev->dev, "No resources available\n");
+                return -1;
+        }
+
         pci_eisa_root.dev              = &pdev->dev;
-        pci_eisa_root.res              = pdev->bus->resource[0];
-        pci_eisa_root.bus_base_addr    = pdev->bus->resource[0]->start;
+        pci_eisa_root.res              = bus_res;
+        pci_eisa_root.bus_base_addr    = bus_res->start;
         pci_eisa_root.slots            = EISA_MAX_SLOTS;
         pci_eisa_root.dma_mask         = pdev->dma_mask;
         dev_set_drvdata(pci_eisa_root.dev, &pci_eisa_root);
@@ -45,22 +66,26 @@ static int __init pci_eisa_init(struct pci_dev *pdev,
         return 0;
 }
 
-static struct pci_device_id pci_eisa_pci_tbl[] = {
-        { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-          PCI_CLASS_BRIDGE_EISA << 8, 0xffff00, 0 },
-        { 0, }
-};
+/*
+ * We have to call pci_eisa_init_early() before pnpacpi_init()/isapnp_init().
+ *   Otherwise pnp resource will get enabled early and could prevent eisa
+ *   to be initialized.
+ * Also need to make sure pci_eisa_init_early() is called after
+ * x86/pci_subsys_init().
+ * So need to use subsys_initcall_sync with it.
+ */
+static int __init pci_eisa_init_early(void)
+{
+        struct pci_dev *dev = NULL;
+        int ret;
 
-static struct pci_driver __refdata pci_eisa_driver = {
-        .name           = "pci_eisa",
-        .id_table       = pci_eisa_pci_tbl,
-        .probe          = pci_eisa_init,
-};
+        for_each_pci_dev(dev)
+                if ((dev->class >> 8) == PCI_CLASS_BRIDGE_EISA) {
+                        ret = pci_eisa_init(dev);
+                        if (ret)
+                                return ret;
+                }
 
-static int __init pci_eisa_init_module (void)
-{
-        return pci_register_driver (&pci_eisa_driver);
+        return 0;
 }
-
-device_initcall(pci_eisa_init_module);
-MODULE_DEVICE_TABLE(pci, pci_eisa_pci_tbl);
+subsys_initcall_sync(pci_eisa_init_early);
diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
index f9dbd503fc40..de3c317bd3e2 100644
--- a/drivers/gpio/gpio-ich.c
+++ b/drivers/gpio/gpio-ich.c
@@ -214,7 +214,7 @@ static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
          * If it can't be trusted, assume that the pin can be used as a GPIO.
          */
         if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
-                return 1;
+                return 0;
 
         return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
 }
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index b820869ca93c..06ed257c5d31 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/bitops.h>
 #include <linux/workqueue.h>
 #include <linux/gpio.h>
@@ -22,6 +23,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/slab.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/pm.h>
 #include <asm/mach/irq.h>
 
@@ -51,8 +53,7 @@ struct pl061_gpio {
         spinlock_t              lock;
 
         void __iomem            *base;
-        int                     irq_base;
-        struct irq_chip_generic *irq_gc;
+        struct irq_domain       *domain;
         struct gpio_chip        gc;
 
 #ifdef CONFIG_PM
@@ -60,6 +61,17 @@ struct pl061_gpio {
 #endif
 };
 
+static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        /*
+         * Map back to global GPIO space and request muxing, the direction
+         * parameter does not matter for this controller.
+         */
+        int gpio = chip->base + offset;
+
+        return pinctrl_request_gpio(gpio);
+}
+
 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
 {
         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
@@ -122,24 +134,20 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
 {
         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 
-        if (chip->irq_base <= 0)
-                return -EINVAL;
-
-        return chip->irq_base + offset;
+        return irq_create_mapping(chip->domain, offset);
 }
 
 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
 {
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        struct pl061_gpio *chip = gc->private;
-        int offset = d->irq - chip->irq_base;
+        struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
+        int offset = irqd_to_hwirq(d);
         unsigned long flags;
         u8 gpiois, gpioibe, gpioiev;
 
         if (offset < 0 || offset >= PL061_GPIO_NR)
                 return -EINVAL;
 
-        raw_spin_lock_irqsave(&gc->lock, flags);
+        spin_lock_irqsave(&chip->lock, flags);
 
         gpioiev = readb(chip->base + GPIOIEV);
 
@@ -168,7 +176,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
 
         writeb(gpioiev, chip->base + GPIOIEV);
 
-        raw_spin_unlock_irqrestore(&gc->lock, flags);
+        spin_unlock_irqrestore(&chip->lock, flags);
 
         return 0;
 }
@@ -192,31 +200,61 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
         chained_irq_exit(irqchip, desc);
 }
 
-static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
+static void pl061_irq_mask(struct irq_data *d)
 {
-        struct irq_chip_type *ct;
+        struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
+        u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
+        u8 gpioie;
+
+        spin_lock(&chip->lock);
+        gpioie = readb(chip->base + GPIOIE) & ~mask;
+        writeb(gpioie, chip->base + GPIOIE);
+        spin_unlock(&chip->lock);
+}
+
+static void pl061_irq_unmask(struct irq_data *d)
+{
+        struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
+        u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
+        u8 gpioie;
+
+        spin_lock(&chip->lock);
+        gpioie = readb(chip->base + GPIOIE) | mask;
+        writeb(gpioie, chip->base + GPIOIE);
+        spin_unlock(&chip->lock);
+}
 
-        chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
-                                              chip->base, handle_simple_irq);
-        chip->irq_gc->private = chip;
+static struct irq_chip pl061_irqchip = {
+        .name           = "pl061 gpio",
+        .irq_mask       = pl061_irq_mask,
+        .irq_unmask     = pl061_irq_unmask,
+        .irq_set_type   = pl061_irq_type,
+};
+
+static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
+                         irq_hw_number_t hw)
+{
+        struct pl061_gpio *chip = d->host_data;
 
-        ct = chip->irq_gc->chip_types;
-        ct->chip.irq_mask = irq_gc_mask_clr_bit;
-        ct->chip.irq_unmask = irq_gc_mask_set_bit;
-        ct->chip.irq_set_type = pl061_irq_type;
-        ct->chip.irq_set_wake = irq_gc_set_wake;
-        ct->regs.mask = GPIOIE;
+        irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
+                                      "pl061");
+        irq_set_chip_data(virq, chip);
+        irq_set_irq_type(virq, IRQ_TYPE_NONE);
 
-        irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
-                               IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
+        return 0;
 }
 
+static const struct irq_domain_ops pl061_domain_ops = {
+        .map    = pl061_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
 {
         struct device *dev = &adev->dev;
         struct pl061_platform_data *pdata = dev->platform_data;
         struct pl061_gpio *chip;
-        int ret, irq, i;
+        int ret, irq, i, irq_base;
 
         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
         if (chip == NULL)
@@ -224,24 +262,31 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
 
         if (pdata) {
                 chip->gc.base = pdata->gpio_base;
-                chip->irq_base = pdata->irq_base;
-        } else if (adev->dev.of_node) {
+                irq_base = pdata->irq_base;
+                if (irq_base <= 0)
+                        return -ENODEV;
+        } else {
                 chip->gc.base = -1;
-                chip->irq_base = 0;
-        } else
-                return -ENODEV;
+                irq_base = 0;
+        }
 
         if (!devm_request_mem_region(dev, adev->res.start,
-                                resource_size(&adev->res), "pl061"))
+                                     resource_size(&adev->res), "pl061"))
                 return -EBUSY;
 
         chip->base = devm_ioremap(dev, adev->res.start,
-                                resource_size(&adev->res));
-        if (chip->base == NULL)
+                                  resource_size(&adev->res));
+        if (!chip->base)
                 return -ENOMEM;
 
+        chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
+                                             irq_base, &pl061_domain_ops, chip);
+        if (!chip->domain)
+                return -ENODEV;
+
         spin_lock_init(&chip->lock);
 
+        chip->gc.request = pl061_gpio_request;
         chip->gc.direction_input = pl061_direction_input;
         chip->gc.direction_output = pl061_direction_output;
         chip->gc.get = pl061_get_value;
@@ -259,12 +304,6 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
         /*
          * irq_chip support
          */
-
-        if (chip->irq_base <= 0)
-                return 0;
-
-        pl061_init_gc(chip, chip->irq_base);
-
         writeb(0, chip->base + GPIOIE); /* disable irqs */
         irq = adev->irq[0];
         if (irq < 0)
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 9cc108d2b770..b80717e1ce5b 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -86,20 +86,61 @@ struct pxa_gpio_chip {
 #endif
 };
 
-enum {
+enum pxa_gpio_type {
         PXA25X_GPIO = 0,
         PXA26X_GPIO,
         PXA27X_GPIO,
         PXA3XX_GPIO,
         PXA93X_GPIO,
         MMP_GPIO = 0x10,
+        MMP2_GPIO,
+};
+
+struct pxa_gpio_id {
+        enum pxa_gpio_type      type;
+        int                     gpio_nums;
 };
 
 static DEFINE_SPINLOCK(gpio_lock);
 static struct pxa_gpio_chip *pxa_gpio_chips;
-static int gpio_type;
+static enum pxa_gpio_type gpio_type;
 static void __iomem *gpio_reg_base;
 
+static struct pxa_gpio_id pxa25x_id = {
+        .type           = PXA25X_GPIO,
+        .gpio_nums      = 85,
+};
+
+static struct pxa_gpio_id pxa26x_id = {
+        .type           = PXA26X_GPIO,
+        .gpio_nums      = 90,
+};
+
+static struct pxa_gpio_id pxa27x_id = {
+        .type           = PXA27X_GPIO,
+        .gpio_nums      = 121,
+};
+
+static struct pxa_gpio_id pxa3xx_id = {
+        .type           = PXA3XX_GPIO,
+        .gpio_nums      = 128,
+};
+
+static struct pxa_gpio_id pxa93x_id = {
+        .type           = PXA93X_GPIO,
+        .gpio_nums      = 192,
+};
+
+static struct pxa_gpio_id mmp_id = {
+        .type           = MMP_GPIO,
+        .gpio_nums      = 128,
+};
+
+static struct pxa_gpio_id mmp2_id = {
+        .type           = MMP2_GPIO,
+        .gpio_nums      = 192,
+};
+
 #define for_each_gpio_chip(i, c)                        \
         for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
 
@@ -432,47 +473,39 @@ static struct irq_chip pxa_muxed_gpio_chip = {
         .irq_set_wake   = pxa_gpio_set_wake,
 };
 
-static int pxa_gpio_nums(void)
+static int pxa_gpio_nums(struct platform_device *pdev)
 {
+        const struct platform_device_id *id = platform_get_device_id(pdev);
+        struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
         int count = 0;
 
-#ifdef CONFIG_ARCH_PXA
-        if (cpu_is_pxa25x()) {
-#ifdef CONFIG_CPU_PXA26x
-                count = 89;
-                gpio_type = PXA26X_GPIO;
-#elif defined(CONFIG_PXA25x)
-                count = 84;
-                gpio_type = PXA26X_GPIO;
-#endif /* CONFIG_CPU_PXA26x */
-        } else if (cpu_is_pxa27x()) {
-                count = 120;
-                gpio_type = PXA27X_GPIO;
-        } else if (cpu_is_pxa93x()) {
-                count = 191;
-                gpio_type = PXA93X_GPIO;
-        } else if (cpu_is_pxa3xx()) {
-                count = 127;
-                gpio_type = PXA3XX_GPIO;
-        }
-#endif /* CONFIG_ARCH_PXA */
-
-#ifdef CONFIG_ARCH_MMP
-        if (cpu_is_pxa168() || cpu_is_pxa910()) {
-                count = 127;
-                gpio_type = MMP_GPIO;
-        } else if (cpu_is_mmp2()) {
-                count = 191;
-                gpio_type = MMP_GPIO;
+        switch (pxa_id->type) {
+        case PXA25X_GPIO:
+        case PXA26X_GPIO:
+        case PXA27X_GPIO:
+        case PXA3XX_GPIO:
+        case PXA93X_GPIO:
+        case MMP_GPIO:
+        case MMP2_GPIO:
+                gpio_type = pxa_id->type;
+                count = pxa_id->gpio_nums - 1;
+                break;
+        default:
+                count = -EINVAL;
+                break;
         }
-#endif /* CONFIG_ARCH_MMP */
         return count;
 }
 
 #ifdef CONFIG_OF
 static struct of_device_id pxa_gpio_dt_ids[] = {
-        { .compatible = "mrvl,pxa-gpio" },
-        { .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO },
+        { .compatible = "intel,pxa25x-gpio",    .data = &pxa25x_id, },
+        { .compatible = "intel,pxa26x-gpio",    .data = &pxa26x_id, },
+        { .compatible = "intel,pxa27x-gpio",    .data = &pxa27x_id, },
+        { .compatible = "intel,pxa3xx-gpio",    .data = &pxa3xx_id, },
+        { .compatible = "marvell,pxa93x-gpio",  .data = &pxa93x_id, },
+        { .compatible = "marvell,mmp-gpio",     .data = &mmp_id, },
+        { .compatible = "marvell,mmp2-gpio",    .data = &mmp2_id, },
         {}
 };
 
@@ -492,16 +525,18 @@ const struct irq_domain_ops pxa_irq_domain_ops = {
 
 static int pxa_gpio_probe_dt(struct platform_device *pdev)
 {
-        int ret, nr_banks, nr_gpios;
+        int ret, nr_gpios;
         struct device_node *prev, *next, *np = pdev->dev.of_node;
         const struct of_device_id *of_id =
                                 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
+        const struct pxa_gpio_id *gpio_id;
 
-        if (!of_id) {
+        if (!of_id || !of_id->data) {
                 dev_err(&pdev->dev, "Failed to find gpio controller\n");
                 return -EFAULT;
         }
-        gpio_type = (int)of_id->data;
+        gpio_id = of_id->data;
+        gpio_type = gpio_id->type;
 
         next = of_get_next_child(np, NULL);
         prev = next;
@@ -510,14 +545,8 @@ static int pxa_gpio_probe_dt(struct platform_device *pdev)
                 ret = -EINVAL;
                 goto err;
         }
-        for (nr_banks = 1; ; nr_banks++) {
-                next = of_get_next_child(np, prev);
-                if (!next)
-                        break;
-                prev = next;
-        }
         of_node_put(prev);
-        nr_gpios = nr_banks << 5;
+        nr_gpios = gpio_id->gpio_nums;
         pxa_last_gpio = nr_gpios - 1;
 
         irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
@@ -546,19 +575,18 @@ static int pxa_gpio_probe(struct platform_device *pdev)
         int gpio, irq, ret, use_of = 0;
         int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
 
-        ret = pxa_gpio_probe_dt(pdev);
-        if (ret < 0) {
-                pxa_last_gpio = pxa_gpio_nums();
-#ifdef CONFIG_ARCH_PXA
-                if (gpio_is_pxa_type(gpio_type))
-                        irq_base = PXA_GPIO_TO_IRQ(0);
-#endif
-#ifdef CONFIG_ARCH_MMP
-                if (gpio_is_mmp_type(gpio_type))
-                        irq_base = MMP_GPIO_TO_IRQ(0);
-#endif
+        info = dev_get_platdata(&pdev->dev);
+        if (info) {
+                irq_base = info->irq_base;
+                if (irq_base <= 0)
+                        return -EINVAL;
+                pxa_last_gpio = pxa_gpio_nums(pdev);
         } else {
+                irq_base = 0;
                 use_of = 1;
+                ret = pxa_gpio_probe_dt(pdev);
+                if (ret < 0)
+                        return -EINVAL;
         }
 
         if (!pxa_last_gpio)
@@ -595,7 +623,6 @@ static int pxa_gpio_probe(struct platform_device *pdev)
         }
 
         /* Initialize GPIO chips */
-        info = dev_get_platdata(&pdev->dev);
         pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
 
         /* clear all GPIO edge detects */
@@ -635,12 +662,24 @@ static int pxa_gpio_probe(struct platform_device *pdev)
         return 0;
 }
 
+static const struct platform_device_id gpio_id_table[] = {
+        { "pxa25x-gpio",        (unsigned long)&pxa25x_id },
+        { "pxa26x-gpio",        (unsigned long)&pxa26x_id },
+        { "pxa27x-gpio",        (unsigned long)&pxa27x_id },
+        { "pxa3xx-gpio",        (unsigned long)&pxa3xx_id },
+        { "pxa93x-gpio",        (unsigned long)&pxa93x_id },
+        { "mmp-gpio",           (unsigned long)&mmp_id },
+        { "mmp2-gpio",          (unsigned long)&mmp2_id },
+        { },
+};
+
 static struct platform_driver pxa_gpio_driver = {
         .probe          = pxa_gpio_probe,
         .driver         = {
                 .name   = "pxa-gpio",
                 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
         },
+        .id_table       = gpio_id_table,
 };
 module_platform_driver(pxa_gpio_driver);
 
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index 770476a9da87..3ce5bc38ac31 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -307,11 +307,15 @@ static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
         .xlate = irq_domain_xlate_twocell,
 };
 
-static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
+static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
+                struct device_node *np)
 {
-        int base = stmpe_gpio->irq_base;
+        int base = 0;
 
-        stmpe_gpio->domain = irq_domain_add_simple(NULL,
+        if (!np)
+                base = stmpe_gpio->irq_base;
+
+        stmpe_gpio->domain = irq_domain_add_simple(np,
                                 stmpe_gpio->chip.ngpio, base,
                                 &stmpe_gpio_irq_simple_ops, stmpe_gpio);
         if (!stmpe_gpio->domain) {
@@ -346,6 +350,9 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
         stmpe_gpio->chip = template_chip;
         stmpe_gpio->chip.ngpio = stmpe->num_gpios;
         stmpe_gpio->chip.dev = &pdev->dev;
+#ifdef CONFIG_OF
+        stmpe_gpio->chip.of_node = np;
+#endif
         stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
 
         if (pdata)
@@ -366,7 +373,7 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
                 goto out_free;
 
         if (irq >= 0) {
-                ret = stmpe_gpio_irq_init(stmpe_gpio);
+                ret = stmpe_gpio_irq_init(stmpe_gpio, np);
                 if (ret)
                         goto out_disable;
 
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index 5150df6cba08..465f4ca57e80 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -203,22 +203,11 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
                 if (!pctldev)
                         break;
 
-                /*
-                 * This assumes that the n GPIO pins are consecutive in the
-                 * GPIO number space, and that the pins are also consecutive
-                 * in their local number space. Currently it is not possible
-                 * to add different ranges for one and the same GPIO chip,
-                 * as the code assumes that we have one consecutive range
-                 * on both, mapping 1-to-1.
-                 *
-                 * TODO: make the OF bindings handle multiple sparse ranges
-                 * on the same GPIO chip.
-                 */
                 ret = gpiochip_add_pin_range(chip,
                                              pinctrl_dev_get_devname(pctldev),
-                                             0, /* offset in gpiochip */
                                              pinspec.args[0],
-                                             pinspec.args[1]);
+                                             pinspec.args[1],
+                                             pinspec.args[2]);
 
                 if (ret)
                         break;
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 792c3e3795ca..dd64a06dc5b4 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2326,7 +2326,6 @@ int drm_mode_addfb(struct drm_device *dev,
         fb = dev->mode_config.funcs->fb_create(dev, file_priv, &r);
         if (IS_ERR(fb)) {
                 DRM_DEBUG_KMS("could not create framebuffer\n");
-                drm_modeset_unlock_all(dev);
                 return PTR_ERR(fb);
         }
 
@@ -2506,7 +2505,6 @@ int drm_mode_addfb2(struct drm_device *dev,
         fb = dev->mode_config.funcs->fb_create(dev, file_priv, r);
         if (IS_ERR(fb)) {
                 DRM_DEBUG_KMS("could not create framebuffer\n");
-                drm_modeset_unlock_all(dev);
                 return PTR_ERR(fb);
         }
 
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index 13fdcd10a605..429e07d0b0f1 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -123,6 +123,7 @@ int drm_open(struct inode *inode, struct file *filp)
         int retcode = 0;
         int need_setup = 0;
         struct address_space *old_mapping;
+        struct address_space *old_imapping;
 
         minor = idr_find(&drm_minors_idr, minor_id);
         if (!minor)
@@ -137,6 +138,7 @@ int drm_open(struct inode *inode, struct file *filp)
         if (!dev->open_count++)
                 need_setup = 1;
         mutex_lock(&dev->struct_mutex);
+        old_imapping = inode->i_mapping;
         old_mapping = dev->dev_mapping;
         if (old_mapping == NULL)
                 dev->dev_mapping = &inode->i_data;
@@ -159,8 +161,8 @@ int drm_open(struct inode *inode, struct file *filp)
 
 err_undo:
         mutex_lock(&dev->struct_mutex);
-        filp->f_mapping = old_mapping;
-        inode->i_mapping = old_mapping;
+        filp->f_mapping = old_imapping;
+        inode->i_mapping = old_imapping;
         iput(container_of(dev->dev_mapping, struct inode, i_data));
         dev->dev_mapping = old_mapping;
         mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 3b11ab0fbc96..9a48e1a2d417 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -57,7 +57,7 @@ eb_create(struct drm_i915_gem_execbuffer2 *args)
         if (eb == NULL) {
                 int size = args->buffer_count;
                 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
-                BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head)));
+                BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
                 while (count > 2*size)
                         count >>= 1;
                 eb = kzalloc(count*sizeof(struct hlist_head) +
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 32a3693905ec..1ce45a0a2d3e 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -45,6 +45,9 @@
 
 struct intel_crt {
         struct intel_encoder base;
+        /* DPMS state is stored in the connector, which we need in the
+         * encoder's enable/disable callbacks */
+        struct intel_connector *connector;
         bool force_hotplug_required;
         u32 adpa_reg;
 };
@@ -81,29 +84,6 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
         return true;
 }
 
-static void intel_disable_crt(struct intel_encoder *encoder)
-{
-        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-        struct intel_crt *crt = intel_encoder_to_crt(encoder);
-        u32 temp;
-
-        temp = I915_READ(crt->adpa_reg);
-        temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
-        temp &= ~ADPA_DAC_ENABLE;
-        I915_WRITE(crt->adpa_reg, temp);
-}
-
-static void intel_enable_crt(struct intel_encoder *encoder)
-{
-        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-        struct intel_crt *crt = intel_encoder_to_crt(encoder);
-        u32 temp;
-
-        temp = I915_READ(crt->adpa_reg);
-        temp |= ADPA_DAC_ENABLE;
-        I915_WRITE(crt->adpa_reg, temp);
-}
-
 /* Note: The caller is required to filter out dpms modes not supported by the
  * platform. */
 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
@@ -135,6 +115,19 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
         I915_WRITE(crt->adpa_reg, temp);
 }
 
+static void intel_disable_crt(struct intel_encoder *encoder)
+{
+        intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void intel_enable_crt(struct intel_encoder *encoder)
+{
+        struct intel_crt *crt = intel_encoder_to_crt(encoder);
+
+        intel_crt_set_dpms(encoder, crt->connector->base.dpms);
+}
+
+
 static void intel_crt_dpms(struct drm_connector *connector, int mode)
 {
         struct drm_device *dev = connector->dev;
@@ -746,6 +739,7 @@ void intel_crt_init(struct drm_device *dev)
         }
 
         connector = &intel_connector->base;
+        crt->connector = intel_connector;
         drm_connector_init(dev, &intel_connector->base,
                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d7d4afe01341..8fc93f90a7cd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2559,12 +2559,15 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
 {
         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
         struct intel_dp *intel_dp = &intel_dig_port->dp;
+        struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
         i2c_del_adapter(&intel_dp->adapter);
         drm_encoder_cleanup(encoder);
         if (is_edp(intel_dp)) {
                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
+                mutex_lock(&dev->mode_config.mutex);
                 ironlake_panel_vdd_off_sync(intel_dp);
+                mutex_unlock(&dev->mode_config.mutex);
         }
         kfree(intel_dig_port);
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
index e816f06637a7..0e2c1a4f1659 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
@@ -248,6 +248,22 @@ nouveau_bios_shadow_pci(struct nouveau_bios *bios)
         }
 }
 
+static void
+nouveau_bios_shadow_platform(struct nouveau_bios *bios)
+{
+        struct pci_dev *pdev = nv_device(bios)->pdev;
+        size_t size;
+
+        void __iomem *rom = pci_platform_rom(pdev, &size);
+        if (rom && size) {
+                bios->data = kmalloc(size, GFP_KERNEL);
+                if (bios->data) {
+                        memcpy_fromio(bios->data, rom, size);
+                        bios->size = size;
+                }
+        }
+}
+
 static int
 nouveau_bios_score(struct nouveau_bios *bios, const bool writeable)
 {
@@ -288,6 +304,7 @@ nouveau_bios_shadow(struct nouveau_bios *bios)
                 { "PROM", nouveau_bios_shadow_prom, false, 0, 0, NULL },
                 { "ACPI", nouveau_bios_shadow_acpi, true, 0, 0, NULL },
                 { "PCIROM", nouveau_bios_shadow_pci, true, 0, 0, NULL },
+                { "PLATFORM", nouveau_bios_shadow_platform, true, 0, 0, NULL },
                 {}
         };
         struct methods *mthd, *best;
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index 3b6dc883e150..5eb3e0da7c6e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -391,7 +391,7 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS)
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct nouveau_device *device = nv_device(drm->device);
         struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev);
-        struct nouveau_abi16_chan *chan, *temp;
+        struct nouveau_abi16_chan *chan = NULL, *temp;
         struct nouveau_abi16_ntfy *ntfy;
         struct nouveau_object *object;
         struct nv_dma_class args = {};
@@ -404,10 +404,11 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS)
         if (unlikely(nv_device(abi16->device)->card_type >= NV_C0))
                 return nouveau_abi16_put(abi16, -EINVAL);
 
-        list_for_each_entry_safe(chan, temp, &abi16->channels, head) {
-                if (chan->chan->handle == (NVDRM_CHAN | info->channel))
+        list_for_each_entry(temp, &abi16->channels, head) {
+                if (temp->chan->handle == (NVDRM_CHAN | info->channel)) {
+                        chan = temp;
                         break;
-                chan = NULL;
+                }
         }
 
         if (!chan)
@@ -459,17 +460,18 @@ nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS)
 {
         struct drm_nouveau_gpuobj_free *fini = data;
         struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev);
-        struct nouveau_abi16_chan *chan, *temp;
+        struct nouveau_abi16_chan *chan = NULL, *temp;
         struct nouveau_abi16_ntfy *ntfy;
         int ret;
 
         if (unlikely(!abi16))
                 return -ENOMEM;
 
-        list_for_each_entry_safe(chan, temp, &abi16->channels, head) {
-                if (chan->chan->handle == (NVDRM_CHAN | fini->channel))
+        list_for_each_entry(temp, &abi16->channels, head) {
+                if (temp->chan->handle == (NVDRM_CHAN | fini->channel)) {
+                        chan = temp;
                         break;
-                chan = NULL;
+                }
         }
 
         if (!chan)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index d1099365bfc1..c95decf543e9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -72,11 +72,25 @@ module_param_named(modeset, nouveau_modeset, int, 0400);
 static struct drm_driver driver;
 
 static int
+nouveau_drm_vblank_handler(struct nouveau_eventh *event, int head)
+{
+        struct nouveau_drm *drm =
+                container_of(event, struct nouveau_drm, vblank[head]);
+        drm_handle_vblank(drm->dev, head);
+        return NVKM_EVENT_KEEP;
+}
+
+static int
 nouveau_drm_vblank_enable(struct drm_device *dev, int head)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct nouveau_disp *pdisp = nouveau_disp(drm->device);
-        nouveau_event_get(pdisp->vblank, head, &drm->vblank);
+
+        if (WARN_ON_ONCE(head > ARRAY_SIZE(drm->vblank)))
+                return -EIO;
+        WARN_ON_ONCE(drm->vblank[head].func);
+        drm->vblank[head].func = nouveau_drm_vblank_handler;
+        nouveau_event_get(pdisp->vblank, head, &drm->vblank[head]);
         return 0;
 }
 
@@ -85,16 +99,11 @@ nouveau_drm_vblank_disable(struct drm_device *dev, int head)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct nouveau_disp *pdisp = nouveau_disp(drm->device);
-        nouveau_event_put(pdisp->vblank, head, &drm->vblank);
-}
-
-static int
-nouveau_drm_vblank_handler(struct nouveau_eventh *event, int head)
-{
-        struct nouveau_drm *drm =
-                container_of(event, struct nouveau_drm, vblank);
-        drm_handle_vblank(drm->dev, head);
-        return NVKM_EVENT_KEEP;
+        if (drm->vblank[head].func)
+                nouveau_event_put(pdisp->vblank, head, &drm->vblank[head]);
+        else
+                WARN_ON_ONCE(1);
+        drm->vblank[head].func = NULL;
 }
 
 static u64
@@ -292,7 +301,6 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
 
         dev->dev_private = drm;
         drm->dev = dev;
-        drm->vblank.func = nouveau_drm_vblank_handler;
 
         INIT_LIST_HEAD(&drm->clients);
         spin_lock_init(&drm->tile.lock);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h
index b25df374c901..9c39bafbef2c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.h
@@ -113,7 +113,7 @@ struct nouveau_drm {
         struct nvbios vbios;
         struct nouveau_display *display;
         struct backlight_device *backlight;
-        struct nouveau_eventh vblank;
+        struct nouveau_eventh vblank[4];
 
         /* power management */
         struct nouveau_pm *pm;
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index b8015913d382..fa3c56fba294 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -99,6 +99,29 @@ static bool radeon_read_bios(struct radeon_device *rdev)
         return true;
 }
 
+static bool radeon_read_platform_bios(struct radeon_device *rdev)
+{
+        uint8_t __iomem *bios;
+        size_t size;
+
+        rdev->bios = NULL;
+
+        bios = pci_platform_rom(rdev->pdev, &size);
+        if (!bios) {
+                return false;
+        }
+
+        if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
+                return false;
+        }
+        rdev->bios = kmemdup(bios, size, GFP_KERNEL);
+        if (rdev->bios == NULL) {
+                return false;
+        }
+
+        return true;
+}
+
 #ifdef CONFIG_ACPI
 /* ATRM is used to get the BIOS on the discrete cards in
  * dual-gpu systems.
@@ -620,6 +643,9 @@ bool radeon_get_bios(struct radeon_device *rdev)
         if (r == false) {
                 r = radeon_read_disabled_bios(rdev);
         }
+        if (r == false) {
+                r = radeon_read_platform_bios(rdev);
+        }
         if (r == false || rdev->bios == NULL) {
                 DRM_ERROR("Unable to locate a BIOS ROM\n");
                 rdev->bios = NULL;
diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c
index 512b01c04ea7..aa341d135867 100644
--- a/drivers/hid/hid-core.c
+++ b/drivers/hid/hid-core.c
@@ -2077,7 +2077,6 @@ static const struct hid_device_id hid_ignore_list[] = {
         { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_HYBRID) },
         { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_HEATCONTROL) },
         { HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_BEATPAD) },
-        { HID_USB_DEVICE(USB_VENDOR_ID_MASTERKIT, USB_DEVICE_ID_MASTERKIT_MA901RADIO) },
         { HID_USB_DEVICE(USB_VENDOR_ID_MCC, USB_DEVICE_ID_MCC_PMD1024LS) },
         { HID_USB_DEVICE(USB_VENDOR_ID_MCC, USB_DEVICE_ID_MCC_PMD1208LS) },
         { HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_PICKIT1) },
@@ -2244,6 +2243,18 @@ bool hid_ignore(struct hid_device *hdev)
                      hdev->product <= USB_DEVICE_ID_VELLEMAN_K8061_LAST))
                         return true;
                 break;
+        case USB_VENDOR_ID_ATMEL_V_USB:
+                /* Masterkit MA901 usb radio based on Atmel tiny85 chip and
+                 * it has the same USB ID as many Atmel V-USB devices. This
+                 * usb radio is handled by radio-ma901.c driver so we want
+                 * ignore the hid. Check the name, bus, product and ignore
+                 * if we have MA901 usb radio.
+                 */
+                if (hdev->product == USB_DEVICE_ID_ATMEL_V_USB &&
+                        hdev->bus == BUS_USB &&
+                        strncmp(hdev->name, "www.masterkit.ru MA901", 22) == 0)
+                        return true;
+                break;
         }
 
         if (hdev->type == HID_TYPE_USBMOUSE &&
diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index c4388776f4e4..5309fd5eb0eb 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -158,6 +158,8 @@
 #define USB_VENDOR_ID_ATMEL             0x03eb
 #define USB_DEVICE_ID_ATMEL_MULTITOUCH  0x211c
 #define USB_DEVICE_ID_ATMEL_MXT_DIGITIZER       0x2118
+#define USB_VENDOR_ID_ATMEL_V_USB       0x16c0
+#define USB_DEVICE_ID_ATMEL_V_USB       0x05df
 
 #define USB_VENDOR_ID_AUREAL            0x0755
 #define USB_DEVICE_ID_AUREAL_W01RN      0x2626
@@ -557,9 +559,6 @@
 #define USB_VENDOR_ID_MADCATZ           0x0738
 #define USB_DEVICE_ID_MADCATZ_BEATPAD   0x4540
 
-#define USB_VENDOR_ID_MASTERKIT                 0x16c0
-#define USB_DEVICE_ID_MASTERKIT_MA901RADIO      0x05df
-
 #define USB_VENDOR_ID_MCC               0x09db
 #define USB_DEVICE_ID_MCC_PMD1024LS     0x0076
 #define USB_DEVICE_ID_MCC_PMD1208LS     0x007a
diff --git a/drivers/hid/hid-magicmouse.c b/drivers/hid/hid-magicmouse.c
index f7f113ba083e..a8ce44296cfd 100644
--- a/drivers/hid/hid-magicmouse.c
+++ b/drivers/hid/hid-magicmouse.c
@@ -462,6 +462,21 @@ static int magicmouse_input_mapping(struct hid_device *hdev,
         return 0;
 }
 
+static void magicmouse_input_configured(struct hid_device *hdev,
+                struct hid_input *hi)
+
+{
+        struct magicmouse_sc *msc = hid_get_drvdata(hdev);
+
+        int ret = magicmouse_setup_input(msc->input, hdev);
+        if (ret) {
+                hid_err(hdev, "magicmouse setup input failed (%d)\n", ret);
+                /* clean msc->input to notify probe() of the failure */
+                msc->input = NULL;
+        }
+}
+
+
 static int magicmouse_probe(struct hid_device *hdev,
         const struct hid_device_id *id)
 {
@@ -493,15 +508,10 @@ static int magicmouse_probe(struct hid_device *hdev,
                 goto err_free;
         }
 
-        /* We do this after hid-input is done parsing reports so that
-         * hid-input uses the most natural button and axis IDs.
-         */
-        if (msc->input) {
-                ret = magicmouse_setup_input(msc->input, hdev);
-                if (ret) {
-                        hid_err(hdev, "magicmouse setup input failed (%d)\n", ret);
-                        goto err_stop_hw;
-                }
+        if (!msc->input) {
+                hid_err(hdev, "magicmouse input not registered\n");
+                ret = -ENOMEM;
+                goto err_stop_hw;
         }
 
         if (id->product == USB_DEVICE_ID_APPLE_MAGICMOUSE)
@@ -568,6 +578,7 @@ static struct hid_driver magicmouse_driver = {
         .remove = magicmouse_remove,
         .raw_event = magicmouse_raw_event,
         .input_mapping = magicmouse_input_mapping,
+        .input_configured = magicmouse_input_configured,
 };
 module_hid_driver(magicmouse_driver);
 
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 0ceb6e1b0f65..e3085c487ace 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -182,7 +182,6 @@ static int dw_i2c_probe(struct platform_device *pdev)
         adap->algo = &i2c_dw_algo;
         adap->dev.parent = &pdev->dev;
         adap->dev.of_node = pdev->dev.of_node;
-        ACPI_HANDLE_SET(&adap->dev, ACPI_HANDLE(&pdev->dev));
 
         r = i2c_add_numbered_adapter(adap);
         if (r) {
diff --git a/drivers/infiniband/hw/qib/qib_sd7220.c b/drivers/infiniband/hw/qib/qib_sd7220.c
index 08a6c6d39e56..911205d3d5a0 100644
--- a/drivers/infiniband/hw/qib/qib_sd7220.c
+++ b/drivers/infiniband/hw/qib/qib_sd7220.c
@@ -44,7 +44,7 @@
 #include "qib.h"
 #include "qib_7220.h"
 
-#define SD7220_FW_NAME "intel/sd7220.fw"
+#define SD7220_FW_NAME "qlogic/sd7220.fw"
 MODULE_FIRMWARE(SD7220_FW_NAME);
 
 /*
diff --git a/drivers/md/dm-cache-target.c b/drivers/md/dm-cache-target.c
index 66120bd46d15..10744091e6ca 100644
--- a/drivers/md/dm-cache-target.c
+++ b/drivers/md/dm-cache-target.c
@@ -6,6 +6,7 @@
 
 #include "dm.h"
 #include "dm-bio-prison.h"
+#include "dm-bio-record.h"
 #include "dm-cache-metadata.h"
 
 #include <linux/dm-io.h>
@@ -201,10 +202,15 @@ struct per_bio_data {
         unsigned req_nr:2;
         struct dm_deferred_entry *all_io_entry;
 
-        /* writethrough fields */
+        /*
+         * writethrough fields.  These MUST remain at the end of this
+         * structure and the 'cache' member must be the first as it
+         * is used to determine the offsetof the writethrough fields.
+         */
         struct cache *cache;
         dm_cblock_t cblock;
         bio_end_io_t *saved_bi_end_io;
+        struct dm_bio_details bio_details;
 };
 
 struct dm_cache_migration {
@@ -513,16 +519,28 @@ static void save_stats(struct cache *cache)
 /*----------------------------------------------------------------
  * Per bio data
  *--------------------------------------------------------------*/
-static struct per_bio_data *get_per_bio_data(struct bio *bio)
+
+/*
+ * If using writeback, leave out struct per_bio_data's writethrough fields.
+ */
+#define PB_DATA_SIZE_WB (offsetof(struct per_bio_data, cache))
+#define PB_DATA_SIZE_WT (sizeof(struct per_bio_data))
+
+static size_t get_per_bio_data_size(struct cache *cache)
+{
+        return cache->features.write_through ? PB_DATA_SIZE_WT : PB_DATA_SIZE_WB;
+}
+
+static struct per_bio_data *get_per_bio_data(struct bio *bio, size_t data_size)
 {
-        struct per_bio_data *pb = dm_per_bio_data(bio, sizeof(struct per_bio_data));
+        struct per_bio_data *pb = dm_per_bio_data(bio, data_size);
         BUG_ON(!pb);
         return pb;
 }
 
-static struct per_bio_data *init_per_bio_data(struct bio *bio)
+static struct per_bio_data *init_per_bio_data(struct bio *bio, size_t data_size)
 {
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        struct per_bio_data *pb = get_per_bio_data(bio, data_size);
 
         pb->tick = false;
         pb->req_nr = dm_bio_get_target_bio_nr(bio);
@@ -556,7 +574,8 @@ static void remap_to_cache(struct cache *cache, struct bio *bio,
 static void check_if_tick_bio_needed(struct cache *cache, struct bio *bio)
 {
         unsigned long flags;
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        size_t pb_data_size = get_per_bio_data_size(cache);
+        struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size);
 
         spin_lock_irqsave(&cache->lock, flags);
         if (cache->need_tick_bio &&
@@ -635,7 +654,7 @@ static void defer_writethrough_bio(struct cache *cache, struct bio *bio)
 
 static void writethrough_endio(struct bio *bio, int err)
 {
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        struct per_bio_data *pb = get_per_bio_data(bio, PB_DATA_SIZE_WT);
         bio->bi_end_io = pb->saved_bi_end_io;
 
         if (err) {
@@ -643,6 +662,7 @@ static void writethrough_endio(struct bio *bio, int err)
                 return;
         }
 
+        dm_bio_restore(&pb->bio_details, bio);
         remap_to_cache(pb->cache, bio, pb->cblock);
 
         /*
@@ -662,11 +682,12 @@ static void writethrough_endio(struct bio *bio, int err)
 static void remap_to_origin_then_cache(struct cache *cache, struct bio *bio,
                                        dm_oblock_t oblock, dm_cblock_t cblock)
 {
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        struct per_bio_data *pb = get_per_bio_data(bio, PB_DATA_SIZE_WT);
 
         pb->cache = cache;
         pb->cblock = cblock;
         pb->saved_bi_end_io = bio->bi_end_io;
+        dm_bio_record(&pb->bio_details, bio);
         bio->bi_end_io = writethrough_endio;
 
         remap_to_origin_clear_discard(pb->cache, bio, oblock);
@@ -1035,7 +1056,8 @@ static void defer_bio(struct cache *cache, struct bio *bio)
 
 static void process_flush_bio(struct cache *cache, struct bio *bio)
 {
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        size_t pb_data_size = get_per_bio_data_size(cache);
+        struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size);
 
         BUG_ON(bio->bi_size);
         if (!pb->req_nr)
@@ -1107,7 +1129,8 @@ static void process_bio(struct cache *cache, struct prealloc *structs,
         dm_oblock_t block = get_bio_block(cache, bio);
         struct dm_bio_prison_cell *cell_prealloc, *old_ocell, *new_ocell;
         struct policy_result lookup_result;
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        size_t pb_data_size = get_per_bio_data_size(cache);
+        struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size);
         bool discarded_block = is_discarded_oblock(cache, block);
         bool can_migrate = discarded_block || spare_migration_bandwidth(cache);
 
@@ -1881,7 +1904,6 @@ static int cache_create(struct cache_args *ca, struct cache **result)
 
         cache->ti = ca->ti;
         ti->private = cache;
-        ti->per_bio_data_size = sizeof(struct per_bio_data);
         ti->num_flush_bios = 2;
         ti->flush_supported = true;
 
@@ -1890,6 +1912,7 @@ static int cache_create(struct cache_args *ca, struct cache **result)
         ti->discard_zeroes_data_unsupported = true;
 
         memcpy(&cache->features, &ca->features, sizeof(cache->features));
+        ti->per_bio_data_size = get_per_bio_data_size(cache);
 
         cache->callbacks.congested_fn = cache_is_congested;
         dm_table_add_target_callbacks(ti->table, &cache->callbacks);
@@ -2092,6 +2115,7 @@ static int cache_map(struct dm_target *ti, struct bio *bio)
 
         int r;
         dm_oblock_t block = get_bio_block(cache, bio);
+        size_t pb_data_size = get_per_bio_data_size(cache);
         bool can_migrate = false;
         bool discarded_block;
         struct dm_bio_prison_cell *cell;
@@ -2108,7 +2132,7 @@ static int cache_map(struct dm_target *ti, struct bio *bio)
                 return DM_MAPIO_REMAPPED;
         }
 
-        pb = init_per_bio_data(bio);
+        pb = init_per_bio_data(bio, pb_data_size);
 
         if (bio->bi_rw & (REQ_FLUSH | REQ_FUA | REQ_DISCARD)) {
                 defer_bio(cache, bio);
@@ -2193,7 +2217,8 @@ static int cache_end_io(struct dm_target *ti, struct bio *bio, int error)
 {
         struct cache *cache = ti->private;
         unsigned long flags;
-        struct per_bio_data *pb = get_per_bio_data(bio);
+        size_t pb_data_size = get_per_bio_data_size(cache);
+        struct per_bio_data *pb = get_per_bio_data(bio, pb_data_size);
 
         if (pb->tick) {
                 policy_tick(cache->policy);
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 05d7b6333461..a0639e779973 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -204,7 +204,7 @@ config VIDEO_SAMSUNG_EXYNOS_GSC
 
 config VIDEO_SH_VEU
         tristate "SuperH VEU mem2mem video processing driver"
-        depends on VIDEO_DEV && VIDEO_V4L2
+        depends on VIDEO_DEV && VIDEO_V4L2 && GENERIC_HARDIRQS
         select VIDEOBUF2_DMA_CONTIG
         select V4L2_MEM2MEM_DEV
         help
diff --git a/drivers/media/radio/radio-ma901.c b/drivers/media/radio/radio-ma901.c
index c61f590029ad..348dafc0318a 100644
--- a/drivers/media/radio/radio-ma901.c
+++ b/drivers/media/radio/radio-ma901.c
@@ -347,9 +347,20 @@ static void usb_ma901radio_release(struct v4l2_device *v4l2_dev)
 static int usb_ma901radio_probe(struct usb_interface *intf,
                                 const struct usb_device_id *id)
 {
+        struct usb_device *dev = interface_to_usbdev(intf);
         struct ma901radio_device *radio;
         int retval = 0;
 
+        /* Masterkit MA901 usb radio has the same USB ID as many others
+         * Atmel V-USB devices. Let's make additional checks to be sure
+         * that this is our device.
+         */
+
+        if (dev->product && dev->manufacturer &&
+                (strncmp(dev->product, "MA901", 5) != 0
+                || strncmp(dev->manufacturer, "www.masterkit.ru", 16) != 0))
+                return -ENODEV;
+
         radio = kzalloc(sizeof(struct ma901radio_device), GFP_KERNEL);
         if (!radio) {
                 dev_err(&intf->dev, "kzalloc for ma901radio_device failed\n");
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 6bbd90e1123c..171b10f167a5 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -1976,12 +1976,11 @@ static int __bond_release_one(struct net_device *bond_dev,
                 return -EINVAL;
         }
 
+        write_unlock_bh(&bond->lock);
         /* unregister rx_handler early so bond_handle_frame wouldn't be called
          * for this slave anymore.
          */
         netdev_rx_handler_unregister(slave_dev);
-        write_unlock_bh(&bond->lock);
-        synchronize_net();
         write_lock_bh(&bond->lock);
 
         if (!all && !bond->params.fail_over_mac) {
@@ -4903,8 +4902,8 @@ static void __exit bonding_exit(void)
 
         bond_destroy_debugfs();
 
-        rtnl_link_unregister(&bond_link_ops);
         unregister_pernet_subsys(&bond_net_ops);
+        rtnl_link_unregister(&bond_link_ops);
 
 #ifdef CONFIG_NET_POLL_CONTROLLER
         /*
diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c
index db103e03ba05..ea7a388f4843 100644
--- a/drivers/net/bonding/bond_sysfs.c
+++ b/drivers/net/bonding/bond_sysfs.c
@@ -527,7 +527,7 @@ static ssize_t bonding_store_arp_interval(struct device *d,
                 goto out;
         }
         if (new_value < 0) {
-                pr_err("%s: Invalid arp_interval value %d not in range 1-%d; rejected.\n",
+                pr_err("%s: Invalid arp_interval value %d not in range 0-%d; rejected.\n",
                        bond->dev->name, new_value, INT_MAX);
                 ret = -EINVAL;
                 goto out;
@@ -542,14 +542,15 @@ static ssize_t bonding_store_arp_interval(struct device *d,
         pr_info("%s: Setting ARP monitoring interval to %d.\n",
                 bond->dev->name, new_value);
         bond->params.arp_interval = new_value;
-        if (bond->params.miimon) {
-                pr_info("%s: ARP monitoring cannot be used with MII monitoring. %s Disabling MII monitoring.\n",
-                        bond->dev->name, bond->dev->name);
-                bond->params.miimon = 0;
-        }
-        if (!bond->params.arp_targets[0]) {
-                pr_info("%s: ARP monitoring has been set up, but no ARP targets have been specified.\n",
-                        bond->dev->name);
+        if (new_value) {
+                if (bond->params.miimon) {
+                        pr_info("%s: ARP monitoring cannot be used with MII monitoring. %s Disabling MII monitoring.\n",
+                                bond->dev->name, bond->dev->name);
+                        bond->params.miimon = 0;
+                }
+                if (!bond->params.arp_targets[0])
+                        pr_info("%s: ARP monitoring has been set up, but no ARP targets have been specified.\n",
+                                bond->dev->name);
         }
         if (bond->dev->flags & IFF_UP) {
                 /* If the interface is up, we may need to fire off
@@ -557,10 +558,13 @@ static ssize_t bonding_store_arp_interval(struct device *d,
                  * timer will get fired off when the open function
                  * is called.
                  */
-                cancel_delayed_work_sync(&bond->mii_work);
-                queue_delayed_work(bond->wq, &bond->arp_work, 0);
+                if (!new_value) {
+                        cancel_delayed_work_sync(&bond->arp_work);
+                } else {
+                        cancel_delayed_work_sync(&bond->mii_work);
+                        queue_delayed_work(bond->wq, &bond->arp_work, 0);
+                }
         }
-
 out:
         rtnl_unlock();
         return ret;
@@ -702,7 +706,7 @@ static ssize_t bonding_store_downdelay(struct device *d,
         }
         if (new_value < 0) {
                 pr_err("%s: Invalid down delay value %d not in range %d-%d; rejected.\n",
-                       bond->dev->name, new_value, 1, INT_MAX);
+                       bond->dev->name, new_value, 0, INT_MAX);
                 ret = -EINVAL;
                 goto out;
         } else {
@@ -757,8 +761,8 @@ static ssize_t bonding_store_updelay(struct device *d,
                 goto out;
         }
         if (new_value < 0) {
-                pr_err("%s: Invalid down delay value %d not in range %d-%d; rejected.\n",
-                       bond->dev->name, new_value, 1, INT_MAX);
+                pr_err("%s: Invalid up delay value %d not in range %d-%d; rejected.\n",
+                       bond->dev->name, new_value, 0, INT_MAX);
                 ret = -EINVAL;
                 goto out;
         } else {
@@ -968,37 +972,37 @@ static ssize_t bonding_store_miimon(struct device *d,
         }
         if (new_value < 0) {
                 pr_err("%s: Invalid miimon value %d not in range %d-%d; rejected.\n",
-                       bond->dev->name, new_value, 1, INT_MAX);
+                       bond->dev->name, new_value, 0, INT_MAX);
                 ret = -EINVAL;
                 goto out;
-        } else {
-                pr_info("%s: Setting MII monitoring interval to %d.\n",
-                        bond->dev->name, new_value);
-                bond->params.miimon = new_value;
-                if (bond->params.updelay)
-                        pr_info("%s: Note: Updating updelay (to %d) since it is a multiple of the miimon value.\n",
-                                bond->dev->name,
-                                bond->params.updelay * bond->params.miimon);
-                if (bond->params.downdelay)
-                        pr_info("%s: Note: Updating downdelay (to %d) since it is a multiple of the miimon value.\n",
-                                bond->dev->name,
-                                bond->params.downdelay * bond->params.miimon);
-                if (bond->params.arp_interval) {
-                        pr_info("%s: MII monitoring cannot be used with ARP monitoring. Disabling ARP monitoring...\n",
-                                bond->dev->name);
-                        bond->params.arp_interval = 0;
-                        if (bond->params.arp_validate) {
-                                bond->params.arp_validate =
-                                        BOND_ARP_VALIDATE_NONE;
-                        }
-                }
-
-                if (bond->dev->flags & IFF_UP) {
-                        /* If the interface is up, we may need to fire off
-                         * the MII timer. If the interface is down, the
-                         * timer will get fired off when the open function
-                         * is called.
-                         */
+        }
+        pr_info("%s: Setting MII monitoring interval to %d.\n",
+                bond->dev->name, new_value);
+        bond->params.miimon = new_value;
+        if (bond->params.updelay)
+                pr_info("%s: Note: Updating updelay (to %d) since it is a multiple of the miimon value.\n",
+                        bond->dev->name,
+                        bond->params.updelay * bond->params.miimon);
+        if (bond->params.downdelay)
+                pr_info("%s: Note: Updating downdelay (to %d) since it is a multiple of the miimon value.\n",
+                        bond->dev->name,
+                        bond->params.downdelay * bond->params.miimon);
+        if (new_value && bond->params.arp_interval) {
+                pr_info("%s: MII monitoring cannot be used with ARP monitoring. Disabling ARP monitoring...\n",
+                        bond->dev->name);
+                bond->params.arp_interval = 0;
+                if (bond->params.arp_validate)
+                        bond->params.arp_validate = BOND_ARP_VALIDATE_NONE;
+        }
+        if (bond->dev->flags & IFF_UP) {
+                /* If the interface is up, we may need to fire off
+                 * the MII timer. If the interface is down, the
+                 * timer will get fired off when the open function
+                 * is called.
+                 */
+                if (!new_value) {
+                        cancel_delayed_work_sync(&bond->mii_work);
+                } else {
                         cancel_delayed_work_sync(&bond->arp_work);
                         queue_delayed_work(bond->wq, &bond->mii_work, 0);
                 }
diff --git a/drivers/net/can/sja1000/Kconfig b/drivers/net/can/sja1000/Kconfig
index b39ca5b3ea7f..ff2ba86cd4a4 100644
--- a/drivers/net/can/sja1000/Kconfig
+++ b/drivers/net/can/sja1000/Kconfig
@@ -46,6 +46,7 @@ config CAN_EMS_PCI
 config CAN_PEAK_PCMCIA
         tristate "PEAK PCAN-PC Card"
         depends on PCMCIA
+        depends on HAS_IOPORT
         ---help---
           This driver is for the PCAN-PC Card PCMCIA adapter (1 or 2 channels)
           from PEAK-System (http://www.peak-system.com). To compile this
diff --git a/drivers/net/can/sja1000/plx_pci.c b/drivers/net/can/sja1000/plx_pci.c
index a042cdc260dc..3c18d7d000ed 100644
--- a/drivers/net/can/sja1000/plx_pci.c
+++ b/drivers/net/can/sja1000/plx_pci.c
@@ -348,7 +348,7 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
          */
         if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
             REG_CR_BASICCAN_INITIAL &&
-            (priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) &&
+            (priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_BASICCAN_INITIAL) &&
             (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL))
                 flag = 1;
 
@@ -360,7 +360,7 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
          * See states on p. 23 of the Datasheet.
          */
         if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL &&
-            priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL &&
+            priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_PELICAN_INITIAL &&
             priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL)
                 return flag;
 
diff --git a/drivers/net/can/sja1000/sja1000.c b/drivers/net/can/sja1000/sja1000.c
index daf4013a8fc7..e4df307eaa90 100644
--- a/drivers/net/can/sja1000/sja1000.c
+++ b/drivers/net/can/sja1000/sja1000.c
@@ -92,7 +92,7 @@ static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val)
          */
         spin_lock_irqsave(&priv->cmdreg_lock, flags);
         priv->write_reg(priv, REG_CMR, val);
-        priv->read_reg(priv, REG_SR);
+        priv->read_reg(priv, SJA1000_REG_SR);
         spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
 }
 
@@ -502,7 +502,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
 
         while ((isrc = priv->read_reg(priv, REG_IR)) && (n < SJA1000_MAX_IRQ)) {
                 n++;
-                status = priv->read_reg(priv, REG_SR);
+                status = priv->read_reg(priv, SJA1000_REG_SR);
                 /* check for absent controller due to hw unplug */
                 if (status == 0xFF && sja1000_is_absent(priv))
                         return IRQ_NONE;
@@ -530,7 +530,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
                         /* receive interrupt */
                         while (status & SR_RBS) {
                                 sja1000_rx(dev);
-                                status = priv->read_reg(priv, REG_SR);
+                                status = priv->read_reg(priv, SJA1000_REG_SR);
                                 /* check for absent controller */
                                 if (status == 0xFF && sja1000_is_absent(priv))
                                         return IRQ_NONE;
diff --git a/drivers/net/can/sja1000/sja1000.h b/drivers/net/can/sja1000/sja1000.h
index afa99847a510..aa48e053da27 100644
--- a/drivers/net/can/sja1000/sja1000.h
+++ b/drivers/net/can/sja1000/sja1000.h
@@ -56,7 +56,7 @@
 /* SJA1000 registers - manual section 6.4 (Pelican Mode) */
 #define REG_MOD         0x00
 #define REG_CMR         0x01
-#define REG_SR          0x02
+#define SJA1000_REG_SR          0x02
 #define REG_IR          0x03
 #define REG_IER         0x04
 #define REG_ALC         0x0B
diff --git a/drivers/net/ethernet/atheros/atl1e/atl1e.h b/drivers/net/ethernet/atheros/atl1e/atl1e.h
index 829b5ad71d0d..b5fd934585e9 100644
--- a/drivers/net/ethernet/atheros/atl1e/atl1e.h
+++ b/drivers/net/ethernet/atheros/atl1e/atl1e.h
@@ -186,7 +186,7 @@ struct atl1e_tpd_desc {
 /* how about 0x2000 */
 #define MAX_TX_BUF_LEN      0x2000
 #define MAX_TX_BUF_SHIFT    13
-/*#define MAX_TX_BUF_LEN  0x3000 */
+#define MAX_TSO_SEG_SIZE    0x3c00
 
 /* rrs word 1 bit 0:31 */
 #define RRS_RX_CSUM_MASK        0xFFFF
@@ -438,7 +438,6 @@ struct atl1e_adapter {
         struct atl1e_hw        hw;
         struct atl1e_hw_stats  hw_stats;
 
-        bool have_msi;
         u32 wol;
         u16 link_speed;
         u16 link_duplex;
diff --git a/drivers/net/ethernet/atheros/atl1e/atl1e_main.c b/drivers/net/ethernet/atheros/atl1e/atl1e_main.c
index 92f4734f860d..ac25f05ff68f 100644
--- a/drivers/net/ethernet/atheros/atl1e/atl1e_main.c
+++ b/drivers/net/ethernet/atheros/atl1e/atl1e_main.c
@@ -1849,34 +1849,19 @@ static void atl1e_free_irq(struct atl1e_adapter *adapter)
         struct net_device *netdev = adapter->netdev;
 
         free_irq(adapter->pdev->irq, netdev);
-
-        if (adapter->have_msi)
-                pci_disable_msi(adapter->pdev);
 }
 
 static int atl1e_request_irq(struct atl1e_adapter *adapter)
 {
         struct pci_dev    *pdev   = adapter->pdev;
         struct net_device *netdev = adapter->netdev;
-        int flags = 0;
         int err = 0;
 
-        adapter->have_msi = true;
-        err = pci_enable_msi(pdev);
-        if (err) {
-                netdev_dbg(netdev,
-                           "Unable to allocate MSI interrupt Error: %d\n", err);
-                adapter->have_msi = false;
-        }
-
-        if (!adapter->have_msi)
-                flags |= IRQF_SHARED;
-        err = request_irq(pdev->irq, atl1e_intr, flags, netdev->name, netdev);
+        err = request_irq(pdev->irq, atl1e_intr, IRQF_SHARED, netdev->name,
+                          netdev);
         if (err) {
                 netdev_dbg(adapter->netdev,
                            "Unable to allocate interrupt Error: %d\n", err);
-                if (adapter->have_msi)
-                        pci_disable_msi(pdev);
                 return err;
         }
         netdev_dbg(netdev, "atl1e_request_irq OK\n");
@@ -2344,6 +2329,7 @@ static int atl1e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         INIT_WORK(&adapter->reset_task, atl1e_reset_task);
         INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
+        netif_set_gso_max_size(netdev, MAX_TSO_SEG_SIZE);
         err = register_netdev(netdev);
         if (err) {
                 netdev_err(netdev, "register netdevice failed\n");
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 67d2663b3974..17a972734ba7 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -14604,8 +14604,11 @@ static void tg3_read_vpd(struct tg3 *tp)
                 if (j + len > block_end)
                         goto partno;
 
-                memcpy(tp->fw_ver, &vpd_data[j], len);
-                strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
+                if (len >= sizeof(tp->fw_ver))
+                        len = sizeof(tp->fw_ver) - 1;
+                memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
+                snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
+                         &vpd_data[j]);
         }
 
 partno:
diff --git a/drivers/net/ethernet/calxeda/xgmac.c b/drivers/net/ethernet/calxeda/xgmac.c
index a170065b5973..b0ebc9f6d55e 100644
--- a/drivers/net/ethernet/calxeda/xgmac.c
+++ b/drivers/net/ethernet/calxeda/xgmac.c
@@ -163,6 +163,7 @@
 #define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001      /* Flow Control Busy ... */
 
 /* XGMAC_INT_STAT reg */
+#define XGMAC_INT_STAT_PMTIM    0x00800000      /* PMT Interrupt Mask */
 #define XGMAC_INT_STAT_PMT      0x0080          /* PMT Interrupt Status */
 #define XGMAC_INT_STAT_LPI      0x0040          /* LPI Interrupt Status */
 
@@ -960,6 +961,9 @@ static int xgmac_hw_init(struct net_device *dev)
         writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);
         writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);
 
+        /* Mask power mgt interrupt */
+        writel(XGMAC_INT_STAT_PMTIM, ioaddr + XGMAC_INT_STAT);
+
         /* XGMAC requires AXI bus init. This is a 'magic number' for now */
         writel(0x0077000E, ioaddr + XGMAC_DMA_AXI_BUS);
 
@@ -1141,6 +1145,9 @@ static int xgmac_rx(struct xgmac_priv *priv, int limit)
                 struct sk_buff *skb;
                 int frame_len;
 
+                if (!dma_ring_cnt(priv->rx_head, priv->rx_tail, DMA_RX_RING_SZ))
+                        break;
+
                 entry = priv->rx_tail;
                 p = priv->dma_rx + entry;
                 if (desc_get_owner(p))
@@ -1825,7 +1832,7 @@ static void xgmac_pmt(void __iomem *ioaddr, unsigned long mode)
         unsigned int pmt = 0;
 
         if (mode & WAKE_MAGIC)
-                pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT;
+                pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT_EN;
         if (mode & WAKE_UCAST)
                 pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_GLBL_UNICAST;
 
diff --git a/drivers/net/ethernet/davicom/dm9000.c b/drivers/net/ethernet/davicom/dm9000.c
index 8cdf02503d13..9eada8e86078 100644
--- a/drivers/net/ethernet/davicom/dm9000.c
+++ b/drivers/net/ethernet/davicom/dm9000.c
@@ -257,6 +257,107 @@ static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
                 tmp = readl(reg);
 }
 
+/*
+ * Sleep, either by using msleep() or if we are suspending, then
+ * use mdelay() to sleep.
+ */
+static void dm9000_msleep(board_info_t *db, unsigned int ms)
+{
+        if (db->in_suspend)
+                mdelay(ms);
+        else
+                msleep(ms);
+}
+
+/* Read a word from phyxcer */
+static int
+dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
+{
+        board_info_t *db = netdev_priv(dev);
+        unsigned long flags;
+        unsigned int reg_save;
+        int ret;
+
+        mutex_lock(&db->addr_lock);
+
+        spin_lock_irqsave(&db->lock, flags);
+
+        /* Save previous register address */
+        reg_save = readb(db->io_addr);
+
+        /* Fill the phyxcer register into REG_0C */
+        iow(db, DM9000_EPAR, DM9000_PHY | reg);
+
+        /* Issue phyxcer read command */
+        iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);
+
+        writeb(reg_save, db->io_addr);
+        spin_unlock_irqrestore(&db->lock, flags);
+
+        dm9000_msleep(db, 1);           /* Wait read complete */
+
+        spin_lock_irqsave(&db->lock, flags);
+        reg_save = readb(db->io_addr);
+
+        iow(db, DM9000_EPCR, 0x0);      /* Clear phyxcer read command */
+
+        /* The read data keeps on REG_0D & REG_0E */
+        ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
+
+        /* restore the previous address */
+        writeb(reg_save, db->io_addr);
+        spin_unlock_irqrestore(&db->lock, flags);
+
+        mutex_unlock(&db->addr_lock);
+
+        dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
+        return ret;
+}
+
+/* Write a word to phyxcer */
+static void
+dm9000_phy_write(struct net_device *dev,
+                 int phyaddr_unused, int reg, int value)
+{
+        board_info_t *db = netdev_priv(dev);
+        unsigned long flags;
+        unsigned long reg_save;
+
+        dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
+        mutex_lock(&db->addr_lock);
+
+        spin_lock_irqsave(&db->lock, flags);
+
+        /* Save previous register address */
+        reg_save = readb(db->io_addr);
+
+        /* Fill the phyxcer register into REG_0C */
+        iow(db, DM9000_EPAR, DM9000_PHY | reg);
+
+        /* Fill the written data into REG_0D & REG_0E */
+        iow(db, DM9000_EPDRL, value);
+        iow(db, DM9000_EPDRH, value >> 8);
+
+        /* Issue phyxcer write command */
+        iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);
+
+        writeb(reg_save, db->io_addr);
+        spin_unlock_irqrestore(&db->lock, flags);
+
+        dm9000_msleep(db, 1);           /* Wait write complete */
+
+        spin_lock_irqsave(&db->lock, flags);
+        reg_save = readb(db->io_addr);
+
+        iow(db, DM9000_EPCR, 0x0);      /* Clear phyxcer write command */
+
+        /* restore the previous address */
+        writeb(reg_save, db->io_addr);
+
+        spin_unlock_irqrestore(&db->lock, flags);
+        mutex_unlock(&db->addr_lock);
+}
+
 /* dm9000_set_io
  *
  * select the specified set of io routines to use with the
@@ -795,6 +896,9 @@ dm9000_init_dm9000(struct net_device *dev)
 
         iow(db, DM9000_GPCR, GPCR_GEP_CNTL);    /* Let GPIO0 output */
 
+        dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
+        dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM); /* Init */
+
         ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;
 
         /* if wol is needed, then always set NCR_WAKEEN otherwise we end
@@ -1201,109 +1305,6 @@ dm9000_open(struct net_device *dev)
         return 0;
 }
 
-/*
- * Sleep, either by using msleep() or if we are suspending, then
- * use mdelay() to sleep.
- */
-static void dm9000_msleep(board_info_t *db, unsigned int ms)
-{
-        if (db->in_suspend)
-                mdelay(ms);
-        else
-                msleep(ms);
-}
-
-/*
- *   Read a word from phyxcer
- */
-static int
-dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
-{
-        board_info_t *db = netdev_priv(dev);
-        unsigned long flags;
-        unsigned int reg_save;
-        int ret;
-
-        mutex_lock(&db->addr_lock);
-
-        spin_lock_irqsave(&db->lock,flags);
-
-        /* Save previous register address */
-        reg_save = readb(db->io_addr);
-
-        /* Fill the phyxcer register into REG_0C */
-        iow(db, DM9000_EPAR, DM9000_PHY | reg);
-
-        iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);   /* Issue phyxcer read command */
-
-        writeb(reg_save, db->io_addr);
-        spin_unlock_irqrestore(&db->lock,flags);
-
-        dm9000_msleep(db, 1);           /* Wait read complete */
-
-        spin_lock_irqsave(&db->lock,flags);
-        reg_save = readb(db->io_addr);
-
-        iow(db, DM9000_EPCR, 0x0);      /* Clear phyxcer read command */
-
-        /* The read data keeps on REG_0D & REG_0E */
-        ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
-
-        /* restore the previous address */
-        writeb(reg_save, db->io_addr);
-        spin_unlock_irqrestore(&db->lock,flags);
-
-        mutex_unlock(&db->addr_lock);
-
-        dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
-        return ret;
-}
-
-/*
- *   Write a word to phyxcer
- */
-static void
-dm9000_phy_write(struct net_device *dev,
-                 int phyaddr_unused, int reg, int value)
-{
-        board_info_t *db = netdev_priv(dev);
-        unsigned long flags;
-        unsigned long reg_save;
-
-        dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
-        mutex_lock(&db->addr_lock);
-
-        spin_lock_irqsave(&db->lock,flags);
-
-        /* Save previous register address */
-        reg_save = readb(db->io_addr);
-
-        /* Fill the phyxcer register into REG_0C */
-        iow(db, DM9000_EPAR, DM9000_PHY | reg);
-
-        /* Fill the written data into REG_0D & REG_0E */
-        iow(db, DM9000_EPDRL, value);
-        iow(db, DM9000_EPDRH, value >> 8);
-
-        iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);   /* Issue phyxcer write command */
-
-        writeb(reg_save, db->io_addr);
-        spin_unlock_irqrestore(&db->lock, flags);
-
-        dm9000_msleep(db, 1);           /* Wait write complete */
-
-        spin_lock_irqsave(&db->lock,flags);
-        reg_save = readb(db->io_addr);
-
-        iow(db, DM9000_EPCR, 0x0);      /* Clear phyxcer write command */
-
-        /* restore the previous address */
-        writeb(reg_save, db->io_addr);
-
-        spin_unlock_irqrestore(&db->lock, flags);
-        mutex_unlock(&db->addr_lock);
-}
-
 static void
 dm9000_shutdown(struct net_device *dev)
 {
@@ -1502,7 +1503,12 @@ dm9000_probe(struct platform_device *pdev)
         db->flags |= DM9000_PLATF_SIMPLE_PHY;
 #endif
 
-        dm9000_reset(db);
+        /* Fixing bug on dm9000_probe, takeover dm9000_reset(db),
+         * Need 'NCR_MAC_LBK' bit to indeed stable our DM9000 fifo
+         * while probe stage.
+         */
+
+        iow(db, DM9000_NCR, NCR_MAC_LBK | NCR_RST);
 
         /* try multiple times, DM9000 sometimes gets the read wrong */
         for (i = 0; i < 8; i++) {
diff --git a/drivers/net/ethernet/davicom/dm9000.h b/drivers/net/ethernet/davicom/dm9000.h
index 55688bd1a3ef..9ce058adabab 100644
--- a/drivers/net/ethernet/davicom/dm9000.h
+++ b/drivers/net/ethernet/davicom/dm9000.h
@@ -69,7 +69,9 @@
 #define NCR_WAKEEN          (1<<6)
 #define NCR_FCOL            (1<<4)
 #define NCR_FDX             (1<<3)
-#define NCR_LBK             (3<<1)
+
+#define NCR_RESERVED        (3<<1)
+#define NCR_MAC_LBK         (1<<1)
 #define NCR_RST             (1<<0)
 
 #define NSR_SPEED           (1<<7)
@@ -167,5 +169,12 @@
 #define ISR_LNKCHNG             (1<<5)
 #define ISR_UNDERRUN            (1<<4)
 
+/* Davicom MII registers.
+ */
+
+#define MII_DM_DSPCR            0x1b    /* DSP Control Register */
+
+#define DSPCR_INIT_PARAM        0xE100  /* DSP init parameter */
+
 #endif /* _DM9000X_H_ */
 
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index 911d0253dbb2..f292c3aa423f 100644
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -345,6 +345,53 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
         return NETDEV_TX_OK;
 }
 
+/* Init RX & TX buffer descriptors
+ */
+static void fec_enet_bd_init(struct net_device *dev)
+{
+        struct fec_enet_private *fep = netdev_priv(dev);
+        struct bufdesc *bdp;
+        unsigned int i;
+
+        /* Initialize the receive buffer descriptors. */
+        bdp = fep->rx_bd_base;
+        for (i = 0; i < RX_RING_SIZE; i++) {
+
+                /* Initialize the BD for every fragment in the page. */
+                if (bdp->cbd_bufaddr)
+                        bdp->cbd_sc = BD_ENET_RX_EMPTY;
+                else
+                        bdp->cbd_sc = 0;
+                bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
+        }
+
+        /* Set the last buffer to wrap */
+        bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
+        bdp->cbd_sc |= BD_SC_WRAP;
+
+        fep->cur_rx = fep->rx_bd_base;
+
+        /* ...and the same for transmit */
+        bdp = fep->tx_bd_base;
+        fep->cur_tx = bdp;
+        for (i = 0; i < TX_RING_SIZE; i++) {
+
+                /* Initialize the BD for every fragment in the page. */
+                bdp->cbd_sc = 0;
+                if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
+                        dev_kfree_skb_any(fep->tx_skbuff[i]);
+                        fep->tx_skbuff[i] = NULL;
+                }
+                bdp->cbd_bufaddr = 0;
+                bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
+        }
+
+        /* Set the last buffer to wrap */
+        bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
+        bdp->cbd_sc |= BD_SC_WRAP;
+        fep->dirty_tx = bdp;
+}
+
 /* This function is called to start or restart the FEC during a link
  * change.  This only happens when switching between half and full
  * duplex.
@@ -388,6 +435,8 @@ fec_restart(struct net_device *ndev, int duplex)
         /* Set maximum receive buffer size. */
         writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
 
+        fec_enet_bd_init(ndev);
+
         /* Set receive and transmit descriptor base. */
         writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
         if (fep->bufdesc_ex)
@@ -397,7 +446,6 @@ fec_restart(struct net_device *ndev, int duplex)
                 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
                         * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
 
-        fep->cur_rx = fep->rx_bd_base;
 
         for (i = 0; i <= TX_RING_MOD_MASK; i++) {
                 if (fep->tx_skbuff[i]) {
@@ -1597,8 +1645,6 @@ static int fec_enet_init(struct net_device *ndev)
 {
         struct fec_enet_private *fep = netdev_priv(ndev);
         struct bufdesc *cbd_base;
-        struct bufdesc *bdp;
-        unsigned int i;
 
         /* Allocate memory for buffer descriptors. */
         cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
@@ -1608,6 +1654,7 @@ static int fec_enet_init(struct net_device *ndev)
                 return -ENOMEM;
         }
 
+        memset(cbd_base, 0, PAGE_SIZE);
         spin_lock_init(&fep->hw_lock);
 
         fep->netdev = ndev;
@@ -1631,35 +1678,6 @@ static int fec_enet_init(struct net_device *ndev)
         writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
         netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
 
-        /* Initialize the receive buffer descriptors. */
-        bdp = fep->rx_bd_base;
-        for (i = 0; i < RX_RING_SIZE; i++) {
-
-                /* Initialize the BD for every fragment in the page. */
-                bdp->cbd_sc = 0;
-                bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
-        }
-
-        /* Set the last buffer to wrap */
-        bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
-        bdp->cbd_sc |= BD_SC_WRAP;
-
-        /* ...and the same for transmit */
-        bdp = fep->tx_bd_base;
-        fep->cur_tx = bdp;
-        for (i = 0; i < TX_RING_SIZE; i++) {
-
-                /* Initialize the BD for every fragment in the page. */
-                bdp->cbd_sc = 0;
-                bdp->cbd_bufaddr = 0;
-                bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
-        }
-
-        /* Set the last buffer to wrap */
-        bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
-        bdp->cbd_sc |= BD_SC_WRAP;
-        fep->dirty_tx = bdp;
-
         fec_restart(ndev, 0);
 
         return 0;
diff --git a/drivers/net/ethernet/intel/e1000/e1000_ethtool.c b/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
index 43462d596a4e..ffd287196bf8 100644
--- a/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
+++ b/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
@@ -1053,6 +1053,10 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
                 txdr->buffer_info[i].dma =
                         dma_map_single(&pdev->dev, skb->data, skb->len,
                                        DMA_TO_DEVICE);
+                if (dma_mapping_error(&pdev->dev, txdr->buffer_info[i].dma)) {
+                        ret_val = 4;
+                        goto err_nomem;
+                }
                 tx_desc->buffer_addr = cpu_to_le64(txdr->buffer_info[i].dma);
                 tx_desc->lower.data = cpu_to_le32(skb->len);
                 tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
@@ -1069,7 +1073,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
         rxdr->buffer_info = kcalloc(rxdr->count, sizeof(struct e1000_buffer),
                                     GFP_KERNEL);
         if (!rxdr->buffer_info) {
-                ret_val = 4;
+                ret_val = 5;
                 goto err_nomem;
         }
 
@@ -1077,7 +1081,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
         rxdr->desc = dma_alloc_coherent(&pdev->dev, rxdr->size, &rxdr->dma,
                                         GFP_KERNEL);
         if (!rxdr->desc) {
-                ret_val = 5;
+                ret_val = 6;
                 goto err_nomem;
         }
         memset(rxdr->desc, 0, rxdr->size);
@@ -1101,7 +1105,7 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
 
                 skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
                 if (!skb) {
-                        ret_val = 6;
+                        ret_val = 7;
                         goto err_nomem;
                 }
                 skb_reserve(skb, NET_IP_ALIGN);
@@ -1110,6 +1114,10 @@ static int e1000_setup_desc_rings(struct e1000_adapter *adapter)
                 rxdr->buffer_info[i].dma =
                         dma_map_single(&pdev->dev, skb->data,
                                        E1000_RXBUFFER_2048, DMA_FROM_DEVICE);
+                if (dma_mapping_error(&pdev->dev, rxdr->buffer_info[i].dma)) {
+                        ret_val = 8;
+                        goto err_nomem;
+                }
                 rx_desc->buffer_addr = cpu_to_le64(rxdr->buffer_info[i].dma);
                 memset(skb->data, 0x00, skb->len);
         }
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 948b86ffa4f0..7e615e2bf7e6 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -848,11 +848,16 @@ check_page:
                         }
                 }
 
-                if (!buffer_info->dma)
+                if (!buffer_info->dma) {
                         buffer_info->dma = dma_map_page(&pdev->dev,
                                                         buffer_info->page, 0,
                                                         PAGE_SIZE,
                                                         DMA_FROM_DEVICE);
+                        if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
+                                adapter->alloc_rx_buff_failed++;
+                                break;
+                        }
+                }
 
                 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
                 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
diff --git a/drivers/net/ethernet/intel/ixgb/ixgb_main.c b/drivers/net/ethernet/intel/ixgb/ixgb_main.c
index ea4808373435..b5f94abe3cff 100644
--- a/drivers/net/ethernet/intel/ixgb/ixgb_main.c
+++ b/drivers/net/ethernet/intel/ixgb/ixgb_main.c
@@ -2159,6 +2159,10 @@ map_skb:
                                                   skb->data,
                                                   adapter->rx_buffer_len,
                                                   DMA_FROM_DEVICE);
+                if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
+                        adapter->alloc_rx_buff_failed++;
+                        break;
+                }
 
                 rx_desc = IXGB_RX_DESC(*rx_ring, i);
                 rx_desc->buff_addr = cpu_to_le64(buffer_info->dma);
@@ -2168,7 +2172,8 @@ map_skb:
                 rx_desc->status = 0;
 
 
-                if (++i == rx_ring->count) i = 0;
+                if (++i == rx_ring->count)
+                        i = 0;
                 buffer_info = &rx_ring->buffer_info[i];
         }
 
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index db5611ae407e..79f4a26ea6cc 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -7922,12 +7922,19 @@ static int __init ixgbe_init_module(void)
         ixgbe_dbg_init();
 #endif /* CONFIG_DEBUG_FS */
 
+        ret = pci_register_driver(&ixgbe_driver);
+        if (ret) {
+#ifdef CONFIG_DEBUG_FS
+                ixgbe_dbg_exit();
+#endif /* CONFIG_DEBUG_FS */
+                return ret;
+        }
+
 #ifdef CONFIG_IXGBE_DCA
         dca_register_notify(&dca_notifier);
 #endif
 
-        ret = pci_register_driver(&ixgbe_driver);
-        return ret;
+        return 0;
 }
 
 module_init(ixgbe_init_module);
diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
index fc07ca35721b..6a0e671fcecd 100644
--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
@@ -1067,7 +1067,7 @@ static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
                 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
                 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
 
-                tp = space - 2048/8;
+                tp = space - 8192/8;
                 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
                 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
         } else {
diff --git a/drivers/net/ethernet/marvell/sky2.h b/drivers/net/ethernet/marvell/sky2.h
index 615ac63ea860..ec6dcd80152b 100644
--- a/drivers/net/ethernet/marvell/sky2.h
+++ b/drivers/net/ethernet/marvell/sky2.h
@@ -2074,7 +2074,7 @@ enum {
         GM_IS_RX_FF_OR  = 1<<1, /* Receive FIFO Overrun */
         GM_IS_RX_COMPL  = 1<<0, /* Frame Reception Complete */
 
-#define GMAC_DEF_MSK     GM_IS_TX_FF_UR
+#define GMAC_DEF_MSK     (GM_IS_TX_FF_UR | GM_IS_RX_FF_OR)
 };
 
 /*      GMAC_LINK_CTRL  16 bit  GMAC Link Control Reg (YUKON only) */
diff --git a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
index f278b10ef714..30d78f806dc3 100644
--- a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
+++ b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
@@ -411,8 +411,8 @@ static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
 
 static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
 {
-        unsigned int i;
-        for (i = ETH_ALEN - 1; i; --i) {
+        int i;
+        for (i = ETH_ALEN - 1; i >= 0; --i) {
                 dst_mac[i] = src_mac & 0xff;
                 src_mac >>= 8;
         }
diff --git a/drivers/net/ethernet/micrel/ks8851.c b/drivers/net/ethernet/micrel/ks8851.c
index 33bcb63d56a2..8fb481252e2c 100644
--- a/drivers/net/ethernet/micrel/ks8851.c
+++ b/drivers/net/ethernet/micrel/ks8851.c
@@ -528,7 +528,7 @@ static void ks8851_rx_pkts(struct ks8851_net *ks)
         for (; rxfc != 0; rxfc--) {
                 rxh = ks8851_rdreg32(ks, KS_RXFHSR);
                 rxstat = rxh & 0xffff;
-                rxlen = rxh >> 16;
+                rxlen = (rxh >> 16) & 0xfff;
 
                 netif_dbg(ks, rx_status, ks->netdev,
                           "rx: stat 0x%04x, len 0x%04x\n", rxstat, rxlen);
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 28fb50a1e9c3..4ecbe64a758d 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -3818,6 +3818,30 @@ static void rtl_init_mdio_ops(struct rtl8169_private *tp)
         }
 }
 
+static void rtl_speed_down(struct rtl8169_private *tp)
+{
+        u32 adv;
+        int lpa;
+
+        rtl_writephy(tp, 0x1f, 0x0000);
+        lpa = rtl_readphy(tp, MII_LPA);
+
+        if (lpa & (LPA_10HALF | LPA_10FULL))
+                adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+        else if (lpa & (LPA_100HALF | LPA_100FULL))
+                adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
+                      ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
+        else
+                adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
+                      ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
+                      (tp->mii.supports_gmii ?
+                       ADVERTISED_1000baseT_Half |
+                       ADVERTISED_1000baseT_Full : 0);
+
+        rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
+                          adv);
+}
+
 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
 {
         void __iomem *ioaddr = tp->mmio_addr;
@@ -3848,9 +3872,7 @@ static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
                 return false;
 
-        rtl_writephy(tp, 0x1f, 0x0000);
-        rtl_writephy(tp, MII_BMCR, 0x0000);
-
+        rtl_speed_down(tp);
         rtl_wol_suspend_quirk(tp);
 
         return true;
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index bf5e3cf97c4d..6ed333fe5c04 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -1216,10 +1216,7 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
                 if (felic_stat & ECSR_LCHNG) {
                         /* Link Changed */
                         if (mdp->cd->no_psr || mdp->no_ether_link) {
-                                if (mdp->link == PHY_DOWN)
-                                        link_stat = 0;
-                                else
-                                        link_stat = PHY_ST_LINK;
+                                goto ignore_link;
                         } else {
                                 link_stat = (sh_eth_read(ndev, PSR));
                                 if (mdp->ether_link_active_low)
@@ -1242,6 +1239,7 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
                 }
         }
 
+ignore_link:
         if (intr_status & EESR_TWB) {
                 /* Write buck end. unused write back interrupt */
                 if (intr_status & EESR_TABT)    /* Transmit Abort int */
@@ -1326,12 +1324,18 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
         struct sh_eth_private *mdp = netdev_priv(ndev);
         struct sh_eth_cpu_data *cd = mdp->cd;
         irqreturn_t ret = IRQ_NONE;
-        u32 intr_status = 0;
+        unsigned long intr_status;
 
         spin_lock(&mdp->lock);
 
-        /* Get interrpt stat */
+        /* Get interrupt status */
         intr_status = sh_eth_read(ndev, EESR);
+        /* Mask it with the interrupt mask, forcing ECI interrupt to be always
+         * enabled since it's the one that  comes thru regardless of the mask,
+         * and we need to fully handle it in sh_eth_error() in order to quench
+         * it as it doesn't get cleared by just writing 1 to the ECI bit...
+         */
+        intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
         /* Clear interrupt */
         if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
                         EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
@@ -1373,7 +1377,7 @@ static void sh_eth_adjust_link(struct net_device *ndev)
         struct phy_device *phydev = mdp->phydev;
         int new_state = 0;
 
-        if (phydev->link != PHY_DOWN) {
+        if (phydev->link) {
                 if (phydev->duplex != mdp->duplex) {
                         new_state = 1;
                         mdp->duplex = phydev->duplex;
@@ -1387,17 +1391,21 @@ static void sh_eth_adjust_link(struct net_device *ndev)
                         if (mdp->cd->set_rate)
                                 mdp->cd->set_rate(ndev);
                 }
-                if (mdp->link == PHY_DOWN) {
+                if (!mdp->link) {
                         sh_eth_write(ndev,
                                 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
                         new_state = 1;
                         mdp->link = phydev->link;
+                        if (mdp->cd->no_psr || mdp->no_ether_link)
+                                sh_eth_rcv_snd_enable(ndev);
                 }
         } else if (mdp->link) {
                 new_state = 1;
-                mdp->link = PHY_DOWN;
+                mdp->link = 0;
                 mdp->speed = 0;
                 mdp->duplex = -1;
+                if (mdp->cd->no_psr || mdp->no_ether_link)
+                        sh_eth_rcv_snd_disable(ndev);
         }
 
         if (new_state && netif_msg_link(mdp))
@@ -1414,7 +1422,7 @@ static int sh_eth_phy_init(struct net_device *ndev)
         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
                 mdp->mii_bus->id , mdp->phy_id);
 
-        mdp->link = PHY_DOWN;
+        mdp->link = 0;
         mdp->speed = 0;
         mdp->duplex = -1;
 
diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h
index e6655678458e..828be4515008 100644
--- a/drivers/net/ethernet/renesas/sh_eth.h
+++ b/drivers/net/ethernet/renesas/sh_eth.h
@@ -723,7 +723,7 @@ struct sh_eth_private {
         u32 phy_id;                                     /* PHY ID */
         struct mii_bus *mii_bus;        /* MDIO bus control */
         struct phy_device *phydev;      /* PHY device control */
-        enum phy_state link;
+        int link;
         phy_interface_t phy_interface;
         int msg_enable;
         int speed;
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index df32a090d08e..80cad06e5eb2 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -436,7 +436,7 @@ void cpsw_tx_handler(void *token, int len, int status)
          * queue is stopped then start the queue as we have free desc for tx
          */
         if (unlikely(netif_queue_stopped(ndev)))
-                netif_start_queue(ndev);
+                netif_wake_queue(ndev);
         cpts_tx_timestamp(priv->cpts, skb);
         priv->stats.tx_packets++;
         priv->stats.tx_bytes += len;
diff --git a/drivers/net/ethernet/ti/davinci_emac.c b/drivers/net/ethernet/ti/davinci_emac.c
index ae1b77aa199f..72300bc9e378 100644
--- a/drivers/net/ethernet/ti/davinci_emac.c
+++ b/drivers/net/ethernet/ti/davinci_emac.c
@@ -1053,7 +1053,7 @@ static void emac_tx_handler(void *token, int len, int status)
          * queue is stopped then start the queue as we have free desc for tx
          */
         if (unlikely(netif_queue_stopped(ndev)))
-                netif_start_queue(ndev);
+                netif_wake_queue(ndev);
         ndev->stats.tx_packets++;
         ndev->stats.tx_bytes += len;
         dev_kfree_skb_any(skb);
diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c
index 9abe51710f22..1a15ec14c386 100644
--- a/drivers/net/usb/smsc75xx.c
+++ b/drivers/net/usb/smsc75xx.c
@@ -914,8 +914,12 @@ static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
 static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
 {
         struct usbnet *dev = netdev_priv(netdev);
+        int ret;
+
+        if (new_mtu > MAX_SINGLE_PACKET_SIZE)
+                return -EINVAL;
 
-        int ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu);
+        ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
         if (ret < 0) {
                 netdev_warn(dev->net, "Failed to set mac rx frame length\n");
                 return ret;
@@ -1324,7 +1328,7 @@ static int smsc75xx_reset(struct usbnet *dev)
 
         netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
 
-        ret = smsc75xx_set_rx_max_frame_length(dev, 1514);
+        ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
         if (ret < 0) {
                 netdev_warn(dev->net, "Failed to set max rx frame length\n");
                 return ret;
@@ -2134,8 +2138,8 @@ static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
                         else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
                                 dev->net->stats.rx_frame_errors++;
                 } else {
-                        /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
-                        if (unlikely(size > (ETH_FRAME_LEN + 12))) {
+                        /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
+                        if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
                                 netif_dbg(dev, rx_err, dev->net,
                                           "size err rx_cmd_a=0x%08x\n",
                                           rx_cmd_a);
diff --git a/drivers/net/wireless/ath/ath9k/link.c b/drivers/net/wireless/ath/ath9k/link.c
index 39c84ecf6a42..7fdac6c7b3ea 100644
--- a/drivers/net/wireless/ath/ath9k/link.c
+++ b/drivers/net/wireless/ath/ath9k/link.c
@@ -170,7 +170,8 @@ void ath_rx_poll(unsigned long data)
 {
         struct ath_softc *sc = (struct ath_softc *)data;
 
-        ieee80211_queue_work(sc->hw, &sc->hw_check_work);
+        if (!test_bit(SC_OP_INVALID, &sc->sc_flags))
+                ieee80211_queue_work(sc->hw, &sc->hw_check_work);
 }
 
 /*
diff --git a/drivers/net/wireless/b43/dma.c b/drivers/net/wireless/b43/dma.c
index 38bc5a7997ff..122146943bf2 100644
--- a/drivers/net/wireless/b43/dma.c
+++ b/drivers/net/wireless/b43/dma.c
@@ -1487,8 +1487,12 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
         const struct b43_dma_ops *ops;
         struct b43_dmaring *ring;
         struct b43_dmadesc_meta *meta;
+        static const struct b43_txstatus fake; /* filled with 0 */
+        const struct b43_txstatus *txstat;
         int slot, firstused;
         bool frame_succeed;
+        int skip;
+        static u8 err_out1, err_out2;
 
         ring = parse_cookie(dev, status->cookie, &slot);
         if (unlikely(!ring))
@@ -1501,13 +1505,36 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
         firstused = ring->current_slot - ring->used_slots + 1;
         if (firstused < 0)
                 firstused = ring->nr_slots + firstused;
+
+        skip = 0;
         if (unlikely(slot != firstused)) {
                 /* This possibly is a firmware bug and will result in
-                 * malfunction, memory leaks and/or stall of DMA functionality. */
-                b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. "
-                       "Expected %d, but got %d\n",
-                       ring->index, firstused, slot);
-                return;
+                 * malfunction, memory leaks and/or stall of DMA functionality.
+                 */
+                if (slot == next_slot(ring, next_slot(ring, firstused))) {
+                        /* If a single header/data pair was missed, skip over
+                         * the first two slots in an attempt to recover.
+                         */
+                        slot = firstused;
+                        skip = 2;
+                        if (!err_out1) {
+                                /* Report the error once. */
+                                b43dbg(dev->wl,
+                                       "Skip on DMA ring %d slot %d.\n",
+                                       ring->index, slot);
+                                err_out1 = 1;
+                        }
+                } else {
+                        /* More than a single header/data pair were missed.
+                         * Report this error once.
+                         */
+                        if (!err_out2)
+                                b43dbg(dev->wl,
+                                       "Out of order TX status report on DMA ring %d. Expected %d, but got %d\n",
+                                       ring->index, firstused, slot);
+                        err_out2 = 1;
+                        return;
+                }
         }
 
         ops = ring->ops;
@@ -1522,11 +1549,13 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
                                slot, firstused, ring->index);
                         break;
                 }
+
                 if (meta->skb) {
                         struct b43_private_tx_info *priv_info =
-                                b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
+                             b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb));
 
-                        unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
+                        unmap_descbuffer(ring, meta->dmaaddr,
+                                         meta->skb->len, 1);
                         kfree(priv_info->bouncebuffer);
                         priv_info->bouncebuffer = NULL;
                 } else {
@@ -1538,8 +1567,9 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
                         struct ieee80211_tx_info *info;
 
                         if (unlikely(!meta->skb)) {
-                                /* This is a scatter-gather fragment of a frame, so
-                                 * the skb pointer must not be NULL. */
+                                /* This is a scatter-gather fragment of a frame,
+                                 * so the skb pointer must not be NULL.
+                                 */
                                 b43dbg(dev->wl, "TX status unexpected NULL skb "
                                        "at slot %d (first=%d) on ring %d\n",
                                        slot, firstused, ring->index);
@@ -1550,9 +1580,18 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
 
                         /*
                          * Call back to inform the ieee80211 subsystem about
-                         * the status of the transmission.
+                         * the status of the transmission. When skipping over
+                         * a missed TX status report, use a status structure
+                         * filled with zeros to indicate that the frame was not
+                         * sent (frame_count 0) and not acknowledged
                          */
-                        frame_succeed = b43_fill_txstatus_report(dev, info, status);
+                        if (unlikely(skip))
+                                txstat = &fake;
+                        else
+                                txstat = status;
+
+                        frame_succeed = b43_fill_txstatus_report(dev, info,
+                                                                 txstat);
 #ifdef CONFIG_B43_DEBUG
                         if (frame_succeed)
                                 ring->nr_succeed_tx_packets++;
@@ -1580,12 +1619,14 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
                 /* Everything unmapped and free'd. So it's not used anymore. */
                 ring->used_slots--;
 
-                if (meta->is_last_fragment) {
+                if (meta->is_last_fragment && !skip) {
                         /* This is the last scatter-gather
                          * fragment of the frame. We are done. */
                         break;
                 }
                 slot = next_slot(ring, slot);
+                if (skip > 0)
+                        --skip;
         }
         if (ring->stopped) {
                 B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME);
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 3c35382ee6c2..e8486c1e091a 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -1564,7 +1564,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
 
         u8 vcm_final = 0;
-        s8 offset[4];
+        s32 offset[4];
         s32 results[8][4] = { };
         s32 results_min[4] = { };
         s32 poll_results[4] = { };
@@ -1615,7 +1615,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
                 }
                 for (i = 0; i < 4; i += 2) {
                         s32 curr;
-                        s32 mind = 40;
+                        s32 mind = 0x100000;
                         s32 minpoll = 249;
                         u8 minvcm = 0;
                         if (2 * core != i)
@@ -1732,7 +1732,7 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
         u8 regs_save_radio[2];
         u16 regs_save_phy[2];
 
-        s8 offset[4];
+        s32 offset[4];
         u8 core;
         u8 rail;
 
@@ -1799,7 +1799,7 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
         }
 
         for (i = 0; i < 4; i++) {
-                s32 mind = 40;
+                s32 mind = 0x100000;
                 u8 minvcm = 0;
                 s32 minpoll = 249;
                 s32 curr;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
index 21a824232478..18d37645e2cd 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
@@ -1137,9 +1137,8 @@ wlc_lcnphy_set_rx_gain_by_distribution(struct brcms_phy *pi,
         gain0_15 = ((biq1 & 0xf) << 12) |
                    ((tia & 0xf) << 8) |
                    ((lna2 & 0x3) << 6) |
-                   ((lna2 & 0x3) << 4) |
-                   ((lna1 & 0x3) << 2) |
-                   ((lna1 & 0x3) << 0);
+                   ((lna2 &
+                     0x3) << 4) | ((lna1 & 0x3) << 2) | ((lna1 & 0x3) << 0);
 
         mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
         mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
@@ -1157,8 +1156,6 @@ wlc_lcnphy_set_rx_gain_by_distribution(struct brcms_phy *pi,
         }
 
         mod_phy_reg(pi, 0x44d, (0x1 << 0), (!trsw) << 0);
-        mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11);
-        mod_phy_reg(pi, 0x4e6, (0x3 << 3), lna1 << 3);
 
 }
 
@@ -1331,43 +1328,6 @@ static u32 wlc_lcnphy_measure_digital_power(struct brcms_phy *pi, u16 nsamples)
         return (iq_est.i_pwr + iq_est.q_pwr) / nsamples;
 }
 
-static bool wlc_lcnphy_rx_iq_cal_gain(struct brcms_phy *pi, u16 biq1_gain,
-                                      u16 tia_gain, u16 lna2_gain)
-{
-        u32 i_thresh_l, q_thresh_l;
-        u32 i_thresh_h, q_thresh_h;
-        struct lcnphy_iq_est iq_est_h, iq_est_l;
-
-        wlc_lcnphy_set_rx_gain_by_distribution(pi, 0, 0, 0, biq1_gain, tia_gain,
-                                               lna2_gain, 0);
-
-        wlc_lcnphy_rx_gain_override_enable(pi, true);
-        wlc_lcnphy_start_tx_tone(pi, 2000, (40 >> 1), 0);
-        udelay(500);
-        write_radio_reg(pi, RADIO_2064_REG112, 0);
-        if (!wlc_lcnphy_rx_iq_est(pi, 1024, 32, &iq_est_l))
-                return false;
-
-        wlc_lcnphy_start_tx_tone(pi, 2000, 40, 0);
-        udelay(500);
-        write_radio_reg(pi, RADIO_2064_REG112, 0);
-        if (!wlc_lcnphy_rx_iq_est(pi, 1024, 32, &iq_est_h))
-                return false;
-
-        i_thresh_l = (iq_est_l.i_pwr << 1);
-        i_thresh_h = (iq_est_l.i_pwr << 2) + iq_est_l.i_pwr;
-
-        q_thresh_l = (iq_est_l.q_pwr << 1);
-        q_thresh_h = (iq_est_l.q_pwr << 2) + iq_est_l.q_pwr;
-        if ((iq_est_h.i_pwr > i_thresh_l) &&
-            (iq_est_h.i_pwr < i_thresh_h) &&
-            (iq_est_h.q_pwr > q_thresh_l) &&
-            (iq_est_h.q_pwr < q_thresh_h))
-                return true;
-
-        return false;
-}
-
 static bool
 wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi,
                      const struct lcnphy_rx_iqcomp *iqcomp,
@@ -1382,8 +1342,8 @@ wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi,
             RFOverrideVal0_old, rfoverride2_old, rfoverride2val_old,
             rfoverride3_old, rfoverride3val_old, rfoverride4_old,
             rfoverride4val_old, afectrlovr_old, afectrlovrval_old;
-        int tia_gain, lna2_gain, biq1_gain;
-        bool set_gain;
+        int tia_gain;
+        u32 received_power, rx_pwr_threshold;
         u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl;
         u16 values_to_save[11];
         s16 *ptr;
@@ -1408,134 +1368,126 @@ wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi,
                 goto cal_done;
         }
 
-        WARN_ON(module != 1);
-        tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
-        wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
-
-        for (i = 0; i < 11; i++)
-                values_to_save[i] =
-                        read_radio_reg(pi, rxiq_cal_rf_reg[i]);
-        Core1TxControl_old = read_phy_reg(pi, 0x631);
-
-        or_phy_reg(pi, 0x631, 0x0015);
-
-        RFOverride0_old = read_phy_reg(pi, 0x44c);
-        RFOverrideVal0_old = read_phy_reg(pi, 0x44d);
-        rfoverride2_old = read_phy_reg(pi, 0x4b0);
-        rfoverride2val_old = read_phy_reg(pi, 0x4b1);
-        rfoverride3_old = read_phy_reg(pi, 0x4f9);
-        rfoverride3val_old = read_phy_reg(pi, 0x4fa);
-        rfoverride4_old = read_phy_reg(pi, 0x938);
-        rfoverride4val_old = read_phy_reg(pi, 0x939);
-        afectrlovr_old = read_phy_reg(pi, 0x43b);
-        afectrlovrval_old = read_phy_reg(pi, 0x43c);
-        old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
-        old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
-
-        tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
-        if (tx_gain_override_old) {
-                wlc_lcnphy_get_tx_gain(pi, &old_gains);
-                tx_gain_index_old = pi_lcn->lcnphy_current_index;
-        }
-
-        wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx);
+        if (module == 1) {
 
-        mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
-        mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
+                tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+                wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
 
-        mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
-        mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
+                for (i = 0; i < 11; i++)
+                        values_to_save[i] =
+                                read_radio_reg(pi, rxiq_cal_rf_reg[i]);
+                Core1TxControl_old = read_phy_reg(pi, 0x631);
+
+                or_phy_reg(pi, 0x631, 0x0015);
+
+                RFOverride0_old = read_phy_reg(pi, 0x44c);
+                RFOverrideVal0_old = read_phy_reg(pi, 0x44d);
+                rfoverride2_old = read_phy_reg(pi, 0x4b0);
+                rfoverride2val_old = read_phy_reg(pi, 0x4b1);
+                rfoverride3_old = read_phy_reg(pi, 0x4f9);
+                rfoverride3val_old = read_phy_reg(pi, 0x4fa);
+                rfoverride4_old = read_phy_reg(pi, 0x938);
+                rfoverride4val_old = read_phy_reg(pi, 0x939);
+                afectrlovr_old = read_phy_reg(pi, 0x43b);
+                afectrlovrval_old = read_phy_reg(pi, 0x43c);
+                old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
+                old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
+
+                tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
+                if (tx_gain_override_old) {
+                        wlc_lcnphy_get_tx_gain(pi, &old_gains);
+                        tx_gain_index_old = pi_lcn->lcnphy_current_index;
+                }
 
-        write_radio_reg(pi, RADIO_2064_REG116, 0x06);
-        write_radio_reg(pi, RADIO_2064_REG12C, 0x07);
-        write_radio_reg(pi, RADIO_2064_REG06A, 0xd3);
-        write_radio_reg(pi, RADIO_2064_REG098, 0x03);
-        write_radio_reg(pi, RADIO_2064_REG00B, 0x7);
-        mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4);
-        write_radio_reg(pi, RADIO_2064_REG01D, 0x01);
-        write_radio_reg(pi, RADIO_2064_REG114, 0x01);
-        write_radio_reg(pi, RADIO_2064_REG02E, 0x10);
-        write_radio_reg(pi, RADIO_2064_REG12A, 0x08);
-
-        mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0);
-        mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0);
-        mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1);
-        mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1);
-        mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2);
-        mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2);
-        mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3);
-        mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3);
-        mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5);
-        mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5);
+                wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx);
 
-        mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
-        mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
+                mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
+                mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
 
-        write_phy_reg(pi, 0x6da, 0xffff);
-        or_phy_reg(pi, 0x6db, 0x3);
+                mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
+                mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
 
-        wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch);
-        set_gain = false;
-
-        lna2_gain = 3;
-        while ((lna2_gain >= 0) && !set_gain) {
-                tia_gain = 4;
-
-                while ((tia_gain >= 0) && !set_gain) {
-                        biq1_gain = 6;
-
-                        while ((biq1_gain >= 0) && !set_gain) {
-                                set_gain = wlc_lcnphy_rx_iq_cal_gain(pi,
-                                                                     (u16)
-                                                                     biq1_gain,
-                                                                     (u16)
-                                                                     tia_gain,
-                                                                     (u16)
-                                                                     lna2_gain);
-                                biq1_gain -= 1;
-                        }
+                write_radio_reg(pi, RADIO_2064_REG116, 0x06);
+                write_radio_reg(pi, RADIO_2064_REG12C, 0x07);
+                write_radio_reg(pi, RADIO_2064_REG06A, 0xd3);
+                write_radio_reg(pi, RADIO_2064_REG098, 0x03);
+                write_radio_reg(pi, RADIO_2064_REG00B, 0x7);
+                mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4);
+                write_radio_reg(pi, RADIO_2064_REG01D, 0x01);
+                write_radio_reg(pi, RADIO_2064_REG114, 0x01);
+                write_radio_reg(pi, RADIO_2064_REG02E, 0x10);
+                write_radio_reg(pi, RADIO_2064_REG12A, 0x08);
+
+                mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0);
+                mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0);
+                mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1);
+                mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1);
+                mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2);
+                mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2);
+                mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3);
+                mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3);
+                mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5);
+                mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5);
+
+                mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
+                mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
+
+                wlc_lcnphy_start_tx_tone(pi, 2000, 120, 0);
+                write_phy_reg(pi, 0x6da, 0xffff);
+                or_phy_reg(pi, 0x6db, 0x3);
+                wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch);
+                wlc_lcnphy_rx_gain_override_enable(pi, true);
+
+                tia_gain = 8;
+                rx_pwr_threshold = 950;
+                while (tia_gain > 0) {
                         tia_gain -= 1;
+                        wlc_lcnphy_set_rx_gain_by_distribution(pi,
+                                                               0, 0, 2, 2,
+                                                               (u16)
+                                                               tia_gain, 1, 0);
+                        udelay(500);
+
+                        received_power =
+                                wlc_lcnphy_measure_digital_power(pi, 2000);
+                        if (received_power < rx_pwr_threshold)
+                                break;
                 }
-                lna2_gain -= 1;
-        }
+                result = wlc_lcnphy_calc_rx_iq_comp(pi, 0xffff);
 
-        if (set_gain)
-                result = wlc_lcnphy_calc_rx_iq_comp(pi, 1024);
-        else
-                result = false;
+                wlc_lcnphy_stop_tx_tone(pi);
 
-        wlc_lcnphy_stop_tx_tone(pi);
+                write_phy_reg(pi, 0x631, Core1TxControl_old);
 
-        write_phy_reg(pi, 0x631, Core1TxControl_old);
-
-        write_phy_reg(pi, 0x44c, RFOverrideVal0_old);
-        write_phy_reg(pi, 0x44d, RFOverrideVal0_old);
-        write_phy_reg(pi, 0x4b0, rfoverride2_old);
-        write_phy_reg(pi, 0x4b1, rfoverride2val_old);
-        write_phy_reg(pi, 0x4f9, rfoverride3_old);
-        write_phy_reg(pi, 0x4fa, rfoverride3val_old);
-        write_phy_reg(pi, 0x938, rfoverride4_old);
-        write_phy_reg(pi, 0x939, rfoverride4val_old);
-        write_phy_reg(pi, 0x43b, afectrlovr_old);
-        write_phy_reg(pi, 0x43c, afectrlovrval_old);
-        write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
-        write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl);
+                write_phy_reg(pi, 0x44c, RFOverrideVal0_old);
+                write_phy_reg(pi, 0x44d, RFOverrideVal0_old);
+                write_phy_reg(pi, 0x4b0, rfoverride2_old);
+                write_phy_reg(pi, 0x4b1, rfoverride2val_old);
+                write_phy_reg(pi, 0x4f9, rfoverride3_old);
+                write_phy_reg(pi, 0x4fa, rfoverride3val_old);
+                write_phy_reg(pi, 0x938, rfoverride4_old);
+                write_phy_reg(pi, 0x939, rfoverride4val_old);
+                write_phy_reg(pi, 0x43b, afectrlovr_old);
+                write_phy_reg(pi, 0x43c, afectrlovrval_old);
+                write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
+                write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl);
 
-        wlc_lcnphy_clear_trsw_override(pi);
+                wlc_lcnphy_clear_trsw_override(pi);
 
-        mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2);
+                mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2);
 
-        for (i = 0; i < 11; i++)
-                write_radio_reg(pi, rxiq_cal_rf_reg[i],
-                                values_to_save[i]);
+                for (i = 0; i < 11; i++)
+                        write_radio_reg(pi, rxiq_cal_rf_reg[i],
+                                        values_to_save[i]);
 
-        if (tx_gain_override_old)
-                wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old);
-        else
-                wlc_lcnphy_disable_tx_gain_override(pi);
+                if (tx_gain_override_old)
+                        wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old);
+                else
+                        wlc_lcnphy_disable_tx_gain_override(pi);
 
-        wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl);
-        wlc_lcnphy_rx_gain_override_enable(pi, false);
+                wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl);
+                wlc_lcnphy_rx_gain_override_enable(pi, false);
+        }
 
 cal_done:
         kfree(ptr);
@@ -1829,17 +1781,6 @@ wlc_lcnphy_radio_2064_channel_tune_4313(struct brcms_phy *pi, u8 channel)
                 write_radio_reg(pi, RADIO_2064_REG038, 3);
                 write_radio_reg(pi, RADIO_2064_REG091, 7);
         }
-
-        if (!(pi->sh->boardflags & BFL_FEM)) {
-                u8 reg038[14] = {0xd, 0xe, 0xd, 0xd, 0xd, 0xc,
-                        0xa, 0xb, 0xb, 0x3, 0x3, 0x2, 0x0, 0x0};
-
-                write_radio_reg(pi, RADIO_2064_REG02A, 0xf);
-                write_radio_reg(pi, RADIO_2064_REG091, 0x3);
-                write_radio_reg(pi, RADIO_2064_REG038, 0x3);
-
-                write_radio_reg(pi, RADIO_2064_REG038, reg038[channel - 1]);
-        }
 }
 
 static int
@@ -2034,16 +1975,6 @@ wlc_lcnphy_set_tssi_mux(struct brcms_phy *pi, enum lcnphy_tssi_mode pos)
                 } else {
                         mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1);
                         mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
-                        mod_radio_reg(pi, RADIO_2064_REG028, 0x1, 0x0);
-                        mod_radio_reg(pi, RADIO_2064_REG11A, 0x4, 1<<2);
-                        mod_radio_reg(pi, RADIO_2064_REG036, 0x10, 0x0);
-                        mod_radio_reg(pi, RADIO_2064_REG11A, 0x10, 1<<4);
-                        mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0);
-                        mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x77);
-                        mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0xe<<1);
-                        mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 1<<7);
-                        mod_radio_reg(pi, RADIO_2064_REG005, 0x7, 1<<1);
-                        mod_radio_reg(pi, RADIO_2064_REG029, 0xf0, 0<<4);
                 }
         } else {
                 mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2);
@@ -2130,14 +2061,12 @@ static void wlc_lcnphy_pwrctrl_rssiparams(struct brcms_phy *pi)
                     (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
 
         mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5));
-        mod_radio_reg(pi, RADIO_2064_REG07C, (1 << 0), (1 << 0));
 }
 
 static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
 {
         struct phytbl_info tab;
         u32 rfseq, ind;
-        u8 tssi_sel;
 
         tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
         tab.tbl_width = 32;
@@ -2159,13 +2088,7 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
 
         mod_phy_reg(pi, 0x503, (0x1 << 4), (1) << 4);
 
-        if (pi->sh->boardflags & BFL_FEM) {
-                tssi_sel = 0x1;
-                wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT);
-        } else {
-                tssi_sel = 0xe;
-                wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_POST_PA);
-        }
+        wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT);
         mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
 
         mod_phy_reg(pi, 0x4a4, (0x1 << 15), (1) << 15);
@@ -2201,10 +2124,9 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
         mod_phy_reg(pi, 0x49a, (0x1ff << 0), (0xff) << 0);
 
         if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
-                mod_radio_reg(pi, RADIO_2064_REG028, 0xf, tssi_sel);
+                mod_radio_reg(pi, RADIO_2064_REG028, 0xf, 0xe);
                 mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
         } else {
-                mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, tssi_sel << 1);
                 mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
                 mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 1 << 3);
         }
@@ -2251,10 +2173,6 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
 
         mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8);
 
-        mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x0);
-        mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0);
-        mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
-
         wlc_lcnphy_pwrctrl_rssiparams(pi);
 }
 
@@ -2873,8 +2791,6 @@ static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi)
                 read_radio_reg(pi, RADIO_2064_REG007) & 1;
         u16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10;
         u16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4;
-        u8 SAVE_bbmult = wlc_lcnphy_get_bbmult(pi);
-
         idleTssi = read_phy_reg(pi, 0x4ab);
         suspend = (0 == (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
                          MCTL_EN_MAC));
@@ -2892,12 +2808,6 @@ static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi)
         mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 1 << 4);
         mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 1 << 2);
         wlc_lcnphy_tssi_setup(pi);
-
-        mod_phy_reg(pi, 0x4d7, (0x1 << 0), (1 << 0));
-        mod_phy_reg(pi, 0x4d7, (0x1 << 6), (1 << 6));
-
-        wlc_lcnphy_set_bbmult(pi, 0x0);
-
         wlc_phy_do_dummy_tx(pi, true, OFF);
         idleTssi = ((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
                     >> 0);
@@ -2919,7 +2829,6 @@ static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi)
 
         mod_phy_reg(pi, 0x44c, (0x1 << 12), (0) << 12);
 
-        wlc_lcnphy_set_bbmult(pi, SAVE_bbmult);
         wlc_lcnphy_set_tx_gain_override(pi, tx_gain_override_old);
         wlc_lcnphy_set_tx_gain(pi, &old_gains);
         wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
@@ -3133,11 +3042,6 @@ static void wlc_lcnphy_tx_pwr_ctrl_init(struct brcms_phy_pub *ppi)
                         wlc_lcnphy_write_table(pi, &tab);
                         tab.tbl_offset++;
                 }
-                mod_phy_reg(pi, 0x4d0, (0x1 << 0), (0) << 0);
-                mod_phy_reg(pi, 0x4d3, (0xff << 0), (0) << 0);
-                mod_phy_reg(pi, 0x4d3, (0xff << 8), (0) << 8);
-                mod_phy_reg(pi, 0x4d0, (0x1 << 4), (0) << 4);
-                mod_phy_reg(pi, 0x4d0, (0x1 << 2), (0) << 2);
 
                 mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7);
 
@@ -3939,6 +3843,7 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(struct brcms_phy *pi)
         target_gains.pad_gain = 21;
         target_gains.dac_gain = 0;
         wlc_lcnphy_set_tx_gain(pi, &target_gains);
+        wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
 
         if (LCNREV_IS(pi->pubpi.phy_rev, 1) || pi_lcn->lcnphy_hw_iqcal_en) {
 
@@ -3949,7 +3854,6 @@ static void wlc_lcnphy_txpwrtbl_iqlo_cal(struct brcms_phy *pi)
                                         lcnphy_recal ? LCNPHY_CAL_RECAL :
                                         LCNPHY_CAL_FULL), false);
         } else {
-                wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
                 wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
         }
 
@@ -4374,22 +4278,17 @@ wlc_lcnphy_load_tx_gain_table(struct brcms_phy *pi,
         if (CHSPEC_IS5G(pi->radio_chanspec))
                 pa_gain = 0x70;
         else
-                pa_gain = 0x60;
+                pa_gain = 0x70;
 
         if (pi->sh->boardflags & BFL_FEM)
                 pa_gain = 0x10;
-
         tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
         tab.tbl_width = 32;
         tab.tbl_len = 1;
         tab.tbl_ptr = &val;
 
         for (j = 0; j < 128; j++) {
-                if (pi->sh->boardflags & BFL_FEM)
-                        gm_gain = gain_table[j].gm;
-                else
-                        gm_gain = 15;
-
+                gm_gain = gain_table[j].gm;
                 val = (((u32) pa_gain << 24) |
                        (gain_table[j].pad << 16) |
                        (gain_table[j].pga << 8) | gm_gain);
@@ -4600,10 +4499,7 @@ static void wlc_radio_2064_init(struct brcms_phy *pi)
 
         write_phy_reg(pi, 0x4ea, 0x4688);
 
-        if (pi->sh->boardflags & BFL_FEM)
-                mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0);
-        else
-                mod_phy_reg(pi, 0x4eb, (0x7 << 0), 3 << 0);
+        mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0);
 
         mod_phy_reg(pi, 0x4eb, (0x7 << 6), 0 << 6);
 
@@ -4614,13 +4510,6 @@ static void wlc_radio_2064_init(struct brcms_phy *pi)
         wlc_lcnphy_rcal(pi);
 
         wlc_lcnphy_rc_cal(pi);
-
-        if (!(pi->sh->boardflags & BFL_FEM)) {
-                write_radio_reg(pi, RADIO_2064_REG032, 0x6f);
-                write_radio_reg(pi, RADIO_2064_REG033, 0x19);
-                write_radio_reg(pi, RADIO_2064_REG039, 0xe);
-        }
-
 }
 
 static void wlc_lcnphy_radio_init(struct brcms_phy *pi)
@@ -4650,20 +4539,22 @@ static void wlc_lcnphy_tbl_init(struct brcms_phy *pi)
                 wlc_lcnphy_write_table(pi, &tab);
         }
 
-        if (!(pi->sh->boardflags & BFL_FEM)) {
-                tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
-                tab.tbl_width = 16;
-                tab.tbl_ptr = &val;
-                tab.tbl_len = 1;
+        tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
+        tab.tbl_width = 16;
+        tab.tbl_ptr = &val;
+        tab.tbl_len = 1;
 
-                val = 150;
-                tab.tbl_offset = 0;
-                wlc_lcnphy_write_table(pi, &tab);
+        val = 114;
+        tab.tbl_offset = 0;
+        wlc_lcnphy_write_table(pi, &tab);
 
-                val = 220;
-                tab.tbl_offset = 1;
-                wlc_lcnphy_write_table(pi, &tab);
-        }
+        val = 130;
+        tab.tbl_offset = 1;
+        wlc_lcnphy_write_table(pi, &tab);
+
+        val = 6;
+        tab.tbl_offset = 8;
+        wlc_lcnphy_write_table(pi, &tab);
 
         if (CHSPEC_IS2G(pi->radio_chanspec)) {
                 if (pi->sh->boardflags & BFL_FEM)
@@ -5055,7 +4946,6 @@ void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi, u16 chanspec)
                 wlc_lcnphy_load_tx_iir_filter(pi, true, 3);
 
         mod_phy_reg(pi, 0x4eb, (0x7 << 3), (1) << 3);
-        wlc_lcnphy_tssi_setup(pi);
 }
 
 void wlc_phy_detach_lcnphy(struct brcms_phy *pi)
@@ -5094,7 +4984,8 @@ bool wlc_phy_attach_lcnphy(struct brcms_phy *pi)
         if (!wlc_phy_txpwr_srom_read_lcnphy(pi))
                 return false;
 
-        if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
+        if ((pi->sh->boardflags & BFL_FEM) &&
+            (LCNREV_IS(pi->pubpi.phy_rev, 1))) {
                 if (pi_lcn->lcnphy_tempsense_option == 3) {
                         pi->hwpwrctrl = true;
                         pi->hwpwrctrl_capable = true;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c b/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c
index b7e95acc2084..622c01ca72c5 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c
@@ -1992,70 +1992,70 @@ static const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0[] = {
 };
 
 static const u16 dot11lcn_sw_ctrl_tbl_4313_rev0[] = {
-        0x0009,
         0x000a,
-        0x0005,
-        0x0006,
         0x0009,
-        0x000a,
-        0x0005,
         0x0006,
-        0x0009,
-        0x000a,
         0x0005,
-        0x0006,
-        0x0009,
         0x000a,
-        0x0005,
-        0x0006,
         0x0009,
-        0x000a,
-        0x0005,
         0x0006,
-        0x0009,
-        0x000a,
         0x0005,
-        0x0006,
-        0x0009,
         0x000a,
-        0x0005,
-        0x0006,
         0x0009,
-        0x000a,
-        0x0005,
         0x0006,
-        0x0009,
-        0x000a,
         0x0005,
-        0x0006,
-        0x0009,
         0x000a,
-        0x0005,
-        0x0006,
         0x0009,
-        0x000a,
-        0x0005,
         0x0006,
-        0x0009,
-        0x000a,
         0x0005,
-        0x0006,
+        0x000a,
         0x0009,
+        0x0006,
+        0x0005,
         0x000a,
+        0x0009,
+        0x0006,
         0x0005,
+        0x000a,
+        0x0009,
         0x0006,
+        0x0005,
+        0x000a,
         0x0009,
+        0x0006,
+        0x0005,
         0x000a,
+        0x0009,
+        0x0006,
         0x0005,
+        0x000a,
+        0x0009,
         0x0006,
+        0x0005,
+        0x000a,
         0x0009,
+        0x0006,
+        0x0005,
         0x000a,
+        0x0009,
+        0x0006,
         0x0005,
+        0x000a,
+        0x0009,
         0x0006,
+        0x0005,
+        0x000a,
         0x0009,
+        0x0006,
+        0x0005,
         0x000a,
+        0x0009,
+        0x0006,
         0x0005,
+        0x000a,
+        0x0009,
         0x0006,
+        0x0005,
 };
 
 static const u16 dot11lcn_sw_ctrl_tbl_rev0[] = {
diff --git a/drivers/net/wireless/iwlegacy/4965-rs.c b/drivers/net/wireless/iwlegacy/4965-rs.c
index e8324b5e5bfe..6c7493c2d698 100644
--- a/drivers/net/wireless/iwlegacy/4965-rs.c
+++ b/drivers/net/wireless/iwlegacy/4965-rs.c
@@ -2152,7 +2152,7 @@ il4965_rs_initialize_lq(struct il_priv *il, struct ieee80211_conf *conf,
         int rate_idx;
         int i;
         u32 rate;
-        u8 use_green = il4965_rs_use_green(il, sta);
+        u8 use_green;
         u8 active_tbl = 0;
         u8 valid_tx_ant;
         struct il_station_priv *sta_priv;
@@ -2160,6 +2160,7 @@ il4965_rs_initialize_lq(struct il_priv *il, struct ieee80211_conf *conf,
         if (!sta || !lq_sta)
                 return;
 
+        use_green = il4965_rs_use_green(il, sta);
         sta_priv = (void *)sta->drv_priv;
 
         i = lq_sta->last_txrate_idx;
diff --git a/drivers/net/wireless/iwlwifi/dvm/lib.c b/drivers/net/wireless/iwlwifi/dvm/lib.c
index 86ea5f4c3939..44ca0e57f9f7 100644
--- a/drivers/net/wireless/iwlwifi/dvm/lib.c
+++ b/drivers/net/wireless/iwlwifi/dvm/lib.c
@@ -1262,6 +1262,15 @@ int iwl_dvm_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
         }
 
         /*
+         * This can happen upon FW ASSERT: we clear the STATUS_FW_ERROR flag
+         * in iwl_down but cancel the workers only later.
+         */
+        if (!priv->ucode_loaded) {
+                IWL_ERR(priv, "Fw not loaded - dropping CMD: %x\n", cmd->id);
+                return -EIO;
+        }
+
+        /*
          * Synchronous commands from this op-mode must hold
          * the mutex, this ensures we don't try to send two
          * (or more) synchronous commands at a time.
diff --git a/drivers/net/wireless/iwlwifi/dvm/rxon.c b/drivers/net/wireless/iwlwifi/dvm/rxon.c
index 23be948cf162..a82b6b39d4ff 100644
--- a/drivers/net/wireless/iwlwifi/dvm/rxon.c
+++ b/drivers/net/wireless/iwlwifi/dvm/rxon.c
@@ -1419,6 +1419,14 @@ void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
 
         mutex_lock(&priv->mutex);
 
+        if (changes & BSS_CHANGED_IDLE && bss_conf->idle) {
+                /*
+                 * If we go idle, then clearly no "passive-no-rx"
+                 * workaround is needed any more, this is a reset.
+                 */
+                iwlagn_lift_passive_no_rx(priv);
+        }
+
         if (unlikely(!iwl_is_ready(priv))) {
                 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
                 mutex_unlock(&priv->mutex);
@@ -1450,16 +1458,6 @@ void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
                         priv->timestamp = bss_conf->sync_tsf;
                         ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
                 } else {
-                        /*
-                         * If we disassociate while there are pending
-                         * frames, just wake up the queues and let the
-                         * frames "escape" ... This shouldn't really
-                         * be happening to start with, but we should
-                         * not get stuck in this case either since it
-                         * can happen if userspace gets confused.
-                         */
-                        iwlagn_lift_passive_no_rx(priv);
-
                         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
 
                         if (ctx->ctxid == IWL_RXON_CTX_BSS)
diff --git a/drivers/net/wireless/iwlwifi/dvm/tx.c b/drivers/net/wireless/iwlwifi/dvm/tx.c
index 6aec2df3bb27..d1a670d7b10c 100644
--- a/drivers/net/wireless/iwlwifi/dvm/tx.c
+++ b/drivers/net/wireless/iwlwifi/dvm/tx.c
@@ -1192,7 +1192,7 @@ int iwlagn_rx_reply_tx(struct iwl_priv *priv, struct iwl_rx_cmd_buffer *rxb,
                         memset(&info->status, 0, sizeof(info->status));
 
                         if (status == TX_STATUS_FAIL_PASSIVE_NO_RX &&
-                            iwl_is_associated_ctx(ctx) && ctx->vif &&
+                            ctx->vif &&
                             ctx->vif->type == NL80211_IFTYPE_STATION) {
                                 /* block and stop all queues */
                                 priv->passive_no_rx = true;
diff --git a/drivers/net/wireless/iwlwifi/dvm/ucode.c b/drivers/net/wireless/iwlwifi/dvm/ucode.c
index 736fe9bb140e..1a4ac9236a44 100644
--- a/drivers/net/wireless/iwlwifi/dvm/ucode.c
+++ b/drivers/net/wireless/iwlwifi/dvm/ucode.c
@@ -367,6 +367,8 @@ int iwl_load_ucode_wait_alive(struct iwl_priv *priv,
                 return -EIO;
         }
 
+        priv->ucode_loaded = true;
+
         if (ucode_type != IWL_UCODE_WOWLAN) {
                 /* delay a bit to give rfkill time to run */
                 msleep(5);
@@ -380,8 +382,6 @@ int iwl_load_ucode_wait_alive(struct iwl_priv *priv,
                 return ret;
         }
 
-        priv->ucode_loaded = true;
-
         return 0;
 }
 
diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index 17bedc50e753..12c4f31ca8fb 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -475,6 +475,10 @@ static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 
         /* If platform's RF_KILL switch is NOT set to KILL */
         hw_rfkill = iwl_is_rfkill_set(trans);
+        if (hw_rfkill)
+                set_bit(STATUS_RFKILL, &trans_pcie->status);
+        else
+                clear_bit(STATUS_RFKILL, &trans_pcie->status);
         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
         if (hw_rfkill && !run_in_rfkill)
                 return -ERFKILL;
@@ -641,6 +645,7 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 
 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 {
+        struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
         bool hw_rfkill;
         int err;
 
@@ -656,6 +661,10 @@ static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
         iwl_enable_rfkill_int(trans);
 
         hw_rfkill = iwl_is_rfkill_set(trans);
+        if (hw_rfkill)
+                set_bit(STATUS_RFKILL, &trans_pcie->status);
+        else
+                clear_bit(STATUS_RFKILL, &trans_pcie->status);
         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 
         return 0;
@@ -694,6 +703,10 @@ static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
                  * op_mode.
                  */
                 hw_rfkill = iwl_is_rfkill_set(trans);
+                if (hw_rfkill)
+                        set_bit(STATUS_RFKILL, &trans_pcie->status);
+                else
+                        clear_bit(STATUS_RFKILL, &trans_pcie->status);
                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
         }
 }
diff --git a/drivers/net/wireless/iwlwifi/pcie/tx.c b/drivers/net/wireless/iwlwifi/pcie/tx.c
index 8595c16f74de..cb5c6792e3a8 100644
--- a/drivers/net/wireless/iwlwifi/pcie/tx.c
+++ b/drivers/net/wireless/iwlwifi/pcie/tx.c
@@ -1264,7 +1264,7 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
         for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
                 int copy = 0;
 
-                if (!cmd->len)
+                if (!cmd->len[i])
                         continue;
 
                 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
diff --git a/drivers/net/wireless/mwifiex/cfg80211.c b/drivers/net/wireless/mwifiex/cfg80211.c
index a44023a7bd57..8aaf56ade4d9 100644
--- a/drivers/net/wireless/mwifiex/cfg80211.c
+++ b/drivers/net/wireless/mwifiex/cfg80211.c
@@ -1892,7 +1892,8 @@ mwifiex_cfg80211_scan(struct wiphy *wiphy,
                 }
         }
 
-        for (i = 0; i < request->n_channels; i++) {
+        for (i = 0; i < min_t(u32, request->n_channels,
+                              MWIFIEX_USER_SCAN_CHAN_MAX); i++) {
                 chan = request->channels[i];
                 priv->user_scan_cfg->chan_list[i].chan_number = chan->hw_value;
                 priv->user_scan_cfg->chan_list[i].radio_type = chan->band;
diff --git a/drivers/net/wireless/mwifiex/pcie.c b/drivers/net/wireless/mwifiex/pcie.c
index 5c395e2e6a2b..feb204613397 100644
--- a/drivers/net/wireless/mwifiex/pcie.c
+++ b/drivers/net/wireless/mwifiex/pcie.c
@@ -1508,6 +1508,7 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter)
                 }
                 memcpy(adapter->upld_buf, skb->data,
                        min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len));
+                skb_push(skb, INTF_HEADER_LEN);
                 if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE,
                                            PCI_DMA_FROMDEVICE))
                         return -1;
diff --git a/drivers/nfc/microread/mei.c b/drivers/nfc/microread/mei.c
index eef38cfd812e..ca33ae193935 100644
--- a/drivers/nfc/microread/mei.c
+++ b/drivers/nfc/microread/mei.c
@@ -22,7 +22,7 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/gpio.h>
-#include <linux/mei_bus.h>
+#include <linux/mei_cl_bus.h>
 
 #include <linux/nfc.h>
 #include <net/nfc/hci.h>
@@ -32,9 +32,6 @@
 
 #define MICROREAD_DRIVER_NAME "microread"
 
-#define MICROREAD_UUID UUID_LE(0x0bb17a78, 0x2a8e, 0x4c50, 0x94, \
-                               0xd4, 0x50, 0x26, 0x67, 0x23, 0x77, 0x5c)
-
 struct mei_nfc_hdr {
         u8 cmd;
         u8 status;
@@ -48,7 +45,7 @@ struct mei_nfc_hdr {
 #define MEI_NFC_MAX_READ (MEI_NFC_HEADER_SIZE + MEI_NFC_MAX_HCI_PAYLOAD)
 
 struct microread_mei_phy {
-        struct mei_device *mei_device;
+        struct mei_cl_device *device;
         struct nfc_hci_dev *hdev;
 
         int powered;
@@ -105,14 +102,14 @@ static int microread_mei_write(void *phy_id, struct sk_buff *skb)
 
         MEI_DUMP_SKB_OUT("mei frame sent", skb);
 
-        r = mei_send(phy->device, skb->data, skb->len);
+        r = mei_cl_send(phy->device, skb->data, skb->len);
         if (r > 0)
                 r = 0;
 
         return r;
 }
 
-static void microread_event_cb(struct mei_device *device, u32 events,
+static void microread_event_cb(struct mei_cl_device *device, u32 events,
                                void *context)
 {
         struct microread_mei_phy *phy = context;
@@ -120,7 +117,7 @@ static void microread_event_cb(struct mei_device *device, u32 events,
         if (phy->hard_fault != 0)
                 return;
 
-        if (events & BIT(MEI_EVENT_RX)) {
+        if (events & BIT(MEI_CL_EVENT_RX)) {
                 struct sk_buff *skb;
                 int reply_size;
 
@@ -128,7 +125,7 @@ static void microread_event_cb(struct mei_device *device, u32 events,
                 if (!skb)
                         return;
 
-                reply_size = mei_recv(device, skb->data, MEI_NFC_MAX_READ);
+                reply_size = mei_cl_recv(device, skb->data, MEI_NFC_MAX_READ);
                 if (reply_size < MEI_NFC_HEADER_SIZE) {
                         kfree(skb);
                         return;
@@ -149,8 +146,8 @@ static struct nfc_phy_ops mei_phy_ops = {
         .disable = microread_mei_disable,
 };
 
-static int microread_mei_probe(struct mei_device *device,
-                               const struct mei_id *id)
+static int microread_mei_probe(struct mei_cl_device *device,
+                               const struct mei_cl_device_id *id)
 {
         struct microread_mei_phy *phy;
         int r;
@@ -164,9 +161,9 @@ static int microread_mei_probe(struct mei_device *device,
         }
 
         phy->device = device;
-        mei_set_clientdata(device, phy);
+        mei_cl_set_drvdata(device, phy);
 
-        r = mei_register_event_cb(device, microread_event_cb, phy);
+        r = mei_cl_register_event_cb(device, microread_event_cb, phy);
         if (r) {
                 pr_err(MICROREAD_DRIVER_NAME ": event cb registration failed\n");
                 goto err_out;
@@ -186,9 +183,9 @@ err_out:
         return r;
 }
 
-static int microread_mei_remove(struct mei_device *device)
+static int microread_mei_remove(struct mei_cl_device *device)
 {
-        struct microread_mei_phy *phy = mei_get_clientdata(device);
+        struct microread_mei_phy *phy = mei_cl_get_drvdata(device);
 
         pr_info("Removing microread\n");
 
@@ -202,16 +199,15 @@ static int microread_mei_remove(struct mei_device *device)
         return 0;
 }
 
-static struct mei_id microread_mei_tbl[] = {
-        { MICROREAD_DRIVER_NAME, MICROREAD_UUID },
+static struct mei_cl_device_id microread_mei_tbl[] = {
+        { MICROREAD_DRIVER_NAME },
 
         /* required last entry */
         { }
 };
-
 MODULE_DEVICE_TABLE(mei, microread_mei_tbl);
 
-static struct mei_driver microread_driver = {
+static struct mei_cl_driver microread_driver = {
         .id_table = microread_mei_tbl,
         .name = MICROREAD_DRIVER_NAME,
 
@@ -225,7 +221,7 @@ static int microread_mei_init(void)
 
         pr_debug(DRIVER_DESC ": %s\n", __func__);
 
-        r = mei_driver_register(&microread_driver);
+        r = mei_cl_driver_register(&microread_driver);
         if (r) {
                 pr_err(MICROREAD_DRIVER_NAME ": driver registration failed\n");
                 return r;
@@ -236,7 +232,7 @@ static int microread_mei_init(void)
 
 static void microread_mei_exit(void)
 {
-        mei_driver_unregister(&microread_driver);
+        mei_cl_driver_unregister(&microread_driver);
 }
 
 module_init(microread_mei_init);
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index dee5dddaa292..5147c210df52 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -53,14 +53,15 @@ static void pci_acpi_wake_dev(acpi_handle handle, u32 event, void *context)
                 return;
         }
 
-        if (!pci_dev->pm_cap || !pci_dev->pme_support
-             || pci_check_pme_status(pci_dev)) {
-                if (pci_dev->pme_poll)
-                        pci_dev->pme_poll = false;
+        /* Clear PME Status if set. */
+        if (pci_dev->pme_support)
+                pci_check_pme_status(pci_dev);
 
-                pci_wakeup_event(pci_dev);
-                pm_runtime_resume(&pci_dev->dev);
-        }
+        if (pci_dev->pme_poll)
+                pci_dev->pme_poll = false;
+
+        pci_wakeup_event(pci_dev);
+        pm_runtime_resume(&pci_dev->dev);
 
         if (pci_dev->subordinate)
                 pci_pme_wakeup_bus(pci_dev->subordinate);
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 1fa1e482a999..79277fb36c6b 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -390,9 +390,10 @@ static void pci_device_shutdown(struct device *dev)
 
         /*
          * Turn off Bus Master bit on the device to tell it to not
-         * continue to do DMA
+         * continue to do DMA. Don't touch devices in D3cold or unknown states.
          */
-        pci_clear_master(pci_dev);
+        if (pci_dev->current_state <= PCI_D3hot)
+                pci_clear_master(pci_dev);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index 08c243ab034e..ed4d09498337 100644
--- a/drivers/pci/pcie/portdrv_pci.c
+++ b/drivers/pci/pcie/portdrv_pci.c
@@ -185,14 +185,6 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = {
 #endif /* !PM */
 
 /*
- * PCIe port runtime suspend is broken for some chipsets, so use a
- * black list to disable runtime PM for these chipsets.
- */
-static const struct pci_device_id port_runtime_pm_black_list[] = {
-        { /* end: all zeroes */ }
-};
-
-/*
  * pcie_portdrv_probe - Probe PCI-Express port devices
  * @dev: PCI-Express port device being probed
  *
@@ -225,16 +217,11 @@ static int pcie_portdrv_probe(struct pci_dev *dev,
          * it by default.
          */
         dev->d3cold_allowed = false;
-        if (!pci_match_id(port_runtime_pm_black_list, dev))
-                pm_runtime_put_noidle(&dev->dev);
-
         return 0;
 }
 
 static void pcie_portdrv_remove(struct pci_dev *dev)
 {
-        if (!pci_match_id(port_runtime_pm_black_list, dev))
-                pm_runtime_get_noresume(&dev->dev);
         pcie_port_device_remove(dev);
         pci_disable_device(dev);
 }
diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c
index b41ac7756a4b..c5d0a08a8747 100644
--- a/drivers/pci/rom.c
+++ b/drivers/pci/rom.c
@@ -100,27 +100,6 @@ size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
         return min((size_t)(image - rom), size);
 }
 
-static loff_t pci_find_rom(struct pci_dev *pdev, size_t *size)
-{
-        struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-        loff_t start;
-
-        /* assign the ROM an address if it doesn't have one */
-        if (res->parent == NULL && pci_assign_resource(pdev, PCI_ROM_RESOURCE))
-                return 0;
-        start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
-        *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
-
-        if (*size == 0)
-                return 0;
-
-        /* Enable ROM space decodes */
-        if (pci_enable_rom(pdev))
-                return 0;
-
-        return start;
-}
-
 /**
  * pci_map_rom - map a PCI ROM to kernel space
  * @pdev: pointer to pci device struct
@@ -135,7 +114,7 @@ static loff_t pci_find_rom(struct pci_dev *pdev, size_t *size)
 void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
 {
         struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-        loff_t start = 0;
+        loff_t start;
         void __iomem *rom;
 
         /*
@@ -154,21 +133,21 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
                         return (void __iomem *)(unsigned long)
                                 pci_resource_start(pdev, PCI_ROM_RESOURCE);
                 } else {
-                        start = pci_find_rom(pdev, size);
-                }
-        }
+                        /* assign the ROM an address if it doesn't have one */
+                        if (res->parent == NULL &&
+                            pci_assign_resource(pdev,PCI_ROM_RESOURCE))
+                                return NULL;
+                        start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
+                        *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
+                        if (*size == 0)
+                                return NULL;
 
-        /*
-         * Some devices may provide ROMs via a source other than the BAR
-         */
-        if (!start && pdev->rom && pdev->romlen) {
-                *size = pdev->romlen;
-                return phys_to_virt(pdev->rom);
+                        /* Enable ROM space decodes */
+                        if (pci_enable_rom(pdev))
+                                return NULL;
+                }
         }
 
-        if (!start)
-                return NULL;
-
         rom = ioremap(start, *size);
         if (!rom) {
                 /* restore enable if ioremap fails */
@@ -202,8 +181,7 @@ void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
         if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY))
                 return;
 
-        if (!pdev->rom || !pdev->romlen)
-                iounmap(rom);
+        iounmap(rom);
 
         /* Disable again before continuing, leave enabled if pci=rom */
         if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW)))
@@ -227,7 +205,24 @@ void pci_cleanup_rom(struct pci_dev *pdev)
         }
 }
 
+/**
+ * pci_platform_rom - provides a pointer to any ROM image provided by the
+ * platform
+ * @pdev: pointer to pci device struct
+ * @size: pointer to receive size of pci window over ROM
+ */
+void __iomem *pci_platform_rom(struct pci_dev *pdev, size_t *size)
+{
+        if (pdev->rom && pdev->romlen) {
+                *size = pdev->romlen;
+                return phys_to_virt((phys_addr_t)pdev->rom);
+        }
+
+        return NULL;
+}
+
 EXPORT_SYMBOL(pci_map_rom);
 EXPORT_SYMBOL(pci_unmap_rom);
 EXPORT_SYMBOL_GPL(pci_enable_rom);
 EXPORT_SYMBOL_GPL(pci_disable_rom);
+EXPORT_SYMBOL(pci_platform_rom);
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 34f51d2d90d2..5a690ce6d60d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -166,6 +166,7 @@ config PINCTRL_SINGLE
         depends on OF
         select PINMUX
         select PINCONF
+        select GENERIC_PINCONF
         help
           This selects the device tree based generic pinctrl driver.
 
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index b0de6e7f1fdb..f8a632dc877b 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -27,6 +27,7 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/machine.h>
+#include <asm-generic/gpio.h>
 #include "core.h"
 #include "devicetree.h"
 #include "pinmux.h"
@@ -277,6 +278,39 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
 }
 
 /**
+ * pinctrl_ready_for_gpio_range() - check if other GPIO pins of
+ * the same GPIO chip are in range
+ * @gpio: gpio pin to check taken from the global GPIO pin space
+ *
+ * This function is complement of pinctrl_match_gpio_range(). If the return
+ * value of pinctrl_match_gpio_range() is NULL, this function could be used
+ * to check whether pinctrl device is ready or not. Maybe some GPIO pins
+ * of the same GPIO chip don't have back-end pinctrl interface.
+ * If the return value is true, it means that pinctrl device is ready & the
+ * certain GPIO pin doesn't have back-end pinctrl device. If the return value
+ * is false, it means that pinctrl device may not be ready.
+ */
+static bool pinctrl_ready_for_gpio_range(unsigned gpio)
+{
+        struct pinctrl_dev *pctldev;
+        struct pinctrl_gpio_range *range = NULL;
+        struct gpio_chip *chip = gpio_to_chip(gpio);
+
+        /* Loop over the pin controllers */
+        list_for_each_entry(pctldev, &pinctrldev_list, node) {
+                /* Loop over the ranges */
+                list_for_each_entry(range, &pctldev->gpio_ranges, node) {
+                        /* Check if any gpio range overlapped with gpio chip */
+                        if (range->base + range->npins - 1 < chip->base ||
+                            range->base > chip->base + chip->ngpio - 1)
+                                continue;
+                        return true;
+                }
+        }
+        return false;
+}
+
+/**
  * pinctrl_get_device_gpio_range() - find device for GPIO range
  * @gpio: the pin to locate the pin controller for
  * @outdev: the pin control device if found
@@ -443,6 +477,8 @@ int pinctrl_request_gpio(unsigned gpio)
 
         ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
         if (ret) {
+                if (pinctrl_ready_for_gpio_range(gpio))
+                        ret = 0;
                 mutex_unlock(&pinctrl_mutex);
                 return ret;
         }
@@ -979,9 +1015,8 @@ static int devm_pinctrl_match(struct device *dev, void *res, void *data)
  */
 void devm_pinctrl_put(struct pinctrl *p)
 {
-        WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
+        WARN_ON(devres_release(p->dev, devm_pinctrl_release,
                                devm_pinctrl_match, p));
-        pinctrl_put(p);
 }
 EXPORT_SYMBOL_GPL(devm_pinctrl_put);
 
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index fd40a11ad645..c7b7cb477129 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -41,7 +41,7 @@ static void dt_free_map(struct pinctrl_dev *pctldev,
                      struct pinctrl_map *map, unsigned num_maps)
 {
         if (pctldev) {
-                struct pinctrl_ops *ops = pctldev->desc->pctlops;
+                const struct pinctrl_ops *ops = pctldev->desc->pctlops;
                 ops->dt_free_map(pctldev, map, num_maps);
         } else {
                 /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
@@ -122,7 +122,7 @@ static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
 {
         struct device_node *np_pctldev;
         struct pinctrl_dev *pctldev;
-        struct pinctrl_ops *ops;
+        const struct pinctrl_ops *ops;
         int ret;
         struct pinctrl_map *map;
         unsigned num_maps;
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index 2d2f0a43d36b..7f34a2b212d2 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -263,7 +263,7 @@ static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
         return;
 }
 
-static struct pinconf_ops mvebu_pinconf_ops = {
+static const struct pinconf_ops mvebu_pinconf_ops = {
         .pin_config_group_get = mvebu_pinconf_group_get,
         .pin_config_group_set = mvebu_pinconf_group_set,
         .pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
@@ -369,7 +369,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
         return -ENOTSUPP;
 }
 
-static struct pinmux_ops mvebu_pinmux_ops = {
+static const struct pinmux_ops mvebu_pinmux_ops = {
         .get_functions_count = mvebu_pinmux_get_funcs_count,
         .get_function_name = mvebu_pinmux_get_func_name,
         .get_function_groups = mvebu_pinmux_get_groups,
@@ -470,7 +470,7 @@ static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
         kfree(map);
 }
 
-static struct pinctrl_ops mvebu_pinctrl_ops = {
+static const struct pinctrl_ops mvebu_pinctrl_ops = {
         .get_groups_count = mvebu_pinctrl_get_groups_count,
         .get_group_name = mvebu_pinctrl_get_group_name,
         .get_group_pins = mvebu_pinctrl_get_group_pins,
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 06c304ac6f7d..9c436858812c 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -12,6 +12,7 @@
 #define pr_fmt(fmt) "generic pinconfig core: " fmt
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/slab.h>
@@ -120,4 +121,17 @@ void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
         }
 }
 
+void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
+                                 struct seq_file *s, unsigned long config)
+{
+        int i;
+
+        for(i = 0; i < ARRAY_SIZE(conf_items); i++) {
+                if (pinconf_to_config_param(config) != conf_items[i].param)
+                        continue;
+                seq_printf(s, "%s: 0x%x", conf_items[i].display,
+                           pinconf_to_config_argument(config));
+        }
+}
+EXPORT_SYMBOL_GPL(pinconf_generic_dump_config);
 #endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index d611ecfcbf70..dae927f91088 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -670,7 +670,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
         struct pinctrl_maps *maps_node;
         struct pinctrl_map const *map;
         struct pinctrl_dev *pctldev = NULL;
-        struct pinconf_ops *confops = NULL;
+        const struct pinconf_ops *confops = NULL;
         int i, j;
         bool found = false;
 
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index bfda73d64eed..92c7267244d2 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -98,6 +98,8 @@ void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
 void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
                               struct seq_file *s, const char *gname);
 
+void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
+                                 struct seq_file *s, unsigned long config);
 #else
 
 static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
@@ -114,4 +116,10 @@ static inline void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
         return;
 }
 
+static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
+                                               struct seq_file *s,
+                                               unsigned long config)
+{
+        return;
+}
 #endif
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
index c542a97c82f3..0cf3fa4a21ae 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -656,7 +656,7 @@ static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
 {
 }
 
-static struct pinmux_ops abx500_pinmux_ops = {
+static const struct pinmux_ops abx500_pinmux_ops = {
         .get_functions_count = abx500_pmx_get_funcs_cnt,
         .get_function_name = abx500_pmx_get_func_name,
         .get_function_groups = abx500_pmx_get_func_groups,
@@ -704,7 +704,7 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
                                  chip->base + offset - 1);
 }
 
-static struct pinctrl_ops abx500_pinctrl_ops = {
+static const struct pinctrl_ops abx500_pinctrl_ops = {
         .get_groups_count = abx500_get_groups_cnt,
         .get_group_name = abx500_get_group_name,
         .get_group_pins = abx500_get_group_pins,
@@ -778,7 +778,7 @@ int abx500_pin_config_set(struct pinctrl_dev *pctldev,
         return ret;
 }
 
-static struct pinconf_ops abx500_pinconf_ops = {
+static const struct pinconf_ops abx500_pinconf_ops = {
         .pin_config_get = abx500_pin_config_get,
         .pin_config_set = abx500_pin_config_set,
 };
@@ -834,6 +834,7 @@ static const struct of_device_id abx500_gpio_match[] = {
         { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
         { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
         { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
+        { }
 };
 
 static int abx500_gpio_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index efb7f10e902a..bddd1dd9efdf 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -294,7 +294,7 @@ static void at91_dt_free_map(struct pinctrl_dev *pctldev,
 {
 }
 
-static struct pinctrl_ops at91_pctrl_ops = {
+static const struct pinctrl_ops at91_pctrl_ops = {
         .get_groups_count       = at91_get_groups_count,
         .get_group_name         = at91_get_group_name,
         .get_group_pins         = at91_get_group_pins,
@@ -696,7 +696,7 @@ static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
         /* Set the pin to some default state, GPIO is usually default */
 }
 
-static struct pinmux_ops at91_pmx_ops = {
+static const struct pinmux_ops at91_pmx_ops = {
         .get_functions_count    = at91_pmx_get_funcs_count,
         .get_function_name      = at91_pmx_get_func_name,
         .get_function_groups    = at91_pmx_get_groups,
@@ -776,7 +776,7 @@ static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 {
 }
 
-static struct pinconf_ops at91_pinconf_ops = {
+static const struct pinconf_ops at91_pinconf_ops = {
         .pin_config_get                 = at91_pinconf_get,
         .pin_config_set                 = at91_pinconf_set,
         .pin_config_dbg_show            = at91_pinconf_dbg_show,
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index 4eb6d2c4e4df..f28d4b08771a 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -795,7 +795,7 @@ out:
         return err;
 }
 
-static struct pinctrl_ops bcm2835_pctl_ops = {
+static const struct pinctrl_ops bcm2835_pctl_ops = {
         .get_groups_count = bcm2835_pctl_get_groups_count,
         .get_group_name = bcm2835_pctl_get_group_name,
         .get_group_pins = bcm2835_pctl_get_group_pins,
@@ -872,7 +872,7 @@ static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
         return 0;
 }
 
-static struct pinmux_ops bcm2835_pmx_ops = {
+static const struct pinmux_ops bcm2835_pmx_ops = {
         .get_functions_count = bcm2835_pmx_get_functions_count,
         .get_function_name = bcm2835_pmx_get_function_name,
         .get_function_groups = bcm2835_pmx_get_function_groups,
@@ -916,7 +916,7 @@ static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
         return 0;
 }
 
-static struct pinconf_ops bcm2835_pinconf_ops = {
+static const struct pinconf_ops bcm2835_pinconf_ops = {
         .pin_config_get = bcm2835_pinconf_get,
         .pin_config_set = bcm2835_pinconf_set,
 };
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
index 1376eb7305db..169ea3e5f777 100644
--- a/drivers/pinctrl/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -286,7 +286,7 @@ static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
 }
 
 /* list of pinctrl callbacks for the pinctrl core */
-static struct pinctrl_ops exynos5440_pctrl_ops = {
+static const struct pinctrl_ops exynos5440_pctrl_ops = {
         .get_groups_count       = exynos5440_get_group_count,
         .get_group_name         = exynos5440_get_group_name,
         .get_group_pins         = exynos5440_get_group_pins,
@@ -374,7 +374,7 @@ static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
 }
 
 /* list of pinmux callbacks for the pinmux vertical in pinctrl core */
-static struct pinmux_ops exynos5440_pinmux_ops = {
+static const struct pinmux_ops exynos5440_pinmux_ops = {
         .get_functions_count    = exynos5440_get_functions_count,
         .get_function_name      = exynos5440_pinmux_get_fname,
         .get_function_groups    = exynos5440_pinmux_get_groups,
@@ -523,7 +523,7 @@ static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
 }
 
 /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
-static struct pinconf_ops exynos5440_pinconf_ops = {
+static const struct pinconf_ops exynos5440_pinconf_ops = {
         .pin_config_get         = exynos5440_pinconf_get,
         .pin_config_set         = exynos5440_pinconf_set,
         .pin_config_group_get   = exynos5440_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
index af97a1f90007..f9b2a1d4854f 100644
--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
@@ -353,7 +353,7 @@ static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
 {
 }
 
-static struct pinconf_ops falcon_pinconf_ops = {
+static const struct pinconf_ops falcon_pinconf_ops = {
         .pin_config_get                 = falcon_pinconf_get,
         .pin_config_set                 = falcon_pinconf_set,
         .pin_config_group_get           = falcon_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 4cebb9c6c5c5..0ef190449eab 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -207,7 +207,7 @@ static void imx_dt_free_map(struct pinctrl_dev *pctldev,
         kfree(map);
 }
 
-static struct pinctrl_ops imx_pctrl_ops = {
+static const struct pinctrl_ops imx_pctrl_ops = {
         .get_groups_count = imx_get_groups_count,
         .get_group_name = imx_get_group_name,
         .get_group_pins = imx_get_group_pins,
@@ -299,7 +299,7 @@ static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
         return 0;
 }
 
-static struct pinmux_ops imx_pmx_ops = {
+static const struct pinmux_ops imx_pmx_ops = {
         .get_functions_count = imx_pmx_get_funcs_count,
         .get_function_name = imx_pmx_get_func_name,
         .get_function_groups = imx_pmx_get_groups,
@@ -397,7 +397,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
         }
 }
 
-static struct pinconf_ops imx_pinconf_ops = {
+static const struct pinconf_ops imx_pinconf_ops = {
         .pin_config_get = imx_pinconf_get,
         .pin_config_set = imx_pinconf_set,
         .pin_config_dbg_show = imx_pinconf_dbg_show,
diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c
index a70384611351..615c5002b757 100644
--- a/drivers/pinctrl/pinctrl-lantiq.c
+++ b/drivers/pinctrl/pinctrl-lantiq.c
@@ -169,7 +169,7 @@ static int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
         return 0;
 }
 
-static struct pinctrl_ops ltq_pctrl_ops = {
+static const struct pinctrl_ops ltq_pctrl_ops = {
         .get_groups_count       = ltq_get_group_count,
         .get_group_name         = ltq_get_group_name,
         .get_group_pins         = ltq_get_group_pins,
@@ -311,7 +311,7 @@ static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev,
         return info->apply_mux(pctrldev, mfp, pin_func);
 }
 
-static struct pinmux_ops ltq_pmx_ops = {
+static const struct pinmux_ops ltq_pmx_ops = {
         .get_functions_count    = ltq_pmx_func_count,
         .get_function_name      = ltq_pmx_func_name,
         .get_function_groups    = ltq_pmx_get_groups,
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
index 23af9f1f9c35..b45c4eb35798 100644
--- a/drivers/pinctrl/pinctrl-mxs.c
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -158,7 +158,7 @@ static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
         kfree(map);
 }
 
-static struct pinctrl_ops mxs_pinctrl_ops = {
+static const struct pinctrl_ops mxs_pinctrl_ops = {
         .get_groups_count = mxs_get_groups_count,
         .get_group_name = mxs_get_group_name,
         .get_group_pins = mxs_get_group_pins,
@@ -219,7 +219,7 @@ static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
         return 0;
 }
 
-static struct pinmux_ops mxs_pinmux_ops = {
+static const struct pinmux_ops mxs_pinmux_ops = {
         .get_functions_count = mxs_pinctrl_get_funcs_count,
         .get_function_name = mxs_pinctrl_get_func_name,
         .get_function_groups = mxs_pinctrl_get_func_groups,
@@ -319,7 +319,7 @@ static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
                 seq_printf(s, "0x%lx", config);
 }
 
-static struct pinconf_ops mxs_pinconf_ops = {
+static const struct pinconf_ops mxs_pinconf_ops = {
         .pin_config_get = mxs_pinconf_get,
         .pin_config_set = mxs_pinconf_set,
         .pin_config_group_get = mxs_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 36d20293de5c..2328baaa86bf 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -1764,7 +1764,7 @@ int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
         return 0;
 }
 
-static struct pinctrl_ops nmk_pinctrl_ops = {
+static const struct pinctrl_ops nmk_pinctrl_ops = {
         .get_groups_count = nmk_get_groups_cnt,
         .get_group_name = nmk_get_group_name,
         .get_group_pins = nmk_get_group_pins,
@@ -1975,7 +1975,7 @@ static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
         /* Set the pin to some default state, GPIO is usually default */
 }
 
-static struct pinmux_ops nmk_pinmux_ops = {
+static const struct pinmux_ops nmk_pinmux_ops = {
         .get_functions_count = nmk_pmx_get_funcs_cnt,
         .get_function_name = nmk_pmx_get_func_name,
         .get_function_groups = nmk_pmx_get_func_groups,
@@ -2089,7 +2089,7 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
         return 0;
 }
 
-static struct pinconf_ops nmk_pinconf_ops = {
+static const struct pinconf_ops nmk_pinconf_ops = {
         .pin_config_get = nmk_pin_config_get,
         .pin_config_set = nmk_pin_config_set,
 };
diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c
index 1f49bb02a6af..05e11de1d144 100644
--- a/drivers/pinctrl/pinctrl-pxa3xx.c
+++ b/drivers/pinctrl/pinctrl-pxa3xx.c
@@ -53,7 +53,7 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
         return 0;
 }
 
-static struct pinctrl_ops pxa3xx_pctrl_ops = {
+static const struct pinctrl_ops pxa3xx_pctrl_ops = {
         .get_groups_count = pxa3xx_get_groups_count,
         .get_group_name = pxa3xx_get_group_name,
         .get_group_pins = pxa3xx_get_group_pins,
@@ -161,7 +161,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
         return 0;
 }
 
-static struct pinmux_ops pxa3xx_pmx_ops = {
+static const struct pinmux_ops pxa3xx_pmx_ops = {
         .get_functions_count    = pxa3xx_pmx_get_funcs_count,
         .get_function_name      = pxa3xx_pmx_get_func_name,
         .get_function_groups    = pxa3xx_pmx_get_groups,
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index f206df175656..3475b92b24a4 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -214,7 +214,7 @@ static void samsung_dt_free_map(struct pinctrl_dev *pctldev,
 }
 
 /* list of pinctrl callbacks for the pinctrl core */
-static struct pinctrl_ops samsung_pctrl_ops = {
+static const struct pinctrl_ops samsung_pctrl_ops = {
         .get_groups_count       = samsung_get_group_count,
         .get_group_name         = samsung_get_group_name,
         .get_group_pins         = samsung_get_group_pins,
@@ -357,7 +357,7 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
 }
 
 /* list of pinmux callbacks for the pinmux vertical in pinctrl core */
-static struct pinmux_ops samsung_pinmux_ops = {
+static const struct pinmux_ops samsung_pinmux_ops = {
         .get_functions_count    = samsung_get_functions_count,
         .get_function_name      = samsung_pinmux_get_fname,
         .get_function_groups    = samsung_pinmux_get_groups,
@@ -468,7 +468,7 @@ static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev,
 }
 
 /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
-static struct pinconf_ops samsung_pinconf_ops = {
+static const struct pinconf_ops samsung_pinconf_ops = {
         .pin_config_get         = samsung_pinconf_get,
         .pin_config_set         = samsung_pinconf_set,
         .pin_config_group_get   = samsung_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 5c32e880bcb2..e35dabd3135d 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -22,8 +22,10 @@
 
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf-generic.h>
 
 #include "core.h"
+#include "pinconf.h"
 
 #define DRIVER_NAME                     "pinctrl-single"
 #define PCS_MUX_PINS_NAME               "pinctrl-single,pins"
@@ -59,6 +61,33 @@ struct pcs_func_vals {
 };
 
 /**
+ * struct pcs_conf_vals - pinconf parameter, pinconf register offset
+ * and value, enable, disable, mask
+ * @param:      config parameter
+ * @val:        user input bits in the pinconf register
+ * @enable:     enable bits in the pinconf register
+ * @disable:    disable bits in the pinconf register
+ * @mask:       mask bits in the register value
+ */
+struct pcs_conf_vals {
+        enum pin_config_param param;
+        unsigned val;
+        unsigned enable;
+        unsigned disable;
+        unsigned mask;
+};
+
+/**
+ * struct pcs_conf_type - pinconf property name, pinconf param pair
+ * @name:       property name in DTS file
+ * @param:      config parameter
+ */
+struct pcs_conf_type {
+        const char *name;
+        enum pin_config_param param;
+};
+
+/**
  * struct pcs_function - pinctrl function
  * @name:       pinctrl function name
  * @vals:       register and vals array
@@ -73,6 +102,22 @@ struct pcs_function {
         unsigned nvals;
         const char **pgnames;
         int npgnames;
+        struct pcs_conf_vals *conf;
+        int nconfs;
+        struct list_head node;
+};
+
+/**
+ * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
+ * @offset:     offset base of pins
+ * @npins:      number pins with the same mux value of gpio function
+ * @gpiofunc:   mux value of gpio function
+ * @node:       list node
+ */
+struct pcs_gpiofunc_range {
+        unsigned offset;
+        unsigned npins;
+        unsigned gpiofunc;
         struct list_head node;
 };
 
@@ -117,12 +162,14 @@ struct pcs_name {
  * @fshift:     function register shift
  * @foff:       value to turn mux off
  * @fmax:       max number of functions in fmask
+ * @is_pinconf: whether supports pinconf
  * @names:      array of register names for pins
  * @pins:       physical pins on the SoC
  * @pgtree:     pingroup index radix tree
  * @ftree:      function index radix tree
  * @pingroups:  list of pingroups
  * @functions:  list of functions
+ * @gpiofuncs:  list of gpio functions
  * @ngroups:    number of pingroups
  * @nfuncs:     number of functions
  * @desc:       pin controller descriptor
@@ -142,12 +189,14 @@ struct pcs_device {
         unsigned foff;
         unsigned fmax;
         bool bits_per_mux;
+        bool is_pinconf;
         struct pcs_name *names;
         struct pcs_data pins;
         struct radix_tree_root pgtree;
         struct radix_tree_root ftree;
         struct list_head pingroups;
         struct list_head functions;
+        struct list_head gpiofuncs;
         unsigned ngroups;
         unsigned nfuncs;
         struct pinctrl_desc desc;
@@ -155,6 +204,16 @@ struct pcs_device {
         void (*write)(unsigned val, void __iomem *reg);
 };
 
+static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
+                           unsigned long *config);
+static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
+                           unsigned long config);
+
+static enum pin_config_param pcs_bias[] = {
+        PIN_CONFIG_BIAS_PULL_DOWN,
+        PIN_CONFIG_BIAS_PULL_UP,
+};
+
 /*
  * REVISIT: Reads and writes could eventually use regmap or something
  * generic. But at least on omaps, some mux registers are performance
@@ -270,7 +329,7 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
                                 struct device_node *np_config,
                                 struct pinctrl_map **map, unsigned *num_maps);
 
-static struct pinctrl_ops pcs_pinctrl_ops = {
+static const struct pinctrl_ops pcs_pinctrl_ops = {
         .get_groups_count = pcs_get_groups_count,
         .get_group_name = pcs_get_group_name,
         .get_group_pins = pcs_get_group_pins,
@@ -326,6 +385,28 @@ static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
         return 0;
 }
 
+static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
+                            struct pcs_function **func)
+{
+        struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+        struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
+        const struct pinctrl_setting_mux *setting;
+        unsigned fselector;
+
+        /* If pin is not described in DTS & enabled, mux_setting is NULL. */
+        setting = pdesc->mux_setting;
+        if (!setting)
+                return -ENOTSUPP;
+        fselector = setting->func;
+        *func = radix_tree_lookup(&pcs->ftree, fselector);
+        if (!(*func)) {
+                dev_err(pcs->dev, "%s could not find function%i\n",
+                        __func__, fselector);
+                return -ENOTSUPP;
+        }
+        return 0;
+}
+
 static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
         unsigned group)
 {
@@ -334,6 +415,9 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
         int i;
 
         pcs = pinctrl_dev_get_drvdata(pctldev);
+        /* If function mask is null, needn't enable it. */
+        if (!pcs->fmask)
+                return 0;
         func = radix_tree_lookup(&pcs->ftree, fselector);
         if (!func)
                 return -EINVAL;
@@ -368,6 +452,10 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
         int i;
 
         pcs = pinctrl_dev_get_drvdata(pctldev);
+        /* If function mask is null, needn't disable it. */
+        if (!pcs->fmask)
+                return;
+
         func = radix_tree_lookup(&pcs->ftree, fselector);
         if (!func) {
                 dev_err(pcs->dev, "%s could not find function%i\n",
@@ -403,12 +491,33 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
 }
 
 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
-                        struct pinctrl_gpio_range *range, unsigned offset)
+                            struct pinctrl_gpio_range *range, unsigned pin)
 {
-        return -ENOTSUPP;
+        struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+        struct pcs_gpiofunc_range *frange = NULL;
+        struct list_head *pos, *tmp;
+        int mux_bytes = 0;
+        unsigned data;
+
+        /* If function mask is null, return directly. */
+        if (!pcs->fmask)
+                return -ENOTSUPP;
+
+        list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
+                frange = list_entry(pos, struct pcs_gpiofunc_range, node);
+                if (pin >= frange->offset + frange->npins
+                        || pin < frange->offset)
+                        continue;
+                mux_bytes = pcs->width / BITS_PER_BYTE;
+                data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
+                data |= frange->gpiofunc;
+                pcs->write(data, pcs->base + pin * mux_bytes);
+                break;
+        }
+        return 0;
 }
 
-static struct pinmux_ops pcs_pinmux_ops = {
+static const struct pinmux_ops pcs_pinmux_ops = {
         .get_functions_count = pcs_get_functions_count,
         .get_function_name = pcs_get_function_name,
         .get_function_groups = pcs_get_function_groups,
@@ -417,32 +526,191 @@ static struct pinmux_ops pcs_pinmux_ops = {
         .gpio_request_enable = pcs_request_gpio,
 };
 
+/* Clear BIAS value */
+static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
+{
+        unsigned long config;
+        int i;
+        for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
+                config = pinconf_to_config_packed(pcs_bias[i], 0);
+                pcs_pinconf_set(pctldev, pin, config);
+        }
+}
+
+/*
+ * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
+ * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
+ */
+static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
+{
+        unsigned long config;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
+                config = pinconf_to_config_packed(pcs_bias[i], 0);
+                if (!pcs_pinconf_get(pctldev, pin, &config))
+                        goto out;
+        }
+        return true;
+out:
+        return false;
+}
+
 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
                                 unsigned pin, unsigned long *config)
 {
+        struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+        struct pcs_function *func;
+        enum pin_config_param param;
+        unsigned offset = 0, data = 0, i, j, ret;
+
+        ret = pcs_get_function(pctldev, pin, &func);
+        if (ret)
+                return ret;
+
+        for (i = 0; i < func->nconfs; i++) {
+                param = pinconf_to_config_param(*config);
+                if (param == PIN_CONFIG_BIAS_DISABLE) {
+                        if (pcs_pinconf_bias_disable(pctldev, pin)) {
+                                *config = 0;
+                                return 0;
+                        } else {
+                                return -ENOTSUPP;
+                        }
+                } else if (param != func->conf[i].param) {
+                        continue;
+                }
+
+                offset = pin * (pcs->width / BITS_PER_BYTE);
+                data = pcs->read(pcs->base + offset) & func->conf[i].mask;
+                switch (func->conf[i].param) {
+                /* 4 parameters */
+                case PIN_CONFIG_BIAS_PULL_DOWN:
+                case PIN_CONFIG_BIAS_PULL_UP:
+                case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+                        if ((data != func->conf[i].enable) ||
+                            (data == func->conf[i].disable))
+                                return -ENOTSUPP;
+                        *config = 0;
+                        break;
+                /* 2 parameters */
+                case PIN_CONFIG_INPUT_SCHMITT:
+                        for (j = 0; j < func->nconfs; j++) {
+                                switch (func->conf[j].param) {
+                                case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+                                        if (data != func->conf[j].enable)
+                                                return -ENOTSUPP;
+                                        break;
+                                default:
+                                        break;
+                                }
+                        }
+                        *config = data;
+                        break;
+                case PIN_CONFIG_DRIVE_STRENGTH:
+                case PIN_CONFIG_SLEW_RATE:
+                default:
+                        *config = data;
+                        break;
+                }
+                return 0;
+        }
         return -ENOTSUPP;
 }
 
 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
                                 unsigned pin, unsigned long config)
 {
+        struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+        struct pcs_function *func;
+        unsigned offset = 0, shift = 0, arg = 0, i, data, ret;
+        u16 argument;
+
+        ret = pcs_get_function(pctldev, pin, &func);
+        if (ret)
+                return ret;
+
+        for (i = 0; i < func->nconfs; i++) {
+                if (pinconf_to_config_param(config) == func->conf[i].param) {
+                        offset = pin * (pcs->width / BITS_PER_BYTE);
+                        data = pcs->read(pcs->base + offset);
+                        argument = pinconf_to_config_argument(config);
+                        switch (func->conf[i].param) {
+                        /* 2 parameters */
+                        case PIN_CONFIG_INPUT_SCHMITT:
+                        case PIN_CONFIG_DRIVE_STRENGTH:
+                        case PIN_CONFIG_SLEW_RATE:
+                                shift = ffs(func->conf[i].mask) - 1;
+                                arg = pinconf_to_config_argument(config);
+                                data &= ~func->conf[i].mask;
+                                data |= (arg << shift) & func->conf[i].mask;
+                                break;
+                        /* 4 parameters */
+                        case PIN_CONFIG_BIAS_DISABLE:
+                                pcs_pinconf_clear_bias(pctldev, pin);
+                                break;
+                        case PIN_CONFIG_BIAS_PULL_DOWN:
+                        case PIN_CONFIG_BIAS_PULL_UP:
+                                if (argument)
+                                        pcs_pinconf_clear_bias(pctldev, pin);
+                                /* fall through */
+                        case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+                                data &= ~func->conf[i].mask;
+                                if (argument)
+                                        data |= func->conf[i].enable;
+                                else
+                                        data |= func->conf[i].disable;
+                                break;
+                        default:
+                                return -ENOTSUPP;
+                        }
+                        pcs->write(data, pcs->base + offset);
+                        return 0;
+                }
+        }
         return -ENOTSUPP;
 }
 
 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
                                 unsigned group, unsigned long *config)
 {
-        return -ENOTSUPP;
+        const unsigned *pins;
+        unsigned npins, old = 0;
+        int i, ret;
+
+        ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
+        if (ret)
+                return ret;
+        for (i = 0; i < npins; i++) {
+                if (pcs_pinconf_get(pctldev, pins[i], config))
+                        return -ENOTSUPP;
+                /* configs do not match between two pins */
+                if (i && (old != *config))
+                        return -ENOTSUPP;
+                old = *config;
+        }
+        return 0;
 }
 
 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
                                 unsigned group, unsigned long config)
 {
-        return -ENOTSUPP;
+        const unsigned *pins;
+        unsigned npins;
+        int i, ret;
+
+        ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
+        if (ret)
+                return ret;
+        for (i = 0; i < npins; i++) {
+                if (pcs_pinconf_set(pctldev, pins[i], config))
+                        return -ENOTSUPP;
+        }
+        return 0;
 }
 
 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
-                                struct seq_file *s, unsigned offset)
+                                struct seq_file *s, unsigned pin)
 {
 }
 
@@ -451,13 +719,22 @@ static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 {
 }
 
-static struct pinconf_ops pcs_pinconf_ops = {
+static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
+                                        struct seq_file *s,
+                                        unsigned long config)
+{
+        pinconf_generic_dump_config(pctldev, s, config);
+}
+
+static const struct pinconf_ops pcs_pinconf_ops = {
         .pin_config_get = pcs_pinconf_get,
         .pin_config_set = pcs_pinconf_set,
         .pin_config_group_get = pcs_pinconf_group_get,
         .pin_config_group_set = pcs_pinconf_group_set,
         .pin_config_dbg_show = pcs_pinconf_dbg_show,
         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
+        .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
+        .is_generic = true,
 };
 
 /**
@@ -648,11 +925,157 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
         return index;
 }
 
+/*
+ * check whether data matches enable bits or disable bits
+ * Return value: 1 for matching enable bits, 0 for matching disable bits,
+ *               and negative value for matching failure.
+ */
+static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
+{
+        int ret = -EINVAL;
+
+        if (data == enable)
+                ret = 1;
+        else if (data == disable)
+                ret = 0;
+        return ret;
+}
+
+static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
+                       unsigned value, unsigned enable, unsigned disable,
+                       unsigned mask)
+{
+        (*conf)->param = param;
+        (*conf)->val = value;
+        (*conf)->enable = enable;
+        (*conf)->disable = disable;
+        (*conf)->mask = mask;
+        (*conf)++;
+}
+
+static void add_setting(unsigned long **setting, enum pin_config_param param,
+                        unsigned arg)
+{
+        **setting = pinconf_to_config_packed(param, arg);
+        (*setting)++;
+}
+
+/* add pinconf setting with 2 parameters */
+static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
+                          const char *name, enum pin_config_param param,
+                          struct pcs_conf_vals **conf, unsigned long **settings)
+{
+        unsigned value[2];
+        int ret;
+
+        ret = of_property_read_u32_array(np, name, value, 2);
+        if (ret)
+                return;
+        /* set value & mask */
+        value[0] &= value[1];
+        /* skip enable & disable */
+        add_config(conf, param, value[0], 0, 0, value[1]);
+        add_setting(settings, param, value[0]);
+}
+
+/* add pinconf setting with 4 parameters */
+static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
+                          const char *name, enum pin_config_param param,
+                          struct pcs_conf_vals **conf, unsigned long **settings)
+{
+        unsigned value[4];
+        int ret;
+
+        /* value to set, enable, disable, mask */
+        ret = of_property_read_u32_array(np, name, value, 4);
+        if (ret)
+                return;
+        if (!value[3]) {
+                dev_err(pcs->dev, "mask field of the property can't be 0\n");
+                return;
+        }
+        value[0] &= value[3];
+        value[1] &= value[3];
+        value[2] &= value[3];
+        ret = pcs_config_match(value[0], value[1], value[2]);
+        if (ret < 0)
+                dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
+        add_config(conf, param, value[0], value[1], value[2], value[3]);
+        add_setting(settings, param, ret);
+}
+
+static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
+                             struct pcs_function *func,
+                             struct pinctrl_map **map)
+
+{
+        struct pinctrl_map *m = *map;
+        int i = 0, nconfs = 0;
+        unsigned long *settings = NULL, *s = NULL;
+        struct pcs_conf_vals *conf = NULL;
+        struct pcs_conf_type prop2[] = {
+                { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
+                { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
+                { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
+        };
+        struct pcs_conf_type prop4[] = {
+                { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
+                { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
+                { "pinctrl-single,input-schmitt-enable",
+                        PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
+        };
+
+        /* If pinconf isn't supported, don't parse properties in below. */
+        if (!pcs->is_pinconf)
+                return 0;
+
+        /* cacluate how much properties are supported in current node */
+        for (i = 0; i < ARRAY_SIZE(prop2); i++) {
+                if (of_find_property(np, prop2[i].name, NULL))
+                        nconfs++;
+        }
+        for (i = 0; i < ARRAY_SIZE(prop4); i++) {
+                if (of_find_property(np, prop4[i].name, NULL))
+                        nconfs++;
+        }
+        if (!nconfs)
+                return 0;
+
+        func->conf = devm_kzalloc(pcs->dev,
+                                  sizeof(struct pcs_conf_vals) * nconfs,
+                                  GFP_KERNEL);
+        if (!func->conf)
+                return -ENOMEM;
+        func->nconfs = nconfs;
+        conf = &(func->conf[0]);
+        m++;
+        settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
+                                GFP_KERNEL);
+        if (!settings)
+                return -ENOMEM;
+        s = &settings[0];
+
+        for (i = 0; i < ARRAY_SIZE(prop2); i++)
+                pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
+                              &conf, &s);
+        for (i = 0; i < ARRAY_SIZE(prop4); i++)
+                pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
+                              &conf, &s);
+        m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
+        m->data.configs.group_or_pin = np->name;
+        m->data.configs.configs = settings;
+        m->data.configs.num_configs = nconfs;
+        return 0;
+}
+
+static void pcs_free_pingroups(struct pcs_device *pcs);
+
 /**
  * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
  * @pcs: pinctrl driver instance
  * @np: device node of the mux entry
  * @map: map entry
+ * @num_maps: number of map
  * @pgnames: pingroup names
  *
  * Note that this binding currently supports only sets of one register + value.
@@ -669,6 +1092,7 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
                                                 struct device_node *np,
                                                 struct pinctrl_map **map,
+                                                unsigned *num_maps,
                                                 const char **pgnames)
 {
         struct pcs_func_vals *vals;
@@ -741,8 +1165,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
         (*map)->data.mux.group = np->name;
         (*map)->data.mux.function = np->name;
 
+        if (pcs->is_pinconf) {
+                if (pcs_parse_pinconf(pcs, np, function, map))
+                        goto free_pingroups;
+                *num_maps = 2;
+        } else {
+                *num_maps = 1;
+        }
         return 0;
 
+free_pingroups:
+        pcs_free_pingroups(pcs);
+        *num_maps = 1;
 free_function:
         pcs_remove_function(pcs, function);
 
@@ -771,7 +1205,8 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 
         pcs = pinctrl_dev_get_drvdata(pctldev);
 
-        *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL);
+        /* create 2 maps. One is for pinmux, and the other is for pinconf. */
+        *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
         if (!*map)
                 return -ENOMEM;
 
@@ -783,13 +1218,13 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
                 goto free_map;
         }
 
-        ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames);
+        ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps,
+                                          pgnames);
         if (ret < 0) {
                 dev_err(pcs->dev, "no pins entries for %s\n",
                         np_config->name);
                 goto free_pgnames;
         }
-        *num_maps = 1;
 
         return 0;
 
@@ -879,6 +1314,37 @@ static void pcs_free_resources(struct pcs_device *pcs)
 
 static struct of_device_id pcs_of_match[];
 
+static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
+{
+        const char *propname = "pinctrl-single,gpio-range";
+        const char *cellname = "#pinctrl-single,gpio-range-cells";
+        struct of_phandle_args gpiospec;
+        struct pcs_gpiofunc_range *range;
+        int ret, i;
+
+        for (i = 0; ; i++) {
+                ret = of_parse_phandle_with_args(node, propname, cellname,
+                                                 i, &gpiospec);
+                /* Do not treat it as error. Only treat it as end condition. */
+                if (ret) {
+                        ret = 0;
+                        break;
+                }
+                range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
+                if (!range) {
+                        ret = -ENOMEM;
+                        break;
+                }
+                range->offset = gpiospec.args[0];
+                range->npins = gpiospec.args[1];
+                range->gpiofunc = gpiospec.args[2];
+                mutex_lock(&pcs->mutex);
+                list_add_tail(&range->node, &pcs->gpiofuncs);
+                mutex_unlock(&pcs->mutex);
+        }
+        return ret;
+}
+
 static int pcs_probe(struct platform_device *pdev)
 {
         struct device_node *np = pdev->dev.of_node;
@@ -900,14 +1366,23 @@ static int pcs_probe(struct platform_device *pdev)
         mutex_init(&pcs->mutex);
         INIT_LIST_HEAD(&pcs->pingroups);
         INIT_LIST_HEAD(&pcs->functions);
+        INIT_LIST_HEAD(&pcs->gpiofuncs);
+        pcs->is_pinconf = match->data;
 
         PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
                          "register width not specified\n");
 
-        PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask,
-                         "function register mask not specified\n");
-        pcs->fshift = ffs(pcs->fmask) - 1;
-        pcs->fmax = pcs->fmask >> pcs->fshift;
+        ret = of_property_read_u32(np, "pinctrl-single,function-mask",
+                                   &pcs->fmask);
+        if (!ret) {
+                pcs->fshift = ffs(pcs->fmask) - 1;
+                pcs->fmax = pcs->fmask >> pcs->fshift;
+        } else {
+                /* If mask property doesn't exist, function mux is invalid. */
+                pcs->fmask = 0;
+                pcs->fshift = 0;
+                pcs->fmax = 0;
+        }
 
         ret = of_property_read_u32(np, "pinctrl-single,function-off",
                                         &pcs->foff);
@@ -961,7 +1436,8 @@ static int pcs_probe(struct platform_device *pdev)
         pcs->desc.name = DRIVER_NAME;
         pcs->desc.pctlops = &pcs_pinctrl_ops;
         pcs->desc.pmxops = &pcs_pinmux_ops;
-        pcs->desc.confops = &pcs_pinconf_ops;
+        if (pcs->is_pinconf)
+                pcs->desc.confops = &pcs_pinconf_ops;
         pcs->desc.owner = THIS_MODULE;
 
         ret = pcs_allocate_pin_table(pcs);
@@ -975,6 +1451,10 @@ static int pcs_probe(struct platform_device *pdev)
                 goto free;
         }
 
+        ret = pcs_add_gpio_func(np, pcs);
+        if (ret < 0)
+                goto free;
+
         dev_info(pcs->dev, "%i pins at pa %p size %u\n",
                  pcs->desc.npins, pcs->base, pcs->size);
 
@@ -999,7 +1479,8 @@ static int pcs_remove(struct platform_device *pdev)
 }
 
 static struct of_device_id pcs_of_match[] = {
-        { .compatible = DRIVER_NAME, },
+        { .compatible = "pinctrl-single", .data = (void *)false },
+        { .compatible = "pinconf-single", .data = (void *)true },
         { },
 };
 MODULE_DEVICE_TABLE(of, pcs_of_match);
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index d02498b30c6e..0990a721758e 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -979,7 +979,7 @@ static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
         kfree(map);
 }
 
-static struct pinctrl_ops sirfsoc_pctrl_ops = {
+static const struct pinctrl_ops sirfsoc_pctrl_ops = {
         .get_groups_count = sirfsoc_get_groups_count,
         .get_group_name = sirfsoc_get_group_name,
         .get_group_pins = sirfsoc_get_group_pins,
@@ -1181,7 +1181,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
         return 0;
 }
 
-static struct pinmux_ops sirfsoc_pinmux_ops = {
+static const struct pinmux_ops sirfsoc_pinmux_ops = {
         .enable = sirfsoc_pinmux_enable,
         .disable = sirfsoc_pinmux_disable,
         .get_functions_count = sirfsoc_pinmux_get_funcs_count,
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 80b11e3415bc..cb491d6ba601 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -30,482 +30,856 @@
 static const struct sunxi_desc_pin sun4i_a10_pins[] = {
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ERXD3 */
+                SUNXI_FUNCTION(0x3, "spi1"),            /* CS0 */
+                SUNXI_FUNCTION(0x4, "uart2")),          /* RTS */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ERXD2 */
+                SUNXI_FUNCTION(0x3, "spi1"),            /* CLK */
+                SUNXI_FUNCTION(0x4, "uart2")),          /* CTS */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ERXD1 */
+                SUNXI_FUNCTION(0x3, "spi1"),            /* MOSI */
+                SUNXI_FUNCTION(0x4, "uart2")),          /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ERXD0 */
+                SUNXI_FUNCTION(0x3, "spi1"),            /* MISO */
+                SUNXI_FUNCTION(0x4, "uart2")),          /* RX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ETXD3 */
+                SUNXI_FUNCTION(0x3, "spi1")),           /* CS1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ETXD2 */
+                SUNXI_FUNCTION(0x3, "spi3")),           /* CS0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ETXD1 */
+                SUNXI_FUNCTION(0x3, "spi3")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ETXD0 */
+                SUNXI_FUNCTION(0x3, "spi3")),           /* MOSI */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ERXCK */
+                SUNXI_FUNCTION(0x3, "spi3")),           /* MISO */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ERXERR */
+                SUNXI_FUNCTION(0x3, "spi3")),           /* CS1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ERXDV */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* EMDC */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* RX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* EMDIO */
+                SUNXI_FUNCTION(0x3, "uart6"),           /* TX */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* RTS */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ETXEN */
+                SUNXI_FUNCTION(0x3, "uart6"),           /* RX */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* CTS */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ETXCK */
+                SUNXI_FUNCTION(0x3, "uart7"),           /* TX */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* DTR */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ECRS */
+                SUNXI_FUNCTION(0x3, "uart7"),           /* RX */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* DSR */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ECOL */
+                SUNXI_FUNCTION(0x3, "can"),             /* TX */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* DCD */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "wemac"),           /* ETXERR */
+                SUNXI_FUNCTION(0x3, "can"),             /* RX */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* RING */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c0")),           /* SCK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c0")),           /* SDA */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "pwm")),            /* PWM0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ir0")),            /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ir0")),            /* RX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2s"),             /* MCLK */
+                SUNXI_FUNCTION(0x3, "ac97")),           /* MCLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2s"),             /* BCLK */
+                SUNXI_FUNCTION(0x3, "ac97")),           /* BCLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2s"),             /* LRCK */
+                SUNXI_FUNCTION(0x3, "ac97")),           /* SYNC */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2s"),             /* DO0 */
+                SUNXI_FUNCTION(0x3, "ac97")),           /* DO */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2s")),            /* DO1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2s")),            /* DO2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2s")),            /* DO3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2s"),             /* DI */
+                SUNXI_FUNCTION(0x3, "ac97")),           /* DI */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi2")),           /* CS1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi2"),            /* CS0 */
+                SUNXI_FUNCTION(0x3, "jtag")),           /* MS0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi2"),            /* CLK */
+                SUNXI_FUNCTION(0x3, "jtag")),           /* CK0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi2"),            /* MOSI */
+                SUNXI_FUNCTION(0x3, "jtag")),           /* DO0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi2"),            /* MISO */
+                SUNXI_FUNCTION(0x3, "jtag")),           /* DI0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c1")),           /* SCK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c1")),           /* SDA */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c2")),           /* SCK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c2")),           /* SDA */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
-                SUNXI_FUNCTION(0x2, "uart0")),          /* TX */
+                SUNXI_FUNCTION(0x2, "uart0"),           /* TX */
+                SUNXI_FUNCTION(0x3, "ir1")),            /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
-                SUNXI_FUNCTION(0x2, "uart0")),          /* RX */
+                SUNXI_FUNCTION(0x2, "uart0"),           /* RX */
+                SUNXI_FUNCTION(0x3, "ir1")),            /* RX */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NWE */
+                SUNXI_FUNCTION(0x3, "spi0")),           /* MOSI */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NALE */
+                SUNXI_FUNCTION(0x3, "spi0")),           /* MISO */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NCLE */
+                SUNXI_FUNCTION(0x3, "spi0")),           /* SCK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NCE1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NCE0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),  /* NRE# */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NRB0 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* CMD */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NRB1 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ0 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ1 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ2 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ3 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NDQ4 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NDQ5 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NDQ6 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NDQ7 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NWP */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NCE2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NCE3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NCE4 */
+                SUNXI_FUNCTION(0x3, "spi2")),           /* CS0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NCE5 */
+                SUNXI_FUNCTION(0x3, "spi2")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NCE6 */
+                SUNXI_FUNCTION(0x3, "spi2")),           /* MOSI */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NCE7 */
+                SUNXI_FUNCTION(0x3, "spi2")),           /* MISO */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x3, "spi0")),           /* CS0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NDQS */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D0 */
+                SUNXI_FUNCTION(0x3, "lvds0")),          /* VP0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D1 */
+                SUNXI_FUNCTION(0x3, "lvds0")),          /* VN0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D2 */
+                SUNXI_FUNCTION(0x3, "lvds0")),          /* VP1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D3 */
+                SUNXI_FUNCTION(0x3, "lvds0")),          /* VN1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D4 */
+                SUNXI_FUNCTION(0x3, "lvds0")),          /* VP2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D5 */
+                SUNXI_FUNCTION(0x3, "lvds0")),          /* VN2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D6 */
+                SUNXI_FUNCTION(0x3, "lvds0")),          /* VPC */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D7 */
+                SUNXI_FUNCTION(0x3, "lvds0")),          /* VNC */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D8 */
+                SUNXI_FUNCTION(0x3, "lvds0")),          /* VP3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D9 */
+                SUNXI_FUNCTION(0x3, "lvds0")),          /* VM3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D10 */
+                SUNXI_FUNCTION(0x3, "lvds1")),          /* VP0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D11 */
+                SUNXI_FUNCTION(0x3, "lvds1")),          /* VN0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D12 */
+                SUNXI_FUNCTION(0x3, "lvds1")),          /* VP1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D13 */
+                SUNXI_FUNCTION(0x3, "lvds1")),          /* VN1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D14 */
+                SUNXI_FUNCTION(0x3, "lvds1")),          /* VP2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D15 */
+                SUNXI_FUNCTION(0x3, "lvds1")),          /* VN2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D16 */
+                SUNXI_FUNCTION(0x3, "lvds1")),          /* VPC */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D17 */
+                SUNXI_FUNCTION(0x3, "lvds1")),          /* VNC */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D18 */
+                SUNXI_FUNCTION(0x3, "lvds1")),          /* VP3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D19 */
+                SUNXI_FUNCTION(0x3, "lvds1")),          /* VN3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D20 */
+                SUNXI_FUNCTION(0x3, "csi1")),           /* MCLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D21 */
+                SUNXI_FUNCTION(0x3, "sim")),            /* VPPEN */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D22 */
+                SUNXI_FUNCTION(0x3, "sim")),            /* VPPPP */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* D23 */
+                SUNXI_FUNCTION(0x3, "sim")),            /* DET */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* CLK */
+                SUNXI_FUNCTION(0x3, "sim")),            /* VCCEN */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* DE */
+                SUNXI_FUNCTION(0x3, "sim")),            /* RST */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* HSYNC */
+                SUNXI_FUNCTION(0x3, "sim")),            /* SCK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0"),            /* VSYNC */
+                SUNXI_FUNCTION(0x3, "sim")),            /* SDA */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* CLK */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* PCK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* ERR */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* CK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* SYNC */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* HSYNC */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* DVLD */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* VSYNC */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* D0 */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* D0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* D1 */
+                SUNXI_FUNCTION(0x3, "csi0"),            /* D1 */
+                SUNXI_FUNCTION(0x4, "sim")),            /* VPPEN */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* D2 */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* D2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* D3 */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* D3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* D4 */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* D4 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* D5 */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* D5 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* D6 */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* D6 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts0"),             /* D7 */
+                SUNXI_FUNCTION(0x3, "csi0")),           /* D7 */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc0"),            /* D1 */
+                SUNXI_FUNCTION(0x4, "jtag")),           /* MSI */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc0"),            /* D0 */
+                SUNXI_FUNCTION(0x4, "jtag")),           /* DI1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc0"),            /* CLK */
                 SUNXI_FUNCTION(0x4, "uart0")),          /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc0"),            /* CMD */
+                SUNXI_FUNCTION(0x4, "jtag")),           /* DO1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc0"),            /* D3 */
                 SUNXI_FUNCTION(0x4, "uart0")),          /* RX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc0"),            /* D2 */
+                SUNXI_FUNCTION(0x4, "jtag")),           /* CK1 */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* CLK */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* PCK */
+                SUNXI_FUNCTION(0x4, "mmc1")),           /* CMD */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* ERR */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* CK */
+                SUNXI_FUNCTION(0x4, "mmc1")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* SYNC */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* HSYNC */
+                SUNXI_FUNCTION(0x4, "mmc1")),           /* D0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* DVLD */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* VSYNC */
+                SUNXI_FUNCTION(0x4, "mmc1")),           /* D1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* D0 */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* D0 */
+                SUNXI_FUNCTION(0x4, "mmc1"),            /* D2 */
+                SUNXI_FUNCTION(0x5, "csi0")),           /* D8 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* D1 */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* D1 */
+                SUNXI_FUNCTION(0x4, "mmc1"),            /* D3 */
+                SUNXI_FUNCTION(0x5, "csi0")),           /* D9 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* D2 */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* D2 */
+                SUNXI_FUNCTION(0x4, "uart3"),           /* TX */
+                SUNXI_FUNCTION(0x5, "csi0")),           /* D10 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* D3 */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* D3 */
+                SUNXI_FUNCTION(0x4, "uart3"),           /* RX */
+                SUNXI_FUNCTION(0x5, "csi0")),           /* D11 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* D4 */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* D4 */
+                SUNXI_FUNCTION(0x4, "uart3"),           /* RTS */
+                SUNXI_FUNCTION(0x5, "csi0")),           /* D12 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* D5 */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* D5 */
+                SUNXI_FUNCTION(0x4, "uart3"),           /* CTS */
+                SUNXI_FUNCTION(0x5, "csi0")),           /* D13 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* D6 */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* D6 */
+                SUNXI_FUNCTION(0x4, "uart4"),           /* TX */
+                SUNXI_FUNCTION(0x5, "csi0")),           /* D14 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ts1"),             /* D7 */
+                SUNXI_FUNCTION(0x3, "csi1"),            /* D7 */
+                SUNXI_FUNCTION(0x4, "uart4"),           /* RX */
+                SUNXI_FUNCTION(0x5, "csi0")),           /* D15 */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D0 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAA0 */
+                SUNXI_FUNCTION(0x4, "uart3"),           /* TX */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D1 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAA1 */
+                SUNXI_FUNCTION(0x4, "uart3"),           /* RX */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D2 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAA2 */
+                SUNXI_FUNCTION(0x4, "uart3"),           /* RTS */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D3 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAIRQ */
+                SUNXI_FUNCTION(0x4, "uart3"),           /* CTS */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D4 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD0 */
+                SUNXI_FUNCTION(0x4, "uart4"),           /* TX */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D4 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D5 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD1 */
+                SUNXI_FUNCTION(0x4, "uart4"),           /* RX */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D5 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D6 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD2 */
+                SUNXI_FUNCTION(0x4, "uart5"),           /* TX */
+                SUNXI_FUNCTION(0x5, "ms"),              /* BS */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D6 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D7 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD3 */
+                SUNXI_FUNCTION(0x4, "uart5"),           /* RX */
+                SUNXI_FUNCTION(0x5, "ms"),              /* CLK */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D7 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D8 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD4 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* IN0 */
+                SUNXI_FUNCTION(0x5, "ms"),              /* D0 */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D8 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D9 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD5 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* IN1 */
+                SUNXI_FUNCTION(0x5, "ms"),              /* D1 */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D9 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D10 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD6 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* IN2 */
+                SUNXI_FUNCTION(0x5, "ms"),              /* D2 */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D10 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D11 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD7 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* IN3 */
+                SUNXI_FUNCTION(0x5, "ms"),              /* D3 */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D11 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D12 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD8 */
+                SUNXI_FUNCTION(0x4, "ps2"),             /* SCK1 */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D12 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D13 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD9 */
+                SUNXI_FUNCTION(0x4, "ps2"),             /* SDA1 */
+                SUNXI_FUNCTION(0x5, "sim"),             /* RST */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D13 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D14 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD10 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* IN4 */
+                SUNXI_FUNCTION(0x5, "sim"),             /* VPPEN */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D14 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D15 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD11 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* IN5 */
+                SUNXI_FUNCTION(0x5, "sim"),             /* VPPPP */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D15 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D16 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD12 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* IN6 */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D16 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D17 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD13 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* IN7 */
+                SUNXI_FUNCTION(0x5, "sim"),             /* VCCEN */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D17 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D18 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD14 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* OUT0 */
+                SUNXI_FUNCTION(0x5, "sim"),             /* SCK */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D18 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D19 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAD15 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* OUT1 */
+                SUNXI_FUNCTION(0x5, "sim"),             /* SDA */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D19 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D20 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAOE */
+                SUNXI_FUNCTION(0x4, "can"),             /* TX */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D20 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D21 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATADREQ */
+                SUNXI_FUNCTION(0x4, "can"),             /* RX */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D21 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D22 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATADACK */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* OUT2 */
+                SUNXI_FUNCTION(0x5, "mmc1"),            /* CMD */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D22 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* D23 */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATACS0 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* OUT3 */
+                SUNXI_FUNCTION(0x5, "mmc1"),            /* CLK */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* D23 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* CLK */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATACS1 */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* OUT4 */
+                SUNXI_FUNCTION(0x5, "mmc1"),            /* D0 */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* PCLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* DE */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAIORDY */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* OUT5 */
+                SUNXI_FUNCTION(0x5, "mmc1"),            /* D1 */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* FIELD */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* HSYNC */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAIOR */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* OUT6 */
+                SUNXI_FUNCTION(0x5, "mmc1"),            /* D2 */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* HSYNC */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd1"),            /* VSYNC */
+                SUNXI_FUNCTION(0x3, "pata"),            /* ATAIOW */
+                SUNXI_FUNCTION(0x4, "keypad"),          /* OUT7 */
+                SUNXI_FUNCTION(0x5, "mmc1"),            /* D3 */
+                SUNXI_FUNCTION(0x7, "csi1")),           /* VSYNC */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -518,277 +892,401 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
                 SUNXI_FUNCTION(0x1, "gpio_out")),
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "pwm")),            /* PWM1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc3")),           /* CMD */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc3")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc3")),           /* D0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc3")),           /* D1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc3")),           /* D2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc3")),           /* D3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi0"),            /* CS0 */
+                SUNXI_FUNCTION(0x3, "uart5")),          /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi0"),            /* CLK */
+                SUNXI_FUNCTION(0x3, "uart5")),          /* RX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi0"),            /* MOSI */
+                SUNXI_FUNCTION(0x3, "uart6")),          /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi0"),            /* MISO */
+                SUNXI_FUNCTION(0x3, "uart6")),          /* RX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi0"),            /* CS1 */
+                SUNXI_FUNCTION(0x3, "ps2"),             /* SCK1 */
+                SUNXI_FUNCTION(0x4, "timer4")),         /* TCLKIN0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi1"),            /* CS1 */
+                SUNXI_FUNCTION(0x3, "ps2"),             /* SDA1 */
+                SUNXI_FUNCTION(0x4, "timer5")),         /* TCLKIN1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi1"),            /* CS0 */
+                SUNXI_FUNCTION(0x3, "uart2")),          /* RTS */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi1"),            /* CLK */
+                SUNXI_FUNCTION(0x3, "uart2")),          /* CTS */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi1"),            /* MOSI */
+                SUNXI_FUNCTION(0x3, "uart2")),          /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi1"),            /* MISO */
+                SUNXI_FUNCTION(0x3, "uart2")),          /* RX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ps2"),             /* SCK0 */
+                SUNXI_FUNCTION(0x3, "uart7"),           /* TX */
+                SUNXI_FUNCTION(0x4, "hdmi")),           /* HSCL */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ps2"),             /* SDA0 */
+                SUNXI_FUNCTION(0x3, "uart7"),           /* RX */
+                SUNXI_FUNCTION(0x4, "hdmi")),           /* HSDA */
 };
 
 static const struct sunxi_desc_pin sun5i_a13_pins[] = {
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c0")),           /* SCK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c0")),           /* SDA */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "pwm")),
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ir0")),            /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "ir0")),            /* RX */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi2")),           /* CS1 */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c1")),           /* SCK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c1")),           /* SDA */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c2")),           /* SCK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "i2c2")),           /* SDA */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NWE */
+                SUNXI_FUNCTION(0x3, "spi0")),           /* MOSI */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NALE */
+                SUNXI_FUNCTION(0x3, "spi0")),           /* MISO */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NCLE */
+                SUNXI_FUNCTION(0x3, "spi0")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NCE1 */
+                SUNXI_FUNCTION(0x3, "spi0")),           /* CS0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NCE0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0")),          /* NRE */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NRB0 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* CMD */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NRB1 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ0 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ1 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ2 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ3 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ4 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D4 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ5 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D5 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ6 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D6 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQ7 */
+                SUNXI_FUNCTION(0x3, "mmc2")),           /* D7 */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "nand0"),           /* NDQS */
+                SUNXI_FUNCTION(0x4, "uart3")),          /* RTS */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D4 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D5 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D6 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D7 */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D10 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D11 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D12 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D13 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D14 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D15 */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D18 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D19 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D20 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D21 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D22 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* D23 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* DE */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* HSYNC */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "lcd0")),           /* VSYNC */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* PCLK */
+                SUNXI_FUNCTION(0x4, "spi2")),           /* CS0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* MCLK */
+                SUNXI_FUNCTION(0x4, "spi2")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* HSYNC */
+                SUNXI_FUNCTION(0x4, "spi2")),           /* MOSI */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* VSYNC */
+                SUNXI_FUNCTION(0x4, "spi2")),           /* MISO */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* D0 */
+                SUNXI_FUNCTION(0x4, "mmc2")),           /* D0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* D1 */
+                SUNXI_FUNCTION(0x4, "mmc2")),           /* D1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* D2 */
+                SUNXI_FUNCTION(0x4, "mmc2")),           /* D2 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* D3 */
+                SUNXI_FUNCTION(0x4, "mmc2")),           /* D3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* D4 */
+                SUNXI_FUNCTION(0x4, "mmc2")),           /* CMD */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* D5 */
+                SUNXI_FUNCTION(0x4, "mmc2")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* D6 */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x3, "csi0"),            /* D7 */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* RX */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x4, "mmc0")),           /* D1 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x4, "mmc0")),           /* D0 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x4, "mmc0")),           /* CLK */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x4, "mmc0")),           /* CMD */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x4, "mmc0")),           /* D3 */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x4, "mmc0")),           /* D2 */
         /* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -802,24 +1300,34 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc1"),            /* CMD */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
                 SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "mmc1"),            /* CLK */
                 SUNXI_FUNCTION(0x4, "uart1")),          /* RX */
-        /* Hole */
+/* Hole */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi1"),            /* CS0 */
+                SUNXI_FUNCTION(0x3, "uart3")),          /* TX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi1"),            /* CLK */
+                SUNXI_FUNCTION(0x3, "uart3")),          /* RX */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi1"),            /* MOSI */
+                SUNXI_FUNCTION(0x3, "uart3")),          /* CTS */
         SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
                 SUNXI_FUNCTION(0x0, "gpio_in"),
-                SUNXI_FUNCTION(0x1, "gpio_out")),
+                SUNXI_FUNCTION(0x1, "gpio_out"),
+                SUNXI_FUNCTION(0x2, "spi1"),            /* MISO */
+                SUNXI_FUNCTION(0x3, "uart3")),          /* RTS */
 };
 
 static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
@@ -1029,7 +1537,7 @@ static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
         kfree(map);
 }
 
-static struct pinctrl_ops sunxi_pctrl_ops = {
+static const struct pinctrl_ops sunxi_pctrl_ops = {
         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
         .dt_free_map            = sunxi_pctrl_dt_free_map,
         .get_groups_count       = sunxi_pctrl_get_groups_count,
@@ -1098,7 +1606,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
         return 0;
 }
 
-static struct pinconf_ops sunxi_pconf_ops = {
+static const struct pinconf_ops sunxi_pconf_ops = {
         .pin_config_group_get   = sunxi_pconf_group_get,
         .pin_config_group_set   = sunxi_pconf_group_set,
 };
@@ -1204,7 +1712,7 @@ error:
         return ret;
 }
 
-static struct pinmux_ops sunxi_pmx_ops = {
+static const struct pinmux_ops sunxi_pmx_ops = {
         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
         .get_function_name      = sunxi_pmx_get_func_name,
         .get_function_groups    = sunxi_pmx_get_func_groups,
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index f195d77a3572..2fa9bc6cd7ab 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -316,7 +316,7 @@ static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
         return 0;
 }
 
-static struct pinctrl_ops tegra_pinctrl_ops = {
+static const struct pinctrl_ops tegra_pinctrl_ops = {
         .get_groups_count = tegra_pinctrl_get_groups_count,
         .get_group_name = tegra_pinctrl_get_group_name,
         .get_group_pins = tegra_pinctrl_get_group_pins,
@@ -401,7 +401,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 }
 
-static struct pinmux_ops tegra_pinmux_ops = {
+static const struct pinmux_ops tegra_pinmux_ops = {
         .get_functions_count = tegra_pinctrl_get_funcs_count,
         .get_function_name = tegra_pinctrl_get_func_name,
         .get_function_groups = tegra_pinctrl_get_func_groups,
@@ -676,7 +676,7 @@ static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 }
 #endif
 
-static struct pinconf_ops tegra_pinconf_ops = {
+static const struct pinconf_ops tegra_pinconf_ops = {
         .pin_config_get = tegra_pinconf_get,
         .pin_config_set = tegra_pinconf_set,
         .pin_config_group_get = tegra_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 2b5772550836..6a3a7503e6a0 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -860,7 +860,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
         seq_printf(s, " " DRIVER_NAME);
 }
 
-static struct pinctrl_ops u300_pctrl_ops = {
+static const struct pinctrl_ops u300_pctrl_ops = {
         .get_groups_count = u300_get_groups_count,
         .get_group_name = u300_get_group_name,
         .get_group_pins = u300_get_group_pins,
@@ -1003,7 +1003,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
         return 0;
 }
 
-static struct pinmux_ops u300_pmx_ops = {
+static const struct pinmux_ops u300_pmx_ops = {
         .get_functions_count = u300_pmx_get_funcs_count,
         .get_function_name = u300_pmx_get_func_name,
         .get_function_groups = u300_pmx_get_groups,
@@ -1046,7 +1046,7 @@ static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
         return 0;
 }
 
-static struct pinconf_ops u300_pconf_ops = {
+static const struct pinconf_ops u300_pconf_ops = {
         .is_generic = true,
         .pin_config_get = u300_pin_config_get,
         .pin_config_set = u300_pin_config_set,
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index 068224efa6fa..f2977cff8366 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -553,7 +553,7 @@ int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
         return ret;
 }
 
-static struct pinconf_ops xway_pinconf_ops = {
+static const struct pinconf_ops xway_pinconf_ops = {
         .pin_config_get = xway_pinconf_get,
         .pin_config_set = xway_pinconf_set,
         .pin_config_group_set = xway_pinconf_group_set,
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index c3340f54d2ad..af16f8f6ab6c 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -10,6 +10,7 @@ config PINCTRL_SH_PFC
         select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
         select PINMUX
         select PINCONF
+        select GENERIC_PINCONF
         def_bool y
         help
           This enables pin control drivers for SH and SH Mobile platforms
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 970ddff2b0b6..feef89792568 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -10,7 +10,6 @@
  */
 
 #define DRV_NAME "sh-pfc"
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
 #include <linux/bitops.h>
 #include <linux/err.h>
@@ -30,10 +29,8 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
         struct resource *res;
         int k;
 
-        if (pdev->num_resources == 0) {
-                pfc->num_windows = 0;
-                return 0;
-        }
+        if (pdev->num_resources == 0)
+                return -EINVAL;
 
         pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
                                    sizeof(*pfc->window), GFP_NOWAIT);
@@ -59,11 +56,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
                                          unsigned long address)
 {
         struct sh_pfc_window *window;
-        int k;
+        unsigned int i;
 
         /* scan through physical windows and convert address */
-        for (k = 0; k < pfc->num_windows; k++) {
-                window = pfc->window + k;
+        for (i = 0; i < pfc->num_windows; i++) {
+                window = pfc->window + i;
 
                 if (address < window->phys)
                         continue;
@@ -74,11 +71,32 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
                 return window->virt + (address - window->phys);
         }
 
-        /* no windows defined, register must be 1:1 mapped virt:phys */
-        return (void __iomem *)address;
+        BUG();
 }
 
-static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
+int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
+{
+        unsigned int offset;
+        unsigned int i;
+
+        if (pfc->info->ranges == NULL)
+                return pin;
+
+        for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
+                const struct pinmux_range *range = &pfc->info->ranges[i];
+
+                if (pin <= range->end)
+                        return pin >= range->begin
+                             ? offset + pin - range->begin : -1;
+
+                offset += range->end - range->begin + 1;
+        }
+
+        return -EINVAL;
+}
+
+static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
+                                const struct pinmux_range *r)
 {
         if (enum_id < r->begin)
                 return 0;
@@ -89,8 +107,8 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
         return 1;
 }
 
-static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
-                                         unsigned long reg_width)
+unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
+                                  unsigned long reg_width)
 {
         switch (reg_width) {
         case 8:
@@ -105,8 +123,8 @@ static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
         return 0;
 }
 
-static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
-                                 unsigned long reg_width, unsigned long data)
+void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
+                          unsigned long data)
 {
         switch (reg_width) {
         case 8:
@@ -123,39 +141,8 @@ static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
         BUG();
 }
 
-int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
-{
-        unsigned long pos;
-
-        pos = dr->reg_width - (in_pos + 1);
-
-        pr_debug("read_bit: addr = %lx, pos = %ld, "
-                 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
-
-        return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
-}
-
-void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
-                      unsigned long value)
-{
-        unsigned long pos;
-
-        pos = dr->reg_width - (in_pos + 1);
-
-        pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
-                 "r_width = %ld\n",
-                 dr->reg, !!value, pos, dr->reg_width);
-
-        if (value)
-                set_bit(pos, &dr->reg_shadow);
-        else
-                clear_bit(pos, &dr->reg_shadow);
-
-        sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
-}
-
 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
-                                     struct pinmux_cfg_reg *crp,
+                                     const struct pinmux_cfg_reg *crp,
                                      unsigned long in_pos,
                                      void __iomem **mapped_regp,
                                      unsigned long *maskp,
@@ -176,24 +163,8 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
         }
 }
 
-static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
-                                  struct pinmux_cfg_reg *crp,
-                                  unsigned long field)
-{
-        void __iomem *mapped_reg;
-        unsigned long mask, pos;
-
-        sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
-
-        pr_debug("read_reg: addr = %lx, field = %ld, "
-                 "r_width = %ld, f_width = %ld\n",
-                 crp->reg, field, crp->reg_width, crp->field_width);
-
-        return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
-}
-
 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
-                                    struct pinmux_cfg_reg *crp,
+                                    const struct pinmux_cfg_reg *crp,
                                     unsigned long field, unsigned long value)
 {
         void __iomem *mapped_reg;
@@ -201,9 +172,9 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 
         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 
-        pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
-                 "r_width = %ld, f_width = %ld\n",
-                 crp->reg, value, field, crp->reg_width, crp->field_width);
+        dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
+                "r_width = %ld, f_width = %ld\n",
+                crp->reg, value, field, crp->reg_width, crp->field_width);
 
         mask = ~(mask << pos);
         value = value << pos;
@@ -220,83 +191,11 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 }
 
-static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
-{
-        struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
-        struct pinmux_data_reg *data_reg;
-        int k, n;
-
-        if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
-                return -1;
-
-        k = 0;
-        while (1) {
-                data_reg = pfc->info->data_regs + k;
-
-                if (!data_reg->reg_width)
-                        break;
-
-                data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
-
-                for (n = 0; n < data_reg->reg_width; n++) {
-                        if (data_reg->enum_ids[n] == gpiop->enum_id) {
-                                gpiop->flags &= ~PINMUX_FLAG_DREG;
-                                gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
-                                gpiop->flags &= ~PINMUX_FLAG_DBIT;
-                                gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
-                                return 0;
-                        }
-                }
-                k++;
-        }
-
-        BUG();
-
-        return -1;
-}
-
-static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
-{
-        struct pinmux_data_reg *drp;
-        int k;
-
-        for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++)
-                sh_pfc_setup_data_reg(pfc, k);
-
-        k = 0;
-        while (1) {
-                drp = pfc->info->data_regs + k;
-
-                if (!drp->reg_width)
-                        break;
-
-                drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
-                                                      drp->reg_width);
-                k++;
-        }
-}
-
-int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
-                        struct pinmux_data_reg **drp, int *bitp)
-{
-        struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
-        int k, n;
-
-        if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
-                return -1;
-
-        k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
-        n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
-        *drp = pfc->info->data_regs + k;
-        *bitp = n;
-        return 0;
-}
-
 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
-                                 struct pinmux_cfg_reg **crp, int *fieldp,
-                                 int *valuep, unsigned long **cntp)
+                                 const struct pinmux_cfg_reg **crp, int *fieldp,
+                                 int *valuep)
 {
-        struct pinmux_cfg_reg *config_reg;
+        const struct pinmux_cfg_reg *config_reg;
         unsigned long r_width, f_width, curr_width, ncomb;
         int k, m, n, pos, bit_pos;
 
@@ -324,7 +223,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
                                         *crp = config_reg;
                                         *fieldp = m;
                                         *valuep = n;
-                                        *cntp = &config_reg->cnt[m];
                                         return 0;
                                 }
                         }
@@ -334,47 +232,39 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
                 k++;
         }
 
-        return -1;
+        return -EINVAL;
 }
 
-int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
-                        pinmux_enum_t *enum_idp)
+static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
+                              pinmux_enum_t *enum_idp)
 {
-        pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id;
-        pinmux_enum_t *data = pfc->info->gpio_data;
+        const pinmux_enum_t *data = pfc->info->gpio_data;
         int k;
 
-        if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) {
-                if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) {
-                        pr_err("non data/mark enum_id for gpio %d\n", gpio);
-                        return -1;
-                }
-        }
-
         if (pos) {
                 *enum_idp = data[pos + 1];
                 return pos + 1;
         }
 
         for (k = 0; k < pfc->info->gpio_data_size; k++) {
-                if (data[k] == enum_id) {
+                if (data[k] == mark) {
                         *enum_idp = data[k + 1];
                         return k + 1;
                 }
         }
 
-        pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
-        return -1;
+        dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
+                mark);
+        return -EINVAL;
 }
 
-int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
-                       int cfg_mode)
+int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 {
-        struct pinmux_cfg_reg *cr = NULL;
+        const struct pinmux_cfg_reg *cr = NULL;
         pinmux_enum_t enum_id;
-        struct pinmux_range *range;
+        const struct pinmux_range *range;
         int in_range, pos, field, value;
-        unsigned long *cntp;
+        int ret;
 
         switch (pinmux_type) {
 
@@ -399,7 +289,7 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
                 break;
 
         default:
-                goto out_err;
+                return -EINVAL;
         }
 
         pos = 0;
@@ -407,9 +297,9 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
         field = 0;
         value = 0;
         while (1) {
-                pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
-                if (pos <= 0)
-                        goto out_err;
+                pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
+                if (pos < 0)
+                        return pos;
 
                 if (!enum_id)
                         break;
@@ -452,44 +342,22 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
                 if (!in_range)
                         continue;
 
-                if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
-                                          &field, &value, &cntp) != 0)
-                        goto out_err;
-
-                switch (cfg_mode) {
-                case GPIO_CFG_DRYRUN:
-                        if (!*cntp ||
-                            (sh_pfc_read_config_reg(pfc, cr, field) != value))
-                                continue;
-                        break;
-
-                case GPIO_CFG_REQ:
-                        sh_pfc_write_config_reg(pfc, cr, field, value);
-                        *cntp = *cntp + 1;
-                        break;
+                ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
+                if (ret < 0)
+                        return ret;
 
-                case GPIO_CFG_FREE:
-                        *cntp = *cntp - 1;
-                        break;
-                }
+                sh_pfc_write_config_reg(pfc, cr, field, value);
         }
 
         return 0;
- out_err:
-        return -1;
 }
 
 static int sh_pfc_probe(struct platform_device *pdev)
 {
-        struct sh_pfc_soc_info *info;
+        const struct sh_pfc_soc_info *info;
         struct sh_pfc *pfc;
         int ret;
 
-        /*
-         * Ensure that the type encoding fits
-         */
-        BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
-
         info = pdev->id_entry->driver_data
               ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
         if (info == NULL)
@@ -509,7 +377,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
         spin_lock_init(&pfc->lock);
 
         pinctrl_provide_dummies();
-        sh_pfc_setup_data_regs(pfc);
 
         /*
          * Initialize pinctrl bindings first
@@ -529,13 +396,13 @@ static int sh_pfc_probe(struct platform_device *pdev)
                  * PFC state as it is, given that there are already
                  * extant users of it that have succeeded by this point.
                  */
-                pr_notice("failed to init GPIO chip, ignoring...\n");
+                dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
         }
 #endif
 
         platform_set_drvdata(pdev, pfc);
 
-        pr_info("%s support registered\n", info->name);
+        dev_info(pfc->dev, "%s support registered\n", info->name);
 
         return 0;
 }
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index ba7c33c33599..763d717ca979 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -26,13 +26,17 @@ struct sh_pfc_pinctrl;
 
 struct sh_pfc {
         struct device *dev;
-        struct sh_pfc_soc_info *info;
+        const struct sh_pfc_soc_info *info;
         spinlock_t lock;
 
         unsigned int num_windows;
         struct sh_pfc_window *window;
 
+        unsigned int nr_pins;
+
         struct sh_pfc_chip *gpio;
+        struct sh_pfc_chip *func;
+
         struct sh_pfc_pinctrl *pinctrl;
 };
 
@@ -42,31 +46,29 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
 int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
 int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
 
-int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);
-void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
-                      unsigned long value);
-int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
-                        struct pinmux_data_reg **drp, int *bitp);
-int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
-                        pinmux_enum_t *enum_idp);
-int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
-                       int cfg_mode);
+unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
+                                  unsigned long reg_width);
+void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
+                          unsigned long data);
+
+int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
+int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
 
-extern struct sh_pfc_soc_info r8a7740_pinmux_info;
-extern struct sh_pfc_soc_info r8a7779_pinmux_info;
-extern struct sh_pfc_soc_info sh7203_pinmux_info;
-extern struct sh_pfc_soc_info sh7264_pinmux_info;
-extern struct sh_pfc_soc_info sh7269_pinmux_info;
-extern struct sh_pfc_soc_info sh7372_pinmux_info;
-extern struct sh_pfc_soc_info sh73a0_pinmux_info;
-extern struct sh_pfc_soc_info sh7720_pinmux_info;
-extern struct sh_pfc_soc_info sh7722_pinmux_info;
-extern struct sh_pfc_soc_info sh7723_pinmux_info;
-extern struct sh_pfc_soc_info sh7724_pinmux_info;
-extern struct sh_pfc_soc_info sh7734_pinmux_info;
-extern struct sh_pfc_soc_info sh7757_pinmux_info;
-extern struct sh_pfc_soc_info sh7785_pinmux_info;
-extern struct sh_pfc_soc_info sh7786_pinmux_info;
-extern struct sh_pfc_soc_info shx3_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
+extern const struct sh_pfc_soc_info sh7203_pinmux_info;
+extern const struct sh_pfc_soc_info sh7264_pinmux_info;
+extern const struct sh_pfc_soc_info sh7269_pinmux_info;
+extern const struct sh_pfc_soc_info sh7372_pinmux_info;
+extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
+extern const struct sh_pfc_soc_info sh7720_pinmux_info;
+extern const struct sh_pfc_soc_info sh7722_pinmux_info;
+extern const struct sh_pfc_soc_info sh7723_pinmux_info;
+extern const struct sh_pfc_soc_info sh7724_pinmux_info;
+extern const struct sh_pfc_soc_info sh7734_pinmux_info;
+extern const struct sh_pfc_soc_info sh7757_pinmux_info;
+extern const struct sh_pfc_soc_info sh7785_pinmux_info;
+extern const struct sh_pfc_soc_info sh7786_pinmux_info;
+extern const struct sh_pfc_soc_info shx3_pinmux_info;
 
 #endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index a535075c8b69..d7acb06d888c 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -9,8 +9,6 @@
  * for more details.
  */
 
-#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt
-
 #include <linux/device.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
@@ -21,9 +19,23 @@
 
 #include "core.h"
 
+struct sh_pfc_gpio_data_reg {
+        const struct pinmux_data_reg *info;
+        unsigned long shadow;
+};
+
+struct sh_pfc_gpio_pin {
+        u8 dbit;
+        u8 dreg;
+};
+
 struct sh_pfc_chip {
-        struct sh_pfc           *pfc;
-        struct gpio_chip        gpio_chip;
+        struct sh_pfc                   *pfc;
+        struct gpio_chip                gpio_chip;
+
+        struct sh_pfc_window            *mem;
+        struct sh_pfc_gpio_data_reg     *regs;
+        struct sh_pfc_gpio_pin          *pins;
 };
 
 static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
@@ -36,143 +48,358 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
         return gpio_to_pfc_chip(gc)->pfc;
 }
 
-static int sh_gpio_request(struct gpio_chip *gc, unsigned offset)
+static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio,
+                              struct sh_pfc_gpio_data_reg **reg,
+                              unsigned int *bit)
 {
-        return pinctrl_request_gpio(offset);
+        int idx = sh_pfc_get_pin_index(chip->pfc, gpio);
+        struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
+
+        *reg = &chip->regs[gpio_pin->dreg];
+        *bit = gpio_pin->dbit;
 }
 
-static void sh_gpio_free(struct gpio_chip *gc, unsigned offset)
+static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip,
+                                        const struct pinmux_data_reg *dreg)
 {
-        pinctrl_free_gpio(offset);
+        void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
+
+        return sh_pfc_read_raw_reg(mem, dreg->reg_width);
 }
 
-static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value)
+static void gpio_write_data_reg(struct sh_pfc_chip *chip,
+                                const struct pinmux_data_reg *dreg,
+                                unsigned long value)
 {
-        struct pinmux_data_reg *dr = NULL;
-        int bit = 0;
+        void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
 
-        if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
-                BUG();
-        else
-                sh_pfc_write_bit(dr, bit, value);
+        sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
+}
+
+static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
+{
+        struct sh_pfc *pfc = chip->pfc;
+        struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio];
+        const struct sh_pfc_pin *pin = &pfc->info->pins[gpio];
+        const struct pinmux_data_reg *dreg;
+        unsigned int bit;
+        unsigned int i;
+
+        for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) {
+                for (bit = 0; bit < dreg->reg_width; bit++) {
+                        if (dreg->enum_ids[bit] == pin->enum_id) {
+                                gpio_pin->dreg = i;
+                                gpio_pin->dbit = bit;
+                                return;
+                        }
+                }
+        }
+
+        BUG();
+}
+
+static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
+{
+        struct sh_pfc *pfc = chip->pfc;
+        unsigned long addr = pfc->info->data_regs[0].reg;
+        const struct pinmux_data_reg *dreg;
+        unsigned int i;
+
+        /* Find the window that contain the GPIO registers. */
+        for (i = 0; i < pfc->num_windows; ++i) {
+                struct sh_pfc_window *window = &pfc->window[i];
+
+                if (addr >= window->phys && addr < window->phys + window->size)
+                        break;
+        }
+
+        if (i == pfc->num_windows)
+                return -EINVAL;
+
+        /* GPIO data registers must be in the first memory resource. */
+        chip->mem = &pfc->window[i];
+
+        /* Count the number of data registers, allocate memory and initialize
+         * them.
+         */
+        for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
+                ;
+
+        chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
+                                  GFP_KERNEL);
+        if (chip->regs == NULL)
+                return -ENOMEM;
+
+        for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
+                chip->regs[i].info = dreg;
+                chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
+        }
+
+        for (i = 0; i < pfc->info->nr_pins; i++) {
+                if (pfc->info->pins[i].enum_id == 0)
+                        continue;
+
+                gpio_setup_data_reg(chip, i);
+        }
+
+        return 0;
 }
 
-static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio)
+/* -----------------------------------------------------------------------------
+ * Pin GPIOs
+ */
+
+static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
 {
-        struct pinmux_data_reg *dr = NULL;
-        int bit = 0;
+        struct sh_pfc *pfc = gpio_to_pfc(gc);
+        int idx = sh_pfc_get_pin_index(pfc, offset);
 
-        if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
+        if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
                 return -EINVAL;
 
-        return sh_pfc_read_bit(dr, bit);
+        return pinctrl_request_gpio(offset);
 }
 
-static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
+{
+        return pinctrl_free_gpio(offset);
+}
+
+static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
+                               int value)
+{
+        struct sh_pfc_gpio_data_reg *reg;
+        unsigned long pos;
+        unsigned int bit;
+
+        gpio_get_data_reg(chip, offset, &reg, &bit);
+
+        pos = reg->info->reg_width - (bit + 1);
+
+        if (value)
+                set_bit(pos, &reg->shadow);
+        else
+                clear_bit(pos, &reg->shadow);
+
+        gpio_write_data_reg(chip, reg->info, reg->shadow);
+}
+
+static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
 {
         return pinctrl_gpio_direction_input(offset);
 }
 
-static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
+static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
                                     int value)
 {
-        sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
+        gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
 
         return pinctrl_gpio_direction_output(offset);
 }
 
-static int sh_gpio_get(struct gpio_chip *gc, unsigned offset)
+static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
 {
-        return sh_gpio_get_value(gpio_to_pfc(gc), offset);
+        struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
+        struct sh_pfc_gpio_data_reg *reg;
+        unsigned long pos;
+        unsigned int bit;
+
+        gpio_get_data_reg(chip, offset, &reg, &bit);
+
+        pos = reg->info->reg_width - (bit + 1);
+
+        return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
 }
 
-static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
+static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
 {
-        sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
+        gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
 }
 
-static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
 {
         struct sh_pfc *pfc = gpio_to_pfc(gc);
-        pinmux_enum_t enum_id;
-        pinmux_enum_t *enum_ids;
-        int i, k, pos;
-
-        pos = 0;
-        enum_id = 0;
-        while (1) {
-                pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id);
-                if (pos <= 0 || !enum_id)
-                        break;
+        int i, k;
 
-                for (i = 0; i < pfc->info->gpio_irq_size; i++) {
-                        enum_ids = pfc->info->gpio_irq[i].enum_ids;
-                        for (k = 0; enum_ids[k]; k++) {
-                                if (enum_ids[k] == enum_id)
-                                        return pfc->info->gpio_irq[i].irq;
-                        }
+        for (i = 0; i < pfc->info->gpio_irq_size; i++) {
+                unsigned short *gpios = pfc->info->gpio_irq[i].gpios;
+
+                for (k = 0; gpios[k]; k++) {
+                        if (gpios[k] == offset)
+                                return pfc->info->gpio_irq[i].irq;
                 }
         }
 
         return -ENOSYS;
 }
 
-static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip)
+static int gpio_pin_setup(struct sh_pfc_chip *chip)
 {
         struct sh_pfc *pfc = chip->pfc;
         struct gpio_chip *gc = &chip->gpio_chip;
+        int ret;
+
+        chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins),
+                                  GFP_KERNEL);
+        if (chip->pins == NULL)
+                return -ENOMEM;
 
-        gc->request = sh_gpio_request;
-        gc->free = sh_gpio_free;
-        gc->direction_input = sh_gpio_direction_input;
-        gc->get = sh_gpio_get;
-        gc->direction_output = sh_gpio_direction_output;
-        gc->set = sh_gpio_set;
-        gc->to_irq = sh_gpio_to_irq;
+        ret = gpio_setup_data_regs(chip);
+        if (ret < 0)
+                return ret;
 
-        WARN_ON(pfc->info->first_gpio != 0); /* needs testing */
+        gc->request = gpio_pin_request;
+        gc->free = gpio_pin_free;
+        gc->direction_input = gpio_pin_direction_input;
+        gc->get = gpio_pin_get;
+        gc->direction_output = gpio_pin_direction_output;
+        gc->set = gpio_pin_set;
+        gc->to_irq = gpio_pin_to_irq;
 
         gc->label = pfc->info->name;
+        gc->dev = pfc->dev;
         gc->owner = THIS_MODULE;
-        gc->base = pfc->info->first_gpio;
-        gc->ngpio = (pfc->info->last_gpio - pfc->info->first_gpio) + 1;
+        gc->base = 0;
+        gc->ngpio = pfc->nr_pins;
+
+        return 0;
 }
 
-int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
+/* -----------------------------------------------------------------------------
+ * Function GPIOs
+ */
+
+static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
+{
+        static bool __print_once;
+        struct sh_pfc *pfc = gpio_to_pfc(gc);
+        unsigned int mark = pfc->info->func_gpios[offset].enum_id;
+        unsigned long flags;
+        int ret;
+
+        if (!__print_once) {
+                dev_notice(pfc->dev,
+                           "Use of GPIO API for function requests is deprecated."
+                           " Convert to pinctrl\n");
+                __print_once = true;
+        }
+
+        if (mark == 0)
+                return -EINVAL;
+
+        spin_lock_irqsave(&pfc->lock, flags);
+        ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
+        spin_unlock_irqrestore(&pfc->lock, flags);
+
+        return ret;
+}
+
+static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
+{
+}
+
+static int gpio_function_setup(struct sh_pfc_chip *chip)
+{
+        struct sh_pfc *pfc = chip->pfc;
+        struct gpio_chip *gc = &chip->gpio_chip;
+
+        gc->request = gpio_function_request;
+        gc->free = gpio_function_free;
+
+        gc->label = pfc->info->name;
+        gc->owner = THIS_MODULE;
+        gc->base = pfc->nr_pins;
+        gc->ngpio = pfc->info->nr_func_gpios;
+
+        return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Register/unregister
+ */
+
+static struct sh_pfc_chip *
+sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *))
 {
         struct sh_pfc_chip *chip;
         int ret;
 
         chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
         if (unlikely(!chip))
-                return -ENOMEM;
+                return ERR_PTR(-ENOMEM);
 
         chip->pfc = pfc;
 
-        sh_pfc_gpio_setup(chip);
+        ret = setup(chip);
+        if (ret < 0)
+                return ERR_PTR(ret);
 
         ret = gpiochip_add(&chip->gpio_chip);
         if (unlikely(ret < 0))
-                return ret;
+                return ERR_PTR(ret);
+
+        dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
+                 chip->gpio_chip.label, chip->gpio_chip.base,
+                 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
+
+        return chip;
+}
+
+int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
+{
+        const struct pinmux_range *ranges;
+        struct pinmux_range def_range;
+        struct sh_pfc_chip *chip;
+        unsigned int nr_ranges;
+        unsigned int i;
+        int ret;
+
+        /* Register the real GPIOs chip. */
+        chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
+        if (IS_ERR(chip))
+                return PTR_ERR(chip);
 
         pfc->gpio = chip;
 
-        pr_info("%s handling gpio %d -> %d\n",
-                pfc->info->name, pfc->info->first_gpio,
-                pfc->info->last_gpio);
+        /* Register the GPIO to pin mappings. */
+        if (pfc->info->ranges == NULL) {
+                def_range.begin = 0;
+                def_range.end = pfc->info->nr_pins - 1;
+                ranges = &def_range;
+                nr_ranges = 1;
+        } else {
+                ranges = pfc->info->ranges;
+                nr_ranges = pfc->info->nr_ranges;
+        }
+
+        for (i = 0; i < nr_ranges; ++i) {
+                const struct pinmux_range *range = &ranges[i];
+
+                ret = gpiochip_add_pin_range(&chip->gpio_chip,
+                                             dev_name(pfc->dev),
+                                             range->begin, range->begin,
+                                             range->end - range->begin + 1);
+                if (ret < 0)
+                        return ret;
+        }
+
+        /* Register the function GPIOs chip. */
+        chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
+        if (IS_ERR(chip))
+                return PTR_ERR(chip);
+
+        pfc->func = chip;
 
         return 0;
 }
 
 int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
 {
-        struct sh_pfc_chip *chip = pfc->gpio;
+        int err;
         int ret;
 
-        ret = gpiochip_remove(&chip->gpio_chip);
-        if (unlikely(ret < 0))
-                return ret;
+        ret = gpiochip_remove(&pfc->gpio->gpio_chip);
+        err = gpiochip_remove(&pfc->func->gpio_chip);
 
-        pfc->gpio = NULL;
-        return 0;
+        return ret < 0 ? ret : err;
 }
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 214788c4a606..3621d3e81fc3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -577,7 +577,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
         /* specify valid pin states for each pin in GPIO mode */
 
         /* I/O and Pull U/D */
@@ -1654,11 +1654,532 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,                    MSEL5CR_30_1,   MSEL5CR_29_0),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
-
-        /* PORT */
+static struct sh_pfc_pin pinmux_pins[] = {
         GPIO_PORT_ALL(),
+};
+
+/* - LCD0 ------------------------------------------------------------------- */
+static const unsigned int lcd0_data8_pins[] = {
+        /* D[0:7] */
+        58, 57, 56, 55, 54, 53, 52, 51,
+};
+static const unsigned int lcd0_data8_mux[] = {
+        LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+        LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+};
+static const unsigned int lcd0_data9_pins[] = {
+        /* D[0:8] */
+        58, 57, 56, 55, 54, 53, 52, 51,
+        50,
+};
+static const unsigned int lcd0_data9_mux[] = {
+        LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+        LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+        LCD0_D8_MARK,
+};
+static const unsigned int lcd0_data12_pins[] = {
+        /* D[0:11] */
+        58, 57, 56, 55, 54, 53, 52, 51,
+        50, 49, 48, 47,
+};
+static const unsigned int lcd0_data12_mux[] = {
+        LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+        LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+        LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+};
+static const unsigned int lcd0_data16_pins[] = {
+        /* D[0:15] */
+        58, 57, 56, 55, 54, 53, 52, 51,
+        50, 49, 48, 47, 46, 45, 44, 43,
+};
+static const unsigned int lcd0_data16_mux[] = {
+        LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+        LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+        LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+        LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+};
+static const unsigned int lcd0_data18_pins[] = {
+        /* D[0:17] */
+        58, 57, 56, 55, 54, 53, 52, 51,
+        50, 49, 48, 47, 46, 45, 44, 43,
+        42, 41,
+};
+static const unsigned int lcd0_data18_mux[] = {
+        LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+        LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+        LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+        LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+        LCD0_D16_MARK, LCD0_D17_MARK,
+};
+static const unsigned int lcd0_data24_0_pins[] = {
+        /* D[0:23] */
+        58, 57, 56, 55, 54, 53, 52, 51,
+        50, 49, 48, 47, 46, 45, 44, 43,
+        42, 41, 40, 4, 3, 2, 0, 1,
+};
+static const unsigned int lcd0_data24_0_mux[] = {
+        LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+        LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+        LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+        LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+        LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
+        LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
+        LCD0_D23_PORT1_MARK,
+};
+static const unsigned int lcd0_data24_1_pins[] = {
+        /* D[0:23] */
+        58, 57, 56, 55, 54, 53, 52, 51,
+        50, 49, 48, 47, 46, 45, 44, 43,
+        42, 41, 163, 162, 161, 158, 160, 159,
+};
+static const unsigned int lcd0_data24_1_mux[] = {
+        LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+        LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+        LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+        LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
+        LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
+        LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
+};
+static const unsigned int lcd0_display_pins[] = {
+        /* DON, VCPWC, VEPWC */
+        61, 59, 60,
+};
+static const unsigned int lcd0_display_mux[] = {
+        LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
+};
+static const unsigned int lcd0_lclk_0_pins[] = {
+        /* LCLK */
+        102,
+};
+static const unsigned int lcd0_lclk_0_mux[] = {
+        LCD0_LCLK_PORT102_MARK,
+};
+static const unsigned int lcd0_lclk_1_pins[] = {
+        /* LCLK */
+        165,
+};
+static const unsigned int lcd0_lclk_1_mux[] = {
+        LCD0_LCLK_PORT165_MARK,
+};
+static const unsigned int lcd0_sync_pins[] = {
+        /* VSYN, HSYN, DCK, DISP */
+        63, 64, 62, 65,
+};
+static const unsigned int lcd0_sync_mux[] = {
+        LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
+};
+static const unsigned int lcd0_sys_pins[] = {
+        /* CS, WR, RD, RS */
+        64, 62, 164, 65,
+};
+static const unsigned int lcd0_sys_mux[] = {
+        LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
+};
+/* - LCD1 ------------------------------------------------------------------- */
+static const unsigned int lcd1_data8_pins[] = {
+        /* D[0:7] */
+        4, 3, 2, 1, 0, 91, 92, 23,
+};
+static const unsigned int lcd1_data8_mux[] = {
+        LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+        LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+};
+static const unsigned int lcd1_data9_pins[] = {
+        /* D[0:8] */
+        4, 3, 2, 1, 0, 91, 92, 23,
+        93,
+};
+static const unsigned int lcd1_data9_mux[] = {
+        LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+        LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+        LCD1_D8_MARK,
+};
+static const unsigned int lcd1_data12_pins[] = {
+        /* D[0:12] */
+        4, 3, 2, 1, 0, 91, 92, 23,
+        93, 94, 21, 201,
+};
+static const unsigned int lcd1_data12_mux[] = {
+        LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+        LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+        LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+};
+static const unsigned int lcd1_data16_pins[] = {
+        /* D[0:15] */
+        4, 3, 2, 1, 0, 91, 92, 23,
+        93, 94, 21, 201, 200, 199, 196, 195,
+};
+static const unsigned int lcd1_data16_mux[] = {
+        LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+        LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+        LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+        LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+};
+static const unsigned int lcd1_data18_pins[] = {
+        /* D[0:17] */
+        4, 3, 2, 1, 0, 91, 92, 23,
+        93, 94, 21, 201, 200, 199, 196, 195,
+        194, 193,
+};
+static const unsigned int lcd1_data18_mux[] = {
+        LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+        LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+        LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+        LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+        LCD1_D16_MARK, LCD1_D17_MARK,
+};
+static const unsigned int lcd1_data24_pins[] = {
+        /* D[0:23] */
+        4, 3, 2, 1, 0, 91, 92, 23,
+        93, 94, 21, 201, 200, 199, 196, 195,
+        194, 193, 198, 197, 75, 74, 15, 14,
+};
+static const unsigned int lcd1_data24_mux[] = {
+        LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+        LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+        LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+        LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+        LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
+        LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
+};
+static const unsigned int lcd1_display_pins[] = {
+        /* DON, VCPWC, VEPWC */
+        100, 5, 6,
+};
+static const unsigned int lcd1_display_mux[] = {
+        LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
+};
+static const unsigned int lcd1_lclk_pins[] = {
+        /* LCLK */
+        40,
+};
+static const unsigned int lcd1_lclk_mux[] = {
+        LCD1_LCLK_MARK,
+};
+static const unsigned int lcd1_sync_pins[] = {
+        /* VSYN, HSYN, DCK, DISP */
+        98, 97, 99, 12,
+};
+static const unsigned int lcd1_sync_mux[] = {
+        LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
+};
+static const unsigned int lcd1_sys_pins[] = {
+        /* CS, WR, RD, RS */
+        97, 99, 13, 12,
+};
+static const unsigned int lcd1_sys_mux[] = {
+        LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
+};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_0_pins[] = {
+        /* D[0] */
+        68,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+        MMC0_D0_PORT68_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+        /* D[0:3] */
+        68, 69, 70, 71,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+        MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+        /* D[0:7] */
+        68, 69, 70, 71, 72, 73, 74, 75,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+        MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+        MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+        /* CMD, CLK */
+        67, 66,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+        MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+        /* D[0] */
+        149,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+        MMC1_D0_PORT149_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+        /* D[0:3] */
+        149, 148, 147, 146,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+        MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+        /* D[0:7] */
+        149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+        MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+        MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+        /* CMD, CLK */
+        104, 103,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+        MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+        /* D0 */
+        77,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+        SDHI0_D0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+        /* D[0:3] */
+        77, 78, 79, 80,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+        SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+        /* CMD, CLK */
+        76, 82,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+        SDHI0_CMD_MARK, SDHI0_CLK_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+        /* CD */
+        81,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+        SDHI0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+        /* WP */
+        83,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+        SDHI0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+        /* D0 */
+        68,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+        SDHI1_D0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+        /* D[0:3] */
+        68, 69, 70, 71,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+        SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+        /* CMD, CLK */
+        67, 66,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+        SDHI1_CMD_MARK, SDHI1_CLK_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+        /* CD */
+        72,
+};
+static const unsigned int sdhi1_cd_mux[] = {
+        SDHI1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+        /* WP */
+        73,
+};
+static const unsigned int sdhi1_wp_mux[] = {
+        SDHI1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+        /* D0 */
+        205,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+        SDHI2_D0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+        /* D[0:3] */
+        205, 206, 207, 208,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+        SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+        /* CMD, CLK */
+        204, 203,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+        SDHI2_CMD_MARK, SDHI2_CLK_MARK,
+};
+static const unsigned int sdhi2_cd_0_pins[] = {
+        /* CD */
+        202,
+};
+static const unsigned int sdhi2_cd_0_mux[] = {
+        SDHI2_CD_PORT202_MARK,
+};
+static const unsigned int sdhi2_wp_0_pins[] = {
+        /* WP */
+        177,
+};
+static const unsigned int sdhi2_wp_0_mux[] = {
+        SDHI2_WP_PORT177_MARK,
+};
+static const unsigned int sdhi2_cd_1_pins[] = {
+        /* CD */
+        24,
+};
+static const unsigned int sdhi2_cd_1_mux[] = {
+        SDHI2_CD_PORT24_MARK,
+};
+static const unsigned int sdhi2_wp_1_pins[] = {
+        /* WP */
+        25,
+};
+static const unsigned int sdhi2_wp_1_mux[] = {
+        SDHI2_WP_PORT25_MARK,
+};
 
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(lcd0_data8),
+        SH_PFC_PIN_GROUP(lcd0_data9),
+        SH_PFC_PIN_GROUP(lcd0_data12),
+        SH_PFC_PIN_GROUP(lcd0_data16),
+        SH_PFC_PIN_GROUP(lcd0_data18),
+        SH_PFC_PIN_GROUP(lcd0_data24_0),
+        SH_PFC_PIN_GROUP(lcd0_data24_1),
+        SH_PFC_PIN_GROUP(lcd0_display),
+        SH_PFC_PIN_GROUP(lcd0_lclk_0),
+        SH_PFC_PIN_GROUP(lcd0_lclk_1),
+        SH_PFC_PIN_GROUP(lcd0_sync),
+        SH_PFC_PIN_GROUP(lcd0_sys),
+        SH_PFC_PIN_GROUP(lcd1_data8),
+        SH_PFC_PIN_GROUP(lcd1_data9),
+        SH_PFC_PIN_GROUP(lcd1_data12),
+        SH_PFC_PIN_GROUP(lcd1_data16),
+        SH_PFC_PIN_GROUP(lcd1_data18),
+        SH_PFC_PIN_GROUP(lcd1_data24),
+        SH_PFC_PIN_GROUP(lcd1_display),
+        SH_PFC_PIN_GROUP(lcd1_lclk),
+        SH_PFC_PIN_GROUP(lcd1_sync),
+        SH_PFC_PIN_GROUP(lcd1_sys),
+        SH_PFC_PIN_GROUP(mmc0_data1_0),
+        SH_PFC_PIN_GROUP(mmc0_data4_0),
+        SH_PFC_PIN_GROUP(mmc0_data8_0),
+        SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+        SH_PFC_PIN_GROUP(mmc0_data1_1),
+        SH_PFC_PIN_GROUP(mmc0_data4_1),
+        SH_PFC_PIN_GROUP(mmc0_data8_1),
+        SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_data1),
+        SH_PFC_PIN_GROUP(sdhi1_data4),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi1_cd),
+        SH_PFC_PIN_GROUP(sdhi1_wp),
+        SH_PFC_PIN_GROUP(sdhi2_data1),
+        SH_PFC_PIN_GROUP(sdhi2_data4),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(sdhi2_cd_0),
+        SH_PFC_PIN_GROUP(sdhi2_wp_0),
+        SH_PFC_PIN_GROUP(sdhi2_cd_1),
+        SH_PFC_PIN_GROUP(sdhi2_wp_1),
+};
+
+static const char * const lcd0_groups[] = {
+        "lcd0_data8",
+        "lcd0_data9",
+        "lcd0_data12",
+        "lcd0_data16",
+        "lcd0_data18",
+        "lcd0_data24_0",
+        "lcd0_data24_1",
+        "lcd0_display",
+        "lcd0_lclk_0",
+        "lcd0_lclk_1",
+        "lcd0_sync",
+        "lcd0_sys",
+};
+
+static const char * const lcd1_groups[] = {
+        "lcd1_data8",
+        "lcd1_data9",
+        "lcd1_data12",
+        "lcd1_data16",
+        "lcd1_data18",
+        "lcd1_data24",
+        "lcd1_display",
+        "lcd1_lclk",
+        "lcd1_sync",
+        "lcd1_sys",
+};
+
+static const char * const mmc0_groups[] = {
+        "mmc0_data1_0",
+        "mmc0_data4_0",
+        "mmc0_data8_0",
+        "mmc0_ctrl_0",
+        "mmc0_data1_1",
+        "mmc0_data4_1",
+        "mmc0_data8_1",
+        "mmc0_ctrl_1",
+};
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_ctrl",
+        "sdhi0_cd",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_data1",
+        "sdhi1_data4",
+        "sdhi1_ctrl",
+        "sdhi1_cd",
+        "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_data1",
+        "sdhi2_data4",
+        "sdhi2_ctrl",
+        "sdhi2_cd_0",
+        "sdhi2_wp_0",
+        "sdhi2_cd_1",
+        "sdhi2_wp_1",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(lcd0),
+        SH_PFC_FUNCTION(lcd1),
+        SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
+
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* IRQ */
         GPIO_FN(IRQ0_PORT2),    GPIO_FN(IRQ0_PORT13),
         GPIO_FN(IRQ1),
@@ -1792,43 +2313,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(SCIFB_RTS_PORT172),
         GPIO_FN(SCIFB_CTS_PORT173),
 
-        /* LCD0 */
-        GPIO_FN(LCD0_D0),       GPIO_FN(LCD0_D1),       GPIO_FN(LCD0_D2),
-        GPIO_FN(LCD0_D3),       GPIO_FN(LCD0_D4),       GPIO_FN(LCD0_D5),
-        GPIO_FN(LCD0_D6),       GPIO_FN(LCD0_D7),       GPIO_FN(LCD0_D8),
-        GPIO_FN(LCD0_D9),       GPIO_FN(LCD0_D10),      GPIO_FN(LCD0_D11),
-        GPIO_FN(LCD0_D12),      GPIO_FN(LCD0_D13),      GPIO_FN(LCD0_D14),
-        GPIO_FN(LCD0_D15),      GPIO_FN(LCD0_D16),      GPIO_FN(LCD0_D17),
-        GPIO_FN(LCD0_DON),      GPIO_FN(LCD0_VCPWC),    GPIO_FN(LCD0_VEPWC),
-        GPIO_FN(LCD0_DCK),      GPIO_FN(LCD0_VSYN),
-        GPIO_FN(LCD0_HSYN),     GPIO_FN(LCD0_DISP),
-        GPIO_FN(LCD0_WR),       GPIO_FN(LCD0_RD),
-        GPIO_FN(LCD0_CS),       GPIO_FN(LCD0_RS),
-
-        GPIO_FN(LCD0_D18_PORT163),      GPIO_FN(LCD0_D19_PORT162),
-        GPIO_FN(LCD0_D20_PORT161),      GPIO_FN(LCD0_D21_PORT158),
-        GPIO_FN(LCD0_D22_PORT160),      GPIO_FN(LCD0_D23_PORT159),
-        GPIO_FN(LCD0_LCLK_PORT165),     /* MSEL5CR_6_1 */
-
-        GPIO_FN(LCD0_D18_PORT40),       GPIO_FN(LCD0_D19_PORT4),
-        GPIO_FN(LCD0_D20_PORT3),        GPIO_FN(LCD0_D21_PORT2),
-        GPIO_FN(LCD0_D22_PORT0),        GPIO_FN(LCD0_D23_PORT1),
-        GPIO_FN(LCD0_LCLK_PORT102),     /* MSEL5CR_6_0 */
-
-        /* LCD1 */
-        GPIO_FN(LCD1_D0),       GPIO_FN(LCD1_D1),       GPIO_FN(LCD1_D2),
-        GPIO_FN(LCD1_D3),       GPIO_FN(LCD1_D4),       GPIO_FN(LCD1_D5),
-        GPIO_FN(LCD1_D6),       GPIO_FN(LCD1_D7),       GPIO_FN(LCD1_D8),
-        GPIO_FN(LCD1_D9),       GPIO_FN(LCD1_D10),      GPIO_FN(LCD1_D11),
-        GPIO_FN(LCD1_D12),      GPIO_FN(LCD1_D13),      GPIO_FN(LCD1_D14),
-        GPIO_FN(LCD1_D15),      GPIO_FN(LCD1_D16),      GPIO_FN(LCD1_D17),
-        GPIO_FN(LCD1_D18),      GPIO_FN(LCD1_D19),      GPIO_FN(LCD1_D20),
-        GPIO_FN(LCD1_D21),      GPIO_FN(LCD1_D22),      GPIO_FN(LCD1_D23),
-        GPIO_FN(LCD1_RS),       GPIO_FN(LCD1_RD),       GPIO_FN(LCD1_CS),
-        GPIO_FN(LCD1_WR),       GPIO_FN(LCD1_DCK),      GPIO_FN(LCD1_DON),
-        GPIO_FN(LCD1_VCPWC),    GPIO_FN(LCD1_LCLK),     GPIO_FN(LCD1_HSYN),
-        GPIO_FN(LCD1_VSYN),     GPIO_FN(LCD1_VEPWC),    GPIO_FN(LCD1_DISP),
-
         /* RSPI */
         GPIO_FN(RSPI_SSL0_A),   GPIO_FN(RSPI_SSL1_A),   GPIO_FN(RSPI_SSL2_A),
         GPIO_FN(RSPI_SSL3_A),   GPIO_FN(RSPI_CK_A),     GPIO_FN(RSPI_MOSI_A),
@@ -1889,26 +2373,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(SIM_D_PORT22), /* SIM_D  Port 22/199 */
         GPIO_FN(SIM_D_PORT199),
 
-        /* SDHI0 */
-        GPIO_FN(SDHI0_D0),      GPIO_FN(SDHI0_D1),      GPIO_FN(SDHI0_D2),
-        GPIO_FN(SDHI0_D3),      GPIO_FN(SDHI0_CD),      GPIO_FN(SDHI0_WP),
-        GPIO_FN(SDHI0_CMD),     GPIO_FN(SDHI0_CLK),
-
-        /* SDHI1 */
-        GPIO_FN(SDHI1_D0),      GPIO_FN(SDHI1_D1),      GPIO_FN(SDHI1_D2),
-        GPIO_FN(SDHI1_D3),      GPIO_FN(SDHI1_CD),      GPIO_FN(SDHI1_WP),
-        GPIO_FN(SDHI1_CMD),     GPIO_FN(SDHI1_CLK),
-
-        /* SDHI2 */
-        GPIO_FN(SDHI2_D0),      GPIO_FN(SDHI2_D1),      GPIO_FN(SDHI2_D2),
-        GPIO_FN(SDHI2_D3),      GPIO_FN(SDHI2_CLK),     GPIO_FN(SDHI2_CMD),
-
-        GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
-        GPIO_FN(SDHI2_WP_PORT25),
-
-        GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
-        GPIO_FN(SDHI2_CD_PORT202),
-
         /* MSIOF2 */
         GPIO_FN(MSIOF2_TXD),    GPIO_FN(MSIOF2_RXD),    GPIO_FN(MSIOF2_TSCK),
         GPIO_FN(MSIOF2_SS2),    GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_SS1),
@@ -1953,21 +2417,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(MEMC_WAIT),     GPIO_FN(MEMC_DREQ1),    GPIO_FN(MEMC_BUSCLK),
         GPIO_FN(MEMC_A0),
 
-        /* MMC */
-        GPIO_FN(MMC0_D0_PORT68),        GPIO_FN(MMC0_D1_PORT69),
-        GPIO_FN(MMC0_D2_PORT70),        GPIO_FN(MMC0_D3_PORT71),
-        GPIO_FN(MMC0_D4_PORT72),        GPIO_FN(MMC0_D5_PORT73),
-        GPIO_FN(MMC0_D6_PORT74),        GPIO_FN(MMC0_D7_PORT75),
-        GPIO_FN(MMC0_CLK_PORT66),
-        GPIO_FN(MMC0_CMD_PORT67),       /* MSEL4CR_15_0 */
-
-        GPIO_FN(MMC1_D0_PORT149),       GPIO_FN(MMC1_D1_PORT148),
-        GPIO_FN(MMC1_D2_PORT147),       GPIO_FN(MMC1_D3_PORT146),
-        GPIO_FN(MMC1_D4_PORT145),       GPIO_FN(MMC1_D5_PORT144),
-        GPIO_FN(MMC1_D6_PORT143),       GPIO_FN(MMC1_D7_PORT142),
-        GPIO_FN(MMC1_CLK_PORT103),
-        GPIO_FN(MMC1_CMD_PORT104),      /* MSEL4CR_15_1 */
-
         /* MSIOF0 */
         GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),    GPIO_FN(MSIOF0_RXD),
         GPIO_FN(MSIOF0_TXD),    GPIO_FN(MSIOF0_MCK0),   GPIO_FN(MSIOF0_MCK1),
@@ -2126,7 +2575,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(TRACEAUD_FROM_MEMC),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0,       0xe6050000), /* PORT0CR */
         PORTCR(1,       0xe6050001), /* PORT1CR */
         PORTCR(2,       0xe6050002), /* PORT2CR */
@@ -2440,7 +2889,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         { },
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
                 PORT31_DATA,    PORT30_DATA,    PORT29_DATA,    PORT28_DATA,
                 PORT27_DATA,    PORT26_DATA,    PORT25_DATA,    PORT24_DATA,
@@ -2544,46 +2993,43 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-static struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0,   PORT13_FN0),   /* IRQ0A */
-        PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0),                /* IRQ1A */
-        PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0,  PORT12_FN0),   /* IRQ2A */
-        PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0,  PORT14_FN0),   /* IRQ3A */
-        PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0,  PORT172_FN0),  /* IRQ4A */
-        PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0,   PORT1_FN0),    /* IRQ5A */
-        PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0),  /* IRQ6A */
-        PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0),  /* IRQ7A */
-        PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0),               /* IRQ8A */
-        PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0),  /* IRQ9A */
-        PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0),                /* IRQ10A */
-        PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0),               /* IRQ11A */
-        PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0,  PORT97_FN0),   /* IRQ12A */
-        PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0,  PORT98_FN0),   /* IRQ13A */
-        PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0,  PORT99_FN0),   /* IRQ14A */
-        PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0,  PORT100_FN0),  /* IRQ15A */
-        PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0,  PORT211_FN0),  /* IRQ16A */
-        PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0),                /* IRQ17A */
-        PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0),                /* IRQ18A */
-        PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0),                /* IRQ19A */
-        PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0),                /* IRQ20A */
-        PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0),               /* IRQ21A */
-        PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0),                /* IRQ22A */
-        PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0),                /* IRQ23A */
-        PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0),               /* IRQ24A */
-        PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0),                /* IRQ25A */
-        PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0,  PORT81_FN0),   /* IRQ26A */
-        PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0,  PORT168_FN0),  /* IRQ27A */
-        PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0,  PORT169_FN0),  /* IRQ28A */
-        PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0,  PORT170_FN0),  /* IRQ29A */
-        PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0,  PORT171_FN0),  /* IRQ30A */
-        PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0,  PORT167_FN0),  /* IRQ31A */
-};
-
-struct sh_pfc_soc_info r8a7740_pinmux_info = {
+static const struct pinmux_irq pinmux_irqs[] = {
+        PINMUX_IRQ(evt2irq(0x0200), GPIO_PORT2,   GPIO_PORT13), /* IRQ0A */
+        PINMUX_IRQ(evt2irq(0x0220), GPIO_PORT20),               /* IRQ1A */
+        PINMUX_IRQ(evt2irq(0x0240), GPIO_PORT11,  GPIO_PORT12), /* IRQ2A */
+        PINMUX_IRQ(evt2irq(0x0260), GPIO_PORT10,  GPIO_PORT14), /* IRQ3A */
+        PINMUX_IRQ(evt2irq(0x0280), GPIO_PORT15,  GPIO_PORT172),/* IRQ4A */
+        PINMUX_IRQ(evt2irq(0x02A0), GPIO_PORT0,   GPIO_PORT1),  /* IRQ5A */
+        PINMUX_IRQ(evt2irq(0x02C0), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
+        PINMUX_IRQ(evt2irq(0x02E0), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
+        PINMUX_IRQ(evt2irq(0x0300), GPIO_PORT119),              /* IRQ8A */
+        PINMUX_IRQ(evt2irq(0x0320), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
+        PINMUX_IRQ(evt2irq(0x0340), GPIO_PORT19),               /* IRQ10A */
+        PINMUX_IRQ(evt2irq(0x0360), GPIO_PORT104),              /* IRQ11A */
+        PINMUX_IRQ(evt2irq(0x0380), GPIO_PORT42,  GPIO_PORT97), /* IRQ12A */
+        PINMUX_IRQ(evt2irq(0x03A0), GPIO_PORT64,  GPIO_PORT98), /* IRQ13A */
+        PINMUX_IRQ(evt2irq(0x03C0), GPIO_PORT63,  GPIO_PORT99), /* IRQ14A */
+        PINMUX_IRQ(evt2irq(0x03E0), GPIO_PORT62,  GPIO_PORT100),/* IRQ15A */
+        PINMUX_IRQ(evt2irq(0x3200), GPIO_PORT68,  GPIO_PORT211),/* IRQ16A */
+        PINMUX_IRQ(evt2irq(0x3220), GPIO_PORT69),               /* IRQ17A */
+        PINMUX_IRQ(evt2irq(0x3240), GPIO_PORT70),               /* IRQ18A */
+        PINMUX_IRQ(evt2irq(0x3260), GPIO_PORT71),               /* IRQ19A */
+        PINMUX_IRQ(evt2irq(0x3280), GPIO_PORT67),               /* IRQ20A */
+        PINMUX_IRQ(evt2irq(0x32A0), GPIO_PORT202),              /* IRQ21A */
+        PINMUX_IRQ(evt2irq(0x32C0), GPIO_PORT95),               /* IRQ22A */
+        PINMUX_IRQ(evt2irq(0x32E0), GPIO_PORT96),               /* IRQ23A */
+        PINMUX_IRQ(evt2irq(0x3300), GPIO_PORT180),              /* IRQ24A */
+        PINMUX_IRQ(evt2irq(0x3320), GPIO_PORT38),               /* IRQ25A */
+        PINMUX_IRQ(evt2irq(0x3340), GPIO_PORT58,  GPIO_PORT81), /* IRQ26A */
+        PINMUX_IRQ(evt2irq(0x3360), GPIO_PORT57,  GPIO_PORT168),/* IRQ27A */
+        PINMUX_IRQ(evt2irq(0x3380), GPIO_PORT56,  GPIO_PORT169),/* IRQ28A */
+        PINMUX_IRQ(evt2irq(0x33A0), GPIO_PORT50,  GPIO_PORT170),/* IRQ29A */
+        PINMUX_IRQ(evt2irq(0x33C0), GPIO_PORT49,  GPIO_PORT171),/* IRQ30A */
+        PINMUX_IRQ(evt2irq(0x33E0), GPIO_PORT41,  GPIO_PORT167),/* IRQ31A */
+};
+
+const struct sh_pfc_soc_info r8a7740_pinmux_info = {
         .name           = "r8a7740_pfc",
-        .reserved_id    = PINMUX_RESERVED,
-        .data           = { PINMUX_DATA_BEGIN,
-                            PINMUX_DATA_END },
         .input          = { PINMUX_INPUT_BEGIN,
                             PINMUX_INPUT_END },
         .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
@@ -2592,15 +3038,19 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = {
                             PINMUX_INPUT_PULLDOWN_END },
         .output         = { PINMUX_OUTPUT_BEGIN,
                             PINMUX_OUTPUT_END },
-        .mark           = { PINMUX_MARK_BEGIN,
-                            PINMUX_MARK_END },
         .function       = { PINMUX_FUNCTION_BEGIN,
                             PINMUX_FUNCTION_END },
 
-        .first_gpio     = GPIO_PORT0,
-        .last_gpio      = GPIO_FN_TRACEAUD_FROM_MEMC,
+        .pins           = pinmux_pins,
+        .nr_pins        = ARRAY_SIZE(pinmux_pins),
+        .groups         = pinmux_groups,
+        .nr_groups      = ARRAY_SIZE(pinmux_groups),
+        .functions      = pinmux_functions,
+        .nr_functions   = ARRAY_SIZE(pinmux_functions),
+
+        .func_gpios     = pinmux_func_gpios,
+        .nr_func_gpios  = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios          = pinmux_gpios,
         .cfg_regs       = pinmux_config_regs,
         .data_regs      = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 13feaa0c0eb7..1d7b0dfbbb21 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -23,11 +23,6 @@
 
 #include "sh_pfc.h"
 
-#define CPU_32_PORT(fn, pfx, sfx)                               \
-        PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),        \
-        PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),     \
-        PORT_1(fn, pfx##31, sfx)
-
 #define CPU_32_PORT6(fn, pfx, sfx)                              \
         PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),       \
         PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),       \
@@ -36,12 +31,12 @@
         PORT_1(fn, pfx##8, sfx)
 
 #define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        CPU_32_PORT(fn, pfx##_0_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_1_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_2_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_3_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_4_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_5_, sfx),                         \
+        PORT_32(fn, pfx##_0_, sfx),                             \
+        PORT_32(fn, pfx##_1_, sfx),                             \
+        PORT_32(fn, pfx##_2_, sfx),                             \
+        PORT_32(fn, pfx##_3_, sfx),                             \
+        PORT_32(fn, pfx##_4_, sfx),                             \
+        PORT_32(fn, pfx##_5_, sfx),                             \
         CPU_32_PORT6(fn, pfx##_6_, sfx)
 
 #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
@@ -55,21 +50,8 @@
 #define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, , unused)
 #define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, , unused)
 
-
-#define PORT_10_REV(fn, pfx, sfx)                               \
-        PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),       \
-        PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),       \
-        PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),       \
-        PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),       \
-        PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx)                                   \
-        PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),             \
-        PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),     \
-        PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
 
 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
@@ -371,7 +353,7 @@ enum {
         FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
         FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
         FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
-        FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
+        FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
         FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
         FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
 
@@ -447,7 +429,8 @@ enum {
         A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
         BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
         ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
-        USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
+        USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
+        SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
         SCIF_CLK_MARK, TCLK0_C_MARK,
 
         EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -632,7 +615,7 @@ enum {
         HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
         MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
         SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
-        VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK,
+        VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
         DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
         VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
         DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
@@ -649,7 +632,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 
         PINMUX_DATA(AVS1_MARK, FN_AVS1),
@@ -658,6 +641,9 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(A18_MARK, FN_A18),
         PINMUX_DATA(A19_MARK, FN_A19),
 
+        PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
+        PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
+
         PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
         PINMUX_IPSR_DATA(IP0_2_0, PWM1),
@@ -1399,7 +1385,6 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
         PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
         PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
-        PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
         PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
         PINMUX_IPSR_DATA(IP11_26_24, TX2),
@@ -1450,140 +1435,1372 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
         PINMUX_GPIO_GP_ALL(),
+};
+
+/* - DU0 -------------------------------------------------------------------- */
+static const unsigned int du0_rgb666_pins[] = {
+        /* R[7:2], G[7:2], B[7:2] */
+        188, 187, 186, 185, 184, 183,
+        194, 193, 192, 191, 190, 189,
+        200, 199, 198, 197, 196, 195,
+};
+static const unsigned int du0_rgb666_mux[] = {
+        DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
+        DU0_DR3_MARK, DU0_DR2_MARK,
+        DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
+        DU0_DG3_MARK, DU0_DG2_MARK,
+        DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
+        DU0_DB3_MARK, DU0_DB2_MARK,
+};
+static const unsigned int du0_rgb888_pins[] = {
+        /* R[7:0], G[7:0], B[7:0] */
+        188, 187, 186, 185, 184, 183, 24, 23,
+        194, 193, 192, 191, 190, 189, 26, 25,
+        200, 199, 198, 197, 196, 195, 28, 27,
+};
+static const unsigned int du0_rgb888_mux[] = {
+        DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
+        DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
+        DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
+        DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
+        DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
+        DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
+};
+static const unsigned int du0_clk_0_pins[] = {
+        /* CLKIN, CLKOUT */
+        29, 180,
+};
+static const unsigned int du0_clk_0_mux[] = {
+        DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT0_MARK,
+};
+static const unsigned int du0_clk_1_pins[] = {
+        /* CLKIN, CLKOUT */
+        29, 30,
+};
+static const unsigned int du0_clk_1_mux[] = {
+        DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT1_MARK,
+};
+static const unsigned int du0_sync_0_pins[] = {
+        /* VSYNC, HSYNC, DISP */
+        182, 181, 31,
+};
+static const unsigned int du0_sync_0_mux[] = {
+        DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
+        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du0_sync_1_pins[] = {
+        /* VSYNC, HSYNC, DISP */
+        182, 181, 32,
+};
+static const unsigned int du0_sync_1_mux[] = {
+        DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
+        DU0_DISP_MARK
+};
+static const unsigned int du0_oddf_pins[] = {
+        /* ODDF */
+        31,
+};
+static const unsigned int du0_oddf_mux[] = {
+        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du0_cde_pins[] = {
+        /* CDE */
+        33,
+};
+static const unsigned int du0_cde_mux[] = {
+        DU0_CDE_MARK
+};
+/* - DU1 -------------------------------------------------------------------- */
+static const unsigned int du1_rgb666_pins[] = {
+        /* R[7:2], G[7:2], B[7:2] */
+        41, 40, 39, 38, 37, 36,
+        49, 48, 47, 46, 45, 44,
+        57, 56, 55, 54, 53, 52,
+};
+static const unsigned int du1_rgb666_mux[] = {
+        DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+        DU1_DR3_MARK, DU1_DR2_MARK,
+        DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+        DU1_DG3_MARK, DU1_DG2_MARK,
+        DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+        DU1_DB3_MARK, DU1_DB2_MARK,
+};
+static const unsigned int du1_rgb888_pins[] = {
+        /* R[7:0], G[7:0], B[7:0] */
+        41, 40, 39, 38, 37, 36, 35, 34,
+        49, 48, 47, 46, 45, 44, 43, 32,
+        57, 56, 55, 54, 53, 52, 51, 50,
+};
+static const unsigned int du1_rgb888_mux[] = {
+        DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+        DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
+        DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+        DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
+        DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+        DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
+};
+static const unsigned int du1_clk_pins[] = {
+        /* CLKIN, CLKOUT */
+        58, 59,
+};
+static const unsigned int du1_clk_mux[] = {
+        DU1_DOTCLKIN_MARK, DU1_DOTCLKOUT_MARK,
+};
+static const unsigned int du1_sync_0_pins[] = {
+        /* VSYNC, HSYNC, DISP */
+        61, 60, 62,
+};
+static const unsigned int du1_sync_0_mux[] = {
+        DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+        DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du1_sync_1_pins[] = {
+        /* VSYNC, HSYNC, DISP */
+        61, 60, 63,
+};
+static const unsigned int du1_sync_1_mux[] = {
+        DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+        DU1_DISP_MARK
+};
+static const unsigned int du1_oddf_pins[] = {
+        /* ODDF */
+        62,
+};
+static const unsigned int du1_oddf_mux[] = {
+        DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du1_cde_pins[] = {
+        /* CDE */
+        64,
+};
+static const unsigned int du1_cde_mux[] = {
+        DU1_CDE_MARK
+};
+/* - HSPI0 ------------------------------------------------------------------ */
+static const unsigned int hspi0_pins[] = {
+        /* CLK, CS, RX, TX */
+        150, 151, 153, 152,
+};
+static const unsigned int hspi0_mux[] = {
+        HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
+};
+/* - HSPI1 ------------------------------------------------------------------ */
+static const unsigned int hspi1_pins[] = {
+        /* CLK, CS, RX, TX */
+        63, 58, 64, 62,
+};
+static const unsigned int hspi1_mux[] = {
+        HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
+};
+static const unsigned int hspi1_b_pins[] = {
+        /* CLK, CS, RX, TX */
+        90, 91, 93, 92,
+};
+static const unsigned int hspi1_b_mux[] = {
+        HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
+};
+static const unsigned int hspi1_c_pins[] = {
+        /* CLK, CS, RX, TX */
+        141, 142, 144, 143,
+};
+static const unsigned int hspi1_c_mux[] = {
+        HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
+};
+static const unsigned int hspi1_d_pins[] = {
+        /* CLK, CS, RX, TX */
+        101, 102, 104, 103,
+};
+static const unsigned int hspi1_d_mux[] = {
+        HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
+};
+/* - HSPI2 ------------------------------------------------------------------ */
+static const unsigned int hspi2_pins[] = {
+        /* CLK, CS, RX, TX */
+        9, 10, 11, 14,
+};
+static const unsigned int hspi2_mux[] = {
+        HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
+};
+static const unsigned int hspi2_b_pins[] = {
+        /* CLK, CS, RX, TX */
+        7, 13, 8, 6,
+};
+static const unsigned int hspi2_b_mux[] = {
+        HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+        /* IRQ */
+        78,
+};
+static const unsigned int intc_irq0_mux[] = {
+        IRQ0_MARK,
+};
+static const unsigned int intc_irq0_b_pins[] = {
+        /* IRQ */
+        141,
+};
+static const unsigned int intc_irq0_b_mux[] = {
+        IRQ0_B_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+        /* IRQ */
+        79,
+};
+static const unsigned int intc_irq1_mux[] = {
+        IRQ1_MARK,
+};
+static const unsigned int intc_irq1_b_pins[] = {
+        /* IRQ */
+        142,
+};
+static const unsigned int intc_irq1_b_mux[] = {
+        IRQ1_B_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+        /* IRQ */
+        88,
+};
+static const unsigned int intc_irq2_mux[] = {
+        IRQ2_MARK,
+};
+static const unsigned int intc_irq2_b_pins[] = {
+        /* IRQ */
+        143,
+};
+static const unsigned int intc_irq2_b_mux[] = {
+        IRQ2_B_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+        /* IRQ */
+        89,
+};
+static const unsigned int intc_irq3_mux[] = {
+        IRQ3_MARK,
+};
+static const unsigned int intc_irq3_b_pins[] = {
+        /* IRQ */
+        144,
+};
+static const unsigned int intc_irq3_b_mux[] = {
+        IRQ3_B_MARK,
+};
+/* - LSBC ------------------------------------------------------------------- */
+static const unsigned int lbsc_cs0_pins[] = {
+        /* CS */
+        13,
+};
+static const unsigned int lbsc_cs0_mux[] = {
+        CS0_MARK,
+};
+static const unsigned int lbsc_cs1_pins[] = {
+        /* CS */
+        14,
+};
+static const unsigned int lbsc_cs1_mux[] = {
+        CS1_A26_MARK,
+};
+static const unsigned int lbsc_ex_cs0_pins[] = {
+        /* CS */
+        15,
+};
+static const unsigned int lbsc_ex_cs0_mux[] = {
+        EX_CS0_MARK,
+};
+static const unsigned int lbsc_ex_cs1_pins[] = {
+        /* CS */
+        16,
+};
+static const unsigned int lbsc_ex_cs1_mux[] = {
+        EX_CS1_MARK,
+};
+static const unsigned int lbsc_ex_cs2_pins[] = {
+        /* CS */
+        17,
+};
+static const unsigned int lbsc_ex_cs2_mux[] = {
+        EX_CS2_MARK,
+};
+static const unsigned int lbsc_ex_cs3_pins[] = {
+        /* CS */
+        18,
+};
+static const unsigned int lbsc_ex_cs3_mux[] = {
+        EX_CS3_MARK,
+};
+static const unsigned int lbsc_ex_cs4_pins[] = {
+        /* CS */
+        19,
+};
+static const unsigned int lbsc_ex_cs4_mux[] = {
+        EX_CS4_MARK,
+};
+static const unsigned int lbsc_ex_cs5_pins[] = {
+        /* CS */
+        20,
+};
+static const unsigned int lbsc_ex_cs5_mux[] = {
+        EX_CS5_MARK,
+};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_pins[] = {
+        /* D[0] */
+        19,
+};
+static const unsigned int mmc0_data1_mux[] = {
+        MMC0_D0_MARK,
+};
+static const unsigned int mmc0_data4_pins[] = {
+        /* D[0:3] */
+        19, 20, 21, 2,
+};
+static const unsigned int mmc0_data4_mux[] = {
+        MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+};
+static const unsigned int mmc0_data8_pins[] = {
+        /* D[0:7] */
+        19, 20, 21, 2, 10, 11, 15, 16,
+};
+static const unsigned int mmc0_data8_mux[] = {
+        MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+        MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
+};
+static const unsigned int mmc0_ctrl_pins[] = {
+        /* CMD, CLK */
+        18, 17,
+};
+static const unsigned int mmc0_ctrl_mux[] = {
+        MMC0_CMD_MARK, MMC0_CLK_MARK,
+};
+static const unsigned int mmc1_data1_pins[] = {
+        /* D[0] */
+        72,
+};
+static const unsigned int mmc1_data1_mux[] = {
+        MMC1_D0_MARK,
+};
+static const unsigned int mmc1_data4_pins[] = {
+        /* D[0:3] */
+        72, 73, 74, 75,
+};
+static const unsigned int mmc1_data4_mux[] = {
+        MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+};
+static const unsigned int mmc1_data8_pins[] = {
+        /* D[0:7] */
+        72, 73, 74, 75, 76, 77, 80, 81,
+};
+static const unsigned int mmc1_data8_mux[] = {
+        MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+        MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
+};
+static const unsigned int mmc1_ctrl_pins[] = {
+        /* CMD, CLK */
+        68, 65,
+};
+static const unsigned int mmc1_ctrl_mux[] = {
+        MMC1_CMD_MARK, MMC1_CLK_MARK,
+};
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+        /* RXD, TXD */
+        153, 152,
+};
+static const unsigned int scif0_data_mux[] = {
+        RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+        /* SCK */
+        156,
+};
+static const unsigned int scif0_clk_mux[] = {
+        SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+        /* RTS, CTS */
+        151, 150,
+};
+static const unsigned int scif0_ctrl_mux[] = {
+        RTS0_TANS_MARK, CTS0_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+        /* RXD, TXD */
+        20, 19,
+};
+static const unsigned int scif0_data_b_mux[] = {
+        RX0_B_MARK, TX0_B_MARK,
+};
+static const unsigned int scif0_clk_b_pins[] = {
+        /* SCK */
+        33,
+};
+static const unsigned int scif0_clk_b_mux[] = {
+        SCK0_B_MARK,
+};
+static const unsigned int scif0_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        18, 11,
+};
+static const unsigned int scif0_ctrl_b_mux[] = {
+        RTS0_B_TANS_B_MARK, CTS0_B_MARK,
+};
+static const unsigned int scif0_data_c_pins[] = {
+        /* RXD, TXD */
+        146, 147,
+};
+static const unsigned int scif0_data_c_mux[] = {
+        RX0_C_MARK, TX0_C_MARK,
+};
+static const unsigned int scif0_clk_c_pins[] = {
+        /* SCK */
+        145,
+};
+static const unsigned int scif0_clk_c_mux[] = {
+        SCK0_C_MARK,
+};
+static const unsigned int scif0_ctrl_c_pins[] = {
+        /* RTS, CTS */
+        149, 148,
+};
+static const unsigned int scif0_ctrl_c_mux[] = {
+        RTS0_C_TANS_C_MARK, CTS0_C_MARK,
+};
+static const unsigned int scif0_data_d_pins[] = {
+        /* RXD, TXD */
+        43, 42,
+};
+static const unsigned int scif0_data_d_mux[] = {
+        RX0_D_MARK, TX0_D_MARK,
+};
+static const unsigned int scif0_clk_d_pins[] = {
+        /* SCK */
+        50,
+};
+static const unsigned int scif0_clk_d_mux[] = {
+        SCK0_D_MARK,
+};
+static const unsigned int scif0_ctrl_d_pins[] = {
+        /* RTS, CTS */
+        51, 35,
+};
+static const unsigned int scif0_ctrl_d_mux[] = {
+        RTS0_D_TANS_D_MARK, CTS0_D_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+        /* RXD, TXD */
+        149, 148,
+};
+static const unsigned int scif1_data_mux[] = {
+        RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+        /* SCK */
+        145,
+};
+static const unsigned int scif1_clk_mux[] = {
+        SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+        /* RTS, CTS */
+        147, 146,
+};
+static const unsigned int scif1_ctrl_mux[] = {
+        RTS1_TANS_MARK, CTS1_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+        /* RXD, TXD */
+        117, 114,
+};
+static const unsigned int scif1_data_b_mux[] = {
+        RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_clk_b_pins[] = {
+        /* SCK */
+        113,
+};
+static const unsigned int scif1_clk_b_mux[] = {
+        SCK1_B_MARK,
+};
+static const unsigned int scif1_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        115, 116,
+};
+static const unsigned int scif1_ctrl_b_mux[] = {
+        RTS1_B_TANS_B_MARK, CTS1_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+        /* RXD, TXD */
+        67, 66,
+};
+static const unsigned int scif1_data_c_mux[] = {
+        RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_clk_c_pins[] = {
+        /* SCK */
+        86,
+};
+static const unsigned int scif1_clk_c_mux[] = {
+        SCK1_C_MARK,
+};
+static const unsigned int scif1_ctrl_c_pins[] = {
+        /* RTS, CTS */
+        69, 68,
+};
+static const unsigned int scif1_ctrl_c_mux[] = {
+        RTS1_C_TANS_C_MARK, CTS1_C_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+        /* RXD, TXD */
+        106, 105,
+};
+static const unsigned int scif2_data_mux[] = {
+        RX2_MARK, TX2_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+        /* SCK */
+        107,
+};
+static const unsigned int scif2_clk_mux[] = {
+        SCK2_MARK,
+};
+static const unsigned int scif2_data_b_pins[] = {
+        /* RXD, TXD */
+        120, 119,
+};
+static const unsigned int scif2_data_b_mux[] = {
+        RX2_B_MARK, TX2_B_MARK,
+};
+static const unsigned int scif2_clk_b_pins[] = {
+        /* SCK */
+        118,
+};
+static const unsigned int scif2_clk_b_mux[] = {
+        SCK2_B_MARK,
+};
+static const unsigned int scif2_data_c_pins[] = {
+        /* RXD, TXD */
+        33, 31,
+};
+static const unsigned int scif2_data_c_mux[] = {
+        RX2_C_MARK, TX2_C_MARK,
+};
+static const unsigned int scif2_clk_c_pins[] = {
+        /* SCK */
+        32,
+};
+static const unsigned int scif2_clk_c_mux[] = {
+        SCK2_C_MARK,
+};
+static const unsigned int scif2_data_d_pins[] = {
+        /* RXD, TXD */
+        64, 62,
+};
+static const unsigned int scif2_data_d_mux[] = {
+        RX2_D_MARK, TX2_D_MARK,
+};
+static const unsigned int scif2_clk_d_pins[] = {
+        /* SCK */
+        63,
+};
+static const unsigned int scif2_clk_d_mux[] = {
+        SCK2_D_MARK,
+};
+static const unsigned int scif2_data_e_pins[] = {
+        /* RXD, TXD */
+        20, 19,
+};
+static const unsigned int scif2_data_e_mux[] = {
+        RX2_E_MARK, TX2_E_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+        /* RXD, TXD */
+        137, 136,
+};
+static const unsigned int scif3_data_mux[] = {
+        RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+        /* SCK */
+        135,
+};
+static const unsigned int scif3_clk_mux[] = {
+        SCK3_MARK,
+};
+
+static const unsigned int scif3_data_b_pins[] = {
+        /* RXD, TXD */
+        64, 62,
+};
+static const unsigned int scif3_data_b_mux[] = {
+        RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
+};
+static const unsigned int scif3_data_c_pins[] = {
+        /* RXD, TXD */
+        15, 12,
+};
+static const unsigned int scif3_data_c_mux[] = {
+        RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
+};
+static const unsigned int scif3_data_d_pins[] = {
+        /* RXD, TXD */
+        30, 29,
+};
+static const unsigned int scif3_data_d_mux[] = {
+        RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
+};
+static const unsigned int scif3_data_e_pins[] = {
+        /* RXD, TXD */
+        35, 34,
+};
+static const unsigned int scif3_data_e_mux[] = {
+        RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
+};
+static const unsigned int scif3_clk_e_pins[] = {
+        /* SCK */
+        42,
+};
+static const unsigned int scif3_clk_e_mux[] = {
+        SCK3_E_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+        /* RXD, TXD */
+        123, 122,
+};
+static const unsigned int scif4_data_mux[] = {
+        RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+        /* SCK */
+        121,
+};
+static const unsigned int scif4_clk_mux[] = {
+        SCK4_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+        /* RXD, TXD */
+        111, 110,
+};
+static const unsigned int scif4_data_b_mux[] = {
+        RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_clk_b_pins[] = {
+        /* SCK */
+        112,
+};
+static const unsigned int scif4_clk_b_mux[] = {
+        SCK4_B_MARK,
+};
+static const unsigned int scif4_data_c_pins[] = {
+        /* RXD, TXD */
+        22, 21,
+};
+static const unsigned int scif4_data_c_mux[] = {
+        RX4_C_MARK, TX4_C_MARK,
+};
+static const unsigned int scif4_data_d_pins[] = {
+        /* RXD, TXD */
+        69, 68,
+};
+static const unsigned int scif4_data_d_mux[] = {
+        RX4_D_MARK, TX4_D_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_pins[] = {
+        /* RXD, TXD */
+        51, 50,
+};
+static const unsigned int scif5_data_mux[] = {
+        RX5_MARK, TX5_MARK,
+};
+static const unsigned int scif5_clk_pins[] = {
+        /* SCK */
+        43,
+};
+static const unsigned int scif5_clk_mux[] = {
+        SCK5_MARK,
+};
+static const unsigned int scif5_data_b_pins[] = {
+        /* RXD, TXD */
+        18, 11,
+};
+static const unsigned int scif5_data_b_mux[] = {
+        RX5_B_MARK, TX5_B_MARK,
+};
+static const unsigned int scif5_clk_b_pins[] = {
+        /* SCK */
+        19,
+};
+static const unsigned int scif5_clk_b_mux[] = {
+        SCK5_B_MARK,
+};
+static const unsigned int scif5_data_c_pins[] = {
+        /* RXD, TXD */
+        24, 23,
+};
+static const unsigned int scif5_data_c_mux[] = {
+        RX5_C_MARK, TX5_C_MARK,
+};
+static const unsigned int scif5_clk_c_pins[] = {
+        /* SCK */
+        28,
+};
+static const unsigned int scif5_clk_c_mux[] = {
+        SCK5_C_MARK,
+};
+static const unsigned int scif5_data_d_pins[] = {
+        /* RXD, TXD */
+        8, 6,
+};
+static const unsigned int scif5_data_d_mux[] = {
+        RX5_D_MARK, TX5_D_MARK,
+};
+static const unsigned int scif5_clk_d_pins[] = {
+        /* SCK */
+        7,
+};
+static const unsigned int scif5_clk_d_mux[] = {
+        SCK5_D_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+        /* D0 */
+        117,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+        SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+        /* D[0:3] */
+        117, 118, 119, 120,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+        SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+        /* CMD, CLK */
+        114, 113,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+        SD0_CMD_MARK, SD0_CLK_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+        /* CD */
+        115,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+        SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+        /* WP */
+        116,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+        SD0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+        /* D0 */
+        19,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+        SD1_DAT0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+        /* D[0:3] */
+        19, 20, 21, 2,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+        SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+        /* CMD, CLK */
+        18, 17,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+        SD1_CMD_MARK, SD1_CLK_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+        /* CD */
+        10,
+};
+static const unsigned int sdhi1_cd_mux[] = {
+        SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+        /* WP */
+        11,
+};
+static const unsigned int sdhi1_wp_mux[] = {
+        SD1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+        /* D0 */
+        97,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+        SD2_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+        /* D[0:3] */
+        97, 98, 99, 100,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+        SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+        /* CMD, CLK */
+        102, 101,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+        SD2_CMD_MARK, SD2_CLK_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+        /* CD */
+        103,
+};
+static const unsigned int sdhi2_cd_mux[] = {
+        SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+        /* WP */
+        104,
+};
+static const unsigned int sdhi2_wp_mux[] = {
+        SD2_WP_MARK,
+};
+/* - SDHI3 ------------------------------------------------------------------ */
+static const unsigned int sdhi3_data1_pins[] = {
+        /* D0 */
+        50,
+};
+static const unsigned int sdhi3_data1_mux[] = {
+        SD3_DAT0_MARK,
+};
+static const unsigned int sdhi3_data4_pins[] = {
+        /* D[0:3] */
+        50, 51, 52, 53,
+};
+static const unsigned int sdhi3_data4_mux[] = {
+        SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+static const unsigned int sdhi3_ctrl_pins[] = {
+        /* CMD, CLK */
+        35, 34,
+};
+static const unsigned int sdhi3_ctrl_mux[] = {
+        SD3_CMD_MARK, SD3_CLK_MARK,
+};
+static const unsigned int sdhi3_cd_pins[] = {
+        /* CD */
+        62,
+};
+static const unsigned int sdhi3_cd_mux[] = {
+        SD3_CD_MARK,
+};
+static const unsigned int sdhi3_wp_pins[] = {
+        /* WP */
+        64,
+};
+static const unsigned int sdhi3_wp_mux[] = {
+        SD3_WP_MARK,
+};
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+        /* OVC */
+        150, 154,
+};
+static const unsigned int usb0_mux[] = {
+        USB_OVC0_MARK, USB_PENC0_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+        /* OVC */
+        152, 155,
+};
+static const unsigned int usb1_mux[] = {
+        USB_OVC1_MARK, USB_PENC1_MARK,
+};
+/* - USB2 ------------------------------------------------------------------- */
+static const unsigned int usb2_pins[] = {
+        /* OVC, PENC */
+        125, 156,
+};
+static const unsigned int usb2_mux[] = {
+        USB_OVC2_MARK, USB_PENC2_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(du0_rgb666),
+        SH_PFC_PIN_GROUP(du0_rgb888),
+        SH_PFC_PIN_GROUP(du0_clk_0),
+        SH_PFC_PIN_GROUP(du0_clk_1),
+        SH_PFC_PIN_GROUP(du0_sync_0),
+        SH_PFC_PIN_GROUP(du0_sync_1),
+        SH_PFC_PIN_GROUP(du0_oddf),
+        SH_PFC_PIN_GROUP(du0_cde),
+        SH_PFC_PIN_GROUP(du1_rgb666),
+        SH_PFC_PIN_GROUP(du1_rgb888),
+        SH_PFC_PIN_GROUP(du1_clk),
+        SH_PFC_PIN_GROUP(du1_sync_0),
+        SH_PFC_PIN_GROUP(du1_sync_1),
+        SH_PFC_PIN_GROUP(du1_oddf),
+        SH_PFC_PIN_GROUP(du1_cde),
+        SH_PFC_PIN_GROUP(hspi0),
+        SH_PFC_PIN_GROUP(hspi1),
+        SH_PFC_PIN_GROUP(hspi1_b),
+        SH_PFC_PIN_GROUP(hspi1_c),
+        SH_PFC_PIN_GROUP(hspi1_d),
+        SH_PFC_PIN_GROUP(hspi2),
+        SH_PFC_PIN_GROUP(hspi2_b),
+        SH_PFC_PIN_GROUP(intc_irq0),
+        SH_PFC_PIN_GROUP(intc_irq0_b),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq1_b),
+        SH_PFC_PIN_GROUP(intc_irq2),
+        SH_PFC_PIN_GROUP(intc_irq2_b),
+        SH_PFC_PIN_GROUP(intc_irq3),
+        SH_PFC_PIN_GROUP(intc_irq3_b),
+        SH_PFC_PIN_GROUP(lbsc_cs0),
+        SH_PFC_PIN_GROUP(lbsc_cs1),
+        SH_PFC_PIN_GROUP(lbsc_ex_cs0),
+        SH_PFC_PIN_GROUP(lbsc_ex_cs1),
+        SH_PFC_PIN_GROUP(lbsc_ex_cs2),
+        SH_PFC_PIN_GROUP(lbsc_ex_cs3),
+        SH_PFC_PIN_GROUP(lbsc_ex_cs4),
+        SH_PFC_PIN_GROUP(lbsc_ex_cs5),
+        SH_PFC_PIN_GROUP(mmc0_data1),
+        SH_PFC_PIN_GROUP(mmc0_data4),
+        SH_PFC_PIN_GROUP(mmc0_data8),
+        SH_PFC_PIN_GROUP(mmc0_ctrl),
+        SH_PFC_PIN_GROUP(mmc1_data1),
+        SH_PFC_PIN_GROUP(mmc1_data4),
+        SH_PFC_PIN_GROUP(mmc1_data8),
+        SH_PFC_PIN_GROUP(mmc1_ctrl),
+        SH_PFC_PIN_GROUP(scif0_data),
+        SH_PFC_PIN_GROUP(scif0_clk),
+        SH_PFC_PIN_GROUP(scif0_ctrl),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif0_clk_b),
+        SH_PFC_PIN_GROUP(scif0_ctrl_b),
+        SH_PFC_PIN_GROUP(scif0_data_c),
+        SH_PFC_PIN_GROUP(scif0_clk_c),
+        SH_PFC_PIN_GROUP(scif0_ctrl_c),
+        SH_PFC_PIN_GROUP(scif0_data_d),
+        SH_PFC_PIN_GROUP(scif0_clk_d),
+        SH_PFC_PIN_GROUP(scif0_ctrl_d),
+        SH_PFC_PIN_GROUP(scif1_data),
+        SH_PFC_PIN_GROUP(scif1_clk),
+        SH_PFC_PIN_GROUP(scif1_ctrl),
+        SH_PFC_PIN_GROUP(scif1_data_b),
+        SH_PFC_PIN_GROUP(scif1_clk_b),
+        SH_PFC_PIN_GROUP(scif1_ctrl_b),
+        SH_PFC_PIN_GROUP(scif1_data_c),
+        SH_PFC_PIN_GROUP(scif1_clk_c),
+        SH_PFC_PIN_GROUP(scif1_ctrl_c),
+        SH_PFC_PIN_GROUP(scif2_data),
+        SH_PFC_PIN_GROUP(scif2_clk),
+        SH_PFC_PIN_GROUP(scif2_data_b),
+        SH_PFC_PIN_GROUP(scif2_clk_b),
+        SH_PFC_PIN_GROUP(scif2_data_c),
+        SH_PFC_PIN_GROUP(scif2_clk_c),
+        SH_PFC_PIN_GROUP(scif2_data_d),
+        SH_PFC_PIN_GROUP(scif2_clk_d),
+        SH_PFC_PIN_GROUP(scif2_data_e),
+        SH_PFC_PIN_GROUP(scif3_data),
+        SH_PFC_PIN_GROUP(scif3_clk),
+        SH_PFC_PIN_GROUP(scif3_data_b),
+        SH_PFC_PIN_GROUP(scif3_data_c),
+        SH_PFC_PIN_GROUP(scif3_data_d),
+        SH_PFC_PIN_GROUP(scif3_data_e),
+        SH_PFC_PIN_GROUP(scif3_clk_e),
+        SH_PFC_PIN_GROUP(scif4_data),
+        SH_PFC_PIN_GROUP(scif4_clk),
+        SH_PFC_PIN_GROUP(scif4_data_b),
+        SH_PFC_PIN_GROUP(scif4_clk_b),
+        SH_PFC_PIN_GROUP(scif4_data_c),
+        SH_PFC_PIN_GROUP(scif4_data_d),
+        SH_PFC_PIN_GROUP(scif5_data),
+        SH_PFC_PIN_GROUP(scif5_clk),
+        SH_PFC_PIN_GROUP(scif5_data_b),
+        SH_PFC_PIN_GROUP(scif5_clk_b),
+        SH_PFC_PIN_GROUP(scif5_data_c),
+        SH_PFC_PIN_GROUP(scif5_clk_c),
+        SH_PFC_PIN_GROUP(scif5_data_d),
+        SH_PFC_PIN_GROUP(scif5_clk_d),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_data1),
+        SH_PFC_PIN_GROUP(sdhi1_data4),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi1_cd),
+        SH_PFC_PIN_GROUP(sdhi1_wp),
+        SH_PFC_PIN_GROUP(sdhi2_data1),
+        SH_PFC_PIN_GROUP(sdhi2_data4),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(sdhi2_cd),
+        SH_PFC_PIN_GROUP(sdhi2_wp),
+        SH_PFC_PIN_GROUP(sdhi3_data1),
+        SH_PFC_PIN_GROUP(sdhi3_data4),
+        SH_PFC_PIN_GROUP(sdhi3_ctrl),
+        SH_PFC_PIN_GROUP(sdhi3_cd),
+        SH_PFC_PIN_GROUP(sdhi3_wp),
+        SH_PFC_PIN_GROUP(usb0),
+        SH_PFC_PIN_GROUP(usb1),
+        SH_PFC_PIN_GROUP(usb2),
+};
+
+static const char * const du0_groups[] = {
+        "du0_rgb666",
+        "du0_rgb888",
+        "du0_clk_0",
+        "du0_clk_1",
+        "du0_sync_0",
+        "du0_sync_1",
+        "du0_oddf",
+        "du0_cde",
+};
+
+static const char * const du1_groups[] = {
+        "du1_rgb666",
+        "du1_rgb888",
+        "du1_clk",
+        "du1_sync_0",
+        "du1_sync_1",
+        "du1_oddf",
+        "du1_cde",
+};
+
+static const char * const hspi0_groups[] = {
+        "hspi0",
+};
+
+static const char * const hspi1_groups[] = {
+        "hspi1",
+        "hspi1_b",
+        "hspi1_c",
+        "hspi1_d",
+};
+
+static const char * const hspi2_groups[] = {
+        "hspi2",
+        "hspi2_b",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0",
+        "intc_irq0_b",
+        "intc_irq1",
+        "intc_irq1_b",
+        "intc_irq2",
+        "intc_irq2_b",
+        "intc_irq3",
+        "intc_irq4_b",
+};
+
+static const char * const lbsc_groups[] = {
+        "lbsc_cs0",
+        "lbsc_cs1",
+        "lbsc_ex_cs0",
+        "lbsc_ex_cs1",
+        "lbsc_ex_cs2",
+        "lbsc_ex_cs3",
+        "lbsc_ex_cs4",
+        "lbsc_ex_cs5",
+};
+
+static const char * const mmc0_groups[] = {
+        "mmc0_data1",
+        "mmc0_data4",
+        "mmc0_data8",
+        "mmc0_ctrl",
+};
+
+static const char * const mmc1_groups[] = {
+        "mmc1_data1",
+        "mmc1_data4",
+        "mmc1_data8",
+        "mmc1_ctrl",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data",
+        "scif0_clk",
+        "scif0_ctrl",
+        "scif0_data_b",
+        "scif0_clk_b",
+        "scif0_ctrl_b",
+        "scif0_data_c",
+        "scif0_clk_c",
+        "scif0_ctrl_c",
+        "scif0_data_d",
+        "scif0_clk_d",
+        "scif0_ctrl_d",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data",
+        "scif1_clk",
+        "scif1_ctrl",
+        "scif1_data_b",
+        "scif1_clk_b",
+        "scif1_ctrl_b",
+        "scif1_data_c",
+        "scif1_clk_c",
+        "scif1_ctrl_c",
+};
+
+static const char * const scif2_groups[] = {
+        "scif2_data",
+        "scif2_clk",
+        "scif2_data_b",
+        "scif2_clk_b",
+        "scif2_data_c",
+        "scif2_clk_c",
+        "scif2_data_d",
+        "scif2_clk_d",
+        "scif2_data_e",
+};
+
+static const char * const scif3_groups[] = {
+        "scif3_data",
+        "scif3_clk",
+        "scif3_data_b",
+        "scif3_data_c",
+        "scif3_data_d",
+        "scif3_data_e",
+        "scif3_clk_e",
+};
+
+static const char * const scif4_groups[] = {
+        "scif4_data",
+        "scif4_clk",
+        "scif4_data_b",
+        "scif4_clk_b",
+        "scif4_data_c",
+        "scif4_data_d",
+};
+
+static const char * const scif5_groups[] = {
+        "scif5_data",
+        "scif5_clk",
+        "scif5_data_b",
+        "scif5_clk_b",
+        "scif5_data_c",
+        "scif5_clk_c",
+        "scif5_data_d",
+        "scif5_clk_d",
+};
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_ctrl",
+        "sdhi0_cd",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_data1",
+        "sdhi1_data4",
+        "sdhi1_ctrl",
+        "sdhi1_cd",
+        "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_data1",
+        "sdhi2_data4",
+        "sdhi2_ctrl",
+        "sdhi2_cd",
+        "sdhi2_wp",
+};
+
+static const char * const sdhi3_groups[] = {
+        "sdhi3_data1",
+        "sdhi3_data4",
+        "sdhi3_ctrl",
+        "sdhi3_cd",
+        "sdhi3_wp",
+};
+
+static const char * const usb0_groups[] = {
+        "usb0",
+};
+
+static const char * const usb1_groups[] = {
+        "usb1",
+};
+
+static const char * const usb2_groups[] = {
+        "usb2",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(du0),
+        SH_PFC_FUNCTION(du1),
+        SH_PFC_FUNCTION(hspi0),
+        SH_PFC_FUNCTION(hspi1),
+        SH_PFC_FUNCTION(hspi2),
+        SH_PFC_FUNCTION(intc),
+        SH_PFC_FUNCTION(lbsc),
+        SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(mmc1),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(sdhi3),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scif2),
+        SH_PFC_FUNCTION(scif3),
+        SH_PFC_FUNCTION(scif4),
+        SH_PFC_FUNCTION(scif5),
+        SH_PFC_FUNCTION(usb0),
+        SH_PFC_FUNCTION(usb1),
+        SH_PFC_FUNCTION(usb2),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
+
+static const struct pinmux_func pinmux_func_gpios[] = {
         GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
         GPIO_FN(A19),
 
         /* IPSR0 */
-        GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
-        GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
-        GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
-        GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
-        GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
-        GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
-        GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
-        GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
-        GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD),
-        GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
-        GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5),
-        GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
-        GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
-        GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
-        GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
+        GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
+        GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS),
+        GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
+        GPIO_FN(HCTS1), GPIO_FN(A0),
+        GPIO_FN(FD3), GPIO_FN(A20),
+        GPIO_FN(A21),
+        GPIO_FN(A22),
+        GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
+        GPIO_FN(VI1_R1), GPIO_FN(A24),
+        GPIO_FN(FD4),   GPIO_FN(VI1_R2),
+        GPIO_FN(SSI_WS78_B), GPIO_FN(A25),
+        GPIO_FN(FD5), GPIO_FN(VI1_R3),
+        GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT),
+        GPIO_FN(PWM0_B),
         GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
-        GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
+        GPIO_FN(VI1_R7), GPIO_FN(HRTS1),
 
         /* IPSR1 */
-        GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6),
-        GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7),
-        GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE),
-        GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD),
-        GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
-        GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
-        GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0),
-        GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
-        GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
-        GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1),
-        GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
-        GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
-        GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
-        GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
-        GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA),
-        GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
+        GPIO_FN(FD6), GPIO_FN(FD7),
+        GPIO_FN(FALE),
+        GPIO_FN(ATACS00),
+        GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4),
+        GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B),
+        GPIO_FN(SSI_SDATA9),
+        GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
+        GPIO_FN(HTX1),
+        GPIO_FN(SSI_SCK9),
+        GPIO_FN(FD1),   GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
+        GPIO_FN(HRX1), GPIO_FN(SSI_WS9),
+        GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(MLB_SIG),
+        GPIO_FN(PWM3), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
+        GPIO_FN(HTX0), GPIO_FN(SDATA),
+        GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
         GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
         GPIO_FN(CC5_STATE34),
 
         /* IPSR2 */
-        GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C),
+        GPIO_FN(HRX0), GPIO_FN(SCKZ),
         GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
         GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
-        GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5),
-        GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
+        GPIO_FN(HSCK0), GPIO_FN(MTS), GPIO_FN(PWM5),
+        GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
         GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
         GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
-        GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C),
+        GPIO_FN(STM), GPIO_FN(PWM0_D),
         GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
-        GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
-        GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
+        GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0),
+        GPIO_FN(MDATA), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
         GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
-        GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0),
+        GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0),
         GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
-        GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
-        GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
-        GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3),
-        GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5),
-        GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7),
-        GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
+        GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
+        GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1),
+        GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3),
+        GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5),
+        GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7),
+        GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
         GPIO_FN(AUDATA2),
 
         /* IPSR3 */
-        GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
-        GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10),
-        GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4),
-        GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13),
-        GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7),
-        GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16),
+        GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
+        GPIO_FN(AUDATA3), GPIO_FN(LCDOUT10),
+        GPIO_FN(LCDOUT11),
+        GPIO_FN(LCDOUT12), GPIO_FN(LCDOUT13),
+        GPIO_FN(LCDOUT14),
+        GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16),
         GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
-        GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
-        GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
-        GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3),
-        GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20),
-        GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6),
-        GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23),
-        GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
-        GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK),
-        GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
+        GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
+        GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5),
+        GPIO_FN(LCDOUT18),
+        GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20),
+        GPIO_FN(LCDOUT21),
+        GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23),
+        GPIO_FN(QSTVA_QVS),
+        GPIO_FN(SCL3_B), GPIO_FN(QCLK),
+        GPIO_FN(QSTVB_QVE),
         GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
-        GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS),
-        GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
-        GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
-        GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
+        GPIO_FN(QSTH_QHS),
+        GPIO_FN(QSTB_QHE),
+        GPIO_FN(QCPV_QDE),
+        GPIO_FN(CAN1_TX), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
 
         /* IPSR4 */
-        GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
-        GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
-        GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
-        GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
-        GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
-        GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1),
-        GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
-        GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0),
-        GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2),
-        GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4),
-        GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0),
-        GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
-        GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1),
-        GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
-        GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2),
-        GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4),
-        GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6),
-        GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0),
-        GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
-        GPIO_FN(TX5), GPIO_FN(SCK0_D),
+        GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C),
+        GPIO_FN(QPOLB), GPIO_FN(CAN1_RX),
+        GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B),
+        GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
+        GPIO_FN(AUDCK),
+        GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1),
+        GPIO_FN(PWM0),
+        GPIO_FN(AUDSYNC), GPIO_FN(VI2_G0),
+        GPIO_FN(VI2_G1), GPIO_FN(VI2_G2),
+        GPIO_FN(VI2_G3), GPIO_FN(VI2_G4),
+        GPIO_FN(VI2_G5),
+        GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B),
+        GPIO_FN(AUDATA6),
+        GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B),
+        GPIO_FN(AUDATA7),
+        GPIO_FN(VI2_G6), GPIO_FN(VI2_G7),
+        GPIO_FN(VI2_R0), GPIO_FN(VI2_R1),
+        GPIO_FN(VI2_R2), GPIO_FN(VI2_R3),
+        GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B),
 
         /* IPSR5 */
-        GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
-        GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
-        GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5),
-        GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7),
-        GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D),
-        GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
-        GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD),
-        GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC),
-        GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC),
-        GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE),
-        GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
-        GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
-        GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
-        GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6),
-        GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
-        GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
-        GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
-        GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
-        GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
+        GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
+        GPIO_FN(VI2_R4), GPIO_FN(VI2_R5),
+        GPIO_FN(VI2_R6), GPIO_FN(VI2_R7),
+        GPIO_FN(SCL2_D), GPIO_FN(SDA2_D),
+        GPIO_FN(VI2_CLKENB),
+        GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD),
+        GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC),
+        GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC),
+        GPIO_FN(VI3_VSYNC),
+        GPIO_FN(VI2_CLK),
+        GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
+        GPIO_FN(AUDIO_CLKC), GPIO_FN(SPEEDIN),
+        GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6),
+        GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B),
+        GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
+        GPIO_FN(VI2_DATA7_VI2_B7),
+        GPIO_FN(VI1_FIELD),
+        GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT),
         GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
-        GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
+        GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB),
         GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
 
         /* IPSR6 */
@@ -1599,89 +2816,87 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
         GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
         GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
-        GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
+        GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(TCLK0_D),
         GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
-        GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
-        GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
+        GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
+        GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6),
         GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
 
         /* IPSR7 */
         GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
         GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
         GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
-        GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
-        GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
-        GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
-        GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
-        GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
-        GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
-        GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
-        GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
-        GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
-        GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
-        GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
-        GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
-        GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
-        GPIO_FN(CTS1_B),
+        GPIO_FN(SSI_SCK9_B),
+        GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14),
+        GPIO_FN(SSI_WS9_B), GPIO_FN(SSI_SDATA7),
+        GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(TCLK1_C),
+        GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
+        GPIO_FN(ATACS01), GPIO_FN(ATACS11),
+        GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1),
+        GPIO_FN(CC5_TRST), GPIO_FN(ATAG1),
+        GPIO_FN(CC5_TMS), GPIO_FN(ATARD1),
+        GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1),
+        GPIO_FN(CC5_TDI), GPIO_FN(DREQ2),
+        GPIO_FN(DACK2),
 
         /* IPSR8 */
-        GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
+        GPIO_FN(AD_CLK),
         GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
-        GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
-        GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
+        GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36),
+        GPIO_FN(AD_DI),
         GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
-        GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
-        GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
+        GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37),
+        GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
         GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
-        GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
-        GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
+        GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38),
+        GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
         GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
         GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
         GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
-        GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
-        GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
-        GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
-        GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
-        GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
+        GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB),
+        GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
+        GPIO_FN(VI0_FIELD), GPIO_FN(HRX1_B),
+        GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B),
+        GPIO_FN(HSCK1_B),
         GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
-        GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
+        GPIO_FN(PWMFSW0_C),
 
         /* IPSR9 */
         GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
         GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
-        GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3),
-        GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2),
-        GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6),
-        GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
-        GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
-        GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
-        GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
+        GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(VI0_DATA3_VI0_B3),
+        GPIO_FN(VI0_DATA4_VI0_B4),
+        GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(VI0_DATA6_VI0_B6),
+        GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
+        GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
+        GPIO_FN(SSI_SCK78_C), GPIO_FN(ARM_TRACEDATA_2),
+        GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C),
         GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
-        GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
-        GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
+        GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
+        GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV),
         GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
-        GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
-        GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
+        GPIO_FN(ETH_TX_EN), GPIO_FN(ARM_TRACEDATA_6),
+        GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER),
         GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
-        GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
-        GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
+        GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
+        GPIO_FN(ETH_RXD1), GPIO_FN(ARM_TRACEDATA_9),
 
         /* IPSR10 */
-        GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
+        GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C),
         GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
         GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
         GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
-        GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2),
+        GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK),
         GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
-        GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
-        GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
-        GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
+        GPIO_FN(ARM_TRACEDATA_13),
+        GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK),
+        GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
         GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
-        GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
+        GPIO_FN(ARM_TRACEDATA_15),
         GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
-        GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
+        GPIO_FN(DREQ2_C), GPIO_FN(TRACECLK),
         GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
-        GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
+        GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C),
         GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
         GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
         GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
@@ -1690,40 +2905,40 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
 
         /* IPSR11 */
-        GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST),
+        GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SIM_RST),
         GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
-        GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
-        GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2),
+        GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
+        GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2),
         GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
-        GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
+        GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(MT0_BEN),
         GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
-        GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
-        GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
-        GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
-        GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
-        GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
-        GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
-        GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
-        GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
-        GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
+        GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
+        GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
+        GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
+        GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
+        GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
+        GPIO_FN(VI1_DATA7_VI1_B7),
+        GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI),
+        GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0),
+        GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(SPA_TDO),
         GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
-        GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
+        GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B),
         GPIO_FN(HRTS0_B),
 
         /* IPSR12 */
         GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
-        GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
+        GPIO_FN(TS_SPSYNC1), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
         GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
         GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
         GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
         GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
-        GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B),
+        GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(SIM_D_B),
         GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
-        GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
-        GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
+        GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
+        GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
                 GP_0_31_FN, FN_IP3_31_29,
                 GP_0_30_FN, FN_IP3_26_24,
@@ -2412,7 +3627,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
             FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
             FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
             /* IP11_26_24 [3] */
-            FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1,
+            FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
             FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
             /* IP11_23_21 [3] */
             FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
@@ -2584,7 +3799,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         { },
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
         { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
         { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
@@ -2600,22 +3815,25 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info r8a7779_pinmux_info = {
+const struct sh_pfc_soc_info r8a7779_pinmux_info = {
         .name = "r8a7779_pfc",
 
         .unlock_reg = 0xfffc0000, /* PMMR */
 
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_GP_0_0,
-        .last_gpio = GPIO_FN_SCK4_B,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index 01b425dfd162..f63d51dc3f4c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -272,7 +272,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
 
         /* PA */
         PINMUX_DATA(PA7_DATA, PA7_IN),
@@ -703,7 +703,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
 
         /* PA */
         PINMUX_GPIO(GPIO_PA7, PA7_DATA),
@@ -815,265 +815,269 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PF2, PF2_DATA),
         PINMUX_GPIO(GPIO_PF1, PF1_DATA),
         PINMUX_GPIO(GPIO_PF0, PF0_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* INTC */
-        PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
-
-        PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK),
+        GPIO_FN(PINT7_PB),
+        GPIO_FN(PINT6_PB),
+        GPIO_FN(PINT5_PB),
+        GPIO_FN(PINT4_PB),
+        GPIO_FN(PINT3_PB),
+        GPIO_FN(PINT2_PB),
+        GPIO_FN(PINT1_PB),
+        GPIO_FN(PINT0_PB),
+        GPIO_FN(PINT7_PD),
+        GPIO_FN(PINT6_PD),
+        GPIO_FN(PINT5_PD),
+        GPIO_FN(PINT4_PD),
+        GPIO_FN(PINT3_PD),
+        GPIO_FN(PINT2_PD),
+        GPIO_FN(PINT1_PD),
+        GPIO_FN(PINT0_PD),
+        GPIO_FN(IRQ7_PB),
+        GPIO_FN(IRQ6_PB),
+        GPIO_FN(IRQ5_PB),
+        GPIO_FN(IRQ4_PB),
+        GPIO_FN(IRQ3_PB),
+        GPIO_FN(IRQ2_PB),
+        GPIO_FN(IRQ1_PB),
+        GPIO_FN(IRQ0_PB),
+        GPIO_FN(IRQ7_PD),
+        GPIO_FN(IRQ6_PD),
+        GPIO_FN(IRQ5_PD),
+        GPIO_FN(IRQ4_PD),
+        GPIO_FN(IRQ3_PD),
+        GPIO_FN(IRQ2_PD),
+        GPIO_FN(IRQ1_PD),
+        GPIO_FN(IRQ0_PD),
+        GPIO_FN(IRQ7_PE),
+        GPIO_FN(IRQ6_PE),
+        GPIO_FN(IRQ5_PE),
+        GPIO_FN(IRQ4_PE),
+        GPIO_FN(IRQ3_PE),
+        GPIO_FN(IRQ2_PE),
+        GPIO_FN(IRQ1_PE),
+        GPIO_FN(IRQ0_PE),
+
+        GPIO_FN(WDTOVF),
+        GPIO_FN(IRQOUT),
+        GPIO_FN(REFOUT),
+        GPIO_FN(IRQOUT_REFOUT),
+        GPIO_FN(UBCTRG),
 
         /* CAN */
-        PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
-        PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
-        PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
-        PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK),
-        PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
-        PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
+        GPIO_FN(CTX1),
+        GPIO_FN(CRX1),
+        GPIO_FN(CTX0),
+        GPIO_FN(CTX0_CTX1),
+        GPIO_FN(CRX0),
+        GPIO_FN(CRX0_CRX1),
 
         /* IIC3 */
-        PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
+        GPIO_FN(SDA3),
+        GPIO_FN(SCL3),
+        GPIO_FN(SDA2),
+        GPIO_FN(SCL2),
+        GPIO_FN(SDA1),
+        GPIO_FN(SCL1),
+        GPIO_FN(SDA0),
+        GPIO_FN(SCL0),
 
         /* DMAC */
-        PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
+        GPIO_FN(TEND0_PD),
+        GPIO_FN(TEND0_PE),
+        GPIO_FN(DACK0_PD),
+        GPIO_FN(DACK0_PE),
+        GPIO_FN(DREQ0_PD),
+        GPIO_FN(DREQ0_PE),
+        GPIO_FN(TEND1_PD),
+        GPIO_FN(TEND1_PE),
+        GPIO_FN(DACK1_PD),
+        GPIO_FN(DACK1_PE),
+        GPIO_FN(DREQ1_PD),
+        GPIO_FN(DREQ1_PE),
+        GPIO_FN(DACK2),
+        GPIO_FN(DREQ2),
+        GPIO_FN(DACK3),
+        GPIO_FN(DREQ3),
 
         /* ADC */
-        PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK),
+        GPIO_FN(ADTRG_PD),
+        GPIO_FN(ADTRG_PE),
 
         /* BSC */
-        PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
-        PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
-        PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
-        PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
-        PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
-        PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
-        PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
-        PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
-        PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
-        PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
-        PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
-        PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
-        PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
-        PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
-        PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
-        PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
-        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
-        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
-        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
-        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
-        PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
-        PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
-        PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK),
-        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
-        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
-        PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
-        PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK),
-        PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
-        PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
-        PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
-        PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK),
-        PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
-        PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK),
-        PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
-        PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK),
-        PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK),
-        PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK),
-        PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK),
-        PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK),
-        PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK),
-        PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
-        PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
-        PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
-        PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
-        PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK),
+        GPIO_FN(D31),
+        GPIO_FN(D30),
+        GPIO_FN(D29),
+        GPIO_FN(D28),
+        GPIO_FN(D27),
+        GPIO_FN(D26),
+        GPIO_FN(D25),
+        GPIO_FN(D24),
+        GPIO_FN(D23),
+        GPIO_FN(D22),
+        GPIO_FN(D21),
+        GPIO_FN(D20),
+        GPIO_FN(D19),
+        GPIO_FN(D18),
+        GPIO_FN(D17),
+        GPIO_FN(D16),
+        GPIO_FN(A25),
+        GPIO_FN(A24),
+        GPIO_FN(A23),
+        GPIO_FN(A22),
+        GPIO_FN(A21),
+        GPIO_FN(CS4),
+        GPIO_FN(MRES),
+        GPIO_FN(BS),
+        GPIO_FN(IOIS16),
+        GPIO_FN(CS1),
+        GPIO_FN(CS6_CE1B),
+        GPIO_FN(CE2B),
+        GPIO_FN(CS5_CE1A),
+        GPIO_FN(CE2A),
+        GPIO_FN(FRAME),
+        GPIO_FN(WAIT),
+        GPIO_FN(RDWR),
+        GPIO_FN(CKE),
+        GPIO_FN(CASU),
+        GPIO_FN(BREQ),
+        GPIO_FN(RASU),
+        GPIO_FN(BACK),
+        GPIO_FN(CASL),
+        GPIO_FN(RASL),
+        GPIO_FN(WE3_DQMUU_AH_ICIO_WR),
+        GPIO_FN(WE2_DQMUL_ICIORD),
+        GPIO_FN(WE1_DQMLU_WE),
+        GPIO_FN(WE0_DQMLL),
+        GPIO_FN(CS3),
+        GPIO_FN(CS2),
+        GPIO_FN(A1),
+        GPIO_FN(A0),
+        GPIO_FN(CS7),
 
         /* TMU */
-        PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK),
+        GPIO_FN(TIOC4D),
+        GPIO_FN(TIOC4C),
+        GPIO_FN(TIOC4B),
+        GPIO_FN(TIOC4A),
+        GPIO_FN(TIOC3D),
+        GPIO_FN(TIOC3C),
+        GPIO_FN(TIOC3B),
+        GPIO_FN(TIOC3A),
+        GPIO_FN(TIOC2B),
+        GPIO_FN(TIOC1B),
+        GPIO_FN(TIOC2A),
+        GPIO_FN(TIOC1A),
+        GPIO_FN(TIOC0D),
+        GPIO_FN(TIOC0C),
+        GPIO_FN(TIOC0B),
+        GPIO_FN(TIOC0A),
+        GPIO_FN(TCLKD_PD),
+        GPIO_FN(TCLKC_PD),
+        GPIO_FN(TCLKB_PD),
+        GPIO_FN(TCLKA_PD),
+        GPIO_FN(TCLKD_PF),
+        GPIO_FN(TCLKC_PF),
+        GPIO_FN(TCLKB_PF),
+        GPIO_FN(TCLKA_PF),
 
         /* SSU */
-        PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK),
+        GPIO_FN(SCS0_PD),
+        GPIO_FN(SSO0_PD),
+        GPIO_FN(SSI0_PD),
+        GPIO_FN(SSCK0_PD),
+        GPIO_FN(SCS0_PF),
+        GPIO_FN(SSO0_PF),
+        GPIO_FN(SSI0_PF),
+        GPIO_FN(SSCK0_PF),
+        GPIO_FN(SCS1_PD),
+        GPIO_FN(SSO1_PD),
+        GPIO_FN(SSI1_PD),
+        GPIO_FN(SSCK1_PD),
+        GPIO_FN(SCS1_PF),
+        GPIO_FN(SSO1_PF),
+        GPIO_FN(SSI1_PF),
+        GPIO_FN(SSCK1_PF),
 
         /* SCIF */
-        PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
+        GPIO_FN(TXD0),
+        GPIO_FN(RXD0),
+        GPIO_FN(SCK0),
+        GPIO_FN(TXD1),
+        GPIO_FN(RXD1),
+        GPIO_FN(SCK1),
+        GPIO_FN(TXD2),
+        GPIO_FN(RXD2),
+        GPIO_FN(SCK2),
+        GPIO_FN(RTS3),
+        GPIO_FN(CTS3),
+        GPIO_FN(TXD3),
+        GPIO_FN(RXD3),
+        GPIO_FN(SCK3),
 
         /* SSI */
-        PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
-        PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
-        PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
+        GPIO_FN(AUDIO_CLK),
+        GPIO_FN(SSIDATA3),
+        GPIO_FN(SSIWS3),
+        GPIO_FN(SSISCK3),
+        GPIO_FN(SSIDATA2),
+        GPIO_FN(SSIWS2),
+        GPIO_FN(SSISCK2),
+        GPIO_FN(SSIDATA1),
+        GPIO_FN(SSIWS1),
+        GPIO_FN(SSISCK1),
+        GPIO_FN(SSIDATA0),
+        GPIO_FN(SSIWS0),
+        GPIO_FN(SSISCK0),
 
         /* FLCTL */
-        PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
-        PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
-        PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
-        PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
-        PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
-        PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
+        GPIO_FN(FCE),
+        GPIO_FN(FRB),
+        GPIO_FN(NAF7),
+        GPIO_FN(NAF6),
+        GPIO_FN(NAF5),
+        GPIO_FN(NAF4),
+        GPIO_FN(NAF3),
+        GPIO_FN(NAF2),
+        GPIO_FN(NAF1),
+        GPIO_FN(NAF0),
+        GPIO_FN(FSC),
+        GPIO_FN(FOE),
+        GPIO_FN(FCDE),
+        GPIO_FN(FWE),
 
         /* LCDC */
-        PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
+        GPIO_FN(LCD_VEPWC),
+        GPIO_FN(LCD_VCPWC),
+        GPIO_FN(LCD_CLK),
+        GPIO_FN(LCD_FLM),
+        GPIO_FN(LCD_M_DISP),
+        GPIO_FN(LCD_CL2),
+        GPIO_FN(LCD_CL1),
+        GPIO_FN(LCD_DON),
+        GPIO_FN(LCD_DATA15),
+        GPIO_FN(LCD_DATA14),
+        GPIO_FN(LCD_DATA13),
+        GPIO_FN(LCD_DATA12),
+        GPIO_FN(LCD_DATA11),
+        GPIO_FN(LCD_DATA10),
+        GPIO_FN(LCD_DATA9),
+        GPIO_FN(LCD_DATA8),
+        GPIO_FN(LCD_DATA7),
+        GPIO_FN(LCD_DATA6),
+        GPIO_FN(LCD_DATA5),
+        GPIO_FN(LCD_DATA4),
+        GPIO_FN(LCD_DATA3),
+        GPIO_FN(LCD_DATA2),
+        GPIO_FN(LCD_DATA1),
+        GPIO_FN(LCD_DATA0),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
                 0, 0,
                 0, 0,
@@ -1525,7 +1529,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         {}
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) {
                 0, 0, 0, 0,
                 0, 0, 0, 0,
@@ -1571,19 +1575,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info sh7203_pinmux_info = {
+const struct sh_pfc_soc_info sh7203_pinmux_info = {
         .name = "sh7203_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PA7,
-        .last_gpio = GPIO_FN_LCD_DATA0,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index 2ba5639dcf34..284675249ed9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -604,7 +604,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
 
         /* Port A */
         PINMUX_DATA(PA3_DATA, PA3_IN),
@@ -1072,7 +1072,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(SD_D2_MARK, PK0MD_10),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
 
         /* Port A */
         PINMUX_GPIO(GPIO_PA3, PA3_DATA),
@@ -1216,257 +1216,261 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PK2, PK2_DATA),
         PINMUX_GPIO(GPIO_PK1, PK1_DATA),
         PINMUX_GPIO(GPIO_PK0, PK0_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* INTC */
-        PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
-
-        PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
+        GPIO_FN(PINT7_PG),
+        GPIO_FN(PINT6_PG),
+        GPIO_FN(PINT5_PG),
+        GPIO_FN(PINT4_PG),
+        GPIO_FN(PINT3_PG),
+        GPIO_FN(PINT2_PG),
+        GPIO_FN(PINT1_PG),
+
+        GPIO_FN(IRQ7_PC),
+        GPIO_FN(IRQ6_PC),
+        GPIO_FN(IRQ5_PC),
+        GPIO_FN(IRQ4_PC),
+        GPIO_FN(IRQ3_PG),
+        GPIO_FN(IRQ2_PG),
+        GPIO_FN(IRQ1_PJ),
+        GPIO_FN(IRQ0_PJ),
+        GPIO_FN(IRQ3_PE),
+        GPIO_FN(IRQ2_PE),
+        GPIO_FN(IRQ1_PE),
+        GPIO_FN(IRQ0_PE),
 
         /* WDT */
-        PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
+        GPIO_FN(WDTOVF),
 
         /* CAN */
-        PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
-        PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
-        PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
-        PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
-        PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
+        GPIO_FN(CTX1),
+        GPIO_FN(CRX1),
+        GPIO_FN(CTX0),
+        GPIO_FN(CRX0),
+        GPIO_FN(CRX0_CRX1),
 
         /* DMAC */
-        PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
+        GPIO_FN(TEND0),
+        GPIO_FN(DACK0),
+        GPIO_FN(DREQ0),
+        GPIO_FN(TEND1),
+        GPIO_FN(DACK1),
+        GPIO_FN(DREQ1),
 
         /* ADC */
-        PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
+        GPIO_FN(ADTRG),
 
         /* BSCh */
-        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
-        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
-        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
-        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
-        PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
-        PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
-        PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
-        PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
-        PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
-        PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
-        PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
-        PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
-        PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
-        PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
-        PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
-        PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
-        PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
-        PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
-        PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
-        PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
-        PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
-        PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
-        PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
-        PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
-        PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
-        PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
-
-        PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
-        PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
-        PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
-        PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
-        PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
-        PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
-        PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
-        PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
-        PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
-        PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
-        PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
-        PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
-        PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
-        PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
-        PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
-        PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
-
-        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
-        PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
-        PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
-        PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
-        PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
-        PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
-        PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
-        PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
-        PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK),
-        PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK),
-        PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
-        PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
-        PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
-        PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
-        PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
-        PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
-        PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
-        PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
-        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
+        GPIO_FN(A25),
+        GPIO_FN(A24),
+        GPIO_FN(A23),
+        GPIO_FN(A22),
+        GPIO_FN(A21),
+        GPIO_FN(A20),
+        GPIO_FN(A19),
+        GPIO_FN(A18),
+        GPIO_FN(A17),
+        GPIO_FN(A16),
+        GPIO_FN(A15),
+        GPIO_FN(A14),
+        GPIO_FN(A13),
+        GPIO_FN(A12),
+        GPIO_FN(A11),
+        GPIO_FN(A10),
+        GPIO_FN(A9),
+        GPIO_FN(A8),
+        GPIO_FN(A7),
+        GPIO_FN(A6),
+        GPIO_FN(A5),
+        GPIO_FN(A4),
+        GPIO_FN(A3),
+        GPIO_FN(A2),
+        GPIO_FN(A1),
+        GPIO_FN(A0),
+
+        GPIO_FN(D15),
+        GPIO_FN(D14),
+        GPIO_FN(D13),
+        GPIO_FN(D12),
+        GPIO_FN(D11),
+        GPIO_FN(D10),
+        GPIO_FN(D9),
+        GPIO_FN(D8),
+        GPIO_FN(D7),
+        GPIO_FN(D6),
+        GPIO_FN(D5),
+        GPIO_FN(D4),
+        GPIO_FN(D3),
+        GPIO_FN(D2),
+        GPIO_FN(D1),
+        GPIO_FN(D0),
+
+        GPIO_FN(BS),
+        GPIO_FN(CS4),
+        GPIO_FN(CS3),
+        GPIO_FN(CS2),
+        GPIO_FN(CS1),
+        GPIO_FN(CS0),
+        GPIO_FN(CS6CE1B),
+        GPIO_FN(CS5CE1A),
+        GPIO_FN(CE2A),
+        GPIO_FN(CE2B),
+        GPIO_FN(RD),
+        GPIO_FN(RDWR),
+        GPIO_FN(ICIOWRAH),
+        GPIO_FN(ICIORD),
+        GPIO_FN(WE1DQMUWE),
+        GPIO_FN(WE0DQML),
+        GPIO_FN(RAS),
+        GPIO_FN(CAS),
+        GPIO_FN(CKE),
+        GPIO_FN(WAIT),
+        GPIO_FN(BREQ),
+        GPIO_FN(BACK),
+        GPIO_FN(IOIS16),
 
         /* TMU */
-        PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
+        GPIO_FN(TIOC4D),
+        GPIO_FN(TIOC4C),
+        GPIO_FN(TIOC4B),
+        GPIO_FN(TIOC4A),
+        GPIO_FN(TIOC3D),
+        GPIO_FN(TIOC3C),
+        GPIO_FN(TIOC3B),
+        GPIO_FN(TIOC3A),
+        GPIO_FN(TIOC2B),
+        GPIO_FN(TIOC1B),
+        GPIO_FN(TIOC2A),
+        GPIO_FN(TIOC1A),
+        GPIO_FN(TIOC0D),
+        GPIO_FN(TIOC0C),
+        GPIO_FN(TIOC0B),
+        GPIO_FN(TIOC0A),
+        GPIO_FN(TCLKD),
+        GPIO_FN(TCLKC),
+        GPIO_FN(TCLKB),
+        GPIO_FN(TCLKA),
 
         /* SCIF */
-        PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
+        GPIO_FN(TXD0),
+        GPIO_FN(RXD0),
+        GPIO_FN(SCK0),
+        GPIO_FN(TXD1),
+        GPIO_FN(RXD1),
+        GPIO_FN(SCK1),
+        GPIO_FN(TXD2),
+        GPIO_FN(RXD2),
+        GPIO_FN(SCK2),
+        GPIO_FN(RTS3),
+        GPIO_FN(CTS3),
+        GPIO_FN(TXD3),
+        GPIO_FN(RXD3),
+        GPIO_FN(SCK3),
+        GPIO_FN(TXD4),
+        GPIO_FN(RXD4),
+        GPIO_FN(TXD5),
+        GPIO_FN(RXD5),
+        GPIO_FN(TXD6),
+        GPIO_FN(RXD6),
+        GPIO_FN(TXD7),
+        GPIO_FN(RXD7),
+        GPIO_FN(RTS1),
+        GPIO_FN(CTS1),
 
         /* RSPI */
-        PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK),
-        PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK),
-        PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK),
-        PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK),
-        PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
-        PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
-        PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK),
-        PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
+        GPIO_FN(RSPCK0),
+        GPIO_FN(MOSI0),
+        GPIO_FN(MISO0_PF12),
+        GPIO_FN(MISO1),
+        GPIO_FN(SSL00),
+        GPIO_FN(RSPCK1),
+        GPIO_FN(MOSI1),
+        GPIO_FN(MISO1_PG19),
+        GPIO_FN(SSL10),
 
         /* IIC3 */
-        PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
+        GPIO_FN(SCL0),
+        GPIO_FN(SCL1),
+        GPIO_FN(SCL2),
+        GPIO_FN(SDA0),
+        GPIO_FN(SDA1),
+        GPIO_FN(SDA2),
 
         /* SSI */
-        PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
-        PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
-        PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
+        GPIO_FN(SSISCK0),
+        GPIO_FN(SSIWS0),
+        GPIO_FN(SSITXD0),
+        GPIO_FN(SSIRXD0),
+        GPIO_FN(SSIWS1),
+        GPIO_FN(SSIWS2),
+        GPIO_FN(SSIWS3),
+        GPIO_FN(SSISCK1),
+        GPIO_FN(SSISCK2),
+        GPIO_FN(SSISCK3),
+        GPIO_FN(SSIDATA1),
+        GPIO_FN(SSIDATA2),
+        GPIO_FN(SSIDATA3),
+        GPIO_FN(AUDIO_CLK),
 
         /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
-        PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
+        GPIO_FN(SIOFTXD),
+        GPIO_FN(SIOFRXD),
+        GPIO_FN(SIOFSYNC),
+        GPIO_FN(SIOFSCK),
 
         /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
-        PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
-        PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
+        GPIO_FN(SPDIF_IN),
+        GPIO_FN(SPDIF_OUT),
 
         /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
-        PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
-        PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
+        GPIO_FN(FCE),
+        GPIO_FN(FRB),
 
         /* VDC3 */
-        PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
-
-        PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
-
-        PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
-
-        PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
-
-        PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
+        GPIO_FN(DV_CLK),
+        GPIO_FN(DV_VSYNC),
+        GPIO_FN(DV_HSYNC),
+
+        GPIO_FN(DV_DATA7),
+        GPIO_FN(DV_DATA6),
+        GPIO_FN(DV_DATA5),
+        GPIO_FN(DV_DATA4),
+        GPIO_FN(DV_DATA3),
+        GPIO_FN(DV_DATA2),
+        GPIO_FN(DV_DATA1),
+        GPIO_FN(DV_DATA0),
+
+        GPIO_FN(LCD_CLK),
+        GPIO_FN(LCD_EXTCLK),
+        GPIO_FN(LCD_VSYNC),
+        GPIO_FN(LCD_HSYNC),
+        GPIO_FN(LCD_DE),
+
+        GPIO_FN(LCD_DATA15),
+        GPIO_FN(LCD_DATA14),
+        GPIO_FN(LCD_DATA13),
+        GPIO_FN(LCD_DATA12),
+        GPIO_FN(LCD_DATA11),
+        GPIO_FN(LCD_DATA10),
+        GPIO_FN(LCD_DATA9),
+        GPIO_FN(LCD_DATA8),
+        GPIO_FN(LCD_DATA7),
+        GPIO_FN(LCD_DATA6),
+        GPIO_FN(LCD_DATA5),
+        GPIO_FN(LCD_DATA4),
+        GPIO_FN(LCD_DATA3),
+        GPIO_FN(LCD_DATA2),
+        GPIO_FN(LCD_DATA1),
+        GPIO_FN(LCD_DATA0),
+
+        GPIO_FN(LCD_M_DISP),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
                 0, 0, 0, 0, 0, 0, 0, 0,
                 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2032,7 +2036,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         {}
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
                 0, 0, 0, 0, 0, 0, 0, PA3_DATA,
                 0, 0, 0, 0, 0, 0, 0, PA2_DATA }
@@ -2110,19 +2114,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { }
 };
 
-struct sh_pfc_soc_info sh7264_pinmux_info = {
+const struct sh_pfc_soc_info sh7264_pinmux_info = {
         .name = "sh7264_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PA3,
-        .last_gpio = GPIO_FN_LCD_M_DISP,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index b1b5d6d4ad76..4c401a74acd5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -781,7 +781,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
 
         /* Port A */
         PINMUX_DATA(PA1_DATA, PA1_IN),
@@ -1452,7 +1452,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
         /* Port A */
         PINMUX_GPIO(GPIO_PA1, PA1_DATA),
         PINMUX_GPIO(GPIO_PA0, PA0_DATA),
@@ -1613,339 +1613,343 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
         PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
         PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* INTC */
-        PINMUX_GPIO(GPIO_FN_IRQ7_PG, IRQ7_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ6_PG, IRQ6_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ5_PG, IRQ5_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ4_PG, IRQ4_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1_PG, IRQ1_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0_PG, IRQ0_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ7_PF, IRQ7_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ6_PF, IRQ6_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ5_PF, IRQ5_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ4_PF, IRQ4_PF_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3_PJ, IRQ3_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2_PJ, IRQ2_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1_PC, IRQ1_PC_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0_PC, IRQ0_PC_MARK),
-
-        PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT0_PG, PINT0_PG_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT7_PH, PINT7_PH_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT6_PH, PINT6_PH_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT5_PH, PINT5_PH_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT4_PH, PINT4_PH_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT3_PH, PINT3_PH_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT2_PH, PINT2_PH_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT1_PH, PINT1_PH_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT0_PH, PINT0_PH_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT7_PJ, PINT7_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT6_PJ, PINT6_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT5_PJ, PINT5_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT4_PJ, PINT4_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT3_PJ, PINT3_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT2_PJ, PINT2_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT1_PJ, PINT1_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_PINT0_PJ, PINT0_PJ_MARK),
+        GPIO_FN(IRQ7_PG),
+        GPIO_FN(IRQ6_PG),
+        GPIO_FN(IRQ5_PG),
+        GPIO_FN(IRQ4_PG),
+        GPIO_FN(IRQ3_PG),
+        GPIO_FN(IRQ2_PG),
+        GPIO_FN(IRQ1_PG),
+        GPIO_FN(IRQ0_PG),
+        GPIO_FN(IRQ7_PF),
+        GPIO_FN(IRQ6_PF),
+        GPIO_FN(IRQ5_PF),
+        GPIO_FN(IRQ4_PF),
+        GPIO_FN(IRQ3_PJ),
+        GPIO_FN(IRQ2_PJ),
+        GPIO_FN(IRQ1_PJ),
+        GPIO_FN(IRQ0_PJ),
+        GPIO_FN(IRQ1_PC),
+        GPIO_FN(IRQ0_PC),
+
+        GPIO_FN(PINT7_PG),
+        GPIO_FN(PINT6_PG),
+        GPIO_FN(PINT5_PG),
+        GPIO_FN(PINT4_PG),
+        GPIO_FN(PINT3_PG),
+        GPIO_FN(PINT2_PG),
+        GPIO_FN(PINT1_PG),
+        GPIO_FN(PINT0_PG),
+        GPIO_FN(PINT7_PH),
+        GPIO_FN(PINT6_PH),
+        GPIO_FN(PINT5_PH),
+        GPIO_FN(PINT4_PH),
+        GPIO_FN(PINT3_PH),
+        GPIO_FN(PINT2_PH),
+        GPIO_FN(PINT1_PH),
+        GPIO_FN(PINT0_PH),
+        GPIO_FN(PINT7_PJ),
+        GPIO_FN(PINT6_PJ),
+        GPIO_FN(PINT5_PJ),
+        GPIO_FN(PINT4_PJ),
+        GPIO_FN(PINT3_PJ),
+        GPIO_FN(PINT2_PJ),
+        GPIO_FN(PINT1_PJ),
+        GPIO_FN(PINT0_PJ),
 
         /* WDT */
-        PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
+        GPIO_FN(WDTOVF),
 
         /* CAN */
-        PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
-        PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
-        PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
-        PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
-        PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
-        PINMUX_GPIO(GPIO_FN_CRX0_CRX1_CRX2, CRX0_CRX1_CRX2_MARK),
+        GPIO_FN(CTX1),
+        GPIO_FN(CRX1),
+        GPIO_FN(CTX0),
+        GPIO_FN(CRX0),
+        GPIO_FN(CRX0_CRX1),
+        GPIO_FN(CRX0_CRX1_CRX2),
 
         /* DMAC */
-        PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
+        GPIO_FN(TEND0),
+        GPIO_FN(DACK0),
+        GPIO_FN(DREQ0),
+        GPIO_FN(TEND1),
+        GPIO_FN(DACK1),
+        GPIO_FN(DREQ1),
 
         /* ADC */
-        PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
+        GPIO_FN(ADTRG),
 
         /* BSCh */
-        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
-        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
-        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
-        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
-        PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
-        PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
-        PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
-        PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
-        PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
-        PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
-        PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
-        PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
-        PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
-        PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
-        PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
-        PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
-        PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
-        PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
-        PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
-        PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
-        PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
-        PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
-        PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
-        PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
-        PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
-        PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
-
-        PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
-        PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
-        PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
-        PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
-        PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
-        PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
-        PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
-        PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
-        PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
-        PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
-        PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
-        PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
-        PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
-        PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
-        PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
-        PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
-
-        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
-        PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
-        PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
-        PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
-        PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
-        PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
-        PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
-        PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
-        PINMUX_GPIO(GPIO_FN_WE3ICIOWRAHDQMUU, WE3ICIOWRAHDQMUU_MARK),
-        PINMUX_GPIO(GPIO_FN_WE2ICIORDDQMUL, WE2ICIORDDQMUL_MARK),
-        PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
-        PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
-        PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
-        PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
-        PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
-        PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
-        PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
-        PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
-        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
+        GPIO_FN(A25),
+        GPIO_FN(A24),
+        GPIO_FN(A23),
+        GPIO_FN(A22),
+        GPIO_FN(A21),
+        GPIO_FN(A20),
+        GPIO_FN(A19),
+        GPIO_FN(A18),
+        GPIO_FN(A17),
+        GPIO_FN(A16),
+        GPIO_FN(A15),
+        GPIO_FN(A14),
+        GPIO_FN(A13),
+        GPIO_FN(A12),
+        GPIO_FN(A11),
+        GPIO_FN(A10),
+        GPIO_FN(A9),
+        GPIO_FN(A8),
+        GPIO_FN(A7),
+        GPIO_FN(A6),
+        GPIO_FN(A5),
+        GPIO_FN(A4),
+        GPIO_FN(A3),
+        GPIO_FN(A2),
+        GPIO_FN(A1),
+        GPIO_FN(A0),
+
+        GPIO_FN(D15),
+        GPIO_FN(D14),
+        GPIO_FN(D13),
+        GPIO_FN(D12),
+        GPIO_FN(D11),
+        GPIO_FN(D10),
+        GPIO_FN(D9),
+        GPIO_FN(D8),
+        GPIO_FN(D7),
+        GPIO_FN(D6),
+        GPIO_FN(D5),
+        GPIO_FN(D4),
+        GPIO_FN(D3),
+        GPIO_FN(D2),
+        GPIO_FN(D1),
+        GPIO_FN(D0),
+
+        GPIO_FN(BS),
+        GPIO_FN(CS4),
+        GPIO_FN(CS3),
+        GPIO_FN(CS2),
+        GPIO_FN(CS1),
+        GPIO_FN(CS0),
+        GPIO_FN(CS5CE1A),
+        GPIO_FN(CE2A),
+        GPIO_FN(CE2B),
+        GPIO_FN(RD),
+        GPIO_FN(RDWR),
+        GPIO_FN(WE3ICIOWRAHDQMUU),
+        GPIO_FN(WE2ICIORDDQMUL),
+        GPIO_FN(WE1DQMUWE),
+        GPIO_FN(WE0DQML),
+        GPIO_FN(RAS),
+        GPIO_FN(CAS),
+        GPIO_FN(CKE),
+        GPIO_FN(WAIT),
+        GPIO_FN(BREQ),
+        GPIO_FN(BACK),
+        GPIO_FN(IOIS16),
 
         /* TMU */
-        PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
-        PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
+        GPIO_FN(TIOC4D),
+        GPIO_FN(TIOC4C),
+        GPIO_FN(TIOC4B),
+        GPIO_FN(TIOC4A),
+        GPIO_FN(TIOC3D),
+        GPIO_FN(TIOC3C),
+        GPIO_FN(TIOC3B),
+        GPIO_FN(TIOC3A),
+        GPIO_FN(TIOC2B),
+        GPIO_FN(TIOC1B),
+        GPIO_FN(TIOC2A),
+        GPIO_FN(TIOC1A),
+        GPIO_FN(TIOC0D),
+        GPIO_FN(TIOC0C),
+        GPIO_FN(TIOC0B),
+        GPIO_FN(TIOC0A),
+        GPIO_FN(TCLKD),
+        GPIO_FN(TCLKC),
+        GPIO_FN(TCLKB),
+        GPIO_FN(TCLKA),
 
         /* SCIF */
-        PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK5, SCK5_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS5, RTS5_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS5, CTS5_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK6, SCK6_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK7, SCK7_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS7, RTS7_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS7, CTS7_MARK),
+        GPIO_FN(SCK0),
+        GPIO_FN(TXD0),
+        GPIO_FN(RXD0),
+        GPIO_FN(SCK1),
+        GPIO_FN(TXD1),
+        GPIO_FN(RXD1),
+        GPIO_FN(RTS1),
+        GPIO_FN(CTS1),
+        GPIO_FN(SCK2),
+        GPIO_FN(TXD2),
+        GPIO_FN(RXD2),
+        GPIO_FN(SCK3),
+        GPIO_FN(TXD3),
+        GPIO_FN(RXD3),
+        GPIO_FN(SCK4),
+        GPIO_FN(TXD4),
+        GPIO_FN(RXD4),
+        GPIO_FN(SCK5),
+        GPIO_FN(TXD5),
+        GPIO_FN(RXD5),
+        GPIO_FN(RTS5),
+        GPIO_FN(CTS5),
+        GPIO_FN(SCK6),
+        GPIO_FN(TXD6),
+        GPIO_FN(RXD6),
+        GPIO_FN(SCK7),
+        GPIO_FN(TXD7),
+        GPIO_FN(RXD7),
+        GPIO_FN(RTS7),
+        GPIO_FN(CTS7),
 
         /* RSPI */
-        PINMUX_GPIO(GPIO_FN_RSPCK0_PJ16, RSPCK0_PJ16_MARK),
-        PINMUX_GPIO(GPIO_FN_SSL00_PJ17, SSL00_PJ17_MARK),
-        PINMUX_GPIO(GPIO_FN_MOSI0_PJ18, MOSI0_PJ18_MARK),
-        PINMUX_GPIO(GPIO_FN_MISO0_PJ19, MISO0_PJ19_MARK),
-        PINMUX_GPIO(GPIO_FN_RSPCK0_PB17, RSPCK0_PB17_MARK),
-        PINMUX_GPIO(GPIO_FN_SSL00_PB18, SSL00_PB18_MARK),
-        PINMUX_GPIO(GPIO_FN_MOSI0_PB19, MOSI0_PB19_MARK),
-        PINMUX_GPIO(GPIO_FN_MISO0_PB20, MISO0_PB20_MARK),
-        PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
-        PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
-        PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
+        GPIO_FN(RSPCK0_PJ16),
+        GPIO_FN(SSL00_PJ17),
+        GPIO_FN(MOSI0_PJ18),
+        GPIO_FN(MISO0_PJ19),
+        GPIO_FN(RSPCK0_PB17),
+        GPIO_FN(SSL00_PB18),
+        GPIO_FN(MOSI0_PB19),
+        GPIO_FN(MISO0_PB20),
+        GPIO_FN(RSPCK1),
+        GPIO_FN(MOSI1),
+        GPIO_FN(MISO1),
+        GPIO_FN(SSL10),
 
         /* IIC3 */
-        PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
+        GPIO_FN(SCL0),
+        GPIO_FN(SCL1),
+        GPIO_FN(SCL2),
+        GPIO_FN(SDA0),
+        GPIO_FN(SDA1),
+        GPIO_FN(SDA2),
 
         /* SSI */
-        PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
-        PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
-        PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDIO_XOUT, AUDIO_XOUT_MARK),
+        GPIO_FN(SSISCK0),
+        GPIO_FN(SSIWS0),
+        GPIO_FN(SSITXD0),
+        GPIO_FN(SSIRXD0),
+        GPIO_FN(SSIWS1),
+        GPIO_FN(SSIWS2),
+        GPIO_FN(SSIWS3),
+        GPIO_FN(SSISCK1),
+        GPIO_FN(SSISCK2),
+        GPIO_FN(SSISCK3),
+        GPIO_FN(SSIDATA1),
+        GPIO_FN(SSIDATA2),
+        GPIO_FN(SSIDATA3),
+        GPIO_FN(AUDIO_CLK),
+        GPIO_FN(AUDIO_XOUT),
 
         /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
-        PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
+        GPIO_FN(SIOFTXD),
+        GPIO_FN(SIOFRXD),
+        GPIO_FN(SIOFSYNC),
+        GPIO_FN(SIOFSCK),
 
         /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
-        PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
-        PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
+        GPIO_FN(SPDIF_IN),
+        GPIO_FN(SPDIF_OUT),
 
         /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
-        PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
-        PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
+        GPIO_FN(FCE),
+        GPIO_FN(FRB),
 
         /* VDC3 */
-        PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
-
-        PINMUX_GPIO(GPIO_FN_DV_DATA23, DV_DATA23_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA22, DV_DATA22_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA21, DV_DATA21_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA20, DV_DATA20_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA19, DV_DATA19_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA18, DV_DATA18_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA17, DV_DATA17_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA16, DV_DATA16_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA15, DV_DATA15_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA14, DV_DATA14_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA13, DV_DATA13_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA12, DV_DATA12_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA11, DV_DATA11_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA10, DV_DATA10_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA9, DV_DATA9_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA8, DV_DATA8_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
-
-        PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
-
-        PINMUX_GPIO(GPIO_FN_LCD_DATA23_PG23, LCD_DATA23_PG23_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA22_PG22, LCD_DATA22_PG22_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA21_PG21, LCD_DATA21_PG21_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA20_PG20, LCD_DATA20_PG20_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA19_PG19, LCD_DATA19_PG19_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA18_PG18, LCD_DATA18_PG18_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA17_PG17, LCD_DATA17_PG17_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA16_PG16, LCD_DATA16_PG16_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA15_PG15, LCD_DATA15_PG15_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA14_PG14, LCD_DATA14_PG14_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA13_PG13, LCD_DATA13_PG13_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA12_PG12, LCD_DATA12_PG12_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA11_PG11, LCD_DATA11_PG11_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA10_PG10, LCD_DATA10_PG10_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA9_PG9, LCD_DATA9_PG9_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA8_PG8, LCD_DATA8_PG8_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA7_PG7, LCD_DATA7_PG7_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA6_PG6, LCD_DATA6_PG6_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA5_PG5, LCD_DATA5_PG5_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA4_PG4, LCD_DATA4_PG4_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA3_PG3, LCD_DATA3_PG3_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA2_PG2, LCD_DATA2_PG2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA1_PG1, LCD_DATA1_PG1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA0_PG0, LCD_DATA0_PG0_MARK),
-
-        PINMUX_GPIO(GPIO_FN_LCD_DATA23_PJ23, LCD_DATA23_PJ23_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA22_PJ22, LCD_DATA22_PJ22_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA21_PJ21, LCD_DATA21_PJ21_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA20_PJ20, LCD_DATA20_PJ20_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA19_PJ19, LCD_DATA19_PJ19_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA18_PJ18, LCD_DATA18_PJ18_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA17_PJ17, LCD_DATA17_PJ17_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA16_PJ16, LCD_DATA16_PJ16_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA15_PJ15, LCD_DATA15_PJ15_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA14_PJ14, LCD_DATA14_PJ14_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA13_PJ13, LCD_DATA13_PJ13_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA12_PJ12, LCD_DATA12_PJ12_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA11_PJ11, LCD_DATA11_PJ11_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA10_PJ10, LCD_DATA10_PJ10_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA9_PJ9, LCD_DATA9_PJ9_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA8_PJ8, LCD_DATA8_PJ8_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA7_PJ7, LCD_DATA7_PJ7_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA6_PJ6, LCD_DATA6_PJ6_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA5_PJ5, LCD_DATA5_PJ5_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA4_PJ4, LCD_DATA4_PJ4_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA3_PJ3, LCD_DATA3_PJ3_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA2_PJ2, LCD_DATA2_PJ2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA1_PJ1, LCD_DATA1_PJ1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA0_PJ0, LCD_DATA0_PJ0_MARK),
-
-        PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
+        GPIO_FN(DV_CLK),
+        GPIO_FN(DV_VSYNC),
+        GPIO_FN(DV_HSYNC),
+
+        GPIO_FN(DV_DATA23),
+        GPIO_FN(DV_DATA22),
+        GPIO_FN(DV_DATA21),
+        GPIO_FN(DV_DATA20),
+        GPIO_FN(DV_DATA19),
+        GPIO_FN(DV_DATA18),
+        GPIO_FN(DV_DATA17),
+        GPIO_FN(DV_DATA16),
+        GPIO_FN(DV_DATA15),
+        GPIO_FN(DV_DATA14),
+        GPIO_FN(DV_DATA13),
+        GPIO_FN(DV_DATA12),
+        GPIO_FN(DV_DATA11),
+        GPIO_FN(DV_DATA10),
+        GPIO_FN(DV_DATA9),
+        GPIO_FN(DV_DATA8),
+        GPIO_FN(DV_DATA7),
+        GPIO_FN(DV_DATA6),
+        GPIO_FN(DV_DATA5),
+        GPIO_FN(DV_DATA4),
+        GPIO_FN(DV_DATA3),
+        GPIO_FN(DV_DATA2),
+        GPIO_FN(DV_DATA1),
+        GPIO_FN(DV_DATA0),
+
+        GPIO_FN(LCD_CLK),
+        GPIO_FN(LCD_EXTCLK),
+        GPIO_FN(LCD_VSYNC),
+        GPIO_FN(LCD_HSYNC),
+        GPIO_FN(LCD_DE),
+
+        GPIO_FN(LCD_DATA23_PG23),
+        GPIO_FN(LCD_DATA22_PG22),
+        GPIO_FN(LCD_DATA21_PG21),
+        GPIO_FN(LCD_DATA20_PG20),
+        GPIO_FN(LCD_DATA19_PG19),
+        GPIO_FN(LCD_DATA18_PG18),
+        GPIO_FN(LCD_DATA17_PG17),
+        GPIO_FN(LCD_DATA16_PG16),
+        GPIO_FN(LCD_DATA15_PG15),
+        GPIO_FN(LCD_DATA14_PG14),
+        GPIO_FN(LCD_DATA13_PG13),
+        GPIO_FN(LCD_DATA12_PG12),
+        GPIO_FN(LCD_DATA11_PG11),
+        GPIO_FN(LCD_DATA10_PG10),
+        GPIO_FN(LCD_DATA9_PG9),
+        GPIO_FN(LCD_DATA8_PG8),
+        GPIO_FN(LCD_DATA7_PG7),
+        GPIO_FN(LCD_DATA6_PG6),
+        GPIO_FN(LCD_DATA5_PG5),
+        GPIO_FN(LCD_DATA4_PG4),
+        GPIO_FN(LCD_DATA3_PG3),
+        GPIO_FN(LCD_DATA2_PG2),
+        GPIO_FN(LCD_DATA1_PG1),
+        GPIO_FN(LCD_DATA0_PG0),
+
+        GPIO_FN(LCD_DATA23_PJ23),
+        GPIO_FN(LCD_DATA22_PJ22),
+        GPIO_FN(LCD_DATA21_PJ21),
+        GPIO_FN(LCD_DATA20_PJ20),
+        GPIO_FN(LCD_DATA19_PJ19),
+        GPIO_FN(LCD_DATA18_PJ18),
+        GPIO_FN(LCD_DATA17_PJ17),
+        GPIO_FN(LCD_DATA16_PJ16),
+        GPIO_FN(LCD_DATA15_PJ15),
+        GPIO_FN(LCD_DATA14_PJ14),
+        GPIO_FN(LCD_DATA13_PJ13),
+        GPIO_FN(LCD_DATA12_PJ12),
+        GPIO_FN(LCD_DATA11_PJ11),
+        GPIO_FN(LCD_DATA10_PJ10),
+        GPIO_FN(LCD_DATA9_PJ9),
+        GPIO_FN(LCD_DATA8_PJ8),
+        GPIO_FN(LCD_DATA7_PJ7),
+        GPIO_FN(LCD_DATA6_PJ6),
+        GPIO_FN(LCD_DATA5_PJ5),
+        GPIO_FN(LCD_DATA4_PJ4),
+        GPIO_FN(LCD_DATA3_PJ3),
+        GPIO_FN(LCD_DATA2_PJ2),
+        GPIO_FN(LCD_DATA1_PJ1),
+        GPIO_FN(LCD_DATA0_PJ0),
+
+        GPIO_FN(LCD_M_DISP),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         /* "name" addr register_size Field_Width */
 
         /* where Field_Width is 1 for single mode registers or 4 for upto 16
@@ -2734,7 +2738,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         {}
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
                 0, 0, 0, 0, 0, 0, 0, PA1_DATA,
                 0, 0, 0, 0, 0, 0, 0, PA0_DATA }
@@ -2813,19 +2817,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { }
 };
 
-struct sh_pfc_soc_info sh7269_pinmux_info = {
+const struct sh_pfc_soc_info sh7269_pinmux_info = {
         .name = "sh7269_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PA1,
-        .last_gpio = GPIO_FN_LCD_M_DISP,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index d44e7f02069b..df0ae21a5ac8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -368,7 +368,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
 
         /* specify valid pin states for each pin in GPIO mode */
         PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
@@ -929,11 +929,214 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(MFIv4_MARK,         MSEL4CR_6_1),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
-
-        /* PORT */
+static struct sh_pfc_pin pinmux_pins[] = {
         GPIO_PORT_ALL(),
+};
 
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_0_pins[] = {
+        /* D[0] */
+        84,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+        MMCD0_0_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+        /* D[0:3] */
+        84, 85, 86, 87,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+        MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+        /* D[0:7] */
+        84, 85, 86, 87, 88, 89, 90, 91,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+        MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+        MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+        /* CMD, CLK */
+        92, 99,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+        MMCCMD0_MARK, MMCCLK0_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+        /* D[0] */
+        54,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+        MMCD1_0_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+        /* D[0:3] */
+        54, 55, 56, 57,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+        MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+        /* D[0:7] */
+        54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+        MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+        MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+        /* CMD, CLK */
+        67, 66,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+        MMCCMD1_MARK, MMCCLK1_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+        /* D0 */
+        173,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+        SDHID0_0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+        /* D[0:3] */
+        173, 174, 175, 176,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+        SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+        /* CMD, CLK */
+        177, 171,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+        SDHICMD0_MARK, SDHICLK0_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+        /* CD */
+        172,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+        SDHICD0_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+        /* WP */
+        178,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+        SDHIWP0_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+        /* D0 */
+        180,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+        SDHID1_0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+        /* D[0:3] */
+        180, 181, 182, 183,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+        SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+        /* CMD, CLK */
+        184, 179,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+        SDHICMD1_MARK, SDHICLK1_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+        /* D0 */
+        186,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+        SDHID2_0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+        /* D[0:3] */
+        186, 187, 188, 189,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+        SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+        /* CMD, CLK */
+        190, 185,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+        SDHICMD2_MARK, SDHICLK2_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(mmc0_data1_0),
+        SH_PFC_PIN_GROUP(mmc0_data4_0),
+        SH_PFC_PIN_GROUP(mmc0_data8_0),
+        SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+        SH_PFC_PIN_GROUP(mmc0_data1_1),
+        SH_PFC_PIN_GROUP(mmc0_data4_1),
+        SH_PFC_PIN_GROUP(mmc0_data8_1),
+        SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_data1),
+        SH_PFC_PIN_GROUP(sdhi1_data4),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi2_data1),
+        SH_PFC_PIN_GROUP(sdhi2_data4),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl),
+};
+
+static const char * const mmc0_groups[] = {
+        "mmc0_data1_0",
+        "mmc0_data4_0",
+        "mmc0_data8_0",
+        "mmc0_ctrl_0",
+        "mmc0_data1_1",
+        "mmc0_data4_1",
+        "mmc0_data8_1",
+        "mmc0_ctrl_1",
+};
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_ctrl",
+        "sdhi0_cd",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_data1",
+        "sdhi1_data4",
+        "sdhi1_ctrl",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_data1",
+        "sdhi2_data4",
+        "sdhi2_ctrl",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
+
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* IRQ */
         GPIO_FN(IRQ0_6),        GPIO_FN(IRQ0_162),      GPIO_FN(IRQ1),
         GPIO_FN(IRQ2_4),        GPIO_FN(IRQ2_5),        GPIO_FN(IRQ3_8),
@@ -1074,18 +1277,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(D11_NAF11),     GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),
         GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),
 
-        /* MMCIF(1) */
-        GPIO_FN(MMCD0_0),       GPIO_FN(MMCD0_1),       GPIO_FN(MMCD0_2),
-        GPIO_FN(MMCD0_3),       GPIO_FN(MMCD0_4),       GPIO_FN(MMCD0_5),
-        GPIO_FN(MMCD0_6),       GPIO_FN(MMCD0_7),       GPIO_FN(MMCCMD0),
-        GPIO_FN(MMCCLK0),
-
-        /* MMCIF(2) */
-        GPIO_FN(MMCD1_0),       GPIO_FN(MMCD1_1),       GPIO_FN(MMCD1_2),
-        GPIO_FN(MMCD1_3),       GPIO_FN(MMCD1_4),       GPIO_FN(MMCD1_5),
-        GPIO_FN(MMCD1_6),       GPIO_FN(MMCD1_7),       GPIO_FN(MMCCLK1),
-        GPIO_FN(MMCCMD1),
-
         /* SPU2 */
         GPIO_FN(VINT_I),
 
@@ -1182,25 +1373,12 @@ static struct pinmux_gpio pinmux_gpios[] = {
         /* HDMI */
         GPIO_FN(HDMI_HPD),      GPIO_FN(HDMI_CEC),
 
-        /* SDHI0 */
-        GPIO_FN(SDHICLK0),      GPIO_FN(SDHICD0),       GPIO_FN(SDHICMD0),
-        GPIO_FN(SDHIWP0),       GPIO_FN(SDHID0_0),      GPIO_FN(SDHID0_1),
-        GPIO_FN(SDHID0_2),      GPIO_FN(SDHID0_3),
-
-        /* SDHI1 */
-        GPIO_FN(SDHICLK1),      GPIO_FN(SDHICMD1),      GPIO_FN(SDHID1_0),
-        GPIO_FN(SDHID1_1),      GPIO_FN(SDHID1_2),      GPIO_FN(SDHID1_3),
-
-        /* SDHI2 */
-        GPIO_FN(SDHICLK2),      GPIO_FN(SDHICMD2),      GPIO_FN(SDHID2_0),
-        GPIO_FN(SDHID2_1),      GPIO_FN(SDHID2_2),      GPIO_FN(SDHID2_3),
-
         /* SDENC */
         GPIO_FN(SDENC_CPG),
         GPIO_FN(SDENC_DV_CLKI),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0,       0xE6051000), /* PORT0CR */
         PORTCR(1,       0xE6051001), /* PORT1CR */
         PORTCR(2,       0xE6051002), /* PORT2CR */
@@ -1472,7 +1650,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         { },
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
                         PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
                         PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
@@ -1597,56 +1775,59 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
 
 #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
 #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
-static struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0),
+static const struct pinmux_irq pinmux_irqs[] = {
+        PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
+        PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
+        PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
+        PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
+        PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
+        PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
+        PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
+        PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
+        PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
+        PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
+        PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
+        PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
+        PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
+        PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
+        PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
+        PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
+        PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
+        PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
+        PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
+        PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
+        PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
+        PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
+        PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
+        PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
+        PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
+        PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
+        PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
+        PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
+        PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
+        PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
+        PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
+        PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
 };
 
-struct sh_pfc_soc_info sh7372_pinmux_info = {
+const struct sh_pfc_soc_info sh7372_pinmux_info = {
         .name = "sh7372_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
         .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
         .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PORT0,
-        .last_gpio = GPIO_FN_SDENC_DV_CLKI,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 709008e94124..cde4387edce1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -18,18 +18,18 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/sh73a0.h>
 #include <mach/irqs.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        PORT_10(fn, pfx,    sfx), PORT_10(fn, pfx##1, sfx),     \
-        PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx),     \
-        PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx),     \
-        PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx),     \
-        PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx),     \
+        PORT_10(fn, pfx,    sfx), PORT_90(fn, pfx, sfx),        \
         PORT_10(fn, pfx##10, sfx),                              \
         PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx),   \
         PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx),   \
@@ -66,14 +66,6 @@ enum {
         PORT_ALL(IN),                   /* PORT0_IN -> PORT309_IN */
         PINMUX_INPUT_END,
 
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),                /* PORT0_IN_PU -> PORT309_IN_PU */
-        PINMUX_INPUT_PULLUP_END,
-
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),                /* PORT0_IN_PD -> PORT309_IN_PD */
-        PINMUX_INPUT_PULLDOWN_END,
-
         PINMUX_OUTPUT_BEGIN,
         PORT_ALL(OUT),                  /* PORT0_OUT -> PORT309_OUT */
         PINMUX_OUTPUT_END,
@@ -468,328 +460,15 @@ enum {
         EDBGREQ_PD_MARK,
         EDBGREQ_PU_MARK,
 
-        /* Functions with pull-ups */
-        KEYIN0_PU_MARK,
-        KEYIN1_PU_MARK,
-        KEYIN2_PU_MARK,
-        KEYIN3_PU_MARK,
-        KEYIN4_PU_MARK,
-        KEYIN5_PU_MARK,
-        KEYIN6_PU_MARK,
-        KEYIN7_PU_MARK,
-        SDHICD0_PU_MARK,
-        SDHID0_0_PU_MARK,
-        SDHID0_1_PU_MARK,
-        SDHID0_2_PU_MARK,
-        SDHID0_3_PU_MARK,
-        SDHICMD0_PU_MARK,
-        SDHIWP0_PU_MARK,
-        SDHID1_0_PU_MARK,
-        SDHID1_1_PU_MARK,
-        SDHID1_2_PU_MARK,
-        SDHID1_3_PU_MARK,
-        SDHICMD1_PU_MARK,
-        SDHID2_0_PU_MARK,
-        SDHID2_1_PU_MARK,
-        SDHID2_2_PU_MARK,
-        SDHID2_3_PU_MARK,
-        SDHICMD2_PU_MARK,
-        MMCCMD0_PU_MARK,
-        MMCCMD1_PU_MARK,
-        MMCD0_0_PU_MARK,
-        MMCD0_1_PU_MARK,
-        MMCD0_2_PU_MARK,
-        MMCD0_3_PU_MARK,
-        MMCD0_4_PU_MARK,
-        MMCD0_5_PU_MARK,
-        MMCD0_6_PU_MARK,
-        MMCD0_7_PU_MARK,
-        FSIBISLD_PU_MARK,
-        FSIACK_PU_MARK,
-        FSIAILR_PU_MARK,
-        FSIAIBT_PU_MARK,
-        FSIAISLD_PU_MARK,
-
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
+#define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
 
-        /* Table 25-1 (I/O and Pull U/D) */
-        PORT_DATA_I_PD(0),
-        PORT_DATA_I_PU(1),
-        PORT_DATA_I_PU(2),
-        PORT_DATA_I_PU(3),
-        PORT_DATA_I_PU(4),
-        PORT_DATA_I_PU(5),
-        PORT_DATA_I_PU(6),
-        PORT_DATA_I_PU(7),
-        PORT_DATA_I_PU(8),
-        PORT_DATA_I_PD(9),
-        PORT_DATA_I_PD(10),
-        PORT_DATA_I_PU_PD(11),
-        PORT_DATA_IO_PU_PD(12),
-        PORT_DATA_IO_PU_PD(13),
-        PORT_DATA_IO_PU_PD(14),
-        PORT_DATA_IO_PU_PD(15),
-        PORT_DATA_IO_PD(16),
-        PORT_DATA_IO_PD(17),
-        PORT_DATA_IO_PU(18),
-        PORT_DATA_IO_PU(19),
-        PORT_DATA_O(20),
-        PORT_DATA_O(21),
-        PORT_DATA_O(22),
-        PORT_DATA_O(23),
-        PORT_DATA_O(24),
-        PORT_DATA_I_PD(25),
-        PORT_DATA_I_PD(26),
-        PORT_DATA_IO_PU(27),
-        PORT_DATA_IO_PU(28),
-        PORT_DATA_IO_PD(29),
-        PORT_DATA_IO_PD(30),
-        PORT_DATA_IO_PU(31),
-        PORT_DATA_IO_PD(32),
-        PORT_DATA_I_PU_PD(33),
-        PORT_DATA_IO_PD(34),
-        PORT_DATA_I_PU_PD(35),
-        PORT_DATA_IO_PD(36),
-        PORT_DATA_IO(37),
-        PORT_DATA_O(38),
-        PORT_DATA_I_PU(39),
-        PORT_DATA_I_PU_PD(40),
-        PORT_DATA_O(41),
-        PORT_DATA_IO_PD(42),
-        PORT_DATA_IO_PU_PD(43),
-        PORT_DATA_IO_PU_PD(44),
-        PORT_DATA_IO_PD(45),
-        PORT_DATA_IO_PD(46),
-        PORT_DATA_IO_PD(47),
-        PORT_DATA_I_PD(48),
-        PORT_DATA_IO_PU_PD(49),
-        PORT_DATA_IO_PD(50),
-
-        PORT_DATA_IO_PD(51),
-        PORT_DATA_O(52),
-        PORT_DATA_IO_PU_PD(53),
-        PORT_DATA_IO_PU_PD(54),
-        PORT_DATA_IO_PD(55),
-        PORT_DATA_I_PU_PD(56),
-        PORT_DATA_IO(57),
-        PORT_DATA_IO(58),
-        PORT_DATA_IO(59),
-        PORT_DATA_IO(60),
-        PORT_DATA_IO(61),
-        PORT_DATA_IO_PD(62),
-        PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PU_PD(64),
-        PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66),
-        PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68),
-        PORT_DATA_IO_PU_PD(69),
-        PORT_DATA_IO_PU_PD(70),
-        PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72),
-        PORT_DATA_I_PU_PD(73),
-        PORT_DATA_IO_PU(74),
-        PORT_DATA_IO_PU(75),
-        PORT_DATA_IO_PU(76),
-        PORT_DATA_IO_PU(77),
-        PORT_DATA_IO_PU(78),
-        PORT_DATA_IO_PU(79),
-        PORT_DATA_IO_PU(80),
-        PORT_DATA_IO_PU(81),
-        PORT_DATA_IO_PU(82),
-        PORT_DATA_IO_PU(83),
-        PORT_DATA_IO_PU(84),
-        PORT_DATA_IO_PU(85),
-        PORT_DATA_IO_PU(86),
-        PORT_DATA_IO_PU(87),
-        PORT_DATA_IO_PU(88),
-        PORT_DATA_IO_PU(89),
-        PORT_DATA_O(90),
-        PORT_DATA_IO_PU(91),
-        PORT_DATA_O(92),
-        PORT_DATA_IO_PU(93),
-        PORT_DATA_O(94),
-        PORT_DATA_I_PU_PD(95),
-        PORT_DATA_IO(96),
-        PORT_DATA_IO(97),
-        PORT_DATA_IO(98),
-        PORT_DATA_I_PU(99),
-        PORT_DATA_O(100),
-        PORT_DATA_O(101),
-        PORT_DATA_I_PU(102),
-        PORT_DATA_IO_PD(103),
-        PORT_DATA_I_PU_PD(104),
-        PORT_DATA_I_PD(105),
-        PORT_DATA_I_PD(106),
-        PORT_DATA_I_PU_PD(107),
-        PORT_DATA_I_PU_PD(108),
-        PORT_DATA_IO_PD(109),
-        PORT_DATA_IO_PD(110),
-        PORT_DATA_IO_PU_PD(111),
-        PORT_DATA_IO_PU_PD(112),
-        PORT_DATA_IO_PU_PD(113),
-        PORT_DATA_IO_PD(114),
-        PORT_DATA_IO_PU(115),
-        PORT_DATA_IO_PU(116),
-        PORT_DATA_IO_PU_PD(117),
-        PORT_DATA_IO_PU_PD(118),
-        PORT_DATA_IO_PD(128),
-
-        PORT_DATA_IO_PD(129),
-        PORT_DATA_IO_PU_PD(130),
-        PORT_DATA_IO_PD(131),
-        PORT_DATA_IO_PD(132),
-        PORT_DATA_IO_PD(133),
-        PORT_DATA_IO_PU_PD(134),
-        PORT_DATA_IO_PU_PD(135),
-        PORT_DATA_IO_PU_PD(136),
-        PORT_DATA_IO_PU_PD(137),
-        PORT_DATA_IO_PD(138),
-        PORT_DATA_IO_PD(139),
-        PORT_DATA_IO_PD(140),
-        PORT_DATA_IO_PD(141),
-        PORT_DATA_IO_PD(142),
-        PORT_DATA_IO_PD(143),
-        PORT_DATA_IO_PU_PD(144),
-        PORT_DATA_IO_PD(145),
-        PORT_DATA_IO_PU_PD(146),
-        PORT_DATA_IO_PU_PD(147),
-        PORT_DATA_IO_PU_PD(148),
-        PORT_DATA_IO_PU_PD(149),
-        PORT_DATA_I_PU_PD(150),
-        PORT_DATA_IO_PU_PD(151),
-        PORT_DATA_IO_PU_PD(152),
-        PORT_DATA_IO_PD(153),
-        PORT_DATA_IO_PD(154),
-        PORT_DATA_I_PU_PD(155),
-        PORT_DATA_IO_PU_PD(156),
-        PORT_DATA_I_PD(157),
-        PORT_DATA_IO_PD(158),
-        PORT_DATA_IO_PU_PD(159),
-        PORT_DATA_IO_PU_PD(160),
-        PORT_DATA_I_PU_PD(161),
-        PORT_DATA_I_PU_PD(162),
-        PORT_DATA_IO_PU_PD(163),
-        PORT_DATA_I_PU_PD(164),
-        PORT_DATA_IO_PD(192),
-        PORT_DATA_IO_PU_PD(193),
-        PORT_DATA_IO_PD(194),
-        PORT_DATA_IO_PU_PD(195),
-        PORT_DATA_IO_PD(196),
-        PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PD(198),
-        PORT_DATA_IO_PD(199),
-        PORT_DATA_IO_PU_PD(200),
-        PORT_DATA_IO_PU_PD(201),
-        PORT_DATA_IO_PU_PD(202),
-        PORT_DATA_IO_PU_PD(203),
-        PORT_DATA_IO_PU_PD(204),
-        PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206),
-        PORT_DATA_IO_PD(207),
-        PORT_DATA_IO_PD(208),
-        PORT_DATA_IO_PD(209),
-        PORT_DATA_IO_PD(210),
-        PORT_DATA_IO_PD(211),
-        PORT_DATA_IO_PD(212),
-        PORT_DATA_IO_PD(213),
-        PORT_DATA_IO_PU_PD(214),
-        PORT_DATA_IO_PU_PD(215),
-        PORT_DATA_IO_PD(216),
-        PORT_DATA_IO_PD(217),
-        PORT_DATA_O(218),
-        PORT_DATA_IO_PD(219),
-        PORT_DATA_IO_PD(220),
-        PORT_DATA_IO_PU_PD(221),
-        PORT_DATA_IO_PU_PD(222),
-        PORT_DATA_I_PU_PD(223),
-        PORT_DATA_I_PU_PD(224),
-
-        PORT_DATA_IO_PU_PD(225),
-        PORT_DATA_O(226),
-        PORT_DATA_IO_PU_PD(227),
-        PORT_DATA_I_PU_PD(228),
-        PORT_DATA_I_PD(229),
-        PORT_DATA_IO(230),
-        PORT_DATA_IO_PU_PD(231),
-        PORT_DATA_IO_PU_PD(232),
-        PORT_DATA_I_PU_PD(233),
-        PORT_DATA_IO_PU_PD(234),
-        PORT_DATA_IO_PU_PD(235),
-        PORT_DATA_IO_PU_PD(236),
-        PORT_DATA_IO_PD(237),
-        PORT_DATA_IO_PU_PD(238),
-        PORT_DATA_IO_PU_PD(239),
-        PORT_DATA_IO_PU_PD(240),
-        PORT_DATA_O(241),
-        PORT_DATA_I_PD(242),
-        PORT_DATA_IO_PU_PD(243),
-        PORT_DATA_IO_PU_PD(244),
-        PORT_DATA_IO_PU_PD(245),
-        PORT_DATA_IO_PU_PD(246),
-        PORT_DATA_IO_PU_PD(247),
-        PORT_DATA_IO_PU_PD(248),
-        PORT_DATA_IO_PU_PD(249),
-        PORT_DATA_IO_PU_PD(250),
-        PORT_DATA_IO_PU_PD(251),
-        PORT_DATA_IO_PU_PD(252),
-        PORT_DATA_IO_PU_PD(253),
-        PORT_DATA_IO_PU_PD(254),
-        PORT_DATA_IO_PU_PD(255),
-        PORT_DATA_IO_PU_PD(256),
-        PORT_DATA_IO_PU_PD(257),
-        PORT_DATA_IO_PU_PD(258),
-        PORT_DATA_IO_PU_PD(259),
-        PORT_DATA_IO_PU_PD(260),
-        PORT_DATA_IO_PU_PD(261),
-        PORT_DATA_IO_PU_PD(262),
-        PORT_DATA_IO_PU_PD(263),
-        PORT_DATA_IO_PU_PD(264),
-        PORT_DATA_IO_PU_PD(265),
-        PORT_DATA_IO_PU_PD(266),
-        PORT_DATA_IO_PU_PD(267),
-        PORT_DATA_IO_PU_PD(268),
-        PORT_DATA_IO_PU_PD(269),
-        PORT_DATA_IO_PU_PD(270),
-        PORT_DATA_IO_PU_PD(271),
-        PORT_DATA_IO_PU_PD(272),
-        PORT_DATA_IO_PU_PD(273),
-        PORT_DATA_IO_PU_PD(274),
-        PORT_DATA_IO_PU_PD(275),
-        PORT_DATA_IO_PU_PD(276),
-        PORT_DATA_IO_PU_PD(277),
-        PORT_DATA_IO_PU_PD(278),
-        PORT_DATA_IO_PU_PD(279),
-        PORT_DATA_IO_PU_PD(280),
-        PORT_DATA_O(281),
-        PORT_DATA_O(282),
-        PORT_DATA_I_PU(288),
-        PORT_DATA_IO_PU_PD(289),
-        PORT_DATA_IO_PU_PD(290),
-        PORT_DATA_IO_PU_PD(291),
-        PORT_DATA_IO_PU_PD(292),
-        PORT_DATA_IO_PU_PD(293),
-        PORT_DATA_IO_PU_PD(294),
-        PORT_DATA_IO_PU_PD(295),
-        PORT_DATA_IO_PU_PD(296),
-        PORT_DATA_IO_PU_PD(297),
-        PORT_DATA_IO_PU_PD(298),
-
-        PORT_DATA_IO_PU_PD(299),
-        PORT_DATA_IO_PU_PD(300),
-        PORT_DATA_IO_PU_PD(301),
-        PORT_DATA_IO_PU_PD(302),
-        PORT_DATA_IO_PU_PD(303),
-        PORT_DATA_IO_PU_PD(304),
-        PORT_DATA_IO_PU_PD(305),
-        PORT_DATA_O(306),
-        PORT_DATA_O(307),
-        PORT_DATA_I_PU(308),
-        PORT_DATA_O(309),
+static const pinmux_enum_t pinmux_data[] = {
+        /* specify valid pin states for each pin in GPIO mode */
+        PINMUX_DATA_GP_ALL(),
 
         /* Table 25-1 (Function 0-7) */
         PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
@@ -1358,28 +1037,19 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
         PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
         PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
-                MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
         PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
-        PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
-                MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
         PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
-        PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
-                MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
         PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
-        PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
-                MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
         PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
-        PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
-                MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
         PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
         PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
         PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
@@ -1485,69 +1155,1791 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
         PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
         PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
+};
+
+#define SH73A0_PIN(pin, cfgs)                                           \
+        {                                                               \
+                .name = __stringify(PORT##pin),                         \
+                .enum_id = PORT##pin##_DATA,                            \
+                .configs = cfgs,                                        \
+        }
+
+#define __I             (SH_PFC_PIN_CFG_INPUT)
+#define __O             (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU            (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define SH73A0_PIN_I_PD(pin)            SH73A0_PIN(pin, __I | __PD)
+#define SH73A0_PIN_I_PU(pin)            SH73A0_PIN(pin, __I | __PU)
+#define SH73A0_PIN_I_PU_PD(pin)         SH73A0_PIN(pin, __I | __PUD)
+#define SH73A0_PIN_IO(pin)              SH73A0_PIN(pin, __IO)
+#define SH73A0_PIN_IO_PD(pin)           SH73A0_PIN(pin, __IO | __PD)
+#define SH73A0_PIN_IO_PU(pin)           SH73A0_PIN(pin, __IO | __PU)
+#define SH73A0_PIN_IO_PU_PD(pin)        SH73A0_PIN(pin, __IO | __PUD)
+#define SH73A0_PIN_O(pin)               SH73A0_PIN(pin, __O)
+
+static struct sh_pfc_pin pinmux_pins[] = {
+        /* Table 25-1 (I/O and Pull U/D) */
+        SH73A0_PIN_I_PD(0),
+        SH73A0_PIN_I_PU(1),
+        SH73A0_PIN_I_PU(2),
+        SH73A0_PIN_I_PU(3),
+        SH73A0_PIN_I_PU(4),
+        SH73A0_PIN_I_PU(5),
+        SH73A0_PIN_I_PU(6),
+        SH73A0_PIN_I_PU(7),
+        SH73A0_PIN_I_PU(8),
+        SH73A0_PIN_I_PD(9),
+        SH73A0_PIN_I_PD(10),
+        SH73A0_PIN_I_PU_PD(11),
+        SH73A0_PIN_IO_PU_PD(12),
+        SH73A0_PIN_IO_PU_PD(13),
+        SH73A0_PIN_IO_PU_PD(14),
+        SH73A0_PIN_IO_PU_PD(15),
+        SH73A0_PIN_IO_PD(16),
+        SH73A0_PIN_IO_PD(17),
+        SH73A0_PIN_IO_PU(18),
+        SH73A0_PIN_IO_PU(19),
+        SH73A0_PIN_O(20),
+        SH73A0_PIN_O(21),
+        SH73A0_PIN_O(22),
+        SH73A0_PIN_O(23),
+        SH73A0_PIN_O(24),
+        SH73A0_PIN_I_PD(25),
+        SH73A0_PIN_I_PD(26),
+        SH73A0_PIN_IO_PU(27),
+        SH73A0_PIN_IO_PU(28),
+        SH73A0_PIN_IO_PD(29),
+        SH73A0_PIN_IO_PD(30),
+        SH73A0_PIN_IO_PU(31),
+        SH73A0_PIN_IO_PD(32),
+        SH73A0_PIN_I_PU_PD(33),
+        SH73A0_PIN_IO_PD(34),
+        SH73A0_PIN_I_PU_PD(35),
+        SH73A0_PIN_IO_PD(36),
+        SH73A0_PIN_IO(37),
+        SH73A0_PIN_O(38),
+        SH73A0_PIN_I_PU(39),
+        SH73A0_PIN_I_PU_PD(40),
+        SH73A0_PIN_O(41),
+        SH73A0_PIN_IO_PD(42),
+        SH73A0_PIN_IO_PU_PD(43),
+        SH73A0_PIN_IO_PU_PD(44),
+        SH73A0_PIN_IO_PD(45),
+        SH73A0_PIN_IO_PD(46),
+        SH73A0_PIN_IO_PD(47),
+        SH73A0_PIN_I_PD(48),
+        SH73A0_PIN_IO_PU_PD(49),
+        SH73A0_PIN_IO_PD(50),
+        SH73A0_PIN_IO_PD(51),
+        SH73A0_PIN_O(52),
+        SH73A0_PIN_IO_PU_PD(53),
+        SH73A0_PIN_IO_PU_PD(54),
+        SH73A0_PIN_IO_PD(55),
+        SH73A0_PIN_I_PU_PD(56),
+        SH73A0_PIN_IO(57),
+        SH73A0_PIN_IO(58),
+        SH73A0_PIN_IO(59),
+        SH73A0_PIN_IO(60),
+        SH73A0_PIN_IO(61),
+        SH73A0_PIN_IO_PD(62),
+        SH73A0_PIN_IO_PD(63),
+        SH73A0_PIN_IO_PU_PD(64),
+        SH73A0_PIN_IO_PD(65),
+        SH73A0_PIN_IO_PU_PD(66),
+        SH73A0_PIN_IO_PU_PD(67),
+        SH73A0_PIN_IO_PU_PD(68),
+        SH73A0_PIN_IO_PU_PD(69),
+        SH73A0_PIN_IO_PU_PD(70),
+        SH73A0_PIN_IO_PU_PD(71),
+        SH73A0_PIN_IO_PU_PD(72),
+        SH73A0_PIN_I_PU_PD(73),
+        SH73A0_PIN_IO_PU(74),
+        SH73A0_PIN_IO_PU(75),
+        SH73A0_PIN_IO_PU(76),
+        SH73A0_PIN_IO_PU(77),
+        SH73A0_PIN_IO_PU(78),
+        SH73A0_PIN_IO_PU(79),
+        SH73A0_PIN_IO_PU(80),
+        SH73A0_PIN_IO_PU(81),
+        SH73A0_PIN_IO_PU(82),
+        SH73A0_PIN_IO_PU(83),
+        SH73A0_PIN_IO_PU(84),
+        SH73A0_PIN_IO_PU(85),
+        SH73A0_PIN_IO_PU(86),
+        SH73A0_PIN_IO_PU(87),
+        SH73A0_PIN_IO_PU(88),
+        SH73A0_PIN_IO_PU(89),
+        SH73A0_PIN_O(90),
+        SH73A0_PIN_IO_PU(91),
+        SH73A0_PIN_O(92),
+        SH73A0_PIN_IO_PU(93),
+        SH73A0_PIN_O(94),
+        SH73A0_PIN_I_PU_PD(95),
+        SH73A0_PIN_IO(96),
+        SH73A0_PIN_IO(97),
+        SH73A0_PIN_IO(98),
+        SH73A0_PIN_I_PU(99),
+        SH73A0_PIN_O(100),
+        SH73A0_PIN_O(101),
+        SH73A0_PIN_I_PU(102),
+        SH73A0_PIN_IO_PD(103),
+        SH73A0_PIN_I_PU_PD(104),
+        SH73A0_PIN_I_PD(105),
+        SH73A0_PIN_I_PD(106),
+        SH73A0_PIN_I_PU_PD(107),
+        SH73A0_PIN_I_PU_PD(108),
+        SH73A0_PIN_IO_PD(109),
+        SH73A0_PIN_IO_PD(110),
+        SH73A0_PIN_IO_PU_PD(111),
+        SH73A0_PIN_IO_PU_PD(112),
+        SH73A0_PIN_IO_PU_PD(113),
+        SH73A0_PIN_IO_PD(114),
+        SH73A0_PIN_IO_PU(115),
+        SH73A0_PIN_IO_PU(116),
+        SH73A0_PIN_IO_PU_PD(117),
+        SH73A0_PIN_IO_PU_PD(118),
+        SH73A0_PIN_IO_PD(128),
+        SH73A0_PIN_IO_PD(129),
+        SH73A0_PIN_IO_PU_PD(130),
+        SH73A0_PIN_IO_PD(131),
+        SH73A0_PIN_IO_PD(132),
+        SH73A0_PIN_IO_PD(133),
+        SH73A0_PIN_IO_PU_PD(134),
+        SH73A0_PIN_IO_PU_PD(135),
+        SH73A0_PIN_IO_PU_PD(136),
+        SH73A0_PIN_IO_PU_PD(137),
+        SH73A0_PIN_IO_PD(138),
+        SH73A0_PIN_IO_PD(139),
+        SH73A0_PIN_IO_PD(140),
+        SH73A0_PIN_IO_PD(141),
+        SH73A0_PIN_IO_PD(142),
+        SH73A0_PIN_IO_PD(143),
+        SH73A0_PIN_IO_PU_PD(144),
+        SH73A0_PIN_IO_PD(145),
+        SH73A0_PIN_IO_PU_PD(146),
+        SH73A0_PIN_IO_PU_PD(147),
+        SH73A0_PIN_IO_PU_PD(148),
+        SH73A0_PIN_IO_PU_PD(149),
+        SH73A0_PIN_I_PU_PD(150),
+        SH73A0_PIN_IO_PU_PD(151),
+        SH73A0_PIN_IO_PU_PD(152),
+        SH73A0_PIN_IO_PD(153),
+        SH73A0_PIN_IO_PD(154),
+        SH73A0_PIN_I_PU_PD(155),
+        SH73A0_PIN_IO_PU_PD(156),
+        SH73A0_PIN_I_PD(157),
+        SH73A0_PIN_IO_PD(158),
+        SH73A0_PIN_IO_PU_PD(159),
+        SH73A0_PIN_IO_PU_PD(160),
+        SH73A0_PIN_I_PU_PD(161),
+        SH73A0_PIN_I_PU_PD(162),
+        SH73A0_PIN_IO_PU_PD(163),
+        SH73A0_PIN_I_PU_PD(164),
+        SH73A0_PIN_IO_PD(192),
+        SH73A0_PIN_IO_PU_PD(193),
+        SH73A0_PIN_IO_PD(194),
+        SH73A0_PIN_IO_PU_PD(195),
+        SH73A0_PIN_IO_PD(196),
+        SH73A0_PIN_IO_PD(197),
+        SH73A0_PIN_IO_PD(198),
+        SH73A0_PIN_IO_PD(199),
+        SH73A0_PIN_IO_PU_PD(200),
+        SH73A0_PIN_IO_PU_PD(201),
+        SH73A0_PIN_IO_PU_PD(202),
+        SH73A0_PIN_IO_PU_PD(203),
+        SH73A0_PIN_IO_PU_PD(204),
+        SH73A0_PIN_IO_PU_PD(205),
+        SH73A0_PIN_IO_PU_PD(206),
+        SH73A0_PIN_IO_PD(207),
+        SH73A0_PIN_IO_PD(208),
+        SH73A0_PIN_IO_PD(209),
+        SH73A0_PIN_IO_PD(210),
+        SH73A0_PIN_IO_PD(211),
+        SH73A0_PIN_IO_PD(212),
+        SH73A0_PIN_IO_PD(213),
+        SH73A0_PIN_IO_PU_PD(214),
+        SH73A0_PIN_IO_PU_PD(215),
+        SH73A0_PIN_IO_PD(216),
+        SH73A0_PIN_IO_PD(217),
+        SH73A0_PIN_O(218),
+        SH73A0_PIN_IO_PD(219),
+        SH73A0_PIN_IO_PD(220),
+        SH73A0_PIN_IO_PU_PD(221),
+        SH73A0_PIN_IO_PU_PD(222),
+        SH73A0_PIN_I_PU_PD(223),
+        SH73A0_PIN_I_PU_PD(224),
+        SH73A0_PIN_IO_PU_PD(225),
+        SH73A0_PIN_O(226),
+        SH73A0_PIN_IO_PU_PD(227),
+        SH73A0_PIN_I_PU_PD(228),
+        SH73A0_PIN_I_PD(229),
+        SH73A0_PIN_IO(230),
+        SH73A0_PIN_IO_PU_PD(231),
+        SH73A0_PIN_IO_PU_PD(232),
+        SH73A0_PIN_I_PU_PD(233),
+        SH73A0_PIN_IO_PU_PD(234),
+        SH73A0_PIN_IO_PU_PD(235),
+        SH73A0_PIN_IO_PU_PD(236),
+        SH73A0_PIN_IO_PD(237),
+        SH73A0_PIN_IO_PU_PD(238),
+        SH73A0_PIN_IO_PU_PD(239),
+        SH73A0_PIN_IO_PU_PD(240),
+        SH73A0_PIN_O(241),
+        SH73A0_PIN_I_PD(242),
+        SH73A0_PIN_IO_PU_PD(243),
+        SH73A0_PIN_IO_PU_PD(244),
+        SH73A0_PIN_IO_PU_PD(245),
+        SH73A0_PIN_IO_PU_PD(246),
+        SH73A0_PIN_IO_PU_PD(247),
+        SH73A0_PIN_IO_PU_PD(248),
+        SH73A0_PIN_IO_PU_PD(249),
+        SH73A0_PIN_IO_PU_PD(250),
+        SH73A0_PIN_IO_PU_PD(251),
+        SH73A0_PIN_IO_PU_PD(252),
+        SH73A0_PIN_IO_PU_PD(253),
+        SH73A0_PIN_IO_PU_PD(254),
+        SH73A0_PIN_IO_PU_PD(255),
+        SH73A0_PIN_IO_PU_PD(256),
+        SH73A0_PIN_IO_PU_PD(257),
+        SH73A0_PIN_IO_PU_PD(258),
+        SH73A0_PIN_IO_PU_PD(259),
+        SH73A0_PIN_IO_PU_PD(260),
+        SH73A0_PIN_IO_PU_PD(261),
+        SH73A0_PIN_IO_PU_PD(262),
+        SH73A0_PIN_IO_PU_PD(263),
+        SH73A0_PIN_IO_PU_PD(264),
+        SH73A0_PIN_IO_PU_PD(265),
+        SH73A0_PIN_IO_PU_PD(266),
+        SH73A0_PIN_IO_PU_PD(267),
+        SH73A0_PIN_IO_PU_PD(268),
+        SH73A0_PIN_IO_PU_PD(269),
+        SH73A0_PIN_IO_PU_PD(270),
+        SH73A0_PIN_IO_PU_PD(271),
+        SH73A0_PIN_IO_PU_PD(272),
+        SH73A0_PIN_IO_PU_PD(273),
+        SH73A0_PIN_IO_PU_PD(274),
+        SH73A0_PIN_IO_PU_PD(275),
+        SH73A0_PIN_IO_PU_PD(276),
+        SH73A0_PIN_IO_PU_PD(277),
+        SH73A0_PIN_IO_PU_PD(278),
+        SH73A0_PIN_IO_PU_PD(279),
+        SH73A0_PIN_IO_PU_PD(280),
+        SH73A0_PIN_O(281),
+        SH73A0_PIN_O(282),
+        SH73A0_PIN_I_PU(288),
+        SH73A0_PIN_IO_PU_PD(289),
+        SH73A0_PIN_IO_PU_PD(290),
+        SH73A0_PIN_IO_PU_PD(291),
+        SH73A0_PIN_IO_PU_PD(292),
+        SH73A0_PIN_IO_PU_PD(293),
+        SH73A0_PIN_IO_PU_PD(294),
+        SH73A0_PIN_IO_PU_PD(295),
+        SH73A0_PIN_IO_PU_PD(296),
+        SH73A0_PIN_IO_PU_PD(297),
+        SH73A0_PIN_IO_PU_PD(298),
+        SH73A0_PIN_IO_PU_PD(299),
+        SH73A0_PIN_IO_PU_PD(300),
+        SH73A0_PIN_IO_PU_PD(301),
+        SH73A0_PIN_IO_PU_PD(302),
+        SH73A0_PIN_IO_PU_PD(303),
+        SH73A0_PIN_IO_PU_PD(304),
+        SH73A0_PIN_IO_PU_PD(305),
+        SH73A0_PIN_O(306),
+        SH73A0_PIN_O(307),
+        SH73A0_PIN_I_PU(308),
+        SH73A0_PIN_O(309),
+};
+
+static const struct pinmux_range pinmux_ranges[] = {
+        {.begin = 0, .end = 118,},
+        {.begin = 128, .end = 164,},
+        {.begin = 192, .end = 282,},
+        {.begin = 288, .end = 309,},
+};
+
+/* Pin numbers for pins without a corresponding GPIO port number are computed
+ * from the row and column numbers with a 1000 offset to avoid collisions with
+ * GPIO port numbers.
+ */
+#define PIN_NUMBER(row, col)            (1000+((row)-1)*34+(col)-1)
+
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data_0_7_pins[] = {
+        /* D[0:7] */
+        74, 75, 76, 77, 78, 79, 80, 81,
+};
+static const unsigned int bsc_data_0_7_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data_8_15_pins[] = {
+        /* D[8:15] */
+        82, 83, 84, 85, 86, 87, 88, 89,
+};
+static const unsigned int bsc_data_8_15_mux[] = {
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+        /* CS */
+        90,
+};
+static const unsigned int bsc_cs4_mux[] = {
+        CS4__MARK,
+};
+static const unsigned int bsc_cs5_a_pins[] = {
+        /* CS */
+        91,
+};
+static const unsigned int bsc_cs5_a_mux[] = {
+        CS5A__MARK,
+};
+static const unsigned int bsc_cs5_b_pins[] = {
+        /* CS */
+        92,
+};
+static const unsigned int bsc_cs5_b_mux[] = {
+        CS5B__MARK,
+};
+static const unsigned int bsc_cs6_a_pins[] = {
+        /* CS */
+        94,
+};
+static const unsigned int bsc_cs6_a_mux[] = {
+        CS6A__MARK,
+};
+static const unsigned int bsc_cs6_b_pins[] = {
+        /* CS */
+        93,
+};
+static const unsigned int bsc_cs6_b_mux[] = {
+        CS6B__MARK,
+};
+static const unsigned int bsc_rd_pins[] = {
+        /* RD */
+        96,
+};
+static const unsigned int bsc_rd_mux[] = {
+        RD__FSC_MARK,
+};
+static const unsigned int bsc_rdwr_0_pins[] = {
+        /* RDWR */
+        91,
+};
+static const unsigned int bsc_rdwr_0_mux[] = {
+        PORT91_RDWR_MARK,
+};
+static const unsigned int bsc_rdwr_1_pins[] = {
+        /* RDWR */
+        97,
+};
+static const unsigned int bsc_rdwr_1_mux[] = {
+        RDWR_FWE_MARK,
+};
+static const unsigned int bsc_rdwr_2_pins[] = {
+        /* RDWR */
+        149,
+};
+static const unsigned int bsc_rdwr_2_mux[] = {
+        PORT149_RDWR_MARK,
+};
+static const unsigned int bsc_we0_pins[] = {
+        /* WE0 */
+        97,
+};
+static const unsigned int bsc_we0_mux[] = {
+        WE0__FWE_MARK,
+};
+static const unsigned int bsc_we1_pins[] = {
+        /* WE1 */
+        98,
+};
+static const unsigned int bsc_we1_mux[] = {
+        WE1__MARK,
+};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+        /* CK */
+        49,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+        FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+        /* OMC */
+        49,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+        FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+        /* ILR, IBT */
+        50, 51,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+        FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+        /* OLR, OBT */
+        50, 51,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+        FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_pins[] = {
+        /* ISLD */
+        55,
+};
+static const unsigned int fsia_data_in_mux[] = {
+        FSIAISLD_MARK,
+};
+static const unsigned int fsia_data_out_pins[] = {
+        /* OSLD */
+        52,
+};
+static const unsigned int fsia_data_out_mux[] = {
+        FSIAOSLD_MARK,
+};
+static const unsigned int fsia_spdif_pins[] = {
+        /* SPDIF */
+        53,
+};
+static const unsigned int fsia_spdif_mux[] = {
+        FSIASPDIF_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+        /* CK */
+        54,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+        FSIBCK_MARK,
+};
+static const unsigned int fsib_mclk_out_pins[] = {
+        /* OMC */
+        54,
+};
+static const unsigned int fsib_mclk_out_mux[] = {
+        FSIBOMC_MARK,
+};
+static const unsigned int fsib_sclk_in_pins[] = {
+        /* ILR, IBT */
+        37, 36,
+};
+static const unsigned int fsib_sclk_in_mux[] = {
+        FSIBILR_MARK, FSIBIBT_MARK,
+};
+static const unsigned int fsib_sclk_out_pins[] = {
+        /* OLR, OBT */
+        37, 36,
+};
+static const unsigned int fsib_sclk_out_mux[] = {
+        FSIBOLR_MARK, FSIBOBT_MARK,
+};
+static const unsigned int fsib_data_in_pins[] = {
+        /* ISLD */
+        39,
+};
+static const unsigned int fsib_data_in_mux[] = {
+        FSIBISLD_MARK,
+};
+static const unsigned int fsib_data_out_pins[] = {
+        /* OSLD */
+        38,
+};
+static const unsigned int fsib_data_out_mux[] = {
+        FSIBOSLD_MARK,
+};
+static const unsigned int fsib_spdif_pins[] = {
+        /* SPDIF */
+        53,
+};
+static const unsigned int fsib_spdif_mux[] = {
+        FSIBSPDIF_MARK,
+};
+/* - FSIC ------------------------------------------------------------------- */
+static const unsigned int fsic_mclk_in_pins[] = {
+        /* CK */
+        54,
+};
+static const unsigned int fsic_mclk_in_mux[] = {
+        FSICCK_MARK,
+};
+static const unsigned int fsic_mclk_out_pins[] = {
+        /* OMC */
+        54,
+};
+static const unsigned int fsic_mclk_out_mux[] = {
+        FSICOMC_MARK,
+};
+static const unsigned int fsic_sclk_in_pins[] = {
+        /* ILR, IBT */
+        46, 45,
+};
+static const unsigned int fsic_sclk_in_mux[] = {
+        FSICILR_MARK, FSICIBT_MARK,
+};
+static const unsigned int fsic_sclk_out_pins[] = {
+        /* OLR, OBT */
+        46, 45,
+};
+static const unsigned int fsic_sclk_out_mux[] = {
+        FSICOLR_MARK, FSICOBT_MARK,
+};
+static const unsigned int fsic_data_in_pins[] = {
+        /* ISLD */
+        48,
+};
+static const unsigned int fsic_data_in_mux[] = {
+        FSICISLD_MARK,
+};
+static const unsigned int fsic_data_out_pins[] = {
+        /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
+        47, 44, 42, 16,
+};
+static const unsigned int fsic_data_out_mux[] = {
+        FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
+};
+static const unsigned int fsic_spdif_0_pins[] = {
+        /* SPDIF */
+        53,
+};
+static const unsigned int fsic_spdif_0_mux[] = {
+        PORT53_FSICSPDIF_MARK,
+};
+static const unsigned int fsic_spdif_1_pins[] = {
+        /* SPDIF */
+        47,
+};
+static const unsigned int fsic_spdif_1_mux[] = {
+        PORT47_FSICSPDIF_MARK,
+};
+/* - FSID ------------------------------------------------------------------- */
+static const unsigned int fsid_sclk_in_pins[] = {
+        /* ILR, IBT */
+        46, 45,
+};
+static const unsigned int fsid_sclk_in_mux[] = {
+        FSIDILR_MARK, FSIDIBT_MARK,
+};
+static const unsigned int fsid_sclk_out_pins[] = {
+        /* OLR, OBT */
+        46, 45,
+};
+static const unsigned int fsid_sclk_out_mux[] = {
+        FSIDOLR_MARK, FSIDOBT_MARK,
+};
+static const unsigned int fsid_data_in_pins[] = {
+        /* ISLD */
+        48,
+};
+static const unsigned int fsid_data_in_mux[] = {
+        FSIDISLD_MARK,
+};
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_0_pins[] = {
+        /* SCL, SDA */
+        237, 236,
+};
+static const unsigned int i2c2_0_mux[] = {
+        PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
+};
+static const unsigned int i2c2_1_pins[] = {
+        /* SCL, SDA */
+        27, 28,
+};
+static const unsigned int i2c2_1_mux[] = {
+        PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
+};
+static const unsigned int i2c2_2_pins[] = {
+        /* SCL, SDA */
+        115, 116,
+};
+static const unsigned int i2c2_2_mux[] = {
+        PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
+};
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_0_pins[] = {
+        /* SCL, SDA */
+        248, 249,
+};
+static const unsigned int i2c3_0_mux[] = {
+        PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
+};
+static const unsigned int i2c3_1_pins[] = {
+        /* SCL, SDA */
+        27, 28,
+};
+static const unsigned int i2c3_1_mux[] = {
+        PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
+};
+static const unsigned int i2c3_2_pins[] = {
+        /* SCL, SDA */
+        115, 116,
+};
+static const unsigned int i2c3_2_mux[] = {
+        PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
+};
+/* - IrDA ------------------------------------------------------------------- */
+static const unsigned int irda_0_pins[] = {
+        /* OUT, IN, FIRSEL */
+        241, 242, 243,
+};
+static const unsigned int irda_0_mux[] = {
+        PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
+};
+static const unsigned int irda_1_pins[] = {
+        /* OUT, IN, FIRSEL */
+        49, 53, 54,
+};
+static const unsigned int irda_1_mux[] = {
+        PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
+};
+/* - KEYSC ------------------------------------------------------------------ */
+static const unsigned int keysc_in5_pins[] = {
+        /* KEYIN[0:4] */
+        66, 67, 68, 69, 70,
+};
+static const unsigned int keysc_in5_mux[] = {
+        KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+        KEYIN4_MARK,
+};
+static const unsigned int keysc_in6_pins[] = {
+        /* KEYIN[0:5] */
+        66, 67, 68, 69, 70, 71,
+};
+static const unsigned int keysc_in6_mux[] = {
+        KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+        KEYIN4_MARK, KEYIN5_MARK,
+};
+static const unsigned int keysc_in7_pins[] = {
+        /* KEYIN[0:6] */
+        66, 67, 68, 69, 70, 71, 72,
+};
+static const unsigned int keysc_in7_mux[] = {
+        KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+        KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
+};
+static const unsigned int keysc_in8_pins[] = {
+        /* KEYIN[0:7] */
+        66, 67, 68, 69, 70, 71, 72, 73,
+};
+static const unsigned int keysc_in8_mux[] = {
+        KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+        KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
+};
+static const unsigned int keysc_out04_pins[] = {
+        /* KEYOUT[0:4] */
+        65, 64, 63, 62, 61,
+};
+static const unsigned int keysc_out04_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
+};
+static const unsigned int keysc_out5_pins[] = {
+        /* KEYOUT5 */
+        60,
+};
+static const unsigned int keysc_out5_mux[] = {
+        KEYOUT5_MARK,
+};
+static const unsigned int keysc_out6_0_pins[] = {
+        /* KEYOUT6 */
+        59,
+};
+static const unsigned int keysc_out6_0_mux[] = {
+        PORT59_KEYOUT6_MARK,
+};
+static const unsigned int keysc_out6_1_pins[] = {
+        /* KEYOUT6 */
+        131,
+};
+static const unsigned int keysc_out6_1_mux[] = {
+        PORT131_KEYOUT6_MARK,
+};
+static const unsigned int keysc_out6_2_pins[] = {
+        /* KEYOUT6 */
+        143,
+};
+static const unsigned int keysc_out6_2_mux[] = {
+        PORT143_KEYOUT6_MARK,
+};
+static const unsigned int keysc_out7_0_pins[] = {
+        /* KEYOUT7 */
+        58,
+};
+static const unsigned int keysc_out7_0_mux[] = {
+        PORT58_KEYOUT7_MARK,
+};
+static const unsigned int keysc_out7_1_pins[] = {
+        /* KEYOUT7 */
+        132,
+};
+static const unsigned int keysc_out7_1_mux[] = {
+        PORT132_KEYOUT7_MARK,
+};
+static const unsigned int keysc_out7_2_pins[] = {
+        /* KEYOUT7 */
+        144,
+};
+static const unsigned int keysc_out7_2_mux[] = {
+        PORT144_KEYOUT7_MARK,
+};
+static const unsigned int keysc_out8_0_pins[] = {
+        /* KEYOUT8 */
+        PIN_NUMBER(6, 26),
+};
+static const unsigned int keysc_out8_0_mux[] = {
+        KEYOUT8_MARK,
+};
+static const unsigned int keysc_out8_1_pins[] = {
+        /* KEYOUT8 */
+        136,
+};
+static const unsigned int keysc_out8_1_mux[] = {
+        PORT136_KEYOUT8_MARK,
+};
+static const unsigned int keysc_out8_2_pins[] = {
+        /* KEYOUT8 */
+        138,
+};
+static const unsigned int keysc_out8_2_mux[] = {
+        PORT138_KEYOUT8_MARK,
+};
+static const unsigned int keysc_out9_0_pins[] = {
+        /* KEYOUT9 */
+        137,
+};
+static const unsigned int keysc_out9_0_mux[] = {
+        PORT137_KEYOUT9_MARK,
+};
+static const unsigned int keysc_out9_1_pins[] = {
+        /* KEYOUT9 */
+        139,
+};
+static const unsigned int keysc_out9_1_mux[] = {
+        PORT139_KEYOUT9_MARK,
+};
+static const unsigned int keysc_out9_2_pins[] = {
+        /* KEYOUT9 */
+        149,
+};
+static const unsigned int keysc_out9_2_mux[] = {
+        PORT149_KEYOUT9_MARK,
+};
+static const unsigned int keysc_out10_0_pins[] = {
+        /* KEYOUT10 */
+        132,
+};
+static const unsigned int keysc_out10_0_mux[] = {
+        PORT132_KEYOUT10_MARK,
+};
+static const unsigned int keysc_out10_1_pins[] = {
+        /* KEYOUT10 */
+        142,
+};
+static const unsigned int keysc_out10_1_mux[] = {
+        PORT142_KEYOUT10_MARK,
+};
+static const unsigned int keysc_out11_0_pins[] = {
+        /* KEYOUT11 */
+        131,
+};
+static const unsigned int keysc_out11_0_mux[] = {
+        PORT131_KEYOUT11_MARK,
+};
+static const unsigned int keysc_out11_1_pins[] = {
+        /* KEYOUT11 */
+        143,
+};
+static const unsigned int keysc_out11_1_mux[] = {
+        PORT143_KEYOUT11_MARK,
+};
+/* - LCD -------------------------------------------------------------------- */
+static const unsigned int lcd_data8_pins[] = {
+        /* D[0:7] */
+        192, 193, 194, 195, 196, 197, 198, 199,
+};
+static const unsigned int lcd_data8_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+};
+static const unsigned int lcd_data9_pins[] = {
+        /* D[0:8] */
+        192, 193, 194, 195, 196, 197, 198, 199,
+        200,
+};
+static const unsigned int lcd_data9_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK,
+};
+static const unsigned int lcd_data12_pins[] = {
+        /* D[0:11] */
+        192, 193, 194, 195, 196, 197, 198, 199,
+        200, 201, 202, 203,
+};
+static const unsigned int lcd_data12_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+};
+static const unsigned int lcd_data16_pins[] = {
+        /* D[0:15] */
+        192, 193, 194, 195, 196, 197, 198, 199,
+        200, 201, 202, 203, 204, 205, 206, 207,
+};
+static const unsigned int lcd_data16_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+};
+static const unsigned int lcd_data18_pins[] = {
+        /* D[0:17] */
+        192, 193, 194, 195, 196, 197, 198, 199,
+        200, 201, 202, 203, 204, 205, 206, 207,
+        208, 209,
+};
+static const unsigned int lcd_data18_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+        LCDD16_MARK, LCDD17_MARK,
+};
+static const unsigned int lcd_data24_pins[] = {
+        /* D[0:23] */
+        192, 193, 194, 195, 196, 197, 198, 199,
+        200, 201, 202, 203, 204, 205, 206, 207,
+        208, 209, 210, 211, 212, 213, 214, 215
+};
+static const unsigned int lcd_data24_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+        LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
+        LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
+};
+static const unsigned int lcd_display_pins[] = {
+        /* DON */
+        222,
+};
+static const unsigned int lcd_display_mux[] = {
+        LCDDON_MARK,
+};
+static const unsigned int lcd_lclk_pins[] = {
+        /* LCLK */
+        221,
+};
+static const unsigned int lcd_lclk_mux[] = {
+        LCDLCLK_MARK,
+};
+static const unsigned int lcd_sync_pins[] = {
+        /* VSYN, HSYN, DCK, DISP */
+        220, 218, 216, 219,
+};
+static const unsigned int lcd_sync_mux[] = {
+        LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
+};
+static const unsigned int lcd_sys_pins[] = {
+        /* CS, WR, RD, RS */
+        218, 216, 217, 219,
+};
+static const unsigned int lcd_sys_mux[] = {
+        LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
+};
+/* - LCD2 ------------------------------------------------------------------- */
+static const unsigned int lcd2_data8_pins[] = {
+        /* D[0:7] */
+        128, 129, 142, 143, 144, 145, 138, 139,
+};
+static const unsigned int lcd2_data8_mux[] = {
+        LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+        LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+};
+static const unsigned int lcd2_data9_pins[] = {
+        /* D[0:8] */
+        128, 129, 142, 143, 144, 145, 138, 139,
+        140,
+};
+static const unsigned int lcd2_data9_mux[] = {
+        LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+        LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+        LCD2D8_MARK,
+};
+static const unsigned int lcd2_data12_pins[] = {
+        /* D[0:12] */
+        128, 129, 142, 143, 144, 145, 138, 139,
+        140, 141, 130, 131,
+};
+static const unsigned int lcd2_data12_mux[] = {
+        LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+        LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+        LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
+};
+static const unsigned int lcd2_data16_pins[] = {
+        /* D[0:15] */
+        128, 129, 142, 143, 144, 145, 138, 139,
+        140, 141, 130, 131, 132, 133, 134, 135,
+};
+static const unsigned int lcd2_data16_mux[] = {
+        LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+        LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+        LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
+        LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
+};
+static const unsigned int lcd2_data18_pins[] = {
+        /* D[0:17] */
+        128, 129, 142, 143, 144, 145, 138, 139,
+        140, 141, 130, 131, 132, 133, 134, 135,
+        136, 137,
+};
+static const unsigned int lcd2_data18_mux[] = {
+        LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+        LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+        LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
+        LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
+        LCD2D16_MARK, LCD2D17_MARK,
+};
+static const unsigned int lcd2_data24_pins[] = {
+        /* D[0:23] */
+        128, 129, 142, 143, 144, 145, 138, 139,
+        140, 141, 130, 131, 132, 133, 134, 135,
+        136, 137, 146, 147, 234, 235, 238, 239
+};
+static const unsigned int lcd2_data24_mux[] = {
+        LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
+        LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
+        LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
+        LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
+        LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
+        LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
+};
+static const unsigned int lcd2_sync_0_pins[] = {
+        /* VSYN, HSYN, DCK, DISP */
+        128, 129, 146, 145,
+};
+static const unsigned int lcd2_sync_0_mux[] = {
+        PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
+        LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
+};
+static const unsigned int lcd2_sync_1_pins[] = {
+        /* VSYN, HSYN, DCK, DISP */
+        222, 221, 219, 217,
+};
+static const unsigned int lcd2_sync_1_mux[] = {
+        PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
+        LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
+};
+static const unsigned int lcd2_sys_0_pins[] = {
+        /* CS, WR, RD, RS */
+        129, 146, 147, 145,
+};
+static const unsigned int lcd2_sys_0_mux[] = {
+        PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
+        LCD2RD__MARK, PORT145_LCD2RS_MARK,
+};
+static const unsigned int lcd2_sys_1_pins[] = {
+        /* CS, WR, RD, RS */
+        221, 219, 147, 217,
+};
+static const unsigned int lcd2_sys_1_mux[] = {
+        PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
+        LCD2RD__MARK, PORT217_LCD2RS_MARK,
+};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_0_pins[] = {
+        /* D[0] */
+        271,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+        MMCD0_0_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+        /* D[0:3] */
+        271, 272, 273, 274,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+        MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+        /* D[0:7] */
+        271, 272, 273, 274, 275, 276, 277, 278,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+        MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+        MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+        /* CMD, CLK */
+        279, 270,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+        MMCCMD0_MARK, MMCCLK0_MARK,
+};
 
-        /* Functions with pull-ups */
-        PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
-        PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
-        PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
-        PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
-        PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
-        PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
-        PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
-        PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
-
-        PINMUX_DATA(SDHICD0_PU_MARK,  PORT251_FN1, PORT251_IN_PU),
-        PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU),
-        PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU),
-        PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
-        PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
-        PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
-        PINMUX_DATA(SDHIWP0_PU_MARK,  PORT257_FN1, PORT256_IN_PU),
-        PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
-        PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
-        PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
-        PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU),
-        PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU),
-        PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU),
-        PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU),
-        PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU),
-        PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU),
-        PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU),
-
-        PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
-                MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
-                MSEL4CR_MSEL15_1),
-
-        PINMUX_DATA(MMCD0_0_PU_MARK,
-                    PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_1_PU_MARK,
-                    PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_2_PU_MARK,
-                    PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_3_PU_MARK,
-                    PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_4_PU_MARK,
-                    PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_5_PU_MARK,
-                    PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_6_PU_MARK,
-                    PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
-        PINMUX_DATA(MMCD0_7_PU_MARK,
-                    PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
-
-        PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
-        PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
-        PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
-        PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
-        PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
-};
-
-static struct pinmux_gpio pinmux_gpios[] = {
-        GPIO_PORT_ALL(),
+static const unsigned int mmc0_data1_1_pins[] = {
+        /* D[0] */
+        305,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+        MMCD1_0_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+        /* D[0:3] */
+        305, 304, 303, 302,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+        MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+        /* D[0:7] */
+        305, 304, 303, 302, 301, 300, 299, 298,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+        MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+        MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+        /* CMD, CLK */
+        297, 289,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+        MMCCMD1_MARK, MMCCLK1_MARK,
+};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        43, 17,
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        16,
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        42, 44,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        228, 225,
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        226,
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        227, 229,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_0_pins[] = {
+        /* RXD, TXD */
+        155, 154,
+};
+static const unsigned int scifa2_data_0_mux[] = {
+        SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
+};
+static const unsigned int scifa2_clk_0_pins[] = {
+        /* SCK */
+        158,
+};
+static const unsigned int scifa2_clk_0_mux[] = {
+        SCIFA2_SCK1_MARK,
+};
+static const unsigned int scifa2_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        156, 157,
+};
+static const unsigned int scifa2_ctrl_0_mux[] = {
+        SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
+};
+static const unsigned int scifa2_data_1_pins[] = {
+        /* RXD, TXD */
+        233, 230,
+};
+static const unsigned int scifa2_data_1_mux[] = {
+        SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
+};
+static const unsigned int scifa2_clk_1_pins[] = {
+        /* SCK */
+        232,
+};
+static const unsigned int scifa2_clk_1_mux[] = {
+        SCIFA2_SCK2_MARK,
+};
+static const unsigned int scifa2_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        234, 231,
+};
+static const unsigned int scifa2_ctrl_1_mux[] = {
+        SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_pins[] = {
+        /* RXD, TXD */
+        108, 110,
+};
+static const unsigned int scifa3_data_mux[] = {
+        SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
+};
+static const unsigned int scifa3_ctrl_pins[] = {
+        /* RTS, CTS */
+        109, 107,
+};
+static const unsigned int scifa3_ctrl_mux[] = {
+        SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_pins[] = {
+        /* RXD, TXD */
+        33, 32,
+};
+static const unsigned int scifa4_data_mux[] = {
+        SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
+};
+static const unsigned int scifa4_ctrl_pins[] = {
+        /* RTS, CTS */
+        34, 35,
+};
+static const unsigned int scifa4_ctrl_mux[] = {
+        SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_0_pins[] = {
+        /* RXD, TXD */
+        246, 247,
+};
+static const unsigned int scifa5_data_0_mux[] = {
+        PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
+};
+static const unsigned int scifa5_clk_0_pins[] = {
+        /* SCK */
+        248,
+};
+static const unsigned int scifa5_clk_0_mux[] = {
+        PORT248_SCIFA5_SCK_MARK,
+};
+static const unsigned int scifa5_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        245, 244,
+};
+static const unsigned int scifa5_ctrl_0_mux[] = {
+        PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
+};
+static const unsigned int scifa5_data_1_pins[] = {
+        /* RXD, TXD */
+        195, 196,
+};
+static const unsigned int scifa5_data_1_mux[] = {
+        PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
+};
+static const unsigned int scifa5_clk_1_pins[] = {
+        /* SCK */
+        197,
+};
+static const unsigned int scifa5_clk_1_mux[] = {
+        PORT197_SCIFA5_SCK_MARK,
+};
+static const unsigned int scifa5_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        194, 193,
+};
+static const unsigned int scifa5_ctrl_1_mux[] = {
+        PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
+};
+static const unsigned int scifa5_data_2_pins[] = {
+        /* RXD, TXD */
+        162, 160,
+};
+static const unsigned int scifa5_data_2_mux[] = {
+        PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
+};
+static const unsigned int scifa5_clk_2_pins[] = {
+        /* SCK */
+        159,
+};
+static const unsigned int scifa5_clk_2_mux[] = {
+        PORT159_SCIFA5_SCK_MARK,
+};
+static const unsigned int scifa5_ctrl_2_pins[] = {
+        /* RTS, CTS */
+        163, 161,
+};
+static const unsigned int scifa5_ctrl_2_mux[] = {
+        PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
+};
+/* - SCIFA6 ----------------------------------------------------------------- */
+static const unsigned int scifa6_pins[] = {
+        /* TXD */
+        240,
+};
+static const unsigned int scifa6_mux[] = {
+        SCIFA6_TXD_MARK,
+};
+/* - SCIFA7 ----------------------------------------------------------------- */
+static const unsigned int scifa7_data_pins[] = {
+        /* RXD, TXD */
+        12, 18,
+};
+static const unsigned int scifa7_data_mux[] = {
+        SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
+};
+static const unsigned int scifa7_ctrl_pins[] = {
+        /* RTS, CTS */
+        19, 13,
+};
+static const unsigned int scifa7_ctrl_mux[] = {
+        SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_0_pins[] = {
+        /* RXD, TXD */
+        162, 160,
+};
+static const unsigned int scifb_data_0_mux[] = {
+        PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
+};
+static const unsigned int scifb_clk_0_pins[] = {
+        /* SCK */
+        159,
+};
+static const unsigned int scifb_clk_0_mux[] = {
+        PORT159_SCIFB_SCK_MARK,
+};
+static const unsigned int scifb_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        163, 161,
+};
+static const unsigned int scifb_ctrl_0_mux[] = {
+        PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
+};
+static const unsigned int scifb_data_1_pins[] = {
+        /* RXD, TXD */
+        246, 247,
+};
+static const unsigned int scifb_data_1_mux[] = {
+        PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
+};
+static const unsigned int scifb_clk_1_pins[] = {
+        /* SCK */
+        248,
+};
+static const unsigned int scifb_clk_1_mux[] = {
+        PORT248_SCIFB_SCK_MARK,
+};
+static const unsigned int scifb_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        245, 244,
+};
+static const unsigned int scifb_ctrl_1_mux[] = {
+        PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+        /* D0 */
+        252,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+        SDHID0_0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+        /* D[0:3] */
+        252, 253, 254, 255,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+        SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+        /* CMD, CLK */
+        256, 250,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+        SDHICMD0_MARK, SDHICLK0_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+        /* CD */
+        251,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+        SDHICD0_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+        /* WP */
+        257,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+        SDHIWP0_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+        /* D0 */
+        259,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+        SDHID1_0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+        /* D[0:3] */
+        259, 260, 261, 262,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+        SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+        /* CMD, CLK */
+        263, 258,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+        SDHICMD1_MARK, SDHICLK1_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+        /* D0 */
+        265,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+        SDHID2_0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+        /* D[0:3] */
+        265, 266, 267, 268,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+        SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+        /* CMD, CLK */
+        269, 264,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+        SDHICMD2_MARK, SDHICLK2_MARK,
+};
+/* - USB -------------------------------------------------------------------- */
+static const unsigned int usb_vbus_pins[] = {
+        /* VBUS */
+        0,
+};
+static const unsigned int usb_vbus_mux[] = {
+        VBUS_0_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(bsc_data_0_7),
+        SH_PFC_PIN_GROUP(bsc_data_8_15),
+        SH_PFC_PIN_GROUP(bsc_cs4),
+        SH_PFC_PIN_GROUP(bsc_cs5_a),
+        SH_PFC_PIN_GROUP(bsc_cs5_b),
+        SH_PFC_PIN_GROUP(bsc_cs6_a),
+        SH_PFC_PIN_GROUP(bsc_cs6_b),
+        SH_PFC_PIN_GROUP(bsc_rd),
+        SH_PFC_PIN_GROUP(bsc_rdwr_0),
+        SH_PFC_PIN_GROUP(bsc_rdwr_1),
+        SH_PFC_PIN_GROUP(bsc_rdwr_2),
+        SH_PFC_PIN_GROUP(bsc_we0),
+        SH_PFC_PIN_GROUP(bsc_we1),
+        SH_PFC_PIN_GROUP(fsia_mclk_in),
+        SH_PFC_PIN_GROUP(fsia_mclk_out),
+        SH_PFC_PIN_GROUP(fsia_sclk_in),
+        SH_PFC_PIN_GROUP(fsia_sclk_out),
+        SH_PFC_PIN_GROUP(fsia_data_in),
+        SH_PFC_PIN_GROUP(fsia_data_out),
+        SH_PFC_PIN_GROUP(fsia_spdif),
+        SH_PFC_PIN_GROUP(fsib_mclk_in),
+        SH_PFC_PIN_GROUP(fsib_mclk_out),
+        SH_PFC_PIN_GROUP(fsib_sclk_in),
+        SH_PFC_PIN_GROUP(fsib_sclk_out),
+        SH_PFC_PIN_GROUP(fsib_data_in),
+        SH_PFC_PIN_GROUP(fsib_data_out),
+        SH_PFC_PIN_GROUP(fsib_spdif),
+        SH_PFC_PIN_GROUP(fsic_mclk_in),
+        SH_PFC_PIN_GROUP(fsic_mclk_out),
+        SH_PFC_PIN_GROUP(fsic_sclk_in),
+        SH_PFC_PIN_GROUP(fsic_sclk_out),
+        SH_PFC_PIN_GROUP(fsic_data_in),
+        SH_PFC_PIN_GROUP(fsic_data_out),
+        SH_PFC_PIN_GROUP(fsic_spdif_0),
+        SH_PFC_PIN_GROUP(fsic_spdif_1),
+        SH_PFC_PIN_GROUP(fsid_sclk_in),
+        SH_PFC_PIN_GROUP(fsid_sclk_out),
+        SH_PFC_PIN_GROUP(fsid_data_in),
+        SH_PFC_PIN_GROUP(i2c2_0),
+        SH_PFC_PIN_GROUP(i2c2_1),
+        SH_PFC_PIN_GROUP(i2c2_2),
+        SH_PFC_PIN_GROUP(i2c3_0),
+        SH_PFC_PIN_GROUP(i2c3_1),
+        SH_PFC_PIN_GROUP(i2c3_2),
+        SH_PFC_PIN_GROUP(irda_0),
+        SH_PFC_PIN_GROUP(irda_1),
+        SH_PFC_PIN_GROUP(keysc_in5),
+        SH_PFC_PIN_GROUP(keysc_in6),
+        SH_PFC_PIN_GROUP(keysc_in7),
+        SH_PFC_PIN_GROUP(keysc_in8),
+        SH_PFC_PIN_GROUP(keysc_out04),
+        SH_PFC_PIN_GROUP(keysc_out5),
+        SH_PFC_PIN_GROUP(keysc_out6_0),
+        SH_PFC_PIN_GROUP(keysc_out6_1),
+        SH_PFC_PIN_GROUP(keysc_out6_2),
+        SH_PFC_PIN_GROUP(keysc_out7_0),
+        SH_PFC_PIN_GROUP(keysc_out7_1),
+        SH_PFC_PIN_GROUP(keysc_out7_2),
+        SH_PFC_PIN_GROUP(keysc_out8_0),
+        SH_PFC_PIN_GROUP(keysc_out8_1),
+        SH_PFC_PIN_GROUP(keysc_out8_2),
+        SH_PFC_PIN_GROUP(keysc_out9_0),
+        SH_PFC_PIN_GROUP(keysc_out9_1),
+        SH_PFC_PIN_GROUP(keysc_out9_2),
+        SH_PFC_PIN_GROUP(keysc_out10_0),
+        SH_PFC_PIN_GROUP(keysc_out10_1),
+        SH_PFC_PIN_GROUP(keysc_out11_0),
+        SH_PFC_PIN_GROUP(keysc_out11_1),
+        SH_PFC_PIN_GROUP(lcd_data8),
+        SH_PFC_PIN_GROUP(lcd_data9),
+        SH_PFC_PIN_GROUP(lcd_data12),
+        SH_PFC_PIN_GROUP(lcd_data16),
+        SH_PFC_PIN_GROUP(lcd_data18),
+        SH_PFC_PIN_GROUP(lcd_data24),
+        SH_PFC_PIN_GROUP(lcd_display),
+        SH_PFC_PIN_GROUP(lcd_lclk),
+        SH_PFC_PIN_GROUP(lcd_sync),
+        SH_PFC_PIN_GROUP(lcd_sys),
+        SH_PFC_PIN_GROUP(lcd2_data8),
+        SH_PFC_PIN_GROUP(lcd2_data9),
+        SH_PFC_PIN_GROUP(lcd2_data12),
+        SH_PFC_PIN_GROUP(lcd2_data16),
+        SH_PFC_PIN_GROUP(lcd2_data18),
+        SH_PFC_PIN_GROUP(lcd2_data24),
+        SH_PFC_PIN_GROUP(lcd2_sync_0),
+        SH_PFC_PIN_GROUP(lcd2_sync_1),
+        SH_PFC_PIN_GROUP(lcd2_sys_0),
+        SH_PFC_PIN_GROUP(lcd2_sys_1),
+        SH_PFC_PIN_GROUP(mmc0_data1_0),
+        SH_PFC_PIN_GROUP(mmc0_data4_0),
+        SH_PFC_PIN_GROUP(mmc0_data8_0),
+        SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+        SH_PFC_PIN_GROUP(mmc0_data1_1),
+        SH_PFC_PIN_GROUP(mmc0_data4_1),
+        SH_PFC_PIN_GROUP(mmc0_data8_1),
+        SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data_0),
+        SH_PFC_PIN_GROUP(scifa2_clk_0),
+        SH_PFC_PIN_GROUP(scifa2_ctrl_0),
+        SH_PFC_PIN_GROUP(scifa2_data_1),
+        SH_PFC_PIN_GROUP(scifa2_clk_1),
+        SH_PFC_PIN_GROUP(scifa2_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa3_data),
+        SH_PFC_PIN_GROUP(scifa3_ctrl),
+        SH_PFC_PIN_GROUP(scifa4_data),
+        SH_PFC_PIN_GROUP(scifa4_ctrl),
+        SH_PFC_PIN_GROUP(scifa5_data_0),
+        SH_PFC_PIN_GROUP(scifa5_clk_0),
+        SH_PFC_PIN_GROUP(scifa5_ctrl_0),
+        SH_PFC_PIN_GROUP(scifa5_data_1),
+        SH_PFC_PIN_GROUP(scifa5_clk_1),
+        SH_PFC_PIN_GROUP(scifa5_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa5_data_2),
+        SH_PFC_PIN_GROUP(scifa5_clk_2),
+        SH_PFC_PIN_GROUP(scifa5_ctrl_2),
+        SH_PFC_PIN_GROUP(scifa6),
+        SH_PFC_PIN_GROUP(scifa7_data),
+        SH_PFC_PIN_GROUP(scifa7_ctrl),
+        SH_PFC_PIN_GROUP(scifb_data_0),
+        SH_PFC_PIN_GROUP(scifb_clk_0),
+        SH_PFC_PIN_GROUP(scifb_ctrl_0),
+        SH_PFC_PIN_GROUP(scifb_data_1),
+        SH_PFC_PIN_GROUP(scifb_clk_1),
+        SH_PFC_PIN_GROUP(scifb_ctrl_1),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_data1),
+        SH_PFC_PIN_GROUP(sdhi1_data4),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi2_data1),
+        SH_PFC_PIN_GROUP(sdhi2_data4),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(usb_vbus),
+};
+
+static const char * const bsc_groups[] = {
+        "bsc_data_0_7",
+        "bsc_data_8_15",
+        "bsc_cs4",
+        "bsc_cs5_a",
+        "bsc_cs5_b",
+        "bsc_cs6_a",
+        "bsc_cs6_b",
+        "bsc_rd",
+        "bsc_rdwr_0",
+        "bsc_rdwr_1",
+        "bsc_rdwr_2",
+        "bsc_we0",
+        "bsc_we1",
+};
+
+static const char * const fsia_groups[] = {
+        "fsia_mclk_in",
+        "fsia_mclk_out",
+        "fsia_sclk_in",
+        "fsia_sclk_out",
+        "fsia_data_in",
+        "fsia_data_out",
+        "fsia_spdif",
+};
+
+static const char * const fsib_groups[] = {
+        "fsib_mclk_in",
+        "fsib_mclk_out",
+        "fsib_sclk_in",
+        "fsib_sclk_out",
+        "fsib_data_in",
+        "fsib_data_out",
+        "fsib_spdif",
+};
+
+static const char * const fsic_groups[] = {
+        "fsic_mclk_in",
+        "fsic_mclk_out",
+        "fsic_sclk_in",
+        "fsic_sclk_out",
+        "fsic_data_in",
+        "fsic_data_out",
+        "fsic_spdif",
+};
+
+static const char * const fsid_groups[] = {
+        "fsid_sclk_in",
+        "fsid_sclk_out",
+        "fsid_data_in",
+};
+
+static const char * const i2c2_groups[] = {
+        "i2c2_0",
+        "i2c2_1",
+        "i2c2_2",
+};
+
+static const char * const i2c3_groups[] = {
+        "i2c3_0",
+        "i2c3_1",
+        "i2c3_2",
+};
+
+static const char * const irda_groups[] = {
+        "irda_0",
+        "irda_1",
+};
 
+static const char * const keysc_groups[] = {
+        "keysc_in5",
+        "keysc_in6",
+        "keysc_in7",
+        "keysc_in8",
+        "keysc_out04",
+        "keysc_out5",
+        "keysc_out6_0",
+        "keysc_out6_1",
+        "keysc_out6_2",
+        "keysc_out7_0",
+        "keysc_out7_1",
+        "keysc_out7_2",
+        "keysc_out8_0",
+        "keysc_out8_1",
+        "keysc_out8_2",
+        "keysc_out9_0",
+        "keysc_out9_1",
+        "keysc_out9_2",
+        "keysc_out10_0",
+        "keysc_out10_1",
+        "keysc_out11_0",
+        "keysc_out11_1",
+};
+
+static const char * const lcd_groups[] = {
+        "lcd_data8",
+        "lcd_data9",
+        "lcd_data12",
+        "lcd_data16",
+        "lcd_data18",
+        "lcd_data24",
+        "lcd_display",
+        "lcd_lclk",
+        "lcd_sync",
+        "lcd_sys",
+};
+
+static const char * const lcd2_groups[] = {
+        "lcd2_data8",
+        "lcd2_data9",
+        "lcd2_data12",
+        "lcd2_data16",
+        "lcd2_data18",
+        "lcd2_data24",
+        "lcd2_sync_0",
+        "lcd2_sync_1",
+        "lcd2_sys_0",
+        "lcd2_sys_1",
+};
+
+static const char * const mmc0_groups[] = {
+        "mmc0_data1_0",
+        "mmc0_data4_0",
+        "mmc0_data8_0",
+        "mmc0_ctrl_0",
+        "mmc0_data1_1",
+        "mmc0_data4_1",
+        "mmc0_data8_1",
+        "mmc0_ctrl_1",
+};
+
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data_0",
+        "scifa2_clk_0",
+        "scifa2_ctrl_0",
+        "scifa2_data_1",
+        "scifa2_clk_1",
+        "scifa2_ctrl_1",
+};
+
+static const char * const scifa3_groups[] = {
+        "scifa3_data",
+        "scifa3_ctrl",
+};
+
+static const char * const scifa4_groups[] = {
+        "scifa4_data",
+        "scifa4_ctrl",
+};
+
+static const char * const scifa5_groups[] = {
+        "scifa5_data_0",
+        "scifa5_clk_0",
+        "scifa5_ctrl_0",
+        "scifa5_data_1",
+        "scifa5_clk_1",
+        "scifa5_ctrl_1",
+        "scifa5_data_2",
+        "scifa5_clk_2",
+        "scifa5_ctrl_2",
+};
+
+static const char * const scifa6_groups[] = {
+        "scifa6",
+};
+
+static const char * const scifa7_groups[] = {
+        "scifa7_data",
+        "scifa7_ctrl",
+};
+
+static const char * const scifb_groups[] = {
+        "scifb_data_0",
+        "scifb_clk_0",
+        "scifb_ctrl_0",
+        "scifb_data_1",
+        "scifb_clk_1",
+        "scifb_ctrl_1",
+};
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_ctrl",
+        "sdhi0_cd",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_data1",
+        "sdhi1_data4",
+        "sdhi1_ctrl",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_data1",
+        "sdhi2_data4",
+        "sdhi2_ctrl",
+};
+
+static const char * const usb_groups[] = {
+        "usb_vbus",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(bsc),
+        SH_PFC_FUNCTION(fsia),
+        SH_PFC_FUNCTION(fsib),
+        SH_PFC_FUNCTION(fsic),
+        SH_PFC_FUNCTION(fsid),
+        SH_PFC_FUNCTION(i2c2),
+        SH_PFC_FUNCTION(i2c3),
+        SH_PFC_FUNCTION(irda),
+        SH_PFC_FUNCTION(keysc),
+        SH_PFC_FUNCTION(lcd),
+        SH_PFC_FUNCTION(lcd2),
+        SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifa3),
+        SH_PFC_FUNCTION(scifa4),
+        SH_PFC_FUNCTION(scifa5),
+        SH_PFC_FUNCTION(scifa6),
+        SH_PFC_FUNCTION(scifa7),
+        SH_PFC_FUNCTION(scifb),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(usb),
+};
+
+#define PINMUX_FN_BASE  GPIO_FN_GPI0
+
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* Table 25-1 (Functions 0-7) */
-        GPIO_FN(VBUS_0),
         GPIO_FN(GPI0),
         GPIO_FN(GPI1),
         GPIO_FN(GPI2),
@@ -1556,19 +2948,12 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(GPI5),
         GPIO_FN(GPI6),
         GPIO_FN(GPI7),
-        GPIO_FN(SCIFA7_RXD),
-        GPIO_FN(SCIFA7_CTS_),
         GPIO_FN(GPO7), \
         GPIO_FN(MFG0_OUT2),
         GPIO_FN(GPO6), \
         GPIO_FN(MFG1_OUT2),
         GPIO_FN(GPO5), \
-        GPIO_FN(SCIFA0_SCK), \
-        GPIO_FN(FSICOSLDT3), \
         GPIO_FN(PORT16_VIO_CKOR),
-        GPIO_FN(SCIFA0_TXD),
-        GPIO_FN(SCIFA7_TXD),
-        GPIO_FN(SCIFA7_RTS_), \
         GPIO_FN(PORT19_VIO_CKO2),
         GPIO_FN(GPO0),
         GPIO_FN(GPO1),
@@ -1581,13 +2966,9 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(VINT),
         GPIO_FN(TCKON),
         GPIO_FN(XDVFS1), \
-        GPIO_FN(PORT27_I2C_SCL2), \
-        GPIO_FN(PORT27_I2C_SCL3), \
         GPIO_FN(MFG0_OUT1), \
         GPIO_FN(PORT27_IROUT),
         GPIO_FN(XDVFS2), \
-        GPIO_FN(PORT28_I2C_SDA2), \
-        GPIO_FN(PORT28_I2C_SDA3), \
         GPIO_FN(PORT28_TPU1TO1),
         GPIO_FN(SIM_RST), \
         GPIO_FN(PORT29_TPU1TO1),
@@ -1595,140 +2976,53 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(PORT30_VIO_CKOR),
         GPIO_FN(SIM_D), \
         GPIO_FN(PORT31_IROUT),
-        GPIO_FN(SCIFA4_TXD),
-        GPIO_FN(SCIFA4_RXD), \
         GPIO_FN(XWUP),
-        GPIO_FN(SCIFA4_RTS_),
-        GPIO_FN(SCIFA4_CTS_),
-        GPIO_FN(FSIBOBT), \
-        GPIO_FN(FSIBIBT),
-        GPIO_FN(FSIBOLR), \
-        GPIO_FN(FSIBILR),
-        GPIO_FN(FSIBOSLD),
-        GPIO_FN(FSIBISLD),
         GPIO_FN(VACK),
         GPIO_FN(XTAL1L),
-        GPIO_FN(SCIFA0_RTS_), \
-        GPIO_FN(FSICOSLDT2),
-        GPIO_FN(SCIFA0_RXD),
-        GPIO_FN(SCIFA0_CTS_), \
-        GPIO_FN(FSICOSLDT1),
-        GPIO_FN(FSICOBT), \
-        GPIO_FN(FSICIBT), \
-        GPIO_FN(FSIDOBT), \
-        GPIO_FN(FSIDIBT),
-        GPIO_FN(FSICOLR), \
-        GPIO_FN(FSICILR), \
-        GPIO_FN(FSIDOLR), \
-        GPIO_FN(FSIDILR),
-        GPIO_FN(FSICOSLD), \
-        GPIO_FN(PORT47_FSICSPDIF),
-        GPIO_FN(FSICISLD), \
-        GPIO_FN(FSIDISLD),
-        GPIO_FN(FSIACK), \
-        GPIO_FN(PORT49_IRDA_OUT), \
         GPIO_FN(PORT49_IROUT), \
-        GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIAOLR), \
         GPIO_FN(BBIF2_TSYNC2), \
         GPIO_FN(TPU2TO2), \
-        GPIO_FN(FSIAILR),
 
-        GPIO_FN(FSIAOBT), \
         GPIO_FN(BBIF2_TSCK2), \
         GPIO_FN(TPU2TO3), \
-        GPIO_FN(FSIAIBT),
-        GPIO_FN(FSIAOSLD), \
         GPIO_FN(BBIF2_TXD2),
-        GPIO_FN(FSIASPDIF), \
-        GPIO_FN(PORT53_IRDA_IN), \
         GPIO_FN(TPU3TO3), \
-        GPIO_FN(FSIBSPDIF), \
-        GPIO_FN(PORT53_FSICSPDIF),
-        GPIO_FN(FSIBCK), \
-        GPIO_FN(PORT54_IRDA_FIRSEL), \
         GPIO_FN(TPU3TO2), \
-        GPIO_FN(FSIBOMC), \
-        GPIO_FN(FSICCK), \
-        GPIO_FN(FSICOMC),
-        GPIO_FN(FSIAISLD), \
         GPIO_FN(TPU0TO0),
         GPIO_FN(A0), \
         GPIO_FN(BS_),
         GPIO_FN(A12), \
-        GPIO_FN(PORT58_KEYOUT7), \
         GPIO_FN(TPU4TO2),
         GPIO_FN(A13), \
-        GPIO_FN(PORT59_KEYOUT6), \
         GPIO_FN(TPU0TO1),
         GPIO_FN(A14), \
-        GPIO_FN(KEYOUT5),
         GPIO_FN(A15), \
-        GPIO_FN(KEYOUT4),
         GPIO_FN(A16), \
-        GPIO_FN(KEYOUT3), \
         GPIO_FN(MSIOF0_SS1),
         GPIO_FN(A17), \
-        GPIO_FN(KEYOUT2), \
         GPIO_FN(MSIOF0_TSYNC),
         GPIO_FN(A18), \
-        GPIO_FN(KEYOUT1), \
         GPIO_FN(MSIOF0_TSCK),
         GPIO_FN(A19), \
-        GPIO_FN(KEYOUT0), \
         GPIO_FN(MSIOF0_TXD),
         GPIO_FN(A20), \
-        GPIO_FN(KEYIN0), \
         GPIO_FN(MSIOF0_RSCK),
         GPIO_FN(A21), \
-        GPIO_FN(KEYIN1), \
         GPIO_FN(MSIOF0_RSYNC),
         GPIO_FN(A22), \
-        GPIO_FN(KEYIN2), \
         GPIO_FN(MSIOF0_MCK0),
         GPIO_FN(A23), \
-        GPIO_FN(KEYIN3), \
         GPIO_FN(MSIOF0_MCK1),
         GPIO_FN(A24), \
-        GPIO_FN(KEYIN4), \
         GPIO_FN(MSIOF0_RXD),
         GPIO_FN(A25), \
-        GPIO_FN(KEYIN5), \
         GPIO_FN(MSIOF0_SS2),
         GPIO_FN(A26), \
-        GPIO_FN(KEYIN6),
-        GPIO_FN(KEYIN7),
-        GPIO_FN(D0_NAF0),
-        GPIO_FN(D1_NAF1),
-        GPIO_FN(D2_NAF2),
-        GPIO_FN(D3_NAF3),
-        GPIO_FN(D4_NAF4),
-        GPIO_FN(D5_NAF5),
-        GPIO_FN(D6_NAF6),
-        GPIO_FN(D7_NAF7),
-        GPIO_FN(D8_NAF8),
-        GPIO_FN(D9_NAF9),
-        GPIO_FN(D10_NAF10),
-        GPIO_FN(D11_NAF11),
-        GPIO_FN(D12_NAF12),
-        GPIO_FN(D13_NAF13),
-        GPIO_FN(D14_NAF14),
-        GPIO_FN(D15_NAF15),
-        GPIO_FN(CS4_),
-        GPIO_FN(CS5A_), \
-        GPIO_FN(PORT91_RDWR),
-        GPIO_FN(CS5B_), \
         GPIO_FN(FCE1_),
-        GPIO_FN(CS6B_), \
         GPIO_FN(DACK0),
         GPIO_FN(FCE0_), \
-        GPIO_FN(CS6A_),
         GPIO_FN(WAIT_), \
         GPIO_FN(DREQ0),
-        GPIO_FN(RD__FSC),
-        GPIO_FN(WE0__FWE), \
-        GPIO_FN(RDWR_FWE),
-        GPIO_FN(WE1_),
         GPIO_FN(FRB),
         GPIO_FN(CKO),
         GPIO_FN(NBRSTOUT_),
@@ -1737,14 +3031,10 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(BBIF2_RXD),
         GPIO_FN(BBIF2_SYNC),
         GPIO_FN(BBIF2_SCK),
-        GPIO_FN(SCIFA3_CTS_), \
         GPIO_FN(MFG3_IN2),
-        GPIO_FN(SCIFA3_RXD), \
         GPIO_FN(MFG3_IN1),
         GPIO_FN(BBIF1_SS2), \
-        GPIO_FN(SCIFA3_RTS_), \
         GPIO_FN(MFG3_OUT1),
-        GPIO_FN(SCIFA3_TXD),
         GPIO_FN(HSI_RX_DATA), \
         GPIO_FN(BBIF1_RXD),
         GPIO_FN(HSI_TX_WAKE), \
@@ -1755,103 +3045,57 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(BBIF1_TXD),
         GPIO_FN(HSI_RX_READY), \
         GPIO_FN(BBIF1_RSCK), \
-        GPIO_FN(PORT115_I2C_SCL2), \
-        GPIO_FN(PORT115_I2C_SCL3),
         GPIO_FN(HSI_RX_WAKE), \
         GPIO_FN(BBIF1_RSYNC), \
-        GPIO_FN(PORT116_I2C_SDA2), \
-        GPIO_FN(PORT116_I2C_SDA3),
         GPIO_FN(HSI_RX_FLAG), \
         GPIO_FN(BBIF1_SS1), \
         GPIO_FN(BBIF1_FLOW),
         GPIO_FN(HSI_TX_FLAG),
         GPIO_FN(VIO_VD), \
-        GPIO_FN(PORT128_LCD2VSYN), \
         GPIO_FN(VIO2_VD), \
-        GPIO_FN(LCD2D0),
 
         GPIO_FN(VIO_HD), \
-        GPIO_FN(PORT129_LCD2HSYN), \
-        GPIO_FN(PORT129_LCD2CS_), \
         GPIO_FN(VIO2_HD), \
-        GPIO_FN(LCD2D1),
         GPIO_FN(VIO_D0), \
         GPIO_FN(PORT130_MSIOF2_RXD), \
-        GPIO_FN(LCD2D10),
         GPIO_FN(VIO_D1), \
-        GPIO_FN(PORT131_KEYOUT6), \
         GPIO_FN(PORT131_MSIOF2_SS1), \
-        GPIO_FN(PORT131_KEYOUT11), \
-        GPIO_FN(LCD2D11),
         GPIO_FN(VIO_D2), \
-        GPIO_FN(PORT132_KEYOUT7), \
         GPIO_FN(PORT132_MSIOF2_SS2), \
-        GPIO_FN(PORT132_KEYOUT10), \
-        GPIO_FN(LCD2D12),
         GPIO_FN(VIO_D3), \
         GPIO_FN(MSIOF2_TSYNC), \
-        GPIO_FN(LCD2D13),
         GPIO_FN(VIO_D4), \
         GPIO_FN(MSIOF2_TXD), \
-        GPIO_FN(LCD2D14),
         GPIO_FN(VIO_D5), \
         GPIO_FN(MSIOF2_TSCK), \
-        GPIO_FN(LCD2D15),
         GPIO_FN(VIO_D6), \
-        GPIO_FN(PORT136_KEYOUT8), \
-        GPIO_FN(LCD2D16),
         GPIO_FN(VIO_D7), \
-        GPIO_FN(PORT137_KEYOUT9), \
-        GPIO_FN(LCD2D17),
         GPIO_FN(VIO_D8), \
-        GPIO_FN(PORT138_KEYOUT8), \
         GPIO_FN(VIO2_D0), \
-        GPIO_FN(LCD2D6),
         GPIO_FN(VIO_D9), \
-        GPIO_FN(PORT139_KEYOUT9), \
         GPIO_FN(VIO2_D1), \
-        GPIO_FN(LCD2D7),
         GPIO_FN(VIO_D10), \
         GPIO_FN(TPU0TO2), \
         GPIO_FN(VIO2_D2), \
-        GPIO_FN(LCD2D8),
         GPIO_FN(VIO_D11), \
         GPIO_FN(TPU0TO3), \
         GPIO_FN(VIO2_D3), \
-        GPIO_FN(LCD2D9),
         GPIO_FN(VIO_D12), \
-        GPIO_FN(PORT142_KEYOUT10), \
         GPIO_FN(VIO2_D4), \
-        GPIO_FN(LCD2D2),
         GPIO_FN(VIO_D13), \
-        GPIO_FN(PORT143_KEYOUT11), \
-        GPIO_FN(PORT143_KEYOUT6), \
         GPIO_FN(VIO2_D5), \
-        GPIO_FN(LCD2D3),
         GPIO_FN(VIO_D14), \
-        GPIO_FN(PORT144_KEYOUT7), \
         GPIO_FN(VIO2_D6), \
-        GPIO_FN(LCD2D4),
         GPIO_FN(VIO_D15), \
         GPIO_FN(TPU1TO3), \
-        GPIO_FN(PORT145_LCD2DISP), \
-        GPIO_FN(PORT145_LCD2RS), \
         GPIO_FN(VIO2_D7), \
-        GPIO_FN(LCD2D5),
         GPIO_FN(VIO_CLK), \
-        GPIO_FN(LCD2DCK), \
-        GPIO_FN(PORT146_LCD2WR_), \
         GPIO_FN(VIO2_CLK), \
-        GPIO_FN(LCD2D18),
         GPIO_FN(VIO_FIELD), \
-        GPIO_FN(LCD2RD_), \
         GPIO_FN(VIO2_FIELD), \
-        GPIO_FN(LCD2D19),
         GPIO_FN(VIO_CKO),
         GPIO_FN(A27), \
-        GPIO_FN(PORT149_RDWR), \
         GPIO_FN(MFG0_IN1), \
-        GPIO_FN(PORT149_KEYOUT9),
         GPIO_FN(MFG0_IN2),
         GPIO_FN(TS_SPSYNC3), \
         GPIO_FN(MSIOF2_RSCK),
@@ -1860,201 +3104,105 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(TPU1TO2), \
         GPIO_FN(TS_SDEN3), \
         GPIO_FN(PORT153_MSIOF2_SS1),
-        GPIO_FN(SCIFA2_TXD1), \
         GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(SCIFA2_RXD1), \
         GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(SCIFA2_RTS1_), \
         GPIO_FN(PORT156_MSIOF2_SS2),
-        GPIO_FN(SCIFA2_CTS1_), \
         GPIO_FN(PORT157_MSIOF2_RXD),
         GPIO_FN(DINT_), \
-        GPIO_FN(SCIFA2_SCK1), \
         GPIO_FN(TS_SCK3),
-        GPIO_FN(PORT159_SCIFB_SCK), \
-        GPIO_FN(PORT159_SCIFA5_SCK), \
         GPIO_FN(NMI),
-        GPIO_FN(PORT160_SCIFB_TXD), \
-        GPIO_FN(PORT160_SCIFA5_TXD),
-        GPIO_FN(PORT161_SCIFB_CTS_), \
-        GPIO_FN(PORT161_SCIFA5_CTS_),
-        GPIO_FN(PORT162_SCIFB_RXD), \
-        GPIO_FN(PORT162_SCIFA5_RXD),
-        GPIO_FN(PORT163_SCIFB_RTS_), \
-        GPIO_FN(PORT163_SCIFA5_RTS_), \
         GPIO_FN(TPU3TO0),
-        GPIO_FN(LCDD0),
-        GPIO_FN(LCDD1), \
-        GPIO_FN(PORT193_SCIFA5_CTS_), \
         GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(LCDD2), \
-        GPIO_FN(PORT194_SCIFA5_RTS_), \
         GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(LCDD3), \
-        GPIO_FN(PORT195_SCIFA5_RXD), \
         GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(LCDD4), \
-        GPIO_FN(PORT196_SCIFA5_TXD),
-        GPIO_FN(LCDD5), \
-        GPIO_FN(PORT197_SCIFA5_SCK), \
         GPIO_FN(MFG2_OUT2), \
         GPIO_FN(TPU2TO1),
-        GPIO_FN(LCDD6),
-        GPIO_FN(LCDD7), \
         GPIO_FN(TPU4TO1), \
         GPIO_FN(MFG4_OUT2),
-        GPIO_FN(LCDD8), \
         GPIO_FN(D16),
-        GPIO_FN(LCDD9), \
         GPIO_FN(D17),
-        GPIO_FN(LCDD10), \
         GPIO_FN(D18),
-        GPIO_FN(LCDD11), \
         GPIO_FN(D19),
-        GPIO_FN(LCDD12), \
         GPIO_FN(D20),
-        GPIO_FN(LCDD13), \
         GPIO_FN(D21),
-        GPIO_FN(LCDD14), \
         GPIO_FN(D22),
-        GPIO_FN(LCDD15), \
         GPIO_FN(PORT207_MSIOF0L_SS1), \
         GPIO_FN(D23),
-        GPIO_FN(LCDD16), \
         GPIO_FN(PORT208_MSIOF0L_SS2), \
         GPIO_FN(D24),
-        GPIO_FN(LCDD17), \
         GPIO_FN(D25),
-        GPIO_FN(LCDD18), \
         GPIO_FN(DREQ2), \
         GPIO_FN(PORT210_MSIOF0L_SS1), \
         GPIO_FN(D26),
-        GPIO_FN(LCDD19), \
         GPIO_FN(PORT211_MSIOF0L_SS2), \
         GPIO_FN(D27),
-        GPIO_FN(LCDD20), \
         GPIO_FN(TS_SPSYNC1), \
         GPIO_FN(MSIOF0L_MCK0), \
         GPIO_FN(D28),
-        GPIO_FN(LCDD21), \
         GPIO_FN(TS_SDAT1), \
         GPIO_FN(MSIOF0L_MCK1), \
         GPIO_FN(D29),
-        GPIO_FN(LCDD22), \
         GPIO_FN(TS_SDEN1), \
         GPIO_FN(MSIOF0L_RSCK), \
         GPIO_FN(D30),
-        GPIO_FN(LCDD23), \
         GPIO_FN(TS_SCK1), \
         GPIO_FN(MSIOF0L_RSYNC), \
         GPIO_FN(D31),
-        GPIO_FN(LCDDCK), \
-        GPIO_FN(LCDWR_),
-        GPIO_FN(LCDRD_), \
         GPIO_FN(DACK2), \
-        GPIO_FN(PORT217_LCD2RS), \
         GPIO_FN(MSIOF0L_TSYNC), \
         GPIO_FN(VIO2_FIELD3), \
-        GPIO_FN(PORT217_LCD2DISP),
-        GPIO_FN(LCDHSYN), \
-        GPIO_FN(LCDCS_), \
-        GPIO_FN(LCDCS2_), \
         GPIO_FN(DACK3), \
         GPIO_FN(PORT218_VIO_CKOR),
-        GPIO_FN(LCDDISP), \
-        GPIO_FN(LCDRS), \
-        GPIO_FN(PORT219_LCD2WR_), \
         GPIO_FN(DREQ3), \
         GPIO_FN(MSIOF0L_TSCK), \
         GPIO_FN(VIO2_CLK3), \
-        GPIO_FN(LCD2DCK_2),
-        GPIO_FN(LCDVSYN), \
-        GPIO_FN(LCDVSYN2),
-        GPIO_FN(LCDLCLK), \
         GPIO_FN(DREQ1), \
-        GPIO_FN(PORT221_LCD2CS_), \
         GPIO_FN(PWEN), \
         GPIO_FN(MSIOF0L_RXD), \
         GPIO_FN(VIO2_HD3), \
-        GPIO_FN(PORT221_LCD2HSYN),
-        GPIO_FN(LCDDON), \
-        GPIO_FN(LCDDON2), \
         GPIO_FN(DACK1), \
         GPIO_FN(OVCN), \
         GPIO_FN(MSIOF0L_TXD), \
         GPIO_FN(VIO2_VD3), \
-        GPIO_FN(PORT222_LCD2VSYN),
 
-        GPIO_FN(SCIFA1_TXD), \
         GPIO_FN(OVCN2),
         GPIO_FN(EXTLP), \
-        GPIO_FN(SCIFA1_SCK), \
         GPIO_FN(PORT226_VIO_CKO2),
-        GPIO_FN(SCIFA1_RTS_), \
         GPIO_FN(IDIN),
-        GPIO_FN(SCIFA1_RXD),
-        GPIO_FN(SCIFA1_CTS_), \
         GPIO_FN(MFG1_IN1),
         GPIO_FN(MSIOF1_TXD), \
-        GPIO_FN(SCIFA2_TXD2),
         GPIO_FN(MSIOF1_TSYNC), \
-        GPIO_FN(SCIFA2_CTS2_),
         GPIO_FN(MSIOF1_TSCK), \
-        GPIO_FN(SCIFA2_SCK2),
         GPIO_FN(MSIOF1_RXD), \
-        GPIO_FN(SCIFA2_RXD2),
         GPIO_FN(MSIOF1_RSCK), \
-        GPIO_FN(SCIFA2_RTS2_), \
         GPIO_FN(VIO2_CLK2), \
-        GPIO_FN(LCD2D20),
         GPIO_FN(MSIOF1_RSYNC), \
         GPIO_FN(MFG1_IN2), \
         GPIO_FN(VIO2_VD2), \
-        GPIO_FN(LCD2D21),
         GPIO_FN(MSIOF1_MCK0), \
-        GPIO_FN(PORT236_I2C_SDA2),
         GPIO_FN(MSIOF1_MCK1), \
-        GPIO_FN(PORT237_I2C_SCL2),
         GPIO_FN(MSIOF1_SS1), \
         GPIO_FN(VIO2_FIELD2), \
-        GPIO_FN(LCD2D22),
         GPIO_FN(MSIOF1_SS2), \
         GPIO_FN(VIO2_HD2), \
-        GPIO_FN(LCD2D23),
-        GPIO_FN(SCIFA6_TXD),
-        GPIO_FN(PORT241_IRDA_OUT), \
         GPIO_FN(PORT241_IROUT), \
         GPIO_FN(MFG4_OUT1), \
         GPIO_FN(TPU4TO0),
-        GPIO_FN(PORT242_IRDA_IN), \
         GPIO_FN(MFG4_IN2),
-        GPIO_FN(PORT243_IRDA_FIRSEL), \
         GPIO_FN(PORT243_VIO_CKO2),
-        GPIO_FN(PORT244_SCIFA5_CTS_), \
         GPIO_FN(MFG2_IN1), \
-        GPIO_FN(PORT244_SCIFB_CTS_), \
         GPIO_FN(MSIOF2R_RXD),
-        GPIO_FN(PORT245_SCIFA5_RTS_), \
         GPIO_FN(MFG2_IN2), \
-        GPIO_FN(PORT245_SCIFB_RTS_), \
         GPIO_FN(MSIOF2R_TXD),
-        GPIO_FN(PORT246_SCIFA5_RXD), \
         GPIO_FN(MFG1_OUT1), \
-        GPIO_FN(PORT246_SCIFB_RXD), \
         GPIO_FN(TPU1TO0),
-        GPIO_FN(PORT247_SCIFA5_TXD), \
         GPIO_FN(MFG3_OUT2), \
-        GPIO_FN(PORT247_SCIFB_TXD), \
         GPIO_FN(TPU3TO1),
-        GPIO_FN(PORT248_SCIFA5_SCK), \
         GPIO_FN(MFG2_OUT1), \
-        GPIO_FN(PORT248_SCIFB_SCK), \
         GPIO_FN(TPU2TO0), \
-        GPIO_FN(PORT248_I2C_SCL3), \
         GPIO_FN(MSIOF2R_TSCK),
         GPIO_FN(PORT249_IROUT), \
         GPIO_FN(MFG4_IN1), \
-        GPIO_FN(PORT249_I2C_SDA3), \
         GPIO_FN(MSIOF2R_TSYNC),
         GPIO_FN(SDHICLK0),
         GPIO_FN(SDHICD0),
@@ -2172,56 +3320,24 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(IRQ9_MEM_INT),
         GPIO_FN(IRQ9_MCP_INT),
         GPIO_FN(A11),
-        GPIO_FN(KEYOUT8),
         GPIO_FN(TPU4TO3),
         GPIO_FN(RESETA_N_PU_ON),
         GPIO_FN(RESETA_N_PU_OFF),
         GPIO_FN(EDBGREQ_PD),
         GPIO_FN(EDBGREQ_PU),
+};
 
-        /* Functions with pull-ups */
-        GPIO_FN(KEYIN0_PU),
-        GPIO_FN(KEYIN1_PU),
-        GPIO_FN(KEYIN2_PU),
-        GPIO_FN(KEYIN3_PU),
-        GPIO_FN(KEYIN4_PU),
-        GPIO_FN(KEYIN5_PU),
-        GPIO_FN(KEYIN6_PU),
-        GPIO_FN(KEYIN7_PU),
-        GPIO_FN(SDHICD0_PU),
-        GPIO_FN(SDHID0_0_PU),
-        GPIO_FN(SDHID0_1_PU),
-        GPIO_FN(SDHID0_2_PU),
-        GPIO_FN(SDHID0_3_PU),
-        GPIO_FN(SDHICMD0_PU),
-        GPIO_FN(SDHIWP0_PU),
-        GPIO_FN(SDHID1_0_PU),
-        GPIO_FN(SDHID1_1_PU),
-        GPIO_FN(SDHID1_2_PU),
-        GPIO_FN(SDHID1_3_PU),
-        GPIO_FN(SDHICMD1_PU),
-        GPIO_FN(SDHID2_0_PU),
-        GPIO_FN(SDHID2_1_PU),
-        GPIO_FN(SDHID2_2_PU),
-        GPIO_FN(SDHID2_3_PU),
-        GPIO_FN(SDHICMD2_PU),
-        GPIO_FN(MMCCMD0_PU),
-        GPIO_FN(MMCCMD1_PU),
-        GPIO_FN(MMCD0_0_PU),
-        GPIO_FN(MMCD0_1_PU),
-        GPIO_FN(MMCD0_2_PU),
-        GPIO_FN(MMCD0_3_PU),
-        GPIO_FN(MMCD0_4_PU),
-        GPIO_FN(MMCD0_5_PU),
-        GPIO_FN(MMCD0_6_PU),
-        GPIO_FN(MMCD0_7_PU),
-        GPIO_FN(FSIACK_PU),
-        GPIO_FN(FSIAILR_PU),
-        GPIO_FN(FSIAIBT_PU),
-        GPIO_FN(FSIAISLD_PU),
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+#undef PORTCR
+#define PORTCR(nr, reg)                                                 \
+        {                                                               \
+                PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
+                        _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
+                                PORT##nr##_FN0, PORT##nr##_FN1,         \
+                                PORT##nr##_FN2, PORT##nr##_FN3,         \
+                                PORT##nr##_FN4, PORT##nr##_FN5,         \
+                                PORT##nr##_FN6, PORT##nr##_FN7 }        \
+        }
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0, 0xe6050000), /* PORT0CR */
         PORTCR(1, 0xe6050001), /* PORT1CR */
         PORTCR(2, 0xe6050002), /* PORT2CR */
@@ -2629,7 +3745,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         { },
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
                         PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
                         PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
@@ -2737,56 +3853,112 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
 #define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
 #define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
 
-static struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
-        PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
-        PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
-};
-
-struct sh_pfc_soc_info sh73a0_pinmux_info = {
+static const struct pinmux_irq pinmux_irqs[] = {
+        PINMUX_IRQ(EXT_IRQ16H(19), 9),
+        PINMUX_IRQ(EXT_IRQ16L(1), 10),
+        PINMUX_IRQ(EXT_IRQ16L(0), 11),
+        PINMUX_IRQ(EXT_IRQ16H(18), 13),
+        PINMUX_IRQ(EXT_IRQ16H(20), 14),
+        PINMUX_IRQ(EXT_IRQ16H(21), 15),
+        PINMUX_IRQ(EXT_IRQ16H(31), 26),
+        PINMUX_IRQ(EXT_IRQ16H(30), 27),
+        PINMUX_IRQ(EXT_IRQ16H(29), 28),
+        PINMUX_IRQ(EXT_IRQ16H(22), 40),
+        PINMUX_IRQ(EXT_IRQ16H(23), 53),
+        PINMUX_IRQ(EXT_IRQ16L(10), 54),
+        PINMUX_IRQ(EXT_IRQ16L(9), 56),
+        PINMUX_IRQ(EXT_IRQ16H(26), 115),
+        PINMUX_IRQ(EXT_IRQ16H(27), 116),
+        PINMUX_IRQ(EXT_IRQ16H(28), 117),
+        PINMUX_IRQ(EXT_IRQ16H(24), 118),
+        PINMUX_IRQ(EXT_IRQ16L(6), 147),
+        PINMUX_IRQ(EXT_IRQ16L(2), 149),
+        PINMUX_IRQ(EXT_IRQ16L(7), 150),
+        PINMUX_IRQ(EXT_IRQ16L(12), 156),
+        PINMUX_IRQ(EXT_IRQ16L(4), 159),
+        PINMUX_IRQ(EXT_IRQ16H(25), 164),
+        PINMUX_IRQ(EXT_IRQ16L(8), 223),
+        PINMUX_IRQ(EXT_IRQ16L(3), 224),
+        PINMUX_IRQ(EXT_IRQ16L(5), 227),
+        PINMUX_IRQ(EXT_IRQ16H(17), 234),
+        PINMUX_IRQ(EXT_IRQ16L(11), 238),
+        PINMUX_IRQ(EXT_IRQ16L(13), 239),
+        PINMUX_IRQ(EXT_IRQ16H(16), 249),
+        PINMUX_IRQ(EXT_IRQ16L(14), 251),
+        PINMUX_IRQ(EXT_IRQ16L(9), 308),
+};
+
+#define PORTnCR_PULMD_OFF       (0 << 6)
+#define PORTnCR_PULMD_DOWN      (2 << 6)
+#define PORTnCR_PULMD_UP        (3 << 6)
+#define PORTnCR_PULMD_MASK      (3 << 6)
+
+static const unsigned int sh73a0_portcr_offsets[] = {
+        0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
+        0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
+};
+
+static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+        void __iomem *addr = pfc->window->virt
+                           + sh73a0_portcr_offsets[pin >> 5] + pin;
+        u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+        switch (value) {
+        case PORTnCR_PULMD_UP:
+                return PIN_CONFIG_BIAS_PULL_UP;
+        case PORTnCR_PULMD_DOWN:
+                return PIN_CONFIG_BIAS_PULL_DOWN;
+        case PORTnCR_PULMD_OFF:
+        default:
+                return PIN_CONFIG_BIAS_DISABLE;
+        }
+}
+
+static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+                                   unsigned int bias)
+{
+        void __iomem *addr = pfc->window->virt
+                           + sh73a0_portcr_offsets[pin >> 5] + pin;
+        u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+        switch (bias) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+                value |= PORTnCR_PULMD_UP;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                value |= PORTnCR_PULMD_DOWN;
+                break;
+        }
+
+        iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
+        .get_bias = sh73a0_pinmux_get_bias,
+        .set_bias = sh73a0_pinmux_set_bias,
+};
+
+const struct sh_pfc_soc_info sh73a0_pinmux_info = {
         .name = "sh73a0_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .ops = &sh73a0_pinmux_ops,
+
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PORT0,
-        .last_gpio = GPIO_FN_FSIAISLD_PU,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .ranges = pinmux_ranges,
+        .nr_ranges = ARRAY_SIZE(pinmux_ranges),
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 10872ed688a6..52e9f6be665f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -262,7 +262,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
         /* PTA GPIO */
         PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
         PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
@@ -606,7 +606,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
         /* PTA */
         PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
         PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -759,202 +759,205 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
         PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
         PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* BSC */
-        PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
-        PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
-        PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
-        PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
-        PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
-        PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
-        PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
-        PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
-        PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
-        PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
-        PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
-        PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
-        PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
-        PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
-        PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
-        PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
-        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
-        PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
-        PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
-        PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
-        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
-        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
-        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
-        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
-        PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
-        PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
-        PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
-        PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
-        PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
+        GPIO_FN(D31),
+        GPIO_FN(D30),
+        GPIO_FN(D29),
+        GPIO_FN(D28),
+        GPIO_FN(D27),
+        GPIO_FN(D26),
+        GPIO_FN(D25),
+        GPIO_FN(D24),
+        GPIO_FN(D23),
+        GPIO_FN(D22),
+        GPIO_FN(D21),
+        GPIO_FN(D20),
+        GPIO_FN(D19),
+        GPIO_FN(D18),
+        GPIO_FN(D17),
+        GPIO_FN(D16),
+        GPIO_FN(IOIS16),
+        GPIO_FN(RAS),
+        GPIO_FN(CAS),
+        GPIO_FN(CKE),
+        GPIO_FN(CS5B_CE1A),
+        GPIO_FN(CS6B_CE1B),
+        GPIO_FN(A25),
+        GPIO_FN(A24),
+        GPIO_FN(A23),
+        GPIO_FN(A22),
+        GPIO_FN(A21),
+        GPIO_FN(A20),
+        GPIO_FN(A19),
+        GPIO_FN(A0),
+        GPIO_FN(REFOUT),
+        GPIO_FN(IRQOUT),
 
         /* LCDC */
-        PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK),
+        GPIO_FN(LCD_DATA15),
+        GPIO_FN(LCD_DATA14),
+        GPIO_FN(LCD_DATA13),
+        GPIO_FN(LCD_DATA12),
+        GPIO_FN(LCD_DATA11),
+        GPIO_FN(LCD_DATA10),
+        GPIO_FN(LCD_DATA9),
+        GPIO_FN(LCD_DATA8),
+        GPIO_FN(LCD_DATA7),
+        GPIO_FN(LCD_DATA6),
+        GPIO_FN(LCD_DATA5),
+        GPIO_FN(LCD_DATA4),
+        GPIO_FN(LCD_DATA3),
+        GPIO_FN(LCD_DATA2),
+        GPIO_FN(LCD_DATA1),
+        GPIO_FN(LCD_DATA0),
+        GPIO_FN(LCD_M_DISP),
+        GPIO_FN(LCD_CL1),
+        GPIO_FN(LCD_CL2),
+        GPIO_FN(LCD_DON),
+        GPIO_FN(LCD_FLM),
+        GPIO_FN(LCD_VEPWC),
+        GPIO_FN(LCD_VCPWC),
 
         /* AFEIF */
-        PINMUX_GPIO(GPIO_FN_AFE_RXIN, AFE_RXIN_MARK),
-        PINMUX_GPIO(GPIO_FN_AFE_RDET, AFE_RDET_MARK),
-        PINMUX_GPIO(GPIO_FN_AFE_FS, AFE_FS_MARK),
-        PINMUX_GPIO(GPIO_FN_AFE_TXOUT, AFE_TXOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_AFE_SCLK, AFE_SCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_AFE_RLYCNT, AFE_RLYCNT_MARK),
-        PINMUX_GPIO(GPIO_FN_AFE_HC1, AFE_HC1_MARK),
+        GPIO_FN(AFE_RXIN),
+        GPIO_FN(AFE_RDET),
+        GPIO_FN(AFE_FS),
+        GPIO_FN(AFE_TXOUT),
+        GPIO_FN(AFE_SCLK),
+        GPIO_FN(AFE_RLYCNT),
+        GPIO_FN(AFE_HC1),
 
         /* IIC */
-        PINMUX_GPIO(GPIO_FN_IIC_SCL, IIC_SCL_MARK),
-        PINMUX_GPIO(GPIO_FN_IIC_SDA, IIC_SDA_MARK),
+        GPIO_FN(IIC_SCL),
+        GPIO_FN(IIC_SDA),
 
         /* DAC */
-        PINMUX_GPIO(GPIO_FN_DA1, DA1_MARK),
-        PINMUX_GPIO(GPIO_FN_DA0, DA0_MARK),
+        GPIO_FN(DA1),
+        GPIO_FN(DA0),
 
         /* ADC */
-        PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK),
-        PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK),
-        PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK),
-        PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK),
-        PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
+        GPIO_FN(AN3),
+        GPIO_FN(AN2),
+        GPIO_FN(AN1),
+        GPIO_FN(AN0),
+        GPIO_FN(ADTRG),
 
         /* USB */
-        PINMUX_GPIO(GPIO_FN_USB1D_RCV, USB1D_RCV_MARK),
-        PINMUX_GPIO(GPIO_FN_USB1D_TXSE0, USB1D_TXSE0_MARK),
-        PINMUX_GPIO(GPIO_FN_USB1D_TXDPLS, USB1D_TXDPLS_MARK),
-        PINMUX_GPIO(GPIO_FN_USB1D_DMNS, USB1D_DMNS_MARK),
-        PINMUX_GPIO(GPIO_FN_USB1D_DPLS, USB1D_DPLS_MARK),
-        PINMUX_GPIO(GPIO_FN_USB1D_SPEED, USB1D_SPEED_MARK),
-        PINMUX_GPIO(GPIO_FN_USB1D_TXENL, USB1D_TXENL_MARK),
-
-        PINMUX_GPIO(GPIO_FN_USB2_PWR_EN, USB2_PWR_EN_MARK),
-        PINMUX_GPIO(GPIO_FN_USB1_PWR_EN_USBF_UPLUP,
-                    USB1_PWR_EN_USBF_UPLUP_MARK),
-        PINMUX_GPIO(GPIO_FN_USB1D_SUSPEND, USB1D_SUSPEND_MARK),
+        GPIO_FN(USB1D_RCV),
+        GPIO_FN(USB1D_TXSE0),
+        GPIO_FN(USB1D_TXDPLS),
+        GPIO_FN(USB1D_DMNS),
+        GPIO_FN(USB1D_DPLS),
+        GPIO_FN(USB1D_SPEED),
+        GPIO_FN(USB1D_TXENL),
+
+        GPIO_FN(USB2_PWR_EN),
+        GPIO_FN(USB1_PWR_EN_USBF_UPLUP),
+        GPIO_FN(USB1D_SUSPEND),
 
         /* INTC */
-        PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3_IRL3, IRQ3_IRL3_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2_IRL2, IRQ2_IRL2_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1_IRL1, IRQ1_IRL1_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0_IRL0, IRQ0_IRL0_MARK),
+        GPIO_FN(IRQ5),
+        GPIO_FN(IRQ4),
+        GPIO_FN(IRQ3_IRL3),
+        GPIO_FN(IRQ2_IRL2),
+        GPIO_FN(IRQ1_IRL1),
+        GPIO_FN(IRQ0_IRL0),
 
         /* PCC */
-        PINMUX_GPIO(GPIO_FN_PCC_REG, PCC_REG_MARK),
-        PINMUX_GPIO(GPIO_FN_PCC_DRV, PCC_DRV_MARK),
-        PINMUX_GPIO(GPIO_FN_PCC_BVD2, PCC_BVD2_MARK),
-        PINMUX_GPIO(GPIO_FN_PCC_BVD1, PCC_BVD1_MARK),
-        PINMUX_GPIO(GPIO_FN_PCC_CD2, PCC_CD2_MARK),
-        PINMUX_GPIO(GPIO_FN_PCC_CD1, PCC_CD1_MARK),
-        PINMUX_GPIO(GPIO_FN_PCC_RESET, PCC_RESET_MARK),
-        PINMUX_GPIO(GPIO_FN_PCC_RDY, PCC_RDY_MARK),
-        PINMUX_GPIO(GPIO_FN_PCC_VS2, PCC_VS2_MARK),
-        PINMUX_GPIO(GPIO_FN_PCC_VS1, PCC_VS1_MARK),
+        GPIO_FN(PCC_REG),
+        GPIO_FN(PCC_DRV),
+        GPIO_FN(PCC_BVD2),
+        GPIO_FN(PCC_BVD1),
+        GPIO_FN(PCC_CD2),
+        GPIO_FN(PCC_CD1),
+        GPIO_FN(PCC_RESET),
+        GPIO_FN(PCC_RDY),
+        GPIO_FN(PCC_VS2),
+        GPIO_FN(PCC_VS1),
 
         /* HUDI */
-        PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_ASEBRKAK, ASEBRKAK_MARK),
-        PINMUX_GPIO(GPIO_FN_TRST, TRST_MARK),
-        PINMUX_GPIO(GPIO_FN_TMS, TMS_MARK),
-        PINMUX_GPIO(GPIO_FN_TDO, TDO_MARK),
-        PINMUX_GPIO(GPIO_FN_TDI, TDI_MARK),
-        PINMUX_GPIO(GPIO_FN_TCK, TCK_MARK),
+        GPIO_FN(AUDATA3),
+        GPIO_FN(AUDATA2),
+        GPIO_FN(AUDATA1),
+        GPIO_FN(AUDATA0),
+        GPIO_FN(AUDCK),
+        GPIO_FN(AUDSYNC),
+        GPIO_FN(ASEBRKAK),
+        GPIO_FN(TRST),
+        GPIO_FN(TMS),
+        GPIO_FN(TDO),
+        GPIO_FN(TDI),
+        GPIO_FN(TCK),
 
         /* DMAC */
-        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
+        GPIO_FN(DACK1),
+        GPIO_FN(DREQ1),
+        GPIO_FN(DACK0),
+        GPIO_FN(DREQ0),
+        GPIO_FN(TEND1),
+        GPIO_FN(TEND0),
 
         /* SIOF0 */
-        PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF0_MCLK, SIOF0_MCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK),
+        GPIO_FN(SIOF0_SYNC),
+        GPIO_FN(SIOF0_MCLK),
+        GPIO_FN(SIOF0_TXD),
+        GPIO_FN(SIOF0_RXD),
+        GPIO_FN(SIOF0_SCK),
 
         /* SIOF1 */
-        PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF1_MCLK, SIOF1_MCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK),
+        GPIO_FN(SIOF1_SYNC),
+        GPIO_FN(SIOF1_MCLK),
+        GPIO_FN(SIOF1_TXD),
+        GPIO_FN(SIOF1_RXD),
+        GPIO_FN(SIOF1_SCK),
 
         /* SCIF0 */
-        PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
+        GPIO_FN(SCIF0_TXD),
+        GPIO_FN(SCIF0_RXD),
+        GPIO_FN(SCIF0_RTS),
+        GPIO_FN(SCIF0_CTS),
+        GPIO_FN(SCIF0_SCK),
 
         /* SCIF1 */
-        PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
+        GPIO_FN(SCIF1_TXD),
+        GPIO_FN(SCIF1_RXD),
+        GPIO_FN(SCIF1_RTS),
+        GPIO_FN(SCIF1_CTS),
+        GPIO_FN(SCIF1_SCK),
 
         /* TPU */
-        PINMUX_GPIO(GPIO_FN_TPU_TO1, TPU_TO1_MARK),
-        PINMUX_GPIO(GPIO_FN_TPU_TO0, TPU_TO0_MARK),
-        PINMUX_GPIO(GPIO_FN_TPU_TI3B, TPU_TI3B_MARK),
-        PINMUX_GPIO(GPIO_FN_TPU_TI3A, TPU_TI3A_MARK),
-        PINMUX_GPIO(GPIO_FN_TPU_TI2B, TPU_TI2B_MARK),
-        PINMUX_GPIO(GPIO_FN_TPU_TI2A, TPU_TI2A_MARK),
-        PINMUX_GPIO(GPIO_FN_TPU_TO3, TPU_TO3_MARK),
-        PINMUX_GPIO(GPIO_FN_TPU_TO2, TPU_TO2_MARK),
+        GPIO_FN(TPU_TO1),
+        GPIO_FN(TPU_TO0),
+        GPIO_FN(TPU_TI3B),
+        GPIO_FN(TPU_TI3A),
+        GPIO_FN(TPU_TI2B),
+        GPIO_FN(TPU_TI2A),
+        GPIO_FN(TPU_TO3),
+        GPIO_FN(TPU_TO2),
 
         /* SIM */
-        PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
-        PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
+        GPIO_FN(SIM_D),
+        GPIO_FN(SIM_CLK),
+        GPIO_FN(SIM_RST),
 
         /* MMC */
-        PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK),
+        GPIO_FN(MMC_DAT),
+        GPIO_FN(MMC_CMD),
+        GPIO_FN(MMC_CLK),
+        GPIO_FN(MMC_VDDON),
+        GPIO_FN(MMC_ODMOD),
 
         /* SYSC */
-        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
-        PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
+        GPIO_FN(STATUS0),
+        GPIO_FN(STATUS1),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
                 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
                 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
@@ -1138,7 +1141,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         {}
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PADR", 0xa4050140, 8) {
                 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
                 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1214,20 +1217,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info sh7720_pinmux_info = {
+const struct sh_pfc_soc_info sh7720_pinmux_info = {
         .name = "sh7720_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
         .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PTA7,
-        .last_gpio = GPIO_FN_STATUS1,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index 2de0929315e6..32034387477b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -296,7 +296,7 @@ enum {
         PINMUX_FUNCTION_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
         /* PTA */
         PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT),
         PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD),
@@ -787,7 +787,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
         /* PTA */
         PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
         PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -982,289 +982,293 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
         PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
         PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* SCIF0 */
-        PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
+        GPIO_FN(SCIF0_TXD),
+        GPIO_FN(SCIF0_RXD),
+        GPIO_FN(SCIF0_RTS),
+        GPIO_FN(SCIF0_CTS),
+        GPIO_FN(SCIF0_SCK),
 
         /* SCIF1 */
-        PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
+        GPIO_FN(SCIF1_TXD),
+        GPIO_FN(SCIF1_RXD),
+        GPIO_FN(SCIF1_RTS),
+        GPIO_FN(SCIF1_CTS),
+        GPIO_FN(SCIF1_SCK),
 
         /* SCIF2 */
-        PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK),
+        GPIO_FN(SCIF2_TXD),
+        GPIO_FN(SCIF2_RXD),
+        GPIO_FN(SCIF2_RTS),
+        GPIO_FN(SCIF2_CTS),
+        GPIO_FN(SCIF2_SCK),
 
         /* SIO */
-        PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK),
+        GPIO_FN(SIOTXD),
+        GPIO_FN(SIORXD),
+        GPIO_FN(SIOD),
+        GPIO_FN(SIOSTRB0),
+        GPIO_FN(SIOSTRB1),
+        GPIO_FN(SIOSCK),
+        GPIO_FN(SIOMCK),
 
         /* CEU */
-        PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK),
+        GPIO_FN(VIO_D15),
+        GPIO_FN(VIO_D14),
+        GPIO_FN(VIO_D13),
+        GPIO_FN(VIO_D12),
+        GPIO_FN(VIO_D11),
+        GPIO_FN(VIO_D10),
+        GPIO_FN(VIO_D9),
+        GPIO_FN(VIO_D8),
+        GPIO_FN(VIO_D7),
+        GPIO_FN(VIO_D6),
+        GPIO_FN(VIO_D5),
+        GPIO_FN(VIO_D4),
+        GPIO_FN(VIO_D3),
+        GPIO_FN(VIO_D2),
+        GPIO_FN(VIO_D1),
+        GPIO_FN(VIO_D0),
+        GPIO_FN(VIO_CLK),
+        GPIO_FN(VIO_VD),
+        GPIO_FN(VIO_HD),
+        GPIO_FN(VIO_FLD),
+        GPIO_FN(VIO_CKO),
+        GPIO_FN(VIO_STEX),
+        GPIO_FN(VIO_STEM),
+        GPIO_FN(VIO_VD2),
+        GPIO_FN(VIO_HD2),
+        GPIO_FN(VIO_CLK2),
 
         /* LCDC */
-        PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK),
+        GPIO_FN(LCDD23),
+        GPIO_FN(LCDD22),
+        GPIO_FN(LCDD21),
+        GPIO_FN(LCDD20),
+        GPIO_FN(LCDD19),
+        GPIO_FN(LCDD18),
+        GPIO_FN(LCDD17),
+        GPIO_FN(LCDD16),
+        GPIO_FN(LCDD15),
+        GPIO_FN(LCDD14),
+        GPIO_FN(LCDD13),
+        GPIO_FN(LCDD12),
+        GPIO_FN(LCDD11),
+        GPIO_FN(LCDD10),
+        GPIO_FN(LCDD9),
+        GPIO_FN(LCDD8),
+        GPIO_FN(LCDD7),
+        GPIO_FN(LCDD6),
+        GPIO_FN(LCDD5),
+        GPIO_FN(LCDD4),
+        GPIO_FN(LCDD3),
+        GPIO_FN(LCDD2),
+        GPIO_FN(LCDD1),
+        GPIO_FN(LCDD0),
+        GPIO_FN(LCDLCLK),
         /* Main LCD */
-        PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
+        GPIO_FN(LCDDON),
+        GPIO_FN(LCDVCPWC),
+        GPIO_FN(LCDVEPWC),
+        GPIO_FN(LCDVSYN),
         /* Main LCD - RGB Mode */
-        PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
+        GPIO_FN(LCDDCK),
+        GPIO_FN(LCDHSYN),
+        GPIO_FN(LCDDISP),
         /* Main LCD - SYS Mode */
-        PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
+        GPIO_FN(LCDRS),
+        GPIO_FN(LCDCS),
+        GPIO_FN(LCDWR),
+        GPIO_FN(LCDRD),
         /* Sub LCD - SYS Mode */
-        PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK),
+        GPIO_FN(LCDDON2),
+        GPIO_FN(LCDVCPWC2),
+        GPIO_FN(LCDVEPWC2),
+        GPIO_FN(LCDVSYN2),
+        GPIO_FN(LCDCS2),
 
         /* BSC */
-        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
-        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
-        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
-        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
-        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
-        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
-        PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
+        GPIO_FN(IOIS16),
+        GPIO_FN(A25),
+        GPIO_FN(A24),
+        GPIO_FN(A23),
+        GPIO_FN(A22),
+        GPIO_FN(BS),
+        GPIO_FN(CS6B_CE1B),
+        GPIO_FN(WAIT),
+        GPIO_FN(CS6A_CE2B),
 
         /* SBSC */
-        PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK),
-        PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK),
-        PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK),
-        PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK),
-        PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK),
-        PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK),
+        GPIO_FN(HPD63),
+        GPIO_FN(HPD62),
+        GPIO_FN(HPD61),
+        GPIO_FN(HPD60),
+        GPIO_FN(HPD59),
+        GPIO_FN(HPD58),
+        GPIO_FN(HPD57),
+        GPIO_FN(HPD56),
+        GPIO_FN(HPD55),
+        GPIO_FN(HPD54),
+        GPIO_FN(HPD53),
+        GPIO_FN(HPD52),
+        GPIO_FN(HPD51),
+        GPIO_FN(HPD50),
+        GPIO_FN(HPD49),
+        GPIO_FN(HPD48),
+        GPIO_FN(HPDQM7),
+        GPIO_FN(HPDQM6),
+        GPIO_FN(HPDQM5),
+        GPIO_FN(HPDQM4),
 
         /* IRQ */
-        PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
+        GPIO_FN(IRQ0),
+        GPIO_FN(IRQ1),
+        GPIO_FN(IRQ2),
+        GPIO_FN(IRQ3),
+        GPIO_FN(IRQ4),
+        GPIO_FN(IRQ5),
+        GPIO_FN(IRQ6),
+        GPIO_FN(IRQ7),
 
         /* SDHI */
-        PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK),
+        GPIO_FN(SDHICD),
+        GPIO_FN(SDHIWP),
+        GPIO_FN(SDHID3),
+        GPIO_FN(SDHID2),
+        GPIO_FN(SDHID1),
+        GPIO_FN(SDHID0),
+        GPIO_FN(SDHICMD),
+        GPIO_FN(SDHICLK),
 
         /* SIU - Port A */
-        PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK),
+        GPIO_FN(SIUAOLR),
+        GPIO_FN(SIUAOBT),
+        GPIO_FN(SIUAISLD),
+        GPIO_FN(SIUAILR),
+        GPIO_FN(SIUAIBT),
+        GPIO_FN(SIUAOSLD),
+        GPIO_FN(SIUMCKA),
+        GPIO_FN(SIUFCKA),
 
         /* SIU - Port B */
-        PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK),
+        GPIO_FN(SIUBOLR),
+        GPIO_FN(SIUBOBT),
+        GPIO_FN(SIUBISLD),
+        GPIO_FN(SIUBILR),
+        GPIO_FN(SIUBIBT),
+        GPIO_FN(SIUBOSLD),
+        GPIO_FN(SIUMCKB),
+        GPIO_FN(SIUFCKB),
 
         /* AUD */
-        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
+        GPIO_FN(AUDSYNC),
+        GPIO_FN(AUDATA3),
+        GPIO_FN(AUDATA2),
+        GPIO_FN(AUDATA1),
+        GPIO_FN(AUDATA0),
 
         /* DMAC */
-        PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
+        GPIO_FN(DACK),
+        GPIO_FN(DREQ0),
 
         /* VOU */
-        PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
+        GPIO_FN(DV_CLKI),
+        GPIO_FN(DV_CLK),
+        GPIO_FN(DV_HSYNC),
+        GPIO_FN(DV_VSYNC),
+        GPIO_FN(DV_D15),
+        GPIO_FN(DV_D14),
+        GPIO_FN(DV_D13),
+        GPIO_FN(DV_D12),
+        GPIO_FN(DV_D11),
+        GPIO_FN(DV_D10),
+        GPIO_FN(DV_D9),
+        GPIO_FN(DV_D8),
+        GPIO_FN(DV_D7),
+        GPIO_FN(DV_D6),
+        GPIO_FN(DV_D5),
+        GPIO_FN(DV_D4),
+        GPIO_FN(DV_D3),
+        GPIO_FN(DV_D2),
+        GPIO_FN(DV_D1),
+        GPIO_FN(DV_D0),
 
         /* CPG */
-        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
-        PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
+        GPIO_FN(STATUS0),
+        GPIO_FN(PDSTATUS),
 
         /* SIOF0 */
-        PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK),
+        GPIO_FN(SIOF0_MCK),
+        GPIO_FN(SIOF0_SCK),
+        GPIO_FN(SIOF0_SYNC),
+        GPIO_FN(SIOF0_SS1),
+        GPIO_FN(SIOF0_SS2),
+        GPIO_FN(SIOF0_TXD),
+        GPIO_FN(SIOF0_RXD),
 
         /* SIOF1 */
-        PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK),
+        GPIO_FN(SIOF1_MCK),
+        GPIO_FN(SIOF1_SCK),
+        GPIO_FN(SIOF1_SYNC),
+        GPIO_FN(SIOF1_SS1),
+        GPIO_FN(SIOF1_SS2),
+        GPIO_FN(SIOF1_TXD),
+        GPIO_FN(SIOF1_RXD),
 
         /* SIM */
-        PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
-        PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
+        GPIO_FN(SIM_D),
+        GPIO_FN(SIM_CLK),
+        GPIO_FN(SIM_RST),
 
         /* TSIF */
-        PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK),
-        PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK),
-        PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK),
+        GPIO_FN(TS_SDAT),
+        GPIO_FN(TS_SCK),
+        GPIO_FN(TS_SDEN),
+        GPIO_FN(TS_SPSYNC),
 
         /* IRDA */
-        PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
-        PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
+        GPIO_FN(IRDA_IN),
+        GPIO_FN(IRDA_OUT),
 
         /* TPU */
-        PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK),
+        GPIO_FN(TPUTO),
 
         /* FLCTL */
-        PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
-        PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
-        PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
-        PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
-        PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
-        PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
+        GPIO_FN(FCE),
+        GPIO_FN(NAF7),
+        GPIO_FN(NAF6),
+        GPIO_FN(NAF5),
+        GPIO_FN(NAF4),
+        GPIO_FN(NAF3),
+        GPIO_FN(NAF2),
+        GPIO_FN(NAF1),
+        GPIO_FN(NAF0),
+        GPIO_FN(FCDE),
+        GPIO_FN(FOE),
+        GPIO_FN(FSC),
+        GPIO_FN(FWE),
+        GPIO_FN(FRB),
 
         /* KEYSC */
-        PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
+        GPIO_FN(KEYIN0),
+        GPIO_FN(KEYIN1),
+        GPIO_FN(KEYIN2),
+        GPIO_FN(KEYIN3),
+        GPIO_FN(KEYIN4),
+        GPIO_FN(KEYOUT0),
+        GPIO_FN(KEYOUT1),
+        GPIO_FN(KEYOUT2),
+        GPIO_FN(KEYOUT3),
+        GPIO_FN(KEYOUT4_IN6),
+        GPIO_FN(KEYOUT5_IN5),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
                 VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN,
                 VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN,
@@ -1660,7 +1664,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         {}
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
                 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
                 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1756,21 +1760,19 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info sh7722_pinmux_info = {
+const struct sh_pfc_soc_info sh7722_pinmux_info = {
         .name = "sh7722_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
         .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
         .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PTA7,
-        .last_gpio = GPIO_FN_KEYOUT5_IN5,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index 609673d3d70e..07ad1d8d6c8b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -350,7 +350,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
         /* PTA GPIO */
         PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
         PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@@ -923,7 +923,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
         /* PTA */
         PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
         PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1139,379 +1139,383 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
         PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
         PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* SCIF0 */
-        PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK),
+        GPIO_FN(SCIF0_PTT_TXD),
+        GPIO_FN(SCIF0_PTT_RXD),
+        GPIO_FN(SCIF0_PTT_SCK),
+        GPIO_FN(SCIF0_PTU_TXD),
+        GPIO_FN(SCIF0_PTU_RXD),
+        GPIO_FN(SCIF0_PTU_SCK),
 
         /* SCIF1 */
-        PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK),
+        GPIO_FN(SCIF1_PTS_TXD),
+        GPIO_FN(SCIF1_PTS_RXD),
+        GPIO_FN(SCIF1_PTS_SCK),
+        GPIO_FN(SCIF1_PTV_TXD),
+        GPIO_FN(SCIF1_PTV_RXD),
+        GPIO_FN(SCIF1_PTV_SCK),
 
         /* SCIF2 */
-        PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK),
+        GPIO_FN(SCIF2_PTT_TXD),
+        GPIO_FN(SCIF2_PTT_RXD),
+        GPIO_FN(SCIF2_PTT_SCK),
+        GPIO_FN(SCIF2_PTU_TXD),
+        GPIO_FN(SCIF2_PTU_RXD),
+        GPIO_FN(SCIF2_PTU_SCK),
 
         /* SCIF3 */
-        PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK),
+        GPIO_FN(SCIF3_PTS_TXD),
+        GPIO_FN(SCIF3_PTS_RXD),
+        GPIO_FN(SCIF3_PTS_SCK),
+        GPIO_FN(SCIF3_PTS_RTS),
+        GPIO_FN(SCIF3_PTS_CTS),
+        GPIO_FN(SCIF3_PTV_TXD),
+        GPIO_FN(SCIF3_PTV_RXD),
+        GPIO_FN(SCIF3_PTV_SCK),
+        GPIO_FN(SCIF3_PTV_RTS),
+        GPIO_FN(SCIF3_PTV_CTS),
 
         /* SCIF4 */
-        PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK),
+        GPIO_FN(SCIF4_PTE_TXD),
+        GPIO_FN(SCIF4_PTE_RXD),
+        GPIO_FN(SCIF4_PTE_SCK),
+        GPIO_FN(SCIF4_PTN_TXD),
+        GPIO_FN(SCIF4_PTN_RXD),
+        GPIO_FN(SCIF4_PTN_SCK),
 
         /* SCIF5 */
-        PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK),
+        GPIO_FN(SCIF5_PTE_TXD),
+        GPIO_FN(SCIF5_PTE_RXD),
+        GPIO_FN(SCIF5_PTE_SCK),
+        GPIO_FN(SCIF5_PTN_TXD),
+        GPIO_FN(SCIF5_PTN_RXD),
+        GPIO_FN(SCIF5_PTN_SCK),
 
         /* CEU */
-        PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK),
+        GPIO_FN(VIO_D15),
+        GPIO_FN(VIO_D14),
+        GPIO_FN(VIO_D13),
+        GPIO_FN(VIO_D12),
+        GPIO_FN(VIO_D11),
+        GPIO_FN(VIO_D10),
+        GPIO_FN(VIO_D9),
+        GPIO_FN(VIO_D8),
+        GPIO_FN(VIO_D7),
+        GPIO_FN(VIO_D6),
+        GPIO_FN(VIO_D5),
+        GPIO_FN(VIO_D4),
+        GPIO_FN(VIO_D3),
+        GPIO_FN(VIO_D2),
+        GPIO_FN(VIO_D1),
+        GPIO_FN(VIO_D0),
+        GPIO_FN(VIO_CLK1),
+        GPIO_FN(VIO_VD1),
+        GPIO_FN(VIO_HD1),
+        GPIO_FN(VIO_FLD),
+        GPIO_FN(VIO_CKO),
+        GPIO_FN(VIO_VD2),
+        GPIO_FN(VIO_HD2),
+        GPIO_FN(VIO_CLK2),
 
         /* LCDC */
-        PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK),
+        GPIO_FN(LCDD23),
+        GPIO_FN(LCDD22),
+        GPIO_FN(LCDD21),
+        GPIO_FN(LCDD20),
+        GPIO_FN(LCDD19),
+        GPIO_FN(LCDD18),
+        GPIO_FN(LCDD17),
+        GPIO_FN(LCDD16),
+        GPIO_FN(LCDD15),
+        GPIO_FN(LCDD14),
+        GPIO_FN(LCDD13),
+        GPIO_FN(LCDD12),
+        GPIO_FN(LCDD11),
+        GPIO_FN(LCDD10),
+        GPIO_FN(LCDD9),
+        GPIO_FN(LCDD8),
+        GPIO_FN(LCDD7),
+        GPIO_FN(LCDD6),
+        GPIO_FN(LCDD5),
+        GPIO_FN(LCDD4),
+        GPIO_FN(LCDD3),
+        GPIO_FN(LCDD2),
+        GPIO_FN(LCDD1),
+        GPIO_FN(LCDD0),
+        GPIO_FN(LCDLCLK_PTR),
+        GPIO_FN(LCDLCLK_PTW),
         /* Main LCD */
-        PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
+        GPIO_FN(LCDDON),
+        GPIO_FN(LCDVCPWC),
+        GPIO_FN(LCDVEPWC),
+        GPIO_FN(LCDVSYN),
         /* Main LCD - RGB Mode */
-        PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
+        GPIO_FN(LCDDCK),
+        GPIO_FN(LCDHSYN),
+        GPIO_FN(LCDDISP),
         /* Main LCD - SYS Mode */
-        PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
+        GPIO_FN(LCDRS),
+        GPIO_FN(LCDCS),
+        GPIO_FN(LCDWR),
+        GPIO_FN(LCDRD),
 
         /* IRQ */
-        PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
+        GPIO_FN(IRQ0),
+        GPIO_FN(IRQ1),
+        GPIO_FN(IRQ2),
+        GPIO_FN(IRQ3),
+        GPIO_FN(IRQ4),
+        GPIO_FN(IRQ5),
+        GPIO_FN(IRQ6),
+        GPIO_FN(IRQ7),
 
         /* AUD */
-        PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
+        GPIO_FN(AUDCK),
+        GPIO_FN(AUDSYNC),
+        GPIO_FN(AUDATA3),
+        GPIO_FN(AUDATA2),
+        GPIO_FN(AUDATA1),
+        GPIO_FN(AUDATA0),
 
         /* SDHI0 (PTD) */
-        PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK),
+        GPIO_FN(SDHI0CD_PTD),
+        GPIO_FN(SDHI0WP_PTD),
+        GPIO_FN(SDHI0D3_PTD),
+        GPIO_FN(SDHI0D2_PTD),
+        GPIO_FN(SDHI0D1_PTD),
+        GPIO_FN(SDHI0D0_PTD),
+        GPIO_FN(SDHI0CMD_PTD),
+        GPIO_FN(SDHI0CLK_PTD),
 
         /* SDHI0 (PTS) */
-        PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK),
+        GPIO_FN(SDHI0CD_PTS),
+        GPIO_FN(SDHI0WP_PTS),
+        GPIO_FN(SDHI0D3_PTS),
+        GPIO_FN(SDHI0D2_PTS),
+        GPIO_FN(SDHI0D1_PTS),
+        GPIO_FN(SDHI0D0_PTS),
+        GPIO_FN(SDHI0CMD_PTS),
+        GPIO_FN(SDHI0CLK_PTS),
 
         /* SDHI1 */
-        PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK),
+        GPIO_FN(SDHI1CD),
+        GPIO_FN(SDHI1WP),
+        GPIO_FN(SDHI1D3),
+        GPIO_FN(SDHI1D2),
+        GPIO_FN(SDHI1D1),
+        GPIO_FN(SDHI1D0),
+        GPIO_FN(SDHI1CMD),
+        GPIO_FN(SDHI1CLK),
 
         /* SIUA */
-        PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUAOSPD, SIUAOSPD_MARK),
+        GPIO_FN(SIUAFCK),
+        GPIO_FN(SIUAILR),
+        GPIO_FN(SIUAIBT),
+        GPIO_FN(SIUAISLD),
+        GPIO_FN(SIUAOLR),
+        GPIO_FN(SIUAOBT),
+        GPIO_FN(SIUAOSLD),
+        GPIO_FN(SIUAMCK),
+        GPIO_FN(SIUAISPD),
+        GPIO_FN(SIUAOSPD),
 
         /* SIUB */
-        PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK),
+        GPIO_FN(SIUBFCK),
+        GPIO_FN(SIUBILR),
+        GPIO_FN(SIUBIBT),
+        GPIO_FN(SIUBISLD),
+        GPIO_FN(SIUBOLR),
+        GPIO_FN(SIUBOBT),
+        GPIO_FN(SIUBOSLD),
+        GPIO_FN(SIUBMCK),
 
         /* IRDA */
-        PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
-        PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
+        GPIO_FN(IRDA_IN),
+        GPIO_FN(IRDA_OUT),
 
         /* VOU */
-        PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
+        GPIO_FN(DV_CLKI),
+        GPIO_FN(DV_CLK),
+        GPIO_FN(DV_HSYNC),
+        GPIO_FN(DV_VSYNC),
+        GPIO_FN(DV_D15),
+        GPIO_FN(DV_D14),
+        GPIO_FN(DV_D13),
+        GPIO_FN(DV_D12),
+        GPIO_FN(DV_D11),
+        GPIO_FN(DV_D10),
+        GPIO_FN(DV_D9),
+        GPIO_FN(DV_D8),
+        GPIO_FN(DV_D7),
+        GPIO_FN(DV_D6),
+        GPIO_FN(DV_D5),
+        GPIO_FN(DV_D4),
+        GPIO_FN(DV_D3),
+        GPIO_FN(DV_D2),
+        GPIO_FN(DV_D1),
+        GPIO_FN(DV_D0),
 
         /* KEYSC */
-        PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
+        GPIO_FN(KEYIN0),
+        GPIO_FN(KEYIN1),
+        GPIO_FN(KEYIN2),
+        GPIO_FN(KEYIN3),
+        GPIO_FN(KEYIN4),
+        GPIO_FN(KEYOUT0),
+        GPIO_FN(KEYOUT1),
+        GPIO_FN(KEYOUT2),
+        GPIO_FN(KEYOUT3),
+        GPIO_FN(KEYOUT4_IN6),
+        GPIO_FN(KEYOUT5_IN5),
 
         /* MSIOF0 (PTF) */
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK),
+        GPIO_FN(MSIOF0_PTF_TXD),
+        GPIO_FN(MSIOF0_PTF_RXD),
+        GPIO_FN(MSIOF0_PTF_MCK),
+        GPIO_FN(MSIOF0_PTF_TSYNC),
+        GPIO_FN(MSIOF0_PTF_TSCK),
+        GPIO_FN(MSIOF0_PTF_RSYNC),
+        GPIO_FN(MSIOF0_PTF_RSCK),
+        GPIO_FN(MSIOF0_PTF_SS1),
+        GPIO_FN(MSIOF0_PTF_SS2),
 
         /* MSIOF0 (PTT+PTX) */
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK),
+        GPIO_FN(MSIOF0_PTT_TXD),
+        GPIO_FN(MSIOF0_PTT_RXD),
+        GPIO_FN(MSIOF0_PTX_MCK),
+        GPIO_FN(MSIOF0_PTT_TSYNC),
+        GPIO_FN(MSIOF0_PTT_TSCK),
+        GPIO_FN(MSIOF0_PTT_RSYNC),
+        GPIO_FN(MSIOF0_PTT_RSCK),
+        GPIO_FN(MSIOF0_PTT_SS1),
+        GPIO_FN(MSIOF0_PTT_SS2),
 
         /* MSIOF1 */
-        PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK),
+        GPIO_FN(MSIOF1_TXD),
+        GPIO_FN(MSIOF1_RXD),
+        GPIO_FN(MSIOF1_MCK),
+        GPIO_FN(MSIOF1_TSYNC),
+        GPIO_FN(MSIOF1_TSCK),
+        GPIO_FN(MSIOF1_RSYNC),
+        GPIO_FN(MSIOF1_RSCK),
+        GPIO_FN(MSIOF1_SS1),
+        GPIO_FN(MSIOF1_SS2),
 
         /* TSIF */
-        PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK),
-        PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK),
-        PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK),
+        GPIO_FN(TS0_SDAT),
+        GPIO_FN(TS0_SCK),
+        GPIO_FN(TS0_SDEN),
+        GPIO_FN(TS0_SPSYNC),
 
         /* FLCTL */
-        PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
-        PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
-        PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
-        PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
-        PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
-        PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
-        PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
+        GPIO_FN(FCE),
+        GPIO_FN(NAF7),
+        GPIO_FN(NAF6),
+        GPIO_FN(NAF5),
+        GPIO_FN(NAF4),
+        GPIO_FN(NAF3),
+        GPIO_FN(NAF2),
+        GPIO_FN(NAF1),
+        GPIO_FN(NAF0),
+        GPIO_FN(FCDE),
+        GPIO_FN(FOE),
+        GPIO_FN(FSC),
+        GPIO_FN(FWE),
+        GPIO_FN(FRB),
 
         /* DMAC */
-        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
+        GPIO_FN(DACK1),
+        GPIO_FN(DREQ1),
+        GPIO_FN(DACK0),
+        GPIO_FN(DREQ0),
 
         /* ADC */
-        PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK),
-        PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK),
-        PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK),
-        PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK),
-        PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
+        GPIO_FN(AN3),
+        GPIO_FN(AN2),
+        GPIO_FN(AN1),
+        GPIO_FN(AN0),
+        GPIO_FN(ADTRG),
 
         /* CPG */
-        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
-        PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
+        GPIO_FN(STATUS0),
+        GPIO_FN(PDSTATUS),
 
         /* TPU */
-        PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK),
-        PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK),
-        PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK),
-        PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK),
+        GPIO_FN(TPUTO0),
+        GPIO_FN(TPUTO1),
+        GPIO_FN(TPUTO2),
+        GPIO_FN(TPUTO3),
 
         /* BSC */
-        PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
-        PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
-        PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
-        PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
-        PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
-        PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
-        PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
-        PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
-        PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
-        PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
-        PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
-        PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
-        PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
-        PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
-        PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
-        PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
-        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
-        PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
-        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
-        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
-        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
-        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
-        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK),
-        PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
-        PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
+        GPIO_FN(D31),
+        GPIO_FN(D30),
+        GPIO_FN(D29),
+        GPIO_FN(D28),
+        GPIO_FN(D27),
+        GPIO_FN(D26),
+        GPIO_FN(D25),
+        GPIO_FN(D24),
+        GPIO_FN(D23),
+        GPIO_FN(D22),
+        GPIO_FN(D21),
+        GPIO_FN(D20),
+        GPIO_FN(D19),
+        GPIO_FN(D18),
+        GPIO_FN(D17),
+        GPIO_FN(D16),
+        GPIO_FN(IOIS16),
+        GPIO_FN(WAIT),
+        GPIO_FN(BS),
+        GPIO_FN(A25),
+        GPIO_FN(A24),
+        GPIO_FN(A23),
+        GPIO_FN(A22),
+        GPIO_FN(CS6B_CE1B),
+        GPIO_FN(CS6A_CE2B),
+        GPIO_FN(CS5B_CE1A),
+        GPIO_FN(CS5A_CE2A),
+        GPIO_FN(WE3_ICIOWR),
+        GPIO_FN(WE2_ICIORD),
 
         /* ATAPI */
-        PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK),
-        PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK),
-        PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK),
-        PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK),
-        PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK),
-        PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK),
-        PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK),
-        PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK),
+        GPIO_FN(IDED15),
+        GPIO_FN(IDED14),
+        GPIO_FN(IDED13),
+        GPIO_FN(IDED12),
+        GPIO_FN(IDED11),
+        GPIO_FN(IDED10),
+        GPIO_FN(IDED9),
+        GPIO_FN(IDED8),
+        GPIO_FN(IDED7),
+        GPIO_FN(IDED6),
+        GPIO_FN(IDED5),
+        GPIO_FN(IDED4),
+        GPIO_FN(IDED3),
+        GPIO_FN(IDED2),
+        GPIO_FN(IDED1),
+        GPIO_FN(IDED0),
+        GPIO_FN(DIRECTION),
+        GPIO_FN(EXBUF_ENB),
+        GPIO_FN(IDERST),
+        GPIO_FN(IODACK),
+        GPIO_FN(IODREQ),
+        GPIO_FN(IDEIORDY),
+        GPIO_FN(IDEINT),
+        GPIO_FN(IDEIOWR),
+        GPIO_FN(IDEIORD),
+        GPIO_FN(IDECS1),
+        GPIO_FN(IDECS0),
+        GPIO_FN(IDEA2),
+        GPIO_FN(IDEA1),
+        GPIO_FN(IDEA0),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
                 PTA7_FN, PTA7_OUT, 0, PTA7_IN,
                 PTA6_FN, PTA6_OUT, 0, PTA6_IN,
@@ -1785,7 +1789,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         {}
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
                 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
                 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1881,20 +1885,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info sh7723_pinmux_info = {
+const struct sh_pfc_soc_info sh7723_pinmux_info = {
         .name = "sh7723_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
         .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PTA7,
-        .last_gpio = GPIO_FN_IDEA0,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 233fbf750b39..35e551609805 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -572,7 +572,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
         /* PTA GPIO */
         PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
         PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
@@ -1192,7 +1192,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(SCIF3_I_TXD_MARK,   PSB14_1, PTZ3_FN),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
         /* PTA */
         PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
         PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1418,372 +1418,376 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
         PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
         PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* BSC */
-        PINMUX_GPIO(GPIO_FN_D31,        D31_MARK),
-        PINMUX_GPIO(GPIO_FN_D30,        D30_MARK),
-        PINMUX_GPIO(GPIO_FN_D29,        D29_MARK),
-        PINMUX_GPIO(GPIO_FN_D28,        D28_MARK),
-        PINMUX_GPIO(GPIO_FN_D27,        D27_MARK),
-        PINMUX_GPIO(GPIO_FN_D26,        D26_MARK),
-        PINMUX_GPIO(GPIO_FN_D25,        D25_MARK),
-        PINMUX_GPIO(GPIO_FN_D24,        D24_MARK),
-        PINMUX_GPIO(GPIO_FN_D23,        D23_MARK),
-        PINMUX_GPIO(GPIO_FN_D22,        D22_MARK),
-        PINMUX_GPIO(GPIO_FN_D21,        D21_MARK),
-        PINMUX_GPIO(GPIO_FN_D20,        D20_MARK),
-        PINMUX_GPIO(GPIO_FN_D19,        D19_MARK),
-        PINMUX_GPIO(GPIO_FN_D18,        D18_MARK),
-        PINMUX_GPIO(GPIO_FN_D17,        D17_MARK),
-        PINMUX_GPIO(GPIO_FN_D16,        D16_MARK),
-        PINMUX_GPIO(GPIO_FN_D15,        D15_MARK),
-        PINMUX_GPIO(GPIO_FN_D14,        D14_MARK),
-        PINMUX_GPIO(GPIO_FN_D13,        D13_MARK),
-        PINMUX_GPIO(GPIO_FN_D12,        D12_MARK),
-        PINMUX_GPIO(GPIO_FN_D11,        D11_MARK),
-        PINMUX_GPIO(GPIO_FN_D10,        D10_MARK),
-        PINMUX_GPIO(GPIO_FN_D9,         D9_MARK),
-        PINMUX_GPIO(GPIO_FN_D8,         D8_MARK),
-        PINMUX_GPIO(GPIO_FN_D7,         D7_MARK),
-        PINMUX_GPIO(GPIO_FN_D6,         D6_MARK),
-        PINMUX_GPIO(GPIO_FN_D5,         D5_MARK),
-        PINMUX_GPIO(GPIO_FN_D4,         D4_MARK),
-        PINMUX_GPIO(GPIO_FN_D3,         D3_MARK),
-        PINMUX_GPIO(GPIO_FN_D2,         D2_MARK),
-        PINMUX_GPIO(GPIO_FN_D1,         D1_MARK),
-        PINMUX_GPIO(GPIO_FN_D0,         D0_MARK),
-        PINMUX_GPIO(GPIO_FN_A25,        A25_MARK),
-        PINMUX_GPIO(GPIO_FN_A24,        A24_MARK),
-        PINMUX_GPIO(GPIO_FN_A23,        A23_MARK),
-        PINMUX_GPIO(GPIO_FN_A22,        A22_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6B_CE1B,  CS6B_CE1B_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6A_CE2B,  CS6A_CE2B_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5B_CE1A,  CS5B_CE1A_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5A_CE2A,  CS5A_CE2A_MARK),
-        PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
-        PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
-        PINMUX_GPIO(GPIO_FN_IOIS16,     IOIS16_MARK),
-        PINMUX_GPIO(GPIO_FN_WAIT,       WAIT_MARK),
-        PINMUX_GPIO(GPIO_FN_BS,         BS_MARK),
+        GPIO_FN(D31),
+        GPIO_FN(D30),
+        GPIO_FN(D29),
+        GPIO_FN(D28),
+        GPIO_FN(D27),
+        GPIO_FN(D26),
+        GPIO_FN(D25),
+        GPIO_FN(D24),
+        GPIO_FN(D23),
+        GPIO_FN(D22),
+        GPIO_FN(D21),
+        GPIO_FN(D20),
+        GPIO_FN(D19),
+        GPIO_FN(D18),
+        GPIO_FN(D17),
+        GPIO_FN(D16),
+        GPIO_FN(D15),
+        GPIO_FN(D14),
+        GPIO_FN(D13),
+        GPIO_FN(D12),
+        GPIO_FN(D11),
+        GPIO_FN(D10),
+        GPIO_FN(D9),
+        GPIO_FN(D8),
+        GPIO_FN(D7),
+        GPIO_FN(D6),
+        GPIO_FN(D5),
+        GPIO_FN(D4),
+        GPIO_FN(D3),
+        GPIO_FN(D2),
+        GPIO_FN(D1),
+        GPIO_FN(D0),
+        GPIO_FN(A25),
+        GPIO_FN(A24),
+        GPIO_FN(A23),
+        GPIO_FN(A22),
+        GPIO_FN(CS6B_CE1B),
+        GPIO_FN(CS6A_CE2B),
+        GPIO_FN(CS5B_CE1A),
+        GPIO_FN(CS5A_CE2A),
+        GPIO_FN(WE3_ICIOWR),
+        GPIO_FN(WE2_ICIORD),
+        GPIO_FN(IOIS16),
+        GPIO_FN(WAIT),
+        GPIO_FN(BS),
 
         /* KEYSC */
-        PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5,        KEYOUT5_IN5_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6,        KEYOUT4_IN6_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN4,             KEYIN4_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN3,             KEYIN3_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN2,             KEYIN2_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN1,             KEYIN1_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYIN0,             KEYIN0_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT3,            KEYOUT3_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT2,            KEYOUT2_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT1,            KEYOUT1_MARK),
-        PINMUX_GPIO(GPIO_FN_KEYOUT0,            KEYOUT0_MARK),
+        GPIO_FN(KEYOUT5_IN5),
+        GPIO_FN(KEYOUT4_IN6),
+        GPIO_FN(KEYIN4),
+        GPIO_FN(KEYIN3),
+        GPIO_FN(KEYIN2),
+        GPIO_FN(KEYIN1),
+        GPIO_FN(KEYIN0),
+        GPIO_FN(KEYOUT3),
+        GPIO_FN(KEYOUT2),
+        GPIO_FN(KEYOUT1),
+        GPIO_FN(KEYOUT0),
 
         /* ATAPI */
-        PINMUX_GPIO(GPIO_FN_IDED15,     IDED15_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED14,     IDED14_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED13,     IDED13_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED12,     IDED12_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED11,     IDED11_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED10,     IDED10_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED9,      IDED9_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED8,      IDED8_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED7,      IDED7_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED6,      IDED6_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED5,      IDED5_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED4,      IDED4_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED3,      IDED3_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED2,      IDED2_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED1,      IDED1_MARK),
-        PINMUX_GPIO(GPIO_FN_IDED0,      IDED0_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEA2,      IDEA2_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEA1,      IDEA1_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEA0,      IDEA0_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEIOWR,    IDEIOWR_MARK),
-        PINMUX_GPIO(GPIO_FN_IODREQ,     IODREQ_MARK),
-        PINMUX_GPIO(GPIO_FN_IDECS0,     IDECS0_MARK),
-        PINMUX_GPIO(GPIO_FN_IDECS1,     IDECS1_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEIORD,    IDEIORD_MARK),
-        PINMUX_GPIO(GPIO_FN_DIRECTION,  DIRECTION_MARK),
-        PINMUX_GPIO(GPIO_FN_EXBUF_ENB,  EXBUF_ENB_MARK),
-        PINMUX_GPIO(GPIO_FN_IDERST,     IDERST_MARK),
-        PINMUX_GPIO(GPIO_FN_IODACK,     IODACK_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEINT,     IDEINT_MARK),
-        PINMUX_GPIO(GPIO_FN_IDEIORDY,   IDEIORDY_MARK),
+        GPIO_FN(IDED15),
+        GPIO_FN(IDED14),
+        GPIO_FN(IDED13),
+        GPIO_FN(IDED12),
+        GPIO_FN(IDED11),
+        GPIO_FN(IDED10),
+        GPIO_FN(IDED9),
+        GPIO_FN(IDED8),
+        GPIO_FN(IDED7),
+        GPIO_FN(IDED6),
+        GPIO_FN(IDED5),
+        GPIO_FN(IDED4),
+        GPIO_FN(IDED3),
+        GPIO_FN(IDED2),
+        GPIO_FN(IDED1),
+        GPIO_FN(IDED0),
+        GPIO_FN(IDEA2),
+        GPIO_FN(IDEA1),
+        GPIO_FN(IDEA0),
+        GPIO_FN(IDEIOWR),
+        GPIO_FN(IODREQ),
+        GPIO_FN(IDECS0),
+        GPIO_FN(IDECS1),
+        GPIO_FN(IDEIORD),
+        GPIO_FN(DIRECTION),
+        GPIO_FN(EXBUF_ENB),
+        GPIO_FN(IDERST),
+        GPIO_FN(IODACK),
+        GPIO_FN(IDEINT),
+        GPIO_FN(IDEIORDY),
 
         /* TPU */
-        PINMUX_GPIO(GPIO_FN_TPUTO3,     TPUTO3_MARK),
-        PINMUX_GPIO(GPIO_FN_TPUTO2,     TPUTO2_MARK),
-        PINMUX_GPIO(GPIO_FN_TPUTO1,     TPUTO1_MARK),
-        PINMUX_GPIO(GPIO_FN_TPUTO0,     TPUTO0_MARK),
-        PINMUX_GPIO(GPIO_FN_TPUTI3,     TPUTI3_MARK),
-        PINMUX_GPIO(GPIO_FN_TPUTI2,     TPUTI2_MARK),
+        GPIO_FN(TPUTO3),
+        GPIO_FN(TPUTO2),
+        GPIO_FN(TPUTO1),
+        GPIO_FN(TPUTO0),
+        GPIO_FN(TPUTI3),
+        GPIO_FN(TPUTI2),
 
         /* LCDC */
-        PINMUX_GPIO(GPIO_FN_LCDD23,     LCDD23_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD22,     LCDD22_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD21,     LCDD21_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD20,     LCDD20_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD19,     LCDD19_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD18,     LCDD18_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD17,     LCDD17_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD16,     LCDD16_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD15,     LCDD15_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD14,     LCDD14_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD13,     LCDD13_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD12,     LCDD12_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD11,     LCDD11_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD10,     LCDD10_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD9,      LCDD9_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD8,      LCDD8_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD7,      LCDD7_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD6,      LCDD6_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD5,      LCDD5_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD4,      LCDD4_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD3,      LCDD3_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD2,      LCDD2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD1,      LCDD1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDD0,      LCDD0_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVSYN,    LCDVSYN_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDDISP,    LCDDISP_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDRS,      LCDRS_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDHSYN,    LCDHSYN_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDCS,      LCDCS_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDDON,     LCDDON_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDDCK,     LCDDCK_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDWR,      LCDWR_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVEPWC,   LCDVEPWC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDVCPWC,   LCDVCPWC_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDRD,      LCDRD_MARK),
-        PINMUX_GPIO(GPIO_FN_LCDLCLK,    LCDLCLK_MARK),
+        GPIO_FN(LCDD23),
+        GPIO_FN(LCDD22),
+        GPIO_FN(LCDD21),
+        GPIO_FN(LCDD20),
+        GPIO_FN(LCDD19),
+        GPIO_FN(LCDD18),
+        GPIO_FN(LCDD17),
+        GPIO_FN(LCDD16),
+        GPIO_FN(LCDD15),
+        GPIO_FN(LCDD14),
+        GPIO_FN(LCDD13),
+        GPIO_FN(LCDD12),
+        GPIO_FN(LCDD11),
+        GPIO_FN(LCDD10),
+        GPIO_FN(LCDD9),
+        GPIO_FN(LCDD8),
+        GPIO_FN(LCDD7),
+        GPIO_FN(LCDD6),
+        GPIO_FN(LCDD5),
+        GPIO_FN(LCDD4),
+        GPIO_FN(LCDD3),
+        GPIO_FN(LCDD2),
+        GPIO_FN(LCDD1),
+        GPIO_FN(LCDD0),
+        GPIO_FN(LCDVSYN),
+        GPIO_FN(LCDDISP),
+        GPIO_FN(LCDRS),
+        GPIO_FN(LCDHSYN),
+        GPIO_FN(LCDCS),
+        GPIO_FN(LCDDON),
+        GPIO_FN(LCDDCK),
+        GPIO_FN(LCDWR),
+        GPIO_FN(LCDVEPWC),
+        GPIO_FN(LCDVCPWC),
+        GPIO_FN(LCDRD),
+        GPIO_FN(LCDLCLK),
 
         /* SCIF0 */
-        PINMUX_GPIO(GPIO_FN_SCIF0_TXD,  SCIF0_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_RXD,  SCIF0_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_SCK,  SCIF0_SCK_MARK),
+        GPIO_FN(SCIF0_TXD),
+        GPIO_FN(SCIF0_RXD),
+        GPIO_FN(SCIF0_SCK),
 
         /* SCIF1 */
-        PINMUX_GPIO(GPIO_FN_SCIF1_SCK,  SCIF1_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_RXD,  SCIF1_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_TXD,  SCIF1_TXD_MARK),
+        GPIO_FN(SCIF1_SCK),
+        GPIO_FN(SCIF1_RXD),
+        GPIO_FN(SCIF1_TXD),
 
         /* SCIF2 */
-        PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD,        SCIF2_L_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK,        SCIF2_L_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD,        SCIF2_L_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD,        SCIF2_V_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK,        SCIF2_V_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD,        SCIF2_V_RXD_MARK),
+        GPIO_FN(SCIF2_L_TXD),
+        GPIO_FN(SCIF2_L_SCK),
+        GPIO_FN(SCIF2_L_RXD),
+        GPIO_FN(SCIF2_V_TXD),
+        GPIO_FN(SCIF2_V_SCK),
+        GPIO_FN(SCIF2_V_RXD),
 
         /* SCIF3 */
-        PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK,        SCIF3_V_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD,        SCIF3_V_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD,        SCIF3_V_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS,        SCIF3_V_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS,        SCIF3_V_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK,        SCIF3_I_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD,        SCIF3_I_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD,        SCIF3_I_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS,        SCIF3_I_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS,        SCIF3_I_RTS_MARK),
+        GPIO_FN(SCIF3_V_SCK),
+        GPIO_FN(SCIF3_V_RXD),
+        GPIO_FN(SCIF3_V_TXD),
+        GPIO_FN(SCIF3_V_CTS),
+        GPIO_FN(SCIF3_V_RTS),
+        GPIO_FN(SCIF3_I_SCK),
+        GPIO_FN(SCIF3_I_RXD),
+        GPIO_FN(SCIF3_I_TXD),
+        GPIO_FN(SCIF3_I_CTS),
+        GPIO_FN(SCIF3_I_RTS),
 
         /* SCIF4 */
-        PINMUX_GPIO(GPIO_FN_SCIF4_SCK,  SCIF4_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_RXD,  SCIF4_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_TXD,  SCIF4_TXD_MARK),
+        GPIO_FN(SCIF4_SCK),
+        GPIO_FN(SCIF4_RXD),
+        GPIO_FN(SCIF4_TXD),
 
         /* SCIF5 */
-        PINMUX_GPIO(GPIO_FN_SCIF5_SCK,  SCIF5_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_RXD,  SCIF5_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_TXD,  SCIF5_TXD_MARK),
+        GPIO_FN(SCIF5_SCK),
+        GPIO_FN(SCIF5_RXD),
+        GPIO_FN(SCIF5_TXD),
 
         /* FSI */
-        PINMUX_GPIO(GPIO_FN_FSIMCKB,    FSIMCKB_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIMCKA,    FSIMCKA_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIOASD,    FSIOASD_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIIABCK,   FSIIABCK_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIIALRCK,  FSIIALRCK_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIOABCK,   FSIOABCK_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIOALRCK,  FSIOALRCK_MARK),
-        PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIIBSD,    FSIIBSD_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIOBSD,    FSIOBSD_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIIBBCK,   FSIIBBCK_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIIBLRCK,  FSIIBLRCK_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIOBBCK,   FSIOBBCK_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIOBLRCK,  FSIOBLRCK_MARK),
-        PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK),
-        PINMUX_GPIO(GPIO_FN_FSIIASD,    FSIIASD_MARK),
+        GPIO_FN(FSIMCKB),
+        GPIO_FN(FSIMCKA),
+        GPIO_FN(FSIOASD),
+        GPIO_FN(FSIIABCK),
+        GPIO_FN(FSIIALRCK),
+        GPIO_FN(FSIOABCK),
+        GPIO_FN(FSIOALRCK),
+        GPIO_FN(CLKAUDIOAO),
+        GPIO_FN(FSIIBSD),
+        GPIO_FN(FSIOBSD),
+        GPIO_FN(FSIIBBCK),
+        GPIO_FN(FSIIBLRCK),
+        GPIO_FN(FSIOBBCK),
+        GPIO_FN(FSIOBLRCK),
+        GPIO_FN(CLKAUDIOBO),
+        GPIO_FN(FSIIASD),
 
         /* AUD */
-        PINMUX_GPIO(GPIO_FN_AUDCK,      AUDCK_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDSYNC,    AUDSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA3,    AUDATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA2,    AUDATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA1,    AUDATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA0,    AUDATA0_MARK),
+        GPIO_FN(AUDCK),
+        GPIO_FN(AUDSYNC),
+        GPIO_FN(AUDATA3),
+        GPIO_FN(AUDATA2),
+        GPIO_FN(AUDATA1),
+        GPIO_FN(AUDATA0),
 
         /* VIO */
-        PINMUX_GPIO(GPIO_FN_VIO_CKO,    VIO_CKO_MARK),
+        GPIO_FN(VIO_CKO),
 
         /* VIO0 */
-        PINMUX_GPIO(GPIO_FN_VIO0_D15,   VIO0_D15_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D14,   VIO0_D14_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D13,   VIO0_D13_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D12,   VIO0_D12_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D11,   VIO0_D11_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D10,   VIO0_D10_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D9,    VIO0_D9_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D8,    VIO0_D8_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D7,    VIO0_D7_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D6,    VIO0_D6_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D5,    VIO0_D5_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D4,    VIO0_D4_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D3,    VIO0_D3_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D2,    VIO0_D2_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D1,    VIO0_D1_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_D0,    VIO0_D0_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_VD,    VIO0_VD_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_CLK,   VIO0_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_FLD,   VIO0_FLD_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO0_HD,    VIO0_HD_MARK),
+        GPIO_FN(VIO0_D15),
+        GPIO_FN(VIO0_D14),
+        GPIO_FN(VIO0_D13),
+        GPIO_FN(VIO0_D12),
+        GPIO_FN(VIO0_D11),
+        GPIO_FN(VIO0_D10),
+        GPIO_FN(VIO0_D9),
+        GPIO_FN(VIO0_D8),
+        GPIO_FN(VIO0_D7),
+        GPIO_FN(VIO0_D6),
+        GPIO_FN(VIO0_D5),
+        GPIO_FN(VIO0_D4),
+        GPIO_FN(VIO0_D3),
+        GPIO_FN(VIO0_D2),
+        GPIO_FN(VIO0_D1),
+        GPIO_FN(VIO0_D0),
+        GPIO_FN(VIO0_VD),
+        GPIO_FN(VIO0_CLK),
+        GPIO_FN(VIO0_FLD),
+        GPIO_FN(VIO0_HD),
 
         /* VIO1 */
-        PINMUX_GPIO(GPIO_FN_VIO1_D7,    VIO1_D7_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_D6,    VIO1_D6_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_D5,    VIO1_D5_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_D4,    VIO1_D4_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_D3,    VIO1_D3_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_D2,    VIO1_D2_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_D1,    VIO1_D1_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_D0,    VIO1_D0_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_FLD,   VIO1_FLD_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_HD,    VIO1_HD_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_VD,    VIO1_VD_MARK),
-        PINMUX_GPIO(GPIO_FN_VIO1_CLK,   VIO1_CLK_MARK),
+        GPIO_FN(VIO1_D7),
+        GPIO_FN(VIO1_D6),
+        GPIO_FN(VIO1_D5),
+        GPIO_FN(VIO1_D4),
+        GPIO_FN(VIO1_D3),
+        GPIO_FN(VIO1_D2),
+        GPIO_FN(VIO1_D1),
+        GPIO_FN(VIO1_D0),
+        GPIO_FN(VIO1_FLD),
+        GPIO_FN(VIO1_HD),
+        GPIO_FN(VIO1_VD),
+        GPIO_FN(VIO1_CLK),
 
         /* Eth */
-        PINMUX_GPIO(GPIO_FN_RMII_RXD0,          RMII_RXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII_RXD1,          RMII_RXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII_TXD0,          RMII_TXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII_TXD1,          RMII_TXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII_REF_CLK,       RMII_REF_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII_TX_EN,         RMII_TX_EN_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII_RX_ER,         RMII_RX_ER_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII_CRS_DV,        RMII_CRS_DV_MARK),
-        PINMUX_GPIO(GPIO_FN_LNKSTA,             LNKSTA_MARK),
-        PINMUX_GPIO(GPIO_FN_MDIO,               MDIO_MARK),
-        PINMUX_GPIO(GPIO_FN_MDC,                MDC_MARK),
+        GPIO_FN(RMII_RXD0),
+        GPIO_FN(RMII_RXD1),
+        GPIO_FN(RMII_TXD0),
+        GPIO_FN(RMII_TXD1),
+        GPIO_FN(RMII_REF_CLK),
+        GPIO_FN(RMII_TX_EN),
+        GPIO_FN(RMII_RX_ER),
+        GPIO_FN(RMII_CRS_DV),
+        GPIO_FN(LNKSTA),
+        GPIO_FN(MDIO),
+        GPIO_FN(MDC),
 
         /* System */
-        PINMUX_GPIO(GPIO_FN_PDSTATUS,   PDSTATUS_MARK),
-        PINMUX_GPIO(GPIO_FN_STATUS2,    STATUS2_MARK),
-        PINMUX_GPIO(GPIO_FN_STATUS0,    STATUS0_MARK),
+        GPIO_FN(PDSTATUS),
+        GPIO_FN(STATUS2),
+        GPIO_FN(STATUS0),
 
         /* VOU */
-        PINMUX_GPIO(GPIO_FN_DV_D15,     DV_D15_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D14,     DV_D14_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D13,     DV_D13_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D12,     DV_D12_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D11,     DV_D11_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D10,     DV_D10_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D9,      DV_D9_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D8,      DV_D8_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D7,      DV_D7_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D6,      DV_D6_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D5,      DV_D5_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D4,      DV_D4_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D3,      DV_D3_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D2,      DV_D2_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D1,      DV_D1_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_D0,      DV_D0_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_CLKI,    DV_CLKI_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_CLK,     DV_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_VSYNC,   DV_VSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_DV_HSYNC,   DV_HSYNC_MARK),
+        GPIO_FN(DV_D15),
+        GPIO_FN(DV_D14),
+        GPIO_FN(DV_D13),
+        GPIO_FN(DV_D12),
+        GPIO_FN(DV_D11),
+        GPIO_FN(DV_D10),
+        GPIO_FN(DV_D9),
+        GPIO_FN(DV_D8),
+        GPIO_FN(DV_D7),
+        GPIO_FN(DV_D6),
+        GPIO_FN(DV_D5),
+        GPIO_FN(DV_D4),
+        GPIO_FN(DV_D3),
+        GPIO_FN(DV_D2),
+        GPIO_FN(DV_D1),
+        GPIO_FN(DV_D0),
+        GPIO_FN(DV_CLKI),
+        GPIO_FN(DV_CLK),
+        GPIO_FN(DV_VSYNC),
+        GPIO_FN(DV_HSYNC),
 
         /* MSIOF0 */
-        PINMUX_GPIO(GPIO_FN_MSIOF0_RXD,         MSIOF0_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_TXD,         MSIOF0_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_MCK,         MSIOF0_MCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK,        MSIOF0_TSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_SS1,         MSIOF0_SS1_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_SS2,         MSIOF0_SS2_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC,       MSIOF0_TSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK,        MSIOF0_RSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC,       MSIOF0_RSYNC_MARK),
+        GPIO_FN(MSIOF0_RXD),
+        GPIO_FN(MSIOF0_TXD),
+        GPIO_FN(MSIOF0_MCK),
+        GPIO_FN(MSIOF0_TSCK),
+        GPIO_FN(MSIOF0_SS1),
+        GPIO_FN(MSIOF0_SS2),
+        GPIO_FN(MSIOF0_TSYNC),
+        GPIO_FN(MSIOF0_RSCK),
+        GPIO_FN(MSIOF0_RSYNC),
 
         /* MSIOF1 */
-        PINMUX_GPIO(GPIO_FN_MSIOF1_RXD,         MSIOF1_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_TXD,         MSIOF1_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_MCK,         MSIOF1_MCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK,        MSIOF1_TSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_SS1,         MSIOF1_SS1_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_SS2,         MSIOF1_SS2_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC,       MSIOF1_TSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK,        MSIOF1_RSCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC,       MSIOF1_RSYNC_MARK),
+        GPIO_FN(MSIOF1_RXD),
+        GPIO_FN(MSIOF1_TXD),
+        GPIO_FN(MSIOF1_MCK),
+        GPIO_FN(MSIOF1_TSCK),
+        GPIO_FN(MSIOF1_SS1),
+        GPIO_FN(MSIOF1_SS2),
+        GPIO_FN(MSIOF1_TSYNC),
+        GPIO_FN(MSIOF1_RSCK),
+        GPIO_FN(MSIOF1_RSYNC),
 
         /* DMAC */
-        PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK),
-        PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK),
-        PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK),
+        GPIO_FN(DMAC_DACK0),
+        GPIO_FN(DMAC_DREQ0),
+        GPIO_FN(DMAC_DACK1),
+        GPIO_FN(DMAC_DREQ1),
 
         /* SDHI0 */
-        PINMUX_GPIO(GPIO_FN_SDHI0CD,    SDHI0CD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0WP,    SDHI0WP_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0CMD,   SDHI0CMD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0CLK,   SDHI0CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D3,    SDHI0D3_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D2,    SDHI0D2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D1,    SDHI0D1_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI0D0,    SDHI0D0_MARK),
+        GPIO_FN(SDHI0CD),
+        GPIO_FN(SDHI0WP),
+        GPIO_FN(SDHI0CMD),
+        GPIO_FN(SDHI0CLK),
+        GPIO_FN(SDHI0D3),
+        GPIO_FN(SDHI0D2),
+        GPIO_FN(SDHI0D1),
+        GPIO_FN(SDHI0D0),
 
         /* SDHI1 */
-        PINMUX_GPIO(GPIO_FN_SDHI1CD,    SDHI1CD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1WP,    SDHI1WP_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1CMD,   SDHI1CMD_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1CLK,   SDHI1CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1D3,    SDHI1D3_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1D2,    SDHI1D2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1D1,    SDHI1D1_MARK),
-        PINMUX_GPIO(GPIO_FN_SDHI1D0,    SDHI1D0_MARK),
+        GPIO_FN(SDHI1CD),
+        GPIO_FN(SDHI1WP),
+        GPIO_FN(SDHI1CMD),
+        GPIO_FN(SDHI1CLK),
+        GPIO_FN(SDHI1D3),
+        GPIO_FN(SDHI1D2),
+        GPIO_FN(SDHI1D1),
+        GPIO_FN(SDHI1D0),
 
         /* MMC */
-        PINMUX_GPIO(GPIO_FN_MMC_D7,     MMC_D7_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_D6,     MMC_D6_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_D5,     MMC_D5_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_D4,     MMC_D4_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_D3,     MMC_D3_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_D2,     MMC_D2_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_D1,     MMC_D1_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_D0,     MMC_D0_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_CLK,    MMC_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_MMC_CMD,    MMC_CMD_MARK),
+        GPIO_FN(MMC_D7),
+        GPIO_FN(MMC_D6),
+        GPIO_FN(MMC_D5),
+        GPIO_FN(MMC_D4),
+        GPIO_FN(MMC_D3),
+        GPIO_FN(MMC_D2),
+        GPIO_FN(MMC_D1),
+        GPIO_FN(MMC_D0),
+        GPIO_FN(MMC_CLK),
+        GPIO_FN(MMC_CMD),
 
         /* IrDA */
-        PINMUX_GPIO(GPIO_FN_IRDA_OUT,   IRDA_OUT_MARK),
-        PINMUX_GPIO(GPIO_FN_IRDA_IN,    IRDA_IN_MARK),
+        GPIO_FN(IRDA_OUT),
+        GPIO_FN(IRDA_IN),
 
         /* TSIF */
-        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT,      TSIF_TS0_SDAT_MARK),
-        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK,       TSIF_TS0_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN,      TSIF_TS0_SDEN_MARK),
-        PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC,    TSIF_TS0_SPSYNC_MARK),
+        GPIO_FN(TSIF_TS0_SDAT),
+        GPIO_FN(TSIF_TS0_SCK),
+        GPIO_FN(TSIF_TS0_SDEN),
+        GPIO_FN(TSIF_TS0_SPSYNC),
 
         /* IRQ */
-        PINMUX_GPIO(GPIO_FN_INTC_IRQ7,  INTC_IRQ7_MARK),
-        PINMUX_GPIO(GPIO_FN_INTC_IRQ6,  INTC_IRQ6_MARK),
-        PINMUX_GPIO(GPIO_FN_INTC_IRQ5,  INTC_IRQ5_MARK),
-        PINMUX_GPIO(GPIO_FN_INTC_IRQ4,  INTC_IRQ4_MARK),
-        PINMUX_GPIO(GPIO_FN_INTC_IRQ3,  INTC_IRQ3_MARK),
-        PINMUX_GPIO(GPIO_FN_INTC_IRQ2,  INTC_IRQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_INTC_IRQ1,  INTC_IRQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_INTC_IRQ0,  INTC_IRQ0_MARK),
+        GPIO_FN(INTC_IRQ7),
+        GPIO_FN(INTC_IRQ6),
+        GPIO_FN(INTC_IRQ5),
+        GPIO_FN(INTC_IRQ4),
+        GPIO_FN(INTC_IRQ3),
+        GPIO_FN(INTC_IRQ2),
+        GPIO_FN(INTC_IRQ1),
+        GPIO_FN(INTC_IRQ0),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
                 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
                 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
@@ -2107,7 +2111,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         {}
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
                 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
                 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -2203,20 +2207,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info sh7724_pinmux_info = {
+const struct sh_pfc_soc_info sh7724_pinmux_info = {
         .name = "sh7724_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
         .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PTA7,
-        .last_gpio = GPIO_FN_INTC_IRQ0,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index 23d76d262c32..2fd5b7d4cb94 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -14,11 +14,6 @@
 
 #include "sh_pfc.h"
 
-#define CPU_32_PORT(fn, pfx, sfx)                               \
-        PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),        \
-        PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),     \
-        PORT_1(fn, pfx##31, sfx)
-
 #define CPU_32_PORT5(fn, pfx, sfx)                              \
         PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),       \
         PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),       \
@@ -29,11 +24,11 @@
 
 /* GPSR0 - GPSR5 */
 #define CPU_ALL_PORT(fn, pfx, sfx)                              \
-        CPU_32_PORT(fn, pfx##_0_, sfx),                 \
-        CPU_32_PORT(fn, pfx##_1_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_2_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_3_, sfx),                         \
-        CPU_32_PORT(fn, pfx##_4_, sfx),                         \
+        PORT_32(fn, pfx##_0_, sfx),                     \
+        PORT_32(fn, pfx##_1_, sfx),                             \
+        PORT_32(fn, pfx##_2_, sfx),                             \
+        PORT_32(fn, pfx##_3_, sfx),                             \
+        PORT_32(fn, pfx##_4_, sfx),                             \
         CPU_32_PORT5(fn, pfx##_5_, sfx)
 
 #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
@@ -47,20 +42,8 @@
 #define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, , unused)
 #define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, , unused)
 
-#define PORT_10_REV(fn, pfx, sfx)       \
-        PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),       \
-        PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),       \
-        PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),       \
-        PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),       \
-        PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx)   \
-        PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),     \
-        PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),     \
-        PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
 
 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
@@ -609,7 +592,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 
         PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
@@ -1384,9 +1367,13 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
         PINMUX_GPIO_GP_ALL(),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
         GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
         GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
@@ -1665,7 +1652,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) {
                 GP_0_31_FN, FN_IP2_2_0,
                 GP_0_30_FN, FN_IP1_31_29,
@@ -2434,7 +2421,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         { },
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         /* GPIO 0 - 5*/
         { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } },
         { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } },
@@ -2451,22 +2438,20 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info sh7734_pinmux_info = {
+const struct sh_pfc_soc_info sh7734_pinmux_info = {
         .name = "sh7734_pfc",
 
         .unlock_reg = 0xFFFC0000,
 
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_GP_0_0,
-        .last_gpio = GPIO_FN_ST_CLKOUT,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index 5ed74cd0ba99..e074230e6243 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -526,7 +526,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
         /* PTA GPIO */
         PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
         PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@@ -1114,7 +1114,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
         /* PTA */
         PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
         PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1370,359 +1370,363 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
         PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
         PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* PTA (mobule: LBSC, RGMII) */
-        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
-        PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
-        PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK),
-        PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK),
-        PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK),
-        PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK),
-        PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK),
-        PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK),
+        GPIO_FN(BS),
+        GPIO_FN(RDWR),
+        GPIO_FN(WE1),
+        GPIO_FN(RDY),
+        GPIO_FN(ET0_MDC),
+        GPIO_FN(ET0_MDIO),
+        GPIO_FN(ET1_MDC),
+        GPIO_FN(ET1_MDIO),
 
         /* PTB (mobule: INTC, ONFI, TMU) */
-        PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
+        GPIO_FN(IRQ15),
+        GPIO_FN(IRQ14),
+        GPIO_FN(IRQ13),
+        GPIO_FN(IRQ12),
+        GPIO_FN(IRQ11),
+        GPIO_FN(IRQ10),
+        GPIO_FN(IRQ9),
+        GPIO_FN(IRQ8),
+        GPIO_FN(ON_NRE),
+        GPIO_FN(ON_NWE),
+        GPIO_FN(ON_NWP),
+        GPIO_FN(ON_NCE0),
+        GPIO_FN(ON_R_B0),
+        GPIO_FN(ON_ALE),
+        GPIO_FN(ON_CLE),
+        GPIO_FN(TCLK),
 
         /* PTC (mobule: IRQ, PWMU) */
-        PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK),
+        GPIO_FN(IRQ7),
+        GPIO_FN(IRQ6),
+        GPIO_FN(IRQ5),
+        GPIO_FN(IRQ4),
+        GPIO_FN(IRQ3),
+        GPIO_FN(IRQ2),
+        GPIO_FN(IRQ1),
+        GPIO_FN(IRQ0),
+        GPIO_FN(PWMU0),
+        GPIO_FN(PWMU1),
+        GPIO_FN(PWMU2),
+        GPIO_FN(PWMU3),
+        GPIO_FN(PWMU4),
+        GPIO_FN(PWMU5),
 
         /* PTD (mobule: SPI0, DMAC) */
-        PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK),
-        PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK),
-        PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK),
-        PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK),
-        PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
-        PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK),
-        PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
+        GPIO_FN(SP0_MOSI),
+        GPIO_FN(SP0_MISO),
+        GPIO_FN(SP0_SCK),
+        GPIO_FN(SP0_SCK_FB),
+        GPIO_FN(SP0_SS0),
+        GPIO_FN(SP0_SS1),
+        GPIO_FN(SP0_SS2),
+        GPIO_FN(SP0_SS3),
+        GPIO_FN(DREQ0),
+        GPIO_FN(DACK0),
+        GPIO_FN(TEND0),
 
         /* PTE (mobule: RMII) */
-        PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK),
+        GPIO_FN(RMII0_CRS_DV),
+        GPIO_FN(RMII0_TXD1),
+        GPIO_FN(RMII0_TXD0),
+        GPIO_FN(RMII0_TXEN),
+        GPIO_FN(RMII0_REFCLK),
+        GPIO_FN(RMII0_RXD1),
+        GPIO_FN(RMII0_RXD0),
+        GPIO_FN(RMII0_RX_ER),
 
         /* PTF (mobule: RMII, SerMux) */
-        PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK),
-        PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
+        GPIO_FN(RMII1_CRS_DV),
+        GPIO_FN(RMII1_TXD1),
+        GPIO_FN(RMII1_TXD0),
+        GPIO_FN(RMII1_TXEN),
+        GPIO_FN(RMII1_REFCLK),
+        GPIO_FN(RMII1_RXD1),
+        GPIO_FN(RMII1_RXD0),
+        GPIO_FN(RMII1_RX_ER),
+        GPIO_FN(RAC_RI),
 
         /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
-        PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK),
-        PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK),
-        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
-        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
-        PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK),
-        PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
-        PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK),
-        PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK),
+        GPIO_FN(BOOTFMS),
+        GPIO_FN(BOOTWP),
+        GPIO_FN(A25),
+        GPIO_FN(A24),
+        GPIO_FN(SERIRQ),
+        GPIO_FN(WDTOVF),
+        GPIO_FN(LPCPD),
+        GPIO_FN(LDRQ),
+        GPIO_FN(MMCCLK),
+        GPIO_FN(MMCCMD),
 
         /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
-        PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK),
-        PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK),
-        PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK),
-        PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK),
-        PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK),
-        PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
-        PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
-        PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
-        PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
+        GPIO_FN(SP1_MOSI),
+        GPIO_FN(SP1_MISO),
+        GPIO_FN(SP1_SCK),
+        GPIO_FN(SP1_SCK_FB),
+        GPIO_FN(SP1_SS0),
+        GPIO_FN(SP1_SS1),
+        GPIO_FN(WP),
+        GPIO_FN(FMS0),
+        GPIO_FN(TEND1),
+        GPIO_FN(DREQ1),
+        GPIO_FN(DACK1),
+        GPIO_FN(ADTRG1),
+        GPIO_FN(ADTRG0),
 
         /* PTI (mobule: LBSC, SDHI) */
-        PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
-        PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
-        PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
-        PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
-        PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
-        PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
-        PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
-        PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
+        GPIO_FN(D15),
+        GPIO_FN(D14),
+        GPIO_FN(D13),
+        GPIO_FN(D12),
+        GPIO_FN(D11),
+        GPIO_FN(D10),
+        GPIO_FN(D9),
+        GPIO_FN(D8),
+        GPIO_FN(SD_WP),
+        GPIO_FN(SD_CD),
+        GPIO_FN(SD_CLK),
+        GPIO_FN(SD_CMD),
+        GPIO_FN(SD_D3),
+        GPIO_FN(SD_D2),
+        GPIO_FN(SD_D1),
+        GPIO_FN(SD_D0),
 
         /* PTJ (mobule: SCIF234, SERMUX) */
-        PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
+        GPIO_FN(RTS3),
+        GPIO_FN(CTS3),
+        GPIO_FN(TXD3),
+        GPIO_FN(RXD3),
+        GPIO_FN(RTS4),
+        GPIO_FN(RXD4),
+        GPIO_FN(TXD4),
 
         /* PTK (mobule: SERMUX, LBSC, SCIF) */
-        PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK),
-        PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK),
-        PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK),
-        PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
+        GPIO_FN(COM2_TXD),
+        GPIO_FN(COM2_RXD),
+        GPIO_FN(COM2_RTS),
+        GPIO_FN(COM2_CTS),
+        GPIO_FN(COM2_DTR),
+        GPIO_FN(COM2_DSR),
+        GPIO_FN(COM2_DCD),
+        GPIO_FN(CLKOUT),
+        GPIO_FN(SCK2),
+        GPIO_FN(SCK4),
+        GPIO_FN(SCK3),
 
         /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
-        PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK),
-        PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK),
-        PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK),
-        PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
+        GPIO_FN(RAC_RXD),
+        GPIO_FN(RAC_RTS),
+        GPIO_FN(RAC_CTS),
+        GPIO_FN(RAC_DTR),
+        GPIO_FN(RAC_DSR),
+        GPIO_FN(RAC_DCD),
+        GPIO_FN(RAC_TXD),
+        GPIO_FN(RXD2),
+        GPIO_FN(CS5),
+        GPIO_FN(CS6),
+        GPIO_FN(AUDSYNC),
+        GPIO_FN(AUDCK),
+        GPIO_FN(TXD2),
 
         /* PTM (mobule: LBSC, IIC) */
-        PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
-        PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
-        PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
-        PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK),
+        GPIO_FN(CS4),
+        GPIO_FN(RD),
+        GPIO_FN(WE0),
+        GPIO_FN(CS0),
+        GPIO_FN(SDA6),
+        GPIO_FN(SCL6),
+        GPIO_FN(SDA7),
+        GPIO_FN(SCL7),
 
         /* PTN (mobule: USB, JMC, SGPIO, WDT) */
-        PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK),
-        PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK),
-        PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
-        PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
-        PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
-        PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
-        PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
-        PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK),
+        GPIO_FN(VBUS_EN),
+        GPIO_FN(VBUS_OC),
+        GPIO_FN(JMCTCK),
+        GPIO_FN(JMCTMS),
+        GPIO_FN(JMCTDO),
+        GPIO_FN(JMCTDI),
+        GPIO_FN(JMCTRST),
+        GPIO_FN(SGPIO1_CLK),
+        GPIO_FN(SGPIO1_LOAD),
+        GPIO_FN(SGPIO1_DI),
+        GPIO_FN(SGPIO1_DO),
+        GPIO_FN(SUB_CLKIN),
 
         /* PTO (mobule: SGPIO, SerMux) */
-        PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK),
-        PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
+        GPIO_FN(SGPIO0_CLK),
+        GPIO_FN(SGPIO0_LOAD),
+        GPIO_FN(SGPIO0_DI),
+        GPIO_FN(SGPIO0_DO),
+        GPIO_FN(SGPIO2_CLK),
+        GPIO_FN(SGPIO2_LOAD),
+        GPIO_FN(SGPIO2_DI),
+        GPIO_FN(SGPIO2_DO),
+        GPIO_FN(COM1_TXD),
+        GPIO_FN(COM1_RXD),
+        GPIO_FN(COM1_RTS),
+        GPIO_FN(COM1_CTS),
 
         /* PTP (mobule: EVC, ADC) */
 
         /* PTQ (mobule: LPC) */
-        PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK),
-        PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK),
-        PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK),
-        PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK),
-        PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK),
-        PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK),
-        PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK),
+        GPIO_FN(LAD3),
+        GPIO_FN(LAD2),
+        GPIO_FN(LAD1),
+        GPIO_FN(LAD0),
+        GPIO_FN(LFRAME),
+        GPIO_FN(LRESET),
+        GPIO_FN(LCLK),
 
         /* PTR (mobule: GRA, IIC) */
-        PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK),
-        PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
+        GPIO_FN(DDC3),
+        GPIO_FN(DDC2),
+        GPIO_FN(SDA8),
+        GPIO_FN(SCL8),
+        GPIO_FN(SDA2),
+        GPIO_FN(SCL2),
+        GPIO_FN(SDA1),
+        GPIO_FN(SCL1),
+        GPIO_FN(SDA0),
+        GPIO_FN(SCL0),
 
         /* PTS (mobule: GRA, IIC) */
-        PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK),
-        PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK),
-        PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
-        PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
+        GPIO_FN(DDC1),
+        GPIO_FN(DDC0),
+        GPIO_FN(SDA9),
+        GPIO_FN(SCL9),
+        GPIO_FN(SDA5),
+        GPIO_FN(SCL5),
+        GPIO_FN(SDA4),
+        GPIO_FN(SCL4),
+        GPIO_FN(SDA3),
+        GPIO_FN(SCL3),
 
         /* PTT (mobule: PWMX, AUD) */
-        PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK),
-        PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
-        PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
-        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
+        GPIO_FN(PWMX7),
+        GPIO_FN(PWMX6),
+        GPIO_FN(PWMX5),
+        GPIO_FN(PWMX4),
+        GPIO_FN(PWMX3),
+        GPIO_FN(PWMX2),
+        GPIO_FN(PWMX1),
+        GPIO_FN(PWMX0),
+        GPIO_FN(AUDATA3),
+        GPIO_FN(AUDATA2),
+        GPIO_FN(AUDATA1),
+        GPIO_FN(AUDATA0),
+        GPIO_FN(STATUS1),
+        GPIO_FN(STATUS0),
 
         /* PTU (mobule: LPC, APM) */
-        PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
-        PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK),
-        PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK),
-        PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK),
-        PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK),
-        PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK),
-        PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK),
-        PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK),
-        PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK),
+        GPIO_FN(LGPIO7),
+        GPIO_FN(LGPIO6),
+        GPIO_FN(LGPIO5),
+        GPIO_FN(LGPIO4),
+        GPIO_FN(LGPIO3),
+        GPIO_FN(LGPIO2),
+        GPIO_FN(LGPIO1),
+        GPIO_FN(LGPIO0),
+        GPIO_FN(APMONCTL_O),
+        GPIO_FN(APMPWBTOUT_O),
+        GPIO_FN(APMSCI_O),
+        GPIO_FN(APMVDDON),
+        GPIO_FN(APMSLPBTN),
+        GPIO_FN(APMPWRBTN),
+        GPIO_FN(APMS5N),
+        GPIO_FN(APMS3N),
 
         /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
-        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
-        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
-        PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
-        PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
-        PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
-        PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
-        PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
-        PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
-        PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
-        PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK),
-        PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK),
-        PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK),
-        PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK),
-        PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
-        PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK),
-        PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK),
-        PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK),
+        GPIO_FN(A23),
+        GPIO_FN(A22),
+        GPIO_FN(A21),
+        GPIO_FN(A20),
+        GPIO_FN(A19),
+        GPIO_FN(A18),
+        GPIO_FN(A17),
+        GPIO_FN(A16),
+        GPIO_FN(COM2_RI),
+        GPIO_FN(R_SPI_MOSI),
+        GPIO_FN(R_SPI_MISO),
+        GPIO_FN(R_SPI_RSPCK),
+        GPIO_FN(R_SPI_SSL0),
+        GPIO_FN(R_SPI_SSL1),
+        GPIO_FN(EVENT7),
+        GPIO_FN(EVENT6),
+        GPIO_FN(VBIOS_DI),
+        GPIO_FN(VBIOS_DO),
+        GPIO_FN(VBIOS_CLK),
+        GPIO_FN(VBIOS_CS),
 
         /* PTW (mobule: LBSC, EVC, SCIF) */
-        PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
-        PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
-        PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
-        PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
-        PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
-        PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
-        PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
-        PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
-        PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
+        GPIO_FN(A16),
+        GPIO_FN(A15),
+        GPIO_FN(A14),
+        GPIO_FN(A13),
+        GPIO_FN(A12),
+        GPIO_FN(A11),
+        GPIO_FN(A10),
+        GPIO_FN(A9),
+        GPIO_FN(A8),
+        GPIO_FN(EVENT5),
+        GPIO_FN(EVENT4),
+        GPIO_FN(EVENT3),
+        GPIO_FN(EVENT2),
+        GPIO_FN(EVENT1),
+        GPIO_FN(EVENT0),
+        GPIO_FN(CTS4),
+        GPIO_FN(CTS2),
 
         /* PTX (mobule: LBSC) */
-        PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
-        PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
-        PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
-        PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
-        PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
-        PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
-        PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
-        PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
-        PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
-        PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
+        GPIO_FN(A7),
+        GPIO_FN(A6),
+        GPIO_FN(A5),
+        GPIO_FN(A4),
+        GPIO_FN(A3),
+        GPIO_FN(A2),
+        GPIO_FN(A1),
+        GPIO_FN(A0),
+        GPIO_FN(RTS2),
+        GPIO_FN(SIM_D),
+        GPIO_FN(SIM_CLK),
+        GPIO_FN(SIM_RST),
 
         /* PTY (mobule: LBSC) */
-        PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
-        PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
-        PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
-        PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
-        PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
-        PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
-        PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
-        PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
+        GPIO_FN(D7),
+        GPIO_FN(D6),
+        GPIO_FN(D5),
+        GPIO_FN(D4),
+        GPIO_FN(D3),
+        GPIO_FN(D2),
+        GPIO_FN(D1),
+        GPIO_FN(D0),
 
         /* PTZ (mobule: eMMC, ONFI) */
-        PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK),
+        GPIO_FN(MMCDAT7),
+        GPIO_FN(MMCDAT6),
+        GPIO_FN(MMCDAT5),
+        GPIO_FN(MMCDAT4),
+        GPIO_FN(MMCDAT3),
+        GPIO_FN(MMCDAT2),
+        GPIO_FN(MMCDAT1),
+        GPIO_FN(MMCDAT0),
+        GPIO_FN(ON_DQ7),
+        GPIO_FN(ON_DQ6),
+        GPIO_FN(ON_DQ5),
+        GPIO_FN(ON_DQ4),
+        GPIO_FN(ON_DQ3),
+        GPIO_FN(ON_DQ2),
+        GPIO_FN(ON_DQ1),
+        GPIO_FN(ON_DQ0),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
                 PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
                 PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
@@ -2152,7 +2156,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         {}
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
                 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
                 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -2260,20 +2264,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info sh7757_pinmux_info = {
+const struct sh_pfc_soc_info sh7757_pinmux_info = {
         .name = "sh7757_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
         .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PTA0,
-        .last_gpio = GPIO_FN_ON_DQ0,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index 3b1825d925bb..c176b794f240 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -355,7 +355,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
 
         /* PA GPIO */
         PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -702,7 +702,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
         /* PA */
         PINMUX_GPIO(GPIO_PA7, PA7_DATA),
         PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -845,176 +845,180 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PR2, PR2_DATA),
         PINMUX_GPIO(GPIO_PR1, PR1_DATA),
         PINMUX_GPIO(GPIO_PR0, PR0_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* FN */
-        PINMUX_GPIO(GPIO_FN_D63_AD31, D63_AD31_MARK),
-        PINMUX_GPIO(GPIO_FN_D62_AD30, D62_AD30_MARK),
-        PINMUX_GPIO(GPIO_FN_D61_AD29, D61_AD29_MARK),
-        PINMUX_GPIO(GPIO_FN_D60_AD28, D60_AD28_MARK),
-        PINMUX_GPIO(GPIO_FN_D59_AD27, D59_AD27_MARK),
-        PINMUX_GPIO(GPIO_FN_D58_AD26, D58_AD26_MARK),
-        PINMUX_GPIO(GPIO_FN_D57_AD25, D57_AD25_MARK),
-        PINMUX_GPIO(GPIO_FN_D56_AD24, D56_AD24_MARK),
-        PINMUX_GPIO(GPIO_FN_D55_AD23, D55_AD23_MARK),
-        PINMUX_GPIO(GPIO_FN_D54_AD22, D54_AD22_MARK),
-        PINMUX_GPIO(GPIO_FN_D53_AD21, D53_AD21_MARK),
-        PINMUX_GPIO(GPIO_FN_D52_AD20, D52_AD20_MARK),
-        PINMUX_GPIO(GPIO_FN_D51_AD19, D51_AD19_MARK),
-        PINMUX_GPIO(GPIO_FN_D50_AD18, D50_AD18_MARK),
-        PINMUX_GPIO(GPIO_FN_D49_AD17_DB5, D49_AD17_DB5_MARK),
-        PINMUX_GPIO(GPIO_FN_D48_AD16_DB4, D48_AD16_DB4_MARK),
-        PINMUX_GPIO(GPIO_FN_D47_AD15_DB3, D47_AD15_DB3_MARK),
-        PINMUX_GPIO(GPIO_FN_D46_AD14_DB2, D46_AD14_DB2_MARK),
-        PINMUX_GPIO(GPIO_FN_D45_AD13_DB1, D45_AD13_DB1_MARK),
-        PINMUX_GPIO(GPIO_FN_D44_AD12_DB0, D44_AD12_DB0_MARK),
-        PINMUX_GPIO(GPIO_FN_D43_AD11_DG5, D43_AD11_DG5_MARK),
-        PINMUX_GPIO(GPIO_FN_D42_AD10_DG4, D42_AD10_DG4_MARK),
-        PINMUX_GPIO(GPIO_FN_D41_AD9_DG3, D41_AD9_DG3_MARK),
-        PINMUX_GPIO(GPIO_FN_D40_AD8_DG2, D40_AD8_DG2_MARK),
-        PINMUX_GPIO(GPIO_FN_D39_AD7_DG1, D39_AD7_DG1_MARK),
-        PINMUX_GPIO(GPIO_FN_D38_AD6_DG0, D38_AD6_DG0_MARK),
-        PINMUX_GPIO(GPIO_FN_D37_AD5_DR5, D37_AD5_DR5_MARK),
-        PINMUX_GPIO(GPIO_FN_D36_AD4_DR4, D36_AD4_DR4_MARK),
-        PINMUX_GPIO(GPIO_FN_D35_AD3_DR3, D35_AD3_DR3_MARK),
-        PINMUX_GPIO(GPIO_FN_D34_AD2_DR2, D34_AD2_DR2_MARK),
-        PINMUX_GPIO(GPIO_FN_D33_AD1_DR1, D33_AD1_DR1_MARK),
-        PINMUX_GPIO(GPIO_FN_D32_AD0_DR0, D32_AD0_DR0_MARK),
-        PINMUX_GPIO(GPIO_FN_REQ1, REQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_REQ2, REQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_REQ3, REQ3_MARK),
-        PINMUX_GPIO(GPIO_FN_GNT1, GNT1_MARK),
-        PINMUX_GPIO(GPIO_FN_GNT2, GNT2_MARK),
-        PINMUX_GPIO(GPIO_FN_GNT3, GNT3_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
-        PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
-        PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
-        PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
-        PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
-        PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
-        PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
-        PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
-        PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
-        PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
-        PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
-        PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
-        PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
-        PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
-        PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
-        PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_INTD, INTD_MARK),
-        PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK),
-        PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_FRE, FRE_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK),
-        PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK),
-        PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF_TXD_PJ, SIOF_TXD_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF_RXD_PJ, SIOF_RXD_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF_SYNC_PJ, SIOF_SYNC_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF_MCLK_PJ, SIOF_MCLK_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF_SCK_PJ, SIOF_SCK_PJ_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
-        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK0_PK3, DRAK0_PK3_MARK),
-        PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK1_PK2, DRAK1_PK2_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF_TXD_PK, SIOF_TXD_PK_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_MMCDAT, MMCDAT_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF_SCK_PK, SIOF_SCK_PK_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK0_PK1, DRAK0_PK1_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK1_PK0, DRAK1_PK0_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_INTB, INTB_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
-        PINMUX_GPIO(GPIO_FN_INTC, INTC_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK),
-        PINMUX_GPIO(GPIO_FN_FD4, FD4_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK),
-        PINMUX_GPIO(GPIO_FN_FD5, FD5_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK),
-        PINMUX_GPIO(GPIO_FN_FD6, FD6_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK),
-        PINMUX_GPIO(GPIO_FN_FD7, FD7_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
-        PINMUX_GPIO(GPIO_FN_BREQ_BSACK, BREQ_BSACK_MARK),
-        PINMUX_GPIO(GPIO_FN_BACK_BSREQ, BACK_BSREQ_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_FD0, FD0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_FD1, FD1_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_FD2, FD2_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_FD3, FD3_MARK),
-        PINMUX_GPIO(GPIO_FN_DEVSEL_DCLKOUT, DEVSEL_DCLKOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_STOP_CDE, STOP_CDE_MARK),
-        PINMUX_GPIO(GPIO_FN_LOCK_ODDF, LOCK_ODDF_MARK),
-        PINMUX_GPIO(GPIO_FN_TRDY_DISPL, TRDY_DISPL_MARK),
-        PINMUX_GPIO(GPIO_FN_IRDY_HSYNC, IRDY_HSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_PCIFRAME_VSYNC, PCIFRAME_VSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_INTA, INTA_MARK),
-        PINMUX_GPIO(GPIO_FN_GNT0_GNTIN, GNT0_GNTIN_MARK),
-        PINMUX_GPIO(GPIO_FN_REQ0_REQOUT, REQ0_REQOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_PERR, PERR_MARK),
-        PINMUX_GPIO(GPIO_FN_SERR, SERR_MARK),
-        PINMUX_GPIO(GPIO_FN_WE7_CBE3, WE7_CBE3_MARK),
-        PINMUX_GPIO(GPIO_FN_WE6_CBE2, WE6_CBE2_MARK),
-        PINMUX_GPIO(GPIO_FN_WE5_CBE1, WE5_CBE1_MARK),
-        PINMUX_GPIO(GPIO_FN_WE4_CBE0, WE4_CBE0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SIOF_RXD, SIOF_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_MRESETOUT, MRESETOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
+        GPIO_FN(D63_AD31),
+        GPIO_FN(D62_AD30),
+        GPIO_FN(D61_AD29),
+        GPIO_FN(D60_AD28),
+        GPIO_FN(D59_AD27),
+        GPIO_FN(D58_AD26),
+        GPIO_FN(D57_AD25),
+        GPIO_FN(D56_AD24),
+        GPIO_FN(D55_AD23),
+        GPIO_FN(D54_AD22),
+        GPIO_FN(D53_AD21),
+        GPIO_FN(D52_AD20),
+        GPIO_FN(D51_AD19),
+        GPIO_FN(D50_AD18),
+        GPIO_FN(D49_AD17_DB5),
+        GPIO_FN(D48_AD16_DB4),
+        GPIO_FN(D47_AD15_DB3),
+        GPIO_FN(D46_AD14_DB2),
+        GPIO_FN(D45_AD13_DB1),
+        GPIO_FN(D44_AD12_DB0),
+        GPIO_FN(D43_AD11_DG5),
+        GPIO_FN(D42_AD10_DG4),
+        GPIO_FN(D41_AD9_DG3),
+        GPIO_FN(D40_AD8_DG2),
+        GPIO_FN(D39_AD7_DG1),
+        GPIO_FN(D38_AD6_DG0),
+        GPIO_FN(D37_AD5_DR5),
+        GPIO_FN(D36_AD4_DR4),
+        GPIO_FN(D35_AD3_DR3),
+        GPIO_FN(D34_AD2_DR2),
+        GPIO_FN(D33_AD1_DR1),
+        GPIO_FN(D32_AD0_DR0),
+        GPIO_FN(REQ1),
+        GPIO_FN(REQ2),
+        GPIO_FN(REQ3),
+        GPIO_FN(GNT1),
+        GPIO_FN(GNT2),
+        GPIO_FN(GNT3),
+        GPIO_FN(MMCCLK),
+        GPIO_FN(D31),
+        GPIO_FN(D30),
+        GPIO_FN(D29),
+        GPIO_FN(D28),
+        GPIO_FN(D27),
+        GPIO_FN(D26),
+        GPIO_FN(D25),
+        GPIO_FN(D24),
+        GPIO_FN(D23),
+        GPIO_FN(D22),
+        GPIO_FN(D21),
+        GPIO_FN(D20),
+        GPIO_FN(D19),
+        GPIO_FN(D18),
+        GPIO_FN(D17),
+        GPIO_FN(D16),
+        GPIO_FN(SCIF1_SCK),
+        GPIO_FN(SCIF1_RXD),
+        GPIO_FN(SCIF1_TXD),
+        GPIO_FN(SCIF0_CTS),
+        GPIO_FN(INTD),
+        GPIO_FN(FCE),
+        GPIO_FN(SCIF0_RTS),
+        GPIO_FN(HSPI_CS),
+        GPIO_FN(FSE),
+        GPIO_FN(SCIF0_SCK),
+        GPIO_FN(HSPI_CLK),
+        GPIO_FN(FRE),
+        GPIO_FN(SCIF0_RXD),
+        GPIO_FN(HSPI_RX),
+        GPIO_FN(FRB),
+        GPIO_FN(SCIF0_TXD),
+        GPIO_FN(HSPI_TX),
+        GPIO_FN(FWE),
+        GPIO_FN(SCIF5_TXD),
+        GPIO_FN(HAC1_SYNC),
+        GPIO_FN(SSI1_WS),
+        GPIO_FN(SIOF_TXD_PJ),
+        GPIO_FN(HAC0_SDOUT),
+        GPIO_FN(SSI0_SDATA),
+        GPIO_FN(SIOF_RXD_PJ),
+        GPIO_FN(HAC0_SDIN),
+        GPIO_FN(SSI0_SCK),
+        GPIO_FN(SIOF_SYNC_PJ),
+        GPIO_FN(HAC0_SYNC),
+        GPIO_FN(SSI0_WS),
+        GPIO_FN(SIOF_MCLK_PJ),
+        GPIO_FN(HAC_RES),
+        GPIO_FN(SIOF_SCK_PJ),
+        GPIO_FN(HAC0_BITCLK),
+        GPIO_FN(SSI0_CLK),
+        GPIO_FN(HAC1_BITCLK),
+        GPIO_FN(SSI1_CLK),
+        GPIO_FN(TCLK),
+        GPIO_FN(IOIS16),
+        GPIO_FN(STATUS0),
+        GPIO_FN(DRAK0_PK3),
+        GPIO_FN(STATUS1),
+        GPIO_FN(DRAK1_PK2),
+        GPIO_FN(DACK2),
+        GPIO_FN(SCIF2_TXD),
+        GPIO_FN(MMCCMD),
+        GPIO_FN(SIOF_TXD_PK),
+        GPIO_FN(DACK3),
+        GPIO_FN(SCIF2_SCK),
+        GPIO_FN(MMCDAT),
+        GPIO_FN(SIOF_SCK_PK),
+        GPIO_FN(DREQ0),
+        GPIO_FN(DREQ1),
+        GPIO_FN(DRAK0_PK1),
+        GPIO_FN(DRAK1_PK0),
+        GPIO_FN(DREQ2),
+        GPIO_FN(INTB),
+        GPIO_FN(DREQ3),
+        GPIO_FN(INTC),
+        GPIO_FN(DRAK2),
+        GPIO_FN(CE2A),
+        GPIO_FN(IRL4),
+        GPIO_FN(FD4),
+        GPIO_FN(IRL5),
+        GPIO_FN(FD5),
+        GPIO_FN(IRL6),
+        GPIO_FN(FD6),
+        GPIO_FN(IRL7),
+        GPIO_FN(FD7),
+        GPIO_FN(DRAK3),
+        GPIO_FN(CE2B),
+        GPIO_FN(BREQ_BSACK),
+        GPIO_FN(BACK_BSREQ),
+        GPIO_FN(SCIF5_RXD),
+        GPIO_FN(HAC1_SDIN),
+        GPIO_FN(SSI1_SCK),
+        GPIO_FN(SCIF5_SCK),
+        GPIO_FN(HAC1_SDOUT),
+        GPIO_FN(SSI1_SDATA),
+        GPIO_FN(SCIF3_TXD),
+        GPIO_FN(FCLE),
+        GPIO_FN(SCIF3_RXD),
+        GPIO_FN(FALE),
+        GPIO_FN(SCIF3_SCK),
+        GPIO_FN(FD0),
+        GPIO_FN(SCIF4_TXD),
+        GPIO_FN(FD1),
+        GPIO_FN(SCIF4_RXD),
+        GPIO_FN(FD2),
+        GPIO_FN(SCIF4_SCK),
+        GPIO_FN(FD3),
+        GPIO_FN(DEVSEL_DCLKOUT),
+        GPIO_FN(STOP_CDE),
+        GPIO_FN(LOCK_ODDF),
+        GPIO_FN(TRDY_DISPL),
+        GPIO_FN(IRDY_HSYNC),
+        GPIO_FN(PCIFRAME_VSYNC),
+        GPIO_FN(INTA),
+        GPIO_FN(GNT0_GNTIN),
+        GPIO_FN(REQ0_REQOUT),
+        GPIO_FN(PERR),
+        GPIO_FN(SERR),
+        GPIO_FN(WE7_CBE3),
+        GPIO_FN(WE6_CBE2),
+        GPIO_FN(WE5_CBE1),
+        GPIO_FN(WE4_CBE0),
+        GPIO_FN(SCIF2_RXD),
+        GPIO_FN(SIOF_RXD),
+        GPIO_FN(MRESETOUT),
+        GPIO_FN(IRQOUT),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) {
                 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
                 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -1214,7 +1218,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         {}
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PADR", 0xffe70020, 8) {
                 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
                 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
@@ -1282,20 +1286,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info sh7785_pinmux_info = {
+const struct sh_pfc_soc_info sh7785_pinmux_info = {
         .name = "sh7785_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
         .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PA7,
-        .last_gpio = GPIO_FN_IRQOUT,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index 1e18b58f9e5f..8ae0e32844e9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -191,7 +191,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
 
         /* PA GPIO */
         PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -427,7 +427,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(SSI3_SCK_MARK,      P2MSEL6_1, P2MSEL5_1, PJ1_FN),
 };
 
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
         /* PA */
         PINMUX_GPIO(GPIO_PA7, PA7_DATA),
         PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -505,147 +505,151 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
         PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
         PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
 
+static const struct pinmux_func pinmux_func_gpios[] = {
         /* FN */
-        PINMUX_GPIO(GPIO_FN_CDE,                CDE_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_MAGIC,          ETH_MAGIC_MARK),
-        PINMUX_GPIO(GPIO_FN_DISP,               DISP_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_LINK,           ETH_LINK_MARK),
-        PINMUX_GPIO(GPIO_FN_DR5,                DR5_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_TX_ER,          ETH_TX_ER_MARK),
-        PINMUX_GPIO(GPIO_FN_DR4,                DR4_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_TX_EN,          ETH_TX_EN_MARK),
-        PINMUX_GPIO(GPIO_FN_DR3,                DR3_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_TXD3,           ETH_TXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_DR2,                DR2_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_TXD2,           ETH_TXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_DR1,                DR1_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_TXD1,           ETH_TXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_DR0,                DR0_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_TXD0,           ETH_TXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_VSYNC,              VSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_HSPI_CLK,           HSPI_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_ODDF,               ODDF_MARK),
-        PINMUX_GPIO(GPIO_FN_HSPI_CS,            HSPI_CS_MARK),
-        PINMUX_GPIO(GPIO_FN_DG5,                DG5_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_MDIO,           ETH_MDIO_MARK),
-        PINMUX_GPIO(GPIO_FN_DG4,                DG4_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_RX_CLK,         ETH_RX_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_DG3,                DG3_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_MDC,            ETH_MDC_MARK),
-        PINMUX_GPIO(GPIO_FN_DG2,                DG2_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_COL,            ETH_COL_MARK),
-        PINMUX_GPIO(GPIO_FN_DG1,                DG1_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_TX_CLK,         ETH_TX_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_DG0,                DG0_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_CRS,            ETH_CRS_MARK),
-        PINMUX_GPIO(GPIO_FN_DCLKIN,             DCLKIN_MARK),
-        PINMUX_GPIO(GPIO_FN_HSPI_RX,            HSPI_RX_MARK),
-        PINMUX_GPIO(GPIO_FN_HSYNC,              HSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_HSPI_TX,            HSPI_TX_MARK),
-        PINMUX_GPIO(GPIO_FN_DB5,                DB5_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_RXD3,           ETH_RXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_DB4,                DB4_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_RXD2,           ETH_RXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_DB3,                DB3_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_RXD1,           ETH_RXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_DB2,                DB2_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_RXD0,           ETH_RXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_DB1,                DB1_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_RX_DV,          ETH_RX_DV_MARK),
-        PINMUX_GPIO(GPIO_FN_DB0,                DB0_MARK),
-        PINMUX_GPIO(GPIO_FN_ETH_RX_ER,          ETH_RX_ER_MARK),
-        PINMUX_GPIO(GPIO_FN_DCLKOUT,            DCLKOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_SCK,          SCIF1_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_RXD,          SCIF1_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF1_TXD,          SCIF1_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK1,              DACK1_MARK),
-        PINMUX_GPIO(GPIO_FN_BACK,               BACK_MARK),
-        PINMUX_GPIO(GPIO_FN_FALE,               FALE_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK0,              DACK0_MARK),
-        PINMUX_GPIO(GPIO_FN_FCLE,               FCLE_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1,              DREQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_BREQ,               BREQ_MARK),
-        PINMUX_GPIO(GPIO_FN_USB_OVC1,           USB_OVC1_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0,              DREQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_USB_OVC0,           USB_OVC0_MARK),
-        PINMUX_GPIO(GPIO_FN_USB_PENC1,          USB_PENC1_MARK),
-        PINMUX_GPIO(GPIO_FN_USB_PENC0,          USB_PENC0_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC1_SDOUT,         HAC1_SDOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI1_SDATA,         SSI1_SDATA_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF1CMD,           SDIF1CMD_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC1_SDIN,          HAC1_SDIN_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI1_SCK,           SSI1_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF1CD,            SDIF1CD_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC1_SYNC,          HAC1_SYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI1_WS,            SSI1_WS_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF1WP,            SDIF1WP_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC1_BITCLK,        HAC1_BITCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI1_CLK,           SSI1_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF1CLK,           SDIF1CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC0_SDOUT,         HAC0_SDOUT_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI0_SDATA,         SSI0_SDATA_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF1D3,            SDIF1D3_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC0_SDIN,          HAC0_SDIN_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI0_SCK,           SSI0_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF1D2,            SDIF1D2_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC0_SYNC,          HAC0_SYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI0_WS,            SSI0_WS_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF1D1,            SDIF1D1_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC0_BITCLK,        HAC0_BITCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI0_CLK,           SSI0_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF1D0,            SDIF1D0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_SCK,          SCIF3_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI2_SDATA,         SSI2_SDATA_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_RXD,          SCIF3_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_TCLK,               TCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI2_SCK,           SSI2_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF3_TXD,          SCIF3_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_HAC_RES,            HAC_RES_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI2_WS,            SSI2_WS_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK3,              DACK3_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF0CMD,           SDIF0CMD_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK2,              DACK2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF0CD,            SDIF0CD_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ3,              DREQ3_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF0WP,            SDIF0WP_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_CTS,          SCIF0_CTS_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ2,              DREQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF0CLK,           SDIF0CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_RTS,          SCIF0_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL7,               IRL7_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF0D3,            SDIF0D3_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_SCK,          SCIF0_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL6,               IRL6_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF0D2,            SDIF0D2_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_RXD,          SCIF0_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL5,               IRL5_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF0D1,            SDIF0D1_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF0_TXD,          SCIF0_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL4,               IRL4_MARK),
-        PINMUX_GPIO(GPIO_FN_SDIF0D0,            SDIF0D0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_SCK,          SCIF5_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_FRB,                FRB_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_RXD,          SCIF5_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_IOIS16,             IOIS16_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF5_TXD,          SCIF5_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2B,               CE2B_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK3,              DRAK3_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2A,               CE2A_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_SCK,          SCIF4_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK2,              DRAK2_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI3_WS,            SSI3_WS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_RXD,          SCIF4_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK1,              DRAK1_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI3_SDATA,         SSI3_SDATA_MARK),
-        PINMUX_GPIO(GPIO_FN_FSTATUS,            FSTATUS_MARK),
-        PINMUX_GPIO(GPIO_FN_SCIF4_TXD,          SCIF4_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK0,              DRAK0_MARK),
-        PINMUX_GPIO(GPIO_FN_SSI3_SCK,           SSI3_SCK_MARK),
-        PINMUX_GPIO(GPIO_FN_FSE,                FSE_MARK),
+        GPIO_FN(CDE),
+        GPIO_FN(ETH_MAGIC),
+        GPIO_FN(DISP),
+        GPIO_FN(ETH_LINK),
+        GPIO_FN(DR5),
+        GPIO_FN(ETH_TX_ER),
+        GPIO_FN(DR4),
+        GPIO_FN(ETH_TX_EN),
+        GPIO_FN(DR3),
+        GPIO_FN(ETH_TXD3),
+        GPIO_FN(DR2),
+        GPIO_FN(ETH_TXD2),
+        GPIO_FN(DR1),
+        GPIO_FN(ETH_TXD1),
+        GPIO_FN(DR0),
+        GPIO_FN(ETH_TXD0),
+        GPIO_FN(VSYNC),
+        GPIO_FN(HSPI_CLK),
+        GPIO_FN(ODDF),
+        GPIO_FN(HSPI_CS),
+        GPIO_FN(DG5),
+        GPIO_FN(ETH_MDIO),
+        GPIO_FN(DG4),
+        GPIO_FN(ETH_RX_CLK),
+        GPIO_FN(DG3),
+        GPIO_FN(ETH_MDC),
+        GPIO_FN(DG2),
+        GPIO_FN(ETH_COL),
+        GPIO_FN(DG1),
+        GPIO_FN(ETH_TX_CLK),
+        GPIO_FN(DG0),
+        GPIO_FN(ETH_CRS),
+        GPIO_FN(DCLKIN),
+        GPIO_FN(HSPI_RX),
+        GPIO_FN(HSYNC),
+        GPIO_FN(HSPI_TX),
+        GPIO_FN(DB5),
+        GPIO_FN(ETH_RXD3),
+        GPIO_FN(DB4),
+        GPIO_FN(ETH_RXD2),
+        GPIO_FN(DB3),
+        GPIO_FN(ETH_RXD1),
+        GPIO_FN(DB2),
+        GPIO_FN(ETH_RXD0),
+        GPIO_FN(DB1),
+        GPIO_FN(ETH_RX_DV),
+        GPIO_FN(DB0),
+        GPIO_FN(ETH_RX_ER),
+        GPIO_FN(DCLKOUT),
+        GPIO_FN(SCIF1_SCK),
+        GPIO_FN(SCIF1_RXD),
+        GPIO_FN(SCIF1_TXD),
+        GPIO_FN(DACK1),
+        GPIO_FN(BACK),
+        GPIO_FN(FALE),
+        GPIO_FN(DACK0),
+        GPIO_FN(FCLE),
+        GPIO_FN(DREQ1),
+        GPIO_FN(BREQ),
+        GPIO_FN(USB_OVC1),
+        GPIO_FN(DREQ0),
+        GPIO_FN(USB_OVC0),
+        GPIO_FN(USB_PENC1),
+        GPIO_FN(USB_PENC0),
+        GPIO_FN(HAC1_SDOUT),
+        GPIO_FN(SSI1_SDATA),
+        GPIO_FN(SDIF1CMD),
+        GPIO_FN(HAC1_SDIN),
+        GPIO_FN(SSI1_SCK),
+        GPIO_FN(SDIF1CD),
+        GPIO_FN(HAC1_SYNC),
+        GPIO_FN(SSI1_WS),
+        GPIO_FN(SDIF1WP),
+        GPIO_FN(HAC1_BITCLK),
+        GPIO_FN(SSI1_CLK),
+        GPIO_FN(SDIF1CLK),
+        GPIO_FN(HAC0_SDOUT),
+        GPIO_FN(SSI0_SDATA),
+        GPIO_FN(SDIF1D3),
+        GPIO_FN(HAC0_SDIN),
+        GPIO_FN(SSI0_SCK),
+        GPIO_FN(SDIF1D2),
+        GPIO_FN(HAC0_SYNC),
+        GPIO_FN(SSI0_WS),
+        GPIO_FN(SDIF1D1),
+        GPIO_FN(HAC0_BITCLK),
+        GPIO_FN(SSI0_CLK),
+        GPIO_FN(SDIF1D0),
+        GPIO_FN(SCIF3_SCK),
+        GPIO_FN(SSI2_SDATA),
+        GPIO_FN(SCIF3_RXD),
+        GPIO_FN(TCLK),
+        GPIO_FN(SSI2_SCK),
+        GPIO_FN(SCIF3_TXD),
+        GPIO_FN(HAC_RES),
+        GPIO_FN(SSI2_WS),
+        GPIO_FN(DACK3),
+        GPIO_FN(SDIF0CMD),
+        GPIO_FN(DACK2),
+        GPIO_FN(SDIF0CD),
+        GPIO_FN(DREQ3),
+        GPIO_FN(SDIF0WP),
+        GPIO_FN(SCIF0_CTS),
+        GPIO_FN(DREQ2),
+        GPIO_FN(SDIF0CLK),
+        GPIO_FN(SCIF0_RTS),
+        GPIO_FN(IRL7),
+        GPIO_FN(SDIF0D3),
+        GPIO_FN(SCIF0_SCK),
+        GPIO_FN(IRL6),
+        GPIO_FN(SDIF0D2),
+        GPIO_FN(SCIF0_RXD),
+        GPIO_FN(IRL5),
+        GPIO_FN(SDIF0D1),
+        GPIO_FN(SCIF0_TXD),
+        GPIO_FN(IRL4),
+        GPIO_FN(SDIF0D0),
+        GPIO_FN(SCIF5_SCK),
+        GPIO_FN(FRB),
+        GPIO_FN(SCIF5_RXD),
+        GPIO_FN(IOIS16),
+        GPIO_FN(SCIF5_TXD),
+        GPIO_FN(CE2B),
+        GPIO_FN(DRAK3),
+        GPIO_FN(CE2A),
+        GPIO_FN(SCIF4_SCK),
+        GPIO_FN(DRAK2),
+        GPIO_FN(SSI3_WS),
+        GPIO_FN(SCIF4_RXD),
+        GPIO_FN(DRAK1),
+        GPIO_FN(SSI3_SDATA),
+        GPIO_FN(FSTATUS),
+        GPIO_FN(SCIF4_TXD),
+        GPIO_FN(DRAK0),
+        GPIO_FN(SSI3_SCK),
+        GPIO_FN(FSE),
 };
 
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
                 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
                 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -775,7 +779,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
         {}
 };
 
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
                 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
                 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
@@ -815,20 +819,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info sh7786_pinmux_info = {
+const struct sh_pfc_soc_info sh7786_pinmux_info = {
         .name = "sh7786_pfc",
-        .reserved_id = PINMUX_RESERVED,
-        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
         .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
-        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PA7,
-        .last_gpio = GPIO_FN_IRL4,
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .func_gpios = pinmux_func_gpios,
+        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
 
-        .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index ccf6918b03c6..6594c8c48747 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -147,7 +147,7 @@ enum {
         PINMUX_MARK_END,
 };
 
-static pinmux_enum_t shx3_pinmux_data[] = {
+static const pinmux_enum_t shx3_pinmux_data[] = {
 
         /* PA GPIO */
         PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -306,7 +306,7 @@ static pinmux_enum_t shx3_pinmux_data[] = {
         PINMUX_DATA(IRQOUT_MARK,        PH0_FN),
 };
 
-static struct pinmux_gpio shx3_pinmux_gpios[] = {
+static struct sh_pfc_pin shx3_pinmux_pins[] = {
         /* PA */
         PINMUX_GPIO(GPIO_PA7, PA7_DATA),
         PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -384,73 +384,77 @@ static struct pinmux_gpio shx3_pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PH2, PH2_DATA),
         PINMUX_GPIO(GPIO_PH1, PH1_DATA),
         PINMUX_GPIO(GPIO_PH0, PH0_DATA),
+};
+
+#define PINMUX_FN_BASE  ARRAY_SIZE(shx3_pinmux_pins)
 
+static const struct pinmux_func shx3_pinmux_func_gpios[] = {
         /* FN */
-        PINMUX_GPIO(GPIO_FN_D31,        D31_MARK),
-        PINMUX_GPIO(GPIO_FN_D30,        D30_MARK),
-        PINMUX_GPIO(GPIO_FN_D29,        D29_MARK),
-        PINMUX_GPIO(GPIO_FN_D28,        D28_MARK),
-        PINMUX_GPIO(GPIO_FN_D27,        D27_MARK),
-        PINMUX_GPIO(GPIO_FN_D26,        D26_MARK),
-        PINMUX_GPIO(GPIO_FN_D25,        D25_MARK),
-        PINMUX_GPIO(GPIO_FN_D24,        D24_MARK),
-        PINMUX_GPIO(GPIO_FN_D23,        D23_MARK),
-        PINMUX_GPIO(GPIO_FN_D22,        D22_MARK),
-        PINMUX_GPIO(GPIO_FN_D21,        D21_MARK),
-        PINMUX_GPIO(GPIO_FN_D20,        D20_MARK),
-        PINMUX_GPIO(GPIO_FN_D19,        D19_MARK),
-        PINMUX_GPIO(GPIO_FN_D18,        D18_MARK),
-        PINMUX_GPIO(GPIO_FN_D17,        D17_MARK),
-        PINMUX_GPIO(GPIO_FN_D16,        D16_MARK),
-        PINMUX_GPIO(GPIO_FN_BACK,       BACK_MARK),
-        PINMUX_GPIO(GPIO_FN_BREQ,       BREQ_MARK),
-        PINMUX_GPIO(GPIO_FN_WE3,        WE3_MARK),
-        PINMUX_GPIO(GPIO_FN_WE2,        WE2_MARK),
-        PINMUX_GPIO(GPIO_FN_CS6,        CS6_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5,        CS5_MARK),
-        PINMUX_GPIO(GPIO_FN_CS4,        CS4_MARK),
-        PINMUX_GPIO(GPIO_FN_CLKOUTENB,  CLKOUTENB_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK3,      DACK3_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK2,      DACK2_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK1,      DACK1_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK0,      DACK0_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ3,      DREQ3_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ2,      DREQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1,      DREQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0,      DREQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ3,       IRQ3_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ2,       IRQ2_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ1,       IRQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ0,       IRQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK3,      DRAK3_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK2,      DRAK2_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK1,      DRAK1_MARK),
-        PINMUX_GPIO(GPIO_FN_DRAK0,      DRAK0_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK3,       SCK3_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK2,       SCK2_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK1,       SCK1_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK0,       SCK0_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL3,       IRL3_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL2,       IRL2_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL1,       IRL1_MARK),
-        PINMUX_GPIO(GPIO_FN_IRL0,       IRL0_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD3,       TXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD2,       TXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD1,       TXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD0,       TXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD3,       RXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD2,       RXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD1,       RXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD0,       RXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2B,       CE2B_MARK),
-        PINMUX_GPIO(GPIO_FN_CE2A,       CE2A_MARK),
-        PINMUX_GPIO(GPIO_FN_IOIS16,     IOIS16_MARK),
-        PINMUX_GPIO(GPIO_FN_STATUS1,    STATUS1_MARK),
-        PINMUX_GPIO(GPIO_FN_STATUS0,    STATUS0_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQOUT,     IRQOUT_MARK),
+        GPIO_FN(D31),
+        GPIO_FN(D30),
+        GPIO_FN(D29),
+        GPIO_FN(D28),
+        GPIO_FN(D27),
+        GPIO_FN(D26),
+        GPIO_FN(D25),
+        GPIO_FN(D24),
+        GPIO_FN(D23),
+        GPIO_FN(D22),
+        GPIO_FN(D21),
+        GPIO_FN(D20),
+        GPIO_FN(D19),
+        GPIO_FN(D18),
+        GPIO_FN(D17),
+        GPIO_FN(D16),
+        GPIO_FN(BACK),
+        GPIO_FN(BREQ),
+        GPIO_FN(WE3),
+        GPIO_FN(WE2),
+        GPIO_FN(CS6),
+        GPIO_FN(CS5),
+        GPIO_FN(CS4),
+        GPIO_FN(CLKOUTENB),
+        GPIO_FN(DACK3),
+        GPIO_FN(DACK2),
+        GPIO_FN(DACK1),
+        GPIO_FN(DACK0),
+        GPIO_FN(DREQ3),
+        GPIO_FN(DREQ2),
+        GPIO_FN(DREQ1),
+        GPIO_FN(DREQ0),
+        GPIO_FN(IRQ3),
+        GPIO_FN(IRQ2),
+        GPIO_FN(IRQ1),
+        GPIO_FN(IRQ0),
+        GPIO_FN(DRAK3),
+        GPIO_FN(DRAK2),
+        GPIO_FN(DRAK1),
+        GPIO_FN(DRAK0),
+        GPIO_FN(SCK3),
+        GPIO_FN(SCK2),
+        GPIO_FN(SCK1),
+        GPIO_FN(SCK0),
+        GPIO_FN(IRL3),
+        GPIO_FN(IRL2),
+        GPIO_FN(IRL1),
+        GPIO_FN(IRL0),
+        GPIO_FN(TXD3),
+        GPIO_FN(TXD2),
+        GPIO_FN(TXD1),
+        GPIO_FN(TXD0),
+        GPIO_FN(RXD3),
+        GPIO_FN(RXD2),
+        GPIO_FN(RXD1),
+        GPIO_FN(RXD0),
+        GPIO_FN(CE2B),
+        GPIO_FN(CE2A),
+        GPIO_FN(IOIS16),
+        GPIO_FN(STATUS1),
+        GPIO_FN(STATUS0),
+        GPIO_FN(IRQOUT),
 };
 
-static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
                 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
                 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -526,7 +530,7 @@ static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
         { },
 };
 
-static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
+static const struct pinmux_data_reg shx3_pinmux_data_regs[] = {
         { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
                 0, 0, 0, 0, 0, 0, 0, 0,
                 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
@@ -562,19 +566,17 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
         { },
 };
 
-struct sh_pfc_soc_info shx3_pinmux_info = {
+const struct sh_pfc_soc_info shx3_pinmux_info = {
         .name           = "shx3_pfc",
-        .reserved_id    = PINMUX_RESERVED,
-        .data           = { PINMUX_DATA_BEGIN,     PINMUX_DATA_END },
         .input          = { PINMUX_INPUT_BEGIN,    PINMUX_INPUT_END },
         .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
                             PINMUX_INPUT_PULLUP_END },
         .output         = { PINMUX_OUTPUT_BEGIN,   PINMUX_OUTPUT_END },
-        .mark           = { PINMUX_MARK_BEGIN,     PINMUX_MARK_END },
         .function       = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
-        .first_gpio     = GPIO_PA7,
-        .last_gpio      = GPIO_FN_STATUS0,
-        .gpios          = shx3_pinmux_gpios,
+        .pins           = shx3_pinmux_pins,
+        .nr_pins        = ARRAY_SIZE(shx3_pinmux_pins),
+        .func_gpios     = shx3_pinmux_func_gpios,
+        .nr_func_gpios  = ARRAY_SIZE(shx3_pinmux_func_gpios),
         .gpio_data      = shx3_pinmux_data,
         .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
         .cfg_regs       = shx3_pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 11e0e1374d65..aef268bc17ba 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -9,7 +9,6 @@
  */
 
 #define DRV_NAME "sh-pfc"
-#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
 
 #include <linux/device.h>
 #include <linux/err.h>
@@ -24,25 +23,28 @@
 #include <linux/spinlock.h>
 
 #include "core.h"
+#include "../core.h"
+#include "../pinconf.h"
+
+struct sh_pfc_pin_config {
+        u32 type;
+};
 
 struct sh_pfc_pinctrl {
         struct pinctrl_dev *pctl;
-        struct sh_pfc *pfc;
-
-        struct pinmux_gpio **functions;
-        unsigned int nr_functions;
+        struct pinctrl_desc pctl_desc;
 
-        struct pinctrl_pin_desc *pads;
-        unsigned int nr_pads;
+        struct sh_pfc *pfc;
 
-        spinlock_t lock;
+        struct pinctrl_pin_desc *pins;
+        struct sh_pfc_pin_config *configs;
 };
 
 static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
 {
         struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        return pmx->nr_pads;
+        return pmx->pfc->info->nr_groups;
 }
 
 static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
@@ -50,16 +52,16 @@ static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
 {
         struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        return pmx->pads[selector].name;
+        return pmx->pfc->info->groups[selector].name;
 }
 
-static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
+static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
                                  const unsigned **pins, unsigned *num_pins)
 {
         struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        *pins = &pmx->pads[group].number;
-        *num_pins = 1;
+        *pins = pmx->pfc->info->groups[selector].pins;
+        *num_pins = pmx->pfc->info->groups[selector].nr_pins;
 
         return 0;
 }
@@ -70,7 +72,7 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
         seq_printf(s, "%s", DRV_NAME);
 }
 
-static struct pinctrl_ops sh_pfc_pinctrl_ops = {
+static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
         .get_groups_count       = sh_pfc_get_groups_count,
         .get_group_name         = sh_pfc_get_group_name,
         .get_group_pins         = sh_pfc_get_group_pins,
@@ -81,7 +83,7 @@ static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
 {
         struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        return pmx->nr_functions;
+        return pmx->pfc->info->nr_functions;
 }
 
 static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
@@ -89,136 +91,102 @@ static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
 {
         struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        return pmx->functions[selector]->name;
+        return pmx->pfc->info->functions[selector].name;
 }
 
-static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
+static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
+                                      unsigned selector,
                                       const char * const **groups,
                                       unsigned * const num_groups)
 {
         struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-        *groups = &pmx->functions[func]->name;
-        *num_groups = 1;
+        *groups = pmx->pfc->info->functions[selector].groups;
+        *num_groups = pmx->pfc->info->functions[selector].nr_groups;
 
         return 0;
 }
 
-static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
+static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
                               unsigned group)
 {
-        return 0;
-}
+        struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+        struct sh_pfc *pfc = pmx->pfc;
+        const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
+        unsigned long flags;
+        unsigned int i;
+        int ret = 0;
 
-static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
-                                unsigned group)
-{
-}
+        spin_lock_irqsave(&pfc->lock, flags);
 
-static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
-{
-        if (sh_pfc_config_gpio(pfc, offset,
-                               PINMUX_TYPE_FUNCTION,
-                               GPIO_CFG_DRYRUN) != 0)
-                return -EINVAL;
+        for (i = 0; i < grp->nr_pins; ++i) {
+                int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+                struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 
-        if (sh_pfc_config_gpio(pfc, offset,
-                               PINMUX_TYPE_FUNCTION,
-                               GPIO_CFG_REQ) != 0)
-                return -EINVAL;
+                if (cfg->type != PINMUX_TYPE_NONE) {
+                        ret = -EBUSY;
+                        goto done;
+                }
+        }
 
-        return 0;
+        for (i = 0; i < grp->nr_pins; ++i) {
+                ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
+                if (ret < 0)
+                        break;
+        }
+
+done:
+        spin_unlock_irqrestore(&pfc->lock, flags);
+        return ret;
 }
 
-static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
-                               int new_type)
+static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
+                                unsigned group)
 {
+        struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+        struct sh_pfc *pfc = pmx->pfc;
+        const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
         unsigned long flags;
-        int pinmux_type;
-        int ret = -EINVAL;
+        unsigned int i;
 
         spin_lock_irqsave(&pfc->lock, flags);
 
-        pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
+        for (i = 0; i < grp->nr_pins; ++i) {
+                int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
+                struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 
-        /*
-         * See if the present config needs to first be de-configured.
-         */
-        switch (pinmux_type) {
-        case PINMUX_TYPE_GPIO:
-                break;
-        case PINMUX_TYPE_OUTPUT:
-        case PINMUX_TYPE_INPUT:
-        case PINMUX_TYPE_INPUT_PULLUP:
-        case PINMUX_TYPE_INPUT_PULLDOWN:
-                sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
-                break;
-        default:
-                goto err;
+                cfg->type = PINMUX_TYPE_NONE;
         }
 
-        /*
-         * Dry run
-         */
-        if (sh_pfc_config_gpio(pfc, offset, new_type,
-                               GPIO_CFG_DRYRUN) != 0)
-                goto err;
-
-        /*
-         * Request
-         */
-        if (sh_pfc_config_gpio(pfc, offset, new_type,
-                               GPIO_CFG_REQ) != 0)
-                goto err;
-
-        pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
-        pfc->info->gpios[offset].flags |= new_type;
-
-        ret = 0;
-
-err:
         spin_unlock_irqrestore(&pfc->lock, flags);
-
-        return ret;
 }
 
-
 static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
                                       struct pinctrl_gpio_range *range,
                                       unsigned offset)
 {
         struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
         struct sh_pfc *pfc = pmx->pfc;
+        int idx = sh_pfc_get_pin_index(pfc, offset);
+        struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
         unsigned long flags;
-        int ret, pinmux_type;
+        int ret;
 
         spin_lock_irqsave(&pfc->lock, flags);
 
-        pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
-
-        switch (pinmux_type) {
-        case PINMUX_TYPE_FUNCTION:
-                pr_notice_once("Use of GPIO API for function requests is "
-                               "deprecated, convert to pinctrl\n");
-                /* handle for now */
-                ret = sh_pfc_config_function(pfc, offset);
-                if (unlikely(ret < 0))
-                        goto err;
-
-                break;
-        case PINMUX_TYPE_GPIO:
-        case PINMUX_TYPE_INPUT:
-        case PINMUX_TYPE_OUTPUT:
-                break;
-        default:
-                pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
-                ret = -ENOTSUPP;
-                goto err;
+        if (cfg->type != PINMUX_TYPE_NONE) {
+                dev_err(pfc->dev,
+                        "Pin %u is busy, can't configure it as GPIO.\n",
+                        offset);
+                ret = -EBUSY;
+                goto done;
         }
 
+        cfg->type = PINMUX_TYPE_GPIO;
+
         ret = 0;
 
-err:
+done:
         spin_unlock_irqrestore(&pfc->lock, flags);
 
         return ret;
@@ -230,15 +198,12 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
 {
         struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
         struct sh_pfc *pfc = pmx->pfc;
+        int idx = sh_pfc_get_pin_index(pfc, offset);
+        struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
         unsigned long flags;
-        int pinmux_type;
 
         spin_lock_irqsave(&pfc->lock, flags);
-
-        pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
-
-        sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
-
+        cfg->type = PINMUX_TYPE_NONE;
         spin_unlock_irqrestore(&pfc->lock, flags);
 }
 
@@ -247,207 +212,242 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
                                      unsigned offset, bool input)
 {
         struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-        int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
+        struct sh_pfc *pfc = pmx->pfc;
+        int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
+        int idx = sh_pfc_get_pin_index(pfc, offset);
+        const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+        struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
+        unsigned long flags;
+        unsigned int dir;
+        int ret;
+
+        /* Check if the requested direction is supported by the pin. Not all SoC
+         * provide pin config data, so perform the check conditionally.
+         */
+        if (pin->configs) {
+                dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
+                if (!(pin->configs & dir))
+                        return -EINVAL;
+        }
+
+        spin_lock_irqsave(&pfc->lock, flags);
+
+        ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
+        if (ret < 0)
+                goto done;
+
+        cfg->type = new_type;
 
-        return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
+done:
+        spin_unlock_irqrestore(&pfc->lock, flags);
+        return ret;
 }
 
-static struct pinmux_ops sh_pfc_pinmux_ops = {
+static const struct pinmux_ops sh_pfc_pinmux_ops = {
         .get_functions_count    = sh_pfc_get_functions_count,
         .get_function_name      = sh_pfc_get_function_name,
         .get_function_groups    = sh_pfc_get_function_groups,
-        .enable                 = sh_pfc_noop_enable,
-        .disable                = sh_pfc_noop_disable,
+        .enable                 = sh_pfc_func_enable,
+        .disable                = sh_pfc_func_disable,
         .gpio_request_enable    = sh_pfc_gpio_request_enable,
         .gpio_disable_free      = sh_pfc_gpio_disable_free,
         .gpio_set_direction     = sh_pfc_gpio_set_direction,
 };
 
-static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
-                              unsigned long *config)
+/* Check whether the requested parameter is supported for a pin. */
+static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
+                                    enum pin_config_param param)
 {
-        struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-        struct sh_pfc *pfc = pmx->pfc;
+        int idx = sh_pfc_get_pin_index(pfc, _pin);
+        const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 
-        *config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE;
+        switch (param) {
+        case PIN_CONFIG_BIAS_DISABLE:
+                return true;
 
-        return 0;
-}
+        case PIN_CONFIG_BIAS_PULL_UP:
+                return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 
-static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
-                              unsigned long config)
-{
-        struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-        /* Validate the new type */
-        if (config >= PINMUX_FLAG_TYPE)
-                return -EINVAL;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 
-        return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
+        default:
+                return false;
+        }
 }
 
-static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
-                                    struct seq_file *s, unsigned pin)
+static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
+                              unsigned long *config)
 {
-        const char *pinmux_type_str[] = {
-                [PINMUX_TYPE_NONE]              = "none",
-                [PINMUX_TYPE_FUNCTION]          = "function",
-                [PINMUX_TYPE_GPIO]              = "gpio",
-                [PINMUX_TYPE_OUTPUT]            = "output",
-                [PINMUX_TYPE_INPUT]             = "input",
-                [PINMUX_TYPE_INPUT_PULLUP]      = "input bias pull up",
-                [PINMUX_TYPE_INPUT_PULLDOWN]    = "input bias pull down",
-        };
-        unsigned long config;
-        int rc;
-
-        rc = sh_pfc_pinconf_get(pctldev, pin, &config);
-        if (unlikely(rc != 0))
-                return;
-
-        seq_printf(s, " %s", pinmux_type_str[config]);
-}
+        struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+        struct sh_pfc *pfc = pmx->pfc;
+        enum pin_config_param param = pinconf_to_config_param(*config);
+        unsigned long flags;
+        unsigned int bias;
 
-static struct pinconf_ops sh_pfc_pinconf_ops = {
-        .pin_config_get         = sh_pfc_pinconf_get,
-        .pin_config_set         = sh_pfc_pinconf_set,
-        .pin_config_dbg_show    = sh_pfc_pinconf_dbg_show,
-};
+        if (!sh_pfc_pinconf_validate(pfc, _pin, param))
+                return -ENOTSUPP;
 
-static struct pinctrl_gpio_range sh_pfc_gpio_range = {
-        .name           = DRV_NAME,
-        .id             = 0,
-};
+        switch (param) {
+        case PIN_CONFIG_BIAS_DISABLE:
+        case PIN_CONFIG_BIAS_PULL_UP:
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                if (!pfc->info->ops || !pfc->info->ops->get_bias)
+                        return -ENOTSUPP;
 
-static struct pinctrl_desc sh_pfc_pinctrl_desc = {
-        .name           = DRV_NAME,
-        .owner          = THIS_MODULE,
-        .pctlops        = &sh_pfc_pinctrl_ops,
-        .pmxops         = &sh_pfc_pinmux_ops,
-        .confops        = &sh_pfc_pinconf_ops,
-};
+                spin_lock_irqsave(&pfc->lock, flags);
+                bias = pfc->info->ops->get_bias(pfc, _pin);
+                spin_unlock_irqrestore(&pfc->lock, flags);
 
-static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx,
-                                struct pinmux_gpio *gpio, unsigned offset)
-{
-        struct pinmux_data_reg *dummy;
-        unsigned long flags;
-        int bit;
-
-        gpio->flags &= ~PINMUX_FLAG_TYPE;
+                if (bias != param)
+                        return -EINVAL;
 
-        if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
-                gpio->flags |= PINMUX_TYPE_GPIO;
-        else {
-                gpio->flags |= PINMUX_TYPE_FUNCTION;
+                *config = 0;
+                break;
 
-                spin_lock_irqsave(&pmx->lock, flags);
-                pmx->nr_functions++;
-                spin_unlock_irqrestore(&pmx->lock, flags);
+        default:
+                return -ENOTSUPP;
         }
+
+        return 0;
 }
 
-/* pinmux ranges -> pinctrl pin descs */
-static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
+static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
+                              unsigned long config)
 {
+        struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+        struct sh_pfc *pfc = pmx->pfc;
+        enum pin_config_param param = pinconf_to_config_param(config);
         unsigned long flags;
-        int i;
 
-        pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1;
+        if (!sh_pfc_pinconf_validate(pfc, _pin, param))
+                return -ENOTSUPP;
 
-        pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads,
-                                 GFP_KERNEL);
-        if (unlikely(!pmx->pads)) {
-                pmx->nr_pads = 0;
-                return -ENOMEM;
-        }
+        switch (param) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+        case PIN_CONFIG_BIAS_DISABLE:
+                if (!pfc->info->ops || !pfc->info->ops->set_bias)
+                        return -ENOTSUPP;
 
-        spin_lock_irqsave(&pfc->lock, flags);
+                spin_lock_irqsave(&pfc->lock, flags);
+                pfc->info->ops->set_bias(pfc, _pin, param);
+                spin_unlock_irqrestore(&pfc->lock, flags);
 
-        /*
-         * We don't necessarily have a 1:1 mapping between pin and linux
-         * GPIO number, as the latter maps to the associated enum_id.
-         * Care needs to be taken to translate back to pin space when
-         * dealing with any pin configurations.
-         */
-        for (i = 0; i < pmx->nr_pads; i++) {
-                struct pinctrl_pin_desc *pin = pmx->pads + i;
-                struct pinmux_gpio *gpio = pfc->info->gpios + i;
+                break;
 
-                pin->number = pfc->info->first_gpio + i;
-                pin->name = gpio->name;
+        default:
+                return -ENOTSUPP;
+        }
 
-                /* XXX */
-                if (unlikely(!gpio->enum_id))
-                        continue;
+        return 0;
+}
 
-                sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
-        }
+static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
+                                    unsigned long config)
+{
+        struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
+        const unsigned int *pins;
+        unsigned int num_pins;
+        unsigned int i;
 
-        spin_unlock_irqrestore(&pfc->lock, flags);
+        pins = pmx->pfc->info->groups[group].pins;
+        num_pins = pmx->pfc->info->groups[group].nr_pins;
 
-        sh_pfc_pinctrl_desc.pins = pmx->pads;
-        sh_pfc_pinctrl_desc.npins = pmx->nr_pads;
+        for (i = 0; i < num_pins; ++i)
+                sh_pfc_pinconf_set(pctldev, pins[i], config);
 
         return 0;
 }
 
-static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
+static const struct pinconf_ops sh_pfc_pinconf_ops = {
+        .is_generic                     = true,
+        .pin_config_get                 = sh_pfc_pinconf_get,
+        .pin_config_set                 = sh_pfc_pinconf_set,
+        .pin_config_group_set           = sh_pfc_pinconf_group_set,
+        .pin_config_config_dbg_show     = pinconf_generic_dump_config,
+};
+
+/* PFC ranges -> pinctrl pin descs */
+static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 {
-        unsigned long flags;
-        int i, fn;
+        const struct pinmux_range *ranges;
+        struct pinmux_range def_range;
+        unsigned int nr_ranges;
+        unsigned int nr_pins;
+        unsigned int i;
+
+        if (pfc->info->ranges == NULL) {
+                def_range.begin = 0;
+                def_range.end = pfc->info->nr_pins - 1;
+                ranges = &def_range;
+                nr_ranges = 1;
+        } else {
+                ranges = pfc->info->ranges;
+                nr_ranges = pfc->info->nr_ranges;
+        }
 
-        pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions *
-                                      sizeof(*pmx->functions), GFP_KERNEL);
-        if (unlikely(!pmx->functions))
+        pmx->pins = devm_kzalloc(pfc->dev,
+                                 sizeof(*pmx->pins) * pfc->info->nr_pins,
+                                 GFP_KERNEL);
+        if (unlikely(!pmx->pins))
                 return -ENOMEM;
 
-        spin_lock_irqsave(&pmx->lock, flags);
-
-        for (i = fn = 0; i < pmx->nr_pads; i++) {
-                struct pinmux_gpio *gpio = pfc->info->gpios + i;
+        pmx->configs = devm_kzalloc(pfc->dev,
+                                    sizeof(*pmx->configs) * pfc->info->nr_pins,
+                                    GFP_KERNEL);
+        if (unlikely(!pmx->configs))
+                return -ENOMEM;
 
-                if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
-                        pmx->functions[fn++] = gpio;
+        for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
+                const struct pinmux_range *range = &ranges[i];
+                unsigned int number;
+
+                for (number = range->begin; number <= range->end;
+                     number++, nr_pins++) {
+                        struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
+                        struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
+                        const struct sh_pfc_pin *info =
+                                &pfc->info->pins[nr_pins];
+
+                        pin->number = number;
+                        pin->name = info->name;
+                        cfg->type = PINMUX_TYPE_NONE;
+                }
         }
 
-        spin_unlock_irqrestore(&pmx->lock, flags);
+        pfc->nr_pins = ranges[nr_ranges-1].end + 1;
 
-        return 0;
+        return nr_ranges;
 }
 
 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
 {
         struct sh_pfc_pinctrl *pmx;
-        int ret;
+        int nr_ranges;
 
         pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
         if (unlikely(!pmx))
                 return -ENOMEM;
 
-        spin_lock_init(&pmx->lock);
-
         pmx->pfc = pfc;
         pfc->pinctrl = pmx;
 
-        ret = sh_pfc_map_gpios(pfc, pmx);
-        if (unlikely(ret != 0))
-                return ret;
+        nr_ranges = sh_pfc_map_pins(pfc, pmx);
+        if (unlikely(nr_ranges < 0))
+                return nr_ranges;
 
-        ret = sh_pfc_map_functions(pfc, pmx);
-        if (unlikely(ret != 0))
-                return ret;
+        pmx->pctl_desc.name = DRV_NAME;
+        pmx->pctl_desc.owner = THIS_MODULE;
+        pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
+        pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
+        pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
+        pmx->pctl_desc.pins = pmx->pins;
+        pmx->pctl_desc.npins = pfc->info->nr_pins;
 
-        pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx);
-        if (IS_ERR(pmx->pctl))
-                return PTR_ERR(pmx->pctl);
-
-        sh_pfc_gpio_range.npins = pfc->info->last_gpio
-                                - pfc->info->first_gpio + 1;
-        sh_pfc_gpio_range.base = pfc->info->first_gpio;
-        sh_pfc_gpio_range.pin_base = pfc->info->first_gpio;
-
-        pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range);
+        pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
+        if (pmx->pctl == NULL)
+                return -EINVAL;
 
         return 0;
 }
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 13049c4c8d30..3b785fc428d5 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -15,7 +15,8 @@
 #include <asm-generic/gpio.h>
 
 typedef unsigned short pinmux_enum_t;
-typedef unsigned short pinmux_flag_t;
+
+#define SH_PFC_MARK_INVALID     ((pinmux_enum_t)-1)
 
 enum {
         PINMUX_TYPE_NONE,
@@ -30,44 +31,81 @@ enum {
         PINMUX_FLAG_TYPE,       /* must be last */
 };
 
-#define PINMUX_FLAG_DBIT_SHIFT      5
-#define PINMUX_FLAG_DBIT            (0x1f << PINMUX_FLAG_DBIT_SHIFT)
-#define PINMUX_FLAG_DREG_SHIFT      10
-#define PINMUX_FLAG_DREG            (0x3f << PINMUX_FLAG_DREG_SHIFT)
+#define SH_PFC_PIN_CFG_INPUT            (1 << 0)
+#define SH_PFC_PIN_CFG_OUTPUT           (1 << 1)
+#define SH_PFC_PIN_CFG_PULL_UP          (1 << 2)
+#define SH_PFC_PIN_CFG_PULL_DOWN        (1 << 3)
 
-struct pinmux_gpio {
-        pinmux_enum_t enum_id;
-        pinmux_flag_t flags;
+struct sh_pfc_pin {
+        const pinmux_enum_t enum_id;
         const char *name;
+        unsigned int configs;
 };
 
-#define PINMUX_GPIO(gpio, data_or_mark) \
-        [gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE }
+#define SH_PFC_PIN_GROUP(n)                             \
+        {                                               \
+                .name = #n,                             \
+                .pins = n##_pins,                       \
+                .mux = n##_mux,                         \
+                .nr_pins = ARRAY_SIZE(n##_pins),        \
+        }
+
+struct sh_pfc_pin_group {
+        const char *name;
+        const unsigned int *pins;
+        const unsigned int *mux;
+        unsigned int nr_pins;
+};
+
+#define SH_PFC_FUNCTION(n)                              \
+        {                                               \
+                .name = #n,                             \
+                .groups = n##_groups,                   \
+                .nr_groups = ARRAY_SIZE(n##_groups),    \
+        }
+
+struct sh_pfc_function {
+        const char *name;
+        const char * const *groups;
+        unsigned int nr_groups;
+};
+
+struct pinmux_func {
+        const pinmux_enum_t enum_id;
+        const char *name;
+};
+
+#define PINMUX_GPIO(gpio, data_or_mark)                 \
+        [gpio] = {                                      \
+                .name = __stringify(gpio),              \
+                .enum_id = data_or_mark,                \
+        }
+#define PINMUX_GPIO_FN(gpio, base, data_or_mark)        \
+        [gpio - (base)] = {                             \
+                .name = __stringify(gpio),              \
+                .enum_id = data_or_mark,                \
+        }
 
 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
 
 struct pinmux_cfg_reg {
         unsigned long reg, reg_width, field_width;
-        unsigned long *cnt;
-        pinmux_enum_t *enum_ids;
-        unsigned long *var_field_width;
+        const pinmux_enum_t *enum_ids;
+        const unsigned long *var_field_width;
 };
 
 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
         .reg = r, .reg_width = r_width, .field_width = f_width,         \
-        .cnt = (unsigned long [r_width / f_width]) {}, \
         .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
 
 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
         .reg = r, .reg_width = r_width, \
-        .cnt = (unsigned long [r_width]) {}, \
         .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
         .enum_ids = (pinmux_enum_t [])
 
 struct pinmux_data_reg {
-        unsigned long reg, reg_width, reg_shadow;
-        pinmux_enum_t *enum_ids;
-        void __iomem *mapped_reg;
+        unsigned long reg, reg_width;
+        const pinmux_enum_t *enum_ids;
 };
 
 #define PINMUX_DATA_REG(name, r, r_width) \
@@ -76,11 +114,11 @@ struct pinmux_data_reg {
 
 struct pinmux_irq {
         int irq;
-        pinmux_enum_t *enum_ids;
+        unsigned short *gpios;
 };
 
 #define PINMUX_IRQ(irq_nr, ids...)                         \
-        { .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } }    \
+        { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } }      \
 
 struct pinmux_range {
         pinmux_enum_t begin;
@@ -88,33 +126,49 @@ struct pinmux_range {
         pinmux_enum_t force;
 };
 
+struct sh_pfc;
+
+struct sh_pfc_soc_operations {
+        unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
+        void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
+                         unsigned int bias);
+};
+
 struct sh_pfc_soc_info {
-        char *name;
-        pinmux_enum_t reserved_id;
-        struct pinmux_range data;
+        const char *name;
+        const struct sh_pfc_soc_operations *ops;
+
         struct pinmux_range input;
         struct pinmux_range input_pd;
         struct pinmux_range input_pu;
         struct pinmux_range output;
-        struct pinmux_range mark;
         struct pinmux_range function;
 
-        unsigned first_gpio, last_gpio;
+        const struct sh_pfc_pin *pins;
+        unsigned int nr_pins;
+        const struct pinmux_range *ranges;
+        unsigned int nr_ranges;
+        const struct sh_pfc_pin_group *groups;
+        unsigned int nr_groups;
+        const struct sh_pfc_function *functions;
+        unsigned int nr_functions;
+
+        const struct pinmux_func *func_gpios;
+        unsigned int nr_func_gpios;
 
-        struct pinmux_gpio *gpios;
-        struct pinmux_cfg_reg *cfg_regs;
-        struct pinmux_data_reg *data_regs;
+        const struct pinmux_cfg_reg *cfg_regs;
+        const struct pinmux_data_reg *data_regs;
 
-        pinmux_enum_t *gpio_data;
+        const pinmux_enum_t *gpio_data;
         unsigned int gpio_data_size;
 
-        struct pinmux_irq *gpio_irq;
+        const struct pinmux_irq *gpio_irq;
         unsigned int gpio_irq_size;
 
         unsigned long unlock_reg;
 };
 
-enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
+enum { GPIO_CFG_REQ, GPIO_CFG_FREE };
 
 /* helper macro for port */
 #define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
@@ -126,6 +180,23 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
         PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),       \
         PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
 
+#define PORT_10_REV(fn, pfx, sfx)       \
+        PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),       \
+        PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),       \
+        PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),       \
+        PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),       \
+        PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+
+#define PORT_32(fn, pfx, sfx)                                   \
+        PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),        \
+        PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),     \
+        PORT_1(fn, pfx##31, sfx)
+
+#define PORT_32_REV(fn, pfx, sfx)                                       \
+        PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),             \
+        PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),     \
+        PORT_10_REV(fn, pfx, sfx)
+
 #define PORT_90(fn, pfx, sfx) \
         PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx),     \
         PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx),     \
@@ -137,7 +208,7 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
 #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
 #define PORT_ALL(str)   CPU_ALL_PORT(_PORT_ALL, PORT, str)
 #define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
-#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
 
 /* helper macro for pinmux_enum_t */
 #define PORT_DATA_I(nr) \
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
index 6a7dae70db08..116da0412c4b 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.c
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -198,7 +198,7 @@ static void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
         kfree(map);
 }
 
-static struct pinctrl_ops spear_pinctrl_ops = {
+static const struct pinctrl_ops spear_pinctrl_ops = {
         .get_groups_count = spear_pinctrl_get_groups_cnt,
         .get_group_name = spear_pinctrl_get_group_name,
         .get_group_pins = spear_pinctrl_get_group_pins,
@@ -340,7 +340,7 @@ static void gpio_disable_free(struct pinctrl_dev *pctldev,
         gpio_request_endisable(pctldev, range, offset, false);
 }
 
-static struct pinmux_ops spear_pinmux_ops = {
+static const struct pinmux_ops spear_pinmux_ops = {
         .get_functions_count = spear_pinctrl_get_funcs_count,
         .get_function_name = spear_pinctrl_get_func_name,
         .get_function_groups = spear_pinctrl_get_func_groups,
diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index 0a9f27e094ea..434ebc3a99dc 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -44,7 +44,6 @@ static DECLARE_COMPLETION(at91_rtc_updated);
 static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
 static void __iomem *at91_rtc_regs;
 static int irq;
-static u32 at91_rtc_imr;
 
 /*
  * Decode time/date into rtc_time structure
@@ -109,11 +108,9 @@ static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
         cr = at91_rtc_read(AT91_RTC_CR);
         at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
 
-        at91_rtc_imr |= AT91_RTC_ACKUPD;
         at91_rtc_write(AT91_RTC_IER, AT91_RTC_ACKUPD);
         wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
         at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD);
-        at91_rtc_imr &= ~AT91_RTC_ACKUPD;
 
         at91_rtc_write(AT91_RTC_TIMR,
                           bin2bcd(tm->tm_sec) << 0
@@ -145,7 +142,7 @@ static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
         tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
         tm->tm_year = at91_alarm_year - 1900;
 
-        alrm->enabled = (at91_rtc_imr & AT91_RTC_ALARM)
+        alrm->enabled = (at91_rtc_read(AT91_RTC_IMR) & AT91_RTC_ALARM)
                         ? 1 : 0;
 
         dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__,
@@ -171,7 +168,6 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
         tm.tm_sec = alrm->time.tm_sec;
 
         at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
-        at91_rtc_imr &= ~AT91_RTC_ALARM;
         at91_rtc_write(AT91_RTC_TIMALR,
                   bin2bcd(tm.tm_sec) << 0
                 | bin2bcd(tm.tm_min) << 8
@@ -184,7 +180,6 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 
         if (alrm->enabled) {
                 at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-                at91_rtc_imr |= AT91_RTC_ALARM;
                 at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
         }
 
@@ -201,12 +196,9 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 
         if (enabled) {
                 at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-                at91_rtc_imr |= AT91_RTC_ALARM;
                 at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
-        } else {
+        } else
                 at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
-                at91_rtc_imr &= ~AT91_RTC_ALARM;
-        }
 
         return 0;
 }
@@ -215,10 +207,12 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  */
 static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
 {
+        unsigned long imr = at91_rtc_read(AT91_RTC_IMR);
+
         seq_printf(seq, "update_IRQ\t: %s\n",
-                        (at91_rtc_imr & AT91_RTC_ACKUPD) ? "yes" : "no");
+                        (imr & AT91_RTC_ACKUPD) ? "yes" : "no");
         seq_printf(seq, "periodic_IRQ\t: %s\n",
-                        (at91_rtc_imr & AT91_RTC_SECEV) ? "yes" : "no");
+                        (imr & AT91_RTC_SECEV) ? "yes" : "no");
 
         return 0;
 }
@@ -233,7 +227,7 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
         unsigned int rtsr;
         unsigned long events = 0;
 
-        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_imr;
+        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read(AT91_RTC_IMR);
         if (rtsr) {             /* this interrupt is shared!  Is it ours? */
                 if (rtsr & AT91_RTC_ALARM)
                         events |= (RTC_AF | RTC_IRQF);
@@ -297,7 +291,6 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
         at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
                                         AT91_RTC_SECEV | AT91_RTC_TIMEV |
                                         AT91_RTC_CALEV);
-        at91_rtc_imr = 0;
 
         ret = request_irq(irq, at91_rtc_interrupt,
                                 IRQF_SHARED,
@@ -336,7 +329,6 @@ static int __exit at91_rtc_remove(struct platform_device *pdev)
         at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
                                         AT91_RTC_SECEV | AT91_RTC_TIMEV |
                                         AT91_RTC_CALEV);
-        at91_rtc_imr = 0;
         free_irq(irq, pdev);
 
         rtc_device_unregister(rtc);
@@ -349,35 +341,31 @@ static int __exit at91_rtc_remove(struct platform_device *pdev)
 
 /* AT91RM9200 RTC Power management control */
 
-static u32 at91_rtc_bkpimr;
-
+static u32 at91_rtc_imr;
 
 static int at91_rtc_suspend(struct device *dev)
 {
         /* this IRQ is shared with DBGU and other hardware which isn't
          * necessarily doing PM like we are...
          */
-        at91_rtc_bkpimr = at91_rtc_imr & (AT91_RTC_ALARM|AT91_RTC_SECEV);
-        if (at91_rtc_bkpimr) {
-                if (device_may_wakeup(dev)) {
+        at91_rtc_imr = at91_rtc_read(AT91_RTC_IMR)
+                        & (AT91_RTC_ALARM|AT91_RTC_SECEV);
+        if (at91_rtc_imr) {
+                if (device_may_wakeup(dev))
                         enable_irq_wake(irq);
-                } else {
-                        at91_rtc_write(AT91_RTC_IDR, at91_rtc_bkpimr);
-                        at91_rtc_imr &= ~at91_rtc_bkpimr;
-                }
-}
+                else
+                        at91_rtc_write(AT91_RTC_IDR, at91_rtc_imr);
+        }
         return 0;
 }
 
 static int at91_rtc_resume(struct device *dev)
 {
-        if (at91_rtc_bkpimr) {
-                if (device_may_wakeup(dev)) {
+        if (at91_rtc_imr) {
+                if (device_may_wakeup(dev))
                         disable_irq_wake(irq);
-                } else {
-                        at91_rtc_imr |= at91_rtc_bkpimr;
-                        at91_rtc_write(AT91_RTC_IER, at91_rtc_bkpimr);
-                }
+                else
+                        at91_rtc_write(AT91_RTC_IER, at91_rtc_imr);
         }
         return 0;
 }
diff --git a/drivers/rtc/rtc-at91rm9200.h b/drivers/rtc/rtc-at91rm9200.h
index 5f940b6844cb..da1945e5f714 100644
--- a/drivers/rtc/rtc-at91rm9200.h
+++ b/drivers/rtc/rtc-at91rm9200.h
@@ -64,6 +64,7 @@
 #define AT91_RTC_SCCR           0x1c                    /* Status Clear Command Register */
 #define AT91_RTC_IER            0x20                    /* Interrupt Enable Register */
 #define AT91_RTC_IDR            0x24                    /* Interrupt Disable Register */
+#define AT91_RTC_IMR            0x28                    /* Interrupt Mask Register */
 
 #define AT91_RTC_VER            0x2c                    /* Valid Entry Register */
 #define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
diff --git a/drivers/s390/block/scm_blk.c b/drivers/s390/block/scm_blk.c
index 5ac9c935c151..e9b9c8392832 100644
--- a/drivers/s390/block/scm_blk.c
+++ b/drivers/s390/block/scm_blk.c
@@ -307,7 +307,7 @@ static void scm_blk_handle_error(struct scm_request *scmrq)
         case EQC_WR_PROHIBIT:
                 spin_lock_irqsave(&bdev->lock, flags);
                 if (bdev->state != SCM_WR_PROHIBIT)
-                        pr_info("%lu: Write access to the SCM increment is suspended\n",
+                        pr_info("%lx: Write access to the SCM increment is suspended\n",
                                 (unsigned long) bdev->scmdev->address);
                 bdev->state = SCM_WR_PROHIBIT;
                 spin_unlock_irqrestore(&bdev->lock, flags);
@@ -445,7 +445,7 @@ void scm_blk_set_available(struct scm_blk_dev *bdev)
 
         spin_lock_irqsave(&bdev->lock, flags);
         if (bdev->state == SCM_WR_PROHIBIT)
-                pr_info("%lu: Write access to the SCM increment is restored\n",
+                pr_info("%lx: Write access to the SCM increment is restored\n",
                         (unsigned long) bdev->scmdev->address);
         bdev->state = SCM_OPER;
         spin_unlock_irqrestore(&bdev->lock, flags);
@@ -463,12 +463,15 @@ static int __init scm_blk_init(void)
                 goto out;
 
         scm_major = ret;
-        if (scm_alloc_rqs(nr_requests))
+        ret = scm_alloc_rqs(nr_requests);
+        if (ret)
                 goto out_unreg;
 
         scm_debug = debug_register("scm_log", 16, 1, 16);
-        if (!scm_debug)
+        if (!scm_debug) {
+                ret = -ENOMEM;
                 goto out_free;
+        }
 
         debug_register_view(scm_debug, &debug_hex_ascii_view);
         debug_set_level(scm_debug, 2);
diff --git a/drivers/s390/block/scm_drv.c b/drivers/s390/block/scm_drv.c
index 5f6180d6ff08..c98cf52d78d1 100644
--- a/drivers/s390/block/scm_drv.c
+++ b/drivers/s390/block/scm_drv.c
@@ -19,7 +19,7 @@ static void scm_notify(struct scm_device *scmdev, enum scm_event event)
 
         switch (event) {
         case SCM_CHANGE:
-                pr_info("%lu: The capabilities of the SCM increment changed\n",
+                pr_info("%lx: The capabilities of the SCM increment changed\n",
                         (unsigned long) scmdev->address);
                 SCM_LOG(2, "State changed");
                 SCM_LOG_STATE(2, scmdev);
diff --git a/drivers/s390/char/tty3270.c b/drivers/s390/char/tty3270.c
index b907dba24025..cee69dac3e18 100644
--- a/drivers/s390/char/tty3270.c
+++ b/drivers/s390/char/tty3270.c
@@ -915,7 +915,7 @@ static int tty3270_install(struct tty_driver *driver, struct tty_struct *tty)
         int i, rc;
 
         /* Check if the tty3270 is already there. */
-        view = raw3270_find_view(&tty3270_fn, tty->index);
+        view = raw3270_find_view(&tty3270_fn, tty->index + RAW3270_FIRSTMINOR);
         if (!IS_ERR(view)) {
                 tp = container_of(view, struct tty3270, view);
                 tty->driver_data = tp;
@@ -927,15 +927,16 @@ static int tty3270_install(struct tty_driver *driver, struct tty_struct *tty)
                 tp->inattr = TF_INPUT;
                 return tty_port_install(&tp->port, driver, tty);
         }
-        if (tty3270_max_index < tty->index)
-                tty3270_max_index = tty->index;
+        if (tty3270_max_index < tty->index + 1)
+                tty3270_max_index = tty->index + 1;
 
         /* Allocate tty3270 structure on first open. */
         tp = tty3270_alloc_view();
         if (IS_ERR(tp))
                 return PTR_ERR(tp);
 
-        rc = raw3270_add_view(&tp->view, &tty3270_fn, tty->index);
+        rc = raw3270_add_view(&tp->view, &tty3270_fn,
+                              tty->index + RAW3270_FIRSTMINOR);
         if (rc) {
                 tty3270_free_view(tp);
                 return rc;
@@ -1846,12 +1847,12 @@ static const struct tty_operations tty3270_ops = {
 
 void tty3270_create_cb(int minor)
 {
-        tty_register_device(tty3270_driver, minor, NULL);
+        tty_register_device(tty3270_driver, minor - RAW3270_FIRSTMINOR, NULL);
 }
 
 void tty3270_destroy_cb(int minor)
 {
-        tty_unregister_device(tty3270_driver, minor);
+        tty_unregister_device(tty3270_driver, minor - RAW3270_FIRSTMINOR);
 }
 
 struct raw3270_notifier tty3270_notifier =
@@ -1884,7 +1885,8 @@ static int __init tty3270_init(void)
         driver->driver_name = "tty3270";
         driver->name = "3270/tty";
         driver->major = IBM_TTY3270_MAJOR;
-        driver->minor_start = 0;
+        driver->minor_start = RAW3270_FIRSTMINOR;
+        driver->name_base = RAW3270_FIRSTMINOR;
         driver->type = TTY_DRIVER_TYPE_SYSTEM;
         driver->subtype = SYSTEM_TYPE_TTY;
         driver->init_termios = tty_std_termios;
diff --git a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
index 2daf4b0da434..90bc7bd00966 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
+++ b/drivers/scsi/bnx2fc/bnx2fc_fcoe.c
@@ -940,6 +940,7 @@ static int bnx2fc_libfc_config(struct fc_lport *lport)
         fc_exch_init(lport);
         fc_rport_init(lport);
         fc_disc_init(lport);
+        fc_disc_config(lport, lport);
         return 0;
 }
 
@@ -2133,6 +2134,7 @@ static int _bnx2fc_create(struct net_device *netdev,
         }
 
         ctlr = bnx2fc_to_ctlr(interface);
+        cdev = fcoe_ctlr_to_ctlr_dev(ctlr);
         interface->vlan_id = vlan_id;
 
         interface->timer_work_queue =
@@ -2143,7 +2145,7 @@ static int _bnx2fc_create(struct net_device *netdev,
                 goto ifput_err;
         }
 
-        lport = bnx2fc_if_create(interface, &interface->hba->pcidev->dev, 0);
+        lport = bnx2fc_if_create(interface, &cdev->dev, 0);
         if (!lport) {
                 printk(KERN_ERR PFX "Failed to create interface (%s)\n",
                         netdev->name);
@@ -2159,8 +2161,6 @@ static int _bnx2fc_create(struct net_device *netdev,
         /* Make this master N_port */
         ctlr->lp = lport;
 
-        cdev = fcoe_ctlr_to_ctlr_dev(ctlr);
-
         if (link_state == BNX2FC_CREATE_LINK_UP)
                 cdev->enabled = FCOE_CTLR_ENABLED;
         else
diff --git a/drivers/scsi/fcoe/fcoe.c b/drivers/scsi/fcoe/fcoe.c
index b5d92fc93c70..9bfdc9a3f897 100644
--- a/drivers/scsi/fcoe/fcoe.c
+++ b/drivers/scsi/fcoe/fcoe.c
@@ -490,7 +490,6 @@ static void fcoe_interface_cleanup(struct fcoe_interface *fcoe)
 {
         struct net_device *netdev = fcoe->netdev;
         struct fcoe_ctlr *fip = fcoe_to_ctlr(fcoe);
-        struct fcoe_ctlr_device *ctlr_dev = fcoe_ctlr_to_ctlr_dev(fip);
 
         rtnl_lock();
         if (!fcoe->removed)
@@ -501,7 +500,6 @@ static void fcoe_interface_cleanup(struct fcoe_interface *fcoe)
         /* tear-down the FCoE controller */
         fcoe_ctlr_destroy(fip);
         scsi_host_put(fip->lp->host);
-        fcoe_ctlr_device_delete(ctlr_dev);
         dev_put(netdev);
         module_put(THIS_MODULE);
 }
@@ -2194,6 +2192,8 @@ out_nodev:
  */
 static void fcoe_destroy_work(struct work_struct *work)
 {
+        struct fcoe_ctlr_device *cdev;
+        struct fcoe_ctlr *ctlr;
         struct fcoe_port *port;
         struct fcoe_interface *fcoe;
         struct Scsi_Host *shost;
@@ -2224,10 +2224,15 @@ static void fcoe_destroy_work(struct work_struct *work)
         mutex_lock(&fcoe_config_mutex);
 
         fcoe = port->priv;
+        ctlr = fcoe_to_ctlr(fcoe);
+        cdev = fcoe_ctlr_to_ctlr_dev(ctlr);
+
         fcoe_if_destroy(port->lport);
         fcoe_interface_cleanup(fcoe);
 
         mutex_unlock(&fcoe_config_mutex);
+
+        fcoe_ctlr_device_delete(cdev);
 }
 
 /**
@@ -2335,7 +2340,9 @@ static int _fcoe_create(struct net_device *netdev, enum fip_state fip_mode,
                 rc = -EIO;
                 rtnl_unlock();
                 fcoe_interface_cleanup(fcoe);
-                goto out_nortnl;
+                mutex_unlock(&fcoe_config_mutex);
+                fcoe_ctlr_device_delete(ctlr_dev);
+                goto out;
         }
 
         /* Make this the "master" N_Port */
@@ -2375,8 +2382,8 @@ static int _fcoe_create(struct net_device *netdev, enum fip_state fip_mode,
 
 out_nodev:
         rtnl_unlock();
-out_nortnl:
         mutex_unlock(&fcoe_config_mutex);
+out:
         return rc;
 }
 
diff --git a/drivers/scsi/fcoe/fcoe_ctlr.c b/drivers/scsi/fcoe/fcoe_ctlr.c
index 08c3bc398da2..a76247201be5 100644
--- a/drivers/scsi/fcoe/fcoe_ctlr.c
+++ b/drivers/scsi/fcoe/fcoe_ctlr.c
@@ -2815,6 +2815,47 @@ unlock:
 }
 
 /**
+ * fcoe_ctlr_mode_set() - Set or reset the ctlr's mode
+ * @lport: The local port to be (re)configured
+ * @fip:   The FCoE controller whose mode is changing
+ * @fip_mode: The new fip mode
+ *
+ * Note that the we shouldn't be changing the libfc discovery settings
+ * (fc_disc_config) while an lport is going through the libfc state
+ * machine. The mode can only be changed when a fcoe_ctlr device is
+ * disabled, so that should ensure that this routine is only called
+ * when nothing is happening.
+ */
+void fcoe_ctlr_mode_set(struct fc_lport *lport, struct fcoe_ctlr *fip,
+                        enum fip_state fip_mode)
+{
+        void *priv;
+
+        WARN_ON(lport->state != LPORT_ST_RESET &&
+                lport->state != LPORT_ST_DISABLED);
+
+        if (fip_mode == FIP_MODE_VN2VN) {
+                lport->rport_priv_size = sizeof(struct fcoe_rport);
+                lport->point_to_multipoint = 1;
+                lport->tt.disc_recv_req = fcoe_ctlr_disc_recv;
+                lport->tt.disc_start = fcoe_ctlr_disc_start;
+                lport->tt.disc_stop = fcoe_ctlr_disc_stop;
+                lport->tt.disc_stop_final = fcoe_ctlr_disc_stop_final;
+                priv = fip;
+        } else {
+                lport->rport_priv_size = 0;
+                lport->point_to_multipoint = 0;
+                lport->tt.disc_recv_req = NULL;
+                lport->tt.disc_start = NULL;
+                lport->tt.disc_stop = NULL;
+                lport->tt.disc_stop_final = NULL;
+                priv = lport;
+        }
+
+        fc_disc_config(lport, priv);
+}
+
+/**
  * fcoe_libfc_config() - Sets up libfc related properties for local port
  * @lport:    The local port to configure libfc for
  * @fip:      The FCoE controller in use by the local port
@@ -2833,21 +2874,9 @@ int fcoe_libfc_config(struct fc_lport *lport, struct fcoe_ctlr *fip,
         fc_exch_init(lport);
         fc_elsct_init(lport);
         fc_lport_init(lport);
-        if (fip->mode == FIP_MODE_VN2VN)
-                lport->rport_priv_size = sizeof(struct fcoe_rport);
         fc_rport_init(lport);
-        if (fip->mode == FIP_MODE_VN2VN) {
-                lport->point_to_multipoint = 1;
-                lport->tt.disc_recv_req = fcoe_ctlr_disc_recv;
-                lport->tt.disc_start = fcoe_ctlr_disc_start;
-                lport->tt.disc_stop = fcoe_ctlr_disc_stop;
-                lport->tt.disc_stop_final = fcoe_ctlr_disc_stop_final;
-                mutex_init(&lport->disc.disc_mutex);
-                INIT_LIST_HEAD(&lport->disc.rports);
-                lport->disc.priv = fip;
-        } else {
-                fc_disc_init(lport);
-        }
+        fc_disc_init(lport);
+        fcoe_ctlr_mode_set(lport, fip, fip->mode);
         return 0;
 }
 EXPORT_SYMBOL_GPL(fcoe_libfc_config);
@@ -2875,6 +2904,7 @@ EXPORT_SYMBOL(fcoe_fcf_get_selected);
 void fcoe_ctlr_set_fip_mode(struct fcoe_ctlr_device *ctlr_dev)
 {
         struct fcoe_ctlr *ctlr = fcoe_ctlr_device_priv(ctlr_dev);
+        struct fc_lport *lport = ctlr->lp;
 
         mutex_lock(&ctlr->ctlr_mutex);
         switch (ctlr_dev->mode) {
@@ -2888,5 +2918,7 @@ void fcoe_ctlr_set_fip_mode(struct fcoe_ctlr_device *ctlr_dev)
         }
 
         mutex_unlock(&ctlr->ctlr_mutex);
+
+        fcoe_ctlr_mode_set(lport, ctlr, ctlr->mode);
 }
 EXPORT_SYMBOL(fcoe_ctlr_set_fip_mode);
diff --git a/drivers/scsi/libfc/fc_disc.c b/drivers/scsi/libfc/fc_disc.c
index 8e561e6a557c..880a9068ca12 100644
--- a/drivers/scsi/libfc/fc_disc.c
+++ b/drivers/scsi/libfc/fc_disc.c
@@ -712,12 +712,13 @@ static void fc_disc_stop_final(struct fc_lport *lport)
 }
 
 /**
- * fc_disc_init() - Initialize the discovery layer for a local port
- * @lport: The local port that needs the discovery layer to be initialized
+ * fc_disc_config() - Configure the discovery layer for a local port
+ * @lport: The local port that needs the discovery layer to be configured
+ * @priv: Private data structre for users of the discovery layer
  */
-int fc_disc_init(struct fc_lport *lport)
+void fc_disc_config(struct fc_lport *lport, void *priv)
 {
-        struct fc_disc *disc;
+        struct fc_disc *disc = &lport->disc;
 
         if (!lport->tt.disc_start)
                 lport->tt.disc_start = fc_disc_start;
@@ -732,12 +733,21 @@ int fc_disc_init(struct fc_lport *lport)
                 lport->tt.disc_recv_req = fc_disc_recv_req;
 
         disc = &lport->disc;
+
+        disc->priv = priv;
+}
+EXPORT_SYMBOL(fc_disc_config);
+
+/**
+ * fc_disc_init() - Initialize the discovery layer for a local port
+ * @lport: The local port that needs the discovery layer to be initialized
+ */
+void fc_disc_init(struct fc_lport *lport)
+{
+        struct fc_disc *disc = &lport->disc;
+
         INIT_DELAYED_WORK(&disc->disc_work, fc_disc_timeout);
         mutex_init(&disc->disc_mutex);
         INIT_LIST_HEAD(&disc->rports);
-
-        disc->priv = lport;
-
-        return 0;
 }
 EXPORT_SYMBOL(fc_disc_init);
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index f80eee74a311..2be0de920d67 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -55,6 +55,7 @@ comment "SPI Master Controller Drivers"
 
 config SPI_ALTERA
         tristate "Altera SPI Controller"
+        depends on GENERIC_HARDIRQS
         select SPI_BITBANG
         help
           This is the driver for the Altera SPI Controller.
@@ -310,7 +311,7 @@ config SPI_PXA2XX_DMA
 
 config SPI_PXA2XX
         tristate "PXA2xx SSP SPI master"
-        depends on ARCH_PXA || PCI || ACPI
+        depends on (ARCH_PXA || PCI || ACPI) && GENERIC_HARDIRQS
         select PXA_SSP if ARCH_PXA
         help
           This enables using a PXA2xx or Sodaville SSP port as a SPI master
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index 9578af782a77..d7df435d962e 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -152,7 +152,6 @@ static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
 static int bcm63xx_spi_setup(struct spi_device *spi)
 {
         struct bcm63xx_spi *bs;
-        int ret;
 
         bs = spi_master_get_devdata(spi->master);
 
@@ -490,7 +489,7 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
         default:
                 dev_err(dev, "unsupported MSG_CTL width: %d\n",
                          bs->msg_ctl_width);
-                goto out_clk_disable;
+                goto out_err;
         }
 
         /* Initialize hardware */
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 89480b281d74..3e490ee7f275 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -164,7 +164,7 @@ static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
 
                 for (i = count; i > 0; i--) {
                         data = tx_buf ? *tx_buf++ : 0;
-                        if (len == EOFBYTE)
+                        if (len == EOFBYTE && t->cs_change)
                                 setbits32(&fifo->txcmd, MPC512x_PSC_FIFO_EOF);
                         out_8(&fifo->txdata_8, data);
                         len--;
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 90b27a3508a6..810413883c79 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1168,7 +1168,6 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
 
         master->dev.parent = &pdev->dev;
         master->dev.of_node = pdev->dev.of_node;
-        ACPI_HANDLE_SET(&master->dev, ACPI_HANDLE(&pdev->dev));
         /* the spi->mode bits understood by this driver: */
         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
 
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index e862ab8853aa..4188b2faac5c 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -994,25 +994,30 @@ static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 {
         struct s3c64xx_spi_driver_data *sdd = data;
         struct spi_master *spi = sdd->master;
-        unsigned int val;
+        unsigned int val, clr = 0;
 
-        val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR);
+        val = readl(sdd->regs + S3C64XX_SPI_STATUS);
 
-        val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR |
-                S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
-                S3C64XX_SPI_PND_TX_OVERRUN_CLR |
-                S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
-
-        writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR);
-
-        if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR)
+        if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
+                clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
                 dev_err(&spi->dev, "RX overrun\n");
-        if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR)
+        }
+        if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
+                clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
                 dev_err(&spi->dev, "RX underrun\n");
-        if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR)
+        }
+        if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
+                clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
                 dev_err(&spi->dev, "TX overrun\n");
-        if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR)
+        }
+        if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
+                clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
                 dev_err(&spi->dev, "TX underrun\n");
+        }
+
+        /* Clear the pending irq by setting and then clearing it */
+        writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
+        writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 
         return IRQ_HANDLED;
 }
@@ -1036,9 +1041,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
         writel(0, regs + S3C64XX_SPI_MODE_CFG);
         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 
-        /* Clear any irq pending bits */
-        writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
-                                regs + S3C64XX_SPI_PENDING_CLR);
+        /* Clear any irq pending bits, should set and clear the bits */
+        val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
+                S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
+                S3C64XX_SPI_PND_TX_OVERRUN_CLR |
+                S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
+        writel(val, regs + S3C64XX_SPI_PENDING_CLR);
+        writel(0, regs + S3C64XX_SPI_PENDING_CLR);
 
         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
 
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index b8698b389ef3..a829563f4713 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -858,21 +858,6 @@ static int tegra_slink_setup(struct spi_device *spi)
         return 0;
 }
 
-static int tegra_slink_prepare_transfer(struct spi_master *master)
-{
-        struct tegra_slink_data *tspi = spi_master_get_devdata(master);
-
-        return pm_runtime_get_sync(tspi->dev);
-}
-
-static int tegra_slink_unprepare_transfer(struct spi_master *master)
-{
-        struct tegra_slink_data *tspi = spi_master_get_devdata(master);
-
-        pm_runtime_put(tspi->dev);
-        return 0;
-}
-
 static int tegra_slink_transfer_one_message(struct spi_master *master,
                         struct spi_message *msg)
 {
@@ -885,6 +870,12 @@ static int tegra_slink_transfer_one_message(struct spi_master *master,
 
         msg->status = 0;
         msg->actual_length = 0;
+        ret = pm_runtime_get_sync(tspi->dev);
+        if (ret < 0) {
+                dev_err(tspi->dev, "runtime get failed: %d\n", ret);
+                goto done;
+        }
+
         single_xfer = list_is_singular(&msg->transfers);
         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
                 INIT_COMPLETION(tspi->xfer_completion);
@@ -921,6 +912,8 @@ static int tegra_slink_transfer_one_message(struct spi_master *master,
 exit:
         tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
         tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
+        pm_runtime_put(tspi->dev);
+done:
         msg->status = ret;
         spi_finalize_current_message(master);
         return ret;
@@ -1148,9 +1141,7 @@ static int tegra_slink_probe(struct platform_device *pdev)
         /* the spi->mode bits understood by this driver: */
         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
         master->setup = tegra_slink_setup;
-        master->prepare_transfer_hardware = tegra_slink_prepare_transfer;
         master->transfer_one_message = tegra_slink_transfer_one_message;
-        master->unprepare_transfer_hardware = tegra_slink_unprepare_transfer;
         master->num_chipselect = MAX_CHIP_SELECT;
         master->bus_num = -1;
 
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index f996c600eb8c..004b10f184d4 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -543,17 +543,16 @@ static void spi_pump_messages(struct kthread_work *work)
         /* Lock queue and check for queue work */
         spin_lock_irqsave(&master->queue_lock, flags);
         if (list_empty(&master->queue) || !master->running) {
-                if (master->busy && master->unprepare_transfer_hardware) {
-                        ret = master->unprepare_transfer_hardware(master);
-                        if (ret) {
-                                spin_unlock_irqrestore(&master->queue_lock, flags);
-                                dev_err(&master->dev,
-                                        "failed to unprepare transfer hardware\n");
-                                return;
-                        }
+                if (!master->busy) {
+                        spin_unlock_irqrestore(&master->queue_lock, flags);
+                        return;
                 }
                 master->busy = false;
                 spin_unlock_irqrestore(&master->queue_lock, flags);
+                if (master->unprepare_transfer_hardware &&
+                    master->unprepare_transfer_hardware(master))
+                        dev_err(&master->dev,
+                                "failed to unprepare transfer hardware\n");
                 return;
         }
 
@@ -984,7 +983,7 @@ static void acpi_register_spi_devices(struct spi_master *master)
         acpi_status status;
         acpi_handle handle;
 
-        handle = ACPI_HANDLE(&master->dev);
+        handle = ACPI_HANDLE(master->dev.parent);
         if (!handle)
                 return;
 
diff --git a/drivers/usb/core/port.c b/drivers/usb/core/port.c
index 797f9d514732..65d4e55552c6 100644
--- a/drivers/usb/core/port.c
+++ b/drivers/usb/core/port.c
@@ -67,7 +67,6 @@ static void usb_port_device_release(struct device *dev)
 {
         struct usb_port *port_dev = to_usb_port(dev);
 
-        dev_pm_qos_hide_flags(dev);
         kfree(port_dev);
 }
 
diff --git a/drivers/video/fbmon.c b/drivers/video/fbmon.c
index 94ad0f71383c..7f6709991a5c 100644
--- a/drivers/video/fbmon.c
+++ b/drivers/video/fbmon.c
@@ -1400,7 +1400,7 @@ int fb_videomode_from_videomode(const struct videomode *vm,
         fbmode->vmode = 0;
         if (vm->dmt_flags & VESA_DMT_HSYNC_HIGH)
                 fbmode->sync |= FB_SYNC_HOR_HIGH_ACT;
-        if (vm->dmt_flags & VESA_DMT_HSYNC_HIGH)
+        if (vm->dmt_flags & VESA_DMT_VSYNC_HIGH)
                 fbmode->sync |= FB_SYNC_VERT_HIGH_ACT;
         if (vm->data_flags & DISPLAY_FLAGS_INTERLACED)
                 fbmode->vmode |= FB_VMODE_INTERLACED;
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index 63203acef812..0264704a52be 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -858,6 +858,7 @@ static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
         tmp = ((mode->xres & 7) << 24) | ((display_h_total & 7) << 16)
             | ((mode->hsync_len & 7) << 8) | (hsync_pos & 7);
         lcdc_write_chan(ch, LDHAJR, tmp);
+        lcdc_write_chan_mirror(ch, LDHAJR, tmp);
 }
 
 static void sh_mobile_lcdc_overlay_setup(struct sh_mobile_lcdc_overlay *ovl)
diff --git a/drivers/video/uvesafb.c b/drivers/video/uvesafb.c
index b75db0186488..d4284458377e 100644
--- a/drivers/video/uvesafb.c
+++ b/drivers/video/uvesafb.c
@@ -1973,7 +1973,8 @@ static int uvesafb_init(void)
                         err = -ENOMEM;
 
                 if (err) {
-                        platform_device_put(uvesafb_device);
+                        if (uvesafb_device)
+                                platform_device_put(uvesafb_device);
                         platform_driver_unregister(&uvesafb_driver);
                         cn_del_callback(&uvesafb_cn_id);
                         return err;
diff --git a/firmware/Makefile b/firmware/Makefile
index 5d8ee1319b5c..cbb09ce9730a 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -82,7 +82,7 @@ fw-shipped-$(CONFIG_SCSI_ADVANSYS) += advansys/mcode.bin advansys/38C1600.bin \
 fw-shipped-$(CONFIG_SCSI_QLOGIC_1280) += qlogic/1040.bin qlogic/1280.bin \
                                          qlogic/12160.bin
 fw-shipped-$(CONFIG_SCSI_QLOGICPTI) += qlogic/isp1000.bin
-fw-shipped-$(CONFIG_INFINIBAND_QIB) += intel/sd7220.fw
+fw-shipped-$(CONFIG_INFINIBAND_QIB) += qlogic/sd7220.fw
 fw-shipped-$(CONFIG_SND_KORG1212) += korg/k1212.dsp
 fw-shipped-$(CONFIG_SND_MAESTRO3) += ess/maestro3_assp_kernel.fw \
                                      ess/maestro3_assp_minisrc.fw
diff --git a/firmware/intel/sd7220.fw.ihex b/firmware/qlogic/sd7220.fw.ihex
index a33636319112..a33636319112 100644
--- a/firmware/intel/sd7220.fw.ihex
+++ b/firmware/qlogic/sd7220.fw.ihex
diff --git a/fs/block_dev.c b/fs/block_dev.c
index aea605c98ba6..aae187a7f94a 100644
--- a/fs/block_dev.c
+++ b/fs/block_dev.c
@@ -551,6 +551,7 @@ struct block_device *bdgrab(struct block_device *bdev)
         ihold(bdev->bd_inode);
         return bdev;
 }
+EXPORT_SYMBOL(bdgrab);
 
 long nr_blockdev_pages(void)
 {
diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c
index 56efcaadf848..9c6d06dcef8b 100644
--- a/fs/ext4/extents.c
+++ b/fs/ext4/extents.c
@@ -2999,20 +2999,23 @@ static int ext4_split_extent_at(handle_t *handle,
                         if (split_flag & EXT4_EXT_DATA_VALID1) {
                                 err = ext4_ext_zeroout(inode, ex2);
                                 zero_ex.ee_block = ex2->ee_block;
-                                zero_ex.ee_len = ext4_ext_get_actual_len(ex2);
+                                zero_ex.ee_len = cpu_to_le16(
+                                                ext4_ext_get_actual_len(ex2));
                                 ext4_ext_store_pblock(&zero_ex,
                                                       ext4_ext_pblock(ex2));
                         } else {
                                 err = ext4_ext_zeroout(inode, ex);
                                 zero_ex.ee_block = ex->ee_block;
-                                zero_ex.ee_len = ext4_ext_get_actual_len(ex);
+                                zero_ex.ee_len = cpu_to_le16(
+                                                ext4_ext_get_actual_len(ex));
                                 ext4_ext_store_pblock(&zero_ex,
                                                       ext4_ext_pblock(ex));
                         }
                 } else {
                         err = ext4_ext_zeroout(inode, &orig_ex);
                         zero_ex.ee_block = orig_ex.ee_block;
-                        zero_ex.ee_len = ext4_ext_get_actual_len(&orig_ex);
+                        zero_ex.ee_len = cpu_to_le16(
+                                                ext4_ext_get_actual_len(&orig_ex));
                         ext4_ext_store_pblock(&zero_ex,
                                               ext4_ext_pblock(&orig_ex));
                 }
@@ -3272,7 +3275,7 @@ static int ext4_ext_convert_to_initialized(handle_t *handle,
                 if (err)
                         goto out;
                 zero_ex.ee_block = ex->ee_block;
-                zero_ex.ee_len = ext4_ext_get_actual_len(ex);
+                zero_ex.ee_len = cpu_to_le16(ext4_ext_get_actual_len(ex));
                 ext4_ext_store_pblock(&zero_ex, ext4_ext_pblock(ex));
 
                 err = ext4_ext_get_access(handle, inode, path + depth);
diff --git a/fs/ext4/indirect.c b/fs/ext4/indirect.c
index b505a145a593..a04183127ef0 100644
--- a/fs/ext4/indirect.c
+++ b/fs/ext4/indirect.c
@@ -1539,9 +1539,9 @@ static int free_hole_blocks(handle_t *handle, struct inode *inode,
                 blk = *i_data;
                 if (level > 0) {
                         ext4_lblk_t first2;
-                        bh = sb_bread(inode->i_sb, blk);
+                        bh = sb_bread(inode->i_sb, le32_to_cpu(blk));
                         if (!bh) {
-                                EXT4_ERROR_INODE_BLOCK(inode, blk,
+                                EXT4_ERROR_INODE_BLOCK(inode, le32_to_cpu(blk),
                                                        "Read failure");
                                 return -EIO;
                         }
diff --git a/fs/gfs2/file.c b/fs/gfs2/file.c
index 019f45e45097..d79c2dadc536 100644
--- a/fs/gfs2/file.c
+++ b/fs/gfs2/file.c
@@ -923,8 +923,11 @@ static int gfs2_lock(struct file *file, int cmd, struct file_lock *fl)
                 cmd = F_SETLK;
                 fl->fl_type = F_UNLCK;
         }
-        if (unlikely(test_bit(SDF_SHUTDOWN, &sdp->sd_flags)))
+        if (unlikely(test_bit(SDF_SHUTDOWN, &sdp->sd_flags))) {
+                if (fl->fl_type == F_UNLCK)
+                        posix_lock_file_wait(file, fl);
                 return -EIO;
+        }
         if (IS_GETLK(cmd))
                 return dlm_posix_get(ls->ls_dlm, ip->i_no_addr, file, fl);
         else if (fl->fl_type == F_UNLCK)
diff --git a/fs/gfs2/incore.h b/fs/gfs2/incore.h
index 156e42ec84ea..5c29216e9cc1 100644
--- a/fs/gfs2/incore.h
+++ b/fs/gfs2/incore.h
@@ -588,6 +588,7 @@ struct lm_lockstruct {
         struct dlm_lksb ls_control_lksb; /* control_lock */
         char ls_control_lvb[GDLM_LVB_SIZE]; /* control_lock lvb */
         struct completion ls_sync_wait; /* {control,mounted}_{lock,unlock} */
+        char *ls_lvb_bits;
 
         spinlock_t ls_recover_spin; /* protects following fields */
         unsigned long ls_recover_flags; /* DFL_ */
diff --git a/fs/gfs2/lock_dlm.c b/fs/gfs2/lock_dlm.c
index 9802de0f85e6..c8423d6de6c3 100644
--- a/fs/gfs2/lock_dlm.c
+++ b/fs/gfs2/lock_dlm.c
@@ -483,12 +483,8 @@ static void control_lvb_write(struct lm_lockstruct *ls, uint32_t lvb_gen,
 
 static int all_jid_bits_clear(char *lvb)
 {
-        int i;
-        for (i = JID_BITMAP_OFFSET; i < GDLM_LVB_SIZE; i++) {
-                if (lvb[i])
-                        return 0;
-        }
-        return 1;
+        return !memchr_inv(lvb + JID_BITMAP_OFFSET, 0,
+                        GDLM_LVB_SIZE - JID_BITMAP_OFFSET);
 }
 
 static void sync_wait_cb(void *arg)
@@ -580,7 +576,6 @@ static void gfs2_control_func(struct work_struct *work)
 {
         struct gfs2_sbd *sdp = container_of(work, struct gfs2_sbd, sd_control_work.work);
         struct lm_lockstruct *ls = &sdp->sd_lockstruct;
-        char lvb_bits[GDLM_LVB_SIZE];
         uint32_t block_gen, start_gen, lvb_gen, flags;
         int recover_set = 0;
         int write_lvb = 0;
@@ -634,7 +629,7 @@ static void gfs2_control_func(struct work_struct *work)
                 return;
         }
 
-        control_lvb_read(ls, &lvb_gen, lvb_bits);
+        control_lvb_read(ls, &lvb_gen, ls->ls_lvb_bits);
 
         spin_lock(&ls->ls_recover_spin);
         if (block_gen != ls->ls_recover_block ||
@@ -664,10 +659,10 @@ static void gfs2_control_func(struct work_struct *work)
 
                         ls->ls_recover_result[i] = 0;
 
-                        if (!test_bit_le(i, lvb_bits + JID_BITMAP_OFFSET))
+                        if (!test_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET))
                                 continue;
 
-                        __clear_bit_le(i, lvb_bits + JID_BITMAP_OFFSET);
+                        __clear_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET);
                         write_lvb = 1;
                 }
         }
@@ -691,7 +686,7 @@ static void gfs2_control_func(struct work_struct *work)
                                 continue;
                         if (ls->ls_recover_submit[i] < start_gen) {
                                 ls->ls_recover_submit[i] = 0;
-                                __set_bit_le(i, lvb_bits + JID_BITMAP_OFFSET);
+                                __set_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET);
                         }
                 }
                 /* even if there are no bits to set, we need to write the
@@ -705,7 +700,7 @@ static void gfs2_control_func(struct work_struct *work)
         spin_unlock(&ls->ls_recover_spin);
 
         if (write_lvb) {
-                control_lvb_write(ls, start_gen, lvb_bits);
+                control_lvb_write(ls, start_gen, ls->ls_lvb_bits);
                 flags = DLM_LKF_CONVERT | DLM_LKF_VALBLK;
         } else {
                 flags = DLM_LKF_CONVERT;
@@ -725,7 +720,7 @@ static void gfs2_control_func(struct work_struct *work)
          */
 
         for (i = 0; i < recover_size; i++) {
-                if (test_bit_le(i, lvb_bits + JID_BITMAP_OFFSET)) {
+                if (test_bit_le(i, ls->ls_lvb_bits + JID_BITMAP_OFFSET)) {
                         fs_info(sdp, "recover generation %u jid %d\n",
                                 start_gen, i);
                         gfs2_recover_set(sdp, i);
@@ -758,7 +753,6 @@ static void gfs2_control_func(struct work_struct *work)
 static int control_mount(struct gfs2_sbd *sdp)
 {
         struct lm_lockstruct *ls = &sdp->sd_lockstruct;
-        char lvb_bits[GDLM_LVB_SIZE];
         uint32_t start_gen, block_gen, mount_gen, lvb_gen;
         int mounted_mode;
         int retries = 0;
@@ -857,7 +851,7 @@ locks_done:
          * lvb_gen will be non-zero.
          */
 
-        control_lvb_read(ls, &lvb_gen, lvb_bits);
+        control_lvb_read(ls, &lvb_gen, ls->ls_lvb_bits);
 
         if (lvb_gen == 0xFFFFFFFF) {
                 /* special value to force mount attempts to fail */
@@ -887,7 +881,7 @@ locks_done:
          * and all lvb bits to be clear (no pending journal recoveries.)
          */
 
-        if (!all_jid_bits_clear(lvb_bits)) {
+        if (!all_jid_bits_clear(ls->ls_lvb_bits)) {
                 /* journals need recovery, wait until all are clear */
                 fs_info(sdp, "control_mount wait for journal recovery\n");
                 goto restart;
@@ -949,7 +943,6 @@ static int dlm_recovery_wait(void *word)
 static int control_first_done(struct gfs2_sbd *sdp)
 {
         struct lm_lockstruct *ls = &sdp->sd_lockstruct;
-        char lvb_bits[GDLM_LVB_SIZE];
         uint32_t start_gen, block_gen;
         int error;
 
@@ -991,8 +984,8 @@ restart:
         memset(ls->ls_recover_result, 0, ls->ls_recover_size*sizeof(uint32_t));
         spin_unlock(&ls->ls_recover_spin);
 
-        memset(lvb_bits, 0, sizeof(lvb_bits));
-        control_lvb_write(ls, start_gen, lvb_bits);
+        memset(ls->ls_lvb_bits, 0, GDLM_LVB_SIZE);
+        control_lvb_write(ls, start_gen, ls->ls_lvb_bits);
 
         error = mounted_lock(sdp, DLM_LOCK_PR, DLM_LKF_CONVERT);
         if (error)
@@ -1022,6 +1015,12 @@ static int set_recover_size(struct gfs2_sbd *sdp, struct dlm_slot *slots,
         uint32_t old_size, new_size;
         int i, max_jid;
 
+        if (!ls->ls_lvb_bits) {
+                ls->ls_lvb_bits = kzalloc(GDLM_LVB_SIZE, GFP_NOFS);
+                if (!ls->ls_lvb_bits)
+                        return -ENOMEM;
+        }
+
         max_jid = 0;
         for (i = 0; i < num_slots; i++) {
                 if (max_jid < slots[i].slot - 1)
@@ -1057,6 +1056,7 @@ static int set_recover_size(struct gfs2_sbd *sdp, struct dlm_slot *slots,
 
 static void free_recover_size(struct lm_lockstruct *ls)
 {
+        kfree(ls->ls_lvb_bits);
         kfree(ls->ls_recover_submit);
         kfree(ls->ls_recover_result);
         ls->ls_recover_submit = NULL;
@@ -1205,6 +1205,7 @@ static int gdlm_mount(struct gfs2_sbd *sdp, const char *table)
         ls->ls_recover_size = 0;
         ls->ls_recover_submit = NULL;
         ls->ls_recover_result = NULL;
+        ls->ls_lvb_bits = NULL;
 
         error = set_recover_size(sdp, NULL, 0);
         if (error)
diff --git a/fs/gfs2/rgrp.c b/fs/gfs2/rgrp.c
index d1f51fd73f86..5a51265a4341 100644
--- a/fs/gfs2/rgrp.c
+++ b/fs/gfs2/rgrp.c
@@ -576,7 +576,7 @@ int gfs2_rs_alloc(struct gfs2_inode *ip)
         RB_CLEAR_NODE(&ip->i_res->rs_node);
 out:
         up_write(&ip->i_rw_mutex);
-        return 0;
+        return error;
 }
 
 static void dump_rs(struct seq_file *seq, const struct gfs2_blkreserv *rs)
@@ -1181,12 +1181,9 @@ int gfs2_rgrp_send_discards(struct gfs2_sbd *sdp, u64 offset,
                              const struct gfs2_bitmap *bi, unsigned minlen, u64 *ptrimmed)
 {
         struct super_block *sb = sdp->sd_vfs;
-        struct block_device *bdev = sb->s_bdev;
-        const unsigned int sects_per_blk = sdp->sd_sb.sb_bsize /
-                                           bdev_logical_block_size(sb->s_bdev);
         u64 blk;
         sector_t start = 0;
-        sector_t nr_sects = 0;
+        sector_t nr_blks = 0;
         int rv;
         unsigned int x;
         u32 trimmed = 0;
@@ -1206,35 +1203,34 @@ int gfs2_rgrp_send_discards(struct gfs2_sbd *sdp, u64 offset,
                 if (diff == 0)
                         continue;
                 blk = offset + ((bi->bi_start + x) * GFS2_NBBY);
-                blk *= sects_per_blk; /* convert to sectors */
                 while(diff) {
                         if (diff & 1) {
-                                if (nr_sects == 0)
+                                if (nr_blks == 0)
                                         goto start_new_extent;
-                                if ((start + nr_sects) != blk) {
-                                        if (nr_sects >= minlen) {
-                                                rv = blkdev_issue_discard(bdev,
-                                                        start, nr_sects,
+                                if ((start + nr_blks) != blk) {
+                                        if (nr_blks >= minlen) {
+                                                rv = sb_issue_discard(sb,
+                                                        start, nr_blks,
                                                         GFP_NOFS, 0);
                                                 if (rv)
                                                         goto fail;
-                                                trimmed += nr_sects;
+                                                trimmed += nr_blks;
                                         }
-                                        nr_sects = 0;
+                                        nr_blks = 0;
 start_new_extent:
                                         start = blk;
                                 }
-                                nr_sects += sects_per_blk;
+                                nr_blks++;
                         }
                         diff >>= 2;
-                        blk += sects_per_blk;
+                        blk++;
                 }
         }
-        if (nr_sects >= minlen) {
-                rv = blkdev_issue_discard(bdev, start, nr_sects, GFP_NOFS, 0);
+        if (nr_blks >= minlen) {
+                rv = sb_issue_discard(sb, start, nr_blks, GFP_NOFS, 0);
                 if (rv)
                         goto fail;
-                trimmed += nr_sects;
+                trimmed += nr_blks;
         }
         if (ptrimmed)
                 *ptrimmed = trimmed;
diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c
index 01168865dd37..a2720071f282 100644
--- a/fs/nfsd/nfs4xdr.c
+++ b/fs/nfsd/nfs4xdr.c
@@ -264,7 +264,7 @@ nfsd4_decode_fattr(struct nfsd4_compoundargs *argp, u32 *bmval,
                 iattr->ia_valid |= ATTR_SIZE;
         }
         if (bmval[0] & FATTR4_WORD0_ACL) {
-                int nace;
+                u32 nace;
                 struct nfs4_ace *ace;
 
                 READ_BUF(4); len += 4;
diff --git a/fs/reiserfs/xattr.c b/fs/reiserfs/xattr.c
index c196369fe408..4cce1d9552fb 100644
--- a/fs/reiserfs/xattr.c
+++ b/fs/reiserfs/xattr.c
@@ -187,8 +187,8 @@ fill_with_dentries(void *buf, const char *name, int namelen, loff_t offset,
         if (dbuf->count == ARRAY_SIZE(dbuf->dentries))
                 return -ENOSPC;
 
-        if (name[0] == '.' && (name[1] == '\0' ||
-                               (name[1] == '.' && name[2] == '\0')))
+        if (name[0] == '.' && (namelen < 2 ||
+                               (namelen == 2 && name[1] == '.')))
                 return 0;
 
         dentry = lookup_one_len(name, dbuf->xadir, namelen);
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index ac838b844936..f21acf0ef01f 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -1568,6 +1568,12 @@ static int ubifs_remount_rw(struct ubifs_info *c)
         c->remounting_rw = 1;
         c->ro_mount = 0;
 
+        if (c->space_fixup) {
+                err = ubifs_fixup_free_space(c);
+                if (err)
+                        return err;
+        }
+
         err = check_free_space(c);
         if (err)
                 goto out;
@@ -1684,12 +1690,6 @@ static int ubifs_remount_rw(struct ubifs_info *c)
                 err = dbg_check_space_info(c);
         }
 
-        if (c->space_fixup) {
-                err = ubifs_fixup_free_space(c);
-                if (err)
-                        goto out;
-        }
-
         mutex_unlock(&c->umount_mutex);
         return err;
 
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 76a87fb57ac2..377cd8c3395e 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -141,11 +141,11 @@ typedef struct {
 } compat_sigset_t;
 
 struct compat_sigaction {
-#ifndef __ARCH_HAS_ODD_SIGACTION
+#ifndef __ARCH_HAS_IRIX_SIGACTION
         compat_uptr_t                   sa_handler;
         compat_ulong_t                  sa_flags;
 #else
-        compat_ulong_t                  sa_flags;
+        compat_uint_t                   sa_flags;
         compat_uptr_t                   sa_handler;
 #endif
 #ifdef __ARCH_HAS_SA_RESTORER
diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
index e83ef39b3bea..fe8c4476f7e4 100644
--- a/include/linux/devfreq.h
+++ b/include/linux/devfreq.h
@@ -213,7 +213,7 @@ struct devfreq_simple_ondemand_data {
 #endif
 
 #else /* !CONFIG_PM_DEVFREQ */
-static struct devfreq *devfreq_add_device(struct device *dev,
+static inline struct devfreq *devfreq_add_device(struct device *dev,
                                           struct devfreq_dev_profile *profile,
                                           const char *governor_name,
                                           void *data)
@@ -221,34 +221,34 @@ static struct devfreq *devfreq_add_device(struct device *dev,
         return NULL;
 }
 
-static int devfreq_remove_device(struct devfreq *devfreq)
+static inline int devfreq_remove_device(struct devfreq *devfreq)
 {
         return 0;
 }
 
-static int devfreq_suspend_device(struct devfreq *devfreq)
+static inline int devfreq_suspend_device(struct devfreq *devfreq)
 {
         return 0;
 }
 
-static int devfreq_resume_device(struct devfreq *devfreq)
+static inline int devfreq_resume_device(struct devfreq *devfreq)
 {
         return 0;
 }
 
-static struct opp *devfreq_recommended_opp(struct device *dev,
+static inline struct opp *devfreq_recommended_opp(struct device *dev,
                                            unsigned long *freq, u32 flags)
 {
-        return -EINVAL;
+        return ERR_PTR(-EINVAL);
 }
 
-static int devfreq_register_opp_notifier(struct device *dev,
+static inline int devfreq_register_opp_notifier(struct device *dev,
                                          struct devfreq *devfreq)
 {
         return -EINVAL;
 }
 
-static int devfreq_unregister_opp_notifier(struct device *dev,
+static inline int devfreq_unregister_opp_notifier(struct device *dev,
                                            struct devfreq *devfreq)
 {
         return -EINVAL;
diff --git a/include/linux/gpio-pxa.h b/include/linux/gpio-pxa.h
index d755b28ba635..d90ebbe02ca4 100644
--- a/include/linux/gpio-pxa.h
+++ b/include/linux/gpio-pxa.h
@@ -14,6 +14,7 @@ extern int pxa_last_gpio;
 extern int pxa_irq_to_gpio(int irq);
 
 struct pxa_gpio_platform_data {
+        int irq_base;
         int (*gpio_set_wake)(unsigned int gpio, unsigned int on);
 };
 
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index cad77fe09d77..c13958251927 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -518,7 +518,7 @@ int kvm_write_guest(struct kvm *kvm, gpa_t gpa, const void *data,
 int kvm_write_guest_cached(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
                            void *data, unsigned long len);
 int kvm_gfn_to_hva_cache_init(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
-                              gpa_t gpa);
+                              gpa_t gpa, unsigned long len);
 int kvm_clear_guest_page(struct kvm *kvm, gfn_t gfn, int offset, int len);
 int kvm_clear_guest(struct kvm *kvm, gpa_t gpa, unsigned long len);
 struct kvm_memory_slot *gfn_to_memslot(struct kvm *kvm, gfn_t gfn);
diff --git a/include/linux/kvm_types.h b/include/linux/kvm_types.h
index fa7cc7244cbd..b0bcce0ddc95 100644
--- a/include/linux/kvm_types.h
+++ b/include/linux/kvm_types.h
@@ -71,6 +71,7 @@ struct gfn_to_hva_cache {
         u64 generation;
         gpa_t gpa;
         unsigned long hva;
+        unsigned long len;
         struct kvm_memory_slot *memslot;
 };
 
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index b3d00fa4b314..6151e903eef0 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -210,9 +210,9 @@ struct netdev_hw_addr {
 #define NETDEV_HW_ADDR_T_SLAVE          3
 #define NETDEV_HW_ADDR_T_UNICAST        4
 #define NETDEV_HW_ADDR_T_MULTICAST      5
-        bool                    synced;
         bool                    global_use;
         int                     refcount;
+        int                     synced;
         struct rcu_head         rcu_head;
 };
 
@@ -895,7 +895,7 @@ struct netdev_fcoe_hbainfo {
  *
  * int (*ndo_bridge_setlink)(struct net_device *dev, struct nlmsghdr *nlh)
  * int (*ndo_bridge_getlink)(struct sk_buff *skb, u32 pid, u32 seq,
- *                           struct net_device *dev)
+ *                           struct net_device *dev, u32 filter_mask)
  *
  * int (*ndo_change_carrier)(struct net_device *dev, bool new_carrier);
  *      Called to change device carrier. Soft-devices (like dummy, team, etc)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 2461033a7987..710067f3618c 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -916,6 +916,7 @@ void pci_disable_rom(struct pci_dev *pdev);
 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
+void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
 
 /* Power management related routines */
 int pci_save_state(struct pci_dev *dev);
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 778804df293f..2c2a9e8d8578 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -118,9 +118,9 @@ struct pinctrl_desc {
         const char *name;
         struct pinctrl_pin_desc const *pins;
         unsigned int npins;
-        struct pinctrl_ops *pctlops;
-        struct pinmux_ops *pmxops;
-        struct pinconf_ops *confops;
+        const struct pinctrl_ops *pctlops;
+        const struct pinmux_ops *pmxops;
+        const struct pinconf_ops *confops;
         struct module *owner;
 };
 
diff --git a/include/linux/signal.h b/include/linux/signal.h
index a2dcb94ea49d..9475c5cb28bc 100644
--- a/include/linux/signal.h
+++ b/include/linux/signal.h
@@ -250,11 +250,11 @@ extern int show_unhandled_signals;
 extern int sigsuspend(sigset_t *);
 
 struct sigaction {
-#ifndef __ARCH_HAS_ODD_SIGACTION
+#ifndef __ARCH_HAS_IRIX_SIGACTION
         __sighandler_t  sa_handler;
         unsigned long   sa_flags;
 #else
-        unsigned long   sa_flags;
+        unsigned int    sa_flags;
         __sighandler_t  sa_handler;
 #endif
 #ifdef __ARCH_HAS_SA_RESTORER
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 441f5bfdab8e..b8292d8cc9fa 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -2643,6 +2643,13 @@ static inline void nf_reset(struct sk_buff *skb)
 #endif
 }
 
+static inline void nf_reset_trace(struct sk_buff *skb)
+{
+#if IS_ENABLED(CONFIG_NETFILTER_XT_TARGET_TRACE)
+        skb->nf_trace = 0;
+#endif
+}
+
 /* Note: This doesn't put any conntrack and bridge info in dst. */
 static inline void __nf_copy(struct sk_buff *dst, const struct sk_buff *src)
 {
diff --git a/include/scsi/libfc.h b/include/scsi/libfc.h
index 399162b50a8d..e1379b4e8faf 100644
--- a/include/scsi/libfc.h
+++ b/include/scsi/libfc.h
@@ -1074,7 +1074,8 @@ void fc_rport_terminate_io(struct fc_rport *);
 /*
  * DISCOVERY LAYER
  *****************************/
-int fc_disc_init(struct fc_lport *);
+void fc_disc_init(struct fc_lport *);
+void fc_disc_config(struct fc_lport *, void *);
 
 static inline struct fc_lport *fc_disc_lport(struct fc_disc *disc)
 {
diff --git a/include/sound/max98090.h b/include/sound/max98090.h
index 95efb13f8478..95efb13f8478 100755..100644
--- a/include/sound/max98090.h
+++ b/include/sound/max98090.h
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index e1ef63d4a5c4..44a30b108683 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -488,6 +488,7 @@ struct snd_soc_dapm_path {
         /* status */
         u32 connect:1;  /* source and sink widgets are connected */
         u32 walked:1;   /* path has been walked */
+        u32 walking:1;  /* path is in the process of being walked */
         u32 weak:1;     /* path ignored for power management */
 
         int (*connected)(struct snd_soc_dapm_widget *source,
diff --git a/ipc/msg.c b/ipc/msg.c
index 31cd1bf6af27..fede1d06ef30 100644
--- a/ipc/msg.c
+++ b/ipc/msg.c
@@ -872,6 +872,7 @@ long do_msgrcv(int msqid, void __user *buf, size_t bufsz, long msgtyp,
                                                         goto out_unlock;
                                                 break;
                                         }
+                                        msg = ERR_PTR(-EAGAIN);
                                 } else
                                         break;
                                 msg_counter++;
diff --git a/mm/mmap.c b/mm/mmap.c
index 6466699b16cb..0db0de1c2fbe 100644
--- a/mm/mmap.c
+++ b/mm/mmap.c
@@ -1940,7 +1940,7 @@ struct vm_area_struct *find_vma(struct mm_struct *mm, unsigned long addr)
 
         /* Check the cache first. */
         /* (Cache hit rate is typically around 35%.) */
-        vma = mm->mmap_cache;
+        vma = ACCESS_ONCE(mm->mmap_cache);
         if (!(vma && vma->vm_end > addr && vma->vm_start <= addr)) {
                 struct rb_node *rb_node;
 
diff --git a/mm/nommu.c b/mm/nommu.c
index e19328087534..2f3ea749c318 100644
--- a/mm/nommu.c
+++ b/mm/nommu.c
@@ -821,7 +821,7 @@ struct vm_area_struct *find_vma(struct mm_struct *mm, unsigned long addr)
         struct vm_area_struct *vma;
 
         /* check the cache first */
-        vma = mm->mmap_cache;
+        vma = ACCESS_ONCE(mm->mmap_cache);
         if (vma && vma->vm_start <= addr && vma->vm_end > addr)
                 return vma;
 
diff --git a/net/core/dev.c b/net/core/dev.c
index b13e5c766c11..e7d68ed8aafe 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -1624,7 +1624,6 @@ int dev_forward_skb(struct net_device *dev, struct sk_buff *skb)
         }
 
         skb_orphan(skb);
-        nf_reset(skb);
 
         if (unlikely(!is_skb_forwardable(dev, skb))) {
                 atomic_long_inc(&dev->rx_dropped);
@@ -1640,6 +1639,7 @@ int dev_forward_skb(struct net_device *dev, struct sk_buff *skb)
         skb->mark = 0;
         secpath_reset(skb);
         nf_reset(skb);
+        nf_reset_trace(skb);
         return netif_rx(skb);
 }
 EXPORT_SYMBOL_GPL(dev_forward_skb);
@@ -3314,6 +3314,7 @@ int netdev_rx_handler_register(struct net_device *dev,
         if (dev->rx_handler)
                 return -EBUSY;
 
+        /* Note: rx_handler_data must be set before rx_handler */
         rcu_assign_pointer(dev->rx_handler_data, rx_handler_data);
         rcu_assign_pointer(dev->rx_handler, rx_handler);
 
@@ -3334,6 +3335,11 @@ void netdev_rx_handler_unregister(struct net_device *dev)
 
         ASSERT_RTNL();
         RCU_INIT_POINTER(dev->rx_handler, NULL);
+        /* a reader seeing a non NULL rx_handler in a rcu_read_lock()
+         * section has a guarantee to see a non NULL rx_handler_data
+         * as well.
+         */
+        synchronize_net();
         RCU_INIT_POINTER(dev->rx_handler_data, NULL);
 }
 EXPORT_SYMBOL_GPL(netdev_rx_handler_unregister);
diff --git a/net/core/dev_addr_lists.c b/net/core/dev_addr_lists.c
index bd2eb9d3e369..abdc9e6ef33e 100644
--- a/net/core/dev_addr_lists.c
+++ b/net/core/dev_addr_lists.c
@@ -37,7 +37,7 @@ static int __hw_addr_create_ex(struct netdev_hw_addr_list *list,
         ha->type = addr_type;
         ha->refcount = 1;
         ha->global_use = global;
-        ha->synced = false;
+        ha->synced = 0;
         list_add_tail_rcu(&ha->list, &list->list);
         list->count++;
 
@@ -165,7 +165,7 @@ int __hw_addr_sync(struct netdev_hw_addr_list *to_list,
                                             addr_len, ha->type);
                         if (err)
                                 break;
-                        ha->synced = true;
+                        ha->synced++;
                         ha->refcount++;
                 } else if (ha->refcount == 1) {
                         __hw_addr_del(to_list, ha->addr, addr_len, ha->type);
@@ -186,7 +186,7 @@ void __hw_addr_unsync(struct netdev_hw_addr_list *to_list,
                 if (ha->synced) {
                         __hw_addr_del(to_list, ha->addr,
                                       addr_len, ha->type);
-                        ha->synced = false;
+                        ha->synced--;
                         __hw_addr_del(from_list, ha->addr,
                                       addr_len, ha->type);
                 }
diff --git a/net/core/flow.c b/net/core/flow.c
index c56ea6f7f6c7..2bfd081c59f7 100644
--- a/net/core/flow.c
+++ b/net/core/flow.c
@@ -328,7 +328,7 @@ static void flow_cache_flush_per_cpu(void *data)
         struct flow_flush_info *info = data;
         struct tasklet_struct *tasklet;
 
-        tasklet = this_cpu_ptr(&info->cache->percpu->flush_tasklet);
+        tasklet = &this_cpu_ptr(info->cache->percpu)->flush_tasklet;
         tasklet->data = (unsigned long)info;
         tasklet_schedule(tasklet);
 }
diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c
index 5fb8d7e47294..b65441da74ab 100644
--- a/net/core/rtnetlink.c
+++ b/net/core/rtnetlink.c
@@ -496,8 +496,10 @@ static int rtnl_link_fill(struct sk_buff *skb, const struct net_device *dev)
         }
         if (ops->fill_info) {
                 data = nla_nest_start(skb, IFLA_INFO_DATA);
-                if (data == NULL)
+                if (data == NULL) {
+                        err = -EMSGSIZE;
                         goto err_cancel_link;
+                }
                 err = ops->fill_info(skb, dev);
                 if (err < 0)
                         goto err_cancel_data;
diff --git a/net/ipv4/devinet.c b/net/ipv4/devinet.c
index f678507bc829..96083b7a436b 100644
--- a/net/ipv4/devinet.c
+++ b/net/ipv4/devinet.c
@@ -802,8 +802,10 @@ static int inet_rtm_newaddr(struct sk_buff *skb, struct nlmsghdr *nlh, void *arg
                 if (nlh->nlmsg_flags & NLM_F_EXCL ||
                     !(nlh->nlmsg_flags & NLM_F_REPLACE))
                         return -EEXIST;
-
-                set_ifa_lifetime(ifa_existing, valid_lft, prefered_lft);
+                ifa = ifa_existing;
+                set_ifa_lifetime(ifa, valid_lft, prefered_lft);
+                rtmsg_ifa(RTM_NEWADDR, ifa, nlh, NETLINK_CB(skb).portid);
+                blocking_notifier_call_chain(&inetaddr_chain, NETDEV_UP, ifa);
         }
         return 0;
 }
diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c
index 26512250e095..a459c4f5b769 100644
--- a/net/ipv6/addrconf.c
+++ b/net/ipv6/addrconf.c
@@ -2529,6 +2529,9 @@ static void sit_add_v4_addrs(struct inet6_dev *idev)
 static void init_loopback(struct net_device *dev)
 {
         struct inet6_dev  *idev;
+        struct net_device *sp_dev;
+        struct inet6_ifaddr *sp_ifa;
+        struct rt6_info *sp_rt;
 
         /* ::1 */
 
@@ -2540,6 +2543,30 @@ static void init_loopback(struct net_device *dev)
         }
 
         add_addr(idev, &in6addr_loopback, 128, IFA_HOST);
+
+        /* Add routes to other interface's IPv6 addresses */
+        for_each_netdev(dev_net(dev), sp_dev) {
+                if (!strcmp(sp_dev->name, dev->name))
+                        continue;
+
+                idev = __in6_dev_get(sp_dev);
+                if (!idev)
+                        continue;
+
+                read_lock_bh(&idev->lock);
+                list_for_each_entry(sp_ifa, &idev->addr_list, if_list) {
+
+                        if (sp_ifa->flags & (IFA_F_DADFAILED | IFA_F_TENTATIVE))
+                                continue;
+
+                        sp_rt = addrconf_dst_alloc(idev, &sp_ifa->addr, 0);
+
+                        /* Failure cases are ignored */
+                        if (!IS_ERR(sp_rt))
+                                ip6_ins_rt(sp_rt);
+                }
+                read_unlock_bh(&idev->lock);
+        }
 }
 
 static void addrconf_add_linklocal(struct inet6_dev *idev, const struct in6_addr *addr)
diff --git a/net/ipv6/ip6_input.c b/net/ipv6/ip6_input.c
index e33fe0ab2568..2bab2aa59745 100644
--- a/net/ipv6/ip6_input.c
+++ b/net/ipv6/ip6_input.c
@@ -118,6 +118,18 @@ int ipv6_rcv(struct sk_buff *skb, struct net_device *dev, struct packet_type *pt
             ipv6_addr_loopback(&hdr->daddr))
                 goto err;
 
+        /* RFC4291 Errata ID: 3480
+         * Interface-Local scope spans only a single interface on a
+         * node and is useful only for loopback transmission of
+         * multicast.  Packets with interface-local scope received
+         * from another node must be discarded.
+         */
+        if (!(skb->pkt_type == PACKET_LOOPBACK ||
+              dev->flags & IFF_LOOPBACK) &&
+            ipv6_addr_is_multicast(&hdr->daddr) &&
+            IPV6_ADDR_MC_SCOPE(&hdr->daddr) == 1)
+                goto err;
+
         /* RFC4291 2.7
          * Nodes must not originate a packet to a multicast address whose scope
          * field contains the reserved value 0; if such a packet is received, it
diff --git a/net/ipv6/netfilter/ip6t_NPT.c b/net/ipv6/netfilter/ip6t_NPT.c
index 33608c610276..cb631143721c 100644
--- a/net/ipv6/netfilter/ip6t_NPT.c
+++ b/net/ipv6/netfilter/ip6t_NPT.c
@@ -57,7 +57,7 @@ static bool ip6t_npt_map_pfx(const struct ip6t_npt_tginfo *npt,
                 if (pfx_len - i >= 32)
                         mask = 0;
                 else
-                        mask = htonl(~((1 << (pfx_len - i)) - 1));
+                        mask = htonl((1 << (i - pfx_len + 32)) - 1);
 
                 idx = i / 32;
                 addr->s6_addr32[idx] &= mask;
diff --git a/net/key/af_key.c b/net/key/af_key.c
index 8555f331ea60..5b1e5af25713 100644
--- a/net/key/af_key.c
+++ b/net/key/af_key.c
@@ -2693,6 +2693,7 @@ static int key_notify_policy_flush(const struct km_event *c)
         hdr->sadb_msg_pid = c->portid;
         hdr->sadb_msg_version = PF_KEY_V2;
         hdr->sadb_msg_errno = (uint8_t) 0;
+        hdr->sadb_msg_satype = SADB_SATYPE_UNSPEC;
         hdr->sadb_msg_len = (sizeof(struct sadb_msg) / sizeof(uint64_t));
         pfkey_broadcast(skb_out, GFP_ATOMIC, BROADCAST_ALL, NULL, c->net);
         return 0;
diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c
index fb306814576a..a6893602f87a 100644
--- a/net/mac80211/cfg.c
+++ b/net/mac80211/cfg.c
@@ -2582,7 +2582,7 @@ static int ieee80211_cancel_roc(struct ieee80211_local *local,
                         list_del(&dep->list);
                         mutex_unlock(&local->mtx);
 
-                        ieee80211_roc_notify_destroy(dep);
+                        ieee80211_roc_notify_destroy(dep, true);
                         return 0;
                 }
 
@@ -2622,7 +2622,7 @@ static int ieee80211_cancel_roc(struct ieee80211_local *local,
                         ieee80211_start_next_roc(local);
                 mutex_unlock(&local->mtx);
 
-                ieee80211_roc_notify_destroy(found);
+                ieee80211_roc_notify_destroy(found, true);
         } else {
                 /* work may be pending so use it all the time */
                 found->abort = true;
@@ -2632,6 +2632,8 @@ static int ieee80211_cancel_roc(struct ieee80211_local *local,
 
                 /* work will clean up etc */
                 flush_delayed_work(&found->work);
+                WARN_ON(!found->to_be_freed);
+                kfree(found);
         }
 
         return 0;
diff --git a/net/mac80211/chan.c b/net/mac80211/chan.c
index 78c0d90dd641..931be419ab5a 100644
--- a/net/mac80211/chan.c
+++ b/net/mac80211/chan.c
@@ -63,6 +63,7 @@ ieee80211_new_chanctx(struct ieee80211_local *local,
                       enum ieee80211_chanctx_mode mode)
 {
         struct ieee80211_chanctx *ctx;
+        u32 changed;
         int err;
 
         lockdep_assert_held(&local->chanctx_mtx);
@@ -76,6 +77,13 @@ ieee80211_new_chanctx(struct ieee80211_local *local,
         ctx->conf.rx_chains_dynamic = 1;
         ctx->mode = mode;
 
+        /* acquire mutex to prevent idle from changing */
+        mutex_lock(&local->mtx);
+        /* turn idle off *before* setting channel -- some drivers need that */
+        changed = ieee80211_idle_off(local);
+        if (changed)
+                ieee80211_hw_config(local, changed);
+
         if (!local->use_chanctx) {
                 local->_oper_channel_type =
                         cfg80211_get_chandef_type(chandef);
@@ -85,14 +93,17 @@ ieee80211_new_chanctx(struct ieee80211_local *local,
                 err = drv_add_chanctx(local, ctx);
                 if (err) {
                         kfree(ctx);
-                        return ERR_PTR(err);
+                        ctx = ERR_PTR(err);
+
+                        ieee80211_recalc_idle(local);
+                        goto out;
                 }
         }
 
+        /* and keep the mutex held until the new chanctx is on the list */
         list_add_rcu(&ctx->list, &local->chanctx_list);
 
-        mutex_lock(&local->mtx);
-        ieee80211_recalc_idle(local);
+ out:
         mutex_unlock(&local->mtx);
 
         return ctx;
diff --git a/net/mac80211/ieee80211_i.h b/net/mac80211/ieee80211_i.h
index 388580a1bada..5672533a0832 100644
--- a/net/mac80211/ieee80211_i.h
+++ b/net/mac80211/ieee80211_i.h
@@ -309,6 +309,7 @@ struct ieee80211_roc_work {
         struct ieee80211_channel *chan;
 
         bool started, abort, hw_begun, notified;
+        bool to_be_freed;
 
         unsigned long hw_start_time;
 
@@ -1347,7 +1348,7 @@ void ieee80211_offchannel_return(struct ieee80211_local *local);
 void ieee80211_roc_setup(struct ieee80211_local *local);
 void ieee80211_start_next_roc(struct ieee80211_local *local);
 void ieee80211_roc_purge(struct ieee80211_sub_if_data *sdata);
-void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc);
+void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc, bool free);
 void ieee80211_sw_roc_work(struct work_struct *work);
 void ieee80211_handle_roc_started(struct ieee80211_roc_work *roc);
 
@@ -1361,6 +1362,7 @@ int ieee80211_if_change_type(struct ieee80211_sub_if_data *sdata,
                              enum nl80211_iftype type);
 void ieee80211_if_remove(struct ieee80211_sub_if_data *sdata);
 void ieee80211_remove_interfaces(struct ieee80211_local *local);
+u32 ieee80211_idle_off(struct ieee80211_local *local);
 void ieee80211_recalc_idle(struct ieee80211_local *local);
 void ieee80211_adjust_monitor_flags(struct ieee80211_sub_if_data *sdata,
                                     const int offset);
diff --git a/net/mac80211/iface.c b/net/mac80211/iface.c
index baaa8608e52d..58150f877ec3 100644
--- a/net/mac80211/iface.c
+++ b/net/mac80211/iface.c
@@ -78,7 +78,7 @@ void ieee80211_recalc_txpower(struct ieee80211_sub_if_data *sdata)
                 ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_TXPOWER);
 }
 
-static u32 ieee80211_idle_off(struct ieee80211_local *local)
+u32 ieee80211_idle_off(struct ieee80211_local *local)
 {
         if (!(local->hw.conf.flags & IEEE80211_CONF_IDLE))
                 return 0;
@@ -349,21 +349,19 @@ static void ieee80211_set_default_queues(struct ieee80211_sub_if_data *sdata)
 static int ieee80211_add_virtual_monitor(struct ieee80211_local *local)
 {
         struct ieee80211_sub_if_data *sdata;
-        int ret = 0;
+        int ret;
 
         if (!(local->hw.flags & IEEE80211_HW_WANT_MONITOR_VIF))
                 return 0;
 
-        mutex_lock(&local->iflist_mtx);
+        ASSERT_RTNL();
 
         if (local->monitor_sdata)
-                goto out_unlock;
+                return 0;
 
         sdata = kzalloc(sizeof(*sdata) + local->hw.vif_data_size, GFP_KERNEL);
-        if (!sdata) {
-                ret = -ENOMEM;
-                goto out_unlock;
-        }
+        if (!sdata)
+                return -ENOMEM;
 
         /* set up data */
         sdata->local = local;
@@ -377,13 +375,13 @@ static int ieee80211_add_virtual_monitor(struct ieee80211_local *local)
         if (WARN_ON(ret)) {
                 /* ok .. stupid driver, it asked for this! */
                 kfree(sdata);
-                goto out_unlock;
+                return ret;
         }
 
         ret = ieee80211_check_queues(sdata);
         if (ret) {
                 kfree(sdata);
-                goto out_unlock;
+                return ret;
         }
 
         ret = ieee80211_vif_use_channel(sdata, &local->monitor_chandef,
@@ -391,13 +389,14 @@ static int ieee80211_add_virtual_monitor(struct ieee80211_local *local)
         if (ret) {
                 drv_remove_interface(local, sdata);
                 kfree(sdata);
-                goto out_unlock;
+                return ret;
         }
 
+        mutex_lock(&local->iflist_mtx);
         rcu_assign_pointer(local->monitor_sdata, sdata);
- out_unlock:
         mutex_unlock(&local->iflist_mtx);
-        return ret;
+
+        return 0;
 }
 
 static void ieee80211_del_virtual_monitor(struct ieee80211_local *local)
@@ -407,14 +406,20 @@ static void ieee80211_del_virtual_monitor(struct ieee80211_local *local)
         if (!(local->hw.flags & IEEE80211_HW_WANT_MONITOR_VIF))
                 return;
 
+        ASSERT_RTNL();
+
         mutex_lock(&local->iflist_mtx);
 
         sdata = rcu_dereference_protected(local->monitor_sdata,
                                           lockdep_is_held(&local->iflist_mtx));
-        if (!sdata)
-                goto out_unlock;
+        if (!sdata) {
+                mutex_unlock(&local->iflist_mtx);
+                return;
+        }
 
         rcu_assign_pointer(local->monitor_sdata, NULL);
+        mutex_unlock(&local->iflist_mtx);
+
         synchronize_net();
 
         ieee80211_vif_release_channel(sdata);
@@ -422,8 +427,6 @@ static void ieee80211_del_virtual_monitor(struct ieee80211_local *local)
         drv_remove_interface(local, sdata);
 
         kfree(sdata);
- out_unlock:
-        mutex_unlock(&local->iflist_mtx);
 }
 
 /*
diff --git a/net/mac80211/mesh.c b/net/mac80211/mesh.c
index 29ce2aa87e7b..4749b3858695 100644
--- a/net/mac80211/mesh.c
+++ b/net/mac80211/mesh.c
@@ -1060,7 +1060,8 @@ void ieee80211_mesh_notify_scan_completed(struct ieee80211_local *local)
 
         rcu_read_lock();
         list_for_each_entry_rcu(sdata, &local->interfaces, list)
-                if (ieee80211_vif_is_mesh(&sdata->vif))
+                if (ieee80211_vif_is_mesh(&sdata->vif) &&
+                    ieee80211_sdata_running(sdata))
                         ieee80211_queue_work(&local->hw, &sdata->work);
         rcu_read_unlock();
 }
diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c
index 141577412d84..82cc30318a86 100644
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
@@ -3608,8 +3608,10 @@ void ieee80211_mlme_notify_scan_completed(struct ieee80211_local *local)
 
         /* Restart STA timers */
         rcu_read_lock();
-        list_for_each_entry_rcu(sdata, &local->interfaces, list)
-                ieee80211_restart_sta_timer(sdata);
+        list_for_each_entry_rcu(sdata, &local->interfaces, list) {
+                if (ieee80211_sdata_running(sdata))
+                        ieee80211_restart_sta_timer(sdata);
+        }
         rcu_read_unlock();
 }
 
diff --git a/net/mac80211/offchannel.c b/net/mac80211/offchannel.c
index cc79b4a2e821..430bd254e496 100644
--- a/net/mac80211/offchannel.c
+++ b/net/mac80211/offchannel.c
@@ -297,10 +297,13 @@ void ieee80211_start_next_roc(struct ieee80211_local *local)
         }
 }
 
-void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc)
+void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc, bool free)
 {
         struct ieee80211_roc_work *dep, *tmp;
 
+        if (WARN_ON(roc->to_be_freed))
+                return;
+
         /* was never transmitted */
         if (roc->frame) {
                 cfg80211_mgmt_tx_status(&roc->sdata->wdev,
@@ -316,9 +319,12 @@ void ieee80211_roc_notify_destroy(struct ieee80211_roc_work *roc)
                                                    GFP_KERNEL);
 
         list_for_each_entry_safe(dep, tmp, &roc->dependents, list)
-                ieee80211_roc_notify_destroy(dep);
+                ieee80211_roc_notify_destroy(dep, true);
 
-        kfree(roc);
+        if (free)
+                kfree(roc);
+        else
+                roc->to_be_freed = true;
 }
 
 void ieee80211_sw_roc_work(struct work_struct *work)
@@ -331,6 +337,9 @@ void ieee80211_sw_roc_work(struct work_struct *work)
 
         mutex_lock(&local->mtx);
 
+        if (roc->to_be_freed)
+                goto out_unlock;
+
         if (roc->abort)
                 goto finish;
 
@@ -370,7 +379,7 @@ void ieee80211_sw_roc_work(struct work_struct *work)
  finish:
                 list_del(&roc->list);
                 started = roc->started;
-                ieee80211_roc_notify_destroy(roc);
+                ieee80211_roc_notify_destroy(roc, !roc->abort);
 
                 if (started) {
                         drv_flush(local, false);
@@ -410,7 +419,7 @@ static void ieee80211_hw_roc_done(struct work_struct *work)
 
         list_del(&roc->list);
 
-        ieee80211_roc_notify_destroy(roc);
+        ieee80211_roc_notify_destroy(roc, true);
 
         /* if there's another roc, start it now */
         ieee80211_start_next_roc(local);
@@ -460,12 +469,14 @@ void ieee80211_roc_purge(struct ieee80211_sub_if_data *sdata)
         list_for_each_entry_safe(roc, tmp, &tmp_list, list) {
                 if (local->ops->remain_on_channel) {
                         list_del(&roc->list);
-                        ieee80211_roc_notify_destroy(roc);
+                        ieee80211_roc_notify_destroy(roc, true);
                 } else {
                         ieee80211_queue_delayed_work(&local->hw, &roc->work, 0);
 
                         /* work will clean up etc */
                         flush_delayed_work(&roc->work);
+                        WARN_ON(!roc->to_be_freed);
+                        kfree(roc);
                 }
         }
 
diff --git a/net/mac80211/rx.c b/net/mac80211/rx.c
index bb73ed2d20b9..c6844ad080be 100644
--- a/net/mac80211/rx.c
+++ b/net/mac80211/rx.c
@@ -2675,7 +2675,19 @@ ieee80211_rx_h_action_return(struct ieee80211_rx_data *rx)
 
                 memset(nskb->cb, 0, sizeof(nskb->cb));
 
-                ieee80211_tx_skb(rx->sdata, nskb);
+                if (rx->sdata->vif.type == NL80211_IFTYPE_P2P_DEVICE) {
+                        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(nskb);
+
+                        info->flags = IEEE80211_TX_CTL_TX_OFFCHAN |
+                                      IEEE80211_TX_INTFL_OFFCHAN_TX_OK |
+                                      IEEE80211_TX_CTL_NO_CCK_RATE;
+                        if (local->hw.flags & IEEE80211_HW_QUEUE_CONTROL)
+                                info->hw_queue =
+                                        local->hw.offchannel_tx_hw_queue;
+                }
+
+                __ieee80211_tx_skb_tid_band(rx->sdata, nskb, 7,
+                                            status->band);
         }
         dev_kfree_skb(rx->skb);
         return RX_QUEUED;
diff --git a/net/mac80211/sta_info.c b/net/mac80211/sta_info.c
index a79ce820cb50..238a0cca320e 100644
--- a/net/mac80211/sta_info.c
+++ b/net/mac80211/sta_info.c
@@ -766,6 +766,7 @@ int __must_check __sta_info_destroy(struct sta_info *sta)
         struct ieee80211_local *local;
         struct ieee80211_sub_if_data *sdata;
         int ret, i;
+        bool have_key = false;
 
         might_sleep();
 
@@ -793,12 +794,19 @@ int __must_check __sta_info_destroy(struct sta_info *sta)
         list_del_rcu(&sta->list);
 
         mutex_lock(&local->key_mtx);
-        for (i = 0; i < NUM_DEFAULT_KEYS; i++)
+        for (i = 0; i < NUM_DEFAULT_KEYS; i++) {
                 __ieee80211_key_free(key_mtx_dereference(local, sta->gtk[i]));
-        if (sta->ptk)
+                have_key = true;
+        }
+        if (sta->ptk) {
                 __ieee80211_key_free(key_mtx_dereference(local, sta->ptk));
+                have_key = true;
+        }
         mutex_unlock(&local->key_mtx);
 
+        if (!have_key)
+                synchronize_net();
+
         sta->dead = true;
 
         local->num_sta--;
diff --git a/net/netfilter/nf_conntrack_standalone.c b/net/netfilter/nf_conntrack_standalone.c
index 6bcce401fd1c..fedee3943661 100644
--- a/net/netfilter/nf_conntrack_standalone.c
+++ b/net/netfilter/nf_conntrack_standalone.c
@@ -568,6 +568,7 @@ static int __init nf_conntrack_standalone_init(void)
                 register_net_sysctl(&init_net, "net", nf_ct_netfilter_table);
         if (!nf_ct_netfilter_header) {
                 pr_err("nf_conntrack: can't register to sysctl.\n");
+                ret = -ENOMEM;
                 goto out_sysctl;
         }
 #endif
diff --git a/net/netfilter/nfnetlink_acct.c b/net/netfilter/nfnetlink_acct.c
index 589d686f0b4c..dc3fd5d44464 100644
--- a/net/netfilter/nfnetlink_acct.c
+++ b/net/netfilter/nfnetlink_acct.c
@@ -49,6 +49,8 @@ nfnl_acct_new(struct sock *nfnl, struct sk_buff *skb,
                 return -EINVAL;
 
         acct_name = nla_data(tb[NFACCT_NAME]);
+        if (strlen(acct_name) == 0)
+                return -EINVAL;
 
         list_for_each_entry(nfacct, &nfnl_acct_list, head) {
                 if (strncmp(nfacct->name, acct_name, NFACCT_NAME_MAX) != 0)
diff --git a/net/netfilter/nfnetlink_queue_core.c b/net/netfilter/nfnetlink_queue_core.c
index 1cb48540f86a..42680b2baa11 100644
--- a/net/netfilter/nfnetlink_queue_core.c
+++ b/net/netfilter/nfnetlink_queue_core.c
@@ -1062,8 +1062,10 @@ static int __init nfnetlink_queue_init(void)
 
 #ifdef CONFIG_PROC_FS
         if (!proc_create("nfnetlink_queue", 0440,
-                         proc_net_netfilter, &nfqnl_file_ops))
+                         proc_net_netfilter, &nfqnl_file_ops)) {
+                status = -ENOMEM;
                 goto cleanup_subsys;
+        }
 #endif
 
         register_netdevice_notifier(&nfqnl_dev_notifier);
diff --git a/net/nfc/llcp/llcp.c b/net/nfc/llcp/llcp.c
index b530afadd76c..ee25f25f0cd6 100644
--- a/net/nfc/llcp/llcp.c
+++ b/net/nfc/llcp/llcp.c
@@ -107,8 +107,6 @@ static void nfc_llcp_socket_release(struct nfc_llcp_local *local, bool listen,
                                 accept_sk->sk_state_change(sk);
 
                                 bh_unlock_sock(accept_sk);
-
-                                sock_orphan(accept_sk);
                         }
 
                         if (listen == true) {
@@ -134,8 +132,6 @@ static void nfc_llcp_socket_release(struct nfc_llcp_local *local, bool listen,
 
                 bh_unlock_sock(sk);
 
-                sock_orphan(sk);
-
                 sk_del_node_init(sk);
         }
 
@@ -164,8 +160,6 @@ static void nfc_llcp_socket_release(struct nfc_llcp_local *local, bool listen,
 
                 bh_unlock_sock(sk);
 
-                sock_orphan(sk);
-
                 sk_del_node_init(sk);
         }
 
@@ -827,7 +821,6 @@ static void nfc_llcp_recv_ui(struct nfc_llcp_local *local,
                 skb_get(skb);
         } else {
                 pr_err("Receive queue is full\n");
-                kfree_skb(skb);
         }
 
         nfc_llcp_sock_put(llcp_sock);
@@ -1028,7 +1021,6 @@ static void nfc_llcp_recv_hdlc(struct nfc_llcp_local *local,
                         skb_get(skb);
                 } else {
                         pr_err("Receive queue is full\n");
-                        kfree_skb(skb);
                 }
         }
 
diff --git a/net/nfc/llcp/sock.c b/net/nfc/llcp/sock.c
index 5c7cdf3f2a83..8f025746f337 100644
--- a/net/nfc/llcp/sock.c
+++ b/net/nfc/llcp/sock.c
@@ -270,7 +270,9 @@ struct sock *nfc_llcp_accept_dequeue(struct sock *parent,
                 }
 
                 if (sk->sk_state == LLCP_CONNECTED || !newsock) {
-                        nfc_llcp_accept_unlink(sk);
+                        list_del_init(&lsk->accept_queue);
+                        sock_put(sk);
+
                         if (newsock)
                                 sock_graft(sk, newsock);
 
@@ -464,8 +466,6 @@ static int llcp_sock_release(struct socket *sock)
                         nfc_llcp_accept_unlink(accept_sk);
 
                         release_sock(accept_sk);
-
-                        sock_orphan(accept_sk);
                 }
         }
 
diff --git a/net/sched/sch_cbq.c b/net/sched/sch_cbq.c
index 13aa47aa2ffb..1bc210ffcba2 100644
--- a/net/sched/sch_cbq.c
+++ b/net/sched/sch_cbq.c
@@ -962,8 +962,11 @@ cbq_dequeue(struct Qdisc *sch)
                 cbq_update(q);
                 if ((incr -= incr2) < 0)
                         incr = 0;
+                q->now += incr;
+        } else {
+                if (now > q->now)
+                        q->now = now;
         }
-        q->now += incr;
         q->now_rt = now;
 
         for (;;) {
diff --git a/net/sched/sch_fq_codel.c b/net/sched/sch_fq_codel.c
index 4e606fcb2534..55786283a3df 100644
--- a/net/sched/sch_fq_codel.c
+++ b/net/sched/sch_fq_codel.c
@@ -195,7 +195,7 @@ static int fq_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch)
                 flow->deficit = q->quantum;
                 flow->dropped = 0;
         }
-        if (++sch->q.qlen < sch->limit)
+        if (++sch->q.qlen <= sch->limit)
                 return NET_XMIT_SUCCESS;
 
         q->drop_overlimit++;
diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c
index ffad48109a22..eac7e0ee23c1 100644
--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
@@ -904,7 +904,7 @@ void psched_ratecfg_precompute(struct psched_ratecfg *r, u32 rate)
         u64 mult;
         int shift;
 
-        r->rate_bps = rate << 3;
+        r->rate_bps = (u64)rate << 3;
         r->shift = 0;
         r->mult = 1;
         /*
diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c
index 971282b6f6a3..2db702d82e7d 100644
--- a/net/unix/af_unix.c
+++ b/net/unix/af_unix.c
@@ -1412,8 +1412,8 @@ static void maybe_add_creds(struct sk_buff *skb, const struct socket *sock,
         if (UNIXCB(skb).cred)
                 return;
         if (test_bit(SOCK_PASSCRED, &sock->flags) ||
-            (other->sk_socket &&
-            test_bit(SOCK_PASSCRED, &other->sk_socket->flags))) {
+            !other->sk_socket ||
+            test_bit(SOCK_PASSCRED, &other->sk_socket->flags)) {
                 UNIXCB(skb).pid  = get_pid(task_tgid(current));
                 UNIXCB(skb).cred = get_current_cred();
         }
@@ -1993,7 +1993,7 @@ again:
                         if ((UNIXCB(skb).pid  != siocb->scm->pid) ||
                             (UNIXCB(skb).cred != siocb->scm->cred))
                                 break;
-                } else {
+                } else if (test_bit(SOCK_PASSCRED, &sock->flags)) {
                         /* Copy credentials */
                         scm_set_cred(siocb->scm, UNIXCB(skb).pid, UNIXCB(skb).cred);
                         check_creds = 1;
diff --git a/net/vmw_vsock/af_vsock.c b/net/vmw_vsock/af_vsock.c
index ca511c4f388a..d8079daf1bde 100644
--- a/net/vmw_vsock/af_vsock.c
+++ b/net/vmw_vsock/af_vsock.c
@@ -207,7 +207,7 @@ static struct sock *__vsock_find_bound_socket(struct sockaddr_vm *addr)
         struct vsock_sock *vsk;
 
         list_for_each_entry(vsk, vsock_bound_sockets(addr), bound_table)
-                if (vsock_addr_equals_addr_any(addr, &vsk->local_addr))
+                if (addr->svm_port == vsk->local_addr.svm_port)
                         return sk_vsock(vsk);
 
         return NULL;
@@ -220,8 +220,8 @@ static struct sock *__vsock_find_connected_socket(struct sockaddr_vm *src,
 
         list_for_each_entry(vsk, vsock_connected_sockets(src, dst),
                             connected_table) {
-                if (vsock_addr_equals_addr(src, &vsk->remote_addr)
-                    && vsock_addr_equals_addr(dst, &vsk->local_addr)) {
+                if (vsock_addr_equals_addr(src, &vsk->remote_addr) &&
+                    dst->svm_port == vsk->local_addr.svm_port) {
                         return sk_vsock(vsk);
                 }
         }
diff --git a/net/vmw_vsock/vmci_transport.c b/net/vmw_vsock/vmci_transport.c
index a70ace83a153..1f6508e249ae 100644
--- a/net/vmw_vsock/vmci_transport.c
+++ b/net/vmw_vsock/vmci_transport.c
@@ -464,19 +464,16 @@ static struct sock *vmci_transport_get_pending(
         struct vsock_sock *vlistener;
         struct vsock_sock *vpending;
         struct sock *pending;
+        struct sockaddr_vm src;
+
+        vsock_addr_init(&src, pkt->dg.src.context, pkt->src_port);
 
         vlistener = vsock_sk(listener);
 
         list_for_each_entry(vpending, &vlistener->pending_links,
                             pending_links) {
-                struct sockaddr_vm src;
-                struct sockaddr_vm dst;
-
-                vsock_addr_init(&src, pkt->dg.src.context, pkt->src_port);
-                vsock_addr_init(&dst, pkt->dg.dst.context, pkt->dst_port);
-
                 if (vsock_addr_equals_addr(&src, &vpending->remote_addr) &&
-                    vsock_addr_equals_addr(&dst, &vpending->local_addr)) {
+                    pkt->dst_port == vpending->local_addr.svm_port) {
                         pending = sk_vsock(vpending);
                         sock_hold(pending);
                         goto found;
@@ -739,10 +736,15 @@ static int vmci_transport_recv_stream_cb(void *data, struct vmci_datagram *dg)
          */
         bh_lock_sock(sk);
 
-        if (!sock_owned_by_user(sk) && sk->sk_state == SS_CONNECTED)
-                vmci_trans(vsk)->notify_ops->handle_notify_pkt(
-                                sk, pkt, true, &dst, &src,
-                                &bh_process_pkt);
+        if (!sock_owned_by_user(sk)) {
+                /* The local context ID may be out of date, update it. */
+                vsk->local_addr.svm_cid = dst.svm_cid;
+
+                if (sk->sk_state == SS_CONNECTED)
+                        vmci_trans(vsk)->notify_ops->handle_notify_pkt(
+                                        sk, pkt, true, &dst, &src,
+                                        &bh_process_pkt);
+        }
 
         bh_unlock_sock(sk);
 
@@ -902,6 +904,9 @@ static void vmci_transport_recv_pkt_work(struct work_struct *work)
 
         lock_sock(sk);
 
+        /* The local context ID may be out of date. */
+        vsock_sk(sk)->local_addr.svm_cid = pkt->dg.dst.context;
+
         switch (sk->sk_state) {
         case SS_LISTEN:
                 vmci_transport_recv_listen(sk, pkt);
@@ -958,6 +963,10 @@ static int vmci_transport_recv_listen(struct sock *sk,
         pending = vmci_transport_get_pending(sk, pkt);
         if (pending) {
                 lock_sock(pending);
+
+                /* The local context ID may be out of date. */
+                vsock_sk(pending)->local_addr.svm_cid = pkt->dg.dst.context;
+
                 switch (pending->sk_state) {
                 case SS_CONNECTING:
                         err = vmci_transport_recv_connecting_server(sk,
diff --git a/net/vmw_vsock/vsock_addr.c b/net/vmw_vsock/vsock_addr.c
index b7df1aea7c59..ec2611b4ea0e 100644
--- a/net/vmw_vsock/vsock_addr.c
+++ b/net/vmw_vsock/vsock_addr.c
@@ -64,16 +64,6 @@ bool vsock_addr_equals_addr(const struct sockaddr_vm *addr,
 }
 EXPORT_SYMBOL_GPL(vsock_addr_equals_addr);
 
-bool vsock_addr_equals_addr_any(const struct sockaddr_vm *addr,
-                                const struct sockaddr_vm *other)
-{
-        return (addr->svm_cid == VMADDR_CID_ANY ||
-                other->svm_cid == VMADDR_CID_ANY ||
-                addr->svm_cid == other->svm_cid) &&
-               addr->svm_port == other->svm_port;
-}
-EXPORT_SYMBOL_GPL(vsock_addr_equals_addr_any);
-
 int vsock_addr_cast(const struct sockaddr *addr,
                     size_t len, struct sockaddr_vm **out_addr)
 {
diff --git a/net/vmw_vsock/vsock_addr.h b/net/vmw_vsock/vsock_addr.h
index cdfbcefdf843..9ccd5316eac0 100644
--- a/net/vmw_vsock/vsock_addr.h
+++ b/net/vmw_vsock/vsock_addr.h
@@ -24,8 +24,6 @@ bool vsock_addr_bound(const struct sockaddr_vm *addr);
 void vsock_addr_unbind(struct sockaddr_vm *addr);
 bool vsock_addr_equals_addr(const struct sockaddr_vm *addr,
                             const struct sockaddr_vm *other);
-bool vsock_addr_equals_addr_any(const struct sockaddr_vm *addr,
-                                const struct sockaddr_vm *other);
 int vsock_addr_cast(const struct sockaddr *addr, size_t len,
                     struct sockaddr_vm **out_addr);
 
diff --git a/net/wireless/core.c b/net/wireless/core.c
index ea4155fe9733..6ddf74f0ae1e 100644
--- a/net/wireless/core.c
+++ b/net/wireless/core.c
@@ -212,6 +212,39 @@ static void cfg80211_rfkill_poll(struct rfkill *rfkill, void *data)
         rdev_rfkill_poll(rdev);
 }
 
+void cfg80211_stop_p2p_device(struct cfg80211_registered_device *rdev,
+                              struct wireless_dev *wdev)
+{
+        lockdep_assert_held(&rdev->devlist_mtx);
+        lockdep_assert_held(&rdev->sched_scan_mtx);
+
+        if (WARN_ON(wdev->iftype != NL80211_IFTYPE_P2P_DEVICE))
+                return;
+
+        if (!wdev->p2p_started)
+                return;
+
+        rdev_stop_p2p_device(rdev, wdev);
+        wdev->p2p_started = false;
+
+        rdev->opencount--;
+
+        if (rdev->scan_req && rdev->scan_req->wdev == wdev) {
+                bool busy = work_busy(&rdev->scan_done_wk);
+
+                /*
+                 * If the work isn't pending or running (in which case it would
+                 * be waiting for the lock we hold) the driver didn't properly
+                 * cancel the scan when the interface was removed. In this case
+                 * warn and leak the scan request object to not crash later.
+                 */
+                WARN_ON(!busy);
+
+                rdev->scan_req->aborted = true;
+                ___cfg80211_scan_done(rdev, !busy);
+        }
+}
+
 static int cfg80211_rfkill_set_block(void *data, bool blocked)
 {
         struct cfg80211_registered_device *rdev = data;
@@ -221,7 +254,8 @@ static int cfg80211_rfkill_set_block(void *data, bool blocked)
                 return 0;
 
         rtnl_lock();
-        mutex_lock(&rdev->devlist_mtx);
+
+        /* read-only iteration need not hold the devlist_mtx */
 
         list_for_each_entry(wdev, &rdev->wdev_list, list) {
                 if (wdev->netdev) {
@@ -231,18 +265,18 @@ static int cfg80211_rfkill_set_block(void *data, bool blocked)
                 /* otherwise, check iftype */
                 switch (wdev->iftype) {
                 case NL80211_IFTYPE_P2P_DEVICE:
-                        if (!wdev->p2p_started)
-                                break;
-                        rdev_stop_p2p_device(rdev, wdev);
-                        wdev->p2p_started = false;
-                        rdev->opencount--;
+                        /* but this requires it */
+                        mutex_lock(&rdev->devlist_mtx);
+                        mutex_lock(&rdev->sched_scan_mtx);
+                        cfg80211_stop_p2p_device(rdev, wdev);
+                        mutex_unlock(&rdev->sched_scan_mtx);
+                        mutex_unlock(&rdev->devlist_mtx);
                         break;
                 default:
                         break;
                 }
         }
 
-        mutex_unlock(&rdev->devlist_mtx);
         rtnl_unlock();
 
         return 0;
@@ -745,17 +779,13 @@ static void wdev_cleanup_work(struct work_struct *work)
         wdev = container_of(work, struct wireless_dev, cleanup_work);
         rdev = wiphy_to_dev(wdev->wiphy);
 
-        cfg80211_lock_rdev(rdev);
+        mutex_lock(&rdev->sched_scan_mtx);
 
         if (WARN_ON(rdev->scan_req && rdev->scan_req->wdev == wdev)) {
                 rdev->scan_req->aborted = true;
                 ___cfg80211_scan_done(rdev, true);
         }
 
-        cfg80211_unlock_rdev(rdev);
-
-        mutex_lock(&rdev->sched_scan_mtx);
-
         if (WARN_ON(rdev->sched_scan_req &&
                     rdev->sched_scan_req->dev == wdev->netdev)) {
                 __cfg80211_stop_sched_scan(rdev, false);
@@ -781,21 +811,19 @@ void cfg80211_unregister_wdev(struct wireless_dev *wdev)
                 return;
 
         mutex_lock(&rdev->devlist_mtx);
+        mutex_lock(&rdev->sched_scan_mtx);
         list_del_rcu(&wdev->list);
         rdev->devlist_generation++;
 
         switch (wdev->iftype) {
         case NL80211_IFTYPE_P2P_DEVICE:
-                if (!wdev->p2p_started)
-                        break;
-                rdev_stop_p2p_device(rdev, wdev);
-                wdev->p2p_started = false;
-                rdev->opencount--;
+                cfg80211_stop_p2p_device(rdev, wdev);
                 break;
         default:
                 WARN_ON_ONCE(1);
                 break;
         }
+        mutex_unlock(&rdev->sched_scan_mtx);
         mutex_unlock(&rdev->devlist_mtx);
 }
 EXPORT_SYMBOL(cfg80211_unregister_wdev);
@@ -936,6 +964,7 @@ static int cfg80211_netdev_notifier_call(struct notifier_block *nb,
                 cfg80211_update_iface_num(rdev, wdev->iftype, 1);
                 cfg80211_lock_rdev(rdev);
                 mutex_lock(&rdev->devlist_mtx);
+                mutex_lock(&rdev->sched_scan_mtx);
                 wdev_lock(wdev);
                 switch (wdev->iftype) {
 #ifdef CONFIG_CFG80211_WEXT
@@ -967,6 +996,7 @@ static int cfg80211_netdev_notifier_call(struct notifier_block *nb,
                         break;
                 }
                 wdev_unlock(wdev);
+                mutex_unlock(&rdev->sched_scan_mtx);
                 rdev->opencount++;
                 mutex_unlock(&rdev->devlist_mtx);
                 cfg80211_unlock_rdev(rdev);
diff --git a/net/wireless/core.h b/net/wireless/core.h
index 3aec0e429d8a..5845c2b37aa8 100644
--- a/net/wireless/core.h
+++ b/net/wireless/core.h
@@ -503,6 +503,9 @@ int cfg80211_validate_beacon_int(struct cfg80211_registered_device *rdev,
 void cfg80211_update_iface_num(struct cfg80211_registered_device *rdev,
                                enum nl80211_iftype iftype, int num);
 
+void cfg80211_stop_p2p_device(struct cfg80211_registered_device *rdev,
+                              struct wireless_dev *wdev);
+
 #define CFG80211_MAX_NUM_DIFFERENT_CHANNELS 10
 
 #ifdef CONFIG_CFG80211_DEVELOPER_WARNINGS
diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index d44ab216c0ec..58e13a8c95f9 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -4702,14 +4702,19 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info)
         if (!rdev->ops->scan)
                 return -EOPNOTSUPP;
 
-        if (rdev->scan_req)
-                return -EBUSY;
+        mutex_lock(&rdev->sched_scan_mtx);
+        if (rdev->scan_req) {
+                err = -EBUSY;
+                goto unlock;
+        }
 
         if (info->attrs[NL80211_ATTR_SCAN_FREQUENCIES]) {
                 n_channels = validate_scan_freqs(
                                 info->attrs[NL80211_ATTR_SCAN_FREQUENCIES]);
-                if (!n_channels)
-                        return -EINVAL;
+                if (!n_channels) {
+                        err = -EINVAL;
+                        goto unlock;
+                }
         } else {
                 enum ieee80211_band band;
                 n_channels = 0;
@@ -4723,23 +4728,29 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info)
                 nla_for_each_nested(attr, info->attrs[NL80211_ATTR_SCAN_SSIDS], tmp)
                         n_ssids++;
 
-        if (n_ssids > wiphy->max_scan_ssids)
-                return -EINVAL;
+        if (n_ssids > wiphy->max_scan_ssids) {
+                err = -EINVAL;
+                goto unlock;
+        }
 
         if (info->attrs[NL80211_ATTR_IE])
                 ie_len = nla_len(info->attrs[NL80211_ATTR_IE]);
         else
                 ie_len = 0;
 
-        if (ie_len > wiphy->max_scan_ie_len)
-                return -EINVAL;
+        if (ie_len > wiphy->max_scan_ie_len) {
+                err = -EINVAL;
+                goto unlock;
+        }
 
         request = kzalloc(sizeof(*request)
                         + sizeof(*request->ssids) * n_ssids
                         + sizeof(*request->channels) * n_channels
                         + ie_len, GFP_KERNEL);
-        if (!request)
-                return -ENOMEM;
+        if (!request) {
+                err = -ENOMEM;
+                goto unlock;
+        }
 
         if (n_ssids)
                 request->ssids = (void *)&request->channels[n_channels];
@@ -4876,6 +4887,8 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info)
                 kfree(request);
         }
 
+ unlock:
+        mutex_unlock(&rdev->sched_scan_mtx);
         return err;
 }
 
@@ -7749,20 +7762,9 @@ static int nl80211_stop_p2p_device(struct sk_buff *skb, struct genl_info *info)
         if (!rdev->ops->stop_p2p_device)
                 return -EOPNOTSUPP;
 
-        if (!wdev->p2p_started)
-                return 0;
-
-        rdev_stop_p2p_device(rdev, wdev);
-        wdev->p2p_started = false;
-
-        mutex_lock(&rdev->devlist_mtx);
-        rdev->opencount--;
-        mutex_unlock(&rdev->devlist_mtx);
-
-        if (WARN_ON(rdev->scan_req && rdev->scan_req->wdev == wdev)) {
-                rdev->scan_req->aborted = true;
-                ___cfg80211_scan_done(rdev, true);
-        }
+        mutex_lock(&rdev->sched_scan_mtx);
+        cfg80211_stop_p2p_device(rdev, wdev);
+        mutex_unlock(&rdev->sched_scan_mtx);
 
         return 0;
 }
@@ -8486,7 +8488,7 @@ static int nl80211_add_scan_req(struct sk_buff *msg,
         struct nlattr *nest;
         int i;
 
-        ASSERT_RDEV_LOCK(rdev);
+        lockdep_assert_held(&rdev->sched_scan_mtx);
 
         if (WARN_ON(!req))
                 return 0;
diff --git a/net/wireless/scan.c b/net/wireless/scan.c
index 674aadca0079..fd99ea495b7e 100644
--- a/net/wireless/scan.c
+++ b/net/wireless/scan.c
@@ -169,7 +169,7 @@ void ___cfg80211_scan_done(struct cfg80211_registered_device *rdev, bool leak)
         union iwreq_data wrqu;
 #endif
 
-        ASSERT_RDEV_LOCK(rdev);
+        lockdep_assert_held(&rdev->sched_scan_mtx);
 
         request = rdev->scan_req;
 
@@ -230,9 +230,9 @@ void __cfg80211_scan_done(struct work_struct *wk)
         rdev = container_of(wk, struct cfg80211_registered_device,
                             scan_done_wk);
 
-        cfg80211_lock_rdev(rdev);
+        mutex_lock(&rdev->sched_scan_mtx);
         ___cfg80211_scan_done(rdev, false);
-        cfg80211_unlock_rdev(rdev);
+        mutex_unlock(&rdev->sched_scan_mtx);
 }
 
 void cfg80211_scan_done(struct cfg80211_scan_request *request, bool aborted)
@@ -698,11 +698,6 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev,
         found = rb_find_bss(dev, tmp, BSS_CMP_REGULAR);
 
         if (found) {
-                found->pub.beacon_interval = tmp->pub.beacon_interval;
-                found->pub.signal = tmp->pub.signal;
-                found->pub.capability = tmp->pub.capability;
-                found->ts = tmp->ts;
-
                 /* Update IEs */
                 if (rcu_access_pointer(tmp->pub.proberesp_ies)) {
                         const struct cfg80211_bss_ies *old;
@@ -723,6 +718,8 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev,
 
                         if (found->pub.hidden_beacon_bss &&
                             !list_empty(&found->hidden_list)) {
+                                const struct cfg80211_bss_ies *f;
+
                                 /*
                                  * The found BSS struct is one of the probe
                                  * response members of a group, but we're
@@ -732,6 +729,10 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev,
                                  * SSID to showing it, which is confusing so
                                  * drop this information.
                                  */
+
+                                f = rcu_access_pointer(tmp->pub.beacon_ies);
+                                kfree_rcu((struct cfg80211_bss_ies *)f,
+                                          rcu_head);
                                 goto drop;
                         }
 
@@ -761,6 +762,11 @@ cfg80211_bss_update(struct cfg80211_registered_device *dev,
                                 kfree_rcu((struct cfg80211_bss_ies *)old,
                                           rcu_head);
                 }
+
+                found->pub.beacon_interval = tmp->pub.beacon_interval;
+                found->pub.signal = tmp->pub.signal;
+                found->pub.capability = tmp->pub.capability;
+                found->ts = tmp->ts;
         } else {
                 struct cfg80211_internal_bss *new;
                 struct cfg80211_internal_bss *hidden;
@@ -1056,6 +1062,7 @@ int cfg80211_wext_siwscan(struct net_device *dev,
         if (IS_ERR(rdev))
                 return PTR_ERR(rdev);
 
+        mutex_lock(&rdev->sched_scan_mtx);
         if (rdev->scan_req) {
                 err = -EBUSY;
                 goto out;
@@ -1162,6 +1169,7 @@ int cfg80211_wext_siwscan(struct net_device *dev,
                 dev_hold(dev);
         }
  out:
+        mutex_unlock(&rdev->sched_scan_mtx);
         kfree(creq);
         cfg80211_unlock_rdev(rdev);
         return err;
diff --git a/net/wireless/sme.c b/net/wireless/sme.c
index f432bd3755b1..09d994d192ff 100644
--- a/net/wireless/sme.c
+++ b/net/wireless/sme.c
@@ -85,6 +85,7 @@ static int cfg80211_conn_scan(struct wireless_dev *wdev)
         ASSERT_RTNL();
         ASSERT_RDEV_LOCK(rdev);
         ASSERT_WDEV_LOCK(wdev);
+        lockdep_assert_held(&rdev->sched_scan_mtx);
 
         if (rdev->scan_req)
                 return -EBUSY;
@@ -320,11 +321,9 @@ void cfg80211_sme_scan_done(struct net_device *dev)
 {
         struct wireless_dev *wdev = dev->ieee80211_ptr;
 
-        mutex_lock(&wiphy_to_dev(wdev->wiphy)->devlist_mtx);
         wdev_lock(wdev);
         __cfg80211_sme_scan_done(dev);
         wdev_unlock(wdev);
-        mutex_unlock(&wiphy_to_dev(wdev->wiphy)->devlist_mtx);
 }
 
 void cfg80211_sme_rx_auth(struct net_device *dev,
@@ -924,9 +923,12 @@ int cfg80211_connect(struct cfg80211_registered_device *rdev,
         int err;
 
         mutex_lock(&rdev->devlist_mtx);
+        /* might request scan - scan_mtx -> wdev_mtx dependency */
+        mutex_lock(&rdev->sched_scan_mtx);
         wdev_lock(dev->ieee80211_ptr);
         err = __cfg80211_connect(rdev, dev, connect, connkeys, NULL);
         wdev_unlock(dev->ieee80211_ptr);
+        mutex_unlock(&rdev->sched_scan_mtx);
         mutex_unlock(&rdev->devlist_mtx);
 
         return err;
diff --git a/net/wireless/trace.h b/net/wireless/trace.h
index b7a531380e19..7586de77a2f8 100644
--- a/net/wireless/trace.h
+++ b/net/wireless/trace.h
@@ -27,7 +27,8 @@
 #define WIPHY_PR_ARG    __entry->wiphy_name
 
 #define WDEV_ENTRY      __field(u32, id)
-#define WDEV_ASSIGN     (__entry->id) = (wdev ? wdev->identifier : 0)
+#define WDEV_ASSIGN     (__entry->id) = (!IS_ERR_OR_NULL(wdev)  \
+                                         ? wdev->identifier : 0)
 #define WDEV_PR_FMT     "wdev(%u)"
 #define WDEV_PR_ARG     (__entry->id)
 
@@ -1778,7 +1779,7 @@ TRACE_EVENT(rdev_set_mac_acl,
         ),
         TP_fast_assign(
                 WIPHY_ASSIGN;
-                WIPHY_ASSIGN;
+                NETDEV_ASSIGN;
                 __entry->acl_policy = params->acl_policy;
         ),
         TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", acl policy: %d",
diff --git a/net/wireless/wext-sme.c b/net/wireless/wext-sme.c
index fb9622f6d99c..e79cb5c0655a 100644
--- a/net/wireless/wext-sme.c
+++ b/net/wireless/wext-sme.c
@@ -89,6 +89,7 @@ int cfg80211_mgd_wext_siwfreq(struct net_device *dev,
 
         cfg80211_lock_rdev(rdev);
         mutex_lock(&rdev->devlist_mtx);
+        mutex_lock(&rdev->sched_scan_mtx);
         wdev_lock(wdev);
 
         if (wdev->sme_state != CFG80211_SME_IDLE) {
@@ -135,6 +136,7 @@ int cfg80211_mgd_wext_siwfreq(struct net_device *dev,
         err = cfg80211_mgd_wext_connect(rdev, wdev);
  out:
         wdev_unlock(wdev);
+        mutex_unlock(&rdev->sched_scan_mtx);
         mutex_unlock(&rdev->devlist_mtx);
         cfg80211_unlock_rdev(rdev);
         return err;
@@ -190,6 +192,7 @@ int cfg80211_mgd_wext_siwessid(struct net_device *dev,
 
         cfg80211_lock_rdev(rdev);
         mutex_lock(&rdev->devlist_mtx);
+        mutex_lock(&rdev->sched_scan_mtx);
         wdev_lock(wdev);
 
         err = 0;
@@ -223,6 +226,7 @@ int cfg80211_mgd_wext_siwessid(struct net_device *dev,
         err = cfg80211_mgd_wext_connect(rdev, wdev);
  out:
         wdev_unlock(wdev);
+        mutex_unlock(&rdev->sched_scan_mtx);
         mutex_unlock(&rdev->devlist_mtx);
         cfg80211_unlock_rdev(rdev);
         return err;
@@ -285,6 +289,7 @@ int cfg80211_mgd_wext_siwap(struct net_device *dev,
 
         cfg80211_lock_rdev(rdev);
         mutex_lock(&rdev->devlist_mtx);
+        mutex_lock(&rdev->sched_scan_mtx);
         wdev_lock(wdev);
 
         if (wdev->sme_state != CFG80211_SME_IDLE) {
@@ -313,6 +318,7 @@ int cfg80211_mgd_wext_siwap(struct net_device *dev,
         err = cfg80211_mgd_wext_connect(rdev, wdev);
  out:
         wdev_unlock(wdev);
+        mutex_unlock(&rdev->sched_scan_mtx);
         mutex_unlock(&rdev->devlist_mtx);
         cfg80211_unlock_rdev(rdev);
         return err;
diff --git a/net/xfrm/xfrm_replay.c b/net/xfrm/xfrm_replay.c
index 35754cc8a9e5..8dafe6d3c6e4 100644
--- a/net/xfrm/xfrm_replay.c
+++ b/net/xfrm/xfrm_replay.c
@@ -334,6 +334,70 @@ static void xfrm_replay_notify_bmp(struct xfrm_state *x, int event)
                 x->xflags &= ~XFRM_TIME_DEFER;
 }
 
+static void xfrm_replay_notify_esn(struct xfrm_state *x, int event)
+{
+        u32 seq_diff, oseq_diff;
+        struct km_event c;
+        struct xfrm_replay_state_esn *replay_esn = x->replay_esn;
+        struct xfrm_replay_state_esn *preplay_esn = x->preplay_esn;
+
+        /* we send notify messages in case
+         *  1. we updated on of the sequence numbers, and the seqno difference
+         *     is at least x->replay_maxdiff, in this case we also update the
+         *     timeout of our timer function
+         *  2. if x->replay_maxage has elapsed since last update,
+         *     and there were changes
+         *
+         *  The state structure must be locked!
+         */
+
+        switch (event) {
+        case XFRM_REPLAY_UPDATE:
+                if (!x->replay_maxdiff)
+                        break;
+
+                if (replay_esn->seq_hi == preplay_esn->seq_hi)
+                        seq_diff = replay_esn->seq - preplay_esn->seq;
+                else
+                        seq_diff = ~preplay_esn->seq + replay_esn->seq + 1;
+
+                if (replay_esn->oseq_hi == preplay_esn->oseq_hi)
+                        oseq_diff = replay_esn->oseq - preplay_esn->oseq;
+                else
+                        oseq_diff = ~preplay_esn->oseq + replay_esn->oseq + 1;
+
+                if (seq_diff < x->replay_maxdiff &&
+                    oseq_diff < x->replay_maxdiff) {
+
+                        if (x->xflags & XFRM_TIME_DEFER)
+                                event = XFRM_REPLAY_TIMEOUT;
+                        else
+                                return;
+                }
+
+                break;
+
+        case XFRM_REPLAY_TIMEOUT:
+                if (memcmp(x->replay_esn, x->preplay_esn,
+                           xfrm_replay_state_esn_len(replay_esn)) == 0) {
+                        x->xflags |= XFRM_TIME_DEFER;
+                        return;
+                }
+
+                break;
+        }
+
+        memcpy(x->preplay_esn, x->replay_esn,
+               xfrm_replay_state_esn_len(replay_esn));
+        c.event = XFRM_MSG_NEWAE;
+        c.data.aevent = event;
+        km_state_notify(x, &c);
+
+        if (x->replay_maxage &&
+            !mod_timer(&x->rtimer, jiffies + x->replay_maxage))
+                x->xflags &= ~XFRM_TIME_DEFER;
+}
+
 static int xfrm_replay_overflow_esn(struct xfrm_state *x, struct sk_buff *skb)
 {
         int err = 0;
@@ -510,7 +574,7 @@ static struct xfrm_replay xfrm_replay_esn = {
         .advance        = xfrm_replay_advance_esn,
         .check          = xfrm_replay_check_esn,
         .recheck        = xfrm_replay_recheck_esn,
-        .notify         = xfrm_replay_notify_bmp,
+        .notify         = xfrm_replay_notify_esn,
         .overflow       = xfrm_replay_overflow_esn,
 };
 
diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c
index ecdf30eb5879..4aba7646dd9c 100644
--- a/sound/pci/hda/hda_codec.c
+++ b/sound/pci/hda/hda_codec.c
@@ -173,7 +173,7 @@ const char *snd_hda_get_jack_type(u32 cfg)
                 "Line Out", "Speaker", "HP Out", "CD",
                 "SPDIF Out", "Digital Out", "Modem Line", "Modem Hand",
                 "Line In", "Aux", "Mic", "Telephony",
-                "SPDIF In", "Digitial In", "Reserved", "Other"
+                "SPDIF In", "Digital In", "Reserved", "Other"
         };
 
         return jack_types[(cfg & AC_DEFCFG_DEVICE)
diff --git a/sound/pci/hda/hda_eld.c b/sound/pci/hda/hda_eld.c
index 7dd846380a50..d0d7ac1e99d2 100644
--- a/sound/pci/hda/hda_eld.c
+++ b/sound/pci/hda/hda_eld.c
@@ -320,7 +320,7 @@ int snd_hdmi_get_eld(struct hda_codec *codec, hda_nid_t nid,
                      unsigned char *buf, int *eld_size)
 {
         int i;
-        int ret;
+        int ret = 0;
         int size;
 
         /*
diff --git a/sound/pci/hda/hda_generic.c b/sound/pci/hda/hda_generic.c
index 43c2ea539561..2dbe767be16b 100644
--- a/sound/pci/hda/hda_generic.c
+++ b/sound/pci/hda/hda_generic.c
@@ -740,7 +740,7 @@ EXPORT_SYMBOL_HDA(snd_hda_activate_path);
 static void path_power_down_sync(struct hda_codec *codec, struct nid_path *path)
 {
         struct hda_gen_spec *spec = codec->spec;
-        bool changed;
+        bool changed = false;
         int i;
 
         if (!spec->power_down_unused || path->active)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 418bfc0eb0a3..bcd40ee488e3 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -134,8 +134,8 @@ MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
  * this may give more power-saving, but will take longer time to
  * wake up.
  */
-static int power_save_controller = -1;
-module_param(power_save_controller, bint, 0644);
+static bool power_save_controller = 1;
+module_param(power_save_controller, bool, 0644);
 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 #endif /* CONFIG_PM */
 
@@ -2931,8 +2931,6 @@ static int azx_runtime_idle(struct device *dev)
         struct snd_card *card = dev_get_drvdata(dev);
         struct azx *chip = card->private_data;
 
-        if (power_save_controller > 0)
-                return 0;
         if (!power_save_controller ||
             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
                 return -EBUSY;
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 78e1827d0a95..de8ac5c07fd0 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -1196,7 +1196,7 @@ static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
 
         _snd_printd(SND_PR_VERBOSE,
                 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
-                codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
+                codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
 
         if (eld->eld_valid) {
                 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 563c24df4d6f..f15c36bde540 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -3440,7 +3440,8 @@ static int alc662_parse_auto_config(struct hda_codec *codec)
         const hda_nid_t *ssids;
 
         if (codec->vendor_id == 0x10ec0272 || codec->vendor_id == 0x10ec0663 ||
-            codec->vendor_id == 0x10ec0665 || codec->vendor_id == 0x10ec0670)
+            codec->vendor_id == 0x10ec0665 || codec->vendor_id == 0x10ec0670 ||
+            codec->vendor_id == 0x10ec0671)
                 ssids = alc663_ssids;
         else
                 ssids = alc662_ssids;
@@ -3894,6 +3895,7 @@ static const struct hda_codec_preset snd_hda_preset_realtek[] = {
         { .id = 0x10ec0665, .name = "ALC665", .patch = patch_alc662 },
         { .id = 0x10ec0668, .name = "ALC668", .patch = patch_alc662 },
         { .id = 0x10ec0670, .name = "ALC670", .patch = patch_alc662 },
+        { .id = 0x10ec0671, .name = "ALC671", .patch = patch_alc662 },
         { .id = 0x10ec0680, .name = "ALC680", .patch = patch_alc680 },
         { .id = 0x10ec0880, .name = "ALC880", .patch = patch_alc880 },
         { .id = 0x10ec0882, .name = "ALC882", .patch = patch_alc882 },
diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
index fc176044994d..fc176044994d 100755..100644
--- a/sound/soc/codecs/max98090.c
+++ b/sound/soc/codecs/max98090.c
diff --git a/sound/soc/codecs/max98090.h b/sound/soc/codecs/max98090.h
index 7e103f249053..7e103f249053 100755..100644
--- a/sound/soc/codecs/max98090.h
+++ b/sound/soc/codecs/max98090.h
diff --git a/sound/soc/codecs/si476x.c b/sound/soc/codecs/si476x.c
index f2d61a187830..566ea3256e2d 100644
--- a/sound/soc/codecs/si476x.c
+++ b/sound/soc/codecs/si476x.c
@@ -159,6 +159,7 @@ static int si476x_codec_hw_params(struct snd_pcm_substream *substream,
         switch (params_format(params)) {
         case SNDRV_PCM_FORMAT_S8:
                 width = SI476X_PCM_FORMAT_S8;
+                break;
         case SNDRV_PCM_FORMAT_S16_LE:
                 width = SI476X_PCM_FORMAT_S16_LE;
                 break;
diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index f3f7e75f8628..9af1bddc4c62 100644
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -828,7 +828,8 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp)
                                                 &buf_list);
                         if (!buf) {
                                 adsp_err(dsp, "Out of memory\n");
-                                return -ENOMEM;
+                                ret = -ENOMEM;
+                                goto out_fw;
                         }
 
                         adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
@@ -865,7 +866,7 @@ out_fw:
         wm_adsp_buf_free(&buf_list);
 out:
         kfree(file);
-        return 0;
+        return ret;
 }
 
 int wm_adsp1_init(struct wm_adsp *adsp)
diff --git a/sound/soc/fsl/imx-ssi.c b/sound/soc/fsl/imx-ssi.c
index 55464a5b0706..810c7eeb7b03 100644
--- a/sound/soc/fsl/imx-ssi.c
+++ b/sound/soc/fsl/imx-ssi.c
@@ -496,6 +496,8 @@ static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
 
         if (imx_ssi->ac97_reset)
                 imx_ssi->ac97_reset(ac97);
+        /* First read sometimes fails, do a dummy read */
+        imx_ssi_ac97_read(ac97, 0);
 }
 
 static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
@@ -504,6 +506,9 @@ static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
 
         if (imx_ssi->ac97_warm_reset)
                 imx_ssi->ac97_warm_reset(ac97);
+
+        /* First read sometimes fails, do a dummy read */
+        imx_ssi_ac97_read(ac97, 0);
 }
 
 struct snd_ac97_bus_ops soc_ac97_ops = {
diff --git a/sound/soc/fsl/pcm030-audio-fabric.c b/sound/soc/fsl/pcm030-audio-fabric.c
index 8e52c1485df3..eb4373840bb6 100644
--- a/sound/soc/fsl/pcm030-audio-fabric.c
+++ b/sound/soc/fsl/pcm030-audio-fabric.c
@@ -51,7 +51,7 @@ static struct snd_soc_card pcm030_card = {
         .num_links = ARRAY_SIZE(pcm030_fabric_dai),
 };
 
-static int __init pcm030_fabric_probe(struct platform_device *op)
+static int pcm030_fabric_probe(struct platform_device *op)
 {
         struct device_node *np = op->dev.of_node;
         struct device_node *platform_np;
diff --git a/sound/soc/sh/dma-sh7760.c b/sound/soc/sh/dma-sh7760.c
index 19eff8fc4fdd..1a8b03e4b41b 100644
--- a/sound/soc/sh/dma-sh7760.c
+++ b/sound/soc/sh/dma-sh7760.c
@@ -342,8 +342,8 @@ static int camelot_pcm_new(struct snd_soc_pcm_runtime *rtd)
         return 0;
 }
 
-static struct snd_soc_platform sh7760_soc_platform = {
-        .pcm_ops        = &camelot_pcm_ops,
+static struct snd_soc_platform_driver sh7760_soc_platform = {
+        .ops            = &camelot_pcm_ops,
         .pcm_new        = camelot_pcm_new,
         .pcm_free       = camelot_pcm_free,
 };
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index b7e84a7cd9ee..507d251916af 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -3140,7 +3140,7 @@ int snd_soc_bytes_put(struct snd_kcontrol *kcontrol,
         if (params->mask) {
                 ret = regmap_read(codec->control_data, params->base, &val);
                 if (ret != 0)
-                        return ret;
+                        goto out;
 
                 val &= params->mask;
 
@@ -3158,13 +3158,15 @@ int snd_soc_bytes_put(struct snd_kcontrol *kcontrol,
                         ((u32 *)data)[0] |= cpu_to_be32(val);
                         break;
                 default:
-                        return -EINVAL;
+                        ret = -EINVAL;
+                        goto out;
                 }
         }
 
         ret = regmap_raw_write(codec->control_data, params->base,
                                data, len);
 
+out:
         kfree(data);
 
         return ret;
@@ -4197,7 +4199,6 @@ int snd_soc_of_parse_audio_routing(struct snd_soc_card *card,
                         dev_err(card->dev,
                                 "ASoC: Property '%s' index %d could not be read: %d\n",
                                 propname, 2 * i, ret);
-                        kfree(routes);
                         return -EINVAL;
                 }
                 ret = of_property_read_string_index(np, propname,
@@ -4206,7 +4207,6 @@ int snd_soc_of_parse_audio_routing(struct snd_soc_card *card,
                         dev_err(card->dev,
                                 "ASoC: Property '%s' index %d could not be read: %d\n",
                                 propname, (2 * i) + 1, ret);
-                        kfree(routes);
                         return -EINVAL;
                 }
         }
diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 1d6a9b3ceb27..d6d9ba2e6916 100644
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -831,6 +831,9 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget,
                 if (path->weak)
                         continue;
 
+                if (path->walking)
+                        return 1;
+
                 if (path->walked)
                         continue;
 
@@ -838,6 +841,7 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget,
 
                 if (path->sink && path->connect) {
                         path->walked = 1;
+                        path->walking = 1;
 
                         /* do we need to add this widget to the list ? */
                         if (list) {
@@ -847,11 +851,14 @@ static int is_connected_output_ep(struct snd_soc_dapm_widget *widget,
                                         dev_err(widget->dapm->dev,
                                                 "ASoC: could not add widget %s\n",
                                                 widget->name);
+                                        path->walking = 0;
                                         return con;
                                 }
                         }
 
                         con += is_connected_output_ep(path->sink, list);
+
+                        path->walking = 0;
                 }
         }
 
@@ -931,6 +938,9 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget,
                 if (path->weak)
                         continue;
 
+                if (path->walking)
+                        return 1;
+
                 if (path->walked)
                         continue;
 
@@ -938,6 +948,7 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget,
 
                 if (path->source && path->connect) {
                         path->walked = 1;
+                        path->walking = 1;
 
                         /* do we need to add this widget to the list ? */
                         if (list) {
@@ -947,11 +958,14 @@ static int is_connected_input_ep(struct snd_soc_dapm_widget *widget,
                                         dev_err(widget->dapm->dev,
                                                 "ASoC: could not add widget %s\n",
                                                 widget->name);
+                                        path->walking = 0;
                                         return con;
                                 }
                         }
 
                         con += is_connected_input_ep(path->source, list);
+
+                        path->walking = 0;
                 }
         }
 
diff --git a/sound/soc/spear/spear_pcm.c b/sound/soc/spear/spear_pcm.c
index 9b76cc5a1148..5e7aebe1e664 100644
--- a/sound/soc/spear/spear_pcm.c
+++ b/sound/soc/spear/spear_pcm.c
@@ -149,9 +149,9 @@ static void spear_pcm_free(struct snd_pcm *pcm)
 
 static u64 spear_pcm_dmamask = DMA_BIT_MASK(32);
 
-static int spear_pcm_new(struct snd_card *card,
-                struct snd_soc_dai *dai, struct snd_pcm *pcm)
+static int spear_pcm_new(struct snd_soc_pcm_runtime *rtd)
 {
+        struct snd_card *card = rtd->card->snd_card;
         int ret;
 
         if (!card->dev->dma_mask)
@@ -159,16 +159,16 @@ static int spear_pcm_new(struct snd_card *card,
         if (!card->dev->coherent_dma_mask)
                 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
 
-        if (dai->driver->playback.channels_min) {
-                ret = spear_pcm_preallocate_dma_buffer(pcm,
+        if (rtd->cpu_dai->driver->playback.channels_min) {
+                ret = spear_pcm_preallocate_dma_buffer(rtd->pcm,
                                 SNDRV_PCM_STREAM_PLAYBACK,
                                 spear_pcm_hardware.buffer_bytes_max);
                 if (ret)
                         return ret;
         }
 
-        if (dai->driver->capture.channels_min) {
-                ret = spear_pcm_preallocate_dma_buffer(pcm,
+        if (rtd->cpu_dai->driver->capture.channels_min) {
+                ret = spear_pcm_preallocate_dma_buffer(rtd->pcm,
                                 SNDRV_PCM_STREAM_CAPTURE,
                                 spear_pcm_hardware.buffer_bytes_max);
                 if (ret)
diff --git a/sound/usb/clock.c b/sound/usb/clock.c
index 5e634a2eb282..9e2703a25156 100644
--- a/sound/usb/clock.c
+++ b/sound/usb/clock.c
@@ -253,7 +253,7 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface,
 {
         struct usb_device *dev = chip->dev;
         unsigned char data[4];
-        int err, crate;
+        int err, cur_rate, prev_rate;
         int clock = snd_usb_clock_find_source(chip, fmt->clock);
 
         if (clock < 0)
@@ -266,6 +266,19 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface,
                 return -ENXIO;
         }
 
+        err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR,
+                              USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN,
+                              UAC2_CS_CONTROL_SAM_FREQ << 8,
+                              snd_usb_ctrl_intf(chip) | (clock << 8),
+                              data, sizeof(data));
+        if (err < 0) {
+                snd_printk(KERN_WARNING "%d:%d:%d: cannot get freq (v2)\n",
+                           dev->devnum, iface, fmt->altsetting);
+                prev_rate = 0;
+        } else {
+                prev_rate = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
+        }
+
         data[0] = rate;
         data[1] = rate >> 8;
         data[2] = rate >> 16;
@@ -280,19 +293,31 @@ static int set_sample_rate_v2(struct snd_usb_audio *chip, int iface,
                 return err;
         }
 
-        if ((err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR,
-                                   USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN,
-                                   UAC2_CS_CONTROL_SAM_FREQ << 8,
-                                   snd_usb_ctrl_intf(chip) | (clock << 8),
-                                   data, sizeof(data))) < 0) {
+        err = snd_usb_ctl_msg(dev, usb_rcvctrlpipe(dev, 0), UAC2_CS_CUR,
+                              USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN,
+                              UAC2_CS_CONTROL_SAM_FREQ << 8,
+                              snd_usb_ctrl_intf(chip) | (clock << 8),
+                              data, sizeof(data));
+        if (err < 0) {
                 snd_printk(KERN_WARNING "%d:%d:%d: cannot get freq (v2)\n",
                            dev->devnum, iface, fmt->altsetting);
-                return err;
+                cur_rate = 0;
+        } else {
+                cur_rate = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
         }
 
-        crate = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
-        if (crate != rate)
-                snd_printd(KERN_WARNING "current rate %d is different from the runtime rate %d\n", crate, rate);
+        if (cur_rate != rate) {
+                snd_printd(KERN_WARNING
+                           "current rate %d is different from the runtime rate %d\n",
+                           cur_rate, rate);
+        }
+
+        /* Some devices doesn't respond to sample rate changes while the
+         * interface is active. */
+        if (rate != prev_rate) {
+                usb_set_interface(dev, iface, 0);
+                usb_set_interface(dev, iface, fmt->altsetting);
+        }
 
         return 0;
 }
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index adc68feb5c5a..f18013f09e68 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -1541,21 +1541,38 @@ int kvm_write_guest(struct kvm *kvm, gpa_t gpa, const void *data,
 }
 
 int kvm_gfn_to_hva_cache_init(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
-                              gpa_t gpa)
+                              gpa_t gpa, unsigned long len)
 {
         struct kvm_memslots *slots = kvm_memslots(kvm);
         int offset = offset_in_page(gpa);
-        gfn_t gfn = gpa >> PAGE_SHIFT;
+        gfn_t start_gfn = gpa >> PAGE_SHIFT;
+        gfn_t end_gfn = (gpa + len - 1) >> PAGE_SHIFT;
+        gfn_t nr_pages_needed = end_gfn - start_gfn + 1;
+        gfn_t nr_pages_avail;
 
         ghc->gpa = gpa;
         ghc->generation = slots->generation;
-        ghc->memslot = gfn_to_memslot(kvm, gfn);
-        ghc->hva = gfn_to_hva_many(ghc->memslot, gfn, NULL);
-        if (!kvm_is_error_hva(ghc->hva))
+        ghc->len = len;
+        ghc->memslot = gfn_to_memslot(kvm, start_gfn);
+        ghc->hva = gfn_to_hva_many(ghc->memslot, start_gfn, &nr_pages_avail);
+        if (!kvm_is_error_hva(ghc->hva) && nr_pages_avail >= nr_pages_needed) {
                 ghc->hva += offset;
-        else
-                return -EFAULT;
-
+        } else {
+                /*
+                 * If the requested region crosses two memslots, we still
+                 * verify that the entire region is valid here.
+                 */
+                while (start_gfn <= end_gfn) {
+                        ghc->memslot = gfn_to_memslot(kvm, start_gfn);
+                        ghc->hva = gfn_to_hva_many(ghc->memslot, start_gfn,
+                                                   &nr_pages_avail);
+                        if (kvm_is_error_hva(ghc->hva))
+                                return -EFAULT;
+                        start_gfn += nr_pages_avail;
+                }
+                /* Use the slow path for cross page reads and writes. */
+                ghc->memslot = NULL;
+        }
         return 0;
 }
 EXPORT_SYMBOL_GPL(kvm_gfn_to_hva_cache_init);
@@ -1566,8 +1583,13 @@ int kvm_write_guest_cached(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
         struct kvm_memslots *slots = kvm_memslots(kvm);
         int r;
 
+        BUG_ON(len > ghc->len);
+
         if (slots->generation != ghc->generation)
-                kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa);
+                kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa, ghc->len);
+
+        if (unlikely(!ghc->memslot))
+                return kvm_write_guest(kvm, ghc->gpa, data, len);
 
         if (kvm_is_error_hva(ghc->hva))
                 return -EFAULT;
@@ -1587,8 +1609,13 @@ int kvm_read_guest_cached(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
         struct kvm_memslots *slots = kvm_memslots(kvm);
         int r;
 
+        BUG_ON(len > ghc->len);
+
         if (slots->generation != ghc->generation)
-                kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa);
+                kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa, ghc->len);
+
+        if (unlikely(!ghc->memslot))
+                return kvm_read_guest(kvm, ghc->gpa, data, len);
 
         if (kvm_is_error_hva(ghc->hva))
                 return -EFAULT;