diff options
-rw-r--r-- | drivers/tty/serial/Kconfig | 4 | ||||
-rw-r--r-- | drivers/tty/serial/max310x.c | 918 | ||||
-rw-r--r-- | include/linux/platform_data/max310x.h | 5 |
3 files changed, 454 insertions, 473 deletions
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 5e3d68917ffe..25772c15276d 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig | |||
@@ -291,9 +291,9 @@ config SERIAL_MAX3100 | |||
291 | 291 | ||
292 | config SERIAL_MAX310X | 292 | config SERIAL_MAX310X |
293 | bool "MAX310X support" | 293 | bool "MAX310X support" |
294 | depends on SPI | 294 | depends on SPI_MASTER |
295 | select SERIAL_CORE | 295 | select SERIAL_CORE |
296 | select REGMAP_SPI if SPI | 296 | select REGMAP_SPI if SPI_MASTER |
297 | default n | 297 | default n |
298 | help | 298 | help |
299 | This selects support for an advanced UART from Maxim (Dallas). | 299 | This selects support for an advanced UART from Maxim (Dallas). |
diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c index 8941e6418942..4620289e9e49 100644 --- a/drivers/tty/serial/max310x.c +++ b/drivers/tty/serial/max310x.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Maxim (Dallas) MAX3107/8 serial driver | 2 | * Maxim (Dallas) MAX3107/8 serial driver |
3 | * | 3 | * |
4 | * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> | 4 | * Copyright (C) 2012-2013 Alexander Shiyan <shc_work@mail.ru> |
5 | * | 5 | * |
6 | * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> | 6 | * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> |
7 | * Based on max3110.c, by Feng Tang <feng.tang@intel.com> | 7 | * Based on max3110.c, by Feng Tang <feng.tang@intel.com> |
@@ -17,7 +17,9 @@ | |||
17 | /* TODO: MAX14830 support (Quad) */ | 17 | /* TODO: MAX14830 support (Quad) */ |
18 | 18 | ||
19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
20 | #include <linux/delay.h> | ||
20 | #include <linux/device.h> | 21 | #include <linux/device.h> |
22 | #include <linux/bitops.h> | ||
21 | #include <linux/serial_core.h> | 23 | #include <linux/serial_core.h> |
22 | #include <linux/serial.h> | 24 | #include <linux/serial.h> |
23 | #include <linux/tty.h> | 25 | #include <linux/tty.h> |
@@ -25,8 +27,10 @@ | |||
25 | #include <linux/regmap.h> | 27 | #include <linux/regmap.h> |
26 | #include <linux/gpio.h> | 28 | #include <linux/gpio.h> |
27 | #include <linux/spi/spi.h> | 29 | #include <linux/spi/spi.h> |
30 | |||
28 | #include <linux/platform_data/max310x.h> | 31 | #include <linux/platform_data/max310x.h> |
29 | 32 | ||
33 | #define MAX310X_NAME "max310x" | ||
30 | #define MAX310X_MAJOR 204 | 34 | #define MAX310X_MAJOR 204 |
31 | #define MAX310X_MINOR 209 | 35 | #define MAX310X_MINOR 209 |
32 | 36 | ||
@@ -37,7 +41,8 @@ | |||
37 | #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ | 41 | #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ |
38 | #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ | 42 | #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ |
39 | #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ | 43 | #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ |
40 | #define MAX310X_SPCHR_IRQEN_REG (0x05) /* Special char IRQ enable */ | 44 | #define MAX310X_REG_05 (0x05) |
45 | #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ | ||
41 | #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ | 46 | #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ |
42 | #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ | 47 | #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ |
43 | #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ | 48 | #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ |
@@ -63,8 +68,15 @@ | |||
63 | #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ | 68 | #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ |
64 | #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ | 69 | #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ |
65 | #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ | 70 | #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ |
66 | /* Only present in MAX3107 */ | 71 | #define MAX310X_REG_1F (0x1f) |
67 | #define MAX3107_REVID_REG (0x1f) /* Revision identification */ | 72 | |
73 | #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ | ||
74 | |||
75 | #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ | ||
76 | #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ | ||
77 | |||
78 | /* Extended registers */ | ||
79 | #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ | ||
68 | 80 | ||
69 | /* IRQ register bits */ | 81 | /* IRQ register bits */ |
70 | #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ | 82 | #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ |
@@ -246,58 +258,139 @@ | |||
246 | #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ | 258 | #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ |
247 | #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ | 259 | #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ |
248 | 260 | ||
261 | /* Global commands */ | ||
262 | #define MAX310X_EXTREG_ENBL (0xce) | ||
263 | #define MAX310X_EXTREG_DSBL (0xcd) | ||
264 | |||
249 | /* Misc definitions */ | 265 | /* Misc definitions */ |
250 | #define MAX310X_FIFO_SIZE (128) | 266 | #define MAX310X_FIFO_SIZE (128) |
267 | #define MAX310x_REV_MASK (0xfc) | ||
251 | 268 | ||
252 | /* MAX3107 specific */ | 269 | /* MAX3107 specific */ |
253 | #define MAX3107_REV_ID (0xa0) | 270 | #define MAX3107_REV_ID (0xa0) |
254 | #define MAX3107_REV_MASK (0xfe) | 271 | |
255 | 272 | struct max310x_devtype { | |
256 | /* IRQ status bits definitions */ | 273 | char name[9]; |
257 | #define MAX310X_IRQ_TX (MAX310X_IRQ_TXFIFO_BIT | \ | 274 | int nr; |
258 | MAX310X_IRQ_TXEMPTY_BIT) | 275 | int (*detect)(struct device *); |
259 | #define MAX310X_IRQ_RX (MAX310X_IRQ_RXFIFO_BIT | \ | 276 | void (*power)(struct uart_port *, int); |
260 | MAX310X_IRQ_RXEMPTY_BIT) | ||
261 | |||
262 | /* Supported chip types */ | ||
263 | enum { | ||
264 | MAX310X_TYPE_MAX3107 = 3107, | ||
265 | MAX310X_TYPE_MAX3108 = 3108, | ||
266 | }; | 277 | }; |
267 | 278 | ||
268 | struct max310x_port { | 279 | struct max310x_one { |
269 | struct uart_driver uart; | ||
270 | struct uart_port port; | 280 | struct uart_port port; |
281 | struct work_struct tx_work; | ||
282 | }; | ||
271 | 283 | ||
272 | const char *name; | 284 | struct max310x_port { |
273 | int uartclk; | 285 | struct uart_driver uart; |
274 | 286 | struct max310x_devtype *devtype; | |
275 | unsigned int nr_gpio; | 287 | struct regmap *regmap; |
288 | struct regmap_config regcfg; | ||
289 | struct mutex mutex; | ||
290 | struct max310x_pdata *pdata; | ||
291 | int gpio_used; | ||
276 | #ifdef CONFIG_GPIOLIB | 292 | #ifdef CONFIG_GPIOLIB |
277 | struct gpio_chip gpio; | 293 | struct gpio_chip gpio; |
278 | #endif | 294 | #endif |
295 | struct max310x_one p[0]; | ||
296 | }; | ||
279 | 297 | ||
280 | struct regmap *regmap; | 298 | static u8 max310x_port_read(struct uart_port *port, u8 reg) |
281 | struct regmap_config regcfg; | 299 | { |
300 | struct max310x_port *s = dev_get_drvdata(port->dev); | ||
301 | unsigned int val = 0; | ||
282 | 302 | ||
283 | struct workqueue_struct *wq; | 303 | regmap_read(s->regmap, port->iobase + reg, &val); |
284 | struct work_struct tx_work; | ||
285 | 304 | ||
286 | struct mutex max310x_mutex; | 305 | return val; |
306 | } | ||
287 | 307 | ||
288 | struct max310x_pdata *pdata; | 308 | static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) |
309 | { | ||
310 | struct max310x_port *s = dev_get_drvdata(port->dev); | ||
311 | |||
312 | regmap_write(s->regmap, port->iobase + reg, val); | ||
313 | } | ||
314 | |||
315 | static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) | ||
316 | { | ||
317 | struct max310x_port *s = dev_get_drvdata(port->dev); | ||
318 | |||
319 | regmap_update_bits(s->regmap, port->iobase + reg, mask, val); | ||
320 | } | ||
321 | |||
322 | static int max3107_detect(struct device *dev) | ||
323 | { | ||
324 | struct max310x_port *s = dev_get_drvdata(dev); | ||
325 | unsigned int val = 0; | ||
326 | int ret; | ||
327 | |||
328 | ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); | ||
329 | if (ret) | ||
330 | return ret; | ||
331 | |||
332 | if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { | ||
333 | dev_err(dev, | ||
334 | "%s ID 0x%02x does not match\n", s->devtype->name, val); | ||
335 | return -ENODEV; | ||
336 | } | ||
337 | |||
338 | return 0; | ||
339 | } | ||
340 | |||
341 | static int max3108_detect(struct device *dev) | ||
342 | { | ||
343 | struct max310x_port *s = dev_get_drvdata(dev); | ||
344 | unsigned int val = 0; | ||
345 | int ret; | ||
346 | |||
347 | /* MAX3108 have not REV ID register, we just check default value | ||
348 | * from clocksource register to make sure everything works. | ||
349 | */ | ||
350 | ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); | ||
351 | if (ret) | ||
352 | return ret; | ||
353 | |||
354 | if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { | ||
355 | dev_err(dev, "%s not present\n", s->devtype->name); | ||
356 | return -ENODEV; | ||
357 | } | ||
358 | |||
359 | return 0; | ||
360 | } | ||
361 | |||
362 | static void max310x_power(struct uart_port *port, int on) | ||
363 | { | ||
364 | max310x_port_update(port, MAX310X_MODE1_REG, | ||
365 | MAX310X_MODE1_FORCESLEEP_BIT, | ||
366 | on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); | ||
367 | if (on) | ||
368 | msleep(50); | ||
369 | } | ||
370 | |||
371 | static const struct max310x_devtype max3107_devtype = { | ||
372 | .name = "MAX3107", | ||
373 | .nr = 1, | ||
374 | .detect = max3107_detect, | ||
375 | .power = max310x_power, | ||
289 | }; | 376 | }; |
290 | 377 | ||
291 | static bool max3107_8_reg_writeable(struct device *dev, unsigned int reg) | 378 | static const struct max310x_devtype max3108_devtype = { |
379 | .name = "MAX3108", | ||
380 | .nr = 1, | ||
381 | .detect = max3108_detect, | ||
382 | .power = max310x_power, | ||
383 | }; | ||
384 | |||
385 | static bool max310x_reg_writeable(struct device *dev, unsigned int reg) | ||
292 | { | 386 | { |
293 | switch (reg) { | 387 | switch (reg & 0x1f) { |
294 | case MAX310X_IRQSTS_REG: | 388 | case MAX310X_IRQSTS_REG: |
295 | case MAX310X_LSR_IRQSTS_REG: | 389 | case MAX310X_LSR_IRQSTS_REG: |
296 | case MAX310X_SPCHR_IRQSTS_REG: | 390 | case MAX310X_SPCHR_IRQSTS_REG: |
297 | case MAX310X_STS_IRQSTS_REG: | 391 | case MAX310X_STS_IRQSTS_REG: |
298 | case MAX310X_TXFIFOLVL_REG: | 392 | case MAX310X_TXFIFOLVL_REG: |
299 | case MAX310X_RXFIFOLVL_REG: | 393 | case MAX310X_RXFIFOLVL_REG: |
300 | case MAX3107_REVID_REG: /* Only available on MAX3107 */ | ||
301 | return false; | 394 | return false; |
302 | default: | 395 | default: |
303 | break; | 396 | break; |
@@ -308,7 +401,7 @@ static bool max3107_8_reg_writeable(struct device *dev, unsigned int reg) | |||
308 | 401 | ||
309 | static bool max310x_reg_volatile(struct device *dev, unsigned int reg) | 402 | static bool max310x_reg_volatile(struct device *dev, unsigned int reg) |
310 | { | 403 | { |
311 | switch (reg) { | 404 | switch (reg & 0x1f) { |
312 | case MAX310X_RHR_REG: | 405 | case MAX310X_RHR_REG: |
313 | case MAX310X_IRQSTS_REG: | 406 | case MAX310X_IRQSTS_REG: |
314 | case MAX310X_LSR_IRQSTS_REG: | 407 | case MAX310X_LSR_IRQSTS_REG: |
@@ -317,6 +410,9 @@ static bool max310x_reg_volatile(struct device *dev, unsigned int reg) | |||
317 | case MAX310X_TXFIFOLVL_REG: | 410 | case MAX310X_TXFIFOLVL_REG: |
318 | case MAX310X_RXFIFOLVL_REG: | 411 | case MAX310X_RXFIFOLVL_REG: |
319 | case MAX310X_GPIODATA_REG: | 412 | case MAX310X_GPIODATA_REG: |
413 | case MAX310X_BRGDIVLSB_REG: | ||
414 | case MAX310X_REG_05: | ||
415 | case MAX310X_REG_1F: | ||
320 | return true; | 416 | return true; |
321 | default: | 417 | default: |
322 | break; | 418 | break; |
@@ -327,7 +423,7 @@ static bool max310x_reg_volatile(struct device *dev, unsigned int reg) | |||
327 | 423 | ||
328 | static bool max310x_reg_precious(struct device *dev, unsigned int reg) | 424 | static bool max310x_reg_precious(struct device *dev, unsigned int reg) |
329 | { | 425 | { |
330 | switch (reg) { | 426 | switch (reg & 0x1f) { |
331 | case MAX310X_RHR_REG: | 427 | case MAX310X_RHR_REG: |
332 | case MAX310X_IRQSTS_REG: | 428 | case MAX310X_IRQSTS_REG: |
333 | case MAX310X_SPCHR_IRQSTS_REG: | 429 | case MAX310X_SPCHR_IRQSTS_REG: |
@@ -340,42 +436,25 @@ static bool max310x_reg_precious(struct device *dev, unsigned int reg) | |||
340 | return false; | 436 | return false; |
341 | } | 437 | } |
342 | 438 | ||
343 | static void max310x_set_baud(struct max310x_port *s, int baud) | 439 | static void max310x_set_baud(struct uart_port *port, int baud) |
344 | { | 440 | { |
345 | unsigned int mode = 0, div = s->uartclk / baud; | 441 | unsigned int mode = 0, div = port->uartclk / baud; |
346 | 442 | ||
347 | if (!(div / 16)) { | 443 | if (!(div / 16)) { |
348 | /* Mode x2 */ | 444 | /* Mode x2 */ |
349 | mode = MAX310X_BRGCFG_2XMODE_BIT; | 445 | mode = MAX310X_BRGCFG_2XMODE_BIT; |
350 | div = (s->uartclk * 2) / baud; | 446 | div = (port->uartclk * 2) / baud; |
351 | } | 447 | } |
352 | 448 | ||
353 | if (!(div / 16)) { | 449 | if (!(div / 16)) { |
354 | /* Mode x4 */ | 450 | /* Mode x4 */ |
355 | mode = MAX310X_BRGCFG_4XMODE_BIT; | 451 | mode = MAX310X_BRGCFG_4XMODE_BIT; |
356 | div = (s->uartclk * 4) / baud; | 452 | div = (port->uartclk * 4) / baud; |
357 | } | 453 | } |
358 | 454 | ||
359 | regmap_write(s->regmap, MAX310X_BRGDIVMSB_REG, | 455 | max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8); |
360 | ((div / 16) >> 8) & 0xff); | 456 | max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16); |
361 | regmap_write(s->regmap, MAX310X_BRGDIVLSB_REG, (div / 16) & 0xff); | 457 | max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode); |
362 | regmap_write(s->regmap, MAX310X_BRGCFG_REG, (div % 16) | mode); | ||
363 | } | ||
364 | |||
365 | static void max310x_wait_pll(struct max310x_port *s) | ||
366 | { | ||
367 | int tryes = 1000; | ||
368 | |||
369 | /* Wait for PLL only if crystal is used */ | ||
370 | if (!(s->pdata->driver_flags & MAX310X_EXT_CLK)) { | ||
371 | unsigned int sts = 0; | ||
372 | |||
373 | while (tryes--) { | ||
374 | regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &sts); | ||
375 | if (sts & MAX310X_STS_CLKREADY_BIT) | ||
376 | break; | ||
377 | } | ||
378 | } | ||
379 | } | 458 | } |
380 | 459 | ||
381 | static int max310x_update_best_err(unsigned long f, long *besterr) | 460 | static int max310x_update_best_err(unsigned long f, long *besterr) |
@@ -449,49 +528,49 @@ static int max310x_set_ref_clk(struct max310x_port *s) | |||
449 | 528 | ||
450 | regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); | 529 | regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); |
451 | 530 | ||
452 | if (pllcfg) | 531 | /* Wait for crystal */ |
453 | max310x_wait_pll(s); | 532 | if (pllcfg && !(s->pdata->driver_flags & MAX310X_EXT_CLK)) |
454 | 533 | msleep(10); | |
455 | dev_dbg(s->port.dev, "Reference clock set to %lu Hz\n", bestfreq); | ||
456 | 534 | ||
457 | return (int)bestfreq; | 535 | return (int)bestfreq; |
458 | } | 536 | } |
459 | 537 | ||
460 | static void max310x_handle_rx(struct max310x_port *s, unsigned int rxlen) | 538 | static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) |
461 | { | 539 | { |
462 | unsigned int sts = 0, ch = 0, flag; | 540 | unsigned int sts, ch, flag; |
463 | 541 | ||
464 | if (unlikely(rxlen >= MAX310X_FIFO_SIZE)) { | 542 | if (unlikely(rxlen >= port->fifosize)) { |
465 | dev_warn(s->port.dev, "Possible RX FIFO overrun %d\n", rxlen); | 543 | dev_warn_ratelimited(port->dev, |
544 | "Port %i: Possible RX FIFO overrun\n", | ||
545 | port->line); | ||
546 | port->icount.buf_overrun++; | ||
466 | /* Ensure sanity of RX level */ | 547 | /* Ensure sanity of RX level */ |
467 | rxlen = MAX310X_FIFO_SIZE; | 548 | rxlen = port->fifosize; |
468 | } | 549 | } |
469 | 550 | ||
470 | dev_dbg(s->port.dev, "RX Len = %u\n", rxlen); | ||
471 | |||
472 | while (rxlen--) { | 551 | while (rxlen--) { |
473 | regmap_read(s->regmap, MAX310X_RHR_REG, &ch); | 552 | ch = max310x_port_read(port, MAX310X_RHR_REG); |
474 | regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &sts); | 553 | sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); |
475 | 554 | ||
476 | sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | | 555 | sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | |
477 | MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; | 556 | MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; |
478 | 557 | ||
479 | s->port.icount.rx++; | 558 | port->icount.rx++; |
480 | flag = TTY_NORMAL; | 559 | flag = TTY_NORMAL; |
481 | 560 | ||
482 | if (unlikely(sts)) { | 561 | if (unlikely(sts)) { |
483 | if (sts & MAX310X_LSR_RXBRK_BIT) { | 562 | if (sts & MAX310X_LSR_RXBRK_BIT) { |
484 | s->port.icount.brk++; | 563 | port->icount.brk++; |
485 | if (uart_handle_break(&s->port)) | 564 | if (uart_handle_break(port)) |
486 | continue; | 565 | continue; |
487 | } else if (sts & MAX310X_LSR_RXPAR_BIT) | 566 | } else if (sts & MAX310X_LSR_RXPAR_BIT) |
488 | s->port.icount.parity++; | 567 | port->icount.parity++; |
489 | else if (sts & MAX310X_LSR_FRERR_BIT) | 568 | else if (sts & MAX310X_LSR_FRERR_BIT) |
490 | s->port.icount.frame++; | 569 | port->icount.frame++; |
491 | else if (sts & MAX310X_LSR_RXOVR_BIT) | 570 | else if (sts & MAX310X_LSR_RXOVR_BIT) |
492 | s->port.icount.overrun++; | 571 | port->icount.overrun++; |
493 | 572 | ||
494 | sts &= s->port.read_status_mask; | 573 | sts &= port->read_status_mask; |
495 | if (sts & MAX310X_LSR_RXBRK_BIT) | 574 | if (sts & MAX310X_LSR_RXBRK_BIT) |
496 | flag = TTY_BREAK; | 575 | flag = TTY_BREAK; |
497 | else if (sts & MAX310X_LSR_RXPAR_BIT) | 576 | else if (sts & MAX310X_LSR_RXPAR_BIT) |
@@ -502,129 +581,129 @@ static void max310x_handle_rx(struct max310x_port *s, unsigned int rxlen) | |||
502 | flag = TTY_OVERRUN; | 581 | flag = TTY_OVERRUN; |
503 | } | 582 | } |
504 | 583 | ||
505 | if (uart_handle_sysrq_char(s->port, ch)) | 584 | if (uart_handle_sysrq_char(port, ch)) |
506 | continue; | 585 | continue; |
507 | 586 | ||
508 | if (sts & s->port.ignore_status_mask) | 587 | if (sts & port->ignore_status_mask) |
509 | continue; | 588 | continue; |
510 | 589 | ||
511 | uart_insert_char(&s->port, sts, MAX310X_LSR_RXOVR_BIT, | 590 | uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); |
512 | ch, flag); | ||
513 | } | 591 | } |
514 | 592 | ||
515 | tty_flip_buffer_push(&s->port.state->port); | 593 | tty_flip_buffer_push(&port->state->port); |
516 | } | 594 | } |
517 | 595 | ||
518 | static void max310x_handle_tx(struct max310x_port *s) | 596 | static void max310x_handle_tx(struct uart_port *port) |
519 | { | 597 | { |
520 | struct circ_buf *xmit = &s->port.state->xmit; | 598 | struct circ_buf *xmit = &port->state->xmit; |
521 | unsigned int txlen = 0, to_send; | 599 | unsigned int txlen, to_send; |
522 | 600 | ||
523 | if (unlikely(s->port.x_char)) { | 601 | if (unlikely(port->x_char)) { |
524 | regmap_write(s->regmap, MAX310X_THR_REG, s->port.x_char); | 602 | max310x_port_write(port, MAX310X_THR_REG, port->x_char); |
525 | s->port.icount.tx++; | 603 | port->icount.tx++; |
526 | s->port.x_char = 0; | 604 | port->x_char = 0; |
527 | return; | 605 | return; |
528 | } | 606 | } |
529 | 607 | ||
530 | if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port)) | 608 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
531 | return; | 609 | return; |
532 | 610 | ||
533 | /* Get length of data pending in circular buffer */ | 611 | /* Get length of data pending in circular buffer */ |
534 | to_send = uart_circ_chars_pending(xmit); | 612 | to_send = uart_circ_chars_pending(xmit); |
535 | if (likely(to_send)) { | 613 | if (likely(to_send)) { |
536 | /* Limit to size of TX FIFO */ | 614 | /* Limit to size of TX FIFO */ |
537 | regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &txlen); | 615 | txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); |
538 | txlen = MAX310X_FIFO_SIZE - txlen; | 616 | txlen = port->fifosize - txlen; |
539 | to_send = (to_send > txlen) ? txlen : to_send; | 617 | to_send = (to_send > txlen) ? txlen : to_send; |
540 | 618 | ||
541 | dev_dbg(s->port.dev, "TX Len = %u\n", to_send); | ||
542 | |||
543 | /* Add data to send */ | 619 | /* Add data to send */ |
544 | s->port.icount.tx += to_send; | 620 | port->icount.tx += to_send; |
545 | while (to_send--) { | 621 | while (to_send--) { |
546 | regmap_write(s->regmap, MAX310X_THR_REG, | 622 | max310x_port_write(port, MAX310X_THR_REG, |
547 | xmit->buf[xmit->tail]); | 623 | xmit->buf[xmit->tail]); |
548 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | 624 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
549 | }; | 625 | }; |
550 | } | 626 | } |
551 | 627 | ||
552 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | 628 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
553 | uart_write_wakeup(&s->port); | 629 | uart_write_wakeup(port); |
554 | } | 630 | } |
555 | 631 | ||
556 | static irqreturn_t max310x_ist(int irq, void *dev_id) | 632 | static void max310x_port_irq(struct max310x_port *s, int portno) |
557 | { | 633 | { |
558 | struct max310x_port *s = (struct max310x_port *)dev_id; | 634 | struct uart_port *port = &s->p[portno].port; |
559 | unsigned int ists = 0, lsr = 0, rxlen = 0; | ||
560 | 635 | ||
561 | mutex_lock(&s->max310x_mutex); | 636 | do { |
637 | unsigned int ists, lsr, rxlen; | ||
562 | 638 | ||
563 | for (;;) { | ||
564 | /* Read IRQ status & RX FIFO level */ | 639 | /* Read IRQ status & RX FIFO level */ |
565 | regmap_read(s->regmap, MAX310X_IRQSTS_REG, &ists); | 640 | ists = max310x_port_read(port, MAX310X_IRQSTS_REG); |
566 | regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &lsr); | 641 | rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); |
567 | regmap_read(s->regmap, MAX310X_RXFIFOLVL_REG, &rxlen); | 642 | if (!ists && !rxlen) |
568 | if (!ists && !(lsr & MAX310X_LSR_RXTO_BIT) && !rxlen) | ||
569 | break; | 643 | break; |
570 | 644 | ||
571 | dev_dbg(s->port.dev, "IRQ status: 0x%02x\n", ists); | 645 | if (ists & MAX310X_IRQ_CTS_BIT) { |
572 | 646 | lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); | |
573 | if (rxlen) | 647 | uart_handle_cts_change(port, |
574 | max310x_handle_rx(s, rxlen); | ||
575 | if (ists & MAX310X_IRQ_TX) | ||
576 | max310x_handle_tx(s); | ||
577 | if (ists & MAX310X_IRQ_CTS_BIT) | ||
578 | uart_handle_cts_change(&s->port, | ||
579 | !!(lsr & MAX310X_LSR_CTS_BIT)); | 648 | !!(lsr & MAX310X_LSR_CTS_BIT)); |
580 | } | 649 | } |
650 | if (rxlen) | ||
651 | max310x_handle_rx(port, rxlen); | ||
652 | if (ists & MAX310X_IRQ_TXEMPTY_BIT) { | ||
653 | mutex_lock(&s->mutex); | ||
654 | max310x_handle_tx(port); | ||
655 | mutex_unlock(&s->mutex); | ||
656 | } | ||
657 | } while (1); | ||
658 | } | ||
581 | 659 | ||
582 | mutex_unlock(&s->max310x_mutex); | 660 | static irqreturn_t max310x_ist(int irq, void *dev_id) |
661 | { | ||
662 | struct max310x_port *s = (struct max310x_port *)dev_id; | ||
663 | |||
664 | if (s->uart.nr > 1) { | ||
665 | do { | ||
666 | unsigned int val = ~0; | ||
667 | |||
668 | WARN_ON_ONCE(regmap_read(s->regmap, | ||
669 | MAX310X_GLOBALIRQ_REG, &val)); | ||
670 | val = ((1 << s->uart.nr) - 1) & ~val; | ||
671 | if (!val) | ||
672 | break; | ||
673 | max310x_port_irq(s, fls(val) - 1); | ||
674 | } while (1); | ||
675 | } else | ||
676 | max310x_port_irq(s, 0); | ||
583 | 677 | ||
584 | return IRQ_HANDLED; | 678 | return IRQ_HANDLED; |
585 | } | 679 | } |
586 | 680 | ||
587 | static void max310x_wq_proc(struct work_struct *ws) | 681 | static void max310x_wq_proc(struct work_struct *ws) |
588 | { | 682 | { |
589 | struct max310x_port *s = container_of(ws, struct max310x_port, tx_work); | 683 | struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); |
684 | struct max310x_port *s = dev_get_drvdata(one->port.dev); | ||
590 | 685 | ||
591 | mutex_lock(&s->max310x_mutex); | 686 | mutex_lock(&s->mutex); |
592 | max310x_handle_tx(s); | 687 | max310x_handle_tx(&one->port); |
593 | mutex_unlock(&s->max310x_mutex); | 688 | mutex_unlock(&s->mutex); |
594 | } | 689 | } |
595 | 690 | ||
596 | static void max310x_start_tx(struct uart_port *port) | 691 | static void max310x_start_tx(struct uart_port *port) |
597 | { | 692 | { |
598 | struct max310x_port *s = container_of(port, struct max310x_port, port); | 693 | struct max310x_one *one = container_of(port, struct max310x_one, port); |
599 | 694 | ||
600 | queue_work(s->wq, &s->tx_work); | 695 | if (!work_pending(&one->tx_work)) |
601 | } | 696 | schedule_work(&one->tx_work); |
602 | |||
603 | static void max310x_stop_tx(struct uart_port *port) | ||
604 | { | ||
605 | /* Do nothing */ | ||
606 | } | ||
607 | |||
608 | static void max310x_stop_rx(struct uart_port *port) | ||
609 | { | ||
610 | /* Do nothing */ | ||
611 | } | 697 | } |
612 | 698 | ||
613 | static unsigned int max310x_tx_empty(struct uart_port *port) | 699 | static unsigned int max310x_tx_empty(struct uart_port *port) |
614 | { | 700 | { |
615 | unsigned int val = 0; | 701 | unsigned int lvl, sts; |
616 | struct max310x_port *s = container_of(port, struct max310x_port, port); | ||
617 | |||
618 | mutex_lock(&s->max310x_mutex); | ||
619 | regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &val); | ||
620 | mutex_unlock(&s->max310x_mutex); | ||
621 | 702 | ||
622 | return val ? 0 : TIOCSER_TEMT; | 703 | lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); |
623 | } | 704 | sts = max310x_port_read(port, MAX310X_IRQSTS_REG); |
624 | 705 | ||
625 | static void max310x_enable_ms(struct uart_port *port) | 706 | return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0; |
626 | { | ||
627 | /* Modem status not supported */ | ||
628 | } | 707 | } |
629 | 708 | ||
630 | static unsigned int max310x_get_mctrl(struct uart_port *port) | 709 | static unsigned int max310x_get_mctrl(struct uart_port *port) |
@@ -644,28 +723,20 @@ static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) | |||
644 | 723 | ||
645 | static void max310x_break_ctl(struct uart_port *port, int break_state) | 724 | static void max310x_break_ctl(struct uart_port *port, int break_state) |
646 | { | 725 | { |
647 | struct max310x_port *s = container_of(port, struct max310x_port, port); | 726 | max310x_port_update(port, MAX310X_LCR_REG, |
648 | 727 | MAX310X_LCR_TXBREAK_BIT, | |
649 | mutex_lock(&s->max310x_mutex); | 728 | break_state ? MAX310X_LCR_TXBREAK_BIT : 0); |
650 | regmap_update_bits(s->regmap, MAX310X_LCR_REG, | ||
651 | MAX310X_LCR_TXBREAK_BIT, | ||
652 | break_state ? MAX310X_LCR_TXBREAK_BIT : 0); | ||
653 | mutex_unlock(&s->max310x_mutex); | ||
654 | } | 729 | } |
655 | 730 | ||
656 | static void max310x_set_termios(struct uart_port *port, | 731 | static void max310x_set_termios(struct uart_port *port, |
657 | struct ktermios *termios, | 732 | struct ktermios *termios, |
658 | struct ktermios *old) | 733 | struct ktermios *old) |
659 | { | 734 | { |
660 | struct max310x_port *s = container_of(port, struct max310x_port, port); | ||
661 | unsigned int lcr, flow = 0; | 735 | unsigned int lcr, flow = 0; |
662 | int baud; | 736 | int baud; |
663 | 737 | ||
664 | mutex_lock(&s->max310x_mutex); | ||
665 | |||
666 | /* Mask termios capabilities we don't support */ | 738 | /* Mask termios capabilities we don't support */ |
667 | termios->c_cflag &= ~CMSPAR; | 739 | termios->c_cflag &= ~CMSPAR; |
668 | termios->c_iflag &= ~IXANY; | ||
669 | 740 | ||
670 | /* Word size */ | 741 | /* Word size */ |
671 | switch (termios->c_cflag & CSIZE) { | 742 | switch (termios->c_cflag & CSIZE) { |
@@ -696,7 +767,7 @@ static void max310x_set_termios(struct uart_port *port, | |||
696 | lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ | 767 | lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ |
697 | 768 | ||
698 | /* Update LCR register */ | 769 | /* Update LCR register */ |
699 | regmap_write(s->regmap, MAX310X_LCR_REG, lcr); | 770 | max310x_port_write(port, MAX310X_LCR_REG, lcr); |
700 | 771 | ||
701 | /* Set read status mask */ | 772 | /* Set read status mask */ |
702 | port->read_status_mask = MAX310X_LSR_RXOVR_BIT; | 773 | port->read_status_mask = MAX310X_LSR_RXOVR_BIT; |
@@ -717,8 +788,8 @@ static void max310x_set_termios(struct uart_port *port, | |||
717 | MAX310X_LSR_RXBRK_BIT; | 788 | MAX310X_LSR_RXBRK_BIT; |
718 | 789 | ||
719 | /* Configure flow control */ | 790 | /* Configure flow control */ |
720 | regmap_write(s->regmap, MAX310X_XON1_REG, termios->c_cc[VSTART]); | 791 | max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); |
721 | regmap_write(s->regmap, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); | 792 | max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); |
722 | if (termios->c_cflag & CRTSCTS) | 793 | if (termios->c_cflag & CRTSCTS) |
723 | flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | | 794 | flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | |
724 | MAX310X_FLOWCTRL_AUTORTS_BIT; | 795 | MAX310X_FLOWCTRL_AUTORTS_BIT; |
@@ -728,7 +799,7 @@ static void max310x_set_termios(struct uart_port *port, | |||
728 | if (termios->c_iflag & IXOFF) | 799 | if (termios->c_iflag & IXOFF) |
729 | flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | | 800 | flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | |
730 | MAX310X_FLOWCTRL_SWFLOWEN_BIT; | 801 | MAX310X_FLOWCTRL_SWFLOWEN_BIT; |
731 | regmap_write(s->regmap, MAX310X_FLOWCTRL_REG, flow); | 802 | max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); |
732 | 803 | ||
733 | /* Get baud rate generator configuration */ | 804 | /* Get baud rate generator configuration */ |
734 | baud = uart_get_baud_rate(port, termios, old, | 805 | baud = uart_get_baud_rate(port, termios, old, |
@@ -736,36 +807,30 @@ static void max310x_set_termios(struct uart_port *port, | |||
736 | port->uartclk / 4); | 807 | port->uartclk / 4); |
737 | 808 | ||
738 | /* Setup baudrate generator */ | 809 | /* Setup baudrate generator */ |
739 | max310x_set_baud(s, baud); | 810 | max310x_set_baud(port, baud); |
740 | 811 | ||
741 | /* Update timeout according to new baud rate */ | 812 | /* Update timeout according to new baud rate */ |
742 | uart_update_timeout(port, termios->c_cflag, baud); | 813 | uart_update_timeout(port, termios->c_cflag, baud); |
743 | |||
744 | mutex_unlock(&s->max310x_mutex); | ||
745 | } | 814 | } |
746 | 815 | ||
747 | static int max310x_startup(struct uart_port *port) | 816 | static int max310x_startup(struct uart_port *port) |
748 | { | 817 | { |
749 | unsigned int val, line = port->line; | 818 | unsigned int val, line = port->line; |
750 | struct max310x_port *s = container_of(port, struct max310x_port, port); | 819 | struct max310x_port *s = dev_get_drvdata(port->dev); |
751 | 820 | ||
752 | if (s->pdata->suspend) | 821 | s->devtype->power(port, 1); |
753 | s->pdata->suspend(0); | ||
754 | |||
755 | mutex_lock(&s->max310x_mutex); | ||
756 | 822 | ||
757 | /* Configure baud rate, 9600 as default */ | 823 | /* Configure baud rate, 9600 as default */ |
758 | max310x_set_baud(s, 9600); | 824 | max310x_set_baud(port, 9600); |
759 | 825 | ||
760 | /* Configure LCR register, 8N1 mode by default */ | 826 | /* Configure LCR register, 8N1 mode by default */ |
761 | val = MAX310X_LCR_WORD_LEN_8; | 827 | max310x_port_write(port, MAX310X_LCR_REG, MAX310X_LCR_WORD_LEN_8); |
762 | regmap_write(s->regmap, MAX310X_LCR_REG, val); | ||
763 | 828 | ||
764 | /* Configure MODE1 register */ | 829 | /* Configure MODE1 register */ |
765 | regmap_update_bits(s->regmap, MAX310X_MODE1_REG, | 830 | max310x_port_update(port, MAX310X_MODE1_REG, |
766 | MAX310X_MODE1_TRNSCVCTRL_BIT, | 831 | MAX310X_MODE1_TRNSCVCTRL_BIT, |
767 | (s->pdata->uart_flags[line] & MAX310X_AUTO_DIR_CTRL) | 832 | (s->pdata->uart_flags[line] & MAX310X_AUTO_DIR_CTRL) |
768 | ? MAX310X_MODE1_TRNSCVCTRL_BIT : 0); | 833 | ? MAX310X_MODE1_TRNSCVCTRL_BIT : 0); |
769 | 834 | ||
770 | /* Configure MODE2 register */ | 835 | /* Configure MODE2 register */ |
771 | val = MAX310X_MODE2_RXEMPTINV_BIT; | 836 | val = MAX310X_MODE2_RXEMPTINV_BIT; |
@@ -776,63 +841,40 @@ static int max310x_startup(struct uart_port *port) | |||
776 | 841 | ||
777 | /* Reset FIFOs */ | 842 | /* Reset FIFOs */ |
778 | val |= MAX310X_MODE2_FIFORST_BIT; | 843 | val |= MAX310X_MODE2_FIFORST_BIT; |
779 | regmap_write(s->regmap, MAX310X_MODE2_REG, val); | 844 | max310x_port_write(port, MAX310X_MODE2_REG, val); |
780 | 845 | max310x_port_update(port, MAX310X_MODE2_REG, | |
781 | /* Configure FIFO trigger level register */ | 846 | MAX310X_MODE2_FIFORST_BIT, 0); |
782 | /* RX FIFO trigger for 16 words, TX FIFO trigger for 64 words */ | ||
783 | val = MAX310X_FIFOTRIGLVL_RX(16) | MAX310X_FIFOTRIGLVL_TX(64); | ||
784 | regmap_write(s->regmap, MAX310X_FIFOTRIGLVL_REG, val); | ||
785 | 847 | ||
786 | /* Configure flow control levels */ | 848 | /* Configure flow control levels */ |
787 | /* Flow control halt level 96, resume level 48 */ | 849 | /* Flow control halt level 96, resume level 48 */ |
788 | val = MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96); | 850 | max310x_port_write(port, MAX310X_FLOWLVL_REG, |
789 | regmap_write(s->regmap, MAX310X_FLOWLVL_REG, val); | 851 | MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); |
790 | |||
791 | /* Clear timeout register */ | ||
792 | regmap_write(s->regmap, MAX310X_RXTO_REG, 0); | ||
793 | |||
794 | /* Configure LSR interrupt enable register */ | ||
795 | /* Enable RX timeout interrupt */ | ||
796 | val = MAX310X_LSR_RXTO_BIT; | ||
797 | regmap_write(s->regmap, MAX310X_LSR_IRQEN_REG, val); | ||
798 | 852 | ||
799 | /* Clear FIFO reset */ | 853 | /* Clear IRQ status register */ |
800 | regmap_update_bits(s->regmap, MAX310X_MODE2_REG, | 854 | max310x_port_read(port, MAX310X_IRQSTS_REG); |
801 | MAX310X_MODE2_FIFORST_BIT, 0); | ||
802 | 855 | ||
803 | /* Clear IRQ status register by reading it */ | 856 | /* Enable RX, TX, CTS change interrupts */ |
804 | regmap_read(s->regmap, MAX310X_IRQSTS_REG, &val); | 857 | val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; |
805 | 858 | max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); | |
806 | /* Configure interrupt enable register */ | ||
807 | /* Enable CTS change interrupt */ | ||
808 | val = MAX310X_IRQ_CTS_BIT; | ||
809 | /* Enable RX, TX interrupts */ | ||
810 | val |= MAX310X_IRQ_RX | MAX310X_IRQ_TX; | ||
811 | regmap_write(s->regmap, MAX310X_IRQEN_REG, val); | ||
812 | |||
813 | mutex_unlock(&s->max310x_mutex); | ||
814 | 859 | ||
815 | return 0; | 860 | return 0; |
816 | } | 861 | } |
817 | 862 | ||
818 | static void max310x_shutdown(struct uart_port *port) | 863 | static void max310x_shutdown(struct uart_port *port) |
819 | { | 864 | { |
820 | struct max310x_port *s = container_of(port, struct max310x_port, port); | 865 | struct max310x_port *s = dev_get_drvdata(port->dev); |
821 | 866 | ||
822 | /* Disable all interrupts */ | 867 | /* Disable all interrupts */ |
823 | mutex_lock(&s->max310x_mutex); | 868 | max310x_port_write(port, MAX310X_IRQEN_REG, 0); |
824 | regmap_write(s->regmap, MAX310X_IRQEN_REG, 0); | ||
825 | mutex_unlock(&s->max310x_mutex); | ||
826 | 869 | ||
827 | if (s->pdata->suspend) | 870 | s->devtype->power(port, 0); |
828 | s->pdata->suspend(1); | ||
829 | } | 871 | } |
830 | 872 | ||
831 | static const char *max310x_type(struct uart_port *port) | 873 | static const char *max310x_type(struct uart_port *port) |
832 | { | 874 | { |
833 | struct max310x_port *s = container_of(port, struct max310x_port, port); | 875 | struct max310x_port *s = dev_get_drvdata(port->dev); |
834 | 876 | ||
835 | return (port->type == PORT_MAX310X) ? s->name : NULL; | 877 | return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; |
836 | } | 878 | } |
837 | 879 | ||
838 | static int max310x_request_port(struct uart_port *port) | 880 | static int max310x_request_port(struct uart_port *port) |
@@ -841,134 +883,100 @@ static int max310x_request_port(struct uart_port *port) | |||
841 | return 0; | 883 | return 0; |
842 | } | 884 | } |
843 | 885 | ||
844 | static void max310x_release_port(struct uart_port *port) | ||
845 | { | ||
846 | /* Do nothing */ | ||
847 | } | ||
848 | |||
849 | static void max310x_config_port(struct uart_port *port, int flags) | 886 | static void max310x_config_port(struct uart_port *port, int flags) |
850 | { | 887 | { |
851 | if (flags & UART_CONFIG_TYPE) | 888 | if (flags & UART_CONFIG_TYPE) |
852 | port->type = PORT_MAX310X; | 889 | port->type = PORT_MAX310X; |
853 | } | 890 | } |
854 | 891 | ||
855 | static int max310x_verify_port(struct uart_port *port, struct serial_struct *ser) | 892 | static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) |
856 | { | 893 | { |
857 | if ((ser->type == PORT_UNKNOWN) || (ser->type == PORT_MAX310X)) | 894 | if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) |
858 | return 0; | 895 | return -EINVAL; |
859 | if (ser->irq == port->irq) | 896 | if (s->irq != port->irq) |
860 | return 0; | 897 | return -EINVAL; |
861 | 898 | ||
862 | return -EINVAL; | 899 | return 0; |
863 | } | 900 | } |
864 | 901 | ||
865 | static struct uart_ops max310x_ops = { | 902 | static void max310x_null_void(struct uart_port *port) |
903 | { | ||
904 | /* Do nothing */ | ||
905 | } | ||
906 | |||
907 | static const struct uart_ops max310x_ops = { | ||
866 | .tx_empty = max310x_tx_empty, | 908 | .tx_empty = max310x_tx_empty, |
867 | .set_mctrl = max310x_set_mctrl, | 909 | .set_mctrl = max310x_set_mctrl, |
868 | .get_mctrl = max310x_get_mctrl, | 910 | .get_mctrl = max310x_get_mctrl, |
869 | .stop_tx = max310x_stop_tx, | 911 | .stop_tx = max310x_null_void, |
870 | .start_tx = max310x_start_tx, | 912 | .start_tx = max310x_start_tx, |
871 | .stop_rx = max310x_stop_rx, | 913 | .stop_rx = max310x_null_void, |
872 | .enable_ms = max310x_enable_ms, | 914 | .enable_ms = max310x_null_void, |
873 | .break_ctl = max310x_break_ctl, | 915 | .break_ctl = max310x_break_ctl, |
874 | .startup = max310x_startup, | 916 | .startup = max310x_startup, |
875 | .shutdown = max310x_shutdown, | 917 | .shutdown = max310x_shutdown, |
876 | .set_termios = max310x_set_termios, | 918 | .set_termios = max310x_set_termios, |
877 | .type = max310x_type, | 919 | .type = max310x_type, |
878 | .request_port = max310x_request_port, | 920 | .request_port = max310x_request_port, |
879 | .release_port = max310x_release_port, | 921 | .release_port = max310x_null_void, |
880 | .config_port = max310x_config_port, | 922 | .config_port = max310x_config_port, |
881 | .verify_port = max310x_verify_port, | 923 | .verify_port = max310x_verify_port, |
882 | }; | 924 | }; |
883 | 925 | ||
884 | #ifdef CONFIG_PM_SLEEP | 926 | static int __maybe_unused max310x_suspend(struct spi_device *spi, |
885 | 927 | pm_message_t state) | |
886 | static int max310x_suspend(struct device *dev) | ||
887 | { | 928 | { |
888 | int ret; | 929 | struct max310x_port *s = dev_get_drvdata(&spi->dev); |
889 | struct max310x_port *s = dev_get_drvdata(dev); | 930 | int i; |
890 | |||
891 | dev_dbg(dev, "Suspend\n"); | ||
892 | 931 | ||
893 | ret = uart_suspend_port(&s->uart, &s->port); | 932 | for (i = 0; i < s->uart.nr; i++) { |
894 | 933 | uart_suspend_port(&s->uart, &s->p[i].port); | |
895 | mutex_lock(&s->max310x_mutex); | 934 | s->devtype->power(&s->p[i].port, 0); |
896 | 935 | } | |
897 | /* Enable sleep mode */ | ||
898 | regmap_update_bits(s->regmap, MAX310X_MODE1_REG, | ||
899 | MAX310X_MODE1_FORCESLEEP_BIT, | ||
900 | MAX310X_MODE1_FORCESLEEP_BIT); | ||
901 | |||
902 | mutex_unlock(&s->max310x_mutex); | ||
903 | |||
904 | if (s->pdata->suspend) | ||
905 | s->pdata->suspend(1); | ||
906 | 936 | ||
907 | return ret; | 937 | return 0; |
908 | } | 938 | } |
909 | 939 | ||
910 | static int max310x_resume(struct device *dev) | 940 | static int __maybe_unused max310x_resume(struct spi_device *spi) |
911 | { | 941 | { |
912 | struct max310x_port *s = dev_get_drvdata(dev); | 942 | struct max310x_port *s = dev_get_drvdata(&spi->dev); |
913 | 943 | int i; | |
914 | dev_dbg(dev, "Resume\n"); | ||
915 | |||
916 | if (s->pdata->suspend) | ||
917 | s->pdata->suspend(0); | ||
918 | |||
919 | mutex_lock(&s->max310x_mutex); | ||
920 | 944 | ||
921 | /* Disable sleep mode */ | 945 | for (i = 0; i < s->uart.nr; i++) { |
922 | regmap_update_bits(s->regmap, MAX310X_MODE1_REG, | 946 | s->devtype->power(&s->p[i].port, 1); |
923 | MAX310X_MODE1_FORCESLEEP_BIT, | 947 | uart_resume_port(&s->uart, &s->p[i].port); |
924 | 0); | 948 | } |
925 | |||
926 | max310x_wait_pll(s); | ||
927 | |||
928 | mutex_unlock(&s->max310x_mutex); | ||
929 | 949 | ||
930 | return uart_resume_port(&s->uart, &s->port); | 950 | return 0; |
931 | } | 951 | } |
932 | 952 | ||
933 | static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); | ||
934 | #define MAX310X_PM_OPS (&max310x_pm_ops) | ||
935 | |||
936 | #else | ||
937 | #define MAX310X_PM_OPS NULL | ||
938 | #endif | ||
939 | |||
940 | #ifdef CONFIG_GPIOLIB | 953 | #ifdef CONFIG_GPIOLIB |
941 | static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) | 954 | static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) |
942 | { | 955 | { |
943 | unsigned int val = 0; | 956 | unsigned int val; |
944 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | 957 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); |
958 | struct uart_port *port = &s->p[offset / 4].port; | ||
945 | 959 | ||
946 | mutex_lock(&s->max310x_mutex); | 960 | val = max310x_port_read(port, MAX310X_GPIODATA_REG); |
947 | regmap_read(s->regmap, MAX310X_GPIODATA_REG, &val); | ||
948 | mutex_unlock(&s->max310x_mutex); | ||
949 | 961 | ||
950 | return !!((val >> 4) & (1 << offset)); | 962 | return !!((val >> 4) & (1 << (offset % 4))); |
951 | } | 963 | } |
952 | 964 | ||
953 | static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | 965 | static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
954 | { | 966 | { |
955 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | 967 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); |
968 | struct uart_port *port = &s->p[offset / 4].port; | ||
956 | 969 | ||
957 | mutex_lock(&s->max310x_mutex); | 970 | max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), |
958 | regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ? | 971 | value ? 1 << (offset % 4) : 0); |
959 | 1 << offset : 0); | ||
960 | mutex_unlock(&s->max310x_mutex); | ||
961 | } | 972 | } |
962 | 973 | ||
963 | static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | 974 | static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
964 | { | 975 | { |
965 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | 976 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); |
977 | struct uart_port *port = &s->p[offset / 4].port; | ||
966 | 978 | ||
967 | mutex_lock(&s->max310x_mutex); | 979 | max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); |
968 | |||
969 | regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset, 0); | ||
970 | |||
971 | mutex_unlock(&s->max310x_mutex); | ||
972 | 980 | ||
973 | return 0; | 981 | return 0; |
974 | } | 982 | } |
@@ -977,74 +985,42 @@ static int max310x_gpio_direction_output(struct gpio_chip *chip, | |||
977 | unsigned offset, int value) | 985 | unsigned offset, int value) |
978 | { | 986 | { |
979 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | 987 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); |
988 | struct uart_port *port = &s->p[offset / 4].port; | ||
980 | 989 | ||
981 | mutex_lock(&s->max310x_mutex); | 990 | max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), |
982 | 991 | value ? 1 << (offset % 4) : 0); | |
983 | regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset, | 992 | max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), |
984 | 1 << offset); | 993 | 1 << (offset % 4)); |
985 | regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ? | ||
986 | 1 << offset : 0); | ||
987 | |||
988 | mutex_unlock(&s->max310x_mutex); | ||
989 | 994 | ||
990 | return 0; | 995 | return 0; |
991 | } | 996 | } |
992 | #endif | 997 | #endif |
993 | 998 | ||
994 | /* Generic platform data */ | 999 | static int max310x_probe(struct device *dev, int is_spi, |
995 | static struct max310x_pdata generic_plat_data = { | 1000 | struct max310x_devtype *devtype, int irq) |
996 | .driver_flags = MAX310X_EXT_CLK, | ||
997 | .uart_flags[0] = MAX310X_ECHO_SUPRESS, | ||
998 | .frequency = 26000000, | ||
999 | }; | ||
1000 | |||
1001 | static int max310x_probe(struct spi_device *spi) | ||
1002 | { | 1001 | { |
1003 | struct max310x_port *s; | 1002 | struct max310x_port *s; |
1004 | struct device *dev = &spi->dev; | 1003 | struct max310x_pdata *pdata = dev_get_platdata(dev); |
1005 | int chiptype = spi_get_device_id(spi)->driver_data; | 1004 | int i, ret, uartclk; |
1006 | struct max310x_pdata *pdata = dev->platform_data; | ||
1007 | unsigned int val = 0; | ||
1008 | int ret; | ||
1009 | 1005 | ||
1010 | /* Check for IRQ */ | 1006 | /* Check for IRQ */ |
1011 | if (spi->irq <= 0) { | 1007 | if (irq <= 0) { |
1012 | dev_err(dev, "No IRQ specified\n"); | 1008 | dev_err(dev, "No IRQ specified\n"); |
1013 | return -ENOTSUPP; | 1009 | return -ENOTSUPP; |
1014 | } | 1010 | } |
1015 | 1011 | ||
1012 | if (!pdata) { | ||
1013 | dev_err(dev, "No platform data supplied\n"); | ||
1014 | return -EINVAL; | ||
1015 | } | ||
1016 | |||
1016 | /* Alloc port structure */ | 1017 | /* Alloc port structure */ |
1017 | s = devm_kzalloc(dev, sizeof(struct max310x_port), GFP_KERNEL); | 1018 | s = devm_kzalloc(dev, sizeof(*s) + |
1019 | sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL); | ||
1018 | if (!s) { | 1020 | if (!s) { |
1019 | dev_err(dev, "Error allocating port structure\n"); | 1021 | dev_err(dev, "Error allocating port structure\n"); |
1020 | return -ENOMEM; | 1022 | return -ENOMEM; |
1021 | } | 1023 | } |
1022 | dev_set_drvdata(dev, s); | ||
1023 | |||
1024 | if (!pdata) { | ||
1025 | dev_warn(dev, "No platform data supplied, using defaults\n"); | ||
1026 | pdata = &generic_plat_data; | ||
1027 | } | ||
1028 | s->pdata = pdata; | ||
1029 | |||
1030 | /* Individual chip settings */ | ||
1031 | switch (chiptype) { | ||
1032 | case MAX310X_TYPE_MAX3107: | ||
1033 | s->name = "MAX3107"; | ||
1034 | s->nr_gpio = 4; | ||
1035 | s->uart.nr = 1; | ||
1036 | s->regcfg.max_register = 0x1f; | ||
1037 | break; | ||
1038 | case MAX310X_TYPE_MAX3108: | ||
1039 | s->name = "MAX3108"; | ||
1040 | s->nr_gpio = 4; | ||
1041 | s->uart.nr = 1; | ||
1042 | s->regcfg.max_register = 0x1e; | ||
1043 | break; | ||
1044 | default: | ||
1045 | dev_err(dev, "Unsupported chip type %i\n", chiptype); | ||
1046 | return -ENOTSUPP; | ||
1047 | } | ||
1048 | 1024 | ||
1049 | /* Check input frequency */ | 1025 | /* Check input frequency */ |
1050 | if ((pdata->driver_flags & MAX310X_EXT_CLK) && | 1026 | if ((pdata->driver_flags & MAX310X_EXT_CLK) && |
@@ -1055,13 +1031,11 @@ static int max310x_probe(struct spi_device *spi) | |||
1055 | ((pdata->frequency < 1000000) || (pdata->frequency > 4000000))) | 1031 | ((pdata->frequency < 1000000) || (pdata->frequency > 4000000))) |
1056 | goto err_freq; | 1032 | goto err_freq; |
1057 | 1033 | ||
1058 | mutex_init(&s->max310x_mutex); | 1034 | s->pdata = pdata; |
1035 | s->devtype = devtype; | ||
1036 | dev_set_drvdata(dev, s); | ||
1059 | 1037 | ||
1060 | /* Setup SPI bus */ | 1038 | mutex_init(&s->mutex); |
1061 | spi->mode = SPI_MODE_0; | ||
1062 | spi->bits_per_word = 8; | ||
1063 | spi->max_speed_hz = 26000000; | ||
1064 | spi_setup(spi); | ||
1065 | 1039 | ||
1066 | /* Setup regmap */ | 1040 | /* Setup regmap */ |
1067 | s->regcfg.reg_bits = 8; | 1041 | s->regcfg.reg_bits = 8; |
@@ -1069,109 +1043,100 @@ static int max310x_probe(struct spi_device *spi) | |||
1069 | s->regcfg.read_flag_mask = 0x00; | 1043 | s->regcfg.read_flag_mask = 0x00; |
1070 | s->regcfg.write_flag_mask = 0x80; | 1044 | s->regcfg.write_flag_mask = 0x80; |
1071 | s->regcfg.cache_type = REGCACHE_RBTREE; | 1045 | s->regcfg.cache_type = REGCACHE_RBTREE; |
1072 | s->regcfg.writeable_reg = max3107_8_reg_writeable; | 1046 | s->regcfg.writeable_reg = max310x_reg_writeable; |
1073 | s->regcfg.volatile_reg = max310x_reg_volatile; | 1047 | s->regcfg.volatile_reg = max310x_reg_volatile; |
1074 | s->regcfg.precious_reg = max310x_reg_precious; | 1048 | s->regcfg.precious_reg = max310x_reg_precious; |
1075 | s->regmap = devm_regmap_init_spi(spi, &s->regcfg); | 1049 | s->regcfg.max_register = devtype->nr * 0x20 - 1; |
1050 | |||
1051 | if (IS_ENABLED(CONFIG_SPI_MASTER) && is_spi) { | ||
1052 | struct spi_device *spi = to_spi_device(dev); | ||
1053 | |||
1054 | s->regmap = devm_regmap_init_spi(spi, &s->regcfg); | ||
1055 | } else | ||
1056 | return -ENOTSUPP; | ||
1057 | |||
1076 | if (IS_ERR(s->regmap)) { | 1058 | if (IS_ERR(s->regmap)) { |
1077 | ret = PTR_ERR(s->regmap); | ||
1078 | dev_err(dev, "Failed to initialize register map\n"); | 1059 | dev_err(dev, "Failed to initialize register map\n"); |
1079 | goto err_out; | 1060 | return PTR_ERR(s->regmap); |
1080 | } | ||
1081 | |||
1082 | /* Reset chip & check SPI function */ | ||
1083 | ret = regmap_write(s->regmap, MAX310X_MODE2_REG, MAX310X_MODE2_RST_BIT); | ||
1084 | if (ret) { | ||
1085 | dev_err(dev, "SPI transfer failed\n"); | ||
1086 | goto err_out; | ||
1087 | } | ||
1088 | /* Clear chip reset */ | ||
1089 | regmap_write(s->regmap, MAX310X_MODE2_REG, 0); | ||
1090 | |||
1091 | switch (chiptype) { | ||
1092 | case MAX310X_TYPE_MAX3107: | ||
1093 | /* Check REV ID to ensure we are talking to what we expect */ | ||
1094 | regmap_read(s->regmap, MAX3107_REVID_REG, &val); | ||
1095 | if (((val & MAX3107_REV_MASK) != MAX3107_REV_ID)) { | ||
1096 | dev_err(dev, "%s ID 0x%02x does not match\n", | ||
1097 | s->name, val); | ||
1098 | ret = -ENODEV; | ||
1099 | goto err_out; | ||
1100 | } | ||
1101 | break; | ||
1102 | case MAX310X_TYPE_MAX3108: | ||
1103 | /* MAX3108 have not REV ID register, we just check default value | ||
1104 | * from clocksource register to make sure everything works. | ||
1105 | */ | ||
1106 | regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); | ||
1107 | if (val != (MAX310X_CLKSRC_EXTCLK_BIT | | ||
1108 | MAX310X_CLKSRC_PLLBYP_BIT)) { | ||
1109 | dev_err(dev, "%s not present\n", s->name); | ||
1110 | ret = -ENODEV; | ||
1111 | goto err_out; | ||
1112 | } | ||
1113 | break; | ||
1114 | } | 1061 | } |
1115 | 1062 | ||
1116 | /* Board specific configure */ | 1063 | /* Board specific configure */ |
1117 | if (pdata->init) | 1064 | if (s->pdata->init) |
1118 | pdata->init(); | 1065 | s->pdata->init(); |
1119 | if (pdata->suspend) | 1066 | |
1120 | pdata->suspend(0); | 1067 | /* Check device to ensure we are talking to what we expect */ |
1121 | 1068 | ret = devtype->detect(dev); | |
1122 | /* Calculate referecne clock */ | 1069 | if (ret) |
1123 | s->uartclk = max310x_set_ref_clk(s); | 1070 | return ret; |
1124 | 1071 | ||
1125 | /* Disable all interrupts */ | 1072 | for (i = 0; i < devtype->nr; i++) { |
1126 | regmap_write(s->regmap, MAX310X_IRQEN_REG, 0); | 1073 | unsigned int offs = i << 5; |
1127 | 1074 | ||
1128 | /* Setup MODE1 register */ | 1075 | /* Reset port */ |
1129 | val = MAX310X_MODE1_IRQSEL_BIT; /* Enable IRQ pin */ | 1076 | regmap_write(s->regmap, MAX310X_MODE2_REG + offs, |
1130 | if (pdata->driver_flags & MAX310X_AUTOSLEEP) | 1077 | MAX310X_MODE2_RST_BIT); |
1131 | val = MAX310X_MODE1_AUTOSLEEP_BIT; | 1078 | /* Clear port reset */ |
1132 | regmap_write(s->regmap, MAX310X_MODE1_REG, val); | 1079 | regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); |
1133 | 1080 | ||
1134 | /* Setup interrupt */ | 1081 | /* Wait for port startup */ |
1135 | ret = devm_request_threaded_irq(dev, spi->irq, NULL, max310x_ist, | 1082 | do { |
1136 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | 1083 | regmap_read(s->regmap, |
1137 | dev_name(dev), s); | 1084 | MAX310X_BRGDIVLSB_REG + offs, &ret); |
1138 | if (ret) { | 1085 | } while (ret != 0x01); |
1139 | dev_err(dev, "Unable to reguest IRQ %i\n", spi->irq); | 1086 | |
1140 | goto err_out; | 1087 | regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs, |
1088 | MAX310X_MODE1_AUTOSLEEP_BIT, | ||
1089 | MAX310X_MODE1_AUTOSLEEP_BIT); | ||
1141 | } | 1090 | } |
1142 | 1091 | ||
1092 | uartclk = max310x_set_ref_clk(s); | ||
1093 | dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); | ||
1094 | |||
1143 | /* Register UART driver */ | 1095 | /* Register UART driver */ |
1144 | s->uart.owner = THIS_MODULE; | 1096 | s->uart.owner = THIS_MODULE; |
1145 | s->uart.driver_name = dev_name(dev); | ||
1146 | s->uart.dev_name = "ttyMAX"; | 1097 | s->uart.dev_name = "ttyMAX"; |
1147 | s->uart.major = MAX310X_MAJOR; | 1098 | s->uart.major = MAX310X_MAJOR; |
1148 | s->uart.minor = MAX310X_MINOR; | 1099 | s->uart.minor = MAX310X_MINOR; |
1100 | s->uart.nr = devtype->nr; | ||
1149 | ret = uart_register_driver(&s->uart); | 1101 | ret = uart_register_driver(&s->uart); |
1150 | if (ret) { | 1102 | if (ret) { |
1151 | dev_err(dev, "Registering UART driver failed\n"); | 1103 | dev_err(dev, "Registering UART driver failed\n"); |
1152 | goto err_out; | 1104 | return ret; |
1153 | } | 1105 | } |
1154 | 1106 | ||
1155 | /* Initialize workqueue for start TX */ | 1107 | for (i = 0; i < devtype->nr; i++) { |
1156 | s->wq = create_freezable_workqueue(dev_name(dev)); | 1108 | /* Initialize port data */ |
1157 | INIT_WORK(&s->tx_work, max310x_wq_proc); | 1109 | s->p[i].port.line = i; |
1158 | 1110 | s->p[i].port.dev = dev; | |
1159 | /* Initialize UART port data */ | 1111 | s->p[i].port.irq = irq; |
1160 | s->port.line = 0; | 1112 | s->p[i].port.type = PORT_MAX310X; |
1161 | s->port.dev = dev; | 1113 | s->p[i].port.fifosize = MAX310X_FIFO_SIZE; |
1162 | s->port.irq = spi->irq; | 1114 | s->p[i].port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE | |
1163 | s->port.type = PORT_MAX310X; | 1115 | UPF_LOW_LATENCY; |
1164 | s->port.fifosize = MAX310X_FIFO_SIZE; | 1116 | s->p[i].port.iotype = UPIO_PORT; |
1165 | s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; | 1117 | s->p[i].port.iobase = i * 0x20; |
1166 | s->port.iotype = UPIO_PORT; | 1118 | s->p[i].port.membase = (void __iomem *)~0; |
1167 | s->port.membase = (void __iomem *)0xffffffff; /* Bogus value */ | 1119 | s->p[i].port.uartclk = uartclk; |
1168 | s->port.uartclk = s->uartclk; | 1120 | s->p[i].port.ops = &max310x_ops; |
1169 | s->port.ops = &max310x_ops; | 1121 | /* Disable all interrupts */ |
1170 | uart_add_one_port(&s->uart, &s->port); | 1122 | max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); |
1123 | /* Clear IRQ status register */ | ||
1124 | max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); | ||
1125 | /* Enable IRQ pin */ | ||
1126 | max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG, | ||
1127 | MAX310X_MODE1_IRQSEL_BIT, | ||
1128 | MAX310X_MODE1_IRQSEL_BIT); | ||
1129 | /* Initialize queue for start TX */ | ||
1130 | INIT_WORK(&s->p[i].tx_work, max310x_wq_proc); | ||
1131 | /* Register port */ | ||
1132 | uart_add_one_port(&s->uart, &s->p[i].port); | ||
1133 | /* Go to suspend mode */ | ||
1134 | devtype->power(&s->p[i].port, 0); | ||
1135 | } | ||
1171 | 1136 | ||
1172 | #ifdef CONFIG_GPIOLIB | 1137 | #ifdef CONFIG_GPIOLIB |
1173 | /* Setup GPIO cotroller */ | 1138 | /* Setup GPIO cotroller */ |
1174 | if (pdata->gpio_base) { | 1139 | if (s->pdata->gpio_base) { |
1175 | s->gpio.owner = THIS_MODULE; | 1140 | s->gpio.owner = THIS_MODULE; |
1176 | s->gpio.dev = dev; | 1141 | s->gpio.dev = dev; |
1177 | s->gpio.label = dev_name(dev); | 1142 | s->gpio.label = dev_name(dev); |
@@ -1179,86 +1144,105 @@ static int max310x_probe(struct spi_device *spi) | |||
1179 | s->gpio.get = max310x_gpio_get; | 1144 | s->gpio.get = max310x_gpio_get; |
1180 | s->gpio.direction_output= max310x_gpio_direction_output; | 1145 | s->gpio.direction_output= max310x_gpio_direction_output; |
1181 | s->gpio.set = max310x_gpio_set; | 1146 | s->gpio.set = max310x_gpio_set; |
1182 | s->gpio.base = pdata->gpio_base; | 1147 | s->gpio.base = s->pdata->gpio_base; |
1183 | s->gpio.ngpio = s->nr_gpio; | 1148 | s->gpio.ngpio = devtype->nr * 4; |
1184 | s->gpio.can_sleep = 1; | 1149 | s->gpio.can_sleep = 1; |
1185 | if (gpiochip_add(&s->gpio)) { | 1150 | if (!gpiochip_add(&s->gpio)) |
1186 | /* Indicate that we should not call gpiochip_remove */ | 1151 | s->gpio_used = 1; |
1187 | s->gpio.base = 0; | ||
1188 | } | ||
1189 | } else | 1152 | } else |
1190 | dev_info(dev, "GPIO support not enabled\n"); | 1153 | dev_info(dev, "GPIO support not enabled\n"); |
1191 | #endif | 1154 | #endif |
1192 | 1155 | ||
1193 | /* Go to suspend mode */ | 1156 | /* Setup interrupt */ |
1194 | if (pdata->suspend) | 1157 | ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, |
1195 | pdata->suspend(1); | 1158 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
1159 | dev_name(dev), s); | ||
1160 | if (ret) { | ||
1161 | dev_err(dev, "Unable to reguest IRQ %i\n", irq); | ||
1162 | #ifdef CONFIG_GPIOLIB | ||
1163 | if (s->gpio_used) | ||
1164 | WARN_ON(gpiochip_remove(&s->gpio)); | ||
1165 | #endif | ||
1166 | } | ||
1196 | 1167 | ||
1197 | return 0; | 1168 | return ret; |
1198 | 1169 | ||
1199 | err_freq: | 1170 | err_freq: |
1200 | dev_err(dev, "Frequency parameter incorrect\n"); | 1171 | dev_err(dev, "Frequency parameter incorrect\n"); |
1201 | ret = -EINVAL; | 1172 | return -EINVAL; |
1202 | |||
1203 | err_out: | ||
1204 | dev_set_drvdata(dev, NULL); | ||
1205 | |||
1206 | return ret; | ||
1207 | } | 1173 | } |
1208 | 1174 | ||
1209 | static int max310x_remove(struct spi_device *spi) | 1175 | static int max310x_remove(struct device *dev) |
1210 | { | 1176 | { |
1211 | struct device *dev = &spi->dev; | ||
1212 | struct max310x_port *s = dev_get_drvdata(dev); | 1177 | struct max310x_port *s = dev_get_drvdata(dev); |
1213 | int ret = 0; | 1178 | int i, ret = 0; |
1214 | |||
1215 | dev_dbg(dev, "Removing port\n"); | ||
1216 | |||
1217 | devm_free_irq(dev, s->port.irq, s); | ||
1218 | 1179 | ||
1219 | destroy_workqueue(s->wq); | 1180 | for (i = 0; i < s->uart.nr; i++) { |
1220 | 1181 | cancel_work_sync(&s->p[i].tx_work); | |
1221 | uart_remove_one_port(&s->uart, &s->port); | 1182 | uart_remove_one_port(&s->uart, &s->p[i].port); |
1183 | s->devtype->power(&s->p[i].port, 0); | ||
1184 | } | ||
1222 | 1185 | ||
1223 | uart_unregister_driver(&s->uart); | 1186 | uart_unregister_driver(&s->uart); |
1224 | 1187 | ||
1225 | #ifdef CONFIG_GPIOLIB | 1188 | #ifdef CONFIG_GPIOLIB |
1226 | if (s->pdata->gpio_base) { | 1189 | if (s->gpio_used) |
1227 | ret = gpiochip_remove(&s->gpio); | 1190 | ret = gpiochip_remove(&s->gpio); |
1228 | if (ret) | ||
1229 | dev_err(dev, "Failed to remove gpio chip: %d\n", ret); | ||
1230 | } | ||
1231 | #endif | 1191 | #endif |
1232 | 1192 | ||
1233 | dev_set_drvdata(dev, NULL); | ||
1234 | |||
1235 | if (s->pdata->suspend) | ||
1236 | s->pdata->suspend(1); | ||
1237 | if (s->pdata->exit) | 1193 | if (s->pdata->exit) |
1238 | s->pdata->exit(); | 1194 | s->pdata->exit(); |
1239 | 1195 | ||
1240 | return ret; | 1196 | return ret; |
1241 | } | 1197 | } |
1242 | 1198 | ||
1199 | #ifdef CONFIG_SPI_MASTER | ||
1200 | static int max310x_spi_probe(struct spi_device *spi) | ||
1201 | { | ||
1202 | struct max310x_devtype *devtype = | ||
1203 | (struct max310x_devtype *)spi_get_device_id(spi)->driver_data; | ||
1204 | int ret; | ||
1205 | |||
1206 | /* Setup SPI bus */ | ||
1207 | spi->bits_per_word = 8; | ||
1208 | spi->mode = spi->mode ? : SPI_MODE_0; | ||
1209 | spi->max_speed_hz = spi->max_speed_hz ? : 26000000; | ||
1210 | ret = spi_setup(spi); | ||
1211 | if (ret) { | ||
1212 | dev_err(&spi->dev, "SPI setup failed\n"); | ||
1213 | return ret; | ||
1214 | } | ||
1215 | |||
1216 | return max310x_probe(&spi->dev, 1, devtype, spi->irq); | ||
1217 | } | ||
1218 | |||
1219 | static int max310x_spi_remove(struct spi_device *spi) | ||
1220 | { | ||
1221 | return max310x_remove(&spi->dev); | ||
1222 | } | ||
1223 | |||
1224 | static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); | ||
1225 | |||
1243 | static const struct spi_device_id max310x_id_table[] = { | 1226 | static const struct spi_device_id max310x_id_table[] = { |
1244 | { "max3107", MAX310X_TYPE_MAX3107 }, | 1227 | { "max3107", (kernel_ulong_t)&max3107_devtype, }, |
1245 | { "max3108", MAX310X_TYPE_MAX3108 }, | 1228 | { "max3108", (kernel_ulong_t)&max3108_devtype, }, |
1246 | { } | 1229 | { } |
1247 | }; | 1230 | }; |
1248 | MODULE_DEVICE_TABLE(spi, max310x_id_table); | 1231 | MODULE_DEVICE_TABLE(spi, max310x_id_table); |
1249 | 1232 | ||
1250 | static struct spi_driver max310x_driver = { | 1233 | static struct spi_driver max310x_uart_driver = { |
1251 | .driver = { | 1234 | .driver = { |
1252 | .name = "max310x", | 1235 | .name = MAX310X_NAME, |
1253 | .owner = THIS_MODULE, | 1236 | .owner = THIS_MODULE, |
1254 | .pm = MAX310X_PM_OPS, | 1237 | .pm = &max310x_pm_ops, |
1255 | }, | 1238 | }, |
1256 | .probe = max310x_probe, | 1239 | .probe = max310x_spi_probe, |
1257 | .remove = max310x_remove, | 1240 | .remove = max310x_spi_remove, |
1258 | .id_table = max310x_id_table, | 1241 | .id_table = max310x_id_table, |
1259 | }; | 1242 | }; |
1260 | module_spi_driver(max310x_driver); | 1243 | module_spi_driver(max310x_uart_driver); |
1244 | #endif | ||
1261 | 1245 | ||
1262 | MODULE_LICENSE("GPL v2"); | 1246 | MODULE_LICENSE("GPL"); |
1263 | MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); | 1247 | MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); |
1264 | MODULE_DESCRIPTION("MAX310X serial driver"); | 1248 | MODULE_DESCRIPTION("MAX310X serial driver"); |
diff --git a/include/linux/platform_data/max310x.h b/include/linux/platform_data/max310x.h index 91648bf5fc5c..1aec0b620ac3 100644 --- a/include/linux/platform_data/max310x.h +++ b/include/linux/platform_data/max310x.h | |||
@@ -42,9 +42,8 @@ | |||
42 | /* MAX310X platform data structure */ | 42 | /* MAX310X platform data structure */ |
43 | struct max310x_pdata { | 43 | struct max310x_pdata { |
44 | /* Flags global to driver */ | 44 | /* Flags global to driver */ |
45 | const u8 driver_flags:2; | 45 | const u8 driver_flags; |
46 | #define MAX310X_EXT_CLK (0x00000001) /* External clock enable */ | 46 | #define MAX310X_EXT_CLK (0x00000001) /* External clock enable */ |
47 | #define MAX310X_AUTOSLEEP (0x00000002) /* Enable AutoSleep mode */ | ||
48 | /* Flags global to UART port */ | 47 | /* Flags global to UART port */ |
49 | const u8 uart_flags[MAX310X_MAX_UARTS]; | 48 | const u8 uart_flags[MAX310X_MAX_UARTS]; |
50 | #define MAX310X_LOOPBACK (0x00000001) /* Loopback mode enable */ | 49 | #define MAX310X_LOOPBACK (0x00000001) /* Loopback mode enable */ |
@@ -60,8 +59,6 @@ struct max310x_pdata { | |||
60 | void (*init)(void); | 59 | void (*init)(void); |
61 | /* Called before finish */ | 60 | /* Called before finish */ |
62 | void (*exit)(void); | 61 | void (*exit)(void); |
63 | /* Suspend callback */ | ||
64 | void (*suspend)(int do_suspend); | ||
65 | }; | 62 | }; |
66 | 63 | ||
67 | #endif | 64 | #endif |