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-rw-r--r--drivers/video/matrox/g450_pll.c24
-rw-r--r--drivers/video/matrox/i2c-matroxfb.c6
-rw-r--r--drivers/video/matrox/matroxfb_DAC1064.c378
-rw-r--r--drivers/video/matrox/matroxfb_Ti3026.c94
-rw-r--r--drivers/video/matrox/matroxfb_accel.c86
-rw-r--r--drivers/video/matrox/matroxfb_base.c604
-rw-r--r--drivers/video/matrox/matroxfb_base.h27
-rw-r--r--drivers/video/matrox/matroxfb_crtc2.c130
-rw-r--r--drivers/video/matrox/matroxfb_g450.c80
-rw-r--r--drivers/video/matrox/matroxfb_maven.c38
-rw-r--r--drivers/video/matrox/matroxfb_misc.c210
-rw-r--r--drivers/video/matrox/matroxfb_misc.h2
12 files changed, 837 insertions, 842 deletions
diff --git a/drivers/video/matrox/g450_pll.c b/drivers/video/matrox/g450_pll.c
index d42346e7fdda..8c75427ad96f 100644
--- a/drivers/video/matrox/g450_pll.c
+++ b/drivers/video/matrox/g450_pll.c
@@ -30,7 +30,7 @@ static unsigned int g450_mnp2vco(CPMINFO unsigned int mnp) {
30 30
31 m = ((mnp >> 16) & 0x0FF) + 1; 31 m = ((mnp >> 16) & 0x0FF) + 1;
32 n = ((mnp >> 7) & 0x1FE) + 4; 32 n = ((mnp >> 7) & 0x1FE) + 4;
33 return (ACCESS_FBINFO(features).pll.ref_freq * n + (m >> 1)) / m; 33 return (minfo->features.pll.ref_freq * n + (m >> 1)) / m;
34} 34}
35 35
36unsigned int g450_mnp2f(CPMINFO unsigned int mnp) { 36unsigned int g450_mnp2f(CPMINFO unsigned int mnp) {
@@ -90,7 +90,7 @@ static unsigned int g450_nextpll(CPMINFO const struct matrox_pll_limits* pi, uns
90 } else { 90 } else {
91 m--; 91 m--;
92 } 92 }
93 n = ((tvco * (m+1) + ACCESS_FBINFO(features).pll.ref_freq) / (ACCESS_FBINFO(features).pll.ref_freq * 2)) - 2; 93 n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2;
94 } while (n < 0x03 || n > 0x7A); 94 } while (n < 0x03 || n > 0x7A);
95 return (m << 16) | (n << 8) | p; 95 return (m << 16) | (n << 8) | p;
96} 96}
@@ -333,7 +333,7 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
333 matroxfb_DAC_out(PMINFO M1064_XPIXCLKCTRL, tmp); 333 matroxfb_DAC_out(PMINFO M1064_XPIXCLKCTRL, tmp);
334 /* DVI PLL preferred for frequencies up to 334 /* DVI PLL preferred for frequencies up to
335 panel link max, standard PLL otherwise */ 335 panel link max, standard PLL otherwise */
336 if (fout >= MINFO->max_pixel_clock_panellink) 336 if (fout >= minfo->max_pixel_clock_panellink)
337 tmp = 0; 337 tmp = 0;
338 else tmp = 338 else tmp =
339 M1064_XDVICLKCTRL_DVIDATAPATHSEL | 339 M1064_XDVICLKCTRL_DVIDATAPATHSEL |
@@ -363,20 +363,20 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
363 } 363 }
364 mga_outb(M_MISC_REG, misc); 364 mga_outb(M_MISC_REG, misc);
365 } 365 }
366 pi = &ACCESS_FBINFO(limits.pixel); 366 pi = &minfo->limits.pixel;
367 ci = &ACCESS_FBINFO(cache.pixel); 367 ci = &minfo->cache.pixel;
368 break; 368 break;
369 case M_SYSTEM_PLL: 369 case M_SYSTEM_PLL:
370 { 370 {
371 u_int32_t opt; 371 u_int32_t opt;
372 372
373 pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, &opt); 373 pci_read_config_dword(minfo->pcidev, PCI_OPTION_REG, &opt);
374 if (!(opt & 0x20)) { 374 if (!(opt & 0x20)) {
375 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, opt | 0x20); 375 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, opt | 0x20);
376 } 376 }
377 } 377 }
378 pi = &ACCESS_FBINFO(limits.system); 378 pi = &minfo->limits.system;
379 ci = &ACCESS_FBINFO(cache.system); 379 ci = &minfo->cache.system;
380 break; 380 break;
381 case M_VIDEO_PLL: 381 case M_VIDEO_PLL:
382 { 382 {
@@ -395,8 +395,8 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
395 pixel_vco = g450_mnp2vco(PMINFO mnp); 395 pixel_vco = g450_mnp2vco(PMINFO mnp);
396 matroxfb_DAC_unlock_irqrestore(flags); 396 matroxfb_DAC_unlock_irqrestore(flags);
397 } 397 }
398 pi = &ACCESS_FBINFO(limits.video); 398 pi = &minfo->limits.video;
399 ci = &ACCESS_FBINFO(cache.video); 399 ci = &minfo->cache.video;
400 break; 400 break;
401 default: 401 default:
402 return -EINVAL; 402 return -EINVAL;
@@ -475,7 +475,7 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
475 mnp = g450_findworkingpll(PMINFO pll, mnparray, mnpcount); 475 mnp = g450_findworkingpll(PMINFO pll, mnparray, mnpcount);
476 g450_addcache(ci, mnparray[0], mnp); 476 g450_addcache(ci, mnparray[0], mnp);
477 } 477 }
478 updatehwstate_clk(&ACCESS_FBINFO(hw), mnp, pll); 478 updatehwstate_clk(&minfo->hw, mnp, pll);
479 matroxfb_DAC_unlock_irqrestore(flags); 479 matroxfb_DAC_unlock_irqrestore(flags);
480 return mnp; 480 return mnp;
481 } 481 }
diff --git a/drivers/video/matrox/i2c-matroxfb.c b/drivers/video/matrox/i2c-matroxfb.c
index c14e3e2212b3..cefabe818a12 100644
--- a/drivers/video/matrox/i2c-matroxfb.c
+++ b/drivers/video/matrox/i2c-matroxfb.c
@@ -112,7 +112,7 @@ static int i2c_bus_reg(struct i2c_bit_adapter* b, struct matrox_fb_info* minfo,
112 i2c_set_adapdata(&b->adapter, b); 112 i2c_set_adapdata(&b->adapter, b);
113 b->adapter.class = class; 113 b->adapter.class = class;
114 b->adapter.algo_data = &b->bac; 114 b->adapter.algo_data = &b->bac;
115 b->adapter.dev.parent = &ACCESS_FBINFO(pcidev)->dev; 115 b->adapter.dev.parent = &minfo->pcidev->dev;
116 b->bac = matrox_i2c_algo_template; 116 b->bac = matrox_i2c_algo_template;
117 b->bac.data = b; 117 b->bac.data = b;
118 err = i2c_bit_add_bus(&b->adapter); 118 err = i2c_bit_add_bus(&b->adapter);
@@ -153,7 +153,7 @@ static void* i2c_matroxfb_probe(struct matrox_fb_info* minfo) {
153 matroxfb_DAC_out(PMINFO DAC_XGENIOCTRL, 0x00); 153 matroxfb_DAC_out(PMINFO DAC_XGENIOCTRL, 0x00);
154 matroxfb_DAC_unlock_irqrestore(flags); 154 matroxfb_DAC_unlock_irqrestore(flags);
155 155
156 switch (ACCESS_FBINFO(chip)) { 156 switch (minfo->chip) {
157 case MGA_2064: 157 case MGA_2064:
158 case MGA_2164: 158 case MGA_2164:
159 err = i2c_bus_reg(&m2info->ddc1, minfo, 159 err = i2c_bus_reg(&m2info->ddc1, minfo,
@@ -168,7 +168,7 @@ static void* i2c_matroxfb_probe(struct matrox_fb_info* minfo) {
168 } 168 }
169 if (err) 169 if (err)
170 goto fail_ddc1; 170 goto fail_ddc1;
171 if (ACCESS_FBINFO(devflags.dualhead)) { 171 if (minfo->devflags.dualhead) {
172 err = i2c_bus_reg(&m2info->ddc2, minfo, 172 err = i2c_bus_reg(&m2info->ddc2, minfo,
173 DDC2_DATA, DDC2_CLK, 173 DDC2_DATA, DDC2_CLK,
174 "DDC:fb%u #1", I2C_CLASS_DDC); 174 "DDC:fb%u #1", I2C_CLASS_DDC);
diff --git a/drivers/video/matrox/matroxfb_DAC1064.c b/drivers/video/matrox/matroxfb_DAC1064.c
index a74e5da17aa0..7662a2862898 100644
--- a/drivers/video/matrox/matroxfb_DAC1064.c
+++ b/drivers/video/matrox/matroxfb_DAC1064.c
@@ -85,19 +85,19 @@ static void DAC1064_setpclk(WPMINFO unsigned long fout) {
85 85
86 DBG(__func__) 86 DBG(__func__)
87 87
88 DAC1064_calcclock(PMINFO fout, ACCESS_FBINFO(max_pixel_clock), &m, &n, &p); 88 DAC1064_calcclock(PMINFO fout, minfo->max_pixel_clock, &m, &n, &p);
89 ACCESS_FBINFO(hw).DACclk[0] = m; 89 minfo->hw.DACclk[0] = m;
90 ACCESS_FBINFO(hw).DACclk[1] = n; 90 minfo->hw.DACclk[1] = n;
91 ACCESS_FBINFO(hw).DACclk[2] = p; 91 minfo->hw.DACclk[2] = p;
92} 92}
93 93
94static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) { 94static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) {
95 u_int32_t mx; 95 u_int32_t mx;
96 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 96 struct matrox_hw_state *hw = &minfo->hw;
97 97
98 DBG(__func__) 98 DBG(__func__)
99 99
100 if (ACCESS_FBINFO(devflags.noinit)) { 100 if (minfo->devflags.noinit) {
101 /* read MCLK and give up... */ 101 /* read MCLK and give up... */
102 hw->DACclk[3] = inDAC1064(PMINFO DAC1064_XSYSPLLM); 102 hw->DACclk[3] = inDAC1064(PMINFO DAC1064_XSYSPLLM);
103 hw->DACclk[4] = inDAC1064(PMINFO DAC1064_XSYSPLLN); 103 hw->DACclk[4] = inDAC1064(PMINFO DAC1064_XSYSPLLN);
@@ -105,7 +105,7 @@ static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) {
105 return; 105 return;
106 } 106 }
107 mx = hw->MXoptionReg | 0x00000004; 107 mx = hw->MXoptionReg | 0x00000004;
108 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mx); 108 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
109 mx &= ~0x000000BB; 109 mx &= ~0x000000BB;
110 if (oscinfo & DAC1064_OPT_GDIV1) 110 if (oscinfo & DAC1064_OPT_GDIV1)
111 mx |= 0x00000008; 111 mx |= 0x00000008;
@@ -120,9 +120,9 @@ static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) {
120 120
121 /* powerup system PLL, select PCI clock */ 121 /* powerup system PLL, select PCI clock */
122 mx |= 0x00000020; 122 mx |= 0x00000020;
123 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mx); 123 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
124 mx &= ~0x00000004; 124 mx &= ~0x00000004;
125 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mx); 125 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
126 126
127 /* !!! you must not access device if MCLK is not running !!! 127 /* !!! you must not access device if MCLK is not running !!!
128 Doing so cause immediate PCI lockup :-( Maybe they should 128 Doing so cause immediate PCI lockup :-( Maybe they should
@@ -131,7 +131,7 @@ static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) {
131 perfect... */ 131 perfect... */
132 /* (bit 2 of PCI_OPTION_REG must be 0... and bits 0,1 must not 132 /* (bit 2 of PCI_OPTION_REG must be 0... and bits 0,1 must not
133 select PLL... because of PLL can be stopped at this time) */ 133 select PLL... because of PLL can be stopped at this time) */
134 DAC1064_calcclock(PMINFO fmem, ACCESS_FBINFO(max_pixel_clock), &m, &n, &p); 134 DAC1064_calcclock(PMINFO fmem, minfo->max_pixel_clock, &m, &n, &p);
135 outDAC1064(PMINFO DAC1064_XSYSPLLM, hw->DACclk[3] = m); 135 outDAC1064(PMINFO DAC1064_XSYSPLLM, hw->DACclk[3] = m);
136 outDAC1064(PMINFO DAC1064_XSYSPLLN, hw->DACclk[4] = n); 136 outDAC1064(PMINFO DAC1064_XSYSPLLN, hw->DACclk[4] = n);
137 outDAC1064(PMINFO DAC1064_XSYSPLLP, hw->DACclk[5] = p); 137 outDAC1064(PMINFO DAC1064_XSYSPLLP, hw->DACclk[5] = p);
@@ -147,9 +147,9 @@ static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) {
147 /* select specified system clock source */ 147 /* select specified system clock source */
148 mx |= oscinfo & DAC1064_OPT_SCLK_MASK; 148 mx |= oscinfo & DAC1064_OPT_SCLK_MASK;
149 } 149 }
150 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mx); 150 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
151 mx &= ~0x00000004; 151 mx &= ~0x00000004;
152 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mx); 152 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
153 hw->MXoptionReg = mx; 153 hw->MXoptionReg = mx;
154} 154}
155 155
@@ -157,19 +157,19 @@ static void DAC1064_setmclk(WPMINFO int oscinfo, unsigned long fmem) {
157static void g450_set_plls(WPMINFO2) { 157static void g450_set_plls(WPMINFO2) {
158 u_int32_t c2_ctl; 158 u_int32_t c2_ctl;
159 unsigned int pxc; 159 unsigned int pxc;
160 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 160 struct matrox_hw_state *hw = &minfo->hw;
161 int pixelmnp; 161 int pixelmnp;
162 int videomnp; 162 int videomnp;
163 163
164 c2_ctl = hw->crtc2.ctl & ~0x4007; /* Clear PLL + enable for CRTC2 */ 164 c2_ctl = hw->crtc2.ctl & ~0x4007; /* Clear PLL + enable for CRTC2 */
165 c2_ctl |= 0x0001; /* Enable CRTC2 */ 165 c2_ctl |= 0x0001; /* Enable CRTC2 */
166 hw->DACreg[POS1064_XPWRCTRL] &= ~0x02; /* Stop VIDEO PLL */ 166 hw->DACreg[POS1064_XPWRCTRL] &= ~0x02; /* Stop VIDEO PLL */
167 pixelmnp = ACCESS_FBINFO(crtc1).mnp; 167 pixelmnp = minfo->crtc1.mnp;
168 videomnp = ACCESS_FBINFO(crtc2).mnp; 168 videomnp = minfo->crtc2.mnp;
169 if (videomnp < 0) { 169 if (videomnp < 0) {
170 c2_ctl &= ~0x0001; /* Disable CRTC2 */ 170 c2_ctl &= ~0x0001; /* Disable CRTC2 */
171 hw->DACreg[POS1064_XPWRCTRL] &= ~0x10; /* Powerdown CRTC2 */ 171 hw->DACreg[POS1064_XPWRCTRL] &= ~0x10; /* Powerdown CRTC2 */
172 } else if (ACCESS_FBINFO(crtc2).pixclock == ACCESS_FBINFO(features).pll.ref_freq) { 172 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) {
173 c2_ctl |= 0x4002; /* Use reference directly */ 173 c2_ctl |= 0x4002; /* Use reference directly */
174 } else if (videomnp == pixelmnp) { 174 } else if (videomnp == pixelmnp) {
175 c2_ctl |= 0x0004; /* Use pixel PLL */ 175 c2_ctl |= 0x0004; /* Use pixel PLL */
@@ -200,11 +200,11 @@ static void g450_set_plls(WPMINFO2) {
200 mga_outl(0x3C10, c2_ctl); 200 mga_outl(0x3C10, c2_ctl);
201 } 201 }
202 202
203 pxc = ACCESS_FBINFO(crtc1).pixclock; 203 pxc = minfo->crtc1.pixclock;
204 if (pxc == 0 || ACCESS_FBINFO(outputs[2]).src == MATROXFB_SRC_CRTC2) { 204 if (pxc == 0 || minfo->outputs[2].src == MATROXFB_SRC_CRTC2) {
205 pxc = ACCESS_FBINFO(crtc2).pixclock; 205 pxc = minfo->crtc2.pixclock;
206 } 206 }
207 if (ACCESS_FBINFO(chip) == MGA_G550) { 207 if (minfo->chip == MGA_G550) {
208 if (pxc < 45000) { 208 if (pxc < 45000) {
209 hw->DACreg[POS1064_XPANMODE] = 0x00; /* 0-50 */ 209 hw->DACreg[POS1064_XPANMODE] = 0x00; /* 0-50 */
210 } else if (pxc < 55000) { 210 } else if (pxc < 55000) {
@@ -246,17 +246,17 @@ static void g450_set_plls(WPMINFO2) {
246#endif 246#endif
247 247
248void DAC1064_global_init(WPMINFO2) { 248void DAC1064_global_init(WPMINFO2) {
249 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 249 struct matrox_hw_state *hw = &minfo->hw;
250 250
251 hw->DACreg[POS1064_XMISCCTRL] &= M1064_XMISCCTRL_DAC_WIDTHMASK; 251 hw->DACreg[POS1064_XMISCCTRL] &= M1064_XMISCCTRL_DAC_WIDTHMASK;
252 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_LUT_EN; 252 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_LUT_EN;
253 hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_PLL; 253 hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_PLL;
254#ifdef CONFIG_FB_MATROX_G 254#ifdef CONFIG_FB_MATROX_G
255 if (ACCESS_FBINFO(devflags.g450dac)) { 255 if (minfo->devflags.g450dac) {
256 hw->DACreg[POS1064_XPWRCTRL] = 0x1F; /* powerup everything */ 256 hw->DACreg[POS1064_XPWRCTRL] = 0x1F; /* powerup everything */
257 hw->DACreg[POS1064_XOUTPUTCONN] = 0x00; /* disable outputs */ 257 hw->DACreg[POS1064_XOUTPUTCONN] = 0x00; /* disable outputs */
258 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN; 258 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN;
259 switch (ACCESS_FBINFO(outputs[0]).src) { 259 switch (minfo->outputs[0].src) {
260 case MATROXFB_SRC_CRTC1: 260 case MATROXFB_SRC_CRTC1:
261 case MATROXFB_SRC_CRTC2: 261 case MATROXFB_SRC_CRTC2:
262 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x01; /* enable output; CRTC1/2 selection is in CRTC2 ctl */ 262 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x01; /* enable output; CRTC1/2 selection is in CRTC2 ctl */
@@ -265,12 +265,12 @@ void DAC1064_global_init(WPMINFO2) {
265 hw->DACreg[POS1064_XMISCCTRL] &= ~M1064_XMISCCTRL_DAC_EN; 265 hw->DACreg[POS1064_XMISCCTRL] &= ~M1064_XMISCCTRL_DAC_EN;
266 break; 266 break;
267 } 267 }
268 switch (ACCESS_FBINFO(outputs[1]).src) { 268 switch (minfo->outputs[1].src) {
269 case MATROXFB_SRC_CRTC1: 269 case MATROXFB_SRC_CRTC1:
270 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x04; 270 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x04;
271 break; 271 break;
272 case MATROXFB_SRC_CRTC2: 272 case MATROXFB_SRC_CRTC2:
273 if (ACCESS_FBINFO(outputs[1]).mode == MATROXFB_OUTPUT_MODE_MONITOR) { 273 if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_MONITOR) {
274 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x08; 274 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x08;
275 } else { 275 } else {
276 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x0C; 276 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x0C;
@@ -280,7 +280,7 @@ void DAC1064_global_init(WPMINFO2) {
280 hw->DACreg[POS1064_XPWRCTRL] &= ~0x01; /* Poweroff DAC2 */ 280 hw->DACreg[POS1064_XPWRCTRL] &= ~0x01; /* Poweroff DAC2 */
281 break; 281 break;
282 } 282 }
283 switch (ACCESS_FBINFO(outputs[2]).src) { 283 switch (minfo->outputs[2].src) {
284 case MATROXFB_SRC_CRTC1: 284 case MATROXFB_SRC_CRTC1:
285 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x20; 285 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x20;
286 break; 286 break;
@@ -303,30 +303,30 @@ void DAC1064_global_init(WPMINFO2) {
303 } else 303 } else
304#endif 304#endif
305 { 305 {
306 if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC1) { 306 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) {
307 hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_EXT; 307 hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_EXT;
308 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_MAFC12; 308 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_MAFC12;
309 } else if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC2) { 309 } else if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) {
310 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_C2_MAFC12; 310 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_C2_MAFC12;
311 } else if (ACCESS_FBINFO(outputs[2]).src == MATROXFB_SRC_CRTC1) 311 } else if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1)
312 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_PANELLINK | G400_XMISCCTRL_VDO_MAFC12; 312 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_PANELLINK | G400_XMISCCTRL_VDO_MAFC12;
313 else 313 else
314 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_DIS; 314 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_DIS;
315 315
316 if (ACCESS_FBINFO(outputs[0]).src != MATROXFB_SRC_NONE) 316 if (minfo->outputs[0].src != MATROXFB_SRC_NONE)
317 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN; 317 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN;
318 } 318 }
319} 319}
320 320
321void DAC1064_global_restore(WPMINFO2) { 321void DAC1064_global_restore(WPMINFO2) {
322 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 322 struct matrox_hw_state *hw = &minfo->hw;
323 323
324 outDAC1064(PMINFO M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); 324 outDAC1064(PMINFO M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
325 outDAC1064(PMINFO M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]); 325 outDAC1064(PMINFO M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]);
326 if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG400) { 326 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) {
327 outDAC1064(PMINFO 0x20, 0x04); 327 outDAC1064(PMINFO 0x20, 0x04);
328 outDAC1064(PMINFO 0x1F, ACCESS_FBINFO(devflags.dfp_type)); 328 outDAC1064(PMINFO 0x1F, minfo->devflags.dfp_type);
329 if (ACCESS_FBINFO(devflags.g450dac)) { 329 if (minfo->devflags.g450dac) {
330 outDAC1064(PMINFO M1064_XSYNCCTRL, 0xCC); 330 outDAC1064(PMINFO M1064_XSYNCCTRL, 0xCC);
331 outDAC1064(PMINFO M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); 331 outDAC1064(PMINFO M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
332 outDAC1064(PMINFO M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]); 332 outDAC1064(PMINFO M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]);
@@ -336,18 +336,18 @@ void DAC1064_global_restore(WPMINFO2) {
336} 336}
337 337
338static int DAC1064_init_1(WPMINFO struct my_timming* m) { 338static int DAC1064_init_1(WPMINFO struct my_timming* m) {
339 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 339 struct matrox_hw_state *hw = &minfo->hw;
340 340
341 DBG(__func__) 341 DBG(__func__)
342 342
343 memcpy(hw->DACreg, MGA1064_DAC, sizeof(MGA1064_DAC_regs)); 343 memcpy(hw->DACreg, MGA1064_DAC, sizeof(MGA1064_DAC_regs));
344 switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) { 344 switch (minfo->fbcon.var.bits_per_pixel) {
345 /* case 4: not supported by MGA1064 DAC */ 345 /* case 4: not supported by MGA1064 DAC */
346 case 8: 346 case 8:
347 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_8BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; 347 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_8BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
348 break; 348 break;
349 case 16: 349 case 16:
350 if (ACCESS_FBINFO(fbcon).var.green.length == 5) 350 if (minfo->fbcon.var.green.length == 5)
351 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_15BPP_1BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; 351 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_15BPP_1BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
352 else 352 else
353 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_16BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; 353 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_16BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
@@ -361,7 +361,7 @@ static int DAC1064_init_1(WPMINFO struct my_timming* m) {
361 default: 361 default:
362 return 1; /* unsupported depth */ 362 return 1; /* unsupported depth */
363 } 363 }
364 hw->DACreg[POS1064_XVREFCTRL] = ACCESS_FBINFO(features.DAC1064.xvrefctrl); 364 hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl;
365 hw->DACreg[POS1064_XGENCTRL] &= ~M1064_XGENCTRL_SYNC_ON_GREEN_MASK; 365 hw->DACreg[POS1064_XGENCTRL] &= ~M1064_XGENCTRL_SYNC_ON_GREEN_MASK;
366 hw->DACreg[POS1064_XGENCTRL] |= (m->sync & FB_SYNC_ON_GREEN)?M1064_XGENCTRL_SYNC_ON_GREEN:M1064_XGENCTRL_NO_SYNC_ON_GREEN; 366 hw->DACreg[POS1064_XGENCTRL] |= (m->sync & FB_SYNC_ON_GREEN)?M1064_XGENCTRL_SYNC_ON_GREEN:M1064_XGENCTRL_NO_SYNC_ON_GREEN;
367 hw->DACreg[POS1064_XCURADDL] = 0; 367 hw->DACreg[POS1064_XCURADDL] = 0;
@@ -372,11 +372,11 @@ static int DAC1064_init_1(WPMINFO struct my_timming* m) {
372} 372}
373 373
374static int DAC1064_init_2(WPMINFO struct my_timming* m) { 374static int DAC1064_init_2(WPMINFO struct my_timming* m) {
375 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 375 struct matrox_hw_state *hw = &minfo->hw;
376 376
377 DBG(__func__) 377 DBG(__func__)
378 378
379 if (ACCESS_FBINFO(fbcon).var.bits_per_pixel > 16) { /* 256 entries */ 379 if (minfo->fbcon.var.bits_per_pixel > 16) { /* 256 entries */
380 int i; 380 int i;
381 381
382 for (i = 0; i < 256; i++) { 382 for (i = 0; i < 256; i++) {
@@ -384,8 +384,8 @@ static int DAC1064_init_2(WPMINFO struct my_timming* m) {
384 hw->DACpal[i * 3 + 1] = i; 384 hw->DACpal[i * 3 + 1] = i;
385 hw->DACpal[i * 3 + 2] = i; 385 hw->DACpal[i * 3 + 2] = i;
386 } 386 }
387 } else if (ACCESS_FBINFO(fbcon).var.bits_per_pixel > 8) { 387 } else if (minfo->fbcon.var.bits_per_pixel > 8) {
388 if (ACCESS_FBINFO(fbcon).var.green.length == 5) { /* 0..31, 128..159 */ 388 if (minfo->fbcon.var.green.length == 5) { /* 0..31, 128..159 */
389 int i; 389 int i;
390 390
391 for (i = 0; i < 32; i++) { 391 for (i = 0; i < 32; i++) {
@@ -414,7 +414,7 @@ static int DAC1064_init_2(WPMINFO struct my_timming* m) {
414} 414}
415 415
416static void DAC1064_restore_1(WPMINFO2) { 416static void DAC1064_restore_1(WPMINFO2) {
417 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 417 struct matrox_hw_state *hw = &minfo->hw;
418 418
419 CRITFLAGS 419 CRITFLAGS
420 420
@@ -453,12 +453,12 @@ static void DAC1064_restore_2(WPMINFO2) {
453#ifdef DEBUG 453#ifdef DEBUG
454 dprintk(KERN_DEBUG "DAC1064regs "); 454 dprintk(KERN_DEBUG "DAC1064regs ");
455 for (i = 0; i < sizeof(MGA1064_DAC_regs); i++) { 455 for (i = 0; i < sizeof(MGA1064_DAC_regs); i++) {
456 dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], ACCESS_FBINFO(hw).DACreg[i]); 456 dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]);
457 if ((i & 0x7) == 0x7) dprintk(KERN_DEBUG "continuing... "); 457 if ((i & 0x7) == 0x7) dprintk(KERN_DEBUG "continuing... ");
458 } 458 }
459 dprintk(KERN_DEBUG "DAC1064clk "); 459 dprintk(KERN_DEBUG "DAC1064clk ");
460 for (i = 0; i < 6; i++) 460 for (i = 0; i < 6; i++)
461 dprintk("C%02X=%02X ", i, ACCESS_FBINFO(hw).DACclk[i]); 461 dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]);
462 dprintk("\n"); 462 dprintk("\n");
463#endif 463#endif
464} 464}
@@ -475,7 +475,7 @@ static int m1064_compute(void* out, struct my_timming* m) {
475 CRITBEGIN 475 CRITBEGIN
476 476
477 for (i = 0; i < 3; i++) 477 for (i = 0; i < 3; i++)
478 outDAC1064(PMINFO M1064_XPIXPLLCM + i, ACCESS_FBINFO(hw).DACclk[i]); 478 outDAC1064(PMINFO M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]);
479 for (tmout = 500000; tmout; tmout--) { 479 for (tmout = 500000; tmout; tmout--) {
480 if (inDAC1064(PMINFO M1064_XPIXPLLSTAT) & 0x40) 480 if (inDAC1064(PMINFO M1064_XPIXPLLSTAT) & 0x40)
481 break; 481 break;
@@ -519,7 +519,7 @@ static struct matrox_altout g450out = {
519 519
520#ifdef CONFIG_FB_MATROX_MYSTIQUE 520#ifdef CONFIG_FB_MATROX_MYSTIQUE
521static int MGA1064_init(WPMINFO struct my_timming* m) { 521static int MGA1064_init(WPMINFO struct my_timming* m) {
522 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 522 struct matrox_hw_state *hw = &minfo->hw;
523 523
524 DBG(__func__) 524 DBG(__func__)
525 525
@@ -541,7 +541,7 @@ static int MGA1064_init(WPMINFO struct my_timming* m) {
541 541
542#ifdef CONFIG_FB_MATROX_G 542#ifdef CONFIG_FB_MATROX_G
543static int MGAG100_init(WPMINFO struct my_timming* m) { 543static int MGAG100_init(WPMINFO struct my_timming* m) {
544 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 544 struct matrox_hw_state *hw = &minfo->hw;
545 545
546 DBG(__func__) 546 DBG(__func__)
547 547
@@ -567,15 +567,15 @@ static void MGA1064_ramdac_init(WPMINFO2) {
567 567
568 DBG(__func__) 568 DBG(__func__)
569 569
570 /* ACCESS_FBINFO(features.DAC1064.vco_freq_min) = 120000; */ 570 /* minfo->features.DAC1064.vco_freq_min = 120000; */
571 ACCESS_FBINFO(features.pll.vco_freq_min) = 62000; 571 minfo->features.pll.vco_freq_min = 62000;
572 ACCESS_FBINFO(features.pll.ref_freq) = 14318; 572 minfo->features.pll.ref_freq = 14318;
573 ACCESS_FBINFO(features.pll.feed_div_min) = 100; 573 minfo->features.pll.feed_div_min = 100;
574 ACCESS_FBINFO(features.pll.feed_div_max) = 127; 574 minfo->features.pll.feed_div_max = 127;
575 ACCESS_FBINFO(features.pll.in_div_min) = 1; 575 minfo->features.pll.in_div_min = 1;
576 ACCESS_FBINFO(features.pll.in_div_max) = 31; 576 minfo->features.pll.in_div_max = 31;
577 ACCESS_FBINFO(features.pll.post_shift_max) = 3; 577 minfo->features.pll.post_shift_max = 3;
578 ACCESS_FBINFO(features.DAC1064.xvrefctrl) = DAC1064_XVREFCTRL_EXTERNAL; 578 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_EXTERNAL;
579 /* maybe cmdline MCLK= ?, doc says gclk=44MHz, mclk=66MHz... it was 55/83 with old values */ 579 /* maybe cmdline MCLK= ?, doc says gclk=44MHz, mclk=66MHz... it was 55/83 with old values */
580 DAC1064_setmclk(PMINFO DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PLL, 133333); 580 DAC1064_setmclk(PMINFO DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PLL, 133333);
581} 581}
@@ -638,7 +638,7 @@ static void MGAG100_setPixClock(CPMINFO int flags, int freq) {
638 638
639 DBG(__func__) 639 DBG(__func__)
640 640
641 DAC1064_calcclock(PMINFO freq, ACCESS_FBINFO(max_pixel_clock), &m, &n, &p); 641 DAC1064_calcclock(PMINFO freq, minfo->max_pixel_clock, &m, &n, &p);
642 MGAG100_progPixClock(PMINFO flags, m, n, p); 642 MGAG100_progPixClock(PMINFO flags, m, n, p);
643} 643}
644#endif 644#endif
@@ -648,30 +648,30 @@ static int MGA1064_preinit(WPMINFO2) {
648 static const int vxres_mystique[] = { 512, 640, 768, 800, 832, 960, 648 static const int vxres_mystique[] = { 512, 640, 768, 800, 832, 960,
649 1024, 1152, 1280, 1600, 1664, 1920, 649 1024, 1152, 1280, 1600, 1664, 1920,
650 2048, 0}; 650 2048, 0};
651 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 651 struct matrox_hw_state *hw = &minfo->hw;
652 652
653 DBG(__func__) 653 DBG(__func__)
654 654
655 /* ACCESS_FBINFO(capable.cfb4) = 0; ... preinitialized by 0 */ 655 /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */
656 ACCESS_FBINFO(capable.text) = 1; 656 minfo->capable.text = 1;
657 ACCESS_FBINFO(capable.vxres) = vxres_mystique; 657 minfo->capable.vxres = vxres_mystique;
658 658
659 ACCESS_FBINFO(outputs[0]).output = &m1064; 659 minfo->outputs[0].output = &m1064;
660 ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src; 660 minfo->outputs[0].src = minfo->outputs[0].default_src;
661 ACCESS_FBINFO(outputs[0]).data = MINFO; 661 minfo->outputs[0].data = minfo;
662 ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR; 662 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
663 663
664 if (ACCESS_FBINFO(devflags.noinit)) 664 if (minfo->devflags.noinit)
665 return 0; /* do not modify settings */ 665 return 0; /* do not modify settings */
666 hw->MXoptionReg &= 0xC0000100; 666 hw->MXoptionReg &= 0xC0000100;
667 hw->MXoptionReg |= 0x00094E20; 667 hw->MXoptionReg |= 0x00094E20;
668 if (ACCESS_FBINFO(devflags.novga)) 668 if (minfo->devflags.novga)
669 hw->MXoptionReg &= ~0x00000100; 669 hw->MXoptionReg &= ~0x00000100;
670 if (ACCESS_FBINFO(devflags.nobios)) 670 if (minfo->devflags.nobios)
671 hw->MXoptionReg &= ~0x40000000; 671 hw->MXoptionReg &= ~0x40000000;
672 if (ACCESS_FBINFO(devflags.nopciretry)) 672 if (minfo->devflags.nopciretry)
673 hw->MXoptionReg |= 0x20000000; 673 hw->MXoptionReg |= 0x20000000;
674 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); 674 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
675 mga_setr(M_SEQ_INDEX, 0x01, 0x20); 675 mga_setr(M_SEQ_INDEX, 0x01, 0x20);
676 mga_outl(M_CTLWTST, 0x00000000); 676 mga_outl(M_CTLWTST, 0x00000000);
677 udelay(200); 677 udelay(200);
@@ -692,14 +692,14 @@ static void MGA1064_reset(WPMINFO2) {
692#ifdef CONFIG_FB_MATROX_G 692#ifdef CONFIG_FB_MATROX_G
693static void g450_mclk_init(WPMINFO2) { 693static void g450_mclk_init(WPMINFO2) {
694 /* switch all clocks to PCI source */ 694 /* switch all clocks to PCI source */
695 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg | 4); 695 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
696 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION3_REG, ACCESS_FBINFO(values).reg.opt3 & ~0x00300C03); 696 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3 & ~0x00300C03);
697 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); 697 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
698 698
699 if (((ACCESS_FBINFO(values).reg.opt3 & 0x000003) == 0x000003) || 699 if (((minfo->values.reg.opt3 & 0x000003) == 0x000003) ||
700 ((ACCESS_FBINFO(values).reg.opt3 & 0x000C00) == 0x000C00) || 700 ((minfo->values.reg.opt3 & 0x000C00) == 0x000C00) ||
701 ((ACCESS_FBINFO(values).reg.opt3 & 0x300000) == 0x300000)) { 701 ((minfo->values.reg.opt3 & 0x300000) == 0x300000)) {
702 matroxfb_g450_setclk(PMINFO ACCESS_FBINFO(values.pll.video), M_VIDEO_PLL); 702 matroxfb_g450_setclk(PMINFO minfo->values.pll.video, M_VIDEO_PLL);
703 } else { 703 } else {
704 unsigned long flags; 704 unsigned long flags;
705 unsigned int pwr; 705 unsigned int pwr;
@@ -709,53 +709,53 @@ static void g450_mclk_init(WPMINFO2) {
709 outDAC1064(PMINFO M1064_XPWRCTRL, pwr); 709 outDAC1064(PMINFO M1064_XPWRCTRL, pwr);
710 matroxfb_DAC_unlock_irqrestore(flags); 710 matroxfb_DAC_unlock_irqrestore(flags);
711 } 711 }
712 matroxfb_g450_setclk(PMINFO ACCESS_FBINFO(values.pll.system), M_SYSTEM_PLL); 712 matroxfb_g450_setclk(PMINFO minfo->values.pll.system, M_SYSTEM_PLL);
713 713
714 /* switch clocks to their real PLL source(s) */ 714 /* switch clocks to their real PLL source(s) */
715 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg | 4); 715 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
716 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION3_REG, ACCESS_FBINFO(values).reg.opt3); 716 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3);
717 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); 717 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
718 718
719} 719}
720 720
721static void g450_memory_init(WPMINFO2) { 721static void g450_memory_init(WPMINFO2) {
722 /* disable memory refresh */ 722 /* disable memory refresh */
723 ACCESS_FBINFO(hw).MXoptionReg &= ~0x001F8000; 723 minfo->hw.MXoptionReg &= ~0x001F8000;
724 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); 724 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
725 725
726 /* set memory interface parameters */ 726 /* set memory interface parameters */
727 ACCESS_FBINFO(hw).MXoptionReg &= ~0x00207E00; 727 minfo->hw.MXoptionReg &= ~0x00207E00;
728 ACCESS_FBINFO(hw).MXoptionReg |= 0x00207E00 & ACCESS_FBINFO(values).reg.opt; 728 minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt;
729 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); 729 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
730 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, ACCESS_FBINFO(values).reg.opt2); 730 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2);
731 731
732 mga_outl(M_CTLWTST, ACCESS_FBINFO(values).reg.mctlwtst); 732 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
733 733
734 /* first set up memory interface with disabled memory interface clocks */ 734 /* first set up memory interface with disabled memory interface clocks */
735 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_MEMMISC_REG, ACCESS_FBINFO(values).reg.memmisc & ~0x80000000U); 735 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U);
736 mga_outl(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk); 736 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
737 mga_outl(M_MACCESS, ACCESS_FBINFO(values).reg.maccess); 737 mga_outl(M_MACCESS, minfo->values.reg.maccess);
738 /* start memory clocks */ 738 /* start memory clocks */
739 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_MEMMISC_REG, ACCESS_FBINFO(values).reg.memmisc | 0x80000000U); 739 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U);
740 740
741 udelay(200); 741 udelay(200);
742 742
743 if (ACCESS_FBINFO(values).memory.ddr && (!ACCESS_FBINFO(values).memory.emrswen || !ACCESS_FBINFO(values).memory.dll)) { 743 if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) {
744 mga_outl(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk & ~0x1000); 744 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000);
745 } 745 }
746 mga_outl(M_MACCESS, ACCESS_FBINFO(values).reg.maccess | 0x8000); 746 mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000);
747 747
748 udelay(200); 748 udelay(200);
749 749
750 ACCESS_FBINFO(hw).MXoptionReg |= 0x001F8000 & ACCESS_FBINFO(values).reg.opt; 750 minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt;
751 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); 751 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
752 752
753 /* value is written to memory chips only if old != new */ 753 /* value is written to memory chips only if old != new */
754 mga_outl(M_PLNWT, 0); 754 mga_outl(M_PLNWT, 0);
755 mga_outl(M_PLNWT, ~0); 755 mga_outl(M_PLNWT, ~0);
756 756
757 if (ACCESS_FBINFO(values).reg.mctlwtst != ACCESS_FBINFO(values).reg.mctlwtst_core) { 757 if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) {
758 mga_outl(M_CTLWTST, ACCESS_FBINFO(values).reg.mctlwtst_core); 758 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core);
759 } 759 }
760 760
761} 761}
@@ -765,17 +765,17 @@ static void g450_preinit(WPMINFO2) {
765 u_int8_t curctl; 765 u_int8_t curctl;
766 u_int8_t c1ctl; 766 u_int8_t c1ctl;
767 767
768 /* ACCESS_FBINFO(hw).MXoptionReg = minfo->values.reg.opt; */ 768 /* minfo->hw.MXoptionReg = minfo->values.reg.opt; */
769 ACCESS_FBINFO(hw).MXoptionReg &= 0xC0000100; 769 minfo->hw.MXoptionReg &= 0xC0000100;
770 ACCESS_FBINFO(hw).MXoptionReg |= 0x00000020; 770 minfo->hw.MXoptionReg |= 0x00000020;
771 if (ACCESS_FBINFO(devflags.novga)) 771 if (minfo->devflags.novga)
772 ACCESS_FBINFO(hw).MXoptionReg &= ~0x00000100; 772 minfo->hw.MXoptionReg &= ~0x00000100;
773 if (ACCESS_FBINFO(devflags.nobios)) 773 if (minfo->devflags.nobios)
774 ACCESS_FBINFO(hw).MXoptionReg &= ~0x40000000; 774 minfo->hw.MXoptionReg &= ~0x40000000;
775 if (ACCESS_FBINFO(devflags.nopciretry)) 775 if (minfo->devflags.nopciretry)
776 ACCESS_FBINFO(hw).MXoptionReg |= 0x20000000; 776 minfo->hw.MXoptionReg |= 0x20000000;
777 ACCESS_FBINFO(hw).MXoptionReg |= ACCESS_FBINFO(values).reg.opt & 0x03400040; 777 minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040;
778 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); 778 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
779 779
780 /* Init system clocks */ 780 /* Init system clocks */
781 781
@@ -812,7 +812,7 @@ static int MGAG100_preinit(WPMINFO2) {
812 static const int vxres_g100[] = { 512, 640, 768, 800, 832, 960, 812 static const int vxres_g100[] = { 512, 640, 768, 800, 832, 960,
813 1024, 1152, 1280, 1600, 1664, 1920, 813 1024, 1152, 1280, 1600, 1664, 1920,
814 2048, 0}; 814 2048, 0};
815 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 815 struct matrox_hw_state *hw = &minfo->hw;
816 816
817 u_int32_t reg50; 817 u_int32_t reg50;
818#if 0 818#if 0
@@ -822,68 +822,68 @@ static int MGAG100_preinit(WPMINFO2) {
822 DBG(__func__) 822 DBG(__func__)
823 823
824 /* there are some instabilities if in_div > 19 && vco < 61000 */ 824 /* there are some instabilities if in_div > 19 && vco < 61000 */
825 if (ACCESS_FBINFO(devflags.g450dac)) { 825 if (minfo->devflags.g450dac) {
826 ACCESS_FBINFO(features.pll.vco_freq_min) = 130000; /* my sample: >118 */ 826 minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */
827 } else { 827 } else {
828 ACCESS_FBINFO(features.pll.vco_freq_min) = 62000; 828 minfo->features.pll.vco_freq_min = 62000;
829 } 829 }
830 if (!ACCESS_FBINFO(features.pll.ref_freq)) { 830 if (!minfo->features.pll.ref_freq) {
831 ACCESS_FBINFO(features.pll.ref_freq) = 27000; 831 minfo->features.pll.ref_freq = 27000;
832 } 832 }
833 ACCESS_FBINFO(features.pll.feed_div_min) = 7; 833 minfo->features.pll.feed_div_min = 7;
834 ACCESS_FBINFO(features.pll.feed_div_max) = 127; 834 minfo->features.pll.feed_div_max = 127;
835 ACCESS_FBINFO(features.pll.in_div_min) = 1; 835 minfo->features.pll.in_div_min = 1;
836 ACCESS_FBINFO(features.pll.in_div_max) = 31; 836 minfo->features.pll.in_div_max = 31;
837 ACCESS_FBINFO(features.pll.post_shift_max) = 3; 837 minfo->features.pll.post_shift_max = 3;
838 ACCESS_FBINFO(features.DAC1064.xvrefctrl) = DAC1064_XVREFCTRL_G100_DEFAULT; 838 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_G100_DEFAULT;
839 /* ACCESS_FBINFO(capable.cfb4) = 0; ... preinitialized by 0 */ 839 /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */
840 ACCESS_FBINFO(capable.text) = 1; 840 minfo->capable.text = 1;
841 ACCESS_FBINFO(capable.vxres) = vxres_g100; 841 minfo->capable.vxres = vxres_g100;
842 ACCESS_FBINFO(capable.plnwt) = ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG100 842 minfo->capable.plnwt = minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100
843 ? ACCESS_FBINFO(devflags.sgram) : 1; 843 ? minfo->devflags.sgram : 1;
844 844
845#ifdef CONFIG_FB_MATROX_G 845#ifdef CONFIG_FB_MATROX_G
846 if (ACCESS_FBINFO(devflags.g450dac)) { 846 if (minfo->devflags.g450dac) {
847 ACCESS_FBINFO(outputs[0]).output = &g450out; 847 minfo->outputs[0].output = &g450out;
848 } else 848 } else
849#endif 849#endif
850 { 850 {
851 ACCESS_FBINFO(outputs[0]).output = &m1064; 851 minfo->outputs[0].output = &m1064;
852 } 852 }
853 ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src; 853 minfo->outputs[0].src = minfo->outputs[0].default_src;
854 ACCESS_FBINFO(outputs[0]).data = MINFO; 854 minfo->outputs[0].data = minfo;
855 ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR; 855 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
856 856
857 if (ACCESS_FBINFO(devflags.g450dac)) { 857 if (minfo->devflags.g450dac) {
858 /* we must do this always, BIOS does not do it for us 858 /* we must do this always, BIOS does not do it for us
859 and accelerator dies without it */ 859 and accelerator dies without it */
860 mga_outl(0x1C0C, 0); 860 mga_outl(0x1C0C, 0);
861 } 861 }
862 if (ACCESS_FBINFO(devflags.noinit)) 862 if (minfo->devflags.noinit)
863 return 0; 863 return 0;
864 if (ACCESS_FBINFO(devflags.g450dac)) { 864 if (minfo->devflags.g450dac) {
865 g450_preinit(PMINFO2); 865 g450_preinit(PMINFO2);
866 return 0; 866 return 0;
867 } 867 }
868 hw->MXoptionReg &= 0xC0000100; 868 hw->MXoptionReg &= 0xC0000100;
869 hw->MXoptionReg |= 0x00000020; 869 hw->MXoptionReg |= 0x00000020;
870 if (ACCESS_FBINFO(devflags.novga)) 870 if (minfo->devflags.novga)
871 hw->MXoptionReg &= ~0x00000100; 871 hw->MXoptionReg &= ~0x00000100;
872 if (ACCESS_FBINFO(devflags.nobios)) 872 if (minfo->devflags.nobios)
873 hw->MXoptionReg &= ~0x40000000; 873 hw->MXoptionReg &= ~0x40000000;
874 if (ACCESS_FBINFO(devflags.nopciretry)) 874 if (minfo->devflags.nopciretry)
875 hw->MXoptionReg |= 0x20000000; 875 hw->MXoptionReg |= 0x20000000;
876 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); 876 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
877 DAC1064_setmclk(PMINFO DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PCI, 133333); 877 DAC1064_setmclk(PMINFO DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PCI, 133333);
878 878
879 if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG100) { 879 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100) {
880 pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, &reg50); 880 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, &reg50);
881 reg50 &= ~0x3000; 881 reg50 &= ~0x3000;
882 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, reg50); 882 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
883 883
884 hw->MXoptionReg |= 0x1080; 884 hw->MXoptionReg |= 0x1080;
885 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); 885 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
886 mga_outl(M_CTLWTST, ACCESS_FBINFO(values).reg.mctlwtst); 886 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
887 udelay(100); 887 udelay(100);
888 mga_outb(0x1C05, 0x00); 888 mga_outb(0x1C05, 0x00);
889 mga_outb(0x1C05, 0x80); 889 mga_outb(0x1C05, 0x80);
@@ -893,68 +893,68 @@ static int MGAG100_preinit(WPMINFO2) {
893 udelay(100); 893 udelay(100);
894 reg50 &= ~0xFF; 894 reg50 &= ~0xFF;
895 reg50 |= 0x07; 895 reg50 |= 0x07;
896 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, reg50); 896 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
897 /* it should help with G100 */ 897 /* it should help with G100 */
898 mga_outb(M_GRAPHICS_INDEX, 6); 898 mga_outb(M_GRAPHICS_INDEX, 6);
899 mga_outb(M_GRAPHICS_DATA, (mga_inb(M_GRAPHICS_DATA) & 3) | 4); 899 mga_outb(M_GRAPHICS_DATA, (mga_inb(M_GRAPHICS_DATA) & 3) | 4);
900 mga_setr(M_EXTVGA_INDEX, 0x03, 0x81); 900 mga_setr(M_EXTVGA_INDEX, 0x03, 0x81);
901 mga_setr(M_EXTVGA_INDEX, 0x04, 0x00); 901 mga_setr(M_EXTVGA_INDEX, 0x04, 0x00);
902 mga_writeb(ACCESS_FBINFO(video.vbase), 0x0000, 0xAA); 902 mga_writeb(minfo->video.vbase, 0x0000, 0xAA);
903 mga_writeb(ACCESS_FBINFO(video.vbase), 0x0800, 0x55); 903 mga_writeb(minfo->video.vbase, 0x0800, 0x55);
904 mga_writeb(ACCESS_FBINFO(video.vbase), 0x4000, 0x55); 904 mga_writeb(minfo->video.vbase, 0x4000, 0x55);
905#if 0 905#if 0
906 if (mga_readb(ACCESS_FBINFO(video.vbase), 0x0000) != 0xAA) { 906 if (mga_readb(minfo->video.vbase, 0x0000) != 0xAA) {
907 hw->MXoptionReg &= ~0x1000; 907 hw->MXoptionReg &= ~0x1000;
908 } 908 }
909#endif 909#endif
910 hw->MXoptionReg |= 0x00078020; 910 hw->MXoptionReg |= 0x00078020;
911 } else if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG200) { 911 } else if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG200) {
912 pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, &reg50); 912 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, &reg50);
913 reg50 &= ~0x3000; 913 reg50 &= ~0x3000;
914 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, reg50); 914 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
915 915
916 if (ACCESS_FBINFO(devflags.memtype) == -1) 916 if (minfo->devflags.memtype == -1)
917 hw->MXoptionReg |= ACCESS_FBINFO(values).reg.opt & 0x1C00; 917 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
918 else 918 else
919 hw->MXoptionReg |= (ACCESS_FBINFO(devflags.memtype) & 7) << 10; 919 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
920 if (ACCESS_FBINFO(devflags.sgram)) 920 if (minfo->devflags.sgram)
921 hw->MXoptionReg |= 0x4000; 921 hw->MXoptionReg |= 0x4000;
922 mga_outl(M_CTLWTST, ACCESS_FBINFO(values).reg.mctlwtst); 922 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
923 mga_outl(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk); 923 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
924 udelay(200); 924 udelay(200);
925 mga_outl(M_MACCESS, 0x00000000); 925 mga_outl(M_MACCESS, 0x00000000);
926 mga_outl(M_MACCESS, 0x00008000); 926 mga_outl(M_MACCESS, 0x00008000);
927 udelay(100); 927 udelay(100);
928 mga_outw(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk); 928 mga_outw(M_MEMRDBK, minfo->values.reg.memrdbk);
929 hw->MXoptionReg |= 0x00078020; 929 hw->MXoptionReg |= 0x00078020;
930 } else { 930 } else {
931 pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, &reg50); 931 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, &reg50);
932 reg50 &= ~0x00000100; 932 reg50 &= ~0x00000100;
933 reg50 |= 0x00000000; 933 reg50 |= 0x00000000;
934 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION2_REG, reg50); 934 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
935 935
936 if (ACCESS_FBINFO(devflags.memtype) == -1) 936 if (minfo->devflags.memtype == -1)
937 hw->MXoptionReg |= ACCESS_FBINFO(values).reg.opt & 0x1C00; 937 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
938 else 938 else
939 hw->MXoptionReg |= (ACCESS_FBINFO(devflags.memtype) & 7) << 10; 939 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
940 if (ACCESS_FBINFO(devflags.sgram)) 940 if (minfo->devflags.sgram)
941 hw->MXoptionReg |= 0x4000; 941 hw->MXoptionReg |= 0x4000;
942 mga_outl(M_CTLWTST, ACCESS_FBINFO(values).reg.mctlwtst); 942 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
943 mga_outl(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk); 943 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
944 udelay(200); 944 udelay(200);
945 mga_outl(M_MACCESS, 0x00000000); 945 mga_outl(M_MACCESS, 0x00000000);
946 mga_outl(M_MACCESS, 0x00008000); 946 mga_outl(M_MACCESS, 0x00008000);
947 udelay(100); 947 udelay(100);
948 mga_outl(M_MEMRDBK, ACCESS_FBINFO(values).reg.memrdbk); 948 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
949 hw->MXoptionReg |= 0x00040020; 949 hw->MXoptionReg |= 0x00040020;
950 } 950 }
951 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); 951 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
952 return 0; 952 return 0;
953} 953}
954 954
955static void MGAG100_reset(WPMINFO2) { 955static void MGAG100_reset(WPMINFO2) {
956 u_int8_t b; 956 u_int8_t b;
957 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 957 struct matrox_hw_state *hw = &minfo->hw;
958 958
959 DBG(__func__) 959 DBG(__func__)
960 960
@@ -964,22 +964,22 @@ static void MGAG100_reset(WPMINFO2) {
964 964
965 find 1014/22 (IBM/82351); /* if found and bridging Matrox, do some strange stuff */ 965 find 1014/22 (IBM/82351); /* if found and bridging Matrox, do some strange stuff */
966 pci_read_config_byte(ibm, PCI_SECONDARY_BUS, &b); 966 pci_read_config_byte(ibm, PCI_SECONDARY_BUS, &b);
967 if (b == ACCESS_FBINFO(pcidev)->bus->number) { 967 if (b == minfo->pcidev->bus->number) {
968 pci_write_config_byte(ibm, PCI_COMMAND+1, 0); /* disable back-to-back & SERR */ 968 pci_write_config_byte(ibm, PCI_COMMAND+1, 0); /* disable back-to-back & SERR */
969 pci_write_config_byte(ibm, 0x41, 0xF4); /* ??? */ 969 pci_write_config_byte(ibm, 0x41, 0xF4); /* ??? */
970 pci_write_config_byte(ibm, PCI_IO_BASE, 0xF0); /* ??? */ 970 pci_write_config_byte(ibm, PCI_IO_BASE, 0xF0); /* ??? */
971 pci_write_config_byte(ibm, PCI_IO_LIMIT, 0x00); /* ??? */ 971 pci_write_config_byte(ibm, PCI_IO_LIMIT, 0x00); /* ??? */
972 } 972 }
973#endif 973#endif
974 if (!ACCESS_FBINFO(devflags.noinit)) { 974 if (!minfo->devflags.noinit) {
975 if (x7AF4 & 8) { 975 if (x7AF4 & 8) {
976 hw->MXoptionReg |= 0x40; /* FIXME... */ 976 hw->MXoptionReg |= 0x40; /* FIXME... */
977 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); 977 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
978 } 978 }
979 mga_setr(M_EXTVGA_INDEX, 0x06, 0x00); 979 mga_setr(M_EXTVGA_INDEX, 0x06, 0x00);
980 } 980 }
981 } 981 }
982 if (ACCESS_FBINFO(devflags.g450dac)) { 982 if (minfo->devflags.g450dac) {
983 /* either leave MCLK as is... or they were set in preinit */ 983 /* either leave MCLK as is... or they were set in preinit */
984 hw->DACclk[3] = inDAC1064(PMINFO DAC1064_XSYSPLLM); 984 hw->DACclk[3] = inDAC1064(PMINFO DAC1064_XSYSPLLM);
985 hw->DACclk[4] = inDAC1064(PMINFO DAC1064_XSYSPLLN); 985 hw->DACclk[4] = inDAC1064(PMINFO DAC1064_XSYSPLLN);
@@ -987,14 +987,14 @@ static void MGAG100_reset(WPMINFO2) {
987 } else { 987 } else {
988 DAC1064_setmclk(PMINFO DAC1064_OPT_RESERVED | DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV1 | DAC1064_OPT_SCLK_PLL, 133333); 988 DAC1064_setmclk(PMINFO DAC1064_OPT_RESERVED | DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV1 | DAC1064_OPT_SCLK_PLL, 133333);
989 } 989 }
990 if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG400) { 990 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) {
991 if (ACCESS_FBINFO(devflags.dfp_type) == -1) { 991 if (minfo->devflags.dfp_type == -1) {
992 ACCESS_FBINFO(devflags.dfp_type) = inDAC1064(PMINFO 0x1F); 992 minfo->devflags.dfp_type = inDAC1064(PMINFO 0x1F);
993 } 993 }
994 } 994 }
995 if (ACCESS_FBINFO(devflags.noinit)) 995 if (minfo->devflags.noinit)
996 return; 996 return;
997 if (ACCESS_FBINFO(devflags.g450dac)) { 997 if (minfo->devflags.g450dac) {
998 } else { 998 } else {
999 MGAG100_setPixClock(PMINFO 4, 25175); 999 MGAG100_setPixClock(PMINFO 4, 25175);
1000 MGAG100_setPixClock(PMINFO 5, 28322); 1000 MGAG100_setPixClock(PMINFO 5, 28322);
@@ -1011,7 +1011,7 @@ static void MGAG100_reset(WPMINFO2) {
1011#ifdef CONFIG_FB_MATROX_MYSTIQUE 1011#ifdef CONFIG_FB_MATROX_MYSTIQUE
1012static void MGA1064_restore(WPMINFO2) { 1012static void MGA1064_restore(WPMINFO2) {
1013 int i; 1013 int i;
1014 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 1014 struct matrox_hw_state *hw = &minfo->hw;
1015 1015
1016 CRITFLAGS 1016 CRITFLAGS
1017 1017
@@ -1019,7 +1019,7 @@ static void MGA1064_restore(WPMINFO2) {
1019 1019
1020 CRITBEGIN 1020 CRITBEGIN
1021 1021
1022 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); 1022 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1023 mga_outb(M_IEN, 0x00); 1023 mga_outb(M_IEN, 0x00);
1024 mga_outb(M_CACHEFLUSH, 0x00); 1024 mga_outb(M_CACHEFLUSH, 0x00);
1025 1025
@@ -1027,7 +1027,7 @@ static void MGA1064_restore(WPMINFO2) {
1027 1027
1028 DAC1064_restore_1(PMINFO2); 1028 DAC1064_restore_1(PMINFO2);
1029 matroxfb_vgaHWrestore(PMINFO2); 1029 matroxfb_vgaHWrestore(PMINFO2);
1030 ACCESS_FBINFO(crtc1.panpos) = -1; 1030 minfo->crtc1.panpos = -1;
1031 for (i = 0; i < 6; i++) 1031 for (i = 0; i < 6; i++)
1032 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]); 1032 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
1033 DAC1064_restore_2(PMINFO2); 1033 DAC1064_restore_2(PMINFO2);
@@ -1037,7 +1037,7 @@ static void MGA1064_restore(WPMINFO2) {
1037#ifdef CONFIG_FB_MATROX_G 1037#ifdef CONFIG_FB_MATROX_G
1038static void MGAG100_restore(WPMINFO2) { 1038static void MGAG100_restore(WPMINFO2) {
1039 int i; 1039 int i;
1040 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 1040 struct matrox_hw_state *hw = &minfo->hw;
1041 1041
1042 CRITFLAGS 1042 CRITFLAGS
1043 1043
@@ -1045,16 +1045,16 @@ static void MGAG100_restore(WPMINFO2) {
1045 1045
1046 CRITBEGIN 1046 CRITBEGIN
1047 1047
1048 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); 1048 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
1049 CRITEND 1049 CRITEND
1050 1050
1051 DAC1064_restore_1(PMINFO2); 1051 DAC1064_restore_1(PMINFO2);
1052 matroxfb_vgaHWrestore(PMINFO2); 1052 matroxfb_vgaHWrestore(PMINFO2);
1053#ifdef CONFIG_FB_MATROX_32MB 1053#ifdef CONFIG_FB_MATROX_32MB
1054 if (ACCESS_FBINFO(devflags.support32MB)) 1054 if (minfo->devflags.support32MB)
1055 mga_setr(M_EXTVGA_INDEX, 8, hw->CRTCEXT[8]); 1055 mga_setr(M_EXTVGA_INDEX, 8, hw->CRTCEXT[8]);
1056#endif 1056#endif
1057 ACCESS_FBINFO(crtc1.panpos) = -1; 1057 minfo->crtc1.panpos = -1;
1058 for (i = 0; i < 6; i++) 1058 for (i = 0; i < 6; i++)
1059 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]); 1059 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
1060 DAC1064_restore_2(PMINFO2); 1060 DAC1064_restore_2(PMINFO2);
diff --git a/drivers/video/matrox/matroxfb_Ti3026.c b/drivers/video/matrox/matroxfb_Ti3026.c
index 4e825112a601..bc9c27499b39 100644
--- a/drivers/video/matrox/matroxfb_Ti3026.c
+++ b/drivers/video/matrox/matroxfb_Ti3026.c
@@ -295,11 +295,11 @@ static int Ti3026_calcclock(CPMINFO unsigned int freq, unsigned int fmax, int* i
295static int Ti3026_setpclk(WPMINFO int clk) { 295static int Ti3026_setpclk(WPMINFO int clk) {
296 unsigned int f_pll; 296 unsigned int f_pll;
297 unsigned int pixfeed, pixin, pixpost; 297 unsigned int pixfeed, pixin, pixpost;
298 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 298 struct matrox_hw_state *hw = &minfo->hw;
299 299
300 DBG(__func__) 300 DBG(__func__)
301 301
302 f_pll = Ti3026_calcclock(PMINFO clk, ACCESS_FBINFO(max_pixel_clock), &pixin, &pixfeed, &pixpost); 302 f_pll = Ti3026_calcclock(PMINFO clk, minfo->max_pixel_clock, &pixin, &pixfeed, &pixpost);
303 303
304 hw->DACclk[0] = pixin | 0xC0; 304 hw->DACclk[0] = pixin | 0xC0;
305 hw->DACclk[1] = pixfeed; 305 hw->DACclk[1] = pixfeed;
@@ -309,9 +309,9 @@ static int Ti3026_setpclk(WPMINFO int clk) {
309 unsigned int loopfeed, loopin, looppost, loopdiv, z; 309 unsigned int loopfeed, loopin, looppost, loopdiv, z;
310 unsigned int Bpp; 310 unsigned int Bpp;
311 311
312 Bpp = ACCESS_FBINFO(curr.final_bppShift); 312 Bpp = minfo->curr.final_bppShift;
313 313
314 if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) { 314 if (minfo->fbcon.var.bits_per_pixel == 24) {
315 loopfeed = 3; /* set lm to any possible value */ 315 loopfeed = 3; /* set lm to any possible value */
316 loopin = 3 * 32 / Bpp; 316 loopin = 3 * 32 / Bpp;
317 } else { 317 } else {
@@ -330,18 +330,18 @@ static int Ti3026_setpclk(WPMINFO int clk) {
330 looppost = 3; 330 looppost = 3;
331 loopdiv = z/16; 331 loopdiv = z/16;
332 } 332 }
333 if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) { 333 if (minfo->fbcon.var.bits_per_pixel == 24) {
334 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0; 334 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
335 hw->DACclk[4] = (65 - loopfeed) | 0x80; 335 hw->DACclk[4] = (65 - loopfeed) | 0x80;
336 if (ACCESS_FBINFO(accel.ramdac_rev) > 0x20) { 336 if (minfo->accel.ramdac_rev > 0x20) {
337 if (isInterleave(MINFO)) 337 if (isInterleave(minfo))
338 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3; 338 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
339 else { 339 else {
340 hw->DACclk[4] &= ~0xC0; 340 hw->DACclk[4] &= ~0xC0;
341 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3; 341 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
342 } 342 }
343 } else { 343 } else {
344 if (isInterleave(MINFO)) 344 if (isInterleave(minfo))
345 ; /* default... */ 345 ; /* default... */
346 else { 346 else {
347 hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */ 347 hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */
@@ -349,7 +349,7 @@ static int Ti3026_setpclk(WPMINFO int clk) {
349 } 349 }
350 } 350 }
351 hw->DACclk[5] = looppost | 0xF8; 351 hw->DACclk[5] = looppost | 0xF8;
352 if (ACCESS_FBINFO(devflags.mga_24bpp_fix)) 352 if (minfo->devflags.mga_24bpp_fix)
353 hw->DACclk[5] ^= 0x40; 353 hw->DACclk[5] ^= 0x40;
354 } else { 354 } else {
355 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0; 355 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
@@ -362,13 +362,13 @@ static int Ti3026_setpclk(WPMINFO int clk) {
362} 362}
363 363
364static int Ti3026_init(WPMINFO struct my_timming* m) { 364static int Ti3026_init(WPMINFO struct my_timming* m) {
365 u_int8_t muxctrl = isInterleave(MINFO) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT; 365 u_int8_t muxctrl = isInterleave(minfo) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
366 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 366 struct matrox_hw_state *hw = &minfo->hw;
367 367
368 DBG(__func__) 368 DBG(__func__)
369 369
370 memcpy(hw->DACreg, MGADACbpp32, sizeof(hw->DACreg)); 370 memcpy(hw->DACreg, MGADACbpp32, sizeof(hw->DACreg));
371 switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) { 371 switch (minfo->fbcon.var.bits_per_pixel) {
372 case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */ 372 case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */
373 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR; 373 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
374 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT; 374 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
@@ -383,7 +383,7 @@ static int Ti3026_init(WPMINFO struct my_timming* m) {
383 break; 383 break;
384 case 16: 384 case 16:
385 /* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used everytime) */ 385 /* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used everytime) */
386 hw->DACreg[POS3026_XTRUECOLORCTRL] = (ACCESS_FBINFO(fbcon).var.green.length == 5)? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555 ) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565); 386 hw->DACreg[POS3026_XTRUECOLORCTRL] = (minfo->fbcon.var.green.length == 5) ? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
387 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT; 387 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
388 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2; 388 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
389 break; 389 break;
@@ -412,9 +412,9 @@ static int Ti3026_init(WPMINFO struct my_timming* m) {
412 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN; 412 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
413 413
414 /* set DELAY */ 414 /* set DELAY */
415 if (ACCESS_FBINFO(video.len) < 0x400000) 415 if (minfo->video.len < 0x400000)
416 hw->CRTCEXT[3] |= 0x08; 416 hw->CRTCEXT[3] |= 0x08;
417 else if (ACCESS_FBINFO(video.len) > 0x400000) 417 else if (minfo->video.len > 0x400000)
418 hw->CRTCEXT[3] |= 0x10; 418 hw->CRTCEXT[3] |= 0x10;
419 419
420 /* set HWCURSOR */ 420 /* set HWCURSOR */
@@ -426,7 +426,7 @@ static int Ti3026_init(WPMINFO struct my_timming* m) {
426 426
427 /* set interleaving */ 427 /* set interleaving */
428 hw->MXoptionReg &= ~0x00001000; 428 hw->MXoptionReg &= ~0x00001000;
429 if (isInterleave(MINFO)) hw->MXoptionReg |= 0x00001000; 429 if (isInterleave(minfo)) hw->MXoptionReg |= 0x00001000;
430 430
431 /* set DAC */ 431 /* set DAC */
432 Ti3026_setpclk(PMINFO m->pixclock); 432 Ti3026_setpclk(PMINFO m->pixclock);
@@ -442,7 +442,7 @@ static void ti3026_setMCLK(WPMINFO int fout){
442 442
443 DBG(__func__) 443 DBG(__func__)
444 444
445 f_pll = Ti3026_calcclock(PMINFO fout, ACCESS_FBINFO(max_pixel_clock), &mclk_n, &mclk_m, &mclk_p); 445 f_pll = Ti3026_calcclock(PMINFO fout, minfo->max_pixel_clock, &mclk_n, &mclk_m, &mclk_p);
446 446
447 /* save pclk */ 447 /* save pclk */
448 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC); 448 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
@@ -496,7 +496,7 @@ static void ti3026_setMCLK(WPMINFO int fout){
496 printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n"); 496 printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
497 497
498 f_pll = f_pll * 333 / (10000 << mclk_p); 498 f_pll = f_pll * 333 / (10000 << mclk_p);
499 if (isMilleniumII(MINFO)) { 499 if (isMilleniumII(minfo)) {
500 rfhcnt = (f_pll - 128) / 256; 500 rfhcnt = (f_pll - 128) / 256;
501 if (rfhcnt > 15) 501 if (rfhcnt > 15)
502 rfhcnt = 15; 502 rfhcnt = 15;
@@ -505,8 +505,8 @@ static void ti3026_setMCLK(WPMINFO int fout){
505 if (rfhcnt > 15) 505 if (rfhcnt > 15)
506 rfhcnt = 0; 506 rfhcnt = 0;
507 } 507 }
508 ACCESS_FBINFO(hw).MXoptionReg = (ACCESS_FBINFO(hw).MXoptionReg & ~0x000F0000) | (rfhcnt << 16); 508 minfo->hw.MXoptionReg = (minfo->hw.MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
509 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg); 509 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
510 510
511 /* output MCLK to MCLK pin */ 511 /* output MCLK to MCLK pin */
512 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL); 512 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
@@ -536,14 +536,14 @@ static void ti3026_ramdac_init(WPMINFO2) {
536 536
537 DBG(__func__) 537 DBG(__func__)
538 538
539 ACCESS_FBINFO(features.pll.vco_freq_min) = 110000; 539 minfo->features.pll.vco_freq_min = 110000;
540 ACCESS_FBINFO(features.pll.ref_freq) = 114545; 540 minfo->features.pll.ref_freq = 114545;
541 ACCESS_FBINFO(features.pll.feed_div_min) = 2; 541 minfo->features.pll.feed_div_min = 2;
542 ACCESS_FBINFO(features.pll.feed_div_max) = 24; 542 minfo->features.pll.feed_div_max = 24;
543 ACCESS_FBINFO(features.pll.in_div_min) = 2; 543 minfo->features.pll.in_div_min = 2;
544 ACCESS_FBINFO(features.pll.in_div_max) = 63; 544 minfo->features.pll.in_div_max = 63;
545 ACCESS_FBINFO(features.pll.post_shift_max) = 3; 545 minfo->features.pll.post_shift_max = 3;
546 if (ACCESS_FBINFO(devflags.noinit)) 546 if (minfo->devflags.noinit)
547 return; 547 return;
548 ti3026_setMCLK(PMINFO 60000); 548 ti3026_setMCLK(PMINFO 60000);
549} 549}
@@ -551,7 +551,7 @@ static void ti3026_ramdac_init(WPMINFO2) {
551static void Ti3026_restore(WPMINFO2) { 551static void Ti3026_restore(WPMINFO2) {
552 int i; 552 int i;
553 unsigned char progdac[6]; 553 unsigned char progdac[6];
554 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 554 struct matrox_hw_state *hw = &minfo->hw;
555 CRITFLAGS 555 CRITFLAGS
556 556
557 DBG(__func__) 557 DBG(__func__)
@@ -565,7 +565,7 @@ static void Ti3026_restore(WPMINFO2) {
565 565
566 CRITBEGIN 566 CRITBEGIN
567 567
568 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); 568 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
569 569
570 CRITEND 570 CRITEND
571 571
@@ -573,7 +573,7 @@ static void Ti3026_restore(WPMINFO2) {
573 573
574 CRITBEGIN 574 CRITBEGIN
575 575
576 ACCESS_FBINFO(crtc1.panpos) = -1; 576 minfo->crtc1.panpos = -1;
577 for (i = 0; i < 6; i++) 577 for (i = 0; i < 6; i++)
578 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]); 578 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
579 579
@@ -678,35 +678,35 @@ static int Ti3026_preinit(WPMINFO2) {
678 static const int vxres_mill1[] = { 640, 768, 800, 960, 678 static const int vxres_mill1[] = { 640, 768, 800, 960,
679 1024, 1152, 1280, 1600, 1920, 679 1024, 1152, 1280, 1600, 1920,
680 2048, 0}; 680 2048, 0};
681 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw); 681 struct matrox_hw_state *hw = &minfo->hw;
682 682
683 DBG(__func__) 683 DBG(__func__)
684 684
685 ACCESS_FBINFO(millenium) = 1; 685 minfo->millenium = 1;
686 ACCESS_FBINFO(milleniumII) = (ACCESS_FBINFO(pcidev)->device != PCI_DEVICE_ID_MATROX_MIL); 686 minfo->milleniumII = (minfo->pcidev->device != PCI_DEVICE_ID_MATROX_MIL);
687 ACCESS_FBINFO(capable.cfb4) = 1; 687 minfo->capable.cfb4 = 1;
688 ACCESS_FBINFO(capable.text) = 1; /* isMilleniumII(MINFO); */ 688 minfo->capable.text = 1; /* isMilleniumII(minfo); */
689 ACCESS_FBINFO(capable.vxres) = isMilleniumII(MINFO)?vxres_mill2:vxres_mill1; 689 minfo->capable.vxres = isMilleniumII(minfo) ? vxres_mill2 : vxres_mill1;
690 690
691 ACCESS_FBINFO(outputs[0]).data = MINFO; 691 minfo->outputs[0].data = minfo;
692 ACCESS_FBINFO(outputs[0]).output = &ti3026_output; 692 minfo->outputs[0].output = &ti3026_output;
693 ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src; 693 minfo->outputs[0].src = minfo->outputs[0].default_src;
694 ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR; 694 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
695 695
696 if (ACCESS_FBINFO(devflags.noinit)) 696 if (minfo->devflags.noinit)
697 return 0; 697 return 0;
698 /* preserve VGA I/O, BIOS and PPC */ 698 /* preserve VGA I/O, BIOS and PPC */
699 hw->MXoptionReg &= 0xC0000100; 699 hw->MXoptionReg &= 0xC0000100;
700 hw->MXoptionReg |= 0x002C0000; 700 hw->MXoptionReg |= 0x002C0000;
701 if (ACCESS_FBINFO(devflags.novga)) 701 if (minfo->devflags.novga)
702 hw->MXoptionReg &= ~0x00000100; 702 hw->MXoptionReg &= ~0x00000100;
703 if (ACCESS_FBINFO(devflags.nobios)) 703 if (minfo->devflags.nobios)
704 hw->MXoptionReg &= ~0x40000000; 704 hw->MXoptionReg &= ~0x40000000;
705 if (ACCESS_FBINFO(devflags.nopciretry)) 705 if (minfo->devflags.nopciretry)
706 hw->MXoptionReg |= 0x20000000; 706 hw->MXoptionReg |= 0x20000000;
707 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg); 707 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
708 708
709 ACCESS_FBINFO(accel.ramdac_rev) = inTi3026(PMINFO TVP3026_XSILICONREV); 709 minfo->accel.ramdac_rev = inTi3026(PMINFO TVP3026_XSILICONREV);
710 710
711 outTi3026(PMINFO TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED); 711 outTi3026(PMINFO TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
712 outTi3026(PMINFO TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR); 712 outTi3026(PMINFO TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
diff --git a/drivers/video/matrox/matroxfb_accel.c b/drivers/video/matrox/matroxfb_accel.c
index 9c3aeee1cc4f..ed42bf6a0c15 100644
--- a/drivers/video/matrox/matroxfb_accel.c
+++ b/drivers/video/matrox/matroxfb_accel.c
@@ -81,7 +81,7 @@
81#include "matroxfb_Ti3026.h" 81#include "matroxfb_Ti3026.h"
82#include "matroxfb_misc.h" 82#include "matroxfb_misc.h"
83 83
84#define curr_ydstorg(x) ACCESS_FBINFO2(x, curr.ydstorg.pixels) 84#define curr_ydstorg(x) ((x)->curr.ydstorg.pixels)
85 85
86#define mga_ydstlen(y,l) mga_outl(M_YDSTLEN | M_EXEC, ((y) << 16) | (l)) 86#define mga_ydstlen(y,l) mga_outl(M_YDSTLEN | M_EXEC, ((y) << 16) | (l))
87 87
@@ -115,59 +115,59 @@ void matrox_cfbX_init(WPMINFO2) {
115 115
116 DBG(__func__) 116 DBG(__func__)
117 117
118 mpitch = ACCESS_FBINFO(fbcon).var.xres_virtual; 118 mpitch = minfo->fbcon.var.xres_virtual;
119 119
120 ACCESS_FBINFO(fbops).fb_copyarea = cfb_copyarea; 120 minfo->fbops.fb_copyarea = cfb_copyarea;
121 ACCESS_FBINFO(fbops).fb_fillrect = cfb_fillrect; 121 minfo->fbops.fb_fillrect = cfb_fillrect;
122 ACCESS_FBINFO(fbops).fb_imageblit = cfb_imageblit; 122 minfo->fbops.fb_imageblit = cfb_imageblit;
123 ACCESS_FBINFO(fbops).fb_cursor = NULL; 123 minfo->fbops.fb_cursor = NULL;
124 124
125 accel = (ACCESS_FBINFO(fbcon).var.accel_flags & FB_ACCELF_TEXT) == FB_ACCELF_TEXT; 125 accel = (minfo->fbcon.var.accel_flags & FB_ACCELF_TEXT) == FB_ACCELF_TEXT;
126 126
127 switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) { 127 switch (minfo->fbcon.var.bits_per_pixel) {
128 case 4: maccess = 0x00000000; /* accelerate as 8bpp video */ 128 case 4: maccess = 0x00000000; /* accelerate as 8bpp video */
129 mpitch = (mpitch >> 1) | 0x8000; /* disable linearization */ 129 mpitch = (mpitch >> 1) | 0x8000; /* disable linearization */
130 mopmode = M_OPMODE_4BPP; 130 mopmode = M_OPMODE_4BPP;
131 matrox_cfb4_pal(ACCESS_FBINFO(cmap)); 131 matrox_cfb4_pal(minfo->cmap);
132 if (accel && !(mpitch & 1)) { 132 if (accel && !(mpitch & 1)) {
133 ACCESS_FBINFO(fbops).fb_copyarea = matroxfb_cfb4_copyarea; 133 minfo->fbops.fb_copyarea = matroxfb_cfb4_copyarea;
134 ACCESS_FBINFO(fbops).fb_fillrect = matroxfb_cfb4_fillrect; 134 minfo->fbops.fb_fillrect = matroxfb_cfb4_fillrect;
135 } 135 }
136 break; 136 break;
137 case 8: maccess = 0x00000000; 137 case 8: maccess = 0x00000000;
138 mopmode = M_OPMODE_8BPP; 138 mopmode = M_OPMODE_8BPP;
139 matrox_cfb8_pal(ACCESS_FBINFO(cmap)); 139 matrox_cfb8_pal(minfo->cmap);
140 if (accel) { 140 if (accel) {
141 ACCESS_FBINFO(fbops).fb_copyarea = matroxfb_copyarea; 141 minfo->fbops.fb_copyarea = matroxfb_copyarea;
142 ACCESS_FBINFO(fbops).fb_fillrect = matroxfb_fillrect; 142 minfo->fbops.fb_fillrect = matroxfb_fillrect;
143 ACCESS_FBINFO(fbops).fb_imageblit = matroxfb_imageblit; 143 minfo->fbops.fb_imageblit = matroxfb_imageblit;
144 } 144 }
145 break; 145 break;
146 case 16: if (ACCESS_FBINFO(fbcon).var.green.length == 5) 146 case 16: if (minfo->fbcon.var.green.length == 5)
147 maccess = 0xC0000001; 147 maccess = 0xC0000001;
148 else 148 else
149 maccess = 0x40000001; 149 maccess = 0x40000001;
150 mopmode = M_OPMODE_16BPP; 150 mopmode = M_OPMODE_16BPP;
151 if (accel) { 151 if (accel) {
152 ACCESS_FBINFO(fbops).fb_copyarea = matroxfb_copyarea; 152 minfo->fbops.fb_copyarea = matroxfb_copyarea;
153 ACCESS_FBINFO(fbops).fb_fillrect = matroxfb_fillrect; 153 minfo->fbops.fb_fillrect = matroxfb_fillrect;
154 ACCESS_FBINFO(fbops).fb_imageblit = matroxfb_imageblit; 154 minfo->fbops.fb_imageblit = matroxfb_imageblit;
155 } 155 }
156 break; 156 break;
157 case 24: maccess = 0x00000003; 157 case 24: maccess = 0x00000003;
158 mopmode = M_OPMODE_24BPP; 158 mopmode = M_OPMODE_24BPP;
159 if (accel) { 159 if (accel) {
160 ACCESS_FBINFO(fbops).fb_copyarea = matroxfb_copyarea; 160 minfo->fbops.fb_copyarea = matroxfb_copyarea;
161 ACCESS_FBINFO(fbops).fb_fillrect = matroxfb_fillrect; 161 minfo->fbops.fb_fillrect = matroxfb_fillrect;
162 ACCESS_FBINFO(fbops).fb_imageblit = matroxfb_imageblit; 162 minfo->fbops.fb_imageblit = matroxfb_imageblit;
163 } 163 }
164 break; 164 break;
165 case 32: maccess = 0x00000002; 165 case 32: maccess = 0x00000002;
166 mopmode = M_OPMODE_32BPP; 166 mopmode = M_OPMODE_32BPP;
167 if (accel) { 167 if (accel) {
168 ACCESS_FBINFO(fbops).fb_copyarea = matroxfb_copyarea; 168 minfo->fbops.fb_copyarea = matroxfb_copyarea;
169 ACCESS_FBINFO(fbops).fb_fillrect = matroxfb_fillrect; 169 minfo->fbops.fb_fillrect = matroxfb_fillrect;
170 ACCESS_FBINFO(fbops).fb_imageblit = matroxfb_imageblit; 170 minfo->fbops.fb_imageblit = matroxfb_imageblit;
171 } 171 }
172 break; 172 break;
173 default: maccess = 0x00000000; 173 default: maccess = 0x00000000;
@@ -176,10 +176,10 @@ void matrox_cfbX_init(WPMINFO2) {
176 } 176 }
177 mga_fifo(8); 177 mga_fifo(8);
178 mga_outl(M_PITCH, mpitch); 178 mga_outl(M_PITCH, mpitch);
179 mga_outl(M_YDSTORG, curr_ydstorg(MINFO)); 179 mga_outl(M_YDSTORG, curr_ydstorg(minfo));
180 if (ACCESS_FBINFO(capable.plnwt)) 180 if (minfo->capable.plnwt)
181 mga_outl(M_PLNWT, -1); 181 mga_outl(M_PLNWT, -1);
182 if (ACCESS_FBINFO(capable.srcorg)) { 182 if (minfo->capable.srcorg) {
183 mga_outl(M_SRCORG, 0); 183 mga_outl(M_SRCORG, 0);
184 mga_outl(M_DSTORG, 0); 184 mga_outl(M_DSTORG, 0);
185 } 185 }
@@ -188,9 +188,9 @@ void matrox_cfbX_init(WPMINFO2) {
188 mga_outl(M_YTOP, 0); 188 mga_outl(M_YTOP, 0);
189 mga_outl(M_YBOT, 0x01FFFFFF); 189 mga_outl(M_YBOT, 0x01FFFFFF);
190 mga_outl(M_MACCESS, maccess); 190 mga_outl(M_MACCESS, maccess);
191 ACCESS_FBINFO(accel.m_dwg_rect) = M_DWG_TRAP | M_DWG_SOLID | M_DWG_ARZERO | M_DWG_SGNZERO | M_DWG_SHIFTZERO; 191 minfo->accel.m_dwg_rect = M_DWG_TRAP | M_DWG_SOLID | M_DWG_ARZERO | M_DWG_SGNZERO | M_DWG_SHIFTZERO;
192 if (isMilleniumII(MINFO)) ACCESS_FBINFO(accel.m_dwg_rect) |= M_DWG_TRANSC; 192 if (isMilleniumII(minfo)) minfo->accel.m_dwg_rect |= M_DWG_TRANSC;
193 ACCESS_FBINFO(accel.m_opmode) = mopmode; 193 minfo->accel.m_opmode = mopmode;
194} 194}
195 195
196EXPORT_SYMBOL(matrox_cfbX_init); 196EXPORT_SYMBOL(matrox_cfbX_init);
@@ -209,7 +209,7 @@ static void matrox_accel_bmove(WPMINFO int vxres, int sy, int sx, int dy, int dx
209 M_DWG_BFCOL | M_DWG_REPLACE); 209 M_DWG_BFCOL | M_DWG_REPLACE);
210 mga_outl(M_AR5, vxres); 210 mga_outl(M_AR5, vxres);
211 width--; 211 width--;
212 start = sy*vxres+sx+curr_ydstorg(MINFO); 212 start = sy*vxres+sx+curr_ydstorg(minfo);
213 end = start+width; 213 end = start+width;
214 } else { 214 } else {
215 mga_fifo(3); 215 mga_fifo(3);
@@ -217,7 +217,7 @@ static void matrox_accel_bmove(WPMINFO int vxres, int sy, int sx, int dy, int dx
217 mga_outl(M_SGN, 5); 217 mga_outl(M_SGN, 5);
218 mga_outl(M_AR5, -vxres); 218 mga_outl(M_AR5, -vxres);
219 width--; 219 width--;
220 end = (sy+height-1)*vxres+sx+curr_ydstorg(MINFO); 220 end = (sy+height-1)*vxres+sx+curr_ydstorg(minfo);
221 start = end+width; 221 start = end+width;
222 dy += height-1; 222 dy += height-1;
223 } 223 }
@@ -245,7 +245,7 @@ static void matrox_accel_bmove_lin(WPMINFO int vxres, int sy, int sx, int dy, in
245 M_DWG_BFCOL | M_DWG_REPLACE); 245 M_DWG_BFCOL | M_DWG_REPLACE);
246 mga_outl(M_AR5, vxres); 246 mga_outl(M_AR5, vxres);
247 width--; 247 width--;
248 start = sy*vxres+sx+curr_ydstorg(MINFO); 248 start = sy*vxres+sx+curr_ydstorg(minfo);
249 end = start+width; 249 end = start+width;
250 } else { 250 } else {
251 mga_fifo(3); 251 mga_fifo(3);
@@ -253,7 +253,7 @@ static void matrox_accel_bmove_lin(WPMINFO int vxres, int sy, int sx, int dy, in
253 mga_outl(M_SGN, 5); 253 mga_outl(M_SGN, 5);
254 mga_outl(M_AR5, -vxres); 254 mga_outl(M_AR5, -vxres);
255 width--; 255 width--;
256 end = (sy+height-1)*vxres+sx+curr_ydstorg(MINFO); 256 end = (sy+height-1)*vxres+sx+curr_ydstorg(minfo);
257 start = end+width; 257 start = end+width;
258 dy += height-1; 258 dy += height-1;
259 } 259 }
@@ -274,13 +274,13 @@ static void matroxfb_cfb4_copyarea(struct fb_info* info, const struct fb_copyare
274 if ((area->sx | area->dx | area->width) & 1) 274 if ((area->sx | area->dx | area->width) & 1)
275 cfb_copyarea(info, area); 275 cfb_copyarea(info, area);
276 else 276 else
277 matrox_accel_bmove_lin(PMINFO ACCESS_FBINFO(fbcon.var.xres_virtual) >> 1, area->sy, area->sx >> 1, area->dy, area->dx >> 1, area->height, area->width >> 1); 277 matrox_accel_bmove_lin(PMINFO minfo->fbcon.var.xres_virtual >> 1, area->sy, area->sx >> 1, area->dy, area->dx >> 1, area->height, area->width >> 1);
278} 278}
279 279
280static void matroxfb_copyarea(struct fb_info* info, const struct fb_copyarea* area) { 280static void matroxfb_copyarea(struct fb_info* info, const struct fb_copyarea* area) {
281 MINFO_FROM_INFO(info); 281 MINFO_FROM_INFO(info);
282 282
283 matrox_accel_bmove(PMINFO ACCESS_FBINFO(fbcon.var.xres_virtual), area->sy, area->sx, area->dy, area->dx, area->height, area->width); 283 matrox_accel_bmove(PMINFO minfo->fbcon.var.xres_virtual, area->sy, area->sx, area->dy, area->dx, area->height, area->width);
284} 284}
285 285
286static void matroxfb_accel_clear(WPMINFO u_int32_t color, int sy, int sx, int height, 286static void matroxfb_accel_clear(WPMINFO u_int32_t color, int sy, int sx, int height,
@@ -292,7 +292,7 @@ static void matroxfb_accel_clear(WPMINFO u_int32_t color, int sy, int sx, int he
292 CRITBEGIN 292 CRITBEGIN
293 293
294 mga_fifo(5); 294 mga_fifo(5);
295 mga_outl(M_DWGCTL, ACCESS_FBINFO(accel.m_dwg_rect) | M_DWG_REPLACE); 295 mga_outl(M_DWGCTL, minfo->accel.m_dwg_rect | M_DWG_REPLACE);
296 mga_outl(M_FCOL, color); 296 mga_outl(M_FCOL, color);
297 mga_outl(M_FXBNDRY, ((sx + width) << 16) | sx); 297 mga_outl(M_FXBNDRY, ((sx + width) << 16) | sx);
298 mga_ydstlen(sy, height); 298 mga_ydstlen(sy, height);
@@ -333,16 +333,16 @@ static void matroxfb_cfb4_clear(WPMINFO u_int32_t bgx, int sy, int sx, int heigh
333 sx >>= 1; 333 sx >>= 1;
334 if (width) { 334 if (width) {
335 mga_fifo(5); 335 mga_fifo(5);
336 mga_outl(M_DWGCTL, ACCESS_FBINFO(accel.m_dwg_rect) | M_DWG_REPLACE2); 336 mga_outl(M_DWGCTL, minfo->accel.m_dwg_rect | M_DWG_REPLACE2);
337 mga_outl(M_FCOL, bgx); 337 mga_outl(M_FCOL, bgx);
338 mga_outl(M_FXBNDRY, ((sx + width) << 16) | sx); 338 mga_outl(M_FXBNDRY, ((sx + width) << 16) | sx);
339 mga_outl(M_YDST, sy * ACCESS_FBINFO(fbcon).var.xres_virtual >> 6); 339 mga_outl(M_YDST, sy * minfo->fbcon.var.xres_virtual >> 6);
340 mga_outl(M_LEN | M_EXEC, height); 340 mga_outl(M_LEN | M_EXEC, height);
341 WaitTillIdle(); 341 WaitTillIdle();
342 } 342 }
343 if (whattodo) { 343 if (whattodo) {
344 u_int32_t step = ACCESS_FBINFO(fbcon).var.xres_virtual >> 1; 344 u_int32_t step = minfo->fbcon.var.xres_virtual >> 1;
345 vaddr_t vbase = ACCESS_FBINFO(video.vbase); 345 vaddr_t vbase = minfo->video.vbase;
346 if (whattodo & 1) { 346 if (whattodo & 1) {
347 unsigned int uaddr = sy * step + sx - 1; 347 unsigned int uaddr = sy * step + sx - 1;
348 u_int32_t loop; 348 u_int32_t loop;
@@ -412,7 +412,7 @@ static void matroxfb_1bpp_imageblit(WPMINFO u_int32_t fgx, u_int32_t bgx,
412 mga_outl(M_FCOL, fgx); 412 mga_outl(M_FCOL, fgx);
413 mga_outl(M_BCOL, bgx); 413 mga_outl(M_BCOL, bgx);
414 fxbndry = ((xx + width - 1) << 16) | xx; 414 fxbndry = ((xx + width - 1) << 16) | xx;
415 mmio = ACCESS_FBINFO(mmio.vbase); 415 mmio = minfo->mmio.vbase;
416 416
417 mga_fifo(6); 417 mga_fifo(6);
418 mga_writel(mmio, M_FXBNDRY, fxbndry); 418 mga_writel(mmio, M_FXBNDRY, fxbndry);
diff --git a/drivers/video/matrox/matroxfb_base.c b/drivers/video/matrox/matroxfb_base.c
index 6ede98da4618..867a4d915e77 100644
--- a/drivers/video/matrox/matroxfb_base.c
+++ b/drivers/video/matrox/matroxfb_base.c
@@ -155,20 +155,20 @@ static struct fb_var_screeninfo vesafb_defined = {
155 155
156/* --------------------------------------------------------------------- */ 156/* --------------------------------------------------------------------- */
157static void update_crtc2(WPMINFO unsigned int pos) { 157static void update_crtc2(WPMINFO unsigned int pos) {
158 struct matroxfb_dh_fb_info* info = ACCESS_FBINFO(crtc2.info); 158 struct matroxfb_dh_fb_info *info = minfo->crtc2.info;
159 159
160 /* Make sure that displays are compatible */ 160 /* Make sure that displays are compatible */
161 if (info && (info->fbcon.var.bits_per_pixel == ACCESS_FBINFO(fbcon).var.bits_per_pixel) 161 if (info && (info->fbcon.var.bits_per_pixel == minfo->fbcon.var.bits_per_pixel)
162 && (info->fbcon.var.xres_virtual == ACCESS_FBINFO(fbcon).var.xres_virtual) 162 && (info->fbcon.var.xres_virtual == minfo->fbcon.var.xres_virtual)
163 && (info->fbcon.var.green.length == ACCESS_FBINFO(fbcon).var.green.length) 163 && (info->fbcon.var.green.length == minfo->fbcon.var.green.length)
164 ) { 164 ) {
165 switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) { 165 switch (minfo->fbcon.var.bits_per_pixel) {
166 case 16: 166 case 16:
167 case 32: 167 case 32:
168 pos = pos * 8; 168 pos = pos * 8;
169 if (info->interlaced) { 169 if (info->interlaced) {
170 mga_outl(0x3C2C, pos); 170 mga_outl(0x3C2C, pos);
171 mga_outl(0x3C28, pos + ACCESS_FBINFO(fbcon).var.xres_virtual * ACCESS_FBINFO(fbcon).var.bits_per_pixel / 8); 171 mga_outl(0x3C28, pos + minfo->fbcon.var.xres_virtual * minfo->fbcon.var.bits_per_pixel / 8);
172 } else { 172 } else {
173 mga_outl(0x3C28, pos); 173 mga_outl(0x3C28, pos);
174 } 174 }
@@ -178,16 +178,16 @@ static void update_crtc2(WPMINFO unsigned int pos) {
178} 178}
179 179
180static void matroxfb_crtc1_panpos(WPMINFO2) { 180static void matroxfb_crtc1_panpos(WPMINFO2) {
181 if (ACCESS_FBINFO(crtc1.panpos) >= 0) { 181 if (minfo->crtc1.panpos >= 0) {
182 unsigned long flags; 182 unsigned long flags;
183 int panpos; 183 int panpos;
184 184
185 matroxfb_DAC_lock_irqsave(flags); 185 matroxfb_DAC_lock_irqsave(flags);
186 panpos = ACCESS_FBINFO(crtc1.panpos); 186 panpos = minfo->crtc1.panpos;
187 if (panpos >= 0) { 187 if (panpos >= 0) {
188 unsigned int extvga_reg; 188 unsigned int extvga_reg;
189 189
190 ACCESS_FBINFO(crtc1.panpos) = -1; /* No update pending anymore */ 190 minfo->crtc1.panpos = -1; /* No update pending anymore */
191 extvga_reg = mga_inb(M_EXTVGA_INDEX); 191 extvga_reg = mga_inb(M_EXTVGA_INDEX);
192 mga_setr(M_EXTVGA_INDEX, 0x00, panpos); 192 mga_setr(M_EXTVGA_INDEX, 0x00, panpos);
193 if (extvga_reg != 0x00) { 193 if (extvga_reg != 0x00) {
@@ -209,15 +209,15 @@ static irqreturn_t matrox_irq(int irq, void *dev_id)
209 209
210 if (status & 0x20) { 210 if (status & 0x20) {
211 mga_outl(M_ICLEAR, 0x20); 211 mga_outl(M_ICLEAR, 0x20);
212 ACCESS_FBINFO(crtc1.vsync.cnt)++; 212 minfo->crtc1.vsync.cnt++;
213 matroxfb_crtc1_panpos(PMINFO2); 213 matroxfb_crtc1_panpos(PMINFO2);
214 wake_up_interruptible(&ACCESS_FBINFO(crtc1.vsync.wait)); 214 wake_up_interruptible(&minfo->crtc1.vsync.wait);
215 handled = 1; 215 handled = 1;
216 } 216 }
217 if (status & 0x200) { 217 if (status & 0x200) {
218 mga_outl(M_ICLEAR, 0x200); 218 mga_outl(M_ICLEAR, 0x200);
219 ACCESS_FBINFO(crtc2.vsync.cnt)++; 219 minfo->crtc2.vsync.cnt++;
220 wake_up_interruptible(&ACCESS_FBINFO(crtc2.vsync.wait)); 220 wake_up_interruptible(&minfo->crtc2.vsync.wait);
221 handled = 1; 221 handled = 1;
222 } 222 }
223 return IRQ_RETVAL(handled); 223 return IRQ_RETVAL(handled);
@@ -226,15 +226,15 @@ static irqreturn_t matrox_irq(int irq, void *dev_id)
226int matroxfb_enable_irq(WPMINFO int reenable) { 226int matroxfb_enable_irq(WPMINFO int reenable) {
227 u_int32_t bm; 227 u_int32_t bm;
228 228
229 if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG400) 229 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
230 bm = 0x220; 230 bm = 0x220;
231 else 231 else
232 bm = 0x020; 232 bm = 0x020;
233 233
234 if (!test_and_set_bit(0, &ACCESS_FBINFO(irq_flags))) { 234 if (!test_and_set_bit(0, &minfo->irq_flags)) {
235 if (request_irq(ACCESS_FBINFO(pcidev)->irq, matrox_irq, 235 if (request_irq(minfo->pcidev->irq, matrox_irq,
236 IRQF_SHARED, "matroxfb", MINFO)) { 236 IRQF_SHARED, "matroxfb", minfo)) {
237 clear_bit(0, &ACCESS_FBINFO(irq_flags)); 237 clear_bit(0, &minfo->irq_flags);
238 return -EINVAL; 238 return -EINVAL;
239 } 239 }
240 /* Clear any pending field interrupts */ 240 /* Clear any pending field interrupts */
@@ -253,14 +253,14 @@ int matroxfb_enable_irq(WPMINFO int reenable) {
253} 253}
254 254
255static void matroxfb_disable_irq(WPMINFO2) { 255static void matroxfb_disable_irq(WPMINFO2) {
256 if (test_and_clear_bit(0, &ACCESS_FBINFO(irq_flags))) { 256 if (test_and_clear_bit(0, &minfo->irq_flags)) {
257 /* Flush pending pan-at-vbl request... */ 257 /* Flush pending pan-at-vbl request... */
258 matroxfb_crtc1_panpos(PMINFO2); 258 matroxfb_crtc1_panpos(PMINFO2);
259 if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG400) 259 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
260 mga_outl(M_IEN, mga_inl(M_IEN) & ~0x220); 260 mga_outl(M_IEN, mga_inl(M_IEN) & ~0x220);
261 else 261 else
262 mga_outl(M_IEN, mga_inl(M_IEN) & ~0x20); 262 mga_outl(M_IEN, mga_inl(M_IEN) & ~0x20);
263 free_irq(ACCESS_FBINFO(pcidev)->irq, MINFO); 263 free_irq(minfo->pcidev->irq, minfo);
264 } 264 }
265} 265}
266 266
@@ -271,13 +271,13 @@ int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc) {
271 271
272 switch (crtc) { 272 switch (crtc) {
273 case 0: 273 case 0:
274 vs = &ACCESS_FBINFO(crtc1.vsync); 274 vs = &minfo->crtc1.vsync;
275 break; 275 break;
276 case 1: 276 case 1:
277 if (ACCESS_FBINFO(devflags.accelerator) != FB_ACCEL_MATROX_MGAG400) { 277 if (minfo->devflags.accelerator != FB_ACCEL_MATROX_MGAG400) {
278 return -ENODEV; 278 return -ENODEV;
279 } 279 }
280 vs = &ACCESS_FBINFO(crtc2.vsync); 280 vs = &minfo->crtc2.vsync;
281 break; 281 break;
282 default: 282 default:
283 return -ENODEV; 283 return -ENODEV;
@@ -314,18 +314,18 @@ static void matrox_pan_var(WPMINFO struct fb_var_screeninfo *var) {
314 314
315 DBG(__func__) 315 DBG(__func__)
316 316
317 if (ACCESS_FBINFO(dead)) 317 if (minfo->dead)
318 return; 318 return;
319 319
320 ACCESS_FBINFO(fbcon).var.xoffset = var->xoffset; 320 minfo->fbcon.var.xoffset = var->xoffset;
321 ACCESS_FBINFO(fbcon).var.yoffset = var->yoffset; 321 minfo->fbcon.var.yoffset = var->yoffset;
322 pos = (ACCESS_FBINFO(fbcon).var.yoffset * ACCESS_FBINFO(fbcon).var.xres_virtual + ACCESS_FBINFO(fbcon).var.xoffset) * ACCESS_FBINFO(curr.final_bppShift) / 32; 322 pos = (minfo->fbcon.var.yoffset * minfo->fbcon.var.xres_virtual + minfo->fbcon.var.xoffset) * minfo->curr.final_bppShift / 32;
323 pos += ACCESS_FBINFO(curr.ydstorg.chunks); 323 pos += minfo->curr.ydstorg.chunks;
324 p0 = ACCESS_FBINFO(hw).CRTC[0x0D] = pos & 0xFF; 324 p0 = minfo->hw.CRTC[0x0D] = pos & 0xFF;
325 p1 = ACCESS_FBINFO(hw).CRTC[0x0C] = (pos & 0xFF00) >> 8; 325 p1 = minfo->hw.CRTC[0x0C] = (pos & 0xFF00) >> 8;
326 p2 = ACCESS_FBINFO(hw).CRTCEXT[0] = (ACCESS_FBINFO(hw).CRTCEXT[0] & 0xB0) | ((pos >> 16) & 0x0F) | ((pos >> 14) & 0x40); 326 p2 = minfo->hw.CRTCEXT[0] = (minfo->hw.CRTCEXT[0] & 0xB0) | ((pos >> 16) & 0x0F) | ((pos >> 14) & 0x40);
327#ifdef CONFIG_FB_MATROX_32MB 327#ifdef CONFIG_FB_MATROX_32MB
328 p3 = ACCESS_FBINFO(hw).CRTCEXT[8] = pos >> 21; 328 p3 = minfo->hw.CRTCEXT[8] = pos >> 21;
329#endif 329#endif
330 330
331 /* FB_ACTIVATE_VBL and we can acquire interrupts? Honor FB_ACTIVATE_VBL then... */ 331 /* FB_ACTIVATE_VBL and we can acquire interrupts? Honor FB_ACTIVATE_VBL then... */
@@ -337,14 +337,14 @@ static void matrox_pan_var(WPMINFO struct fb_var_screeninfo *var) {
337 mga_setr(M_CRTC_INDEX, 0x0D, p0); 337 mga_setr(M_CRTC_INDEX, 0x0D, p0);
338 mga_setr(M_CRTC_INDEX, 0x0C, p1); 338 mga_setr(M_CRTC_INDEX, 0x0C, p1);
339#ifdef CONFIG_FB_MATROX_32MB 339#ifdef CONFIG_FB_MATROX_32MB
340 if (ACCESS_FBINFO(devflags.support32MB)) 340 if (minfo->devflags.support32MB)
341 mga_setr(M_EXTVGA_INDEX, 0x08, p3); 341 mga_setr(M_EXTVGA_INDEX, 0x08, p3);
342#endif 342#endif
343 if (vbl) { 343 if (vbl) {
344 ACCESS_FBINFO(crtc1.panpos) = p2; 344 minfo->crtc1.panpos = p2;
345 } else { 345 } else {
346 /* Abort any pending change */ 346 /* Abort any pending change */
347 ACCESS_FBINFO(crtc1.panpos) = -1; 347 minfo->crtc1.panpos = -1;
348 mga_setr(M_EXTVGA_INDEX, 0x00, p2); 348 mga_setr(M_EXTVGA_INDEX, 0x00, p2);
349 } 349 }
350 matroxfb_DAC_unlock_irqrestore(flags); 350 matroxfb_DAC_unlock_irqrestore(flags);
@@ -363,22 +363,22 @@ static void matroxfb_remove(WPMINFO int dummy) {
363 * write data without causing too much damage... 363 * write data without causing too much damage...
364 */ 364 */
365 365
366 ACCESS_FBINFO(dead) = 1; 366 minfo->dead = 1;
367 if (ACCESS_FBINFO(usecount)) { 367 if (minfo->usecount) {
368 /* destroy it later */ 368 /* destroy it later */
369 return; 369 return;
370 } 370 }
371 matroxfb_unregister_device(MINFO); 371 matroxfb_unregister_device(minfo);
372 unregister_framebuffer(&ACCESS_FBINFO(fbcon)); 372 unregister_framebuffer(&minfo->fbcon);
373 matroxfb_g450_shutdown(PMINFO2); 373 matroxfb_g450_shutdown(PMINFO2);
374#ifdef CONFIG_MTRR 374#ifdef CONFIG_MTRR
375 if (ACCESS_FBINFO(mtrr.vram_valid)) 375 if (minfo->mtrr.vram_valid)
376 mtrr_del(ACCESS_FBINFO(mtrr.vram), ACCESS_FBINFO(video.base), ACCESS_FBINFO(video.len)); 376 mtrr_del(minfo->mtrr.vram, minfo->video.base, minfo->video.len);
377#endif 377#endif
378 mga_iounmap(ACCESS_FBINFO(mmio.vbase)); 378 mga_iounmap(minfo->mmio.vbase);
379 mga_iounmap(ACCESS_FBINFO(video.vbase)); 379 mga_iounmap(minfo->video.vbase);
380 release_mem_region(ACCESS_FBINFO(video.base), ACCESS_FBINFO(video.len_maximum)); 380 release_mem_region(minfo->video.base, minfo->video.len_maximum);
381 release_mem_region(ACCESS_FBINFO(mmio.base), 16384); 381 release_mem_region(minfo->mmio.base, 16384);
382 kfree(minfo); 382 kfree(minfo);
383} 383}
384 384
@@ -392,12 +392,12 @@ static int matroxfb_open(struct fb_info *info, int user)
392 392
393 DBG_LOOP(__func__) 393 DBG_LOOP(__func__)
394 394
395 if (ACCESS_FBINFO(dead)) { 395 if (minfo->dead) {
396 return -ENXIO; 396 return -ENXIO;
397 } 397 }
398 ACCESS_FBINFO(usecount)++; 398 minfo->usecount++;
399 if (user) { 399 if (user) {
400 ACCESS_FBINFO(userusecount)++; 400 minfo->userusecount++;
401 } 401 }
402 return(0); 402 return(0);
403} 403}
@@ -409,11 +409,11 @@ static int matroxfb_release(struct fb_info *info, int user)
409 DBG_LOOP(__func__) 409 DBG_LOOP(__func__)
410 410
411 if (user) { 411 if (user) {
412 if (0 == --ACCESS_FBINFO(userusecount)) { 412 if (0 == --minfo->userusecount) {
413 matroxfb_disable_irq(PMINFO2); 413 matroxfb_disable_irq(PMINFO2);
414 } 414 }
415 } 415 }
416 if (!(--ACCESS_FBINFO(usecount)) && ACCESS_FBINFO(dead)) { 416 if (!(--minfo->usecount) && minfo->dead) {
417 matroxfb_remove(PMINFO 0); 417 matroxfb_remove(PMINFO 0);
418 } 418 }
419 return(0); 419 return(0);
@@ -438,9 +438,9 @@ static int matroxfb_get_final_bppShift(CPMINFO int bpp) {
438 if (!bppshft2) { 438 if (!bppshft2) {
439 return 8; 439 return 8;
440 } 440 }
441 if (isInterleave(MINFO)) 441 if (isInterleave(minfo))
442 bppshft2 >>= 1; 442 bppshft2 >>= 1;
443 if (ACCESS_FBINFO(devflags.video64bits)) 443 if (minfo->devflags.video64bits)
444 bppshft2 >>= 1; 444 bppshft2 >>= 1;
445 return bppshft2; 445 return bppshft2;
446} 446}
@@ -463,11 +463,11 @@ static int matroxfb_test_and_set_rounding(CPMINFO int xres, int bpp) {
463 break; 463 break;
464 default: rounding = 16; 464 default: rounding = 16;
465 /* on G400, 16 really does not work */ 465 /* on G400, 16 really does not work */
466 if (ACCESS_FBINFO(devflags.accelerator) == FB_ACCEL_MATROX_MGAG400) 466 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
467 rounding = 32; 467 rounding = 32;
468 break; 468 break;
469 } 469 }
470 if (isInterleave(MINFO)) { 470 if (isInterleave(minfo)) {
471 rounding *= 2; 471 rounding *= 2;
472 } 472 }
473 over = xres % rounding; 473 over = xres % rounding;
@@ -484,9 +484,9 @@ static int matroxfb_pitch_adjust(CPMINFO int xres, int bpp) {
484 484
485 if (!bpp) return xres; 485 if (!bpp) return xres;
486 486
487 width = ACCESS_FBINFO(capable.vxres); 487 width = minfo->capable.vxres;
488 488
489 if (ACCESS_FBINFO(devflags.precise_width)) { 489 if (minfo->devflags.precise_width) {
490 while (*width) { 490 while (*width) {
491 if ((*width >= xres) && (matroxfb_test_and_set_rounding(PMINFO *width, bpp) == *width)) { 491 if ((*width >= xres) && (matroxfb_test_and_set_rounding(PMINFO *width, bpp) == *width)) {
492 break; 492 break;
@@ -549,7 +549,7 @@ static int matroxfb_decode_var(CPMINFO struct fb_var_screeninfo *var, int *visua
549 DBG(__func__) 549 DBG(__func__)
550 550
551 switch (bpp) { 551 switch (bpp) {
552 case 4: if (!ACCESS_FBINFO(capable.cfb4)) return -EINVAL; 552 case 4: if (!minfo->capable.cfb4) return -EINVAL;
553 break; 553 break;
554 case 8: break; 554 case 8: break;
555 case 16: break; 555 case 16: break;
@@ -558,7 +558,7 @@ static int matroxfb_decode_var(CPMINFO struct fb_var_screeninfo *var, int *visua
558 default: return -EINVAL; 558 default: return -EINVAL;
559 } 559 }
560 *ydstorg = 0; 560 *ydstorg = 0;
561 vramlen = ACCESS_FBINFO(video.len_usable); 561 vramlen = minfo->video.len_usable;
562 if (var->yres_virtual < var->yres) 562 if (var->yres_virtual < var->yres)
563 var->yres_virtual = var->yres; 563 var->yres_virtual = var->yres;
564 if (var->xres_virtual < var->xres) 564 if (var->xres_virtual < var->xres)
@@ -573,7 +573,7 @@ static int matroxfb_decode_var(CPMINFO struct fb_var_screeninfo *var, int *visua
573 /* There is hardware bug that no line can cross 4MB boundary */ 573 /* There is hardware bug that no line can cross 4MB boundary */
574 /* give up for CFB24, it is impossible to easy workaround it */ 574 /* give up for CFB24, it is impossible to easy workaround it */
575 /* for other try to do something */ 575 /* for other try to do something */
576 if (!ACCESS_FBINFO(capable.cross4MB) && (memlen > 0x400000)) { 576 if (!minfo->capable.cross4MB && (memlen > 0x400000)) {
577 if (bpp == 24) { 577 if (bpp == 24) {
578 /* sorry */ 578 /* sorry */
579 } else { 579 } else {
@@ -653,20 +653,20 @@ static int matroxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
653 * != 0 for invalid regno. 653 * != 0 for invalid regno.
654 */ 654 */
655 655
656 if (regno >= ACCESS_FBINFO(curr.cmap_len)) 656 if (regno >= minfo->curr.cmap_len)
657 return 1; 657 return 1;
658 658
659 if (ACCESS_FBINFO(fbcon).var.grayscale) { 659 if (minfo->fbcon.var.grayscale) {
660 /* gray = 0.30*R + 0.59*G + 0.11*B */ 660 /* gray = 0.30*R + 0.59*G + 0.11*B */
661 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; 661 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
662 } 662 }
663 663
664 red = CNVT_TOHW(red, ACCESS_FBINFO(fbcon).var.red.length); 664 red = CNVT_TOHW(red, minfo->fbcon.var.red.length);
665 green = CNVT_TOHW(green, ACCESS_FBINFO(fbcon).var.green.length); 665 green = CNVT_TOHW(green, minfo->fbcon.var.green.length);
666 blue = CNVT_TOHW(blue, ACCESS_FBINFO(fbcon).var.blue.length); 666 blue = CNVT_TOHW(blue, minfo->fbcon.var.blue.length);
667 transp = CNVT_TOHW(transp, ACCESS_FBINFO(fbcon).var.transp.length); 667 transp = CNVT_TOHW(transp, minfo->fbcon.var.transp.length);
668 668
669 switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) { 669 switch (minfo->fbcon.var.bits_per_pixel) {
670 case 4: 670 case 4:
671 case 8: 671 case 8:
672 mga_outb(M_DAC_REG, regno); 672 mga_outb(M_DAC_REG, regno);
@@ -679,22 +679,22 @@ static int matroxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
679 break; 679 break;
680 { 680 {
681 u_int16_t col = 681 u_int16_t col =
682 (red << ACCESS_FBINFO(fbcon).var.red.offset) | 682 (red << minfo->fbcon.var.red.offset) |
683 (green << ACCESS_FBINFO(fbcon).var.green.offset) | 683 (green << minfo->fbcon.var.green.offset) |
684 (blue << ACCESS_FBINFO(fbcon).var.blue.offset) | 684 (blue << minfo->fbcon.var.blue.offset) |
685 (transp << ACCESS_FBINFO(fbcon).var.transp.offset); /* for 1:5:5:5 */ 685 (transp << minfo->fbcon.var.transp.offset); /* for 1:5:5:5 */
686 ACCESS_FBINFO(cmap[regno]) = col | (col << 16); 686 minfo->cmap[regno] = col | (col << 16);
687 } 687 }
688 break; 688 break;
689 case 24: 689 case 24:
690 case 32: 690 case 32:
691 if (regno >= 16) 691 if (regno >= 16)
692 break; 692 break;
693 ACCESS_FBINFO(cmap[regno]) = 693 minfo->cmap[regno] =
694 (red << ACCESS_FBINFO(fbcon).var.red.offset) | 694 (red << minfo->fbcon.var.red.offset) |
695 (green << ACCESS_FBINFO(fbcon).var.green.offset) | 695 (green << minfo->fbcon.var.green.offset) |
696 (blue << ACCESS_FBINFO(fbcon).var.blue.offset) | 696 (blue << minfo->fbcon.var.blue.offset) |
697 (transp << ACCESS_FBINFO(fbcon).var.transp.offset); /* 8:8:8:8 */ 697 (transp << minfo->fbcon.var.transp.offset); /* 8:8:8:8 */
698 break; 698 break;
699 } 699 }
700 return 0; 700 return 0;
@@ -702,7 +702,7 @@ static int matroxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
702 702
703static void matroxfb_init_fix(WPMINFO2) 703static void matroxfb_init_fix(WPMINFO2)
704{ 704{
705 struct fb_fix_screeninfo *fix = &ACCESS_FBINFO(fbcon).fix; 705 struct fb_fix_screeninfo *fix = &minfo->fbcon.fix;
706 DBG(__func__) 706 DBG(__func__)
707 707
708 strcpy(fix->id,"MATROX"); 708 strcpy(fix->id,"MATROX");
@@ -710,20 +710,20 @@ static void matroxfb_init_fix(WPMINFO2)
710 fix->xpanstep = 8; /* 8 for 8bpp, 4 for 16bpp, 2 for 32bpp */ 710 fix->xpanstep = 8; /* 8 for 8bpp, 4 for 16bpp, 2 for 32bpp */
711 fix->ypanstep = 1; 711 fix->ypanstep = 1;
712 fix->ywrapstep = 0; 712 fix->ywrapstep = 0;
713 fix->mmio_start = ACCESS_FBINFO(mmio.base); 713 fix->mmio_start = minfo->mmio.base;
714 fix->mmio_len = ACCESS_FBINFO(mmio.len); 714 fix->mmio_len = minfo->mmio.len;
715 fix->accel = ACCESS_FBINFO(devflags.accelerator); 715 fix->accel = minfo->devflags.accelerator;
716} 716}
717 717
718static void matroxfb_update_fix(WPMINFO2) 718static void matroxfb_update_fix(WPMINFO2)
719{ 719{
720 struct fb_fix_screeninfo *fix = &ACCESS_FBINFO(fbcon).fix; 720 struct fb_fix_screeninfo *fix = &minfo->fbcon.fix;
721 DBG(__func__) 721 DBG(__func__)
722 722
723 mutex_lock(&ACCESS_FBINFO(fbcon).mm_lock); 723 mutex_lock(&minfo->fbcon.mm_lock);
724 fix->smem_start = ACCESS_FBINFO(video.base) + ACCESS_FBINFO(curr.ydstorg.bytes); 724 fix->smem_start = minfo->video.base + minfo->curr.ydstorg.bytes;
725 fix->smem_len = ACCESS_FBINFO(video.len_usable) - ACCESS_FBINFO(curr.ydstorg.bytes); 725 fix->smem_len = minfo->video.len_usable - minfo->curr.ydstorg.bytes;
726 mutex_unlock(&ACCESS_FBINFO(fbcon).mm_lock); 726 mutex_unlock(&minfo->fbcon.mm_lock);
727} 727}
728 728
729static int matroxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 729static int matroxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
@@ -734,7 +734,7 @@ static int matroxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *inf
734 unsigned int ydstorg; 734 unsigned int ydstorg;
735 MINFO_FROM_INFO(info); 735 MINFO_FROM_INFO(info);
736 736
737 if (ACCESS_FBINFO(dead)) { 737 if (minfo->dead) {
738 return -ENXIO; 738 return -ENXIO;
739 } 739 }
740 if ((err = matroxfb_decode_var(PMINFO var, &visual, &cmap_len, &ydstorg)) != 0) 740 if ((err = matroxfb_decode_var(PMINFO var, &visual, &cmap_len, &ydstorg)) != 0)
@@ -753,31 +753,31 @@ static int matroxfb_set_par(struct fb_info *info)
753 753
754 DBG(__func__) 754 DBG(__func__)
755 755
756 if (ACCESS_FBINFO(dead)) { 756 if (minfo->dead) {
757 return -ENXIO; 757 return -ENXIO;
758 } 758 }
759 759
760 var = &info->var; 760 var = &info->var;
761 if ((err = matroxfb_decode_var(PMINFO var, &visual, &cmap_len, &ydstorg)) != 0) 761 if ((err = matroxfb_decode_var(PMINFO var, &visual, &cmap_len, &ydstorg)) != 0)
762 return err; 762 return err;
763 ACCESS_FBINFO(fbcon.screen_base) = vaddr_va(ACCESS_FBINFO(video.vbase)) + ydstorg; 763 minfo->fbcon.screen_base = vaddr_va(minfo->video.vbase) + ydstorg;
764 matroxfb_update_fix(PMINFO2); 764 matroxfb_update_fix(PMINFO2);
765 ACCESS_FBINFO(fbcon).fix.visual = visual; 765 minfo->fbcon.fix.visual = visual;
766 ACCESS_FBINFO(fbcon).fix.type = FB_TYPE_PACKED_PIXELS; 766 minfo->fbcon.fix.type = FB_TYPE_PACKED_PIXELS;
767 ACCESS_FBINFO(fbcon).fix.type_aux = 0; 767 minfo->fbcon.fix.type_aux = 0;
768 ACCESS_FBINFO(fbcon).fix.line_length = (var->xres_virtual * var->bits_per_pixel) >> 3; 768 minfo->fbcon.fix.line_length = (var->xres_virtual * var->bits_per_pixel) >> 3;
769 { 769 {
770 unsigned int pos; 770 unsigned int pos;
771 771
772 ACCESS_FBINFO(curr.cmap_len) = cmap_len; 772 minfo->curr.cmap_len = cmap_len;
773 ydstorg += ACCESS_FBINFO(devflags.ydstorg); 773 ydstorg += minfo->devflags.ydstorg;
774 ACCESS_FBINFO(curr.ydstorg.bytes) = ydstorg; 774 minfo->curr.ydstorg.bytes = ydstorg;
775 ACCESS_FBINFO(curr.ydstorg.chunks) = ydstorg >> (isInterleave(MINFO)?3:2); 775 minfo->curr.ydstorg.chunks = ydstorg >> (isInterleave(minfo) ? 3 : 2);
776 if (var->bits_per_pixel == 4) 776 if (var->bits_per_pixel == 4)
777 ACCESS_FBINFO(curr.ydstorg.pixels) = ydstorg; 777 minfo->curr.ydstorg.pixels = ydstorg;
778 else 778 else
779 ACCESS_FBINFO(curr.ydstorg.pixels) = (ydstorg * 8) / var->bits_per_pixel; 779 minfo->curr.ydstorg.pixels = (ydstorg * 8) / var->bits_per_pixel;
780 ACCESS_FBINFO(curr.final_bppShift) = matroxfb_get_final_bppShift(PMINFO var->bits_per_pixel); 780 minfo->curr.final_bppShift = matroxfb_get_final_bppShift(PMINFO var->bits_per_pixel);
781 { struct my_timming mt; 781 { struct my_timming mt;
782 struct matrox_hw_state* hw; 782 struct matrox_hw_state* hw;
783 int out; 783 int out;
@@ -793,46 +793,46 @@ static int matroxfb_set_par(struct fb_info *info)
793 default: mt.delay = 31 + 8; break; 793 default: mt.delay = 31 + 8; break;
794 } 794 }
795 795
796 hw = &ACCESS_FBINFO(hw); 796 hw = &minfo->hw;
797 797
798 down_read(&ACCESS_FBINFO(altout).lock); 798 down_read(&minfo->altout.lock);
799 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) { 799 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
800 if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC1 && 800 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
801 ACCESS_FBINFO(outputs[out]).output->compute) { 801 minfo->outputs[out].output->compute) {
802 ACCESS_FBINFO(outputs[out]).output->compute(ACCESS_FBINFO(outputs[out]).data, &mt); 802 minfo->outputs[out].output->compute(minfo->outputs[out].data, &mt);
803 } 803 }
804 } 804 }
805 up_read(&ACCESS_FBINFO(altout).lock); 805 up_read(&minfo->altout.lock);
806 ACCESS_FBINFO(crtc1).pixclock = mt.pixclock; 806 minfo->crtc1.pixclock = mt.pixclock;
807 ACCESS_FBINFO(crtc1).mnp = mt.mnp; 807 minfo->crtc1.mnp = mt.mnp;
808 ACCESS_FBINFO(hw_switch->init(PMINFO &mt)); 808 minfo->hw_switch->init(PMINFO &mt);
809 pos = (var->yoffset * var->xres_virtual + var->xoffset) * ACCESS_FBINFO(curr.final_bppShift) / 32; 809 pos = (var->yoffset * var->xres_virtual + var->xoffset) * minfo->curr.final_bppShift / 32;
810 pos += ACCESS_FBINFO(curr.ydstorg.chunks); 810 pos += minfo->curr.ydstorg.chunks;
811 811
812 hw->CRTC[0x0D] = pos & 0xFF; 812 hw->CRTC[0x0D] = pos & 0xFF;
813 hw->CRTC[0x0C] = (pos & 0xFF00) >> 8; 813 hw->CRTC[0x0C] = (pos & 0xFF00) >> 8;
814 hw->CRTCEXT[0] = (hw->CRTCEXT[0] & 0xF0) | ((pos >> 16) & 0x0F) | ((pos >> 14) & 0x40); 814 hw->CRTCEXT[0] = (hw->CRTCEXT[0] & 0xF0) | ((pos >> 16) & 0x0F) | ((pos >> 14) & 0x40);
815 hw->CRTCEXT[8] = pos >> 21; 815 hw->CRTCEXT[8] = pos >> 21;
816 ACCESS_FBINFO(hw_switch->restore(PMINFO2)); 816 minfo->hw_switch->restore(PMINFO2);
817 update_crtc2(PMINFO pos); 817 update_crtc2(PMINFO pos);
818 down_read(&ACCESS_FBINFO(altout).lock); 818 down_read(&minfo->altout.lock);
819 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) { 819 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
820 if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC1 && 820 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
821 ACCESS_FBINFO(outputs[out]).output->program) { 821 minfo->outputs[out].output->program) {
822 ACCESS_FBINFO(outputs[out]).output->program(ACCESS_FBINFO(outputs[out]).data); 822 minfo->outputs[out].output->program(minfo->outputs[out].data);
823 } 823 }
824 } 824 }
825 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) { 825 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
826 if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC1 && 826 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
827 ACCESS_FBINFO(outputs[out]).output->start) { 827 minfo->outputs[out].output->start) {
828 ACCESS_FBINFO(outputs[out]).output->start(ACCESS_FBINFO(outputs[out]).data); 828 minfo->outputs[out].output->start(minfo->outputs[out].data);
829 } 829 }
830 } 830 }
831 up_read(&ACCESS_FBINFO(altout).lock); 831 up_read(&minfo->altout.lock);
832 matrox_cfbX_init(PMINFO2); 832 matrox_cfbX_init(PMINFO2);
833 } 833 }
834 } 834 }
835 ACCESS_FBINFO(initialized) = 1; 835 minfo->initialized = 1;
836 return 0; 836 return 0;
837} 837}
838 838
@@ -853,13 +853,13 @@ static int matroxfb_get_vblank(WPMINFO struct fb_vblank *vblank)
853 vblank->flags |= FB_VBLANK_HBLANKING; 853 vblank->flags |= FB_VBLANK_HBLANKING;
854 if (sts1 & 8) 854 if (sts1 & 8)
855 vblank->flags |= FB_VBLANK_VSYNCING; 855 vblank->flags |= FB_VBLANK_VSYNCING;
856 if (vblank->vcount >= ACCESS_FBINFO(fbcon).var.yres) 856 if (vblank->vcount >= minfo->fbcon.var.yres)
857 vblank->flags |= FB_VBLANK_VBLANKING; 857 vblank->flags |= FB_VBLANK_VBLANKING;
858 if (test_bit(0, &ACCESS_FBINFO(irq_flags))) { 858 if (test_bit(0, &minfo->irq_flags)) {
859 vblank->flags |= FB_VBLANK_HAVE_COUNT; 859 vblank->flags |= FB_VBLANK_HAVE_COUNT;
860 /* Only one writer, aligned int value... 860 /* Only one writer, aligned int value...
861 it should work without lock and without atomic_t */ 861 it should work without lock and without atomic_t */
862 vblank->count = ACCESS_FBINFO(crtc1).vsync.cnt; 862 vblank->count = minfo->crtc1.vsync.cnt;
863 } 863 }
864 return 0; 864 return 0;
865} 865}
@@ -876,7 +876,7 @@ static int matroxfb_ioctl(struct fb_info *info,
876 876
877 DBG(__func__) 877 DBG(__func__)
878 878
879 if (ACCESS_FBINFO(dead)) { 879 if (minfo->dead) {
880 return -ENXIO; 880 return -ENXIO;
881 } 881 }
882 882
@@ -912,8 +912,8 @@ static int matroxfb_ioctl(struct fb_info *info,
912 return -EFAULT; 912 return -EFAULT;
913 if (mom.output >= MATROXFB_MAX_OUTPUTS) 913 if (mom.output >= MATROXFB_MAX_OUTPUTS)
914 return -ENXIO; 914 return -ENXIO;
915 down_read(&ACCESS_FBINFO(altout.lock)); 915 down_read(&minfo->altout.lock);
916 oproc = ACCESS_FBINFO(outputs[mom.output]).output; 916 oproc = minfo->outputs[mom.output].output;
917 if (!oproc) { 917 if (!oproc) {
918 val = -ENXIO; 918 val = -ENXIO;
919 } else if (!oproc->verifymode) { 919 } else if (!oproc->verifymode) {
@@ -923,18 +923,18 @@ static int matroxfb_ioctl(struct fb_info *info,
923 val = -EINVAL; 923 val = -EINVAL;
924 } 924 }
925 } else { 925 } else {
926 val = oproc->verifymode(ACCESS_FBINFO(outputs[mom.output]).data, mom.mode); 926 val = oproc->verifymode(minfo->outputs[mom.output].data, mom.mode);
927 } 927 }
928 if (!val) { 928 if (!val) {
929 if (ACCESS_FBINFO(outputs[mom.output]).mode != mom.mode) { 929 if (minfo->outputs[mom.output].mode != mom.mode) {
930 ACCESS_FBINFO(outputs[mom.output]).mode = mom.mode; 930 minfo->outputs[mom.output].mode = mom.mode;
931 val = 1; 931 val = 1;
932 } 932 }
933 } 933 }
934 up_read(&ACCESS_FBINFO(altout.lock)); 934 up_read(&minfo->altout.lock);
935 if (val != 1) 935 if (val != 1)
936 return val; 936 return val;
937 switch (ACCESS_FBINFO(outputs[mom.output]).src) { 937 switch (minfo->outputs[mom.output].src) {
938 case MATROXFB_SRC_CRTC1: 938 case MATROXFB_SRC_CRTC1:
939 matroxfb_set_par(info); 939 matroxfb_set_par(info);
940 break; 940 break;
@@ -942,11 +942,11 @@ static int matroxfb_ioctl(struct fb_info *info,
942 { 942 {
943 struct matroxfb_dh_fb_info* crtc2; 943 struct matroxfb_dh_fb_info* crtc2;
944 944
945 down_read(&ACCESS_FBINFO(crtc2.lock)); 945 down_read(&minfo->crtc2.lock);
946 crtc2 = ACCESS_FBINFO(crtc2.info); 946 crtc2 = minfo->crtc2.info;
947 if (crtc2) 947 if (crtc2)
948 crtc2->fbcon.fbops->fb_set_par(&crtc2->fbcon); 948 crtc2->fbcon.fbops->fb_set_par(&crtc2->fbcon);
949 up_read(&ACCESS_FBINFO(crtc2.lock)); 949 up_read(&minfo->crtc2.lock);
950 } 950 }
951 break; 951 break;
952 } 952 }
@@ -962,15 +962,15 @@ static int matroxfb_ioctl(struct fb_info *info,
962 return -EFAULT; 962 return -EFAULT;
963 if (mom.output >= MATROXFB_MAX_OUTPUTS) 963 if (mom.output >= MATROXFB_MAX_OUTPUTS)
964 return -ENXIO; 964 return -ENXIO;
965 down_read(&ACCESS_FBINFO(altout.lock)); 965 down_read(&minfo->altout.lock);
966 oproc = ACCESS_FBINFO(outputs[mom.output]).output; 966 oproc = minfo->outputs[mom.output].output;
967 if (!oproc) { 967 if (!oproc) {
968 val = -ENXIO; 968 val = -ENXIO;
969 } else { 969 } else {
970 mom.mode = ACCESS_FBINFO(outputs[mom.output]).mode; 970 mom.mode = minfo->outputs[mom.output].mode;
971 val = 0; 971 val = 0;
972 } 972 }
973 up_read(&ACCESS_FBINFO(altout.lock)); 973 up_read(&minfo->altout.lock);
974 if (val) 974 if (val)
975 return val; 975 return val;
976 if (copy_to_user(argp, &mom, sizeof(mom))) 976 if (copy_to_user(argp, &mom, sizeof(mom)))
@@ -989,9 +989,9 @@ static int matroxfb_ioctl(struct fb_info *info,
989 if (tmp & (1 << i)) { 989 if (tmp & (1 << i)) {
990 if (i >= MATROXFB_MAX_OUTPUTS) 990 if (i >= MATROXFB_MAX_OUTPUTS)
991 return -ENXIO; 991 return -ENXIO;
992 if (!ACCESS_FBINFO(outputs[i]).output) 992 if (!minfo->outputs[i].output)
993 return -ENXIO; 993 return -ENXIO;
994 switch (ACCESS_FBINFO(outputs[i]).src) { 994 switch (minfo->outputs[i].src) {
995 case MATROXFB_SRC_NONE: 995 case MATROXFB_SRC_NONE:
996 case MATROXFB_SRC_CRTC1: 996 case MATROXFB_SRC_CRTC1:
997 break; 997 break;
@@ -1000,12 +1000,12 @@ static int matroxfb_ioctl(struct fb_info *info,
1000 } 1000 }
1001 } 1001 }
1002 } 1002 }
1003 if (ACCESS_FBINFO(devflags.panellink)) { 1003 if (minfo->devflags.panellink) {
1004 if (tmp & MATROXFB_OUTPUT_CONN_DFP) { 1004 if (tmp & MATROXFB_OUTPUT_CONN_DFP) {
1005 if (tmp & MATROXFB_OUTPUT_CONN_SECONDARY) 1005 if (tmp & MATROXFB_OUTPUT_CONN_SECONDARY)
1006 return -EINVAL; 1006 return -EINVAL;
1007 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) { 1007 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1008 if (ACCESS_FBINFO(outputs[i]).src == MATROXFB_SRC_CRTC2) { 1008 if (minfo->outputs[i].src == MATROXFB_SRC_CRTC2) {
1009 return -EBUSY; 1009 return -EBUSY;
1010 } 1010 }
1011 } 1011 }
@@ -1014,13 +1014,13 @@ static int matroxfb_ioctl(struct fb_info *info,
1014 changes = 0; 1014 changes = 0;
1015 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) { 1015 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1016 if (tmp & (1 << i)) { 1016 if (tmp & (1 << i)) {
1017 if (ACCESS_FBINFO(outputs[i]).src != MATROXFB_SRC_CRTC1) { 1017 if (minfo->outputs[i].src != MATROXFB_SRC_CRTC1) {
1018 changes = 1; 1018 changes = 1;
1019 ACCESS_FBINFO(outputs[i]).src = MATROXFB_SRC_CRTC1; 1019 minfo->outputs[i].src = MATROXFB_SRC_CRTC1;
1020 } 1020 }
1021 } else if (ACCESS_FBINFO(outputs[i]).src == MATROXFB_SRC_CRTC1) { 1021 } else if (minfo->outputs[i].src == MATROXFB_SRC_CRTC1) {
1022 changes = 1; 1022 changes = 1;
1023 ACCESS_FBINFO(outputs[i]).src = MATROXFB_SRC_NONE; 1023 minfo->outputs[i].src = MATROXFB_SRC_NONE;
1024 } 1024 }
1025 } 1025 }
1026 if (!changes) 1026 if (!changes)
@@ -1034,7 +1034,7 @@ static int matroxfb_ioctl(struct fb_info *info,
1034 int i; 1034 int i;
1035 1035
1036 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) { 1036 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1037 if (ACCESS_FBINFO(outputs[i]).src == MATROXFB_SRC_CRTC1) { 1037 if (minfo->outputs[i].src == MATROXFB_SRC_CRTC1) {
1038 conn |= 1 << i; 1038 conn |= 1 << i;
1039 } 1039 }
1040 } 1040 }
@@ -1048,8 +1048,8 @@ static int matroxfb_ioctl(struct fb_info *info,
1048 int i; 1048 int i;
1049 1049
1050 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) { 1050 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1051 if (ACCESS_FBINFO(outputs[i]).output) { 1051 if (minfo->outputs[i].output) {
1052 switch (ACCESS_FBINFO(outputs[i]).src) { 1052 switch (minfo->outputs[i].src) {
1053 case MATROXFB_SRC_NONE: 1053 case MATROXFB_SRC_NONE:
1054 case MATROXFB_SRC_CRTC1: 1054 case MATROXFB_SRC_CRTC1:
1055 conn |= 1 << i; 1055 conn |= 1 << i;
@@ -1057,7 +1057,7 @@ static int matroxfb_ioctl(struct fb_info *info,
1057 } 1057 }
1058 } 1058 }
1059 } 1059 }
1060 if (ACCESS_FBINFO(devflags.panellink)) { 1060 if (minfo->devflags.panellink) {
1061 if (conn & MATROXFB_OUTPUT_CONN_DFP) 1061 if (conn & MATROXFB_OUTPUT_CONN_DFP)
1062 conn &= ~MATROXFB_OUTPUT_CONN_SECONDARY; 1062 conn &= ~MATROXFB_OUTPUT_CONN_SECONDARY;
1063 if (conn & MATROXFB_OUTPUT_CONN_SECONDARY) 1063 if (conn & MATROXFB_OUTPUT_CONN_SECONDARY)
@@ -1073,7 +1073,7 @@ static int matroxfb_ioctl(struct fb_info *info,
1073 int i; 1073 int i;
1074 1074
1075 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) { 1075 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
1076 if (ACCESS_FBINFO(outputs[i]).output) { 1076 if (minfo->outputs[i].output) {
1077 conn |= 1 << i; 1077 conn |= 1 << i;
1078 } 1078 }
1079 } 1079 }
@@ -1088,7 +1088,7 @@ static int matroxfb_ioctl(struct fb_info *info,
1088 memset(&r, 0, sizeof(r)); 1088 memset(&r, 0, sizeof(r));
1089 strcpy(r.driver, "matroxfb"); 1089 strcpy(r.driver, "matroxfb");
1090 strcpy(r.card, "Matrox"); 1090 strcpy(r.card, "Matrox");
1091 sprintf(r.bus_info, "PCI:%s", pci_name(ACCESS_FBINFO(pcidev))); 1091 sprintf(r.bus_info, "PCI:%s", pci_name(minfo->pcidev));
1092 r.version = KERNEL_VERSION(1,0,0); 1092 r.version = KERNEL_VERSION(1,0,0);
1093 r.capabilities = V4L2_CAP_VIDEO_OUTPUT; 1093 r.capabilities = V4L2_CAP_VIDEO_OUTPUT;
1094 if (copy_to_user(argp, &r, sizeof(r))) 1094 if (copy_to_user(argp, &r, sizeof(r)))
@@ -1104,15 +1104,15 @@ static int matroxfb_ioctl(struct fb_info *info,
1104 if (copy_from_user(&qctrl, argp, sizeof(qctrl))) 1104 if (copy_from_user(&qctrl, argp, sizeof(qctrl)))
1105 return -EFAULT; 1105 return -EFAULT;
1106 1106
1107 down_read(&ACCESS_FBINFO(altout).lock); 1107 down_read(&minfo->altout.lock);
1108 if (!ACCESS_FBINFO(outputs[1]).output) { 1108 if (!minfo->outputs[1].output) {
1109 err = -ENXIO; 1109 err = -ENXIO;
1110 } else if (ACCESS_FBINFO(outputs[1]).output->getqueryctrl) { 1110 } else if (minfo->outputs[1].output->getqueryctrl) {
1111 err = ACCESS_FBINFO(outputs[1]).output->getqueryctrl(ACCESS_FBINFO(outputs[1]).data, &qctrl); 1111 err = minfo->outputs[1].output->getqueryctrl(minfo->outputs[1].data, &qctrl);
1112 } else { 1112 } else {
1113 err = -EINVAL; 1113 err = -EINVAL;
1114 } 1114 }
1115 up_read(&ACCESS_FBINFO(altout).lock); 1115 up_read(&minfo->altout.lock);
1116 if (err >= 0 && 1116 if (err >= 0 &&
1117 copy_to_user(argp, &qctrl, sizeof(qctrl))) 1117 copy_to_user(argp, &qctrl, sizeof(qctrl)))
1118 return -EFAULT; 1118 return -EFAULT;
@@ -1126,15 +1126,15 @@ static int matroxfb_ioctl(struct fb_info *info,
1126 if (copy_from_user(&ctrl, argp, sizeof(ctrl))) 1126 if (copy_from_user(&ctrl, argp, sizeof(ctrl)))
1127 return -EFAULT; 1127 return -EFAULT;
1128 1128
1129 down_read(&ACCESS_FBINFO(altout).lock); 1129 down_read(&minfo->altout.lock);
1130 if (!ACCESS_FBINFO(outputs[1]).output) { 1130 if (!minfo->outputs[1].output) {
1131 err = -ENXIO; 1131 err = -ENXIO;
1132 } else if (ACCESS_FBINFO(outputs[1]).output->getctrl) { 1132 } else if (minfo->outputs[1].output->getctrl) {
1133 err = ACCESS_FBINFO(outputs[1]).output->getctrl(ACCESS_FBINFO(outputs[1]).data, &ctrl); 1133 err = minfo->outputs[1].output->getctrl(minfo->outputs[1].data, &ctrl);
1134 } else { 1134 } else {
1135 err = -EINVAL; 1135 err = -EINVAL;
1136 } 1136 }
1137 up_read(&ACCESS_FBINFO(altout).lock); 1137 up_read(&minfo->altout.lock);
1138 if (err >= 0 && 1138 if (err >= 0 &&
1139 copy_to_user(argp, &ctrl, sizeof(ctrl))) 1139 copy_to_user(argp, &ctrl, sizeof(ctrl)))
1140 return -EFAULT; 1140 return -EFAULT;
@@ -1149,15 +1149,15 @@ static int matroxfb_ioctl(struct fb_info *info,
1149 if (copy_from_user(&ctrl, argp, sizeof(ctrl))) 1149 if (copy_from_user(&ctrl, argp, sizeof(ctrl)))
1150 return -EFAULT; 1150 return -EFAULT;
1151 1151
1152 down_read(&ACCESS_FBINFO(altout).lock); 1152 down_read(&minfo->altout.lock);
1153 if (!ACCESS_FBINFO(outputs[1]).output) { 1153 if (!minfo->outputs[1].output) {
1154 err = -ENXIO; 1154 err = -ENXIO;
1155 } else if (ACCESS_FBINFO(outputs[1]).output->setctrl) { 1155 } else if (minfo->outputs[1].output->setctrl) {
1156 err = ACCESS_FBINFO(outputs[1]).output->setctrl(ACCESS_FBINFO(outputs[1]).data, &ctrl); 1156 err = minfo->outputs[1].output->setctrl(minfo->outputs[1].data, &ctrl);
1157 } else { 1157 } else {
1158 err = -EINVAL; 1158 err = -EINVAL;
1159 } 1159 }
1160 up_read(&ACCESS_FBINFO(altout).lock); 1160 up_read(&minfo->altout.lock);
1161 return err; 1161 return err;
1162 } 1162 }
1163 } 1163 }
@@ -1175,7 +1175,7 @@ static int matroxfb_blank(int blank, struct fb_info *info)
1175 1175
1176 DBG(__func__) 1176 DBG(__func__)
1177 1177
1178 if (ACCESS_FBINFO(dead)) 1178 if (minfo->dead)
1179 return 1; 1179 return 1;
1180 1180
1181 switch (blank) { 1181 switch (blank) {
@@ -1287,7 +1287,7 @@ static int matroxfb_getmemory(WPMINFO unsigned int maxSize, unsigned int *realSi
1287 1287
1288 DBG(__func__) 1288 DBG(__func__)
1289 1289
1290 vm = ACCESS_FBINFO(video.vbase); 1290 vm = minfo->video.vbase;
1291 maxSize &= ~0x1FFFFF; /* must be X*2MB (really it must be 2 or X*4MB) */ 1291 maxSize &= ~0x1FFFFF; /* must be X*2MB (really it must be 2 or X*4MB) */
1292 /* at least 2MB */ 1292 /* at least 2MB */
1293 if (maxSize < 0x0200000) return 0; 1293 if (maxSize < 0x0200000) return 0;
@@ -1319,7 +1319,7 @@ static int matroxfb_getmemory(WPMINFO unsigned int maxSize, unsigned int *realSi
1319 1319
1320 *realSize = offs - 0x100000; 1320 *realSize = offs - 0x100000;
1321#ifdef CONFIG_FB_MATROX_MILLENIUM 1321#ifdef CONFIG_FB_MATROX_MILLENIUM
1322 ACCESS_FBINFO(interleave) = !(!isMillenium(MINFO) || ((offs - 0x100000) & 0x3FFFFF)); 1322 minfo->interleave = !(!isMillenium(minfo) || ((offs - 0x100000) & 0x3FFFFF));
1323#endif 1323#endif
1324 return 1; 1324 return 1;
1325} 1325}
@@ -1558,12 +1558,12 @@ static void setDefaultOutputs(WPMINFO2) {
1558 unsigned int i; 1558 unsigned int i;
1559 const char* ptr; 1559 const char* ptr;
1560 1560
1561 ACCESS_FBINFO(outputs[0]).default_src = MATROXFB_SRC_CRTC1; 1561 minfo->outputs[0].default_src = MATROXFB_SRC_CRTC1;
1562 if (ACCESS_FBINFO(devflags.g450dac)) { 1562 if (minfo->devflags.g450dac) {
1563 ACCESS_FBINFO(outputs[1]).default_src = MATROXFB_SRC_CRTC1; 1563 minfo->outputs[1].default_src = MATROXFB_SRC_CRTC1;
1564 ACCESS_FBINFO(outputs[2]).default_src = MATROXFB_SRC_CRTC1; 1564 minfo->outputs[2].default_src = MATROXFB_SRC_CRTC1;
1565 } else if (dfp) { 1565 } else if (dfp) {
1566 ACCESS_FBINFO(outputs[2]).default_src = MATROXFB_SRC_CRTC1; 1566 minfo->outputs[2].default_src = MATROXFB_SRC_CRTC1;
1567 } 1567 }
1568 ptr = outputs; 1568 ptr = outputs;
1569 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) { 1569 for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
@@ -1573,11 +1573,11 @@ static void setDefaultOutputs(WPMINFO2) {
1573 break; 1573 break;
1574 } 1574 }
1575 if (c == '0') { 1575 if (c == '0') {
1576 ACCESS_FBINFO(outputs[i]).default_src = MATROXFB_SRC_NONE; 1576 minfo->outputs[i].default_src = MATROXFB_SRC_NONE;
1577 } else if (c == '1') { 1577 } else if (c == '1') {
1578 ACCESS_FBINFO(outputs[i]).default_src = MATROXFB_SRC_CRTC1; 1578 minfo->outputs[i].default_src = MATROXFB_SRC_CRTC1;
1579 } else if (c == '2' && ACCESS_FBINFO(devflags.crtc2)) { 1579 } else if (c == '2' && minfo->devflags.crtc2) {
1580 ACCESS_FBINFO(outputs[i]).default_src = MATROXFB_SRC_CRTC2; 1580 minfo->outputs[i].default_src = MATROXFB_SRC_CRTC2;
1581 } else { 1581 } else {
1582 printk(KERN_ERR "matroxfb: Unknown outputs setting\n"); 1582 printk(KERN_ERR "matroxfb: Unknown outputs setting\n");
1583 break; 1583 break;
@@ -1603,58 +1603,58 @@ static int initMatrox2(WPMINFO struct board* b){
1603 /* set default values... */ 1603 /* set default values... */
1604 vesafb_defined.accel_flags = FB_ACCELF_TEXT; 1604 vesafb_defined.accel_flags = FB_ACCELF_TEXT;
1605 1605
1606 ACCESS_FBINFO(hw_switch) = b->base->lowlevel; 1606 minfo->hw_switch = b->base->lowlevel;
1607 ACCESS_FBINFO(devflags.accelerator) = b->base->accelID; 1607 minfo->devflags.accelerator = b->base->accelID;
1608 ACCESS_FBINFO(max_pixel_clock) = b->maxclk; 1608 minfo->max_pixel_clock = b->maxclk;
1609 1609
1610 printk(KERN_INFO "matroxfb: Matrox %s detected\n", b->name); 1610 printk(KERN_INFO "matroxfb: Matrox %s detected\n", b->name);
1611 ACCESS_FBINFO(capable.plnwt) = 1; 1611 minfo->capable.plnwt = 1;
1612 ACCESS_FBINFO(chip) = b->chip; 1612 minfo->chip = b->chip;
1613 ACCESS_FBINFO(capable.srcorg) = b->flags & DEVF_SRCORG; 1613 minfo->capable.srcorg = b->flags & DEVF_SRCORG;
1614 ACCESS_FBINFO(devflags.video64bits) = b->flags & DEVF_VIDEO64BIT; 1614 minfo->devflags.video64bits = b->flags & DEVF_VIDEO64BIT;
1615 if (b->flags & DEVF_TEXT4B) { 1615 if (b->flags & DEVF_TEXT4B) {
1616 ACCESS_FBINFO(devflags.vgastep) = 4; 1616 minfo->devflags.vgastep = 4;
1617 ACCESS_FBINFO(devflags.textmode) = 4; 1617 minfo->devflags.textmode = 4;
1618 ACCESS_FBINFO(devflags.text_type_aux) = FB_AUX_TEXT_MGA_STEP16; 1618 minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP16;
1619 } else if (b->flags & DEVF_TEXT16B) { 1619 } else if (b->flags & DEVF_TEXT16B) {
1620 ACCESS_FBINFO(devflags.vgastep) = 16; 1620 minfo->devflags.vgastep = 16;
1621 ACCESS_FBINFO(devflags.textmode) = 1; 1621 minfo->devflags.textmode = 1;
1622 ACCESS_FBINFO(devflags.text_type_aux) = FB_AUX_TEXT_MGA_STEP16; 1622 minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP16;
1623 } else { 1623 } else {
1624 ACCESS_FBINFO(devflags.vgastep) = 8; 1624 minfo->devflags.vgastep = 8;
1625 ACCESS_FBINFO(devflags.textmode) = 1; 1625 minfo->devflags.textmode = 1;
1626 ACCESS_FBINFO(devflags.text_type_aux) = FB_AUX_TEXT_MGA_STEP8; 1626 minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP8;
1627 } 1627 }
1628#ifdef CONFIG_FB_MATROX_32MB 1628#ifdef CONFIG_FB_MATROX_32MB
1629 ACCESS_FBINFO(devflags.support32MB) = (b->flags & DEVF_SUPPORT32MB) != 0; 1629 minfo->devflags.support32MB = (b->flags & DEVF_SUPPORT32MB) != 0;
1630#endif 1630#endif
1631 ACCESS_FBINFO(devflags.precise_width) = !(b->flags & DEVF_ANY_VXRES); 1631 minfo->devflags.precise_width = !(b->flags & DEVF_ANY_VXRES);
1632 ACCESS_FBINFO(devflags.crtc2) = (b->flags & DEVF_CRTC2) != 0; 1632 minfo->devflags.crtc2 = (b->flags & DEVF_CRTC2) != 0;
1633 ACCESS_FBINFO(devflags.maven_capable) = (b->flags & DEVF_MAVEN_CAPABLE) != 0; 1633 minfo->devflags.maven_capable = (b->flags & DEVF_MAVEN_CAPABLE) != 0;
1634 ACCESS_FBINFO(devflags.dualhead) = (b->flags & DEVF_DUALHEAD) != 0; 1634 minfo->devflags.dualhead = (b->flags & DEVF_DUALHEAD) != 0;
1635 ACCESS_FBINFO(devflags.dfp_type) = dfp_type; 1635 minfo->devflags.dfp_type = dfp_type;
1636 ACCESS_FBINFO(devflags.g450dac) = (b->flags & DEVF_G450DAC) != 0; 1636 minfo->devflags.g450dac = (b->flags & DEVF_G450DAC) != 0;
1637 ACCESS_FBINFO(devflags.textstep) = ACCESS_FBINFO(devflags.vgastep) * ACCESS_FBINFO(devflags.textmode); 1637 minfo->devflags.textstep = minfo->devflags.vgastep * minfo->devflags.textmode;
1638 ACCESS_FBINFO(devflags.textvram) = 65536 / ACCESS_FBINFO(devflags.textmode); 1638 minfo->devflags.textvram = 65536 / minfo->devflags.textmode;
1639 setDefaultOutputs(PMINFO2); 1639 setDefaultOutputs(PMINFO2);
1640 if (b->flags & DEVF_PANELLINK_CAPABLE) { 1640 if (b->flags & DEVF_PANELLINK_CAPABLE) {
1641 ACCESS_FBINFO(outputs[2]).data = MINFO; 1641 minfo->outputs[2].data = minfo;
1642 ACCESS_FBINFO(outputs[2]).output = &panellink_output; 1642 minfo->outputs[2].output = &panellink_output;
1643 ACCESS_FBINFO(outputs[2]).src = ACCESS_FBINFO(outputs[2]).default_src; 1643 minfo->outputs[2].src = minfo->outputs[2].default_src;
1644 ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR; 1644 minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
1645 ACCESS_FBINFO(devflags.panellink) = 1; 1645 minfo->devflags.panellink = 1;
1646 } 1646 }
1647 1647
1648 if (ACCESS_FBINFO(capable.cross4MB) < 0) 1648 if (minfo->capable.cross4MB < 0)
1649 ACCESS_FBINFO(capable.cross4MB) = b->flags & DEVF_CROSS4MB; 1649 minfo->capable.cross4MB = b->flags & DEVF_CROSS4MB;
1650 if (b->flags & DEVF_SWAPS) { 1650 if (b->flags & DEVF_SWAPS) {
1651 ctrlptr_phys = pci_resource_start(ACCESS_FBINFO(pcidev), 1); 1651 ctrlptr_phys = pci_resource_start(minfo->pcidev, 1);
1652 video_base_phys = pci_resource_start(ACCESS_FBINFO(pcidev), 0); 1652 video_base_phys = pci_resource_start(minfo->pcidev, 0);
1653 ACCESS_FBINFO(devflags.fbResource) = PCI_BASE_ADDRESS_0; 1653 minfo->devflags.fbResource = PCI_BASE_ADDRESS_0;
1654 } else { 1654 } else {
1655 ctrlptr_phys = pci_resource_start(ACCESS_FBINFO(pcidev), 0); 1655 ctrlptr_phys = pci_resource_start(minfo->pcidev, 0);
1656 video_base_phys = pci_resource_start(ACCESS_FBINFO(pcidev), 1); 1656 video_base_phys = pci_resource_start(minfo->pcidev, 1);
1657 ACCESS_FBINFO(devflags.fbResource) = PCI_BASE_ADDRESS_1; 1657 minfo->devflags.fbResource = PCI_BASE_ADDRESS_1;
1658 } 1658 }
1659 err = -EINVAL; 1659 err = -EINVAL;
1660 if (!ctrlptr_phys) { 1660 if (!ctrlptr_phys) {
@@ -1672,7 +1672,7 @@ static int initMatrox2(WPMINFO struct board* b){
1672 if (!request_mem_region(video_base_phys, memsize, "matroxfb FB")) { 1672 if (!request_mem_region(video_base_phys, memsize, "matroxfb FB")) {
1673 goto failCtrlMR; 1673 goto failCtrlMR;
1674 } 1674 }
1675 ACCESS_FBINFO(video.len_maximum) = memsize; 1675 minfo->video.len_maximum = memsize;
1676 /* convert mem (autodetect k, M) */ 1676 /* convert mem (autodetect k, M) */
1677 if (mem < 1024) mem *= 1024; 1677 if (mem < 1024) mem *= 1024;
1678 if (mem < 0x00100000) mem *= 1024; 1678 if (mem < 0x00100000) mem *= 1024;
@@ -1680,14 +1680,14 @@ static int initMatrox2(WPMINFO struct board* b){
1680 if (mem && (mem < memsize)) 1680 if (mem && (mem < memsize))
1681 memsize = mem; 1681 memsize = mem;
1682 err = -ENOMEM; 1682 err = -ENOMEM;
1683 if (mga_ioremap(ctrlptr_phys, 16384, MGA_IOREMAP_MMIO, &ACCESS_FBINFO(mmio.vbase))) { 1683 if (mga_ioremap(ctrlptr_phys, 16384, MGA_IOREMAP_MMIO, &minfo->mmio.vbase)) {
1684 printk(KERN_ERR "matroxfb: cannot ioremap(%lX, 16384), matroxfb disabled\n", ctrlptr_phys); 1684 printk(KERN_ERR "matroxfb: cannot ioremap(%lX, 16384), matroxfb disabled\n", ctrlptr_phys);
1685 goto failVideoMR; 1685 goto failVideoMR;
1686 } 1686 }
1687 ACCESS_FBINFO(mmio.base) = ctrlptr_phys; 1687 minfo->mmio.base = ctrlptr_phys;
1688 ACCESS_FBINFO(mmio.len) = 16384; 1688 minfo->mmio.len = 16384;
1689 ACCESS_FBINFO(video.base) = video_base_phys; 1689 minfo->video.base = video_base_phys;
1690 if (mga_ioremap(video_base_phys, memsize, MGA_IOREMAP_FB, &ACCESS_FBINFO(video.vbase))) { 1690 if (mga_ioremap(video_base_phys, memsize, MGA_IOREMAP_FB, &minfo->video.vbase)) {
1691 printk(KERN_ERR "matroxfb: cannot ioremap(%lX, %d), matroxfb disabled\n", 1691 printk(KERN_ERR "matroxfb: cannot ioremap(%lX, %d), matroxfb disabled\n",
1692 video_base_phys, memsize); 1692 video_base_phys, memsize);
1693 goto failCtrlIO; 1693 goto failCtrlIO;
@@ -1696,63 +1696,63 @@ static int initMatrox2(WPMINFO struct board* b){
1696 u_int32_t cmd; 1696 u_int32_t cmd;
1697 u_int32_t mga_option; 1697 u_int32_t mga_option;
1698 1698
1699 pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, &mga_option); 1699 pci_read_config_dword(minfo->pcidev, PCI_OPTION_REG, &mga_option);
1700 pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_COMMAND, &cmd); 1700 pci_read_config_dword(minfo->pcidev, PCI_COMMAND, &cmd);
1701 mga_option &= 0x7FFFFFFF; /* clear BIG_ENDIAN */ 1701 mga_option &= 0x7FFFFFFF; /* clear BIG_ENDIAN */
1702 mga_option |= MX_OPTION_BSWAP; 1702 mga_option |= MX_OPTION_BSWAP;
1703 /* disable palette snooping */ 1703 /* disable palette snooping */
1704 cmd &= ~PCI_COMMAND_VGA_PALETTE; 1704 cmd &= ~PCI_COMMAND_VGA_PALETTE;
1705 if (pci_dev_present(intel_82437)) { 1705 if (pci_dev_present(intel_82437)) {
1706 if (!(mga_option & 0x20000000) && !ACCESS_FBINFO(devflags.nopciretry)) { 1706 if (!(mga_option & 0x20000000) && !minfo->devflags.nopciretry) {
1707 printk(KERN_WARNING "matroxfb: Disabling PCI retries due to i82437 present\n"); 1707 printk(KERN_WARNING "matroxfb: Disabling PCI retries due to i82437 present\n");
1708 } 1708 }
1709 mga_option |= 0x20000000; 1709 mga_option |= 0x20000000;
1710 ACCESS_FBINFO(devflags.nopciretry) = 1; 1710 minfo->devflags.nopciretry = 1;
1711 } 1711 }
1712 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_COMMAND, cmd); 1712 pci_write_config_dword(minfo->pcidev, PCI_COMMAND, cmd);
1713 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, mga_option); 1713 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mga_option);
1714 ACCESS_FBINFO(hw).MXoptionReg = mga_option; 1714 minfo->hw.MXoptionReg = mga_option;
1715 1715
1716 /* select non-DMA memory for PCI_MGA_DATA, otherwise dump of PCI cfg space can lock PCI bus */ 1716 /* select non-DMA memory for PCI_MGA_DATA, otherwise dump of PCI cfg space can lock PCI bus */
1717 /* maybe preinit() candidate, but it is same... for all devices... at this time... */ 1717 /* maybe preinit() candidate, but it is same... for all devices... at this time... */
1718 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_MGA_INDEX, 0x00003C00); 1718 pci_write_config_dword(minfo->pcidev, PCI_MGA_INDEX, 0x00003C00);
1719 } 1719 }
1720 1720
1721 err = -ENXIO; 1721 err = -ENXIO;
1722 matroxfb_read_pins(PMINFO2); 1722 matroxfb_read_pins(PMINFO2);
1723 if (ACCESS_FBINFO(hw_switch)->preinit(PMINFO2)) { 1723 if (minfo->hw_switch->preinit(PMINFO2)) {
1724 goto failVideoIO; 1724 goto failVideoIO;
1725 } 1725 }
1726 1726
1727 err = -ENOMEM; 1727 err = -ENOMEM;
1728 if (!matroxfb_getmemory(PMINFO memsize, &ACCESS_FBINFO(video.len)) || !ACCESS_FBINFO(video.len)) { 1728 if (!matroxfb_getmemory(PMINFO memsize, &minfo->video.len) || !minfo->video.len) {
1729 printk(KERN_ERR "matroxfb: cannot determine memory size\n"); 1729 printk(KERN_ERR "matroxfb: cannot determine memory size\n");
1730 goto failVideoIO; 1730 goto failVideoIO;
1731 } 1731 }
1732 ACCESS_FBINFO(devflags.ydstorg) = 0; 1732 minfo->devflags.ydstorg = 0;
1733 1733
1734 ACCESS_FBINFO(video.base) = video_base_phys; 1734 minfo->video.base = video_base_phys;
1735 ACCESS_FBINFO(video.len_usable) = ACCESS_FBINFO(video.len); 1735 minfo->video.len_usable = minfo->video.len;
1736 if (ACCESS_FBINFO(video.len_usable) > b->base->maxdisplayable) 1736 if (minfo->video.len_usable > b->base->maxdisplayable)
1737 ACCESS_FBINFO(video.len_usable) = b->base->maxdisplayable; 1737 minfo->video.len_usable = b->base->maxdisplayable;
1738#ifdef CONFIG_MTRR 1738#ifdef CONFIG_MTRR
1739 if (mtrr) { 1739 if (mtrr) {
1740 ACCESS_FBINFO(mtrr.vram) = mtrr_add(video_base_phys, ACCESS_FBINFO(video.len), MTRR_TYPE_WRCOMB, 1); 1740 minfo->mtrr.vram = mtrr_add(video_base_phys, minfo->video.len, MTRR_TYPE_WRCOMB, 1);
1741 ACCESS_FBINFO(mtrr.vram_valid) = 1; 1741 minfo->mtrr.vram_valid = 1;
1742 printk(KERN_INFO "matroxfb: MTRR's turned on\n"); 1742 printk(KERN_INFO "matroxfb: MTRR's turned on\n");
1743 } 1743 }
1744#endif /* CONFIG_MTRR */ 1744#endif /* CONFIG_MTRR */
1745 1745
1746 if (!ACCESS_FBINFO(devflags.novga)) 1746 if (!minfo->devflags.novga)
1747 request_region(0x3C0, 32, "matrox"); 1747 request_region(0x3C0, 32, "matrox");
1748 matroxfb_g450_connect(PMINFO2); 1748 matroxfb_g450_connect(PMINFO2);
1749 ACCESS_FBINFO(hw_switch->reset(PMINFO2)); 1749 minfo->hw_switch->reset(PMINFO2);
1750 1750
1751 ACCESS_FBINFO(fbcon.monspecs.hfmin) = 0; 1751 minfo->fbcon.monspecs.hfmin = 0;
1752 ACCESS_FBINFO(fbcon.monspecs.hfmax) = fh; 1752 minfo->fbcon.monspecs.hfmax = fh;
1753 ACCESS_FBINFO(fbcon.monspecs.vfmin) = 0; 1753 minfo->fbcon.monspecs.vfmin = 0;
1754 ACCESS_FBINFO(fbcon.monspecs.vfmax) = fv; 1754 minfo->fbcon.monspecs.vfmax = fv;
1755 ACCESS_FBINFO(fbcon.monspecs.dpms) = 0; /* TBD */ 1755 minfo->fbcon.monspecs.dpms = 0; /* TBD */
1756 1756
1757 /* static settings */ 1757 /* static settings */
1758 vesafb_defined.red = colors[depth-1].red; 1758 vesafb_defined.red = colors[depth-1].red;
@@ -1764,24 +1764,24 @@ static int initMatrox2(WPMINFO struct board* b){
1764 if (noaccel) 1764 if (noaccel)
1765 vesafb_defined.accel_flags &= ~FB_ACCELF_TEXT; 1765 vesafb_defined.accel_flags &= ~FB_ACCELF_TEXT;
1766 1766
1767 ACCESS_FBINFO(fbops) = matroxfb_ops; 1767 minfo->fbops = matroxfb_ops;
1768 ACCESS_FBINFO(fbcon.fbops) = &ACCESS_FBINFO(fbops); 1768 minfo->fbcon.fbops = &minfo->fbops;
1769 ACCESS_FBINFO(fbcon.pseudo_palette) = ACCESS_FBINFO(cmap); 1769 minfo->fbcon.pseudo_palette = minfo->cmap;
1770 /* after __init time we are like module... no logo */ 1770 /* after __init time we are like module... no logo */
1771 ACCESS_FBINFO(fbcon.flags) = hotplug ? FBINFO_FLAG_MODULE : FBINFO_FLAG_DEFAULT; 1771 minfo->fbcon.flags = hotplug ? FBINFO_FLAG_MODULE : FBINFO_FLAG_DEFAULT;
1772 ACCESS_FBINFO(fbcon.flags) |= FBINFO_PARTIAL_PAN_OK | /* Prefer panning for scroll under MC viewer/edit */ 1772 minfo->fbcon.flags |= FBINFO_PARTIAL_PAN_OK | /* Prefer panning for scroll under MC viewer/edit */
1773 FBINFO_HWACCEL_COPYAREA | /* We have hw-assisted bmove */ 1773 FBINFO_HWACCEL_COPYAREA | /* We have hw-assisted bmove */
1774 FBINFO_HWACCEL_FILLRECT | /* And fillrect */ 1774 FBINFO_HWACCEL_FILLRECT | /* And fillrect */
1775 FBINFO_HWACCEL_IMAGEBLIT | /* And imageblit */ 1775 FBINFO_HWACCEL_IMAGEBLIT | /* And imageblit */
1776 FBINFO_HWACCEL_XPAN | /* And we support both horizontal */ 1776 FBINFO_HWACCEL_XPAN | /* And we support both horizontal */
1777 FBINFO_HWACCEL_YPAN; /* And vertical panning */ 1777 FBINFO_HWACCEL_YPAN; /* And vertical panning */
1778 ACCESS_FBINFO(video.len_usable) &= PAGE_MASK; 1778 minfo->video.len_usable &= PAGE_MASK;
1779 fb_alloc_cmap(&ACCESS_FBINFO(fbcon.cmap), 256, 1); 1779 fb_alloc_cmap(&minfo->fbcon.cmap, 256, 1);
1780 1780
1781#ifndef MODULE 1781#ifndef MODULE
1782 /* mode database is marked __init!!! */ 1782 /* mode database is marked __init!!! */
1783 if (!hotplug) { 1783 if (!hotplug) {
1784 fb_find_mode(&vesafb_defined, &ACCESS_FBINFO(fbcon), videomode[0]?videomode:NULL, 1784 fb_find_mode(&vesafb_defined, &minfo->fbcon, videomode[0] ? videomode : NULL,
1785 NULL, 0, &defaultmode, vesafb_defined.bits_per_pixel); 1785 NULL, 0, &defaultmode, vesafb_defined.bits_per_pixel);
1786 } 1786 }
1787#endif /* !MODULE */ 1787#endif /* !MODULE */
@@ -1871,51 +1871,51 @@ static int initMatrox2(WPMINFO struct board* b){
1871 to yres_virtual * xres_virtual < 2^32 */ 1871 to yres_virtual * xres_virtual < 2^32 */
1872 } 1872 }
1873 matroxfb_init_fix(PMINFO2); 1873 matroxfb_init_fix(PMINFO2);
1874 ACCESS_FBINFO(fbcon.screen_base) = vaddr_va(ACCESS_FBINFO(video.vbase)); 1874 minfo->fbcon.screen_base = vaddr_va(minfo->video.vbase);
1875 /* Normalize values (namely yres_virtual) */ 1875 /* Normalize values (namely yres_virtual) */
1876 matroxfb_check_var(&vesafb_defined, &ACCESS_FBINFO(fbcon)); 1876 matroxfb_check_var(&vesafb_defined, &minfo->fbcon);
1877 /* And put it into "current" var. Do NOT program hardware yet, or we'll not take over 1877 /* And put it into "current" var. Do NOT program hardware yet, or we'll not take over
1878 * vgacon correctly. fbcon_startup will call fb_set_par for us, WITHOUT check_var, 1878 * vgacon correctly. fbcon_startup will call fb_set_par for us, WITHOUT check_var,
1879 * and unfortunately it will do it BEFORE vgacon contents is saved, so it won't work 1879 * and unfortunately it will do it BEFORE vgacon contents is saved, so it won't work
1880 * anyway. But we at least tried... */ 1880 * anyway. But we at least tried... */
1881 ACCESS_FBINFO(fbcon.var) = vesafb_defined; 1881 minfo->fbcon.var = vesafb_defined;
1882 err = -EINVAL; 1882 err = -EINVAL;
1883 1883
1884 printk(KERN_INFO "matroxfb: %dx%dx%dbpp (virtual: %dx%d)\n", 1884 printk(KERN_INFO "matroxfb: %dx%dx%dbpp (virtual: %dx%d)\n",
1885 vesafb_defined.xres, vesafb_defined.yres, vesafb_defined.bits_per_pixel, 1885 vesafb_defined.xres, vesafb_defined.yres, vesafb_defined.bits_per_pixel,
1886 vesafb_defined.xres_virtual, vesafb_defined.yres_virtual); 1886 vesafb_defined.xres_virtual, vesafb_defined.yres_virtual);
1887 printk(KERN_INFO "matroxfb: framebuffer at 0x%lX, mapped to 0x%p, size %d\n", 1887 printk(KERN_INFO "matroxfb: framebuffer at 0x%lX, mapped to 0x%p, size %d\n",
1888 ACCESS_FBINFO(video.base), vaddr_va(ACCESS_FBINFO(video.vbase)), ACCESS_FBINFO(video.len)); 1888 minfo->video.base, vaddr_va(minfo->video.vbase), minfo->video.len);
1889 1889
1890/* We do not have to set currcon to 0... register_framebuffer do it for us on first console 1890/* We do not have to set currcon to 0... register_framebuffer do it for us on first console
1891 * and we do not want currcon == 0 for subsequent framebuffers */ 1891 * and we do not want currcon == 0 for subsequent framebuffers */
1892 1892
1893 ACCESS_FBINFO(fbcon).device = &ACCESS_FBINFO(pcidev)->dev; 1893 minfo->fbcon.device = &minfo->pcidev->dev;
1894 if (register_framebuffer(&ACCESS_FBINFO(fbcon)) < 0) { 1894 if (register_framebuffer(&minfo->fbcon) < 0) {
1895 goto failVideoIO; 1895 goto failVideoIO;
1896 } 1896 }
1897 printk("fb%d: %s frame buffer device\n", 1897 printk("fb%d: %s frame buffer device\n",
1898 ACCESS_FBINFO(fbcon.node), ACCESS_FBINFO(fbcon.fix.id)); 1898 minfo->fbcon.node, minfo->fbcon.fix.id);
1899 1899
1900 /* there is no console on this fb... but we have to initialize hardware 1900 /* there is no console on this fb... but we have to initialize hardware
1901 * until someone tells me what is proper thing to do */ 1901 * until someone tells me what is proper thing to do */
1902 if (!ACCESS_FBINFO(initialized)) { 1902 if (!minfo->initialized) {
1903 printk(KERN_INFO "fb%d: initializing hardware\n", 1903 printk(KERN_INFO "fb%d: initializing hardware\n",
1904 ACCESS_FBINFO(fbcon.node)); 1904 minfo->fbcon.node);
1905 /* We have to use FB_ACTIVATE_FORCE, as we had to put vesafb_defined to the fbcon.var 1905 /* We have to use FB_ACTIVATE_FORCE, as we had to put vesafb_defined to the fbcon.var
1906 * already before, so register_framebuffer works correctly. */ 1906 * already before, so register_framebuffer works correctly. */
1907 vesafb_defined.activate |= FB_ACTIVATE_FORCE; 1907 vesafb_defined.activate |= FB_ACTIVATE_FORCE;
1908 fb_set_var(&ACCESS_FBINFO(fbcon), &vesafb_defined); 1908 fb_set_var(&minfo->fbcon, &vesafb_defined);
1909 } 1909 }
1910 1910
1911 return 0; 1911 return 0;
1912failVideoIO:; 1912failVideoIO:;
1913 matroxfb_g450_shutdown(PMINFO2); 1913 matroxfb_g450_shutdown(PMINFO2);
1914 mga_iounmap(ACCESS_FBINFO(video.vbase)); 1914 mga_iounmap(minfo->video.vbase);
1915failCtrlIO:; 1915failCtrlIO:;
1916 mga_iounmap(ACCESS_FBINFO(mmio.vbase)); 1916 mga_iounmap(minfo->mmio.vbase);
1917failVideoMR:; 1917failVideoMR:;
1918 release_mem_region(video_base_phys, ACCESS_FBINFO(video.len_maximum)); 1918 release_mem_region(video_base_phys, minfo->video.len_maximum);
1919failCtrlMR:; 1919failCtrlMR:;
1920 release_mem_region(ctrlptr_phys, 16384); 1920 release_mem_region(ctrlptr_phys, 16384);
1921fail:; 1921fail:;
@@ -1971,7 +1971,7 @@ void matroxfb_unregister_driver(struct matroxfb_driver* drv) {
1971static void matroxfb_register_device(struct matrox_fb_info* minfo) { 1971static void matroxfb_register_device(struct matrox_fb_info* minfo) {
1972 struct matroxfb_driver* drv; 1972 struct matroxfb_driver* drv;
1973 int i = 0; 1973 int i = 0;
1974 list_add(&ACCESS_FBINFO(next_fb), &matroxfb_list); 1974 list_add(&minfo->next_fb, &matroxfb_list);
1975 for (drv = matroxfb_driver_l(matroxfb_driver_list.next); 1975 for (drv = matroxfb_driver_l(matroxfb_driver_list.next);
1976 drv != matroxfb_driver_l(&matroxfb_driver_list); 1976 drv != matroxfb_driver_l(&matroxfb_driver_list);
1977 drv = matroxfb_driver_l(drv->node.next)) { 1977 drv = matroxfb_driver_l(drv->node.next)) {
@@ -1991,7 +1991,7 @@ static void matroxfb_register_device(struct matrox_fb_info* minfo) {
1991static void matroxfb_unregister_device(struct matrox_fb_info* minfo) { 1991static void matroxfb_unregister_device(struct matrox_fb_info* minfo) {
1992 int i; 1992 int i;
1993 1993
1994 list_del(&ACCESS_FBINFO(next_fb)); 1994 list_del(&minfo->next_fb);
1995 for (i = 0; i < minfo->drivers_count; i++) { 1995 for (i = 0; i < minfo->drivers_count; i++) {
1996 struct matroxfb_driver* drv = minfo->drivers[i]; 1996 struct matroxfb_driver* drv = minfo->drivers[i];
1997 1997
@@ -2033,51 +2033,51 @@ static int matroxfb_probe(struct pci_dev* pdev, const struct pci_device_id* dumm
2033 minfo = kmalloc(sizeof(*minfo), GFP_KERNEL); 2033 minfo = kmalloc(sizeof(*minfo), GFP_KERNEL);
2034 if (!minfo) 2034 if (!minfo)
2035 return -1; 2035 return -1;
2036 memset(MINFO, 0, sizeof(*MINFO)); 2036 memset(minfo, 0, sizeof(*minfo));
2037 2037
2038 ACCESS_FBINFO(pcidev) = pdev; 2038 minfo->pcidev = pdev;
2039 ACCESS_FBINFO(dead) = 0; 2039 minfo->dead = 0;
2040 ACCESS_FBINFO(usecount) = 0; 2040 minfo->usecount = 0;
2041 ACCESS_FBINFO(userusecount) = 0; 2041 minfo->userusecount = 0;
2042 2042
2043 pci_set_drvdata(pdev, MINFO); 2043 pci_set_drvdata(pdev, minfo);
2044 /* DEVFLAGS */ 2044 /* DEVFLAGS */
2045 ACCESS_FBINFO(devflags.memtype) = memtype; 2045 minfo->devflags.memtype = memtype;
2046 if (memtype != -1) 2046 if (memtype != -1)
2047 noinit = 0; 2047 noinit = 0;
2048 if (cmd & PCI_COMMAND_MEMORY) { 2048 if (cmd & PCI_COMMAND_MEMORY) {
2049 ACCESS_FBINFO(devflags.novga) = novga; 2049 minfo->devflags.novga = novga;
2050 ACCESS_FBINFO(devflags.nobios) = nobios; 2050 minfo->devflags.nobios = nobios;
2051 ACCESS_FBINFO(devflags.noinit) = noinit; 2051 minfo->devflags.noinit = noinit;
2052 /* subsequent heads always needs initialization and must not enable BIOS */ 2052 /* subsequent heads always needs initialization and must not enable BIOS */
2053 novga = 1; 2053 novga = 1;
2054 nobios = 1; 2054 nobios = 1;
2055 noinit = 0; 2055 noinit = 0;
2056 } else { 2056 } else {
2057 ACCESS_FBINFO(devflags.novga) = 1; 2057 minfo->devflags.novga = 1;
2058 ACCESS_FBINFO(devflags.nobios) = 1; 2058 minfo->devflags.nobios = 1;
2059 ACCESS_FBINFO(devflags.noinit) = 0; 2059 minfo->devflags.noinit = 0;
2060 } 2060 }
2061 2061
2062 ACCESS_FBINFO(devflags.nopciretry) = no_pci_retry; 2062 minfo->devflags.nopciretry = no_pci_retry;
2063 ACCESS_FBINFO(devflags.mga_24bpp_fix) = inv24; 2063 minfo->devflags.mga_24bpp_fix = inv24;
2064 ACCESS_FBINFO(devflags.precise_width) = option_precise_width; 2064 minfo->devflags.precise_width = option_precise_width;
2065 ACCESS_FBINFO(devflags.sgram) = sgram; 2065 minfo->devflags.sgram = sgram;
2066 ACCESS_FBINFO(capable.cross4MB) = cross4MB; 2066 minfo->capable.cross4MB = cross4MB;
2067 2067
2068 spin_lock_init(&ACCESS_FBINFO(lock.DAC)); 2068 spin_lock_init(&minfo->lock.DAC);
2069 spin_lock_init(&ACCESS_FBINFO(lock.accel)); 2069 spin_lock_init(&minfo->lock.accel);
2070 init_rwsem(&ACCESS_FBINFO(crtc2.lock)); 2070 init_rwsem(&minfo->crtc2.lock);
2071 init_rwsem(&ACCESS_FBINFO(altout.lock)); 2071 init_rwsem(&minfo->altout.lock);
2072 mutex_init(&ACCESS_FBINFO(fbcon).mm_lock); 2072 mutex_init(&minfo->fbcon.mm_lock);
2073 ACCESS_FBINFO(irq_flags) = 0; 2073 minfo->irq_flags = 0;
2074 init_waitqueue_head(&ACCESS_FBINFO(crtc1.vsync.wait)); 2074 init_waitqueue_head(&minfo->crtc1.vsync.wait);
2075 init_waitqueue_head(&ACCESS_FBINFO(crtc2.vsync.wait)); 2075 init_waitqueue_head(&minfo->crtc2.vsync.wait);
2076 ACCESS_FBINFO(crtc1.panpos) = -1; 2076 minfo->crtc1.panpos = -1;
2077 2077
2078 err = initMatrox2(PMINFO b); 2078 err = initMatrox2(PMINFO b);
2079 if (!err) { 2079 if (!err) {
2080 matroxfb_register_device(MINFO); 2080 matroxfb_register_device(minfo);
2081 return 0; 2081 return 0;
2082 } 2082 }
2083 kfree(minfo); 2083 kfree(minfo);
diff --git a/drivers/video/matrox/matroxfb_base.h b/drivers/video/matrox/matroxfb_base.h
index ba64f5e33467..bbd7c04b0b1f 100644
--- a/drivers/video/matrox/matroxfb_base.h
+++ b/drivers/video/matrox/matroxfb_base.h
@@ -524,11 +524,6 @@ struct matrox_fb_info {
524 524
525#define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon) 525#define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
526 526
527#define ACCESS_FBINFO2(info, x) (info->x)
528#define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
529
530#define MINFO minfo
531
532#define WPMINFO2 struct matrox_fb_info* minfo 527#define WPMINFO2 struct matrox_fb_info* minfo
533#define WPMINFO WPMINFO2 , 528#define WPMINFO WPMINFO2 ,
534#define CPMINFO2 const struct matrox_fb_info* minfo 529#define CPMINFO2 const struct matrox_fb_info* minfo
@@ -707,11 +702,11 @@ void matroxfb_unregister_driver(struct matroxfb_driver* drv);
707#endif 702#endif
708#endif 703#endif
709 704
710#define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr)) 705#define mga_inb(addr) mga_readb(minfo->mmio.vbase, (addr))
711#define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr)) 706#define mga_inl(addr) mga_readl(minfo->mmio.vbase, (addr))
712#define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val)) 707#define mga_outb(addr,val) mga_writeb(minfo->mmio.vbase, (addr), (val))
713#define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val)) 708#define mga_outw(addr,val) mga_writew(minfo->mmio.vbase, (addr), (val))
714#define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val)) 709#define mga_outl(addr,val) mga_writel(minfo->mmio.vbase, (addr), (val))
715#define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1)) 710#define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
716#define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port)) 711#define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
717 712
@@ -730,10 +725,10 @@ void matroxfb_unregister_driver(struct matroxfb_driver* drv);
730#define isMilleniumII(x) (0) 725#define isMilleniumII(x) (0)
731#endif 726#endif
732 727
733#define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC)) 728#define matroxfb_DAC_lock() spin_lock(&minfo->lock.DAC)
734#define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC)) 729#define matroxfb_DAC_unlock() spin_unlock(&minfo->lock.DAC)
735#define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags) 730#define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&minfo->lock.DAC, flags)
736#define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags) 731#define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&minfo->lock.DAC, flags)
737extern void matroxfb_DAC_out(CPMINFO int reg, int val); 732extern void matroxfb_DAC_out(CPMINFO int reg, int val);
738extern int matroxfb_DAC_in(CPMINFO int reg); 733extern int matroxfb_DAC_in(CPMINFO int reg);
739extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt); 734extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
@@ -741,8 +736,8 @@ extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc);
741extern int matroxfb_enable_irq(WPMINFO int reenable); 736extern int matroxfb_enable_irq(WPMINFO int reenable);
742 737
743#ifdef MATROXFB_USE_SPINLOCKS 738#ifdef MATROXFB_USE_SPINLOCKS
744#define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags); 739#define CRITBEGIN spin_lock_irqsave(&minfo->lock.accel, critflags);
745#define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags); 740#define CRITEND spin_unlock_irqrestore(&minfo->lock.accel, critflags);
746#define CRITFLAGS unsigned long critflags; 741#define CRITFLAGS unsigned long critflags;
747#else 742#else
748#define CRITBEGIN 743#define CRITBEGIN
diff --git a/drivers/video/matrox/matroxfb_crtc2.c b/drivers/video/matrox/matroxfb_crtc2.c
index ebcb5c6b4962..8249959cde2e 100644
--- a/drivers/video/matrox/matroxfb_crtc2.c
+++ b/drivers/video/matrox/matroxfb_crtc2.c
@@ -81,11 +81,11 @@ static void matroxfb_dh_restore(struct matroxfb_dh_fb_info* m2info,
81 } 81 }
82 tmp |= 0x00000001; /* enable CRTC2 */ 82 tmp |= 0x00000001; /* enable CRTC2 */
83 datactl = 0; 83 datactl = 0;
84 if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC2) { 84 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) {
85 if (ACCESS_FBINFO(devflags.g450dac)) { 85 if (minfo->devflags.g450dac) {
86 tmp |= 0x00000006; /* source from secondary pixel PLL */ 86 tmp |= 0x00000006; /* source from secondary pixel PLL */
87 /* no vidrst when in monitor mode */ 87 /* no vidrst when in monitor mode */
88 if (ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) { 88 if (minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
89 tmp |= 0xC0001000; /* Enable H/V vidrst */ 89 tmp |= 0xC0001000; /* Enable H/V vidrst */
90 } 90 }
91 } else { 91 } else {
@@ -93,11 +93,11 @@ static void matroxfb_dh_restore(struct matroxfb_dh_fb_info* m2info,
93 tmp |= 0xC0000000; /* enable vvidrst & hvidrst */ 93 tmp |= 0xC0000000; /* enable vvidrst & hvidrst */
94 /* MGA TVO is our clock source */ 94 /* MGA TVO is our clock source */
95 } 95 }
96 } else if (ACCESS_FBINFO(outputs[0]).src == MATROXFB_SRC_CRTC2) { 96 } else if (minfo->outputs[0].src == MATROXFB_SRC_CRTC2) {
97 tmp |= 0x00000004; /* source from pixclock */ 97 tmp |= 0x00000004; /* source from pixclock */
98 /* PIXPLL is our clock source */ 98 /* PIXPLL is our clock source */
99 } 99 }
100 if (ACCESS_FBINFO(outputs[0]).src == MATROXFB_SRC_CRTC2) { 100 if (minfo->outputs[0].src == MATROXFB_SRC_CRTC2) {
101 tmp |= 0x00100000; /* connect CRTC2 to DAC */ 101 tmp |= 0x00100000; /* connect CRTC2 to DAC */
102 } 102 }
103 if (mt->interlaced) { 103 if (mt->interlaced) {
@@ -146,7 +146,7 @@ static void matroxfb_dh_restore(struct matroxfb_dh_fb_info* m2info,
146 } 146 }
147 } 147 }
148 mga_outl(0x3C10, tmp); 148 mga_outl(0x3C10, tmp);
149 ACCESS_FBINFO(hw).crtc2.ctl = tmp; 149 minfo->hw.crtc2.ctl = tmp;
150 150
151 tmp = mt->VDisplay << 16; /* line compare */ 151 tmp = mt->VDisplay << 16; /* line compare */
152 if (mt->sync & FB_SYNC_HOR_HIGH_ACT) 152 if (mt->sync & FB_SYNC_HOR_HIGH_ACT)
@@ -160,7 +160,7 @@ static void matroxfb_dh_disable(struct matroxfb_dh_fb_info* m2info) {
160 MINFO_FROM(m2info->primary_dev); 160 MINFO_FROM(m2info->primary_dev);
161 161
162 mga_outl(0x3C10, 0x00000004); /* disable CRTC2, CRTC1->DAC1, PLL as clock source */ 162 mga_outl(0x3C10, 0x00000004); /* disable CRTC2, CRTC1->DAC1, PLL as clock source */
163 ACCESS_FBINFO(hw).crtc2.ctl = 0x00000004; 163 minfo->hw.crtc2.ctl = 0x00000004;
164} 164}
165 165
166static void matroxfb_dh_pan_var(struct matroxfb_dh_fb_info* m2info, 166static void matroxfb_dh_pan_var(struct matroxfb_dh_fb_info* m2info,
@@ -262,13 +262,13 @@ static int matroxfb_dh_open(struct fb_info* info, int user) {
262#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon)) 262#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
263 MINFO_FROM(m2info->primary_dev); 263 MINFO_FROM(m2info->primary_dev);
264 264
265 if (MINFO) { 265 if (minfo) {
266 int err; 266 int err;
267 267
268 if (ACCESS_FBINFO(dead)) { 268 if (minfo->dead) {
269 return -ENXIO; 269 return -ENXIO;
270 } 270 }
271 err = ACCESS_FBINFO(fbops).fb_open(&ACCESS_FBINFO(fbcon), user); 271 err = minfo->fbops.fb_open(&minfo->fbcon, user);
272 if (err) { 272 if (err) {
273 return err; 273 return err;
274 } 274 }
@@ -282,8 +282,8 @@ static int matroxfb_dh_release(struct fb_info* info, int user) {
282 int err = 0; 282 int err = 0;
283 MINFO_FROM(m2info->primary_dev); 283 MINFO_FROM(m2info->primary_dev);
284 284
285 if (MINFO) { 285 if (minfo) {
286 err = ACCESS_FBINFO(fbops).fb_release(&ACCESS_FBINFO(fbcon), user); 286 err = minfo->fbops.fb_release(&minfo->fbcon, user);
287 } 287 }
288 return err; 288 return err;
289#undef m2info 289#undef m2info
@@ -352,18 +352,18 @@ static int matroxfb_dh_set_par(struct fb_info* info) {
352 pos = (m2info->fbcon.var.yoffset * m2info->fbcon.var.xres_virtual + m2info->fbcon.var.xoffset) * m2info->fbcon.var.bits_per_pixel >> 3; 352 pos = (m2info->fbcon.var.yoffset * m2info->fbcon.var.xres_virtual + m2info->fbcon.var.xoffset) * m2info->fbcon.var.bits_per_pixel >> 3;
353 pos += m2info->video.offbase; 353 pos += m2info->video.offbase;
354 cnt = 0; 354 cnt = 0;
355 down_read(&ACCESS_FBINFO(altout).lock); 355 down_read(&minfo->altout.lock);
356 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) { 356 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
357 if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC2) { 357 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2) {
358 cnt++; 358 cnt++;
359 if (ACCESS_FBINFO(outputs[out]).output->compute) { 359 if (minfo->outputs[out].output->compute) {
360 ACCESS_FBINFO(outputs[out]).output->compute(ACCESS_FBINFO(outputs[out]).data, &mt); 360 minfo->outputs[out].output->compute(minfo->outputs[out].data, &mt);
361 } 361 }
362 } 362 }
363 } 363 }
364 ACCESS_FBINFO(crtc2).pixclock = mt.pixclock; 364 minfo->crtc2.pixclock = mt.pixclock;
365 ACCESS_FBINFO(crtc2).mnp = mt.mnp; 365 minfo->crtc2.mnp = mt.mnp;
366 up_read(&ACCESS_FBINFO(altout).lock); 366 up_read(&minfo->altout.lock);
367 if (cnt) { 367 if (cnt) {
368 matroxfb_dh_restore(m2info, &mt, mode, pos); 368 matroxfb_dh_restore(m2info, &mt, mode, pos);
369 } else { 369 } else {
@@ -371,20 +371,20 @@ static int matroxfb_dh_set_par(struct fb_info* info) {
371 } 371 }
372 DAC1064_global_init(PMINFO2); 372 DAC1064_global_init(PMINFO2);
373 DAC1064_global_restore(PMINFO2); 373 DAC1064_global_restore(PMINFO2);
374 down_read(&ACCESS_FBINFO(altout).lock); 374 down_read(&minfo->altout.lock);
375 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) { 375 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
376 if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC2 && 376 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2 &&
377 ACCESS_FBINFO(outputs[out]).output->program) { 377 minfo->outputs[out].output->program) {
378 ACCESS_FBINFO(outputs[out]).output->program(ACCESS_FBINFO(outputs[out]).data); 378 minfo->outputs[out].output->program(minfo->outputs[out].data);
379 } 379 }
380 } 380 }
381 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) { 381 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
382 if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC2 && 382 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2 &&
383 ACCESS_FBINFO(outputs[out]).output->start) { 383 minfo->outputs[out].output->start) {
384 ACCESS_FBINFO(outputs[out]).output->start(ACCESS_FBINFO(outputs[out]).data); 384 minfo->outputs[out].output->start(minfo->outputs[out].data);
385 } 385 }
386 } 386 }
387 up_read(&ACCESS_FBINFO(altout).lock); 387 up_read(&minfo->altout.lock);
388 } 388 }
389 m2info->initialized = 1; 389 m2info->initialized = 1;
390 return 0; 390 return 0;
@@ -409,11 +409,11 @@ static int matroxfb_dh_get_vblank(const struct matroxfb_dh_fb_info* m2info, stru
409 /* compatibility stuff */ 409 /* compatibility stuff */
410 if (vblank->vcount >= m2info->fbcon.var.yres) 410 if (vblank->vcount >= m2info->fbcon.var.yres)
411 vblank->flags |= FB_VBLANK_VBLANKING; 411 vblank->flags |= FB_VBLANK_VBLANKING;
412 if (test_bit(0, &ACCESS_FBINFO(irq_flags))) { 412 if (test_bit(0, &minfo->irq_flags)) {
413 vblank->flags |= FB_VBLANK_HAVE_COUNT; 413 vblank->flags |= FB_VBLANK_HAVE_COUNT;
414 /* Only one writer, aligned int value... 414 /* Only one writer, aligned int value...
415 it should work without lock and without atomic_t */ 415 it should work without lock and without atomic_t */
416 vblank->count = ACCESS_FBINFO(crtc2).vsync.cnt; 416 vblank->count = minfo->crtc2.vsync.cnt;
417 } 417 }
418 return 0; 418 return 0;
419} 419}
@@ -455,7 +455,7 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
455 case MATROXFB_GET_OUTPUT_MODE: 455 case MATROXFB_GET_OUTPUT_MODE:
456 case MATROXFB_GET_ALL_OUTPUTS: 456 case MATROXFB_GET_ALL_OUTPUTS:
457 { 457 {
458 return ACCESS_FBINFO(fbcon.fbops)->fb_ioctl(&ACCESS_FBINFO(fbcon), cmd, arg); 458 return minfo->fbcon.fbops->fb_ioctl(&minfo->fbcon, cmd, arg);
459 } 459 }
460 case MATROXFB_SET_OUTPUT_CONNECTION: 460 case MATROXFB_SET_OUTPUT_CONNECTION:
461 { 461 {
@@ -469,9 +469,9 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
469 if (tmp & (1 << out)) { 469 if (tmp & (1 << out)) {
470 if (out >= MATROXFB_MAX_OUTPUTS) 470 if (out >= MATROXFB_MAX_OUTPUTS)
471 return -ENXIO; 471 return -ENXIO;
472 if (!ACCESS_FBINFO(outputs[out]).output) 472 if (!minfo->outputs[out].output)
473 return -ENXIO; 473 return -ENXIO;
474 switch (ACCESS_FBINFO(outputs[out]).src) { 474 switch (minfo->outputs[out].src) {
475 case MATROXFB_SRC_NONE: 475 case MATROXFB_SRC_NONE:
476 case MATROXFB_SRC_CRTC2: 476 case MATROXFB_SRC_CRTC2:
477 break; 477 break;
@@ -480,22 +480,22 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
480 } 480 }
481 } 481 }
482 } 482 }
483 if (ACCESS_FBINFO(devflags.panellink)) { 483 if (minfo->devflags.panellink) {
484 if (tmp & MATROXFB_OUTPUT_CONN_DFP) 484 if (tmp & MATROXFB_OUTPUT_CONN_DFP)
485 return -EINVAL; 485 return -EINVAL;
486 if ((ACCESS_FBINFO(outputs[2]).src == MATROXFB_SRC_CRTC1) && tmp) 486 if ((minfo->outputs[2].src == MATROXFB_SRC_CRTC1) && tmp)
487 return -EBUSY; 487 return -EBUSY;
488 } 488 }
489 changes = 0; 489 changes = 0;
490 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) { 490 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
491 if (tmp & (1 << out)) { 491 if (tmp & (1 << out)) {
492 if (ACCESS_FBINFO(outputs[out]).src != MATROXFB_SRC_CRTC2) { 492 if (minfo->outputs[out].src != MATROXFB_SRC_CRTC2) {
493 changes = 1; 493 changes = 1;
494 ACCESS_FBINFO(outputs[out]).src = MATROXFB_SRC_CRTC2; 494 minfo->outputs[out].src = MATROXFB_SRC_CRTC2;
495 } 495 }
496 } else if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC2) { 496 } else if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2) {
497 changes = 1; 497 changes = 1;
498 ACCESS_FBINFO(outputs[out]).src = MATROXFB_SRC_NONE; 498 minfo->outputs[out].src = MATROXFB_SRC_NONE;
499 } 499 }
500 } 500 }
501 if (!changes) 501 if (!changes)
@@ -509,7 +509,7 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
509 int out; 509 int out;
510 510
511 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) { 511 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
512 if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC2) { 512 if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2) {
513 conn |= 1 << out; 513 conn |= 1 << out;
514 } 514 }
515 } 515 }
@@ -523,8 +523,8 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
523 int out; 523 int out;
524 524
525 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) { 525 for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
526 if (ACCESS_FBINFO(outputs[out]).output) { 526 if (minfo->outputs[out].output) {
527 switch (ACCESS_FBINFO(outputs[out]).src) { 527 switch (minfo->outputs[out].src) {
528 case MATROXFB_SRC_NONE: 528 case MATROXFB_SRC_NONE:
529 case MATROXFB_SRC_CRTC2: 529 case MATROXFB_SRC_CRTC2:
530 tmp |= 1 << out; 530 tmp |= 1 << out;
@@ -532,9 +532,9 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
532 } 532 }
533 } 533 }
534 } 534 }
535 if (ACCESS_FBINFO(devflags.panellink)) { 535 if (minfo->devflags.panellink) {
536 tmp &= ~MATROXFB_OUTPUT_CONN_DFP; 536 tmp &= ~MATROXFB_OUTPUT_CONN_DFP;
537 if (ACCESS_FBINFO(outputs[2]).src == MATROXFB_SRC_CRTC1) { 537 if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1) {
538 tmp = 0; 538 tmp = 0;
539 } 539 }
540 } 540 }
@@ -611,21 +611,21 @@ static int matroxfb_dh_regit(CPMINFO struct matroxfb_dh_fb_info* m2info) {
611 if (mem < 64*1024) 611 if (mem < 64*1024)
612 mem *= 1024; 612 mem *= 1024;
613 mem &= ~0x00000FFF; /* PAGE_MASK? */ 613 mem &= ~0x00000FFF; /* PAGE_MASK? */
614 if (ACCESS_FBINFO(video.len_usable) + mem <= ACCESS_FBINFO(video.len)) 614 if (minfo->video.len_usable + mem <= minfo->video.len)
615 m2info->video.offbase = ACCESS_FBINFO(video.len) - mem; 615 m2info->video.offbase = minfo->video.len - mem;
616 else if (ACCESS_FBINFO(video.len) < mem) { 616 else if (minfo->video.len < mem) {
617 return -ENOMEM; 617 return -ENOMEM;
618 } else { /* check yres on first head... */ 618 } else { /* check yres on first head... */
619 m2info->video.borrowed = mem; 619 m2info->video.borrowed = mem;
620 ACCESS_FBINFO(video.len_usable) -= mem; 620 minfo->video.len_usable -= mem;
621 m2info->video.offbase = ACCESS_FBINFO(video.len_usable); 621 m2info->video.offbase = minfo->video.len_usable;
622 } 622 }
623 m2info->video.base = ACCESS_FBINFO(video.base) + m2info->video.offbase; 623 m2info->video.base = minfo->video.base + m2info->video.offbase;
624 m2info->video.len = m2info->video.len_usable = m2info->video.len_maximum = mem; 624 m2info->video.len = m2info->video.len_usable = m2info->video.len_maximum = mem;
625 m2info->video.vbase.vaddr = vaddr_va(ACCESS_FBINFO(video.vbase)) + m2info->video.offbase; 625 m2info->video.vbase.vaddr = vaddr_va(minfo->video.vbase) + m2info->video.offbase;
626 m2info->mmio.base = ACCESS_FBINFO(mmio.base); 626 m2info->mmio.base = minfo->mmio.base;
627 m2info->mmio.vbase = ACCESS_FBINFO(mmio.vbase); 627 m2info->mmio.vbase = minfo->mmio.vbase;
628 m2info->mmio.len = ACCESS_FBINFO(mmio.len); 628 m2info->mmio.len = minfo->mmio.len;
629 629
630 matroxfb_dh_init_fix(m2info); 630 matroxfb_dh_init_fix(m2info);
631 if (register_framebuffer(&m2info->fbcon)) { 631 if (register_framebuffer(&m2info->fbcon)) {
@@ -633,10 +633,10 @@ static int matroxfb_dh_regit(CPMINFO struct matroxfb_dh_fb_info* m2info) {
633 } 633 }
634 if (!m2info->initialized) 634 if (!m2info->initialized)
635 fb_set_var(&m2info->fbcon, &matroxfb_dh_defined); 635 fb_set_var(&m2info->fbcon, &matroxfb_dh_defined);
636 down_write(&ACCESS_FBINFO(crtc2.lock)); 636 down_write(&minfo->crtc2.lock);
637 oldcrtc2 = ACCESS_FBINFO(crtc2.info); 637 oldcrtc2 = minfo->crtc2.info;
638 ACCESS_FBINFO(crtc2.info) = m2info; 638 minfo->crtc2.info = m2info;
639 up_write(&ACCESS_FBINFO(crtc2.lock)); 639 up_write(&minfo->crtc2.lock);
640 if (oldcrtc2) { 640 if (oldcrtc2) {
641 printk(KERN_ERR "matroxfb_crtc2: Internal consistency check failed: crtc2 already present: %p\n", 641 printk(KERN_ERR "matroxfb_crtc2: Internal consistency check failed: crtc2 already present: %p\n",
642 oldcrtc2); 642 oldcrtc2);
@@ -654,7 +654,7 @@ static int matroxfb_dh_registerfb(struct matroxfb_dh_fb_info* m2info) {
654 return -1; 654 return -1;
655 } 655 }
656 printk(KERN_INFO "matroxfb_crtc2: secondary head of fb%u was registered as fb%u\n", 656 printk(KERN_INFO "matroxfb_crtc2: secondary head of fb%u was registered as fb%u\n",
657 ACCESS_FBINFO(fbcon.node), m2info->fbcon.node); 657 minfo->fbcon.node, m2info->fbcon.node);
658 m2info->fbcon_registered = 1; 658 m2info->fbcon_registered = 1;
659 return 0; 659 return 0;
660#undef minfo 660#undef minfo
@@ -666,11 +666,11 @@ static void matroxfb_dh_deregisterfb(struct matroxfb_dh_fb_info* m2info) {
666 int id; 666 int id;
667 struct matroxfb_dh_fb_info* crtc2; 667 struct matroxfb_dh_fb_info* crtc2;
668 668
669 down_write(&ACCESS_FBINFO(crtc2.lock)); 669 down_write(&minfo->crtc2.lock);
670 crtc2 = ACCESS_FBINFO(crtc2.info); 670 crtc2 = minfo->crtc2.info;
671 if (crtc2 == m2info) 671 if (crtc2 == m2info)
672 ACCESS_FBINFO(crtc2.info) = NULL; 672 minfo->crtc2.info = NULL;
673 up_write(&ACCESS_FBINFO(crtc2.lock)); 673 up_write(&minfo->crtc2.lock);
674 if (crtc2 != m2info) { 674 if (crtc2 != m2info) {
675 printk(KERN_ERR "matroxfb_crtc2: Internal consistency check failed: crtc2 mismatch at unload: %p != %p\n", 675 printk(KERN_ERR "matroxfb_crtc2: Internal consistency check failed: crtc2 mismatch at unload: %p != %p\n",
676 crtc2, m2info); 676 crtc2, m2info);
@@ -680,7 +680,7 @@ static void matroxfb_dh_deregisterfb(struct matroxfb_dh_fb_info* m2info) {
680 id = m2info->fbcon.node; 680 id = m2info->fbcon.node;
681 unregister_framebuffer(&m2info->fbcon); 681 unregister_framebuffer(&m2info->fbcon);
682 /* return memory back to primary head */ 682 /* return memory back to primary head */
683 ACCESS_FBINFO(video.len_usable) += m2info->video.borrowed; 683 minfo->video.len_usable += m2info->video.borrowed;
684 printk(KERN_INFO "matroxfb_crtc2: fb%u unregistered\n", id); 684 printk(KERN_INFO "matroxfb_crtc2: fb%u unregistered\n", id);
685 m2info->fbcon_registered = 0; 685 m2info->fbcon_registered = 0;
686 } 686 }
@@ -691,14 +691,14 @@ static void* matroxfb_crtc2_probe(struct matrox_fb_info* minfo) {
691 struct matroxfb_dh_fb_info* m2info; 691 struct matroxfb_dh_fb_info* m2info;
692 692
693 /* hardware is CRTC2 incapable... */ 693 /* hardware is CRTC2 incapable... */
694 if (!ACCESS_FBINFO(devflags.crtc2)) 694 if (!minfo->devflags.crtc2)
695 return NULL; 695 return NULL;
696 m2info = kzalloc(sizeof(*m2info), GFP_KERNEL); 696 m2info = kzalloc(sizeof(*m2info), GFP_KERNEL);
697 if (!m2info) { 697 if (!m2info) {
698 printk(KERN_ERR "matroxfb_crtc2: Not enough memory for CRTC2 control structs\n"); 698 printk(KERN_ERR "matroxfb_crtc2: Not enough memory for CRTC2 control structs\n");
699 return NULL; 699 return NULL;
700 } 700 }
701 m2info->primary_dev = MINFO; 701 m2info->primary_dev = minfo;
702 if (matroxfb_dh_registerfb(m2info)) { 702 if (matroxfb_dh_registerfb(m2info)) {
703 kfree(m2info); 703 kfree(m2info);
704 printk(KERN_ERR "matroxfb_crtc2: CRTC2 framebuffer failed to register\n"); 704 printk(KERN_ERR "matroxfb_crtc2: CRTC2 framebuffer failed to register\n");
diff --git a/drivers/video/matrox/matroxfb_g450.c b/drivers/video/matrox/matroxfb_g450.c
index 6209a761f674..841b439ecca3 100644
--- a/drivers/video/matrox/matroxfb_g450.c
+++ b/drivers/video/matrox/matroxfb_g450.c
@@ -81,7 +81,7 @@ static int get_ctrl_id(__u32 v4l2_id) {
81} 81}
82 82
83static inline int* get_ctrl_ptr(WPMINFO unsigned int idx) { 83static inline int* get_ctrl_ptr(WPMINFO unsigned int idx) {
84 return (int*)((char*)MINFO + g450_controls[idx].control); 84 return (int*)((char*)minfo + g450_controls[idx].control);
85} 85}
86 86
87static void tvo_fill_defaults(WPMINFO2) { 87static void tvo_fill_defaults(WPMINFO2) {
@@ -124,8 +124,8 @@ static void cve2_set_reg10(WPMINFO int reg, int val) {
124} 124}
125 125
126static void g450_compute_bwlevel(CPMINFO int *bl, int *wl) { 126static void g450_compute_bwlevel(CPMINFO int *bl, int *wl) {
127 const int b = ACCESS_FBINFO(altout.tvo_params.brightness) + BLMIN; 127 const int b = minfo->altout.tvo_params.brightness + BLMIN;
128 const int c = ACCESS_FBINFO(altout.tvo_params.contrast); 128 const int c = minfo->altout.tvo_params.contrast;
129 129
130 *bl = max(b - c, BLMIN); 130 *bl = max(b - c, BLMIN);
131 *wl = min(b + c, WLMAX); 131 *wl = min(b + c, WLMAX);
@@ -509,31 +509,31 @@ static void cve2_init_TV(WPMINFO const struct mavenregs* m) {
509static int matroxfb_g450_compute(void* md, struct my_timming* mt) { 509static int matroxfb_g450_compute(void* md, struct my_timming* mt) {
510 MINFO_FROM(md); 510 MINFO_FROM(md);
511 511
512 dprintk(KERN_DEBUG "Computing, mode=%u\n", ACCESS_FBINFO(outputs[1]).mode); 512 dprintk(KERN_DEBUG "Computing, mode=%u\n", minfo->outputs[1].mode);
513 513
514 if (mt->crtc == MATROXFB_SRC_CRTC2 && 514 if (mt->crtc == MATROXFB_SRC_CRTC2 &&
515 ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) { 515 minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
516 const struct output_desc* outd; 516 const struct output_desc* outd;
517 517
518 cve2_init_TVdata(ACCESS_FBINFO(outputs[1]).mode, &ACCESS_FBINFO(hw).maven, &outd); 518 cve2_init_TVdata(minfo->outputs[1].mode, &minfo->hw.maven, &outd);
519 { 519 {
520 int blacklevel, whitelevel; 520 int blacklevel, whitelevel;
521 g450_compute_bwlevel(PMINFO &blacklevel, &whitelevel); 521 g450_compute_bwlevel(PMINFO &blacklevel, &whitelevel);
522 ACCESS_FBINFO(hw).maven.regs[0x0E] = blacklevel >> 2; 522 minfo->hw.maven.regs[0x0E] = blacklevel >> 2;
523 ACCESS_FBINFO(hw).maven.regs[0x0F] = blacklevel & 3; 523 minfo->hw.maven.regs[0x0F] = blacklevel & 3;
524 ACCESS_FBINFO(hw).maven.regs[0x1E] = whitelevel >> 2; 524 minfo->hw.maven.regs[0x1E] = whitelevel >> 2;
525 ACCESS_FBINFO(hw).maven.regs[0x1F] = whitelevel & 3; 525 minfo->hw.maven.regs[0x1F] = whitelevel & 3;
526 526
527 ACCESS_FBINFO(hw).maven.regs[0x20] = 527 minfo->hw.maven.regs[0x20] =
528 ACCESS_FBINFO(hw).maven.regs[0x22] = ACCESS_FBINFO(altout.tvo_params.saturation); 528 minfo->hw.maven.regs[0x22] = minfo->altout.tvo_params.saturation;
529 529
530 ACCESS_FBINFO(hw).maven.regs[0x25] = ACCESS_FBINFO(altout.tvo_params.hue); 530 minfo->hw.maven.regs[0x25] = minfo->altout.tvo_params.hue;
531 531
532 if (ACCESS_FBINFO(altout.tvo_params.testout)) { 532 if (minfo->altout.tvo_params.testout) {
533 ACCESS_FBINFO(hw).maven.regs[0x05] |= 0x02; 533 minfo->hw.maven.regs[0x05] |= 0x02;
534 } 534 }
535 } 535 }
536 computeRegs(PMINFO &ACCESS_FBINFO(hw).maven, mt, outd); 536 computeRegs(PMINFO &minfo->hw.maven, mt, outd);
537 } else if (mt->mnp < 0) { 537 } else if (mt->mnp < 0) {
538 /* We must program clocks before CRTC2, otherwise interlaced mode 538 /* We must program clocks before CRTC2, otherwise interlaced mode
539 startup may fail */ 539 startup may fail */
@@ -547,8 +547,8 @@ static int matroxfb_g450_compute(void* md, struct my_timming* mt) {
547static int matroxfb_g450_program(void* md) { 547static int matroxfb_g450_program(void* md) {
548 MINFO_FROM(md); 548 MINFO_FROM(md);
549 549
550 if (ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) { 550 if (minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
551 cve2_init_TV(PMINFO &ACCESS_FBINFO(hw).maven); 551 cve2_init_TV(PMINFO &minfo->hw.maven);
552 } 552 }
553 return 0; 553 return 0;
554} 554}
@@ -589,33 +589,33 @@ static struct matrox_altout matroxfb_g450_dvi = {
589}; 589};
590 590
591void matroxfb_g450_connect(WPMINFO2) { 591void matroxfb_g450_connect(WPMINFO2) {
592 if (ACCESS_FBINFO(devflags.g450dac)) { 592 if (minfo->devflags.g450dac) {
593 down_write(&ACCESS_FBINFO(altout.lock)); 593 down_write(&minfo->altout.lock);
594 tvo_fill_defaults(PMINFO2); 594 tvo_fill_defaults(PMINFO2);
595 ACCESS_FBINFO(outputs[1]).src = ACCESS_FBINFO(outputs[1]).default_src; 595 minfo->outputs[1].src = minfo->outputs[1].default_src;
596 ACCESS_FBINFO(outputs[1]).data = MINFO; 596 minfo->outputs[1].data = minfo;
597 ACCESS_FBINFO(outputs[1]).output = &matroxfb_g450_altout; 597 minfo->outputs[1].output = &matroxfb_g450_altout;
598 ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR; 598 minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
599 ACCESS_FBINFO(outputs[2]).src = ACCESS_FBINFO(outputs[2]).default_src; 599 minfo->outputs[2].src = minfo->outputs[2].default_src;
600 ACCESS_FBINFO(outputs[2]).data = MINFO; 600 minfo->outputs[2].data = minfo;
601 ACCESS_FBINFO(outputs[2]).output = &matroxfb_g450_dvi; 601 minfo->outputs[2].output = &matroxfb_g450_dvi;
602 ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR; 602 minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
603 up_write(&ACCESS_FBINFO(altout.lock)); 603 up_write(&minfo->altout.lock);
604 } 604 }
605} 605}
606 606
607void matroxfb_g450_shutdown(WPMINFO2) { 607void matroxfb_g450_shutdown(WPMINFO2) {
608 if (ACCESS_FBINFO(devflags.g450dac)) { 608 if (minfo->devflags.g450dac) {
609 down_write(&ACCESS_FBINFO(altout.lock)); 609 down_write(&minfo->altout.lock);
610 ACCESS_FBINFO(outputs[1]).src = MATROXFB_SRC_NONE; 610 minfo->outputs[1].src = MATROXFB_SRC_NONE;
611 ACCESS_FBINFO(outputs[1]).output = NULL; 611 minfo->outputs[1].output = NULL;
612 ACCESS_FBINFO(outputs[1]).data = NULL; 612 minfo->outputs[1].data = NULL;
613 ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR; 613 minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
614 ACCESS_FBINFO(outputs[2]).src = MATROXFB_SRC_NONE; 614 minfo->outputs[2].src = MATROXFB_SRC_NONE;
615 ACCESS_FBINFO(outputs[2]).output = NULL; 615 minfo->outputs[2].output = NULL;
616 ACCESS_FBINFO(outputs[2]).data = NULL; 616 minfo->outputs[2].data = NULL;
617 ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR; 617 minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
618 up_write(&ACCESS_FBINFO(altout.lock)); 618 up_write(&minfo->altout.lock);
619 } 619 }
620} 620}
621 621
diff --git a/drivers/video/matrox/matroxfb_maven.c b/drivers/video/matrox/matroxfb_maven.c
index 042408a8c631..4fbb386b2eff 100644
--- a/drivers/video/matrox/matroxfb_maven.c
+++ b/drivers/video/matrox/matroxfb_maven.c
@@ -460,7 +460,7 @@ static void maven_init_TVdata(const struct maven_data* md, struct mavenregs* dat
460 }, MATROXFB_OUTPUT_MODE_NTSC, 525, 60 }; 460 }, MATROXFB_OUTPUT_MODE_NTSC, 525, 60 };
461 MINFO_FROM(md->primary_head); 461 MINFO_FROM(md->primary_head);
462 462
463 if (ACCESS_FBINFO(outputs[1]).mode == MATROXFB_OUTPUT_MODE_PAL) 463 if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_PAL)
464 *data = palregs; 464 *data = palregs;
465 else 465 else
466 *data = ntscregs; 466 *data = ntscregs;
@@ -496,11 +496,11 @@ static void maven_init_TVdata(const struct maven_data* md, struct mavenregs* dat
496 /* Set saturation */ 496 /* Set saturation */
497 { 497 {
498 data->regs[0x20] = 498 data->regs[0x20] =
499 data->regs[0x22] = ACCESS_FBINFO(altout.tvo_params.saturation); 499 data->regs[0x22] = minfo->altout.tvo_params.saturation;
500 } 500 }
501 501
502 /* Set HUE */ 502 /* Set HUE */
503 data->regs[0x25] = ACCESS_FBINFO(altout.tvo_params.hue); 503 data->regs[0x25] = minfo->altout.tvo_params.hue;
504 return; 504 return;
505} 505}
506 506
@@ -743,7 +743,7 @@ static inline int maven_compute_timming(struct maven_data* md,
743 unsigned int a, bv, c; 743 unsigned int a, bv, c;
744 MINFO_FROM(md->primary_head); 744 MINFO_FROM(md->primary_head);
745 745
746 m->mode = ACCESS_FBINFO(outputs[1]).mode; 746 m->mode = minfo->outputs[1].mode;
747 if (m->mode != MATROXFB_OUTPUT_MODE_MONITOR) { 747 if (m->mode != MATROXFB_OUTPUT_MODE_MONITOR) {
748 unsigned int lmargin; 748 unsigned int lmargin;
749 unsigned int umargin; 749 unsigned int umargin;
@@ -1132,7 +1132,7 @@ static int maven_get_control (struct maven_data* md,
1132static int maven_out_compute(void* md, struct my_timming* mt) { 1132static int maven_out_compute(void* md, struct my_timming* mt) {
1133#define mdinfo ((struct maven_data*)md) 1133#define mdinfo ((struct maven_data*)md)
1134#define minfo (mdinfo->primary_head) 1134#define minfo (mdinfo->primary_head)
1135 return maven_compute_timming(md, mt, &ACCESS_FBINFO(hw).maven); 1135 return maven_compute_timming(md, mt, &minfo->hw.maven);
1136#undef minfo 1136#undef minfo
1137#undef mdinfo 1137#undef mdinfo
1138} 1138}
@@ -1140,7 +1140,7 @@ static int maven_out_compute(void* md, struct my_timming* mt) {
1140static int maven_out_program(void* md) { 1140static int maven_out_program(void* md) {
1141#define mdinfo ((struct maven_data*)md) 1141#define mdinfo ((struct maven_data*)md)
1142#define minfo (mdinfo->primary_head) 1142#define minfo (mdinfo->primary_head)
1143 return maven_program_timming(md, &ACCESS_FBINFO(hw).maven); 1143 return maven_program_timming(md, &minfo->hw.maven);
1144#undef minfo 1144#undef minfo
1145#undef mdinfo 1145#undef mdinfo
1146} 1146}
@@ -1186,14 +1186,14 @@ static int maven_init_client(struct i2c_client* clnt) {
1186 struct maven_data* md = i2c_get_clientdata(clnt); 1186 struct maven_data* md = i2c_get_clientdata(clnt);
1187 MINFO_FROM(container_of(clnt->adapter, struct i2c_bit_adapter, adapter)->minfo); 1187 MINFO_FROM(container_of(clnt->adapter, struct i2c_bit_adapter, adapter)->minfo);
1188 1188
1189 md->primary_head = MINFO; 1189 md->primary_head = minfo;
1190 md->client = clnt; 1190 md->client = clnt;
1191 down_write(&ACCESS_FBINFO(altout.lock)); 1191 down_write(&minfo->altout.lock);
1192 ACCESS_FBINFO(outputs[1]).output = &maven_altout; 1192 minfo->outputs[1].output = &maven_altout;
1193 ACCESS_FBINFO(outputs[1]).src = ACCESS_FBINFO(outputs[1]).default_src; 1193 minfo->outputs[1].src = minfo->outputs[1].default_src;
1194 ACCESS_FBINFO(outputs[1]).data = md; 1194 minfo->outputs[1].data = md;
1195 ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR; 1195 minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
1196 up_write(&ACCESS_FBINFO(altout.lock)); 1196 up_write(&minfo->altout.lock);
1197 if (maven_get_reg(clnt, 0xB2) < 0x14) { 1197 if (maven_get_reg(clnt, 0xB2) < 0x14) {
1198 md->version = MGATVO_B; 1198 md->version = MGATVO_B;
1199 /* Tweak some things for this old chip */ 1199 /* Tweak some things for this old chip */
@@ -1220,12 +1220,12 @@ static int maven_shutdown_client(struct i2c_client* clnt) {
1220 if (md->primary_head) { 1220 if (md->primary_head) {
1221 MINFO_FROM(md->primary_head); 1221 MINFO_FROM(md->primary_head);
1222 1222
1223 down_write(&ACCESS_FBINFO(altout.lock)); 1223 down_write(&minfo->altout.lock);
1224 ACCESS_FBINFO(outputs[1]).src = MATROXFB_SRC_NONE; 1224 minfo->outputs[1].src = MATROXFB_SRC_NONE;
1225 ACCESS_FBINFO(outputs[1]).output = NULL; 1225 minfo->outputs[1].output = NULL;
1226 ACCESS_FBINFO(outputs[1]).data = NULL; 1226 minfo->outputs[1].data = NULL;
1227 ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR; 1227 minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
1228 up_write(&ACCESS_FBINFO(altout.lock)); 1228 up_write(&minfo->altout.lock);
1229 md->primary_head = NULL; 1229 md->primary_head = NULL;
1230 } 1230 }
1231 return 0; 1231 return 0;
diff --git a/drivers/video/matrox/matroxfb_misc.c b/drivers/video/matrox/matroxfb_misc.c
index d5b9e789cca6..fe07af8486e4 100644
--- a/drivers/video/matrox/matroxfb_misc.c
+++ b/drivers/video/matrox/matroxfb_misc.c
@@ -190,7 +190,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
190 unsigned int wd; 190 unsigned int wd;
191 unsigned int divider; 191 unsigned int divider;
192 int i; 192 int i;
193 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw); 193 struct matrox_hw_state * const hw = &minfo->hw;
194 194
195 DBG(__func__) 195 DBG(__func__)
196 196
@@ -240,7 +240,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
240 /* standard timmings are in 8pixels, but for interleaved we cannot */ 240 /* standard timmings are in 8pixels, but for interleaved we cannot */
241 /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */ 241 /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
242 /* using 16 or more pixels per unit can save us */ 242 /* using 16 or more pixels per unit can save us */
243 divider = ACCESS_FBINFO(curr.final_bppShift); 243 divider = minfo->curr.final_bppShift;
244 while (divider & 3) { 244 while (divider & 3) {
245 hd >>= 1; 245 hd >>= 1;
246 hs >>= 1; 246 hs >>= 1;
@@ -270,7 +270,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
270 if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04)) 270 if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
271 ht++; 271 ht++;
272 hbe = ht; 272 hbe = ht;
273 wd = ACCESS_FBINFO(fbcon).var.xres_virtual * ACCESS_FBINFO(curr.final_bppShift) / 64; 273 wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
274 274
275 hw->CRTCEXT[0] = 0; 275 hw->CRTCEXT[0] = 0;
276 hw->CRTCEXT[5] = 0; 276 hw->CRTCEXT[5] = 0;
@@ -287,7 +287,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
287 ((hs & 0x100) >> 6) | /* sync start */ 287 ((hs & 0x100) >> 6) | /* sync start */
288 (hbe & 0x040); /* end hor. blanking */ 288 (hbe & 0x040); /* end hor. blanking */
289 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */ 289 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */
290 if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC1) 290 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
291 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */ 291 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
292 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) | 292 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
293 ((vd & 0x400) >> 8) | /* disp end */ 293 ((vd & 0x400) >> 8) | /* disp end */
@@ -333,7 +333,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
333 333
334void matroxfb_vgaHWrestore(WPMINFO2) { 334void matroxfb_vgaHWrestore(WPMINFO2) {
335 int i; 335 int i;
336 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw); 336 struct matrox_hw_state * const hw = &minfo->hw;
337 CRITFLAGS 337 CRITFLAGS
338 338
339 DBG(__func__) 339 DBG(__func__)
@@ -533,98 +533,98 @@ static int parse_pins1(WPMINFO const struct matrox_bios* bd) {
533 if (get_unaligned_le16(bd->pins + 24)) { 533 if (get_unaligned_le16(bd->pins + 24)) {
534 maxdac = get_unaligned_le16(bd->pins + 24) * 10; 534 maxdac = get_unaligned_le16(bd->pins + 24) * 10;
535 } 535 }
536 MINFO->limits.pixel.vcomax = maxdac; 536 minfo->limits.pixel.vcomax = maxdac;
537 MINFO->values.pll.system = get_unaligned_le16(bd->pins + 28) ? 537 minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
538 get_unaligned_le16(bd->pins + 28) * 10 : 50000; 538 get_unaligned_le16(bd->pins + 28) * 10 : 50000;
539 /* ignore 4MB, 8MB, module clocks */ 539 /* ignore 4MB, 8MB, module clocks */
540 MINFO->features.pll.ref_freq = 14318; 540 minfo->features.pll.ref_freq = 14318;
541 MINFO->values.reg.mctlwtst = 0x00030101; 541 minfo->values.reg.mctlwtst = 0x00030101;
542 return 0; 542 return 0;
543} 543}
544 544
545static void default_pins1(WPMINFO2) { 545static void default_pins1(WPMINFO2) {
546 /* Millennium */ 546 /* Millennium */
547 MINFO->limits.pixel.vcomax = 220000; 547 minfo->limits.pixel.vcomax = 220000;
548 MINFO->values.pll.system = 50000; 548 minfo->values.pll.system = 50000;
549 MINFO->features.pll.ref_freq = 14318; 549 minfo->features.pll.ref_freq = 14318;
550 MINFO->values.reg.mctlwtst = 0x00030101; 550 minfo->values.reg.mctlwtst = 0x00030101;
551} 551}
552 552
553static int parse_pins2(WPMINFO const struct matrox_bios* bd) { 553static int parse_pins2(WPMINFO const struct matrox_bios* bd) {
554 MINFO->limits.pixel.vcomax = 554 minfo->limits.pixel.vcomax =
555 MINFO->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000); 555 minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
556 MINFO->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) | 556 minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
557 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) | 557 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
558 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) | 558 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
559 ((bd->pins[51] & 0x08) ? 0x00020000 : 0); 559 ((bd->pins[51] & 0x08) ? 0x00020000 : 0);
560 MINFO->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000); 560 minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
561 MINFO->features.pll.ref_freq = 14318; 561 minfo->features.pll.ref_freq = 14318;
562 return 0; 562 return 0;
563} 563}
564 564
565static void default_pins2(WPMINFO2) { 565static void default_pins2(WPMINFO2) {
566 /* Millennium II, Mystique */ 566 /* Millennium II, Mystique */
567 MINFO->limits.pixel.vcomax = 567 minfo->limits.pixel.vcomax =
568 MINFO->limits.system.vcomax = 230000; 568 minfo->limits.system.vcomax = 230000;
569 MINFO->values.reg.mctlwtst = 0x00030101; 569 minfo->values.reg.mctlwtst = 0x00030101;
570 MINFO->values.pll.system = 50000; 570 minfo->values.pll.system = 50000;
571 MINFO->features.pll.ref_freq = 14318; 571 minfo->features.pll.ref_freq = 14318;
572} 572}
573 573
574static int parse_pins3(WPMINFO const struct matrox_bios* bd) { 574static int parse_pins3(WPMINFO const struct matrox_bios* bd) {
575 MINFO->limits.pixel.vcomax = 575 minfo->limits.pixel.vcomax =
576 MINFO->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000); 576 minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
577 MINFO->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ? 577 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
578 0x01250A21 : get_unaligned_le32(bd->pins + 48); 578 0x01250A21 : get_unaligned_le32(bd->pins + 48);
579 /* memory config */ 579 /* memory config */
580 MINFO->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) | 580 minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
581 ((bd->pins[57] << 22) & 0x00C00000) | 581 ((bd->pins[57] << 22) & 0x00C00000) |
582 ((bd->pins[56] << 1) & 0x000001E0) | 582 ((bd->pins[56] << 1) & 0x000001E0) |
583 ( bd->pins[56] & 0x0000000F); 583 ( bd->pins[56] & 0x0000000F);
584 MINFO->values.reg.opt = (bd->pins[54] & 7) << 10; 584 minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
585 MINFO->values.reg.opt2 = bd->pins[58] << 12; 585 minfo->values.reg.opt2 = bd->pins[58] << 12;
586 MINFO->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000; 586 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
587 return 0; 587 return 0;
588} 588}
589 589
590static void default_pins3(WPMINFO2) { 590static void default_pins3(WPMINFO2) {
591 /* G100, G200 */ 591 /* G100, G200 */
592 MINFO->limits.pixel.vcomax = 592 minfo->limits.pixel.vcomax =
593 MINFO->limits.system.vcomax = 230000; 593 minfo->limits.system.vcomax = 230000;
594 MINFO->values.reg.mctlwtst = 0x01250A21; 594 minfo->values.reg.mctlwtst = 0x01250A21;
595 MINFO->values.reg.memrdbk = 0x00000000; 595 minfo->values.reg.memrdbk = 0x00000000;
596 MINFO->values.reg.opt = 0x00000C00; 596 minfo->values.reg.opt = 0x00000C00;
597 MINFO->values.reg.opt2 = 0x00000000; 597 minfo->values.reg.opt2 = 0x00000000;
598 MINFO->features.pll.ref_freq = 27000; 598 minfo->features.pll.ref_freq = 27000;
599} 599}
600 600
601static int parse_pins4(WPMINFO const struct matrox_bios* bd) { 601static int parse_pins4(WPMINFO const struct matrox_bios* bd) {
602 MINFO->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000; 602 minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
603 MINFO->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 38] * 4000; 603 minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
604 MINFO->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71); 604 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
605 MINFO->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) | 605 minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
606 ((bd->pins[87] << 22) & 0x00C00000) | 606 ((bd->pins[87] << 22) & 0x00C00000) |
607 ((bd->pins[86] << 1) & 0x000001E0) | 607 ((bd->pins[86] << 1) & 0x000001E0) |
608 ( bd->pins[86] & 0x0000000F); 608 ( bd->pins[86] & 0x0000000F);
609 MINFO->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) | 609 minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
610 ((bd->pins[53] << 22) & 0x10000000) | 610 ((bd->pins[53] << 22) & 0x10000000) |
611 ((bd->pins[53] << 7) & 0x00001C00); 611 ((bd->pins[53] << 7) & 0x00001C00);
612 MINFO->values.reg.opt3 = get_unaligned_le32(bd->pins + 67); 612 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
613 MINFO->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000; 613 minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
614 MINFO->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000; 614 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
615 return 0; 615 return 0;
616} 616}
617 617
618static void default_pins4(WPMINFO2) { 618static void default_pins4(WPMINFO2) {
619 /* G400 */ 619 /* G400 */
620 MINFO->limits.pixel.vcomax = 620 minfo->limits.pixel.vcomax =
621 MINFO->limits.system.vcomax = 252000; 621 minfo->limits.system.vcomax = 252000;
622 MINFO->values.reg.mctlwtst = 0x04A450A1; 622 minfo->values.reg.mctlwtst = 0x04A450A1;
623 MINFO->values.reg.memrdbk = 0x000000E7; 623 minfo->values.reg.memrdbk = 0x000000E7;
624 MINFO->values.reg.opt = 0x10000400; 624 minfo->values.reg.opt = 0x10000400;
625 MINFO->values.reg.opt3 = 0x0190A419; 625 minfo->values.reg.opt3 = 0x0190A419;
626 MINFO->values.pll.system = 200000; 626 minfo->values.pll.system = 200000;
627 MINFO->features.pll.ref_freq = 27000; 627 minfo->features.pll.ref_freq = 27000;
628} 628}
629 629
630static int parse_pins5(WPMINFO const struct matrox_bios* bd) { 630static int parse_pins5(WPMINFO const struct matrox_bios* bd) {
@@ -632,65 +632,65 @@ static int parse_pins5(WPMINFO const struct matrox_bios* bd) {
632 632
633 mult = bd->pins[4]?8000:6000; 633 mult = bd->pins[4]?8000:6000;
634 634
635 MINFO->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult; 635 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
636 MINFO->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 36] * mult; 636 minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
637 MINFO->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? MINFO->limits.system.vcomax : bd->pins[ 37] * mult; 637 minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
638 MINFO->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult; 638 minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
639 MINFO->limits.system.vcomin = (bd->pins[121] == 0xFF) ? MINFO->limits.pixel.vcomin : bd->pins[121] * mult; 639 minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
640 MINFO->limits.video.vcomin = (bd->pins[122] == 0xFF) ? MINFO->limits.system.vcomin : bd->pins[122] * mult; 640 minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
641 MINFO->values.pll.system = 641 minfo->values.pll.system =
642 MINFO->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000; 642 minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
643 MINFO->values.reg.opt = get_unaligned_le32(bd->pins + 48); 643 minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
644 MINFO->values.reg.opt2 = get_unaligned_le32(bd->pins + 52); 644 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
645 MINFO->values.reg.opt3 = get_unaligned_le32(bd->pins + 94); 645 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
646 MINFO->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98); 646 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
647 MINFO->values.reg.memmisc = get_unaligned_le32(bd->pins + 102); 647 minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
648 MINFO->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106); 648 minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
649 MINFO->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000; 649 minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
650 MINFO->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20; 650 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
651 MINFO->values.memory.dll = (bd->pins[115] & 0x02) != 0; 651 minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
652 MINFO->values.memory.emrswen = (bd->pins[115] & 0x01) != 0; 652 minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
653 MINFO->values.reg.maccess = MINFO->values.memory.emrswen ? 0x00004000 : 0x00000000; 653 minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
654 if (bd->pins[115] & 4) { 654 if (bd->pins[115] & 4) {
655 MINFO->values.reg.mctlwtst_core = MINFO->values.reg.mctlwtst; 655 minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
656 } else { 656 } else {
657 u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 }; 657 u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 };
658 MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) | 658 minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
659 wtst_xlat[MINFO->values.reg.mctlwtst & 7]; 659 wtst_xlat[minfo->values.reg.mctlwtst & 7];
660 } 660 }
661 MINFO->max_pixel_clock_panellink = bd->pins[47] * 4000; 661 minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
662 return 0; 662 return 0;
663} 663}
664 664
665static void default_pins5(WPMINFO2) { 665static void default_pins5(WPMINFO2) {
666 /* Mine 16MB G450 with SDRAM DDR */ 666 /* Mine 16MB G450 with SDRAM DDR */
667 MINFO->limits.pixel.vcomax = 667 minfo->limits.pixel.vcomax =
668 MINFO->limits.system.vcomax = 668 minfo->limits.system.vcomax =
669 MINFO->limits.video.vcomax = 600000; 669 minfo->limits.video.vcomax = 600000;
670 MINFO->limits.pixel.vcomin = 670 minfo->limits.pixel.vcomin =
671 MINFO->limits.system.vcomin = 671 minfo->limits.system.vcomin =
672 MINFO->limits.video.vcomin = 256000; 672 minfo->limits.video.vcomin = 256000;
673 MINFO->values.pll.system = 673 minfo->values.pll.system =
674 MINFO->values.pll.video = 284000; 674 minfo->values.pll.video = 284000;
675 MINFO->values.reg.opt = 0x404A1160; 675 minfo->values.reg.opt = 0x404A1160;
676 MINFO->values.reg.opt2 = 0x0000AC00; 676 minfo->values.reg.opt2 = 0x0000AC00;
677 MINFO->values.reg.opt3 = 0x0090A409; 677 minfo->values.reg.opt3 = 0x0090A409;
678 MINFO->values.reg.mctlwtst_core = 678 minfo->values.reg.mctlwtst_core =
679 MINFO->values.reg.mctlwtst = 0x0C81462B; 679 minfo->values.reg.mctlwtst = 0x0C81462B;
680 MINFO->values.reg.memmisc = 0x80000004; 680 minfo->values.reg.memmisc = 0x80000004;
681 MINFO->values.reg.memrdbk = 0x01001103; 681 minfo->values.reg.memrdbk = 0x01001103;
682 MINFO->features.pll.ref_freq = 27000; 682 minfo->features.pll.ref_freq = 27000;
683 MINFO->values.memory.ddr = 1; 683 minfo->values.memory.ddr = 1;
684 MINFO->values.memory.dll = 1; 684 minfo->values.memory.dll = 1;
685 MINFO->values.memory.emrswen = 1; 685 minfo->values.memory.emrswen = 1;
686 MINFO->values.reg.maccess = 0x00004000; 686 minfo->values.reg.maccess = 0x00004000;
687} 687}
688 688
689static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) { 689static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) {
690 unsigned int pins_version; 690 unsigned int pins_version;
691 static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 }; 691 static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
692 692
693 switch (ACCESS_FBINFO(chip)) { 693 switch (minfo->chip) {
694 case MGA_2064: default_pins1(PMINFO2); break; 694 case MGA_2064: default_pins1(PMINFO2); break;
695 case MGA_2164: 695 case MGA_2164:
696 case MGA_1064: 696 case MGA_1064:
@@ -743,19 +743,19 @@ void matroxfb_read_pins(WPMINFO2) {
743 u32 opt; 743 u32 opt;
744 u32 biosbase; 744 u32 biosbase;
745 u32 fbbase; 745 u32 fbbase;
746 struct pci_dev* pdev = ACCESS_FBINFO(pcidev); 746 struct pci_dev *pdev = minfo->pcidev;
747 747
748 memset(&ACCESS_FBINFO(bios), 0, sizeof(ACCESS_FBINFO(bios))); 748 memset(&minfo->bios, 0, sizeof(minfo->bios));
749 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt); 749 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
750 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM); 750 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
751 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase); 751 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
752 pci_read_config_dword(pdev, ACCESS_FBINFO(devflags.fbResource), &fbbase); 752 pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
753 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE); 753 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
754 parse_bios(vaddr_va(ACCESS_FBINFO(video).vbase), &ACCESS_FBINFO(bios)); 754 parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
755 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase); 755 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
756 pci_write_config_dword(pdev, PCI_OPTION_REG, opt); 756 pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
757#ifdef CONFIG_X86 757#ifdef CONFIG_X86
758 if (!ACCESS_FBINFO(bios).bios_valid) { 758 if (!minfo->bios.bios_valid) {
759 unsigned char __iomem* b; 759 unsigned char __iomem* b;
760 760
761 b = ioremap(0x000C0000, 65536); 761 b = ioremap(0x000C0000, 65536);
@@ -769,15 +769,15 @@ void matroxfb_read_pins(WPMINFO2) {
769 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n", 769 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
770 ven, dev, pdev->vendor, pdev->device); 770 ven, dev, pdev->vendor, pdev->device);
771 } else { 771 } else {
772 parse_bios(b, &ACCESS_FBINFO(bios)); 772 parse_bios(b, &minfo->bios);
773 } 773 }
774 iounmap(b); 774 iounmap(b);
775 } 775 }
776 } 776 }
777#endif 777#endif
778 matroxfb_set_limits(PMINFO &ACCESS_FBINFO(bios)); 778 matroxfb_set_limits(PMINFO &minfo->bios);
779 printk(KERN_INFO "PInS memtype = %u\n", 779 printk(KERN_INFO "PInS memtype = %u\n",
780 (ACCESS_FBINFO(values).reg.opt & 0x1C00) >> 10); 780 (minfo->values.reg.opt & 0x1C00) >> 10);
781} 781}
782 782
783EXPORT_SYMBOL(matroxfb_DAC_in); 783EXPORT_SYMBOL(matroxfb_DAC_in);
diff --git a/drivers/video/matrox/matroxfb_misc.h b/drivers/video/matrox/matroxfb_misc.h
index cb62cc0ead96..b46004576fb2 100644
--- a/drivers/video/matrox/matroxfb_misc.h
+++ b/drivers/video/matrox/matroxfb_misc.h
@@ -8,7 +8,7 @@ int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int f
8 unsigned int* in, unsigned int* feed, unsigned int* post); 8 unsigned int* in, unsigned int* feed, unsigned int* post);
9static inline int PLL_calcclock(CPMINFO unsigned int freq, unsigned int fmax, 9static inline int PLL_calcclock(CPMINFO unsigned int freq, unsigned int fmax,
10 unsigned int* in, unsigned int* feed, unsigned int* post) { 10 unsigned int* in, unsigned int* feed, unsigned int* post) {
11 return matroxfb_PLL_calcclock(&ACCESS_FBINFO(features.pll), freq, fmax, in, feed, post); 11 return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post);
12} 12}
13 13
14int matroxfb_vgaHWinit(WPMINFO struct my_timming* m); 14int matroxfb_vgaHWinit(WPMINFO struct my_timming* m);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 12:54:44 -0500