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-rw-r--r--drivers/scsi/pm8001/Makefile7
-rw-r--r--drivers/scsi/pm8001/pm8001_hwi.c4
-rw-r--r--drivers/scsi/pm8001/pm8001_hwi.h2
-rw-r--r--drivers/scsi/pm8001/pm8001_init.c17
-rw-r--r--drivers/scsi/pm8001/pm8001_sas.c17
-rw-r--r--drivers/scsi/pm8001/pm8001_sas.h6
-rw-r--r--drivers/scsi/pm8001/pm80xx_hwi.c3772
-rw-r--r--drivers/scsi/pm8001/pm80xx_hwi.h1480
8 files changed, 5287 insertions, 18 deletions
diff --git a/drivers/scsi/pm8001/Makefile b/drivers/scsi/pm8001/Makefile
index 52f04296171c..ce4cd87c7c66 100644
--- a/drivers/scsi/pm8001/Makefile
+++ b/drivers/scsi/pm8001/Makefile
@@ -4,9 +4,10 @@
4# Copyright (C) 2008-2009 USI Co., Ltd. 4# Copyright (C) 2008-2009 USI Co., Ltd.
5 5
6 6
7obj-$(CONFIG_SCSI_PM8001) += pm8001.o 7obj-$(CONFIG_SCSI_PM8001) += pm80xx.o
8pm8001-y += pm8001_init.o \ 8pm80xx-y += pm8001_init.o \
9 pm8001_sas.o \ 9 pm8001_sas.o \
10 pm8001_ctl.o \ 10 pm8001_ctl.o \
11 pm8001_hwi.o 11 pm8001_hwi.o \
12 pm80xx_hwi.o
12 13
diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c
index 3cdd03ae9430..c486fe868e37 100644
--- a/drivers/scsi/pm8001/pm8001_hwi.c
+++ b/drivers/scsi/pm8001/pm8001_hwi.c
@@ -785,14 +785,14 @@ static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
785 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all 785 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
786 * the FW register status to the originated status. 786 * the FW register status to the originated status.
787 * @pm8001_ha: our hba card information 787 * @pm8001_ha: our hba card information
788 * @signature: signature in host scratch pad0 register.
789 */ 788 */
790static int 789static int
791pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature) 790pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
792{ 791{
793 u32 regVal, toggleVal; 792 u32 regVal, toggleVal;
794 u32 max_wait_count; 793 u32 max_wait_count;
795 u32 regVal1, regVal2, regVal3; 794 u32 regVal1, regVal2, regVal3;
795 u32 signature = 0x252acbcd; /* for host scratch pad0 */
796 unsigned long flags; 796 unsigned long flags;
797 797
798 /* step1: Check FW is ready for soft reset */ 798 /* step1: Check FW is ready for soft reset */
diff --git a/drivers/scsi/pm8001/pm8001_hwi.h b/drivers/scsi/pm8001/pm8001_hwi.h
index d437309cb1e1..2399aabbc4e4 100644
--- a/drivers/scsi/pm8001/pm8001_hwi.h
+++ b/drivers/scsi/pm8001/pm8001_hwi.h
@@ -298,7 +298,7 @@ struct local_phy_ctl_resp {
298 298
299 299
300#define OP_BITS 0x0000FF00 300#define OP_BITS 0x0000FF00
301#define ID_BITS 0x0000000F 301#define ID_BITS 0x000000FF
302 302
303/* 303/*
304 * brief the data structure of PORT Control Command 304 * brief the data structure of PORT Control Command
diff --git a/drivers/scsi/pm8001/pm8001_init.c b/drivers/scsi/pm8001/pm8001_init.c
index 75270ee1a7f0..e522e5908bc0 100644
--- a/drivers/scsi/pm8001/pm8001_init.c
+++ b/drivers/scsi/pm8001/pm8001_init.c
@@ -50,6 +50,10 @@ static struct scsi_transport_template *pm8001_stt;
50 */ 50 */
51static const struct pm8001_chip_info pm8001_chips[] = { 51static const struct pm8001_chip_info pm8001_chips[] = {
52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,}, 52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
53 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
54 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
55 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
56 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
53}; 57};
54static int pm8001_id; 58static int pm8001_id;
55 59
@@ -780,7 +784,7 @@ static int pm8001_pci_probe(struct pci_dev *pdev,
780 goto err_out_free; 784 goto err_out_free;
781 } 785 }
782 list_add_tail(&pm8001_ha->list, &hba_list); 786 list_add_tail(&pm8001_ha->list, &hba_list);
783 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd); 787 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
784 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 788 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
785 if (rc) 789 if (rc)
786 goto err_out_ha_free; 790 goto err_out_ha_free;
@@ -834,7 +838,7 @@ static void pm8001_pci_remove(struct pci_dev *pdev)
834 list_del(&pm8001_ha->list); 838 list_del(&pm8001_ha->list);
835 scsi_remove_host(pm8001_ha->shost); 839 scsi_remove_host(pm8001_ha->shost);
836 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 840 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
837 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd); 841 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
838 842
839#ifdef PM8001_USE_MSIX 843#ifdef PM8001_USE_MSIX
840 for (i = 0; i < pm8001_ha->number_of_intr; i++) 844 for (i = 0; i < pm8001_ha->number_of_intr; i++)
@@ -879,7 +883,7 @@ static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
879 return -ENODEV; 883 return -ENODEV;
880 } 884 }
881 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); 885 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
882 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd); 886 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
883#ifdef PM8001_USE_MSIX 887#ifdef PM8001_USE_MSIX
884 for (i = 0; i < pm8001_ha->number_of_intr; i++) 888 for (i = 0; i < pm8001_ha->number_of_intr; i++)
885 synchronize_irq(pm8001_ha->msix_entries[i].vector); 889 synchronize_irq(pm8001_ha->msix_entries[i].vector);
@@ -937,7 +941,12 @@ static int pm8001_pci_resume(struct pci_dev *pdev)
937 if (rc) 941 if (rc)
938 goto err_out_disable; 942 goto err_out_disable;
939 943
940 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha, 0x252acbcd); 944 /* chip soft rst only for spc */
945 if (pm8001_ha->chip_id == chip_8001) {
946 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
947 PM8001_INIT_DBG(pm8001_ha,
948 pm8001_printk("chip soft reset successful\n"));
949 }
941 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha); 950 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
942 if (rc) 951 if (rc)
943 goto err_out_disable; 952 goto err_out_disable;
diff --git a/drivers/scsi/pm8001/pm8001_sas.c b/drivers/scsi/pm8001/pm8001_sas.c
index b961112395d5..6bba59c7d657 100644
--- a/drivers/scsi/pm8001/pm8001_sas.c
+++ b/drivers/scsi/pm8001/pm8001_sas.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 * 3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd. 4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved. 5 * All rights reserved.
@@ -212,10 +212,12 @@ int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
212 break; 212 break;
213 case PHY_FUNC_GET_EVENTS: 213 case PHY_FUNC_GET_EVENTS:
214 spin_lock_irqsave(&pm8001_ha->lock, flags); 214 spin_lock_irqsave(&pm8001_ha->lock, flags);
215 if (-1 == pm8001_bar4_shift(pm8001_ha, 215 if (pm8001_ha->chip_id == chip_8001) {
216 if (-1 == pm8001_bar4_shift(pm8001_ha,
216 (phy_id < 4) ? 0x30000 : 0x40000)) { 217 (phy_id < 4) ? 0x30000 : 0x40000)) {
217 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 218 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
218 return -EINVAL; 219 return -EINVAL;
220 }
219 } 221 }
220 { 222 {
221 struct sas_phy *phy = sas_phy->phy; 223 struct sas_phy *phy = sas_phy->phy;
@@ -228,7 +230,8 @@ int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
228 phy->loss_of_dword_sync_count = qp[3]; 230 phy->loss_of_dword_sync_count = qp[3];
229 phy->phy_reset_problem_count = qp[4]; 231 phy->phy_reset_problem_count = qp[4];
230 } 232 }
231 pm8001_bar4_shift(pm8001_ha, 0); 233 if (pm8001_ha->chip_id == chip_8001)
234 pm8001_bar4_shift(pm8001_ha, 0);
232 spin_unlock_irqrestore(&pm8001_ha->lock, flags); 235 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
233 return 0; 236 return 0;
234 default: 237 default:
@@ -249,7 +252,9 @@ void pm8001_scan_start(struct Scsi_Host *shost)
249 struct pm8001_hba_info *pm8001_ha; 252 struct pm8001_hba_info *pm8001_ha;
250 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 253 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
251 pm8001_ha = sha->lldd_ha; 254 pm8001_ha = sha->lldd_ha;
252 PM8001_CHIP_DISP->sas_re_init_req(pm8001_ha); 255 /* SAS_RE_INITIALIZATION not available in SPCv/ve */
256 if (pm8001_ha->chip_id == chip_8001)
257 PM8001_CHIP_DISP->sas_re_init_req(pm8001_ha);
253 for (i = 0; i < pm8001_ha->chip->n_phy; ++i) 258 for (i = 0; i < pm8001_ha->chip->n_phy; ++i)
254 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i); 259 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
255} 260}
diff --git a/drivers/scsi/pm8001/pm8001_sas.h b/drivers/scsi/pm8001/pm8001_sas.h
index 8e281c8deff2..c6fd99a67c39 100644
--- a/drivers/scsi/pm8001/pm8001_sas.h
+++ b/drivers/scsi/pm8001/pm8001_sas.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * PMC-Sierra 8001/8081/8088/8089 SAS/SATA based host adapters driver 2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 * 3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd. 4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved. 5 * All rights reserved.
@@ -108,6 +108,7 @@ do { \
108#define PM8001_NAME_LENGTH 32/* generic length of strings */ 108#define PM8001_NAME_LENGTH 32/* generic length of strings */
109extern struct list_head hba_list; 109extern struct list_head hba_list;
110extern const struct pm8001_dispatch pm8001_8001_dispatch; 110extern const struct pm8001_dispatch pm8001_8001_dispatch;
111extern const struct pm8001_dispatch pm8001_80xx_dispatch;
111 112
112struct pm8001_hba_info; 113struct pm8001_hba_info;
113struct pm8001_ccb_info; 114struct pm8001_ccb_info;
@@ -131,7 +132,7 @@ struct pm8001_ioctl_payload {
131struct pm8001_dispatch { 132struct pm8001_dispatch {
132 char *name; 133 char *name;
133 int (*chip_init)(struct pm8001_hba_info *pm8001_ha); 134 int (*chip_init)(struct pm8001_hba_info *pm8001_ha);
134 int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha, u32 signature); 135 int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha);
135 void (*chip_rst)(struct pm8001_hba_info *pm8001_ha); 136 void (*chip_rst)(struct pm8001_hba_info *pm8001_ha);
136 int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha); 137 int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha);
137 void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha); 138 void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha);
@@ -453,6 +454,7 @@ struct pm8001_hba_info {
453#endif 454#endif
454 u32 logging_level; 455 u32 logging_level;
455 u32 fw_status; 456 u32 fw_status;
457 u32 smp_exp_mode;
456 u32 int_vector; 458 u32 int_vector;
457 const struct firmware *fw_image; 459 const struct firmware *fw_image;
458 u8 outq[PM8001_MAX_MSIX_VEC]; 460 u8 outq[PM8001_MAX_MSIX_VEC];
diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
new file mode 100644
index 000000000000..7dee46716a58
--- /dev/null
+++ b/drivers/scsi/pm8001/pm80xx_hwi.c
@@ -0,0 +1,3772 @@
1/*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46#define SMP_DIRECT 1
47#define SMP_INDIRECT 2
48/**
49 * read_main_config_table - read the configure table and save it.
50 * @pm8001_ha: our hba card information
51 */
52static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
53{
54 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
55
56 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
57 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
58 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
59 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
60 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
61 pm8001_mr32(address, MAIN_FW_REVISION);
62 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
63 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
64 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
65 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
66 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
67 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
68 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
69 pm8001_mr32(address, MAIN_GST_OFFSET);
70 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
71 pm8001_mr32(address, MAIN_IBQ_OFFSET);
72 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
73 pm8001_mr32(address, MAIN_OBQ_OFFSET);
74
75 /* read Error Dump Offset and Length */
76 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
78 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
80 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
81 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
82 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
83 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
84
85 /* read GPIO LED settings from the configuration table */
86 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
87 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
88
89 /* read analog Setting offset from the configuration table */
90 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
91 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
92
93 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
94 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
95 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
96 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
97}
98
99/**
100 * read_general_status_table - read the general status table and save it.
101 * @pm8001_ha: our hba card information
102 */
103static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
104{
105 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
106 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
107 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
108 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
109 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
110 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
111 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
112 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
113 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
114 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
115 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
116 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
117 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
118 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
119 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
120 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
121 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
122 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
123 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
124 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
125 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
126 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
127 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
128 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
129 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
130 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
131 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
132 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
133 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
134}
135/**
136 * read_phy_attr_table - read the phy attribute table and save it.
137 * @pm8001_ha: our hba card information
138 */
139static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
140{
141 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
142 pm8001_ha->phy_attr_table.phystart1_16[0] =
143 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
144 pm8001_ha->phy_attr_table.phystart1_16[1] =
145 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
146 pm8001_ha->phy_attr_table.phystart1_16[2] =
147 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
148 pm8001_ha->phy_attr_table.phystart1_16[3] =
149 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
150 pm8001_ha->phy_attr_table.phystart1_16[4] =
151 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
152 pm8001_ha->phy_attr_table.phystart1_16[5] =
153 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
154 pm8001_ha->phy_attr_table.phystart1_16[6] =
155 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
156 pm8001_ha->phy_attr_table.phystart1_16[7] =
157 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
158 pm8001_ha->phy_attr_table.phystart1_16[8] =
159 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
160 pm8001_ha->phy_attr_table.phystart1_16[9] =
161 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
162 pm8001_ha->phy_attr_table.phystart1_16[10] =
163 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
164 pm8001_ha->phy_attr_table.phystart1_16[11] =
165 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
166 pm8001_ha->phy_attr_table.phystart1_16[12] =
167 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
168 pm8001_ha->phy_attr_table.phystart1_16[13] =
169 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
170 pm8001_ha->phy_attr_table.phystart1_16[14] =
171 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
172 pm8001_ha->phy_attr_table.phystart1_16[15] =
173 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
174
175 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
176 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
177 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
178 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
179 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
180 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
181 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
182 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
183 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
184 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
185 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
186 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
187 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
188 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
189 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
190 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
191 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
192 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
193 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
194 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
195 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
196 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
197 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
198 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
199 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
200 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
201 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
202 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
203 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
204 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
205 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
206 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
207
208}
209
210/**
211 * read_inbnd_queue_table - read the inbound queue table and save it.
212 * @pm8001_ha: our hba card information
213 */
214static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
215{
216 int i;
217 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
218 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
219 u32 offset = i * 0x20;
220 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
221 get_pci_bar_index(pm8001_mr32(address,
222 (offset + IB_PIPCI_BAR)));
223 pm8001_ha->inbnd_q_tbl[i].pi_offset =
224 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
225 }
226}
227
228/**
229 * read_outbnd_queue_table - read the outbound queue table and save it.
230 * @pm8001_ha: our hba card information
231 */
232static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
233{
234 int i;
235 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
236 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
237 u32 offset = i * 0x24;
238 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
239 get_pci_bar_index(pm8001_mr32(address,
240 (offset + OB_CIPCI_BAR)));
241 pm8001_ha->outbnd_q_tbl[i].ci_offset =
242 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
243 }
244}
245
246/**
247 * init_default_table_values - init the default table.
248 * @pm8001_ha: our hba card information
249 */
250static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
251{
252 int i;
253 u32 offsetib, offsetob;
254 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
255 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
256
257 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
258 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
259 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
260 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
261 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
262 PM8001_EVENT_LOG_SIZE;
263 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
264 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
265 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
266 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
267 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
268 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
269 PM8001_EVENT_LOG_SIZE;
270 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
271 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
272
273 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
274 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
275 PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30);
276 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
277 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
278 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
279 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
280 pm8001_ha->inbnd_q_tbl[i].base_virt =
281 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
282 pm8001_ha->inbnd_q_tbl[i].total_length =
283 pm8001_ha->memoryMap.region[IB + i].total_len;
284 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
285 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
286 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
287 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
288 pm8001_ha->inbnd_q_tbl[i].ci_virt =
289 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
290 offsetib = i * 0x20;
291 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
292 get_pci_bar_index(pm8001_mr32(addressib,
293 (offsetib + 0x14)));
294 pm8001_ha->inbnd_q_tbl[i].pi_offset =
295 pm8001_mr32(addressib, (offsetib + 0x18));
296 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
297 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
298 }
299 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
300 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
301 PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30);
302 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
303 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
304 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
305 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
306 pm8001_ha->outbnd_q_tbl[i].base_virt =
307 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
308 pm8001_ha->outbnd_q_tbl[i].total_length =
309 pm8001_ha->memoryMap.region[OB + i].total_len;
310 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
311 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
312 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
313 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
314 /* interrupt vector based on oq */
315 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
316 pm8001_ha->outbnd_q_tbl[i].pi_virt =
317 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
318 offsetob = i * 0x24;
319 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
320 get_pci_bar_index(pm8001_mr32(addressob,
321 offsetob + 0x14));
322 pm8001_ha->outbnd_q_tbl[i].ci_offset =
323 pm8001_mr32(addressob, (offsetob + 0x18));
324 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
325 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
326 }
327}
328
329/**
330 * update_main_config_table - update the main default table to the HBA.
331 * @pm8001_ha: our hba card information
332 */
333static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
334{
335 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
336 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
337 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
338 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
339 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
340 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
341 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
342 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
343 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
344 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
345 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
346 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
347 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
348 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
349 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
350 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
351 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
352 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
353 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
354 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
355 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
356
357 /* SPCv specific */
358 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
359 /* Set GPIOLED to 0x2 for LED indicator */
360 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
361 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
362 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
363
364 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
365 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
366 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
367 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
368}
369
370/**
371 * update_inbnd_queue_table - update the inbound queue table to the HBA.
372 * @pm8001_ha: our hba card information
373 */
374static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
375 int number)
376{
377 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
378 u16 offset = number * 0x20;
379 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
380 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
381 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
382 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
383 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
384 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
385 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
386 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
387 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
388 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
389}
390
391/**
392 * update_outbnd_queue_table - update the outbound queue table to the HBA.
393 * @pm8001_ha: our hba card information
394 */
395static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
396 int number)
397{
398 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
399 u16 offset = number * 0x24;
400 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
401 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
402 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
403 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
404 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
405 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
406 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
407 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
408 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
409 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
410 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
411 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
412}
413
414/**
415 * mpi_init_check - check firmware initialization status.
416 * @pm8001_ha: our hba card information
417 */
418static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
419{
420 u32 max_wait_count;
421 u32 value;
422 u32 gst_len_mpistate;
423
424 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
425 table is updated */
426 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
427 /* wait until Inbound DoorBell Clear Register toggled */
428 max_wait_count = 2 * 1000 * 1000;/* 2 sec for spcv/ve */
429 do {
430 udelay(1);
431 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
432 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
433 } while ((value != 0) && (--max_wait_count));
434
435 if (!max_wait_count)
436 return -1;
437 /* check the MPI-State for initialization upto 100ms*/
438 max_wait_count = 100 * 1000;/* 100 msec */
439 do {
440 udelay(1);
441 gst_len_mpistate =
442 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
443 GST_GSTLEN_MPIS_OFFSET);
444 } while ((GST_MPI_STATE_INIT !=
445 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
446 if (!max_wait_count)
447 return -1;
448
449 /* check MPI Initialization error */
450 gst_len_mpistate = gst_len_mpistate >> 16;
451 if (0x0000 != gst_len_mpistate)
452 return -1;
453
454 return 0;
455}
456
457/**
458 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
459 * @pm8001_ha: our hba card information
460 */
461static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
462{
463 u32 value;
464 u32 max_wait_count;
465 u32 max_wait_time;
466 int ret = 0;
467
468 /* reset / PCIe ready */
469 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
470 do {
471 udelay(1);
472 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
473 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
474
475 /* check ila status */
476 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
477 do {
478 udelay(1);
479 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
480 } while (((value & SCRATCH_PAD_ILA_READY) !=
481 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
482 if (!max_wait_count)
483 ret = -1;
484 else {
485 PM8001_MSG_DBG(pm8001_ha,
486 pm8001_printk(" ila ready status in %d millisec\n",
487 (max_wait_time - max_wait_count)));
488 }
489
490 /* check RAAE status */
491 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
492 do {
493 udelay(1);
494 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
495 } while (((value & SCRATCH_PAD_RAAE_READY) !=
496 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
497 if (!max_wait_count)
498 ret = -1;
499 else {
500 PM8001_MSG_DBG(pm8001_ha,
501 pm8001_printk(" raae ready status in %d millisec\n",
502 (max_wait_time - max_wait_count)));
503 }
504
505 /* check iop0 status */
506 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
507 do {
508 udelay(1);
509 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
510 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
511 (--max_wait_count));
512 if (!max_wait_count)
513 ret = -1;
514 else {
515 PM8001_MSG_DBG(pm8001_ha,
516 pm8001_printk(" iop0 ready status in %d millisec\n",
517 (max_wait_time - max_wait_count)));
518 }
519
520 /* check iop1 status only for 16 port controllers */
521 if ((pm8001_ha->chip_id != chip_8008) &&
522 (pm8001_ha->chip_id != chip_8009)) {
523 /* 200 milli sec */
524 max_wait_time = max_wait_count = 200 * 1000;
525 do {
526 udelay(1);
527 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
528 } while (((value & SCRATCH_PAD_IOP1_READY) !=
529 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
530 if (!max_wait_count)
531 ret = -1;
532 else {
533 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
534 "iop1 ready status in %d millisec\n",
535 (max_wait_time - max_wait_count)));
536 }
537 }
538
539 return ret;
540}
541
542static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
543{
544 void __iomem *base_addr;
545 u32 value;
546 u32 offset;
547 u32 pcibar;
548 u32 pcilogic;
549
550 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
551 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
552
553 PM8001_INIT_DBG(pm8001_ha,
554 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
555 offset, value));
556 pcilogic = (value & 0xFC000000) >> 26;
557 pcibar = get_pci_bar_index(pcilogic);
558 PM8001_INIT_DBG(pm8001_ha,
559 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
560 pm8001_ha->main_cfg_tbl_addr = base_addr =
561 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
562 pm8001_ha->general_stat_tbl_addr =
563 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
564 0xFFFFFF);
565 pm8001_ha->inbnd_q_tbl_addr =
566 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
567 0xFFFFFF);
568 pm8001_ha->outbnd_q_tbl_addr =
569 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
570 0xFFFFFF);
571 pm8001_ha->ivt_tbl_addr =
572 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
573 0xFFFFFF);
574 pm8001_ha->pspa_q_tbl_addr =
575 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
576 0xFFFFFF);
577
578 PM8001_INIT_DBG(pm8001_ha,
579 pm8001_printk("GST OFFSET 0x%x\n",
580 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
581 PM8001_INIT_DBG(pm8001_ha,
582 pm8001_printk("INBND OFFSET 0x%x\n",
583 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
584 PM8001_INIT_DBG(pm8001_ha,
585 pm8001_printk("OBND OFFSET 0x%x\n",
586 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
587 PM8001_INIT_DBG(pm8001_ha,
588 pm8001_printk("IVT OFFSET 0x%x\n",
589 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
590 PM8001_INIT_DBG(pm8001_ha,
591 pm8001_printk("PSPA OFFSET 0x%x\n",
592 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
593 PM8001_INIT_DBG(pm8001_ha,
594 pm8001_printk("addr - main cfg %p general status %p\n",
595 pm8001_ha->main_cfg_tbl_addr,
596 pm8001_ha->general_stat_tbl_addr));
597 PM8001_INIT_DBG(pm8001_ha,
598 pm8001_printk("addr - inbnd %p obnd %p\n",
599 pm8001_ha->inbnd_q_tbl_addr,
600 pm8001_ha->outbnd_q_tbl_addr));
601 PM8001_INIT_DBG(pm8001_ha,
602 pm8001_printk("addr - pspa %p ivt %p\n",
603 pm8001_ha->pspa_q_tbl_addr,
604 pm8001_ha->ivt_tbl_addr));
605}
606
607/**
608 * pm80xx_set_thermal_config - support the thermal configuration
609 * @pm8001_ha: our hba card information.
610 */
611static int
612pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
613{
614 struct set_ctrl_cfg_req payload;
615 struct inbound_queue_table *circularQ;
616 int rc;
617 u32 tag;
618 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
619
620 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
621 rc = pm8001_tag_alloc(pm8001_ha, &tag);
622 if (rc)
623 return -1;
624
625 circularQ = &pm8001_ha->inbnd_q_tbl[0];
626 payload.tag = cpu_to_le32(tag);
627 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
628 (THERMAL_ENABLE << 8) | THERMAL_OP_CODE;
629 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
630
631 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
632 return rc;
633
634}
635
636/**
637 * pm80xx_get_encrypt_info - Check for encryption
638 * @pm8001_ha: our hba card information.
639 */
640static int
641pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
642{
643 u32 scratch3_value;
644 int ret;
645
646 /* Read encryption status from SCRATCH PAD 3 */
647 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
648
649 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
650 SCRATCH_PAD3_ENC_READY) {
651 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
652 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
653 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
654 SCRATCH_PAD3_SMF_ENABLED)
655 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
656 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
657 SCRATCH_PAD3_SMA_ENABLED)
658 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
659 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
660 SCRATCH_PAD3_SMB_ENABLED)
661 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
662 pm8001_ha->encrypt_info.status = 0;
663 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
664 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
665 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
666 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
667 pm8001_ha->encrypt_info.sec_mode,
668 pm8001_ha->encrypt_info.status));
669 ret = 0;
670 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
671 SCRATCH_PAD3_ENC_DISABLED) {
672 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
673 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
674 scratch3_value));
675 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
676 pm8001_ha->encrypt_info.cipher_mode = 0;
677 pm8001_ha->encrypt_info.sec_mode = 0;
678 return 0;
679 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
680 SCRATCH_PAD3_ENC_DIS_ERR) {
681 pm8001_ha->encrypt_info.status =
682 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
683 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
684 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
685 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
686 SCRATCH_PAD3_SMF_ENABLED)
687 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
688 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
689 SCRATCH_PAD3_SMA_ENABLED)
690 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
691 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
692 SCRATCH_PAD3_SMB_ENABLED)
693 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
694 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
695 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
696 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
697 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
698 pm8001_ha->encrypt_info.sec_mode,
699 pm8001_ha->encrypt_info.status));
700 ret = -1;
701 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
702 SCRATCH_PAD3_ENC_ENA_ERR) {
703
704 pm8001_ha->encrypt_info.status =
705 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
706 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
707 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
708 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
709 SCRATCH_PAD3_SMF_ENABLED)
710 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
711 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
712 SCRATCH_PAD3_SMA_ENABLED)
713 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
714 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
715 SCRATCH_PAD3_SMB_ENABLED)
716 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
717
718 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
719 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
720 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
721 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
722 pm8001_ha->encrypt_info.sec_mode,
723 pm8001_ha->encrypt_info.status));
724 ret = -1;
725 }
726 return ret;
727}
728
729/**
730 * pm80xx_encrypt_update - update flash with encryption informtion
731 * @pm8001_ha: our hba card information.
732 */
733static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
734{
735 struct kek_mgmt_req payload;
736 struct inbound_queue_table *circularQ;
737 int rc;
738 u32 tag;
739 u32 opc = OPC_INB_KEK_MANAGEMENT;
740
741 memset(&payload, 0, sizeof(struct kek_mgmt_req));
742 rc = pm8001_tag_alloc(pm8001_ha, &tag);
743 if (rc)
744 return -1;
745
746 circularQ = &pm8001_ha->inbnd_q_tbl[0];
747 payload.tag = cpu_to_le32(tag);
748 /* Currently only one key is used. New KEK index is 1.
749 * Current KEK index is 1. Store KEK to NVRAM is 1.
750 */
751 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
752 KEK_MGMT_SUBOP_KEYCARDUPDATE);
753
754 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
755
756 return rc;
757}
758
759/**
760 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
761 * @pm8001_ha: our hba card information
762 */
763static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
764{
765 int ret;
766 u8 i = 0;
767
768 /* check the firmware status */
769 if (-1 == check_fw_ready(pm8001_ha)) {
770 PM8001_FAIL_DBG(pm8001_ha,
771 pm8001_printk("Firmware is not ready!\n"));
772 return -EBUSY;
773 }
774
775 /* Initialize pci space address eg: mpi offset */
776 init_pci_device_addresses(pm8001_ha);
777 init_default_table_values(pm8001_ha);
778 read_main_config_table(pm8001_ha);
779 read_general_status_table(pm8001_ha);
780 read_inbnd_queue_table(pm8001_ha);
781 read_outbnd_queue_table(pm8001_ha);
782 read_phy_attr_table(pm8001_ha);
783
784 /* update main config table ,inbound table and outbound table */
785 update_main_config_table(pm8001_ha);
786 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
787 update_inbnd_queue_table(pm8001_ha, i);
788 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
789 update_outbnd_queue_table(pm8001_ha, i);
790
791 /* notify firmware update finished and check initialization status */
792 if (0 == mpi_init_check(pm8001_ha)) {
793 PM8001_INIT_DBG(pm8001_ha,
794 pm8001_printk("MPI initialize successful!\n"));
795 } else
796 return -EBUSY;
797
798 /* configure thermal */
799 pm80xx_set_thermal_config(pm8001_ha);
800
801 PM8001_INIT_DBG(pm8001_ha,
802 pm8001_printk("Thermal configuration successful!\n"));
803
804 /* Check for encryption */
805 if (pm8001_ha->chip->encrypt) {
806 PM8001_INIT_DBG(pm8001_ha,
807 pm8001_printk("Checking for encryption\n"));
808 ret = pm80xx_get_encrypt_info(pm8001_ha);
809 if (ret == -1) {
810 PM8001_INIT_DBG(pm8001_ha,
811 pm8001_printk("Encryption error !!\n"));
812 if (pm8001_ha->encrypt_info.status == 0x81) {
813 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
814 "Encryption enabled with error."
815 "Saving encryption key to flash\n"));
816 pm80xx_encrypt_update(pm8001_ha);
817 }
818 }
819 }
820 return 0;
821}
822
823static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
824{
825 u32 max_wait_count;
826 u32 value;
827 u32 gst_len_mpistate;
828 init_pci_device_addresses(pm8001_ha);
829 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
830 table is stop */
831 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
832
833 /* wait until Inbound DoorBell Clear Register toggled */
834 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
835 do {
836 udelay(1);
837 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
838 value &= SPCv_MSGU_CFG_TABLE_RESET;
839 } while ((value != 0) && (--max_wait_count));
840
841 if (!max_wait_count) {
842 PM8001_FAIL_DBG(pm8001_ha,
843 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
844 return -1;
845 }
846
847 /* check the MPI-State for termination in progress */
848 /* wait until Inbound DoorBell Clear Register toggled */
849 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
850 do {
851 udelay(1);
852 gst_len_mpistate =
853 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
854 GST_GSTLEN_MPIS_OFFSET);
855 if (GST_MPI_STATE_UNINIT ==
856 (gst_len_mpistate & GST_MPI_STATE_MASK))
857 break;
858 } while (--max_wait_count);
859 if (!max_wait_count) {
860 PM8001_FAIL_DBG(pm8001_ha,
861 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
862 gst_len_mpistate & GST_MPI_STATE_MASK));
863 return -1;
864 }
865
866 return 0;
867}
868
869/**
870 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
871 * the FW register status to the originated status.
872 * @pm8001_ha: our hba card information
873 */
874
875static int
876pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
877{
878 u32 regval;
879 u32 bootloader_state;
880
881 /* Check if MPI is in ready state to reset */
882 if (mpi_uninit_check(pm8001_ha) != 0) {
883 PM8001_FAIL_DBG(pm8001_ha,
884 pm8001_printk("MPI state is not ready\n"));
885 return -1;
886 }
887
888 /* checked for reset register normal state; 0x0 */
889 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
890 PM8001_INIT_DBG(pm8001_ha,
891 pm8001_printk("reset register before write : 0x%x\n", regval));
892
893 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
894 mdelay(500);
895
896 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
897 PM8001_INIT_DBG(pm8001_ha,
898 pm8001_printk("reset register after write 0x%x\n", regval));
899
900 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
901 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
902 PM8001_MSG_DBG(pm8001_ha,
903 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
904 regval));
905 } else {
906 PM8001_MSG_DBG(pm8001_ha,
907 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
908 regval));
909
910 /* check bootloader is successfully executed or in HDA mode */
911 bootloader_state =
912 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
913 SCRATCH_PAD1_BOOTSTATE_MASK;
914
915 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
916 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
917 "Bootloader state - HDA mode SEEPROM\n"));
918 } else if (bootloader_state ==
919 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
920 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
921 "Bootloader state - HDA mode Bootstrap Pin\n"));
922 } else if (bootloader_state ==
923 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
924 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
925 "Bootloader state - HDA mode soft reset\n"));
926 } else if (bootloader_state ==
927 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
928 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
929 "Bootloader state-HDA mode critical error\n"));
930 }
931 return -EBUSY;
932 }
933
934 /* check the firmware status after reset */
935 if (-1 == check_fw_ready(pm8001_ha)) {
936 PM8001_FAIL_DBG(pm8001_ha,
937 pm8001_printk("Firmware is not ready!\n"));
938 return -EBUSY;
939 }
940 PM8001_INIT_DBG(pm8001_ha,
941 pm8001_printk("SPCv soft reset Complete\n"));
942 return 0;
943}
944
945static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
946{
947 u32 i;
948
949 PM8001_INIT_DBG(pm8001_ha,
950 pm8001_printk("chip reset start\n"));
951
952 /* do SPCv chip reset. */
953 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
954 PM8001_INIT_DBG(pm8001_ha,
955 pm8001_printk("SPC soft reset Complete\n"));
956
957 /* Check this ..whether delay is required or no */
958 /* delay 10 usec */
959 udelay(10);
960
961 /* wait for 20 msec until the firmware gets reloaded */
962 i = 20;
963 do {
964 mdelay(1);
965 } while ((--i) != 0);
966
967 PM8001_INIT_DBG(pm8001_ha,
968 pm8001_printk("chip reset finished\n"));
969}
970
971/**
972 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
973 * @pm8001_ha: our hba card information
974 */
975static void
976pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
977{
978 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
979 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
980}
981
982/**
983 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
984 * @pm8001_ha: our hba card information
985 */
986static void
987pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
988{
989 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
990}
991
992/**
993 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
994 * @pm8001_ha: our hba card information
995 */
996static void
997pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
998{
999#ifdef PM8001_USE_MSIX
1000 u32 mask;
1001 mask = (u32)(1 << vec);
1002
1003 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1004 return;
1005#endif
1006 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1007
1008}
1009
1010/**
1011 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1012 * @pm8001_ha: our hba card information
1013 */
1014static void
1015pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1016{
1017#ifdef PM8001_USE_MSIX
1018 u32 mask;
1019 if (vec == 0xFF)
1020 mask = 0xFFFFFFFF;
1021 else
1022 mask = (u32)(1 << vec);
1023 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1024 return;
1025#endif
1026 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1027}
1028
1029/**
1030 * mpi_ssp_completion- process the event that FW response to the SSP request.
1031 * @pm8001_ha: our hba card information
1032 * @piomb: the message contents of this outbound message.
1033 *
1034 * When FW has completed a ssp request for example a IO request, after it has
1035 * filled the SG data with the data, it will trigger this event represent
1036 * that he has finished the job,please check the coresponding buffer.
1037 * So we will tell the caller who maybe waiting the result to tell upper layer
1038 * that the task has been finished.
1039 */
1040static void
1041mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1042{
1043 struct sas_task *t;
1044 struct pm8001_ccb_info *ccb;
1045 unsigned long flags;
1046 u32 status;
1047 u32 param;
1048 u32 tag;
1049 struct ssp_completion_resp *psspPayload;
1050 struct task_status_struct *ts;
1051 struct ssp_response_iu *iu;
1052 struct pm8001_device *pm8001_dev;
1053 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1054 status = le32_to_cpu(psspPayload->status);
1055 tag = le32_to_cpu(psspPayload->tag);
1056 ccb = &pm8001_ha->ccb_info[tag];
1057 if ((status == IO_ABORTED) && ccb->open_retry) {
1058 /* Being completed by another */
1059 ccb->open_retry = 0;
1060 return;
1061 }
1062 pm8001_dev = ccb->device;
1063 param = le32_to_cpu(psspPayload->param);
1064 t = ccb->task;
1065
1066 if (status && status != IO_UNDERFLOW)
1067 PM8001_FAIL_DBG(pm8001_ha,
1068 pm8001_printk("sas IO status 0x%x\n", status));
1069 if (unlikely(!t || !t->lldd_task || !t->dev))
1070 return;
1071 ts = &t->task_status;
1072 switch (status) {
1073 case IO_SUCCESS:
1074 PM8001_IO_DBG(pm8001_ha,
1075 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1076 param));
1077 if (param == 0) {
1078 ts->resp = SAS_TASK_COMPLETE;
1079 ts->stat = SAM_STAT_GOOD;
1080 } else {
1081 ts->resp = SAS_TASK_COMPLETE;
1082 ts->stat = SAS_PROTO_RESPONSE;
1083 ts->residual = param;
1084 iu = &psspPayload->ssp_resp_iu;
1085 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1086 }
1087 if (pm8001_dev)
1088 pm8001_dev->running_req--;
1089 break;
1090 case IO_ABORTED:
1091 PM8001_IO_DBG(pm8001_ha,
1092 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1093 ts->resp = SAS_TASK_COMPLETE;
1094 ts->stat = SAS_ABORTED_TASK;
1095 break;
1096 case IO_UNDERFLOW:
1097 /* SSP Completion with error */
1098 PM8001_IO_DBG(pm8001_ha,
1099 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1100 param));
1101 ts->resp = SAS_TASK_COMPLETE;
1102 ts->stat = SAS_DATA_UNDERRUN;
1103 ts->residual = param;
1104 if (pm8001_dev)
1105 pm8001_dev->running_req--;
1106 break;
1107 case IO_NO_DEVICE:
1108 PM8001_IO_DBG(pm8001_ha,
1109 pm8001_printk("IO_NO_DEVICE\n"));
1110 ts->resp = SAS_TASK_UNDELIVERED;
1111 ts->stat = SAS_PHY_DOWN;
1112 break;
1113 case IO_XFER_ERROR_BREAK:
1114 PM8001_IO_DBG(pm8001_ha,
1115 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1116 ts->resp = SAS_TASK_COMPLETE;
1117 ts->stat = SAS_OPEN_REJECT;
1118 /* Force the midlayer to retry */
1119 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1120 break;
1121 case IO_XFER_ERROR_PHY_NOT_READY:
1122 PM8001_IO_DBG(pm8001_ha,
1123 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1124 ts->resp = SAS_TASK_COMPLETE;
1125 ts->stat = SAS_OPEN_REJECT;
1126 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1127 break;
1128 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1129 PM8001_IO_DBG(pm8001_ha,
1130 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1131 ts->resp = SAS_TASK_COMPLETE;
1132 ts->stat = SAS_OPEN_REJECT;
1133 ts->open_rej_reason = SAS_OREJ_EPROTO;
1134 break;
1135 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1136 PM8001_IO_DBG(pm8001_ha,
1137 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1138 ts->resp = SAS_TASK_COMPLETE;
1139 ts->stat = SAS_OPEN_REJECT;
1140 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1141 break;
1142 case IO_OPEN_CNX_ERROR_BREAK:
1143 PM8001_IO_DBG(pm8001_ha,
1144 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1145 ts->resp = SAS_TASK_COMPLETE;
1146 ts->stat = SAS_OPEN_REJECT;
1147 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1148 break;
1149 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1150 PM8001_IO_DBG(pm8001_ha,
1151 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1152 ts->resp = SAS_TASK_COMPLETE;
1153 ts->stat = SAS_OPEN_REJECT;
1154 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1155 if (!t->uldd_task)
1156 pm8001_handle_event(pm8001_ha,
1157 pm8001_dev,
1158 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1159 break;
1160 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1161 PM8001_IO_DBG(pm8001_ha,
1162 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1163 ts->resp = SAS_TASK_COMPLETE;
1164 ts->stat = SAS_OPEN_REJECT;
1165 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1166 break;
1167 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1168 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1169 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1170 ts->resp = SAS_TASK_COMPLETE;
1171 ts->stat = SAS_OPEN_REJECT;
1172 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1173 break;
1174 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1175 PM8001_IO_DBG(pm8001_ha,
1176 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1177 ts->resp = SAS_TASK_UNDELIVERED;
1178 ts->stat = SAS_OPEN_REJECT;
1179 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1180 break;
1181 case IO_XFER_ERROR_NAK_RECEIVED:
1182 PM8001_IO_DBG(pm8001_ha,
1183 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1184 ts->resp = SAS_TASK_COMPLETE;
1185 ts->stat = SAS_OPEN_REJECT;
1186 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1187 break;
1188 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1189 PM8001_IO_DBG(pm8001_ha,
1190 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1191 ts->resp = SAS_TASK_COMPLETE;
1192 ts->stat = SAS_NAK_R_ERR;
1193 break;
1194 case IO_XFER_ERROR_DMA:
1195 PM8001_IO_DBG(pm8001_ha,
1196 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1197 ts->resp = SAS_TASK_COMPLETE;
1198 ts->stat = SAS_OPEN_REJECT;
1199 break;
1200 case IO_XFER_OPEN_RETRY_TIMEOUT:
1201 PM8001_IO_DBG(pm8001_ha,
1202 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1203 ts->resp = SAS_TASK_COMPLETE;
1204 ts->stat = SAS_OPEN_REJECT;
1205 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1206 break;
1207 case IO_XFER_ERROR_OFFSET_MISMATCH:
1208 PM8001_IO_DBG(pm8001_ha,
1209 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1210 ts->resp = SAS_TASK_COMPLETE;
1211 ts->stat = SAS_OPEN_REJECT;
1212 break;
1213 case IO_PORT_IN_RESET:
1214 PM8001_IO_DBG(pm8001_ha,
1215 pm8001_printk("IO_PORT_IN_RESET\n"));
1216 ts->resp = SAS_TASK_COMPLETE;
1217 ts->stat = SAS_OPEN_REJECT;
1218 break;
1219 case IO_DS_NON_OPERATIONAL:
1220 PM8001_IO_DBG(pm8001_ha,
1221 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1222 ts->resp = SAS_TASK_COMPLETE;
1223 ts->stat = SAS_OPEN_REJECT;
1224 if (!t->uldd_task)
1225 pm8001_handle_event(pm8001_ha,
1226 pm8001_dev,
1227 IO_DS_NON_OPERATIONAL);
1228 break;
1229 case IO_DS_IN_RECOVERY:
1230 PM8001_IO_DBG(pm8001_ha,
1231 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1232 ts->resp = SAS_TASK_COMPLETE;
1233 ts->stat = SAS_OPEN_REJECT;
1234 break;
1235 case IO_TM_TAG_NOT_FOUND:
1236 PM8001_IO_DBG(pm8001_ha,
1237 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1238 ts->resp = SAS_TASK_COMPLETE;
1239 ts->stat = SAS_OPEN_REJECT;
1240 break;
1241 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1242 PM8001_IO_DBG(pm8001_ha,
1243 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1244 ts->resp = SAS_TASK_COMPLETE;
1245 ts->stat = SAS_OPEN_REJECT;
1246 break;
1247 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1248 PM8001_IO_DBG(pm8001_ha,
1249 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1250 ts->resp = SAS_TASK_COMPLETE;
1251 ts->stat = SAS_OPEN_REJECT;
1252 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1253 break;
1254 default:
1255 PM8001_IO_DBG(pm8001_ha,
1256 pm8001_printk("Unknown status 0x%x\n", status));
1257 /* not allowed case. Therefore, return failed status */
1258 ts->resp = SAS_TASK_COMPLETE;
1259 ts->stat = SAS_OPEN_REJECT;
1260 break;
1261 }
1262 PM8001_IO_DBG(pm8001_ha,
1263 pm8001_printk("scsi_status = 0x%x\n ",
1264 psspPayload->ssp_resp_iu.status));
1265 spin_lock_irqsave(&t->task_state_lock, flags);
1266 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1267 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1268 t->task_state_flags |= SAS_TASK_STATE_DONE;
1269 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1270 spin_unlock_irqrestore(&t->task_state_lock, flags);
1271 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1272 "task 0x%p done with io_status 0x%x resp 0x%x "
1273 "stat 0x%x but aborted by upper layer!\n",
1274 t, status, ts->resp, ts->stat));
1275 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1276 } else {
1277 spin_unlock_irqrestore(&t->task_state_lock, flags);
1278 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1279 mb();/* in order to force CPU ordering */
1280 t->task_done(t);
1281 }
1282}
1283
1284/*See the comments for mpi_ssp_completion */
1285static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1286{
1287 struct sas_task *t;
1288 unsigned long flags;
1289 struct task_status_struct *ts;
1290 struct pm8001_ccb_info *ccb;
1291 struct pm8001_device *pm8001_dev;
1292 struct ssp_event_resp *psspPayload =
1293 (struct ssp_event_resp *)(piomb + 4);
1294 u32 event = le32_to_cpu(psspPayload->event);
1295 u32 tag = le32_to_cpu(psspPayload->tag);
1296 u32 port_id = le32_to_cpu(psspPayload->port_id);
1297
1298 ccb = &pm8001_ha->ccb_info[tag];
1299 t = ccb->task;
1300 pm8001_dev = ccb->device;
1301 if (event)
1302 PM8001_FAIL_DBG(pm8001_ha,
1303 pm8001_printk("sas IO status 0x%x\n", event));
1304 if (unlikely(!t || !t->lldd_task || !t->dev))
1305 return;
1306 ts = &t->task_status;
1307 PM8001_IO_DBG(pm8001_ha,
1308 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1309 port_id, tag, event));
1310 switch (event) {
1311 case IO_OVERFLOW:
1312 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1313 ts->resp = SAS_TASK_COMPLETE;
1314 ts->stat = SAS_DATA_OVERRUN;
1315 ts->residual = 0;
1316 if (pm8001_dev)
1317 pm8001_dev->running_req--;
1318 break;
1319 case IO_XFER_ERROR_BREAK:
1320 PM8001_IO_DBG(pm8001_ha,
1321 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1322 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1323 return;
1324 case IO_XFER_ERROR_PHY_NOT_READY:
1325 PM8001_IO_DBG(pm8001_ha,
1326 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1327 ts->resp = SAS_TASK_COMPLETE;
1328 ts->stat = SAS_OPEN_REJECT;
1329 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1330 break;
1331 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1332 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1333 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1334 ts->resp = SAS_TASK_COMPLETE;
1335 ts->stat = SAS_OPEN_REJECT;
1336 ts->open_rej_reason = SAS_OREJ_EPROTO;
1337 break;
1338 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1339 PM8001_IO_DBG(pm8001_ha,
1340 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1341 ts->resp = SAS_TASK_COMPLETE;
1342 ts->stat = SAS_OPEN_REJECT;
1343 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1344 break;
1345 case IO_OPEN_CNX_ERROR_BREAK:
1346 PM8001_IO_DBG(pm8001_ha,
1347 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1348 ts->resp = SAS_TASK_COMPLETE;
1349 ts->stat = SAS_OPEN_REJECT;
1350 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1351 break;
1352 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1353 PM8001_IO_DBG(pm8001_ha,
1354 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1355 ts->resp = SAS_TASK_COMPLETE;
1356 ts->stat = SAS_OPEN_REJECT;
1357 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1358 if (!t->uldd_task)
1359 pm8001_handle_event(pm8001_ha,
1360 pm8001_dev,
1361 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1362 break;
1363 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1364 PM8001_IO_DBG(pm8001_ha,
1365 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1366 ts->resp = SAS_TASK_COMPLETE;
1367 ts->stat = SAS_OPEN_REJECT;
1368 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1369 break;
1370 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1371 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1372 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1373 ts->resp = SAS_TASK_COMPLETE;
1374 ts->stat = SAS_OPEN_REJECT;
1375 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1376 break;
1377 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1378 PM8001_IO_DBG(pm8001_ha,
1379 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1380 ts->resp = SAS_TASK_COMPLETE;
1381 ts->stat = SAS_OPEN_REJECT;
1382 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1383 break;
1384 case IO_XFER_ERROR_NAK_RECEIVED:
1385 PM8001_IO_DBG(pm8001_ha,
1386 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1387 ts->resp = SAS_TASK_COMPLETE;
1388 ts->stat = SAS_OPEN_REJECT;
1389 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1390 break;
1391 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1392 PM8001_IO_DBG(pm8001_ha,
1393 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1394 ts->resp = SAS_TASK_COMPLETE;
1395 ts->stat = SAS_NAK_R_ERR;
1396 break;
1397 case IO_XFER_OPEN_RETRY_TIMEOUT:
1398 PM8001_IO_DBG(pm8001_ha,
1399 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1400 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1401 return;
1402 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1403 PM8001_IO_DBG(pm8001_ha,
1404 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1405 ts->resp = SAS_TASK_COMPLETE;
1406 ts->stat = SAS_DATA_OVERRUN;
1407 break;
1408 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1409 PM8001_IO_DBG(pm8001_ha,
1410 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1411 ts->resp = SAS_TASK_COMPLETE;
1412 ts->stat = SAS_DATA_OVERRUN;
1413 break;
1414 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1415 PM8001_IO_DBG(pm8001_ha,
1416 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1417 ts->resp = SAS_TASK_COMPLETE;
1418 ts->stat = SAS_DATA_OVERRUN;
1419 break;
1420 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1421 PM8001_IO_DBG(pm8001_ha,
1422 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1423 ts->resp = SAS_TASK_COMPLETE;
1424 ts->stat = SAS_DATA_OVERRUN;
1425 break;
1426 case IO_XFER_ERROR_OFFSET_MISMATCH:
1427 PM8001_IO_DBG(pm8001_ha,
1428 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1429 ts->resp = SAS_TASK_COMPLETE;
1430 ts->stat = SAS_DATA_OVERRUN;
1431 break;
1432 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1433 PM8001_IO_DBG(pm8001_ha,
1434 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1435 ts->resp = SAS_TASK_COMPLETE;
1436 ts->stat = SAS_DATA_OVERRUN;
1437 break;
1438 case IO_XFER_CMD_FRAME_ISSUED:
1439 PM8001_IO_DBG(pm8001_ha,
1440 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1441 return;
1442 default:
1443 PM8001_IO_DBG(pm8001_ha,
1444 pm8001_printk("Unknown status 0x%x\n", event));
1445 /* not allowed case. Therefore, return failed status */
1446 ts->resp = SAS_TASK_COMPLETE;
1447 ts->stat = SAS_DATA_OVERRUN;
1448 break;
1449 }
1450 spin_lock_irqsave(&t->task_state_lock, flags);
1451 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1452 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1453 t->task_state_flags |= SAS_TASK_STATE_DONE;
1454 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1455 spin_unlock_irqrestore(&t->task_state_lock, flags);
1456 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1457 "task 0x%p done with event 0x%x resp 0x%x "
1458 "stat 0x%x but aborted by upper layer!\n",
1459 t, event, ts->resp, ts->stat));
1460 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1461 } else {
1462 spin_unlock_irqrestore(&t->task_state_lock, flags);
1463 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1464 mb();/* in order to force CPU ordering */
1465 t->task_done(t);
1466 }
1467}
1468
1469/*See the comments for mpi_ssp_completion */
1470static void
1471mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1472{
1473 struct sas_task *t;
1474 struct pm8001_ccb_info *ccb;
1475 u32 param;
1476 u32 status;
1477 u32 tag;
1478 struct sata_completion_resp *psataPayload;
1479 struct task_status_struct *ts;
1480 struct ata_task_resp *resp ;
1481 u32 *sata_resp;
1482 struct pm8001_device *pm8001_dev;
1483 unsigned long flags = 0;
1484
1485 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1486 status = le32_to_cpu(psataPayload->status);
1487 tag = le32_to_cpu(psataPayload->tag);
1488
1489 ccb = &pm8001_ha->ccb_info[tag];
1490 param = le32_to_cpu(psataPayload->param);
1491 t = ccb->task;
1492 ts = &t->task_status;
1493 pm8001_dev = ccb->device;
1494 if (status)
1495 PM8001_FAIL_DBG(pm8001_ha,
1496 pm8001_printk("sata IO status 0x%x\n", status));
1497 if (unlikely(!t || !t->lldd_task || !t->dev))
1498 return;
1499
1500 switch (status) {
1501 case IO_SUCCESS:
1502 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1503 if (param == 0) {
1504 ts->resp = SAS_TASK_COMPLETE;
1505 ts->stat = SAM_STAT_GOOD;
1506 } else {
1507 u8 len;
1508 ts->resp = SAS_TASK_COMPLETE;
1509 ts->stat = SAS_PROTO_RESPONSE;
1510 ts->residual = param;
1511 PM8001_IO_DBG(pm8001_ha,
1512 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1513 param));
1514 sata_resp = &psataPayload->sata_resp[0];
1515 resp = (struct ata_task_resp *)ts->buf;
1516 if (t->ata_task.dma_xfer == 0 &&
1517 t->data_dir == PCI_DMA_FROMDEVICE) {
1518 len = sizeof(struct pio_setup_fis);
1519 PM8001_IO_DBG(pm8001_ha,
1520 pm8001_printk("PIO read len = %d\n", len));
1521 } else if (t->ata_task.use_ncq) {
1522 len = sizeof(struct set_dev_bits_fis);
1523 PM8001_IO_DBG(pm8001_ha,
1524 pm8001_printk("FPDMA len = %d\n", len));
1525 } else {
1526 len = sizeof(struct dev_to_host_fis);
1527 PM8001_IO_DBG(pm8001_ha,
1528 pm8001_printk("other len = %d\n", len));
1529 }
1530 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1531 resp->frame_len = len;
1532 memcpy(&resp->ending_fis[0], sata_resp, len);
1533 ts->buf_valid_size = sizeof(*resp);
1534 } else
1535 PM8001_IO_DBG(pm8001_ha,
1536 pm8001_printk("response to large\n"));
1537 }
1538 if (pm8001_dev)
1539 pm8001_dev->running_req--;
1540 break;
1541 case IO_ABORTED:
1542 PM8001_IO_DBG(pm8001_ha,
1543 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1544 ts->resp = SAS_TASK_COMPLETE;
1545 ts->stat = SAS_ABORTED_TASK;
1546 if (pm8001_dev)
1547 pm8001_dev->running_req--;
1548 break;
1549 /* following cases are to do cases */
1550 case IO_UNDERFLOW:
1551 /* SATA Completion with error */
1552 PM8001_IO_DBG(pm8001_ha,
1553 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1554 ts->resp = SAS_TASK_COMPLETE;
1555 ts->stat = SAS_DATA_UNDERRUN;
1556 ts->residual = param;
1557 if (pm8001_dev)
1558 pm8001_dev->running_req--;
1559 break;
1560 case IO_NO_DEVICE:
1561 PM8001_IO_DBG(pm8001_ha,
1562 pm8001_printk("IO_NO_DEVICE\n"));
1563 ts->resp = SAS_TASK_UNDELIVERED;
1564 ts->stat = SAS_PHY_DOWN;
1565 break;
1566 case IO_XFER_ERROR_BREAK:
1567 PM8001_IO_DBG(pm8001_ha,
1568 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1569 ts->resp = SAS_TASK_COMPLETE;
1570 ts->stat = SAS_INTERRUPTED;
1571 break;
1572 case IO_XFER_ERROR_PHY_NOT_READY:
1573 PM8001_IO_DBG(pm8001_ha,
1574 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1575 ts->resp = SAS_TASK_COMPLETE;
1576 ts->stat = SAS_OPEN_REJECT;
1577 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1578 break;
1579 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1580 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1581 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1582 ts->resp = SAS_TASK_COMPLETE;
1583 ts->stat = SAS_OPEN_REJECT;
1584 ts->open_rej_reason = SAS_OREJ_EPROTO;
1585 break;
1586 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1587 PM8001_IO_DBG(pm8001_ha,
1588 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1589 ts->resp = SAS_TASK_COMPLETE;
1590 ts->stat = SAS_OPEN_REJECT;
1591 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1592 break;
1593 case IO_OPEN_CNX_ERROR_BREAK:
1594 PM8001_IO_DBG(pm8001_ha,
1595 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1596 ts->resp = SAS_TASK_COMPLETE;
1597 ts->stat = SAS_OPEN_REJECT;
1598 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1599 break;
1600 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1601 PM8001_IO_DBG(pm8001_ha,
1602 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1603 ts->resp = SAS_TASK_COMPLETE;
1604 ts->stat = SAS_DEV_NO_RESPONSE;
1605 if (!t->uldd_task) {
1606 pm8001_handle_event(pm8001_ha,
1607 pm8001_dev,
1608 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1609 ts->resp = SAS_TASK_UNDELIVERED;
1610 ts->stat = SAS_QUEUE_FULL;
1611 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1612 mb();/*in order to force CPU ordering*/
1613 spin_unlock_irq(&pm8001_ha->lock);
1614 t->task_done(t);
1615 spin_lock_irq(&pm8001_ha->lock);
1616 return;
1617 }
1618 break;
1619 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1620 PM8001_IO_DBG(pm8001_ha,
1621 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1622 ts->resp = SAS_TASK_UNDELIVERED;
1623 ts->stat = SAS_OPEN_REJECT;
1624 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1625 if (!t->uldd_task) {
1626 pm8001_handle_event(pm8001_ha,
1627 pm8001_dev,
1628 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1629 ts->resp = SAS_TASK_UNDELIVERED;
1630 ts->stat = SAS_QUEUE_FULL;
1631 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1632 mb();/*ditto*/
1633 spin_unlock_irq(&pm8001_ha->lock);
1634 t->task_done(t);
1635 spin_lock_irq(&pm8001_ha->lock);
1636 return;
1637 }
1638 break;
1639 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1640 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1641 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1642 ts->resp = SAS_TASK_COMPLETE;
1643 ts->stat = SAS_OPEN_REJECT;
1644 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1645 break;
1646 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1647 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1648 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
1649 ts->resp = SAS_TASK_COMPLETE;
1650 ts->stat = SAS_DEV_NO_RESPONSE;
1651 if (!t->uldd_task) {
1652 pm8001_handle_event(pm8001_ha,
1653 pm8001_dev,
1654 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
1655 ts->resp = SAS_TASK_UNDELIVERED;
1656 ts->stat = SAS_QUEUE_FULL;
1657 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1658 mb();/* ditto*/
1659 spin_unlock_irq(&pm8001_ha->lock);
1660 t->task_done(t);
1661 spin_lock_irq(&pm8001_ha->lock);
1662 return;
1663 }
1664 break;
1665 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1666 PM8001_IO_DBG(pm8001_ha,
1667 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1668 ts->resp = SAS_TASK_COMPLETE;
1669 ts->stat = SAS_OPEN_REJECT;
1670 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1671 break;
1672 case IO_XFER_ERROR_NAK_RECEIVED:
1673 PM8001_IO_DBG(pm8001_ha,
1674 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1675 ts->resp = SAS_TASK_COMPLETE;
1676 ts->stat = SAS_NAK_R_ERR;
1677 break;
1678 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1679 PM8001_IO_DBG(pm8001_ha,
1680 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1681 ts->resp = SAS_TASK_COMPLETE;
1682 ts->stat = SAS_NAK_R_ERR;
1683 break;
1684 case IO_XFER_ERROR_DMA:
1685 PM8001_IO_DBG(pm8001_ha,
1686 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1687 ts->resp = SAS_TASK_COMPLETE;
1688 ts->stat = SAS_ABORTED_TASK;
1689 break;
1690 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
1691 PM8001_IO_DBG(pm8001_ha,
1692 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
1693 ts->resp = SAS_TASK_UNDELIVERED;
1694 ts->stat = SAS_DEV_NO_RESPONSE;
1695 break;
1696 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
1697 PM8001_IO_DBG(pm8001_ha,
1698 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
1699 ts->resp = SAS_TASK_COMPLETE;
1700 ts->stat = SAS_DATA_UNDERRUN;
1701 break;
1702 case IO_XFER_OPEN_RETRY_TIMEOUT:
1703 PM8001_IO_DBG(pm8001_ha,
1704 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1705 ts->resp = SAS_TASK_COMPLETE;
1706 ts->stat = SAS_OPEN_TO;
1707 break;
1708 case IO_PORT_IN_RESET:
1709 PM8001_IO_DBG(pm8001_ha,
1710 pm8001_printk("IO_PORT_IN_RESET\n"));
1711 ts->resp = SAS_TASK_COMPLETE;
1712 ts->stat = SAS_DEV_NO_RESPONSE;
1713 break;
1714 case IO_DS_NON_OPERATIONAL:
1715 PM8001_IO_DBG(pm8001_ha,
1716 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1717 ts->resp = SAS_TASK_COMPLETE;
1718 ts->stat = SAS_DEV_NO_RESPONSE;
1719 if (!t->uldd_task) {
1720 pm8001_handle_event(pm8001_ha, pm8001_dev,
1721 IO_DS_NON_OPERATIONAL);
1722 ts->resp = SAS_TASK_UNDELIVERED;
1723 ts->stat = SAS_QUEUE_FULL;
1724 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1725 mb();/*ditto*/
1726 spin_unlock_irq(&pm8001_ha->lock);
1727 t->task_done(t);
1728 spin_lock_irq(&pm8001_ha->lock);
1729 return;
1730 }
1731 break;
1732 case IO_DS_IN_RECOVERY:
1733 PM8001_IO_DBG(pm8001_ha,
1734 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1735 ts->resp = SAS_TASK_COMPLETE;
1736 ts->stat = SAS_DEV_NO_RESPONSE;
1737 break;
1738 case IO_DS_IN_ERROR:
1739 PM8001_IO_DBG(pm8001_ha,
1740 pm8001_printk("IO_DS_IN_ERROR\n"));
1741 ts->resp = SAS_TASK_COMPLETE;
1742 ts->stat = SAS_DEV_NO_RESPONSE;
1743 if (!t->uldd_task) {
1744 pm8001_handle_event(pm8001_ha, pm8001_dev,
1745 IO_DS_IN_ERROR);
1746 ts->resp = SAS_TASK_UNDELIVERED;
1747 ts->stat = SAS_QUEUE_FULL;
1748 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1749 mb();/*ditto*/
1750 spin_unlock_irq(&pm8001_ha->lock);
1751 t->task_done(t);
1752 spin_lock_irq(&pm8001_ha->lock);
1753 return;
1754 }
1755 break;
1756 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1757 PM8001_IO_DBG(pm8001_ha,
1758 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1759 ts->resp = SAS_TASK_COMPLETE;
1760 ts->stat = SAS_OPEN_REJECT;
1761 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1762 default:
1763 PM8001_IO_DBG(pm8001_ha,
1764 pm8001_printk("Unknown status 0x%x\n", status));
1765 /* not allowed case. Therefore, return failed status */
1766 ts->resp = SAS_TASK_COMPLETE;
1767 ts->stat = SAS_DEV_NO_RESPONSE;
1768 break;
1769 }
1770 spin_lock_irqsave(&t->task_state_lock, flags);
1771 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1772 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1773 t->task_state_flags |= SAS_TASK_STATE_DONE;
1774 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1775 spin_unlock_irqrestore(&t->task_state_lock, flags);
1776 PM8001_FAIL_DBG(pm8001_ha,
1777 pm8001_printk("task 0x%p done with io_status 0x%x"
1778 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
1779 t, status, ts->resp, ts->stat));
1780 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1781 } else if (t->uldd_task) {
1782 spin_unlock_irqrestore(&t->task_state_lock, flags);
1783 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1784 mb();/* ditto */
1785 spin_unlock_irq(&pm8001_ha->lock);
1786 t->task_done(t);
1787 spin_lock_irq(&pm8001_ha->lock);
1788 } else if (!t->uldd_task) {
1789 spin_unlock_irqrestore(&t->task_state_lock, flags);
1790 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1791 mb();/*ditto*/
1792 spin_unlock_irq(&pm8001_ha->lock);
1793 t->task_done(t);
1794 spin_lock_irq(&pm8001_ha->lock);
1795 }
1796}
1797
1798/*See the comments for mpi_ssp_completion */
1799static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1800{
1801 struct sas_task *t;
1802 struct task_status_struct *ts;
1803 struct pm8001_ccb_info *ccb;
1804 struct pm8001_device *pm8001_dev;
1805 struct sata_event_resp *psataPayload =
1806 (struct sata_event_resp *)(piomb + 4);
1807 u32 event = le32_to_cpu(psataPayload->event);
1808 u32 tag = le32_to_cpu(psataPayload->tag);
1809 u32 port_id = le32_to_cpu(psataPayload->port_id);
1810 unsigned long flags = 0;
1811
1812 ccb = &pm8001_ha->ccb_info[tag];
1813 t = ccb->task;
1814 pm8001_dev = ccb->device;
1815 if (event)
1816 PM8001_FAIL_DBG(pm8001_ha,
1817 pm8001_printk("sata IO status 0x%x\n", event));
1818 if (unlikely(!t || !t->lldd_task || !t->dev))
1819 return;
1820 ts = &t->task_status;
1821 PM8001_IO_DBG(pm8001_ha,
1822 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1823 port_id, tag, event));
1824 switch (event) {
1825 case IO_OVERFLOW:
1826 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
1827 ts->resp = SAS_TASK_COMPLETE;
1828 ts->stat = SAS_DATA_OVERRUN;
1829 ts->residual = 0;
1830 if (pm8001_dev)
1831 pm8001_dev->running_req--;
1832 break;
1833 case IO_XFER_ERROR_BREAK:
1834 PM8001_IO_DBG(pm8001_ha,
1835 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1836 ts->resp = SAS_TASK_COMPLETE;
1837 ts->stat = SAS_INTERRUPTED;
1838 break;
1839 case IO_XFER_ERROR_PHY_NOT_READY:
1840 PM8001_IO_DBG(pm8001_ha,
1841 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1842 ts->resp = SAS_TASK_COMPLETE;
1843 ts->stat = SAS_OPEN_REJECT;
1844 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1845 break;
1846 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1847 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1848 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1849 ts->resp = SAS_TASK_COMPLETE;
1850 ts->stat = SAS_OPEN_REJECT;
1851 ts->open_rej_reason = SAS_OREJ_EPROTO;
1852 break;
1853 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1854 PM8001_IO_DBG(pm8001_ha,
1855 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1856 ts->resp = SAS_TASK_COMPLETE;
1857 ts->stat = SAS_OPEN_REJECT;
1858 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1859 break;
1860 case IO_OPEN_CNX_ERROR_BREAK:
1861 PM8001_IO_DBG(pm8001_ha,
1862 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1863 ts->resp = SAS_TASK_COMPLETE;
1864 ts->stat = SAS_OPEN_REJECT;
1865 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
1866 break;
1867 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1868 PM8001_IO_DBG(pm8001_ha,
1869 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1870 ts->resp = SAS_TASK_UNDELIVERED;
1871 ts->stat = SAS_DEV_NO_RESPONSE;
1872 if (!t->uldd_task) {
1873 pm8001_handle_event(pm8001_ha,
1874 pm8001_dev,
1875 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1876 ts->resp = SAS_TASK_COMPLETE;
1877 ts->stat = SAS_QUEUE_FULL;
1878 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1879 mb();/*ditto*/
1880 spin_unlock_irq(&pm8001_ha->lock);
1881 t->task_done(t);
1882 spin_lock_irq(&pm8001_ha->lock);
1883 return;
1884 }
1885 break;
1886 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1887 PM8001_IO_DBG(pm8001_ha,
1888 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1889 ts->resp = SAS_TASK_UNDELIVERED;
1890 ts->stat = SAS_OPEN_REJECT;
1891 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1892 break;
1893 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1894 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1895 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1896 ts->resp = SAS_TASK_COMPLETE;
1897 ts->stat = SAS_OPEN_REJECT;
1898 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1899 break;
1900 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1901 PM8001_IO_DBG(pm8001_ha,
1902 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1903 ts->resp = SAS_TASK_COMPLETE;
1904 ts->stat = SAS_OPEN_REJECT;
1905 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1906 break;
1907 case IO_XFER_ERROR_NAK_RECEIVED:
1908 PM8001_IO_DBG(pm8001_ha,
1909 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1910 ts->resp = SAS_TASK_COMPLETE;
1911 ts->stat = SAS_NAK_R_ERR;
1912 break;
1913 case IO_XFER_ERROR_PEER_ABORTED:
1914 PM8001_IO_DBG(pm8001_ha,
1915 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
1916 ts->resp = SAS_TASK_COMPLETE;
1917 ts->stat = SAS_NAK_R_ERR;
1918 break;
1919 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
1920 PM8001_IO_DBG(pm8001_ha,
1921 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
1922 ts->resp = SAS_TASK_COMPLETE;
1923 ts->stat = SAS_DATA_UNDERRUN;
1924 break;
1925 case IO_XFER_OPEN_RETRY_TIMEOUT:
1926 PM8001_IO_DBG(pm8001_ha,
1927 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1928 ts->resp = SAS_TASK_COMPLETE;
1929 ts->stat = SAS_OPEN_TO;
1930 break;
1931 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1932 PM8001_IO_DBG(pm8001_ha,
1933 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1934 ts->resp = SAS_TASK_COMPLETE;
1935 ts->stat = SAS_OPEN_TO;
1936 break;
1937 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1938 PM8001_IO_DBG(pm8001_ha,
1939 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1940 ts->resp = SAS_TASK_COMPLETE;
1941 ts->stat = SAS_OPEN_TO;
1942 break;
1943 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1944 PM8001_IO_DBG(pm8001_ha,
1945 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1946 ts->resp = SAS_TASK_COMPLETE;
1947 ts->stat = SAS_OPEN_TO;
1948 break;
1949 case IO_XFER_ERROR_OFFSET_MISMATCH:
1950 PM8001_IO_DBG(pm8001_ha,
1951 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1952 ts->resp = SAS_TASK_COMPLETE;
1953 ts->stat = SAS_OPEN_TO;
1954 break;
1955 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1956 PM8001_IO_DBG(pm8001_ha,
1957 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1958 ts->resp = SAS_TASK_COMPLETE;
1959 ts->stat = SAS_OPEN_TO;
1960 break;
1961 case IO_XFER_CMD_FRAME_ISSUED:
1962 PM8001_IO_DBG(pm8001_ha,
1963 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1964 break;
1965 case IO_XFER_PIO_SETUP_ERROR:
1966 PM8001_IO_DBG(pm8001_ha,
1967 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
1968 ts->resp = SAS_TASK_COMPLETE;
1969 ts->stat = SAS_OPEN_TO;
1970 break;
1971 default:
1972 PM8001_IO_DBG(pm8001_ha,
1973 pm8001_printk("Unknown status 0x%x\n", event));
1974 /* not allowed case. Therefore, return failed status */
1975 ts->resp = SAS_TASK_COMPLETE;
1976 ts->stat = SAS_OPEN_TO;
1977 break;
1978 }
1979 spin_lock_irqsave(&t->task_state_lock, flags);
1980 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1981 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1982 t->task_state_flags |= SAS_TASK_STATE_DONE;
1983 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1984 spin_unlock_irqrestore(&t->task_state_lock, flags);
1985 PM8001_FAIL_DBG(pm8001_ha,
1986 pm8001_printk("task 0x%p done with io_status 0x%x"
1987 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
1988 t, event, ts->resp, ts->stat));
1989 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1990 } else if (t->uldd_task) {
1991 spin_unlock_irqrestore(&t->task_state_lock, flags);
1992 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1993 mb();/* ditto */
1994 spin_unlock_irq(&pm8001_ha->lock);
1995 t->task_done(t);
1996 spin_lock_irq(&pm8001_ha->lock);
1997 } else if (!t->uldd_task) {
1998 spin_unlock_irqrestore(&t->task_state_lock, flags);
1999 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2000 mb();/*ditto*/
2001 spin_unlock_irq(&pm8001_ha->lock);
2002 t->task_done(t);
2003 spin_lock_irq(&pm8001_ha->lock);
2004 }
2005}
2006
2007/*See the comments for mpi_ssp_completion */
2008static void
2009mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2010{
2011 u32 param, i;
2012 struct sas_task *t;
2013 struct pm8001_ccb_info *ccb;
2014 unsigned long flags;
2015 u32 status;
2016 u32 tag;
2017 struct smp_completion_resp *psmpPayload;
2018 struct task_status_struct *ts;
2019 struct pm8001_device *pm8001_dev;
2020 char *pdma_respaddr = NULL;
2021
2022 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2023 status = le32_to_cpu(psmpPayload->status);
2024 tag = le32_to_cpu(psmpPayload->tag);
2025
2026 ccb = &pm8001_ha->ccb_info[tag];
2027 param = le32_to_cpu(psmpPayload->param);
2028 t = ccb->task;
2029 ts = &t->task_status;
2030 pm8001_dev = ccb->device;
2031 if (status)
2032 PM8001_FAIL_DBG(pm8001_ha,
2033 pm8001_printk("smp IO status 0x%x\n", status));
2034 if (unlikely(!t || !t->lldd_task || !t->dev))
2035 return;
2036
2037 switch (status) {
2038
2039 case IO_SUCCESS:
2040 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2041 ts->resp = SAS_TASK_COMPLETE;
2042 ts->stat = SAM_STAT_GOOD;
2043 if (pm8001_dev)
2044 pm8001_dev->running_req--;
2045 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2046 PM8001_IO_DBG(pm8001_ha,
2047 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2048 param));
2049 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2050 ((u64)sg_dma_address
2051 (&t->smp_task.smp_resp))));
2052 for (i = 0; i < param; i++) {
2053 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2054 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2055 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2056 i, *(pdma_respaddr+i),
2057 psmpPayload->_r_a[i]));
2058 }
2059 }
2060 break;
2061 case IO_ABORTED:
2062 PM8001_IO_DBG(pm8001_ha,
2063 pm8001_printk("IO_ABORTED IOMB\n"));
2064 ts->resp = SAS_TASK_COMPLETE;
2065 ts->stat = SAS_ABORTED_TASK;
2066 if (pm8001_dev)
2067 pm8001_dev->running_req--;
2068 break;
2069 case IO_OVERFLOW:
2070 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2071 ts->resp = SAS_TASK_COMPLETE;
2072 ts->stat = SAS_DATA_OVERRUN;
2073 ts->residual = 0;
2074 if (pm8001_dev)
2075 pm8001_dev->running_req--;
2076 break;
2077 case IO_NO_DEVICE:
2078 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2079 ts->resp = SAS_TASK_COMPLETE;
2080 ts->stat = SAS_PHY_DOWN;
2081 break;
2082 case IO_ERROR_HW_TIMEOUT:
2083 PM8001_IO_DBG(pm8001_ha,
2084 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2085 ts->resp = SAS_TASK_COMPLETE;
2086 ts->stat = SAM_STAT_BUSY;
2087 break;
2088 case IO_XFER_ERROR_BREAK:
2089 PM8001_IO_DBG(pm8001_ha,
2090 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2091 ts->resp = SAS_TASK_COMPLETE;
2092 ts->stat = SAM_STAT_BUSY;
2093 break;
2094 case IO_XFER_ERROR_PHY_NOT_READY:
2095 PM8001_IO_DBG(pm8001_ha,
2096 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2097 ts->resp = SAS_TASK_COMPLETE;
2098 ts->stat = SAM_STAT_BUSY;
2099 break;
2100 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2101 PM8001_IO_DBG(pm8001_ha,
2102 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2103 ts->resp = SAS_TASK_COMPLETE;
2104 ts->stat = SAS_OPEN_REJECT;
2105 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2106 break;
2107 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2108 PM8001_IO_DBG(pm8001_ha,
2109 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2110 ts->resp = SAS_TASK_COMPLETE;
2111 ts->stat = SAS_OPEN_REJECT;
2112 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2113 break;
2114 case IO_OPEN_CNX_ERROR_BREAK:
2115 PM8001_IO_DBG(pm8001_ha,
2116 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2117 ts->resp = SAS_TASK_COMPLETE;
2118 ts->stat = SAS_OPEN_REJECT;
2119 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2120 break;
2121 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2122 PM8001_IO_DBG(pm8001_ha,
2123 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2124 ts->resp = SAS_TASK_COMPLETE;
2125 ts->stat = SAS_OPEN_REJECT;
2126 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2127 pm8001_handle_event(pm8001_ha,
2128 pm8001_dev,
2129 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2130 break;
2131 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2132 PM8001_IO_DBG(pm8001_ha,
2133 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2134 ts->resp = SAS_TASK_COMPLETE;
2135 ts->stat = SAS_OPEN_REJECT;
2136 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2137 break;
2138 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2139 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2140 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2141 ts->resp = SAS_TASK_COMPLETE;
2142 ts->stat = SAS_OPEN_REJECT;
2143 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2144 break;
2145 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2146 PM8001_IO_DBG(pm8001_ha,
2147 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2148 ts->resp = SAS_TASK_COMPLETE;
2149 ts->stat = SAS_OPEN_REJECT;
2150 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2151 break;
2152 case IO_XFER_ERROR_RX_FRAME:
2153 PM8001_IO_DBG(pm8001_ha,
2154 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2155 ts->resp = SAS_TASK_COMPLETE;
2156 ts->stat = SAS_DEV_NO_RESPONSE;
2157 break;
2158 case IO_XFER_OPEN_RETRY_TIMEOUT:
2159 PM8001_IO_DBG(pm8001_ha,
2160 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2161 ts->resp = SAS_TASK_COMPLETE;
2162 ts->stat = SAS_OPEN_REJECT;
2163 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2164 break;
2165 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2166 PM8001_IO_DBG(pm8001_ha,
2167 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2168 ts->resp = SAS_TASK_COMPLETE;
2169 ts->stat = SAS_QUEUE_FULL;
2170 break;
2171 case IO_PORT_IN_RESET:
2172 PM8001_IO_DBG(pm8001_ha,
2173 pm8001_printk("IO_PORT_IN_RESET\n"));
2174 ts->resp = SAS_TASK_COMPLETE;
2175 ts->stat = SAS_OPEN_REJECT;
2176 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2177 break;
2178 case IO_DS_NON_OPERATIONAL:
2179 PM8001_IO_DBG(pm8001_ha,
2180 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2181 ts->resp = SAS_TASK_COMPLETE;
2182 ts->stat = SAS_DEV_NO_RESPONSE;
2183 break;
2184 case IO_DS_IN_RECOVERY:
2185 PM8001_IO_DBG(pm8001_ha,
2186 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2187 ts->resp = SAS_TASK_COMPLETE;
2188 ts->stat = SAS_OPEN_REJECT;
2189 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2190 break;
2191 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2192 PM8001_IO_DBG(pm8001_ha,
2193 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2194 ts->resp = SAS_TASK_COMPLETE;
2195 ts->stat = SAS_OPEN_REJECT;
2196 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2197 break;
2198 default:
2199 PM8001_IO_DBG(pm8001_ha,
2200 pm8001_printk("Unknown status 0x%x\n", status));
2201 ts->resp = SAS_TASK_COMPLETE;
2202 ts->stat = SAS_DEV_NO_RESPONSE;
2203 /* not allowed case. Therefore, return failed status */
2204 break;
2205 }
2206 spin_lock_irqsave(&t->task_state_lock, flags);
2207 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2208 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2209 t->task_state_flags |= SAS_TASK_STATE_DONE;
2210 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2211 spin_unlock_irqrestore(&t->task_state_lock, flags);
2212 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2213 "task 0x%p done with io_status 0x%x resp 0x%x"
2214 "stat 0x%x but aborted by upper layer!\n",
2215 t, status, ts->resp, ts->stat));
2216 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2217 } else {
2218 spin_unlock_irqrestore(&t->task_state_lock, flags);
2219 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2220 mb();/* in order to force CPU ordering */
2221 t->task_done(t);
2222 }
2223}
2224
2225/**
2226 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2227 * @pm8001_ha: our hba card information
2228 * @Qnum: the outbound queue message number.
2229 * @SEA: source of event to ack
2230 * @port_id: port id.
2231 * @phyId: phy id.
2232 * @param0: parameter 0.
2233 * @param1: parameter 1.
2234 */
2235static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2236 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2237{
2238 struct hw_event_ack_req payload;
2239 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2240
2241 struct inbound_queue_table *circularQ;
2242
2243 memset((u8 *)&payload, 0, sizeof(payload));
2244 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2245 payload.tag = cpu_to_le32(1);
2246 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2247 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2248 payload.param0 = cpu_to_le32(param0);
2249 payload.param1 = cpu_to_le32(param1);
2250 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2251}
2252
2253static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2254 u32 phyId, u32 phy_op);
2255
2256/**
2257 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2258 * @pm8001_ha: our hba card information
2259 * @piomb: IO message buffer
2260 */
2261static void
2262hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2263{
2264 struct hw_event_resp *pPayload =
2265 (struct hw_event_resp *)(piomb + 4);
2266 u32 lr_status_evt_portid =
2267 le32_to_cpu(pPayload->lr_status_evt_portid);
2268 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2269
2270 u8 link_rate =
2271 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2272 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2273 u8 phy_id =
2274 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2275 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2276
2277 struct pm8001_port *port = &pm8001_ha->port[port_id];
2278 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2279 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2280 unsigned long flags;
2281 u8 deviceType = pPayload->sas_identify.dev_type;
2282 port->port_state = portstate;
2283 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2284 "portid:%d; phyid:%d; linkrate:%d; "
2285 "portstate:%x; devicetype:%x\n",
2286 port_id, phy_id, link_rate, portstate, deviceType));
2287
2288 switch (deviceType) {
2289 case SAS_PHY_UNUSED:
2290 PM8001_MSG_DBG(pm8001_ha,
2291 pm8001_printk("device type no device.\n"));
2292 break;
2293 case SAS_END_DEVICE:
2294 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2295 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2296 PHY_NOTIFY_ENABLE_SPINUP);
2297 port->port_attached = 1;
2298 pm8001_get_lrate_mode(phy, link_rate);
2299 break;
2300 case SAS_EDGE_EXPANDER_DEVICE:
2301 PM8001_MSG_DBG(pm8001_ha,
2302 pm8001_printk("expander device.\n"));
2303 port->port_attached = 1;
2304 pm8001_get_lrate_mode(phy, link_rate);
2305 break;
2306 case SAS_FANOUT_EXPANDER_DEVICE:
2307 PM8001_MSG_DBG(pm8001_ha,
2308 pm8001_printk("fanout expander device.\n"));
2309 port->port_attached = 1;
2310 pm8001_get_lrate_mode(phy, link_rate);
2311 break;
2312 default:
2313 PM8001_MSG_DBG(pm8001_ha,
2314 pm8001_printk("unknown device type(%x)\n", deviceType));
2315 break;
2316 }
2317 phy->phy_type |= PORT_TYPE_SAS;
2318 phy->identify.device_type = deviceType;
2319 phy->phy_attached = 1;
2320 if (phy->identify.device_type == SAS_END_DEVICE)
2321 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2322 else if (phy->identify.device_type != SAS_PHY_UNUSED)
2323 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2324 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2325 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2326 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2327 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2328 sizeof(struct sas_identify_frame)-4);
2329 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2330 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2331 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2332 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2333 mdelay(200);/*delay a moment to wait disk to spinup*/
2334 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2335}
2336
2337/**
2338 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2339 * @pm8001_ha: our hba card information
2340 * @piomb: IO message buffer
2341 */
2342static void
2343hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2344{
2345 struct hw_event_resp *pPayload =
2346 (struct hw_event_resp *)(piomb + 4);
2347 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2348 u32 lr_status_evt_portid =
2349 le32_to_cpu(pPayload->lr_status_evt_portid);
2350 u8 link_rate =
2351 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2352 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2353 u8 phy_id =
2354 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2355
2356 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2357
2358 struct pm8001_port *port = &pm8001_ha->port[port_id];
2359 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2360 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2361 unsigned long flags;
2362 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2363 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2364 port_id, phy_id, link_rate, portstate));
2365
2366 port->port_state = portstate;
2367 port->port_attached = 1;
2368 pm8001_get_lrate_mode(phy, link_rate);
2369 phy->phy_type |= PORT_TYPE_SATA;
2370 phy->phy_attached = 1;
2371 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2372 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2373 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2374 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2375 sizeof(struct dev_to_host_fis));
2376 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2377 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2378 phy->identify.device_type = SATA_DEV;
2379 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2380 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2381 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2382}
2383
2384/**
2385 * hw_event_phy_down -we should notify the libsas the phy is down.
2386 * @pm8001_ha: our hba card information
2387 * @piomb: IO message buffer
2388 */
2389static void
2390hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
2391{
2392 struct hw_event_resp *pPayload =
2393 (struct hw_event_resp *)(piomb + 4);
2394
2395 u32 lr_status_evt_portid =
2396 le32_to_cpu(pPayload->lr_status_evt_portid);
2397 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2398 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2399 u8 phy_id =
2400 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2401 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2402
2403 struct pm8001_port *port = &pm8001_ha->port[port_id];
2404 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2405 port->port_state = portstate;
2406 phy->phy_type = 0;
2407 phy->identify.device_type = 0;
2408 phy->phy_attached = 0;
2409 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
2410 switch (portstate) {
2411 case PORT_VALID:
2412 break;
2413 case PORT_INVALID:
2414 PM8001_MSG_DBG(pm8001_ha,
2415 pm8001_printk(" PortInvalid portID %d\n", port_id));
2416 PM8001_MSG_DBG(pm8001_ha,
2417 pm8001_printk(" Last phy Down and port invalid\n"));
2418 port->port_attached = 0;
2419 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2420 port_id, phy_id, 0, 0);
2421 break;
2422 case PORT_IN_RESET:
2423 PM8001_MSG_DBG(pm8001_ha,
2424 pm8001_printk(" Port In Reset portID %d\n", port_id));
2425 break;
2426 case PORT_NOT_ESTABLISHED:
2427 PM8001_MSG_DBG(pm8001_ha,
2428 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
2429 port->port_attached = 0;
2430 break;
2431 case PORT_LOSTCOMM:
2432 PM8001_MSG_DBG(pm8001_ha,
2433 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
2434 PM8001_MSG_DBG(pm8001_ha,
2435 pm8001_printk(" Last phy Down and port invalid\n"));
2436 port->port_attached = 0;
2437 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
2438 port_id, phy_id, 0, 0);
2439 break;
2440 default:
2441 port->port_attached = 0;
2442 PM8001_MSG_DBG(pm8001_ha,
2443 pm8001_printk(" phy Down and(default) = 0x%x\n",
2444 portstate));
2445 break;
2446
2447 }
2448}
2449
2450static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2451{
2452 struct phy_start_resp *pPayload =
2453 (struct phy_start_resp *)(piomb + 4);
2454 u32 status =
2455 le32_to_cpu(pPayload->status);
2456 u32 phy_id =
2457 le32_to_cpu(pPayload->phyid);
2458 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2459
2460 PM8001_INIT_DBG(pm8001_ha,
2461 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
2462 status, phy_id));
2463 if (status == 0) {
2464 phy->phy_state = 1;
2465 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2466 complete(phy->enable_completion);
2467 }
2468 return 0;
2469
2470}
2471
2472/**
2473 * mpi_thermal_hw_event -The hw event has come.
2474 * @pm8001_ha: our hba card information
2475 * @piomb: IO message buffer
2476 */
2477static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2478{
2479 struct thermal_hw_event *pPayload =
2480 (struct thermal_hw_event *)(piomb + 4);
2481
2482 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
2483 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
2484
2485 if (thermal_event & 0x40) {
2486 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2487 "Thermal Event: Local high temperature violated!\n"));
2488 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2489 "Thermal Event: Measured local high temperature %d\n",
2490 ((rht_lht & 0xFF00) >> 8)));
2491 }
2492 if (thermal_event & 0x10) {
2493 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2494 "Thermal Event: Remote high temperature violated!\n"));
2495 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2496 "Thermal Event: Measured remote high temperature %d\n",
2497 ((rht_lht & 0xFF000000) >> 24)));
2498 }
2499 return 0;
2500}
2501
2502/**
2503 * mpi_hw_event -The hw event has come.
2504 * @pm8001_ha: our hba card information
2505 * @piomb: IO message buffer
2506 */
2507static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2508{
2509 unsigned long flags;
2510 struct hw_event_resp *pPayload =
2511 (struct hw_event_resp *)(piomb + 4);
2512 u32 lr_status_evt_portid =
2513 le32_to_cpu(pPayload->lr_status_evt_portid);
2514 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2515 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2516 u8 phy_id =
2517 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2518 u16 eventType =
2519 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
2520 u8 status =
2521 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
2522
2523 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2524 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2525 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
2526 PM8001_MSG_DBG(pm8001_ha,
2527 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
2528 port_id, phy_id, eventType, status));
2529
2530 switch (eventType) {
2531
2532 case HW_EVENT_SAS_PHY_UP:
2533 PM8001_MSG_DBG(pm8001_ha,
2534 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
2535 hw_event_sas_phy_up(pm8001_ha, piomb);
2536 break;
2537 case HW_EVENT_SATA_PHY_UP:
2538 PM8001_MSG_DBG(pm8001_ha,
2539 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
2540 hw_event_sata_phy_up(pm8001_ha, piomb);
2541 break;
2542 case HW_EVENT_SATA_SPINUP_HOLD:
2543 PM8001_MSG_DBG(pm8001_ha,
2544 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
2545 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
2546 break;
2547 case HW_EVENT_PHY_DOWN:
2548 PM8001_MSG_DBG(pm8001_ha,
2549 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
2550 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
2551 phy->phy_attached = 0;
2552 phy->phy_state = 0;
2553 hw_event_phy_down(pm8001_ha, piomb);
2554 break;
2555 case HW_EVENT_PORT_INVALID:
2556 PM8001_MSG_DBG(pm8001_ha,
2557 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
2558 sas_phy_disconnected(sas_phy);
2559 phy->phy_attached = 0;
2560 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2561 break;
2562 /* the broadcast change primitive received, tell the LIBSAS this event
2563 to revalidate the sas domain*/
2564 case HW_EVENT_BROADCAST_CHANGE:
2565 PM8001_MSG_DBG(pm8001_ha,
2566 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
2567 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
2568 port_id, phy_id, 1, 0);
2569 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2570 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
2571 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2572 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2573 break;
2574 case HW_EVENT_PHY_ERROR:
2575 PM8001_MSG_DBG(pm8001_ha,
2576 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
2577 sas_phy_disconnected(&phy->sas_phy);
2578 phy->phy_attached = 0;
2579 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
2580 break;
2581 case HW_EVENT_BROADCAST_EXP:
2582 PM8001_MSG_DBG(pm8001_ha,
2583 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
2584 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2585 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
2586 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2587 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2588 break;
2589 case HW_EVENT_LINK_ERR_INVALID_DWORD:
2590 PM8001_MSG_DBG(pm8001_ha,
2591 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
2592 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2593 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
2594 sas_phy_disconnected(sas_phy);
2595 phy->phy_attached = 0;
2596 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2597 break;
2598 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
2599 PM8001_MSG_DBG(pm8001_ha,
2600 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
2601 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2602 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
2603 port_id, phy_id, 0, 0);
2604 sas_phy_disconnected(sas_phy);
2605 phy->phy_attached = 0;
2606 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2607 break;
2608 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
2609 PM8001_MSG_DBG(pm8001_ha,
2610 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
2611 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2612 HW_EVENT_LINK_ERR_CODE_VIOLATION,
2613 port_id, phy_id, 0, 0);
2614 sas_phy_disconnected(sas_phy);
2615 phy->phy_attached = 0;
2616 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2617 break;
2618 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
2619 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2620 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
2621 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2622 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
2623 port_id, phy_id, 0, 0);
2624 sas_phy_disconnected(sas_phy);
2625 phy->phy_attached = 0;
2626 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2627 break;
2628 case HW_EVENT_MALFUNCTION:
2629 PM8001_MSG_DBG(pm8001_ha,
2630 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
2631 break;
2632 case HW_EVENT_BROADCAST_SES:
2633 PM8001_MSG_DBG(pm8001_ha,
2634 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
2635 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
2636 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
2637 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
2638 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2639 break;
2640 case HW_EVENT_INBOUND_CRC_ERROR:
2641 PM8001_MSG_DBG(pm8001_ha,
2642 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
2643 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2644 HW_EVENT_INBOUND_CRC_ERROR,
2645 port_id, phy_id, 0, 0);
2646 break;
2647 case HW_EVENT_HARD_RESET_RECEIVED:
2648 PM8001_MSG_DBG(pm8001_ha,
2649 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
2650 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
2651 break;
2652 case HW_EVENT_ID_FRAME_TIMEOUT:
2653 PM8001_MSG_DBG(pm8001_ha,
2654 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
2655 sas_phy_disconnected(sas_phy);
2656 phy->phy_attached = 0;
2657 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2658 break;
2659 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
2660 PM8001_MSG_DBG(pm8001_ha,
2661 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
2662 pm80xx_hw_event_ack_req(pm8001_ha, 0,
2663 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
2664 port_id, phy_id, 0, 0);
2665 sas_phy_disconnected(sas_phy);
2666 phy->phy_attached = 0;
2667 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2668 break;
2669 case HW_EVENT_PORT_RESET_TIMER_TMO:
2670 PM8001_MSG_DBG(pm8001_ha,
2671 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
2672 sas_phy_disconnected(sas_phy);
2673 phy->phy_attached = 0;
2674 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2675 break;
2676 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
2677 PM8001_MSG_DBG(pm8001_ha,
2678 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
2679 sas_phy_disconnected(sas_phy);
2680 phy->phy_attached = 0;
2681 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
2682 break;
2683 case HW_EVENT_PORT_RECOVER:
2684 PM8001_MSG_DBG(pm8001_ha,
2685 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
2686 break;
2687 case HW_EVENT_PORT_RESET_COMPLETE:
2688 PM8001_MSG_DBG(pm8001_ha,
2689 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
2690 break;
2691 case EVENT_BROADCAST_ASYNCH_EVENT:
2692 PM8001_MSG_DBG(pm8001_ha,
2693 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
2694 break;
2695 default:
2696 PM8001_MSG_DBG(pm8001_ha,
2697 pm8001_printk("Unknown event type 0x%x\n", eventType));
2698 break;
2699 }
2700 return 0;
2701}
2702
2703/**
2704 * mpi_phy_stop_resp - SPCv specific
2705 * @pm8001_ha: our hba card information
2706 * @piomb: IO message buffer
2707 */
2708static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2709{
2710 struct phy_stop_resp *pPayload =
2711 (struct phy_stop_resp *)(piomb + 4);
2712 u32 status =
2713 le32_to_cpu(pPayload->status);
2714 u32 phyid =
2715 le32_to_cpu(pPayload->phyid);
2716 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
2717 PM8001_MSG_DBG(pm8001_ha,
2718 pm8001_printk("phy:0x%x status:0x%x\n",
2719 phyid, status));
2720 if (status == 0)
2721 phy->phy_state = 0;
2722 return 0;
2723}
2724
2725/**
2726 * mpi_set_controller_config_resp - SPCv specific
2727 * @pm8001_ha: our hba card information
2728 * @piomb: IO message buffer
2729 */
2730static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
2731 void *piomb)
2732{
2733 struct set_ctrl_cfg_resp *pPayload =
2734 (struct set_ctrl_cfg_resp *)(piomb + 4);
2735 u32 status = le32_to_cpu(pPayload->status);
2736 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
2737
2738 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2739 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
2740 status, err_qlfr_pgcd));
2741
2742 return 0;
2743}
2744
2745/**
2746 * mpi_get_controller_config_resp - SPCv specific
2747 * @pm8001_ha: our hba card information
2748 * @piomb: IO message buffer
2749 */
2750static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
2751 void *piomb)
2752{
2753 PM8001_MSG_DBG(pm8001_ha,
2754 pm8001_printk(" pm80xx_addition_functionality\n"));
2755
2756 return 0;
2757}
2758
2759/**
2760 * mpi_get_phy_profile_resp - SPCv specific
2761 * @pm8001_ha: our hba card information
2762 * @piomb: IO message buffer
2763 */
2764static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
2765 void *piomb)
2766{
2767 PM8001_MSG_DBG(pm8001_ha,
2768 pm8001_printk(" pm80xx_addition_functionality\n"));
2769
2770 return 0;
2771}
2772
2773/**
2774 * mpi_flash_op_ext_resp - SPCv specific
2775 * @pm8001_ha: our hba card information
2776 * @piomb: IO message buffer
2777 */
2778static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2779{
2780 PM8001_MSG_DBG(pm8001_ha,
2781 pm8001_printk(" pm80xx_addition_functionality\n"));
2782
2783 return 0;
2784}
2785
2786/**
2787 * mpi_set_phy_profile_resp - SPCv specific
2788 * @pm8001_ha: our hba card information
2789 * @piomb: IO message buffer
2790 */
2791static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
2792 void *piomb)
2793{
2794 PM8001_MSG_DBG(pm8001_ha,
2795 pm8001_printk(" pm80xx_addition_functionality\n"));
2796
2797 return 0;
2798}
2799
2800/**
2801 * mpi_kek_management_resp - SPCv specific
2802 * @pm8001_ha: our hba card information
2803 * @piomb: IO message buffer
2804 */
2805static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
2806 void *piomb)
2807{
2808 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
2809
2810 u32 status = le32_to_cpu(pPayload->status);
2811 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
2812 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
2813
2814 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2815 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
2816 status, kidx_new_curr_ksop, err_qlfr));
2817
2818 return 0;
2819}
2820
2821/**
2822 * mpi_dek_management_resp - SPCv specific
2823 * @pm8001_ha: our hba card information
2824 * @piomb: IO message buffer
2825 */
2826static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
2827 void *piomb)
2828{
2829 PM8001_MSG_DBG(pm8001_ha,
2830 pm8001_printk(" pm80xx_addition_functionality\n"));
2831
2832 return 0;
2833}
2834
2835/**
2836 * ssp_coalesced_comp_resp - SPCv specific
2837 * @pm8001_ha: our hba card information
2838 * @piomb: IO message buffer
2839 */
2840static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
2841 void *piomb)
2842{
2843 PM8001_MSG_DBG(pm8001_ha,
2844 pm8001_printk(" pm80xx_addition_functionality\n"));
2845
2846 return 0;
2847}
2848
2849/**
2850 * process_one_iomb - process one outbound Queue memory block
2851 * @pm8001_ha: our hba card information
2852 * @piomb: IO message buffer
2853 */
2854static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
2855{
2856 __le32 pHeader = *(__le32 *)piomb;
2857 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
2858
2859 switch (opc) {
2860 case OPC_OUB_ECHO:
2861 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
2862 break;
2863 case OPC_OUB_HW_EVENT:
2864 PM8001_MSG_DBG(pm8001_ha,
2865 pm8001_printk("OPC_OUB_HW_EVENT\n"));
2866 mpi_hw_event(pm8001_ha, piomb);
2867 break;
2868 case OPC_OUB_THERM_HW_EVENT:
2869 PM8001_MSG_DBG(pm8001_ha,
2870 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
2871 mpi_thermal_hw_event(pm8001_ha, piomb);
2872 break;
2873 case OPC_OUB_SSP_COMP:
2874 PM8001_MSG_DBG(pm8001_ha,
2875 pm8001_printk("OPC_OUB_SSP_COMP\n"));
2876 mpi_ssp_completion(pm8001_ha, piomb);
2877 break;
2878 case OPC_OUB_SMP_COMP:
2879 PM8001_MSG_DBG(pm8001_ha,
2880 pm8001_printk("OPC_OUB_SMP_COMP\n"));
2881 mpi_smp_completion(pm8001_ha, piomb);
2882 break;
2883 case OPC_OUB_LOCAL_PHY_CNTRL:
2884 PM8001_MSG_DBG(pm8001_ha,
2885 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
2886 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
2887 break;
2888 case OPC_OUB_DEV_REGIST:
2889 PM8001_MSG_DBG(pm8001_ha,
2890 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
2891 pm8001_mpi_reg_resp(pm8001_ha, piomb);
2892 break;
2893 case OPC_OUB_DEREG_DEV:
2894 PM8001_MSG_DBG(pm8001_ha,
2895 pm8001_printk("unresgister the deviece\n"));
2896 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
2897 break;
2898 case OPC_OUB_GET_DEV_HANDLE:
2899 PM8001_MSG_DBG(pm8001_ha,
2900 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
2901 break;
2902 case OPC_OUB_SATA_COMP:
2903 PM8001_MSG_DBG(pm8001_ha,
2904 pm8001_printk("OPC_OUB_SATA_COMP\n"));
2905 mpi_sata_completion(pm8001_ha, piomb);
2906 break;
2907 case OPC_OUB_SATA_EVENT:
2908 PM8001_MSG_DBG(pm8001_ha,
2909 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
2910 mpi_sata_event(pm8001_ha, piomb);
2911 break;
2912 case OPC_OUB_SSP_EVENT:
2913 PM8001_MSG_DBG(pm8001_ha,
2914 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
2915 mpi_ssp_event(pm8001_ha, piomb);
2916 break;
2917 case OPC_OUB_DEV_HANDLE_ARRIV:
2918 PM8001_MSG_DBG(pm8001_ha,
2919 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
2920 /*This is for target*/
2921 break;
2922 case OPC_OUB_SSP_RECV_EVENT:
2923 PM8001_MSG_DBG(pm8001_ha,
2924 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
2925 /*This is for target*/
2926 break;
2927 case OPC_OUB_FW_FLASH_UPDATE:
2928 PM8001_MSG_DBG(pm8001_ha,
2929 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
2930 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
2931 break;
2932 case OPC_OUB_GPIO_RESPONSE:
2933 PM8001_MSG_DBG(pm8001_ha,
2934 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
2935 break;
2936 case OPC_OUB_GPIO_EVENT:
2937 PM8001_MSG_DBG(pm8001_ha,
2938 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
2939 break;
2940 case OPC_OUB_GENERAL_EVENT:
2941 PM8001_MSG_DBG(pm8001_ha,
2942 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
2943 pm8001_mpi_general_event(pm8001_ha, piomb);
2944 break;
2945 case OPC_OUB_SSP_ABORT_RSP:
2946 PM8001_MSG_DBG(pm8001_ha,
2947 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
2948 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
2949 break;
2950 case OPC_OUB_SATA_ABORT_RSP:
2951 PM8001_MSG_DBG(pm8001_ha,
2952 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
2953 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
2954 break;
2955 case OPC_OUB_SAS_DIAG_MODE_START_END:
2956 PM8001_MSG_DBG(pm8001_ha,
2957 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
2958 break;
2959 case OPC_OUB_SAS_DIAG_EXECUTE:
2960 PM8001_MSG_DBG(pm8001_ha,
2961 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
2962 break;
2963 case OPC_OUB_GET_TIME_STAMP:
2964 PM8001_MSG_DBG(pm8001_ha,
2965 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
2966 break;
2967 case OPC_OUB_SAS_HW_EVENT_ACK:
2968 PM8001_MSG_DBG(pm8001_ha,
2969 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
2970 break;
2971 case OPC_OUB_PORT_CONTROL:
2972 PM8001_MSG_DBG(pm8001_ha,
2973 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
2974 break;
2975 case OPC_OUB_SMP_ABORT_RSP:
2976 PM8001_MSG_DBG(pm8001_ha,
2977 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
2978 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
2979 break;
2980 case OPC_OUB_GET_NVMD_DATA:
2981 PM8001_MSG_DBG(pm8001_ha,
2982 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
2983 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
2984 break;
2985 case OPC_OUB_SET_NVMD_DATA:
2986 PM8001_MSG_DBG(pm8001_ha,
2987 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
2988 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
2989 break;
2990 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
2991 PM8001_MSG_DBG(pm8001_ha,
2992 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
2993 break;
2994 case OPC_OUB_SET_DEVICE_STATE:
2995 PM8001_MSG_DBG(pm8001_ha,
2996 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
2997 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
2998 break;
2999 case OPC_OUB_GET_DEVICE_STATE:
3000 PM8001_MSG_DBG(pm8001_ha,
3001 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3002 break;
3003 case OPC_OUB_SET_DEV_INFO:
3004 PM8001_MSG_DBG(pm8001_ha,
3005 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3006 break;
3007 /* spcv specifc commands */
3008 case OPC_OUB_PHY_START_RESP:
3009 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3010 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3011 mpi_phy_start_resp(pm8001_ha, piomb);
3012 break;
3013 case OPC_OUB_PHY_STOP_RESP:
3014 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3015 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3016 mpi_phy_stop_resp(pm8001_ha, piomb);
3017 break;
3018 case OPC_OUB_SET_CONTROLLER_CONFIG:
3019 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3020 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3021 mpi_set_controller_config_resp(pm8001_ha, piomb);
3022 break;
3023 case OPC_OUB_GET_CONTROLLER_CONFIG:
3024 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3025 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3026 mpi_get_controller_config_resp(pm8001_ha, piomb);
3027 break;
3028 case OPC_OUB_GET_PHY_PROFILE:
3029 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3030 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3031 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3032 break;
3033 case OPC_OUB_FLASH_OP_EXT:
3034 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3035 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3036 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3037 break;
3038 case OPC_OUB_SET_PHY_PROFILE:
3039 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3040 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3041 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3042 break;
3043 case OPC_OUB_KEK_MANAGEMENT_RESP:
3044 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3045 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3046 mpi_kek_management_resp(pm8001_ha, piomb);
3047 break;
3048 case OPC_OUB_DEK_MANAGEMENT_RESP:
3049 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3050 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3051 mpi_dek_management_resp(pm8001_ha, piomb);
3052 break;
3053 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3054 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3055 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3056 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3057 break;
3058 default:
3059 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3060 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3061 break;
3062 }
3063}
3064
3065static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3066{
3067 struct outbound_queue_table *circularQ;
3068 void *pMsg1 = NULL;
3069 u8 uninitialized_var(bc);
3070 u32 ret = MPI_IO_STATUS_FAIL;
3071 unsigned long flags;
3072
3073 spin_lock_irqsave(&pm8001_ha->lock, flags);
3074 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3075 do {
3076 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3077 if (MPI_IO_STATUS_SUCCESS == ret) {
3078 /* process the outbound message */
3079 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3080 /* free the message from the outbound circular buffer */
3081 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3082 circularQ, bc);
3083 }
3084 if (MPI_IO_STATUS_BUSY == ret) {
3085 /* Update the producer index from SPC */
3086 circularQ->producer_index =
3087 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3088 if (le32_to_cpu(circularQ->producer_index) ==
3089 circularQ->consumer_idx)
3090 /* OQ is empty */
3091 break;
3092 }
3093 } while (1);
3094 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3095 return ret;
3096}
3097
3098/* PCI_DMA_... to our direction translation. */
3099static const u8 data_dir_flags[] = {
3100 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3101 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3102 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3103 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3104};
3105
3106static void build_smp_cmd(u32 deviceID, __le32 hTag,
3107 struct smp_req *psmp_cmd, int mode, int length)
3108{
3109 psmp_cmd->tag = hTag;
3110 psmp_cmd->device_id = cpu_to_le32(deviceID);
3111 if (mode == SMP_DIRECT) {
3112 length = length - 4; /* subtract crc */
3113 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3114 } else {
3115 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3116 }
3117}
3118
3119/**
3120 * pm8001_chip_smp_req - send a SMP task to FW
3121 * @pm8001_ha: our hba card information.
3122 * @ccb: the ccb information this request used.
3123 */
3124static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3125 struct pm8001_ccb_info *ccb)
3126{
3127 int elem, rc;
3128 struct sas_task *task = ccb->task;
3129 struct domain_device *dev = task->dev;
3130 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3131 struct scatterlist *sg_req, *sg_resp;
3132 u32 req_len, resp_len;
3133 struct smp_req smp_cmd;
3134 u32 opc;
3135 struct inbound_queue_table *circularQ;
3136 char *preq_dma_addr = NULL;
3137 __le64 tmp_addr;
3138 u32 i, length;
3139
3140 memset(&smp_cmd, 0, sizeof(smp_cmd));
3141 /*
3142 * DMA-map SMP request, response buffers
3143 */
3144 sg_req = &task->smp_task.smp_req;
3145 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3146 if (!elem)
3147 return -ENOMEM;
3148 req_len = sg_dma_len(sg_req);
3149
3150 sg_resp = &task->smp_task.smp_resp;
3151 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3152 if (!elem) {
3153 rc = -ENOMEM;
3154 goto err_out;
3155 }
3156 resp_len = sg_dma_len(sg_resp);
3157 /* must be in dwords */
3158 if ((req_len & 0x3) || (resp_len & 0x3)) {
3159 rc = -EINVAL;
3160 goto err_out_2;
3161 }
3162
3163 opc = OPC_INB_SMP_REQUEST;
3164 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3165 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3166
3167 length = sg_req->length;
3168 PM8001_IO_DBG(pm8001_ha,
3169 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3170 if (!(length - 8))
3171 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3172 else
3173 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3174
3175 /* DIRECT MODE support only in spcv/ve */
3176 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3177
3178 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3179 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3180
3181 /* INDIRECT MODE command settings. Use DMA */
3182 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3183 PM8001_IO_DBG(pm8001_ha,
3184 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3185 /* for SPCv indirect mode. Place the top 4 bytes of
3186 * SMP Request header here. */
3187 for (i = 0; i < 4; i++)
3188 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3189 /* exclude top 4 bytes for SMP req header */
3190 smp_cmd.long_smp_req.long_req_addr =
3191 cpu_to_le64((u64)sg_dma_address
3192 (&task->smp_task.smp_req) - 4);
3193 /* exclude 4 bytes for SMP req header and CRC */
3194 smp_cmd.long_smp_req.long_req_size =
3195 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3196 smp_cmd.long_smp_req.long_resp_addr =
3197 cpu_to_le64((u64)sg_dma_address
3198 (&task->smp_task.smp_resp));
3199 smp_cmd.long_smp_req.long_resp_size =
3200 cpu_to_le32((u32)sg_dma_len
3201 (&task->smp_task.smp_resp)-4);
3202 } else { /* DIRECT MODE */
3203 smp_cmd.long_smp_req.long_req_addr =
3204 cpu_to_le64((u64)sg_dma_address
3205 (&task->smp_task.smp_req));
3206 smp_cmd.long_smp_req.long_req_size =
3207 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3208 smp_cmd.long_smp_req.long_resp_addr =
3209 cpu_to_le64((u64)sg_dma_address
3210 (&task->smp_task.smp_resp));
3211 smp_cmd.long_smp_req.long_resp_size =
3212 cpu_to_le32
3213 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3214 }
3215 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3216 PM8001_IO_DBG(pm8001_ha,
3217 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3218 for (i = 0; i < length; i++)
3219 if (i < 16) {
3220 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3221 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3222 "Byte[%d]:%x (DMA data:%x)\n",
3223 i, smp_cmd.smp_req16[i],
3224 *(preq_dma_addr)));
3225 } else {
3226 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3227 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3228 "Byte[%d]:%x (DMA data:%x)\n",
3229 i, smp_cmd.smp_req[i],
3230 *(preq_dma_addr)));
3231 }
3232 }
3233
3234 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3235 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3236 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
3237 return 0;
3238
3239err_out_2:
3240 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3241 PCI_DMA_FROMDEVICE);
3242err_out:
3243 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3244 PCI_DMA_TODEVICE);
3245 return rc;
3246}
3247
3248static int check_enc_sas_cmd(struct sas_task *task)
3249{
3250 if ((task->ssp_task.cdb[0] == READ_10)
3251 || (task->ssp_task.cdb[0] == WRITE_10)
3252 || (task->ssp_task.cdb[0] == WRITE_VERIFY))
3253 return 1;
3254 else
3255 return 0;
3256}
3257
3258static int check_enc_sat_cmd(struct sas_task *task)
3259{
3260 int ret = 0;
3261 switch (task->ata_task.fis.command) {
3262 case ATA_CMD_FPDMA_READ:
3263 case ATA_CMD_READ_EXT:
3264 case ATA_CMD_READ:
3265 case ATA_CMD_FPDMA_WRITE:
3266 case ATA_CMD_WRITE_EXT:
3267 case ATA_CMD_WRITE:
3268 case ATA_CMD_PIO_READ:
3269 case ATA_CMD_PIO_READ_EXT:
3270 case ATA_CMD_PIO_WRITE:
3271 case ATA_CMD_PIO_WRITE_EXT:
3272 ret = 1;
3273 break;
3274 default:
3275 ret = 0;
3276 break;
3277 }
3278 return ret;
3279}
3280
3281/**
3282 * pm80xx_chip_ssp_io_req - send a SSP task to FW
3283 * @pm8001_ha: our hba card information.
3284 * @ccb: the ccb information this request used.
3285 */
3286static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3287 struct pm8001_ccb_info *ccb)
3288{
3289 struct sas_task *task = ccb->task;
3290 struct domain_device *dev = task->dev;
3291 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3292 struct ssp_ini_io_start_req ssp_cmd;
3293 u32 tag = ccb->ccb_tag;
3294 int ret;
3295 u64 phys_addr;
3296 struct inbound_queue_table *circularQ;
3297 static u32 inb;
3298 static u32 outb;
3299 u32 opc = OPC_INB_SSPINIIOSTART;
3300 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3301 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3302 /* data address domain added for spcv; set to 0 by host,
3303 * used internally by controller
3304 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3305 */
3306 ssp_cmd.dad_dir_m_tlr =
3307 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3308 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3309 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3310 ssp_cmd.tag = cpu_to_le32(tag);
3311 if (task->ssp_task.enable_first_burst)
3312 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3313 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3314 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3315 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
3316 circularQ = &pm8001_ha->inbnd_q_tbl[inb++];
3317
3318 /* rotate the inb queue */
3319 inb = inb%PM8001_MAX_SPCV_INB_NUM;
3320
3321 /* Check if encryption is set */
3322 if (pm8001_ha->chip->encrypt &&
3323 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3324 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3325 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
3326 task->ssp_task.cdb[0]));
3327 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3328 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3329 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3330 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3331
3332 /* fill in PRD (scatter/gather) table, if any */
3333 if (task->num_scatter > 1) {
3334 pm8001_chip_make_sg(task->scatter,
3335 ccb->n_elem, ccb->buf_prd);
3336 phys_addr = ccb->ccb_dma_handle +
3337 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3338 ssp_cmd.enc_addr_low =
3339 cpu_to_le32(lower_32_bits(phys_addr));
3340 ssp_cmd.enc_addr_high =
3341 cpu_to_le32(upper_32_bits(phys_addr));
3342 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3343 } else if (task->num_scatter == 1) {
3344 u64 dma_addr = sg_dma_address(task->scatter);
3345 ssp_cmd.enc_addr_low =
3346 cpu_to_le32(lower_32_bits(dma_addr));
3347 ssp_cmd.enc_addr_high =
3348 cpu_to_le32(upper_32_bits(dma_addr));
3349 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3350 ssp_cmd.enc_esgl = 0;
3351 } else if (task->num_scatter == 0) {
3352 ssp_cmd.enc_addr_low = 0;
3353 ssp_cmd.enc_addr_high = 0;
3354 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3355 ssp_cmd.enc_esgl = 0;
3356 }
3357 /* XTS mode. All other fields are 0 */
3358 ssp_cmd.key_cmode = 0x6 << 4;
3359 /* set tweak values. Should be the start lba */
3360 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cdb[2] << 24) |
3361 (task->ssp_task.cdb[3] << 16) |
3362 (task->ssp_task.cdb[4] << 8) |
3363 (task->ssp_task.cdb[5]));
3364 } else {
3365 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3366 "Sending Normal SAS command 0x%x inb q %x\n",
3367 task->ssp_task.cdb[0], inb));
3368 /* fill in PRD (scatter/gather) table, if any */
3369 if (task->num_scatter > 1) {
3370 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
3371 ccb->buf_prd);
3372 phys_addr = ccb->ccb_dma_handle +
3373 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3374 ssp_cmd.addr_low =
3375 cpu_to_le32(lower_32_bits(phys_addr));
3376 ssp_cmd.addr_high =
3377 cpu_to_le32(upper_32_bits(phys_addr));
3378 ssp_cmd.esgl = cpu_to_le32(1<<31);
3379 } else if (task->num_scatter == 1) {
3380 u64 dma_addr = sg_dma_address(task->scatter);
3381 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
3382 ssp_cmd.addr_high =
3383 cpu_to_le32(upper_32_bits(dma_addr));
3384 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3385 ssp_cmd.esgl = 0;
3386 } else if (task->num_scatter == 0) {
3387 ssp_cmd.addr_low = 0;
3388 ssp_cmd.addr_high = 0;
3389 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3390 ssp_cmd.esgl = 0;
3391 }
3392 }
3393 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, outb++);
3394
3395 /* rotate the outb queue */
3396 outb = outb%PM8001_MAX_SPCV_OUTB_NUM;
3397
3398 return ret;
3399}
3400
3401static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3402 struct pm8001_ccb_info *ccb)
3403{
3404 struct sas_task *task = ccb->task;
3405 struct domain_device *dev = task->dev;
3406 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3407 u32 tag = ccb->ccb_tag;
3408 int ret;
3409 static u32 inb;
3410 static u32 outb;
3411 struct sata_start_req sata_cmd;
3412 u32 hdr_tag, ncg_tag = 0;
3413 u64 phys_addr;
3414 u32 ATAP = 0x0;
3415 u32 dir;
3416 struct inbound_queue_table *circularQ;
3417 u32 opc = OPC_INB_SATA_HOST_OPSTART;
3418 memset(&sata_cmd, 0, sizeof(sata_cmd));
3419 circularQ = &pm8001_ha->inbnd_q_tbl[inb++];
3420
3421 /* rotate the inb queue */
3422 inb = inb%PM8001_MAX_SPCV_INB_NUM;
3423
3424 if (task->data_dir == PCI_DMA_NONE) {
3425 ATAP = 0x04; /* no data*/
3426 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
3427 } else if (likely(!task->ata_task.device_control_reg_update)) {
3428 if (task->ata_task.dma_xfer) {
3429 ATAP = 0x06; /* DMA */
3430 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
3431 } else {
3432 ATAP = 0x05; /* PIO*/
3433 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
3434 }
3435 if (task->ata_task.use_ncq &&
3436 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3437 ATAP = 0x07; /* FPDMA */
3438 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
3439 }
3440 }
3441 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
3442 ncg_tag = hdr_tag;
3443 dir = data_dir_flags[task->data_dir] << 8;
3444 sata_cmd.tag = cpu_to_le32(tag);
3445 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3446 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3447
3448 sata_cmd.sata_fis = task->ata_task.fis;
3449 if (likely(!task->ata_task.device_control_reg_update))
3450 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3451 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3452
3453 /* Check if encryption is set */
3454 if (pm8001_ha->chip->encrypt &&
3455 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
3456 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3457 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
3458 sata_cmd.sata_fis.command));
3459 opc = OPC_INB_SATA_DIF_ENC_IO;
3460
3461 /* set encryption bit */
3462 sata_cmd.ncqtag_atap_dir_m_dad =
3463 cpu_to_le32(((ncg_tag & 0xff)<<16)|
3464 ((ATAP & 0x3f) << 10) | 0x20 | dir);
3465 /* dad (bit 0-1) is 0 */
3466 /* fill in PRD (scatter/gather) table, if any */
3467 if (task->num_scatter > 1) {
3468 pm8001_chip_make_sg(task->scatter,
3469 ccb->n_elem, ccb->buf_prd);
3470 phys_addr = ccb->ccb_dma_handle +
3471 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3472 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
3473 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
3474 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
3475 } else if (task->num_scatter == 1) {
3476 u64 dma_addr = sg_dma_address(task->scatter);
3477 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
3478 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
3479 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3480 sata_cmd.enc_esgl = 0;
3481 } else if (task->num_scatter == 0) {
3482 sata_cmd.enc_addr_low = 0;
3483 sata_cmd.enc_addr_high = 0;
3484 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3485 sata_cmd.enc_esgl = 0;
3486 }
3487 /* XTS mode. All other fields are 0 */
3488 sata_cmd.key_index_mode = 0x6 << 4;
3489 /* set tweak values. Should be the start lba */
3490 sata_cmd.twk_val0 =
3491 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
3492 (sata_cmd.sata_fis.lbah << 16) |
3493 (sata_cmd.sata_fis.lbam << 8) |
3494 (sata_cmd.sata_fis.lbal));
3495 sata_cmd.twk_val1 =
3496 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
3497 (sata_cmd.sata_fis.lbam_exp));
3498 } else {
3499 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3500 "Sending Normal SATA command 0x%x inb %x\n",
3501 sata_cmd.sata_fis.command, inb));
3502 /* dad (bit 0-1) is 0 */
3503 sata_cmd.ncqtag_atap_dir_m_dad =
3504 cpu_to_le32(((ncg_tag & 0xff)<<16) |
3505 ((ATAP & 0x3f) << 10) | dir);
3506
3507 /* fill in PRD (scatter/gather) table, if any */
3508 if (task->num_scatter > 1) {
3509 pm8001_chip_make_sg(task->scatter,
3510 ccb->n_elem, ccb->buf_prd);
3511 phys_addr = ccb->ccb_dma_handle +
3512 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3513 sata_cmd.addr_low = lower_32_bits(phys_addr);
3514 sata_cmd.addr_high = upper_32_bits(phys_addr);
3515 sata_cmd.esgl = cpu_to_le32(1 << 31);
3516 } else if (task->num_scatter == 1) {
3517 u64 dma_addr = sg_dma_address(task->scatter);
3518 sata_cmd.addr_low = lower_32_bits(dma_addr);
3519 sata_cmd.addr_high = upper_32_bits(dma_addr);
3520 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3521 sata_cmd.esgl = 0;
3522 } else if (task->num_scatter == 0) {
3523 sata_cmd.addr_low = 0;
3524 sata_cmd.addr_high = 0;
3525 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3526 sata_cmd.esgl = 0;
3527 }
3528 /* scsi cdb */
3529 sata_cmd.atapi_scsi_cdb[0] =
3530 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
3531 (task->ata_task.atapi_packet[1] << 8) |
3532 (task->ata_task.atapi_packet[2] << 16) |
3533 (task->ata_task.atapi_packet[3] << 24)));
3534 sata_cmd.atapi_scsi_cdb[1] =
3535 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
3536 (task->ata_task.atapi_packet[5] << 8) |
3537 (task->ata_task.atapi_packet[6] << 16) |
3538 (task->ata_task.atapi_packet[7] << 24)));
3539 sata_cmd.atapi_scsi_cdb[2] =
3540 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
3541 (task->ata_task.atapi_packet[9] << 8) |
3542 (task->ata_task.atapi_packet[10] << 16) |
3543 (task->ata_task.atapi_packet[11] << 24)));
3544 sata_cmd.atapi_scsi_cdb[3] =
3545 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
3546 (task->ata_task.atapi_packet[13] << 8) |
3547 (task->ata_task.atapi_packet[14] << 16) |
3548 (task->ata_task.atapi_packet[15] << 24)));
3549 }
3550 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
3551 &sata_cmd, outb++);
3552
3553 /* rotate the outb queue */
3554 outb = outb%PM8001_MAX_SPCV_OUTB_NUM;
3555 return ret;
3556}
3557
3558/**
3559 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
3560 * @pm8001_ha: our hba card information.
3561 * @num: the inbound queue number
3562 * @phy_id: the phy id which we wanted to start up.
3563 */
3564static int
3565pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
3566{
3567 struct phy_start_req payload;
3568 struct inbound_queue_table *circularQ;
3569 int ret;
3570 u32 tag = 0x01;
3571 u32 opcode = OPC_INB_PHYSTART;
3572 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3573 memset(&payload, 0, sizeof(payload));
3574 payload.tag = cpu_to_le32(tag);
3575
3576 PM8001_INIT_DBG(pm8001_ha,
3577 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
3578 /*
3579 ** [0:7] PHY Identifier
3580 ** [8:11] link rate 1.5G, 3G, 6G
3581 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
3582 ** [14] 0b disable spin up hold; 1b enable spin up hold
3583 ** [15] ob no change in current PHY analig setup 1b enable using SPAST
3584 */
3585 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
3586 LINKMODE_AUTO | LINKRATE_15 |
3587 LINKRATE_30 | LINKRATE_60 | phy_id);
3588 /* SSC Disable and SAS Analog ST configuration */
3589 /**
3590 payload.ase_sh_lm_slr_phyid =
3591 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
3592 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
3593 phy_id);
3594 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
3595 **/
3596
3597 payload.sas_identify.dev_type = SAS_END_DEV;
3598 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
3599 memcpy(payload.sas_identify.sas_addr,
3600 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
3601 payload.sas_identify.phy_id = phy_id;
3602 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
3603 return ret;
3604}
3605
3606/**
3607 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
3608 * @pm8001_ha: our hba card information.
3609 * @num: the inbound queue number
3610 * @phy_id: the phy id which we wanted to start up.
3611 */
3612static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
3613 u8 phy_id)
3614{
3615 struct phy_stop_req payload;
3616 struct inbound_queue_table *circularQ;
3617 int ret;
3618 u32 tag = 0x01;
3619 u32 opcode = OPC_INB_PHYSTOP;
3620 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3621 memset(&payload, 0, sizeof(payload));
3622 payload.tag = cpu_to_le32(tag);
3623 payload.phy_id = cpu_to_le32(phy_id);
3624 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
3625 return ret;
3626}
3627
3628/**
3629 * see comments on pm8001_mpi_reg_resp.
3630 */
3631static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
3632 struct pm8001_device *pm8001_dev, u32 flag)
3633{
3634 struct reg_dev_req payload;
3635 u32 opc;
3636 u32 stp_sspsmp_sata = 0x4;
3637 struct inbound_queue_table *circularQ;
3638 u32 linkrate, phy_id;
3639 int rc, tag = 0xdeadbeef;
3640 struct pm8001_ccb_info *ccb;
3641 u8 retryFlag = 0x1;
3642 u16 firstBurstSize = 0;
3643 u16 ITNT = 2000;
3644 struct domain_device *dev = pm8001_dev->sas_device;
3645 struct domain_device *parent_dev = dev->parent;
3646 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3647
3648 memset(&payload, 0, sizeof(payload));
3649 rc = pm8001_tag_alloc(pm8001_ha, &tag);
3650 if (rc)
3651 return rc;
3652 ccb = &pm8001_ha->ccb_info[tag];
3653 ccb->device = pm8001_dev;
3654 ccb->ccb_tag = tag;
3655 payload.tag = cpu_to_le32(tag);
3656
3657 if (flag == 1) {
3658 stp_sspsmp_sata = 0x02; /*direct attached sata */
3659 } else {
3660 if (pm8001_dev->dev_type == SATA_DEV)
3661 stp_sspsmp_sata = 0x00; /* stp*/
3662 else if (pm8001_dev->dev_type == SAS_END_DEV ||
3663 pm8001_dev->dev_type == EDGE_DEV ||
3664 pm8001_dev->dev_type == FANOUT_DEV)
3665 stp_sspsmp_sata = 0x01; /*ssp or smp*/
3666 }
3667 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
3668 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
3669 else
3670 phy_id = pm8001_dev->attached_phy;
3671
3672 opc = OPC_INB_REG_DEV;
3673
3674 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
3675 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
3676
3677 payload.phyid_portid =
3678 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
3679 ((phy_id & 0xFF) << 8));
3680
3681 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
3682 ((linkrate & 0x0F) << 24) |
3683 ((stp_sspsmp_sata & 0x03) << 28));
3684 payload.firstburstsize_ITNexustimeout =
3685 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
3686
3687 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
3688 SAS_ADDR_SIZE);
3689
3690 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
3691
3692 return rc;
3693}
3694
3695/**
3696 * pm80xx_chip_phy_ctl_req - support the local phy operation
3697 * @pm8001_ha: our hba card information.
3698 * @num: the inbound queue number
3699 * @phy_id: the phy id which we wanted to operate
3700 * @phy_op:
3701 */
3702static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3703 u32 phyId, u32 phy_op)
3704{
3705 struct local_phy_ctl_req payload;
3706 struct inbound_queue_table *circularQ;
3707 int ret;
3708 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
3709 memset(&payload, 0, sizeof(payload));
3710 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3711 payload.tag = cpu_to_le32(1);
3712 payload.phyop_phyid =
3713 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
3714 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
3715 return ret;
3716}
3717
3718static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
3719{
3720 u32 value;
3721#ifdef PM8001_USE_MSIX
3722 return 1;
3723#endif
3724 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
3725 if (value)
3726 return 1;
3727 return 0;
3728
3729}
3730
3731/**
3732 * pm8001_chip_isr - PM8001 isr handler.
3733 * @pm8001_ha: our hba card information.
3734 * @irq: irq number.
3735 * @stat: stat.
3736 */
3737static irqreturn_t
3738pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
3739{
3740 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
3741 process_oq(pm8001_ha, vec);
3742 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
3743 return IRQ_HANDLED;
3744}
3745
3746const struct pm8001_dispatch pm8001_80xx_dispatch = {
3747 .name = "pmc80xx",
3748 .chip_init = pm80xx_chip_init,
3749 .chip_soft_rst = pm80xx_chip_soft_rst,
3750 .chip_rst = pm80xx_hw_chip_rst,
3751 .chip_iounmap = pm8001_chip_iounmap,
3752 .isr = pm80xx_chip_isr,
3753 .is_our_interupt = pm80xx_chip_is_our_interupt,
3754 .isr_process_oq = process_oq,
3755 .interrupt_enable = pm80xx_chip_interrupt_enable,
3756 .interrupt_disable = pm80xx_chip_interrupt_disable,
3757 .make_prd = pm8001_chip_make_sg,
3758 .smp_req = pm80xx_chip_smp_req,
3759 .ssp_io_req = pm80xx_chip_ssp_io_req,
3760 .sata_req = pm80xx_chip_sata_req,
3761 .phy_start_req = pm80xx_chip_phy_start_req,
3762 .phy_stop_req = pm80xx_chip_phy_stop_req,
3763 .reg_dev_req = pm80xx_chip_reg_dev_req,
3764 .dereg_dev_req = pm8001_chip_dereg_dev_req,
3765 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
3766 .task_abort = pm8001_chip_abort_task,
3767 .ssp_tm_req = pm8001_chip_ssp_tm_req,
3768 .get_nvmd_req = pm8001_chip_get_nvmd_req,
3769 .set_nvmd_req = pm8001_chip_set_nvmd_req,
3770 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
3771 .set_dev_state_req = pm8001_chip_set_dev_state_req,
3772};
diff --git a/drivers/scsi/pm8001/pm80xx_hwi.h b/drivers/scsi/pm8001/pm80xx_hwi.h
new file mode 100644
index 000000000000..e281d71f897a
--- /dev/null
+++ b/drivers/scsi/pm8001/pm80xx_hwi.h
@@ -0,0 +1,1480 @@
1/*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41#ifndef _PMC8001_REG_H_
42#define _PMC8001_REG_H_
43
44#include <linux/types.h>
45#include <scsi/libsas.h>
46
47/* for Request Opcode of IOMB */
48#define OPC_INB_ECHO 1 /* 0x000 */
49#define OPC_INB_PHYSTART 4 /* 0x004 */
50#define OPC_INB_PHYSTOP 5 /* 0x005 */
51#define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52#define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53/* 0x8 RESV IN SPCv */
54#define OPC_INB_RSVD 8 /* 0x008 */
55#define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
56#define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
57#define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
58/* 0xC, 0xD, 0xE removed in SPCv */
59#define OPC_INB_SSP_ABORT 15 /* 0x00F */
60#define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
61#define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
62#define OPC_INB_SMP_REQUEST 18 /* 0x012 */
63/* 0x13 SMP_RESPONSE is removed in SPCv */
64#define OPC_INB_SMP_ABORT 20 /* 0x014 */
65/* 0x16 RESV IN SPCv */
66#define OPC_INB_RSVD1 22 /* 0x016 */
67#define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
68#define OPC_INB_SATA_ABORT 24 /* 0x018 */
69#define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
70/* 0x1A RESV IN SPCv */
71#define OPC_INB_RSVD2 26 /* 0x01A */
72#define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
73#define OPC_INB_GPIO 34 /* 0x022 */
74#define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
75#define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
76/* 0x25 RESV IN SPCv */
77#define OPC_INB_RSVD3 37 /* 0x025 */
78#define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
79#define OPC_INB_PORT_CONTROL 39 /* 0x027 */
80#define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
81#define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
82#define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
83#define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
84#define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
85/* 0x2D RESV IN SPCv */
86#define OPC_INB_RSVD4 45 /* 0x02D */
87#define OPC_INB_SGPIO_REGISTER 46 /* 0x02E */
88#define OPC_INB_PCIE_DIAG_EXEC 47 /* 0x02F */
89#define OPC_INB_SET_CONTROLLER_CONFIG 48 /* 0x030 */
90#define OPC_INB_GET_CONTROLLER_CONFIG 49 /* 0x031 */
91#define OPC_INB_REG_DEV 50 /* 0x032 */
92#define OPC_INB_SAS_HW_EVENT_ACK 51 /* 0x033 */
93#define OPC_INB_GET_DEVICE_INFO 52 /* 0x034 */
94#define OPC_INB_GET_PHY_PROFILE 53 /* 0x035 */
95#define OPC_INB_FLASH_OP_EXT 54 /* 0x036 */
96#define OPC_INB_SET_PHY_PROFILE 55 /* 0x037 */
97#define OPC_INB_KEK_MANAGEMENT 256 /* 0x100 */
98#define OPC_INB_DEK_MANAGEMENT 257 /* 0x101 */
99#define OPC_INB_SSP_INI_DIF_ENC_IO 258 /* 0x102 */
100#define OPC_INB_SATA_DIF_ENC_IO 259 /* 0x103 */
101
102/* for Response Opcode of IOMB */
103#define OPC_OUB_ECHO 1 /* 0x001 */
104#define OPC_OUB_RSVD 4 /* 0x004 */
105#define OPC_OUB_SSP_COMP 5 /* 0x005 */
106#define OPC_OUB_SMP_COMP 6 /* 0x006 */
107#define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
108#define OPC_OUB_RSVD1 10 /* 0x00A */
109#define OPC_OUB_DEREG_DEV 11 /* 0x00B */
110#define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
111#define OPC_OUB_SATA_COMP 13 /* 0x00D */
112#define OPC_OUB_SATA_EVENT 14 /* 0x00E */
113#define OPC_OUB_SSP_EVENT 15 /* 0x00F */
114#define OPC_OUB_RSVD2 16 /* 0x010 */
115/* 0x11 - SMP_RECEIVED Notification removed in SPCv*/
116#define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
117#define OPC_OUB_RSVD3 19 /* 0x013 */
118#define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
119#define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
120#define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
121#define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
122#define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
123#define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
124#define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
125#define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
126#define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
127#define OPC_OUB_RSVD4 31 /* 0x01F */
128#define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
129#define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
130#define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
131#define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
132#define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
133#define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
134#define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
135#define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
136#define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
137#define OPC_OUB_RSVD5 41 /* 0x029 */
138#define OPC_OUB_HW_EVENT 1792 /* 0x700 */
139#define OPC_OUB_DEV_HANDLE_ARRIV 1824 /* 0x720 */
140#define OPC_OUB_THERM_HW_EVENT 1840 /* 0x730 */
141#define OPC_OUB_SGPIO_RESP 2094 /* 0x82E */
142#define OPC_OUB_PCIE_DIAG_EXECUTE 2095 /* 0x82F */
143#define OPC_OUB_DEV_REGIST 2098 /* 0x832 */
144#define OPC_OUB_SAS_HW_EVENT_ACK 2099 /* 0x833 */
145#define OPC_OUB_GET_DEVICE_INFO 2100 /* 0x834 */
146/* spcv specific commands */
147#define OPC_OUB_PHY_START_RESP 2052 /* 0x804 */
148#define OPC_OUB_PHY_STOP_RESP 2053 /* 0x805 */
149#define OPC_OUB_SET_CONTROLLER_CONFIG 2096 /* 0x830 */
150#define OPC_OUB_GET_CONTROLLER_CONFIG 2097 /* 0x831 */
151#define OPC_OUB_GET_PHY_PROFILE 2101 /* 0x835 */
152#define OPC_OUB_FLASH_OP_EXT 2102 /* 0x836 */
153#define OPC_OUB_SET_PHY_PROFILE 2103 /* 0x837 */
154#define OPC_OUB_KEK_MANAGEMENT_RESP 2304 /* 0x900 */
155#define OPC_OUB_DEK_MANAGEMENT_RESP 2305 /* 0x901 */
156#define OPC_OUB_SSP_COALESCED_COMP_RESP 2306 /* 0x902 */
157
158/* for phy start*/
159#define SSC_DISABLE_15 (0x01 << 16)
160#define SSC_DISABLE_30 (0x02 << 16)
161#define SSC_DISABLE_60 (0x04 << 16)
162#define SAS_ASE (0x01 << 15)
163#define SPINHOLD_DISABLE (0x00 << 14)
164#define SPINHOLD_ENABLE (0x01 << 14)
165#define LINKMODE_SAS (0x01 << 12)
166#define LINKMODE_DSATA (0x02 << 12)
167#define LINKMODE_AUTO (0x03 << 12)
168#define LINKRATE_15 (0x01 << 8)
169#define LINKRATE_30 (0x02 << 8)
170#define LINKRATE_60 (0x06 << 8)
171
172/* Thermal related */
173#define THERMAL_ENABLE 0x1
174#define THERMAL_LOG_ENABLE 0x1
175#define THERMAL_OP_CODE 0x6
176#define LTEMPHIL 70
177#define RTEMPHIL 100
178
179/* Encryption info */
180#define SCRATCH_PAD3_ENC_DISABLED 0x00000000
181#define SCRATCH_PAD3_ENC_DIS_ERR 0x00000001
182#define SCRATCH_PAD3_ENC_ENA_ERR 0x00000002
183#define SCRATCH_PAD3_ENC_READY 0x00000003
184#define SCRATCH_PAD3_ENC_MASK SCRATCH_PAD3_ENC_READY
185
186#define SCRATCH_PAD3_XTS_ENABLED (1 << 14)
187#define SCRATCH_PAD3_SMA_ENABLED (1 << 4)
188#define SCRATCH_PAD3_SMB_ENABLED (1 << 5)
189#define SCRATCH_PAD3_SMF_ENABLED 0
190#define SCRATCH_PAD3_SM_MASK 0x000000F0
191#define SCRATCH_PAD3_ERR_CODE 0x00FF0000
192
193#define SEC_MODE_SMF 0x0
194#define SEC_MODE_SMA 0x100
195#define SEC_MODE_SMB 0x200
196#define CIPHER_MODE_ECB 0x00000001
197#define CIPHER_MODE_XTS 0x00000002
198#define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4
199
200struct mpi_msg_hdr {
201 __le32 header; /* Bits [11:0] - Message operation code */
202 /* Bits [15:12] - Message Category */
203 /* Bits [21:16] - Outboundqueue ID for the
204 operation completion message */
205 /* Bits [23:22] - Reserved */
206 /* Bits [28:24] - Buffer Count, indicates how
207 many buffer are allocated for the massage */
208 /* Bits [30:29] - Reserved */
209 /* Bits [31] - Message Valid bit */
210} __attribute__((packed, aligned(4)));
211
212/*
213 * brief the data structure of PHY Start Command
214 * use to describe enable the phy (128 bytes)
215 */
216struct phy_start_req {
217 __le32 tag;
218 __le32 ase_sh_lm_slr_phyid;
219 struct sas_identify_frame sas_identify; /* 28 Bytes */
220 __le32 spasti;
221 u32 reserved[21];
222} __attribute__((packed, aligned(4)));
223
224/*
225 * brief the data structure of PHY Start Command
226 * use to disable the phy (128 bytes)
227 */
228struct phy_stop_req {
229 __le32 tag;
230 __le32 phy_id;
231 u32 reserved[29];
232} __attribute__((packed, aligned(4)));
233
234/* set device bits fis - device to host */
235struct set_dev_bits_fis {
236 u8 fis_type; /* 0xA1*/
237 u8 n_i_pmport;
238 /* b7 : n Bit. Notification bit. If set device needs attention. */
239 /* b6 : i Bit. Interrupt Bit */
240 /* b5-b4: reserved2 */
241 /* b3-b0: PM Port */
242 u8 status;
243 u8 error;
244 u32 _r_a;
245} __attribute__ ((packed));
246/* PIO setup FIS - device to host */
247struct pio_setup_fis {
248 u8 fis_type; /* 0x5f */
249 u8 i_d_pmPort;
250 /* b7 : reserved */
251 /* b6 : i bit. Interrupt bit */
252 /* b5 : d bit. data transfer direction. set to 1 for device to host
253 xfer */
254 /* b4 : reserved */
255 /* b3-b0: PM Port */
256 u8 status;
257 u8 error;
258 u8 lbal;
259 u8 lbam;
260 u8 lbah;
261 u8 device;
262 u8 lbal_exp;
263 u8 lbam_exp;
264 u8 lbah_exp;
265 u8 _r_a;
266 u8 sector_count;
267 u8 sector_count_exp;
268 u8 _r_b;
269 u8 e_status;
270 u8 _r_c[2];
271 u8 transfer_count;
272} __attribute__ ((packed));
273
274/*
275 * brief the data structure of SATA Completion Response
276 * use to describe the sata task response (64 bytes)
277 */
278struct sata_completion_resp {
279 __le32 tag;
280 __le32 status;
281 __le32 param;
282 u32 sata_resp[12];
283} __attribute__((packed, aligned(4)));
284
285/*
286 * brief the data structure of SAS HW Event Notification
287 * use to alert the host about the hardware event(64 bytes)
288 */
289/* updated outbound struct for spcv */
290
291struct hw_event_resp {
292 __le32 lr_status_evt_portid;
293 __le32 evt_param;
294 __le32 phyid_npip_portstate;
295 struct sas_identify_frame sas_identify;
296 struct dev_to_host_fis sata_fis;
297} __attribute__((packed, aligned(4)));
298
299/*
300 * brief the data structure for thermal event notification
301 */
302
303struct thermal_hw_event {
304 __le32 thermal_event;
305 __le32 rht_lht;
306} __attribute__((packed, aligned(4)));
307
308/*
309 * brief the data structure of REGISTER DEVICE Command
310 * use to describe MPI REGISTER DEVICE Command (64 bytes)
311 */
312
313struct reg_dev_req {
314 __le32 tag;
315 __le32 phyid_portid;
316 __le32 dtype_dlr_mcn_ir_retry;
317 __le32 firstburstsize_ITNexustimeout;
318 u8 sas_addr[SAS_ADDR_SIZE];
319 __le32 upper_device_id;
320 u32 reserved[24];
321} __attribute__((packed, aligned(4)));
322
323/*
324 * brief the data structure of DEREGISTER DEVICE Command
325 * use to request spc to remove all internal resources associated
326 * with the device id (64 bytes)
327 */
328
329struct dereg_dev_req {
330 __le32 tag;
331 __le32 device_id;
332 u32 reserved[29];
333} __attribute__((packed, aligned(4)));
334
335/*
336 * brief the data structure of DEVICE_REGISTRATION Response
337 * use to notify the completion of the device registration (64 bytes)
338 */
339struct dev_reg_resp {
340 __le32 tag;
341 __le32 status;
342 __le32 device_id;
343 u32 reserved[12];
344} __attribute__((packed, aligned(4)));
345
346/*
347 * brief the data structure of Local PHY Control Command
348 * use to issue PHY CONTROL to local phy (64 bytes)
349 */
350struct local_phy_ctl_req {
351 __le32 tag;
352 __le32 phyop_phyid;
353 u32 reserved1[29];
354} __attribute__((packed, aligned(4)));
355
356/**
357 * brief the data structure of Local Phy Control Response
358 * use to describe MPI Local Phy Control Response (64 bytes)
359 */
360 struct local_phy_ctl_resp {
361 __le32 tag;
362 __le32 phyop_phyid;
363 __le32 status;
364 u32 reserved[12];
365} __attribute__((packed, aligned(4)));
366
367#define OP_BITS 0x0000FF00
368#define ID_BITS 0x000000FF
369
370/*
371 * brief the data structure of PORT Control Command
372 * use to control port properties (64 bytes)
373 */
374
375struct port_ctl_req {
376 __le32 tag;
377 __le32 portop_portid;
378 __le32 param0;
379 __le32 param1;
380 u32 reserved1[27];
381} __attribute__((packed, aligned(4)));
382
383/*
384 * brief the data structure of HW Event Ack Command
385 * use to acknowledge receive HW event (64 bytes)
386 */
387struct hw_event_ack_req {
388 __le32 tag;
389 __le32 phyid_sea_portid;
390 __le32 param0;
391 __le32 param1;
392 u32 reserved1[27];
393} __attribute__((packed, aligned(4)));
394
395/*
396 * brief the data structure of PHY_START Response Command
397 * indicates the completion of PHY_START command (64 bytes)
398 */
399struct phy_start_resp {
400 __le32 tag;
401 __le32 status;
402 __le32 phyid;
403 u32 reserved[12];
404} __attribute__((packed, aligned(4)));
405
406/*
407 * brief the data structure of PHY_STOP Response Command
408 * indicates the completion of PHY_STOP command (64 bytes)
409 */
410struct phy_stop_resp {
411 __le32 tag;
412 __le32 status;
413 __le32 phyid;
414 u32 reserved[12];
415} __attribute__((packed, aligned(4)));
416
417/*
418 * brief the data structure of SSP Completion Response
419 * use to indicate a SSP Completion (n bytes)
420 */
421struct ssp_completion_resp {
422 __le32 tag;
423 __le32 status;
424 __le32 param;
425 __le32 ssptag_rescv_rescpad;
426 struct ssp_response_iu ssp_resp_iu;
427 __le32 residual_count;
428} __attribute__((packed, aligned(4)));
429
430#define SSP_RESCV_BIT 0x00010000
431
432/*
433 * brief the data structure of SATA EVNET response
434 * use to indicate a SATA Completion (64 bytes)
435 */
436struct sata_event_resp {
437 __le32 tag;
438 __le32 event;
439 __le32 port_id;
440 __le32 device_id;
441 u32 reserved;
442 __le32 event_param0;
443 __le32 event_param1;
444 __le32 sata_addr_h32;
445 __le32 sata_addr_l32;
446 __le32 e_udt1_udt0_crc;
447 __le32 e_udt5_udt4_udt3_udt2;
448 __le32 a_udt1_udt0_crc;
449 __le32 a_udt5_udt4_udt3_udt2;
450 __le32 hwdevid_diferr;
451 __le32 err_framelen_byteoffset;
452 __le32 err_dataframe;
453} __attribute__((packed, aligned(4)));
454
455/*
456 * brief the data structure of SSP EVNET esponse
457 * use to indicate a SSP Completion (64 bytes)
458 */
459struct ssp_event_resp {
460 __le32 tag;
461 __le32 event;
462 __le32 port_id;
463 __le32 device_id;
464 __le32 ssp_tag;
465 __le32 event_param0;
466 __le32 event_param1;
467 __le32 sas_addr_h32;
468 __le32 sas_addr_l32;
469 __le32 e_udt1_udt0_crc;
470 __le32 e_udt5_udt4_udt3_udt2;
471 __le32 a_udt1_udt0_crc;
472 __le32 a_udt5_udt4_udt3_udt2;
473 __le32 hwdevid_diferr;
474 __le32 err_framelen_byteoffset;
475 __le32 err_dataframe;
476} __attribute__((packed, aligned(4)));
477
478/**
479 * brief the data structure of General Event Notification Response
480 * use to describe MPI General Event Notification Response (64 bytes)
481 */
482struct general_event_resp {
483 __le32 status;
484 __le32 inb_IOMB_payload[14];
485} __attribute__((packed, aligned(4)));
486
487#define GENERAL_EVENT_PAYLOAD 14
488#define OPCODE_BITS 0x00000fff
489
490/*
491 * brief the data structure of SMP Request Command
492 * use to describe MPI SMP REQUEST Command (64 bytes)
493 */
494struct smp_req {
495 __le32 tag;
496 __le32 device_id;
497 __le32 len_ip_ir;
498 /* Bits [0] - Indirect response */
499 /* Bits [1] - Indirect Payload */
500 /* Bits [15:2] - Reserved */
501 /* Bits [23:16] - direct payload Len */
502 /* Bits [31:24] - Reserved */
503 u8 smp_req16[16];
504 union {
505 u8 smp_req[32];
506 struct {
507 __le64 long_req_addr;/* sg dma address, LE */
508 __le32 long_req_size;/* LE */
509 u32 _r_a;
510 __le64 long_resp_addr;/* sg dma address, LE */
511 __le32 long_resp_size;/* LE */
512 u32 _r_b;
513 } long_smp_req;/* sequencer extension */
514 };
515 __le32 rsvd[16];
516} __attribute__((packed, aligned(4)));
517/*
518 * brief the data structure of SMP Completion Response
519 * use to describe MPI SMP Completion Response (64 bytes)
520 */
521struct smp_completion_resp {
522 __le32 tag;
523 __le32 status;
524 __le32 param;
525 u8 _r_a[252];
526} __attribute__((packed, aligned(4)));
527
528/*
529 *brief the data structure of SSP SMP SATA Abort Command
530 * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
531 */
532struct task_abort_req {
533 __le32 tag;
534 __le32 device_id;
535 __le32 tag_to_abort;
536 __le32 abort_all;
537 u32 reserved[27];
538} __attribute__((packed, aligned(4)));
539
540/* These flags used for SSP SMP & SATA Abort */
541#define ABORT_MASK 0x3
542#define ABORT_SINGLE 0x0
543#define ABORT_ALL 0x1
544
545/**
546 * brief the data structure of SSP SATA SMP Abort Response
547 * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
548 */
549struct task_abort_resp {
550 __le32 tag;
551 __le32 status;
552 __le32 scp;
553 u32 reserved[12];
554} __attribute__((packed, aligned(4)));
555
556/**
557 * brief the data structure of SAS Diagnostic Start/End Command
558 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
559 */
560struct sas_diag_start_end_req {
561 __le32 tag;
562 __le32 operation_phyid;
563 u32 reserved[29];
564} __attribute__((packed, aligned(4)));
565
566/**
567 * brief the data structure of SAS Diagnostic Execute Command
568 * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
569 */
570struct sas_diag_execute_req {
571 __le32 tag;
572 __le32 cmdtype_cmddesc_phyid;
573 __le32 pat1_pat2;
574 __le32 threshold;
575 __le32 codepat_errmsk;
576 __le32 pmon;
577 __le32 pERF1CTL;
578 u32 reserved[24];
579} __attribute__((packed, aligned(4)));
580
581#define SAS_DIAG_PARAM_BYTES 24
582
583/*
584 * brief the data structure of Set Device State Command
585 * use to describe MPI Set Device State Command (64 bytes)
586 */
587struct set_dev_state_req {
588 __le32 tag;
589 __le32 device_id;
590 __le32 nds;
591 u32 reserved[28];
592} __attribute__((packed, aligned(4)));
593
594/*
595 * brief the data structure of SATA Start Command
596 * use to describe MPI SATA IO Start Command (64 bytes)
597 * Note: This structure is common for normal / encryption I/O
598 */
599
600struct sata_start_req {
601 __le32 tag;
602 __le32 device_id;
603 __le32 data_len;
604 __le32 ncqtag_atap_dir_m_dad;
605 struct host_to_dev_fis sata_fis;
606 u32 reserved1;
607 u32 reserved2; /* dword 11. rsvd for normal I/O. */
608 /* EPLE Descl for enc I/O */
609 u32 addr_low; /* dword 12. rsvd for enc I/O */
610 u32 addr_high; /* dword 13. reserved for enc I/O */
611 __le32 len; /* dword 14: length for normal I/O. */
612 /* EPLE Desch for enc I/O */
613 __le32 esgl; /* dword 15. rsvd for enc I/O */
614 __le32 atapi_scsi_cdb[4]; /* dword 16-19. rsvd for enc I/O */
615 /* The below fields are reserved for normal I/O */
616 __le32 key_index_mode; /* dword 20 */
617 __le32 sector_cnt_enss;/* dword 21 */
618 __le32 keytagl; /* dword 22 */
619 __le32 keytagh; /* dword 23 */
620 __le32 twk_val0; /* dword 24 */
621 __le32 twk_val1; /* dword 25 */
622 __le32 twk_val2; /* dword 26 */
623 __le32 twk_val3; /* dword 27 */
624 __le32 enc_addr_low; /* dword 28. Encryption SGL address high */
625 __le32 enc_addr_high; /* dword 29. Encryption SGL address low */
626 __le32 enc_len; /* dword 30. Encryption length */
627 __le32 enc_esgl; /* dword 31. Encryption esgl bit */
628} __attribute__((packed, aligned(4)));
629
630/**
631 * brief the data structure of SSP INI TM Start Command
632 * use to describe MPI SSP INI TM Start Command (64 bytes)
633 */
634struct ssp_ini_tm_start_req {
635 __le32 tag;
636 __le32 device_id;
637 __le32 relate_tag;
638 __le32 tmf;
639 u8 lun[8];
640 __le32 ds_ads_m;
641 u32 reserved[24];
642} __attribute__((packed, aligned(4)));
643
644struct ssp_info_unit {
645 u8 lun[8];/* SCSI Logical Unit Number */
646 u8 reserved1;/* reserved */
647 u8 efb_prio_attr;
648 /* B7 : enabledFirstBurst */
649 /* B6-3 : taskPriority */
650 /* B2-0 : taskAttribute */
651 u8 reserved2; /* reserved */
652 u8 additional_cdb_len;
653 /* B7-2 : additional_cdb_len */
654 /* B1-0 : reserved */
655 u8 cdb[16];/* The SCSI CDB up to 16 bytes length */
656} __attribute__((packed, aligned(4)));
657
658/**
659 * brief the data structure of SSP INI IO Start Command
660 * use to describe MPI SSP INI IO Start Command (64 bytes)
661 * Note: This structure is common for normal / encryption I/O
662 */
663struct ssp_ini_io_start_req {
664 __le32 tag;
665 __le32 device_id;
666 __le32 data_len;
667 __le32 dad_dir_m_tlr;
668 struct ssp_info_unit ssp_iu;
669 __le32 addr_low; /* dword 12: sgl low for normal I/O. */
670 /* epl_descl for encryption I/O */
671 __le32 addr_high; /* dword 13: sgl hi for normal I/O */
672 /* dpl_descl for encryption I/O */
673 __le32 len; /* dword 14: len for normal I/O. */
674 /* edpl_desch for encryption I/O */
675 __le32 esgl; /* dword 15: ESGL bit for normal I/O. */
676 /* user defined tag mask for enc I/O */
677 /* The below fields are reserved for normal I/O */
678 u8 udt[12]; /* dword 16-18 */
679 __le32 sectcnt_ios; /* dword 19 */
680 __le32 key_cmode; /* dword 20 */
681 __le32 ks_enss; /* dword 21 */
682 __le32 keytagl; /* dword 22 */
683 __le32 keytagh; /* dword 23 */
684 __le32 twk_val0; /* dword 24 */
685 __le32 twk_val1; /* dword 25 */
686 __le32 twk_val2; /* dword 26 */
687 __le32 twk_val3; /* dword 27 */
688 __le32 enc_addr_low; /* dword 28: Encryption sgl addr low */
689 __le32 enc_addr_high; /* dword 29: Encryption sgl addr hi */
690 __le32 enc_len; /* dword 30: Encryption length */
691 __le32 enc_esgl; /* dword 31: ESGL bit for encryption */
692} __attribute__((packed, aligned(4)));
693
694/**
695 * brief the data structure for SSP_INI_DIF_ENC_IO COMMAND
696 * use to initiate SSP I/O operation with optional DIF/ENC
697 */
698struct ssp_dif_enc_io_req {
699 __le32 tag;
700 __le32 device_id;
701 __le32 data_len;
702 __le32 dirMTlr;
703 __le32 sspiu0;
704 __le32 sspiu1;
705 __le32 sspiu2;
706 __le32 sspiu3;
707 __le32 sspiu4;
708 __le32 sspiu5;
709 __le32 sspiu6;
710 __le32 epl_des;
711 __le32 dpl_desl_ndplr;
712 __le32 dpl_desh;
713 __le32 uum_uuv_bss_difbits;
714 u8 udt[12];
715 __le32 sectcnt_ios;
716 __le32 key_cmode;
717 __le32 ks_enss;
718 __le32 keytagl;
719 __le32 keytagh;
720 __le32 twk_val0;
721 __le32 twk_val1;
722 __le32 twk_val2;
723 __le32 twk_val3;
724 __le32 addr_low;
725 __le32 addr_high;
726 __le32 len;
727 __le32 esgl;
728} __attribute__((packed, aligned(4)));
729
730/**
731 * brief the data structure of Firmware download
732 * use to describe MPI FW DOWNLOAD Command (64 bytes)
733 */
734struct fw_flash_Update_req {
735 __le32 tag;
736 __le32 cur_image_offset;
737 __le32 cur_image_len;
738 __le32 total_image_len;
739 u32 reserved0[7];
740 __le32 sgl_addr_lo;
741 __le32 sgl_addr_hi;
742 __le32 len;
743 __le32 ext_reserved;
744 u32 reserved1[16];
745} __attribute__((packed, aligned(4)));
746
747#define FWFLASH_IOMB_RESERVED_LEN 0x07
748/**
749 * brief the data structure of FW_FLASH_UPDATE Response
750 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
751 *
752 */
753 struct fw_flash_Update_resp {
754 __le32 tag;
755 __le32 status;
756 u32 reserved[13];
757} __attribute__((packed, aligned(4)));
758
759/**
760 * brief the data structure of Get NVM Data Command
761 * use to get data from NVM in HBA(64 bytes)
762 */
763struct get_nvm_data_req {
764 __le32 tag;
765 __le32 len_ir_vpdd;
766 __le32 vpd_offset;
767 u32 reserved[8];
768 __le32 resp_addr_lo;
769 __le32 resp_addr_hi;
770 __le32 resp_len;
771 u32 reserved1[17];
772} __attribute__((packed, aligned(4)));
773
774struct set_nvm_data_req {
775 __le32 tag;
776 __le32 len_ir_vpdd;
777 __le32 vpd_offset;
778 u32 reserved[8];
779 __le32 resp_addr_lo;
780 __le32 resp_addr_hi;
781 __le32 resp_len;
782 u32 reserved1[17];
783} __attribute__((packed, aligned(4)));
784
785/**
786 * brief the data structure for SET CONTROLLER CONFIG COMMAND
787 * use to modify controller configuration
788 */
789struct set_ctrl_cfg_req {
790 __le32 tag;
791 __le32 cfg_pg[14];
792 u32 reserved[16];
793} __attribute__((packed, aligned(4)));
794
795/**
796 * brief the data structure for GET CONTROLLER CONFIG COMMAND
797 * use to get controller configuration page
798 */
799struct get_ctrl_cfg_req {
800 __le32 tag;
801 __le32 pgcd;
802 __le32 int_vec;
803 u32 reserved[28];
804} __attribute__((packed, aligned(4)));
805
806/**
807 * brief the data structure for KEK_MANAGEMENT COMMAND
808 * use for KEK management
809 */
810struct kek_mgmt_req {
811 __le32 tag;
812 __le32 new_curidx_ksop;
813 u32 reserved;
814 __le32 kblob[12];
815 u32 reserved1[16];
816} __attribute__((packed, aligned(4)));
817
818/**
819 * brief the data structure for DEK_MANAGEMENT COMMAND
820 * use for DEK management
821 */
822struct dek_mgmt_req {
823 __le32 tag;
824 __le32 kidx_dsop;
825 __le32 dekidx;
826 __le32 addr_l;
827 __le32 addr_h;
828 __le32 nent;
829 __le32 dbf_tblsize;
830 u32 reserved[24];
831} __attribute__((packed, aligned(4)));
832
833/**
834 * brief the data structure for SET PHY PROFILE COMMAND
835 * use to retrive phy specific information
836 */
837struct set_phy_profile_req {
838 __le32 tag;
839 __le32 ppc_phyid;
840 u32 reserved[29];
841} __attribute__((packed, aligned(4)));
842
843/**
844 * brief the data structure for GET PHY PROFILE COMMAND
845 * use to retrive phy specific information
846 */
847struct get_phy_profile_req {
848 __le32 tag;
849 __le32 ppc_phyid;
850 __le32 profile[29];
851} __attribute__((packed, aligned(4)));
852
853/**
854 * brief the data structure for EXT FLASH PARTITION
855 * use to manage ext flash partition
856 */
857struct ext_flash_partition_req {
858 __le32 tag;
859 __le32 cmd;
860 __le32 offset;
861 __le32 len;
862 u32 reserved[7];
863 __le32 addr_low;
864 __le32 addr_high;
865 __le32 len1;
866 __le32 ext;
867 u32 reserved1[16];
868} __attribute__((packed, aligned(4)));
869
870#define TWI_DEVICE 0x0
871#define C_SEEPROM 0x1
872#define VPD_FLASH 0x4
873#define AAP1_RDUMP 0x5
874#define IOP_RDUMP 0x6
875#define EXPAN_ROM 0x7
876
877#define IPMode 0x80000000
878#define NVMD_TYPE 0x0000000F
879#define NVMD_STAT 0x0000FFFF
880#define NVMD_LEN 0xFF000000
881/**
882 * brief the data structure of Get NVMD Data Response
883 * use to describe MPI Get NVMD Data Response (64 bytes)
884 */
885struct get_nvm_data_resp {
886 __le32 tag;
887 __le32 ir_tda_bn_dps_das_nvm;
888 __le32 dlen_status;
889 __le32 nvm_data[12];
890} __attribute__((packed, aligned(4)));
891
892/**
893 * brief the data structure of SAS Diagnostic Start/End Response
894 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
895 *
896 */
897struct sas_diag_start_end_resp {
898 __le32 tag;
899 __le32 status;
900 u32 reserved[13];
901} __attribute__((packed, aligned(4)));
902
903/**
904 * brief the data structure of SAS Diagnostic Execute Response
905 * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
906 *
907 */
908struct sas_diag_execute_resp {
909 __le32 tag;
910 __le32 cmdtype_cmddesc_phyid;
911 __le32 Status;
912 __le32 ReportData;
913 u32 reserved[11];
914} __attribute__((packed, aligned(4)));
915
916/**
917 * brief the data structure of Set Device State Response
918 * use to describe MPI Set Device State Response (64 bytes)
919 *
920 */
921struct set_dev_state_resp {
922 __le32 tag;
923 __le32 status;
924 __le32 device_id;
925 __le32 pds_nds;
926 u32 reserved[11];
927} __attribute__((packed, aligned(4)));
928
929/* new outbound structure for spcv - begins */
930/**
931 * brief the data structure for SET CONTROLLER CONFIG COMMAND
932 * use to modify controller configuration
933 */
934struct set_ctrl_cfg_resp {
935 __le32 tag;
936 __le32 status;
937 __le32 err_qlfr_pgcd;
938 u32 reserved[12];
939} __attribute__((packed, aligned(4)));
940
941struct get_ctrl_cfg_resp {
942 __le32 tag;
943 __le32 status;
944 __le32 err_qlfr;
945 __le32 confg_page[12];
946} __attribute__((packed, aligned(4)));
947
948struct kek_mgmt_resp {
949 __le32 tag;
950 __le32 status;
951 __le32 kidx_new_curr_ksop;
952 __le32 err_qlfr;
953 u32 reserved[11];
954} __attribute__((packed, aligned(4)));
955
956struct dek_mgmt_resp {
957 __le32 tag;
958 __le32 status;
959 __le32 kekidx_tbls_dsop;
960 __le32 dekidx;
961 __le32 err_qlfr;
962 u32 reserved[10];
963} __attribute__((packed, aligned(4)));
964
965struct get_phy_profile_resp {
966 __le32 tag;
967 __le32 status;
968 __le32 ppc_phyid;
969 __le32 ppc_specific_rsp[12];
970} __attribute__((packed, aligned(4)));
971
972struct flash_op_ext_resp {
973 __le32 tag;
974 __le32 cmd;
975 __le32 status;
976 __le32 epart_size;
977 __le32 epart_sect_size;
978 u32 reserved[10];
979} __attribute__((packed, aligned(4)));
980
981struct set_phy_profile_resp {
982 __le32 tag;
983 __le32 status;
984 __le32 ppc_phyid;
985 __le32 ppc_specific_rsp[12];
986} __attribute__((packed, aligned(4)));
987
988struct ssp_coalesced_comp_resp {
989 __le32 coal_cnt;
990 __le32 tag0;
991 __le32 ssp_tag0;
992 __le32 tag1;
993 __le32 ssp_tag1;
994 __le32 add_tag_ssp_tag[10];
995} __attribute__((packed, aligned(4)));
996
997/* new outbound structure for spcv - ends */
998
999#define NDS_BITS 0x0F
1000#define PDS_BITS 0xF0
1001
1002/*
1003 * HW Events type
1004 */
1005
1006#define HW_EVENT_RESET_START 0x01
1007#define HW_EVENT_CHIP_RESET_COMPLETE 0x02
1008#define HW_EVENT_PHY_STOP_STATUS 0x03
1009#define HW_EVENT_SAS_PHY_UP 0x04
1010#define HW_EVENT_SATA_PHY_UP 0x05
1011#define HW_EVENT_SATA_SPINUP_HOLD 0x06
1012#define HW_EVENT_PHY_DOWN 0x07
1013#define HW_EVENT_PORT_INVALID 0x08
1014#define HW_EVENT_BROADCAST_CHANGE 0x09
1015#define HW_EVENT_PHY_ERROR 0x0A
1016#define HW_EVENT_BROADCAST_SES 0x0B
1017#define HW_EVENT_INBOUND_CRC_ERROR 0x0C
1018#define HW_EVENT_HARD_RESET_RECEIVED 0x0D
1019#define HW_EVENT_MALFUNCTION 0x0E
1020#define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
1021#define HW_EVENT_BROADCAST_EXP 0x10
1022#define HW_EVENT_PHY_START_STATUS 0x11
1023#define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
1024#define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
1025#define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
1026#define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
1027#define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
1028#define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
1029#define HW_EVENT_PORT_RECOVER 0x18
1030#define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
1031#define HW_EVENT_PORT_RESET_COMPLETE 0x20
1032#define EVENT_BROADCAST_ASYNCH_EVENT 0x21
1033
1034/* port state */
1035#define PORT_NOT_ESTABLISHED 0x00
1036#define PORT_VALID 0x01
1037#define PORT_LOSTCOMM 0x02
1038#define PORT_IN_RESET 0x04
1039#define PORT_3RD_PARTY_RESET 0x07
1040#define PORT_INVALID 0x08
1041
1042/*
1043 * SSP/SMP/SATA IO Completion Status values
1044 */
1045
1046#define IO_SUCCESS 0x00
1047#define IO_ABORTED 0x01
1048#define IO_OVERFLOW 0x02
1049#define IO_UNDERFLOW 0x03
1050#define IO_FAILED 0x04
1051#define IO_ABORT_RESET 0x05
1052#define IO_NOT_VALID 0x06
1053#define IO_NO_DEVICE 0x07
1054#define IO_ILLEGAL_PARAMETER 0x08
1055#define IO_LINK_FAILURE 0x09
1056#define IO_PROG_ERROR 0x0A
1057
1058#define IO_EDC_IN_ERROR 0x0B
1059#define IO_EDC_OUT_ERROR 0x0C
1060#define IO_ERROR_HW_TIMEOUT 0x0D
1061#define IO_XFER_ERROR_BREAK 0x0E
1062#define IO_XFER_ERROR_PHY_NOT_READY 0x0F
1063#define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
1064#define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
1065#define IO_OPEN_CNX_ERROR_BREAK 0x12
1066#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
1067#define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
1068#define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
1069#define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
1070#define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
1071/* This error code 0x18 is not used on SPCv */
1072#define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
1073#define IO_XFER_ERROR_NAK_RECEIVED 0x19
1074#define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
1075#define IO_XFER_ERROR_PEER_ABORTED 0x1B
1076#define IO_XFER_ERROR_RX_FRAME 0x1C
1077#define IO_XFER_ERROR_DMA 0x1D
1078#define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
1079#define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
1080#define IO_XFER_ERROR_SATA 0x20
1081
1082/* This error code 0x22 is not used on SPCv */
1083#define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
1084#define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
1085#define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
1086#define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
1087/* This error code 0x25 is not used on SPCv */
1088#define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
1089#define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
1090#define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
1091#define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
1092#define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
1093
1094/* The following error code 0x31 and 0x32 are not using (obsolete) */
1095#define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
1096#define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
1097
1098#define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
1099#define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
1100#define IO_XFER_CMD_FRAME_ISSUED 0x36
1101#define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
1102#define IO_PORT_IN_RESET 0x38
1103#define IO_DS_NON_OPERATIONAL 0x39
1104#define IO_DS_IN_RECOVERY 0x3A
1105#define IO_TM_TAG_NOT_FOUND 0x3B
1106#define IO_XFER_PIO_SETUP_ERROR 0x3C
1107#define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
1108#define IO_DS_IN_ERROR 0x3E
1109#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
1110#define IO_ABORT_IN_PROGRESS 0x40
1111#define IO_ABORT_DELAYED 0x41
1112#define IO_INVALID_LENGTH 0x42
1113
1114/********** additional response event values *****************/
1115
1116#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT 0x43
1117#define IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED 0x44
1118#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO 0x45
1119#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST 0x46
1120#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE 0x47
1121#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED 0x48
1122#define IO_DS_INVALID 0x49
1123/* WARNING: the value is not contiguous from here */
1124#define IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR 0x52
1125#define IO_XFR_ERROR_INTERNAL_CRC_ERROR 0x54
1126#define MPI_IO_RQE_BUSY_FULL 0x55
1127#define IO_XFER_ERR_EOB_DATA_OVERRUN 0x56
1128#define IO_XFR_ERROR_INVALID_SSP_RSP_FRAME 0x57
1129#define IO_OPEN_CNX_ERROR_OPEN_PREEMPTED 0x58
1130
1131#define MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
1132#define MPI_ERR_ATAPI_DEVICE_BUSY 0x1024
1133
1134#define IO_XFR_ERROR_DEK_KEY_CACHE_MISS 0x2040
1135/*
1136 * An encryption IO request failed due to DEK Key Tag mismatch.
1137 * The key tag supplied in the encryption IOMB does not match with
1138 * the Key Tag in the referenced DEK Entry.
1139 */
1140#define IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH 0x2041
1141#define IO_XFR_ERROR_CIPHER_MODE_INVALID 0x2042
1142/*
1143 * An encryption I/O request failed because the initial value (IV)
1144 * in the unwrapped DEK blob didn't match the IV used to unwrap it.
1145 */
1146#define IO_XFR_ERROR_DEK_IV_MISMATCH 0x2043
1147/* An encryption I/O request failed due to an internal RAM ECC or
1148 * interface error while unwrapping the DEK. */
1149#define IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR 0x2044
1150/* An encryption I/O request failed due to an internal RAM ECC or
1151 * interface error while unwrapping the DEK. */
1152#define IO_XFR_ERROR_INTERNAL_RAM 0x2045
1153/*
1154 * An encryption I/O request failed
1155 * because the DEK index specified in the I/O was outside the bounds of
1156 * the total number of entries in the host DEK table.
1157 */
1158#define IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
1159
1160/* define DIF IO response error status code */
1161#define IO_XFR_ERROR_DIF_MISMATCH 0x3000
1162#define IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
1163#define IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
1164#define IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
1165
1166/* define operator management response status and error qualifier code */
1167#define OPR_MGMT_OP_NOT_SUPPORTED 0x2060
1168#define OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
1169#define OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
1170#define OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
1171#define OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
1172#define OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL 0x2022
1173#define OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE 0x2023
1174/***************** additional response event values ***************/
1175
1176/* WARNING: This error code must always be the last number.
1177 * If you add error code, modify this code also
1178 * It is used as an index
1179 */
1180#define IO_ERROR_UNKNOWN_GENERIC 0x2023
1181
1182/* MSGU CONFIGURATION TABLE*/
1183
1184#define SPCv_MSGU_CFG_TABLE_UPDATE 0x01
1185#define SPCv_MSGU_CFG_TABLE_RESET 0x02
1186#define SPCv_MSGU_CFG_TABLE_FREEZE 0x04
1187#define SPCv_MSGU_CFG_TABLE_UNFREEZE 0x08
1188#define MSGU_IBDB_SET 0x00
1189#define MSGU_HOST_INT_STATUS 0x08
1190#define MSGU_HOST_INT_MASK 0x0C
1191#define MSGU_IOPIB_INT_STATUS 0x18
1192#define MSGU_IOPIB_INT_MASK 0x1C
1193#define MSGU_IBDB_CLEAR 0x20
1194
1195#define MSGU_MSGU_CONTROL 0x24
1196#define MSGU_ODR 0x20
1197#define MSGU_ODCR 0x28
1198
1199#define MSGU_ODMR 0x30
1200#define MSGU_ODMR_U 0x34
1201#define MSGU_ODMR_CLR 0x38
1202#define MSGU_ODMR_CLR_U 0x3C
1203#define MSGU_OD_RSVD 0x40
1204
1205#define MSGU_SCRATCH_PAD_0 0x44
1206#define MSGU_SCRATCH_PAD_1 0x48
1207#define MSGU_SCRATCH_PAD_2 0x4C
1208#define MSGU_SCRATCH_PAD_3 0x50
1209#define MSGU_HOST_SCRATCH_PAD_0 0x54
1210#define MSGU_HOST_SCRATCH_PAD_1 0x58
1211#define MSGU_HOST_SCRATCH_PAD_2 0x5C
1212#define MSGU_HOST_SCRATCH_PAD_3 0x60
1213#define MSGU_HOST_SCRATCH_PAD_4 0x64
1214#define MSGU_HOST_SCRATCH_PAD_5 0x68
1215#define MSGU_HOST_SCRATCH_PAD_6 0x6C
1216#define MSGU_HOST_SCRATCH_PAD_7 0x70
1217
1218/* bit definition for ODMR register */
1219#define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
1220 interrupt vector */
1221#define ODMR_CLEAR_ALL 0 /* clear all
1222 interrupt vector */
1223/* bit definition for ODCR register */
1224#define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
1225 interrupt vector*/
1226/* MSIX Interupts */
1227#define MSIX_TABLE_OFFSET 0x2000
1228#define MSIX_TABLE_ELEMENT_SIZE 0x10
1229#define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
1230#define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + \
1231 MSIX_INTERRUPT_CONTROL_OFFSET)
1232#define MSIX_INTERRUPT_DISABLE 0x1
1233#define MSIX_INTERRUPT_ENABLE 0x0
1234
1235/* state definition for Scratch Pad1 register */
1236#define SCRATCH_PAD_RAAE_READY 0x3
1237#define SCRATCH_PAD_ILA_READY 0xC
1238#define SCRATCH_PAD_BOOT_LOAD_SUCCESS 0x0
1239#define SCRATCH_PAD_IOP0_READY 0xC00
1240#define SCRATCH_PAD_IOP1_READY 0x3000
1241
1242/* boot loader state */
1243#define SCRATCH_PAD1_BOOTSTATE_MASK 0x70 /* Bit 4-6 */
1244#define SCRATCH_PAD1_BOOTSTATE_SUCESS 0x0 /* Load successful */
1245#define SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM 0x10 /* HDA SEEPROM */
1246#define SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP 0x20 /* HDA BootStrap Pins */
1247#define SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET 0x30 /* HDA Soft Reset */
1248#define SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR 0x40 /* HDA critical error */
1249#define SCRATCH_PAD1_BOOTSTATE_R1 0x50 /* Reserved */
1250#define SCRATCH_PAD1_BOOTSTATE_R2 0x60 /* Reserved */
1251#define SCRATCH_PAD1_BOOTSTATE_FATAL 0x70 /* Fatal Error */
1252
1253 /* state definition for Scratch Pad2 register */
1254#define SCRATCH_PAD2_POR 0x00 /* power on state */
1255#define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
1256#define SCRATCH_PAD2_ERR 0x02 /* error state */
1257#define SCRATCH_PAD2_RDY 0x03 /* ready state */
1258#define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW rdy for soft reset flag */
1259#define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
1260#define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
1261 Mask, bit1-0 State */
1262#define SCRATCH_PAD2_RESERVED 0x000003FC/* Scratch Pad1
1263 Reserved bit 2 to 9 */
1264
1265#define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
1266#define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
1267
1268/* main configuration offset - byte offset */
1269#define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 */
1270#define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 */
1271#define MAIN_FW_REVISION 0x08 /* DWORD 0x02 */
1272#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 */
1273#define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 */
1274#define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 */
1275#define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 */
1276#define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 */
1277#define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 */
1278#define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 */
1279
1280/* 0x28 - 0x4C - RSVD */
1281#define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 */
1282#define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 */
1283#define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 */
1284#define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 */
1285#define MAIN_PCS_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 */
1286#define MAIN_PCS_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 */
1287#define MAIN_PCS_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A */
1288#define MAIN_PCS_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B */
1289#define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C */
1290#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D */
1291#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E */
1292#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F */
1293#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 */
1294#define MAIN_GPIO_LED_FLAGS_OFFSET 0x84 /* DWORD 0x21 */
1295#define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 */
1296
1297#define MAIN_INT_VECTOR_TABLE_OFFSET 0x8C /* DWORD 0x23 */
1298#define MAIN_SAS_PHY_ATTR_TABLE_OFFSET 0x90 /* DWORD 0x24 */
1299#define MAIN_PORT_RECOVERY_TIMER 0x94 /* DWORD 0x25 */
1300#define MAIN_INT_REASSERTION_DELAY 0x98 /* DWORD 0x26 */
1301
1302/* Gereral Status Table offset - byte offset */
1303#define GST_GSTLEN_MPIS_OFFSET 0x00
1304#define GST_IQ_FREEZE_STATE0_OFFSET 0x04
1305#define GST_IQ_FREEZE_STATE1_OFFSET 0x08
1306#define GST_MSGUTCNT_OFFSET 0x0C
1307#define GST_IOPTCNT_OFFSET 0x10
1308/* 0x14 - 0x34 - RSVD */
1309#define GST_GPIO_INPUT_VAL 0x38
1310/* 0x3c - 0x40 - RSVD */
1311#define GST_RERRINFO_OFFSET0 0x44
1312#define GST_RERRINFO_OFFSET1 0x48
1313#define GST_RERRINFO_OFFSET2 0x4c
1314#define GST_RERRINFO_OFFSET3 0x50
1315#define GST_RERRINFO_OFFSET4 0x54
1316#define GST_RERRINFO_OFFSET5 0x58
1317#define GST_RERRINFO_OFFSET6 0x5c
1318#define GST_RERRINFO_OFFSET7 0x60
1319
1320/* General Status Table - MPI state */
1321#define GST_MPI_STATE_UNINIT 0x00
1322#define GST_MPI_STATE_INIT 0x01
1323#define GST_MPI_STATE_TERMINATION 0x02
1324#define GST_MPI_STATE_ERROR 0x03
1325#define GST_MPI_STATE_MASK 0x07
1326
1327/* Per SAS PHY Attributes */
1328
1329#define PSPA_PHYSTATE0_OFFSET 0x00 /* Dword V */
1330#define PSPA_OB_HW_EVENT_PID0_OFFSET 0x04 /* DWORD V+1 */
1331#define PSPA_PHYSTATE1_OFFSET 0x08 /* Dword V+2 */
1332#define PSPA_OB_HW_EVENT_PID1_OFFSET 0x0C /* DWORD V+3 */
1333#define PSPA_PHYSTATE2_OFFSET 0x10 /* Dword V+4 */
1334#define PSPA_OB_HW_EVENT_PID2_OFFSET 0x14 /* DWORD V+5 */
1335#define PSPA_PHYSTATE3_OFFSET 0x18 /* Dword V+6 */
1336#define PSPA_OB_HW_EVENT_PID3_OFFSET 0x1C /* DWORD V+7 */
1337#define PSPA_PHYSTATE4_OFFSET 0x20 /* Dword V+8 */
1338#define PSPA_OB_HW_EVENT_PID4_OFFSET 0x24 /* DWORD V+9 */
1339#define PSPA_PHYSTATE5_OFFSET 0x28 /* Dword V+10 */
1340#define PSPA_OB_HW_EVENT_PID5_OFFSET 0x2C /* DWORD V+11 */
1341#define PSPA_PHYSTATE6_OFFSET 0x30 /* Dword V+12 */
1342#define PSPA_OB_HW_EVENT_PID6_OFFSET 0x34 /* DWORD V+13 */
1343#define PSPA_PHYSTATE7_OFFSET 0x38 /* Dword V+14 */
1344#define PSPA_OB_HW_EVENT_PID7_OFFSET 0x3C /* DWORD V+15 */
1345#define PSPA_PHYSTATE8_OFFSET 0x40 /* DWORD V+16 */
1346#define PSPA_OB_HW_EVENT_PID8_OFFSET 0x44 /* DWORD V+17 */
1347#define PSPA_PHYSTATE9_OFFSET 0x48 /* DWORD V+18 */
1348#define PSPA_OB_HW_EVENT_PID9_OFFSET 0x4C /* DWORD V+19 */
1349#define PSPA_PHYSTATE10_OFFSET 0x50 /* DWORD V+20 */
1350#define PSPA_OB_HW_EVENT_PID10_OFFSET 0x54 /* DWORD V+21 */
1351#define PSPA_PHYSTATE11_OFFSET 0x58 /* DWORD V+22 */
1352#define PSPA_OB_HW_EVENT_PID11_OFFSET 0x5C /* DWORD V+23 */
1353#define PSPA_PHYSTATE12_OFFSET 0x60 /* DWORD V+24 */
1354#define PSPA_OB_HW_EVENT_PID12_OFFSET 0x64 /* DWORD V+25 */
1355#define PSPA_PHYSTATE13_OFFSET 0x68 /* DWORD V+26 */
1356#define PSPA_OB_HW_EVENT_PID13_OFFSET 0x6c /* DWORD V+27 */
1357#define PSPA_PHYSTATE14_OFFSET 0x70 /* DWORD V+28 */
1358#define PSPA_OB_HW_EVENT_PID14_OFFSET 0x74 /* DWORD V+29 */
1359#define PSPA_PHYSTATE15_OFFSET 0x78 /* DWORD V+30 */
1360#define PSPA_OB_HW_EVENT_PID15_OFFSET 0x7c /* DWORD V+31 */
1361/* end PSPA */
1362
1363/* inbound queue configuration offset - byte offset */
1364#define IB_PROPERITY_OFFSET 0x00
1365#define IB_BASE_ADDR_HI_OFFSET 0x04
1366#define IB_BASE_ADDR_LO_OFFSET 0x08
1367#define IB_CI_BASE_ADDR_HI_OFFSET 0x0C
1368#define IB_CI_BASE_ADDR_LO_OFFSET 0x10
1369#define IB_PIPCI_BAR 0x14
1370#define IB_PIPCI_BAR_OFFSET 0x18
1371#define IB_RESERVED_OFFSET 0x1C
1372
1373/* outbound queue configuration offset - byte offset */
1374#define OB_PROPERITY_OFFSET 0x00
1375#define OB_BASE_ADDR_HI_OFFSET 0x04
1376#define OB_BASE_ADDR_LO_OFFSET 0x08
1377#define OB_PI_BASE_ADDR_HI_OFFSET 0x0C
1378#define OB_PI_BASE_ADDR_LO_OFFSET 0x10
1379#define OB_CIPCI_BAR 0x14
1380#define OB_CIPCI_BAR_OFFSET 0x18
1381#define OB_INTERRUPT_COALES_OFFSET 0x1C
1382#define OB_DYNAMIC_COALES_OFFSET 0x20
1383#define OB_PROPERTY_INT_ENABLE 0x40000000
1384
1385#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
1386#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
1387/* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
1388#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
1389#define PCIE_EVENT_INTERRUPT 0x003044
1390#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
1391#define PCIE_ERROR_INTERRUPT 0x00304C
1392
1393/* SPCV soft reset */
1394#define SPC_REG_SOFT_RESET 0x00001000
1395#define SPCv_NORMAL_RESET_VALUE 0x1
1396
1397#define SPCv_SOFT_RESET_READ_MASK 0xC0
1398#define SPCv_SOFT_RESET_NO_RESET 0x0
1399#define SPCv_SOFT_RESET_NORMAL_RESET_OCCURED 0x40
1400#define SPCv_SOFT_RESET_HDA_MODE_OCCURED 0x80
1401#define SPCv_SOFT_RESET_CHIP_RESET_OCCURED 0xC0
1402
1403/* signature definition for host scratch pad0 register */
1404#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
1405/* Signature for Soft Reset */
1406
1407/* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
1408#define SPC_REG_RESET 0x000000/* reset register */
1409
1410/* bit definition for SPC_RESET register */
1411#define SPC_REG_RESET_OSSP 0x00000001
1412#define SPC_REG_RESET_RAAE 0x00000002
1413#define SPC_REG_RESET_PCS_SPBC 0x00000004
1414#define SPC_REG_RESET_PCS_IOP_SS 0x00000008
1415#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
1416#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
1417#define SPC_REG_RESET_PCS_LM 0x00000040
1418#define SPC_REG_RESET_PCS 0x00000080
1419#define SPC_REG_RESET_GSM 0x00000100
1420#define SPC_REG_RESET_DDR2 0x00010000
1421#define SPC_REG_RESET_BDMA_CORE 0x00020000
1422#define SPC_REG_RESET_BDMA_SXCBI 0x00040000
1423#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
1424#define SPC_REG_RESET_PCIE_PWR 0x00100000
1425#define SPC_REG_RESET_PCIE_SFT 0x00200000
1426#define SPC_REG_RESET_PCS_SXCBI 0x00400000
1427#define SPC_REG_RESET_LMS_SXCBI 0x00800000
1428#define SPC_REG_RESET_PMIC_SXCBI 0x01000000
1429#define SPC_REG_RESET_PMIC_CORE 0x02000000
1430#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
1431#define SPC_REG_RESET_DEVICE 0x80000000
1432
1433/* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
1434#define SPCV_IBW_AXI_TRANSLATION_LOW 0x001010
1435
1436#define MBIC_AAP1_ADDR_BASE 0x060000
1437#define MBIC_IOP_ADDR_BASE 0x070000
1438#define GSM_ADDR_BASE 0x0700000
1439/* Dynamic map through Bar4 - 0x00700000 */
1440#define GSM_CONFIG_RESET 0x00000000
1441#define RAM_ECC_DB_ERR 0x00000018
1442#define GSM_READ_ADDR_PARITY_INDIC 0x00000058
1443#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
1444#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
1445#define GSM_READ_ADDR_PARITY_CHECK 0x00000038
1446#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
1447#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
1448
1449#define RB6_ACCESS_REG 0x6A0000
1450#define HDAC_EXEC_CMD 0x0002
1451#define HDA_C_PA 0xcb
1452#define HDA_SEQ_ID_BITS 0x00ff0000
1453#define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1454#define HDA_GSM_CMD_OFFSET_BITS 0x42C0
1455#define HDA_GSM_RSP_OFFSET_BITS 0x42E0
1456
1457#define MBIC_AAP1_ADDR_BASE 0x060000
1458#define MBIC_IOP_ADDR_BASE 0x070000
1459#define GSM_ADDR_BASE 0x0700000
1460#define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1461#define GSM_CONFIG_RESET_VALUE 0x00003b00
1462#define GPIO_ADDR_BASE 0x00090000
1463#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1464
1465/* RB6 offset */
1466#define SPC_RB6_OFFSET 0x80C0
1467/* Magic number of soft reset for RB6 */
1468#define RB6_MAGIC_NUMBER_RST 0x1234
1469
1470/* Device Register status */
1471#define DEVREG_SUCCESS 0x00
1472#define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1473#define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1474#define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1475#define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1476#define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1477#define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1478#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1479
1480#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 20:13:43 -0500