diff options
297 files changed, 15464 insertions, 3271 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index f8288ea1b530..6d498c758b45 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt | |||
| @@ -56,3 +56,6 @@ Boards: | |||
| 56 | 56 | ||
| 57 | - OMAP5 EVM : Evaluation Module | 57 | - OMAP5 EVM : Evaluation Module |
| 58 | compatible = "ti,omap5-evm", "ti,omap5" | 58 | compatible = "ti,omap5-evm", "ti,omap5" |
| 59 | |||
| 60 | - AM43x EPOS EVM | ||
| 61 | compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43" | ||
diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt index 19bca04b81c9..6256ec31666d 100644 --- a/Documentation/devicetree/bindings/arm/ste-nomadik.txt +++ b/Documentation/devicetree/bindings/arm/ste-nomadik.txt | |||
| @@ -3,6 +3,11 @@ ST-Ericsson Nomadik Device Tree Bindings | |||
| 3 | For various board the "board" node may contain specific properties | 3 | For various board the "board" node may contain specific properties |
| 4 | that pertain to this particular board, such as board-specific GPIOs. | 4 | that pertain to this particular board, such as board-specific GPIOs. |
| 5 | 5 | ||
| 6 | Required root node property: src | ||
| 7 | - Nomadik System and reset controller used for basic chip control, clock | ||
| 8 | and reset line control. | ||
| 9 | - compatible: must be "stericsson,nomadik,src" | ||
| 10 | |||
| 6 | Boards with the Nomadik SoC include: | 11 | Boards with the Nomadik SoC include: |
| 7 | 12 | ||
| 8 | S8815 "MiniKit" manufactured by Calao Systems: | 13 | S8815 "MiniKit" manufactured by Calao Systems: |
diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt new file mode 100644 index 000000000000..cedc2a9c4785 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | Device tree bindings for i.MX Wireless External Interface Module (WEIM) | ||
| 2 | |||
| 3 | The term "wireless" does not imply that the WEIM is literally an interface | ||
| 4 | without wires. It simply means that this module was originally designed for | ||
| 5 | wireless and mobile applications that use low-power technology. | ||
| 6 | |||
| 7 | The actual devices are instantiated from the child nodes of a WEIM node. | ||
| 8 | |||
| 9 | Required properties: | ||
| 10 | |||
| 11 | - compatible: Should be set to "fsl,imx6q-weim" | ||
| 12 | - reg: A resource specifier for the register space | ||
| 13 | (see the example below) | ||
| 14 | - clocks: the clock, see the example below. | ||
| 15 | - #address-cells: Must be set to 2 to allow memory address translation | ||
| 16 | - #size-cells: Must be set to 1 to allow CS address passing | ||
| 17 | - ranges: Must be set up to reflect the memory layout with four | ||
| 18 | integer values for each chip-select line in use: | ||
| 19 | |||
| 20 | <cs-number> 0 <physical address of mapping> <size> | ||
| 21 | |||
| 22 | Timing property for child nodes. It is mandatory, not optional. | ||
| 23 | |||
| 24 | - fsl,weim-cs-timing: The timing array, contains 6 timing values for the | ||
| 25 | child node. We can get the CS index from the child | ||
| 26 | node's "reg" property. This property contains the values | ||
| 27 | for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1, | ||
| 28 | EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order. | ||
| 29 | |||
| 30 | Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: | ||
| 31 | |||
| 32 | weim: weim@021b8000 { | ||
| 33 | compatible = "fsl,imx6q-weim"; | ||
| 34 | reg = <0x021b8000 0x4000>; | ||
| 35 | clocks = <&clks 196>; | ||
| 36 | #address-cells = <2>; | ||
| 37 | #size-cells = <1>; | ||
| 38 | ranges = <0 0 0x08000000 0x08000000>; | ||
| 39 | |||
| 40 | nor@0,0 { | ||
| 41 | compatible = "cfi-flash"; | ||
| 42 | reg = <0 0 0x02000000>; | ||
| 43 | #address-cells = <1>; | ||
| 44 | #size-cells = <1>; | ||
| 45 | bank-width = <2>; | ||
| 46 | fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 | ||
| 47 | 0x0000c000 0x1404a38e 0x00000000>; | ||
| 48 | }; | ||
| 49 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt index bd0c8416a5c8..0045433eae1f 100644 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt | |||
| @@ -9,6 +9,9 @@ Required properties: | |||
| 9 | "altr,socfpga-pll-clock" - for a PLL clock | 9 | "altr,socfpga-pll-clock" - for a PLL clock |
| 10 | "altr,socfpga-perip-clock" - The peripheral clock divided from the | 10 | "altr,socfpga-perip-clock" - The peripheral clock divided from the |
| 11 | PLL clock. | 11 | PLL clock. |
| 12 | "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and | ||
| 13 | can get gated. | ||
| 14 | |||
| 12 | - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. | 15 | - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. |
| 13 | - clocks : shall be the input parent clock phandle for the clock. This is | 16 | - clocks : shall be the input parent clock phandle for the clock. This is |
| 14 | either an oscillator or a pll output. | 17 | either an oscillator or a pll output. |
| @@ -16,3 +19,7 @@ Required properties: | |||
| 16 | 19 | ||
| 17 | Optional properties: | 20 | Optional properties: |
| 18 | - fixed-divider : If clocks have a fixed divider value, use this property. | 21 | - fixed-divider : If clocks have a fixed divider value, use this property. |
| 22 | - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register | ||
| 23 | and the bit index. | ||
| 24 | - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift, | ||
| 25 | and width. | ||
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index ea5e26f16aec..14d5c2af26f4 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt | |||
| @@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable. | |||
| 102 | sclk_spi0_isp 174 Exynos4x12 | 102 | sclk_spi0_isp 174 Exynos4x12 |
| 103 | sclk_spi1_isp 175 Exynos4x12 | 103 | sclk_spi1_isp 175 Exynos4x12 |
| 104 | sclk_uart_isp 176 Exynos4x12 | 104 | sclk_uart_isp 176 Exynos4x12 |
| 105 | sclk_fimg2d 177 | ||
| 105 | 106 | ||
| 106 | [Peripheral Clock Gates] | 107 | [Peripheral Clock Gates] |
| 107 | 108 | ||
| @@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable. | |||
| 129 | smmu_mfcl 274 | 130 | smmu_mfcl 274 |
| 130 | smmu_mfcr 275 | 131 | smmu_mfcr 275 |
| 131 | g3d 276 | 132 | g3d 276 |
| 132 | g2d 277 Exynos4210 | 133 | g2d 277 |
| 133 | rotator 278 Exynos4210 | 134 | rotator 278 Exynos4210 |
| 134 | mdma 279 Exynos4210 | 135 | mdma 279 Exynos4210 |
| 135 | smmu_g2d 280 Exynos4210 | 136 | smmu_g2d 280 Exynos4210 |
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt index d6cb083b90a2..0c80c2677104 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt | |||
| @@ -12,253 +12,9 @@ Required properties : | |||
| 12 | - clocks : Should contain phandle and clock specifiers for two clocks: | 12 | - clocks : Should contain phandle and clock specifiers for two clocks: |
| 13 | the 32 KHz "32k_in", and the board-specific oscillator "osc". | 13 | the 32 KHz "32k_in", and the board-specific oscillator "osc". |
| 14 | - #clock-cells : Should be 1. | 14 | - #clock-cells : Should be 1. |
| 15 | In clock consumers, this cell represents the clock ID exposed by the CAR. | 15 | In clock consumers, this cell represents the clock ID exposed by the |
| 16 | 16 | CAR. The assignments may be found in header file | |
| 17 | The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB | 17 | <dt-bindings/clock/tegra114-car.h>. |
| 18 | registers. These IDs often match those in the CAR's RST_DEVICES registers, | ||
| 19 | but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In | ||
| 20 | this case, those clocks are assigned IDs above 160 in order to highlight | ||
| 21 | this issue. Implementations that interpret these clock IDs as bit values | ||
| 22 | within the CLK_OUT_ENB or RST_DEVICES registers should be careful to | ||
| 23 | explicitly handle these special cases. | ||
| 24 | |||
| 25 | The balance of the clocks controlled by the CAR are assigned IDs of 160 and | ||
| 26 | above. | ||
| 27 | |||
| 28 | 0 unassigned | ||
| 29 | 1 unassigned | ||
| 30 | 2 unassigned | ||
| 31 | 3 unassigned | ||
| 32 | 4 rtc | ||
| 33 | 5 timer | ||
| 34 | 6 uarta | ||
| 35 | 7 unassigned (register bit affects uartb and vfir) | ||
| 36 | 8 unassigned | ||
| 37 | 9 sdmmc2 | ||
| 38 | 10 unassigned (register bit affects spdif_in and spdif_out) | ||
| 39 | 11 i2s1 | ||
| 40 | 12 i2c1 | ||
| 41 | 13 ndflash | ||
| 42 | 14 sdmmc1 | ||
| 43 | 15 sdmmc4 | ||
| 44 | 16 unassigned | ||
| 45 | 17 pwm | ||
| 46 | 18 i2s2 | ||
| 47 | 19 epp | ||
| 48 | 20 unassigned (register bit affects vi and vi_sensor) | ||
| 49 | 21 2d | ||
| 50 | 22 usbd | ||
| 51 | 23 isp | ||
| 52 | 24 3d | ||
| 53 | 25 unassigned | ||
| 54 | 26 disp2 | ||
| 55 | 27 disp1 | ||
| 56 | 28 host1x | ||
| 57 | 29 vcp | ||
| 58 | 30 i2s0 | ||
| 59 | 31 unassigned | ||
| 60 | |||
| 61 | 32 unassigned | ||
| 62 | 33 unassigned | ||
| 63 | 34 apbdma | ||
| 64 | 35 unassigned | ||
| 65 | 36 kbc | ||
| 66 | 37 unassigned | ||
| 67 | 38 unassigned | ||
| 68 | 39 unassigned (register bit affects fuse and fuse_burn) | ||
| 69 | 40 kfuse | ||
| 70 | 41 sbc1 | ||
| 71 | 42 nor | ||
| 72 | 43 unassigned | ||
| 73 | 44 sbc2 | ||
| 74 | 45 unassigned | ||
| 75 | 46 sbc3 | ||
| 76 | 47 i2c5 | ||
| 77 | 48 dsia | ||
| 78 | 49 unassigned | ||
| 79 | 50 mipi | ||
| 80 | 51 hdmi | ||
| 81 | 52 csi | ||
| 82 | 53 unassigned | ||
| 83 | 54 i2c2 | ||
| 84 | 55 uartc | ||
| 85 | 56 mipi-cal | ||
| 86 | 57 emc | ||
| 87 | 58 usb2 | ||
| 88 | 59 usb3 | ||
| 89 | 60 msenc | ||
| 90 | 61 vde | ||
| 91 | 62 bsea | ||
| 92 | 63 bsev | ||
| 93 | |||
| 94 | 64 unassigned | ||
| 95 | 65 uartd | ||
| 96 | 66 unassigned | ||
| 97 | 67 i2c3 | ||
| 98 | 68 sbc4 | ||
| 99 | 69 sdmmc3 | ||
| 100 | 70 unassigned | ||
| 101 | 71 owr | ||
| 102 | 72 afi | ||
| 103 | 73 csite | ||
| 104 | 74 unassigned | ||
| 105 | 75 unassigned | ||
| 106 | 76 la | ||
| 107 | 77 trace | ||
| 108 | 78 soc_therm | ||
| 109 | 79 dtv | ||
| 110 | 80 ndspeed | ||
| 111 | 81 i2cslow | ||
| 112 | 82 dsib | ||
| 113 | 83 tsec | ||
| 114 | 84 unassigned | ||
| 115 | 85 unassigned | ||
| 116 | 86 unassigned | ||
| 117 | 87 unassigned | ||
| 118 | 88 unassigned | ||
| 119 | 89 xusb_host | ||
| 120 | 90 unassigned | ||
| 121 | 91 msenc | ||
| 122 | 92 csus | ||
| 123 | 93 unassigned | ||
| 124 | 94 unassigned | ||
| 125 | 95 unassigned (bit affects xusb_dev and xusb_dev_src) | ||
| 126 | |||
| 127 | 96 unassigned | ||
| 128 | 97 unassigned | ||
| 129 | 98 unassigned | ||
| 130 | 99 mselect | ||
| 131 | 100 tsensor | ||
| 132 | 101 i2s3 | ||
| 133 | 102 i2s4 | ||
| 134 | 103 i2c4 | ||
| 135 | 104 sbc5 | ||
| 136 | 105 sbc6 | ||
| 137 | 106 d_audio | ||
| 138 | 107 apbif | ||
| 139 | 108 dam0 | ||
| 140 | 109 dam1 | ||
| 141 | 110 dam2 | ||
| 142 | 111 hda2codec_2x | ||
| 143 | 112 unassigned | ||
| 144 | 113 audio0_2x | ||
| 145 | 114 audio1_2x | ||
| 146 | 115 audio2_2x | ||
| 147 | 116 audio3_2x | ||
| 148 | 117 audio4_2x | ||
| 149 | 118 spdif_2x | ||
| 150 | 119 actmon | ||
| 151 | 120 extern1 | ||
| 152 | 121 extern2 | ||
| 153 | 122 extern3 | ||
| 154 | 123 unassigned | ||
| 155 | 124 unassigned | ||
| 156 | 125 hda | ||
| 157 | 126 unassigned | ||
| 158 | 127 se | ||
| 159 | |||
| 160 | 128 hda2hdmi | ||
| 161 | 129 unassigned | ||
| 162 | 130 unassigned | ||
| 163 | 131 unassigned | ||
| 164 | 132 unassigned | ||
| 165 | 133 unassigned | ||
| 166 | 134 unassigned | ||
| 167 | 135 unassigned | ||
| 168 | 136 unassigned | ||
| 169 | 137 unassigned | ||
| 170 | 138 unassigned | ||
| 171 | 139 unassigned | ||
| 172 | 140 unassigned | ||
| 173 | 141 unassigned | ||
| 174 | 142 unassigned | ||
| 175 | 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src, | ||
| 176 | xusb_host_src and xusb_ss_src) | ||
| 177 | 144 cilab | ||
| 178 | 145 cilcd | ||
| 179 | 146 cile | ||
| 180 | 147 dsialp | ||
| 181 | 148 dsiblp | ||
| 182 | 149 unassigned | ||
| 183 | 150 dds | ||
| 184 | 151 unassigned | ||
| 185 | 152 dp2 | ||
| 186 | 153 amx | ||
| 187 | 154 adx | ||
| 188 | 155 unassigned (bit affects dfll_ref and dfll_soc) | ||
| 189 | 156 xusb_ss | ||
| 190 | |||
| 191 | 192 uartb | ||
| 192 | 193 vfir | ||
| 193 | 194 spdif_in | ||
| 194 | 195 spdif_out | ||
| 195 | 196 vi | ||
| 196 | 197 vi_sensor | ||
| 197 | 198 fuse | ||
| 198 | 199 fuse_burn | ||
| 199 | 200 clk_32k | ||
| 200 | 201 clk_m | ||
| 201 | 202 clk_m_div2 | ||
| 202 | 203 clk_m_div4 | ||
| 203 | 204 pll_ref | ||
| 204 | 205 pll_c | ||
| 205 | 206 pll_c_out1 | ||
| 206 | 207 pll_c2 | ||
| 207 | 208 pll_c3 | ||
| 208 | 209 pll_m | ||
| 209 | 210 pll_m_out1 | ||
| 210 | 211 pll_p | ||
| 211 | 212 pll_p_out1 | ||
| 212 | 213 pll_p_out2 | ||
| 213 | 214 pll_p_out3 | ||
| 214 | 215 pll_p_out4 | ||
| 215 | 216 pll_a | ||
| 216 | 217 pll_a_out0 | ||
| 217 | 218 pll_d | ||
| 218 | 219 pll_d_out0 | ||
| 219 | 220 pll_d2 | ||
| 220 | 221 pll_d2_out0 | ||
| 221 | 222 pll_u | ||
| 222 | 223 pll_u_480M | ||
| 223 | 224 pll_u_60M | ||
| 224 | 225 pll_u_48M | ||
| 225 | 226 pll_u_12M | ||
| 226 | 227 pll_x | ||
| 227 | 228 pll_x_out0 | ||
| 228 | 229 pll_re_vco | ||
| 229 | 230 pll_re_out | ||
| 230 | 231 pll_e_out0 | ||
| 231 | 232 spdif_in_sync | ||
| 232 | 233 i2s0_sync | ||
| 233 | 234 i2s1_sync | ||
| 234 | 235 i2s2_sync | ||
| 235 | 236 i2s3_sync | ||
| 236 | 237 i2s4_sync | ||
| 237 | 238 vimclk_sync | ||
| 238 | 239 audio0 | ||
| 239 | 240 audio1 | ||
| 240 | 241 audio2 | ||
| 241 | 242 audio3 | ||
| 242 | 243 audio4 | ||
| 243 | 244 spdif | ||
| 244 | 245 clk_out_1 | ||
| 245 | 246 clk_out_2 | ||
| 246 | 247 clk_out_3 | ||
| 247 | 248 blink | ||
| 248 | 252 xusb_host_src | ||
| 249 | 253 xusb_falcon_src | ||
| 250 | 254 xusb_fs_src | ||
| 251 | 255 xusb_ss_src | ||
| 252 | 256 xusb_dev_src | ||
| 253 | 257 xusb_dev | ||
| 254 | 258 xusb_hs_src | ||
| 255 | 259 sclk | ||
| 256 | 260 hclk | ||
| 257 | 261 pclk | ||
| 258 | 262 cclk_g | ||
| 259 | 263 cclk_lp | ||
| 260 | 264 dfll_ref | ||
| 261 | 265 dfll_soc | ||
| 262 | 18 | ||
| 263 | Example SoC include file: | 19 | Example SoC include file: |
| 264 | 20 | ||
| @@ -270,7 +26,7 @@ Example SoC include file: | |||
| 270 | }; | 26 | }; |
| 271 | 27 | ||
| 272 | usb@c5004000 { | 28 | usb@c5004000 { |
| 273 | clocks = <&tegra_car 58>; /* usb2 */ | 29 | clocks = <&tegra_car TEGRA114_CLK_USB2>; |
| 274 | }; | 30 | }; |
| 275 | }; | 31 | }; |
| 276 | 32 | ||
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt index e885680f6b45..fcfed5bf73fb 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt | |||
| @@ -12,155 +12,9 @@ Required properties : | |||
| 12 | - clocks : Should contain phandle and clock specifiers for two clocks: | 12 | - clocks : Should contain phandle and clock specifiers for two clocks: |
| 13 | the 32 KHz "32k_in", and the board-specific oscillator "osc". | 13 | the 32 KHz "32k_in", and the board-specific oscillator "osc". |
| 14 | - #clock-cells : Should be 1. | 14 | - #clock-cells : Should be 1. |
| 15 | In clock consumers, this cell represents the clock ID exposed by the CAR. | 15 | In clock consumers, this cell represents the clock ID exposed by the |
| 16 | 16 | CAR. The assignments may be found in header file | |
| 17 | The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB | 17 | <dt-bindings/clock/tegra20-car.h>. |
| 18 | registers. These IDs often match those in the CAR's RST_DEVICES registers, | ||
| 19 | but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In | ||
| 20 | this case, those clocks are assigned IDs above 95 in order to highlight | ||
| 21 | this issue. Implementations that interpret these clock IDs as bit values | ||
| 22 | within the CLK_OUT_ENB or RST_DEVICES registers should be careful to | ||
| 23 | explicitly handle these special cases. | ||
| 24 | |||
| 25 | The balance of the clocks controlled by the CAR are assigned IDs of 96 and | ||
| 26 | above. | ||
| 27 | |||
| 28 | 0 cpu | ||
| 29 | 1 unassigned | ||
| 30 | 2 unassigned | ||
| 31 | 3 ac97 | ||
| 32 | 4 rtc | ||
| 33 | 5 tmr | ||
| 34 | 6 uart1 | ||
| 35 | 7 unassigned (register bit affects uart2 and vfir) | ||
| 36 | 8 gpio | ||
| 37 | 9 sdmmc2 | ||
| 38 | 10 unassigned (register bit affects spdif_in and spdif_out) | ||
| 39 | 11 i2s1 | ||
| 40 | 12 i2c1 | ||
| 41 | 13 ndflash | ||
| 42 | 14 sdmmc1 | ||
| 43 | 15 sdmmc4 | ||
| 44 | 16 twc | ||
| 45 | 17 pwm | ||
| 46 | 18 i2s2 | ||
| 47 | 19 epp | ||
| 48 | 20 unassigned (register bit affects vi and vi_sensor) | ||
| 49 | 21 2d | ||
| 50 | 22 usbd | ||
| 51 | 23 isp | ||
| 52 | 24 3d | ||
| 53 | 25 ide | ||
| 54 | 26 disp2 | ||
| 55 | 27 disp1 | ||
| 56 | 28 host1x | ||
| 57 | 29 vcp | ||
| 58 | 30 unassigned | ||
| 59 | 31 cache2 | ||
| 60 | |||
| 61 | 32 mem | ||
| 62 | 33 ahbdma | ||
| 63 | 34 apbdma | ||
| 64 | 35 unassigned | ||
| 65 | 36 kbc | ||
| 66 | 37 stat_mon | ||
| 67 | 38 pmc | ||
| 68 | 39 fuse | ||
| 69 | 40 kfuse | ||
| 70 | 41 sbc1 | ||
| 71 | 42 snor | ||
| 72 | 43 spi1 | ||
| 73 | 44 sbc2 | ||
| 74 | 45 xio | ||
| 75 | 46 sbc3 | ||
| 76 | 47 dvc | ||
| 77 | 48 dsi | ||
| 78 | 49 unassigned (register bit affects tvo and cve) | ||
| 79 | 50 mipi | ||
| 80 | 51 hdmi | ||
| 81 | 52 csi | ||
| 82 | 53 tvdac | ||
| 83 | 54 i2c2 | ||
| 84 | 55 uart3 | ||
| 85 | 56 unassigned | ||
| 86 | 57 emc | ||
| 87 | 58 usb2 | ||
| 88 | 59 usb3 | ||
| 89 | 60 mpe | ||
| 90 | 61 vde | ||
| 91 | 62 bsea | ||
| 92 | 63 bsev | ||
| 93 | |||
| 94 | 64 speedo | ||
| 95 | 65 uart4 | ||
| 96 | 66 uart5 | ||
| 97 | 67 i2c3 | ||
| 98 | 68 sbc4 | ||
| 99 | 69 sdmmc3 | ||
| 100 | 70 pcie | ||
| 101 | 71 owr | ||
| 102 | 72 afi | ||
| 103 | 73 csite | ||
| 104 | 74 unassigned | ||
| 105 | 75 avpucq | ||
| 106 | 76 la | ||
| 107 | 77 unassigned | ||
| 108 | 78 unassigned | ||
| 109 | 79 unassigned | ||
| 110 | 80 unassigned | ||
| 111 | 81 unassigned | ||
| 112 | 82 unassigned | ||
| 113 | 83 unassigned | ||
| 114 | 84 irama | ||
| 115 | 85 iramb | ||
| 116 | 86 iramc | ||
| 117 | 87 iramd | ||
| 118 | 88 cram2 | ||
| 119 | 89 audio_2x a/k/a audio_2x_sync_clk | ||
| 120 | 90 clk_d | ||
| 121 | 91 unassigned | ||
| 122 | 92 sus | ||
| 123 | 93 cdev2 | ||
| 124 | 94 cdev1 | ||
| 125 | 95 unassigned | ||
| 126 | |||
| 127 | 96 uart2 | ||
| 128 | 97 vfir | ||
| 129 | 98 spdif_in | ||
| 130 | 99 spdif_out | ||
| 131 | 100 vi | ||
| 132 | 101 vi_sensor | ||
| 133 | 102 tvo | ||
| 134 | 103 cve | ||
| 135 | 104 osc | ||
| 136 | 105 clk_32k a/k/a clk_s | ||
| 137 | 106 clk_m | ||
| 138 | 107 sclk | ||
| 139 | 108 cclk | ||
| 140 | 109 hclk | ||
| 141 | 110 pclk | ||
| 142 | 111 blink | ||
| 143 | 112 pll_a | ||
| 144 | 113 pll_a_out0 | ||
| 145 | 114 pll_c | ||
| 146 | 115 pll_c_out1 | ||
| 147 | 116 pll_d | ||
| 148 | 117 pll_d_out0 | ||
| 149 | 118 pll_e | ||
| 150 | 119 pll_m | ||
| 151 | 120 pll_m_out1 | ||
| 152 | 121 pll_p | ||
| 153 | 122 pll_p_out1 | ||
| 154 | 123 pll_p_out2 | ||
| 155 | 124 pll_p_out3 | ||
| 156 | 125 pll_p_out4 | ||
| 157 | 126 pll_s | ||
| 158 | 127 pll_u | ||
| 159 | 128 pll_x | ||
| 160 | 129 cop a/k/a avp | ||
| 161 | 130 audio a/k/a audio_sync_clk | ||
| 162 | 131 pll_ref | ||
| 163 | 132 twd | ||
| 164 | 18 | ||
| 165 | Example SoC include file: | 19 | Example SoC include file: |
| 166 | 20 | ||
| @@ -172,7 +26,7 @@ Example SoC include file: | |||
| 172 | }; | 26 | }; |
| 173 | 27 | ||
| 174 | usb@c5004000 { | 28 | usb@c5004000 { |
| 175 | clocks = <&tegra_car 58>; /* usb2 */ | 29 | clocks = <&tegra_car TEGRA20_CLK_USB2>; |
| 176 | }; | 30 | }; |
| 177 | }; | 31 | }; |
| 178 | 32 | ||
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt index f3da3be5fcad..0f714081e986 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt | |||
| @@ -12,212 +12,9 @@ Required properties : | |||
| 12 | - clocks : Should contain phandle and clock specifiers for two clocks: | 12 | - clocks : Should contain phandle and clock specifiers for two clocks: |
| 13 | the 32 KHz "32k_in", and the board-specific oscillator "osc". | 13 | the 32 KHz "32k_in", and the board-specific oscillator "osc". |
| 14 | - #clock-cells : Should be 1. | 14 | - #clock-cells : Should be 1. |
| 15 | In clock consumers, this cell represents the clock ID exposed by the CAR. | 15 | In clock consumers, this cell represents the clock ID exposed by the |
| 16 | 16 | CAR. The assignments may be found in header file | |
| 17 | The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB | 17 | <dt-bindings/clock/tegra30-car.h>. |
| 18 | registers. These IDs often match those in the CAR's RST_DEVICES registers, | ||
| 19 | but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In | ||
| 20 | this case, those clocks are assigned IDs above 160 in order to highlight | ||
| 21 | this issue. Implementations that interpret these clock IDs as bit values | ||
| 22 | within the CLK_OUT_ENB or RST_DEVICES registers should be careful to | ||
| 23 | explicitly handle these special cases. | ||
| 24 | |||
| 25 | The balance of the clocks controlled by the CAR are assigned IDs of 160 and | ||
| 26 | above. | ||
| 27 | |||
| 28 | 0 cpu | ||
| 29 | 1 unassigned | ||
| 30 | 2 unassigned | ||
| 31 | 3 unassigned | ||
| 32 | 4 rtc | ||
| 33 | 5 timer | ||
| 34 | 6 uarta | ||
| 35 | 7 unassigned (register bit affects uartb and vfir) | ||
| 36 | 8 gpio | ||
| 37 | 9 sdmmc2 | ||
| 38 | 10 unassigned (register bit affects spdif_in and spdif_out) | ||
| 39 | 11 i2s1 | ||
| 40 | 12 i2c1 | ||
| 41 | 13 ndflash | ||
| 42 | 14 sdmmc1 | ||
| 43 | 15 sdmmc4 | ||
| 44 | 16 unassigned | ||
| 45 | 17 pwm | ||
| 46 | 18 i2s2 | ||
| 47 | 19 epp | ||
| 48 | 20 unassigned (register bit affects vi and vi_sensor) | ||
| 49 | 21 2d | ||
| 50 | 22 usbd | ||
| 51 | 23 isp | ||
| 52 | 24 3d | ||
| 53 | 25 unassigned | ||
| 54 | 26 disp2 | ||
| 55 | 27 disp1 | ||
| 56 | 28 host1x | ||
| 57 | 29 vcp | ||
| 58 | 30 i2s0 | ||
| 59 | 31 cop_cache | ||
| 60 | |||
| 61 | 32 mc | ||
| 62 | 33 ahbdma | ||
| 63 | 34 apbdma | ||
| 64 | 35 unassigned | ||
| 65 | 36 kbc | ||
| 66 | 37 statmon | ||
| 67 | 38 pmc | ||
| 68 | 39 unassigned (register bit affects fuse and fuse_burn) | ||
| 69 | 40 kfuse | ||
| 70 | 41 sbc1 | ||
| 71 | 42 nor | ||
| 72 | 43 unassigned | ||
| 73 | 44 sbc2 | ||
| 74 | 45 unassigned | ||
| 75 | 46 sbc3 | ||
| 76 | 47 i2c5 | ||
| 77 | 48 dsia | ||
| 78 | 49 unassigned (register bit affects cve and tvo) | ||
| 79 | 50 mipi | ||
| 80 | 51 hdmi | ||
| 81 | 52 csi | ||
| 82 | 53 tvdac | ||
| 83 | 54 i2c2 | ||
| 84 | 55 uartc | ||
| 85 | 56 unassigned | ||
| 86 | 57 emc | ||
| 87 | 58 usb2 | ||
| 88 | 59 usb3 | ||
| 89 | 60 mpe | ||
| 90 | 61 vde | ||
| 91 | 62 bsea | ||
| 92 | 63 bsev | ||
| 93 | |||
| 94 | 64 speedo | ||
| 95 | 65 uartd | ||
| 96 | 66 uarte | ||
| 97 | 67 i2c3 | ||
| 98 | 68 sbc4 | ||
| 99 | 69 sdmmc3 | ||
| 100 | 70 pcie | ||
| 101 | 71 owr | ||
| 102 | 72 afi | ||
| 103 | 73 csite | ||
| 104 | 74 pciex | ||
| 105 | 75 avpucq | ||
| 106 | 76 la | ||
| 107 | 77 unassigned | ||
| 108 | 78 unassigned | ||
| 109 | 79 dtv | ||
| 110 | 80 ndspeed | ||
| 111 | 81 i2cslow | ||
| 112 | 82 dsib | ||
| 113 | 83 unassigned | ||
| 114 | 84 irama | ||
| 115 | 85 iramb | ||
| 116 | 86 iramc | ||
| 117 | 87 iramd | ||
| 118 | 88 cram2 | ||
| 119 | 89 unassigned | ||
| 120 | 90 audio_2x a/k/a audio_2x_sync_clk | ||
| 121 | 91 unassigned | ||
| 122 | 92 csus | ||
| 123 | 93 cdev2 | ||
| 124 | 94 cdev1 | ||
| 125 | 95 unassigned | ||
| 126 | |||
| 127 | 96 cpu_g | ||
| 128 | 97 cpu_lp | ||
| 129 | 98 3d2 | ||
| 130 | 99 mselect | ||
| 131 | 100 tsensor | ||
| 132 | 101 i2s3 | ||
| 133 | 102 i2s4 | ||
| 134 | 103 i2c4 | ||
| 135 | 104 sbc5 | ||
| 136 | 105 sbc6 | ||
| 137 | 106 d_audio | ||
| 138 | 107 apbif | ||
| 139 | 108 dam0 | ||
| 140 | 109 dam1 | ||
| 141 | 110 dam2 | ||
| 142 | 111 hda2codec_2x | ||
| 143 | 112 atomics | ||
| 144 | 113 audio0_2x | ||
| 145 | 114 audio1_2x | ||
| 146 | 115 audio2_2x | ||
| 147 | 116 audio3_2x | ||
| 148 | 117 audio4_2x | ||
| 149 | 118 audio5_2x | ||
| 150 | 119 actmon | ||
| 151 | 120 extern1 | ||
| 152 | 121 extern2 | ||
| 153 | 122 extern3 | ||
| 154 | 123 sata_oob | ||
| 155 | 124 sata | ||
| 156 | 125 hda | ||
| 157 | 127 se | ||
| 158 | 128 hda2hdmi | ||
| 159 | 129 sata_cold | ||
| 160 | |||
| 161 | 160 uartb | ||
| 162 | 161 vfir | ||
| 163 | 162 spdif_in | ||
| 164 | 163 spdif_out | ||
| 165 | 164 vi | ||
| 166 | 165 vi_sensor | ||
| 167 | 166 fuse | ||
| 168 | 167 fuse_burn | ||
| 169 | 168 cve | ||
| 170 | 169 tvo | ||
| 171 | |||
| 172 | 170 clk_32k | ||
| 173 | 171 clk_m | ||
| 174 | 172 clk_m_div2 | ||
| 175 | 173 clk_m_div4 | ||
| 176 | 174 pll_ref | ||
| 177 | 175 pll_c | ||
| 178 | 176 pll_c_out1 | ||
| 179 | 177 pll_m | ||
| 180 | 178 pll_m_out1 | ||
| 181 | 179 pll_p | ||
| 182 | 180 pll_p_out1 | ||
| 183 | 181 pll_p_out2 | ||
| 184 | 182 pll_p_out3 | ||
| 185 | 183 pll_p_out4 | ||
| 186 | 184 pll_a | ||
| 187 | 185 pll_a_out0 | ||
| 188 | 186 pll_d | ||
| 189 | 187 pll_d_out0 | ||
| 190 | 188 pll_d2 | ||
| 191 | 189 pll_d2_out0 | ||
| 192 | 190 pll_u | ||
| 193 | 191 pll_x | ||
| 194 | 192 pll_x_out0 | ||
| 195 | 193 pll_e | ||
| 196 | 194 spdif_in_sync | ||
| 197 | 195 i2s0_sync | ||
| 198 | 196 i2s1_sync | ||
| 199 | 197 i2s2_sync | ||
| 200 | 198 i2s3_sync | ||
| 201 | 199 i2s4_sync | ||
| 202 | 200 vimclk | ||
| 203 | 201 audio0 | ||
| 204 | 202 audio1 | ||
| 205 | 203 audio2 | ||
| 206 | 204 audio3 | ||
| 207 | 205 audio4 | ||
| 208 | 206 audio5 | ||
| 209 | 207 clk_out_1 (extern1) | ||
| 210 | 208 clk_out_2 (extern2) | ||
| 211 | 209 clk_out_3 (extern3) | ||
| 212 | 210 sclk | ||
| 213 | 211 blink | ||
| 214 | 212 cclk_g | ||
| 215 | 213 cclk_lp | ||
| 216 | 214 twd | ||
| 217 | 215 cml0 | ||
| 218 | 216 cml1 | ||
| 219 | 217 hclk | ||
| 220 | 218 pclk | ||
| 221 | 18 | ||
| 222 | Example SoC include file: | 19 | Example SoC include file: |
| 223 | 20 | ||
| @@ -229,7 +26,7 @@ Example SoC include file: | |||
| 229 | }; | 26 | }; |
| 230 | 27 | ||
| 231 | usb@c5004000 { | 28 | usb@c5004000 { |
| 232 | clocks = <&tegra_car 58>; /* usb2 */ | 29 | clocks = <&tegra_car TEGRA30_CLK_USB2>; |
| 233 | }; | 30 | }; |
| 234 | }; | 31 | }; |
| 235 | 32 | ||
diff --git a/Documentation/devicetree/bindings/clock/st,nomadik.txt b/Documentation/devicetree/bindings/clock/st,nomadik.txt new file mode 100644 index 000000000000..7fc09773de46 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,nomadik.txt | |||
| @@ -0,0 +1,104 @@ | |||
| 1 | ST Microelectronics Nomadik SRC System Reset and Control | ||
| 2 | |||
| 3 | This binding uses the common clock binding: | ||
| 4 | Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
| 5 | |||
| 6 | The Nomadik SRC controller is responsible of controlling chrystals, | ||
| 7 | PLLs and clock gates. | ||
| 8 | |||
| 9 | Required properties for the SRC node: | ||
| 10 | - compatible: must be "stericsson,nomadik-src" | ||
| 11 | - reg: must contain the SRC register base and size | ||
| 12 | |||
| 13 | Optional properties for the SRC node: | ||
| 14 | - disable-sxtalo: if present this will disable the SXTALO | ||
| 15 | i.e. the driver output for the slow 32kHz chrystal, if the | ||
| 16 | board has its own circuitry for providing this oscillator | ||
| 17 | - disable-mxtal: if present this will disable the MXTALO, | ||
| 18 | i.e. the driver output for the main (~19.2 MHz) chrystal, | ||
| 19 | if the board has its own circuitry for providing this | ||
| 20 | osciallator | ||
| 21 | |||
| 22 | |||
| 23 | PLL nodes: these nodes represent the two PLLs on the system, | ||
| 24 | which should both have the main chrystal, represented as a | ||
| 25 | fixed frequency clock, as parent. | ||
| 26 | |||
| 27 | Required properties for the two PLL nodes: | ||
| 28 | - compatible: must be "st,nomadik-pll-clock" | ||
| 29 | - clock-cells: must be 0 | ||
| 30 | - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively | ||
| 31 | - clocks: this clock will have main chrystal as parent | ||
| 32 | |||
| 33 | |||
| 34 | HCLK nodes: these represent the clock gates on individual | ||
| 35 | lines from the HCLK clock tree and the gate for individual | ||
| 36 | lines from the PCLK clock tree. | ||
| 37 | |||
| 38 | Requires properties for the HCLK nodes: | ||
| 39 | - compatible: must be "st,nomadik-hclk-clock" | ||
| 40 | - clock-cells: must be 0 | ||
| 41 | - clock-id: must be the clock ID from 0 to 63 according to | ||
| 42 | this table: | ||
| 43 | |||
| 44 | 0: HCLKDMA0 | ||
| 45 | 1: HCLKSMC | ||
| 46 | 2: HCLKSDRAM | ||
| 47 | 3: HCLKDMA1 | ||
| 48 | 4: HCLKCLCD | ||
| 49 | 5: PCLKIRDA | ||
| 50 | 6: PCLKSSP | ||
| 51 | 7: PCLKUART0 | ||
| 52 | 8: PCLKSDI | ||
| 53 | 9: PCLKI2C0 | ||
| 54 | 10: PCLKI2C1 | ||
| 55 | 11: PCLKUART1 | ||
| 56 | 12: PCLMSP0 | ||
| 57 | 13: HCLKUSB | ||
| 58 | 14: HCLKDIF | ||
| 59 | 15: HCLKSAA | ||
| 60 | 16: HCLKSVA | ||
| 61 | 17: PCLKHSI | ||
| 62 | 18: PCLKXTI | ||
| 63 | 19: PCLKUART2 | ||
| 64 | 20: PCLKMSP1 | ||
| 65 | 21: PCLKMSP2 | ||
| 66 | 22: PCLKOWM | ||
| 67 | 23: HCLKHPI | ||
| 68 | 24: PCLKSKE | ||
| 69 | 25: PCLKHSEM | ||
| 70 | 26: HCLK3D | ||
| 71 | 27: HCLKHASH | ||
| 72 | 28: HCLKCRYP | ||
| 73 | 29: PCLKMSHC | ||
| 74 | 30: HCLKUSBM | ||
| 75 | 31: HCLKRNG | ||
| 76 | (32, 33, 34, 35 RESERVED) | ||
| 77 | 36: CLDCLK | ||
| 78 | 37: IRDACLK | ||
| 79 | 38: SSPICLK | ||
| 80 | 39: UART0CLK | ||
| 81 | 40: SDICLK | ||
| 82 | 41: I2C0CLK | ||
| 83 | 42: I2C1CLK | ||
| 84 | 43: UART1CLK | ||
| 85 | 44: MSPCLK0 | ||
| 86 | 45: USBCLK | ||
| 87 | 46: DIFCLK | ||
| 88 | 47: IPI2CCLK | ||
| 89 | 48: IPBMCCLK | ||
| 90 | 49: HSICLKRX | ||
| 91 | 50: HSICLKTX | ||
| 92 | 51: UART2CLK | ||
| 93 | 52: MSPCLK1 | ||
| 94 | 53: MSPCLK2 | ||
| 95 | 54: OWMCLK | ||
| 96 | (55 RESERVED) | ||
| 97 | 56: SKECLK | ||
| 98 | (57 RESERVED) | ||
| 99 | 58: 3DCLK | ||
| 100 | 59: PCLKMSP3 | ||
| 101 | 60: MSPCLK3 | ||
| 102 | 61: MSHCCLK | ||
| 103 | 62: USBMCLK | ||
| 104 | 63: RNGCCLK | ||
diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt index 2b14a940eb75..3f454ffc654a 100644 --- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt +++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt | |||
| @@ -10,11 +10,16 @@ Required properties: | |||
| 10 | mapped region. | 10 | mapped region. |
| 11 | 11 | ||
| 12 | - interrupts : G2D interrupt number to the CPU. | 12 | - interrupts : G2D interrupt number to the CPU. |
| 13 | - clocks : from common clock binding: handle to G2D clocks. | ||
| 14 | - clock-names : from common clock binding: must contain "sclk_fimg2d" and | ||
| 15 | "fimg2d", corresponding to entries in the clocks property. | ||
| 13 | 16 | ||
| 14 | Example: | 17 | Example: |
| 15 | g2d@12800000 { | 18 | g2d@12800000 { |
| 16 | compatible = "samsung,s5pv210-g2d"; | 19 | compatible = "samsung,s5pv210-g2d"; |
| 17 | reg = <0x12800000 0x1000>; | 20 | reg = <0x12800000 0x1000>; |
| 18 | interrupts = <0 89 0>; | 21 | interrupts = <0 89 0>; |
| 22 | clocks = <&clock 177>, <&clock 277>; | ||
| 23 | clock-names = "sclk_fimg2d", "fimg2d"; | ||
| 19 | status = "disabled"; | 24 | status = "disabled"; |
| 20 | }; | 25 | }; |
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file mode 100644 index 000000000000..1f8b0c507c26 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | DT bindings for the R-/SH-Mobile irqpin controller | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | |||
| 5 | - compatible: has to be "renesas,intc-irqpin" | ||
| 6 | - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in | ||
| 7 | interrupts.txt in this directory | ||
| 8 | |||
| 9 | Optional properties: | ||
| 10 | |||
| 11 | - any properties, listed in interrupts.txt, and any standard resource allocation | ||
| 12 | properties | ||
| 13 | - sense-bitfield-width: width of a single sense bitfield in the SENSE register, | ||
| 14 | if different from the default 4 bits | ||
| 15 | - control-parent: disable and enable interrupts on the parent interrupt | ||
| 16 | controller, needed for some broken implementations | ||
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt index bf0182d8da25..df37b0230c75 100644 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt | |||
| @@ -15,6 +15,9 @@ Required properties: | |||
| 15 | mapped region. | 15 | mapped region. |
| 16 | 16 | ||
| 17 | - interrupts : MFC interrupt number to the CPU. | 17 | - interrupts : MFC interrupt number to the CPU. |
| 18 | - clocks : from common clock binding: handle to mfc clocks. | ||
| 19 | - clock-names : from common clock binding: must contain "sclk_mfc" and "mfc", | ||
| 20 | corresponding to entries in the clocks property. | ||
| 18 | 21 | ||
| 19 | - samsung,mfc-r : Base address of the first memory bank used by MFC | 22 | - samsung,mfc-r : Base address of the first memory bank used by MFC |
| 20 | for DMA contiguous memory allocation and its size. | 23 | for DMA contiguous memory allocation and its size. |
| @@ -34,6 +37,8 @@ mfc: codec@13400000 { | |||
| 34 | reg = <0x13400000 0x10000>; | 37 | reg = <0x13400000 0x10000>; |
| 35 | interrupts = <0 94 0>; | 38 | interrupts = <0 94 0>; |
| 36 | samsung,power-domain = <&pd_mfc>; | 39 | samsung,power-domain = <&pd_mfc>; |
| 40 | clocks = <&clock 170>, <&clock 273>; | ||
| 41 | clock-names = "sclk_mfc", "mfc"; | ||
| 37 | }; | 42 | }; |
| 38 | 43 | ||
| 39 | Board specific DT entry: | 44 | Board specific DT entry: |
diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt index c3a14e0ad0ad..cd9e90c5d171 100644 --- a/Documentation/devicetree/bindings/mfd/ab8500.txt +++ b/Documentation/devicetree/bindings/mfd/ab8500.txt | |||
| @@ -120,7 +120,7 @@ ab8500 { | |||
| 120 | "USB_LINK_STATUS", | 120 | "USB_LINK_STATUS", |
| 121 | "USB_ADP_PROBE_PLUG", | 121 | "USB_ADP_PROBE_PLUG", |
| 122 | "USB_ADP_PROBE_UNPLUG"; | 122 | "USB_ADP_PROBE_UNPLUG"; |
| 123 | vddulpivio18-supply = <&ab8500_ldo_initcore_reg>; | 123 | vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; |
| 124 | v-ape-supply = <&db8500_vape_reg>; | 124 | v-ape-supply = <&db8500_vape_reg>; |
| 125 | musb_1v8-supply = <&db8500_vsmps2_reg>; | 125 | musb_1v8-supply = <&db8500_vsmps2_reg>; |
| 126 | }; | 126 | }; |
diff --git a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt new file mode 100644 index 000000000000..094ae010f2fb --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | Broadcom BCM281xx SDHCI | ||
| 2 | |||
| 3 | This file documents differences between the core properties in mmc.txt | ||
| 4 | and the properties present in the bcm281xx SDHCI | ||
| 5 | |||
| 6 | Required properties: | ||
| 7 | - compatible : Should be "bcm,kona-sdhci" | ||
| 8 | |||
| 9 | Example: | ||
| 10 | |||
| 11 | sdio2: sdio@0x3f1a0000 { | ||
| 12 | compatible = "bcm,kona-sdhci"; | ||
| 13 | reg = <0x3f1a0000 0x10000>; | ||
| 14 | interrupts = <0x0 74 0x4>; | ||
| 15 | }; | ||
| 16 | |||
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt index bcfdab5d442e..3a7caf7a744a 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt | |||
| @@ -58,7 +58,7 @@ Some requirements for using fsl,imx-pinctrl binding: | |||
| 58 | 58 | ||
| 59 | Examples: | 59 | Examples: |
| 60 | usdhc@0219c000 { /* uSDHC4 */ | 60 | usdhc@0219c000 { /* uSDHC4 */ |
| 61 | fsl,card-wired; | 61 | non-removable; |
| 62 | vmmc-supply = <®_3p3v>; | 62 | vmmc-supply = <®_3p3v>; |
| 63 | status = "okay"; | 63 | status = "okay"; |
| 64 | pinctrl-names = "default"; | 64 | pinctrl-names = "default"; |
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index c70fca146e91..e15cfc4bb39e 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | |||
| @@ -21,8 +21,18 @@ Required Properties: | |||
| 21 | 21 | ||
| 22 | - gpio-controller: identifies the node as a gpio controller and pin bank. | 22 | - gpio-controller: identifies the node as a gpio controller and pin bank. |
| 23 | - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO | 23 | - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO |
| 24 | binding is used, the amount of cells must be specified as 2. See generic | 24 | binding is used, the amount of cells must be specified as 2. See the below |
| 25 | GPIO binding documentation for description of particular cells. | 25 | mentioned gpio binding representation for description of particular cells. |
| 26 | |||
| 27 | Eg: <&gpx2 6 0> | ||
| 28 | <[phandle of the gpio controller node] | ||
| 29 | [pin number within the gpio controller] | ||
| 30 | [flags]> | ||
| 31 | |||
| 32 | Values for gpio specifier: | ||
| 33 | - Pin number: is a value between 0 to 7. | ||
| 34 | - Flags: 0 - Active High | ||
| 35 | 1 - Active Low | ||
| 26 | 36 | ||
| 27 | - Pin mux/config groups as child nodes: The pin mux (selecting pin function | 37 | - Pin mux/config groups as child nodes: The pin mux (selecting pin function |
| 28 | mode) and pin config (pull up/down, driver strength) settings are represented | 38 | mode) and pin config (pull up/down, driver strength) settings are represented |
| @@ -266,3 +276,33 @@ Example 4: Set up the default pin state for uart controller. | |||
| 266 | 276 | ||
| 267 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | 277 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
| 268 | } | 278 | } |
| 279 | |||
| 280 | Example 5: A display port client node that supports 'default' pinctrl state | ||
| 281 | and gpio binding. | ||
| 282 | |||
| 283 | display-port-controller { | ||
| 284 | /* ... */ | ||
| 285 | |||
| 286 | samsung,hpd-gpio = <&gpx2 6 0>; | ||
| 287 | pinctrl-names = "default"; | ||
| 288 | pinctrl-0 = <&dp_hpd>; | ||
| 289 | }; | ||
| 290 | |||
| 291 | Example 6: Request the gpio for display port controller | ||
| 292 | |||
| 293 | static int exynos_dp_probe(struct platform_device *pdev) | ||
| 294 | { | ||
| 295 | int hpd_gpio, ret; | ||
| 296 | struct device *dev = &pdev->dev; | ||
| 297 | struct device_node *dp_node = dev->of_node; | ||
| 298 | |||
| 299 | /* ... */ | ||
| 300 | |||
| 301 | hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0); | ||
| 302 | |||
| 303 | /* ... */ | ||
| 304 | |||
| 305 | ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN, | ||
| 306 | "hpd_gpio"); | ||
| 307 | /* ... */ | ||
| 308 | } | ||
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt index b3abde736017..d967ba16de60 100644 --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt | |||
| @@ -48,3 +48,37 @@ Example: | |||
| 48 | clocks = <&clock 285>; | 48 | clocks = <&clock 285>; |
| 49 | clock-names = "usbhost"; | 49 | clock-names = "usbhost"; |
| 50 | }; | 50 | }; |
| 51 | |||
| 52 | DWC3 | ||
| 53 | Required properties: | ||
| 54 | - compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3 | ||
| 55 | controller. | ||
| 56 | - #address-cells, #size-cells : should be '1' if the device has sub-nodes | ||
| 57 | with 'reg' property. | ||
| 58 | - ranges: allows valid 1:1 translation between child's address space and | ||
| 59 | parent's address space | ||
| 60 | - clocks: Clock IDs array as required by the controller. | ||
| 61 | - clock-names: names of clocks correseponding to IDs in the clock property | ||
| 62 | |||
| 63 | Sub-nodes: | ||
| 64 | The dwc3 core should be added as subnode to Exynos dwc3 glue. | ||
| 65 | - dwc3 : | ||
| 66 | The binding details of dwc3 can be found in: | ||
| 67 | Documentation/devicetree/bindings/usb/dwc3.txt | ||
| 68 | |||
| 69 | Example: | ||
| 70 | usb@12000000 { | ||
| 71 | compatible = "samsung,exynos5250-dwusb3"; | ||
| 72 | clocks = <&clock 286>; | ||
| 73 | clock-names = "usbdrd30"; | ||
| 74 | #address-cells = <1>; | ||
| 75 | #size-cells = <1>; | ||
| 76 | ranges; | ||
| 77 | |||
| 78 | dwc3 { | ||
| 79 | compatible = "synopsys,dwc3"; | ||
| 80 | reg = <0x12000000 0x10000>; | ||
| 81 | interrupts = <0 72 0>; | ||
| 82 | usb-phy = <&usb2_phy &usb3_phy>; | ||
| 83 | }; | ||
| 84 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt index c60da67a5d76..84f10c16cb38 100644 --- a/Documentation/devicetree/bindings/video/exynos_dp.txt +++ b/Documentation/devicetree/bindings/video/exynos_dp.txt | |||
| @@ -21,6 +21,10 @@ Required properties for dp-controller: | |||
| 21 | of memory mapped region. | 21 | of memory mapped region. |
| 22 | -interrupts: | 22 | -interrupts: |
| 23 | interrupt combiner values. | 23 | interrupt combiner values. |
| 24 | -clocks: | ||
| 25 | from common clock binding: handle to dp clock. | ||
| 26 | -clock-names: | ||
| 27 | from common clock binding: Shall be "dp". | ||
| 24 | -interrupt-parent: | 28 | -interrupt-parent: |
| 25 | phandle to Interrupt combiner node. | 29 | phandle to Interrupt combiner node. |
| 26 | -samsung,color-space: | 30 | -samsung,color-space: |
| @@ -61,6 +65,8 @@ SOC specific portion: | |||
| 61 | reg = <0x145b0000 0x10000>; | 65 | reg = <0x145b0000 0x10000>; |
| 62 | interrupts = <10 3>; | 66 | interrupts = <10 3>; |
| 63 | interrupt-parent = <&combiner>; | 67 | interrupt-parent = <&combiner>; |
| 68 | clocks = <&clock 342>; | ||
| 69 | clock-names = "dp"; | ||
| 64 | 70 | ||
| 65 | dptx-phy { | 71 | dptx-phy { |
| 66 | reg = <0x10040720>; | 72 | reg = <0x10040720>; |
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f9eae2f0ae5d..962c0eee3039 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
| @@ -16,11 +16,13 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb | |||
| 16 | dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb | 16 | dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb |
| 17 | dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb | 17 | dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb |
| 18 | # sam9g20 | 18 | # sam9g20 |
| 19 | dtb-$(CONFIG_ARCH_AT91) += at91-foxg20.dtb | ||
| 19 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb | 20 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb |
| 20 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb | 21 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb |
| 21 | dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb | 22 | dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb |
| 22 | dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb | 23 | dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb |
| 23 | dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb | 24 | dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb |
| 25 | dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb | ||
| 24 | # sam9g45 | 26 | # sam9g45 |
| 25 | dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb | 27 | dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb |
| 26 | dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb | 28 | dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb |
| @@ -86,6 +88,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ | |||
| 86 | kirkwood-ns2max.dtb \ | 88 | kirkwood-ns2max.dtb \ |
| 87 | kirkwood-ns2mini.dtb \ | 89 | kirkwood-ns2mini.dtb \ |
| 88 | kirkwood-nsa310.dtb \ | 90 | kirkwood-nsa310.dtb \ |
| 91 | kirkwood-sheevaplug.dtb \ | ||
| 92 | kirkwood-sheevaplug-esata.dtb \ | ||
| 89 | kirkwood-topkick.dtb \ | 93 | kirkwood-topkick.dtb \ |
| 90 | kirkwood-ts219-6281.dtb \ | 94 | kirkwood-ts219-6281.dtb \ |
| 91 | kirkwood-ts219-6282.dtb \ | 95 | kirkwood-ts219-6282.dtb \ |
| @@ -105,13 +109,15 @@ dtb-$(CONFIG_ARCH_MXC) += \ | |||
| 105 | imx27-apf27.dtb \ | 109 | imx27-apf27.dtb \ |
| 106 | imx27-apf27dev.dtb \ | 110 | imx27-apf27dev.dtb \ |
| 107 | imx27-pdk.dtb \ | 111 | imx27-pdk.dtb \ |
| 108 | imx27-phytec-phycore.dtb \ | 112 | imx27-phytec-phycore-som.dtb \ |
| 113 | imx27-phytec-phycore-rdk.dtb \ | ||
| 109 | imx31-bug.dtb \ | 114 | imx31-bug.dtb \ |
| 110 | imx51-apf51.dtb \ | 115 | imx51-apf51.dtb \ |
| 111 | imx51-apf51dev.dtb \ | 116 | imx51-apf51dev.dtb \ |
| 112 | imx51-babbage.dtb \ | 117 | imx51-babbage.dtb \ |
| 113 | imx53-ard.dtb \ | 118 | imx53-ard.dtb \ |
| 114 | imx53-evk.dtb \ | 119 | imx53-evk.dtb \ |
| 120 | imx53-m53evk.dtb \ | ||
| 115 | imx53-mba53.dtb \ | 121 | imx53-mba53.dtb \ |
| 116 | imx53-qsb.dtb \ | 122 | imx53-qsb.dtb \ |
| 117 | imx53-smd.dtb \ | 123 | imx53-smd.dtb \ |
| @@ -119,10 +125,13 @@ dtb-$(CONFIG_ARCH_MXC) += \ | |||
| 119 | imx6dl-sabresd.dtb \ | 125 | imx6dl-sabresd.dtb \ |
| 120 | imx6dl-wandboard.dtb \ | 126 | imx6dl-wandboard.dtb \ |
| 121 | imx6q-arm2.dtb \ | 127 | imx6q-arm2.dtb \ |
| 128 | imx6q-phytec-pbab01.dtb \ | ||
| 122 | imx6q-sabreauto.dtb \ | 129 | imx6q-sabreauto.dtb \ |
| 123 | imx6q-sabrelite.dtb \ | 130 | imx6q-sabrelite.dtb \ |
| 124 | imx6q-sabresd.dtb \ | 131 | imx6q-sabresd.dtb \ |
| 125 | imx6q-sbc6x.dtb | 132 | imx6q-sbc6x.dtb \ |
| 133 | imx6sl-evk.dtb \ | ||
| 134 | vf610-twr.dtb | ||
| 126 | dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ | 135 | dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ |
| 127 | imx23-olinuxino.dtb \ | 136 | imx23-olinuxino.dtb \ |
| 128 | imx23-stmp378x_devb.dtb \ | 137 | imx23-stmp378x_devb.dtb \ |
| @@ -132,6 +141,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ | |||
| 132 | imx28-cfa10036.dtb \ | 141 | imx28-cfa10036.dtb \ |
| 133 | imx28-cfa10037.dtb \ | 142 | imx28-cfa10037.dtb \ |
| 134 | imx28-cfa10049.dtb \ | 143 | imx28-cfa10049.dtb \ |
| 144 | imx28-cfa10055.dtb \ | ||
| 145 | imx28-cfa10057.dtb \ | ||
| 135 | imx28-evk.dtb \ | 146 | imx28-evk.dtb \ |
| 136 | imx28-m28evk.dtb \ | 147 | imx28-m28evk.dtb \ |
| 137 | imx28-sps1.dtb \ | 148 | imx28-sps1.dtb \ |
| @@ -151,19 +162,26 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ | |||
| 151 | omap4-panda-es.dtb \ | 162 | omap4-panda-es.dtb \ |
| 152 | omap4-var-som.dtb \ | 163 | omap4-var-som.dtb \ |
| 153 | omap4-sdp.dtb \ | 164 | omap4-sdp.dtb \ |
| 154 | omap5-evm.dtb \ | 165 | omap4-sdp-es23plus.dtb \ |
| 166 | omap5-uevm.dtb \ | ||
| 155 | am335x-evm.dtb \ | 167 | am335x-evm.dtb \ |
| 156 | am335x-evmsk.dtb \ | 168 | am335x-evmsk.dtb \ |
| 157 | am335x-bone.dtb | 169 | am335x-bone.dtb \ |
| 170 | am3517-evm.dtb \ | ||
| 171 | am3517_mt_ventoux.dtb \ | ||
| 172 | am43x-epos-evm.dtb | ||
| 158 | dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb | 173 | dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb |
| 159 | dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb | 174 | dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb |
| 160 | dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ | 175 | dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ |
| 161 | hrefprev60.dtb \ | 176 | hrefprev60.dtb \ |
| 162 | hrefv60plus.dtb \ | 177 | hrefv60plus.dtb \ |
| 178 | ccu8540.dtb \ | ||
| 163 | ccu9540.dtb | 179 | ccu9540.dtb |
| 180 | dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb | ||
| 164 | dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ | 181 | dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ |
| 165 | r8a7740-armadillo800eva.dtb \ | 182 | r8a7740-armadillo800eva.dtb \ |
| 166 | r8a7778-bockw.dtb \ | 183 | r8a7778-bockw.dtb \ |
| 184 | r8a7740-armadillo800eva-reference.dtb \ | ||
| 167 | r8a7779-marzen-reference.dtb \ | 185 | r8a7779-marzen-reference.dtb \ |
| 168 | r8a7790-lager.dtb \ | 186 | r8a7790-lager.dtb \ |
| 169 | sh73a0-kzm9g.dtb \ | 187 | sh73a0-kzm9g.dtb \ |
| @@ -183,6 +201,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ | |||
| 183 | sun4i-a10-cubieboard.dtb \ | 201 | sun4i-a10-cubieboard.dtb \ |
| 184 | sun4i-a10-mini-xplus.dtb \ | 202 | sun4i-a10-mini-xplus.dtb \ |
| 185 | sun4i-a10-hackberry.dtb \ | 203 | sun4i-a10-hackberry.dtb \ |
| 204 | sun5i-a10s-olinuxino-micro.dtb \ | ||
| 186 | sun5i-a13-olinuxino.dtb | 205 | sun5i-a13-olinuxino.dtb |
| 187 | dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ | 206 | dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ |
| 188 | tegra20-iris-512.dtb \ | 207 | tegra20-iris-512.dtb \ |
| @@ -210,8 +229,11 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb | |||
| 210 | dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ | 229 | dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \ |
| 211 | wm8505-ref.dtb \ | 230 | wm8505-ref.dtb \ |
| 212 | wm8650-mid.dtb \ | 231 | wm8650-mid.dtb \ |
| 232 | wm8750-apc8750.dtb \ | ||
| 213 | wm8850-w70v2.dtb | 233 | wm8850-w70v2.dtb |
| 214 | dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb | 234 | dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ |
| 235 | zynq-zc706.dtb \ | ||
| 236 | zynq-zed.dtb | ||
| 215 | 237 | ||
| 216 | targets += dtbs | 238 | targets += dtbs |
| 217 | targets += $(dtb-y) | 239 | targets += $(dtb-y) |
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 5302f79c05b7..04feaf8f1420 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "am33xx.dtsi" | 10 | #include "am33xx.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI AM335x BeagleBone"; | 13 | model = "TI AM335x BeagleBone"; |
| @@ -26,24 +26,104 @@ | |||
| 26 | 26 | ||
| 27 | am33xx_pinmux: pinmux@44e10800 { | 27 | am33xx_pinmux: pinmux@44e10800 { |
| 28 | pinctrl-names = "default"; | 28 | pinctrl-names = "default"; |
| 29 | pinctrl-0 = <&user_leds_s0>; | 29 | pinctrl-0 = <&clkout2_pin>; |
| 30 | 30 | ||
| 31 | user_leds_s0: user_leds_s0 { | 31 | user_leds_s0: user_leds_s0 { |
| 32 | pinctrl-single,pins = < | 32 | pinctrl-single,pins = < |
| 33 | 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */ | 33 | 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ |
| 34 | 0x58 0x17 /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */ | 34 | 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ |
| 35 | 0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */ | 35 | 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ |
| 36 | 0x60 0x17 /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */ | 36 | 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ |
| 37 | >; | ||
| 38 | }; | ||
| 39 | |||
| 40 | i2c0_pins: pinmux_i2c0_pins { | ||
| 41 | pinctrl-single,pins = < | ||
| 42 | 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | ||
| 43 | 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | ||
| 44 | >; | ||
| 45 | }; | ||
| 46 | |||
| 47 | uart0_pins: pinmux_uart0_pins { | ||
| 48 | pinctrl-single,pins = < | ||
| 49 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | ||
| 50 | 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ | ||
| 51 | >; | ||
| 52 | }; | ||
| 53 | |||
| 54 | clkout2_pin: pinmux_clkout2_pin { | ||
| 55 | pinctrl-single,pins = < | ||
| 56 | 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ | ||
| 57 | >; | ||
| 58 | }; | ||
| 59 | |||
| 60 | cpsw_default: cpsw_default { | ||
| 61 | pinctrl-single,pins = < | ||
| 62 | /* Slave 1 */ | ||
| 63 | 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ | ||
| 64 | 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ | ||
| 65 | 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ | ||
| 66 | 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ | ||
| 67 | 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ | ||
| 68 | 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ | ||
| 69 | 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ | ||
| 70 | 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ | ||
| 71 | 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ | ||
| 72 | 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ | ||
| 73 | 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ | ||
| 74 | 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ | ||
| 75 | 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ | ||
| 76 | >; | ||
| 77 | }; | ||
| 78 | |||
| 79 | cpsw_sleep: cpsw_sleep { | ||
| 80 | pinctrl-single,pins = < | ||
| 81 | /* Slave 1 reset value */ | ||
| 82 | 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 83 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 84 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 85 | 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 86 | 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 87 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 88 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 89 | 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 90 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 91 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 92 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 93 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 94 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 95 | >; | ||
| 96 | }; | ||
| 97 | |||
| 98 | davinci_mdio_default: davinci_mdio_default { | ||
| 99 | pinctrl-single,pins = < | ||
| 100 | /* MDIO */ | ||
| 101 | 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | ||
| 102 | 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | ||
| 103 | >; | ||
| 104 | }; | ||
| 105 | |||
| 106 | davinci_mdio_sleep: davinci_mdio_sleep { | ||
| 107 | pinctrl-single,pins = < | ||
| 108 | /* MDIO reset value */ | ||
| 109 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 110 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 37 | >; | 111 | >; |
| 38 | }; | 112 | }; |
| 39 | }; | 113 | }; |
| 40 | 114 | ||
| 41 | ocp { | 115 | ocp { |
| 42 | uart1: serial@44e09000 { | 116 | uart0: serial@44e09000 { |
| 117 | pinctrl-names = "default"; | ||
| 118 | pinctrl-0 = <&uart0_pins>; | ||
| 119 | |||
| 43 | status = "okay"; | 120 | status = "okay"; |
| 44 | }; | 121 | }; |
| 45 | 122 | ||
| 46 | i2c0: i2c@44e0b000 { | 123 | i2c0: i2c@44e0b000 { |
| 124 | pinctrl-names = "default"; | ||
| 125 | pinctrl-0 = <&i2c0_pins>; | ||
| 126 | |||
| 47 | status = "okay"; | 127 | status = "okay"; |
| 48 | clock-frequency = <400000>; | 128 | clock-frequency = <400000>; |
| 49 | 129 | ||
| @@ -55,31 +135,34 @@ | |||
| 55 | }; | 135 | }; |
| 56 | 136 | ||
| 57 | leds { | 137 | leds { |
| 138 | pinctrl-names = "default"; | ||
| 139 | pinctrl-0 = <&user_leds_s0>; | ||
| 140 | |||
| 58 | compatible = "gpio-leds"; | 141 | compatible = "gpio-leds"; |
| 59 | 142 | ||
| 60 | led@2 { | 143 | led@2 { |
| 61 | label = "beaglebone:green:heartbeat"; | 144 | label = "beaglebone:green:heartbeat"; |
| 62 | gpios = <&gpio1 21 0>; | 145 | gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; |
| 63 | linux,default-trigger = "heartbeat"; | 146 | linux,default-trigger = "heartbeat"; |
| 64 | default-state = "off"; | 147 | default-state = "off"; |
| 65 | }; | 148 | }; |
| 66 | 149 | ||
| 67 | led@3 { | 150 | led@3 { |
| 68 | label = "beaglebone:green:mmc0"; | 151 | label = "beaglebone:green:mmc0"; |
| 69 | gpios = <&gpio1 22 0>; | 152 | gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; |
| 70 | linux,default-trigger = "mmc0"; | 153 | linux,default-trigger = "mmc0"; |
| 71 | default-state = "off"; | 154 | default-state = "off"; |
| 72 | }; | 155 | }; |
| 73 | 156 | ||
| 74 | led@4 { | 157 | led@4 { |
| 75 | label = "beaglebone:green:usr2"; | 158 | label = "beaglebone:green:usr2"; |
| 76 | gpios = <&gpio1 23 0>; | 159 | gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; |
| 77 | default-state = "off"; | 160 | default-state = "off"; |
| 78 | }; | 161 | }; |
| 79 | 162 | ||
| 80 | led@5 { | 163 | led@5 { |
| 81 | label = "beaglebone:green:usr3"; | 164 | label = "beaglebone:green:usr3"; |
| 82 | gpios = <&gpio1 24 0>; | 165 | gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; |
| 83 | default-state = "off"; | 166 | default-state = "off"; |
| 84 | }; | 167 | }; |
| 85 | }; | 168 | }; |
| @@ -136,3 +219,16 @@ | |||
| 136 | &cpsw_emac1 { | 219 | &cpsw_emac1 { |
| 137 | phy_id = <&davinci_mdio>, <1>; | 220 | phy_id = <&davinci_mdio>, <1>; |
| 138 | }; | 221 | }; |
| 222 | |||
| 223 | &mac { | ||
| 224 | pinctrl-names = "default", "sleep"; | ||
| 225 | pinctrl-0 = <&cpsw_default>; | ||
| 226 | pinctrl-1 = <&cpsw_sleep>; | ||
| 227 | |||
| 228 | }; | ||
| 229 | |||
| 230 | &davinci_mdio { | ||
| 231 | pinctrl-names = "default", "sleep"; | ||
| 232 | pinctrl-0 = <&davinci_mdio_default>; | ||
| 233 | pinctrl-1 = <&davinci_mdio_sleep>; | ||
| 234 | }; | ||
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 0423298a26fe..a16bb9691cc6 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "am33xx.dtsi" | 10 | #include "am33xx.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI AM335x EVM"; | 13 | model = "TI AM335x EVM"; |
| @@ -26,32 +26,143 @@ | |||
| 26 | 26 | ||
| 27 | am33xx_pinmux: pinmux@44e10800 { | 27 | am33xx_pinmux: pinmux@44e10800 { |
| 28 | pinctrl-names = "default"; | 28 | pinctrl-names = "default"; |
| 29 | pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>; | 29 | pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; |
| 30 | 30 | ||
| 31 | matrix_keypad_s0: matrix_keypad_s0 { | 31 | matrix_keypad_s0: matrix_keypad_s0 { |
| 32 | pinctrl-single,pins = < | 32 | pinctrl-single,pins = < |
| 33 | 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */ | 33 | 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ |
| 34 | 0x58 0x7 /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */ | 34 | 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ |
| 35 | 0x64 0x27 /* gpmc_a9.gpio1_25, INPUT | MODE7 */ | 35 | 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ |
| 36 | 0x68 0x27 /* gpmc_a10.gpio1_26, INPUT | MODE7 */ | 36 | 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ |
| 37 | 0x6c 0x27 /* gpmc_a11.gpio1_27, INPUT | MODE7 */ | 37 | 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ |
| 38 | >; | 38 | >; |
| 39 | }; | 39 | }; |
| 40 | 40 | ||
| 41 | volume_keys_s0: volume_keys_s0 { | 41 | volume_keys_s0: volume_keys_s0 { |
| 42 | pinctrl-single,pins = < | 42 | pinctrl-single,pins = < |
| 43 | 0x150 0x27 /* spi0_sclk.gpio0_2, INPUT | MODE7 */ | 43 | 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ |
| 44 | 0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */ | 44 | 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ |
| 45 | >; | ||
| 46 | }; | ||
| 47 | |||
| 48 | i2c0_pins: pinmux_i2c0_pins { | ||
| 49 | pinctrl-single,pins = < | ||
| 50 | 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | ||
| 51 | 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | ||
| 52 | >; | ||
| 53 | }; | ||
| 54 | |||
| 55 | i2c1_pins: pinmux_i2c1_pins { | ||
| 56 | pinctrl-single,pins = < | ||
| 57 | 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ | ||
| 58 | 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ | ||
| 59 | >; | ||
| 60 | }; | ||
| 61 | |||
| 62 | uart0_pins: pinmux_uart0_pins { | ||
| 63 | pinctrl-single,pins = < | ||
| 64 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | ||
| 65 | 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ | ||
| 66 | >; | ||
| 67 | }; | ||
| 68 | |||
| 69 | clkout2_pin: pinmux_clkout2_pin { | ||
| 70 | pinctrl-single,pins = < | ||
| 71 | 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ | ||
| 72 | >; | ||
| 73 | }; | ||
| 74 | |||
| 75 | nandflash_pins_s0: nandflash_pins_s0 { | ||
| 76 | pinctrl-single,pins = < | ||
| 77 | 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ | ||
| 78 | 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ | ||
| 79 | 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ | ||
| 80 | 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ | ||
| 81 | 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ | ||
| 82 | 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ | ||
| 83 | 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ | ||
| 84 | 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ | ||
| 85 | 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ | ||
| 86 | 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ | ||
| 87 | 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ | ||
| 88 | 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ | ||
| 89 | 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ | ||
| 90 | 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ | ||
| 91 | 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ | ||
| 92 | >; | ||
| 93 | }; | ||
| 94 | |||
| 95 | ecap0_pins: backlight_pins { | ||
| 96 | pinctrl-single,pins = < | ||
| 97 | 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ | ||
| 98 | >; | ||
| 99 | }; | ||
| 100 | |||
| 101 | cpsw_default: cpsw_default { | ||
| 102 | pinctrl-single,pins = < | ||
| 103 | /* Slave 1 */ | ||
| 104 | 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ | ||
| 105 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ | ||
| 106 | 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ | ||
| 107 | 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ | ||
| 108 | 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ | ||
| 109 | 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ | ||
| 110 | 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ | ||
| 111 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ | ||
| 112 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ | ||
| 113 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ | ||
| 114 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ | ||
| 115 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ | ||
| 116 | >; | ||
| 117 | }; | ||
| 118 | |||
| 119 | cpsw_sleep: cpsw_sleep { | ||
| 120 | pinctrl-single,pins = < | ||
| 121 | /* Slave 1 reset value */ | ||
| 122 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 123 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 124 | 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 125 | 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 126 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 127 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 128 | 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 129 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 130 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 131 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 132 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 133 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 134 | >; | ||
| 135 | }; | ||
| 136 | |||
| 137 | davinci_mdio_default: davinci_mdio_default { | ||
| 138 | pinctrl-single,pins = < | ||
| 139 | /* MDIO */ | ||
| 140 | 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | ||
| 141 | 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | ||
| 142 | >; | ||
| 143 | }; | ||
| 144 | |||
| 145 | davinci_mdio_sleep: davinci_mdio_sleep { | ||
| 146 | pinctrl-single,pins = < | ||
| 147 | /* MDIO reset value */ | ||
| 148 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 149 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 45 | >; | 150 | >; |
| 46 | }; | 151 | }; |
| 47 | }; | 152 | }; |
| 48 | 153 | ||
| 49 | ocp { | 154 | ocp { |
| 50 | uart1: serial@44e09000 { | 155 | uart0: serial@44e09000 { |
| 156 | pinctrl-names = "default"; | ||
| 157 | pinctrl-0 = <&uart0_pins>; | ||
| 158 | |||
| 51 | status = "okay"; | 159 | status = "okay"; |
| 52 | }; | 160 | }; |
| 53 | 161 | ||
| 54 | i2c0: i2c@44e0b000 { | 162 | i2c0: i2c@44e0b000 { |
| 163 | pinctrl-names = "default"; | ||
| 164 | pinctrl-0 = <&i2c0_pins>; | ||
| 165 | |||
| 55 | status = "okay"; | 166 | status = "okay"; |
| 56 | clock-frequency = <400000>; | 167 | clock-frequency = <400000>; |
| 57 | 168 | ||
| @@ -61,6 +172,9 @@ | |||
| 61 | }; | 172 | }; |
| 62 | 173 | ||
| 63 | i2c1: i2c@4802a000 { | 174 | i2c1: i2c@4802a000 { |
| 175 | pinctrl-names = "default"; | ||
| 176 | pinctrl-0 = <&i2c1_pins>; | ||
| 177 | |||
| 64 | status = "okay"; | 178 | status = "okay"; |
| 65 | clock-frequency = <100000>; | 179 | clock-frequency = <100000>; |
| 66 | 180 | ||
| @@ -102,6 +216,101 @@ | |||
| 102 | reg = <0x48>; | 216 | reg = <0x48>; |
| 103 | }; | 217 | }; |
| 104 | }; | 218 | }; |
| 219 | |||
| 220 | elm: elm@48080000 { | ||
| 221 | status = "okay"; | ||
| 222 | }; | ||
| 223 | |||
| 224 | epwmss0: epwmss@48300000 { | ||
| 225 | status = "okay"; | ||
| 226 | |||
| 227 | ecap0: ecap@48300100 { | ||
| 228 | status = "okay"; | ||
| 229 | pinctrl-names = "default"; | ||
| 230 | pinctrl-0 = <&ecap0_pins>; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | |||
| 234 | gpmc: gpmc@50000000 { | ||
| 235 | status = "okay"; | ||
| 236 | pinctrl-names = "default"; | ||
| 237 | pinctrl-0 = <&nandflash_pins_s0>; | ||
| 238 | ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ | ||
| 239 | nand@0,0 { | ||
| 240 | reg = <0 0 0>; /* CS0, offset 0 */ | ||
| 241 | nand-bus-width = <8>; | ||
| 242 | ti,nand-ecc-opt = "bch8"; | ||
| 243 | gpmc,device-nand = "true"; | ||
| 244 | gpmc,device-width = <1>; | ||
| 245 | gpmc,sync-clk-ps = <0>; | ||
| 246 | gpmc,cs-on-ns = <0>; | ||
| 247 | gpmc,cs-rd-off-ns = <44>; | ||
| 248 | gpmc,cs-wr-off-ns = <44>; | ||
| 249 | gpmc,adv-on-ns = <6>; | ||
| 250 | gpmc,adv-rd-off-ns = <34>; | ||
| 251 | gpmc,adv-wr-off-ns = <44>; | ||
| 252 | gpmc,we-on-ns = <0>; | ||
| 253 | gpmc,we-off-ns = <40>; | ||
| 254 | gpmc,oe-on-ns = <0>; | ||
| 255 | gpmc,oe-off-ns = <54>; | ||
| 256 | gpmc,access-ns = <64>; | ||
| 257 | gpmc,rd-cycle-ns = <82>; | ||
| 258 | gpmc,wr-cycle-ns = <82>; | ||
| 259 | gpmc,wait-on-read = "true"; | ||
| 260 | gpmc,wait-on-write = "true"; | ||
| 261 | gpmc,bus-turnaround-ns = <0>; | ||
| 262 | gpmc,cycle2cycle-delay-ns = <0>; | ||
| 263 | gpmc,clk-activation-ns = <0>; | ||
| 264 | gpmc,wait-monitoring-ns = <0>; | ||
| 265 | gpmc,wr-access-ns = <40>; | ||
| 266 | gpmc,wr-data-mux-bus-ns = <0>; | ||
| 267 | |||
| 268 | #address-cells = <1>; | ||
| 269 | #size-cells = <1>; | ||
| 270 | elm_id = <&elm>; | ||
| 271 | |||
| 272 | /* MTD partition table */ | ||
| 273 | partition@0 { | ||
| 274 | label = "SPL1"; | ||
| 275 | reg = <0x00000000 0x000020000>; | ||
| 276 | }; | ||
| 277 | |||
| 278 | partition@1 { | ||
| 279 | label = "SPL2"; | ||
| 280 | reg = <0x00020000 0x00020000>; | ||
| 281 | }; | ||
| 282 | |||
| 283 | partition@2 { | ||
| 284 | label = "SPL3"; | ||
| 285 | reg = <0x00040000 0x00020000>; | ||
| 286 | }; | ||
| 287 | |||
| 288 | partition@3 { | ||
| 289 | label = "SPL4"; | ||
| 290 | reg = <0x00060000 0x00020000>; | ||
| 291 | }; | ||
| 292 | |||
| 293 | partition@4 { | ||
| 294 | label = "U-boot"; | ||
| 295 | reg = <0x00080000 0x001e0000>; | ||
| 296 | }; | ||
| 297 | |||
| 298 | partition@5 { | ||
| 299 | label = "environment"; | ||
| 300 | reg = <0x00260000 0x00020000>; | ||
| 301 | }; | ||
| 302 | |||
| 303 | partition@6 { | ||
| 304 | label = "Kernel"; | ||
| 305 | reg = <0x00280000 0x00500000>; | ||
| 306 | }; | ||
| 307 | |||
| 308 | partition@7 { | ||
| 309 | label = "File-System"; | ||
| 310 | reg = <0x00780000 0x0F880000>; | ||
| 311 | }; | ||
| 312 | }; | ||
| 313 | }; | ||
| 105 | }; | 314 | }; |
| 106 | 315 | ||
| 107 | vbat: fixedregulator@0 { | 316 | vbat: fixedregulator@0 { |
| @@ -123,12 +332,12 @@ | |||
| 123 | debounce-delay-ms = <5>; | 332 | debounce-delay-ms = <5>; |
| 124 | col-scan-delay-us = <2>; | 333 | col-scan-delay-us = <2>; |
| 125 | 334 | ||
| 126 | row-gpios = <&gpio1 25 0 /* Bank1, pin25 */ | 335 | row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ |
| 127 | &gpio1 26 0 /* Bank1, pin26 */ | 336 | &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ |
| 128 | &gpio1 27 0>; /* Bank1, pin27 */ | 337 | &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ |
| 129 | 338 | ||
| 130 | col-gpios = <&gpio1 21 0 /* Bank1, pin21 */ | 339 | col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ |
| 131 | &gpio1 22 0>; /* Bank1, pin22 */ | 340 | &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ |
| 132 | 341 | ||
| 133 | linux,keymap = <0x0000008b /* MENU */ | 342 | linux,keymap = <0x0000008b /* MENU */ |
| 134 | 0x0100009e /* BACK */ | 343 | 0x0100009e /* BACK */ |
| @@ -147,20 +356,27 @@ | |||
| 147 | switch@9 { | 356 | switch@9 { |
| 148 | label = "volume-up"; | 357 | label = "volume-up"; |
| 149 | linux,code = <115>; | 358 | linux,code = <115>; |
| 150 | gpios = <&gpio0 2 1>; | 359 | gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; |
| 151 | gpio-key,wakeup; | 360 | gpio-key,wakeup; |
| 152 | }; | 361 | }; |
| 153 | 362 | ||
| 154 | switch@10 { | 363 | switch@10 { |
| 155 | label = "volume-down"; | 364 | label = "volume-down"; |
| 156 | linux,code = <114>; | 365 | linux,code = <114>; |
| 157 | gpios = <&gpio0 3 1>; | 366 | gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; |
| 158 | gpio-key,wakeup; | 367 | gpio-key,wakeup; |
| 159 | }; | 368 | }; |
| 160 | }; | 369 | }; |
| 370 | |||
| 371 | backlight { | ||
| 372 | compatible = "pwm-backlight"; | ||
| 373 | pwms = <&ecap0 0 50000 0>; | ||
| 374 | brightness-levels = <0 51 53 56 62 75 101 152 255>; | ||
| 375 | default-brightness-level = <8>; | ||
| 376 | }; | ||
| 161 | }; | 377 | }; |
| 162 | 378 | ||
| 163 | /include/ "tps65910.dtsi" | 379 | #include "tps65910.dtsi" |
| 164 | 380 | ||
| 165 | &tps { | 381 | &tps { |
| 166 | vcc1-supply = <&vbat>; | 382 | vcc1-supply = <&vbat>; |
| @@ -237,6 +453,18 @@ | |||
| 237 | }; | 453 | }; |
| 238 | }; | 454 | }; |
| 239 | 455 | ||
| 456 | &mac { | ||
| 457 | pinctrl-names = "default", "sleep"; | ||
| 458 | pinctrl-0 = <&cpsw_default>; | ||
| 459 | pinctrl-1 = <&cpsw_sleep>; | ||
| 460 | }; | ||
| 461 | |||
| 462 | &davinci_mdio { | ||
| 463 | pinctrl-names = "default", "sleep"; | ||
| 464 | pinctrl-0 = <&davinci_mdio_default>; | ||
| 465 | pinctrl-1 = <&davinci_mdio_sleep>; | ||
| 466 | }; | ||
| 467 | |||
| 240 | &cpsw_emac0 { | 468 | &cpsw_emac0 { |
| 241 | phy_id = <&davinci_mdio>, <0>; | 469 | phy_id = <&davinci_mdio>, <0>; |
| 242 | }; | 470 | }; |
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index f67c360844f4..9e00eef9b74b 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts | |||
| @@ -13,7 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | 15 | ||
| 16 | /include/ "am33xx.dtsi" | 16 | #include "am33xx.dtsi" |
| 17 | 17 | ||
| 18 | / { | 18 | / { |
| 19 | model = "TI AM335x EVM-SK"; | 19 | model = "TI AM335x EVM-SK"; |
| @@ -32,33 +32,145 @@ | |||
| 32 | 32 | ||
| 33 | am33xx_pinmux: pinmux@44e10800 { | 33 | am33xx_pinmux: pinmux@44e10800 { |
| 34 | pinctrl-names = "default"; | 34 | pinctrl-names = "default"; |
| 35 | pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>; | 35 | pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; |
| 36 | 36 | ||
| 37 | user_leds_s0: user_leds_s0 { | 37 | user_leds_s0: user_leds_s0 { |
| 38 | pinctrl-single,pins = < | 38 | pinctrl-single,pins = < |
| 39 | 0x10 0x7 /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */ | 39 | 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ |
| 40 | 0x14 0x7 /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */ | 40 | 0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ |
| 41 | 0x18 0x7 /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */ | 41 | 0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ |
| 42 | 0x1c 0x7 /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */ | 42 | 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ |
| 43 | >; | 43 | >; |
| 44 | }; | 44 | }; |
| 45 | 45 | ||
| 46 | gpio_keys_s0: gpio_keys_s0 { | 46 | gpio_keys_s0: gpio_keys_s0 { |
| 47 | pinctrl-single,pins = < | 47 | pinctrl-single,pins = < |
| 48 | 0x94 0x27 /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */ | 48 | 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ |
| 49 | 0x90 0x27 /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */ | 49 | 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ |
| 50 | 0x70 0x27 /* gpmc_wait0.gpio0_30, INPUT | MODE7 */ | 50 | 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ |
| 51 | 0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */ | 51 | 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ |
| 52 | >; | ||
| 53 | }; | ||
| 54 | |||
| 55 | i2c0_pins: pinmux_i2c0_pins { | ||
| 56 | pinctrl-single,pins = < | ||
| 57 | 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ | ||
| 58 | 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ | ||
| 59 | >; | ||
| 60 | }; | ||
| 61 | |||
| 62 | uart0_pins: pinmux_uart0_pins { | ||
| 63 | pinctrl-single,pins = < | ||
| 64 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ | ||
| 65 | 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ | ||
| 66 | >; | ||
| 67 | }; | ||
| 68 | |||
| 69 | clkout2_pin: pinmux_clkout2_pin { | ||
| 70 | pinctrl-single,pins = < | ||
| 71 | 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ | ||
| 72 | >; | ||
| 73 | }; | ||
| 74 | |||
| 75 | ecap2_pins: backlight_pins { | ||
| 76 | pinctrl-single,pins = < | ||
| 77 | 0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */ | ||
| 78 | >; | ||
| 79 | }; | ||
| 80 | |||
| 81 | cpsw_default: cpsw_default { | ||
| 82 | pinctrl-single,pins = < | ||
| 83 | /* Slave 1 */ | ||
| 84 | 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ | ||
| 85 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ | ||
| 86 | 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ | ||
| 87 | 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ | ||
| 88 | 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ | ||
| 89 | 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ | ||
| 90 | 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ | ||
| 91 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ | ||
| 92 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ | ||
| 93 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ | ||
| 94 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ | ||
| 95 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ | ||
| 96 | |||
| 97 | /* Slave 2 */ | ||
| 98 | 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ | ||
| 99 | 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ | ||
| 100 | 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ | ||
| 101 | 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ | ||
| 102 | 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ | ||
| 103 | 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ | ||
| 104 | 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ | ||
| 105 | 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ | ||
| 106 | 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ | ||
| 107 | 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ | ||
| 108 | 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ | ||
| 109 | 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ | ||
| 110 | >; | ||
| 111 | }; | ||
| 112 | |||
| 113 | cpsw_sleep: cpsw_sleep { | ||
| 114 | pinctrl-single,pins = < | ||
| 115 | /* Slave 1 reset value */ | ||
| 116 | 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 117 | 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 118 | 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 119 | 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 120 | 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 121 | 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 122 | 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 123 | 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 124 | 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 125 | 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 126 | 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 127 | 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 128 | |||
| 129 | /* Slave 2 reset value*/ | ||
| 130 | 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 131 | 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 132 | 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 133 | 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 134 | 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 135 | 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 136 | 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 137 | 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 138 | 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 139 | 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 140 | 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 141 | 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 142 | >; | ||
| 143 | }; | ||
| 144 | |||
| 145 | davinci_mdio_default: davinci_mdio_default { | ||
| 146 | pinctrl-single,pins = < | ||
| 147 | /* MDIO */ | ||
| 148 | 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ | ||
| 149 | 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ | ||
| 150 | >; | ||
| 151 | }; | ||
| 152 | |||
| 153 | davinci_mdio_sleep: davinci_mdio_sleep { | ||
| 154 | pinctrl-single,pins = < | ||
| 155 | /* MDIO reset value */ | ||
| 156 | 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 157 | 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) | ||
| 52 | >; | 158 | >; |
| 53 | }; | 159 | }; |
| 54 | }; | 160 | }; |
| 55 | 161 | ||
| 56 | ocp { | 162 | ocp { |
| 57 | uart1: serial@44e09000 { | 163 | uart0: serial@44e09000 { |
| 164 | pinctrl-names = "default"; | ||
| 165 | pinctrl-0 = <&uart0_pins>; | ||
| 166 | |||
| 58 | status = "okay"; | 167 | status = "okay"; |
| 59 | }; | 168 | }; |
| 60 | 169 | ||
| 61 | i2c0: i2c@44e0b000 { | 170 | i2c0: i2c@44e0b000 { |
| 171 | pinctrl-names = "default"; | ||
| 172 | pinctrl-0 = <&i2c0_pins>; | ||
| 173 | |||
| 62 | status = "okay"; | 174 | status = "okay"; |
| 63 | clock-frequency = <400000>; | 175 | clock-frequency = <400000>; |
| 64 | 176 | ||
| @@ -94,6 +206,16 @@ | |||
| 94 | st,max-limit-z = <750>; | 206 | st,max-limit-z = <750>; |
| 95 | }; | 207 | }; |
| 96 | }; | 208 | }; |
| 209 | |||
| 210 | epwmss2: epwmss@48304000 { | ||
| 211 | status = "okay"; | ||
| 212 | |||
| 213 | ecap2: ecap@48304100 { | ||
| 214 | status = "okay"; | ||
| 215 | pinctrl-names = "default"; | ||
| 216 | pinctrl-0 = <&ecap2_pins>; | ||
| 217 | }; | ||
| 218 | }; | ||
| 97 | }; | 219 | }; |
| 98 | 220 | ||
| 99 | vbat: fixedregulator@0 { | 221 | vbat: fixedregulator@0 { |
| @@ -111,30 +233,33 @@ | |||
| 111 | }; | 233 | }; |
| 112 | 234 | ||
| 113 | leds { | 235 | leds { |
| 236 | pinctrl-names = "default"; | ||
| 237 | pinctrl-0 = <&user_leds_s0>; | ||
| 238 | |||
| 114 | compatible = "gpio-leds"; | 239 | compatible = "gpio-leds"; |
| 115 | 240 | ||
| 116 | led@1 { | 241 | led@1 { |
| 117 | label = "evmsk:green:usr0"; | 242 | label = "evmsk:green:usr0"; |
| 118 | gpios = <&gpio1 4 0>; | 243 | gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; |
| 119 | default-state = "off"; | 244 | default-state = "off"; |
| 120 | }; | 245 | }; |
| 121 | 246 | ||
| 122 | led@2 { | 247 | led@2 { |
| 123 | label = "evmsk:green:usr1"; | 248 | label = "evmsk:green:usr1"; |
| 124 | gpios = <&gpio1 5 0>; | 249 | gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
| 125 | default-state = "off"; | 250 | default-state = "off"; |
| 126 | }; | 251 | }; |
| 127 | 252 | ||
| 128 | led@3 { | 253 | led@3 { |
| 129 | label = "evmsk:green:mmc0"; | 254 | label = "evmsk:green:mmc0"; |
| 130 | gpios = <&gpio1 6 0>; | 255 | gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; |
| 131 | linux,default-trigger = "mmc0"; | 256 | linux,default-trigger = "mmc0"; |
| 132 | default-state = "off"; | 257 | default-state = "off"; |
| 133 | }; | 258 | }; |
| 134 | 259 | ||
| 135 | led@4 { | 260 | led@4 { |
| 136 | label = "evmsk:green:heartbeat"; | 261 | label = "evmsk:green:heartbeat"; |
| 137 | gpios = <&gpio1 7 0>; | 262 | gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
| 138 | linux,default-trigger = "heartbeat"; | 263 | linux,default-trigger = "heartbeat"; |
| 139 | default-state = "off"; | 264 | default-state = "off"; |
| 140 | }; | 265 | }; |
| @@ -148,31 +273,38 @@ | |||
| 148 | switch@1 { | 273 | switch@1 { |
| 149 | label = "button0"; | 274 | label = "button0"; |
| 150 | linux,code = <0x100>; | 275 | linux,code = <0x100>; |
| 151 | gpios = <&gpio2 3 0>; | 276 | gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; |
| 152 | }; | 277 | }; |
| 153 | 278 | ||
| 154 | switch@2 { | 279 | switch@2 { |
| 155 | label = "button1"; | 280 | label = "button1"; |
| 156 | linux,code = <0x101>; | 281 | linux,code = <0x101>; |
| 157 | gpios = <&gpio2 2 0>; | 282 | gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; |
| 158 | }; | 283 | }; |
| 159 | 284 | ||
| 160 | switch@3 { | 285 | switch@3 { |
| 161 | label = "button2"; | 286 | label = "button2"; |
| 162 | linux,code = <0x102>; | 287 | linux,code = <0x102>; |
| 163 | gpios = <&gpio0 30 0>; | 288 | gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; |
| 164 | gpio-key,wakeup; | 289 | gpio-key,wakeup; |
| 165 | }; | 290 | }; |
| 166 | 291 | ||
| 167 | switch@4 { | 292 | switch@4 { |
| 168 | label = "button3"; | 293 | label = "button3"; |
| 169 | linux,code = <0x103>; | 294 | linux,code = <0x103>; |
| 170 | gpios = <&gpio2 5 0>; | 295 | gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; |
| 171 | }; | 296 | }; |
| 172 | }; | 297 | }; |
| 298 | |||
| 299 | backlight { | ||
| 300 | compatible = "pwm-backlight"; | ||
| 301 | pwms = <&ecap2 0 50000 1>; | ||
| 302 | brightness-levels = <0 58 61 66 75 90 125 170 255>; | ||
| 303 | default-brightness-level = <8>; | ||
| 304 | }; | ||
| 173 | }; | 305 | }; |
| 174 | 306 | ||
| 175 | /include/ "tps65910.dtsi" | 307 | #include "tps65910.dtsi" |
| 176 | 308 | ||
| 177 | &tps { | 309 | &tps { |
| 178 | vcc1-supply = <&vbat>; | 310 | vcc1-supply = <&vbat>; |
| @@ -248,3 +380,15 @@ | |||
| 248 | }; | 380 | }; |
| 249 | }; | 381 | }; |
| 250 | }; | 382 | }; |
| 383 | |||
| 384 | &mac { | ||
| 385 | pinctrl-names = "default", "sleep"; | ||
| 386 | pinctrl-0 = <&cpsw_default>; | ||
| 387 | pinctrl-1 = <&cpsw_sleep>; | ||
| 388 | }; | ||
| 389 | |||
| 390 | &davinci_mdio { | ||
| 391 | pinctrl-names = "default", "sleep"; | ||
| 392 | pinctrl-0 = <&davinci_mdio_default>; | ||
| 393 | pinctrl-1 = <&davinci_mdio_sleep>; | ||
| 394 | }; | ||
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 77aa1b0cf6a7..0d4df90477f7 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi | |||
| @@ -8,26 +8,33 @@ | |||
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "skeleton.dtsi" | 11 | #include <dt-bindings/gpio/gpio.h> |
| 12 | #include <dt-bindings/pinctrl/am33xx.h> | ||
| 13 | |||
| 14 | #include "skeleton.dtsi" | ||
| 12 | 15 | ||
| 13 | / { | 16 | / { |
| 14 | compatible = "ti,am33xx"; | 17 | compatible = "ti,am33xx"; |
| 15 | interrupt-parent = <&intc>; | 18 | interrupt-parent = <&intc>; |
| 16 | 19 | ||
| 17 | aliases { | 20 | aliases { |
| 18 | serial0 = &uart1; | 21 | serial0 = &uart0; |
| 19 | serial1 = &uart2; | 22 | serial1 = &uart1; |
| 20 | serial2 = &uart3; | 23 | serial2 = &uart2; |
| 21 | serial3 = &uart4; | 24 | serial3 = &uart3; |
| 22 | serial4 = &uart5; | 25 | serial4 = &uart4; |
| 23 | serial5 = &uart6; | 26 | serial5 = &uart5; |
| 24 | d_can0 = &dcan0; | 27 | d_can0 = &dcan0; |
| 25 | d_can1 = &dcan1; | 28 | d_can1 = &dcan1; |
| 26 | }; | 29 | }; |
| 27 | 30 | ||
| 28 | cpus { | 31 | cpus { |
| 32 | #address-cells = <1>; | ||
| 33 | #size-cells = <0>; | ||
| 29 | cpu@0 { | 34 | cpu@0 { |
| 30 | compatible = "arm,cortex-a8"; | 35 | compatible = "arm,cortex-a8"; |
| 36 | device_type = "cpu"; | ||
| 37 | reg = <0>; | ||
| 31 | 38 | ||
| 32 | /* | 39 | /* |
| 33 | * To consider voltage drop between PMIC and SoC, | 40 | * To consider voltage drop between PMIC and SoC, |
| @@ -133,7 +140,7 @@ | |||
| 133 | interrupts = <62>; | 140 | interrupts = <62>; |
| 134 | }; | 141 | }; |
| 135 | 142 | ||
| 136 | uart1: serial@44e09000 { | 143 | uart0: serial@44e09000 { |
| 137 | compatible = "ti,omap3-uart"; | 144 | compatible = "ti,omap3-uart"; |
| 138 | ti,hwmods = "uart1"; | 145 | ti,hwmods = "uart1"; |
| 139 | clock-frequency = <48000000>; | 146 | clock-frequency = <48000000>; |
| @@ -142,7 +149,7 @@ | |||
| 142 | status = "disabled"; | 149 | status = "disabled"; |
| 143 | }; | 150 | }; |
| 144 | 151 | ||
| 145 | uart2: serial@48022000 { | 152 | uart1: serial@48022000 { |
| 146 | compatible = "ti,omap3-uart"; | 153 | compatible = "ti,omap3-uart"; |
| 147 | ti,hwmods = "uart2"; | 154 | ti,hwmods = "uart2"; |
| 148 | clock-frequency = <48000000>; | 155 | clock-frequency = <48000000>; |
| @@ -151,7 +158,7 @@ | |||
| 151 | status = "disabled"; | 158 | status = "disabled"; |
| 152 | }; | 159 | }; |
| 153 | 160 | ||
| 154 | uart3: serial@48024000 { | 161 | uart2: serial@48024000 { |
| 155 | compatible = "ti,omap3-uart"; | 162 | compatible = "ti,omap3-uart"; |
| 156 | ti,hwmods = "uart3"; | 163 | ti,hwmods = "uart3"; |
| 157 | clock-frequency = <48000000>; | 164 | clock-frequency = <48000000>; |
| @@ -160,7 +167,7 @@ | |||
| 160 | status = "disabled"; | 167 | status = "disabled"; |
| 161 | }; | 168 | }; |
| 162 | 169 | ||
| 163 | uart4: serial@481a6000 { | 170 | uart3: serial@481a6000 { |
| 164 | compatible = "ti,omap3-uart"; | 171 | compatible = "ti,omap3-uart"; |
| 165 | ti,hwmods = "uart4"; | 172 | ti,hwmods = "uart4"; |
| 166 | clock-frequency = <48000000>; | 173 | clock-frequency = <48000000>; |
| @@ -169,7 +176,7 @@ | |||
| 169 | status = "disabled"; | 176 | status = "disabled"; |
| 170 | }; | 177 | }; |
| 171 | 178 | ||
| 172 | uart5: serial@481a8000 { | 179 | uart4: serial@481a8000 { |
| 173 | compatible = "ti,omap3-uart"; | 180 | compatible = "ti,omap3-uart"; |
| 174 | ti,hwmods = "uart5"; | 181 | ti,hwmods = "uart5"; |
| 175 | clock-frequency = <48000000>; | 182 | clock-frequency = <48000000>; |
| @@ -178,7 +185,7 @@ | |||
| 178 | status = "disabled"; | 185 | status = "disabled"; |
| 179 | }; | 186 | }; |
| 180 | 187 | ||
| 181 | uart6: serial@481aa000 { | 188 | uart5: serial@481aa000 { |
| 182 | compatible = "ti,omap3-uart"; | 189 | compatible = "ti,omap3-uart"; |
| 183 | ti,hwmods = "uart6"; | 190 | ti,hwmods = "uart6"; |
| 184 | clock-frequency = <48000000>; | 191 | clock-frequency = <48000000>; |
| @@ -343,6 +350,90 @@ | |||
| 343 | ti,hwmods = "usb_otg_hs"; | 350 | ti,hwmods = "usb_otg_hs"; |
| 344 | }; | 351 | }; |
| 345 | 352 | ||
| 353 | epwmss0: epwmss@48300000 { | ||
| 354 | compatible = "ti,am33xx-pwmss"; | ||
| 355 | reg = <0x48300000 0x10>; | ||
| 356 | ti,hwmods = "epwmss0"; | ||
| 357 | #address-cells = <1>; | ||
| 358 | #size-cells = <1>; | ||
| 359 | status = "disabled"; | ||
| 360 | ranges = <0x48300100 0x48300100 0x80 /* ECAP */ | ||
| 361 | 0x48300180 0x48300180 0x80 /* EQEP */ | ||
| 362 | 0x48300200 0x48300200 0x80>; /* EHRPWM */ | ||
| 363 | |||
| 364 | ecap0: ecap@48300100 { | ||
| 365 | compatible = "ti,am33xx-ecap"; | ||
| 366 | #pwm-cells = <3>; | ||
| 367 | reg = <0x48300100 0x80>; | ||
| 368 | ti,hwmods = "ecap0"; | ||
| 369 | status = "disabled"; | ||
| 370 | }; | ||
| 371 | |||
| 372 | ehrpwm0: ehrpwm@48300200 { | ||
| 373 | compatible = "ti,am33xx-ehrpwm"; | ||
| 374 | #pwm-cells = <3>; | ||
| 375 | reg = <0x48300200 0x80>; | ||
| 376 | ti,hwmods = "ehrpwm0"; | ||
| 377 | status = "disabled"; | ||
| 378 | }; | ||
| 379 | }; | ||
| 380 | |||
| 381 | epwmss1: epwmss@48302000 { | ||
| 382 | compatible = "ti,am33xx-pwmss"; | ||
| 383 | reg = <0x48302000 0x10>; | ||
| 384 | ti,hwmods = "epwmss1"; | ||
| 385 | #address-cells = <1>; | ||
| 386 | #size-cells = <1>; | ||
| 387 | status = "disabled"; | ||
| 388 | ranges = <0x48302100 0x48302100 0x80 /* ECAP */ | ||
| 389 | 0x48302180 0x48302180 0x80 /* EQEP */ | ||
| 390 | 0x48302200 0x48302200 0x80>; /* EHRPWM */ | ||
| 391 | |||
| 392 | ecap1: ecap@48302100 { | ||
| 393 | compatible = "ti,am33xx-ecap"; | ||
| 394 | #pwm-cells = <3>; | ||
| 395 | reg = <0x48302100 0x80>; | ||
| 396 | ti,hwmods = "ecap1"; | ||
| 397 | status = "disabled"; | ||
| 398 | }; | ||
| 399 | |||
| 400 | ehrpwm1: ehrpwm@48302200 { | ||
| 401 | compatible = "ti,am33xx-ehrpwm"; | ||
| 402 | #pwm-cells = <3>; | ||
| 403 | reg = <0x48302200 0x80>; | ||
| 404 | ti,hwmods = "ehrpwm1"; | ||
| 405 | status = "disabled"; | ||
| 406 | }; | ||
| 407 | }; | ||
| 408 | |||
| 409 | epwmss2: epwmss@48304000 { | ||
| 410 | compatible = "ti,am33xx-pwmss"; | ||
| 411 | reg = <0x48304000 0x10>; | ||
| 412 | ti,hwmods = "epwmss2"; | ||
| 413 | #address-cells = <1>; | ||
| 414 | #size-cells = <1>; | ||
| 415 | status = "disabled"; | ||
| 416 | ranges = <0x48304100 0x48304100 0x80 /* ECAP */ | ||
| 417 | 0x48304180 0x48304180 0x80 /* EQEP */ | ||
| 418 | 0x48304200 0x48304200 0x80>; /* EHRPWM */ | ||
| 419 | |||
| 420 | ecap2: ecap@48304100 { | ||
| 421 | compatible = "ti,am33xx-ecap"; | ||
| 422 | #pwm-cells = <3>; | ||
| 423 | reg = <0x48304100 0x80>; | ||
| 424 | ti,hwmods = "ecap2"; | ||
| 425 | status = "disabled"; | ||
| 426 | }; | ||
| 427 | |||
| 428 | ehrpwm2: ehrpwm@48304200 { | ||
| 429 | compatible = "ti,am33xx-ehrpwm"; | ||
| 430 | #pwm-cells = <3>; | ||
| 431 | reg = <0x48304200 0x80>; | ||
| 432 | ti,hwmods = "ehrpwm2"; | ||
| 433 | status = "disabled"; | ||
| 434 | }; | ||
| 435 | }; | ||
| 436 | |||
| 346 | mac: ethernet@4a100000 { | 437 | mac: ethernet@4a100000 { |
| 347 | compatible = "ti,cpsw"; | 438 | compatible = "ti,cpsw"; |
| 348 | ti,hwmods = "cpgmac0"; | 439 | ti,hwmods = "cpgmac0"; |
| @@ -403,6 +494,14 @@ | |||
| 403 | ti,hwmods = "wkup_m3"; | 494 | ti,hwmods = "wkup_m3"; |
| 404 | }; | 495 | }; |
| 405 | 496 | ||
| 497 | elm: elm@48080000 { | ||
| 498 | compatible = "ti,am3352-elm"; | ||
| 499 | reg = <0x48080000 0x2000>; | ||
| 500 | interrupts = <4>; | ||
| 501 | ti,hwmods = "elm"; | ||
| 502 | status = "disabled"; | ||
| 503 | }; | ||
| 504 | |||
| 406 | gpmc: gpmc@50000000 { | 505 | gpmc: gpmc@50000000 { |
| 407 | compatible = "ti,am3352-gpmc"; | 506 | compatible = "ti,am3352-gpmc"; |
| 408 | ti,hwmods = "gpmc"; | 507 | ti,hwmods = "gpmc"; |
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index e9b5bdae4908..e99dfaf70052 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap34xx.dtsi" | 10 | #include "omap34xx.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI AM3517 EVM (AM3517/05)"; | 13 | model = "TI AM3517 EVM (AM3517/05)"; |
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts index 556868388a23..fdf5ce63c8e6 100644 --- a/arch/arm/boot/dts/am3517_mt_ventoux.dts +++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap34xx.dtsi" | 10 | #include "omap34xx.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TeeJet Mt.Ventoux"; | 13 | model = "TeeJet Mt.Ventoux"; |
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi new file mode 100644 index 000000000000..ddc1df77ac52 --- /dev/null +++ b/arch/arm/boot/dts/am4372.dtsi | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * Device Tree Source for AM4372 SoC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public License | ||
| 7 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 8 | * kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 12 | |||
| 13 | #include "skeleton.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | compatible = "ti,am4372", "ti,am43"; | ||
| 17 | interrupt-parent = <&gic>; | ||
| 18 | |||
| 19 | |||
| 20 | aliases { | ||
| 21 | serial0 = &uart0; | ||
| 22 | }; | ||
| 23 | |||
| 24 | cpus { | ||
| 25 | cpu@0 { | ||
| 26 | compatible = "arm,cortex-a9"; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | |||
| 30 | gic: interrupt-controller@48241000 { | ||
| 31 | compatible = "arm,cortex-a9-gic"; | ||
| 32 | interrupt-controller; | ||
| 33 | #interrupt-cells = <3>; | ||
| 34 | reg = <0x48241000 0x1000>, | ||
| 35 | <0x48240100 0x0100>; | ||
| 36 | }; | ||
| 37 | |||
| 38 | ocp { | ||
| 39 | compatible = "simple-bus"; | ||
| 40 | #address-cells = <1>; | ||
| 41 | #size-cells = <1>; | ||
| 42 | ranges; | ||
| 43 | |||
| 44 | uart0: serial@44e09000 { | ||
| 45 | compatible = "ti,am4372-uart","ti,omap2-uart"; | ||
| 46 | reg = <0x44e09000 0x2000>; | ||
| 47 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | timer1: timer@44e31000 { | ||
| 51 | compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; | ||
| 52 | reg = <0x44e31000 0x400>; | ||
| 53 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | ||
| 54 | ti,timer-alwon; | ||
| 55 | }; | ||
| 56 | |||
| 57 | timer2: timer@48040000 { | ||
| 58 | compatible = "ti,am4372-timer","ti,am335x-timer"; | ||
| 59 | reg = <0x48040000 0x400>; | ||
| 60 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | ||
| 61 | }; | ||
| 62 | |||
| 63 | counter32k: counter@44e86000 { | ||
| 64 | compatible = "ti,am4372-counter32k","ti,omap-counter32k"; | ||
| 65 | reg = <0x44e86000 0x40>; | ||
| 66 | }; | ||
| 67 | }; | ||
| 68 | }; | ||
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts new file mode 100644 index 000000000000..74174d48f476 --- /dev/null +++ b/arch/arm/boot/dts/am43x-epos-evm.dts | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /* AM43x EPOS EVM */ | ||
| 10 | |||
| 11 | /dts-v1/; | ||
| 12 | |||
| 13 | #include "am4372.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "TI AM43x EPOS EVM"; | ||
| 17 | compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; | ||
| 18 | }; | ||
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 2353b1f13704..beee1699d49e 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts | |||
| @@ -74,6 +74,7 @@ | |||
| 74 | */ | 74 | */ |
| 75 | status = "disabled"; | 75 | status = "disabled"; |
| 76 | /* No CD or WP GPIOs */ | 76 | /* No CD or WP GPIOs */ |
| 77 | broken-cd; | ||
| 77 | }; | 78 | }; |
| 78 | 79 | ||
| 79 | usb@50000 { | 80 | usb@50000 { |
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 14e36e19d515..45b107763e3b 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts | |||
| @@ -99,6 +99,7 @@ | |||
| 99 | * No CD or WP GPIOs: SDIO interface used for | 99 | * No CD or WP GPIOs: SDIO interface used for |
| 100 | * Wifi/Bluetooth chip | 100 | * Wifi/Bluetooth chip |
| 101 | */ | 101 | */ |
| 102 | broken-cd; | ||
| 102 | }; | 103 | }; |
| 103 | 104 | ||
| 104 | usb@50000 { | 105 | usb@50000 { |
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 130f8390a7e4..a3a2fedb8726 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts | |||
| @@ -64,6 +64,7 @@ | |||
| 64 | pinctrl-names = "default"; | 64 | pinctrl-names = "default"; |
| 65 | status = "okay"; | 65 | status = "okay"; |
| 66 | /* No CD or WP GPIOs */ | 66 | /* No CD or WP GPIOs */ |
| 67 | broken-cd; | ||
| 67 | }; | 68 | }; |
| 68 | 69 | ||
| 69 | usb@50000 { | 70 | usb@50000 { |
| @@ -84,6 +85,22 @@ | |||
| 84 | gpios = <&gpio0 6 1>; | 85 | gpios = <&gpio0 6 1>; |
| 85 | }; | 86 | }; |
| 86 | }; | 87 | }; |
| 88 | |||
| 89 | pcie-controller { | ||
| 90 | status = "okay"; | ||
| 91 | |||
| 92 | /* Internal mini-PCIe connector */ | ||
| 93 | pcie@1,0 { | ||
| 94 | /* Port 0, Lane 0 */ | ||
| 95 | status = "okay"; | ||
| 96 | }; | ||
| 97 | |||
| 98 | /* Internal mini-PCIe connector */ | ||
| 99 | pcie@2,0 { | ||
| 100 | /* Port 1, Lane 0 */ | ||
| 101 | status = "okay"; | ||
| 102 | }; | ||
| 103 | }; | ||
| 87 | }; | 104 | }; |
| 88 | }; | 105 | }; |
| 89 | }; | 106 | }; |
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 52a1f5efc086..90b117624abb 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi | |||
| @@ -22,9 +22,18 @@ | |||
| 22 | model = "Marvell Armada 370 and XP SoC"; | 22 | model = "Marvell Armada 370 and XP SoC"; |
| 23 | compatible = "marvell,armada-370-xp"; | 23 | compatible = "marvell,armada-370-xp"; |
| 24 | 24 | ||
| 25 | aliases { | ||
| 26 | eth0 = ð0; | ||
| 27 | eth1 = ð1; | ||
| 28 | }; | ||
| 29 | |||
| 25 | cpus { | 30 | cpus { |
| 31 | #address-cells = <1>; | ||
| 32 | #size-cells = <0>; | ||
| 26 | cpu@0 { | 33 | cpu@0 { |
| 27 | compatible = "marvell,sheeva-v7"; | 34 | compatible = "marvell,sheeva-v7"; |
| 35 | device_type = "cpu"; | ||
| 36 | reg = <0>; | ||
| 28 | }; | 37 | }; |
| 29 | }; | 38 | }; |
| 30 | 39 | ||
| @@ -94,7 +103,7 @@ | |||
| 94 | reg = <0x72004 0x4>; | 103 | reg = <0x72004 0x4>; |
| 95 | }; | 104 | }; |
| 96 | 105 | ||
| 97 | ethernet@70000 { | 106 | eth0: ethernet@70000 { |
| 98 | compatible = "marvell,armada-370-neta"; | 107 | compatible = "marvell,armada-370-neta"; |
| 99 | reg = <0x70000 0x4000>; | 108 | reg = <0x70000 0x4000>; |
| 100 | interrupts = <8>; | 109 | interrupts = <8>; |
| @@ -102,7 +111,7 @@ | |||
| 102 | status = "disabled"; | 111 | status = "disabled"; |
| 103 | }; | 112 | }; |
| 104 | 113 | ||
| 105 | ethernet@74000 { | 114 | eth1: ethernet@74000 { |
| 106 | compatible = "marvell,armada-370-neta"; | 115 | compatible = "marvell,armada-370-neta"; |
| 107 | reg = <0x74000 0x4000>; | 116 | reg = <0x74000 0x4000>; |
| 108 | interrupts = <10>; | 117 | interrupts = <10>; |
| @@ -143,6 +152,10 @@ | |||
| 143 | reg = <0xd4000 0x200>; | 152 | reg = <0xd4000 0x200>; |
| 144 | interrupts = <54>; | 153 | interrupts = <54>; |
| 145 | clocks = <&gateclk 17>; | 154 | clocks = <&gateclk 17>; |
| 155 | bus-width = <4>; | ||
| 156 | cap-sdio-irq; | ||
| 157 | cap-sd-highspeed; | ||
| 158 | cap-mmc-highspeed; | ||
| 146 | status = "disabled"; | 159 | status = "disabled"; |
| 147 | }; | 160 | }; |
| 148 | 161 | ||
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index aee2b1866ce2..fa3dfc6b4c6a 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi | |||
| @@ -180,10 +180,6 @@ | |||
| 180 | 180 | ||
| 181 | bus-range = <0x00 0xff>; | 181 | bus-range = <0x00 0xff>; |
| 182 | 182 | ||
| 183 | reg = <0x40000 0x2000>, <0x80000 0x2000>; | ||
| 184 | |||
| 185 | reg-names = "pcie0.0", "pcie1.0"; | ||
| 186 | |||
| 187 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ | 183 | ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ |
| 188 | 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ | 184 | 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ |
| 189 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ | 185 | 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ |
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index d6cc8bf8272e..e28e68ff864d 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts | |||
| @@ -30,6 +30,10 @@ | |||
| 30 | }; | 30 | }; |
| 31 | 31 | ||
| 32 | soc { | 32 | soc { |
| 33 | ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ | ||
| 34 | 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ | ||
| 35 | 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */ | ||
| 36 | |||
| 33 | internal-regs { | 37 | internal-regs { |
| 34 | serial@12000 { | 38 | serial@12000 { |
| 35 | clock-frequency = <250000000>; | 39 | clock-frequency = <250000000>; |
| @@ -97,6 +101,7 @@ | |||
| 97 | pinctrl-names = "default"; | 101 | pinctrl-names = "default"; |
| 98 | status = "okay"; | 102 | status = "okay"; |
| 99 | /* No CD or WP GPIOs */ | 103 | /* No CD or WP GPIOs */ |
| 104 | broken-cd; | ||
| 100 | }; | 105 | }; |
| 101 | 106 | ||
| 102 | usb@50000 { | 107 | usb@50000 { |
| @@ -155,6 +160,35 @@ | |||
| 155 | status = "okay"; | 160 | status = "okay"; |
| 156 | }; | 161 | }; |
| 157 | }; | 162 | }; |
| 163 | |||
| 164 | devbus-bootcs@10400 { | ||
| 165 | status = "okay"; | ||
| 166 | ranges = <0 0xf0000000 0x1000000>; | ||
| 167 | |||
| 168 | /* Device Bus parameters are required */ | ||
| 169 | |||
| 170 | /* Read parameters */ | ||
| 171 | devbus,bus-width = <8>; | ||
| 172 | devbus,turn-off-ps = <60000>; | ||
| 173 | devbus,badr-skew-ps = <0>; | ||
| 174 | devbus,acc-first-ps = <124000>; | ||
| 175 | devbus,acc-next-ps = <248000>; | ||
| 176 | devbus,rd-setup-ps = <0>; | ||
| 177 | devbus,rd-hold-ps = <0>; | ||
| 178 | |||
| 179 | /* Write parameters */ | ||
| 180 | devbus,sync-enable = <0>; | ||
| 181 | devbus,wr-high-ps = <60000>; | ||
| 182 | devbus,wr-low-ps = <60000>; | ||
| 183 | devbus,ale-wr-ps = <60000>; | ||
| 184 | |||
| 185 | /* NOR 16 MiB */ | ||
| 186 | nor@0 { | ||
| 187 | compatible = "cfi-flash"; | ||
| 188 | reg = <0 0x1000000>; | ||
| 189 | bank-width = <2>; | ||
| 190 | }; | ||
| 191 | }; | ||
| 158 | }; | 192 | }; |
| 159 | }; | 193 | }; |
| 160 | }; | 194 | }; |
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 76db557adbe7..c87b2de29c30 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts | |||
| @@ -105,6 +105,16 @@ | |||
| 105 | phy-mode = "rgmii-id"; | 105 | phy-mode = "rgmii-id"; |
| 106 | }; | 106 | }; |
| 107 | 107 | ||
| 108 | /* Front-side USB slot */ | ||
| 109 | usb@50000 { | ||
| 110 | status = "okay"; | ||
| 111 | }; | ||
| 112 | |||
| 113 | /* Back-side USB slot */ | ||
| 114 | usb@51000 { | ||
| 115 | status = "okay"; | ||
| 116 | }; | ||
| 117 | |||
| 108 | spi0: spi@10600 { | 118 | spi0: spi@10600 { |
| 109 | status = "okay"; | 119 | status = "okay"; |
| 110 | 120 | ||
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 488ca5eb9a55..c7b1f4d5c1c7 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | gpio0 = &gpio0; | 23 | gpio0 = &gpio0; |
| 24 | gpio1 = &gpio1; | 24 | gpio1 = &gpio1; |
| 25 | gpio2 = &gpio2; | 25 | gpio2 = &gpio2; |
| 26 | eth3 = ð3; | ||
| 26 | }; | 27 | }; |
| 27 | 28 | ||
| 28 | 29 | ||
| @@ -105,7 +106,7 @@ | |||
| 105 | interrupts = <91>; | 106 | interrupts = <91>; |
| 106 | }; | 107 | }; |
| 107 | 108 | ||
| 108 | ethernet@34000 { | 109 | eth3: ethernet@34000 { |
| 109 | compatible = "marvell,armada-370-neta"; | 110 | compatible = "marvell,armada-370-neta"; |
| 110 | reg = <0x34000 0x4000>; | 111 | reg = <0x34000 0x4000>; |
| 111 | interrupts = <14>; | 112 | interrupts = <14>; |
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index fdea75c73411..8f510458ea86 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | |||
| @@ -138,13 +138,22 @@ | |||
| 138 | nr-ports = <2>; | 138 | nr-ports = <2>; |
| 139 | status = "okay"; | 139 | status = "okay"; |
| 140 | }; | 140 | }; |
| 141 | |||
| 142 | /* Front side USB 0 */ | ||
| 141 | usb@50000 { | 143 | usb@50000 { |
| 142 | status = "okay"; | 144 | status = "okay"; |
| 143 | }; | 145 | }; |
| 146 | |||
| 147 | /* Front side USB 1 */ | ||
| 144 | usb@51000 { | 148 | usb@51000 { |
| 145 | status = "okay"; | 149 | status = "okay"; |
| 146 | }; | 150 | }; |
| 147 | 151 | ||
| 152 | /* USB interface in the mini-PCIe connector */ | ||
| 153 | usb@52000 { | ||
| 154 | status = "okay"; | ||
| 155 | }; | ||
| 156 | |||
| 148 | devbus-bootcs@10400 { | 157 | devbus-bootcs@10400 { |
| 149 | status = "okay"; | 158 | status = "okay"; |
| 150 | ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ | 159 | ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ |
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 1ee8540b0eba..416eb9481844 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi | |||
| @@ -22,6 +22,10 @@ | |||
| 22 | model = "Marvell Armada XP family SoC"; | 22 | model = "Marvell Armada XP family SoC"; |
| 23 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; | 23 | compatible = "marvell,armadaxp", "marvell,armada-370-xp"; |
| 24 | 24 | ||
| 25 | aliases { | ||
| 26 | eth2 = ð2; | ||
| 27 | }; | ||
| 28 | |||
| 25 | soc { | 29 | soc { |
| 26 | internal-regs { | 30 | internal-regs { |
| 27 | L2: l2-cache { | 31 | L2: l2-cache { |
| @@ -86,7 +90,7 @@ | |||
| 86 | reg = <0x18200 0x500>; | 90 | reg = <0x18200 0x500>; |
| 87 | }; | 91 | }; |
| 88 | 92 | ||
| 89 | ethernet@30000 { | 93 | eth2: ethernet@30000 { |
| 90 | compatible = "marvell,armada-370-neta"; | 94 | compatible = "marvell,armada-370-neta"; |
| 91 | reg = <0x30000 0x4000>; | 95 | reg = <0x30000 0x4000>; |
| 92 | interrupts = <12>; | 96 | interrupts = <12>; |
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index 5ede7678f298..cce45f5177f9 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | serial3 = &usart2; | 21 | serial3 = &usart2; |
| 22 | serial4 = &usart3; | 22 | serial4 = &usart3; |
| 23 | serial5 = &uart0; | 23 | serial5 = &uart0; |
| 24 | serial6 = &uart1; | ||
| 24 | }; | 25 | }; |
| 25 | 26 | ||
| 26 | chosen { | 27 | chosen { |
| @@ -112,13 +113,17 @@ | |||
| 112 | status = "okay"; | 113 | status = "okay"; |
| 113 | }; | 114 | }; |
| 114 | 115 | ||
| 116 | /* | ||
| 117 | * UART0/1 pins are marked as GPIO on | ||
| 118 | * Aria documentation. | ||
| 119 | * Change to "okay" if you need additional serial ports | ||
| 120 | */ | ||
| 115 | uart0: serial@f8040000 { | 121 | uart0: serial@f8040000 { |
| 116 | compatible = "atmel,at91sam9260-usart"; | 122 | status = "disabled"; |
| 117 | reg = <0xf8040000 0x200>; | 123 | }; |
| 118 | interrupts = <15 4 5>; | 124 | |
| 119 | pinctrl-names = "default"; | 125 | uart1: serial@f8044000 { |
| 120 | pinctrl-0 = <&pinctrl_uart0>; | 126 | status = "disabled"; |
| 121 | status = "okay"; | ||
| 122 | }; | 127 | }; |
| 123 | 128 | ||
| 124 | adc0: adc@f804c000 { | 129 | adc0: adc@f804c000 { |
| @@ -138,6 +143,10 @@ | |||
| 138 | }; | 143 | }; |
| 139 | }; | 144 | }; |
| 140 | }; | 145 | }; |
| 146 | |||
| 147 | rtc@fffffeb0 { | ||
| 148 | status = "okay"; | ||
| 149 | }; | ||
| 141 | }; | 150 | }; |
| 142 | 151 | ||
| 143 | usb0: ohci@00600000 { | 152 | usb0: ohci@00600000 { |
diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts new file mode 100644 index 000000000000..cbe967343997 --- /dev/null +++ b/arch/arm/boot/dts/at91-foxg20.dts | |||
| @@ -0,0 +1,157 @@ | |||
| 1 | /* | ||
| 2 | * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board | ||
| 3 | * | ||
| 4 | * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC) | ||
| 5 | * | ||
| 6 | * Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com> | ||
| 7 | * | ||
| 8 | * Licensed under GPLv2 or later. | ||
| 9 | */ | ||
| 10 | /dts-v1/; | ||
| 11 | #include "at91sam9g20.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Acme Systems FoxG20"; | ||
| 15 | compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9"; | ||
| 16 | |||
| 17 | chosen { | ||
| 18 | bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; | ||
| 19 | }; | ||
| 20 | |||
| 21 | memory { | ||
| 22 | reg = <0x20000000 0x4000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | clocks { | ||
| 26 | #address-cells = <1>; | ||
| 27 | #size-cells = <1>; | ||
| 28 | ranges; | ||
| 29 | |||
| 30 | main_clock: clock@0 { | ||
| 31 | compatible = "atmel,osc", "fixed-clock"; | ||
| 32 | clock-frequency = <18432000>; | ||
| 33 | }; | ||
| 34 | }; | ||
| 35 | |||
| 36 | ahb { | ||
| 37 | apb { | ||
| 38 | usb1: gadget@fffa4000 { | ||
| 39 | atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>; | ||
| 40 | status = "okay"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | mmc0: mmc@fffa8000 { | ||
| 44 | pinctrl-0 = < | ||
| 45 | &pinctrl_mmc0_clk | ||
| 46 | &pinctrl_mmc0_slot1_cmd_dat0 | ||
| 47 | &pinctrl_mmc0_slot1_dat1_3>; | ||
| 48 | status = "okay"; | ||
| 49 | |||
| 50 | slot@1 { | ||
| 51 | reg = <1>; | ||
| 52 | bus-width = <4>; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | usart0: serial@fffb0000 { | ||
| 57 | pinctrl-0 = | ||
| 58 | <&pinctrl_usart0 | ||
| 59 | &pinctrl_usart0_rts | ||
| 60 | &pinctrl_usart0_cts | ||
| 61 | >; | ||
| 62 | status = "okay"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | usart1: serial@fffb4000 { | ||
| 66 | status = "okay"; | ||
| 67 | }; | ||
| 68 | |||
| 69 | usart2: serial@fffb8000 { | ||
| 70 | status = "okay"; | ||
| 71 | }; | ||
| 72 | |||
| 73 | macb0: ethernet@fffc4000 { | ||
| 74 | phy-mode = "rmii"; | ||
| 75 | status = "okay"; | ||
| 76 | }; | ||
| 77 | |||
| 78 | usart3: serial@fffd0000 { | ||
| 79 | status = "okay"; | ||
| 80 | }; | ||
| 81 | |||
| 82 | uart0: serial@fffd4000 { | ||
| 83 | status = "okay"; | ||
| 84 | }; | ||
| 85 | |||
| 86 | uart1: serial@fffd8000 { | ||
| 87 | status = "okay"; | ||
| 88 | }; | ||
| 89 | |||
| 90 | dbgu: serial@fffff200 { | ||
| 91 | status = "okay"; | ||
| 92 | }; | ||
| 93 | |||
| 94 | pinctrl@fffff400 { | ||
| 95 | board { | ||
| 96 | pinctrl_pck0_as_mck: pck0_as_mck { | ||
| 97 | atmel,pins = | ||
| 98 | <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 99 | }; | ||
| 100 | }; | ||
| 101 | |||
| 102 | mmc0_slot1 { | ||
| 103 | pinctrl_board_mmc0_slot1: mmc0_slot1-board { | ||
| 104 | atmel,pins = | ||
| 105 | <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* CD pin */ | ||
| 106 | }; | ||
| 107 | }; | ||
| 108 | |||
| 109 | i2c0 { | ||
| 110 | pinctrl_i2c0: i2c0-0 { | ||
| 111 | atmel,pins = | ||
| 112 | <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* TWD (SDA), open drain */ | ||
| 113 | AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* TWCK (SCL), open drain */ | ||
| 114 | }; | ||
| 115 | }; | ||
| 116 | }; | ||
| 117 | |||
| 118 | watchdog@fffffd40 { | ||
| 119 | status = "okay"; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | |||
| 123 | usb0: ohci@00500000 { | ||
| 124 | num-ports = <2>; | ||
| 125 | status = "okay"; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | i2c@0 { | ||
| 130 | pinctrl-names = "default"; | ||
| 131 | pinctrl-0 = <&pinctrl_i2c0>; | ||
| 132 | i2c-gpio,delay-us = <5>; /* ~85 kHz */ | ||
| 133 | status = "okay"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | leds { | ||
| 137 | compatible = "gpio-leds"; | ||
| 138 | |||
| 139 | /* red LED marked "PC7" near mini USB (device) receptacle */ | ||
| 140 | user_led { | ||
| 141 | label = "user_led"; | ||
| 142 | gpios = <&pioC 7 GPIO_ACTIVE_HIGH>; /* PC7 */ | ||
| 143 | linux,default-trigger = "heartbeat"; | ||
| 144 | }; | ||
| 145 | }; | ||
| 146 | |||
| 147 | gpio_keys { | ||
| 148 | compatible = "gpio-keys"; | ||
| 149 | |||
| 150 | btn { | ||
| 151 | label = "Button"; | ||
| 152 | gpios = <&pioC 4 GPIO_ACTIVE_LOW>; | ||
| 153 | linux,code = <0x103>; | ||
| 154 | gpio-key,wakeup; | ||
| 155 | }; | ||
| 156 | }; | ||
| 157 | }; | ||
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index 4aad0d9f5462..92b9e21389db 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi | |||
| @@ -38,8 +38,12 @@ | |||
| 38 | ssc2 = &ssc2; | 38 | ssc2 = &ssc2; |
| 39 | }; | 39 | }; |
| 40 | cpus { | 40 | cpus { |
| 41 | cpu@0 { | 41 | #address-cells = <0>; |
| 42 | #size-cells = <0>; | ||
| 43 | |||
| 44 | cpu { | ||
| 42 | compatible = "arm,arm920t"; | 45 | compatible = "arm,arm920t"; |
| 46 | device_type = "cpu"; | ||
| 43 | }; | 47 | }; |
| 44 | }; | 48 | }; |
| 45 | 49 | ||
| @@ -398,6 +402,91 @@ | |||
| 398 | }; | 402 | }; |
| 399 | }; | 403 | }; |
| 400 | 404 | ||
| 405 | tcb0 { | ||
| 406 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | ||
| 407 | atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 408 | }; | ||
| 409 | |||
| 410 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { | ||
| 411 | atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 412 | }; | ||
| 413 | |||
| 414 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { | ||
| 415 | atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 416 | }; | ||
| 417 | |||
| 418 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { | ||
| 419 | atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 420 | }; | ||
| 421 | |||
| 422 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { | ||
| 423 | atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 424 | }; | ||
| 425 | |||
| 426 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { | ||
| 427 | atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 428 | }; | ||
| 429 | |||
| 430 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { | ||
| 431 | atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 432 | }; | ||
| 433 | |||
| 434 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { | ||
| 435 | atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 436 | }; | ||
| 437 | |||
| 438 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { | ||
| 439 | atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 440 | }; | ||
| 441 | }; | ||
| 442 | |||
| 443 | tcb1 { | ||
| 444 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { | ||
| 445 | atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 446 | }; | ||
| 447 | |||
| 448 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { | ||
| 449 | atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 450 | }; | ||
| 451 | |||
| 452 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { | ||
| 453 | atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 454 | }; | ||
| 455 | |||
| 456 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { | ||
| 457 | atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 458 | }; | ||
| 459 | |||
| 460 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { | ||
| 461 | atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 462 | }; | ||
| 463 | |||
| 464 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { | ||
| 465 | atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 466 | }; | ||
| 467 | |||
| 468 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { | ||
| 469 | atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 470 | }; | ||
| 471 | |||
| 472 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { | ||
| 473 | atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 474 | }; | ||
| 475 | |||
| 476 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { | ||
| 477 | atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 478 | }; | ||
| 479 | }; | ||
| 480 | |||
| 481 | spi0 { | ||
| 482 | pinctrl_spi0: spi0-0 { | ||
| 483 | atmel,pins = | ||
| 484 | <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ | ||
| 485 | AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ | ||
| 486 | AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ | ||
| 487 | }; | ||
| 488 | }; | ||
| 489 | |||
| 401 | pioA: gpio@fffff400 { | 490 | pioA: gpio@fffff400 { |
| 402 | compatible = "atmel,at91rm9200-gpio"; | 491 | compatible = "atmel,at91rm9200-gpio"; |
| 403 | reg = <0xfffff400 0x200>; | 492 | reg = <0xfffff400 0x200>; |
| @@ -498,6 +587,17 @@ | |||
| 498 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; | 587 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; |
| 499 | status = "disabled"; | 588 | status = "disabled"; |
| 500 | }; | 589 | }; |
| 590 | |||
| 591 | spi0: spi@fffe0000 { | ||
| 592 | #address-cells = <1>; | ||
| 593 | #size-cells = <0>; | ||
| 594 | compatible = "atmel,at91rm9200-spi"; | ||
| 595 | reg = <0xfffe0000 0x200>; | ||
| 596 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; | ||
| 597 | pinctrl-names = "default"; | ||
| 598 | pinctrl-0 = <&pinctrl_spi0>; | ||
| 599 | status = "disabled"; | ||
| 600 | }; | ||
| 501 | }; | 601 | }; |
| 502 | 602 | ||
| 503 | nand0: nand@40000000 { | 603 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index 14058125d123..d2d72c3b44c4 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts | |||
| @@ -53,6 +53,16 @@ | |||
| 53 | atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; | 53 | atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; |
| 54 | status = "okay"; | 54 | status = "okay"; |
| 55 | }; | 55 | }; |
| 56 | |||
| 57 | spi0: spi@fffe0000 { | ||
| 58 | status = "okay"; | ||
| 59 | cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; | ||
| 60 | mtd_dataflash@0 { | ||
| 61 | compatible = "atmel,at45", "atmel,dataflash"; | ||
| 62 | spi-max-frequency = <15000000>; | ||
| 63 | reg = <0>; | ||
| 64 | }; | ||
| 65 | }; | ||
| 56 | }; | 66 | }; |
| 57 | 67 | ||
| 58 | usb0: ohci@00300000 { | 68 | usb0: ohci@00300000 { |
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 44851b977069..c7ccbcbffb3e 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi | |||
| @@ -35,8 +35,12 @@ | |||
| 35 | ssc0 = &ssc0; | 35 | ssc0 = &ssc0; |
| 36 | }; | 36 | }; |
| 37 | cpus { | 37 | cpus { |
| 38 | cpu@0 { | 38 | #address-cells = <0>; |
| 39 | compatible = "arm,arm926ejs"; | 39 | #size-cells = <0>; |
| 40 | |||
| 41 | cpu { | ||
| 42 | compatible = "arm,arm926ej-s"; | ||
| 43 | device_type = "cpu"; | ||
| 40 | }; | 44 | }; |
| 41 | }; | 45 | }; |
| 42 | 46 | ||
| @@ -347,6 +351,90 @@ | |||
| 347 | }; | 351 | }; |
| 348 | }; | 352 | }; |
| 349 | 353 | ||
| 354 | i2c_gpio0 { | ||
| 355 | pinctrl_i2c_gpio0: i2c_gpio0-0 { | ||
| 356 | atmel,pins = | ||
| 357 | <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE | ||
| 358 | AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; | ||
| 359 | }; | ||
| 360 | }; | ||
| 361 | |||
| 362 | tcb0 { | ||
| 363 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | ||
| 364 | atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 365 | }; | ||
| 366 | |||
| 367 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { | ||
| 368 | atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 369 | }; | ||
| 370 | |||
| 371 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { | ||
| 372 | atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 373 | }; | ||
| 374 | |||
| 375 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { | ||
| 376 | atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 377 | }; | ||
| 378 | |||
| 379 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { | ||
| 380 | atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 381 | }; | ||
| 382 | |||
| 383 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { | ||
| 384 | atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 385 | }; | ||
| 386 | |||
| 387 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { | ||
| 388 | atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 389 | }; | ||
| 390 | |||
| 391 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { | ||
| 392 | atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 393 | }; | ||
| 394 | |||
| 395 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { | ||
| 396 | atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 397 | }; | ||
| 398 | }; | ||
| 399 | |||
| 400 | tcb1 { | ||
| 401 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { | ||
| 402 | atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 403 | }; | ||
| 404 | |||
| 405 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { | ||
| 406 | atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 407 | }; | ||
| 408 | |||
| 409 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { | ||
| 410 | atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 411 | }; | ||
| 412 | |||
| 413 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { | ||
| 414 | atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 415 | }; | ||
| 416 | |||
| 417 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { | ||
| 418 | atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 419 | }; | ||
| 420 | |||
| 421 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { | ||
| 422 | atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 423 | }; | ||
| 424 | |||
| 425 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { | ||
| 426 | atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 427 | }; | ||
| 428 | |||
| 429 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { | ||
| 430 | atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 431 | }; | ||
| 432 | |||
| 433 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { | ||
| 434 | atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 435 | }; | ||
| 436 | }; | ||
| 437 | |||
| 350 | pioA: gpio@fffff400 { | 438 | pioA: gpio@fffff400 { |
| 351 | compatible = "atmel,at91rm9200-gpio"; | 439 | compatible = "atmel,at91rm9200-gpio"; |
| 352 | reg = <0xfffff400 0x200>; | 440 | reg = <0xfffff400 0x200>; |
| @@ -599,6 +687,8 @@ | |||
| 599 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | 687 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 600 | #address-cells = <1>; | 688 | #address-cells = <1>; |
| 601 | #size-cells = <0>; | 689 | #size-cells = <0>; |
| 690 | pinctrl-names = "default"; | ||
| 691 | pinctrl-0 = <&pinctrl_i2c_gpio0>; | ||
| 602 | status = "disabled"; | 692 | status = "disabled"; |
| 603 | }; | 693 | }; |
| 604 | }; | 694 | }; |
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index d9cf51a01b60..d5bd65f74602 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi | |||
| @@ -32,8 +32,12 @@ | |||
| 32 | ssc1 = &ssc1; | 32 | ssc1 = &ssc1; |
| 33 | }; | 33 | }; |
| 34 | cpus { | 34 | cpus { |
| 35 | cpu@0 { | 35 | #address-cells = <0>; |
| 36 | compatible = "arm,arm926ejs"; | 36 | #size-cells = <0>; |
| 37 | |||
| 38 | cpu { | ||
| 39 | compatible = "arm,arm926ej-s"; | ||
| 40 | device_type = "cpu"; | ||
| 37 | }; | 41 | }; |
| 38 | }; | 42 | }; |
| 39 | 43 | ||
| @@ -324,6 +328,44 @@ | |||
| 324 | }; | 328 | }; |
| 325 | }; | 329 | }; |
| 326 | 330 | ||
| 331 | tcb0 { | ||
| 332 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | ||
| 333 | atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 334 | }; | ||
| 335 | |||
| 336 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { | ||
| 337 | atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 338 | }; | ||
| 339 | |||
| 340 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { | ||
| 341 | atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 342 | }; | ||
| 343 | |||
| 344 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { | ||
| 345 | atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 346 | }; | ||
| 347 | |||
| 348 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { | ||
| 349 | atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 350 | }; | ||
| 351 | |||
| 352 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { | ||
| 353 | atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 354 | }; | ||
| 355 | |||
| 356 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { | ||
| 357 | atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 358 | }; | ||
| 359 | |||
| 360 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { | ||
| 361 | atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 362 | }; | ||
| 363 | |||
| 364 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { | ||
| 365 | atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 366 | }; | ||
| 367 | }; | ||
| 368 | |||
| 327 | pioA: gpio@fffff200 { | 369 | pioA: gpio@fffff200 { |
| 328 | compatible = "atmel,at91rm9200-gpio"; | 370 | compatible = "atmel,at91rm9200-gpio"; |
| 329 | reg = <0xfffff200 0x200>; | 371 | reg = <0xfffff200 0x200>; |
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index eff1afb81304..70f835b55c0b 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts | |||
| @@ -89,6 +89,10 @@ | |||
| 89 | reg = <0>; | 89 | reg = <0>; |
| 90 | }; | 90 | }; |
| 91 | }; | 91 | }; |
| 92 | |||
| 93 | watchdog@fffffd40 { | ||
| 94 | status = "okay"; | ||
| 95 | }; | ||
| 92 | }; | 96 | }; |
| 93 | 97 | ||
| 94 | nand0: nand@40000000 { | 98 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index c7ffc32918f9..137354689ad0 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi | |||
| @@ -104,6 +104,10 @@ | |||
| 104 | reg = <1>; | 104 | reg = <1>; |
| 105 | }; | 105 | }; |
| 106 | }; | 106 | }; |
| 107 | |||
| 108 | watchdog@fffffd40 { | ||
| 109 | status = "okay"; | ||
| 110 | }; | ||
| 107 | }; | 111 | }; |
| 108 | 112 | ||
| 109 | nand0: nand@40000000 { | 113 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index f0091af6c285..c3e514837074 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | #include <dt-bindings/dma/at91.h> | ||
| 13 | #include <dt-bindings/pinctrl/at91.h> | 14 | #include <dt-bindings/pinctrl/at91.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | #include <dt-bindings/gpio/gpio.h> | 16 | #include <dt-bindings/gpio/gpio.h> |
| @@ -38,8 +39,12 @@ | |||
| 38 | ssc1 = &ssc1; | 39 | ssc1 = &ssc1; |
| 39 | }; | 40 | }; |
| 40 | cpus { | 41 | cpus { |
| 41 | cpu@0 { | 42 | #address-cells = <0>; |
| 42 | compatible = "arm,arm926ejs"; | 43 | #size-cells = <0>; |
| 44 | |||
| 45 | cpu { | ||
| 46 | compatible = "arm,arm926ej-s"; | ||
| 47 | device_type = "cpu"; | ||
| 43 | }; | 48 | }; |
| 44 | }; | 49 | }; |
| 45 | 50 | ||
| @@ -344,6 +349,82 @@ | |||
| 344 | }; | 349 | }; |
| 345 | }; | 350 | }; |
| 346 | 351 | ||
| 352 | tcb0 { | ||
| 353 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | ||
| 354 | atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 355 | }; | ||
| 356 | |||
| 357 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { | ||
| 358 | atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 359 | }; | ||
| 360 | |||
| 361 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { | ||
| 362 | atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 363 | }; | ||
| 364 | |||
| 365 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { | ||
| 366 | atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 367 | }; | ||
| 368 | |||
| 369 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { | ||
| 370 | atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 371 | }; | ||
| 372 | |||
| 373 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { | ||
| 374 | atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 375 | }; | ||
| 376 | |||
| 377 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { | ||
| 378 | atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 379 | }; | ||
| 380 | |||
| 381 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { | ||
| 382 | atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 383 | }; | ||
| 384 | |||
| 385 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { | ||
| 386 | atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 387 | }; | ||
| 388 | }; | ||
| 389 | |||
| 390 | tcb1 { | ||
| 391 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { | ||
| 392 | atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 393 | }; | ||
| 394 | |||
| 395 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { | ||
| 396 | atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 397 | }; | ||
| 398 | |||
| 399 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { | ||
| 400 | atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 401 | }; | ||
| 402 | |||
| 403 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { | ||
| 404 | atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 405 | }; | ||
| 406 | |||
| 407 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { | ||
| 408 | atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 409 | }; | ||
| 410 | |||
| 411 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { | ||
| 412 | atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 413 | }; | ||
| 414 | |||
| 415 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { | ||
| 416 | atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 417 | }; | ||
| 418 | |||
| 419 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { | ||
| 420 | atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 421 | }; | ||
| 422 | |||
| 423 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { | ||
| 424 | atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; | ||
| 425 | }; | ||
| 426 | }; | ||
| 427 | |||
| 347 | pioA: gpio@fffff200 { | 428 | pioA: gpio@fffff200 { |
| 348 | compatible = "atmel,at91rm9200-gpio"; | 429 | compatible = "atmel,at91rm9200-gpio"; |
| 349 | reg = <0xfffff200 0x200>; | 430 | reg = <0xfffff200 0x200>; |
| @@ -537,7 +618,7 @@ | |||
| 537 | compatible = "atmel,hsmci"; | 618 | compatible = "atmel,hsmci"; |
| 538 | reg = <0xfff80000 0x600>; | 619 | reg = <0xfff80000 0x600>; |
| 539 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; | 620 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; |
| 540 | dmas = <&dma 1 0>; | 621 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; |
| 541 | dma-names = "rxtx"; | 622 | dma-names = "rxtx"; |
| 542 | #address-cells = <1>; | 623 | #address-cells = <1>; |
| 543 | #size-cells = <0>; | 624 | #size-cells = <0>; |
| @@ -548,7 +629,7 @@ | |||
| 548 | compatible = "atmel,hsmci"; | 629 | compatible = "atmel,hsmci"; |
| 549 | reg = <0xfffd0000 0x600>; | 630 | reg = <0xfffd0000 0x600>; |
| 550 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; | 631 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; |
| 551 | dmas = <&dma 1 13>; | 632 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; |
| 552 | dma-names = "rxtx"; | 633 | dma-names = "rxtx"; |
| 553 | #address-cells = <1>; | 634 | #address-cells = <1>; |
| 554 | #size-cells = <0>; | 635 | #size-cells = <0>; |
| @@ -582,6 +663,68 @@ | |||
| 582 | pinctrl-0 = <&pinctrl_spi1>; | 663 | pinctrl-0 = <&pinctrl_spi1>; |
| 583 | status = "disabled"; | 664 | status = "disabled"; |
| 584 | }; | 665 | }; |
| 666 | |||
| 667 | usb2: gadget@fff78000 { | ||
| 668 | #address-cells = <1>; | ||
| 669 | #size-cells = <0>; | ||
| 670 | compatible = "atmel,at91sam9rl-udc"; | ||
| 671 | reg = <0x00600000 0x80000 | ||
| 672 | 0xfff78000 0x400>; | ||
| 673 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| 674 | status = "disabled"; | ||
| 675 | |||
| 676 | ep0 { | ||
| 677 | reg = <0>; | ||
| 678 | atmel,fifo-size = <64>; | ||
| 679 | atmel,nb-banks = <1>; | ||
| 680 | }; | ||
| 681 | |||
| 682 | ep1 { | ||
| 683 | reg = <1>; | ||
| 684 | atmel,fifo-size = <1024>; | ||
| 685 | atmel,nb-banks = <2>; | ||
| 686 | atmel,can-dma; | ||
| 687 | atmel,can-isoc; | ||
| 688 | }; | ||
| 689 | |||
| 690 | ep2 { | ||
| 691 | reg = <2>; | ||
| 692 | atmel,fifo-size = <1024>; | ||
| 693 | atmel,nb-banks = <2>; | ||
| 694 | atmel,can-dma; | ||
| 695 | atmel,can-isoc; | ||
| 696 | }; | ||
| 697 | |||
| 698 | ep3 { | ||
| 699 | reg = <3>; | ||
| 700 | atmel,fifo-size = <1024>; | ||
| 701 | atmel,nb-banks = <3>; | ||
| 702 | atmel,can-dma; | ||
| 703 | }; | ||
| 704 | |||
| 705 | ep4 { | ||
| 706 | reg = <4>; | ||
| 707 | atmel,fifo-size = <1024>; | ||
| 708 | atmel,nb-banks = <3>; | ||
| 709 | atmel,can-dma; | ||
| 710 | }; | ||
| 711 | |||
| 712 | ep5 { | ||
| 713 | reg = <5>; | ||
| 714 | atmel,fifo-size = <1024>; | ||
| 715 | atmel,nb-banks = <3>; | ||
| 716 | atmel,can-dma; | ||
| 717 | atmel,can-isoc; | ||
| 718 | }; | ||
| 719 | |||
| 720 | ep6 { | ||
| 721 | reg = <6>; | ||
| 722 | atmel,fifo-size = <1024>; | ||
| 723 | atmel,nb-banks = <3>; | ||
| 724 | atmel,can-dma; | ||
| 725 | atmel,can-isoc; | ||
| 726 | }; | ||
| 727 | }; | ||
| 585 | }; | 728 | }; |
| 586 | 729 | ||
| 587 | nand0: nand@40000000 { | 730 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 89c50d108d44..a4b00e5c61c0 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts | |||
| @@ -59,6 +59,10 @@ | |||
| 59 | status = "okay"; | 59 | status = "okay"; |
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| 62 | watchdog@fffffd40 { | ||
| 63 | status = "okay"; | ||
| 64 | }; | ||
| 65 | |||
| 62 | mmc0: mmc@fff80000 { | 66 | mmc0: mmc@fff80000 { |
| 63 | pinctrl-0 = < | 67 | pinctrl-0 = < |
| 64 | &pinctrl_board_mmc0 | 68 | &pinctrl_board_mmc0 |
| @@ -112,6 +116,11 @@ | |||
| 112 | reg = <0>; | 116 | reg = <0>; |
| 113 | }; | 117 | }; |
| 114 | }; | 118 | }; |
| 119 | |||
| 120 | usb2: gadget@fff78000 { | ||
| 121 | atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; | ||
| 122 | status = "okay"; | ||
| 123 | }; | ||
| 115 | }; | 124 | }; |
| 116 | 125 | ||
| 117 | nand0: nand@40000000 { | 126 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index d864f7a9d2e0..bb7f564b3a55 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi | |||
| @@ -8,6 +8,7 @@ | |||
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #include "skeleton.dtsi" | 10 | #include "skeleton.dtsi" |
| 11 | #include <dt-bindings/dma/at91.h> | ||
| 11 | #include <dt-bindings/pinctrl/at91.h> | 12 | #include <dt-bindings/pinctrl/at91.h> |
| 12 | #include <dt-bindings/interrupt-controller/irq.h> | 13 | #include <dt-bindings/interrupt-controller/irq.h> |
| 13 | #include <dt-bindings/gpio/gpio.h> | 14 | #include <dt-bindings/gpio/gpio.h> |
| @@ -34,8 +35,12 @@ | |||
| 34 | ssc0 = &ssc0; | 35 | ssc0 = &ssc0; |
| 35 | }; | 36 | }; |
| 36 | cpus { | 37 | cpus { |
| 37 | cpu@0 { | 38 | #address-cells = <0>; |
| 38 | compatible = "arm,arm926ejs"; | 39 | #size-cells = <0>; |
| 40 | |||
| 41 | cpu { | ||
| 42 | compatible = "arm,arm926ej-s"; | ||
| 43 | device_type = "cpu"; | ||
| 39 | }; | 44 | }; |
| 40 | }; | 45 | }; |
| 41 | 46 | ||
| @@ -93,7 +98,7 @@ | |||
| 93 | compatible = "atmel,hsmci"; | 98 | compatible = "atmel,hsmci"; |
| 94 | reg = <0xf0008000 0x600>; | 99 | reg = <0xf0008000 0x600>; |
| 95 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; | 100 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; |
| 96 | dmas = <&dma 1 0>; | 101 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; |
| 97 | dma-names = "rxtx"; | 102 | dma-names = "rxtx"; |
| 98 | #address-cells = <1>; | 103 | #address-cells = <1>; |
| 99 | #size-cells = <0>; | 104 | #size-cells = <0>; |
| @@ -286,6 +291,82 @@ | |||
| 286 | }; | 291 | }; |
| 287 | }; | 292 | }; |
| 288 | 293 | ||
| 294 | tcb0 { | ||
| 295 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | ||
| 296 | atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 297 | }; | ||
| 298 | |||
| 299 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { | ||
| 300 | atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 301 | }; | ||
| 302 | |||
| 303 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { | ||
| 304 | atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 305 | }; | ||
| 306 | |||
| 307 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { | ||
| 308 | atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 309 | }; | ||
| 310 | |||
| 311 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { | ||
| 312 | atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 313 | }; | ||
| 314 | |||
| 315 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { | ||
| 316 | atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 317 | }; | ||
| 318 | |||
| 319 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { | ||
| 320 | atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 321 | }; | ||
| 322 | |||
| 323 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { | ||
| 324 | atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 325 | }; | ||
| 326 | |||
| 327 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { | ||
| 328 | atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 329 | }; | ||
| 330 | }; | ||
| 331 | |||
| 332 | tcb1 { | ||
| 333 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { | ||
| 334 | atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 335 | }; | ||
| 336 | |||
| 337 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { | ||
| 338 | atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 339 | }; | ||
| 340 | |||
| 341 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { | ||
| 342 | atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 343 | }; | ||
| 344 | |||
| 345 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { | ||
| 346 | atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 347 | }; | ||
| 348 | |||
| 349 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { | ||
| 350 | atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 351 | }; | ||
| 352 | |||
| 353 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { | ||
| 354 | atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 355 | }; | ||
| 356 | |||
| 357 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { | ||
| 358 | atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 359 | }; | ||
| 360 | |||
| 361 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { | ||
| 362 | atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 363 | }; | ||
| 364 | |||
| 365 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { | ||
| 366 | atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 367 | }; | ||
| 368 | }; | ||
| 369 | |||
| 289 | pioA: gpio@fffff400 { | 370 | pioA: gpio@fffff400 { |
| 290 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 371 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 291 | reg = <0xfffff400 0x200>; | 372 | reg = <0xfffff400 0x200>; |
| @@ -385,8 +466,8 @@ | |||
| 385 | compatible = "atmel,at91sam9x5-i2c"; | 466 | compatible = "atmel,at91sam9x5-i2c"; |
| 386 | reg = <0xf8010000 0x100>; | 467 | reg = <0xf8010000 0x100>; |
| 387 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; | 468 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; |
| 388 | dmas = <&dma 1 13>, | 469 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>, |
| 389 | <&dma 1 14>; | 470 | <&dma 1 AT91_DMA_CFG_PER_ID(14)>; |
| 390 | dma-names = "tx", "rx"; | 471 | dma-names = "tx", "rx"; |
| 391 | #address-cells = <1>; | 472 | #address-cells = <1>; |
| 392 | #size-cells = <0>; | 473 | #size-cells = <0>; |
| @@ -397,8 +478,8 @@ | |||
| 397 | compatible = "atmel,at91sam9x5-i2c"; | 478 | compatible = "atmel,at91sam9x5-i2c"; |
| 398 | reg = <0xf8014000 0x100>; | 479 | reg = <0xf8014000 0x100>; |
| 399 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; | 480 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; |
| 400 | dmas = <&dma 1 15>, | 481 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>, |
| 401 | <&dma 1 16>; | 482 | <&dma 1 AT91_DMA_CFG_PER_ID(16)>; |
| 402 | dma-names = "tx", "rx"; | 483 | dma-names = "tx", "rx"; |
| 403 | #address-cells = <1>; | 484 | #address-cells = <1>; |
| 404 | #size-cells = <0>; | 485 | #size-cells = <0>; |
| @@ -411,6 +492,9 @@ | |||
| 411 | compatible = "atmel,at91rm9200-spi"; | 492 | compatible = "atmel,at91rm9200-spi"; |
| 412 | reg = <0xf0000000 0x100>; | 493 | reg = <0xf0000000 0x100>; |
| 413 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; | 494 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
| 495 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>, | ||
| 496 | <&dma 1 AT91_DMA_CFG_PER_ID(2)>; | ||
| 497 | dma-names = "tx", "rx"; | ||
| 414 | pinctrl-names = "default"; | 498 | pinctrl-names = "default"; |
| 415 | pinctrl-0 = <&pinctrl_spi0>; | 499 | pinctrl-0 = <&pinctrl_spi0>; |
| 416 | status = "disabled"; | 500 | status = "disabled"; |
| @@ -422,10 +506,19 @@ | |||
| 422 | compatible = "atmel,at91rm9200-spi"; | 506 | compatible = "atmel,at91rm9200-spi"; |
| 423 | reg = <0xf0004000 0x100>; | 507 | reg = <0xf0004000 0x100>; |
| 424 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; | 508 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
| 509 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>, | ||
| 510 | <&dma 1 AT91_DMA_CFG_PER_ID(4)>; | ||
| 511 | dma-names = "tx", "rx"; | ||
| 425 | pinctrl-names = "default"; | 512 | pinctrl-names = "default"; |
| 426 | pinctrl-0 = <&pinctrl_spi1>; | 513 | pinctrl-0 = <&pinctrl_spi1>; |
| 427 | status = "disabled"; | 514 | status = "disabled"; |
| 428 | }; | 515 | }; |
| 516 | |||
| 517 | watchdog@fffffe40 { | ||
| 518 | compatible = "atmel,at91sam9260-wdt"; | ||
| 519 | reg = <0xfffffe40 0x10>; | ||
| 520 | status = "disabled"; | ||
| 521 | }; | ||
| 429 | }; | 522 | }; |
| 430 | 523 | ||
| 431 | nand0: nand@40000000 { | 524 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 2e67cd5e47eb..d59b70c6a6a0 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts | |||
| @@ -77,6 +77,10 @@ | |||
| 77 | reg = <0>; | 77 | reg = <0>; |
| 78 | }; | 78 | }; |
| 79 | }; | 79 | }; |
| 80 | |||
| 81 | watchdog@fffffe40 { | ||
| 82 | status = "okay"; | ||
| 83 | }; | ||
| 80 | }; | 84 | }; |
| 81 | 85 | ||
| 82 | nand0: nand@40000000 { | 86 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index af91599488e9..57d45f5bea09 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include "skeleton.dtsi" | 12 | #include "skeleton.dtsi" |
| 13 | #include <dt-bindings/dma/at91.h> | ||
| 13 | #include <dt-bindings/pinctrl/at91.h> | 14 | #include <dt-bindings/pinctrl/at91.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | #include <dt-bindings/gpio/gpio.h> | 16 | #include <dt-bindings/gpio/gpio.h> |
| @@ -36,8 +37,12 @@ | |||
| 36 | ssc0 = &ssc0; | 37 | ssc0 = &ssc0; |
| 37 | }; | 38 | }; |
| 38 | cpus { | 39 | cpus { |
| 39 | cpu@0 { | 40 | #address-cells = <0>; |
| 40 | compatible = "arm,arm926ejs"; | 41 | #size-cells = <0>; |
| 42 | |||
| 43 | cpu { | ||
| 44 | compatible = "arm,arm926ej-s"; | ||
| 45 | device_type = "cpu"; | ||
| 41 | }; | 46 | }; |
| 42 | }; | 47 | }; |
| 43 | 48 | ||
| @@ -414,6 +419,82 @@ | |||
| 414 | }; | 419 | }; |
| 415 | }; | 420 | }; |
| 416 | 421 | ||
| 422 | tcb0 { | ||
| 423 | pinctrl_tcb0_tclk0: tcb0_tclk0-0 { | ||
| 424 | atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 425 | }; | ||
| 426 | |||
| 427 | pinctrl_tcb0_tclk1: tcb0_tclk1-0 { | ||
| 428 | atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 429 | }; | ||
| 430 | |||
| 431 | pinctrl_tcb0_tclk2: tcb0_tclk2-0 { | ||
| 432 | atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 433 | }; | ||
| 434 | |||
| 435 | pinctrl_tcb0_tioa0: tcb0_tioa0-0 { | ||
| 436 | atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 437 | }; | ||
| 438 | |||
| 439 | pinctrl_tcb0_tioa1: tcb0_tioa1-0 { | ||
| 440 | atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 441 | }; | ||
| 442 | |||
| 443 | pinctrl_tcb0_tioa2: tcb0_tioa2-0 { | ||
| 444 | atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 445 | }; | ||
| 446 | |||
| 447 | pinctrl_tcb0_tiob0: tcb0_tiob0-0 { | ||
| 448 | atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 449 | }; | ||
| 450 | |||
| 451 | pinctrl_tcb0_tiob1: tcb0_tiob1-0 { | ||
| 452 | atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 453 | }; | ||
| 454 | |||
| 455 | pinctrl_tcb0_tiob2: tcb0_tiob2-0 { | ||
| 456 | atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; | ||
| 457 | }; | ||
| 458 | }; | ||
| 459 | |||
| 460 | tcb1 { | ||
| 461 | pinctrl_tcb1_tclk0: tcb1_tclk0-0 { | ||
| 462 | atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 463 | }; | ||
| 464 | |||
| 465 | pinctrl_tcb1_tclk1: tcb1_tclk1-0 { | ||
| 466 | atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 467 | }; | ||
| 468 | |||
| 469 | pinctrl_tcb1_tclk2: tcb1_tclk2-0 { | ||
| 470 | atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 471 | }; | ||
| 472 | |||
| 473 | pinctrl_tcb1_tioa0: tcb1_tioa0-0 { | ||
| 474 | atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 475 | }; | ||
| 476 | |||
| 477 | pinctrl_tcb1_tioa1: tcb1_tioa1-0 { | ||
| 478 | atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 479 | }; | ||
| 480 | |||
| 481 | pinctrl_tcb1_tioa2: tcb1_tioa2-0 { | ||
| 482 | atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 483 | }; | ||
| 484 | |||
| 485 | pinctrl_tcb1_tiob0: tcb1_tiob0-0 { | ||
| 486 | atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 487 | }; | ||
| 488 | |||
| 489 | pinctrl_tcb1_tiob1: tcb1_tiob1-0 { | ||
| 490 | atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 491 | }; | ||
| 492 | |||
| 493 | pinctrl_tcb1_tiob2: tcb1_tiob2-0 { | ||
| 494 | atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; | ||
| 495 | }; | ||
| 496 | }; | ||
| 497 | |||
| 417 | pioA: gpio@fffff400 { | 498 | pioA: gpio@fffff400 { |
| 418 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 499 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 419 | reg = <0xfffff400 0x200>; | 500 | reg = <0xfffff400 0x200>; |
| @@ -470,7 +551,7 @@ | |||
| 470 | compatible = "atmel,hsmci"; | 551 | compatible = "atmel,hsmci"; |
| 471 | reg = <0xf0008000 0x600>; | 552 | reg = <0xf0008000 0x600>; |
| 472 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; | 553 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; |
| 473 | dmas = <&dma0 1 0>; | 554 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; |
| 474 | dma-names = "rxtx"; | 555 | dma-names = "rxtx"; |
| 475 | #address-cells = <1>; | 556 | #address-cells = <1>; |
| 476 | #size-cells = <0>; | 557 | #size-cells = <0>; |
| @@ -481,7 +562,7 @@ | |||
| 481 | compatible = "atmel,hsmci"; | 562 | compatible = "atmel,hsmci"; |
| 482 | reg = <0xf000c000 0x600>; | 563 | reg = <0xf000c000 0x600>; |
| 483 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; | 564 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; |
| 484 | dmas = <&dma1 1 0>; | 565 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; |
| 485 | dma-names = "rxtx"; | 566 | dma-names = "rxtx"; |
| 486 | #address-cells = <1>; | 567 | #address-cells = <1>; |
| 487 | #size-cells = <0>; | 568 | #size-cells = <0>; |
| @@ -544,8 +625,8 @@ | |||
| 544 | compatible = "atmel,at91sam9x5-i2c"; | 625 | compatible = "atmel,at91sam9x5-i2c"; |
| 545 | reg = <0xf8010000 0x100>; | 626 | reg = <0xf8010000 0x100>; |
| 546 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; | 627 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>; |
| 547 | dmas = <&dma0 1 7>, | 628 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>, |
| 548 | <&dma0 1 8>; | 629 | <&dma0 1 AT91_DMA_CFG_PER_ID(8)>; |
| 549 | dma-names = "tx", "rx"; | 630 | dma-names = "tx", "rx"; |
| 550 | #address-cells = <1>; | 631 | #address-cells = <1>; |
| 551 | #size-cells = <0>; | 632 | #size-cells = <0>; |
| @@ -558,8 +639,8 @@ | |||
| 558 | compatible = "atmel,at91sam9x5-i2c"; | 639 | compatible = "atmel,at91sam9x5-i2c"; |
| 559 | reg = <0xf8014000 0x100>; | 640 | reg = <0xf8014000 0x100>; |
| 560 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; | 641 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>; |
| 561 | dmas = <&dma1 1 5>, | 642 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>, |
| 562 | <&dma1 1 6>; | 643 | <&dma1 1 AT91_DMA_CFG_PER_ID(6)>; |
| 563 | dma-names = "tx", "rx"; | 644 | dma-names = "tx", "rx"; |
| 564 | #address-cells = <1>; | 645 | #address-cells = <1>; |
| 565 | #size-cells = <0>; | 646 | #size-cells = <0>; |
| @@ -572,8 +653,8 @@ | |||
| 572 | compatible = "atmel,at91sam9x5-i2c"; | 653 | compatible = "atmel,at91sam9x5-i2c"; |
| 573 | reg = <0xf8018000 0x100>; | 654 | reg = <0xf8018000 0x100>; |
| 574 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; | 655 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; |
| 575 | dmas = <&dma0 1 9>, | 656 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>, |
| 576 | <&dma0 1 10>; | 657 | <&dma0 1 AT91_DMA_CFG_PER_ID(10)>; |
| 577 | dma-names = "tx", "rx"; | 658 | dma-names = "tx", "rx"; |
| 578 | #address-cells = <1>; | 659 | #address-cells = <1>; |
| 579 | #size-cells = <0>; | 660 | #size-cells = <0>; |
| @@ -582,6 +663,24 @@ | |||
| 582 | status = "disabled"; | 663 | status = "disabled"; |
| 583 | }; | 664 | }; |
| 584 | 665 | ||
| 666 | uart0: serial@f8040000 { | ||
| 667 | compatible = "atmel,at91sam9260-usart"; | ||
| 668 | reg = <0xf8040000 0x200>; | ||
| 669 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; | ||
| 670 | pinctrl-names = "default"; | ||
| 671 | pinctrl-0 = <&pinctrl_uart0>; | ||
| 672 | status = "disabled"; | ||
| 673 | }; | ||
| 674 | |||
| 675 | uart1: serial@f8044000 { | ||
| 676 | compatible = "atmel,at91sam9260-usart"; | ||
| 677 | reg = <0xf8044000 0x200>; | ||
| 678 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; | ||
| 679 | pinctrl-names = "default"; | ||
| 680 | pinctrl-0 = <&pinctrl_uart1>; | ||
| 681 | status = "disabled"; | ||
| 682 | }; | ||
| 683 | |||
| 585 | adc0: adc@f804c000 { | 684 | adc0: adc@f804c000 { |
| 586 | compatible = "atmel,at91sam9260-adc"; | 685 | compatible = "atmel,at91sam9260-adc"; |
| 587 | reg = <0xf804c000 0x100>; | 686 | reg = <0xf804c000 0x100>; |
| @@ -629,6 +728,9 @@ | |||
| 629 | compatible = "atmel,at91rm9200-spi"; | 728 | compatible = "atmel,at91rm9200-spi"; |
| 630 | reg = <0xf0000000 0x100>; | 729 | reg = <0xf0000000 0x100>; |
| 631 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; | 730 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; |
| 731 | dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>, | ||
| 732 | <&dma0 1 AT91_DMA_CFG_PER_ID(2)>; | ||
| 733 | dma-names = "tx", "rx"; | ||
| 632 | pinctrl-names = "default"; | 734 | pinctrl-names = "default"; |
| 633 | pinctrl-0 = <&pinctrl_spi0>; | 735 | pinctrl-0 = <&pinctrl_spi0>; |
| 634 | status = "disabled"; | 736 | status = "disabled"; |
| @@ -640,13 +742,84 @@ | |||
| 640 | compatible = "atmel,at91rm9200-spi"; | 742 | compatible = "atmel,at91rm9200-spi"; |
| 641 | reg = <0xf0004000 0x100>; | 743 | reg = <0xf0004000 0x100>; |
| 642 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; | 744 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; |
| 745 | dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>, | ||
| 746 | <&dma1 1 AT91_DMA_CFG_PER_ID(2)>; | ||
| 747 | dma-names = "tx", "rx"; | ||
| 643 | pinctrl-names = "default"; | 748 | pinctrl-names = "default"; |
| 644 | pinctrl-0 = <&pinctrl_spi1>; | 749 | pinctrl-0 = <&pinctrl_spi1>; |
| 645 | status = "disabled"; | 750 | status = "disabled"; |
| 646 | }; | 751 | }; |
| 647 | 752 | ||
| 753 | usb2: gadget@f803c000 { | ||
| 754 | #address-cells = <1>; | ||
| 755 | #size-cells = <0>; | ||
| 756 | compatible = "atmel,at91sam9rl-udc"; | ||
| 757 | reg = <0x00500000 0x80000 | ||
| 758 | 0xf803c000 0x400>; | ||
| 759 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; | ||
| 760 | status = "disabled"; | ||
| 761 | |||
| 762 | ep0 { | ||
| 763 | reg = <0>; | ||
| 764 | atmel,fifo-size = <64>; | ||
| 765 | atmel,nb-banks = <1>; | ||
| 766 | }; | ||
| 767 | |||
| 768 | ep1 { | ||
| 769 | reg = <1>; | ||
| 770 | atmel,fifo-size = <1024>; | ||
| 771 | atmel,nb-banks = <2>; | ||
| 772 | atmel,can-dma; | ||
| 773 | atmel,can-isoc; | ||
| 774 | }; | ||
| 775 | |||
| 776 | ep2 { | ||
| 777 | reg = <2>; | ||
| 778 | atmel,fifo-size = <1024>; | ||
| 779 | atmel,nb-banks = <2>; | ||
| 780 | atmel,can-dma; | ||
| 781 | atmel,can-isoc; | ||
| 782 | }; | ||
| 783 | |||
| 784 | ep3 { | ||
| 785 | reg = <3>; | ||
| 786 | atmel,fifo-size = <1024>; | ||
| 787 | atmel,nb-banks = <3>; | ||
| 788 | atmel,can-dma; | ||
| 789 | }; | ||
| 790 | |||
| 791 | ep4 { | ||
| 792 | reg = <4>; | ||
| 793 | atmel,fifo-size = <1024>; | ||
| 794 | atmel,nb-banks = <3>; | ||
| 795 | atmel,can-dma; | ||
| 796 | }; | ||
| 797 | |||
| 798 | ep5 { | ||
| 799 | reg = <5>; | ||
| 800 | atmel,fifo-size = <1024>; | ||
| 801 | atmel,nb-banks = <3>; | ||
| 802 | atmel,can-dma; | ||
| 803 | atmel,can-isoc; | ||
| 804 | }; | ||
| 805 | |||
| 806 | ep6 { | ||
| 807 | reg = <6>; | ||
| 808 | atmel,fifo-size = <1024>; | ||
| 809 | atmel,nb-banks = <3>; | ||
| 810 | atmel,can-dma; | ||
| 811 | atmel,can-isoc; | ||
| 812 | }; | ||
| 813 | }; | ||
| 814 | |||
| 815 | watchdog@fffffe40 { | ||
| 816 | compatible = "atmel,at91sam9260-wdt"; | ||
| 817 | reg = <0xfffffe40 0x10>; | ||
| 818 | status = "disabled"; | ||
| 819 | }; | ||
| 820 | |||
| 648 | rtc@fffffeb0 { | 821 | rtc@fffffeb0 { |
| 649 | compatible = "atmel,at91rm9200-rtc"; | 822 | compatible = "atmel,at91sam9x5-rtc"; |
| 650 | reg = <0xfffffeb0 0x40>; | 823 | reg = <0xfffffeb0 0x40>; |
| 651 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | 824 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
| 652 | status = "disabled"; | 825 | status = "disabled"; |
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index 19c8ebb303f4..b753855b2058 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi | |||
| @@ -52,6 +52,11 @@ | |||
| 52 | status = "okay"; | 52 | status = "okay"; |
| 53 | }; | 53 | }; |
| 54 | 54 | ||
| 55 | usb2: gadget@f803c000 { | ||
| 56 | atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; | ||
| 57 | status = "okay"; | ||
| 58 | }; | ||
| 59 | |||
| 55 | i2c0: i2c@f8010000 { | 60 | i2c0: i2c@f8010000 { |
| 56 | status = "okay"; | 61 | status = "okay"; |
| 57 | }; | 62 | }; |
| @@ -81,6 +86,10 @@ | |||
| 81 | reg = <0>; | 86 | reg = <0>; |
| 82 | }; | 87 | }; |
| 83 | }; | 88 | }; |
| 89 | |||
| 90 | watchdog@fffffe40 { | ||
| 91 | status = "okay"; | ||
| 92 | }; | ||
| 84 | }; | 93 | }; |
| 85 | 94 | ||
| 86 | usb0: ohci@00600000 { | 95 | usb0: ohci@00600000 { |
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts index 248067cf7069..67ec524098b5 100644 --- a/arch/arm/boot/dts/bcm11351-brt.dts +++ b/arch/arm/boot/dts/bcm11351-brt.dts | |||
| @@ -13,7 +13,7 @@ | |||
| 13 | 13 | ||
| 14 | /dts-v1/; | 14 | /dts-v1/; |
| 15 | 15 | ||
| 16 | /include/ "bcm11351.dtsi" | 16 | #include "bcm11351.dtsi" |
| 17 | 17 | ||
| 18 | / { | 18 | / { |
| 19 | model = "BCM11351 BRT board"; | 19 | model = "BCM11351 BRT board"; |
| @@ -27,4 +27,21 @@ | |||
| 27 | status = "okay"; | 27 | status = "okay"; |
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | sdio0: sdio@0x3f180000 { | ||
| 31 | max-frequency = <48000000>; | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | sdio1: sdio@0x3f190000 { | ||
| 36 | non-removable; | ||
| 37 | max-frequency = <48000000>; | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | sdio3: sdio@0x3f1b0000 { | ||
| 42 | max-frequency = <48000000>; | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | |||
| 30 | }; | 47 | }; |
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 41b2c6c33f09..17979d5f23b4 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi | |||
| @@ -11,7 +11,10 @@ | |||
| 11 | * GNU General Public License for more details. | 11 | * GNU General Public License for more details. |
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | /include/ "skeleton.dtsi" | 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 16 | |||
| 17 | #include "skeleton.dtsi" | ||
| 15 | 18 | ||
| 16 | / { | 19 | / { |
| 17 | model = "BCM11351 SoC"; | 20 | model = "BCM11351 SoC"; |
| @@ -33,7 +36,7 @@ | |||
| 33 | 36 | ||
| 34 | smc@0x3404c000 { | 37 | smc@0x3404c000 { |
| 35 | compatible = "bcm,bcm11351-smc", "bcm,kona-smc"; | 38 | compatible = "bcm,bcm11351-smc", "bcm,kona-smc"; |
| 36 | reg = <0x3404c000 0x400>; //1 KiB in SRAM | 39 | reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ |
| 37 | }; | 40 | }; |
| 38 | 41 | ||
| 39 | uart@3e000000 { | 42 | uart@3e000000 { |
| @@ -41,7 +44,7 @@ | |||
| 41 | status = "disabled"; | 44 | status = "disabled"; |
| 42 | reg = <0x3e000000 0x1000>; | 45 | reg = <0x3e000000 0x1000>; |
| 43 | clock-frequency = <13000000>; | 46 | clock-frequency = <13000000>; |
| 44 | interrupts = <0x0 67 0x4>; | 47 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| 45 | reg-shift = <2>; | 48 | reg-shift = <2>; |
| 46 | reg-io-width = <4>; | 49 | reg-io-width = <4>; |
| 47 | }; | 50 | }; |
| @@ -56,8 +59,36 @@ | |||
| 56 | timer@35006000 { | 59 | timer@35006000 { |
| 57 | compatible = "bcm,kona-timer"; | 60 | compatible = "bcm,kona-timer"; |
| 58 | reg = <0x35006000 0x1000>; | 61 | reg = <0x35006000 0x1000>; |
| 59 | interrupts = <0x0 7 0x4>; | 62 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 60 | clock-frequency = <32768>; | 63 | clock-frequency = <32768>; |
| 61 | }; | 64 | }; |
| 62 | 65 | ||
| 66 | sdio0: sdio@0x3f180000 { | ||
| 67 | compatible = "bcm,kona-sdhci"; | ||
| 68 | reg = <0x3f180000 0x10000>; | ||
| 69 | interrupts = <0x0 77 0x4>; | ||
| 70 | status = "disabled"; | ||
| 71 | }; | ||
| 72 | |||
| 73 | sdio1: sdio@0x3f190000 { | ||
| 74 | compatible = "bcm,kona-sdhci"; | ||
| 75 | reg = <0x3f190000 0x10000>; | ||
| 76 | interrupts = <0x0 76 0x4>; | ||
| 77 | status = "disabled"; | ||
| 78 | }; | ||
| 79 | |||
| 80 | sdio2: sdio@0x3f1a0000 { | ||
| 81 | compatible = "bcm,kona-sdhci"; | ||
| 82 | reg = <0x3f1a0000 0x10000>; | ||
| 83 | interrupts = <0x0 74 0x4>; | ||
| 84 | status = "disabled"; | ||
| 85 | }; | ||
| 86 | |||
| 87 | sdio3: sdio@0x3f1b0000 { | ||
| 88 | compatible = "bcm,kona-sdhci"; | ||
| 89 | reg = <0x3f1b0000 0x10000>; | ||
| 90 | interrupts = <0x0 73 0x4>; | ||
| 91 | status = "disabled"; | ||
| 92 | }; | ||
| 93 | |||
| 63 | }; | 94 | }; |
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index aafda174a605..6e9deb786a7d 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts | |||
| @@ -8,6 +8,17 @@ | |||
| 8 | memory { | 8 | memory { |
| 9 | reg = <0 0x10000000>; | 9 | reg = <0 0x10000000>; |
| 10 | }; | 10 | }; |
| 11 | |||
| 12 | leds { | ||
| 13 | compatible = "gpio-leds"; | ||
| 14 | |||
| 15 | act { | ||
| 16 | label = "ACT"; | ||
| 17 | gpios = <&gpio 16 1>; | ||
| 18 | default-state = "keep"; | ||
| 19 | linux,default-trigger = "heartbeat"; | ||
| 20 | }; | ||
| 21 | }; | ||
| 11 | }; | 22 | }; |
| 12 | 23 | ||
| 13 | &gpio { | 24 | &gpio { |
diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts new file mode 100644 index 000000000000..48ff03441f5a --- /dev/null +++ b/arch/arm/boot/dts/ccu8540.dts | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 ST-Ericsson AB | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "dbx5x0.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "ST-Ericsson U8540 platform with Device Tree"; | ||
| 17 | compatible = "st-ericsson,ccu8540", "st-ericsson,u8540"; | ||
| 18 | |||
| 19 | memory@0 { | ||
| 20 | reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | soc { | ||
| 24 | prcmu@80157000 { | ||
| 25 | reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>; | ||
| 26 | reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | uart@80120000 { | ||
| 30 | status = "okay"; | ||
| 31 | }; | ||
| 32 | |||
| 33 | uart@80121000 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
| 36 | |||
| 37 | uart@80007000 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | }; | ||
diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts index 04305463f00d..ed29ec7288e4 100644 --- a/arch/arm/boot/dts/ccu9540.dts +++ b/arch/arm/boot/dts/ccu9540.dts | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | /include/ "dbx5x0.dtsi" | 13 | #include "dbx5x0.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | model = "ST-Ericsson CCU9540 platform with Device Tree"; | 16 | model = "ST-Ericsson CCU9540 platform with Device Tree"; |
| @@ -20,7 +20,7 @@ | |||
| 20 | reg = <0x00000000 0x20000000>; | 20 | reg = <0x00000000 0x20000000>; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | soc-u9500 { | 23 | soc { |
| 24 | uart@80120000 { | 24 | uart@80120000 { |
| 25 | status = "okay"; | 25 | status = "okay"; |
| 26 | }; | 26 | }; |
| @@ -52,7 +52,7 @@ | |||
| 52 | // WLAN SDIO channel | 52 | // WLAN SDIO channel |
| 53 | sdi1_per2@80118000 { | 53 | sdi1_per2@80118000 { |
| 54 | arm,primecell-periphid = <0x10480180>; | 54 | arm,primecell-periphid = <0x10480180>; |
| 55 | max-frequency = <50000000>; | 55 | max-frequency = <100000000>; |
| 56 | bus-width = <4>; | 56 | bus-width = <4>; |
| 57 | 57 | ||
| 58 | status = "okay"; | 58 | status = "okay"; |
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index b6bc4ff17f26..a082f0ba1ddb 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi | |||
| @@ -9,10 +9,11 @@ | |||
| 9 | * http://www.gnu.org/copyleft/gpl.html | 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /include/ "skeleton.dtsi" | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
| 13 | #include "skeleton.dtsi" | ||
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| 15 | soc-u9500 { | 16 | soc { |
| 16 | #address-cells = <1>; | 17 | #address-cells = <1>; |
| 17 | #size-cells = <1>; | 18 | #size-cells = <1>; |
| 18 | compatible = "stericsson,db8500"; | 19 | compatible = "stericsson,db8500"; |
| @@ -31,33 +32,33 @@ | |||
| 31 | L2: l2-cache { | 32 | L2: l2-cache { |
| 32 | compatible = "arm,pl310-cache"; | 33 | compatible = "arm,pl310-cache"; |
| 33 | reg = <0xa0412000 0x1000>; | 34 | reg = <0xa0412000 0x1000>; |
| 34 | interrupts = <0 13 4>; | 35 | interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; |
| 35 | cache-unified; | 36 | cache-unified; |
| 36 | cache-level = <2>; | 37 | cache-level = <2>; |
| 37 | }; | 38 | }; |
| 38 | 39 | ||
| 39 | pmu { | 40 | pmu { |
| 40 | compatible = "arm,cortex-a9-pmu"; | 41 | compatible = "arm,cortex-a9-pmu"; |
| 41 | interrupts = <0 7 0x4>; | 42 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| 42 | }; | 43 | }; |
| 43 | 44 | ||
| 44 | timer@a0410600 { | 45 | timer@a0410600 { |
| 45 | compatible = "arm,cortex-a9-twd-timer"; | 46 | compatible = "arm,cortex-a9-twd-timer"; |
| 46 | reg = <0xa0410600 0x20>; | 47 | reg = <0xa0410600 0x20>; |
| 47 | interrupts = <1 13 0x304>; | 48 | interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ |
| 48 | }; | 49 | }; |
| 49 | 50 | ||
| 50 | rtc@80154000 { | 51 | rtc@80154000 { |
| 51 | compatible = "arm,rtc-pl031", "arm,primecell"; | 52 | compatible = "arm,rtc-pl031", "arm,primecell"; |
| 52 | reg = <0x80154000 0x1000>; | 53 | reg = <0x80154000 0x1000>; |
| 53 | interrupts = <0 18 0x4>; | 54 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; |
| 54 | }; | 55 | }; |
| 55 | 56 | ||
| 56 | gpio0: gpio@8012e000 { | 57 | gpio0: gpio@8012e000 { |
| 57 | compatible = "stericsson,db8500-gpio", | 58 | compatible = "stericsson,db8500-gpio", |
| 58 | "st,nomadik-gpio"; | 59 | "st,nomadik-gpio"; |
| 59 | reg = <0x8012e000 0x80>; | 60 | reg = <0x8012e000 0x80>; |
| 60 | interrupts = <0 119 0x4>; | 61 | interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; |
| 61 | interrupt-controller; | 62 | interrupt-controller; |
| 62 | #interrupt-cells = <2>; | 63 | #interrupt-cells = <2>; |
| 63 | st,supports-sleepmode; | 64 | st,supports-sleepmode; |
| @@ -70,7 +71,7 @@ | |||
| 70 | compatible = "stericsson,db8500-gpio", | 71 | compatible = "stericsson,db8500-gpio", |
| 71 | "st,nomadik-gpio"; | 72 | "st,nomadik-gpio"; |
| 72 | reg = <0x8012e080 0x80>; | 73 | reg = <0x8012e080 0x80>; |
| 73 | interrupts = <0 120 0x4>; | 74 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; |
| 74 | interrupt-controller; | 75 | interrupt-controller; |
| 75 | #interrupt-cells = <2>; | 76 | #interrupt-cells = <2>; |
| 76 | st,supports-sleepmode; | 77 | st,supports-sleepmode; |
| @@ -83,7 +84,7 @@ | |||
| 83 | compatible = "stericsson,db8500-gpio", | 84 | compatible = "stericsson,db8500-gpio", |
| 84 | "st,nomadik-gpio"; | 85 | "st,nomadik-gpio"; |
| 85 | reg = <0x8000e000 0x80>; | 86 | reg = <0x8000e000 0x80>; |
| 86 | interrupts = <0 121 0x4>; | 87 | interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>; |
| 87 | interrupt-controller; | 88 | interrupt-controller; |
| 88 | #interrupt-cells = <2>; | 89 | #interrupt-cells = <2>; |
| 89 | st,supports-sleepmode; | 90 | st,supports-sleepmode; |
| @@ -96,7 +97,7 @@ | |||
| 96 | compatible = "stericsson,db8500-gpio", | 97 | compatible = "stericsson,db8500-gpio", |
| 97 | "st,nomadik-gpio"; | 98 | "st,nomadik-gpio"; |
| 98 | reg = <0x8000e080 0x80>; | 99 | reg = <0x8000e080 0x80>; |
| 99 | interrupts = <0 122 0x4>; | 100 | interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>; |
| 100 | interrupt-controller; | 101 | interrupt-controller; |
| 101 | #interrupt-cells = <2>; | 102 | #interrupt-cells = <2>; |
| 102 | st,supports-sleepmode; | 103 | st,supports-sleepmode; |
| @@ -109,7 +110,7 @@ | |||
| 109 | compatible = "stericsson,db8500-gpio", | 110 | compatible = "stericsson,db8500-gpio", |
| 110 | "st,nomadik-gpio"; | 111 | "st,nomadik-gpio"; |
| 111 | reg = <0x8000e100 0x80>; | 112 | reg = <0x8000e100 0x80>; |
| 112 | interrupts = <0 123 0x4>; | 113 | interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; |
| 113 | interrupt-controller; | 114 | interrupt-controller; |
| 114 | #interrupt-cells = <2>; | 115 | #interrupt-cells = <2>; |
| 115 | st,supports-sleepmode; | 116 | st,supports-sleepmode; |
| @@ -122,7 +123,7 @@ | |||
| 122 | compatible = "stericsson,db8500-gpio", | 123 | compatible = "stericsson,db8500-gpio", |
| 123 | "st,nomadik-gpio"; | 124 | "st,nomadik-gpio"; |
| 124 | reg = <0x8000e180 0x80>; | 125 | reg = <0x8000e180 0x80>; |
| 125 | interrupts = <0 124 0x4>; | 126 | interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; |
| 126 | interrupt-controller; | 127 | interrupt-controller; |
| 127 | #interrupt-cells = <2>; | 128 | #interrupt-cells = <2>; |
| 128 | st,supports-sleepmode; | 129 | st,supports-sleepmode; |
| @@ -135,7 +136,7 @@ | |||
| 135 | compatible = "stericsson,db8500-gpio", | 136 | compatible = "stericsson,db8500-gpio", |
| 136 | "st,nomadik-gpio"; | 137 | "st,nomadik-gpio"; |
| 137 | reg = <0x8011e000 0x80>; | 138 | reg = <0x8011e000 0x80>; |
| 138 | interrupts = <0 125 0x4>; | 139 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; |
| 139 | interrupt-controller; | 140 | interrupt-controller; |
| 140 | #interrupt-cells = <2>; | 141 | #interrupt-cells = <2>; |
| 141 | st,supports-sleepmode; | 142 | st,supports-sleepmode; |
| @@ -148,7 +149,7 @@ | |||
| 148 | compatible = "stericsson,db8500-gpio", | 149 | compatible = "stericsson,db8500-gpio", |
| 149 | "st,nomadik-gpio"; | 150 | "st,nomadik-gpio"; |
| 150 | reg = <0x8011e080 0x80>; | 151 | reg = <0x8011e080 0x80>; |
| 151 | interrupts = <0 126 0x4>; | 152 | interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; |
| 152 | interrupt-controller; | 153 | interrupt-controller; |
| 153 | #interrupt-cells = <2>; | 154 | #interrupt-cells = <2>; |
| 154 | st,supports-sleepmode; | 155 | st,supports-sleepmode; |
| @@ -161,7 +162,7 @@ | |||
| 161 | compatible = "stericsson,db8500-gpio", | 162 | compatible = "stericsson,db8500-gpio", |
| 162 | "st,nomadik-gpio"; | 163 | "st,nomadik-gpio"; |
| 163 | reg = <0xa03fe000 0x80>; | 164 | reg = <0xa03fe000 0x80>; |
| 164 | interrupts = <0 127 0x4>; | 165 | interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>; |
| 165 | interrupt-controller; | 166 | interrupt-controller; |
| 166 | #interrupt-cells = <2>; | 167 | #interrupt-cells = <2>; |
| 167 | st,supports-sleepmode; | 168 | st,supports-sleepmode; |
| @@ -171,29 +172,61 @@ | |||
| 171 | }; | 172 | }; |
| 172 | 173 | ||
| 173 | pinctrl { | 174 | pinctrl { |
| 174 | compatible = "stericsson,nmk-pinctrl"; | 175 | compatible = "stericsson,db8500-pinctrl"; |
| 175 | prcm = <&prcmu>; | 176 | prcm = <&prcmu>; |
| 176 | }; | 177 | }; |
| 177 | 178 | ||
| 178 | usb@a03e0000 { | 179 | usb_per5@a03e0000 { |
| 179 | compatible = "stericsson,db8500-musb", | 180 | compatible = "stericsson,db8500-musb", |
| 180 | "mentor,musb"; | 181 | "mentor,musb"; |
| 181 | reg = <0xa03e0000 0x10000>; | 182 | reg = <0xa03e0000 0x10000>; |
| 182 | interrupts = <0 23 0x4>; | 183 | interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
| 183 | }; | 184 | interrupt-names = "mc"; |
| 184 | 185 | ||
| 185 | dma-controller@801C0000 { | 186 | dr_mode = "otg"; |
| 186 | compatible = "stericsson,db8500-dma40", | 187 | |
| 187 | "stericsson,dma40"; | 188 | dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ |
| 189 | <&dma 38 0 0x0>, /* Logical - MemToDev */ | ||
| 190 | <&dma 37 0 0x2>, /* Logical - DevToMem */ | ||
| 191 | <&dma 37 0 0x0>, /* Logical - MemToDev */ | ||
| 192 | <&dma 36 0 0x2>, /* Logical - DevToMem */ | ||
| 193 | <&dma 36 0 0x0>, /* Logical - MemToDev */ | ||
| 194 | <&dma 19 0 0x2>, /* Logical - DevToMem */ | ||
| 195 | <&dma 19 0 0x0>, /* Logical - MemToDev */ | ||
| 196 | <&dma 18 0 0x2>, /* Logical - DevToMem */ | ||
| 197 | <&dma 18 0 0x0>, /* Logical - MemToDev */ | ||
| 198 | <&dma 17 0 0x2>, /* Logical - DevToMem */ | ||
| 199 | <&dma 17 0 0x0>, /* Logical - MemToDev */ | ||
| 200 | <&dma 16 0 0x2>, /* Logical - DevToMem */ | ||
| 201 | <&dma 16 0 0x0>, /* Logical - MemToDev */ | ||
| 202 | <&dma 39 0 0x2>, /* Logical - DevToMem */ | ||
| 203 | <&dma 39 0 0x0>; /* Logical - MemToDev */ | ||
| 204 | |||
| 205 | dma-names = "iep_1_9", "oep_1_9", | ||
| 206 | "iep_2_10", "oep_2_10", | ||
| 207 | "iep_3_11", "oep_3_11", | ||
| 208 | "iep_4_12", "oep_4_12", | ||
| 209 | "iep_5_13", "oep_5_13", | ||
| 210 | "iep_6_14", "oep_6_14", | ||
| 211 | "iep_7_15", "oep_7_15", | ||
| 212 | "iep_8", "oep_8"; | ||
| 213 | }; | ||
| 214 | |||
| 215 | dma: dma-controller@801C0000 { | ||
| 216 | compatible = "stericsson,db8500-dma40", "stericsson,dma40"; | ||
| 188 | reg = <0x801C0000 0x1000 0x40010000 0x800>; | 217 | reg = <0x801C0000 0x1000 0x40010000 0x800>; |
| 189 | interrupts = <0 25 0x4>; | 218 | reg-names = "base", "lcpa"; |
| 219 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; | ||
| 220 | |||
| 221 | #dma-cells = <3>; | ||
| 222 | memcpy-channels = <56 57 58 59 60>; | ||
| 190 | }; | 223 | }; |
| 191 | 224 | ||
| 192 | prcmu: prcmu@80157000 { | 225 | prcmu: prcmu@80157000 { |
| 193 | compatible = "stericsson,db8500-prcmu"; | 226 | compatible = "stericsson,db8500-prcmu"; |
| 194 | reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; | 227 | reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; |
| 195 | reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; | 228 | reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; |
| 196 | interrupts = <0 47 0x4>; | 229 | interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
| 197 | #address-cells = <1>; | 230 | #address-cells = <1>; |
| 198 | #size-cells = <1>; | 231 | #size-cells = <1>; |
| 199 | interrupt-controller; | 232 | interrupt-controller; |
| @@ -208,7 +241,8 @@ | |||
| 208 | thermal@801573c0 { | 241 | thermal@801573c0 { |
| 209 | compatible = "stericsson,db8500-thermal"; | 242 | compatible = "stericsson,db8500-thermal"; |
| 210 | reg = <0x801573c0 0x40>; | 243 | reg = <0x801573c0 0x40>; |
| 211 | interrupts = <21 0x4>, <22 0x4>; | 244 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, |
| 245 | <22 IRQ_TYPE_LEVEL_HIGH>; | ||
| 212 | interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; | 246 | interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; |
| 213 | status = "disabled"; | 247 | status = "disabled"; |
| 214 | }; | 248 | }; |
| @@ -322,21 +356,21 @@ | |||
| 322 | ab8500 { | 356 | ab8500 { |
| 323 | compatible = "stericsson,ab8500"; | 357 | compatible = "stericsson,ab8500"; |
| 324 | interrupt-parent = <&intc>; | 358 | interrupt-parent = <&intc>; |
| 325 | interrupts = <0 40 0x4>; | 359 | interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
| 326 | interrupt-controller; | 360 | interrupt-controller; |
| 327 | #interrupt-cells = <2>; | 361 | #interrupt-cells = <2>; |
| 328 | 362 | ||
| 329 | ab8500-rtc { | 363 | ab8500-rtc { |
| 330 | compatible = "stericsson,ab8500-rtc"; | 364 | compatible = "stericsson,ab8500-rtc"; |
| 331 | interrupts = <17 0x4 | 365 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH |
| 332 | 18 0x4>; | 366 | 18 IRQ_TYPE_LEVEL_HIGH>; |
| 333 | interrupt-names = "60S", "ALARM"; | 367 | interrupt-names = "60S", "ALARM"; |
| 334 | }; | 368 | }; |
| 335 | 369 | ||
| 336 | ab8500-gpadc { | 370 | ab8500-gpadc { |
| 337 | compatible = "stericsson,ab8500-gpadc"; | 371 | compatible = "stericsson,ab8500-gpadc"; |
| 338 | interrupts = <32 0x4 | 372 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH |
| 339 | 39 0x4>; | 373 | 39 IRQ_TYPE_LEVEL_HIGH>; |
| 340 | interrupt-names = "HW_CONV_END", "SW_CONV_END"; | 374 | interrupt-names = "HW_CONV_END", "SW_CONV_END"; |
| 341 | vddadc-supply = <&ab8500_ldo_tvout_reg>; | 375 | vddadc-supply = <&ab8500_ldo_tvout_reg>; |
| 342 | }; | 376 | }; |
| @@ -369,13 +403,13 @@ | |||
| 369 | 403 | ||
| 370 | ab8500_usb { | 404 | ab8500_usb { |
| 371 | compatible = "stericsson,ab8500-usb"; | 405 | compatible = "stericsson,ab8500-usb"; |
| 372 | interrupts = < 90 0x4 | 406 | interrupts = < 90 IRQ_TYPE_LEVEL_HIGH |
| 373 | 96 0x4 | 407 | 96 IRQ_TYPE_LEVEL_HIGH |
| 374 | 14 0x4 | 408 | 14 IRQ_TYPE_LEVEL_HIGH |
| 375 | 15 0x4 | 409 | 15 IRQ_TYPE_LEVEL_HIGH |
| 376 | 79 0x4 | 410 | 79 IRQ_TYPE_LEVEL_HIGH |
| 377 | 74 0x4 | 411 | 74 IRQ_TYPE_LEVEL_HIGH |
| 378 | 75 0x4>; | 412 | 75 IRQ_TYPE_LEVEL_HIGH>; |
| 379 | interrupt-names = "ID_WAKEUP_R", | 413 | interrupt-names = "ID_WAKEUP_R", |
| 380 | "ID_WAKEUP_F", | 414 | "ID_WAKEUP_F", |
| 381 | "VBUS_DET_F", | 415 | "VBUS_DET_F", |
| @@ -383,15 +417,15 @@ | |||
| 383 | "USB_LINK_STATUS", | 417 | "USB_LINK_STATUS", |
| 384 | "USB_ADP_PROBE_PLUG", | 418 | "USB_ADP_PROBE_PLUG", |
| 385 | "USB_ADP_PROBE_UNPLUG"; | 419 | "USB_ADP_PROBE_UNPLUG"; |
| 386 | vddulpivio18-supply = <&ab8500_ldo_initcore_reg>; | 420 | vddulpivio18-supply = <&ab8500_ldo_intcore_reg>; |
| 387 | v-ape-supply = <&db8500_vape_reg>; | 421 | v-ape-supply = <&db8500_vape_reg>; |
| 388 | musb_1v8-supply = <&db8500_vsmps2_reg>; | 422 | musb_1v8-supply = <&db8500_vsmps2_reg>; |
| 389 | }; | 423 | }; |
| 390 | 424 | ||
| 391 | ab8500-ponkey { | 425 | ab8500-ponkey { |
| 392 | compatible = "stericsson,ab8500-poweron-key"; | 426 | compatible = "stericsson,ab8500-poweron-key"; |
| 393 | interrupts = <6 0x4 | 427 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH |
| 394 | 7 0x4>; | 428 | 7 IRQ_TYPE_LEVEL_HIGH>; |
| 395 | interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; | 429 | interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; |
| 396 | }; | 430 | }; |
| 397 | 431 | ||
| @@ -410,6 +444,11 @@ | |||
| 410 | codec: ab8500-codec { | 444 | codec: ab8500-codec { |
| 411 | compatible = "stericsson,ab8500-codec"; | 445 | compatible = "stericsson,ab8500-codec"; |
| 412 | 446 | ||
| 447 | V-AUD-supply = <&ab8500_ldo_audio_reg>; | ||
| 448 | V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>; | ||
| 449 | V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>; | ||
| 450 | V-DMIC-supply = <&ab8500_ldo_dmic_reg>; | ||
| 451 | |||
| 413 | stericsson,earpeice-cmv = <950>; /* Units in mV. */ | 452 | stericsson,earpeice-cmv = <950>; /* Units in mV. */ |
| 414 | }; | 453 | }; |
| 415 | 454 | ||
| @@ -441,8 +480,8 @@ | |||
| 441 | }; | 480 | }; |
| 442 | 481 | ||
| 443 | // supply for v-intcore12; VINTCORE12 LDO | 482 | // supply for v-intcore12; VINTCORE12 LDO |
| 444 | ab8500_ldo_initcore_reg: ab8500_ldo_initcore { | 483 | ab8500_ldo_intcore_reg: ab8500_ldo_intcore { |
| 445 | regulator-compatible = "ab8500_ldo_initcore"; | 484 | regulator-compatible = "ab8500_ldo_intcore"; |
| 446 | }; | 485 | }; |
| 447 | 486 | ||
| 448 | // supply for tvout; gpadc; TVOUT LDO | 487 | // supply for tvout; gpadc; TVOUT LDO |
| @@ -460,14 +499,14 @@ | |||
| 460 | regulator-compatible = "ab8500_ldo_audio"; | 499 | regulator-compatible = "ab8500_ldo_audio"; |
| 461 | }; | 500 | }; |
| 462 | 501 | ||
| 463 | // supply for v-anamic1 VAMic1-LDO | 502 | // supply for v-anamic1 VAMIC1 LDO |
| 464 | ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { | 503 | ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { |
| 465 | regulator-compatible = "ab8500_ldo_anamic1"; | 504 | regulator-compatible = "ab8500_ldo_anamic1"; |
| 466 | }; | 505 | }; |
| 467 | 506 | ||
| 468 | // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 | 507 | // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 |
| 469 | ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { | 508 | ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { |
| 470 | regulator-compatible = "ab8500_ldo_amamic2"; | 509 | regulator-compatible = "ab8500_ldo_anamic2"; |
| 471 | }; | 510 | }; |
| 472 | 511 | ||
| 473 | // supply for v-dmic; VDMIC LDO | 512 | // supply for v-dmic; VDMIC LDO |
| @@ -486,7 +525,7 @@ | |||
| 486 | i2c@80004000 { | 525 | i2c@80004000 { |
| 487 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; | 526 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
| 488 | reg = <0x80004000 0x1000>; | 527 | reg = <0x80004000 0x1000>; |
| 489 | interrupts = <0 21 0x4>; | 528 | interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; |
| 490 | arm,primecell-periphid = <0x180024>; | 529 | arm,primecell-periphid = <0x180024>; |
| 491 | 530 | ||
| 492 | #address-cells = <1>; | 531 | #address-cells = <1>; |
| @@ -499,7 +538,7 @@ | |||
| 499 | i2c@80122000 { | 538 | i2c@80122000 { |
| 500 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; | 539 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
| 501 | reg = <0x80122000 0x1000>; | 540 | reg = <0x80122000 0x1000>; |
| 502 | interrupts = <0 22 0x4>; | 541 | interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
| 503 | arm,primecell-periphid = <0x180024>; | 542 | arm,primecell-periphid = <0x180024>; |
| 504 | 543 | ||
| 505 | #address-cells = <1>; | 544 | #address-cells = <1>; |
| @@ -512,7 +551,7 @@ | |||
| 512 | i2c@80128000 { | 551 | i2c@80128000 { |
| 513 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; | 552 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
| 514 | reg = <0x80128000 0x1000>; | 553 | reg = <0x80128000 0x1000>; |
| 515 | interrupts = <0 55 0x4>; | 554 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
| 516 | arm,primecell-periphid = <0x180024>; | 555 | arm,primecell-periphid = <0x180024>; |
| 517 | 556 | ||
| 518 | #address-cells = <1>; | 557 | #address-cells = <1>; |
| @@ -525,7 +564,7 @@ | |||
| 525 | i2c@80110000 { | 564 | i2c@80110000 { |
| 526 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; | 565 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
| 527 | reg = <0x80110000 0x1000>; | 566 | reg = <0x80110000 0x1000>; |
| 528 | interrupts = <0 12 0x4>; | 567 | interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; |
| 529 | arm,primecell-periphid = <0x180024>; | 568 | arm,primecell-periphid = <0x180024>; |
| 530 | 569 | ||
| 531 | #address-cells = <1>; | 570 | #address-cells = <1>; |
| @@ -538,7 +577,7 @@ | |||
| 538 | i2c@8012a000 { | 577 | i2c@8012a000 { |
| 539 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; | 578 | compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; |
| 540 | reg = <0x8012a000 0x1000>; | 579 | reg = <0x8012a000 0x1000>; |
| 541 | interrupts = <0 51 0x4>; | 580 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; |
| 542 | arm,primecell-periphid = <0x180024>; | 581 | arm,primecell-periphid = <0x180024>; |
| 543 | 582 | ||
| 544 | #address-cells = <1>; | 583 | #address-cells = <1>; |
| @@ -551,82 +590,114 @@ | |||
| 551 | ssp@80002000 { | 590 | ssp@80002000 { |
| 552 | compatible = "arm,pl022", "arm,primecell"; | 591 | compatible = "arm,pl022", "arm,primecell"; |
| 553 | reg = <0x80002000 0x1000>; | 592 | reg = <0x80002000 0x1000>; |
| 554 | interrupts = <0 14 0x4>; | 593 | interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
| 555 | #address-cells = <1>; | 594 | #address-cells = <1>; |
| 556 | #size-cells = <0>; | 595 | #size-cells = <0>; |
| 557 | status = "disabled"; | 596 | status = "disabled"; |
| 558 | |||
| 559 | // Add one of these for each child device | ||
| 560 | cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4 | ||
| 561 | &gpio6 22 0x4 &gpio7 0 0x4>; | ||
| 562 | |||
| 563 | }; | 597 | }; |
| 564 | 598 | ||
| 565 | uart@80120000 { | 599 | uart@80120000 { |
| 566 | compatible = "arm,pl011", "arm,primecell"; | 600 | compatible = "arm,pl011", "arm,primecell"; |
| 567 | reg = <0x80120000 0x1000>; | 601 | reg = <0x80120000 0x1000>; |
| 568 | interrupts = <0 11 0x4>; | 602 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
| 603 | |||
| 604 | dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ | ||
| 605 | <&dma 13 0 0x0>; /* Logical - MemToDev */ | ||
| 606 | dma-names = "rx", "tx"; | ||
| 607 | |||
| 569 | status = "disabled"; | 608 | status = "disabled"; |
| 570 | }; | 609 | }; |
| 610 | |||
| 571 | uart@80121000 { | 611 | uart@80121000 { |
| 572 | compatible = "arm,pl011", "arm,primecell"; | 612 | compatible = "arm,pl011", "arm,primecell"; |
| 573 | reg = <0x80121000 0x1000>; | 613 | reg = <0x80121000 0x1000>; |
| 574 | interrupts = <0 19 0x4>; | 614 | interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; |
| 615 | |||
| 616 | dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ | ||
| 617 | <&dma 12 0 0x0>; /* Logical - MemToDev */ | ||
| 618 | dma-names = "rx", "tx"; | ||
| 619 | |||
| 575 | status = "disabled"; | 620 | status = "disabled"; |
| 576 | }; | 621 | }; |
| 622 | |||
| 577 | uart@80007000 { | 623 | uart@80007000 { |
| 578 | compatible = "arm,pl011", "arm,primecell"; | 624 | compatible = "arm,pl011", "arm,primecell"; |
| 579 | reg = <0x80007000 0x1000>; | 625 | reg = <0x80007000 0x1000>; |
| 580 | interrupts = <0 26 0x4>; | 626 | interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
| 627 | |||
| 628 | dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ | ||
| 629 | <&dma 11 0 0x0>; /* Logical - MemToDev */ | ||
| 630 | dma-names = "rx", "tx"; | ||
| 631 | |||
| 581 | status = "disabled"; | 632 | status = "disabled"; |
| 582 | }; | 633 | }; |
| 583 | 634 | ||
| 584 | sdi0_per1@80126000 { | 635 | sdi0_per1@80126000 { |
| 585 | compatible = "arm,pl18x", "arm,primecell"; | 636 | compatible = "arm,pl18x", "arm,primecell"; |
| 586 | reg = <0x80126000 0x1000>; | 637 | reg = <0x80126000 0x1000>; |
| 587 | interrupts = <0 60 0x4>; | 638 | interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; |
| 639 | |||
| 640 | dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ | ||
| 641 | <&dma 29 0 0x0>; /* Logical - MemToDev */ | ||
| 642 | dma-names = "rx", "tx"; | ||
| 643 | |||
| 588 | status = "disabled"; | 644 | status = "disabled"; |
| 589 | }; | 645 | }; |
| 590 | 646 | ||
| 591 | sdi1_per2@80118000 { | 647 | sdi1_per2@80118000 { |
| 592 | compatible = "arm,pl18x", "arm,primecell"; | 648 | compatible = "arm,pl18x", "arm,primecell"; |
| 593 | reg = <0x80118000 0x1000>; | 649 | reg = <0x80118000 0x1000>; |
| 594 | interrupts = <0 50 0x4>; | 650 | interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; |
| 651 | |||
| 652 | dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ | ||
| 653 | <&dma 32 0 0x0>; /* Logical - MemToDev */ | ||
| 654 | dma-names = "rx", "tx"; | ||
| 655 | |||
| 595 | status = "disabled"; | 656 | status = "disabled"; |
| 596 | }; | 657 | }; |
| 597 | 658 | ||
| 598 | sdi2_per3@80005000 { | 659 | sdi2_per3@80005000 { |
| 599 | compatible = "arm,pl18x", "arm,primecell"; | 660 | compatible = "arm,pl18x", "arm,primecell"; |
| 600 | reg = <0x80005000 0x1000>; | 661 | reg = <0x80005000 0x1000>; |
| 601 | interrupts = <0 41 0x4>; | 662 | interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
| 663 | |||
| 664 | dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ | ||
| 665 | <&dma 28 0 0x0>; /* Logical - MemToDev */ | ||
| 666 | dma-names = "rx", "tx"; | ||
| 667 | |||
| 602 | status = "disabled"; | 668 | status = "disabled"; |
| 603 | }; | 669 | }; |
| 604 | 670 | ||
| 605 | sdi3_per2@80119000 { | 671 | sdi3_per2@80119000 { |
| 606 | compatible = "arm,pl18x", "arm,primecell"; | 672 | compatible = "arm,pl18x", "arm,primecell"; |
| 607 | reg = <0x80119000 0x1000>; | 673 | reg = <0x80119000 0x1000>; |
| 608 | interrupts = <0 59 0x4>; | 674 | interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; |
| 609 | status = "disabled"; | 675 | status = "disabled"; |
| 610 | }; | 676 | }; |
| 611 | 677 | ||
| 612 | sdi4_per2@80114000 { | 678 | sdi4_per2@80114000 { |
| 613 | compatible = "arm,pl18x", "arm,primecell"; | 679 | compatible = "arm,pl18x", "arm,primecell"; |
| 614 | reg = <0x80114000 0x1000>; | 680 | reg = <0x80114000 0x1000>; |
| 615 | interrupts = <0 99 0x4>; | 681 | interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>; |
| 682 | |||
| 683 | dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ | ||
| 684 | <&dma 42 0 0x0>; /* Logical - MemToDev */ | ||
| 685 | dma-names = "rx", "tx"; | ||
| 686 | |||
| 616 | status = "disabled"; | 687 | status = "disabled"; |
| 617 | }; | 688 | }; |
| 618 | 689 | ||
| 619 | sdi5_per3@80008000 { | 690 | sdi5_per3@80008000 { |
| 620 | compatible = "arm,pl18x", "arm,primecell"; | 691 | compatible = "arm,pl18x", "arm,primecell"; |
| 621 | reg = <0x80008000 0x1000>; | 692 | reg = <0x80008000 0x1000>; |
| 622 | interrupts = <0 100 0x4>; | 693 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; |
| 623 | status = "disabled"; | 694 | status = "disabled"; |
| 624 | }; | 695 | }; |
| 625 | 696 | ||
| 626 | msp0: msp@80123000 { | 697 | msp0: msp@80123000 { |
| 627 | compatible = "stericsson,ux500-msp-i2s"; | 698 | compatible = "stericsson,ux500-msp-i2s"; |
| 628 | reg = <0x80123000 0x1000>; | 699 | reg = <0x80123000 0x1000>; |
| 629 | interrupts = <0 31 0x4>; | 700 | interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
| 630 | v-ape-supply = <&db8500_vape_reg>; | 701 | v-ape-supply = <&db8500_vape_reg>; |
| 631 | status = "disabled"; | 702 | status = "disabled"; |
| 632 | }; | 703 | }; |
| @@ -634,7 +705,7 @@ | |||
| 634 | msp1: msp@80124000 { | 705 | msp1: msp@80124000 { |
| 635 | compatible = "stericsson,ux500-msp-i2s"; | 706 | compatible = "stericsson,ux500-msp-i2s"; |
| 636 | reg = <0x80124000 0x1000>; | 707 | reg = <0x80124000 0x1000>; |
| 637 | interrupts = <0 62 0x4>; | 708 | interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; |
| 638 | v-ape-supply = <&db8500_vape_reg>; | 709 | v-ape-supply = <&db8500_vape_reg>; |
| 639 | status = "disabled"; | 710 | status = "disabled"; |
| 640 | }; | 711 | }; |
| @@ -643,7 +714,7 @@ | |||
| 643 | msp2: msp@80117000 { | 714 | msp2: msp@80117000 { |
| 644 | compatible = "stericsson,ux500-msp-i2s"; | 715 | compatible = "stericsson,ux500-msp-i2s"; |
| 645 | reg = <0x80117000 0x1000>; | 716 | reg = <0x80117000 0x1000>; |
| 646 | interrupts = <0 98 0x4>; | 717 | interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; |
| 647 | v-ape-supply = <&db8500_vape_reg>; | 718 | v-ape-supply = <&db8500_vape_reg>; |
| 648 | status = "disabled"; | 719 | status = "disabled"; |
| 649 | }; | 720 | }; |
| @@ -651,7 +722,7 @@ | |||
| 651 | msp3: msp@80125000 { | 722 | msp3: msp@80125000 { |
| 652 | compatible = "stericsson,ux500-msp-i2s"; | 723 | compatible = "stericsson,ux500-msp-i2s"; |
| 653 | reg = <0x80125000 0x1000>; | 724 | reg = <0x80125000 0x1000>; |
| 654 | interrupts = <0 62 0x4>; | 725 | interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; |
| 655 | v-ape-supply = <&db8500_vape_reg>; | 726 | v-ape-supply = <&db8500_vape_reg>; |
| 656 | status = "disabled"; | 727 | status = "disabled"; |
| 657 | }; | 728 | }; |
| @@ -686,5 +757,20 @@ | |||
| 686 | 757 | ||
| 687 | status = "disabled"; | 758 | status = "disabled"; |
| 688 | }; | 759 | }; |
| 760 | |||
| 761 | cryp@a03cb000 { | ||
| 762 | compatible = "stericsson,ux500-cryp"; | ||
| 763 | reg = <0xa03cb000 0x1000>; | ||
| 764 | interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; | ||
| 765 | |||
| 766 | v-ape-supply = <&db8500_vape_reg>; | ||
| 767 | }; | ||
| 768 | |||
| 769 | hash@a03c2000 { | ||
| 770 | compatible = "stericsson,ux500-hash"; | ||
| 771 | reg = <0xa03c2000 0x1000>; | ||
| 772 | |||
| 773 | v-ape-supply = <&db8500_vape_reg>; | ||
| 774 | }; | ||
| 689 | }; | 775 | }; |
| 690 | }; | 776 | }; |
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 7e3065abd751..5cae2ab69762 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts | |||
| @@ -44,11 +44,60 @@ | |||
| 44 | gpio = <&gpio0 1 0>; | 44 | gpio = <&gpio0 1 0>; |
| 45 | }; | 45 | }; |
| 46 | }; | 46 | }; |
| 47 | |||
| 48 | clocks { | ||
| 49 | /* 25MHz reference crystal */ | ||
| 50 | ref25: oscillator { | ||
| 51 | compatible = "fixed-clock"; | ||
| 52 | #clock-cells = <0>; | ||
| 53 | clock-frequency = <25000000>; | ||
| 54 | }; | ||
| 55 | }; | ||
| 47 | }; | 56 | }; |
| 48 | 57 | ||
| 49 | &uart0 { status = "okay"; }; | 58 | &uart0 { status = "okay"; }; |
| 50 | &sata0 { status = "okay"; }; | 59 | &sata0 { status = "okay"; }; |
| 51 | &i2c0 { status = "okay"; }; | 60 | |
| 61 | &i2c0 { | ||
| 62 | status = "okay"; | ||
| 63 | clock-frequency = <100000>; | ||
| 64 | |||
| 65 | si5351: clock-generator { | ||
| 66 | compatible = "silabs,si5351a-msop"; | ||
| 67 | reg = <0x60>; | ||
| 68 | #address-cells = <1>; | ||
| 69 | #size-cells = <0>; | ||
| 70 | #clock-cells = <1>; | ||
| 71 | |||
| 72 | /* connect xtal input to 25MHz reference */ | ||
| 73 | clocks = <&ref25>; | ||
| 74 | |||
| 75 | /* connect xtal input as source of pll0 and pll1 */ | ||
| 76 | silabs,pll-source = <0 0>, <1 0>; | ||
| 77 | |||
| 78 | clkout0 { | ||
| 79 | reg = <0>; | ||
| 80 | silabs,drive-strength = <8>; | ||
| 81 | silabs,multisynth-source = <0>; | ||
| 82 | silabs,clock-source = <0>; | ||
| 83 | silabs,pll-master; | ||
| 84 | }; | ||
| 85 | |||
| 86 | clkout1 { | ||
| 87 | reg = <1>; | ||
| 88 | silabs,drive-strength = <8>; | ||
| 89 | silabs,multisynth-source = <1>; | ||
| 90 | silabs,clock-source = <0>; | ||
| 91 | silabs,pll-master; | ||
| 92 | }; | ||
| 93 | |||
| 94 | clkout2 { | ||
| 95 | reg = <2>; | ||
| 96 | silabs,multisynth-source = <1>; | ||
| 97 | silabs,clock-source = <0>; | ||
| 98 | }; | ||
| 99 | }; | ||
| 100 | }; | ||
| 52 | 101 | ||
| 53 | &sdio0 { | 102 | &sdio0 { |
| 54 | status = "okay"; | 103 | status = "okay"; |
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 359694c78918..bed40ee2e4f6 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi | |||
| @@ -160,6 +160,8 @@ | |||
| 160 | reg = <0x13400000 0x10000>; | 160 | reg = <0x13400000 0x10000>; |
| 161 | interrupts = <0 94 0>; | 161 | interrupts = <0 94 0>; |
| 162 | samsung,power-domain = <&pd_mfc>; | 162 | samsung,power-domain = <&pd_mfc>; |
| 163 | clocks = <&clock 170>, <&clock 273>; | ||
| 164 | clock-names = "sclk_mfc", "mfc"; | ||
| 163 | status = "disabled"; | 165 | status = "disabled"; |
| 164 | }; | 166 | }; |
| 165 | 167 | ||
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 524b90846df5..08609b8bdaf1 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts | |||
| @@ -41,6 +41,10 @@ | |||
| 41 | enable-active-high; | 41 | enable-active-high; |
| 42 | }; | 42 | }; |
| 43 | 43 | ||
| 44 | tmu@100C0000 { | ||
| 45 | status = "okay"; | ||
| 46 | }; | ||
| 47 | |||
| 44 | sdhci@12530000 { | 48 | sdhci@12530000 { |
| 45 | bus-width = <4>; | 49 | bus-width = <4>; |
| 46 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; | 50 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; |
| @@ -83,6 +87,150 @@ | |||
| 83 | status = "okay"; | 87 | status = "okay"; |
| 84 | }; | 88 | }; |
| 85 | 89 | ||
| 90 | i2c@13860000 { | ||
| 91 | status = "okay"; | ||
| 92 | samsung,i2c-sda-delay = <100>; | ||
| 93 | samsung,i2c-max-bus-freq = <20000>; | ||
| 94 | pinctrl-0 = <&i2c0_bus>; | ||
| 95 | pinctrl-names = "default"; | ||
| 96 | |||
| 97 | max8997_pmic@66 { | ||
| 98 | compatible = "maxim,max8997-pmic"; | ||
| 99 | reg = <0x66>; | ||
| 100 | interrupt-parent = <&gpx0>; | ||
| 101 | interrupts = <4 0>, <3 0>; | ||
| 102 | |||
| 103 | max8997,pmic-buck1-dvs-voltage = <1350000>; | ||
| 104 | max8997,pmic-buck2-dvs-voltage = <1100000>; | ||
| 105 | max8997,pmic-buck5-dvs-voltage = <1200000>; | ||
| 106 | |||
| 107 | regulators { | ||
| 108 | ldo1_reg: LDO1 { | ||
| 109 | regulator-name = "VDD_ABB_3.3V"; | ||
| 110 | regulator-min-microvolt = <3300000>; | ||
| 111 | regulator-max-microvolt = <3300000>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | ldo2_reg: LDO2 { | ||
| 115 | regulator-name = "VDD_ALIVE_1.1V"; | ||
| 116 | regulator-min-microvolt = <1100000>; | ||
| 117 | regulator-max-microvolt = <1100000>; | ||
| 118 | regulator-always-on; | ||
| 119 | }; | ||
| 120 | |||
| 121 | ldo3_reg: LDO3 { | ||
| 122 | regulator-name = "VMIPI_1.1V"; | ||
| 123 | regulator-min-microvolt = <1100000>; | ||
| 124 | regulator-max-microvolt = <1100000>; | ||
| 125 | }; | ||
| 126 | |||
| 127 | ldo4_reg: LDO4 { | ||
| 128 | regulator-name = "VDD_RTC_1.8V"; | ||
| 129 | regulator-min-microvolt = <1800000>; | ||
| 130 | regulator-max-microvolt = <1800000>; | ||
| 131 | regulator-always-on; | ||
| 132 | }; | ||
| 133 | |||
| 134 | ldo6_reg: LDO6 { | ||
| 135 | regulator-name = "VMIPI_1.8V"; | ||
| 136 | regulator-min-microvolt = <1800000>; | ||
| 137 | regulator-max-microvolt = <1800000>; | ||
| 138 | regulator-always-on; | ||
| 139 | }; | ||
| 140 | |||
| 141 | ldo7_reg: LDO7 { | ||
| 142 | regulator-name = "VDD_AUD_1.8V"; | ||
| 143 | regulator-min-microvolt = <1800000>; | ||
| 144 | regulator-max-microvolt = <1800000>; | ||
| 145 | }; | ||
| 146 | |||
| 147 | ldo8_reg: LDO8 { | ||
| 148 | regulator-name = "VADC_3.3V"; | ||
| 149 | regulator-min-microvolt = <3300000>; | ||
| 150 | regulator-max-microvolt = <3300000>; | ||
| 151 | }; | ||
| 152 | |||
| 153 | ldo9_reg: LDO9 { | ||
| 154 | regulator-name = "DVDD_SWB_2.8V"; | ||
| 155 | regulator-min-microvolt = <2800000>; | ||
| 156 | regulator-max-microvolt = <2800000>; | ||
| 157 | regulator-always-on; | ||
| 158 | }; | ||
| 159 | |||
| 160 | ldo10_reg: LDO10 { | ||
| 161 | regulator-name = "VDD_PLL_1.1V"; | ||
| 162 | regulator-min-microvolt = <1100000>; | ||
| 163 | regulator-max-microvolt = <1100000>; | ||
| 164 | regulator-always-on; | ||
| 165 | }; | ||
| 166 | |||
| 167 | ldo11_reg: LDO11 { | ||
| 168 | regulator-name = "VDD_AUD_3V"; | ||
| 169 | regulator-min-microvolt = <3000000>; | ||
| 170 | regulator-max-microvolt = <3000000>; | ||
| 171 | }; | ||
| 172 | |||
| 173 | ldo14_reg: LDO14 { | ||
| 174 | regulator-name = "AVDD18_SWB_1.8V"; | ||
| 175 | regulator-min-microvolt = <1800000>; | ||
| 176 | regulator-max-microvolt = <1800000>; | ||
| 177 | regulator-always-on; | ||
| 178 | }; | ||
| 179 | |||
| 180 | ldo17_reg: LDO17 { | ||
| 181 | regulator-name = "VDD_SWB_3.3V"; | ||
| 182 | regulator-min-microvolt = <3300000>; | ||
| 183 | regulator-max-microvolt = <3300000>; | ||
| 184 | regulator-always-on; | ||
| 185 | }; | ||
| 186 | |||
| 187 | ldo21_reg: LDO21 { | ||
| 188 | regulator-name = "VDD_MIF_1.2V"; | ||
| 189 | regulator-min-microvolt = <1200000>; | ||
| 190 | regulator-max-microvolt = <1200000>; | ||
| 191 | regulator-always-on; | ||
| 192 | }; | ||
| 193 | |||
| 194 | buck1_reg: BUCK1 { | ||
| 195 | regulator-name = "VDD_ARM_1.2V"; | ||
| 196 | regulator-min-microvolt = <950000>; | ||
| 197 | regulator-max-microvolt = <1350000>; | ||
| 198 | regulator-always-on; | ||
| 199 | regulator-boot-on; | ||
| 200 | }; | ||
| 201 | |||
| 202 | buck2_reg: BUCK2 { | ||
| 203 | regulator-name = "VDD_INT_1.1V"; | ||
| 204 | regulator-min-microvolt = <900000>; | ||
| 205 | regulator-max-microvolt = <1100000>; | ||
| 206 | regulator-always-on; | ||
| 207 | regulator-boot-on; | ||
| 208 | }; | ||
| 209 | |||
| 210 | buck3_reg: BUCK3 { | ||
| 211 | regulator-name = "VDD_G3D_1.1V"; | ||
| 212 | regulator-min-microvolt = <900000>; | ||
| 213 | regulator-max-microvolt = <1100000>; | ||
| 214 | }; | ||
| 215 | |||
| 216 | buck5_reg: BUCK5 { | ||
| 217 | regulator-name = "VDDQ_M1M2_1.2V"; | ||
| 218 | regulator-min-microvolt = <1200000>; | ||
| 219 | regulator-max-microvolt = <1200000>; | ||
| 220 | regulator-always-on; | ||
| 221 | }; | ||
| 222 | |||
| 223 | buck7_reg: BUCK7 { | ||
| 224 | regulator-name = "VDD_LCD_3.3V"; | ||
| 225 | regulator-min-microvolt = <3300000>; | ||
| 226 | regulator-max-microvolt = <3300000>; | ||
| 227 | regulator-boot-on; | ||
| 228 | regulator-always-on; | ||
| 229 | }; | ||
| 230 | }; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | |||
| 86 | gpio_keys { | 234 | gpio_keys { |
| 87 | compatible = "gpio-keys"; | 235 | compatible = "gpio-keys"; |
| 88 | #address-cells = <1>; | 236 | #address-cells = <1>; |
| @@ -143,4 +291,25 @@ | |||
| 143 | clock-frequency = <24000000>; | 291 | clock-frequency = <24000000>; |
| 144 | }; | 292 | }; |
| 145 | }; | 293 | }; |
| 294 | |||
| 295 | fimd@11c00000 { | ||
| 296 | pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>; | ||
| 297 | pinctrl-names = "default"; | ||
| 298 | status = "okay"; | ||
| 299 | }; | ||
| 300 | |||
| 301 | display-timings { | ||
| 302 | native-mode = <&timing0>; | ||
| 303 | timing0: timing { | ||
| 304 | clock-frequency = <50000>; | ||
| 305 | hactive = <1024>; | ||
| 306 | vactive = <600>; | ||
| 307 | hfront-porch = <64>; | ||
| 308 | hback-porch = <16>; | ||
| 309 | hsync-len = <48>; | ||
| 310 | vback-porch = <64>; | ||
| 311 | vfront-porch = <16>; | ||
| 312 | vsync-len = <3>; | ||
| 313 | }; | ||
| 314 | }; | ||
| 146 | }; | 315 | }; |
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 55a2efb763d1..553bceae8967 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi | |||
| @@ -330,6 +330,95 @@ | |||
| 330 | samsung,pin-pud = <3>; | 330 | samsung,pin-pud = <3>; |
| 331 | samsung,pin-drv = <0>; | 331 | samsung,pin-drv = <0>; |
| 332 | }; | 332 | }; |
| 333 | |||
| 334 | pwm0_out: pwm0-out { | ||
| 335 | samsung,pins = "gpd0-0"; | ||
| 336 | samsung,pin-function = <2>; | ||
| 337 | samsung,pin-pud = <0>; | ||
| 338 | samsung,pin-drv = <0>; | ||
| 339 | }; | ||
| 340 | |||
| 341 | pwm1_out: pwm1-out { | ||
| 342 | samsung,pins = "gpd0-1"; | ||
| 343 | samsung,pin-function = <2>; | ||
| 344 | samsung,pin-pud = <0>; | ||
| 345 | samsung,pin-drv = <0>; | ||
| 346 | }; | ||
| 347 | |||
| 348 | pwm2_out: pwm2-out { | ||
| 349 | samsung,pins = "gpd0-2"; | ||
| 350 | samsung,pin-function = <2>; | ||
| 351 | samsung,pin-pud = <0>; | ||
| 352 | samsung,pin-drv = <0>; | ||
| 353 | }; | ||
| 354 | |||
| 355 | pwm3_out: pwm3-out { | ||
| 356 | samsung,pins = "gpd0-3"; | ||
| 357 | samsung,pin-function = <2>; | ||
| 358 | samsung,pin-pud = <0>; | ||
| 359 | samsung,pin-drv = <0>; | ||
| 360 | }; | ||
| 361 | |||
| 362 | lcd_ctrl: lcd-ctrl { | ||
| 363 | samsung,pins = "gpd0-0", "gpd0-1"; | ||
| 364 | samsung,pin-function = <3>; | ||
| 365 | samsung,pin-pud = <0>; | ||
| 366 | samsung,pin-drv = <0>; | ||
| 367 | }; | ||
| 368 | |||
| 369 | lcd_sync: lcd-sync { | ||
| 370 | samsung,pins = "gpf0-0", "gpf0-1"; | ||
| 371 | samsung,pin-function = <2>; | ||
| 372 | samsung,pin-pud = <0>; | ||
| 373 | samsung,pin-drv = <0>; | ||
| 374 | }; | ||
| 375 | |||
| 376 | lcd_en: lcd-en { | ||
| 377 | samsung,pins = "gpe3-4"; | ||
| 378 | samsung,pin-function = <2>; | ||
| 379 | samsung,pin-pud = <0>; | ||
| 380 | samsung,pin-drv = <0>; | ||
| 381 | }; | ||
| 382 | |||
| 383 | lcd_clk: lcd-clk { | ||
| 384 | samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; | ||
| 385 | samsung,pin-function = <2>; | ||
| 386 | samsung,pin-pud = <0>; | ||
| 387 | samsung,pin-drv = <0>; | ||
| 388 | }; | ||
| 389 | |||
| 390 | lcd_data16: lcd-data-width16 { | ||
| 391 | samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", | ||
| 392 | "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", | ||
| 393 | "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", | ||
| 394 | "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; | ||
| 395 | samsung,pin-function = <2>; | ||
| 396 | samsung,pin-pud = <0>; | ||
| 397 | samsung,pin-drv = <0>; | ||
| 398 | }; | ||
| 399 | |||
| 400 | lcd_data18: lcd-data-width18 { | ||
| 401 | samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", | ||
| 402 | "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", | ||
| 403 | "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", | ||
| 404 | "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", | ||
| 405 | "gpf3-2", "gpf3-3"; | ||
| 406 | samsung,pin-function = <2>; | ||
| 407 | samsung,pin-pud = <0>; | ||
| 408 | samsung,pin-drv = <0>; | ||
| 409 | }; | ||
| 410 | |||
| 411 | lcd_data24: lcd-data-width24 { | ||
| 412 | samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", | ||
| 413 | "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", | ||
| 414 | "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", | ||
| 415 | "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", | ||
| 416 | "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", | ||
| 417 | "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; | ||
| 418 | samsung,pin-function = <2>; | ||
| 419 | samsung,pin-pud = <0>; | ||
| 420 | samsung,pin-drv = <0>; | ||
| 421 | }; | ||
| 333 | }; | 422 | }; |
| 334 | 423 | ||
| 335 | pinctrl@11000000 { | 424 | pinctrl@11000000 { |
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 54710de82908..d4f8067e89ba 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi | |||
| @@ -112,12 +112,17 @@ | |||
| 112 | interrupt-parent = <&combiner>; | 112 | interrupt-parent = <&combiner>; |
| 113 | reg = <0x100C0000 0x100>; | 113 | reg = <0x100C0000 0x100>; |
| 114 | interrupts = <2 4>; | 114 | interrupts = <2 4>; |
| 115 | clocks = <&clock 383>; | ||
| 116 | clock-names = "tmu_apbif"; | ||
| 117 | status = "disabled"; | ||
| 115 | }; | 118 | }; |
| 116 | 119 | ||
| 117 | g2d@12800000 { | 120 | g2d@12800000 { |
| 118 | compatible = "samsung,s5pv210-g2d"; | 121 | compatible = "samsung,s5pv210-g2d"; |
| 119 | reg = <0x12800000 0x1000>; | 122 | reg = <0x12800000 0x1000>; |
| 120 | interrupts = <0 89 0>; | 123 | interrupts = <0 89 0>; |
| 124 | clocks = <&clock 177>, <&clock 277>; | ||
| 125 | clock-names = "sclk_fimg2d", "fimg2d"; | ||
| 121 | status = "disabled"; | 126 | status = "disabled"; |
| 122 | }; | 127 | }; |
| 123 | }; | 128 | }; |
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 53bc8bf77984..867d9452619b 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts | |||
| @@ -43,6 +43,7 @@ | |||
| 43 | #size-cells = <0>; | 43 | #size-cells = <0>; |
| 44 | pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; | 44 | pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; |
| 45 | pinctrl-names = "default"; | 45 | pinctrl-names = "default"; |
| 46 | vmmc-supply = <&ldo20_reg &buck8_reg>; | ||
| 46 | status = "okay"; | 47 | status = "okay"; |
| 47 | 48 | ||
| 48 | num-slots = <1>; | 49 | num-slots = <1>; |
| @@ -78,6 +79,7 @@ | |||
| 78 | bus-width = <4>; | 79 | bus-width = <4>; |
| 79 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; | 80 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; |
| 80 | pinctrl-names = "default"; | 81 | pinctrl-names = "default"; |
| 82 | vmmc-supply = <&ldo4_reg &ldo21_reg>; | ||
| 81 | status = "okay"; | 83 | status = "okay"; |
| 82 | }; | 84 | }; |
| 83 | 85 | ||
| @@ -108,4 +110,199 @@ | |||
| 108 | clock-frequency = <24000000>; | 110 | clock-frequency = <24000000>; |
| 109 | }; | 111 | }; |
| 110 | }; | 112 | }; |
| 113 | |||
| 114 | i2c@13860000 { | ||
| 115 | pinctrl-0 = <&i2c0_bus>; | ||
| 116 | pinctrl-names = "default"; | ||
| 117 | status = "okay"; | ||
| 118 | |||
| 119 | max77686: pmic@09 { | ||
| 120 | compatible = "maxim,max77686"; | ||
| 121 | reg = <0x09>; | ||
| 122 | |||
| 123 | voltage-regulators { | ||
| 124 | ldo1_reg: LDO1 { | ||
| 125 | regulator-name = "VDD_ALIVE_1.0V"; | ||
| 126 | regulator-min-microvolt = <1000000>; | ||
| 127 | regulator-max-microvolt = <1000000>; | ||
| 128 | regulator-always-on; | ||
| 129 | }; | ||
| 130 | |||
| 131 | ldo2_reg: LDO2 { | ||
| 132 | regulator-name = "VDDQ_M1_2_1.8V"; | ||
| 133 | regulator-min-microvolt = <1800000>; | ||
| 134 | regulator-max-microvolt = <1800000>; | ||
| 135 | regulator-always-on; | ||
| 136 | }; | ||
| 137 | |||
| 138 | ldo3_reg: LDO3 { | ||
| 139 | regulator-name = "VDDQ_EXT_1.8V"; | ||
| 140 | regulator-min-microvolt = <1800000>; | ||
| 141 | regulator-max-microvolt = <1800000>; | ||
| 142 | regulator-always-on; | ||
| 143 | }; | ||
| 144 | |||
| 145 | ldo4_reg: LDO4 { | ||
| 146 | regulator-name = "VDDQ_MMC2_2.8V"; | ||
| 147 | regulator-min-microvolt = <2800000>; | ||
| 148 | regulator-max-microvolt = <2800000>; | ||
| 149 | regulator-always-on; | ||
| 150 | regulator-boot-on; | ||
| 151 | }; | ||
| 152 | |||
| 153 | ldo5_reg: LDO5 { | ||
| 154 | regulator-name = "VDDQ_MMC1_3_1.8V"; | ||
| 155 | regulator-min-microvolt = <1800000>; | ||
| 156 | regulator-max-microvolt = <1800000>; | ||
| 157 | regulator-always-on; | ||
| 158 | regulator-boot-on; | ||
| 159 | }; | ||
| 160 | |||
| 161 | ldo6_reg: LDO6 { | ||
| 162 | regulator-name = "VDD10_MPLL_1.0V"; | ||
| 163 | regulator-min-microvolt = <1000000>; | ||
| 164 | regulator-max-microvolt = <1000000>; | ||
| 165 | regulator-always-on; | ||
| 166 | }; | ||
| 167 | |||
| 168 | ldo7_reg: LDO7 { | ||
| 169 | regulator-name = "VDD10_XPLL_1.0V"; | ||
| 170 | regulator-min-microvolt = <1000000>; | ||
| 171 | regulator-max-microvolt = <1000000>; | ||
| 172 | regulator-always-on; | ||
| 173 | }; | ||
| 174 | |||
| 175 | ldo11_reg: LDO11 { | ||
| 176 | regulator-name = "VDD18_ABB1_1.8V"; | ||
| 177 | regulator-min-microvolt = <1800000>; | ||
| 178 | regulator-max-microvolt = <1800000>; | ||
| 179 | regulator-always-on; | ||
| 180 | }; | ||
| 181 | |||
| 182 | ldo12_reg: LDO12 { | ||
| 183 | regulator-name = "VDD33_USB_3.3V"; | ||
| 184 | regulator-min-microvolt = <3300000>; | ||
| 185 | regulator-max-microvolt = <3300000>; | ||
| 186 | regulator-always-on; | ||
| 187 | regulator-boot-on; | ||
| 188 | }; | ||
| 189 | |||
| 190 | ldo13_reg: LDO13 { | ||
| 191 | regulator-name = "VDDQ_C2C_W_1.8V"; | ||
| 192 | regulator-min-microvolt = <1800000>; | ||
| 193 | regulator-max-microvolt = <1800000>; | ||
| 194 | regulator-always-on; | ||
| 195 | regulator-boot-on; | ||
| 196 | }; | ||
| 197 | |||
| 198 | ldo14_reg: LDO14 { | ||
| 199 | regulator-name = "VDD18_ABB0_2_1.8V"; | ||
| 200 | regulator-min-microvolt = <1800000>; | ||
| 201 | regulator-max-microvolt = <1800000>; | ||
| 202 | regulator-always-on; | ||
| 203 | regulator-boot-on; | ||
| 204 | }; | ||
| 205 | |||
| 206 | ldo15_reg: LDO15 { | ||
| 207 | regulator-name = "VDD10_HSIC_1.0V"; | ||
| 208 | regulator-min-microvolt = <1000000>; | ||
| 209 | regulator-max-microvolt = <1000000>; | ||
| 210 | regulator-always-on; | ||
| 211 | regulator-boot-on; | ||
| 212 | }; | ||
| 213 | |||
| 214 | ldo16_reg: LDO16 { | ||
| 215 | regulator-name = "VDD18_HSIC_1.8V"; | ||
| 216 | regulator-min-microvolt = <1800000>; | ||
| 217 | regulator-max-microvolt = <1800000>; | ||
| 218 | regulator-always-on; | ||
| 219 | regulator-boot-on; | ||
| 220 | }; | ||
| 221 | |||
| 222 | ldo20_reg: LDO20 { | ||
| 223 | regulator-name = "LDO20_1.8V"; | ||
| 224 | regulator-min-microvolt = <1800000>; | ||
| 225 | regulator-max-microvolt = <1800000>; | ||
| 226 | regulator-boot-on; | ||
| 227 | }; | ||
| 228 | |||
| 229 | ldo21_reg: LDO21 { | ||
| 230 | regulator-name = "LDO21_3.3V"; | ||
| 231 | regulator-min-microvolt = <3300000>; | ||
| 232 | regulator-max-microvolt = <3300000>; | ||
| 233 | regulator-always-on; | ||
| 234 | regulator-boot-on; | ||
| 235 | }; | ||
| 236 | |||
| 237 | ldo25_reg: LDO25 { | ||
| 238 | regulator-name = "VDDQ_LCD_1.8V"; | ||
| 239 | regulator-min-microvolt = <1800000>; | ||
| 240 | regulator-max-microvolt = <1800000>; | ||
| 241 | regulator-always-on; | ||
| 242 | regulator-boot-on; | ||
| 243 | }; | ||
| 244 | |||
| 245 | buck1_reg: BUCK1 { | ||
| 246 | regulator-name = "vdd_mif"; | ||
| 247 | regulator-min-microvolt = <1000000>; | ||
| 248 | regulator-max-microvolt = <1000000>; | ||
| 249 | regulator-always-on; | ||
| 250 | regulator-boot-on; | ||
| 251 | }; | ||
| 252 | |||
| 253 | buck2_reg: BUCK2 { | ||
| 254 | regulator-name = "vdd_arm"; | ||
| 255 | regulator-min-microvolt = <900000>; | ||
| 256 | regulator-max-microvolt = <1300000>; | ||
| 257 | regulator-always-on; | ||
| 258 | regulator-boot-on; | ||
| 259 | }; | ||
| 260 | |||
| 261 | buck3_reg: BUCK3 { | ||
| 262 | regulator-name = "vdd_int"; | ||
| 263 | regulator-min-microvolt = <1000000>; | ||
| 264 | regulator-max-microvolt = <1000000>; | ||
| 265 | regulator-always-on; | ||
| 266 | regulator-boot-on; | ||
| 267 | }; | ||
| 268 | |||
| 269 | buck4_reg: BUCK4 { | ||
| 270 | regulator-name = "vdd_g3d"; | ||
| 271 | regulator-min-microvolt = <900000>; | ||
| 272 | regulator-max-microvolt = <1100000>; | ||
| 273 | regulator-microvolt-offset = <50000>; | ||
| 274 | }; | ||
| 275 | |||
| 276 | buck5_reg: BUCK5 { | ||
| 277 | regulator-name = "VDDQ_CKEM1_2_1.2V"; | ||
| 278 | regulator-min-microvolt = <1200000>; | ||
| 279 | regulator-max-microvolt = <1200000>; | ||
| 280 | regulator-always-on; | ||
| 281 | regulator-boot-on; | ||
| 282 | }; | ||
| 283 | |||
| 284 | buck6_reg: BUCK6 { | ||
| 285 | regulator-name = "BUCK6_1.35V"; | ||
| 286 | regulator-min-microvolt = <1350000>; | ||
| 287 | regulator-max-microvolt = <1350000>; | ||
| 288 | regulator-always-on; | ||
| 289 | regulator-boot-on; | ||
| 290 | }; | ||
| 291 | |||
| 292 | buck7_reg: BUCK7 { | ||
| 293 | regulator-name = "BUCK7_2.0V"; | ||
| 294 | regulator-min-microvolt = <2000000>; | ||
| 295 | regulator-max-microvolt = <2000000>; | ||
| 296 | regulator-always-on; | ||
| 297 | }; | ||
| 298 | |||
| 299 | buck8_reg: BUCK8 { | ||
| 300 | regulator-name = "BUCK8_2.8V"; | ||
| 301 | regulator-min-microvolt = <2800000>; | ||
| 302 | regulator-max-microvolt = <2800000>; | ||
| 303 | regulator-always-on; | ||
| 304 | }; | ||
| 305 | }; | ||
| 306 | }; | ||
| 307 | }; | ||
| 111 | }; | 308 | }; |
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 1c21bad32ca9..ca73c42f77e1 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts | |||
| @@ -36,6 +36,72 @@ | |||
| 36 | enable-active-high; | 36 | enable-active-high; |
| 37 | }; | 37 | }; |
| 38 | 38 | ||
| 39 | pinctrl@11000000 { | ||
| 40 | keypad_rows: keypad-rows { | ||
| 41 | samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; | ||
| 42 | samsung,pin-function = <3>; | ||
| 43 | samsung,pin-pud = <3>; | ||
| 44 | samsung,pin-drv = <0>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | keypad_cols: keypad-cols { | ||
| 48 | samsung,pins = "gpx1-0", "gpx1-1"; | ||
| 49 | samsung,pin-function = <3>; | ||
| 50 | samsung,pin-pud = <0>; | ||
| 51 | samsung,pin-drv = <0>; | ||
| 52 | }; | ||
| 53 | }; | ||
| 54 | |||
| 55 | keypad@100A0000 { | ||
| 56 | samsung,keypad-num-rows = <3>; | ||
| 57 | samsung,keypad-num-columns = <2>; | ||
| 58 | linux,keypad-no-autorepeat; | ||
| 59 | linux,keypad-wakeup; | ||
| 60 | pinctrl-0 = <&keypad_rows &keypad_cols>; | ||
| 61 | pinctrl-names = "default"; | ||
| 62 | status = "okay"; | ||
| 63 | |||
| 64 | key_home { | ||
| 65 | keypad,row = <0>; | ||
| 66 | keypad,column = <0>; | ||
| 67 | linux,code = <102>; | ||
| 68 | }; | ||
| 69 | |||
| 70 | key_down { | ||
| 71 | keypad,row = <0>; | ||
| 72 | keypad,column = <1>; | ||
| 73 | linux,code = <108>; | ||
| 74 | }; | ||
| 75 | |||
| 76 | key_up { | ||
| 77 | keypad,row = <1>; | ||
| 78 | keypad,column = <0>; | ||
| 79 | linux,code = <103>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | key_menu { | ||
| 83 | keypad,row = <1>; | ||
| 84 | keypad,column = <1>; | ||
| 85 | linux,code = <139>; | ||
| 86 | }; | ||
| 87 | |||
| 88 | key_back { | ||
| 89 | keypad,row = <2>; | ||
| 90 | keypad,column = <0>; | ||
| 91 | linux,code = <158>; | ||
| 92 | }; | ||
| 93 | |||
| 94 | key_enter { | ||
| 95 | keypad,row = <2>; | ||
| 96 | keypad,column = <1>; | ||
| 97 | linux,code = <28>; | ||
| 98 | }; | ||
| 99 | }; | ||
| 100 | |||
| 101 | g2d@10800000 { | ||
| 102 | status = "okay"; | ||
| 103 | }; | ||
| 104 | |||
| 39 | sdhci@12530000 { | 105 | sdhci@12530000 { |
| 40 | bus-width = <4>; | 106 | bus-width = <4>; |
| 41 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; | 107 | pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; |
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index dd564310d4a5..a8ba195c41ac 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts | |||
| @@ -31,8 +31,91 @@ | |||
| 31 | status = "okay"; | 31 | status = "okay"; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | g2d@10800000 { | 34 | pinctrl@11000000 { |
| 35 | keypad_rows: keypad-rows { | ||
| 36 | samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; | ||
| 37 | samsung,pin-function = <3>; | ||
| 38 | samsung,pin-pud = <3>; | ||
| 39 | samsung,pin-drv = <0>; | ||
| 40 | }; | ||
| 41 | |||
| 42 | keypad_cols: keypad-cols { | ||
| 43 | samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", | ||
| 44 | "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; | ||
| 45 | samsung,pin-function = <3>; | ||
| 46 | samsung,pin-pud = <0>; | ||
| 47 | samsung,pin-drv = <0>; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | keypad@100A0000 { | ||
| 52 | samsung,keypad-num-rows = <3>; | ||
| 53 | samsung,keypad-num-columns = <8>; | ||
| 54 | linux,keypad-no-autorepeat; | ||
| 55 | linux,keypad-wakeup; | ||
| 56 | pinctrl-0 = <&keypad_rows &keypad_cols>; | ||
| 57 | pinctrl-names = "default"; | ||
| 35 | status = "okay"; | 58 | status = "okay"; |
| 59 | |||
| 60 | key_1 { | ||
| 61 | keypad,row = <1>; | ||
| 62 | keypad,column = <3>; | ||
| 63 | linux,code = <2>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | key_2 { | ||
| 67 | keypad,row = <1>; | ||
| 68 | keypad,column = <4>; | ||
| 69 | linux,code = <3>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | key_3 { | ||
| 73 | keypad,row = <1>; | ||
| 74 | keypad,column = <5>; | ||
| 75 | linux,code = <4>; | ||
| 76 | }; | ||
| 77 | |||
| 78 | key_4 { | ||
| 79 | keypad,row = <1>; | ||
| 80 | keypad,column = <6>; | ||
| 81 | linux,code = <5>; | ||
| 82 | }; | ||
| 83 | |||
| 84 | key_5 { | ||
| 85 | keypad,row = <1>; | ||
| 86 | keypad,column = <7>; | ||
| 87 | linux,code = <6>; | ||
| 88 | }; | ||
| 89 | |||
| 90 | key_A { | ||
| 91 | keypad,row = <2>; | ||
| 92 | keypad,column = <6>; | ||
| 93 | linux,code = <30>; | ||
| 94 | }; | ||
| 95 | |||
| 96 | key_B { | ||
| 97 | keypad,row = <2>; | ||
| 98 | keypad,column = <7>; | ||
| 99 | linux,code = <48>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | key_C { | ||
| 103 | keypad,row = <0>; | ||
| 104 | keypad,column = <5>; | ||
| 105 | linux,code = <46>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | key_D { | ||
| 109 | keypad,row = <2>; | ||
| 110 | keypad,column = <5>; | ||
| 111 | linux,code = <32>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | key_E { | ||
| 115 | keypad,row = <0>; | ||
| 116 | keypad,column = <7>; | ||
| 117 | linux,code = <18>; | ||
| 118 | }; | ||
| 36 | }; | 119 | }; |
| 37 | 120 | ||
| 38 | sdhci@12530000 { | 121 | sdhci@12530000 { |
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 099cec79e2ae..704290f7c5c0 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | |||
| @@ -778,62 +778,6 @@ | |||
| 778 | samsung,pin-drv = <3>; | 778 | samsung,pin-drv = <3>; |
| 779 | }; | 779 | }; |
| 780 | 780 | ||
| 781 | keypad_col0: keypad-col0 { | ||
| 782 | samsung,pins = "gpl2-0"; | ||
| 783 | samsung,pin-function = <3>; | ||
| 784 | samsung,pin-pud = <0>; | ||
| 785 | samsung,pin-drv = <0>; | ||
| 786 | }; | ||
| 787 | |||
| 788 | keypad_col1: keypad-col1 { | ||
| 789 | samsung,pins = "gpl2-1"; | ||
| 790 | samsung,pin-function = <3>; | ||
| 791 | samsung,pin-pud = <0>; | ||
| 792 | samsung,pin-drv = <0>; | ||
| 793 | }; | ||
| 794 | |||
| 795 | keypad_col2: keypad-col2 { | ||
| 796 | samsung,pins = "gpl2-2"; | ||
| 797 | samsung,pin-function = <3>; | ||
| 798 | samsung,pin-pud = <0>; | ||
| 799 | samsung,pin-drv = <0>; | ||
| 800 | }; | ||
| 801 | |||
| 802 | keypad_col3: keypad-col3 { | ||
| 803 | samsung,pins = "gpl2-3"; | ||
| 804 | samsung,pin-function = <3>; | ||
| 805 | samsung,pin-pud = <0>; | ||
| 806 | samsung,pin-drv = <0>; | ||
| 807 | }; | ||
| 808 | |||
| 809 | keypad_col4: keypad-col4 { | ||
| 810 | samsung,pins = "gpl2-4"; | ||
| 811 | samsung,pin-function = <3>; | ||
| 812 | samsung,pin-pud = <0>; | ||
| 813 | samsung,pin-drv = <0>; | ||
| 814 | }; | ||
| 815 | |||
| 816 | keypad_col5: keypad-col5 { | ||
| 817 | samsung,pins = "gpl2-5"; | ||
| 818 | samsung,pin-function = <3>; | ||
| 819 | samsung,pin-pud = <0>; | ||
| 820 | samsung,pin-drv = <0>; | ||
| 821 | }; | ||
| 822 | |||
| 823 | keypad_col6: keypad-col6 { | ||
| 824 | samsung,pins = "gpl2-6"; | ||
| 825 | samsung,pin-function = <3>; | ||
| 826 | samsung,pin-pud = <0>; | ||
| 827 | samsung,pin-drv = <0>; | ||
| 828 | }; | ||
| 829 | |||
| 830 | keypad_col7: keypad-col7 { | ||
| 831 | samsung,pins = "gpl2-7"; | ||
| 832 | samsung,pin-function = <3>; | ||
| 833 | samsung,pin-pud = <0>; | ||
| 834 | samsung,pin-drv = <0>; | ||
| 835 | }; | ||
| 836 | |||
| 837 | cam_port_b: cam-port-b { | 781 | cam_port_b: cam-port-b { |
| 838 | samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", | 782 | samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", |
| 839 | "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", | 783 | "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", |
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index e3380a7a285c..35cb2099d55e 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi | |||
| @@ -28,14 +28,6 @@ | |||
| 28 | pinctrl3 = &pinctrl_3; | 28 | pinctrl3 = &pinctrl_3; |
| 29 | }; | 29 | }; |
| 30 | 30 | ||
| 31 | combiner:interrupt-controller@10440000 { | ||
| 32 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | ||
| 33 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | ||
| 34 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | ||
| 35 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | ||
| 36 | <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>; | ||
| 37 | }; | ||
| 38 | |||
| 39 | clock: clock-controller@0x10030000 { | 31 | clock: clock-controller@0x10030000 { |
| 40 | compatible = "samsung,exynos4412-clock"; | 32 | compatible = "samsung,exynos4412-clock"; |
| 41 | reg = <0x10030000 0x20000>; | 33 | reg = <0x10030000 0x20000>; |
| @@ -77,6 +69,8 @@ | |||
| 77 | compatible = "samsung,exynos4212-g2d"; | 69 | compatible = "samsung,exynos4212-g2d"; |
| 78 | reg = <0x10800000 0x1000>; | 70 | reg = <0x10800000 0x1000>; |
| 79 | interrupts = <0 89 0>; | 71 | interrupts = <0 89 0>; |
| 72 | clocks = <&clock 177>, <&clock 277>; | ||
| 73 | clock-names = "sclk_fimg2d", "fimg2d"; | ||
| 80 | status = "disabled"; | 74 | status = "disabled"; |
| 81 | }; | 75 | }; |
| 82 | }; | 76 | }; |
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 02cfc76d002f..c6db281a3430 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts | |||
| @@ -449,4 +449,35 @@ | |||
| 449 | clock-frequency = <24000000>; | 449 | clock-frequency = <24000000>; |
| 450 | }; | 450 | }; |
| 451 | }; | 451 | }; |
| 452 | |||
| 453 | dp-controller { | ||
| 454 | samsung,color-space = <0>; | ||
| 455 | samsung,dynamic-range = <0>; | ||
| 456 | samsung,ycbcr-coeff = <0>; | ||
| 457 | samsung,color-depth = <1>; | ||
| 458 | samsung,link-rate = <0x0a>; | ||
| 459 | samsung,lane-count = <4>; | ||
| 460 | }; | ||
| 461 | |||
| 462 | fimd: fimd@14400000 { | ||
| 463 | display-timings { | ||
| 464 | native-mode = <&timing0>; | ||
| 465 | timing0: timing@0 { | ||
| 466 | /* 2560x1600 DP panel */ | ||
| 467 | clock-frequency = <50000>; | ||
| 468 | hactive = <2560>; | ||
| 469 | vactive = <1600>; | ||
| 470 | hfront-porch = <48>; | ||
| 471 | hback-porch = <80>; | ||
| 472 | hsync-len = <32>; | ||
| 473 | vback-porch = <16>; | ||
| 474 | vfront-porch = <8>; | ||
| 475 | vsync-len = <6>; | ||
| 476 | }; | ||
| 477 | }; | ||
| 478 | }; | ||
| 479 | |||
| 480 | rtc { | ||
| 481 | status = "okay"; | ||
| 482 | }; | ||
| 452 | }; | 483 | }; |
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index ded558bb0f3b..724a22f9b1c8 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi | |||
| @@ -553,6 +553,13 @@ | |||
| 553 | samsung,pin-pud = <0>; | 553 | samsung,pin-pud = <0>; |
| 554 | samaung,pin-drv = <0>; | 554 | samaung,pin-drv = <0>; |
| 555 | }; | 555 | }; |
| 556 | |||
| 557 | dp_hpd: dp_hpd { | ||
| 558 | samsung,pins = "gpx0-7"; | ||
| 559 | samsung,pin-function = <3>; | ||
| 560 | samsung,pin-pud = <0>; | ||
| 561 | samaung,pin-drv = <0>; | ||
| 562 | }; | ||
| 556 | }; | 563 | }; |
| 557 | 564 | ||
| 558 | pinctrl@13400000 { | 565 | pinctrl@13400000 { |
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 3e0c792e2767..1e21200b6d85 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts | |||
| @@ -37,6 +37,30 @@ | |||
| 37 | }; | 37 | }; |
| 38 | }; | 38 | }; |
| 39 | 39 | ||
| 40 | vdd:fixed-regulator@0 { | ||
| 41 | compatible = "regulator-fixed"; | ||
| 42 | regulator-name = "vdd-supply"; | ||
| 43 | regulator-min-microvolt = <1800000>; | ||
| 44 | regulator-max-microvolt = <1800000>; | ||
| 45 | regulator-always-on; | ||
| 46 | }; | ||
| 47 | |||
| 48 | dbvdd:fixed-regulator@1 { | ||
| 49 | compatible = "regulator-fixed"; | ||
| 50 | regulator-name = "dbvdd-supply"; | ||
| 51 | regulator-min-microvolt = <3300000>; | ||
| 52 | regulator-max-microvolt = <3300000>; | ||
| 53 | regulator-always-on; | ||
| 54 | }; | ||
| 55 | |||
| 56 | spkvdd:fixed-regulator@2 { | ||
| 57 | compatible = "regulator-fixed"; | ||
| 58 | regulator-name = "spkvdd-supply"; | ||
| 59 | regulator-min-microvolt = <5000000>; | ||
| 60 | regulator-max-microvolt = <5000000>; | ||
| 61 | regulator-always-on; | ||
| 62 | }; | ||
| 63 | |||
| 40 | i2c@12C70000 { | 64 | i2c@12C70000 { |
| 41 | samsung,i2c-sda-delay = <100>; | 65 | samsung,i2c-sda-delay = <100>; |
| 42 | samsung,i2c-max-bus-freq = <20000>; | 66 | samsung,i2c-max-bus-freq = <20000>; |
| @@ -47,8 +71,17 @@ | |||
| 47 | }; | 71 | }; |
| 48 | 72 | ||
| 49 | wm8994: wm8994@1a { | 73 | wm8994: wm8994@1a { |
| 50 | compatible = "wlf,wm8994"; | 74 | compatible = "wlf,wm8994"; |
| 51 | reg = <0x1a>; | 75 | reg = <0x1a>; |
| 76 | |||
| 77 | gpio-controller; | ||
| 78 | #gpio-cells = <2>; | ||
| 79 | |||
| 80 | AVDD2-supply = <&vdd>; | ||
| 81 | CPVDD-supply = <&vdd>; | ||
| 82 | DBVDD-supply = <&dbvdd>; | ||
| 83 | SPKVDD1-supply = <&spkvdd>; | ||
| 84 | SPKVDD2-supply = <&spkvdd>; | ||
| 52 | }; | 85 | }; |
| 53 | }; | 86 | }; |
| 54 | 87 | ||
| @@ -224,6 +257,9 @@ | |||
| 224 | samsung,color-depth = <1>; | 257 | samsung,color-depth = <1>; |
| 225 | samsung,link-rate = <0x0a>; | 258 | samsung,link-rate = <0x0a>; |
| 226 | samsung,lane-count = <4>; | 259 | samsung,lane-count = <4>; |
| 260 | |||
| 261 | pinctrl-names = "default"; | ||
| 262 | pinctrl-0 = <&dp_hpd>; | ||
| 227 | }; | 263 | }; |
| 228 | 264 | ||
| 229 | display-timings { | 265 | display-timings { |
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index d449feb7e143..05244f150dd9 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts | |||
| @@ -171,6 +171,10 @@ | |||
| 171 | }; | 171 | }; |
| 172 | }; | 172 | }; |
| 173 | 173 | ||
| 174 | rtc { | ||
| 175 | status = "okay"; | ||
| 176 | }; | ||
| 177 | |||
| 174 | /* | 178 | /* |
| 175 | * On Snow we've got SIP WiFi and so can keep drive strengths low to | 179 | * On Snow we've got SIP WiFi and so can keep drive strengths low to |
| 176 | * reduce EMI. | 180 | * reduce EMI. |
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index fc9fb3d526e2..54a35e64c781 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi | |||
| @@ -479,6 +479,36 @@ | |||
| 479 | pinctrl-0 = <&i2s2_bus>; | 479 | pinctrl-0 = <&i2s2_bus>; |
| 480 | }; | 480 | }; |
| 481 | 481 | ||
| 482 | usb@12000000 { | ||
| 483 | compatible = "samsung,exynos5250-dwusb3"; | ||
| 484 | clocks = <&clock 286>; | ||
| 485 | clock-names = "usbdrd30"; | ||
| 486 | #address-cells = <1>; | ||
| 487 | #size-cells = <1>; | ||
| 488 | ranges; | ||
| 489 | |||
| 490 | dwc3 { | ||
| 491 | compatible = "synopsys,dwc3"; | ||
| 492 | reg = <0x12000000 0x10000>; | ||
| 493 | interrupts = <0 72 0>; | ||
| 494 | usb-phy = <&usb2_phy &usb3_phy>; | ||
| 495 | }; | ||
| 496 | }; | ||
| 497 | |||
| 498 | usb3_phy: usbphy@12100000 { | ||
| 499 | compatible = "samsung,exynos5250-usb3phy"; | ||
| 500 | reg = <0x12100000 0x100>; | ||
| 501 | clocks = <&clock 1>, <&clock 286>; | ||
| 502 | clock-names = "ext_xtal", "usbdrd30"; | ||
| 503 | #address-cells = <1>; | ||
| 504 | #size-cells = <1>; | ||
| 505 | ranges; | ||
| 506 | |||
| 507 | usbphy-sys { | ||
| 508 | reg = <0x10040704 0x8>; | ||
| 509 | }; | ||
| 510 | }; | ||
| 511 | |||
| 482 | usb@12110000 { | 512 | usb@12110000 { |
| 483 | compatible = "samsung,exynos4210-ehci"; | 513 | compatible = "samsung,exynos4210-ehci"; |
| 484 | reg = <0x12110000 0x100>; | 514 | reg = <0x12110000 0x100>; |
| @@ -497,7 +527,7 @@ | |||
| 497 | clock-names = "usbhost"; | 527 | clock-names = "usbhost"; |
| 498 | }; | 528 | }; |
| 499 | 529 | ||
| 500 | usbphy@12130000 { | 530 | usb2_phy: usbphy@12130000 { |
| 501 | compatible = "samsung,exynos5250-usb2phy"; | 531 | compatible = "samsung,exynos5250-usb2phy"; |
| 502 | reg = <0x12130000 0x100>; | 532 | reg = <0x12130000 0x100>; |
| 503 | clocks = <&clock 1>, <&clock 285>; | 533 | clocks = <&clock 1>, <&clock 285>; |
| @@ -621,6 +651,8 @@ | |||
| 621 | reg = <0x145b0000 0x1000>; | 651 | reg = <0x145b0000 0x1000>; |
| 622 | interrupts = <10 3>; | 652 | interrupts = <10 3>; |
| 623 | interrupt-parent = <&combiner>; | 653 | interrupt-parent = <&combiner>; |
| 654 | clocks = <&clock 342>; | ||
| 655 | clock-names = "dp"; | ||
| 624 | #address-cells = <1>; | 656 | #address-cells = <1>; |
| 625 | #size-cells = <0>; | 657 | #size-cells = <0>; |
| 626 | 658 | ||
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts index ef747b52b674..f722a0263ac8 100644 --- a/arch/arm/boot/dts/exynos5440-sd5v1.dts +++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | compatible = "samsung,sd5v1", "samsung,exynos5440"; | 17 | compatible = "samsung,sd5v1", "samsung,exynos5440"; |
| 18 | 18 | ||
| 19 | chosen { | 19 | chosen { |
| 20 | bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200"; | 20 | bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | fixed-rate-clocks { | 23 | fixed-rate-clocks { |
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index f96de398c965..ba88cfd2486f 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts | |||
| @@ -17,11 +17,46 @@ | |||
| 17 | compatible = "samsung,ssdk5440", "samsung,exynos5440"; | 17 | compatible = "samsung,ssdk5440", "samsung,exynos5440"; |
| 18 | 18 | ||
| 19 | chosen { | 19 | chosen { |
| 20 | bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200"; | 20 | bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; |
| 21 | }; | 21 | }; |
| 22 | 22 | ||
| 23 | spi { | 23 | spi_0: spi@D0000 { |
| 24 | status = "disabled"; | 24 | |
| 25 | flash: w25q128@0 { | ||
| 26 | #address-cells = <1>; | ||
| 27 | #size-cells = <1>; | ||
| 28 | compatible = "winbond,w25q128"; | ||
| 29 | spi-max-frequency = <15625000>; | ||
| 30 | reg = <0>; | ||
| 31 | controller-data { | ||
| 32 | samsung,spi-feedback-delay = <0>; | ||
| 33 | }; | ||
| 34 | |||
| 35 | partition@00000 { | ||
| 36 | label = "BootLoader"; | ||
| 37 | reg = <0x60000 0x80000>; | ||
| 38 | read-only; | ||
| 39 | }; | ||
| 40 | |||
| 41 | partition@e0000 { | ||
| 42 | label = "Recovery-Kernel"; | ||
| 43 | reg = <0xe0000 0x300000>; | ||
| 44 | read-only; | ||
| 45 | }; | ||
| 46 | |||
| 47 | partition@3e0000 { | ||
| 48 | label = "CRAM-FS"; | ||
| 49 | reg = <0x3e0000 0x700000>; | ||
| 50 | read-only; | ||
| 51 | }; | ||
| 52 | |||
| 53 | partition@ae0000 { | ||
| 54 | label = "User-Data"; | ||
| 55 | reg = <0xae0000 0x520000>; | ||
| 56 | }; | ||
| 57 | |||
| 58 | }; | ||
| 59 | |||
| 25 | }; | 60 | }; |
| 26 | 61 | ||
| 27 | fixed-rate-clocks { | 62 | fixed-rate-clocks { |
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index b7ffc4dfe219..bfcb907b7e33 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi | |||
| @@ -16,6 +16,10 @@ | |||
| 16 | 16 | ||
| 17 | interrupt-parent = <&gic>; | 17 | interrupt-parent = <&gic>; |
| 18 | 18 | ||
| 19 | aliases { | ||
| 20 | spi0 = &spi_0; | ||
| 21 | }; | ||
| 22 | |||
| 19 | clock: clock-controller@0x160000 { | 23 | clock: clock-controller@0x160000 { |
| 20 | compatible = "samsung,exynos5440-clock"; | 24 | compatible = "samsung,exynos5440-clock"; |
| 21 | reg = <0x160000 0x1000>; | 25 | reg = <0x160000 0x1000>; |
| @@ -38,18 +42,22 @@ | |||
| 38 | #size-cells = <0>; | 42 | #size-cells = <0>; |
| 39 | 43 | ||
| 40 | cpu@0 { | 44 | cpu@0 { |
| 45 | device_type = "cpu"; | ||
| 41 | compatible = "arm,cortex-a15"; | 46 | compatible = "arm,cortex-a15"; |
| 42 | reg = <0>; | 47 | reg = <0>; |
| 43 | }; | 48 | }; |
| 44 | cpu@1 { | 49 | cpu@1 { |
| 50 | device_type = "cpu"; | ||
| 45 | compatible = "arm,cortex-a15"; | 51 | compatible = "arm,cortex-a15"; |
| 46 | reg = <1>; | 52 | reg = <1>; |
| 47 | }; | 53 | }; |
| 48 | cpu@2 { | 54 | cpu@2 { |
| 55 | device_type = "cpu"; | ||
| 49 | compatible = "arm,cortex-a15"; | 56 | compatible = "arm,cortex-a15"; |
| 50 | reg = <2>; | 57 | reg = <2>; |
| 51 | }; | 58 | }; |
| 52 | cpu@3 { | 59 | cpu@3 { |
| 60 | device_type = "cpu"; | ||
| 53 | compatible = "arm,cortex-a15"; | 61 | compatible = "arm,cortex-a15"; |
| 54 | reg = <3>; | 62 | reg = <3>; |
| 55 | }; | 63 | }; |
| @@ -79,8 +87,13 @@ | |||
| 79 | interrupts = <0 57 0>; | 87 | interrupts = <0 57 0>; |
| 80 | operating-points = < | 88 | operating-points = < |
| 81 | /* KHz uV */ | 89 | /* KHz uV */ |
| 90 | 1500000 1100000 | ||
| 91 | 1400000 1075000 | ||
| 92 | 1300000 1050000 | ||
| 82 | 1200000 1025000 | 93 | 1200000 1025000 |
| 94 | 1100000 1000000 | ||
| 83 | 1000000 975000 | 95 | 1000000 975000 |
| 96 | 900000 950000 | ||
| 84 | 800000 925000 | 97 | 800000 925000 |
| 85 | >; | 98 | >; |
| 86 | }; | 99 | }; |
| @@ -101,14 +114,14 @@ | |||
| 101 | clock-names = "uart", "clk_uart_baud0"; | 114 | clock-names = "uart", "clk_uart_baud0"; |
| 102 | }; | 115 | }; |
| 103 | 116 | ||
| 104 | spi { | 117 | spi_0: spi@D0000 { |
| 105 | compatible = "samsung,exynos4210-spi"; | 118 | compatible = "samsung,exynos5440-spi"; |
| 106 | reg = <0xD0000 0x1000>; | 119 | reg = <0xD0000 0x100>; |
| 107 | interrupts = <0 4 0>; | 120 | interrupts = <0 4 0>; |
| 108 | tx-dma-channel = <&pdma0 5>; /* preliminary */ | ||
| 109 | rx-dma-channel = <&pdma0 4>; /* preliminary */ | ||
| 110 | #address-cells = <1>; | 121 | #address-cells = <1>; |
| 111 | #size-cells = <0>; | 122 | #size-cells = <0>; |
| 123 | samsung,spi-src-clk = <0>; | ||
| 124 | num-cs = <1>; | ||
| 112 | clocks = <&clock 21>, <&clock 16>; | 125 | clocks = <&clock 21>, <&clock 16>; |
| 113 | clock-names = "spi", "spi_busclk0"; | 126 | clock-names = "spi", "spi_busclk0"; |
| 114 | }; | 127 | }; |
| @@ -184,28 +197,6 @@ | |||
| 184 | compatible = "arm,amba-bus"; | 197 | compatible = "arm,amba-bus"; |
| 185 | interrupt-parent = <&gic>; | 198 | interrupt-parent = <&gic>; |
| 186 | ranges; | 199 | ranges; |
| 187 | |||
| 188 | pdma0: pdma@00121000 { | ||
| 189 | compatible = "arm,pl330", "arm,primecell"; | ||
| 190 | reg = <0x121000 0x1000>; | ||
| 191 | interrupts = <0 46 0>; | ||
| 192 | clocks = <&clock 8>; | ||
| 193 | clock-names = "apb_pclk"; | ||
| 194 | #dma-cells = <1>; | ||
| 195 | #dma-channels = <8>; | ||
| 196 | #dma-requests = <32>; | ||
| 197 | }; | ||
| 198 | |||
| 199 | pdma1: pdma@00120000 { | ||
| 200 | compatible = "arm,pl330", "arm,primecell"; | ||
| 201 | reg = <0x120000 0x1000>; | ||
| 202 | interrupts = <0 47 0>; | ||
| 203 | clocks = <&clock 8>; | ||
| 204 | clock-names = "apb_pclk"; | ||
| 205 | #dma-cells = <1>; | ||
| 206 | #dma-channels = <8>; | ||
| 207 | #dma-requests = <32>; | ||
| 208 | }; | ||
| 209 | }; | 200 | }; |
| 210 | 201 | ||
| 211 | rtc { | 202 | rtc { |
| @@ -214,7 +205,30 @@ | |||
| 214 | interrupts = <0 17 0>, <0 16 0>; | 205 | interrupts = <0 17 0>, <0 16 0>; |
| 215 | clocks = <&clock 21>; | 206 | clocks = <&clock 21>; |
| 216 | clock-names = "rtc"; | 207 | clock-names = "rtc"; |
| 217 | status = "disabled"; | 208 | }; |
| 209 | |||
| 210 | sata@210000 { | ||
| 211 | compatible = "snps,exynos5440-ahci"; | ||
| 212 | reg = <0x210000 0x10000>; | ||
| 213 | interrupts = <0 30 0>; | ||
| 214 | clocks = <&clock 23>; | ||
| 215 | clock-names = "sata"; | ||
| 216 | }; | ||
| 217 | |||
| 218 | ohci@220000 { | ||
| 219 | compatible = "samsung,exynos5440-ohci"; | ||
| 220 | reg = <0x220000 0x1000>; | ||
| 221 | interrupts = <0 29 0>; | ||
| 222 | clocks = <&clock 24>; | ||
| 223 | clock-names = "usbhost"; | ||
| 224 | }; | ||
| 225 | |||
| 226 | ehci@221000 { | ||
| 227 | compatible = "samsung,exynos5440-ehci"; | ||
| 228 | reg = <0x221000 0x1000>; | ||
| 229 | interrupts = <0 29 0>; | ||
| 230 | clocks = <&clock 24>; | ||
| 231 | clock-names = "usbhost"; | ||
| 218 | }; | 232 | }; |
| 219 | 233 | ||
| 220 | pcie@290000 { | 234 | pcie@290000 { |
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi index c0bc426952ea..9db41b9d8358 100644 --- a/arch/arm/boot/dts/href.dtsi +++ b/arch/arm/boot/dts/href.dtsi | |||
| @@ -9,7 +9,8 @@ | |||
| 9 | * http://www.gnu.org/copyleft/gpl.html | 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /include/ "dbx5x0.dtsi" | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
| 13 | #include "dbx5x0.dtsi" | ||
| 13 | 14 | ||
| 14 | / { | 15 | / { |
| 15 | memory { | 16 | memory { |
| @@ -27,7 +28,7 @@ | |||
| 27 | }; | 28 | }; |
| 28 | }; | 29 | }; |
| 29 | 30 | ||
| 30 | soc-u9500 { | 31 | soc { |
| 31 | uart@80120000 { | 32 | uart@80120000 { |
| 32 | status = "okay"; | 33 | status = "okay"; |
| 33 | }; | 34 | }; |
| @@ -45,14 +46,14 @@ | |||
| 45 | compatible = "tc3589x"; | 46 | compatible = "tc3589x"; |
| 46 | reg = <0x42>; | 47 | reg = <0x42>; |
| 47 | interrupt-parent = <&gpio6>; | 48 | interrupt-parent = <&gpio6>; |
| 48 | interrupts = <25 0x1>; | 49 | interrupts = <25 IRQ_TYPE_EDGE_RISING>; |
| 49 | 50 | ||
| 50 | interrupt-controller; | 51 | interrupt-controller; |
| 51 | #interrupt-cells = <2>; | 52 | #interrupt-cells = <2>; |
| 52 | 53 | ||
| 53 | tc3589x_gpio: tc3589x_gpio { | 54 | tc3589x_gpio: tc3589x_gpio { |
| 54 | compatible = "tc3589x-gpio"; | 55 | compatible = "tc3589x-gpio"; |
| 55 | interrupts = <0 0x1>; | 56 | interrupts = <0 IRQ_TYPE_EDGE_RISING>; |
| 56 | 57 | ||
| 57 | interrupt-controller; | 58 | interrupt-controller; |
| 58 | #interrupt-cells = <2>; | 59 | #interrupt-cells = <2>; |
| @@ -63,17 +64,43 @@ | |||
| 63 | }; | 64 | }; |
| 64 | 65 | ||
| 65 | i2c@80128000 { | 66 | i2c@80128000 { |
| 66 | lp5521@0x33 { | 67 | lp5521@33 { |
| 67 | compatible = "lp5521"; | 68 | compatible = "national,lp5521"; |
| 68 | reg = <0x33>; | 69 | reg = <0x33>; |
| 70 | label = "lp5521_pri"; | ||
| 71 | clock-mode = /bits/ 8 <2>; | ||
| 72 | chan0 { | ||
| 73 | led-cur = /bits/ 8 <0x2f>; | ||
| 74 | max-cur = /bits/ 8 <0x5f>; | ||
| 75 | }; | ||
| 76 | chan1 { | ||
| 77 | led-cur = /bits/ 8 <0x2f>; | ||
| 78 | max-cur = /bits/ 8 <0x5f>; | ||
| 79 | }; | ||
| 80 | chan2 { | ||
| 81 | led-cur = /bits/ 8 <0x2f>; | ||
| 82 | max-cur = /bits/ 8 <0x5f>; | ||
| 83 | }; | ||
| 69 | }; | 84 | }; |
| 70 | 85 | lp5521@34 { | |
| 71 | lp5521@0x34 { | 86 | compatible = "national,lp5521"; |
| 72 | compatible = "lp5521"; | ||
| 73 | reg = <0x34>; | 87 | reg = <0x34>; |
| 88 | label = "lp5521_sec"; | ||
| 89 | clock-mode = /bits/ 8 <2>; | ||
| 90 | chan0 { | ||
| 91 | led-cur = /bits/ 8 <0x2f>; | ||
| 92 | max-cur = /bits/ 8 <0x5f>; | ||
| 93 | }; | ||
| 94 | chan1 { | ||
| 95 | led-cur = /bits/ 8 <0x2f>; | ||
| 96 | max-cur = /bits/ 8 <0x5f>; | ||
| 97 | }; | ||
| 98 | chan2 { | ||
| 99 | led-cur = /bits/ 8 <0x2f>; | ||
| 100 | max-cur = /bits/ 8 <0x5f>; | ||
| 101 | }; | ||
| 74 | }; | 102 | }; |
| 75 | 103 | bh1780@29 { | |
| 76 | bh1780@0x29 { | ||
| 77 | compatible = "rohm,bh1780gli"; | 104 | compatible = "rohm,bh1780gli"; |
| 78 | reg = <0x33>; | 105 | reg = <0x33>; |
| 79 | }; | 106 | }; |
| @@ -82,7 +109,7 @@ | |||
| 82 | // External Micro SD slot | 109 | // External Micro SD slot |
| 83 | sdi0_per1@80126000 { | 110 | sdi0_per1@80126000 { |
| 84 | arm,primecell-periphid = <0x10480180>; | 111 | arm,primecell-periphid = <0x10480180>; |
| 85 | max-frequency = <50000000>; | 112 | max-frequency = <100000000>; |
| 86 | bus-width = <4>; | 113 | bus-width = <4>; |
| 87 | mmc-cap-sd-highspeed; | 114 | mmc-cap-sd-highspeed; |
| 88 | mmc-cap-mmc-highspeed; | 115 | mmc-cap-mmc-highspeed; |
| @@ -97,7 +124,7 @@ | |||
| 97 | // WLAN SDIO channel | 124 | // WLAN SDIO channel |
| 98 | sdi1_per2@80118000 { | 125 | sdi1_per2@80118000 { |
| 99 | arm,primecell-periphid = <0x10480180>; | 126 | arm,primecell-periphid = <0x10480180>; |
| 100 | max-frequency = <50000000>; | 127 | max-frequency = <100000000>; |
| 101 | bus-width = <4>; | 128 | bus-width = <4>; |
| 102 | 129 | ||
| 103 | status = "okay"; | 130 | status = "okay"; |
| @@ -106,7 +133,7 @@ | |||
| 106 | // PoP:ed eMMC | 133 | // PoP:ed eMMC |
| 107 | sdi2_per3@80005000 { | 134 | sdi2_per3@80005000 { |
| 108 | arm,primecell-periphid = <0x10480180>; | 135 | arm,primecell-periphid = <0x10480180>; |
| 109 | max-frequency = <50000000>; | 136 | max-frequency = <100000000>; |
| 110 | bus-width = <8>; | 137 | bus-width = <8>; |
| 111 | mmc-cap-mmc-highspeed; | 138 | mmc-cap-mmc-highspeed; |
| 112 | 139 | ||
| @@ -116,7 +143,7 @@ | |||
| 116 | // On-board eMMC | 143 | // On-board eMMC |
| 117 | sdi4_per2@80114000 { | 144 | sdi4_per2@80114000 { |
| 118 | arm,primecell-periphid = <0x10480180>; | 145 | arm,primecell-periphid = <0x10480180>; |
| 119 | max-frequency = <50000000>; | 146 | max-frequency = <100000000>; |
| 120 | bus-width = <8>; | 147 | bus-width = <8>; |
| 121 | mmc-cap-mmc-highspeed; | 148 | mmc-cap-mmc-highspeed; |
| 122 | vmmc-supply = <&ab8500_ldo_aux2_reg>; | 149 | vmmc-supply = <&ab8500_ldo_aux2_reg>; |
| @@ -236,7 +263,7 @@ | |||
| 236 | regulator-name = "V-MMC-SD"; | 263 | regulator-name = "V-MMC-SD"; |
| 237 | }; | 264 | }; |
| 238 | 265 | ||
| 239 | ab8500_ldo_initcore_reg: ab8500_ldo_initcore { | 266 | ab8500_ldo_intcore_reg: ab8500_ldo_intcore { |
| 240 | regulator-name = "V-INTCORE"; | 267 | regulator-name = "V-INTCORE"; |
| 241 | }; | 268 | }; |
| 242 | 269 | ||
| @@ -256,7 +283,7 @@ | |||
| 256 | regulator-name = "V-AMIC1"; | 283 | regulator-name = "V-AMIC1"; |
| 257 | }; | 284 | }; |
| 258 | 285 | ||
| 259 | ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { | 286 | ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { |
| 260 | regulator-name = "V-AMIC2"; | 287 | regulator-name = "V-AMIC2"; |
| 261 | }; | 288 | }; |
| 262 | 289 | ||
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts index c2d274815923..c6bb07df2d1d 100644 --- a/arch/arm/boot/dts/hrefprev60.dts +++ b/arch/arm/boot/dts/hrefprev60.dts | |||
| @@ -10,9 +10,9 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | /include/ "dbx5x0.dtsi" | 13 | #include "dbx5x0.dtsi" |
| 14 | /include/ "href.dtsi" | 14 | #include "href.dtsi" |
| 15 | /include/ "stuib.dtsi" | 15 | #include "stuib.dtsi" |
| 16 | 16 | ||
| 17 | / { | 17 | / { |
| 18 | model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; | 18 | model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; |
| @@ -24,7 +24,7 @@ | |||
| 24 | }; | 24 | }; |
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | soc-u9500 { | 27 | soc { |
| 28 | prcmu@80157000 { | 28 | prcmu@80157000 { |
| 29 | ab8500@5 { | 29 | ab8500@5 { |
| 30 | ab8500-gpio { | 30 | ab8500-gpio { |
| @@ -41,7 +41,7 @@ | |||
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | i2c@80110000 { | 43 | i2c@80110000 { |
| 44 | bu21013_tp@0x5c { | 44 | bu21013_tp@5c { |
| 45 | reset-gpio = <&tc3589x_gpio 13 0x4>; | 45 | reset-gpio = <&tc3589x_gpio 13 0x4>; |
| 46 | }; | 46 | }; |
| 47 | }; | 47 | }; |
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index 2b587a74b813..3d580d6447f9 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts | |||
| @@ -10,9 +10,9 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | /include/ "dbx5x0.dtsi" | 13 | #include "dbx5x0.dtsi" |
| 14 | /include/ "href.dtsi" | 14 | #include "href.dtsi" |
| 15 | /include/ "stuib.dtsi" | 15 | #include "stuib.dtsi" |
| 16 | 16 | ||
| 17 | / { | 17 | / { |
| 18 | model = "ST-Ericsson HREF (v60+) platform with Device Tree"; | 18 | model = "ST-Ericsson HREF (v60+) platform with Device Tree"; |
| @@ -24,7 +24,7 @@ | |||
| 24 | }; | 24 | }; |
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | soc-u9500 { | 27 | soc { |
| 28 | i2c@80110000 { | 28 | i2c@80110000 { |
| 29 | bu21013_tp@0x5c { | 29 | bu21013_tp@0x5c { |
| 30 | reset-gpio = <&gpio4 15 0x4>; | 30 | reset-gpio = <&gpio4 15 0x4>; |
| @@ -34,7 +34,7 @@ | |||
| 34 | // External Micro SD slot | 34 | // External Micro SD slot |
| 35 | sdi0_per1@80126000 { | 35 | sdi0_per1@80126000 { |
| 36 | arm,primecell-periphid = <0x10480180>; | 36 | arm,primecell-periphid = <0x10480180>; |
| 37 | max-frequency = <50000000>; | 37 | max-frequency = <100000000>; |
| 38 | bus-width = <4>; | 38 | bus-width = <4>; |
| 39 | mmc-cap-sd-highspeed; | 39 | mmc-cap-sd-highspeed; |
| 40 | mmc-cap-mmc-highspeed; | 40 | mmc-cap-mmc-highspeed; |
| @@ -48,7 +48,7 @@ | |||
| 48 | // WLAN SDIO channel | 48 | // WLAN SDIO channel |
| 49 | sdi1_per2@80118000 { | 49 | sdi1_per2@80118000 { |
| 50 | arm,primecell-periphid = <0x10480180>; | 50 | arm,primecell-periphid = <0x10480180>; |
| 51 | max-frequency = <50000000>; | 51 | max-frequency = <100000000>; |
| 52 | bus-width = <4>; | 52 | bus-width = <4>; |
| 53 | 53 | ||
| 54 | status = "okay"; | 54 | status = "okay"; |
| @@ -57,7 +57,7 @@ | |||
| 57 | // PoP:ed eMMC | 57 | // PoP:ed eMMC |
| 58 | sdi2_per3@80005000 { | 58 | sdi2_per3@80005000 { |
| 59 | arm,primecell-periphid = <0x10480180>; | 59 | arm,primecell-periphid = <0x10480180>; |
| 60 | max-frequency = <50000000>; | 60 | max-frequency = <100000000>; |
| 61 | bus-width = <8>; | 61 | bus-width = <8>; |
| 62 | mmc-cap-mmc-highspeed; | 62 | mmc-cap-mmc-highspeed; |
| 63 | 63 | ||
| @@ -67,7 +67,7 @@ | |||
| 67 | // On-board eMMC | 67 | // On-board eMMC |
| 68 | sdi4_per2@80114000 { | 68 | sdi4_per2@80114000 { |
| 69 | arm,primecell-periphid = <0x10480180>; | 69 | arm,primecell-periphid = <0x10480180>; |
| 70 | max-frequency = <50000000>; | 70 | max-frequency = <100000000>; |
| 71 | bus-width = <8>; | 71 | bus-width = <8>; |
| 72 | mmc-cap-mmc-highspeed; | 72 | mmc-cap-mmc-highspeed; |
| 73 | vmmc-supply = <&ab8500_ldo_aux2_reg>; | 73 | vmmc-supply = <&ab8500_ldo_aux2_reg>; |
| @@ -172,7 +172,7 @@ | |||
| 172 | regulator-name = "V-MMC-SD"; | 172 | regulator-name = "V-MMC-SD"; |
| 173 | }; | 173 | }; |
| 174 | 174 | ||
| 175 | ab8500_ldo_initcore_reg: ab8500_ldo_initcore { | 175 | ab8500_ldo_intcore_reg: ab8500_ldo_intcore { |
| 176 | regulator-name = "V-INTCORE"; | 176 | regulator-name = "V-INTCORE"; |
| 177 | }; | 177 | }; |
| 178 | 178 | ||
| @@ -192,7 +192,7 @@ | |||
| 192 | regulator-name = "V-AMIC1"; | 192 | regulator-name = "V-AMIC1"; |
| 193 | }; | 193 | }; |
| 194 | 194 | ||
| 195 | ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { | 195 | ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { |
| 196 | regulator-name = "V-AMIC2"; | 196 | regulator-name = "V-AMIC2"; |
| 197 | }; | 197 | }; |
| 198 | 198 | ||
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 73fd7d0887b5..587ceef81e45 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi | |||
| @@ -23,8 +23,12 @@ | |||
| 23 | }; | 23 | }; |
| 24 | 24 | ||
| 25 | cpus { | 25 | cpus { |
| 26 | cpu@0 { | 26 | #address-cells = <0>; |
| 27 | compatible = "arm,arm926ejs"; | 27 | #size-cells = <0>; |
| 28 | |||
| 29 | cpu { | ||
| 30 | compatible = "arm,arm926ej-s"; | ||
| 31 | device_type = "cpu"; | ||
| 28 | }; | 32 | }; |
| 29 | }; | 33 | }; |
| 30 | 34 | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts new file mode 100644 index 000000000000..e7ed9786920a --- /dev/null +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * The code contained herein is licensed under the GNU General Public | ||
| 3 | * License. You may obtain a copy of the GNU General Public License | ||
| 4 | * Version 2 or later at the following locations: | ||
| 5 | * | ||
| 6 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 7 | * http://www.gnu.org/copyleft/gpl.html | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include "imx27-phytec-phycore-som.dts" | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "Phytec pcm970"; | ||
| 14 | compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27"; | ||
| 15 | }; | ||
| 16 | |||
| 17 | &cspi1 { | ||
| 18 | fsl,spi-num-chipselects = <2>; | ||
| 19 | cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>; | ||
| 20 | }; | ||
| 21 | |||
| 22 | &sdhci2 { | ||
| 23 | bus-width = <4>; | ||
| 24 | cd-gpios = <&gpio3 29 0>; | ||
| 25 | wp-gpios = <&gpio3 28 0>; | ||
| 26 | vmmc-supply = <&vmmc1_reg>; | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | &uart1 { | ||
| 31 | fsl,uart-has-rtscts; | ||
| 32 | }; | ||
| 33 | |||
| 34 | &uart2 { | ||
| 35 | fsl,uart-has-rtscts; | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts new file mode 100644 index 000000000000..f0105651869d --- /dev/null +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts | |||
| @@ -0,0 +1,179 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Sascha Hauer, Pengutronix | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx27.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "Phytec pcm038"; | ||
| 17 | compatible = "phytec,imx27-pcm038", "fsl,imx27"; | ||
| 18 | |||
| 19 | memory { | ||
| 20 | reg = <0x0 0x0>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | soc { | ||
| 24 | aipi@10000000 { /* aipi1 */ | ||
| 25 | serial@1000a000 { | ||
| 26 | status = "okay"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | i2c@1001d000 { | ||
| 30 | clock-frequency = <400000>; | ||
| 31 | status = "okay"; | ||
| 32 | at24@52 { | ||
| 33 | compatible = "at,24c32"; | ||
| 34 | pagesize = <32>; | ||
| 35 | reg = <0x52>; | ||
| 36 | }; | ||
| 37 | pcf8563@51 { | ||
| 38 | compatible = "nxp,pcf8563"; | ||
| 39 | reg = <0x51>; | ||
| 40 | }; | ||
| 41 | lm75@4a { | ||
| 42 | compatible = "national,lm75"; | ||
| 43 | reg = <0x4a>; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 48 | aipi@10020000 { /* aipi2 */ | ||
| 49 | ethernet@1002b000 { | ||
| 50 | phy-reset-gpios = <&gpio3 30 0>; | ||
| 51 | status = "okay"; | ||
| 52 | }; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | nor_flash@c0000000 { | ||
| 57 | compatible = "cfi-flash"; | ||
| 58 | bank-width = <2>; | ||
| 59 | reg = <0xc0000000 0x02000000>; | ||
| 60 | linux,mtd-name = "physmap-flash.0"; | ||
| 61 | #address-cells = <1>; | ||
| 62 | #size-cells = <1>; | ||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 66 | &cspi1 { | ||
| 67 | fsl,spi-num-chipselects = <1>; | ||
| 68 | cs-gpios = <&gpio4 28 0>; | ||
| 69 | status = "okay"; | ||
| 70 | |||
| 71 | pmic: mc13783@0 { | ||
| 72 | #address-cells = <1>; | ||
| 73 | #size-cells = <0>; | ||
| 74 | compatible = "fsl,mc13783"; | ||
| 75 | spi-max-frequency = <20000000>; | ||
| 76 | reg = <0>; | ||
| 77 | interrupt-parent = <&gpio2>; | ||
| 78 | interrupts = <23 0x4>; | ||
| 79 | fsl,mc13xxx-uses-adc; | ||
| 80 | fsl,mc13xxx-uses-rtc; | ||
| 81 | |||
| 82 | regulators { | ||
| 83 | sw1a_reg: sw1a { | ||
| 84 | regulator-min-microvolt = <1200000>; | ||
| 85 | regulator-max-microvolt = <1200000>; | ||
| 86 | regulator-always-on; | ||
| 87 | regulator-boot-on; | ||
| 88 | }; | ||
| 89 | |||
| 90 | sw1b_reg: sw1b { | ||
| 91 | regulator-min-microvolt = <1200000>; | ||
| 92 | regulator-max-microvolt = <1200000>; | ||
| 93 | regulator-always-on; | ||
| 94 | regulator-boot-on; | ||
| 95 | }; | ||
| 96 | |||
| 97 | sw2a_reg: sw2a { | ||
| 98 | regulator-min-microvolt = <1800000>; | ||
| 99 | regulator-max-microvolt = <1800000>; | ||
| 100 | regulator-always-on; | ||
| 101 | regulator-boot-on; | ||
| 102 | }; | ||
| 103 | |||
| 104 | sw2b_reg: sw2b { | ||
| 105 | regulator-min-microvolt = <1800000>; | ||
| 106 | regulator-max-microvolt = <1800000>; | ||
| 107 | regulator-always-on; | ||
| 108 | regulator-boot-on; | ||
| 109 | }; | ||
| 110 | |||
| 111 | sw3_reg: sw3 { | ||
| 112 | regulator-min-microvolt = <5000000>; | ||
| 113 | regulator-max-microvolt = <5000000>; | ||
| 114 | regulator-always-on; | ||
| 115 | regulator-boot-on; | ||
| 116 | }; | ||
| 117 | |||
| 118 | vaudio_reg: vaudio { | ||
| 119 | regulator-always-on; | ||
| 120 | regulator-boot-on; | ||
| 121 | }; | ||
| 122 | |||
| 123 | violo_reg: violo { | ||
| 124 | regulator-min-microvolt = <1800000>; | ||
| 125 | regulator-max-microvolt = <1800000>; | ||
| 126 | regulator-always-on; | ||
| 127 | regulator-boot-on; | ||
| 128 | }; | ||
| 129 | |||
| 130 | viohi_reg: viohi { | ||
| 131 | regulator-always-on; | ||
| 132 | regulator-boot-on; | ||
| 133 | }; | ||
| 134 | |||
| 135 | vgen_reg: vgen { | ||
| 136 | regulator-min-microvolt = <1500000>; | ||
| 137 | regulator-max-microvolt = <1500000>; | ||
| 138 | regulator-always-on; | ||
| 139 | regulator-boot-on; | ||
| 140 | }; | ||
| 141 | |||
| 142 | vcam_reg: vcam { | ||
| 143 | regulator-min-microvolt = <2800000>; | ||
| 144 | regulator-max-microvolt = <2800000>; | ||
| 145 | }; | ||
| 146 | |||
| 147 | vrf1_reg: vrf1 { | ||
| 148 | regulator-min-microvolt = <2775000>; | ||
| 149 | regulator-max-microvolt = <2775000>; | ||
| 150 | regulator-always-on; | ||
| 151 | regulator-boot-on; | ||
| 152 | }; | ||
| 153 | |||
| 154 | vrf2_reg: vrf2 { | ||
| 155 | regulator-min-microvolt = <2775000>; | ||
| 156 | regulator-max-microvolt = <2775000>; | ||
| 157 | regulator-always-on; | ||
| 158 | regulator-boot-on; | ||
| 159 | }; | ||
| 160 | |||
| 161 | vmmc1_reg: vmmc1 { | ||
| 162 | regulator-min-microvolt = <1600000>; | ||
| 163 | regulator-max-microvolt = <3000000>; | ||
| 164 | }; | ||
| 165 | |||
| 166 | gpo1_reg: gpo1 { }; | ||
| 167 | |||
| 168 | pwgt1spi_reg: pwgt1spi { | ||
| 169 | regulator-always-on; | ||
| 170 | }; | ||
| 171 | }; | ||
| 172 | }; | ||
| 173 | }; | ||
| 174 | |||
| 175 | &nfc { | ||
| 176 | nand-bus-width = <8>; | ||
| 177 | nand-ecc-mode = "hw"; | ||
| 178 | status = "okay"; | ||
| 179 | }; | ||
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts deleted file mode 100644 index fe64e3a91df0..000000000000 --- a/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ /dev/null | |||
| @@ -1,79 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2012 Sascha Hauer, Pengutronix | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx27.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "Phytec pcm038"; | ||
| 17 | compatible = "phytec,imx27-pcm038", "fsl,imx27"; | ||
| 18 | |||
| 19 | memory { | ||
| 20 | reg = <0x0 0x0>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | soc { | ||
| 24 | aipi@10000000 { /* aipi1 */ | ||
| 25 | serial@1000a000 { | ||
| 26 | fsl,uart-has-rtscts; | ||
| 27 | status = "okay"; | ||
| 28 | }; | ||
| 29 | |||
| 30 | serial@1000b000 { | ||
| 31 | fsl,uart-has-rtscts; | ||
| 32 | status = "okay"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | serial@1000c000 { | ||
| 36 | fsl,uart-has-rtscts; | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | |||
| 40 | i2c@1001d000 { | ||
| 41 | clock-frequency = <400000>; | ||
| 42 | status = "okay"; | ||
| 43 | at24@52 { | ||
| 44 | compatible = "at,24c32"; | ||
| 45 | pagesize = <32>; | ||
| 46 | reg = <0x52>; | ||
| 47 | }; | ||
| 48 | pcf8563@51 { | ||
| 49 | compatible = "nxp,pcf8563"; | ||
| 50 | reg = <0x51>; | ||
| 51 | }; | ||
| 52 | lm75@4a { | ||
| 53 | compatible = "national,lm75"; | ||
| 54 | reg = <0x4a>; | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | }; | ||
| 58 | |||
| 59 | aipi@10020000 { /* aipi2 */ | ||
| 60 | ethernet@1002b000 { | ||
| 61 | status = "okay"; | ||
| 62 | }; | ||
| 63 | }; | ||
| 64 | }; | ||
| 65 | |||
| 66 | nor_flash@c0000000 { | ||
| 67 | compatible = "cfi-flash"; | ||
| 68 | bank-width = <2>; | ||
| 69 | reg = <0xc0000000 0x02000000>; | ||
| 70 | #address-cells = <1>; | ||
| 71 | #size-cells = <1>; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | |||
| 75 | &nfc { | ||
| 76 | nand-bus-width = <8>; | ||
| 77 | nand-ecc-mode = "hw"; | ||
| 78 | status = "okay"; | ||
| 79 | }; | ||
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 75bd11386516..0695264ddf1b 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi | |||
| @@ -25,6 +25,9 @@ | |||
| 25 | gpio3 = &gpio4; | 25 | gpio3 = &gpio4; |
| 26 | gpio4 = &gpio5; | 26 | gpio4 = &gpio5; |
| 27 | gpio5 = &gpio6; | 27 | gpio5 = &gpio6; |
| 28 | spi0 = &cspi1; | ||
| 29 | spi1 = &cspi2; | ||
| 30 | spi2 = &cspi3; | ||
| 28 | }; | 31 | }; |
| 29 | 32 | ||
| 30 | avic: avic-interrupt-controller@e0000000 { | 33 | avic: avic-interrupt-controller@e0000000 { |
| @@ -58,6 +61,16 @@ | |||
| 58 | reg = <0x10000000 0x20000>; | 61 | reg = <0x10000000 0x20000>; |
| 59 | ranges; | 62 | ranges; |
| 60 | 63 | ||
| 64 | dma: dma@10001000 { | ||
| 65 | compatible = "fsl,imx27-dma"; | ||
| 66 | reg = <0x10001000 0x1000>; | ||
| 67 | interrupts = <32>; | ||
| 68 | clocks = <&clks 50>, <&clks 70>; | ||
| 69 | clock-names = "ipg", "ahb"; | ||
| 70 | #dma-cells = <1>; | ||
| 71 | #dma-channels = <16>; | ||
| 72 | }; | ||
| 73 | |||
| 61 | wdog: wdog@10002000 { | 74 | wdog: wdog@10002000 { |
| 62 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; | 75 | compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; |
| 63 | reg = <0x10002000 0x1000>; | 76 | reg = <0x10002000 0x1000>; |
| @@ -89,6 +102,14 @@ | |||
| 89 | clock-names = "ipg", "per"; | 102 | clock-names = "ipg", "per"; |
| 90 | }; | 103 | }; |
| 91 | 104 | ||
| 105 | pwm0: pwm@10006000 { | ||
| 106 | compatible = "fsl,imx27-pwm"; | ||
| 107 | reg = <0x10006000 0x1000>; | ||
| 108 | interrupts = <23>; | ||
| 109 | clocks = <&clks 34>, <&clks 61>; | ||
| 110 | clock-names = "ipg", "per"; | ||
| 111 | }; | ||
| 112 | |||
| 92 | uart1: serial@1000a000 { | 113 | uart1: serial@1000a000 { |
| 93 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; | 114 | compatible = "fsl,imx27-uart", "fsl,imx21-uart"; |
| 94 | reg = <0x1000a000 0x1000>; | 115 | reg = <0x1000a000 0x1000>; |
| @@ -157,6 +178,28 @@ | |||
| 157 | status = "disabled"; | 178 | status = "disabled"; |
| 158 | }; | 179 | }; |
| 159 | 180 | ||
| 181 | sdhci1: sdhci@10013000 { | ||
| 182 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | ||
| 183 | reg = <0x10013000 0x1000>; | ||
| 184 | interrupts = <11>; | ||
| 185 | clocks = <&clks 30>, <&clks 60>; | ||
| 186 | clock-names = "ipg", "per"; | ||
| 187 | dmas = <&dma 7>; | ||
| 188 | dma-names = "rx-tx"; | ||
| 189 | status = "disabled"; | ||
| 190 | }; | ||
| 191 | |||
| 192 | sdhci2: sdhci@10014000 { | ||
| 193 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | ||
| 194 | reg = <0x10014000 0x1000>; | ||
| 195 | interrupts = <10>; | ||
| 196 | clocks = <&clks 29>, <&clks 60>; | ||
| 197 | clock-names = "ipg", "per"; | ||
| 198 | dmas = <&dma 6>; | ||
| 199 | dma-names = "rx-tx"; | ||
| 200 | status = "disabled"; | ||
| 201 | }; | ||
| 202 | |||
| 160 | gpio1: gpio@10015000 { | 203 | gpio1: gpio@10015000 { |
| 161 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; | 204 | compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; |
| 162 | reg = <0x10015000 0x100>; | 205 | reg = <0x10015000 0x100>; |
| @@ -272,6 +315,17 @@ | |||
| 272 | status = "disabled"; | 315 | status = "disabled"; |
| 273 | }; | 316 | }; |
| 274 | 317 | ||
| 318 | sdhci3: sdhci@1001e000 { | ||
| 319 | compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; | ||
| 320 | reg = <0x1001e000 0x1000>; | ||
| 321 | interrupts = <9>; | ||
| 322 | clocks = <&clks 28>, <&clks 60>; | ||
| 323 | clock-names = "ipg", "per"; | ||
| 324 | dmas = <&dma 36>; | ||
| 325 | dma-names = "rx-tx"; | ||
| 326 | status = "disabled"; | ||
| 327 | }; | ||
| 328 | |||
| 275 | gpt6: timer@1001f000 { | 329 | gpt6: timer@1001f000 { |
| 276 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; | 330 | compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; |
| 277 | reg = <0x1001f000 0x1000>; | 331 | reg = <0x1001f000 0x1000>; |
| @@ -288,6 +342,21 @@ | |||
| 288 | reg = <0x10020000 0x20000>; | 342 | reg = <0x10020000 0x20000>; |
| 289 | ranges; | 343 | ranges; |
| 290 | 344 | ||
| 345 | coda: coda@10023000 { | ||
| 346 | compatible = "fsl,imx27-vpu"; | ||
| 347 | reg = <0x10023000 0x0200>; | ||
| 348 | interrupts = <53>; | ||
| 349 | clocks = <&clks 57>, <&clks 66>; | ||
| 350 | clock-names = "per", "ahb"; | ||
| 351 | iram = <&iram>; | ||
| 352 | }; | ||
| 353 | |||
| 354 | clks: ccm@10027000{ | ||
| 355 | compatible = "fsl,imx27-ccm"; | ||
| 356 | reg = <0x10027000 0x1000>; | ||
| 357 | #clock-cells = <1>; | ||
| 358 | }; | ||
| 359 | |||
| 291 | fec: ethernet@1002b000 { | 360 | fec: ethernet@1002b000 { |
| 292 | compatible = "fsl,imx27-fec"; | 361 | compatible = "fsl,imx27-fec"; |
| 293 | reg = <0x1002b000 0x4000>; | 362 | reg = <0x1002b000 0x4000>; |
| @@ -296,19 +365,16 @@ | |||
| 296 | clock-names = "ipg", "ahb", "ptp"; | 365 | clock-names = "ipg", "ahb", "ptp"; |
| 297 | status = "disabled"; | 366 | status = "disabled"; |
| 298 | }; | 367 | }; |
| 299 | |||
| 300 | clks: ccm@10027000{ | ||
| 301 | compatible = "fsl,imx27-ccm"; | ||
| 302 | reg = <0x10027000 0x1000>; | ||
| 303 | #clock-cells = <1>; | ||
| 304 | }; | ||
| 305 | }; | 368 | }; |
| 306 | 369 | ||
| 370 | iram: iram@ffff4c00 { | ||
| 371 | compatible = "mmio-sram"; | ||
| 372 | reg = <0xffff4c00 0xb400>; | ||
| 373 | }; | ||
| 307 | 374 | ||
| 308 | nfc: nand@d8000000 { | 375 | nfc: nand@d8000000 { |
| 309 | #address-cells = <1>; | 376 | #address-cells = <1>; |
| 310 | #size-cells = <1>; | 377 | #size-cells = <1>; |
| 311 | |||
| 312 | compatible = "fsl,imx27-nand"; | 378 | compatible = "fsl,imx27-nand"; |
| 313 | reg = <0xd8000000 0x1000>; | 379 | reg = <0xd8000000 0x1000>; |
| 314 | interrupts = <29>; | 380 | interrupts = <29>; |
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index 3d905d16cbec..b602494c152b 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts | |||
| @@ -103,6 +103,7 @@ | |||
| 103 | 103 | ||
| 104 | apbx@80040000 { | 104 | apbx@80040000 { |
| 105 | lradc@80050000 { | 105 | lradc@80050000 { |
| 106 | fsl,lradc-touchscreen-wires = <4>; | ||
| 106 | status = "okay"; | 107 | status = "okay"; |
| 107 | }; | 108 | }; |
| 108 | 109 | ||
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index 1594694532b9..94c4476972c3 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts | |||
| @@ -45,6 +45,17 @@ | |||
| 45 | fsl,voltage = <1>; | 45 | fsl,voltage = <1>; |
| 46 | fsl,pull-up = <0>; | 46 | fsl,pull-up = <0>; |
| 47 | }; | 47 | }; |
| 48 | |||
| 49 | usb0_otg_cfa10036: otg-10036@0 { | ||
| 50 | reg = <0>; | ||
| 51 | fsl,pinmux-ids = < | ||
| 52 | 0x0142 /* MX28_PAD_GPMI_READY0__USB0_ID */ | ||
| 53 | >; | ||
| 54 | fsl,drive-strength = <0>; | ||
| 55 | fsl,voltage = <1>; | ||
| 56 | fsl,pull-up = <0>; | ||
| 57 | }; | ||
| 58 | |||
| 48 | }; | 59 | }; |
| 49 | 60 | ||
| 50 | ssp0: ssp@80010000 { | 61 | ssp0: ssp@80010000 { |
| @@ -58,12 +69,6 @@ | |||
| 58 | }; | 69 | }; |
| 59 | 70 | ||
| 60 | apbx@80040000 { | 71 | apbx@80040000 { |
| 61 | pwm: pwm@80064000 { | ||
| 62 | pinctrl-names = "default"; | ||
| 63 | pinctrl-0 = <&pwm4_pins_a>; | ||
| 64 | status = "okay"; | ||
| 65 | }; | ||
| 66 | |||
| 67 | duart: serial@80074000 { | 72 | duart: serial@80074000 { |
| 68 | pinctrl-names = "default"; | 73 | pinctrl-names = "default"; |
| 69 | pinctrl-0 = <&duart_pins_b>; | 74 | pinctrl-0 = <&duart_pins_b>; |
| @@ -73,15 +78,30 @@ | |||
| 73 | i2c0: i2c@80058000 { | 78 | i2c0: i2c@80058000 { |
| 74 | pinctrl-names = "default"; | 79 | pinctrl-names = "default"; |
| 75 | pinctrl-0 = <&i2c0_pins_b>; | 80 | pinctrl-0 = <&i2c0_pins_b>; |
| 81 | clock-frequency = <400000>; | ||
| 76 | status = "okay"; | 82 | status = "okay"; |
| 77 | 83 | ||
| 78 | ssd1307: oled@3c { | 84 | ssd1306: oled@3c { |
| 79 | compatible = "solomon,ssd1307fb-i2c"; | 85 | compatible = "solomon,ssd1306fb-i2c"; |
| 80 | reg = <0x3c>; | 86 | reg = <0x3c>; |
| 81 | pwms = <&pwm 4 3000>; | ||
| 82 | reset-gpios = <&gpio2 7 0>; | 87 | reset-gpios = <&gpio2 7 0>; |
| 88 | solomon,height = <32>; | ||
| 89 | solomon,width = <128>; | ||
| 90 | solomon,page-offset = <0>; | ||
| 83 | }; | 91 | }; |
| 84 | }; | 92 | }; |
| 93 | |||
| 94 | usbphy0: usbphy@8007c000 { | ||
| 95 | status = "okay"; | ||
| 96 | }; | ||
| 97 | }; | ||
| 98 | }; | ||
| 99 | |||
| 100 | ahb@80080000 { | ||
| 101 | usb0: usb@80080000 { | ||
| 102 | pinctrl-names = "default"; | ||
| 103 | pinctrl-0 = <&usb0_otg_cfa10036>; | ||
| 104 | status = "okay"; | ||
| 85 | }; | 105 | }; |
| 86 | }; | 106 | }; |
| 87 | 107 | ||
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 063e62059890..04b2f769ffbd 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts | |||
| @@ -33,7 +33,7 @@ | |||
| 33 | 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ | 33 | 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ |
| 34 | 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ | 34 | 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ |
| 35 | 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ | 35 | 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ |
| 36 | 0x3173 /* MX28_PAD_LCD_RESET__GPIO_3_23 */ | 36 | 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ |
| 37 | >; | 37 | >; |
| 38 | fsl,drive-strength = <0>; | 38 | fsl,drive-strength = <0>; |
| 39 | fsl,voltage = <1>; | 39 | fsl,voltage = <1>; |
| @@ -166,8 +166,8 @@ | |||
| 166 | 166 | ||
| 167 | apbx@80040000 { | 167 | apbx@80040000 { |
| 168 | pwm: pwm@80064000 { | 168 | pwm: pwm@80064000 { |
| 169 | pinctrl-names = "default", "default"; | 169 | pinctrl-names = "default"; |
| 170 | pinctrl-1 = <&pwm3_pins_b>; | 170 | pinctrl-0 = <&pwm3_pins_b>; |
| 171 | status = "okay"; | 171 | status = "okay"; |
| 172 | }; | 172 | }; |
| 173 | 173 | ||
| @@ -265,7 +265,7 @@ | |||
| 265 | gpio-sck = <&gpio2 16 0>; | 265 | gpio-sck = <&gpio2 16 0>; |
| 266 | gpio-mosi = <&gpio2 17 0>; | 266 | gpio-mosi = <&gpio2 17 0>; |
| 267 | gpio-miso = <&gpio2 18 0>; | 267 | gpio-miso = <&gpio2 18 0>; |
| 268 | cs-gpios = <&gpio3 23 0>; | 268 | cs-gpios = <&gpio3 5 0>; |
| 269 | num-chipselects = <1>; | 269 | num-chipselects = <1>; |
| 270 | #address-cells = <1>; | 270 | #address-cells = <1>; |
| 271 | #size-cells = <0>; | 271 | #size-cells = <0>; |
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts new file mode 100644 index 000000000000..158111244122 --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10055.dts | |||
| @@ -0,0 +1,179 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Crystalfontz America, Inc. | ||
| 3 | * Free Electrons | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * The CFA-10055 is an expansion board for the CFA-10036 module and | ||
| 15 | * CFA-10037, thus we need to include the CFA-10037 DTS. | ||
| 16 | */ | ||
| 17 | /include/ "imx28-cfa10037.dts" | ||
| 18 | |||
| 19 | / { | ||
| 20 | model = "Crystalfontz CFA-10055 Board"; | ||
| 21 | compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; | ||
| 22 | |||
| 23 | apb@80000000 { | ||
| 24 | apbh@80000000 { | ||
| 25 | pinctrl@80018000 { | ||
| 26 | pinctrl-names = "default", "default"; | ||
| 27 | pinctrl-1 = <&hog_pins_cfa10055 | ||
| 28 | &hog_pins_cfa10055_pullup>; | ||
| 29 | |||
| 30 | hog_pins_cfa10055: hog-10055@0 { | ||
| 31 | reg = <0>; | ||
| 32 | fsl,pinmux-ids = < | ||
| 33 | 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ | ||
| 34 | >; | ||
| 35 | fsl,drive-strength = <0>; | ||
| 36 | fsl,voltage = <1>; | ||
| 37 | fsl,pull-up = <0>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | hog_pins_cfa10055_pullup: hog-10055-pullup@0 { | ||
| 41 | reg = <0>; | ||
| 42 | fsl,pinmux-ids = < | ||
| 43 | 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ | ||
| 44 | >; | ||
| 45 | fsl,drive-strength = <0>; | ||
| 46 | fsl,voltage = <1>; | ||
| 47 | fsl,pull-up = <1>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | spi2_pins_cfa10055: spi2-cfa10055@0 { | ||
| 51 | reg = <0>; | ||
| 52 | fsl,pinmux-ids = < | ||
| 53 | 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ | ||
| 54 | 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ | ||
| 55 | 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ | ||
| 56 | >; | ||
| 57 | fsl,drive-strength = <1>; | ||
| 58 | fsl,voltage = <1>; | ||
| 59 | fsl,pull-up = <1>; | ||
| 60 | }; | ||
| 61 | |||
| 62 | lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { | ||
| 63 | reg = <0>; | ||
| 64 | fsl,pinmux-ids = < | ||
| 65 | 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ | ||
| 66 | 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ | ||
| 67 | 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ | ||
| 68 | 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ | ||
| 69 | 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ | ||
| 70 | 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ | ||
| 71 | 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ | ||
| 72 | 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ | ||
| 73 | 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ | ||
| 74 | 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ | ||
| 75 | 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ | ||
| 76 | 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ | ||
| 77 | 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ | ||
| 78 | 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ | ||
| 79 | 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ | ||
| 80 | 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ | ||
| 81 | 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ | ||
| 82 | 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ | ||
| 83 | >; | ||
| 84 | fsl,drive-strength = <0>; | ||
| 85 | fsl,voltage = <1>; | ||
| 86 | fsl,pull-up = <0>; | ||
| 87 | }; | ||
| 88 | |||
| 89 | lcdif_pins_cfa10055: lcdif-evk@0 { | ||
| 90 | reg = <0>; | ||
| 91 | fsl,pinmux-ids = < | ||
| 92 | 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ | ||
| 93 | 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ | ||
| 94 | 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ | ||
| 95 | 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ | ||
| 96 | >; | ||
| 97 | fsl,drive-strength = <0>; | ||
| 98 | fsl,voltage = <1>; | ||
| 99 | fsl,pull-up = <0>; | ||
| 100 | }; | ||
| 101 | }; | ||
| 102 | |||
| 103 | lcdif@80030000 { | ||
| 104 | pinctrl-names = "default"; | ||
| 105 | pinctrl-0 = <&lcdif_18bit_pins_cfa10055 | ||
| 106 | &lcdif_pins_cfa10055>; | ||
| 107 | display = <&display>; | ||
| 108 | status = "okay"; | ||
| 109 | |||
| 110 | display: display { | ||
| 111 | bits-per-pixel = <32>; | ||
| 112 | bus-width = <18>; | ||
| 113 | |||
| 114 | display-timings { | ||
| 115 | native-mode = <&timing0>; | ||
| 116 | timing0: timing0 { | ||
| 117 | clock-frequency = <9216000>; | ||
| 118 | hactive = <320>; | ||
| 119 | vactive = <480>; | ||
| 120 | hback-porch = <2>; | ||
| 121 | hfront-porch = <2>; | ||
| 122 | vback-porch = <2>; | ||
| 123 | vfront-porch = <2>; | ||
| 124 | hsync-len = <15>; | ||
| 125 | vsync-len = <15>; | ||
| 126 | hsync-active = <0>; | ||
| 127 | vsync-active = <0>; | ||
| 128 | de-active = <1>; | ||
| 129 | pixelclk-active = <1>; | ||
| 130 | }; | ||
| 131 | }; | ||
| 132 | }; | ||
| 133 | }; | ||
| 134 | }; | ||
| 135 | |||
| 136 | apbx@80040000 { | ||
| 137 | lradc@80050000 { | ||
| 138 | fsl,lradc-touchscreen-wires = <4>; | ||
| 139 | status = "okay"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | pwm: pwm@80064000 { | ||
| 143 | pinctrl-names = "default"; | ||
| 144 | pinctrl-0 = <&pwm3_pins_b>; | ||
| 145 | status = "okay"; | ||
| 146 | }; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | |||
| 150 | spi2 { | ||
| 151 | compatible = "spi-gpio"; | ||
| 152 | pinctrl-names = "default"; | ||
| 153 | pinctrl-0 = <&spi2_pins_cfa10055>; | ||
| 154 | status = "okay"; | ||
| 155 | gpio-sck = <&gpio2 16 0>; | ||
| 156 | gpio-mosi = <&gpio2 17 0>; | ||
| 157 | gpio-miso = <&gpio2 18 0>; | ||
| 158 | cs-gpios = <&gpio3 5 0>; | ||
| 159 | num-chipselects = <1>; | ||
| 160 | #address-cells = <1>; | ||
| 161 | #size-cells = <0>; | ||
| 162 | |||
| 163 | hx8357: hx8357@0 { | ||
| 164 | compatible = "himax,hx8357b", "himax,hx8357"; | ||
| 165 | reg = <0>; | ||
| 166 | spi-max-frequency = <100000>; | ||
| 167 | spi-cpol; | ||
| 168 | spi-cpha; | ||
| 169 | gpios-reset = <&gpio3 30 0>; | ||
| 170 | }; | ||
| 171 | }; | ||
| 172 | |||
| 173 | backlight { | ||
| 174 | compatible = "pwm-backlight"; | ||
| 175 | pwms = <&pwm 3 5000000>; | ||
| 176 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 177 | default-brightness-level = <6>; | ||
| 178 | }; | ||
| 179 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts new file mode 100644 index 000000000000..2da713cdb42a --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10057.dts | |||
| @@ -0,0 +1,191 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Crystalfontz America, Inc. | ||
| 3 | * Copyright 2012 Free Electrons | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * The CFA-10057 is an expansion board for the CFA-10036 module, thus we | ||
| 15 | * need to include the CFA-10036 DTS. | ||
| 16 | */ | ||
| 17 | /include/ "imx28-cfa10036.dts" | ||
| 18 | |||
| 19 | / { | ||
| 20 | model = "Crystalfontz CFA-10057 Board"; | ||
| 21 | compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28"; | ||
| 22 | |||
| 23 | apb@80000000 { | ||
| 24 | apbh@80000000 { | ||
| 25 | pinctrl@80018000 { | ||
| 26 | pinctrl-names = "default", "default"; | ||
| 27 | pinctrl-1 = <&hog_pins_cfa10057 | ||
| 28 | &hog_pins_cfa10057_pullup>; | ||
| 29 | |||
| 30 | hog_pins_cfa10057: hog-10057@0 { | ||
| 31 | reg = <0>; | ||
| 32 | fsl,pinmux-ids = < | ||
| 33 | 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ | ||
| 34 | 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ | ||
| 35 | >; | ||
| 36 | fsl,drive-strength = <0>; | ||
| 37 | fsl,voltage = <1>; | ||
| 38 | fsl,pull-up = <0>; | ||
| 39 | }; | ||
| 40 | |||
| 41 | hog_pins_cfa10057_pullup: hog-10057-pullup@0 { | ||
| 42 | reg = <0>; | ||
| 43 | fsl,pinmux-ids = < | ||
| 44 | 0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */ | ||
| 45 | 0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */ | ||
| 46 | 0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */ | ||
| 47 | 0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */ | ||
| 48 | 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ | ||
| 49 | >; | ||
| 50 | fsl,drive-strength = <0>; | ||
| 51 | fsl,voltage = <1>; | ||
| 52 | fsl,pull-up = <1>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { | ||
| 56 | reg = <0>; | ||
| 57 | fsl,pinmux-ids = < | ||
| 58 | 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ | ||
| 59 | 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ | ||
| 60 | 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ | ||
| 61 | 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ | ||
| 62 | 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ | ||
| 63 | 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ | ||
| 64 | 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ | ||
| 65 | 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ | ||
| 66 | 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ | ||
| 67 | 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ | ||
| 68 | 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ | ||
| 69 | 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ | ||
| 70 | 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ | ||
| 71 | 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ | ||
| 72 | 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ | ||
| 73 | 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ | ||
| 74 | 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ | ||
| 75 | 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ | ||
| 76 | >; | ||
| 77 | fsl,drive-strength = <0>; | ||
| 78 | fsl,voltage = <1>; | ||
| 79 | fsl,pull-up = <0>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | lcdif_pins_cfa10057: lcdif-evk@0 { | ||
| 83 | reg = <0>; | ||
| 84 | fsl,pinmux-ids = < | ||
| 85 | 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ | ||
| 86 | 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ | ||
| 87 | 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ | ||
| 88 | 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ | ||
| 89 | >; | ||
| 90 | fsl,drive-strength = <0>; | ||
| 91 | fsl,voltage = <1>; | ||
| 92 | fsl,pull-up = <0>; | ||
| 93 | }; | ||
| 94 | }; | ||
| 95 | |||
| 96 | lcdif@80030000 { | ||
| 97 | pinctrl-names = "default"; | ||
| 98 | pinctrl-0 = <&lcdif_18bit_pins_cfa10057 | ||
| 99 | &lcdif_pins_cfa10057>; | ||
| 100 | display = <&display>; | ||
| 101 | status = "okay"; | ||
| 102 | |||
| 103 | display: display { | ||
| 104 | bits-per-pixel = <32>; | ||
| 105 | bus-width = <18>; | ||
| 106 | |||
| 107 | display-timings { | ||
| 108 | native-mode = <&timing0>; | ||
| 109 | timing0: timing0 { | ||
| 110 | clock-frequency = <30000000>; | ||
| 111 | hactive = <480>; | ||
| 112 | vactive = <800>; | ||
| 113 | hfront-porch = <12>; | ||
| 114 | hback-porch = <2>; | ||
| 115 | vfront-porch = <5>; | ||
| 116 | vback-porch = <3>; | ||
| 117 | hsync-len = <2>; | ||
| 118 | vsync-len = <2>; | ||
| 119 | hsync-active = <0>; | ||
| 120 | vsync-active = <0>; | ||
| 121 | de-active = <1>; | ||
| 122 | pixelclk-active = <1>; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | apbx@80040000 { | ||
| 130 | lradc@80050000 { | ||
| 131 | fsl,lradc-touchscreen-wires = <4>; | ||
| 132 | status = "okay"; | ||
| 133 | }; | ||
| 134 | |||
| 135 | pwm: pwm@80064000 { | ||
| 136 | pinctrl-names = "default"; | ||
| 137 | pinctrl-0 = <&pwm3_pins_b>; | ||
| 138 | status = "okay"; | ||
| 139 | }; | ||
| 140 | |||
| 141 | i2c1: i2c@8005a000 { | ||
| 142 | pinctrl-names = "default"; | ||
| 143 | pinctrl-0 = <&i2c1_pins_a>; | ||
| 144 | status = "okay"; | ||
| 145 | }; | ||
| 146 | |||
| 147 | usbphy1: usbphy@8007e000 { | ||
| 148 | status = "okay"; | ||
| 149 | }; | ||
| 150 | }; | ||
| 151 | }; | ||
| 152 | |||
| 153 | ahb@80080000 { | ||
| 154 | usb1: usb@80090000 { | ||
| 155 | vbus-supply = <®_usb1_vbus>; | ||
| 156 | pinctrl-0 = <&usbphy1_pins_a>; | ||
| 157 | pinctrl-names = "default"; | ||
| 158 | status = "okay"; | ||
| 159 | }; | ||
| 160 | }; | ||
| 161 | |||
| 162 | regulators { | ||
| 163 | compatible = "simple-bus"; | ||
| 164 | |||
| 165 | reg_usb1_vbus: usb1_vbus { | ||
| 166 | compatible = "regulator-fixed"; | ||
| 167 | regulator-name = "usb1_vbus"; | ||
| 168 | regulator-min-microvolt = <5000000>; | ||
| 169 | regulator-max-microvolt = <5000000>; | ||
| 170 | gpio = <&gpio0 7 1>; | ||
| 171 | }; | ||
| 172 | }; | ||
| 173 | |||
| 174 | ahb@80080000 { | ||
| 175 | mac0: ethernet@800f0000 { | ||
| 176 | phy-mode = "rmii"; | ||
| 177 | pinctrl-names = "default"; | ||
| 178 | pinctrl-0 = <&mac0_pins_a>; | ||
| 179 | phy-reset-gpios = <&gpio2 21 0>; | ||
| 180 | phy-reset-duration = <100>; | ||
| 181 | status = "okay"; | ||
| 182 | }; | ||
| 183 | }; | ||
| 184 | |||
| 185 | backlight { | ||
| 186 | compatible = "pwm-backlight"; | ||
| 187 | pwms = <&pwm 3 5000000>; | ||
| 188 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 189 | default-brightness-level = <7>; | ||
| 190 | }; | ||
| 191 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 5aa44e05c9f5..880df2f13be8 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts | |||
| @@ -220,7 +220,19 @@ | |||
| 220 | 220 | ||
| 221 | auart0: serial@8006a000 { | 221 | auart0: serial@8006a000 { |
| 222 | pinctrl-names = "default"; | 222 | pinctrl-names = "default"; |
| 223 | pinctrl-0 = <&auart0_2pins_a>; | 223 | pinctrl-0 = <&auart0_pins_a>; |
| 224 | status = "okay"; | ||
| 225 | }; | ||
| 226 | |||
| 227 | auart1: serial@8006c000 { | ||
| 228 | pinctrl-names = "default"; | ||
| 229 | pinctrl-0 = <&auart1_pins_a>; | ||
| 230 | status = "okay"; | ||
| 231 | }; | ||
| 232 | |||
| 233 | auart2: serial@8006e000 { | ||
| 234 | pinctrl-names = "default"; | ||
| 235 | pinctrl-0 = <&auart2_2pins_b>; | ||
| 224 | status = "okay"; | 236 | status = "okay"; |
| 225 | }; | 237 | }; |
| 226 | }; | 238 | }; |
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 600f7cb51f3e..195451bf7706 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi | |||
| @@ -32,8 +32,12 @@ | |||
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | cpus { | 34 | cpus { |
| 35 | cpu@0 { | 35 | #address-cells = <0>; |
| 36 | compatible = "arm,arm926ejs"; | 36 | #size-cells = <0>; |
| 37 | |||
| 38 | cpu { | ||
| 39 | compatible = "arm,arm926ej-s"; | ||
| 40 | device_type = "cpu"; | ||
| 37 | }; | 41 | }; |
| 38 | }; | 42 | }; |
| 39 | 43 | ||
| @@ -330,6 +334,17 @@ | |||
| 330 | fsl,pull-up = <0>; | 334 | fsl,pull-up = <0>; |
| 331 | }; | 335 | }; |
| 332 | 336 | ||
| 337 | auart2_2pins_b: auart2-2pins@1 { | ||
| 338 | reg = <1>; | ||
| 339 | fsl,pinmux-ids = < | ||
| 340 | 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */ | ||
| 341 | 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */ | ||
| 342 | >; | ||
| 343 | fsl,drive-strength = <0>; | ||
| 344 | fsl,voltage = <1>; | ||
| 345 | fsl,pull-up = <0>; | ||
| 346 | }; | ||
| 347 | |||
| 333 | auart3_pins_a: auart3@0 { | 348 | auart3_pins_a: auart3@0 { |
| 334 | reg = <0>; | 349 | reg = <0>; |
| 335 | fsl,pinmux-ids = < | 350 | fsl,pinmux-ids = < |
| @@ -354,6 +369,28 @@ | |||
| 354 | fsl,pull-up = <0>; | 369 | fsl,pull-up = <0>; |
| 355 | }; | 370 | }; |
| 356 | 371 | ||
| 372 | auart3_2pins_b: auart3-2pins@1 { | ||
| 373 | reg = <1>; | ||
| 374 | fsl,pinmux-ids = < | ||
| 375 | 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ | ||
| 376 | 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ | ||
| 377 | >; | ||
| 378 | fsl,drive-strength = <0>; | ||
| 379 | fsl,voltage = <1>; | ||
| 380 | fsl,pull-up = <0>; | ||
| 381 | }; | ||
| 382 | |||
| 383 | auart4_2pins_a: auart4@0 { | ||
| 384 | reg = <0>; | ||
| 385 | fsl,pinmux-ids = < | ||
| 386 | 0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */ | ||
| 387 | 0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */ | ||
| 388 | >; | ||
| 389 | fsl,drive-strength = <0>; | ||
| 390 | fsl,voltage = <1>; | ||
| 391 | fsl,pull-up = <0>; | ||
| 392 | }; | ||
| 393 | |||
| 357 | mac0_pins_a: mac0@0 { | 394 | mac0_pins_a: mac0@0 { |
| 358 | reg = <0>; | 395 | reg = <0>; |
| 359 | fsl,pinmux-ids = < | 396 | fsl,pinmux-ids = < |
| @@ -669,7 +706,7 @@ | |||
| 669 | }; | 706 | }; |
| 670 | 707 | ||
| 671 | digctl@8001c000 { | 708 | digctl@8001c000 { |
| 672 | compatible = "fsl,imx28-digctl"; | 709 | compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; |
| 673 | reg = <0x8001c000 0x2000>; | 710 | reg = <0x8001c000 0x2000>; |
| 674 | interrupts = <89>; | 711 | interrupts = <89>; |
| 675 | status = "disabled"; | 712 | status = "disabled"; |
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts index 2bcf6981d490..8f7f9ac0b989 100644 --- a/arch/arm/boot/dts/imx51-apf51.dts +++ b/arch/arm/boot/dts/imx51-apf51.dts | |||
| @@ -45,6 +45,13 @@ | |||
| 45 | status = "okay"; | 45 | status = "okay"; |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | &nfc { | ||
| 49 | nand-bus-width = <8>; | ||
| 50 | nand-ecc-mode = "hw"; | ||
| 51 | nand-on-flash-bbt; | ||
| 52 | status = "okay"; | ||
| 53 | }; | ||
| 54 | |||
| 48 | &uart3 { | 55 | &uart3 { |
| 49 | pinctrl-names = "default"; | 56 | pinctrl-names = "default"; |
| 50 | pinctrl-0 = <&pinctrl_uart3_2>; | 57 | pinctrl-0 = <&pinctrl_uart3_2>; |
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 53fdde69bbf4..25764b505a61 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi | |||
| @@ -175,10 +175,20 @@ | |||
| 175 | }; | 175 | }; |
| 176 | }; | 176 | }; |
| 177 | 177 | ||
| 178 | usbphy0: usbphy@0 { | ||
| 179 | compatible = "usb-nop-xceiv"; | ||
| 180 | clocks = <&clks 124>; | ||
| 181 | clock-names = "main_clk"; | ||
| 182 | status = "okay"; | ||
| 183 | }; | ||
| 184 | |||
| 178 | usbotg: usb@73f80000 { | 185 | usbotg: usb@73f80000 { |
| 179 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | 186 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 180 | reg = <0x73f80000 0x0200>; | 187 | reg = <0x73f80000 0x0200>; |
| 181 | interrupts = <18>; | 188 | interrupts = <18>; |
| 189 | clocks = <&clks 108>; | ||
| 190 | fsl,usbmisc = <&usbmisc 0>; | ||
| 191 | fsl,usbphy = <&usbphy0>; | ||
| 182 | status = "disabled"; | 192 | status = "disabled"; |
| 183 | }; | 193 | }; |
| 184 | 194 | ||
| @@ -186,6 +196,8 @@ | |||
| 186 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | 196 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 187 | reg = <0x73f80200 0x0200>; | 197 | reg = <0x73f80200 0x0200>; |
| 188 | interrupts = <14>; | 198 | interrupts = <14>; |
| 199 | clocks = <&clks 108>; | ||
| 200 | fsl,usbmisc = <&usbmisc 1>; | ||
| 189 | status = "disabled"; | 201 | status = "disabled"; |
| 190 | }; | 202 | }; |
| 191 | 203 | ||
| @@ -193,6 +205,8 @@ | |||
| 193 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | 205 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 194 | reg = <0x73f80400 0x0200>; | 206 | reg = <0x73f80400 0x0200>; |
| 195 | interrupts = <16>; | 207 | interrupts = <16>; |
| 208 | clocks = <&clks 108>; | ||
| 209 | fsl,usbmisc = <&usbmisc 2>; | ||
| 196 | status = "disabled"; | 210 | status = "disabled"; |
| 197 | }; | 211 | }; |
| 198 | 212 | ||
| @@ -200,9 +214,18 @@ | |||
| 200 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; | 214 | compatible = "fsl,imx51-usb", "fsl,imx27-usb"; |
| 201 | reg = <0x73f80600 0x0200>; | 215 | reg = <0x73f80600 0x0200>; |
| 202 | interrupts = <17>; | 216 | interrupts = <17>; |
| 217 | clocks = <&clks 108>; | ||
| 218 | fsl,usbmisc = <&usbmisc 3>; | ||
| 203 | status = "disabled"; | 219 | status = "disabled"; |
| 204 | }; | 220 | }; |
| 205 | 221 | ||
| 222 | usbmisc: usbmisc@73f80800 { | ||
| 223 | #index-cells = <1>; | ||
| 224 | compatible = "fsl,imx51-usbmisc"; | ||
| 225 | reg = <0x73f80800 0x200>; | ||
| 226 | clocks = <&clks 108>; | ||
| 227 | }; | ||
| 228 | |||
| 206 | gpio1: gpio@73f84000 { | 229 | gpio1: gpio@73f84000 { |
| 207 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; | 230 | compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; |
| 208 | reg = <0x73f84000 0x4000>; | 231 | reg = <0x73f84000 0x4000>; |
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts new file mode 100644 index 000000000000..7d304d02ed38 --- /dev/null +++ b/arch/arm/boot/dts/imx53-m53evk.dts | |||
| @@ -0,0 +1,259 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Marek Vasut <marex@denx.de> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx53.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "DENX M53EVK"; | ||
| 17 | compatible = "denx,imx53-m53evk", "fsl,imx53"; | ||
| 18 | |||
| 19 | memory { | ||
| 20 | reg = <0x70000000 0x20000000>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | soc { | ||
| 24 | display@di1 { | ||
| 25 | compatible = "fsl,imx-parallel-display"; | ||
| 26 | crtcs = <&ipu 1>; | ||
| 27 | interface-pix-fmt = "bgr666"; | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_ipu_disp2_1>; | ||
| 30 | |||
| 31 | display-timings { | ||
| 32 | 800x480p60 { | ||
| 33 | native-mode; | ||
| 34 | clock-frequency = <31500000>; | ||
| 35 | hactive = <800>; | ||
| 36 | vactive = <480>; | ||
| 37 | hfront-porch = <40>; | ||
| 38 | hback-porch = <88>; | ||
| 39 | hsync-len = <128>; | ||
| 40 | vback-porch = <33>; | ||
| 41 | vfront-porch = <9>; | ||
| 42 | vsync-len = <3>; | ||
| 43 | vsync-active = <1>; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | |||
| 49 | backlight { | ||
| 50 | compatible = "pwm-backlight"; | ||
| 51 | pwms = <&pwm1 0 3000>; | ||
| 52 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
| 53 | default-brightness-level = <6>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | leds { | ||
| 57 | compatible = "gpio-leds"; | ||
| 58 | pinctrl-names = "default"; | ||
| 59 | pinctrl-0 = <&led_pin_gpio>; | ||
| 60 | |||
| 61 | user1 { | ||
| 62 | label = "user1"; | ||
| 63 | gpios = <&gpio2 8 0>; | ||
| 64 | linux,default-trigger = "heartbeat"; | ||
| 65 | }; | ||
| 66 | |||
| 67 | user2 { | ||
| 68 | label = "user2"; | ||
| 69 | gpios = <&gpio2 9 0>; | ||
| 70 | linux,default-trigger = "heartbeat"; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | |||
| 74 | regulators { | ||
| 75 | compatible = "simple-bus"; | ||
| 76 | |||
| 77 | reg_3p2v: 3p2v { | ||
| 78 | compatible = "regulator-fixed"; | ||
| 79 | regulator-name = "3P2V"; | ||
| 80 | regulator-min-microvolt = <3200000>; | ||
| 81 | regulator-max-microvolt = <3200000>; | ||
| 82 | regulator-always-on; | ||
| 83 | }; | ||
| 84 | }; | ||
| 85 | |||
| 86 | sound { | ||
| 87 | compatible = "fsl,imx53-m53evk-sgtl5000", | ||
| 88 | "fsl,imx-audio-sgtl5000"; | ||
| 89 | model = "imx53-m53evk-sgtl5000"; | ||
| 90 | ssi-controller = <&ssi2>; | ||
| 91 | audio-codec = <&sgtl5000>; | ||
| 92 | audio-routing = | ||
| 93 | "MIC_IN", "Mic Jack", | ||
| 94 | "Mic Jack", "Mic Bias", | ||
| 95 | "LINE_IN", "Line In Jack", | ||
| 96 | "Headphone Jack", "HP_OUT", | ||
| 97 | "Ext Spk", "LINE_OUT"; | ||
| 98 | mux-int-port = <2>; | ||
| 99 | mux-ext-port = <4>; | ||
| 100 | }; | ||
| 101 | }; | ||
| 102 | |||
| 103 | &audmux { | ||
| 104 | pinctrl-names = "default"; | ||
| 105 | pinctrl-0 = <&pinctrl_audmux_2>; | ||
| 106 | status = "okay"; | ||
| 107 | }; | ||
| 108 | |||
| 109 | &can1 { | ||
| 110 | pinctrl-names = "default"; | ||
| 111 | pinctrl-0 = <&pinctrl_can1_3>; | ||
| 112 | status = "okay"; | ||
| 113 | }; | ||
| 114 | |||
| 115 | &can2 { | ||
| 116 | pinctrl-names = "default"; | ||
| 117 | pinctrl-0 = <&pinctrl_can2_1>; | ||
| 118 | status = "okay"; | ||
| 119 | }; | ||
| 120 | |||
| 121 | &esdhc1 { | ||
| 122 | pinctrl-names = "default"; | ||
| 123 | pinctrl-0 = <&pinctrl_esdhc1_1>; | ||
| 124 | cd-gpios = <&gpio1 1 0>; | ||
| 125 | wp-gpios = <&gpio1 9 0>; | ||
| 126 | status = "okay"; | ||
| 127 | }; | ||
| 128 | |||
| 129 | &fec { | ||
| 130 | pinctrl-names = "default"; | ||
| 131 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 132 | phy-mode = "rmii"; | ||
| 133 | status = "okay"; | ||
| 134 | }; | ||
| 135 | |||
| 136 | &i2c1 { | ||
| 137 | pinctrl-names = "default"; | ||
| 138 | pinctrl-0 = <&pinctrl_i2c1_2>; | ||
| 139 | status = "okay"; | ||
| 140 | |||
| 141 | sgtl5000: codec@0a { | ||
| 142 | compatible = "fsl,sgtl5000"; | ||
| 143 | reg = <0x0a>; | ||
| 144 | VDDA-supply = <®_3p2v>; | ||
| 145 | VDDIO-supply = <®_3p2v>; | ||
| 146 | clocks = <&clks 150>; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | |||
| 150 | &i2c2 { | ||
| 151 | pinctrl-names = "default"; | ||
| 152 | pinctrl-0 = <&pinctrl_i2c2_2>; | ||
| 153 | clock-frequency = <400000>; | ||
| 154 | status = "okay"; | ||
| 155 | |||
| 156 | stmpe610@41 { | ||
| 157 | compatible = "st,stmpe610"; | ||
| 158 | #address-cells = <1>; | ||
| 159 | #size-cells = <0>; | ||
| 160 | reg = <0x41>; | ||
| 161 | id = <0>; | ||
| 162 | blocks = <0x5>; | ||
| 163 | interrupts = <6 0x0>; | ||
| 164 | interrupt-parent = <&gpio7>; | ||
| 165 | irq-trigger = <0x1>; | ||
| 166 | |||
| 167 | stmpe_touchscreen { | ||
| 168 | compatible = "stmpe,ts"; | ||
| 169 | reg = <0>; | ||
| 170 | ts,sample-time = <4>; | ||
| 171 | ts,mod-12b = <1>; | ||
| 172 | ts,ref-sel = <0>; | ||
| 173 | ts,adc-freq = <1>; | ||
| 174 | ts,ave-ctrl = <3>; | ||
| 175 | ts,touch-det-delay = <3>; | ||
| 176 | ts,settling = <4>; | ||
| 177 | ts,fraction-z = <7>; | ||
| 178 | ts,i-drive = <1>; | ||
| 179 | }; | ||
| 180 | }; | ||
| 181 | |||
| 182 | eeprom: eeprom@50 { | ||
| 183 | compatible = "atmel,24c128"; | ||
| 184 | reg = <0x50>; | ||
| 185 | pagesize = <32>; | ||
| 186 | }; | ||
| 187 | |||
| 188 | rtc: rtc@68 { | ||
| 189 | compatible = "stm,m41t62"; | ||
| 190 | reg = <0x68>; | ||
| 191 | }; | ||
| 192 | }; | ||
| 193 | |||
| 194 | &i2c3 { | ||
| 195 | pinctrl-names = "default"; | ||
| 196 | pinctrl-0 = <&pinctrl_i2c3_1>; | ||
| 197 | status = "okay"; | ||
| 198 | }; | ||
| 199 | |||
| 200 | &iomuxc { | ||
| 201 | pinctrl-names = "default"; | ||
| 202 | pinctrl-0 = <&pinctrl_hog>; | ||
| 203 | |||
| 204 | hog { | ||
| 205 | pinctrl_hog: hoggrp { | ||
| 206 | fsl,pins = < | ||
| 207 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 | ||
| 208 | MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 | ||
| 209 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 | ||
| 210 | MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 | ||
| 211 | |||
| 212 | >; | ||
| 213 | }; | ||
| 214 | |||
| 215 | led_pin_gpio: led_gpio@0 { | ||
| 216 | fsl,pins = < | ||
| 217 | MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 | ||
| 218 | MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000 | ||
| 219 | >; | ||
| 220 | }; | ||
| 221 | }; | ||
| 222 | }; | ||
| 223 | |||
| 224 | &nfc { | ||
| 225 | pinctrl-names = "default"; | ||
| 226 | pinctrl-0 = <&pinctrl_nand_1>; | ||
| 227 | nand-bus-width = <8>; | ||
| 228 | nand-ecc-mode = "hw"; | ||
| 229 | status = "okay"; | ||
| 230 | }; | ||
| 231 | |||
| 232 | &pwm1 { | ||
| 233 | pinctrl-names = "default"; | ||
| 234 | pinctrl-0 = <&pinctrl_pwm1_1>; | ||
| 235 | status = "okay"; | ||
| 236 | }; | ||
| 237 | |||
| 238 | &ssi2 { | ||
| 239 | fsl,mode = "i2s-slave"; | ||
| 240 | status = "okay"; | ||
| 241 | }; | ||
| 242 | |||
| 243 | &uart1 { | ||
| 244 | pinctrl-names = "default"; | ||
| 245 | pinctrl-0 = <&pinctrl_uart1_2>; | ||
| 246 | status = "okay"; | ||
| 247 | }; | ||
| 248 | |||
| 249 | &uart2 { | ||
| 250 | pinctrl-names = "default"; | ||
| 251 | pinctrl-0 = <&pinctrl_uart2_1>; | ||
| 252 | status = "okay"; | ||
| 253 | }; | ||
| 254 | |||
| 255 | &uart3 { | ||
| 256 | pinctrl-names = "default"; | ||
| 257 | pinctrl-0 = <&pinctrl_uart3_1>; | ||
| 258 | status = "okay"; | ||
| 259 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts index 445a01119cc5..aaa33bc99f78 100644 --- a/arch/arm/boot/dts/imx53-mba53.dts +++ b/arch/arm/boot/dts/imx53-mba53.dts | |||
| @@ -16,27 +16,81 @@ | |||
| 16 | / { | 16 | / { |
| 17 | model = "TQ MBa53 starter kit"; | 17 | model = "TQ MBa53 starter kit"; |
| 18 | compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; | 18 | compatible = "tq,mba53", "tq,tqma53", "fsl,imx53"; |
| 19 | |||
| 20 | reg_backlight: fixed@0 { | ||
| 21 | compatible = "regulator-fixed"; | ||
| 22 | regulator-name = "lcd-supply"; | ||
| 23 | gpio = <&gpio2 5 0>; | ||
| 24 | startup-delay-us = <5000>; | ||
| 25 | enable-active-low; | ||
| 26 | }; | ||
| 27 | |||
| 28 | backlight { | ||
| 29 | compatible = "pwm-backlight"; | ||
| 30 | pwms = <&pwm2 0 50000 0 0>; | ||
| 31 | brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>; | ||
| 32 | default-brightness-level = <10>; | ||
| 33 | enable-gpios = <&gpio7 7 0>; | ||
| 34 | power-supply = <®_backlight>; | ||
| 35 | }; | ||
| 36 | |||
| 37 | disp1: display@disp1 { | ||
| 38 | compatible = "fsl,imx-parallel-display"; | ||
| 39 | pinctrl-names = "default"; | ||
| 40 | pinctrl-0 = <&pinctrl_disp1_1>; | ||
| 41 | crtcs = <&ipu 1>; | ||
| 42 | interface-pix-fmt = "rgb24"; | ||
| 43 | status = "disabled"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | reg_3p2v: 3p2v { | ||
| 47 | compatible = "regulator-fixed"; | ||
| 48 | regulator-name = "3P2V"; | ||
| 49 | regulator-min-microvolt = <3200000>; | ||
| 50 | regulator-max-microvolt = <3200000>; | ||
| 51 | regulator-always-on; | ||
| 52 | }; | ||
| 53 | |||
| 54 | sound { | ||
| 55 | compatible = "tq,imx53-mba53-sgtl5000", | ||
| 56 | "fsl,imx-audio-sgtl5000"; | ||
| 57 | model = "imx53-mba53-sgtl5000"; | ||
| 58 | ssi-controller = <&ssi2>; | ||
| 59 | audio-codec = <&codec>; | ||
| 60 | audio-routing = | ||
| 61 | "MIC_IN", "Mic Jack", | ||
| 62 | "Mic Jack", "Mic Bias", | ||
| 63 | "Headphone Jack", "HP_OUT"; | ||
| 64 | mux-int-port = <2>; | ||
| 65 | mux-ext-port = <5>; | ||
| 66 | }; | ||
| 67 | }; | ||
| 68 | |||
| 69 | &ldb { | ||
| 70 | pinctrl-names = "default"; | ||
| 71 | pinctrl-0 = <&pinctrl_lvds1_1>; | ||
| 72 | status = "disabled"; | ||
| 19 | }; | 73 | }; |
| 20 | 74 | ||
| 21 | &iomuxc { | 75 | &iomuxc { |
| 22 | lvds1 { | 76 | lvds1 { |
| 23 | pinctrl_lvds1_1: lvds1-grp1 { | 77 | pinctrl_lvds1_1: lvds1-grp1 { |
| 24 | fsl,pins = < | 78 | fsl,pins = < |
| 25 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000 | 79 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 |
| 26 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000 | 80 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 |
| 27 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000 | 81 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 |
| 28 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000 | 82 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 |
| 29 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000 | 83 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 |
| 30 | >; | 84 | >; |
| 31 | }; | 85 | }; |
| 32 | 86 | ||
| 33 | pinctrl_lvds1_2: lvds1-grp2 { | 87 | pinctrl_lvds1_2: lvds1-grp2 { |
| 34 | fsl,pins = < | 88 | fsl,pins = < |
| 35 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000 | 89 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 |
| 36 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000 | 90 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 |
| 37 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000 | 91 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 |
| 38 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000 | 92 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 |
| 39 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000 | 93 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 |
| 40 | >; | 94 | >; |
| 41 | }; | 95 | }; |
| 42 | }; | 96 | }; |
| @@ -44,33 +98,44 @@ | |||
| 44 | disp1 { | 98 | disp1 { |
| 45 | pinctrl_disp1_1: disp1-grp1 { | 99 | pinctrl_disp1_1: disp1-grp1 { |
| 46 | fsl,pins = < | 100 | fsl,pins = < |
| 47 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */ | 101 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */ |
| 48 | MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */ | 102 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */ |
| 49 | MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */ | 103 | MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */ |
| 50 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000 | 104 | MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */ |
| 51 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000 | 105 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000 |
| 52 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000 | 106 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000 |
| 53 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000 | 107 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000 |
| 54 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000 | 108 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000 |
| 55 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000 | 109 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000 |
| 56 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000 | 110 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000 |
| 57 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000 | 111 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000 |
| 58 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000 | 112 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000 |
| 59 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000 | 113 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000 |
| 60 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000 | 114 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000 |
| 61 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000 | 115 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000 |
| 62 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000 | 116 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000 |
| 63 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000 | 117 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000 |
| 64 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000 | 118 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000 |
| 65 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000 | 119 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000 |
| 66 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000 | 120 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000 |
| 67 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000 | 121 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000 |
| 68 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000 | 122 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000 |
| 69 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000 | 123 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000 |
| 70 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000 | 124 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000 |
| 71 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000 | 125 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000 |
| 72 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000 | 126 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000 |
| 73 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000 | 127 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000 |
| 128 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000 | ||
| 129 | >; | ||
| 130 | }; | ||
| 131 | }; | ||
| 132 | |||
| 133 | tve { | ||
| 134 | pinctrl_vga_sync_1: vgasync-grp1 { | ||
| 135 | fsl,pins = < | ||
| 136 | /* VGA_VSYNC, HSYNC with max drive strength */ | ||
| 137 | MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6 | ||
| 138 | MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6 | ||
| 74 | >; | 139 | >; |
| 75 | }; | 140 | }; |
| 76 | }; | 141 | }; |
| @@ -80,16 +145,27 @@ | |||
| 80 | status = "okay"; | 145 | status = "okay"; |
| 81 | }; | 146 | }; |
| 82 | 147 | ||
| 148 | &audmux { | ||
| 149 | status = "okay"; | ||
| 150 | pinctrl-names = "default"; | ||
| 151 | pinctrl-0 = <&pinctrl_audmux_1>; | ||
| 152 | }; | ||
| 153 | |||
| 83 | &i2c2 { | 154 | &i2c2 { |
| 84 | codec: sgtl5000@a { | 155 | codec: sgtl5000@a { |
| 85 | compatible = "fsl,sgtl5000"; | 156 | compatible = "fsl,sgtl5000"; |
| 86 | reg = <0x0a>; | 157 | reg = <0x0a>; |
| 158 | clocks = <&clks 150>; | ||
| 159 | VDDA-supply = <®_3p2v>; | ||
| 160 | VDDIO-supply = <®_3p2v>; | ||
| 87 | }; | 161 | }; |
| 88 | 162 | ||
| 89 | expander: pca9554@20 { | 163 | expander: pca9554@20 { |
| 90 | compatible = "pca9554"; | 164 | compatible = "pca9554"; |
| 91 | reg = <0x20>; | 165 | reg = <0x20>; |
| 92 | interrupts = <109>; | 166 | interrupts = <109>; |
| 167 | #gpio-cells = <2>; | ||
| 168 | gpio-controller; | ||
| 93 | }; | 169 | }; |
| 94 | 170 | ||
| 95 | sensor2: lm75@49 { | 171 | sensor2: lm75@49 { |
| @@ -99,6 +175,7 @@ | |||
| 99 | }; | 175 | }; |
| 100 | 176 | ||
| 101 | &fec { | 177 | &fec { |
| 178 | phy-reset-gpios = <&gpio7 6 0>; | ||
| 102 | status = "okay"; | 179 | status = "okay"; |
| 103 | }; | 180 | }; |
| 104 | 181 | ||
| @@ -114,10 +191,24 @@ | |||
| 114 | status = "okay"; | 191 | status = "okay"; |
| 115 | }; | 192 | }; |
| 116 | 193 | ||
| 194 | &usbotg { | ||
| 195 | dr_mode = "host"; | ||
| 196 | status = "okay"; | ||
| 197 | }; | ||
| 198 | |||
| 199 | &usbh1 { | ||
| 200 | status = "okay"; | ||
| 201 | }; | ||
| 202 | |||
| 117 | &uart1 { | 203 | &uart1 { |
| 118 | status = "okay"; | 204 | status = "okay"; |
| 119 | }; | 205 | }; |
| 120 | 206 | ||
| 207 | &ssi2 { | ||
| 208 | fsl,mode = "i2s-slave"; | ||
| 209 | status = "okay"; | ||
| 210 | }; | ||
| 211 | |||
| 121 | &uart2 { | 212 | &uart2 { |
| 122 | status = "okay"; | 213 | status = "okay"; |
| 123 | }; | 214 | }; |
| @@ -133,3 +224,13 @@ | |||
| 133 | &i2c3 { | 224 | &i2c3 { |
| 134 | status = "okay"; | 225 | status = "okay"; |
| 135 | }; | 226 | }; |
| 227 | |||
| 228 | &tve { | ||
| 229 | pinctrl-names = "default"; | ||
| 230 | pinctrl-0 = <&pinctrl_vga_sync_1>; | ||
| 231 | ddc = <&i2c3>; | ||
| 232 | fsl,tve-mode = "vga"; | ||
| 233 | fsl,hsync-pin = <4>; | ||
| 234 | fsl,vsync-pin = <6>; | ||
| 235 | status = "okay"; | ||
| 236 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts index 8f0e9ae0e3e6..512a1f608253 100644 --- a/arch/arm/boot/dts/imx53-qsb.dts +++ b/arch/arm/boot/dts/imx53-qsb.dts | |||
| @@ -21,6 +21,33 @@ | |||
| 21 | reg = <0x70000000 0x40000000>; | 21 | reg = <0x70000000 0x40000000>; |
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | display@di0 { | ||
| 25 | compatible = "fsl,imx-parallel-display"; | ||
| 26 | crtcs = <&ipu 0>; | ||
| 27 | interface-pix-fmt = "rgb565"; | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | pinctrl-0 = <&pinctrl_ipu_disp0_1>; | ||
| 30 | status = "disabled"; | ||
| 31 | display-timings { | ||
| 32 | claawvga { | ||
| 33 | native-mode; | ||
| 34 | clock-frequency = <27000000>; | ||
| 35 | hactive = <800>; | ||
| 36 | vactive = <480>; | ||
| 37 | hback-porch = <40>; | ||
| 38 | hfront-porch = <60>; | ||
| 39 | vback-porch = <10>; | ||
| 40 | vfront-porch = <10>; | ||
| 41 | hsync-len = <20>; | ||
| 42 | vsync-len = <10>; | ||
| 43 | hsync-active = <0>; | ||
| 44 | vsync-active = <0>; | ||
| 45 | de-active = <1>; | ||
| 46 | pixelclk-active = <0>; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 24 | gpio-keys { | 51 | gpio-keys { |
| 25 | compatible = "gpio-keys"; | 52 | compatible = "gpio-keys"; |
| 26 | 53 | ||
| @@ -147,6 +174,7 @@ | |||
| 147 | reg = <0x0a>; | 174 | reg = <0x0a>; |
| 148 | VDDA-supply = <®_3p2v>; | 175 | VDDA-supply = <®_3p2v>; |
| 149 | VDDIO-supply = <®_3p2v>; | 176 | VDDIO-supply = <®_3p2v>; |
| 177 | clocks = <&clks 150>; | ||
| 150 | }; | 178 | }; |
| 151 | }; | 179 | }; |
| 152 | 180 | ||
| @@ -268,3 +296,11 @@ | |||
| 268 | phy-reset-gpios = <&gpio7 6 0>; | 296 | phy-reset-gpios = <&gpio7 6 0>; |
| 269 | status = "okay"; | 297 | status = "okay"; |
| 270 | }; | 298 | }; |
| 299 | |||
| 300 | &usbh1 { | ||
| 301 | status = "okay"; | ||
| 302 | }; | ||
| 303 | |||
| 304 | &usbotg { | ||
| 305 | status = "okay"; | ||
| 306 | }; | ||
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index 38bed3ed7c1a..abd72af545bf 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi | |||
| @@ -35,7 +35,9 @@ | |||
| 35 | 35 | ||
| 36 | &esdhc2 { | 36 | &esdhc2 { |
| 37 | pinctrl-names = "default"; | 37 | pinctrl-names = "default"; |
| 38 | pinctrl-0 = <&pinctrl_esdhc2_1>; | 38 | pinctrl-0 = <&pinctrl_esdhc2_1>, |
| 39 | <&pinctrl_tqma53_esdhc2_2>; | ||
| 40 | vmmc-supply = <®_3p3v>; | ||
| 39 | wp-gpios = <&gpio1 2 0>; | 41 | wp-gpios = <&gpio1 2 0>; |
| 40 | cd-gpios = <&gpio1 4 0>; | 42 | cd-gpios = <&gpio1 4 0>; |
| 41 | status = "disabled"; | 43 | status = "disabled"; |
| @@ -69,14 +71,22 @@ | |||
| 69 | pinctrl-names = "default"; | 71 | pinctrl-names = "default"; |
| 70 | pinctrl-0 = <&pinctrl_hog>; | 72 | pinctrl-0 = <&pinctrl_hog>; |
| 71 | 73 | ||
| 74 | esdhc2_2 { | ||
| 75 | pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 { | ||
| 76 | fsl,pins = < | ||
| 77 | MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */ | ||
| 78 | MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */ | ||
| 79 | >; | ||
| 80 | }; | ||
| 81 | }; | ||
| 82 | |||
| 72 | i2s { | 83 | i2s { |
| 73 | pinctrl_i2s_1: i2s-grp1 { | 84 | pinctrl_i2s_1: i2s-grp1 { |
| 74 | fsl,pins = < | 85 | fsl,pins = < |
| 75 | MX53_PAD_GPIO_19__GPIO4_5 0x10000 /* I2S_MCLK */ | 86 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 /* I2S_SCLK */ |
| 76 | MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x10000 /* I2S_SCLK */ | 87 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 /* I2S_DOUT */ |
| 77 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x10000 /* I2S_DOUT */ | 88 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */ |
| 78 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */ | 89 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 /* I2S_DIN */ |
| 79 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x10000 /* I2S_DIN */ | ||
| 80 | >; | 90 | >; |
| 81 | }; | 91 | }; |
| 82 | }; | 92 | }; |
| @@ -84,16 +94,17 @@ | |||
| 84 | hog { | 94 | hog { |
| 85 | pinctrl_hog: hoggrp { | 95 | pinctrl_hog: hoggrp { |
| 86 | fsl,pins = < | 96 | fsl,pins = < |
| 87 | MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x10000 /* VSYNC */ | 97 | MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */ |
| 88 | MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */ | 98 | MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */ |
| 89 | MX53_PAD_PATA_DA_1__GPIO7_7 0x10000 /* LCD_BLT_EN */ | 99 | MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */ |
| 90 | MX53_PAD_PATA_DA_2__GPIO7_8 0x10000 /* LCD_RESET */ | 100 | MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */ |
| 91 | MX53_PAD_PATA_DATA5__GPIO2_5 0x10000 /* LCD_POWER */ | 101 | MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */ |
| 92 | MX53_PAD_PATA_DATA6__GPIO2_6 0x10000 /* PMIC_INT */ | 102 | MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */ |
| 93 | MX53_PAD_PATA_DATA14__GPIO2_14 0x10000 /* CSI_RST */ | 103 | MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */ |
| 94 | MX53_PAD_PATA_DATA15__GPIO2_15 0x10000 /* CSI_PWDN */ | 104 | MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */ |
| 95 | MX53_PAD_GPIO_0__GPIO1_0 0x10000 /* SYSTEM_DOWN */ | 105 | MX53_PAD_GPIO_3__GPIO1_3 0x80000000 |
| 96 | MX53_PAD_GPIO_3__GPIO1_3 0x10000 | 106 | MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */ |
| 107 | MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */ | ||
| 97 | >; | 108 | >; |
| 98 | }; | 109 | }; |
| 99 | }; | 110 | }; |
| @@ -149,7 +160,7 @@ | |||
| 149 | reg = <0x8>; | 160 | reg = <0x8>; |
| 150 | fsl,mc13xxx-uses-rtc; | 161 | fsl,mc13xxx-uses-rtc; |
| 151 | interrupt-parent = <&gpio2>; | 162 | interrupt-parent = <&gpio2>; |
| 152 | interrupts = <6 8>; /* PDATA_DATA6, low active */ | 163 | interrupts = <6 4>; /* PATA_DATA6, active high */ |
| 153 | }; | 164 | }; |
| 154 | 165 | ||
| 155 | sensor1: lm75@48 { | 166 | sensor1: lm75@48 { |
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi new file mode 100644 index 000000000000..f494766700a3 --- /dev/null +++ b/arch/arm/boot/dts/imx53-tx53.dtsi | |||
| @@ -0,0 +1,122 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /include/ "imx53.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Ka-Ro TX53"; | ||
| 16 | compatible = "karo,tx53", "fsl,imx53"; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x70000000 0x40000000>; /* Up to 1GiB */ | ||
| 20 | }; | ||
| 21 | |||
| 22 | regulators { | ||
| 23 | compatible = "simple-bus"; | ||
| 24 | |||
| 25 | reg_3p3v: 3p3v { | ||
| 26 | compatible = "regulator-fixed"; | ||
| 27 | regulator-name = "3P3V"; | ||
| 28 | regulator-min-microvolt = <3300000>; | ||
| 29 | regulator-max-microvolt = <3300000>; | ||
| 30 | regulator-always-on; | ||
| 31 | }; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | &can1 { | ||
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&pinctrl_can1_2>; | ||
| 38 | status = "disabled"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | &can2 { | ||
| 42 | pinctrl-names = "default"; | ||
| 43 | pinctrl-0 = <&pinctrl_can2_1>; | ||
| 44 | status = "disabled"; | ||
| 45 | }; | ||
| 46 | |||
| 47 | &ecspi1 { | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | pinctrl-0 = <&pinctrl_ecspi1_2>; | ||
| 50 | status = "disabled"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | &esdhc1 { | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | pinctrl-0 = <&pinctrl_esdhc1_2>; | ||
| 56 | status = "disabled"; | ||
| 57 | }; | ||
| 58 | |||
| 59 | &esdhc2 { | ||
| 60 | pinctrl-names = "default"; | ||
| 61 | pinctrl-0 = <&pinctrl_esdhc2_1>; | ||
| 62 | status = "disabled"; | ||
| 63 | }; | ||
| 64 | |||
| 65 | &fec { | ||
| 66 | pinctrl-names = "default"; | ||
| 67 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 68 | phy-mode = "rmii"; | ||
| 69 | status = "disabled"; | ||
| 70 | }; | ||
| 71 | |||
| 72 | &i2c3 { | ||
| 73 | pinctrl-names = "default"; | ||
| 74 | pinctrl-0 = <&pinctrl_i2c3_2>; | ||
| 75 | status = "disabled"; | ||
| 76 | }; | ||
| 77 | |||
| 78 | &owire { | ||
| 79 | pinctrl-names = "default"; | ||
| 80 | pinctrl-0 = <&pinctrl_owire_1>; | ||
| 81 | status = "disabled"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | &pwm2 { | ||
| 85 | pinctrl-names = "default"; | ||
| 86 | pinctrl-0 = <&pinctrl_pwm2_1>; | ||
| 87 | status = "disabled"; | ||
| 88 | }; | ||
| 89 | |||
| 90 | &ssi1 { | ||
| 91 | pinctrl-names = "default"; | ||
| 92 | pinctrl-0 = <&pinctrl_audmux_1>; | ||
| 93 | status = "disabled"; | ||
| 94 | }; | ||
| 95 | |||
| 96 | &ssi2 { | ||
| 97 | pinctrl-names = "default"; | ||
| 98 | pinctrl-0 = <&pinctrl_audmux_2>; | ||
| 99 | status = "disabled"; | ||
| 100 | }; | ||
| 101 | |||
| 102 | &uart1 { | ||
| 103 | pinctrl-names = "default"; | ||
| 104 | pinctrl-0 = <&pinctrl_uart1_2>, | ||
| 105 | <&pinctrl_uart1_3>; | ||
| 106 | fsl,uart-has-rtscts; | ||
| 107 | status = "disabled"; | ||
| 108 | }; | ||
| 109 | |||
| 110 | &uart2 { | ||
| 111 | pinctrl-names = "default"; | ||
| 112 | pinctrl-0 = <&pinctrl_uart2_2>; | ||
| 113 | fsl,uart-has-rtscts; | ||
| 114 | status = "disabled"; | ||
| 115 | }; | ||
| 116 | |||
| 117 | &uart3 { | ||
| 118 | pinctrl-names = "default"; | ||
| 119 | pinctrl-0 = <&pinctrl_uart3_1>; | ||
| 120 | fsl,uart-has-rtscts; | ||
| 121 | status = "disabled"; | ||
| 122 | }; | ||
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index eb83aa039b8b..3895fbba8fce 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -27,6 +27,9 @@ | |||
| 27 | gpio4 = &gpio5; | 27 | gpio4 = &gpio5; |
| 28 | gpio5 = &gpio6; | 28 | gpio5 = &gpio6; |
| 29 | gpio6 = &gpio7; | 29 | gpio6 = &gpio7; |
| 30 | i2c0 = &i2c1; | ||
| 31 | i2c1 = &i2c2; | ||
| 32 | i2c2 = &i2c3; | ||
| 30 | }; | 33 | }; |
| 31 | 34 | ||
| 32 | tzic: tz-interrupt-controller@0fffc000 { | 35 | tzic: tz-interrupt-controller@0fffc000 { |
| @@ -163,10 +166,27 @@ | |||
| 163 | }; | 166 | }; |
| 164 | }; | 167 | }; |
| 165 | 168 | ||
| 169 | usbphy0: usbphy@0 { | ||
| 170 | compatible = "usb-nop-xceiv"; | ||
| 171 | clocks = <&clks 124>; | ||
| 172 | clock-names = "main_clk"; | ||
| 173 | status = "okay"; | ||
| 174 | }; | ||
| 175 | |||
| 176 | usbphy1: usbphy@1 { | ||
| 177 | compatible = "usb-nop-xceiv"; | ||
| 178 | clocks = <&clks 125>; | ||
| 179 | clock-names = "main_clk"; | ||
| 180 | status = "okay"; | ||
| 181 | }; | ||
| 182 | |||
| 166 | usbotg: usb@53f80000 { | 183 | usbotg: usb@53f80000 { |
| 167 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | 184 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 168 | reg = <0x53f80000 0x0200>; | 185 | reg = <0x53f80000 0x0200>; |
| 169 | interrupts = <18>; | 186 | interrupts = <18>; |
| 187 | clocks = <&clks 108>; | ||
| 188 | fsl,usbmisc = <&usbmisc 0>; | ||
| 189 | fsl,usbphy = <&usbphy0>; | ||
| 170 | status = "disabled"; | 190 | status = "disabled"; |
| 171 | }; | 191 | }; |
| 172 | 192 | ||
| @@ -174,6 +194,9 @@ | |||
| 174 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | 194 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 175 | reg = <0x53f80200 0x0200>; | 195 | reg = <0x53f80200 0x0200>; |
| 176 | interrupts = <14>; | 196 | interrupts = <14>; |
| 197 | clocks = <&clks 108>; | ||
| 198 | fsl,usbmisc = <&usbmisc 1>; | ||
| 199 | fsl,usbphy = <&usbphy1>; | ||
| 177 | status = "disabled"; | 200 | status = "disabled"; |
| 178 | }; | 201 | }; |
| 179 | 202 | ||
| @@ -181,6 +204,8 @@ | |||
| 181 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | 204 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 182 | reg = <0x53f80400 0x0200>; | 205 | reg = <0x53f80400 0x0200>; |
| 183 | interrupts = <16>; | 206 | interrupts = <16>; |
| 207 | clocks = <&clks 108>; | ||
| 208 | fsl,usbmisc = <&usbmisc 2>; | ||
| 184 | status = "disabled"; | 209 | status = "disabled"; |
| 185 | }; | 210 | }; |
| 186 | 211 | ||
| @@ -188,9 +213,18 @@ | |||
| 188 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; | 213 | compatible = "fsl,imx53-usb", "fsl,imx27-usb"; |
| 189 | reg = <0x53f80600 0x0200>; | 214 | reg = <0x53f80600 0x0200>; |
| 190 | interrupts = <17>; | 215 | interrupts = <17>; |
| 216 | clocks = <&clks 108>; | ||
| 217 | fsl,usbmisc = <&usbmisc 3>; | ||
| 191 | status = "disabled"; | 218 | status = "disabled"; |
| 192 | }; | 219 | }; |
| 193 | 220 | ||
| 221 | usbmisc: usbmisc@53f80800 { | ||
| 222 | #index-cells = <1>; | ||
| 223 | compatible = "fsl,imx53-usbmisc"; | ||
| 224 | reg = <0x53f80800 0x200>; | ||
| 225 | clocks = <&clks 108>; | ||
| 226 | }; | ||
| 227 | |||
| 194 | gpio1: gpio@53f84000 { | 228 | gpio1: gpio@53f84000 { |
| 195 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; | 229 | compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; |
| 196 | reg = <0x53f84000 0x4000>; | 230 | reg = <0x53f84000 0x4000>; |
| @@ -267,6 +301,24 @@ | |||
| 267 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 | 301 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 |
| 268 | >; | 302 | >; |
| 269 | }; | 303 | }; |
| 304 | |||
| 305 | pinctrl_audmux_2: audmuxgrp-2 { | ||
| 306 | fsl,pins = < | ||
| 307 | MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000 | ||
| 308 | MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000 | ||
| 309 | MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000 | ||
| 310 | MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000 | ||
| 311 | >; | ||
| 312 | }; | ||
| 313 | |||
| 314 | pinctrl_audmux_3: audmuxgrp-3 { | ||
| 315 | fsl,pins = < | ||
| 316 | MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000 | ||
| 317 | MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000 | ||
| 318 | MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000 | ||
| 319 | MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000 | ||
| 320 | >; | ||
| 321 | }; | ||
| 270 | }; | 322 | }; |
| 271 | 323 | ||
| 272 | fec { | 324 | fec { |
| @@ -284,6 +336,29 @@ | |||
| 284 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | 336 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 |
| 285 | >; | 337 | >; |
| 286 | }; | 338 | }; |
| 339 | |||
| 340 | pinctrl_fec_2: fecgrp-2 { | ||
| 341 | fsl,pins = < | ||
| 342 | MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 | ||
| 343 | MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 | ||
| 344 | MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 | ||
| 345 | MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 | ||
| 346 | MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 | ||
| 347 | MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 | ||
| 348 | MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 | ||
| 349 | MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 | ||
| 350 | MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 | ||
| 351 | MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 | ||
| 352 | MX53_PAD_KEY_ROW1__FEC_COL 0x80000000 | ||
| 353 | MX53_PAD_KEY_COL3__FEC_CRS 0x80000000 | ||
| 354 | MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000 | ||
| 355 | MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000 | ||
| 356 | MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000 | ||
| 357 | MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000 | ||
| 358 | MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000 | ||
| 359 | MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000 | ||
| 360 | >; | ||
| 361 | }; | ||
| 287 | }; | 362 | }; |
| 288 | 363 | ||
| 289 | csi { | 364 | csi { |
| @@ -312,6 +387,22 @@ | |||
| 312 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 | 387 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 |
| 313 | >; | 388 | >; |
| 314 | }; | 389 | }; |
| 390 | |||
| 391 | pinctrl_csi_2: csigrp-2 { | ||
| 392 | fsl,pins = < | ||
| 393 | MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 | ||
| 394 | MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 | ||
| 395 | MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 | ||
| 396 | MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 | ||
| 397 | MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 | ||
| 398 | MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 | ||
| 399 | MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 | ||
| 400 | MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 | ||
| 401 | MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 | ||
| 402 | MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 | ||
| 403 | MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 | ||
| 404 | >; | ||
| 405 | }; | ||
| 315 | }; | 406 | }; |
| 316 | 407 | ||
| 317 | cspi { | 408 | cspi { |
| @@ -322,6 +413,14 @@ | |||
| 322 | MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 | 413 | MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 |
| 323 | >; | 414 | >; |
| 324 | }; | 415 | }; |
| 416 | |||
| 417 | pinctrl_cspi_2: cspigrp-2 { | ||
| 418 | fsl,pins = < | ||
| 419 | MX53_PAD_EIM_D22__CSPI_MISO 0x1d5 | ||
| 420 | MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5 | ||
| 421 | MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5 | ||
| 422 | >; | ||
| 423 | }; | ||
| 325 | }; | 424 | }; |
| 326 | 425 | ||
| 327 | ecspi1 { | 426 | ecspi1 { |
| @@ -332,6 +431,27 @@ | |||
| 332 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | 431 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 |
| 333 | >; | 432 | >; |
| 334 | }; | 433 | }; |
| 434 | |||
| 435 | pinctrl_ecspi1_2: ecspi1grp-2 { | ||
| 436 | fsl,pins = < | ||
| 437 | MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000 | ||
| 438 | MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000 | ||
| 439 | MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 | ||
| 440 | MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 | ||
| 441 | MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 | ||
| 442 | MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000 | ||
| 443 | >; | ||
| 444 | }; | ||
| 445 | }; | ||
| 446 | |||
| 447 | ecspi2 { | ||
| 448 | pinctrl_ecspi2_1: ecspi2grp-1 { | ||
| 449 | fsl,pins = < | ||
| 450 | MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000 | ||
| 451 | MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000 | ||
| 452 | MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000 | ||
| 453 | >; | ||
| 454 | }; | ||
| 335 | }; | 455 | }; |
| 336 | 456 | ||
| 337 | esdhc1 { | 457 | esdhc1 { |
| @@ -406,6 +526,13 @@ | |||
| 406 | MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 | 526 | MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 |
| 407 | >; | 527 | >; |
| 408 | }; | 528 | }; |
| 529 | |||
| 530 | pinctrl_can1_3: can1grp-3 { | ||
| 531 | fsl,pins = < | ||
| 532 | MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000 | ||
| 533 | MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000 | ||
| 534 | >; | ||
| 535 | }; | ||
| 409 | }; | 536 | }; |
| 410 | 537 | ||
| 411 | can2 { | 538 | can2 { |
| @@ -424,6 +551,13 @@ | |||
| 424 | MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 | 551 | MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 |
| 425 | >; | 552 | >; |
| 426 | }; | 553 | }; |
| 554 | |||
| 555 | pinctrl_i2c1_2: i2c1grp-2 { | ||
| 556 | fsl,pins = < | ||
| 557 | MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000 | ||
| 558 | MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000 | ||
| 559 | >; | ||
| 560 | }; | ||
| 427 | }; | 561 | }; |
| 428 | 562 | ||
| 429 | i2c2 { | 563 | i2c2 { |
| @@ -433,6 +567,13 @@ | |||
| 433 | MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 | 567 | MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 |
| 434 | >; | 568 | >; |
| 435 | }; | 569 | }; |
| 570 | |||
| 571 | pinctrl_i2c2_2: i2c2grp-2 { | ||
| 572 | fsl,pins = < | ||
| 573 | MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000 | ||
| 574 | MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000 | ||
| 575 | >; | ||
| 576 | }; | ||
| 436 | }; | 577 | }; |
| 437 | 578 | ||
| 438 | i2c3 { | 579 | i2c3 { |
| @@ -444,6 +585,119 @@ | |||
| 444 | }; | 585 | }; |
| 445 | }; | 586 | }; |
| 446 | 587 | ||
| 588 | ipu_disp0 { | ||
| 589 | pinctrl_ipu_disp0_1: ipudisp0grp-1 { | ||
| 590 | fsl,pins = < | ||
| 591 | MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 | ||
| 592 | MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 | ||
| 593 | MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 | ||
| 594 | MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 | ||
| 595 | MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 | ||
| 596 | MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 | ||
| 597 | MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 | ||
| 598 | MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 | ||
| 599 | MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 | ||
| 600 | MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 | ||
| 601 | MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 | ||
| 602 | MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 | ||
| 603 | MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 | ||
| 604 | MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 | ||
| 605 | MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 | ||
| 606 | MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 | ||
| 607 | MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 | ||
| 608 | MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 | ||
| 609 | MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 | ||
| 610 | MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 | ||
| 611 | MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 | ||
| 612 | MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 | ||
| 613 | MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 | ||
| 614 | MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 | ||
| 615 | MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 | ||
| 616 | MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 | ||
| 617 | MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 | ||
| 618 | MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 | ||
| 619 | >; | ||
| 620 | }; | ||
| 621 | }; | ||
| 622 | |||
| 623 | ipu_disp1 { | ||
| 624 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | ||
| 625 | fsl,pins = < | ||
| 626 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 | ||
| 627 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 | ||
| 628 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 | ||
| 629 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 | ||
| 630 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 | ||
| 631 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 | ||
| 632 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 | ||
| 633 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 | ||
| 634 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 | ||
| 635 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 | ||
| 636 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 | ||
| 637 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 | ||
| 638 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 | ||
| 639 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 | ||
| 640 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 | ||
| 641 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 | ||
| 642 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 | ||
| 643 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 | ||
| 644 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 | ||
| 645 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 | ||
| 646 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 | ||
| 647 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 | ||
| 648 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 | ||
| 649 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 | ||
| 650 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 | ||
| 651 | MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 | ||
| 652 | MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 | ||
| 653 | MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 | ||
| 654 | MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 | ||
| 655 | MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 | ||
| 656 | MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 | ||
| 657 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 | ||
| 658 | >; | ||
| 659 | }; | ||
| 660 | }; | ||
| 661 | |||
| 662 | ipu_disp2 { | ||
| 663 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | ||
| 664 | fsl,pins = < | ||
| 665 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 | ||
| 666 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 | ||
| 667 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 | ||
| 668 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 | ||
| 669 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 | ||
| 670 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 | ||
| 671 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 | ||
| 672 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 | ||
| 673 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 | ||
| 674 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 | ||
| 675 | >; | ||
| 676 | }; | ||
| 677 | }; | ||
| 678 | |||
| 679 | nand { | ||
| 680 | pinctrl_nand_1: nandgrp-1 { | ||
| 681 | fsl,pins = < | ||
| 682 | MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 | ||
| 683 | MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 | ||
| 684 | MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 | ||
| 685 | MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 | ||
| 686 | MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 | ||
| 687 | MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 | ||
| 688 | MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 | ||
| 689 | MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 | ||
| 690 | MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 | ||
| 691 | MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 | ||
| 692 | MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 | ||
| 693 | MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 | ||
| 694 | MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 | ||
| 695 | MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 | ||
| 696 | MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 | ||
| 697 | >; | ||
| 698 | }; | ||
| 699 | }; | ||
| 700 | |||
| 447 | owire { | 701 | owire { |
| 448 | pinctrl_owire_1: owiregrp-1 { | 702 | pinctrl_owire_1: owiregrp-1 { |
| 449 | fsl,pins = < | 703 | fsl,pins = < |
| @@ -452,6 +706,22 @@ | |||
| 452 | }; | 706 | }; |
| 453 | }; | 707 | }; |
| 454 | 708 | ||
| 709 | pwm1 { | ||
| 710 | pinctrl_pwm1_1: pwm1grp-1 { | ||
| 711 | fsl,pins = < | ||
| 712 | MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 | ||
| 713 | >; | ||
| 714 | }; | ||
| 715 | }; | ||
| 716 | |||
| 717 | pwm2 { | ||
| 718 | pinctrl_pwm2_1: pwm2grp-1 { | ||
| 719 | fsl,pins = < | ||
| 720 | MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 | ||
| 721 | >; | ||
| 722 | }; | ||
| 723 | }; | ||
| 724 | |||
| 455 | uart1 { | 725 | uart1 { |
| 456 | pinctrl_uart1_1: uart1grp-1 { | 726 | pinctrl_uart1_1: uart1grp-1 { |
| 457 | fsl,pins = < | 727 | fsl,pins = < |
| @@ -466,6 +736,13 @@ | |||
| 466 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5 | 736 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5 |
| 467 | >; | 737 | >; |
| 468 | }; | 738 | }; |
| 739 | |||
| 740 | pinctrl_uart1_3: uart1grp-3 { | ||
| 741 | fsl,pins = < | ||
| 742 | MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5 | ||
| 743 | MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5 | ||
| 744 | >; | ||
| 745 | }; | ||
| 469 | }; | 746 | }; |
| 470 | 747 | ||
| 471 | uart2 { | 748 | uart2 { |
| @@ -475,6 +752,15 @@ | |||
| 475 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 | 752 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 |
| 476 | >; | 753 | >; |
| 477 | }; | 754 | }; |
| 755 | |||
| 756 | pinctrl_uart2_2: uart2grp-2 { | ||
| 757 | fsl,pins = < | ||
| 758 | MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 | ||
| 759 | MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 | ||
| 760 | MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5 | ||
| 761 | MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5 | ||
| 762 | >; | ||
| 763 | }; | ||
| 478 | }; | 764 | }; |
| 479 | 765 | ||
| 480 | uart3 { | 766 | uart3 { |
| @@ -513,7 +799,6 @@ | |||
| 513 | >; | 799 | >; |
| 514 | }; | 800 | }; |
| 515 | }; | 801 | }; |
| 516 | |||
| 517 | }; | 802 | }; |
| 518 | 803 | ||
| 519 | gpr: iomuxc-gpr@53fa8000 { | 804 | gpr: iomuxc-gpr@53fa8000 { |
| @@ -781,6 +1066,16 @@ | |||
| 781 | clock-names = "ipg", "ahb", "ptp"; | 1066 | clock-names = "ipg", "ahb", "ptp"; |
| 782 | status = "disabled"; | 1067 | status = "disabled"; |
| 783 | }; | 1068 | }; |
| 1069 | |||
| 1070 | tve: tve@63ff0000 { | ||
| 1071 | compatible = "fsl,imx53-tve"; | ||
| 1072 | reg = <0x63ff0000 0x1000>; | ||
| 1073 | interrupts = <92>; | ||
| 1074 | clocks = <&clks 69>, <&clks 116>; | ||
| 1075 | clock-names = "tve", "di_sel"; | ||
| 1076 | crtcs = <&ipu 1>; | ||
| 1077 | status = "disabled"; | ||
| 1078 | }; | ||
| 784 | }; | 1079 | }; |
| 785 | }; | 1080 | }; |
| 786 | }; | 1081 | }; |
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts index 7adcec360213..95da71185a4a 100644 --- a/arch/arm/boot/dts/imx6dl-sabreauto.dts +++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts | |||
| @@ -28,4 +28,12 @@ | |||
| 28 | >; | 28 | >; |
| 29 | }; | 29 | }; |
| 30 | }; | 30 | }; |
| 31 | |||
| 32 | ecspi1 { | ||
| 33 | pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { | ||
| 34 | fsl,pins = < | ||
| 35 | MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000 | ||
| 36 | >; | ||
| 37 | }; | ||
| 38 | }; | ||
| 31 | }; | 39 | }; |
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts index 7efb05db4783..8989df2b89e5 100644 --- a/arch/arm/boot/dts/imx6dl-sabresd.dts +++ b/arch/arm/boot/dts/imx6dl-sabresd.dts | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 | 29 | MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 |
| 30 | MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 | 30 | MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 |
| 31 | MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 | 31 | MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 |
| 32 | MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0 | ||
| 32 | >; | 33 | >; |
| 33 | }; | 34 | }; |
| 34 | }; | 35 | }; |
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 5bcdf3a90bb3..2b3ecd679350 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi | |||
| @@ -18,12 +18,14 @@ | |||
| 18 | 18 | ||
| 19 | cpu@0 { | 19 | cpu@0 { |
| 20 | compatible = "arm,cortex-a9"; | 20 | compatible = "arm,cortex-a9"; |
| 21 | device_type = "cpu"; | ||
| 21 | reg = <0>; | 22 | reg = <0>; |
| 22 | next-level-cache = <&L2>; | 23 | next-level-cache = <&L2>; |
| 23 | }; | 24 | }; |
| 24 | 25 | ||
| 25 | cpu@1 { | 26 | cpu@1 { |
| 26 | compatible = "arm,cortex-a9"; | 27 | compatible = "arm,cortex-a9"; |
| 28 | device_type = "cpu"; | ||
| 27 | reg = <1>; | 29 | reg = <1>; |
| 28 | next-level-cache = <&L2>; | 30 | next-level-cache = <&L2>; |
| 29 | }; | 31 | }; |
| @@ -35,6 +37,27 @@ | |||
| 35 | compatible = "fsl,imx6dl-iomuxc"; | 37 | compatible = "fsl,imx6dl-iomuxc"; |
| 36 | reg = <0x020e0000 0x4000>; | 38 | reg = <0x020e0000 0x4000>; |
| 37 | 39 | ||
| 40 | audmux { | ||
| 41 | pinctrl_audmux_2: audmux-2 { | ||
| 42 | fsl,pins = < | ||
| 43 | MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 | ||
| 44 | MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 | ||
| 45 | MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 | ||
| 46 | MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 | ||
| 47 | >; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | ecspi1 { | ||
| 52 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 53 | fsl,pins = < | ||
| 54 | MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 55 | MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 56 | MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 57 | >; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | |||
| 38 | enet { | 61 | enet { |
| 39 | pinctrl_enet_1: enetgrp-1 { | 62 | pinctrl_enet_1: enetgrp-1 { |
| 40 | fsl,pins = < | 63 | fsl,pins = < |
| @@ -78,6 +101,39 @@ | |||
| 78 | }; | 101 | }; |
| 79 | }; | 102 | }; |
| 80 | 103 | ||
| 104 | gpmi-nand { | ||
| 105 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | ||
| 106 | fsl,pins = < | ||
| 107 | MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 108 | MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 109 | MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 110 | MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 111 | MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 112 | MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 113 | MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 114 | MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 115 | MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 116 | MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 117 | MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 118 | MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 119 | MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 120 | MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 121 | MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 122 | MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 123 | MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 124 | >; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | |||
| 128 | i2c1 { | ||
| 129 | pinctrl_i2c1_2: i2c1grp-2 { | ||
| 130 | fsl,pins = < | ||
| 131 | MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | ||
| 132 | MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | ||
| 133 | >; | ||
| 134 | }; | ||
| 135 | }; | ||
| 136 | |||
| 81 | uart1 { | 137 | uart1 { |
| 82 | pinctrl_uart1_1: uart1grp-1 { | 138 | pinctrl_uart1_1: uart1grp-1 { |
| 83 | fsl,pins = < | 139 | fsl,pins = < |
| @@ -149,6 +205,64 @@ | |||
| 149 | }; | 205 | }; |
| 150 | }; | 206 | }; |
| 151 | 207 | ||
| 208 | weim { | ||
| 209 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | ||
| 210 | fsl,pins = < | ||
| 211 | MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | ||
| 212 | >; | ||
| 213 | }; | ||
| 214 | |||
| 215 | pinctrl_weim_nor_1: weim_norgrp-1 { | ||
| 216 | fsl,pins = < | ||
| 217 | MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1 | ||
| 218 | MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1 | ||
| 219 | MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | ||
| 220 | /* data */ | ||
| 221 | MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | ||
| 222 | MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | ||
| 223 | MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | ||
| 224 | MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | ||
| 225 | MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | ||
| 226 | MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | ||
| 227 | MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | ||
| 228 | MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | ||
| 229 | MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | ||
| 230 | MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | ||
| 231 | MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | ||
| 232 | MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | ||
| 233 | MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | ||
| 234 | MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | ||
| 235 | MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | ||
| 236 | MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | ||
| 237 | /* address */ | ||
| 238 | MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | ||
| 239 | MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | ||
| 240 | MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | ||
| 241 | MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | ||
| 242 | MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | ||
| 243 | MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | ||
| 244 | MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | ||
| 245 | MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | ||
| 246 | MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1 | ||
| 247 | MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1 | ||
| 248 | MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1 | ||
| 249 | MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1 | ||
| 250 | MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1 | ||
| 251 | MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1 | ||
| 252 | MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1 | ||
| 253 | MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1 | ||
| 254 | MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1 | ||
| 255 | MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1 | ||
| 256 | MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1 | ||
| 257 | MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1 | ||
| 258 | MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1 | ||
| 259 | MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1 | ||
| 260 | MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1 | ||
| 261 | MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1 | ||
| 262 | >; | ||
| 263 | }; | ||
| 264 | |||
| 265 | }; | ||
| 152 | 266 | ||
| 153 | }; | 267 | }; |
| 154 | 268 | ||
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts new file mode 100644 index 000000000000..7d37ec60d58d --- /dev/null +++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | /dts-v1/; | ||
| 13 | #include "imx6q-phytec-pfla02.dtsi" | ||
| 14 | |||
| 15 | / { | ||
| 16 | model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board"; | ||
| 17 | compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q"; | ||
| 18 | }; | ||
| 19 | |||
| 20 | &fec { | ||
| 21 | status = "okay"; | ||
| 22 | }; | ||
| 23 | |||
| 24 | &uart4 { | ||
| 25 | status = "okay"; | ||
| 26 | }; | ||
| 27 | |||
| 28 | &usdhc2 { | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
| 31 | |||
| 32 | &usdhc3 { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi new file mode 100644 index 000000000000..f5e1981025ed --- /dev/null +++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include "imx6q.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Phytec phyFLEX-i.MX6 Ouad"; | ||
| 16 | compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x10000000 0x80000000>; | ||
| 20 | }; | ||
| 21 | }; | ||
| 22 | |||
| 23 | &iomuxc { | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&pinctrl_hog>; | ||
| 26 | |||
| 27 | hog { | ||
| 28 | pinctrl_hog: hoggrp { | ||
| 29 | fsl,pins = < | ||
| 30 | MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 | ||
| 31 | >; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 35 | pfla02 { | ||
| 36 | pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { | ||
| 37 | fsl,pins = < | ||
| 38 | MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 | ||
| 39 | MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 | ||
| 40 | >; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | |||
| 45 | &fec { | ||
| 46 | pinctrl-names = "default"; | ||
| 47 | pinctrl-0 = <&pinctrl_enet_3>; | ||
| 48 | phy-mode = "rgmii"; | ||
| 49 | phy-reset-gpios = <&gpio3 23 0>; | ||
| 50 | status = "disabled"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | &uart4 { | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | pinctrl-0 = <&pinctrl_uart4_1>; | ||
| 56 | status = "disabled"; | ||
| 57 | }; | ||
| 58 | |||
| 59 | &usdhc2 { | ||
| 60 | pinctrl-names = "default"; | ||
| 61 | pinctrl-0 = <&pinctrl_usdhc2_2>; | ||
| 62 | cd-gpios = <&gpio1 4 0>; | ||
| 63 | wp-gpios = <&gpio1 2 0>; | ||
| 64 | status = "disabled"; | ||
| 65 | }; | ||
| 66 | |||
| 67 | &usdhc3 { | ||
| 68 | pinctrl-names = "default"; | ||
| 69 | pinctrl-0 = <&pinctrl_usdhc3_2 | ||
| 70 | &pinctrl_usdhc3_pfla02>; | ||
| 71 | cd-gpios = <&gpio1 27 0>; | ||
| 72 | wp-gpios = <&gpio1 29 0>; | ||
| 73 | status = "disabled"; | ||
| 74 | }; | ||
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts index 49d6f2831ec9..09a75807bc6d 100644 --- a/arch/arm/boot/dts/imx6q-sabreauto.dts +++ b/arch/arm/boot/dts/imx6q-sabreauto.dts | |||
| @@ -32,4 +32,12 @@ | |||
| 32 | >; | 32 | >; |
| 33 | }; | 33 | }; |
| 34 | }; | 34 | }; |
| 35 | |||
| 36 | ecspi1 { | ||
| 37 | pinctrl_ecspi1_sabreauto: ecspi1-sabreauto { | ||
| 38 | fsl,pins = < | ||
| 39 | MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 | ||
| 40 | >; | ||
| 41 | }; | ||
| 42 | }; | ||
| 35 | }; | 43 | }; |
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts index 442051350225..0038228c508c 100644 --- a/arch/arm/boot/dts/imx6q-sabresd.dts +++ b/arch/arm/boot/dts/imx6q-sabresd.dts | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000 | 33 | MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000 |
| 34 | MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000 | 34 | MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000 |
| 35 | MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000 | 35 | MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000 |
| 36 | MX6Q_PAD_GPIO_0__CCM_CLKO1 0x130b0 | ||
| 36 | >; | 37 | >; |
| 37 | }; | 38 | }; |
| 38 | }; | 39 | }; |
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 21e675848bd1..ba09dc32324e 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | 18 | ||
| 19 | cpu@0 { | 19 | cpu@0 { |
| 20 | compatible = "arm,cortex-a9"; | 20 | compatible = "arm,cortex-a9"; |
| 21 | device_type = "cpu"; | ||
| 21 | reg = <0>; | 22 | reg = <0>; |
| 22 | next-level-cache = <&L2>; | 23 | next-level-cache = <&L2>; |
| 23 | operating-points = < | 24 | operating-points = < |
| @@ -39,18 +40,21 @@ | |||
| 39 | 40 | ||
| 40 | cpu@1 { | 41 | cpu@1 { |
| 41 | compatible = "arm,cortex-a9"; | 42 | compatible = "arm,cortex-a9"; |
| 43 | device_type = "cpu"; | ||
| 42 | reg = <1>; | 44 | reg = <1>; |
| 43 | next-level-cache = <&L2>; | 45 | next-level-cache = <&L2>; |
| 44 | }; | 46 | }; |
| 45 | 47 | ||
| 46 | cpu@2 { | 48 | cpu@2 { |
| 47 | compatible = "arm,cortex-a9"; | 49 | compatible = "arm,cortex-a9"; |
| 50 | device_type = "cpu"; | ||
| 48 | reg = <2>; | 51 | reg = <2>; |
| 49 | next-level-cache = <&L2>; | 52 | next-level-cache = <&L2>; |
| 50 | }; | 53 | }; |
| 51 | 54 | ||
| 52 | cpu@3 { | 55 | cpu@3 { |
| 53 | compatible = "arm,cortex-a9"; | 56 | compatible = "arm,cortex-a9"; |
| 57 | device_type = "cpu"; | ||
| 54 | reg = <3>; | 58 | reg = <3>; |
| 55 | next-level-cache = <&L2>; | 59 | next-level-cache = <&L2>; |
| 56 | }; | 60 | }; |
| @@ -157,6 +161,27 @@ | |||
| 157 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | 161 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| 158 | >; | 162 | >; |
| 159 | }; | 163 | }; |
| 164 | |||
| 165 | pinctrl_enet_3: enetgrp-3 { | ||
| 166 | fsl,pins = < | ||
| 167 | MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 | ||
| 168 | MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0 | ||
| 169 | MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 | ||
| 170 | MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 | ||
| 171 | MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 | ||
| 172 | MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 | ||
| 173 | MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 | ||
| 174 | MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 | ||
| 175 | MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 | ||
| 176 | MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 | ||
| 177 | MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 | ||
| 178 | MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 | ||
| 179 | MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 | ||
| 180 | MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 | ||
| 181 | MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 | ||
| 182 | MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 | ||
| 183 | >; | ||
| 184 | }; | ||
| 160 | }; | 185 | }; |
| 161 | 186 | ||
| 162 | gpmi-nand { | 187 | gpmi-nand { |
| @@ -168,8 +193,6 @@ | |||
| 168 | MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 | 193 | MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000 |
| 169 | MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | 194 | MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 |
| 170 | MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | 195 | MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 |
| 171 | MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 | ||
| 172 | MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 | ||
| 173 | MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | 196 | MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1 |
| 174 | MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | 197 | MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1 |
| 175 | MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | 198 | MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1 |
| @@ -192,6 +215,13 @@ | |||
| 192 | MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 | 215 | MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 |
| 193 | >; | 216 | >; |
| 194 | }; | 217 | }; |
| 218 | |||
| 219 | pinctrl_i2c1_2: i2c1grp-2 { | ||
| 220 | fsl,pins = < | ||
| 221 | MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | ||
| 222 | MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | ||
| 223 | >; | ||
| 224 | }; | ||
| 195 | }; | 225 | }; |
| 196 | 226 | ||
| 197 | i2c2 { | 227 | i2c2 { |
| @@ -268,6 +298,17 @@ | |||
| 268 | MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 | 298 | MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059 |
| 269 | >; | 299 | >; |
| 270 | }; | 300 | }; |
| 301 | |||
| 302 | pinctrl_usdhc2_2: usdhc2grp-2 { | ||
| 303 | fsl,pins = < | ||
| 304 | MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 305 | MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 306 | MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 307 | MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 308 | MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 309 | MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 310 | >; | ||
| 311 | }; | ||
| 271 | }; | 312 | }; |
| 272 | 313 | ||
| 273 | usdhc3 { | 314 | usdhc3 { |
| @@ -325,6 +366,65 @@ | |||
| 325 | >; | 366 | >; |
| 326 | }; | 367 | }; |
| 327 | }; | 368 | }; |
| 369 | |||
| 370 | weim { | ||
| 371 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | ||
| 372 | fsl,pins = < | ||
| 373 | MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | ||
| 374 | >; | ||
| 375 | }; | ||
| 376 | |||
| 377 | pinctrl_weim_nor_1: weimnorgrp-1 { | ||
| 378 | fsl,pins = < | ||
| 379 | MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1 | ||
| 380 | MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1 | ||
| 381 | MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | ||
| 382 | /* data */ | ||
| 383 | MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | ||
| 384 | MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | ||
| 385 | MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | ||
| 386 | MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | ||
| 387 | MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | ||
| 388 | MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | ||
| 389 | MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | ||
| 390 | MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | ||
| 391 | MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | ||
| 392 | MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | ||
| 393 | MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | ||
| 394 | MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | ||
| 395 | MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | ||
| 396 | MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | ||
| 397 | MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | ||
| 398 | MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | ||
| 399 | /* address */ | ||
| 400 | MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | ||
| 401 | MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | ||
| 402 | MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | ||
| 403 | MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | ||
| 404 | MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | ||
| 405 | MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | ||
| 406 | MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | ||
| 407 | MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | ||
| 408 | MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1 | ||
| 409 | MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1 | ||
| 410 | MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1 | ||
| 411 | MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1 | ||
| 412 | MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1 | ||
| 413 | MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1 | ||
| 414 | MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1 | ||
| 415 | MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1 | ||
| 416 | MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1 | ||
| 417 | MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1 | ||
| 418 | MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1 | ||
| 419 | MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1 | ||
| 420 | MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1 | ||
| 421 | MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1 | ||
| 422 | MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1 | ||
| 423 | MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1 | ||
| 424 | >; | ||
| 425 | }; | ||
| 426 | |||
| 427 | }; | ||
| 328 | }; | 428 | }; |
| 329 | }; | 429 | }; |
| 330 | 430 | ||
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 4d237cffcc41..e994011220e7 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |||
| @@ -16,6 +16,22 @@ | |||
| 16 | }; | 16 | }; |
| 17 | }; | 17 | }; |
| 18 | 18 | ||
| 19 | &ecspi1 { | ||
| 20 | fsl,spi-num-chipselects = <1>; | ||
| 21 | cs-gpios = <&gpio3 19 0>; | ||
| 22 | pinctrl-names = "default"; | ||
| 23 | pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>; | ||
| 24 | status = "disabled"; /* pin conflict with WEIM NOR */ | ||
| 25 | |||
| 26 | flash: m25p80@0 { | ||
| 27 | #address-cells = <1>; | ||
| 28 | #size-cells = <1>; | ||
| 29 | compatible = "st,m25p32"; | ||
| 30 | spi-max-frequency = <20000000>; | ||
| 31 | reg = <0>; | ||
| 32 | }; | ||
| 33 | }; | ||
| 34 | |||
| 19 | &fec { | 35 | &fec { |
| 20 | pinctrl-names = "default"; | 36 | pinctrl-names = "default"; |
| 21 | pinctrl-0 = <&pinctrl_enet_2>; | 37 | pinctrl-0 = <&pinctrl_enet_2>; |
| @@ -23,6 +39,12 @@ | |||
| 23 | status = "okay"; | 39 | status = "okay"; |
| 24 | }; | 40 | }; |
| 25 | 41 | ||
| 42 | &gpmi { | ||
| 43 | pinctrl-names = "default"; | ||
| 44 | pinctrl-0 = <&pinctrl_gpmi_nand_1>; | ||
| 45 | status = "okay"; | ||
| 46 | }; | ||
| 47 | |||
| 26 | &uart4 { | 48 | &uart4 { |
| 27 | pinctrl-names = "default"; | 49 | pinctrl-names = "default"; |
| 28 | pinctrl-0 = <&pinctrl_uart4_1>; | 50 | pinctrl-0 = <&pinctrl_uart4_1>; |
| @@ -36,3 +58,22 @@ | |||
| 36 | wp-gpios = <&gpio1 13 0>; | 58 | wp-gpios = <&gpio1 13 0>; |
| 37 | status = "okay"; | 59 | status = "okay"; |
| 38 | }; | 60 | }; |
| 61 | |||
| 62 | &weim { | ||
| 63 | pinctrl-names = "default"; | ||
| 64 | pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; | ||
| 65 | #address-cells = <2>; | ||
| 66 | #size-cells = <1>; | ||
| 67 | ranges = <0 0 0x08000000 0x08000000>; | ||
| 68 | status = "disabled"; /* pin conflict with SPI NOR */ | ||
| 69 | |||
| 70 | nor@0,0 { | ||
| 71 | compatible = "cfi-flash"; | ||
| 72 | reg = <0 0 0x02000000>; | ||
| 73 | #address-cells = <1>; | ||
| 74 | #size-cells = <1>; | ||
| 75 | bank-width = <2>; | ||
| 76 | fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 | ||
| 77 | 0x0000c000 0x1404a38e 0x00000000>; | ||
| 78 | }; | ||
| 79 | }; | ||
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index e21f6a89cf0f..6e5dfdb32416 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi | |||
| @@ -26,6 +26,13 @@ | |||
| 26 | gpio = <&gpio3 22 0>; | 26 | gpio = <&gpio3 22 0>; |
| 27 | enable-active-high; | 27 | enable-active-high; |
| 28 | }; | 28 | }; |
| 29 | |||
| 30 | reg_audio: wm8962_supply { | ||
| 31 | compatible = "regulator-fixed"; | ||
| 32 | regulator-name = "wm8962-supply"; | ||
| 33 | gpio = <&gpio4 10 0>; | ||
| 34 | enable-active-high; | ||
| 35 | }; | ||
| 29 | }; | 36 | }; |
| 30 | 37 | ||
| 31 | gpio-keys { | 38 | gpio-keys { |
| @@ -43,6 +50,31 @@ | |||
| 43 | linux,code = <114>; /* KEY_VOLUMEDOWN */ | 50 | linux,code = <114>; /* KEY_VOLUMEDOWN */ |
| 44 | }; | 51 | }; |
| 45 | }; | 52 | }; |
| 53 | |||
| 54 | sound { | ||
| 55 | compatible = "fsl,imx6q-sabresd-wm8962", | ||
| 56 | "fsl,imx-audio-wm8962"; | ||
| 57 | model = "wm8962-audio"; | ||
| 58 | ssi-controller = <&ssi2>; | ||
| 59 | audio-codec = <&codec>; | ||
| 60 | audio-routing = | ||
| 61 | "Headphone Jack", "HPOUTL", | ||
| 62 | "Headphone Jack", "HPOUTR", | ||
| 63 | "Ext Spk", "SPKOUTL", | ||
| 64 | "Ext Spk", "SPKOUTR", | ||
| 65 | "MICBIAS", "AMIC", | ||
| 66 | "IN3R", "MICBIAS", | ||
| 67 | "DMIC", "MICBIAS", | ||
| 68 | "DMICDAT", "DMIC"; | ||
| 69 | mux-int-port = <2>; | ||
| 70 | mux-ext-port = <3>; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | |||
| 74 | &audmux { | ||
| 75 | pinctrl-names = "default"; | ||
| 76 | pinctrl-0 = <&pinctrl_audmux_2>; | ||
| 77 | status = "okay"; | ||
| 46 | }; | 78 | }; |
| 47 | 79 | ||
| 48 | &fec { | 80 | &fec { |
| @@ -52,6 +84,40 @@ | |||
| 52 | status = "okay"; | 84 | status = "okay"; |
| 53 | }; | 85 | }; |
| 54 | 86 | ||
| 87 | &i2c1 { | ||
| 88 | clock-frequency = <100000>; | ||
| 89 | pinctrl-names = "default"; | ||
| 90 | pinctrl-0 = <&pinctrl_i2c1_2>; | ||
| 91 | status = "okay"; | ||
| 92 | |||
| 93 | codec: wm8962@1a { | ||
| 94 | compatible = "wlf,wm8962"; | ||
| 95 | reg = <0x1a>; | ||
| 96 | clocks = <&clks 169>; | ||
| 97 | DCVDD-supply = <®_audio>; | ||
| 98 | DBVDD-supply = <®_audio>; | ||
| 99 | AVDD-supply = <®_audio>; | ||
| 100 | CPVDD-supply = <®_audio>; | ||
| 101 | MICVDD-supply = <®_audio>; | ||
| 102 | PLLVDD-supply = <®_audio>; | ||
| 103 | SPKVDD1-supply = <®_audio>; | ||
| 104 | SPKVDD2-supply = <®_audio>; | ||
| 105 | gpio-cfg = < | ||
| 106 | 0x0000 /* 0:Default */ | ||
| 107 | 0x0000 /* 1:Default */ | ||
| 108 | 0x0013 /* 2:FN_DMICCLK */ | ||
| 109 | 0x0000 /* 3:Default */ | ||
| 110 | 0x8014 /* 4:FN_DMICCDAT */ | ||
| 111 | 0x0000 /* 5:Default */ | ||
| 112 | >; | ||
| 113 | }; | ||
| 114 | }; | ||
| 115 | |||
| 116 | &ssi2 { | ||
| 117 | fsl,mode = "i2s-slave"; | ||
| 118 | status = "okay"; | ||
| 119 | }; | ||
| 120 | |||
| 55 | &uart1 { | 121 | &uart1 { |
| 56 | pinctrl-names = "default"; | 122 | pinctrl-names = "default"; |
| 57 | pinctrl-0 = <&pinctrl_uart1_1>; | 123 | pinctrl-0 = <&pinctrl_uart1_1>; |
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 9e8296e4c343..f21d259080fd 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi | |||
| @@ -106,6 +106,8 @@ | |||
| 106 | interrupts = <0 92 0x04>; | 106 | interrupts = <0 92 0x04>; |
| 107 | cache-unified; | 107 | cache-unified; |
| 108 | cache-level = <2>; | 108 | cache-level = <2>; |
| 109 | arm,tag-latency = <4 2 3>; | ||
| 110 | arm,data-latency = <4 2 3>; | ||
| 109 | }; | 111 | }; |
| 110 | 112 | ||
| 111 | pmu { | 113 | pmu { |
| @@ -638,7 +640,7 @@ | |||
| 638 | status = "disabled"; | 640 | status = "disabled"; |
| 639 | }; | 641 | }; |
| 640 | 642 | ||
| 641 | usbmisc: usbmisc: usbmisc@02184800 { | 643 | usbmisc: usbmisc@02184800 { |
| 642 | #index-cells = <1>; | 644 | #index-cells = <1>; |
| 643 | compatible = "fsl,imx6q-usbmisc"; | 645 | compatible = "fsl,imx6q-usbmisc"; |
| 644 | reg = <0x02184800 0x200>; | 646 | reg = <0x02184800 0x200>; |
| @@ -742,9 +744,11 @@ | |||
| 742 | reg = <0x021b4000 0x4000>; | 744 | reg = <0x021b4000 0x4000>; |
| 743 | }; | 745 | }; |
| 744 | 746 | ||
| 745 | weim@021b8000 { | 747 | weim: weim@021b8000 { |
| 748 | compatible = "fsl,imx6q-weim"; | ||
| 746 | reg = <0x021b8000 0x4000>; | 749 | reg = <0x021b8000 0x4000>; |
| 747 | interrupts = <0 14 0x04>; | 750 | interrupts = <0 14 0x04>; |
| 751 | clocks = <&clks 196>; | ||
| 748 | }; | 752 | }; |
| 749 | 753 | ||
| 750 | ocotp@021bc000 { | 754 | ocotp@021bc000 { |
| @@ -752,11 +756,6 @@ | |||
| 752 | reg = <0x021bc000 0x4000>; | 756 | reg = <0x021bc000 0x4000>; |
| 753 | }; | 757 | }; |
| 754 | 758 | ||
| 755 | ocotp@021c0000 { | ||
| 756 | reg = <0x021c0000 0x4000>; | ||
| 757 | interrupts = <0 21 0x04>; | ||
| 758 | }; | ||
| 759 | |||
| 760 | tzasc@021d0000 { /* TZASC1 */ | 759 | tzasc@021d0000 { /* TZASC1 */ |
| 761 | reg = <0x021d0000 0x4000>; | 760 | reg = <0x021d0000 0x4000>; |
| 762 | interrupts = <0 108 0x04>; | 761 | interrupts = <0 108 0x04>; |
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts new file mode 100644 index 000000000000..2886a590823d --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-evk.dts | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | #include "imx6sl.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Freescale i.MX6 SoloLite EVK Board"; | ||
| 15 | compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; | ||
| 16 | |||
| 17 | memory { | ||
| 18 | reg = <0x80000000 0x40000000>; | ||
| 19 | }; | ||
| 20 | }; | ||
| 21 | |||
| 22 | &fec { | ||
| 23 | pinctrl-names = "default"; | ||
| 24 | pinctrl-0 = <&pinctrl_fec_1>; | ||
| 25 | phy-mode = "rmii"; | ||
| 26 | status = "okay"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | &iomuxc { | ||
| 30 | pinctrl-names = "default"; | ||
| 31 | pinctrl-0 = <&pinctrl_hog>; | ||
| 32 | |||
| 33 | hog { | ||
| 34 | pinctrl_hog: hoggrp { | ||
| 35 | fsl,pins = < | ||
| 36 | MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 | ||
| 37 | MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059 | ||
| 38 | MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059 | ||
| 39 | MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059 | ||
| 40 | MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 | ||
| 41 | >; | ||
| 42 | }; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &uart1 { | ||
| 47 | pinctrl-names = "default"; | ||
| 48 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 49 | status = "okay"; | ||
| 50 | }; | ||
| 51 | |||
| 52 | &usdhc1 { | ||
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&pinctrl_usdhc1_1>; | ||
| 55 | bus-width = <8>; | ||
| 56 | cd-gpios = <&gpio4 7 0>; | ||
| 57 | wp-gpios = <&gpio4 6 0>; | ||
| 58 | status = "okay"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | &usdhc2 { | ||
| 62 | pinctrl-names = "default"; | ||
| 63 | pinctrl-0 = <&pinctrl_usdhc2_1>; | ||
| 64 | cd-gpios = <&gpio5 0 0>; | ||
| 65 | wp-gpios = <&gpio4 29 0>; | ||
| 66 | status = "okay"; | ||
| 67 | }; | ||
| 68 | |||
| 69 | &usdhc3 { | ||
| 70 | pinctrl-names = "default"; | ||
| 71 | pinctrl-0 = <&pinctrl_usdhc3_1>; | ||
| 72 | cd-gpios = <&gpio3 22 0>; | ||
| 73 | status = "okay"; | ||
| 74 | }; | ||
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi new file mode 100644 index 000000000000..c5e5da02d7e3 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl.dtsi | |||
| @@ -0,0 +1,779 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include "skeleton.dtsi" | ||
| 11 | #include "imx6sl-pinfunc.h" | ||
| 12 | #include <dt-bindings/clock/imx6sl-clock.h> | ||
| 13 | |||
| 14 | / { | ||
| 15 | aliases { | ||
| 16 | serial0 = &uart1; | ||
| 17 | serial1 = &uart2; | ||
| 18 | serial2 = &uart3; | ||
| 19 | serial3 = &uart4; | ||
| 20 | serial4 = &uart5; | ||
| 21 | gpio0 = &gpio1; | ||
| 22 | gpio1 = &gpio2; | ||
| 23 | gpio2 = &gpio3; | ||
| 24 | gpio3 = &gpio4; | ||
| 25 | gpio4 = &gpio5; | ||
| 26 | }; | ||
| 27 | |||
| 28 | cpus { | ||
| 29 | #address-cells = <1>; | ||
| 30 | #size-cells = <0>; | ||
| 31 | |||
| 32 | cpu@0 { | ||
| 33 | compatible = "arm,cortex-a9"; | ||
| 34 | device_type = "cpu"; | ||
| 35 | reg = <0x0>; | ||
| 36 | next-level-cache = <&L2>; | ||
| 37 | }; | ||
| 38 | }; | ||
| 39 | |||
| 40 | intc: interrupt-controller@00a01000 { | ||
| 41 | compatible = "arm,cortex-a9-gic"; | ||
| 42 | #interrupt-cells = <3>; | ||
| 43 | #address-cells = <1>; | ||
| 44 | #size-cells = <1>; | ||
| 45 | interrupt-controller; | ||
| 46 | reg = <0x00a01000 0x1000>, | ||
| 47 | <0x00a00100 0x100>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | clocks { | ||
| 51 | #address-cells = <1>; | ||
| 52 | #size-cells = <0>; | ||
| 53 | |||
| 54 | ckil { | ||
| 55 | compatible = "fixed-clock"; | ||
| 56 | clock-frequency = <32768>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | osc { | ||
| 60 | compatible = "fixed-clock"; | ||
| 61 | clock-frequency = <24000000>; | ||
| 62 | }; | ||
| 63 | }; | ||
| 64 | |||
| 65 | soc { | ||
| 66 | #address-cells = <1>; | ||
| 67 | #size-cells = <1>; | ||
| 68 | compatible = "simple-bus"; | ||
| 69 | interrupt-parent = <&intc>; | ||
| 70 | ranges; | ||
| 71 | |||
| 72 | L2: l2-cache@00a02000 { | ||
| 73 | compatible = "arm,pl310-cache"; | ||
| 74 | reg = <0x00a02000 0x1000>; | ||
| 75 | interrupts = <0 92 0x04>; | ||
| 76 | cache-unified; | ||
| 77 | cache-level = <2>; | ||
| 78 | arm,tag-latency = <4 2 3>; | ||
| 79 | arm,data-latency = <4 2 3>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | pmu { | ||
| 83 | compatible = "arm,cortex-a9-pmu"; | ||
| 84 | interrupts = <0 94 0x04>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | aips1: aips-bus@02000000 { | ||
| 88 | compatible = "fsl,aips-bus", "simple-bus"; | ||
| 89 | #address-cells = <1>; | ||
| 90 | #size-cells = <1>; | ||
| 91 | reg = <0x02000000 0x100000>; | ||
| 92 | ranges; | ||
| 93 | |||
| 94 | spba: spba-bus@02000000 { | ||
| 95 | compatible = "fsl,spba-bus", "simple-bus"; | ||
| 96 | #address-cells = <1>; | ||
| 97 | #size-cells = <1>; | ||
| 98 | reg = <0x02000000 0x40000>; | ||
| 99 | ranges; | ||
| 100 | |||
| 101 | spdif: spdif@02004000 { | ||
| 102 | reg = <0x02004000 0x4000>; | ||
| 103 | interrupts = <0 52 0x04>; | ||
| 104 | }; | ||
| 105 | |||
| 106 | ecspi1: ecspi@02008000 { | ||
| 107 | #address-cells = <1>; | ||
| 108 | #size-cells = <0>; | ||
| 109 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; | ||
| 110 | reg = <0x02008000 0x4000>; | ||
| 111 | interrupts = <0 31 0x04>; | ||
| 112 | clocks = <&clks IMX6SL_CLK_ECSPI1>, | ||
| 113 | <&clks IMX6SL_CLK_ECSPI1>; | ||
| 114 | clock-names = "ipg", "per"; | ||
| 115 | status = "disabled"; | ||
| 116 | }; | ||
| 117 | |||
| 118 | ecspi2: ecspi@0200c000 { | ||
| 119 | #address-cells = <1>; | ||
| 120 | #size-cells = <0>; | ||
| 121 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; | ||
| 122 | reg = <0x0200c000 0x4000>; | ||
| 123 | interrupts = <0 32 0x04>; | ||
| 124 | clocks = <&clks IMX6SL_CLK_ECSPI2>, | ||
| 125 | <&clks IMX6SL_CLK_ECSPI2>; | ||
| 126 | clock-names = "ipg", "per"; | ||
| 127 | status = "disabled"; | ||
| 128 | }; | ||
| 129 | |||
| 130 | ecspi3: ecspi@02010000 { | ||
| 131 | #address-cells = <1>; | ||
| 132 | #size-cells = <0>; | ||
| 133 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; | ||
| 134 | reg = <0x02010000 0x4000>; | ||
| 135 | interrupts = <0 33 0x04>; | ||
| 136 | clocks = <&clks IMX6SL_CLK_ECSPI3>, | ||
| 137 | <&clks IMX6SL_CLK_ECSPI3>; | ||
| 138 | clock-names = "ipg", "per"; | ||
| 139 | status = "disabled"; | ||
| 140 | }; | ||
| 141 | |||
| 142 | ecspi4: ecspi@02014000 { | ||
| 143 | #address-cells = <1>; | ||
| 144 | #size-cells = <0>; | ||
| 145 | compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; | ||
| 146 | reg = <0x02014000 0x4000>; | ||
| 147 | interrupts = <0 34 0x04>; | ||
| 148 | clocks = <&clks IMX6SL_CLK_ECSPI4>, | ||
| 149 | <&clks IMX6SL_CLK_ECSPI4>; | ||
| 150 | clock-names = "ipg", "per"; | ||
| 151 | status = "disabled"; | ||
| 152 | }; | ||
| 153 | |||
| 154 | uart5: serial@02018000 { | ||
| 155 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | ||
| 156 | reg = <0x02018000 0x4000>; | ||
| 157 | interrupts = <0 30 0x04>; | ||
| 158 | clocks = <&clks IMX6SL_CLK_UART>, | ||
| 159 | <&clks IMX6SL_CLK_UART_SERIAL>; | ||
| 160 | clock-names = "ipg", "per"; | ||
| 161 | status = "disabled"; | ||
| 162 | }; | ||
| 163 | |||
| 164 | uart1: serial@02020000 { | ||
| 165 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | ||
| 166 | reg = <0x02020000 0x4000>; | ||
| 167 | interrupts = <0 26 0x04>; | ||
| 168 | clocks = <&clks IMX6SL_CLK_UART>, | ||
| 169 | <&clks IMX6SL_CLK_UART_SERIAL>; | ||
| 170 | clock-names = "ipg", "per"; | ||
| 171 | status = "disabled"; | ||
| 172 | }; | ||
| 173 | |||
| 174 | uart2: serial@02024000 { | ||
| 175 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | ||
| 176 | reg = <0x02024000 0x4000>; | ||
| 177 | interrupts = <0 27 0x04>; | ||
| 178 | clocks = <&clks IMX6SL_CLK_UART>, | ||
| 179 | <&clks IMX6SL_CLK_UART_SERIAL>; | ||
| 180 | clock-names = "ipg", "per"; | ||
| 181 | status = "disabled"; | ||
| 182 | }; | ||
| 183 | |||
| 184 | ssi1: ssi@02028000 { | ||
| 185 | compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; | ||
| 186 | reg = <0x02028000 0x4000>; | ||
| 187 | interrupts = <0 46 0x04>; | ||
| 188 | clocks = <&clks IMX6SL_CLK_SSI1>; | ||
| 189 | fsl,fifo-depth = <15>; | ||
| 190 | status = "disabled"; | ||
| 191 | }; | ||
| 192 | |||
| 193 | ssi2: ssi@0202c000 { | ||
| 194 | compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; | ||
| 195 | reg = <0x0202c000 0x4000>; | ||
| 196 | interrupts = <0 47 0x04>; | ||
| 197 | clocks = <&clks IMX6SL_CLK_SSI2>; | ||
| 198 | fsl,fifo-depth = <15>; | ||
| 199 | status = "disabled"; | ||
| 200 | }; | ||
| 201 | |||
| 202 | ssi3: ssi@02030000 { | ||
| 203 | compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi"; | ||
| 204 | reg = <0x02030000 0x4000>; | ||
| 205 | interrupts = <0 48 0x04>; | ||
| 206 | clocks = <&clks IMX6SL_CLK_SSI3>; | ||
| 207 | fsl,fifo-depth = <15>; | ||
| 208 | status = "disabled"; | ||
| 209 | }; | ||
| 210 | |||
| 211 | uart3: serial@02034000 { | ||
| 212 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | ||
| 213 | reg = <0x02034000 0x4000>; | ||
| 214 | interrupts = <0 28 0x04>; | ||
| 215 | clocks = <&clks IMX6SL_CLK_UART>, | ||
| 216 | <&clks IMX6SL_CLK_UART_SERIAL>; | ||
| 217 | clock-names = "ipg", "per"; | ||
| 218 | status = "disabled"; | ||
| 219 | }; | ||
| 220 | |||
| 221 | uart4: serial@02038000 { | ||
| 222 | compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; | ||
| 223 | reg = <0x02038000 0x4000>; | ||
| 224 | interrupts = <0 29 0x04>; | ||
| 225 | clocks = <&clks IMX6SL_CLK_UART>, | ||
| 226 | <&clks IMX6SL_CLK_UART_SERIAL>; | ||
| 227 | clock-names = "ipg", "per"; | ||
| 228 | status = "disabled"; | ||
| 229 | }; | ||
| 230 | }; | ||
| 231 | |||
| 232 | pwm1: pwm@02080000 { | ||
| 233 | #pwm-cells = <2>; | ||
| 234 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; | ||
| 235 | reg = <0x02080000 0x4000>; | ||
| 236 | interrupts = <0 83 0x04>; | ||
| 237 | clocks = <&clks IMX6SL_CLK_PWM1>, | ||
| 238 | <&clks IMX6SL_CLK_PWM1>; | ||
| 239 | clock-names = "ipg", "per"; | ||
| 240 | }; | ||
| 241 | |||
| 242 | pwm2: pwm@02084000 { | ||
| 243 | #pwm-cells = <2>; | ||
| 244 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; | ||
| 245 | reg = <0x02084000 0x4000>; | ||
| 246 | interrupts = <0 84 0x04>; | ||
| 247 | clocks = <&clks IMX6SL_CLK_PWM2>, | ||
| 248 | <&clks IMX6SL_CLK_PWM2>; | ||
| 249 | clock-names = "ipg", "per"; | ||
| 250 | }; | ||
| 251 | |||
| 252 | pwm3: pwm@02088000 { | ||
| 253 | #pwm-cells = <2>; | ||
| 254 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; | ||
| 255 | reg = <0x02088000 0x4000>; | ||
| 256 | interrupts = <0 85 0x04>; | ||
| 257 | clocks = <&clks IMX6SL_CLK_PWM3>, | ||
| 258 | <&clks IMX6SL_CLK_PWM3>; | ||
| 259 | clock-names = "ipg", "per"; | ||
| 260 | }; | ||
| 261 | |||
| 262 | pwm4: pwm@0208c000 { | ||
| 263 | #pwm-cells = <2>; | ||
| 264 | compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; | ||
| 265 | reg = <0x0208c000 0x4000>; | ||
| 266 | interrupts = <0 86 0x04>; | ||
| 267 | clocks = <&clks IMX6SL_CLK_PWM4>, | ||
| 268 | <&clks IMX6SL_CLK_PWM4>; | ||
| 269 | clock-names = "ipg", "per"; | ||
| 270 | }; | ||
| 271 | |||
| 272 | gpt: gpt@02098000 { | ||
| 273 | compatible = "fsl,imx6sl-gpt"; | ||
| 274 | reg = <0x02098000 0x4000>; | ||
| 275 | interrupts = <0 55 0x04>; | ||
| 276 | clocks = <&clks IMX6SL_CLK_GPT>, | ||
| 277 | <&clks IMX6SL_CLK_GPT_SERIAL>; | ||
| 278 | clock-names = "ipg", "per"; | ||
| 279 | }; | ||
| 280 | |||
| 281 | gpio1: gpio@0209c000 { | ||
| 282 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; | ||
| 283 | reg = <0x0209c000 0x4000>; | ||
| 284 | interrupts = <0 66 0x04 0 67 0x04>; | ||
| 285 | gpio-controller; | ||
| 286 | #gpio-cells = <2>; | ||
| 287 | interrupt-controller; | ||
| 288 | #interrupt-cells = <2>; | ||
| 289 | }; | ||
| 290 | |||
| 291 | gpio2: gpio@020a0000 { | ||
| 292 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; | ||
| 293 | reg = <0x020a0000 0x4000>; | ||
| 294 | interrupts = <0 68 0x04 0 69 0x04>; | ||
| 295 | gpio-controller; | ||
| 296 | #gpio-cells = <2>; | ||
| 297 | interrupt-controller; | ||
| 298 | #interrupt-cells = <2>; | ||
| 299 | }; | ||
| 300 | |||
| 301 | gpio3: gpio@020a4000 { | ||
| 302 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; | ||
| 303 | reg = <0x020a4000 0x4000>; | ||
| 304 | interrupts = <0 70 0x04 0 71 0x04>; | ||
| 305 | gpio-controller; | ||
| 306 | #gpio-cells = <2>; | ||
| 307 | interrupt-controller; | ||
| 308 | #interrupt-cells = <2>; | ||
| 309 | }; | ||
| 310 | |||
| 311 | gpio4: gpio@020a8000 { | ||
| 312 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; | ||
| 313 | reg = <0x020a8000 0x4000>; | ||
| 314 | interrupts = <0 72 0x04 0 73 0x04>; | ||
| 315 | gpio-controller; | ||
| 316 | #gpio-cells = <2>; | ||
| 317 | interrupt-controller; | ||
| 318 | #interrupt-cells = <2>; | ||
| 319 | }; | ||
| 320 | |||
| 321 | gpio5: gpio@020ac000 { | ||
| 322 | compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; | ||
| 323 | reg = <0x020ac000 0x4000>; | ||
| 324 | interrupts = <0 74 0x04 0 75 0x04>; | ||
| 325 | gpio-controller; | ||
| 326 | #gpio-cells = <2>; | ||
| 327 | interrupt-controller; | ||
| 328 | #interrupt-cells = <2>; | ||
| 329 | }; | ||
| 330 | |||
| 331 | kpp: kpp@020b8000 { | ||
| 332 | reg = <0x020b8000 0x4000>; | ||
| 333 | interrupts = <0 82 0x04>; | ||
| 334 | }; | ||
| 335 | |||
| 336 | wdog1: wdog@020bc000 { | ||
| 337 | compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; | ||
| 338 | reg = <0x020bc000 0x4000>; | ||
| 339 | interrupts = <0 80 0x04>; | ||
| 340 | clocks = <&clks IMX6SL_CLK_DUMMY>; | ||
| 341 | }; | ||
| 342 | |||
| 343 | wdog2: wdog@020c0000 { | ||
| 344 | compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; | ||
| 345 | reg = <0x020c0000 0x4000>; | ||
| 346 | interrupts = <0 81 0x04>; | ||
| 347 | clocks = <&clks IMX6SL_CLK_DUMMY>; | ||
| 348 | status = "disabled"; | ||
| 349 | }; | ||
| 350 | |||
| 351 | clks: ccm@020c4000 { | ||
| 352 | compatible = "fsl,imx6sl-ccm"; | ||
| 353 | reg = <0x020c4000 0x4000>; | ||
| 354 | interrupts = <0 87 0x04 0 88 0x04>; | ||
| 355 | #clock-cells = <1>; | ||
| 356 | }; | ||
| 357 | |||
| 358 | anatop: anatop@020c8000 { | ||
| 359 | compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus"; | ||
| 360 | reg = <0x020c8000 0x1000>; | ||
| 361 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; | ||
| 362 | |||
| 363 | regulator-1p1@110 { | ||
| 364 | compatible = "fsl,anatop-regulator"; | ||
| 365 | regulator-name = "vdd1p1"; | ||
| 366 | regulator-min-microvolt = <800000>; | ||
| 367 | regulator-max-microvolt = <1375000>; | ||
| 368 | regulator-always-on; | ||
| 369 | anatop-reg-offset = <0x110>; | ||
| 370 | anatop-vol-bit-shift = <8>; | ||
| 371 | anatop-vol-bit-width = <5>; | ||
| 372 | anatop-min-bit-val = <4>; | ||
| 373 | anatop-min-voltage = <800000>; | ||
| 374 | anatop-max-voltage = <1375000>; | ||
| 375 | }; | ||
| 376 | |||
| 377 | regulator-3p0@120 { | ||
| 378 | compatible = "fsl,anatop-regulator"; | ||
| 379 | regulator-name = "vdd3p0"; | ||
| 380 | regulator-min-microvolt = <2800000>; | ||
| 381 | regulator-max-microvolt = <3150000>; | ||
| 382 | regulator-always-on; | ||
| 383 | anatop-reg-offset = <0x120>; | ||
| 384 | anatop-vol-bit-shift = <8>; | ||
| 385 | anatop-vol-bit-width = <5>; | ||
| 386 | anatop-min-bit-val = <0>; | ||
| 387 | anatop-min-voltage = <2625000>; | ||
| 388 | anatop-max-voltage = <3400000>; | ||
| 389 | }; | ||
| 390 | |||
| 391 | regulator-2p5@130 { | ||
| 392 | compatible = "fsl,anatop-regulator"; | ||
| 393 | regulator-name = "vdd2p5"; | ||
| 394 | regulator-min-microvolt = <2100000>; | ||
| 395 | regulator-max-microvolt = <2850000>; | ||
| 396 | regulator-always-on; | ||
| 397 | anatop-reg-offset = <0x130>; | ||
| 398 | anatop-vol-bit-shift = <8>; | ||
| 399 | anatop-vol-bit-width = <5>; | ||
| 400 | anatop-min-bit-val = <0>; | ||
| 401 | anatop-min-voltage = <2100000>; | ||
| 402 | anatop-max-voltage = <2850000>; | ||
| 403 | }; | ||
| 404 | |||
| 405 | reg_arm: regulator-vddcore@140 { | ||
| 406 | compatible = "fsl,anatop-regulator"; | ||
| 407 | regulator-name = "cpu"; | ||
| 408 | regulator-min-microvolt = <725000>; | ||
| 409 | regulator-max-microvolt = <1450000>; | ||
| 410 | regulator-always-on; | ||
| 411 | anatop-reg-offset = <0x140>; | ||
| 412 | anatop-vol-bit-shift = <0>; | ||
| 413 | anatop-vol-bit-width = <5>; | ||
| 414 | anatop-delay-reg-offset = <0x170>; | ||
| 415 | anatop-delay-bit-shift = <24>; | ||
| 416 | anatop-delay-bit-width = <2>; | ||
| 417 | anatop-min-bit-val = <1>; | ||
| 418 | anatop-min-voltage = <725000>; | ||
| 419 | anatop-max-voltage = <1450000>; | ||
| 420 | }; | ||
| 421 | |||
| 422 | reg_pu: regulator-vddpu@140 { | ||
| 423 | compatible = "fsl,anatop-regulator"; | ||
| 424 | regulator-name = "vddpu"; | ||
| 425 | regulator-min-microvolt = <725000>; | ||
| 426 | regulator-max-microvolt = <1450000>; | ||
| 427 | regulator-always-on; | ||
| 428 | anatop-reg-offset = <0x140>; | ||
| 429 | anatop-vol-bit-shift = <9>; | ||
| 430 | anatop-vol-bit-width = <5>; | ||
| 431 | anatop-delay-reg-offset = <0x170>; | ||
| 432 | anatop-delay-bit-shift = <26>; | ||
| 433 | anatop-delay-bit-width = <2>; | ||
| 434 | anatop-min-bit-val = <1>; | ||
| 435 | anatop-min-voltage = <725000>; | ||
| 436 | anatop-max-voltage = <1450000>; | ||
| 437 | }; | ||
| 438 | |||
| 439 | reg_soc: regulator-vddsoc@140 { | ||
| 440 | compatible = "fsl,anatop-regulator"; | ||
| 441 | regulator-name = "vddsoc"; | ||
| 442 | regulator-min-microvolt = <725000>; | ||
| 443 | regulator-max-microvolt = <1450000>; | ||
| 444 | regulator-always-on; | ||
| 445 | anatop-reg-offset = <0x140>; | ||
| 446 | anatop-vol-bit-shift = <18>; | ||
| 447 | anatop-vol-bit-width = <5>; | ||
| 448 | anatop-delay-reg-offset = <0x170>; | ||
| 449 | anatop-delay-bit-shift = <28>; | ||
| 450 | anatop-delay-bit-width = <2>; | ||
| 451 | anatop-min-bit-val = <1>; | ||
| 452 | anatop-min-voltage = <725000>; | ||
| 453 | anatop-max-voltage = <1450000>; | ||
| 454 | }; | ||
| 455 | }; | ||
| 456 | |||
| 457 | usbphy1: usbphy@020c9000 { | ||
| 458 | compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; | ||
| 459 | reg = <0x020c9000 0x1000>; | ||
| 460 | interrupts = <0 44 0x04>; | ||
| 461 | clocks = <&clks IMX6SL_CLK_USBPHY1>; | ||
| 462 | }; | ||
| 463 | |||
| 464 | usbphy2: usbphy@020ca000 { | ||
| 465 | compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; | ||
| 466 | reg = <0x020ca000 0x1000>; | ||
| 467 | interrupts = <0 45 0x04>; | ||
| 468 | clocks = <&clks IMX6SL_CLK_USBPHY2>; | ||
| 469 | }; | ||
| 470 | |||
| 471 | snvs@020cc000 { | ||
| 472 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; | ||
| 473 | #address-cells = <1>; | ||
| 474 | #size-cells = <1>; | ||
| 475 | ranges = <0 0x020cc000 0x4000>; | ||
| 476 | |||
| 477 | snvs-rtc-lp@34 { | ||
| 478 | compatible = "fsl,sec-v4.0-mon-rtc-lp"; | ||
| 479 | reg = <0x34 0x58>; | ||
| 480 | interrupts = <0 19 0x04 0 20 0x04>; | ||
| 481 | }; | ||
| 482 | }; | ||
| 483 | |||
| 484 | epit1: epit@020d0000 { | ||
| 485 | reg = <0x020d0000 0x4000>; | ||
| 486 | interrupts = <0 56 0x04>; | ||
| 487 | }; | ||
| 488 | |||
| 489 | epit2: epit@020d4000 { | ||
| 490 | reg = <0x020d4000 0x4000>; | ||
| 491 | interrupts = <0 57 0x04>; | ||
| 492 | }; | ||
| 493 | |||
| 494 | src: src@020d8000 { | ||
| 495 | compatible = "fsl,imx6sl-src", "fsl,imx51-src"; | ||
| 496 | reg = <0x020d8000 0x4000>; | ||
| 497 | interrupts = <0 91 0x04 0 96 0x04>; | ||
| 498 | #reset-cells = <1>; | ||
| 499 | }; | ||
| 500 | |||
| 501 | gpc: gpc@020dc000 { | ||
| 502 | compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; | ||
| 503 | reg = <0x020dc000 0x4000>; | ||
| 504 | interrupts = <0 89 0x04>; | ||
| 505 | }; | ||
| 506 | |||
| 507 | iomuxc: iomuxc@020e0000 { | ||
| 508 | compatible = "fsl,imx6sl-iomuxc"; | ||
| 509 | reg = <0x020e0000 0x4000>; | ||
| 510 | |||
| 511 | fec { | ||
| 512 | pinctrl_fec_1: fecgrp-1 { | ||
| 513 | fsl,pins = < | ||
| 514 | MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 | ||
| 515 | MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0 | ||
| 516 | MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0 | ||
| 517 | MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0 | ||
| 518 | MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0 | ||
| 519 | MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0 | ||
| 520 | MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0 | ||
| 521 | MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0 | ||
| 522 | MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8 | ||
| 523 | >; | ||
| 524 | }; | ||
| 525 | }; | ||
| 526 | |||
| 527 | uart1 { | ||
| 528 | pinctrl_uart1_1: uart1grp-1 { | ||
| 529 | fsl,pins = < | ||
| 530 | MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 | ||
| 531 | MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 | ||
| 532 | >; | ||
| 533 | }; | ||
| 534 | }; | ||
| 535 | |||
| 536 | usdhc1 { | ||
| 537 | pinctrl_usdhc1_1: usdhc1grp-1 { | ||
| 538 | fsl,pins = < | ||
| 539 | MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 | ||
| 540 | MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 | ||
| 541 | MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 | ||
| 542 | MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 | ||
| 543 | MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 | ||
| 544 | MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 | ||
| 545 | MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 | ||
| 546 | MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 | ||
| 547 | MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 | ||
| 548 | MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 | ||
| 549 | >; | ||
| 550 | }; | ||
| 551 | }; | ||
| 552 | |||
| 553 | usdhc2 { | ||
| 554 | pinctrl_usdhc2_1: usdhc2grp-1 { | ||
| 555 | fsl,pins = < | ||
| 556 | MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 | ||
| 557 | MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 | ||
| 558 | MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 | ||
| 559 | MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 | ||
| 560 | MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 | ||
| 561 | MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 | ||
| 562 | >; | ||
| 563 | }; | ||
| 564 | }; | ||
| 565 | |||
| 566 | usdhc3 { | ||
| 567 | pinctrl_usdhc3_1: usdhc3grp-1 { | ||
| 568 | fsl,pins = < | ||
| 569 | MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 | ||
| 570 | MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 | ||
| 571 | MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 | ||
| 572 | MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 | ||
| 573 | MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 | ||
| 574 | MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 | ||
| 575 | >; | ||
| 576 | }; | ||
| 577 | }; | ||
| 578 | }; | ||
| 579 | |||
| 580 | csi: csi@020e4000 { | ||
| 581 | reg = <0x020e4000 0x4000>; | ||
| 582 | interrupts = <0 7 0x04>; | ||
| 583 | }; | ||
| 584 | |||
| 585 | spdc: spdc@020e8000 { | ||
| 586 | reg = <0x020e8000 0x4000>; | ||
| 587 | interrupts = <0 6 0x04>; | ||
| 588 | }; | ||
| 589 | |||
| 590 | sdma: sdma@020ec000 { | ||
| 591 | compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma"; | ||
| 592 | reg = <0x020ec000 0x4000>; | ||
| 593 | interrupts = <0 2 0x04>; | ||
| 594 | clocks = <&clks IMX6SL_CLK_SDMA>, | ||
| 595 | <&clks IMX6SL_CLK_SDMA>; | ||
| 596 | clock-names = "ipg", "ahb"; | ||
| 597 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin"; | ||
| 598 | }; | ||
| 599 | |||
| 600 | pxp: pxp@020f0000 { | ||
| 601 | reg = <0x020f0000 0x4000>; | ||
| 602 | interrupts = <0 98 0x04>; | ||
| 603 | }; | ||
| 604 | |||
| 605 | epdc: epdc@020f4000 { | ||
| 606 | reg = <0x020f4000 0x4000>; | ||
| 607 | interrupts = <0 97 0x04>; | ||
| 608 | }; | ||
| 609 | |||
| 610 | lcdif: lcdif@020f8000 { | ||
| 611 | reg = <0x020f8000 0x4000>; | ||
| 612 | interrupts = <0 39 0x04>; | ||
| 613 | }; | ||
| 614 | |||
| 615 | dcp: dcp@020fc000 { | ||
| 616 | reg = <0x020fc000 0x4000>; | ||
| 617 | interrupts = <0 99 0x04>; | ||
| 618 | }; | ||
| 619 | }; | ||
| 620 | |||
| 621 | aips2: aips-bus@02100000 { | ||
| 622 | compatible = "fsl,aips-bus", "simple-bus"; | ||
| 623 | #address-cells = <1>; | ||
| 624 | #size-cells = <1>; | ||
| 625 | reg = <0x02100000 0x100000>; | ||
| 626 | ranges; | ||
| 627 | |||
| 628 | usbotg1: usb@02184000 { | ||
| 629 | compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; | ||
| 630 | reg = <0x02184000 0x200>; | ||
| 631 | interrupts = <0 43 0x04>; | ||
| 632 | clocks = <&clks IMX6SL_CLK_USBOH3>; | ||
| 633 | fsl,usbphy = <&usbphy1>; | ||
| 634 | fsl,usbmisc = <&usbmisc 0>; | ||
| 635 | status = "disabled"; | ||
| 636 | }; | ||
| 637 | |||
| 638 | usbotg2: usb@02184200 { | ||
| 639 | compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; | ||
| 640 | reg = <0x02184200 0x200>; | ||
| 641 | interrupts = <0 40 0x04>; | ||
| 642 | clocks = <&clks IMX6SL_CLK_USBOH3>; | ||
| 643 | fsl,usbphy = <&usbphy2>; | ||
| 644 | fsl,usbmisc = <&usbmisc 1>; | ||
| 645 | status = "disabled"; | ||
| 646 | }; | ||
| 647 | |||
| 648 | usbh: usb@02184400 { | ||
| 649 | compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; | ||
| 650 | reg = <0x02184400 0x200>; | ||
| 651 | interrupts = <0 42 0x04>; | ||
| 652 | clocks = <&clks IMX6SL_CLK_USBOH3>; | ||
| 653 | fsl,usbmisc = <&usbmisc 2>; | ||
| 654 | status = "disabled"; | ||
| 655 | }; | ||
| 656 | |||
| 657 | usbmisc: usbmisc@02184800 { | ||
| 658 | #index-cells = <1>; | ||
| 659 | compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; | ||
| 660 | reg = <0x02184800 0x200>; | ||
| 661 | clocks = <&clks IMX6SL_CLK_USBOH3>; | ||
| 662 | }; | ||
| 663 | |||
| 664 | fec: ethernet@02188000 { | ||
| 665 | compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; | ||
| 666 | reg = <0x02188000 0x4000>; | ||
| 667 | interrupts = <0 114 0x04>; | ||
| 668 | clocks = <&clks IMX6SL_CLK_ENET_REF>, | ||
| 669 | <&clks IMX6SL_CLK_ENET_REF>; | ||
| 670 | clock-names = "ipg", "ahb"; | ||
| 671 | status = "disabled"; | ||
| 672 | }; | ||
| 673 | |||
| 674 | usdhc1: usdhc@02190000 { | ||
| 675 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; | ||
| 676 | reg = <0x02190000 0x4000>; | ||
| 677 | interrupts = <0 22 0x04>; | ||
| 678 | clocks = <&clks IMX6SL_CLK_USDHC1>, | ||
| 679 | <&clks IMX6SL_CLK_USDHC1>, | ||
| 680 | <&clks IMX6SL_CLK_USDHC1>; | ||
| 681 | clock-names = "ipg", "ahb", "per"; | ||
| 682 | bus-width = <4>; | ||
| 683 | status = "disabled"; | ||
| 684 | }; | ||
| 685 | |||
| 686 | usdhc2: usdhc@02194000 { | ||
| 687 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; | ||
| 688 | reg = <0x02194000 0x4000>; | ||
| 689 | interrupts = <0 23 0x04>; | ||
| 690 | clocks = <&clks IMX6SL_CLK_USDHC2>, | ||
| 691 | <&clks IMX6SL_CLK_USDHC2>, | ||
| 692 | <&clks IMX6SL_CLK_USDHC2>; | ||
| 693 | clock-names = "ipg", "ahb", "per"; | ||
| 694 | bus-width = <4>; | ||
| 695 | status = "disabled"; | ||
| 696 | }; | ||
| 697 | |||
| 698 | usdhc3: usdhc@02198000 { | ||
| 699 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; | ||
| 700 | reg = <0x02198000 0x4000>; | ||
| 701 | interrupts = <0 24 0x04>; | ||
| 702 | clocks = <&clks IMX6SL_CLK_USDHC3>, | ||
| 703 | <&clks IMX6SL_CLK_USDHC3>, | ||
| 704 | <&clks IMX6SL_CLK_USDHC3>; | ||
| 705 | clock-names = "ipg", "ahb", "per"; | ||
| 706 | bus-width = <4>; | ||
| 707 | status = "disabled"; | ||
| 708 | }; | ||
| 709 | |||
| 710 | usdhc4: usdhc@0219c000 { | ||
| 711 | compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; | ||
| 712 | reg = <0x0219c000 0x4000>; | ||
| 713 | interrupts = <0 25 0x04>; | ||
| 714 | clocks = <&clks IMX6SL_CLK_USDHC4>, | ||
| 715 | <&clks IMX6SL_CLK_USDHC4>, | ||
| 716 | <&clks IMX6SL_CLK_USDHC4>; | ||
| 717 | clock-names = "ipg", "ahb", "per"; | ||
| 718 | bus-width = <4>; | ||
| 719 | status = "disabled"; | ||
| 720 | }; | ||
| 721 | |||
| 722 | i2c1: i2c@021a0000 { | ||
| 723 | #address-cells = <1>; | ||
| 724 | #size-cells = <0>; | ||
| 725 | compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; | ||
| 726 | reg = <0x021a0000 0x4000>; | ||
| 727 | interrupts = <0 36 0x04>; | ||
| 728 | clocks = <&clks IMX6SL_CLK_I2C1>; | ||
| 729 | status = "disabled"; | ||
| 730 | }; | ||
| 731 | |||
| 732 | i2c2: i2c@021a4000 { | ||
| 733 | #address-cells = <1>; | ||
| 734 | #size-cells = <0>; | ||
| 735 | compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; | ||
| 736 | reg = <0x021a4000 0x4000>; | ||
| 737 | interrupts = <0 37 0x04>; | ||
| 738 | clocks = <&clks IMX6SL_CLK_I2C2>; | ||
| 739 | status = "disabled"; | ||
| 740 | }; | ||
| 741 | |||
| 742 | i2c3: i2c@021a8000 { | ||
| 743 | #address-cells = <1>; | ||
| 744 | #size-cells = <0>; | ||
| 745 | compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; | ||
| 746 | reg = <0x021a8000 0x4000>; | ||
| 747 | interrupts = <0 38 0x04>; | ||
| 748 | clocks = <&clks IMX6SL_CLK_I2C3>; | ||
| 749 | status = "disabled"; | ||
| 750 | }; | ||
| 751 | |||
| 752 | mmdc: mmdc@021b0000 { | ||
| 753 | compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; | ||
| 754 | reg = <0x021b0000 0x4000>; | ||
| 755 | }; | ||
| 756 | |||
| 757 | rngb: rngb@021b4000 { | ||
| 758 | reg = <0x021b4000 0x4000>; | ||
| 759 | interrupts = <0 5 0x04>; | ||
| 760 | }; | ||
| 761 | |||
| 762 | weim: weim@021b8000 { | ||
| 763 | reg = <0x021b8000 0x4000>; | ||
| 764 | interrupts = <0 14 0x04>; | ||
| 765 | }; | ||
| 766 | |||
| 767 | ocotp: ocotp@021bc000 { | ||
| 768 | compatible = "fsl,imx6sl-ocotp"; | ||
| 769 | reg = <0x021bc000 0x4000>; | ||
| 770 | }; | ||
| 771 | |||
| 772 | audmux: audmux@021d8000 { | ||
| 773 | compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; | ||
| 774 | reg = <0x021d8000 0x4000>; | ||
| 775 | status = "disabled"; | ||
| 776 | }; | ||
| 777 | }; | ||
| 778 | }; | ||
| 779 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 51376683dbcd..1e5bef0bead7 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi | |||
| @@ -71,5 +71,33 @@ | |||
| 71 | status = "disabled"; | 71 | status = "disabled"; |
| 72 | }; | 72 | }; |
| 73 | }; | 73 | }; |
| 74 | |||
| 75 | rtc@10300 { | ||
| 76 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; | ||
| 77 | reg = <0x10300 0x20>; | ||
| 78 | interrupts = <53>; | ||
| 79 | clocks = <&gate_clk 7>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | sata@80000 { | ||
| 83 | compatible = "marvell,orion-sata"; | ||
| 84 | reg = <0x80000 0x5000>; | ||
| 85 | interrupts = <21>; | ||
| 86 | clocks = <&gate_clk 14>, <&gate_clk 15>; | ||
| 87 | clock-names = "0", "1"; | ||
| 88 | status = "disabled"; | ||
| 89 | }; | ||
| 90 | |||
| 91 | mvsdio@90000 { | ||
| 92 | compatible = "marvell,orion-sdio"; | ||
| 93 | reg = <0x90000 0x200>; | ||
| 94 | interrupts = <28>; | ||
| 95 | clocks = <&gate_clk 4>; | ||
| 96 | bus-width = <4>; | ||
| 97 | cap-sdio-irq; | ||
| 98 | cap-sd-highspeed; | ||
| 99 | cap-mmc-highspeed; | ||
| 100 | status = "disabled"; | ||
| 101 | }; | ||
| 74 | }; | 102 | }; |
| 75 | }; | 103 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 66a751ab5516..a63a11137262 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi | |||
| @@ -49,6 +49,34 @@ | |||
| 49 | }; | 49 | }; |
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | rtc@10300 { | ||
| 53 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; | ||
| 54 | reg = <0x10300 0x20>; | ||
| 55 | interrupts = <53>; | ||
| 56 | clocks = <&gate_clk 7>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | sata@80000 { | ||
| 60 | compatible = "marvell,orion-sata"; | ||
| 61 | reg = <0x80000 0x5000>; | ||
| 62 | interrupts = <21>; | ||
| 63 | clocks = <&gate_clk 14>, <&gate_clk 15>; | ||
| 64 | clock-names = "0", "1"; | ||
| 65 | status = "disabled"; | ||
| 66 | }; | ||
| 67 | |||
| 68 | mvsdio@90000 { | ||
| 69 | compatible = "marvell,orion-sdio"; | ||
| 70 | reg = <0x90000 0x200>; | ||
| 71 | interrupts = <28>; | ||
| 72 | clocks = <&gate_clk 4>; | ||
| 73 | bus-width = <4>; | ||
| 74 | cap-sdio-irq; | ||
| 75 | cap-sd-highspeed; | ||
| 76 | cap-mmc-highspeed; | ||
| 77 | status = "disabled"; | ||
| 78 | }; | ||
| 79 | |||
| 52 | thermal@10078 { | 80 | thermal@10078 { |
| 53 | compatible = "marvell,kirkwood-thermal"; | 81 | compatible = "marvell,kirkwood-thermal"; |
| 54 | reg = <0x10078 0x4>; | 82 | reg = <0x10078 0x4>; |
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 5f21d4e427b0..00c48d26de68 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts | |||
| @@ -18,10 +18,6 @@ | |||
| 18 | 18 | ||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | pinctrl-0 = < &pmx_spi &pmx_uart0 | ||
| 22 | &pmx_cloudbox_sata0 >; | ||
| 23 | pinctrl-names = "default"; | ||
| 24 | |||
| 25 | pmx_cloudbox_sata0: pmx-cloudbox-sata0 { | 21 | pmx_cloudbox_sata0: pmx-cloudbox-sata0 { |
| 26 | marvell,pins = "mpp15"; | 22 | marvell,pins = "mpp15"; |
| 27 | marvell,function = "sata0"; | 23 | marvell,function = "sata0"; |
| @@ -29,16 +25,22 @@ | |||
| 29 | }; | 25 | }; |
| 30 | 26 | ||
| 31 | serial@12000 { | 27 | serial@12000 { |
| 28 | pinctrl-0 = <&pmx_uart0>; | ||
| 29 | pinctrl-names = "default"; | ||
| 32 | clock-frequency = <166666667>; | 30 | clock-frequency = <166666667>; |
| 33 | status = "okay"; | 31 | status = "okay"; |
| 34 | }; | 32 | }; |
| 35 | 33 | ||
| 36 | sata@80000 { | 34 | sata@80000 { |
| 35 | pinctrl-0 = <&pmx_cloudbox_sata0>; | ||
| 36 | pinctrl-names = "default"; | ||
| 37 | status = "okay"; | 37 | status = "okay"; |
| 38 | nr-ports = <1>; | 38 | nr-ports = <1>; |
| 39 | }; | 39 | }; |
| 40 | 40 | ||
| 41 | spi@10600 { | 41 | spi@10600 { |
| 42 | pinctrl-0 = <&pmx_spi>; | ||
| 43 | pinctrl-names = "default"; | ||
| 42 | status = "okay"; | 44 | status = "okay"; |
| 43 | 45 | ||
| 44 | flash@0 { | 46 | flash@0 { |
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index c9c44b2f62d7..14d4ceea3057 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts | |||
| @@ -17,6 +17,11 @@ | |||
| 17 | 17 | ||
| 18 | gpio-leds { | 18 | gpio-leds { |
| 19 | compatible = "gpio-leds"; | 19 | compatible = "gpio-leds"; |
| 20 | pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320 | ||
| 21 | &pmx_led_red_left_hdd &pmx_led_red_right_hdd | ||
| 22 | &pmx_led_white_usb>; | ||
| 23 | pinctrl-names = "default"; | ||
| 24 | |||
| 20 | blue-power { | 25 | blue-power { |
| 21 | label = "dns320:blue:power"; | 26 | label = "dns320:blue:power"; |
| 22 | gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ | 27 | gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ |
| @@ -46,6 +51,8 @@ | |||
| 46 | }; | 51 | }; |
| 47 | 52 | ||
| 48 | serial@12100 { | 53 | serial@12100 { |
| 54 | pinctrl-0 = <&pmx_uart1>; | ||
| 55 | pinctrl-names = "default"; | ||
| 49 | status = "okay"; | 56 | status = "okay"; |
| 50 | }; | 57 | }; |
| 51 | }; | 58 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index e4e4930dc5cf..63872570e6ce 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts | |||
| @@ -17,6 +17,11 @@ | |||
| 17 | 17 | ||
| 18 | gpio-leds { | 18 | gpio-leds { |
| 19 | compatible = "gpio-leds"; | 19 | compatible = "gpio-leds"; |
| 20 | pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325 | ||
| 21 | &pmx_led_red_left_hdd &pmx_led_red_right_hdd | ||
| 22 | &pmx_led_white_usb>; | ||
| 23 | pinctrl-names = "default"; | ||
| 24 | |||
| 20 | white-power { | 25 | white-power { |
| 21 | label = "dns325:white:power"; | 26 | label = "dns325:white:power"; |
| 22 | gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ | 27 | gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ |
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 6875ac00c174..0afe1d07c803 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi | |||
| @@ -9,6 +9,10 @@ | |||
| 9 | compatible = "gpio-keys"; | 9 | compatible = "gpio-keys"; |
| 10 | #address-cells = <1>; | 10 | #address-cells = <1>; |
| 11 | #size-cells = <0>; | 11 | #size-cells = <0>; |
| 12 | pinctrl-0 = <&pmx_button_power &pmx_button_unmount | ||
| 13 | &pmx_button_reset>; | ||
| 14 | pinctrl-names = "default"; | ||
| 15 | |||
| 12 | button@1 { | 16 | button@1 { |
| 13 | label = "Power button"; | 17 | label = "Power button"; |
| 14 | linux,code = <116>; | 18 | linux,code = <116>; |
| @@ -29,6 +33,8 @@ | |||
| 29 | gpio_fan { | 33 | gpio_fan { |
| 30 | /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ | 34 | /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */ |
| 31 | compatible = "gpio-fan"; | 35 | compatible = "gpio-fan"; |
| 36 | pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; | ||
| 37 | pinctrl-names = "default"; | ||
| 32 | gpios = <&gpio1 14 1 | 38 | gpios = <&gpio1 14 1 |
| 33 | &gpio1 13 1>; | 39 | &gpio1 13 1>; |
| 34 | gpio-fan,speed-map = <0 0 | 40 | gpio-fan,speed-map = <0 0 |
| @@ -38,27 +44,17 @@ | |||
| 38 | 44 | ||
| 39 | gpio_poweroff { | 45 | gpio_poweroff { |
| 40 | compatible = "gpio-poweroff"; | 46 | compatible = "gpio-poweroff"; |
| 47 | pinctrl-0 = <&pmx_power_off>; | ||
| 48 | pinctrl-names = "default"; | ||
| 41 | gpios = <&gpio1 4 0>; | 49 | gpios = <&gpio1 4 0>; |
| 42 | }; | 50 | }; |
| 43 | 51 | ||
| 44 | ocp@f1000000 { | 52 | ocp@f1000000 { |
| 45 | pinctrl: pinctrl@10000 { | 53 | pinctrl: pinctrl@10000 { |
| 46 | 54 | ||
| 47 | pinctrl-0 = < &pmx_nand &pmx_uart1 | 55 | pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 |
| 48 | &pmx_sata0 &pmx_sata1 | 56 | &pmx_present_sata1 &pmx_fan_tacho |
| 49 | &pmx_led_power | 57 | &pmx_temp_alarm>; |
| 50 | &pmx_led_red_right_hdd | ||
| 51 | &pmx_led_red_left_hdd | ||
| 52 | &pmx_led_red_usb_325 | ||
| 53 | &pmx_button_power | ||
| 54 | &pmx_led_red_usb_320 | ||
| 55 | &pmx_power_off &pmx_power_back_on | ||
| 56 | &pmx_power_sata0 &pmx_power_sata1 | ||
| 57 | &pmx_present_sata0 &pmx_present_sata1 | ||
| 58 | &pmx_led_white_usb &pmx_fan_tacho | ||
| 59 | &pmx_fan_high_speed &pmx_fan_low_speed | ||
| 60 | &pmx_button_unmount &pmx_button_reset | ||
| 61 | &pmx_temp_alarm >; | ||
| 62 | pinctrl-names = "default"; | 58 | pinctrl-names = "default"; |
| 63 | 59 | ||
| 64 | pmx_sata0: pmx-sata0 { | 60 | pmx_sata0: pmx-sata0 { |
| @@ -147,11 +143,15 @@ | |||
| 147 | }; | 143 | }; |
| 148 | }; | 144 | }; |
| 149 | sata@80000 { | 145 | sata@80000 { |
| 146 | pinctrl-0 = <&pmx_sata0 &pmx_sata1>; | ||
| 147 | pinctrl-names = "default"; | ||
| 150 | status = "okay"; | 148 | status = "okay"; |
| 151 | nr-ports = <2>; | 149 | nr-ports = <2>; |
| 152 | }; | 150 | }; |
| 153 | 151 | ||
| 154 | nand@3000000 { | 152 | nand@3000000 { |
| 153 | pinctrl-0 = <&pmx_nand>; | ||
| 154 | pinctrl-names = "default"; | ||
| 155 | status = "okay"; | 155 | status = "okay"; |
| 156 | chip-delay = <35>; | 156 | chip-delay = <35>; |
| 157 | 157 | ||
| @@ -192,6 +192,8 @@ | |||
| 192 | compatible = "simple-bus"; | 192 | compatible = "simple-bus"; |
| 193 | #address-cells = <1>; | 193 | #address-cells = <1>; |
| 194 | #size-cells = <0>; | 194 | #size-cells = <0>; |
| 195 | pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>; | ||
| 196 | pinctrl-names = "default"; | ||
| 195 | 197 | ||
| 196 | sata0_power: regulator@1 { | 198 | sata0_power: regulator@1 { |
| 197 | compatible = "regulator-fixed"; | 199 | compatible = "regulator-fixed"; |
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 0196cf6b0ef2..7714742bb8d8 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts | |||
| @@ -18,11 +18,6 @@ | |||
| 18 | 18 | ||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | |||
| 22 | pinctrl-0 = < &pmx_usb_power_enable | ||
| 23 | &pmx_led_green &pmx_led_orange >; | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | |||
| 26 | pmx_usb_power_enable: pmx-usb-power-enable { | 21 | pmx_usb_power_enable: pmx-usb-power-enable { |
| 27 | marvell,pins = "mpp29"; | 22 | marvell,pins = "mpp29"; |
| 28 | marvell,function = "gpio"; | 23 | marvell,function = "gpio"; |
| @@ -62,6 +57,8 @@ | |||
| 62 | }; | 57 | }; |
| 63 | gpio-leds { | 58 | gpio-leds { |
| 64 | compatible = "gpio-leds"; | 59 | compatible = "gpio-leds"; |
| 60 | pinctrl-0 = <&pmx_led_green &pmx_led_orange>; | ||
| 61 | pinctrl-names = "default"; | ||
| 65 | 62 | ||
| 66 | health { | 63 | health { |
| 67 | label = "status:green:health"; | 64 | label = "status:green:health"; |
| @@ -77,6 +74,8 @@ | |||
| 77 | compatible = "simple-bus"; | 74 | compatible = "simple-bus"; |
| 78 | #address-cells = <1>; | 75 | #address-cells = <1>; |
| 79 | #size-cells = <0>; | 76 | #size-cells = <0>; |
| 77 | pinctrl-0 = <&pmx_usb_power_enable>; | ||
| 78 | pinctrl-names = "default"; | ||
| 80 | 79 | ||
| 81 | usb_power: regulator@1 { | 80 | usb_power: regulator@1 { |
| 82 | compatible = "regulator-fixed"; | 81 | compatible = "regulator-fixed"; |
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 289e51d86372..36c7ba38d500 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts | |||
| @@ -18,12 +18,6 @@ | |||
| 18 | 18 | ||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | |||
| 22 | pinctrl-0 = < &pmx_spi | ||
| 23 | &pmx_led_bluetooth &pmx_led_wifi | ||
| 24 | &pmx_led_wifi_ap >; | ||
| 25 | pinctrl-names = "default"; | ||
| 26 | |||
| 27 | pmx_led_bluetooth: pmx-led-bluetooth { | 21 | pmx_led_bluetooth: pmx-led-bluetooth { |
| 28 | marvell,pins = "mpp47"; | 22 | marvell,pins = "mpp47"; |
| 29 | marvell,function = "gpio"; | 23 | marvell,function = "gpio"; |
| @@ -43,6 +37,8 @@ | |||
| 43 | 37 | ||
| 44 | spi@10600 { | 38 | spi@10600 { |
| 45 | status = "okay"; | 39 | status = "okay"; |
| 40 | pinctrl-0 = <&pmx_spi>; | ||
| 41 | pinctrl-names = "default"; | ||
| 46 | 42 | ||
| 47 | m25p40@0 { | 43 | m25p40@0 { |
| 48 | #address-cells = <1>; | 44 | #address-cells = <1>; |
| @@ -79,11 +75,15 @@ | |||
| 79 | pinctrl-names = "default"; | 75 | pinctrl-names = "default"; |
| 80 | status = "okay"; | 76 | status = "okay"; |
| 81 | /* No CD or WP GPIOs */ | 77 | /* No CD or WP GPIOs */ |
| 78 | broken-cd; | ||
| 82 | }; | 79 | }; |
| 83 | }; | 80 | }; |
| 84 | 81 | ||
| 85 | gpio-leds { | 82 | gpio-leds { |
| 86 | compatible = "gpio-leds"; | 83 | compatible = "gpio-leds"; |
| 84 | pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi | ||
| 85 | &pmx_led_wifi_ap >; | ||
| 86 | pinctrl-names = "default"; | ||
| 87 | 87 | ||
| 88 | bluetooth { | 88 | bluetooth { |
| 89 | label = "dreamplug:blue:bluetooth"; | 89 | label = "dreamplug:blue:bluetooth"; |
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index c3573be7b92c..31caa6405065 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts | |||
| @@ -18,15 +18,6 @@ | |||
| 18 | 18 | ||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | |||
| 22 | pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange | ||
| 23 | &pmx_led_left_cap_0 &pmx_led_left_cap_1 | ||
| 24 | &pmx_led_left_cap_2 &pmx_led_left_cap_3 | ||
| 25 | &pmx_led_right_cap_0 &pmx_led_right_cap_1 | ||
| 26 | &pmx_led_right_cap_2 &pmx_led_right_cap_3 | ||
| 27 | >; | ||
| 28 | pinctrl-names = "default"; | ||
| 29 | |||
| 30 | pmx_usb_power_enable: pmx-usb-power-enable { | 21 | pmx_usb_power_enable: pmx-usb-power-enable { |
| 31 | marvell,pins = "mpp29"; | 22 | marvell,pins = "mpp29"; |
| 32 | marvell,function = "gpio"; | 23 | marvell,function = "gpio"; |
| @@ -109,6 +100,13 @@ | |||
| 109 | }; | 100 | }; |
| 110 | gpio-leds { | 101 | gpio-leds { |
| 111 | compatible = "gpio-leds"; | 102 | compatible = "gpio-leds"; |
| 103 | pinctrl-0 = < &pmx_led_orange | ||
| 104 | &pmx_led_left_cap_0 &pmx_led_left_cap_1 | ||
| 105 | &pmx_led_left_cap_2 &pmx_led_left_cap_3 | ||
| 106 | &pmx_led_right_cap_0 &pmx_led_right_cap_1 | ||
| 107 | &pmx_led_right_cap_2 &pmx_led_right_cap_3 | ||
| 108 | >; | ||
| 109 | pinctrl-names = "default"; | ||
| 112 | 110 | ||
| 113 | health { | 111 | health { |
| 114 | label = "status:green:health"; | 112 | label = "status:green:health"; |
| @@ -156,6 +154,8 @@ | |||
| 156 | compatible = "simple-bus"; | 154 | compatible = "simple-bus"; |
| 157 | #address-cells = <1>; | 155 | #address-cells = <1>; |
| 158 | #size-cells = <0>; | 156 | #size-cells = <0>; |
| 157 | pinctrl-0 = <&pmx_usb_power_enable>; | ||
| 158 | pinctrl-names = "default"; | ||
| 159 | 159 | ||
| 160 | usb_power: regulator@1 { | 160 | usb_power: regulator@1 { |
| 161 | compatible = "regulator-fixed"; | 161 | compatible = "regulator-fixed"; |
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 44fd97dfc1f3..1e642f39b154 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | |||
| @@ -18,11 +18,6 @@ | |||
| 18 | 18 | ||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | |||
| 22 | pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g | ||
| 23 | &pmx_led_wmode_r &pmx_led_wmode_g >; | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | |||
| 26 | pmx_led_health_r: pmx-led-health-r { | 21 | pmx_led_health_r: pmx-led-health-r { |
| 27 | marvell,pins = "mpp46"; | 22 | marvell,pins = "mpp46"; |
| 28 | marvell,function = "gpio"; | 23 | marvell,function = "gpio"; |
| @@ -72,11 +67,16 @@ | |||
| 72 | 67 | ||
| 73 | mvsdio@90000 { | 68 | mvsdio@90000 { |
| 74 | status = "okay"; | 69 | status = "okay"; |
| 70 | /* No CD or WP GPIOs */ | ||
| 71 | broken-cd; | ||
| 75 | }; | 72 | }; |
| 76 | }; | 73 | }; |
| 77 | 74 | ||
| 78 | gpio-leds { | 75 | gpio-leds { |
| 79 | compatible = "gpio-leds"; | 76 | compatible = "gpio-leds"; |
| 77 | pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g | ||
| 78 | &pmx_led_wmode_r &pmx_led_wmode_g >; | ||
| 79 | pinctrl-names = "default"; | ||
| 80 | 80 | ||
| 81 | health-r { | 81 | health-r { |
| 82 | label = "guruplug:red:health"; | 82 | label = "guruplug:red:health"; |
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index 5335b1aa8601..20c4b081f420 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts | |||
| @@ -18,13 +18,6 @@ | |||
| 18 | 18 | ||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | |||
| 22 | pinctrl-0 = < &pmx_nand | ||
| 23 | &pmx_led_os_red &pmx_power_off | ||
| 24 | &pmx_led_os_green &pmx_led_usb_transfer | ||
| 25 | &pmx_button_reset &pmx_button_usb_copy >; | ||
| 26 | pinctrl-names = "default"; | ||
| 27 | |||
| 28 | pmx_led_os_red: pmx-led-os-red { | 21 | pmx_led_os_red: pmx-led-os-red { |
| 29 | marvell,pins = "mpp22"; | 22 | marvell,pins = "mpp22"; |
| 30 | marvell,function = "gpio"; | 23 | marvell,function = "gpio"; |
| @@ -61,6 +54,8 @@ | |||
| 61 | 54 | ||
| 62 | nand@3000000 { | 55 | nand@3000000 { |
| 63 | status = "okay"; | 56 | status = "okay"; |
| 57 | pinctrl-0 = <&pmx_nand>; | ||
| 58 | pinctrl-names = "default"; | ||
| 64 | 59 | ||
| 65 | partition@0 { | 60 | partition@0 { |
| 66 | label = "u-boot"; | 61 | label = "u-boot"; |
| @@ -84,6 +79,9 @@ | |||
| 84 | compatible = "gpio-keys"; | 79 | compatible = "gpio-keys"; |
| 85 | #address-cells = <1>; | 80 | #address-cells = <1>; |
| 86 | #size-cells = <0>; | 81 | #size-cells = <0>; |
| 82 | pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; | ||
| 83 | pinctrl-names = "default"; | ||
| 84 | |||
| 87 | button@1 { | 85 | button@1 { |
| 88 | label = "USB Copy"; | 86 | label = "USB Copy"; |
| 89 | linux,code = <133>; | 87 | linux,code = <133>; |
| @@ -97,6 +95,9 @@ | |||
| 97 | }; | 95 | }; |
| 98 | gpio-leds { | 96 | gpio-leds { |
| 99 | compatible = "gpio-leds"; | 97 | compatible = "gpio-leds"; |
| 98 | pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green | ||
| 99 | &pmx_led_usb_transfer>; | ||
| 100 | pinctrl-names = "default"; | ||
| 100 | 101 | ||
| 101 | green-os { | 102 | green-os { |
| 102 | label = "ib62x0:green:os"; | 103 | label = "ib62x0:green:os"; |
| @@ -114,6 +115,8 @@ | |||
| 114 | }; | 115 | }; |
| 115 | gpio_poweroff { | 116 | gpio_poweroff { |
| 116 | compatible = "gpio-poweroff"; | 117 | compatible = "gpio-poweroff"; |
| 118 | pinctrl-0 = <&pmx_power_off>; | ||
| 119 | pinctrl-names = "default"; | ||
| 117 | gpios = <&gpio0 24 0>; | 120 | gpios = <&gpio0 24 0>; |
| 118 | }; | 121 | }; |
| 119 | 122 | ||
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index e591d5df769f..441204e8abc6 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts | |||
| @@ -20,51 +20,43 @@ | |||
| 20 | 20 | ||
| 21 | ocp@f1000000 { | 21 | ocp@f1000000 { |
| 22 | pinctrl: pinctrl@10000 { | 22 | pinctrl: pinctrl@10000 { |
| 23 | 23 | pmx_button_reset: pmx-button-reset { | |
| 24 | pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35 | ||
| 25 | &pmx_gpio_41 &pmx_gpio_42 | ||
| 26 | &pmx_gpio_43 &pmx_gpio_44 | ||
| 27 | &pmx_gpio_45 &pmx_gpio_46 | ||
| 28 | &pmx_gpio_47 &pmx_gpio_48 >; | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | |||
| 31 | pmx_gpio_12: pmx-gpio-12 { | ||
| 32 | marvell,pins = "mpp12"; | 24 | marvell,pins = "mpp12"; |
| 33 | marvell,function = "gpio"; | 25 | marvell,function = "gpio"; |
| 34 | }; | 26 | }; |
| 35 | pmx_gpio_35: pmx-gpio-35 { | 27 | pmx_button_otb: pmx-button-otb { |
| 36 | marvell,pins = "mpp35"; | 28 | marvell,pins = "mpp35"; |
| 37 | marvell,function = "gpio"; | 29 | marvell,function = "gpio"; |
| 38 | }; | 30 | }; |
| 39 | pmx_gpio_41: pmx-gpio-41 { | 31 | pmx_led_level: pmx-led-level { |
| 40 | marvell,pins = "mpp41"; | 32 | marvell,pins = "mpp41"; |
| 41 | marvell,function = "gpio"; | 33 | marvell,function = "gpio"; |
| 42 | }; | 34 | }; |
| 43 | pmx_gpio_42: pmx-gpio-42 { | 35 | pmx_led_power_blue: pmx-led-power-blue { |
| 44 | marvell,pins = "mpp42"; | 36 | marvell,pins = "mpp42"; |
| 45 | marvell,function = "gpio"; | 37 | marvell,function = "gpio"; |
| 46 | }; | 38 | }; |
| 47 | pmx_gpio_43: pmx-gpio-43 { | 39 | pmx_led_power_red: pmx-power-red { |
| 48 | marvell,pins = "mpp43"; | 40 | marvell,pins = "mpp43"; |
| 49 | marvell,function = "gpio"; | 41 | marvell,function = "gpio"; |
| 50 | }; | 42 | }; |
| 51 | pmx_gpio_44: pmx-gpio-44 { | 43 | pmx_led_usb1: pmx-led-usb1 { |
| 52 | marvell,pins = "mpp44"; | 44 | marvell,pins = "mpp44"; |
| 53 | marvell,function = "gpio"; | 45 | marvell,function = "gpio"; |
| 54 | }; | 46 | }; |
| 55 | pmx_gpio_45: pmx-gpio-45 { | 47 | pmx_led_usb2: pmx-led-usb2 { |
| 56 | marvell,pins = "mpp45"; | 48 | marvell,pins = "mpp45"; |
| 57 | marvell,function = "gpio"; | 49 | marvell,function = "gpio"; |
| 58 | }; | 50 | }; |
| 59 | pmx_gpio_46: pmx-gpio-46 { | 51 | pmx_led_usb3: pmx-led-usb3 { |
| 60 | marvell,pins = "mpp46"; | 52 | marvell,pins = "mpp46"; |
| 61 | marvell,function = "gpio"; | 53 | marvell,function = "gpio"; |
| 62 | }; | 54 | }; |
| 63 | pmx_gpio_47: pmx-gpio-47 { | 55 | pmx_led_usb4: pmx-led-usb4 { |
| 64 | marvell,pins = "mpp47"; | 56 | marvell,pins = "mpp47"; |
| 65 | marvell,function = "gpio"; | 57 | marvell,function = "gpio"; |
| 66 | }; | 58 | }; |
| 67 | pmx_gpio_48: pmx-gpio-48 { | 59 | pmx_led_otb: pmx-led-otb { |
| 68 | marvell,pins = "mpp48"; | 60 | marvell,pins = "mpp48"; |
| 69 | marvell,function = "gpio"; | 61 | marvell,function = "gpio"; |
| 70 | }; | 62 | }; |
| @@ -121,6 +113,11 @@ | |||
| 121 | 113 | ||
| 122 | gpio-leds { | 114 | gpio-leds { |
| 123 | compatible = "gpio-leds"; | 115 | compatible = "gpio-leds"; |
| 116 | pinctrl-0 = < &pmx_led_level &pmx_led_power_blue | ||
| 117 | &pmx_led_power_red &pmx_led_usb1 | ||
| 118 | &pmx_led_usb2 &pmx_led_usb3 | ||
| 119 | &pmx_led_usb4 &pmx_led_otb >; | ||
| 120 | pinctrl-names = "default"; | ||
| 124 | 121 | ||
| 125 | led-level { | 122 | led-level { |
| 126 | label = "led_level"; | 123 | label = "led_level"; |
| @@ -162,6 +159,9 @@ | |||
| 162 | compatible = "gpio-keys"; | 159 | compatible = "gpio-keys"; |
| 163 | #address-cells = <1>; | 160 | #address-cells = <1>; |
| 164 | #size-cells = <0>; | 161 | #size-cells = <0>; |
| 162 | pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; | ||
| 163 | pinctrl-names = "default"; | ||
| 164 | |||
| 165 | button@1 { | 165 | button@1 { |
| 166 | label = "OTB Button"; | 166 | label = "OTB Button"; |
| 167 | linux,code = <133>; | 167 | linux,code = <133>; |
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 3694e94f6e99..00a7bfe5e83b 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | |||
| @@ -18,12 +18,7 @@ | |||
| 18 | 18 | ||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | 21 | pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 | |
| 22 | pinctrl-0 = < &pmx_button_reset &pmx_button_power | ||
| 23 | &pmx_led_backup &pmx_led_power | ||
| 24 | &pmx_button_otb &pmx_led_rebuild | ||
| 25 | &pmx_led_health | ||
| 26 | &pmx_led_sata_brt_ctrl_1 | ||
| 27 | &pmx_led_sata_brt_ctrl_2 | 22 | &pmx_led_sata_brt_ctrl_2 |
| 28 | &pmx_led_backup_brt_ctrl_1 | 23 | &pmx_led_backup_brt_ctrl_1 |
| 29 | &pmx_led_backup_brt_ctrl_2 | 24 | &pmx_led_backup_brt_ctrl_2 |
| @@ -151,6 +146,9 @@ | |||
| 151 | }; | 146 | }; |
| 152 | gpio-leds { | 147 | gpio-leds { |
| 153 | compatible = "gpio-leds"; | 148 | compatible = "gpio-leds"; |
| 149 | pinctrl-0 = < &pmx_led_backup &pmx_led_power | ||
| 150 | &pmx_led_rebuild &pmx_led_health >; | ||
| 151 | pinctrl-names = "default"; | ||
| 154 | 152 | ||
| 155 | power_led { | 153 | power_led { |
| 156 | label = "status:white:power_led"; | 154 | label = "status:white:power_led"; |
| @@ -174,6 +172,11 @@ | |||
| 174 | compatible = "gpio-keys"; | 172 | compatible = "gpio-keys"; |
| 175 | #address-cells = <1>; | 173 | #address-cells = <1>; |
| 176 | #size-cells = <0>; | 174 | #size-cells = <0>; |
| 175 | pinctrl-0 = <&pmx_button_reset &pmx_button_power | ||
| 176 | &pmx_button_otb>; | ||
| 177 | pinctrl-names = "default"; | ||
| 178 | |||
| 179 | |||
| 177 | Power { | 180 | Power { |
| 178 | label = "Power Button"; | 181 | label = "Power Button"; |
| 179 | linux,code = <116>; | 182 | linux,code = <116>; |
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts index 0bdce0ad7277..c3f036b86cca 100644 --- a/arch/arm/boot/dts/kirkwood-is2.dts +++ b/arch/arm/boot/dts/kirkwood-is2.dts | |||
| @@ -13,6 +13,8 @@ | |||
| 13 | 13 | ||
| 14 | ocp@f1000000 { | 14 | ocp@f1000000 { |
| 15 | sata@80000 { | 15 | sata@80000 { |
| 16 | pinctrl-0 = <&pmx_ns2_sata0>; | ||
| 17 | pinctrl-names = "default"; | ||
| 16 | status = "okay"; | 18 | status = "okay"; |
| 17 | nr-ports = <1>; | 19 | nr-ports = <1>; |
| 18 | }; | 20 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 5bbd0542cdd3..5d9f5ea78700 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts | |||
| @@ -18,9 +18,7 @@ | |||
| 18 | 18 | ||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | 21 | pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; | |
| 22 | pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda | ||
| 23 | &pmx_i2c_gpio_scl >; | ||
| 24 | pinctrl-names = "default"; | 22 | pinctrl-names = "default"; |
| 25 | 23 | ||
| 26 | pmx_i2c_gpio_sda: pmx-gpio-sda { | 24 | pmx_i2c_gpio_sda: pmx-gpio-sda { |
| @@ -38,8 +36,17 @@ | |||
| 38 | }; | 36 | }; |
| 39 | 37 | ||
| 40 | nand@3000000 { | 38 | nand@3000000 { |
| 39 | pinctrl-0 = <&pmx_nand>; | ||
| 40 | pinctrl-names = "default"; | ||
| 41 | status = "ok"; | 41 | status = "ok"; |
| 42 | chip-delay = <25>; | 42 | chip-delay = <25>; |
| 43 | }; | 43 | }; |
| 44 | }; | 44 | }; |
| 45 | |||
| 46 | i2c@0 { | ||
| 47 | compatible = "i2c-gpio"; | ||
| 48 | gpios = < &gpio0 8 0 /* sda */ | ||
| 49 | &gpio0 9 0 >; /* scl */ | ||
| 50 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | ||
| 51 | }; | ||
| 45 | }; | 52 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 996c7fefd253..31b17f5b9d28 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi | |||
| @@ -8,16 +8,6 @@ | |||
| 8 | 8 | ||
| 9 | ocp@f1000000 { | 9 | ocp@f1000000 { |
| 10 | pinctrl: pinctrl@10000 { | 10 | pinctrl: pinctrl@10000 { |
| 11 | |||
| 12 | pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus | ||
| 13 | &pmx_fan_low &pmx_fan_high | ||
| 14 | &pmx_led_function_red &pmx_led_alarm | ||
| 15 | &pmx_led_info &pmx_led_power | ||
| 16 | &pmx_fan_lock &pmx_button_function | ||
| 17 | &pmx_power_switch &pmx_power_auto_switch | ||
| 18 | &pmx_led_function_blue >; | ||
| 19 | pinctrl-names = "default"; | ||
| 20 | |||
| 21 | pmx_power_hdd: pmx-power-hdd { | 11 | pmx_power_hdd: pmx-power-hdd { |
| 22 | marvell,pins = "mpp10"; | 12 | marvell,pins = "mpp10"; |
| 23 | marvell,function = "gpo"; | 13 | marvell,function = "gpo"; |
| @@ -112,6 +102,10 @@ | |||
| 112 | compatible = "gpio-keys"; | 102 | compatible = "gpio-keys"; |
| 113 | #address-cells = <1>; | 103 | #address-cells = <1>; |
| 114 | #size-cells = <0>; | 104 | #size-cells = <0>; |
| 105 | pinctrl-0 = <&pmx_button_function &pmx_power_switch | ||
| 106 | &pmx_power_auto_switch>; | ||
| 107 | pinctrl-names = "default"; | ||
| 108 | |||
| 115 | button@1 { | 109 | button@1 { |
| 116 | label = "Function Button"; | 110 | label = "Function Button"; |
| 117 | linux,code = <357>; | 111 | linux,code = <357>; |
| @@ -133,6 +127,10 @@ | |||
| 133 | 127 | ||
| 134 | gpio_leds { | 128 | gpio_leds { |
| 135 | compatible = "gpio-leds"; | 129 | compatible = "gpio-leds"; |
| 130 | pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm | ||
| 131 | &pmx_led_info &pmx_led_power | ||
| 132 | &pmx_led_function_blue>; | ||
| 133 | pinctrl-names = "default"; | ||
| 136 | 134 | ||
| 137 | led@1 { | 135 | led@1 { |
| 138 | label = "lsxl:blue:func"; | 136 | label = "lsxl:blue:func"; |
| @@ -163,6 +161,8 @@ | |||
| 163 | 161 | ||
| 164 | gpio_fan { | 162 | gpio_fan { |
| 165 | compatible = "gpio-fan"; | 163 | compatible = "gpio-fan"; |
| 164 | pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; | ||
| 165 | pinctrl-names = "default"; | ||
| 166 | gpios = <&gpio0 19 1 | 166 | gpios = <&gpio0 19 1 |
| 167 | &gpio0 18 1>; | 167 | &gpio0 18 1>; |
| 168 | gpio-fan,speed-map = <0 3 | 168 | gpio-fan,speed-map = <0 3 |
| @@ -180,6 +180,8 @@ | |||
| 180 | compatible = "simple-bus"; | 180 | compatible = "simple-bus"; |
| 181 | #address-cells = <1>; | 181 | #address-cells = <1>; |
| 182 | #size-cells = <0>; | 182 | #size-cells = <0>; |
| 183 | pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>; | ||
| 184 | pinctrl-names = "default"; | ||
| 183 | 185 | ||
| 184 | usb_power: regulator@1 { | 186 | usb_power: regulator@1 { |
| 185 | compatible = "regulator-fixed"; | 187 | compatible = "regulator-fixed"; |
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 90501cf129bb..6179333fd71f 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts | |||
| @@ -18,16 +18,6 @@ | |||
| 18 | 18 | ||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | |||
| 22 | pinctrl-0 = < &pmx_nand &pmx_uart0 | ||
| 23 | &pmx_led_health | ||
| 24 | &pmx_sata0 &pmx_sata1 | ||
| 25 | &pmx_led_user1o | ||
| 26 | &pmx_led_user1g &pmx_led_user0o | ||
| 27 | &pmx_led_user0g &pmx_led_misc | ||
| 28 | >; | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | |||
| 31 | pmx_led_health: pmx-led-health { | 21 | pmx_led_health: pmx-led-health { |
| 32 | marvell,pins = "mpp7"; | 22 | marvell,pins = "mpp7"; |
| 33 | marvell,function = "gpo"; | 23 | marvell,function = "gpo"; |
| @@ -91,9 +81,13 @@ | |||
| 91 | 81 | ||
| 92 | serial@12000 { | 82 | serial@12000 { |
| 93 | status = "ok"; | 83 | status = "ok"; |
| 84 | pinctrl-0 = <&pmx_uart0>; | ||
| 85 | pinctrl-names = "default"; | ||
| 94 | }; | 86 | }; |
| 95 | 87 | ||
| 96 | nand@3000000 { | 88 | nand@3000000 { |
| 89 | pinctrl-0 = <&pmx_nand>; | ||
| 90 | pinctrl-names = "default"; | ||
| 97 | status = "okay"; | 91 | status = "okay"; |
| 98 | 92 | ||
| 99 | partition@0 { | 93 | partition@0 { |
| @@ -127,16 +121,17 @@ | |||
| 127 | }; | 121 | }; |
| 128 | 122 | ||
| 129 | sata@80000 { | 123 | sata@80000 { |
| 124 | pinctrl-0 = <&pmx_sata0 &pmx_sata1>; | ||
| 125 | pinctrl-names = "default"; | ||
| 130 | nr-ports = <2>; | 126 | nr-ports = <2>; |
| 131 | status = "okay"; | 127 | status = "okay"; |
| 132 | |||
| 133 | }; | 128 | }; |
| 134 | 129 | ||
| 135 | mvsdio@90000 { | 130 | mvsdio@90000 { |
| 136 | pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; | 131 | pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; |
| 137 | pinctrl-names = "default"; | 132 | pinctrl-names = "default"; |
| 138 | status = "okay"; | 133 | status = "okay"; |
| 139 | cd-gpios = <&gpio1 15 0>; | 134 | cd-gpios = <&gpio1 15 1>; |
| 140 | /* No WP GPIO */ | 135 | /* No WP GPIO */ |
| 141 | }; | 136 | }; |
| 142 | 137 | ||
| @@ -151,6 +146,12 @@ | |||
| 151 | 146 | ||
| 152 | gpio-leds { | 147 | gpio-leds { |
| 153 | compatible = "gpio-leds"; | 148 | compatible = "gpio-leds"; |
| 149 | pinctrl-0 = < &pmx_led_health | ||
| 150 | &pmx_led_user1o | ||
| 151 | &pmx_led_user1g &pmx_led_user0o | ||
| 152 | &pmx_led_user0g &pmx_led_misc | ||
| 153 | >; | ||
| 154 | pinctrl-names = "default"; | ||
| 154 | 155 | ||
| 155 | health { | 156 | health { |
| 156 | label = "status:green:health"; | 157 | label = "status:green:health"; |
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 0f852b40f5c1..ad6ade7d9191 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | |||
| @@ -18,18 +18,6 @@ | |||
| 18 | 18 | ||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | |||
| 22 | pinctrl-0 = < &pmx_uart0 | ||
| 23 | &pmx_button_power | ||
| 24 | &pmx_button_backup | ||
| 25 | &pmx_button_reset | ||
| 26 | &pmx_led_blue_power | ||
| 27 | &pmx_led_blue_activity | ||
| 28 | &pmx_led_blue_disk1 | ||
| 29 | &pmx_led_blue_disk2 | ||
| 30 | &pmx_led_blue_backup >; | ||
| 31 | pinctrl-names = "default"; | ||
| 32 | |||
| 33 | pmx_button_power: pmx-button-power { | 21 | pmx_button_power: pmx-button-power { |
| 34 | marvell,pins = "mpp47"; | 22 | marvell,pins = "mpp47"; |
| 35 | marvell,function = "gpio"; | 23 | marvell,function = "gpio"; |
| @@ -74,6 +62,8 @@ | |||
| 74 | }; | 62 | }; |
| 75 | 63 | ||
| 76 | serial@12000 { | 64 | serial@12000 { |
| 65 | pinctrl-0 = <&pmx_uart0>; | ||
| 66 | pinctrl-names = "default"; | ||
| 77 | status = "okay"; | 67 | status = "okay"; |
| 78 | }; | 68 | }; |
| 79 | 69 | ||
| @@ -123,6 +113,10 @@ | |||
| 123 | 113 | ||
| 124 | gpio-leds { | 114 | gpio-leds { |
| 125 | compatible = "gpio-leds"; | 115 | compatible = "gpio-leds"; |
| 116 | pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity | ||
| 117 | &pmx_led_blue_disk1 &pmx_led_blue_disk2 | ||
| 118 | &pmx_led_blue_backup >; | ||
| 119 | pinctrl-names = "default"; | ||
| 126 | 120 | ||
| 127 | power_led { | 121 | power_led { |
| 128 | label = "status:blue:power_led"; | 122 | label = "status:blue:power_led"; |
| @@ -151,6 +145,10 @@ | |||
| 151 | compatible = "gpio-keys"; | 145 | compatible = "gpio-keys"; |
| 152 | #address-cells = <1>; | 146 | #address-cells = <1>; |
| 153 | #size-cells = <0>; | 147 | #size-cells = <0>; |
| 148 | pinctrl-0 = <&pmx_button_power &pmx_button_backup | ||
| 149 | &pmx_button_reset>; | ||
| 150 | pinctrl-names = "default"; | ||
| 151 | |||
| 154 | button@1 { | 152 | button@1 { |
| 155 | label = "Power Button"; | 153 | label = "Power Button"; |
| 156 | linux,code = <116>; /* KEY_POWER */ | 154 | linux,code = <116>; /* KEY_POWER */ |
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 6affd924fe11..2afac0405816 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi | |||
| @@ -8,10 +8,6 @@ | |||
| 8 | 8 | ||
| 9 | ocp@f1000000 { | 9 | ocp@f1000000 { |
| 10 | pinctrl: pinctrl@10000 { | 10 | pinctrl: pinctrl@10000 { |
| 11 | pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0 | ||
| 12 | &pmx_ns2_sata0 &pmx_ns2_sata1>; | ||
| 13 | pinctrl-names = "default"; | ||
| 14 | |||
| 15 | pmx_ns2_sata0: pmx-ns2-sata0 { | 11 | pmx_ns2_sata0: pmx-ns2-sata0 { |
| 16 | marvell,pins = "mpp21"; | 12 | marvell,pins = "mpp21"; |
| 17 | marvell,function = "sata0"; | 13 | marvell,function = "sata0"; |
| @@ -23,10 +19,14 @@ | |||
| 23 | }; | 19 | }; |
| 24 | 20 | ||
| 25 | serial@12000 { | 21 | serial@12000 { |
| 22 | pinctrl-0 = <&pmx_uart0>; | ||
| 23 | pinctrl-names = "default"; | ||
| 26 | status = "okay"; | 24 | status = "okay"; |
| 27 | }; | 25 | }; |
| 28 | 26 | ||
| 29 | spi@10600 { | 27 | spi@10600 { |
| 28 | pinctrl-0 = <&pmx_spi>; | ||
| 29 | pinctrl-names = "default"; | ||
| 30 | status = "okay"; | 30 | status = "okay"; |
| 31 | 31 | ||
| 32 | flash@0 { | 32 | flash@0 { |
| @@ -45,6 +45,8 @@ | |||
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| 47 | i2c@11000 { | 47 | i2c@11000 { |
| 48 | pinctrl-0 = <&pmx_twsi0>; | ||
| 49 | pinctrl-names = "default"; | ||
| 48 | status = "okay"; | 50 | status = "okay"; |
| 49 | 51 | ||
| 50 | eeprom@50 { | 52 | eeprom@50 { |
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts index f2d36ecf36d8..b50e93d7796c 100644 --- a/arch/arm/boot/dts/kirkwood-ns2.dts +++ b/arch/arm/boot/dts/kirkwood-ns2.dts | |||
| @@ -13,6 +13,8 @@ | |||
| 13 | 13 | ||
| 14 | ocp@f1000000 { | 14 | ocp@f1000000 { |
| 15 | sata@80000 { | 15 | sata@80000 { |
| 16 | pinctrl-0 = <&pmx_ns2_sata0>; | ||
| 17 | pinctrl-names = "default"; | ||
| 16 | status = "okay"; | 18 | status = "okay"; |
| 17 | nr-ports = <1>; | 19 | nr-ports = <1>; |
| 18 | }; | 20 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts index b02eb4ea1bb4..af8259fe8955 100644 --- a/arch/arm/boot/dts/kirkwood-ns2lite.dts +++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts | |||
| @@ -13,6 +13,8 @@ | |||
| 13 | 13 | ||
| 14 | ocp@f1000000 { | 14 | ocp@f1000000 { |
| 15 | sata@80000 { | 15 | sata@80000 { |
| 16 | pinctrl-0 = <&pmx_ns2_sata0>; | ||
| 17 | pinctrl-names = "default"; | ||
| 16 | status = "okay"; | 18 | status = "okay"; |
| 17 | nr-ports = <1>; | 19 | nr-ports = <1>; |
| 18 | }; | 20 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts index bcec4d6cada7..85f24d227e17 100644 --- a/arch/arm/boot/dts/kirkwood-ns2max.dts +++ b/arch/arm/boot/dts/kirkwood-ns2max.dts | |||
| @@ -13,6 +13,8 @@ | |||
| 13 | 13 | ||
| 14 | ocp@f1000000 { | 14 | ocp@f1000000 { |
| 15 | sata@80000 { | 15 | sata@80000 { |
| 16 | pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>; | ||
| 17 | pinctrl-names = "default"; | ||
| 16 | status = "okay"; | 18 | status = "okay"; |
| 17 | nr-ports = <2>; | 19 | nr-ports = <2>; |
| 18 | }; | 20 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts index adab1ab25733..329e530bffe7 100644 --- a/arch/arm/boot/dts/kirkwood-ns2mini.dts +++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts | |||
| @@ -14,6 +14,8 @@ | |||
| 14 | 14 | ||
| 15 | ocp@f1000000 { | 15 | ocp@f1000000 { |
| 16 | sata@80000 { | 16 | sata@80000 { |
| 17 | pinctrl-0 = <&pmx_ns2_sata0>; | ||
| 18 | pinctrl-names = "default"; | ||
| 17 | status = "okay"; | 19 | status = "okay"; |
| 18 | nr-ports = <1>; | 20 | nr-ports = <1>; |
| 19 | }; | 21 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 9ddf218f2cbd..69003598f5fa 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "kirkwood.dtsi" | 3 | /include/ "kirkwood.dtsi" |
| 4 | /include/ "kirkwood-6281.dtsi" | ||
| 4 | 5 | ||
| 5 | / { | 6 | / { |
| 6 | model = "ZyXEL NSA310"; | 7 | model = "ZyXEL NSA310"; |
| @@ -17,22 +18,7 @@ | |||
| 17 | 18 | ||
| 18 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 19 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 20 | pinctrl-0 = < &pmx_led_esata_green | 21 | pinctrl-0 = <&pmx_unknown>; |
| 21 | &pmx_led_esata_red | ||
| 22 | &pmx_led_usb_green | ||
| 23 | &pmx_led_usb_red | ||
| 24 | &pmx_usb_power_off | ||
| 25 | &pmx_led_sys_green | ||
| 26 | &pmx_led_sys_red | ||
| 27 | &pmx_btn_reset | ||
| 28 | &pmx_btn_copy | ||
| 29 | &pmx_led_copy_green | ||
| 30 | &pmx_led_copy_red | ||
| 31 | &pmx_led_hdd_green | ||
| 32 | &pmx_led_hdd_red | ||
| 33 | &pmx_unknown | ||
| 34 | &pmx_btn_power | ||
| 35 | &pmx_pwr_off >; | ||
| 36 | pinctrl-names = "default"; | 22 | pinctrl-names = "default"; |
| 37 | 23 | ||
| 38 | pmx_led_esata_green: pmx-led-esata-green { | 24 | pmx_led_esata_green: pmx-led-esata-green { |
| @@ -190,6 +176,8 @@ | |||
| 190 | compatible = "gpio-keys"; | 176 | compatible = "gpio-keys"; |
| 191 | #address-cells = <1>; | 177 | #address-cells = <1>; |
| 192 | #size-cells = <0>; | 178 | #size-cells = <0>; |
| 179 | pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; | ||
| 180 | pinctrl-names = "default"; | ||
| 193 | 181 | ||
| 194 | button@1 { | 182 | button@1 { |
| 195 | label = "Power Button"; | 183 | label = "Power Button"; |
| @@ -210,6 +198,12 @@ | |||
| 210 | 198 | ||
| 211 | gpio-leds { | 199 | gpio-leds { |
| 212 | compatible = "gpio-leds"; | 200 | compatible = "gpio-leds"; |
| 201 | pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red | ||
| 202 | &pmx_led_usb_green &pmx_led_usb_red | ||
| 203 | &pmx_led_sys_green &pmx_led_sys_red | ||
| 204 | &pmx_led_copy_green &pmx_led_copy_red | ||
| 205 | &pmx_led_hdd_green &pmx_led_hdd_red>; | ||
| 206 | pinctrl-names = "default"; | ||
| 213 | 207 | ||
| 214 | green-sys { | 208 | green-sys { |
| 215 | label = "nsa310:green:sys"; | 209 | label = "nsa310:green:sys"; |
| @@ -255,6 +249,8 @@ | |||
| 255 | 249 | ||
| 256 | gpio_poweroff { | 250 | gpio_poweroff { |
| 257 | compatible = "gpio-poweroff"; | 251 | compatible = "gpio-poweroff"; |
| 252 | pinctrl-0 = <&pmx_pwr_off>; | ||
| 253 | pinctrl-names = "default"; | ||
| 258 | gpios = <&gpio1 16 0>; | 254 | gpios = <&gpio1 16 0>; |
| 259 | }; | 255 | }; |
| 260 | 256 | ||
| @@ -262,6 +258,8 @@ | |||
| 262 | compatible = "simple-bus"; | 258 | compatible = "simple-bus"; |
| 263 | #address-cells = <1>; | 259 | #address-cells = <1>; |
| 264 | #size-cells = <0>; | 260 | #size-cells = <0>; |
| 261 | pinctrl-0 = <&pmx_usb_power_off>; | ||
| 262 | pinctrl-names = "default"; | ||
| 265 | 263 | ||
| 266 | usb0_power_off: regulator@1 { | 264 | usb0_power_off: regulator@1 { |
| 267 | compatible = "regulator-fixed"; | 265 | compatible = "regulator-fixed"; |
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index d27f7245f8e7..38dc8517d777 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts | |||
| @@ -19,15 +19,21 @@ | |||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | serial@12000 { | 20 | serial@12000 { |
| 21 | status = "ok"; | 21 | status = "ok"; |
| 22 | pinctrl-0 = <&pmx_uart0>; | ||
| 23 | pinctrl-names = "default"; | ||
| 22 | }; | 24 | }; |
| 23 | 25 | ||
| 24 | serial@12100 { | 26 | serial@12100 { |
| 25 | status = "ok"; | 27 | status = "ok"; |
| 28 | pinctrl-0 = <&pmx_uart1>; | ||
| 29 | pinctrl-names = "default"; | ||
| 26 | }; | 30 | }; |
| 27 | 31 | ||
| 28 | nand@3000000 { | 32 | nand@3000000 { |
| 29 | chip-delay = <25>; | 33 | chip-delay = <25>; |
| 30 | status = "okay"; | 34 | status = "okay"; |
| 35 | pinctrl-0 = <&pmx_nand>; | ||
| 36 | pinctrl-names = "default"; | ||
| 31 | 37 | ||
| 32 | partition@0 { | 38 | partition@0 { |
| 33 | label = "uboot"; | 39 | label = "uboot"; |
| @@ -67,6 +73,8 @@ | |||
| 67 | 73 | ||
| 68 | i2c@11100 { | 74 | i2c@11100 { |
| 69 | status = "okay"; | 75 | status = "okay"; |
| 76 | pinctrl-0 = <&pmx_twsi1>; | ||
| 77 | pinctrl-names = "default"; | ||
| 70 | 78 | ||
| 71 | s35390a: s35390a@30 { | 79 | s35390a: s35390a@30 { |
| 72 | compatible = "s35390a"; | 80 | compatible = "s35390a"; |
| @@ -75,16 +83,7 @@ | |||
| 75 | }; | 83 | }; |
| 76 | 84 | ||
| 77 | pinctrl: pinctrl@10000 { | 85 | pinctrl: pinctrl@10000 { |
| 78 | pinctrl-0 = < &pmx_nand &pmx_uart0 | 86 | pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; |
| 79 | &pmx_uart1 &pmx_twsi1 | ||
| 80 | &pmx_dip_sw0 &pmx_dip_sw1 | ||
| 81 | &pmx_dip_sw2 &pmx_dip_sw3 | ||
| 82 | &pmx_gpio_0 &pmx_gpio_1 | ||
| 83 | &pmx_gpio_2 &pmx_gpio_3 | ||
| 84 | &pmx_gpio_4 &pmx_gpio_5 | ||
| 85 | &pmx_gpio_6 &pmx_gpio_7 | ||
| 86 | &pmx_led_red &pmx_led_green | ||
| 87 | &pmx_led_yellow >; | ||
| 88 | pinctrl-names = "default"; | 87 | pinctrl-names = "default"; |
| 89 | 88 | ||
| 90 | pmx_uart0: pmx-uart0 { | 89 | pmx_uart0: pmx-uart0 { |
| @@ -104,63 +103,14 @@ | |||
| 104 | marvell,function = "sysrst"; | 103 | marvell,function = "sysrst"; |
| 105 | }; | 104 | }; |
| 106 | 105 | ||
| 107 | pmx_dip_sw0: pmx-dip-sw0 { | 106 | pmx_dip_switches: pmx-dip-switches { |
| 108 | marvell,pins = "mpp20"; | 107 | marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23"; |
| 109 | marvell,function = "gpio"; | ||
| 110 | }; | ||
| 111 | |||
| 112 | pmx_dip_sw1: pmx-dip-sw1 { | ||
| 113 | marvell,pins = "mpp21"; | ||
| 114 | marvell,function = "gpio"; | ||
| 115 | }; | ||
| 116 | |||
| 117 | pmx_dip_sw2: pmx-dip-sw2 { | ||
| 118 | marvell,pins = "mpp22"; | ||
| 119 | marvell,function = "gpio"; | ||
| 120 | }; | ||
| 121 | |||
| 122 | pmx_dip_sw3: pmx-dip-sw3 { | ||
| 123 | marvell,pins = "mpp23"; | ||
| 124 | marvell,function = "gpio"; | ||
| 125 | }; | ||
| 126 | |||
| 127 | pmx_gpio_0: pmx-gpio-0 { | ||
| 128 | marvell,pins = "mpp24"; | ||
| 129 | marvell,function = "gpio"; | ||
| 130 | }; | ||
| 131 | |||
| 132 | pmx_gpio_1: pmx-gpio-1 { | ||
| 133 | marvell,pins = "mpp25"; | ||
| 134 | marvell,function = "gpio"; | ||
| 135 | }; | ||
| 136 | |||
| 137 | pmx_gpio_2: pmx-gpio-2 { | ||
| 138 | marvell,pins = "mpp26"; | ||
| 139 | marvell,function = "gpio"; | 108 | marvell,function = "gpio"; |
| 140 | }; | 109 | }; |
| 141 | 110 | ||
| 142 | pmx_gpio_3: pmx-gpio-3 { | 111 | pmx_gpio_header: pmx-gpio-header { |
| 143 | marvell,pins = "mpp27"; | 112 | marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27", |
| 144 | marvell,function = "gpio"; | 113 | "mpp28", "mpp29", "mpp30", "mpp31"; |
| 145 | }; | ||
| 146 | |||
| 147 | pmx_gpio_4: pmx-gpio-4 { | ||
| 148 | marvell,pins = "mpp28"; | ||
| 149 | marvell,function = "gpio"; | ||
| 150 | }; | ||
| 151 | |||
| 152 | pmx_gpio_5: pmx-gpio-5 { | ||
| 153 | marvell,pins = "mpp29"; | ||
| 154 | marvell,function = "gpio"; | ||
| 155 | }; | ||
| 156 | |||
| 157 | pmx_gpio_6: pmx-gpio-6 { | ||
| 158 | marvell,pins = "mpp30"; | ||
| 159 | marvell,function = "gpio"; | ||
| 160 | }; | ||
| 161 | |||
| 162 | pmx_gpio_7: pmx-gpio-7 { | ||
| 163 | marvell,pins = "mpp31"; | ||
| 164 | marvell,function = "gpio"; | 114 | marvell,function = "gpio"; |
| 165 | }; | 115 | }; |
| 166 | 116 | ||
| @@ -174,18 +124,8 @@ | |||
| 174 | marvell,function = "gpio"; | 124 | marvell,function = "gpio"; |
| 175 | }; | 125 | }; |
| 176 | 126 | ||
| 177 | pmx_led_red: pmx-led-red { | 127 | pmx_leds: pmx-leds { |
| 178 | marvell,pins = "mpp41"; | 128 | marvell,pins = "mpp41", "mpp42", "mpp43"; |
| 179 | marvell,function = "gpio"; | ||
| 180 | }; | ||
| 181 | |||
| 182 | pmx_led_green: pmx-led-green { | ||
| 183 | marvell,pins = "mpp42"; | ||
| 184 | marvell,function = "gpio"; | ||
| 185 | }; | ||
| 186 | |||
| 187 | pmx_led_yellow: pmx-led-yellow { | ||
| 188 | marvell,pins = "mpp43"; | ||
| 189 | marvell,function = "gpio"; | 129 | marvell,function = "gpio"; |
| 190 | }; | 130 | }; |
| 191 | }; | 131 | }; |
| @@ -193,6 +133,8 @@ | |||
| 193 | 133 | ||
| 194 | gpio-leds { | 134 | gpio-leds { |
| 195 | compatible = "gpio-leds"; | 135 | compatible = "gpio-leds"; |
| 136 | pinctrl-0 = <&pmx_leds>; | ||
| 137 | pinctrl-names = "default"; | ||
| 196 | 138 | ||
| 197 | led-red { | 139 | led-red { |
| 198 | label = "obsa6:red:stat"; | 140 | label = "obsa6:red:stat"; |
| @@ -209,4 +151,18 @@ | |||
| 209 | gpios = <&gpio1 11 1>; | 151 | gpios = <&gpio1 11 1>; |
| 210 | }; | 152 | }; |
| 211 | }; | 153 | }; |
| 154 | |||
| 155 | gpio_keys { | ||
| 156 | compatible = "gpio-keys"; | ||
| 157 | pinctrl-0 = <&pmx_gpio_init>; | ||
| 158 | pinctrl-names = "default"; | ||
| 159 | #address-cells = <1>; | ||
| 160 | #size-cells = <0>; | ||
| 161 | |||
| 162 | button@1 { | ||
| 163 | label = "Init Button"; | ||
| 164 | linux,code = <116>; | ||
| 165 | gpios = <&gpio1 6 0>; | ||
| 166 | }; | ||
| 167 | }; | ||
| 212 | }; | 168 | }; |
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi new file mode 100644 index 000000000000..f7143f128504 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi | |||
| @@ -0,0 +1,93 @@ | |||
| 1 | /* | ||
| 2 | * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 | ||
| 7 | */ | ||
| 8 | |||
| 9 | /include/ "kirkwood.dtsi" | ||
| 10 | /include/ "kirkwood-6281.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | memory { | ||
| 14 | device_type = "memory"; | ||
| 15 | reg = <0x00000000 0x20000000>; | ||
| 16 | }; | ||
| 17 | |||
| 18 | chosen { | ||
| 19 | bootargs = "console=ttyS0,115200n8 earlyprintk"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | ocp@f1000000 { | ||
| 23 | pinctrl: pinctrl@10000 { | ||
| 24 | |||
| 25 | pmx_usb_power_enable: pmx-usb-power-enable { | ||
| 26 | marvell,pins = "mpp29"; | ||
| 27 | marvell,function = "gpio"; | ||
| 28 | }; | ||
| 29 | pmx_led_red: pmx-led-red { | ||
| 30 | marvell,pins = "mpp46"; | ||
| 31 | marvell,function = "gpio"; | ||
| 32 | }; | ||
| 33 | pmx_led_blue: pmx-led-blue { | ||
| 34 | marvell,pins = "mpp49"; | ||
| 35 | marvell,function = "gpio"; | ||
| 36 | }; | ||
| 37 | pmx_sdio_cd: pmx-sdio-cd { | ||
| 38 | marvell,pins = "mpp44"; | ||
| 39 | marvell,function = "gpio"; | ||
| 40 | }; | ||
| 41 | pmx_sdio_wp: pmx-sdio-wp { | ||
| 42 | marvell,pins = "mpp47"; | ||
| 43 | marvell,function = "gpio"; | ||
| 44 | }; | ||
| 45 | }; | ||
| 46 | serial@12000 { | ||
| 47 | pinctrl-0 = <&pmx_uart0>; | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | status = "okay"; | ||
| 50 | }; | ||
| 51 | |||
| 52 | nand@3000000 { | ||
| 53 | pinctrl-0 = <&pmx_nand>; | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | status = "okay"; | ||
| 56 | |||
| 57 | partition@0 { | ||
| 58 | label = "u-boot"; | ||
| 59 | reg = <0x0000000 0x100000>; | ||
| 60 | }; | ||
| 61 | |||
| 62 | partition@100000 { | ||
| 63 | label = "uImage"; | ||
| 64 | reg = <0x0100000 0x400000>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | partition@500000 { | ||
| 68 | label = "root"; | ||
| 69 | reg = <0x0500000 0x1fb00000>; | ||
| 70 | }; | ||
| 71 | }; | ||
| 72 | }; | ||
| 73 | |||
| 74 | regulators { | ||
| 75 | compatible = "simple-bus"; | ||
| 76 | #address-cells = <1>; | ||
| 77 | #size-cells = <0>; | ||
| 78 | pinctrl-0 = <&pmx_usb_power_enable>; | ||
| 79 | pinctrl-names = "default"; | ||
| 80 | |||
| 81 | usb_power: regulator@1 { | ||
| 82 | compatible = "regulator-fixed"; | ||
| 83 | reg = <1>; | ||
| 84 | regulator-name = "USB Power"; | ||
| 85 | regulator-min-microvolt = <5000000>; | ||
| 86 | regulator-max-microvolt = <5000000>; | ||
| 87 | enable-active-high; | ||
| 88 | regulator-always-on; | ||
| 89 | regulator-boot-on; | ||
| 90 | gpio = <&gpio0 29 0>; | ||
| 91 | }; | ||
| 92 | }; | ||
| 93 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts new file mode 100644 index 000000000000..f620ce48de97 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /* | ||
| 2 | * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | /include/ "kirkwood-sheevaplug-common.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Globalscale Technologies eSATA SheevaPlug"; | ||
| 15 | compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 16 | |||
| 17 | ocp@f1000000 { | ||
| 18 | sata@80000 { | ||
| 19 | status = "okay"; | ||
| 20 | nr-ports = <2>; | ||
| 21 | }; | ||
| 22 | |||
| 23 | mvsdio@90000 { | ||
| 24 | pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; | ||
| 25 | pinctrl-names = "default"; | ||
| 26 | status = "okay"; | ||
| 27 | cd-gpios = <&gpio1 12 1>; | ||
| 28 | wp-gpios = <&gpio1 15 0>; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | |||
| 32 | gpio-leds { | ||
| 33 | compatible = "gpio-leds"; | ||
| 34 | pinctrl-0 = <&pmx_led_blue>; | ||
| 35 | pinctrl-names = "default"; | ||
| 36 | |||
| 37 | health { | ||
| 38 | label = "sheevaplug:blue:health"; | ||
| 39 | gpios = <&gpio1 17 1>; | ||
| 40 | linux,default-trigger = "default-on"; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts new file mode 100644 index 000000000000..bf1dff251432 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /* | ||
| 2 | * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com> | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 | ||
| 7 | */ | ||
| 8 | |||
| 9 | /dts-v1/; | ||
| 10 | |||
| 11 | /include/ "kirkwood-sheevaplug-common.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "Globalscale Technologies SheevaPlug"; | ||
| 15 | compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; | ||
| 16 | |||
| 17 | ocp@f1000000 { | ||
| 18 | mvsdio@90000 { | ||
| 19 | pinctrl-0 = <&pmx_sdio>; | ||
| 20 | pinctrl-names = "default"; | ||
| 21 | status = "okay"; | ||
| 22 | /* No CD or WP GPIOs */ | ||
| 23 | broken-cd; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | gpio-leds { | ||
| 28 | compatible = "gpio-leds"; | ||
| 29 | pinctrl-0 = <&pmx_led_blue &pmx_led_red>; | ||
| 30 | pinctrl-names = "default"; | ||
| 31 | |||
| 32 | health { | ||
| 33 | label = "sheevaplug:blue:health"; | ||
| 34 | gpios = <&gpio1 17 1>; | ||
| 35 | linux,default-trigger = "default-on"; | ||
| 36 | }; | ||
| 37 | |||
| 38 | misc { | ||
| 39 | label = "sheevaplug:red:misc"; | ||
| 40 | gpios = <&gpio1 14 1>; | ||
| 41 | }; | ||
| 42 | }; | ||
| 43 | }; | ||
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 66eb45b00b25..f2052d7bc10f 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts | |||
| @@ -19,18 +19,6 @@ | |||
| 19 | ocp@f1000000 { | 19 | ocp@f1000000 { |
| 20 | pinctrl: pinctrl@10000 { | 20 | pinctrl: pinctrl@10000 { |
| 21 | /* | 21 | /* |
| 22 | * GPIO LED layout | ||
| 23 | * | ||
| 24 | * /-SYS_LED(2) | ||
| 25 | * | | ||
| 26 | * | /-DISK_LED | ||
| 27 | * | | | ||
| 28 | * | | /-WLAN_LED(2) | ||
| 29 | * | | | | ||
| 30 | * [SW] [*] [*] [*] | ||
| 31 | */ | ||
| 32 | |||
| 33 | /* | ||
| 34 | * Switch positions | 22 | * Switch positions |
| 35 | * | 23 | * |
| 36 | * /-SW_LEFT(2) | 24 | * /-SW_LEFT(2) |
| @@ -41,19 +29,8 @@ | |||
| 41 | * | | | | 29 | * | | | |
| 42 | * PS [L] [I] [R] LEDS | 30 | * PS [L] [I] [R] LEDS |
| 43 | */ | 31 | */ |
| 44 | pinctrl-0 = < &pmx_led_disk_yellow | 32 | pinctrl-0 = <&pmx_sw_left &pmx_sw_right |
| 45 | &pmx_sata0_pwr_enable | 33 | &pmx_sw_idle &pmx_sw_left2>; |
| 46 | &pmx_led_sys_red | ||
| 47 | &pmx_led_sys_blue | ||
| 48 | &pmx_led_wifi_green | ||
| 49 | &pmx_sw_left | ||
| 50 | &pmx_sw_right | ||
| 51 | &pmx_sw_idle | ||
| 52 | &pmx_sw_left2 | ||
| 53 | &pmx_led_wifi_yellow | ||
| 54 | &pmx_uart0 | ||
| 55 | &pmx_nand | ||
| 56 | &pmx_twsi0 >; | ||
| 57 | pinctrl-names = "default"; | 34 | pinctrl-names = "default"; |
| 58 | 35 | ||
| 59 | pmx_led_disk_yellow: pmx-led-disk-yellow { | 36 | pmx_led_disk_yellow: pmx-led-disk-yellow { |
| @@ -109,10 +86,14 @@ | |||
| 109 | 86 | ||
| 110 | serial@12000 { | 87 | serial@12000 { |
| 111 | status = "ok"; | 88 | status = "ok"; |
| 89 | pinctrl-0 = <&pmx_uart0>; | ||
| 90 | pinctrl-names = "default"; | ||
| 112 | }; | 91 | }; |
| 113 | 92 | ||
| 114 | nand@3000000 { | 93 | nand@3000000 { |
| 115 | status = "okay"; | 94 | status = "okay"; |
| 95 | pinctrl-0 = <&pmx_nand>; | ||
| 96 | pinctrl-names = "default"; | ||
| 116 | 97 | ||
| 117 | partition@0 { | 98 | partition@0 { |
| 118 | label = "u-boot"; | 99 | label = "u-boot"; |
| @@ -147,6 +128,8 @@ | |||
| 147 | 128 | ||
| 148 | i2c@11000 { | 129 | i2c@11000 { |
| 149 | status = "ok"; | 130 | status = "ok"; |
| 131 | pinctrl-0 = <&pmx_twsi0>; | ||
| 132 | pinctrl-names = "default"; | ||
| 150 | }; | 133 | }; |
| 151 | 134 | ||
| 152 | mvsdio@90000 { | 135 | mvsdio@90000 { |
| @@ -154,11 +137,28 @@ | |||
| 154 | pinctrl-names = "default"; | 137 | pinctrl-names = "default"; |
| 155 | status = "okay"; | 138 | status = "okay"; |
| 156 | /* No CD or WP GPIOs */ | 139 | /* No CD or WP GPIOs */ |
| 140 | broken-cd; | ||
| 157 | }; | 141 | }; |
| 158 | }; | 142 | }; |
| 159 | 143 | ||
| 160 | gpio-leds { | 144 | gpio-leds { |
| 145 | /* | ||
| 146 | * GPIO LED layout | ||
| 147 | * | ||
| 148 | * /-SYS_LED(2) | ||
| 149 | * | | ||
| 150 | * | /-DISK_LED | ||
| 151 | * | | | ||
| 152 | * | | /-WLAN_LED(2) | ||
| 153 | * | | | | ||
| 154 | * [SW] [*] [*] [*] | ||
| 155 | */ | ||
| 156 | |||
| 161 | compatible = "gpio-leds"; | 157 | compatible = "gpio-leds"; |
| 158 | pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red | ||
| 159 | &pmx_led_sys_blue &pmx_led_wifi_green | ||
| 160 | &pmx_led_wifi_yellow>; | ||
| 161 | pinctrl-names = "default"; | ||
| 162 | 162 | ||
| 163 | disk { | 163 | disk { |
| 164 | label = "topkick:yellow:disk"; | 164 | label = "topkick:yellow:disk"; |
| @@ -187,6 +187,8 @@ | |||
| 187 | compatible = "simple-bus"; | 187 | compatible = "simple-bus"; |
| 188 | #address-cells = <1>; | 188 | #address-cells = <1>; |
| 189 | #size-cells = <0>; | 189 | #size-cells = <0>; |
| 190 | pinctrl-0 = <&pmx_sata0_pwr_enable>; | ||
| 191 | pinctrl-names = "default"; | ||
| 190 | 192 | ||
| 191 | sata0_power: regulator@1 { | 193 | sata0_power: regulator@1 { |
| 192 | compatible = "regulator-fixed"; | 194 | compatible = "regulator-fixed"; |
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index 42648ab77c61..6dd1038e4de4 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts | |||
| @@ -8,10 +8,7 @@ | |||
| 8 | ocp@f1000000 { | 8 | ocp@f1000000 { |
| 9 | pinctrl: pinctrl@10000 { | 9 | pinctrl: pinctrl@10000 { |
| 10 | 10 | ||
| 11 | pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi | 11 | pinctrl-0 = <&pmx_ram_size &pmx_board_id>; |
| 12 | &pmx_twsi0 &pmx_sata0 &pmx_sata1 | ||
| 13 | &pmx_ram_size &pmx_reset_button | ||
| 14 | &pmx_USB_copy_button &pmx_board_id>; | ||
| 15 | pinctrl-names = "default"; | 12 | pinctrl-names = "default"; |
| 16 | 13 | ||
| 17 | pmx_ram_size: pmx-ram-size { | 14 | pmx_ram_size: pmx-ram-size { |
| @@ -39,6 +36,9 @@ | |||
| 39 | compatible = "gpio-keys"; | 36 | compatible = "gpio-keys"; |
| 40 | #address-cells = <1>; | 37 | #address-cells = <1>; |
| 41 | #size-cells = <0>; | 38 | #size-cells = <0>; |
| 39 | pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; | ||
| 40 | pinctrl-names = "default"; | ||
| 41 | |||
| 42 | button@1 { | 42 | button@1 { |
| 43 | label = "USB Copy"; | 43 | label = "USB Copy"; |
| 44 | linux,code = <133>; | 44 | linux,code = <133>; |
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 95ceeb93ba5a..6fdc5ffcaae5 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts | |||
| @@ -8,10 +8,7 @@ | |||
| 8 | ocp@f1000000 { | 8 | ocp@f1000000 { |
| 9 | pinctrl: pinctrl@10000 { | 9 | pinctrl: pinctrl@10000 { |
| 10 | 10 | ||
| 11 | pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi | 11 | pinctrl-0 = <&pmx_ram_size &pmx_board_id>; |
| 12 | &pmx_twsi0 &pmx_sata0 &pmx_sata1 | ||
| 13 | &pmx_ram_size &pmx_reset_button | ||
| 14 | &pmx_USB_copy_button &pmx_board_id>; | ||
| 15 | pinctrl-names = "default"; | 12 | pinctrl-names = "default"; |
| 16 | 13 | ||
| 17 | pmx_ram_size: pmx-ram-size { | 14 | pmx_ram_size: pmx-ram-size { |
| @@ -33,12 +30,23 @@ | |||
| 33 | marvell,function = "gpio"; | 30 | marvell,function = "gpio"; |
| 34 | }; | 31 | }; |
| 35 | }; | 32 | }; |
| 33 | pcie-controller { | ||
| 34 | status = "okay"; | ||
| 35 | |||
| 36 | pcie@2,0 { | ||
| 37 | status = "okay"; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 36 | }; | 41 | }; |
| 37 | 42 | ||
| 38 | gpio_keys { | 43 | gpio_keys { |
| 39 | compatible = "gpio-keys"; | 44 | compatible = "gpio-keys"; |
| 40 | #address-cells = <1>; | 45 | #address-cells = <1>; |
| 41 | #size-cells = <0>; | 46 | #size-cells = <0>; |
| 47 | pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | |||
| 42 | button@1 { | 50 | button@1 { |
| 43 | label = "USB Copy"; | 51 | label = "USB Copy"; |
| 44 | linux,code = <133>; | 52 | linux,code = <133>; |
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 09c820fc177f..0c9a94cd666c 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi | |||
| @@ -15,6 +15,8 @@ | |||
| 15 | i2c@11000 { | 15 | i2c@11000 { |
| 16 | status = "okay"; | 16 | status = "okay"; |
| 17 | clock-frequency = <400000>; | 17 | clock-frequency = <400000>; |
| 18 | pinctrl-0 = <&pmx_twsi0>; | ||
| 19 | pinctrl-names = "default"; | ||
| 18 | 20 | ||
| 19 | s35390a: s35390a@30 { | 21 | s35390a: s35390a@30 { |
| 20 | compatible = "s35390a"; | 22 | compatible = "s35390a"; |
| @@ -24,10 +26,14 @@ | |||
| 24 | serial@12000 { | 26 | serial@12000 { |
| 25 | clock-frequency = <200000000>; | 27 | clock-frequency = <200000000>; |
| 26 | status = "okay"; | 28 | status = "okay"; |
| 29 | pinctrl-0 = <&pmx_uart0>; | ||
| 30 | pinctrl-names = "default"; | ||
| 27 | }; | 31 | }; |
| 28 | serial@12100 { | 32 | serial@12100 { |
| 29 | clock-frequency = <200000000>; | 33 | clock-frequency = <200000000>; |
| 30 | status = "okay"; | 34 | status = "okay"; |
| 35 | pinctrl-0 = <&pmx_uart1>; | ||
| 36 | pinctrl-names = "default"; | ||
| 31 | }; | 37 | }; |
| 32 | poweroff@12100 { | 38 | poweroff@12100 { |
| 33 | compatible = "qnap,power-off"; | 39 | compatible = "qnap,power-off"; |
| @@ -36,6 +42,8 @@ | |||
| 36 | }; | 42 | }; |
| 37 | spi@10600 { | 43 | spi@10600 { |
| 38 | status = "okay"; | 44 | status = "okay"; |
| 45 | pinctrl-0 = <&pmx_spi>; | ||
| 46 | pinctrl-names = "default"; | ||
| 39 | 47 | ||
| 40 | m25p128@0 { | 48 | m25p128@0 { |
| 41 | #address-cells = <1>; | 49 | #address-cells = <1>; |
| @@ -74,6 +82,8 @@ | |||
| 74 | }; | 82 | }; |
| 75 | }; | 83 | }; |
| 76 | sata@80000 { | 84 | sata@80000 { |
| 85 | pinctrl-0 = <&pmx_sata0 &pmx_sata1>; | ||
| 86 | pinctrl-names = "default"; | ||
| 77 | status = "okay"; | 87 | status = "okay"; |
| 78 | nr-ports = <2>; | 88 | nr-ports = <2>; |
| 79 | }; | 89 | }; |
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 7eef88f00fea..9809fc1f105c 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi | |||
| @@ -4,6 +4,18 @@ | |||
| 4 | compatible = "marvell,kirkwood"; | 4 | compatible = "marvell,kirkwood"; |
| 5 | interrupt-parent = <&intc>; | 5 | interrupt-parent = <&intc>; |
| 6 | 6 | ||
| 7 | cpus { | ||
| 8 | #address-cells = <1>; | ||
| 9 | #size-cells = <0>; | ||
| 10 | |||
| 11 | cpu@0 { | ||
| 12 | device_type = "cpu"; | ||
| 13 | compatible = "marvell,feroceon"; | ||
| 14 | clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; | ||
| 15 | clock-names = "cpu_clk", "ddrclk", "powersave"; | ||
| 16 | }; | ||
| 17 | }; | ||
| 18 | |||
| 7 | aliases { | 19 | aliases { |
| 8 | gpio0 = &gpio0; | 20 | gpio0 = &gpio0; |
| 9 | gpio1 = &gpio1; | 21 | gpio1 = &gpio1; |
| @@ -18,8 +30,9 @@ | |||
| 18 | 30 | ||
| 19 | ocp@f1000000 { | 31 | ocp@f1000000 { |
| 20 | compatible = "simple-bus"; | 32 | compatible = "simple-bus"; |
| 21 | ranges = <0x00000000 0xf1000000 0x4000000 | 33 | ranges = <0x00000000 0xf1000000 0x0100000 |
| 22 | 0xe0000000 0xe0000000 0x8100000 /* PCIE */ | 34 | 0xe0000000 0xe0000000 0x8100000 /* PCIE */ |
| 35 | 0xf4000000 0xf4000000 0x0000400 | ||
| 23 | 0xf5000000 0xf5000000 0x0000400>; | 36 | 0xf5000000 0xf5000000 0x0000400>; |
| 24 | #address-cells = <1>; | 37 | #address-cells = <1>; |
| 25 | #size-cells = <1>; | 38 | #size-cells = <1>; |
| @@ -72,13 +85,6 @@ | |||
| 72 | status = "disabled"; | 85 | status = "disabled"; |
| 73 | }; | 86 | }; |
| 74 | 87 | ||
| 75 | rtc@10300 { | ||
| 76 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; | ||
| 77 | reg = <0x10300 0x20>; | ||
| 78 | interrupts = <53>; | ||
| 79 | clocks = <&gate_clk 7>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | spi@10600 { | 88 | spi@10600 { |
| 83 | compatible = "marvell,orion-spi"; | 89 | compatible = "marvell,orion-spi"; |
| 84 | #address-cells = <1>; | 90 | #address-cells = <1>; |
| @@ -152,15 +158,6 @@ | |||
| 152 | status = "okay"; | 158 | status = "okay"; |
| 153 | }; | 159 | }; |
| 154 | 160 | ||
| 155 | sata@80000 { | ||
| 156 | compatible = "marvell,orion-sata"; | ||
| 157 | reg = <0x80000 0x5000>; | ||
| 158 | interrupts = <21>; | ||
| 159 | clocks = <&gate_clk 14>, <&gate_clk 15>; | ||
| 160 | clock-names = "0", "1"; | ||
| 161 | status = "disabled"; | ||
| 162 | }; | ||
| 163 | |||
| 164 | nand@3000000 { | 161 | nand@3000000 { |
| 165 | #address-cells = <1>; | 162 | #address-cells = <1>; |
| 166 | #size-cells = <1>; | 163 | #size-cells = <1>; |
| @@ -168,7 +165,7 @@ | |||
| 168 | ale = <1>; | 165 | ale = <1>; |
| 169 | bank-width = <1>; | 166 | bank-width = <1>; |
| 170 | compatible = "marvell,orion-nand"; | 167 | compatible = "marvell,orion-nand"; |
| 171 | reg = <0x3000000 0x400>; | 168 | reg = <0xf4000000 0x400>; |
| 172 | chip-delay = <25>; | 169 | chip-delay = <25>; |
| 173 | /* set partition map and/or chip-delay in board dts */ | 170 | /* set partition map and/or chip-delay in board dts */ |
| 174 | clocks = <&gate_clk 7>; | 171 | clocks = <&gate_clk 7>; |
| @@ -195,13 +192,5 @@ | |||
| 195 | clocks = <&gate_clk 17>; | 192 | clocks = <&gate_clk 17>; |
| 196 | status = "okay"; | 193 | status = "okay"; |
| 197 | }; | 194 | }; |
| 198 | |||
| 199 | mvsdio@90000 { | ||
| 200 | compatible = "marvell,orion-sdio"; | ||
| 201 | reg = <0x90000 0x200>; | ||
| 202 | interrupts = <28>; | ||
| 203 | clocks = <&gate_clk 4>; | ||
| 204 | status = "disabled"; | ||
| 205 | }; | ||
| 206 | }; | 195 | }; |
| 207 | }; | 196 | }; |
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 1582f484a867..3abebb75fc57 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi | |||
| @@ -18,8 +18,12 @@ | |||
| 18 | interrupt-parent = <&mic>; | 18 | interrupt-parent = <&mic>; |
| 19 | 19 | ||
| 20 | cpus { | 20 | cpus { |
| 21 | cpu@0 { | 21 | #address-cells = <0>; |
| 22 | compatible = "arm,arm926ejs"; | 22 | #size-cells = <0>; |
| 23 | |||
| 24 | cpu { | ||
| 25 | compatible = "arm,arm926ej-s"; | ||
| 26 | device_type = "cpu"; | ||
| 23 | }; | 27 | }; |
| 24 | }; | 28 | }; |
| 25 | 29 | ||
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index 37aa7487d4d8..a2bfcde858a6 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi | |||
| @@ -8,7 +8,10 @@ | |||
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "skeleton.dtsi" | 11 | #include <dt-bindings/gpio/gpio.h> |
| 12 | #include <dt-bindings/pinctrl/omap.h> | ||
| 13 | |||
| 14 | #include "skeleton.dtsi" | ||
| 12 | 15 | ||
| 13 | / { | 16 | / { |
| 14 | compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; | 17 | compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; |
| @@ -21,8 +24,12 @@ | |||
| 21 | }; | 24 | }; |
| 22 | 25 | ||
| 23 | cpus { | 26 | cpus { |
| 24 | cpu@0 { | 27 | #address-cells = <0>; |
| 28 | #size-cells = <0>; | ||
| 29 | |||
| 30 | cpu { | ||
| 25 | compatible = "arm,arm1136jf-s"; | 31 | compatible = "arm,arm1136jf-s"; |
| 32 | device_type = "cpu"; | ||
| 26 | }; | 33 | }; |
| 27 | }; | 34 | }; |
| 28 | 35 | ||
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index 68282ee13e26..224c08f472f4 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap2420.dtsi" | 10 | #include "omap2420.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI OMAP2420 H4 board"; | 13 | model = "TI OMAP2420 H4 board"; |
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index da5b285b73be..c8f9c55169ea 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "omap2.dtsi" | 11 | #include "omap2.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | compatible = "ti,omap2420", "ti,omap2"; | 14 | compatible = "ti,omap2420", "ti,omap2"; |
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 054bc4439568..c535a5a2b27f 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "omap2.dtsi" | 11 | #include "omap2.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | compatible = "ti,omap2430", "ti,omap2"; | 14 | compatible = "ti,omap2430", "ti,omap2"; |
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 3046d1f81be0..afdb16417d4e 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap36xx.dtsi" | 10 | #include "omap36xx.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI OMAP3 BeagleBoard xM"; | 13 | model = "TI OMAP3 BeagleBoard xM"; |
| @@ -29,13 +29,13 @@ | |||
| 29 | 29 | ||
| 30 | heartbeat { | 30 | heartbeat { |
| 31 | label = "beagleboard::usr0"; | 31 | label = "beagleboard::usr0"; |
| 32 | gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ | 32 | gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ |
| 33 | linux,default-trigger = "heartbeat"; | 33 | linux,default-trigger = "heartbeat"; |
| 34 | }; | 34 | }; |
| 35 | 35 | ||
| 36 | mmc { | 36 | mmc { |
| 37 | label = "beagleboard::usr1"; | 37 | label = "beagleboard::usr1"; |
| 38 | gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ | 38 | gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ |
| 39 | linux,default-trigger = "mmc0"; | 39 | linux,default-trigger = "mmc0"; |
| 40 | }; | 40 | }; |
| 41 | }; | 41 | }; |
| @@ -57,6 +57,26 @@ | |||
| 57 | ti,mcbsp = <&mcbsp2>; | 57 | ti,mcbsp = <&mcbsp2>; |
| 58 | ti,codec = <&twl_audio>; | 58 | ti,codec = <&twl_audio>; |
| 59 | }; | 59 | }; |
| 60 | |||
| 61 | gpio_keys { | ||
| 62 | compatible = "gpio-keys"; | ||
| 63 | |||
| 64 | user { | ||
| 65 | label = "user"; | ||
| 66 | gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; | ||
| 67 | linux,code = <0x114>; | ||
| 68 | gpio-key,wakeup; | ||
| 69 | }; | ||
| 70 | |||
| 71 | }; | ||
| 72 | }; | ||
| 73 | |||
| 74 | &omap3_pmx_wkup { | ||
| 75 | gpio1_pins: pinmux_gpio1_pins { | ||
| 76 | pinctrl-single,pins = < | ||
| 77 | 0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */ | ||
| 78 | >; | ||
| 79 | }; | ||
| 60 | }; | 80 | }; |
| 61 | 81 | ||
| 62 | &i2c1 { | 82 | &i2c1 { |
| @@ -75,7 +95,8 @@ | |||
| 75 | }; | 95 | }; |
| 76 | }; | 96 | }; |
| 77 | 97 | ||
| 78 | /include/ "twl4030.dtsi" | 98 | #include "twl4030.dtsi" |
| 99 | #include "twl4030_omap3.dtsi" | ||
| 79 | 100 | ||
| 80 | &i2c2 { | 101 | &i2c2 { |
| 81 | clock-frequency = <400000>; | 102 | clock-frequency = <400000>; |
| @@ -126,3 +147,22 @@ | |||
| 126 | mode = <3>; | 147 | mode = <3>; |
| 127 | power = <50>; | 148 | power = <50>; |
| 128 | }; | 149 | }; |
| 150 | |||
| 151 | &omap3_pmx_core { | ||
| 152 | uart3_pins: pinmux_uart3_pins { | ||
| 153 | pinctrl-single,pins = < | ||
| 154 | 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ | ||
| 155 | 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ | ||
| 156 | >; | ||
| 157 | }; | ||
| 158 | }; | ||
| 159 | |||
| 160 | &uart3 { | ||
| 161 | pinctrl-names = "default"; | ||
| 162 | pinctrl-0 = <&uart3_pins>; | ||
| 163 | }; | ||
| 164 | |||
| 165 | &gpio1 { | ||
| 166 | pinctrl-names = "default"; | ||
| 167 | pinctrl-0 = <&gpio1_pins>; | ||
| 168 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 6eec69997607..dfd83103657a 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap34xx.dtsi" | 10 | #include "omap34xx.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI OMAP3 BeagleBoard"; | 13 | model = "TI OMAP3 BeagleBoard"; |
| @@ -28,18 +28,18 @@ | |||
| 28 | compatible = "gpio-leds"; | 28 | compatible = "gpio-leds"; |
| 29 | pmu_stat { | 29 | pmu_stat { |
| 30 | label = "beagleboard::pmu_stat"; | 30 | label = "beagleboard::pmu_stat"; |
| 31 | gpios = <&twl_gpio 19 0>; /* LEDB */ | 31 | gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | heartbeat { | 34 | heartbeat { |
| 35 | label = "beagleboard::usr0"; | 35 | label = "beagleboard::usr0"; |
| 36 | gpios = <&gpio5 22 0>; /* 150 -> D6 LED */ | 36 | gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ |
| 37 | linux,default-trigger = "heartbeat"; | 37 | linux,default-trigger = "heartbeat"; |
| 38 | }; | 38 | }; |
| 39 | 39 | ||
| 40 | mmc { | 40 | mmc { |
| 41 | label = "beagleboard::usr1"; | 41 | label = "beagleboard::usr1"; |
| 42 | gpios = <&gpio5 21 0>; /* 149 -> D7 LED */ | 42 | gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ |
| 43 | linux,default-trigger = "mmc0"; | 43 | linux,default-trigger = "mmc0"; |
| 44 | }; | 44 | }; |
| 45 | }; | 45 | }; |
| @@ -71,6 +71,26 @@ | |||
| 71 | reset-supply = <&hsusb2_reset>; | 71 | reset-supply = <&hsusb2_reset>; |
| 72 | vcc-supply = <&hsusb2_power>; | 72 | vcc-supply = <&hsusb2_power>; |
| 73 | }; | 73 | }; |
| 74 | |||
| 75 | gpio_keys { | ||
| 76 | compatible = "gpio-keys"; | ||
| 77 | |||
| 78 | user { | ||
| 79 | label = "user"; | ||
| 80 | gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; | ||
| 81 | linux,code = <0x114>; | ||
| 82 | gpio-key,wakeup; | ||
| 83 | }; | ||
| 84 | |||
| 85 | }; | ||
| 86 | }; | ||
| 87 | |||
| 88 | &omap3_pmx_wkup { | ||
| 89 | gpio1_pins: pinmux_gpio1_pins { | ||
| 90 | pinctrl-single,pins = < | ||
| 91 | 0x14 (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */ | ||
| 92 | >; | ||
| 93 | }; | ||
| 74 | }; | 94 | }; |
| 75 | 95 | ||
| 76 | &omap3_pmx_core { | 96 | &omap3_pmx_core { |
| @@ -81,18 +101,25 @@ | |||
| 81 | 101 | ||
| 82 | hsusbb2_pins: pinmux_hsusbb2_pins { | 102 | hsusbb2_pins: pinmux_hsusbb2_pins { |
| 83 | pinctrl-single,pins = < | 103 | pinctrl-single,pins = < |
| 84 | 0x5c0 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */ | 104 | 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */ |
| 85 | 0x5c2 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */ | 105 | 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */ |
| 86 | 0x5c4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */ | 106 | 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */ |
| 87 | 0x5c6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */ | 107 | 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */ |
| 88 | 0x5c8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */ | 108 | 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */ |
| 89 | 0x5cA 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */ | 109 | 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */ |
| 90 | 0x1a4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */ | 110 | 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */ |
| 91 | 0x1a6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */ | 111 | 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */ |
| 92 | 0x1a8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */ | 112 | 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */ |
| 93 | 0x1aa 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */ | 113 | 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */ |
| 94 | 0x1ac 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */ | 114 | 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */ |
| 95 | 0x1ae 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */ | 115 | 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */ |
| 116 | >; | ||
| 117 | }; | ||
| 118 | |||
| 119 | uart3_pins: pinmux_uart3_pins { | ||
| 120 | pinctrl-single,pins = < | ||
| 121 | 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ | ||
| 122 | 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ | ||
| 96 | >; | 123 | >; |
| 97 | }; | 124 | }; |
| 98 | }; | 125 | }; |
| @@ -107,7 +134,8 @@ | |||
| 107 | }; | 134 | }; |
| 108 | }; | 135 | }; |
| 109 | 136 | ||
| 110 | /include/ "twl4030.dtsi" | 137 | #include "twl4030.dtsi" |
| 138 | #include "twl4030_omap3.dtsi" | ||
| 111 | 139 | ||
| 112 | &mmc1 { | 140 | &mmc1 { |
| 113 | vmmc-supply = <&vmmc1>; | 141 | vmmc-supply = <&vmmc1>; |
| @@ -142,3 +170,13 @@ | |||
| 142 | */ | 170 | */ |
| 143 | ti,pulldowns = <0x03a1c4>; | 171 | ti,pulldowns = <0x03a1c4>; |
| 144 | }; | 172 | }; |
| 173 | |||
| 174 | &uart3 { | ||
| 175 | pinctrl-names = "default"; | ||
| 176 | pinctrl-0 = <&uart3_pins>; | ||
| 177 | }; | ||
| 178 | |||
| 179 | &gpio1 { | ||
| 180 | pinctrl-names = "default"; | ||
| 181 | pinctrl-0 = <&gpio1_pins>; | ||
| 182 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index 8a5cdcc6debd..af32eff9f4b7 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap34xx.dtsi" | 10 | #include "omap34xx.dtsi" |
| 11 | / { | 11 | / { |
| 12 | model = "TimLL OMAP3 Devkit8000"; | 12 | model = "TimLL OMAP3 Devkit8000"; |
| 13 | compatible = "timll,omap3-devkit8000", "ti,omap3"; | 13 | compatible = "timll,omap3-devkit8000", "ti,omap3"; |
| @@ -22,21 +22,21 @@ | |||
| 22 | 22 | ||
| 23 | heartbeat { | 23 | heartbeat { |
| 24 | label = "devkit8000::led1"; | 24 | label = "devkit8000::led1"; |
| 25 | gpios = <&gpio6 26 0>; /* 186 -> LED1 */ | 25 | gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ |
| 26 | default-state = "on"; | 26 | default-state = "on"; |
| 27 | linux,default-trigger = "heartbeat"; | 27 | linux,default-trigger = "heartbeat"; |
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | mmc { | 30 | mmc { |
| 31 | label = "devkit8000::led2"; | 31 | label = "devkit8000::led2"; |
| 32 | gpios = <&gpio6 3 0>; /* 163 -> LED2 */ | 32 | gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ |
| 33 | default-state = "on"; | 33 | default-state = "on"; |
| 34 | linux,default-trigger = "none"; | 34 | linux,default-trigger = "none"; |
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | usr { | 37 | usr { |
| 38 | label = "devkit8000::led3"; | 38 | label = "devkit8000::led3"; |
| 39 | gpios = <&gpio6 4 0>; /* 164 -> LED3 */ | 39 | gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ |
| 40 | default-state = "on"; | 40 | default-state = "on"; |
| 41 | linux,default-trigger = "usr"; | 41 | linux,default-trigger = "usr"; |
| 42 | }; | 42 | }; |
| @@ -80,7 +80,8 @@ | |||
| 80 | status = "disabled"; | 80 | status = "disabled"; |
| 81 | }; | 81 | }; |
| 82 | 82 | ||
| 83 | /include/ "twl4030.dtsi" | 83 | #include "twl4030.dtsi" |
| 84 | #include "twl4030_omap3.dtsi" | ||
| 84 | 85 | ||
| 85 | &mmc1 { | 86 | &mmc1 { |
| 86 | vmmc-supply = <&vmmc1>; | 87 | vmmc-supply = <&vmmc1>; |
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 96d1c206a57b..7d4329d179c4 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap34xx.dtsi" | 10 | #include "omap34xx.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; | 13 | model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; |
| @@ -28,7 +28,7 @@ | |||
| 28 | compatible = "gpio-leds"; | 28 | compatible = "gpio-leds"; |
| 29 | ledb { | 29 | ledb { |
| 30 | label = "omap3evm::ledb"; | 30 | label = "omap3evm::ledb"; |
| 31 | gpios = <&twl_gpio 19 0>; /* LEDB */ | 31 | gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ |
| 32 | linux,default-trigger = "default-on"; | 32 | linux,default-trigger = "default-on"; |
| 33 | }; | 33 | }; |
| 34 | }; | 34 | }; |
| @@ -44,7 +44,8 @@ | |||
| 44 | }; | 44 | }; |
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| 47 | /include/ "twl4030.dtsi" | 47 | #include "twl4030.dtsi" |
| 48 | #include "twl4030_omap3.dtsi" | ||
| 48 | 49 | ||
| 49 | &i2c2 { | 50 | &i2c2 { |
| 50 | clock-frequency = <400000>; | 51 | clock-frequency = <400000>; |
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index f8fe3b748c3e..bc48b114eae6 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | /dts-v1/; | 11 | /dts-v1/; |
| 12 | 12 | ||
| 13 | /include/ "omap34xx.dtsi" | 13 | #include "omap34xx.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | memory { | 16 | memory { |
| @@ -29,37 +29,43 @@ | |||
| 29 | &omap3_pmx_core { | 29 | &omap3_pmx_core { |
| 30 | uart1_pins: pinmux_uart1_pins { | 30 | uart1_pins: pinmux_uart1_pins { |
| 31 | pinctrl-single,pins = < | 31 | pinctrl-single,pins = < |
| 32 | 0x152 0x100 /* uart1_rx.uart1_rx INPUT | MODE0 */ | 32 | 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ |
| 33 | 0x14c 0 /* uart1_tx.uart1_tx OUTPUT | MODE0 */ | 33 | 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ |
| 34 | >; | 34 | >; |
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | uart2_pins: pinmux_uart2_pins { | 37 | uart2_pins: pinmux_uart2_pins { |
| 38 | pinctrl-single,pins = < | 38 | pinctrl-single,pins = < |
| 39 | 0x14a 0x100 /* uart2_rx.uart2_rx INPUT | MODE0 */ | 39 | 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ |
| 40 | 0x148 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */ | 40 | 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ |
| 41 | >; | 41 | >; |
| 42 | }; | 42 | }; |
| 43 | 43 | ||
| 44 | uart3_pins: pinmux_uart3_pins { | 44 | uart3_pins: pinmux_uart3_pins { |
| 45 | pinctrl-single,pins = < | 45 | pinctrl-single,pins = < |
| 46 | 0x16e 0x100 /* uart3_rx.uart3_rx INPUT | MODE0 */ | 46 | 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ |
| 47 | 0x170 0 /* uart3_tx.uart3_tx OUTPUT | MODE0 */ | 47 | 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ |
| 48 | >; | 48 | >; |
| 49 | }; | 49 | }; |
| 50 | 50 | ||
| 51 | mmc1_pins: pinmux_mmc1_pins { | 51 | mmc1_pins: pinmux_mmc1_pins { |
| 52 | pinctrl-single,pins = < | 52 | pinctrl-single,pins = < |
| 53 | 0x114 0x0118 /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */ | 53 | 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ |
| 54 | 0x116 0x0118 /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */ | 54 | 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ |
| 55 | 0x118 0x0118 /* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */ | 55 | 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ |
| 56 | 0x11a 0x0118 /* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */ | 56 | 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ |
| 57 | 0x11c 0x0118 /* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */ | 57 | 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ |
| 58 | 0x11e 0x0118 /* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */ | 58 | 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ |
| 59 | 0x120 0x0100 /* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */ | 59 | 0x120 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ |
| 60 | 0x122 0x0100 /* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */ | 60 | 0x122 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ |
| 61 | 0x124 0x0100 /* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */ | 61 | 0x124 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ |
| 62 | 0x126 0x0100 /* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */ | 62 | 0x126 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ |
| 63 | >; | ||
| 64 | }; | ||
| 65 | |||
| 66 | smsc911x_pins: pinmux_smsc911x_pins { | ||
| 67 | pinctrl-single,pins = < | ||
| 68 | 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ | ||
| 63 | >; | 69 | >; |
| 64 | }; | 70 | }; |
| 65 | }; | 71 | }; |
| @@ -80,7 +86,8 @@ | |||
| 80 | }; | 86 | }; |
| 81 | }; | 87 | }; |
| 82 | 88 | ||
| 83 | /include/ "twl4030.dtsi" | 89 | #include "twl4030.dtsi" |
| 90 | #include "twl4030_omap3.dtsi" | ||
| 84 | 91 | ||
| 85 | &i2c2 { | 92 | &i2c2 { |
| 86 | clock-frequency = <400000>; | 93 | clock-frequency = <400000>; |
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index e2b98490cc9a..e8c48284587c 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /include/ "omap3-igep.dtsi" | 12 | #include "omap3-igep.dtsi" |
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | model = "IGEPv2"; | 15 | model = "IGEPv2"; |
| @@ -19,27 +19,39 @@ | |||
| 19 | compatible = "gpio-leds"; | 19 | compatible = "gpio-leds"; |
| 20 | boot { | 20 | boot { |
| 21 | label = "omap3:green:boot"; | 21 | label = "omap3:green:boot"; |
| 22 | gpios = <&gpio1 26 0>; | 22 | gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; |
| 23 | default-state = "on"; | 23 | default-state = "on"; |
| 24 | }; | 24 | }; |
| 25 | 25 | ||
| 26 | user0 { | 26 | user0 { |
| 27 | label = "omap3:red:user0"; | 27 | label = "omap3:red:user0"; |
| 28 | gpios = <&gpio1 27 0>; | 28 | gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; |
| 29 | default-state = "off"; | 29 | default-state = "off"; |
| 30 | }; | 30 | }; |
| 31 | 31 | ||
| 32 | user1 { | 32 | user1 { |
| 33 | label = "omap3:red:user1"; | 33 | label = "omap3:red:user1"; |
| 34 | gpios = <&gpio1 28 0>; | 34 | gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; |
| 35 | default-state = "off"; | 35 | default-state = "off"; |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| 38 | user2 { | 38 | user2 { |
| 39 | label = "omap3:green:user1"; | 39 | label = "omap3:green:user1"; |
| 40 | gpios = <&twl_gpio 19 1>; | 40 | gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; |
| 41 | }; | 41 | }; |
| 42 | }; | 42 | }; |
| 43 | |||
| 44 | vddvario: regulator-vddvario { | ||
| 45 | compatible = "regulator-fixed"; | ||
| 46 | regulator-name = "vddvario"; | ||
| 47 | regulator-always-on; | ||
| 48 | }; | ||
| 49 | |||
| 50 | vdd33a: regulator-vdd33a { | ||
| 51 | compatible = "regulator-fixed"; | ||
| 52 | regulator-name = "vdd33a"; | ||
| 53 | regulator-always-on; | ||
| 54 | }; | ||
| 43 | }; | 55 | }; |
| 44 | 56 | ||
| 45 | &i2c3 { | 57 | &i2c3 { |
| @@ -54,3 +66,92 @@ | |||
| 54 | reg = <0x50>; | 66 | reg = <0x50>; |
| 55 | }; | 67 | }; |
| 56 | }; | 68 | }; |
| 69 | |||
| 70 | &gpmc { | ||
| 71 | ranges = <0 0 0x00000000 0x20000000>, | ||
| 72 | <5 0 0x2c000000 0x01000000>; | ||
| 73 | |||
| 74 | nand@0,0 { | ||
| 75 | linux,mtd-name= "micron,mt29c4g96maz"; | ||
| 76 | reg = <0 0 0>; | ||
| 77 | nand-bus-width = <16>; | ||
| 78 | ti,nand-ecc-opt = "bch8"; | ||
| 79 | |||
| 80 | gpmc,sync-clk-ps = <0>; | ||
| 81 | gpmc,cs-on-ns = <0>; | ||
| 82 | gpmc,cs-rd-off-ns = <44>; | ||
| 83 | gpmc,cs-wr-off-ns = <44>; | ||
| 84 | gpmc,adv-on-ns = <6>; | ||
| 85 | gpmc,adv-rd-off-ns = <34>; | ||
| 86 | gpmc,adv-wr-off-ns = <44>; | ||
| 87 | gpmc,we-off-ns = <40>; | ||
| 88 | gpmc,oe-off-ns = <54>; | ||
| 89 | gpmc,access-ns = <64>; | ||
| 90 | gpmc,rd-cycle-ns = <82>; | ||
| 91 | gpmc,wr-cycle-ns = <82>; | ||
| 92 | gpmc,wr-access-ns = <40>; | ||
| 93 | gpmc,wr-data-mux-bus-ns = <0>; | ||
| 94 | |||
| 95 | #address-cells = <1>; | ||
| 96 | #size-cells = <1>; | ||
| 97 | |||
| 98 | partition@0 { | ||
| 99 | label = "SPL"; | ||
| 100 | reg = <0 0x100000>; | ||
| 101 | }; | ||
| 102 | partition@0x80000 { | ||
| 103 | label = "U-Boot"; | ||
| 104 | reg = <0x100000 0x180000>; | ||
| 105 | }; | ||
| 106 | partition@0x1c0000 { | ||
| 107 | label = "Environment"; | ||
| 108 | reg = <0x280000 0x100000>; | ||
| 109 | }; | ||
| 110 | partition@0x280000 { | ||
| 111 | label = "Kernel"; | ||
| 112 | reg = <0x380000 0x300000>; | ||
| 113 | }; | ||
| 114 | partition@0x780000 { | ||
| 115 | label = "Filesystem"; | ||
| 116 | reg = <0x680000 0x1f980000>; | ||
| 117 | }; | ||
| 118 | }; | ||
| 119 | |||
| 120 | ethernet@5,0 { | ||
| 121 | pinctrl-names = "default"; | ||
| 122 | pinctrl-0 = <&smsc911x_pins>; | ||
| 123 | compatible = "smsc,lan9221", "smsc,lan9115"; | ||
| 124 | reg = <5 0 0xff>; | ||
| 125 | bank-width = <2>; | ||
| 126 | |||
| 127 | gpmc,mux-add-data; | ||
| 128 | gpmc,cs-on-ns = <0>; | ||
| 129 | gpmc,cs-rd-off-ns = <186>; | ||
| 130 | gpmc,cs-wr-off-ns = <186>; | ||
| 131 | gpmc,adv-on-ns = <12>; | ||
| 132 | gpmc,adv-rd-off-ns = <48>; | ||
| 133 | gpmc,adv-wr-off-ns = <48>; | ||
| 134 | gpmc,oe-on-ns = <54>; | ||
| 135 | gpmc,oe-off-ns = <168>; | ||
| 136 | gpmc,we-on-ns = <54>; | ||
| 137 | gpmc,we-off-ns = <168>; | ||
| 138 | gpmc,rd-cycle-ns = <186>; | ||
| 139 | gpmc,wr-cycle-ns = <186>; | ||
| 140 | gpmc,access-ns = <114>; | ||
| 141 | gpmc,page-burst-access-ns = <6>; | ||
| 142 | gpmc,bus-turnaround-ns = <12>; | ||
| 143 | gpmc,cycle2cycle-delay-ns = <18>; | ||
| 144 | gpmc,wr-data-mux-bus-ns = <90>; | ||
| 145 | gpmc,wr-access-ns = <186>; | ||
| 146 | gpmc,cycle2cycle-samecsen; | ||
| 147 | gpmc,cycle2cycle-diffcsen; | ||
| 148 | |||
| 149 | interrupt-parent = <&gpio6>; | ||
| 150 | interrupts = <16 8>; | ||
| 151 | vmmc-supply = <&vddvario>; | ||
| 152 | vmmc_aux-supply = <&vdd33a>; | ||
| 153 | reg-io-width = <4>; | ||
| 154 | |||
| 155 | smsc,save-mac-address; | ||
| 156 | }; | ||
| 157 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts index 9dc48d262ffb..644d05383836 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/omap3-igep0030.dts | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /include/ "omap3-igep.dtsi" | 12 | #include "omap3-igep.dtsi" |
| 13 | 13 | ||
| 14 | / { | 14 | / { |
| 15 | model = "IGEP COM Module"; | 15 | model = "IGEP COM Module"; |
| @@ -19,26 +19,76 @@ | |||
| 19 | compatible = "gpio-leds"; | 19 | compatible = "gpio-leds"; |
| 20 | boot { | 20 | boot { |
| 21 | label = "omap3:green:boot"; | 21 | label = "omap3:green:boot"; |
| 22 | gpios = <&twl_gpio 13 1>; | 22 | gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; |
| 23 | default-state = "on"; | 23 | default-state = "on"; |
| 24 | }; | 24 | }; |
| 25 | 25 | ||
| 26 | user0 { | 26 | user0 { |
| 27 | label = "omap3:red:user0"; | 27 | label = "omap3:red:user0"; |
| 28 | gpios = <&twl_gpio 18 1>; /* LEDA */ | 28 | gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ |
| 29 | default-state = "off"; | 29 | default-state = "off"; |
| 30 | }; | 30 | }; |
| 31 | 31 | ||
| 32 | user1 { | 32 | user1 { |
| 33 | label = "omap3:green:user1"; | 33 | label = "omap3:green:user1"; |
| 34 | gpios = <&twl_gpio 19 1>; /* LEDB */ | 34 | gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ |
| 35 | default-state = "off"; | 35 | default-state = "off"; |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| 38 | user2 { | 38 | user2 { |
| 39 | label = "omap3:red:user1"; | 39 | label = "omap3:red:user1"; |
| 40 | gpios = <&gpio1 16 1>; | 40 | gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; |
| 41 | default-state = "off"; | 41 | default-state = "off"; |
| 42 | }; | 42 | }; |
| 43 | }; | 43 | }; |
| 44 | }; | 44 | }; |
| 45 | |||
| 46 | &gpmc { | ||
| 47 | ranges = <0 0 0x00000000 0x20000000>; | ||
| 48 | |||
| 49 | nand@0,0 { | ||
| 50 | linux,mtd-name= "micron,mt29c4g96maz"; | ||
| 51 | reg = <0 0 0>; | ||
| 52 | nand-bus-width = <16>; | ||
| 53 | ti,nand-ecc-opt = "bch8"; | ||
| 54 | |||
| 55 | gpmc,sync-clk-ps = <0>; | ||
| 56 | gpmc,cs-on-ns = <0>; | ||
| 57 | gpmc,cs-rd-off-ns = <44>; | ||
| 58 | gpmc,cs-wr-off-ns = <44>; | ||
| 59 | gpmc,adv-on-ns = <6>; | ||
| 60 | gpmc,adv-rd-off-ns = <34>; | ||
| 61 | gpmc,adv-wr-off-ns = <44>; | ||
| 62 | gpmc,we-off-ns = <40>; | ||
| 63 | gpmc,oe-off-ns = <54>; | ||
| 64 | gpmc,access-ns = <64>; | ||
| 65 | gpmc,rd-cycle-ns = <82>; | ||
| 66 | gpmc,wr-cycle-ns = <82>; | ||
| 67 | gpmc,wr-access-ns = <40>; | ||
| 68 | gpmc,wr-data-mux-bus-ns = <0>; | ||
| 69 | |||
| 70 | #address-cells = <1>; | ||
| 71 | #size-cells = <1>; | ||
| 72 | |||
| 73 | partition@0 { | ||
| 74 | label = "SPL"; | ||
| 75 | reg = <0 0x100000>; | ||
| 76 | }; | ||
| 77 | partition@0x80000 { | ||
| 78 | label = "U-Boot"; | ||
| 79 | reg = <0x100000 0x180000>; | ||
| 80 | }; | ||
| 81 | partition@0x1c0000 { | ||
| 82 | label = "Environment"; | ||
| 83 | reg = <0x280000 0x100000>; | ||
| 84 | }; | ||
| 85 | partition@0x280000 { | ||
| 86 | label = "Kernel"; | ||
| 87 | reg = <0x380000 0x300000>; | ||
| 88 | }; | ||
| 89 | partition@0x780000 { | ||
| 90 | label = "Filesystem"; | ||
| 91 | reg = <0x680000 0x1f980000>; | ||
| 92 | }; | ||
| 93 | }; | ||
| 94 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi index a626c50041f6..8f1abec78275 100644 --- a/arch/arm/boot/dts/omap3-overo.dtsi +++ b/arch/arm/boot/dts/omap3-overo.dtsi | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | 13 | ||
| 14 | /include/ "omap34xx.dtsi" | 14 | #include "omap34xx.dtsi" |
| 15 | 15 | ||
| 16 | / { | 16 | / { |
| 17 | pwmleds { | 17 | pwmleds { |
| @@ -21,6 +21,7 @@ | |||
| 21 | label = "overo:blue:COM"; | 21 | label = "overo:blue:COM"; |
| 22 | pwms = <&twl_pwmled 1 7812500>; | 22 | pwms = <&twl_pwmled 1 7812500>; |
| 23 | max-brightness = <127>; | 23 | max-brightness = <127>; |
| 24 | linux,default-trigger = "mmc0"; | ||
| 24 | }; | 25 | }; |
| 25 | }; | 26 | }; |
| 26 | 27 | ||
| @@ -49,7 +50,8 @@ | |||
| 49 | }; | 50 | }; |
| 50 | }; | 51 | }; |
| 51 | 52 | ||
| 52 | /include/ "twl4030.dtsi" | 53 | #include "twl4030.dtsi" |
| 54 | #include "twl4030_omap3.dtsi" | ||
| 53 | 55 | ||
| 54 | /* i2c2 pins are used for gpio */ | 56 | /* i2c2 pins are used for gpio */ |
| 55 | &i2c2 { | 57 | &i2c2 { |
| @@ -77,3 +79,17 @@ | |||
| 77 | mode = <3>; | 79 | mode = <3>; |
| 78 | power = <50>; | 80 | power = <50>; |
| 79 | }; | 81 | }; |
| 82 | |||
| 83 | &omap3_pmx_core { | ||
| 84 | uart3_pins: pinmux_uart3_pins { | ||
| 85 | pinctrl-single,pins = < | ||
| 86 | 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ | ||
| 87 | 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ | ||
| 88 | >; | ||
| 89 | }; | ||
| 90 | }; | ||
| 91 | |||
| 92 | &uart3 { | ||
| 93 | pinctrl-names = "default"; | ||
| 94 | pinctrl-0 = <&uart3_pins>; | ||
| 95 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts index a13d12de77ff..7e4ad2aec37a 100644 --- a/arch/arm/boot/dts/omap3-tobi.dts +++ b/arch/arm/boot/dts/omap3-tobi.dts | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | * Tobi expansion board is manufactured by Gumstix Inc. | 10 | * Tobi expansion board is manufactured by Gumstix Inc. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | /include/ "omap3-overo.dtsi" | 13 | #include "omap3-overo.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | model = "TI OMAP3 Gumstix Overo on Tobi"; | 16 | model = "TI OMAP3 Gumstix Overo on Tobi"; |
| @@ -20,10 +20,58 @@ | |||
| 20 | compatible = "gpio-leds"; | 20 | compatible = "gpio-leds"; |
| 21 | heartbeat { | 21 | heartbeat { |
| 22 | label = "overo:red:gpio21"; | 22 | label = "overo:red:gpio21"; |
| 23 | gpios = <&gpio1 21 0>; | 23 | gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; |
| 24 | linux,default-trigger = "heartbeat"; | 24 | linux,default-trigger = "heartbeat"; |
| 25 | }; | 25 | }; |
| 26 | }; | 26 | }; |
| 27 | |||
| 28 | vddvario: regulator-vddvario { | ||
| 29 | compatible = "regulator-fixed"; | ||
| 30 | regulator-name = "vddvario"; | ||
| 31 | regulator-always-on; | ||
| 32 | }; | ||
| 33 | |||
| 34 | vdd33a: regulator-vdd33a { | ||
| 35 | compatible = "regulator-fixed"; | ||
| 36 | regulator-name = "vdd33a"; | ||
| 37 | regulator-always-on; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | &gpmc { | ||
| 42 | ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */ | ||
| 43 | |||
| 44 | ethernet@5,0 { | ||
| 45 | compatible = "smsc,lan9221", "smsc,lan9115"; | ||
| 46 | reg = <5 0 0xff>; | ||
| 47 | bank-width = <2>; | ||
| 48 | |||
| 49 | gpmc,mux-add-data; | ||
| 50 | gpmc,cs-on-ns = <0>; | ||
| 51 | gpmc,cs-rd-off-ns = <42>; | ||
| 52 | gpmc,cs-wr-off-ns = <36>; | ||
| 53 | gpmc,adv-on-ns = <6>; | ||
| 54 | gpmc,adv-rd-off-ns = <12>; | ||
| 55 | gpmc,adv-wr-off-ns = <12>; | ||
| 56 | gpmc,oe-on-ns = <0>; | ||
| 57 | gpmc,oe-off-ns = <42>; | ||
| 58 | gpmc,we-on-ns = <0>; | ||
| 59 | gpmc,we-off-ns = <36>; | ||
| 60 | gpmc,rd-cycle-ns = <60>; | ||
| 61 | gpmc,wr-cycle-ns = <54>; | ||
| 62 | gpmc,access-ns = <36>; | ||
| 63 | gpmc,page-burst-access-ns = <0>; | ||
| 64 | gpmc,bus-turnaround-ns = <0>; | ||
| 65 | gpmc,cycle2cycle-delay-ns = <0>; | ||
| 66 | gpmc,wr-data-mux-bus-ns = <18>; | ||
| 67 | gpmc,wr-access-ns = <42>; | ||
| 68 | gpmc,cycle2cycle-samecsen; | ||
| 69 | gpmc,cycle2cycle-diffcsen; | ||
| 70 | |||
| 71 | interrupt-parent = <&gpio6>; | ||
| 72 | interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */ | ||
| 73 | reg-io-width = <4>; | ||
| 74 | }; | ||
| 27 | }; | 75 | }; |
| 28 | 76 | ||
| 29 | &i2c3 { | 77 | &i2c3 { |
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 99ba6e14ebf3..7d95cda1fae4 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi | |||
| @@ -8,7 +8,11 @@ | |||
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "skeleton.dtsi" | 11 | #include <dt-bindings/gpio/gpio.h> |
| 12 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 13 | #include <dt-bindings/pinctrl/omap.h> | ||
| 14 | |||
| 15 | #include "skeleton.dtsi" | ||
| 12 | 16 | ||
| 13 | / { | 17 | / { |
| 14 | compatible = "ti,omap3430", "ti,omap3"; | 18 | compatible = "ti,omap3430", "ti,omap3"; |
| @@ -21,8 +25,13 @@ | |||
| 21 | }; | 25 | }; |
| 22 | 26 | ||
| 23 | cpus { | 27 | cpus { |
| 28 | #address-cells = <1>; | ||
| 29 | #size-cells = <0>; | ||
| 30 | |||
| 24 | cpu@0 { | 31 | cpu@0 { |
| 25 | compatible = "arm,cortex-a8"; | 32 | compatible = "arm,cortex-a8"; |
| 33 | device_type = "cpu"; | ||
| 34 | reg = <0x0>; | ||
| 26 | }; | 35 | }; |
| 27 | }; | 36 | }; |
| 28 | 37 | ||
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 144ae43453c4..c4a1c0a97728 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap34xx.dtsi" | 10 | #include "omap34xx.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "TI OMAP3430 SDP"; | 13 | model = "TI OMAP3430 SDP"; |
| @@ -28,7 +28,8 @@ | |||
| 28 | }; | 28 | }; |
| 29 | }; | 29 | }; |
| 30 | 30 | ||
| 31 | /include/ "twl4030.dtsi" | 31 | #include "twl4030.dtsi" |
| 32 | #include "twl4030_omap3.dtsi" | ||
| 32 | 33 | ||
| 33 | &mmc1 { | 34 | &mmc1 { |
| 34 | vmmc-supply = <&vmmc1>; | 35 | vmmc-supply = <&vmmc1>; |
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 75ed4ae2e631..5355d6173748 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "omap3.dtsi" | 11 | #include "omap3.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | cpus { | 14 | cpus { |
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index f3447bc1b032..f8b3765eb9be 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "omap3.dtsi" | 11 | #include "omap3.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | aliases { | 14 | aliases { |
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts index e30cdf0f5ac1..133f1b74e8ae 100644 --- a/arch/arm/boot/dts/omap4-panda-a4.dts +++ b/arch/arm/boot/dts/omap4-panda-a4.dts | |||
| @@ -7,14 +7,14 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap443x.dtsi" | 10 | #include "omap443x.dtsi" |
| 11 | /include/ "omap4-panda-common.dtsi" | 11 | #include "omap4-panda-common.dtsi" |
| 12 | 12 | ||
| 13 | /* Pandaboard Rev A4+ have external pullups on SCL & SDA */ | 13 | /* Pandaboard Rev A4+ have external pullups on SCL & SDA */ |
| 14 | &dss_hdmi_pins { | 14 | &dss_hdmi_pins { |
| 15 | pinctrl-single,pins = < | 15 | pinctrl-single,pins = < |
| 16 | 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ | 16 | 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ |
| 17 | 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */ | 17 | 0x5c (PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ |
| 18 | 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */ | 18 | 0x5e (PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ |
| 19 | >; | 19 | >; |
| 20 | }; | 20 | }; |
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index eeb734e25709..faa95b5b242e 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi | |||
| @@ -5,7 +5,7 @@ | |||
| 5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | /include/ "elpida_ecb240abacn.dtsi" | 8 | #include "elpida_ecb240abacn.dtsi" |
| 9 | 9 | ||
| 10 | / { | 10 | / { |
| 11 | model = "TI OMAP4 PandaBoard"; | 11 | model = "TI OMAP4 PandaBoard"; |
| @@ -16,17 +16,22 @@ | |||
| 16 | reg = <0x80000000 0x40000000>; /* 1 GB */ | 16 | reg = <0x80000000 0x40000000>; /* 1 GB */ |
| 17 | }; | 17 | }; |
| 18 | 18 | ||
| 19 | leds { | 19 | leds: leds { |
| 20 | compatible = "gpio-leds"; | 20 | compatible = "gpio-leds"; |
| 21 | pinctrl-names = "default"; | ||
| 22 | pinctrl-0 = < | ||
| 23 | &led_wkgpio_pins | ||
| 24 | >; | ||
| 25 | |||
| 21 | heartbeat { | 26 | heartbeat { |
| 22 | label = "pandaboard::status1"; | 27 | label = "pandaboard::status1"; |
| 23 | gpios = <&gpio1 7 0>; | 28 | gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
| 24 | linux,default-trigger = "heartbeat"; | 29 | linux,default-trigger = "heartbeat"; |
| 25 | }; | 30 | }; |
| 26 | 31 | ||
| 27 | mmc { | 32 | mmc { |
| 28 | label = "pandaboard::status2"; | 33 | label = "pandaboard::status2"; |
| 29 | gpios = <&gpio1 8 0>; | 34 | gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; |
| 30 | linux,default-trigger = "mmc0"; | 35 | linux,default-trigger = "mmc0"; |
| 31 | }; | 36 | }; |
| 32 | }; | 37 | }; |
| @@ -54,6 +59,54 @@ | |||
| 54 | "AFML", "Line In", | 59 | "AFML", "Line In", |
| 55 | "AFMR", "Line In"; | 60 | "AFMR", "Line In"; |
| 56 | }; | 61 | }; |
| 62 | |||
| 63 | /* | ||
| 64 | * Temp hack: Need to be replaced with the proper gpio-controlled | ||
| 65 | * reset driver as soon it will be merged. | ||
| 66 | * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830 | ||
| 67 | */ | ||
| 68 | /* HS USB Port 1 RESET */ | ||
| 69 | hsusb1_reset: hsusb1_reset_reg { | ||
| 70 | compatible = "regulator-fixed"; | ||
| 71 | regulator-name = "hsusb1_reset"; | ||
| 72 | regulator-min-microvolt = <3300000>; | ||
| 73 | regulator-max-microvolt = <3300000>; | ||
| 74 | gpio = <&gpio2 30 0>; /* gpio_62 */ | ||
| 75 | startup-delay-us = <70000>; | ||
| 76 | enable-active-high; | ||
| 77 | }; | ||
| 78 | |||
| 79 | /* HS USB Port 1 Power */ | ||
| 80 | hsusb1_power: hsusb1_power_reg { | ||
| 81 | compatible = "regulator-fixed"; | ||
| 82 | regulator-name = "hsusb1_vbus"; | ||
| 83 | regulator-min-microvolt = <3300000>; | ||
| 84 | regulator-max-microvolt = <3300000>; | ||
| 85 | gpio = <&gpio1 1 0>; /* gpio_1 */ | ||
| 86 | startup-delay-us = <70000>; | ||
| 87 | enable-active-high; | ||
| 88 | /* | ||
| 89 | * boot-on is required along with always-on as the | ||
| 90 | * regulator framework doesn't enable the regulator | ||
| 91 | * if boot-on is not there. | ||
| 92 | */ | ||
| 93 | regulator-always-on; | ||
| 94 | regulator-boot-on; | ||
| 95 | }; | ||
| 96 | |||
| 97 | /* HS USB Host PHY on PORT 1 */ | ||
| 98 | hsusb1_phy: hsusb1_phy { | ||
| 99 | compatible = "usb-nop-xceiv"; | ||
| 100 | reset-supply = <&hsusb1_reset>; | ||
| 101 | vcc-supply = <&hsusb1_power>; | ||
| 102 | /** | ||
| 103 | * FIXME: | ||
| 104 | * put the right clock phandle here when available | ||
| 105 | * clocks = <&auxclk3>; | ||
| 106 | * clock-names = "main_clk"; | ||
| 107 | */ | ||
| 108 | clock-frequency = <19200000>; | ||
| 109 | }; | ||
| 57 | }; | 110 | }; |
| 58 | 111 | ||
| 59 | &omap4_pmx_wkup { | 112 | &omap4_pmx_wkup { |
| @@ -64,7 +117,7 @@ | |||
| 64 | 117 | ||
| 65 | twl6030_wkup_pins: pinmux_twl6030_wkup_pins { | 118 | twl6030_wkup_pins: pinmux_twl6030_wkup_pins { |
| 66 | pinctrl-single,pins = < | 119 | pinctrl-single,pins = < |
| 67 | 0x14 0x2 /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */ | 120 | 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ |
| 68 | >; | 121 | >; |
| 69 | }; | 122 | }; |
| 70 | }; | 123 | }; |
| @@ -78,81 +131,108 @@ | |||
| 78 | &mcbsp1_pins | 131 | &mcbsp1_pins |
| 79 | &dss_hdmi_pins | 132 | &dss_hdmi_pins |
| 80 | &tpd12s015_pins | 133 | &tpd12s015_pins |
| 134 | &hsusbb1_pins | ||
| 81 | >; | 135 | >; |
| 82 | 136 | ||
| 83 | twl6030_pins: pinmux_twl6030_pins { | 137 | twl6030_pins: pinmux_twl6030_pins { |
| 84 | pinctrl-single,pins = < | 138 | pinctrl-single,pins = < |
| 85 | 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */ | 139 | 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ |
| 86 | >; | 140 | >; |
| 87 | }; | 141 | }; |
| 88 | 142 | ||
| 89 | twl6040_pins: pinmux_twl6040_pins { | 143 | twl6040_pins: pinmux_twl6040_pins { |
| 90 | pinctrl-single,pins = < | 144 | pinctrl-single,pins = < |
| 91 | 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ | 145 | 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ |
| 92 | 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */ | 146 | 0x160 (PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ |
| 93 | >; | 147 | >; |
| 94 | }; | 148 | }; |
| 95 | 149 | ||
| 96 | mcpdm_pins: pinmux_mcpdm_pins { | 150 | mcpdm_pins: pinmux_mcpdm_pins { |
| 97 | pinctrl-single,pins = < | 151 | pinctrl-single,pins = < |
| 98 | 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */ | 152 | 0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ |
| 99 | 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */ | 153 | 0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ |
| 100 | 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */ | 154 | 0xca (PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ |
| 101 | 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */ | 155 | 0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ |
| 102 | 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ | 156 | 0xce (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ |
| 103 | >; | 157 | >; |
| 104 | }; | 158 | }; |
| 105 | 159 | ||
| 106 | mcbsp1_pins: pinmux_mcbsp1_pins { | 160 | mcbsp1_pins: pinmux_mcbsp1_pins { |
| 107 | pinctrl-single,pins = < | 161 | pinctrl-single,pins = < |
| 108 | 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */ | 162 | 0xbe (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ |
| 109 | 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */ | 163 | 0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ |
| 110 | 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */ | 164 | 0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ |
| 111 | 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ | 165 | 0xc4 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ |
| 112 | >; | 166 | >; |
| 113 | }; | 167 | }; |
| 114 | 168 | ||
| 115 | dss_hdmi_pins: pinmux_dss_hdmi_pins { | 169 | dss_hdmi_pins: pinmux_dss_hdmi_pins { |
| 116 | pinctrl-single,pins = < | 170 | pinctrl-single,pins = < |
| 117 | 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ | 171 | 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ |
| 118 | 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */ | 172 | 0x5c (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ |
| 119 | 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */ | 173 | 0x5e (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ |
| 120 | >; | 174 | >; |
| 121 | }; | 175 | }; |
| 122 | 176 | ||
| 123 | tpd12s015_pins: pinmux_tpd12s015_pins { | 177 | tpd12s015_pins: pinmux_tpd12s015_pins { |
| 124 | pinctrl-single,pins = < | 178 | pinctrl-single,pins = < |
| 125 | 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */ | 179 | 0x22 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ |
| 126 | 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */ | 180 | 0x48 (PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ |
| 127 | 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */ | 181 | 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ |
| 182 | >; | ||
| 183 | }; | ||
| 184 | |||
| 185 | hsusbb1_pins: pinmux_hsusbb1_pins { | ||
| 186 | pinctrl-single,pins = < | ||
| 187 | 0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */ | ||
| 188 | 0x84 (PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */ | ||
| 189 | 0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */ | ||
| 190 | 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */ | ||
| 191 | 0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */ | ||
| 192 | 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */ | ||
| 193 | 0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */ | ||
| 194 | 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */ | ||
| 195 | 0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */ | ||
| 196 | 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */ | ||
| 197 | 0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */ | ||
| 198 | 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */ | ||
| 128 | >; | 199 | >; |
| 129 | }; | 200 | }; |
| 130 | 201 | ||
| 131 | i2c1_pins: pinmux_i2c1_pins { | 202 | i2c1_pins: pinmux_i2c1_pins { |
| 132 | pinctrl-single,pins = < | 203 | pinctrl-single,pins = < |
| 133 | 0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */ | 204 | 0xe2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ |
| 134 | 0xe4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */ | 205 | 0xe4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ |
| 135 | >; | 206 | >; |
| 136 | }; | 207 | }; |
| 137 | 208 | ||
| 138 | i2c2_pins: pinmux_i2c2_pins { | 209 | i2c2_pins: pinmux_i2c2_pins { |
| 139 | pinctrl-single,pins = < | 210 | pinctrl-single,pins = < |
| 140 | 0xe6 0x118 /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */ | 211 | 0xe6 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ |
| 141 | 0xe8 0x118 /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */ | 212 | 0xe8 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ |
| 142 | >; | 213 | >; |
| 143 | }; | 214 | }; |
| 144 | 215 | ||
| 145 | i2c3_pins: pinmux_i2c3_pins { | 216 | i2c3_pins: pinmux_i2c3_pins { |
| 146 | pinctrl-single,pins = < | 217 | pinctrl-single,pins = < |
| 147 | 0xea 0x118 /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */ | 218 | 0xea (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ |
| 148 | 0xec 0x118 /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */ | 219 | 0xec (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ |
| 149 | >; | 220 | >; |
| 150 | }; | 221 | }; |
| 151 | 222 | ||
| 152 | i2c4_pins: pinmux_i2c4_pins { | 223 | i2c4_pins: pinmux_i2c4_pins { |
| 153 | pinctrl-single,pins = < | 224 | pinctrl-single,pins = < |
| 154 | 0xee 0x118 /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */ | 225 | 0xee (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ |
| 155 | 0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */ | 226 | 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ |
| 227 | >; | ||
| 228 | }; | ||
| 229 | }; | ||
| 230 | |||
| 231 | &omap4_pmx_wkup { | ||
| 232 | led_wkgpio_pins: pinmux_leds_wkpins { | ||
| 233 | pinctrl-single,pins = < | ||
| 234 | 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */ | ||
| 235 | 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ | ||
| 156 | >; | 236 | >; |
| 157 | }; | 237 | }; |
| 158 | }; | 238 | }; |
| @@ -165,18 +245,18 @@ | |||
| 165 | 245 | ||
| 166 | twl: twl@48 { | 246 | twl: twl@48 { |
| 167 | reg = <0x48>; | 247 | reg = <0x48>; |
| 168 | /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ | 248 | /* IRQ# = 7 */ |
| 169 | interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ | 249 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ |
| 170 | interrupt-parent = <&gic>; | 250 | interrupt-parent = <&gic>; |
| 171 | }; | 251 | }; |
| 172 | 252 | ||
| 173 | twl6040: twl@4b { | 253 | twl6040: twl@4b { |
| 174 | compatible = "ti,twl6040"; | 254 | compatible = "ti,twl6040"; |
| 175 | reg = <0x4b>; | 255 | reg = <0x4b>; |
| 176 | /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ | 256 | /* IRQ# = 119 */ |
| 177 | interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ | 257 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ |
| 178 | interrupt-parent = <&gic>; | 258 | interrupt-parent = <&gic>; |
| 179 | ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ | 259 | ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ |
| 180 | 260 | ||
| 181 | vio-supply = <&v1v8>; | 261 | vio-supply = <&v1v8>; |
| 182 | v2v1-supply = <&v2v1>; | 262 | v2v1-supply = <&v2v1>; |
| @@ -184,7 +264,7 @@ | |||
| 184 | }; | 264 | }; |
| 185 | }; | 265 | }; |
| 186 | 266 | ||
| 187 | /include/ "twl6030.dtsi" | 267 | #include "twl6030.dtsi" |
| 188 | 268 | ||
| 189 | &i2c2 { | 269 | &i2c2 { |
| 190 | pinctrl-names = "default"; | 270 | pinctrl-names = "default"; |
| @@ -269,3 +349,11 @@ | |||
| 269 | mode = <3>; | 349 | mode = <3>; |
| 270 | power = <50>; | 350 | power = <50>; |
| 271 | }; | 351 | }; |
| 352 | |||
| 353 | &usbhshost { | ||
| 354 | port1-mode = "ehci-phy"; | ||
| 355 | }; | ||
| 356 | |||
| 357 | &usbhsehci { | ||
| 358 | phys = <&hsusb1_phy>; | ||
| 359 | }; | ||
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index f1d8c217ce12..56c435468e94 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts | |||
| @@ -7,8 +7,8 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap4460.dtsi" | 10 | #include "omap4460.dtsi" |
| 11 | /include/ "omap4-panda-common.dtsi" | 11 | #include "omap4-panda-common.dtsi" |
| 12 | 12 | ||
| 13 | /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ | 13 | /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ |
| 14 | &sound { | 14 | &sound { |
| @@ -29,8 +29,36 @@ | |||
| 29 | /* PandaboardES has external pullups on SCL & SDA */ | 29 | /* PandaboardES has external pullups on SCL & SDA */ |
| 30 | &dss_hdmi_pins { | 30 | &dss_hdmi_pins { |
| 31 | pinctrl-single,pins = < | 31 | pinctrl-single,pins = < |
| 32 | 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ | 32 | 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ |
| 33 | 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */ | 33 | 0x5c (PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ |
| 34 | 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */ | 34 | 0x5e (PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ |
| 35 | >; | 35 | >; |
| 36 | }; | 36 | }; |
| 37 | |||
| 38 | &omap4_pmx_core { | ||
| 39 | led_gpio_pins: gpio_led_pmx { | ||
| 40 | pinctrl-single,pins = < | ||
| 41 | 0xb6 (PIN_OUTPUT | MUX_MODE3) /* gpio_110 */ | ||
| 42 | >; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &led_wkgpio_pins { | ||
| 47 | pinctrl-single,pins = < | ||
| 48 | 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ | ||
| 49 | >; | ||
| 50 | }; | ||
| 51 | |||
| 52 | &leds { | ||
| 53 | pinctrl-0 = < | ||
| 54 | &led_gpio_pins | ||
| 55 | &led_wkgpio_pins | ||
| 56 | >; | ||
| 57 | |||
| 58 | heartbeat { | ||
| 59 | gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; | ||
| 60 | }; | ||
| 61 | mmc { | ||
| 62 | gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; | ||
| 63 | }; | ||
| 64 | }; | ||
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index f8b221f0168e..6189a8b77d7f 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts | |||
| @@ -7,5 +7,5 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap443x.dtsi" | 10 | #include "omap443x.dtsi" |
| 11 | /include/ "omap4-panda-common.dtsi" | 11 | #include "omap4-panda-common.dtsi" |
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts index b4a40ffbce31..aad5dda0f469 100644 --- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts +++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts | |||
| @@ -5,13 +5,13 @@ | |||
| 5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | /include/ "omap4-sdp.dts" | 8 | #include "omap4-sdp.dts" |
| 9 | 9 | ||
| 10 | /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */ | 10 | /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */ |
| 11 | &dss_hdmi_pins { | 11 | &dss_hdmi_pins { |
| 12 | pinctrl-single,pins = < | 12 | pinctrl-single,pins = < |
| 13 | 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ | 13 | 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ |
| 14 | 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */ | 14 | 0x5c (PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */ |
| 15 | 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */ | 15 | 0x5e (PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */ |
| 16 | >; | 16 | >; |
| 17 | }; | 17 | }; |
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 98505a2ef162..7951b4ea500a 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts | |||
| @@ -7,8 +7,8 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap443x.dtsi" | 10 | #include "omap443x.dtsi" |
| 11 | /include/ "elpida_ecb240abacn.dtsi" | 11 | #include "elpida_ecb240abacn.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | model = "TI OMAP4 SDP board"; | 14 | model = "TI OMAP4 SDP board"; |
| @@ -41,42 +41,42 @@ | |||
| 41 | compatible = "gpio-leds"; | 41 | compatible = "gpio-leds"; |
| 42 | debug0 { | 42 | debug0 { |
| 43 | label = "omap4:green:debug0"; | 43 | label = "omap4:green:debug0"; |
| 44 | gpios = <&gpio2 29 0>; /* 61 */ | 44 | gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */ |
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| 47 | debug1 { | 47 | debug1 { |
| 48 | label = "omap4:green:debug1"; | 48 | label = "omap4:green:debug1"; |
| 49 | gpios = <&gpio1 30 0>; /* 30 */ | 49 | gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */ |
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | debug2 { | 52 | debug2 { |
| 53 | label = "omap4:green:debug2"; | 53 | label = "omap4:green:debug2"; |
| 54 | gpios = <&gpio1 7 0>; /* 7 */ | 54 | gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */ |
| 55 | }; | 55 | }; |
| 56 | 56 | ||
| 57 | debug3 { | 57 | debug3 { |
| 58 | label = "omap4:green:debug3"; | 58 | label = "omap4:green:debug3"; |
| 59 | gpios = <&gpio1 8 0>; /* 8 */ | 59 | gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */ |
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| 62 | debug4 { | 62 | debug4 { |
| 63 | label = "omap4:green:debug4"; | 63 | label = "omap4:green:debug4"; |
| 64 | gpios = <&gpio2 18 0>; /* 50 */ | 64 | gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */ |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| 67 | user1 { | 67 | user1 { |
| 68 | label = "omap4:blue:user"; | 68 | label = "omap4:blue:user"; |
| 69 | gpios = <&gpio6 9 0>; /* 169 */ | 69 | gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */ |
| 70 | }; | 70 | }; |
| 71 | 71 | ||
| 72 | user2 { | 72 | user2 { |
| 73 | label = "omap4:red:user"; | 73 | label = "omap4:red:user"; |
| 74 | gpios = <&gpio6 10 0>; /* 170 */ | 74 | gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */ |
| 75 | }; | 75 | }; |
| 76 | 76 | ||
| 77 | user3 { | 77 | user3 { |
| 78 | label = "omap4:green:user"; | 78 | label = "omap4:green:user"; |
| 79 | gpios = <&gpio5 11 0>; /* 139 */ | 79 | gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */ |
| 80 | }; | 80 | }; |
| 81 | }; | 81 | }; |
| 82 | 82 | ||
| @@ -150,7 +150,7 @@ | |||
| 150 | 150 | ||
| 151 | twl6030_wkup_pins: pinmux_twl6030_wkup_pins { | 151 | twl6030_wkup_pins: pinmux_twl6030_wkup_pins { |
| 152 | pinctrl-single,pins = < | 152 | pinctrl-single,pins = < |
| 153 | 0x14 0x2 /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */ | 153 | 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */ |
| 154 | >; | 154 | >; |
| 155 | }; | 155 | }; |
| 156 | }; | 156 | }; |
| @@ -170,129 +170,129 @@ | |||
| 170 | 170 | ||
| 171 | uart2_pins: pinmux_uart2_pins { | 171 | uart2_pins: pinmux_uart2_pins { |
| 172 | pinctrl-single,pins = < | 172 | pinctrl-single,pins = < |
| 173 | 0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */ | 173 | 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ |
| 174 | 0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */ | 174 | 0xda (PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ |
| 175 | 0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */ | 175 | 0xdc (PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ |
| 176 | 0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */ | 176 | 0xde (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ |
| 177 | >; | 177 | >; |
| 178 | }; | 178 | }; |
| 179 | 179 | ||
| 180 | uart3_pins: pinmux_uart3_pins { | 180 | uart3_pins: pinmux_uart3_pins { |
| 181 | pinctrl-single,pins = < | 181 | pinctrl-single,pins = < |
| 182 | 0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */ | 182 | 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ |
| 183 | 0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */ | 183 | 0x102 (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ |
| 184 | 0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */ | 184 | 0x104 (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ |
| 185 | 0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ | 185 | 0x106 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ |
| 186 | >; | 186 | >; |
| 187 | }; | 187 | }; |
| 188 | 188 | ||
| 189 | uart4_pins: pinmux_uart4_pins { | 189 | uart4_pins: pinmux_uart4_pins { |
| 190 | pinctrl-single,pins = < | 190 | pinctrl-single,pins = < |
| 191 | 0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */ | 191 | 0x11c (PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */ |
| 192 | 0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */ | 192 | 0x11e (PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */ |
| 193 | >; | 193 | >; |
| 194 | }; | 194 | }; |
| 195 | 195 | ||
| 196 | twl6030_pins: pinmux_twl6030_pins { | 196 | twl6030_pins: pinmux_twl6030_pins { |
| 197 | pinctrl-single,pins = < | 197 | pinctrl-single,pins = < |
| 198 | 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */ | 198 | 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */ |
| 199 | >; | 199 | >; |
| 200 | }; | 200 | }; |
| 201 | 201 | ||
| 202 | twl6040_pins: pinmux_twl6040_pins { | 202 | twl6040_pins: pinmux_twl6040_pins { |
| 203 | pinctrl-single,pins = < | 203 | pinctrl-single,pins = < |
| 204 | 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ | 204 | 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ |
| 205 | 0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */ | 205 | 0x160 (PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */ |
| 206 | >; | 206 | >; |
| 207 | }; | 207 | }; |
| 208 | 208 | ||
| 209 | mcpdm_pins: pinmux_mcpdm_pins { | 209 | mcpdm_pins: pinmux_mcpdm_pins { |
| 210 | pinctrl-single,pins = < | 210 | pinctrl-single,pins = < |
| 211 | 0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */ | 211 | 0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_ul_data.abe_pdm_ul_data */ |
| 212 | 0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */ | 212 | 0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_dl_data.abe_pdm_dl_data */ |
| 213 | 0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */ | 213 | 0xca (PIN_INPUT_PULLUP | MUX_MODE0) /* abe_pdm_frame.abe_pdm_frame */ |
| 214 | 0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */ | 214 | 0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_pdm_lb_clk.abe_pdm_lb_clk */ |
| 215 | 0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ | 215 | 0xce (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ |
| 216 | >; | 216 | >; |
| 217 | }; | 217 | }; |
| 218 | 218 | ||
| 219 | dmic_pins: pinmux_dmic_pins { | 219 | dmic_pins: pinmux_dmic_pins { |
| 220 | pinctrl-single,pins = < | 220 | pinctrl-single,pins = < |
| 221 | 0xd0 0 /* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */ | 221 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */ |
| 222 | 0xd2 0x100 /* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */ | 222 | 0xd2 (PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */ |
| 223 | 0xd4 0x100 /* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */ | 223 | 0xd4 (PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */ |
| 224 | 0xd6 0x100 /* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */ | 224 | 0xd6 (PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */ |
| 225 | >; | 225 | >; |
| 226 | }; | 226 | }; |
| 227 | 227 | ||
| 228 | mcbsp1_pins: pinmux_mcbsp1_pins { | 228 | mcbsp1_pins: pinmux_mcbsp1_pins { |
| 229 | pinctrl-single,pins = < | 229 | pinctrl-single,pins = < |
| 230 | 0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */ | 230 | 0xbe (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */ |
| 231 | 0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */ | 231 | 0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */ |
| 232 | 0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */ | 232 | 0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */ |
| 233 | 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ | 233 | 0xc4 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */ |
| 234 | >; | 234 | >; |
| 235 | }; | 235 | }; |
| 236 | 236 | ||
| 237 | mcbsp2_pins: pinmux_mcbsp2_pins { | 237 | mcbsp2_pins: pinmux_mcbsp2_pins { |
| 238 | pinctrl-single,pins = < | 238 | pinctrl-single,pins = < |
| 239 | 0xb6 0x100 /* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */ | 239 | 0xb6 (PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */ |
| 240 | 0xb8 0x108 /* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */ | 240 | 0xb8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */ |
| 241 | 0xba 0x8 /* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */ | 241 | 0xba (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */ |
| 242 | 0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */ | 242 | 0xbc (PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */ |
| 243 | >; | 243 | >; |
| 244 | }; | 244 | }; |
| 245 | 245 | ||
| 246 | mcspi1_pins: pinmux_mcspi1_pins { | 246 | mcspi1_pins: pinmux_mcspi1_pins { |
| 247 | pinctrl-single,pins = < | 247 | pinctrl-single,pins = < |
| 248 | 0xf2 0x100 /* mcspi1_clk.mcspi1_clk INPUT | MODE0 */ | 248 | 0xf2 (PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ |
| 249 | 0xf4 0x100 /* mcspi1_somi.mcspi1_somi INPUT | MODE0 */ | 249 | 0xf4 (PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ |
| 250 | 0xf6 0x100 /* mcspi1_simo.mcspi1_simo INPUT | MODE0 */ | 250 | 0xf6 (PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ |
| 251 | 0xf8 0x100 /* mcspi1_cs0.mcspi1_cs0 INPUT | MODE0*/ | 251 | 0xf8 (PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ |
| 252 | >; | 252 | >; |
| 253 | }; | 253 | }; |
| 254 | 254 | ||
| 255 | dss_hdmi_pins: pinmux_dss_hdmi_pins { | 255 | dss_hdmi_pins: pinmux_dss_hdmi_pins { |
| 256 | pinctrl-single,pins = < | 256 | pinctrl-single,pins = < |
| 257 | 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */ | 257 | 0x5a (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec.hdmi_cec */ |
| 258 | 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */ | 258 | 0x5c (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */ |
| 259 | 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */ | 259 | 0x5e (PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */ |
| 260 | >; | 260 | >; |
| 261 | }; | 261 | }; |
| 262 | 262 | ||
| 263 | tpd12s015_pins: pinmux_tpd12s015_pins { | 263 | tpd12s015_pins: pinmux_tpd12s015_pins { |
| 264 | pinctrl-single,pins = < | 264 | pinctrl-single,pins = < |
| 265 | 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */ | 265 | 0x22 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */ |
| 266 | 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */ | 266 | 0x48 (PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */ |
| 267 | 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */ | 267 | 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */ |
| 268 | >; | 268 | >; |
| 269 | }; | 269 | }; |
| 270 | 270 | ||
| 271 | i2c1_pins: pinmux_i2c1_pins { | 271 | i2c1_pins: pinmux_i2c1_pins { |
| 272 | pinctrl-single,pins = < | 272 | pinctrl-single,pins = < |
| 273 | 0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */ | 273 | 0xe2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ |
| 274 | 0xe4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */ | 274 | 0xe4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ |
| 275 | >; | 275 | >; |
| 276 | }; | 276 | }; |
| 277 | 277 | ||
| 278 | i2c2_pins: pinmux_i2c2_pins { | 278 | i2c2_pins: pinmux_i2c2_pins { |
| 279 | pinctrl-single,pins = < | 279 | pinctrl-single,pins = < |
| 280 | 0xe6 0x118 /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */ | 280 | 0xe6 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ |
| 281 | 0xe8 0x118 /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */ | 281 | 0xe8 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ |
| 282 | >; | 282 | >; |
| 283 | }; | 283 | }; |
| 284 | 284 | ||
| 285 | i2c3_pins: pinmux_i2c3_pins { | 285 | i2c3_pins: pinmux_i2c3_pins { |
| 286 | pinctrl-single,pins = < | 286 | pinctrl-single,pins = < |
| 287 | 0xea 0x118 /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */ | 287 | 0xea (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ |
| 288 | 0xec 0x118 /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */ | 288 | 0xec (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ |
| 289 | >; | 289 | >; |
| 290 | }; | 290 | }; |
| 291 | 291 | ||
| 292 | i2c4_pins: pinmux_i2c4_pins { | 292 | i2c4_pins: pinmux_i2c4_pins { |
| 293 | pinctrl-single,pins = < | 293 | pinctrl-single,pins = < |
| 294 | 0xee 0x118 /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */ | 294 | 0xee (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ |
| 295 | 0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */ | 295 | 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ |
| 296 | >; | 296 | >; |
| 297 | }; | 297 | }; |
| 298 | }; | 298 | }; |
| @@ -306,7 +306,7 @@ | |||
| 306 | twl: twl@48 { | 306 | twl: twl@48 { |
| 307 | reg = <0x48>; | 307 | reg = <0x48>; |
| 308 | /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ | 308 | /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ |
| 309 | interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ | 309 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ |
| 310 | interrupt-parent = <&gic>; | 310 | interrupt-parent = <&gic>; |
| 311 | }; | 311 | }; |
| 312 | 312 | ||
| @@ -314,7 +314,7 @@ | |||
| 314 | compatible = "ti,twl6040"; | 314 | compatible = "ti,twl6040"; |
| 315 | reg = <0x4b>; | 315 | reg = <0x4b>; |
| 316 | /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ | 316 | /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ |
| 317 | interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ | 317 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */ |
| 318 | interrupt-parent = <&gic>; | 318 | interrupt-parent = <&gic>; |
| 319 | ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ | 319 | ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ |
| 320 | 320 | ||
| @@ -336,7 +336,7 @@ | |||
| 336 | }; | 336 | }; |
| 337 | }; | 337 | }; |
| 338 | 338 | ||
| 339 | /include/ "twl6030.dtsi" | 339 | #include "twl6030.dtsi" |
| 340 | 340 | ||
| 341 | &i2c2 { | 341 | &i2c2 { |
| 342 | pinctrl-names = "default"; | 342 | pinctrl-names = "default"; |
| @@ -395,7 +395,7 @@ | |||
| 395 | spi-max-frequency = <24000000>; | 395 | spi-max-frequency = <24000000>; |
| 396 | reg = <0>; | 396 | reg = <0>; |
| 397 | interrupt-parent = <&gpio2>; | 397 | interrupt-parent = <&gpio2>; |
| 398 | interrupts = <2 8>; /* gpio line 34, low triggered */ | 398 | interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */ |
| 399 | vdd-supply = <&vdd_eth>; | 399 | vdd-supply = <&vdd_eth>; |
| 400 | }; | 400 | }; |
| 401 | }; | 401 | }; |
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts index 7e04103779c4..b41269e871dd 100644 --- a/arch/arm/boot/dts/omap4-var-som.dts +++ b/arch/arm/boot/dts/omap4-var-som.dts | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | 9 | ||
| 10 | /include/ "omap443x.dtsi" | 10 | #include "omap443x.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | model = "Variscite OMAP4 SOM"; | 13 | model = "Variscite OMAP4 SOM"; |
| @@ -34,12 +34,12 @@ | |||
| 34 | twl: twl@48 { | 34 | twl: twl@48 { |
| 35 | reg = <0x48>; | 35 | reg = <0x48>; |
| 36 | /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ | 36 | /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ |
| 37 | interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ | 37 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ |
| 38 | interrupt-parent = <&gic>; | 38 | interrupt-parent = <&gic>; |
| 39 | }; | 39 | }; |
| 40 | }; | 40 | }; |
| 41 | 41 | ||
| 42 | /include/ "twl6030.dtsi" | 42 | #include "twl6030.dtsi" |
| 43 | 43 | ||
| 44 | &i2c2 { | 44 | &i2c2 { |
| 45 | clock-frequency = <400000>; | 45 | clock-frequency = <400000>; |
| @@ -68,7 +68,7 @@ | |||
| 68 | spi-max-frequency = <24000000>; | 68 | spi-max-frequency = <24000000>; |
| 69 | reg = <0>; | 69 | reg = <0>; |
| 70 | interrupt-parent = <&gpio6>; | 70 | interrupt-parent = <&gpio6>; |
| 71 | interrupts = <11 8>; /* gpio line 171, low triggered */ | 71 | interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171 */ |
| 72 | vdd-supply = <&vdd_eth>; | 72 | vdd-supply = <&vdd_eth>; |
| 73 | }; | 73 | }; |
| 74 | }; | 74 | }; |
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 2a5642882c8a..22d9f2b593d4 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi | |||
| @@ -6,15 +6,11 @@ | |||
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* | 9 | #include <dt-bindings/gpio/gpio.h> |
| 10 | * Carveout for multimedia usecases | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 11 | * It should be the last 48MB of the first 512MB memory part | 11 | #include <dt-bindings/pinctrl/omap.h> |
| 12 | * In theory, it should not even exist. That zone should be reserved | ||
| 13 | * dynamically during the .reserve callback. | ||
| 14 | */ | ||
| 15 | /memreserve/ 0x9d000000 0x03000000; | ||
| 16 | 12 | ||
| 17 | /include/ "skeleton.dtsi" | 13 | #include "skeleton.dtsi" |
| 18 | 14 | ||
| 19 | / { | 15 | / { |
| 20 | compatible = "ti,omap4430", "ti,omap4"; | 16 | compatible = "ti,omap4430", "ti,omap4"; |
| @@ -28,13 +24,20 @@ | |||
| 28 | }; | 24 | }; |
| 29 | 25 | ||
| 30 | cpus { | 26 | cpus { |
| 27 | #address-cells = <1>; | ||
| 28 | #size-cells = <0>; | ||
| 29 | |||
| 31 | cpu@0 { | 30 | cpu@0 { |
| 32 | compatible = "arm,cortex-a9"; | 31 | compatible = "arm,cortex-a9"; |
| 32 | device_type = "cpu"; | ||
| 33 | next-level-cache = <&L2>; | 33 | next-level-cache = <&L2>; |
| 34 | reg = <0x0>; | ||
| 34 | }; | 35 | }; |
| 35 | cpu@1 { | 36 | cpu@1 { |
| 36 | compatible = "arm,cortex-a9"; | 37 | compatible = "arm,cortex-a9"; |
| 38 | device_type = "cpu"; | ||
| 37 | next-level-cache = <&L2>; | 39 | next-level-cache = <&L2>; |
| 40 | reg = <0x1>; | ||
| 38 | }; | 41 | }; |
| 39 | }; | 42 | }; |
| 40 | 43 | ||
| @@ -56,7 +59,7 @@ | |||
| 56 | local-timer@0x48240600 { | 59 | local-timer@0x48240600 { |
| 57 | compatible = "arm,cortex-a9-twd-timer"; | 60 | compatible = "arm,cortex-a9-twd-timer"; |
| 58 | reg = <0x48240600 0x20>; | 61 | reg = <0x48240600 0x20>; |
| 59 | interrupts = <1 13 0x304>; | 62 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; |
| 60 | }; | 63 | }; |
| 61 | 64 | ||
| 62 | /* | 65 | /* |
| @@ -97,8 +100,8 @@ | |||
| 97 | reg = <0x44000000 0x1000>, | 100 | reg = <0x44000000 0x1000>, |
| 98 | <0x44800000 0x2000>, | 101 | <0x44800000 0x2000>, |
| 99 | <0x45000000 0x1000>; | 102 | <0x45000000 0x1000>; |
| 100 | interrupts = <0 9 0x4>, | 103 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 101 | <0 10 0x4>; | 104 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 102 | 105 | ||
| 103 | counter32k: counter@4a304000 { | 106 | counter32k: counter@4a304000 { |
| 104 | compatible = "ti,omap-counter32k"; | 107 | compatible = "ti,omap-counter32k"; |
| @@ -126,10 +129,10 @@ | |||
| 126 | sdma: dma-controller@4a056000 { | 129 | sdma: dma-controller@4a056000 { |
| 127 | compatible = "ti,omap4430-sdma"; | 130 | compatible = "ti,omap4430-sdma"; |
| 128 | reg = <0x4a056000 0x1000>; | 131 | reg = <0x4a056000 0x1000>; |
| 129 | interrupts = <0 12 0x4>, | 132 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 130 | <0 13 0x4>, | 133 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 131 | <0 14 0x4>, | 134 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 132 | <0 15 0x4>; | 135 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 133 | #dma-cells = <1>; | 136 | #dma-cells = <1>; |
| 134 | #dma-channels = <32>; | 137 | #dma-channels = <32>; |
| 135 | #dma-requests = <127>; | 138 | #dma-requests = <127>; |
| @@ -138,7 +141,7 @@ | |||
| 138 | gpio1: gpio@4a310000 { | 141 | gpio1: gpio@4a310000 { |
| 139 | compatible = "ti,omap4-gpio"; | 142 | compatible = "ti,omap4-gpio"; |
| 140 | reg = <0x4a310000 0x200>; | 143 | reg = <0x4a310000 0x200>; |
| 141 | interrupts = <0 29 0x4>; | 144 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| 142 | ti,hwmods = "gpio1"; | 145 | ti,hwmods = "gpio1"; |
| 143 | ti,gpio-always-on; | 146 | ti,gpio-always-on; |
| 144 | gpio-controller; | 147 | gpio-controller; |
| @@ -150,7 +153,7 @@ | |||
| 150 | gpio2: gpio@48055000 { | 153 | gpio2: gpio@48055000 { |
| 151 | compatible = "ti,omap4-gpio"; | 154 | compatible = "ti,omap4-gpio"; |
| 152 | reg = <0x48055000 0x200>; | 155 | reg = <0x48055000 0x200>; |
| 153 | interrupts = <0 30 0x4>; | 156 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 154 | ti,hwmods = "gpio2"; | 157 | ti,hwmods = "gpio2"; |
| 155 | gpio-controller; | 158 | gpio-controller; |
| 156 | #gpio-cells = <2>; | 159 | #gpio-cells = <2>; |
| @@ -161,7 +164,7 @@ | |||
| 161 | gpio3: gpio@48057000 { | 164 | gpio3: gpio@48057000 { |
| 162 | compatible = "ti,omap4-gpio"; | 165 | compatible = "ti,omap4-gpio"; |
| 163 | reg = <0x48057000 0x200>; | 166 | reg = <0x48057000 0x200>; |
| 164 | interrupts = <0 31 0x4>; | 167 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 165 | ti,hwmods = "gpio3"; | 168 | ti,hwmods = "gpio3"; |
| 166 | gpio-controller; | 169 | gpio-controller; |
| 167 | #gpio-cells = <2>; | 170 | #gpio-cells = <2>; |
| @@ -172,7 +175,7 @@ | |||
| 172 | gpio4: gpio@48059000 { | 175 | gpio4: gpio@48059000 { |
| 173 | compatible = "ti,omap4-gpio"; | 176 | compatible = "ti,omap4-gpio"; |
| 174 | reg = <0x48059000 0x200>; | 177 | reg = <0x48059000 0x200>; |
| 175 | interrupts = <0 32 0x4>; | 178 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 176 | ti,hwmods = "gpio4"; | 179 | ti,hwmods = "gpio4"; |
| 177 | gpio-controller; | 180 | gpio-controller; |
| 178 | #gpio-cells = <2>; | 181 | #gpio-cells = <2>; |
| @@ -183,7 +186,7 @@ | |||
| 183 | gpio5: gpio@4805b000 { | 186 | gpio5: gpio@4805b000 { |
| 184 | compatible = "ti,omap4-gpio"; | 187 | compatible = "ti,omap4-gpio"; |
| 185 | reg = <0x4805b000 0x200>; | 188 | reg = <0x4805b000 0x200>; |
| 186 | interrupts = <0 33 0x4>; | 189 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| 187 | ti,hwmods = "gpio5"; | 190 | ti,hwmods = "gpio5"; |
| 188 | gpio-controller; | 191 | gpio-controller; |
| 189 | #gpio-cells = <2>; | 192 | #gpio-cells = <2>; |
| @@ -194,7 +197,7 @@ | |||
| 194 | gpio6: gpio@4805d000 { | 197 | gpio6: gpio@4805d000 { |
| 195 | compatible = "ti,omap4-gpio"; | 198 | compatible = "ti,omap4-gpio"; |
| 196 | reg = <0x4805d000 0x200>; | 199 | reg = <0x4805d000 0x200>; |
| 197 | interrupts = <0 34 0x4>; | 200 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| 198 | ti,hwmods = "gpio6"; | 201 | ti,hwmods = "gpio6"; |
| 199 | gpio-controller; | 202 | gpio-controller; |
| 200 | #gpio-cells = <2>; | 203 | #gpio-cells = <2>; |
| @@ -207,7 +210,7 @@ | |||
| 207 | reg = <0x50000000 0x1000>; | 210 | reg = <0x50000000 0x1000>; |
| 208 | #address-cells = <2>; | 211 | #address-cells = <2>; |
| 209 | #size-cells = <1>; | 212 | #size-cells = <1>; |
| 210 | interrupts = <0 20 0x4>; | 213 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 211 | gpmc,num-cs = <8>; | 214 | gpmc,num-cs = <8>; |
| 212 | gpmc,num-waitpins = <4>; | 215 | gpmc,num-waitpins = <4>; |
| 213 | ti,hwmods = "gpmc"; | 216 | ti,hwmods = "gpmc"; |
| @@ -216,7 +219,7 @@ | |||
| 216 | uart1: serial@4806a000 { | 219 | uart1: serial@4806a000 { |
| 217 | compatible = "ti,omap4-uart"; | 220 | compatible = "ti,omap4-uart"; |
| 218 | reg = <0x4806a000 0x100>; | 221 | reg = <0x4806a000 0x100>; |
| 219 | interrupts = <0 72 0x4>; | 222 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| 220 | ti,hwmods = "uart1"; | 223 | ti,hwmods = "uart1"; |
| 221 | clock-frequency = <48000000>; | 224 | clock-frequency = <48000000>; |
| 222 | }; | 225 | }; |
| @@ -224,7 +227,7 @@ | |||
| 224 | uart2: serial@4806c000 { | 227 | uart2: serial@4806c000 { |
| 225 | compatible = "ti,omap4-uart"; | 228 | compatible = "ti,omap4-uart"; |
| 226 | reg = <0x4806c000 0x100>; | 229 | reg = <0x4806c000 0x100>; |
| 227 | interrupts = <0 73 0x4>; | 230 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 228 | ti,hwmods = "uart2"; | 231 | ti,hwmods = "uart2"; |
| 229 | clock-frequency = <48000000>; | 232 | clock-frequency = <48000000>; |
| 230 | }; | 233 | }; |
| @@ -232,7 +235,7 @@ | |||
| 232 | uart3: serial@48020000 { | 235 | uart3: serial@48020000 { |
| 233 | compatible = "ti,omap4-uart"; | 236 | compatible = "ti,omap4-uart"; |
| 234 | reg = <0x48020000 0x100>; | 237 | reg = <0x48020000 0x100>; |
| 235 | interrupts = <0 74 0x4>; | 238 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 236 | ti,hwmods = "uart3"; | 239 | ti,hwmods = "uart3"; |
| 237 | clock-frequency = <48000000>; | 240 | clock-frequency = <48000000>; |
| 238 | }; | 241 | }; |
| @@ -240,7 +243,7 @@ | |||
| 240 | uart4: serial@4806e000 { | 243 | uart4: serial@4806e000 { |
| 241 | compatible = "ti,omap4-uart"; | 244 | compatible = "ti,omap4-uart"; |
| 242 | reg = <0x4806e000 0x100>; | 245 | reg = <0x4806e000 0x100>; |
| 243 | interrupts = <0 70 0x4>; | 246 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 244 | ti,hwmods = "uart4"; | 247 | ti,hwmods = "uart4"; |
| 245 | clock-frequency = <48000000>; | 248 | clock-frequency = <48000000>; |
| 246 | }; | 249 | }; |
| @@ -248,7 +251,7 @@ | |||
| 248 | i2c1: i2c@48070000 { | 251 | i2c1: i2c@48070000 { |
| 249 | compatible = "ti,omap4-i2c"; | 252 | compatible = "ti,omap4-i2c"; |
| 250 | reg = <0x48070000 0x100>; | 253 | reg = <0x48070000 0x100>; |
| 251 | interrupts = <0 56 0x4>; | 254 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| 252 | #address-cells = <1>; | 255 | #address-cells = <1>; |
| 253 | #size-cells = <0>; | 256 | #size-cells = <0>; |
| 254 | ti,hwmods = "i2c1"; | 257 | ti,hwmods = "i2c1"; |
| @@ -257,7 +260,7 @@ | |||
| 257 | i2c2: i2c@48072000 { | 260 | i2c2: i2c@48072000 { |
| 258 | compatible = "ti,omap4-i2c"; | 261 | compatible = "ti,omap4-i2c"; |
| 259 | reg = <0x48072000 0x100>; | 262 | reg = <0x48072000 0x100>; |
| 260 | interrupts = <0 57 0x4>; | 263 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| 261 | #address-cells = <1>; | 264 | #address-cells = <1>; |
| 262 | #size-cells = <0>; | 265 | #size-cells = <0>; |
| 263 | ti,hwmods = "i2c2"; | 266 | ti,hwmods = "i2c2"; |
| @@ -266,7 +269,7 @@ | |||
| 266 | i2c3: i2c@48060000 { | 269 | i2c3: i2c@48060000 { |
| 267 | compatible = "ti,omap4-i2c"; | 270 | compatible = "ti,omap4-i2c"; |
| 268 | reg = <0x48060000 0x100>; | 271 | reg = <0x48060000 0x100>; |
| 269 | interrupts = <0 61 0x4>; | 272 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| 270 | #address-cells = <1>; | 273 | #address-cells = <1>; |
| 271 | #size-cells = <0>; | 274 | #size-cells = <0>; |
| 272 | ti,hwmods = "i2c3"; | 275 | ti,hwmods = "i2c3"; |
| @@ -275,7 +278,7 @@ | |||
| 275 | i2c4: i2c@48350000 { | 278 | i2c4: i2c@48350000 { |
| 276 | compatible = "ti,omap4-i2c"; | 279 | compatible = "ti,omap4-i2c"; |
| 277 | reg = <0x48350000 0x100>; | 280 | reg = <0x48350000 0x100>; |
| 278 | interrupts = <0 62 0x4>; | 281 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| 279 | #address-cells = <1>; | 282 | #address-cells = <1>; |
| 280 | #size-cells = <0>; | 283 | #size-cells = <0>; |
| 281 | ti,hwmods = "i2c4"; | 284 | ti,hwmods = "i2c4"; |
| @@ -284,7 +287,7 @@ | |||
| 284 | mcspi1: spi@48098000 { | 287 | mcspi1: spi@48098000 { |
| 285 | compatible = "ti,omap4-mcspi"; | 288 | compatible = "ti,omap4-mcspi"; |
| 286 | reg = <0x48098000 0x200>; | 289 | reg = <0x48098000 0x200>; |
| 287 | interrupts = <0 65 0x4>; | 290 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 288 | #address-cells = <1>; | 291 | #address-cells = <1>; |
| 289 | #size-cells = <0>; | 292 | #size-cells = <0>; |
| 290 | ti,hwmods = "mcspi1"; | 293 | ti,hwmods = "mcspi1"; |
| @@ -304,7 +307,7 @@ | |||
| 304 | mcspi2: spi@4809a000 { | 307 | mcspi2: spi@4809a000 { |
| 305 | compatible = "ti,omap4-mcspi"; | 308 | compatible = "ti,omap4-mcspi"; |
| 306 | reg = <0x4809a000 0x200>; | 309 | reg = <0x4809a000 0x200>; |
| 307 | interrupts = <0 66 0x4>; | 310 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| 308 | #address-cells = <1>; | 311 | #address-cells = <1>; |
| 309 | #size-cells = <0>; | 312 | #size-cells = <0>; |
| 310 | ti,hwmods = "mcspi2"; | 313 | ti,hwmods = "mcspi2"; |
| @@ -319,7 +322,7 @@ | |||
| 319 | mcspi3: spi@480b8000 { | 322 | mcspi3: spi@480b8000 { |
| 320 | compatible = "ti,omap4-mcspi"; | 323 | compatible = "ti,omap4-mcspi"; |
| 321 | reg = <0x480b8000 0x200>; | 324 | reg = <0x480b8000 0x200>; |
| 322 | interrupts = <0 91 0x4>; | 325 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| 323 | #address-cells = <1>; | 326 | #address-cells = <1>; |
| 324 | #size-cells = <0>; | 327 | #size-cells = <0>; |
| 325 | ti,hwmods = "mcspi3"; | 328 | ti,hwmods = "mcspi3"; |
| @@ -331,7 +334,7 @@ | |||
| 331 | mcspi4: spi@480ba000 { | 334 | mcspi4: spi@480ba000 { |
| 332 | compatible = "ti,omap4-mcspi"; | 335 | compatible = "ti,omap4-mcspi"; |
| 333 | reg = <0x480ba000 0x200>; | 336 | reg = <0x480ba000 0x200>; |
| 334 | interrupts = <0 48 0x4>; | 337 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| 335 | #address-cells = <1>; | 338 | #address-cells = <1>; |
| 336 | #size-cells = <0>; | 339 | #size-cells = <0>; |
| 337 | ti,hwmods = "mcspi4"; | 340 | ti,hwmods = "mcspi4"; |
| @@ -343,7 +346,7 @@ | |||
| 343 | mmc1: mmc@4809c000 { | 346 | mmc1: mmc@4809c000 { |
| 344 | compatible = "ti,omap4-hsmmc"; | 347 | compatible = "ti,omap4-hsmmc"; |
| 345 | reg = <0x4809c000 0x400>; | 348 | reg = <0x4809c000 0x400>; |
| 346 | interrupts = <0 83 0x4>; | 349 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 347 | ti,hwmods = "mmc1"; | 350 | ti,hwmods = "mmc1"; |
| 348 | ti,dual-volt; | 351 | ti,dual-volt; |
| 349 | ti,needs-special-reset; | 352 | ti,needs-special-reset; |
| @@ -354,7 +357,7 @@ | |||
| 354 | mmc2: mmc@480b4000 { | 357 | mmc2: mmc@480b4000 { |
| 355 | compatible = "ti,omap4-hsmmc"; | 358 | compatible = "ti,omap4-hsmmc"; |
| 356 | reg = <0x480b4000 0x400>; | 359 | reg = <0x480b4000 0x400>; |
| 357 | interrupts = <0 86 0x4>; | 360 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 358 | ti,hwmods = "mmc2"; | 361 | ti,hwmods = "mmc2"; |
| 359 | ti,needs-special-reset; | 362 | ti,needs-special-reset; |
| 360 | dmas = <&sdma 47>, <&sdma 48>; | 363 | dmas = <&sdma 47>, <&sdma 48>; |
| @@ -364,7 +367,7 @@ | |||
| 364 | mmc3: mmc@480ad000 { | 367 | mmc3: mmc@480ad000 { |
| 365 | compatible = "ti,omap4-hsmmc"; | 368 | compatible = "ti,omap4-hsmmc"; |
| 366 | reg = <0x480ad000 0x400>; | 369 | reg = <0x480ad000 0x400>; |
| 367 | interrupts = <0 94 0x4>; | 370 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 368 | ti,hwmods = "mmc3"; | 371 | ti,hwmods = "mmc3"; |
| 369 | ti,needs-special-reset; | 372 | ti,needs-special-reset; |
| 370 | dmas = <&sdma 77>, <&sdma 78>; | 373 | dmas = <&sdma 77>, <&sdma 78>; |
| @@ -374,7 +377,7 @@ | |||
| 374 | mmc4: mmc@480d1000 { | 377 | mmc4: mmc@480d1000 { |
| 375 | compatible = "ti,omap4-hsmmc"; | 378 | compatible = "ti,omap4-hsmmc"; |
| 376 | reg = <0x480d1000 0x400>; | 379 | reg = <0x480d1000 0x400>; |
| 377 | interrupts = <0 96 0x4>; | 380 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 378 | ti,hwmods = "mmc4"; | 381 | ti,hwmods = "mmc4"; |
| 379 | ti,needs-special-reset; | 382 | ti,needs-special-reset; |
| 380 | dmas = <&sdma 57>, <&sdma 58>; | 383 | dmas = <&sdma 57>, <&sdma 58>; |
| @@ -384,7 +387,7 @@ | |||
| 384 | mmc5: mmc@480d5000 { | 387 | mmc5: mmc@480d5000 { |
| 385 | compatible = "ti,omap4-hsmmc"; | 388 | compatible = "ti,omap4-hsmmc"; |
| 386 | reg = <0x480d5000 0x400>; | 389 | reg = <0x480d5000 0x400>; |
| 387 | interrupts = <0 59 0x4>; | 390 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 388 | ti,hwmods = "mmc5"; | 391 | ti,hwmods = "mmc5"; |
| 389 | ti,needs-special-reset; | 392 | ti,needs-special-reset; |
| 390 | dmas = <&sdma 59>, <&sdma 60>; | 393 | dmas = <&sdma 59>, <&sdma 60>; |
| @@ -394,7 +397,7 @@ | |||
| 394 | wdt2: wdt@4a314000 { | 397 | wdt2: wdt@4a314000 { |
| 395 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; | 398 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; |
| 396 | reg = <0x4a314000 0x80>; | 399 | reg = <0x4a314000 0x80>; |
| 397 | interrupts = <0 80 0x4>; | 400 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| 398 | ti,hwmods = "wd_timer2"; | 401 | ti,hwmods = "wd_timer2"; |
| 399 | }; | 402 | }; |
| 400 | 403 | ||
| @@ -403,7 +406,7 @@ | |||
| 403 | reg = <0x40132000 0x7f>, /* MPU private access */ | 406 | reg = <0x40132000 0x7f>, /* MPU private access */ |
| 404 | <0x49032000 0x7f>; /* L3 Interconnect */ | 407 | <0x49032000 0x7f>; /* L3 Interconnect */ |
| 405 | reg-names = "mpu", "dma"; | 408 | reg-names = "mpu", "dma"; |
| 406 | interrupts = <0 112 0x4>; | 409 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| 407 | ti,hwmods = "mcpdm"; | 410 | ti,hwmods = "mcpdm"; |
| 408 | dmas = <&sdma 65>, | 411 | dmas = <&sdma 65>, |
| 409 | <&sdma 66>; | 412 | <&sdma 66>; |
| @@ -415,7 +418,7 @@ | |||
| 415 | reg = <0x4012e000 0x7f>, /* MPU private access */ | 418 | reg = <0x4012e000 0x7f>, /* MPU private access */ |
| 416 | <0x4902e000 0x7f>; /* L3 Interconnect */ | 419 | <0x4902e000 0x7f>; /* L3 Interconnect */ |
| 417 | reg-names = "mpu", "dma"; | 420 | reg-names = "mpu", "dma"; |
| 418 | interrupts = <0 114 0x4>; | 421 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| 419 | ti,hwmods = "dmic"; | 422 | ti,hwmods = "dmic"; |
| 420 | dmas = <&sdma 67>; | 423 | dmas = <&sdma 67>; |
| 421 | dma-names = "up_link"; | 424 | dma-names = "up_link"; |
| @@ -426,7 +429,7 @@ | |||
| 426 | reg = <0x40122000 0xff>, /* MPU private access */ | 429 | reg = <0x40122000 0xff>, /* MPU private access */ |
| 427 | <0x49022000 0xff>; /* L3 Interconnect */ | 430 | <0x49022000 0xff>; /* L3 Interconnect */ |
| 428 | reg-names = "mpu", "dma"; | 431 | reg-names = "mpu", "dma"; |
| 429 | interrupts = <0 17 0x4>; | 432 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| 430 | interrupt-names = "common"; | 433 | interrupt-names = "common"; |
| 431 | ti,buffer-size = <128>; | 434 | ti,buffer-size = <128>; |
| 432 | ti,hwmods = "mcbsp1"; | 435 | ti,hwmods = "mcbsp1"; |
| @@ -440,7 +443,7 @@ | |||
| 440 | reg = <0x40124000 0xff>, /* MPU private access */ | 443 | reg = <0x40124000 0xff>, /* MPU private access */ |
| 441 | <0x49024000 0xff>; /* L3 Interconnect */ | 444 | <0x49024000 0xff>; /* L3 Interconnect */ |
| 442 | reg-names = "mpu", "dma"; | 445 | reg-names = "mpu", "dma"; |
| 443 | interrupts = <0 22 0x4>; | 446 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| 444 | interrupt-names = "common"; | 447 | interrupt-names = "common"; |
| 445 | ti,buffer-size = <128>; | 448 | ti,buffer-size = <128>; |
| 446 | ti,hwmods = "mcbsp2"; | 449 | ti,hwmods = "mcbsp2"; |
| @@ -454,7 +457,7 @@ | |||
| 454 | reg = <0x40126000 0xff>, /* MPU private access */ | 457 | reg = <0x40126000 0xff>, /* MPU private access */ |
| 455 | <0x49026000 0xff>; /* L3 Interconnect */ | 458 | <0x49026000 0xff>; /* L3 Interconnect */ |
| 456 | reg-names = "mpu", "dma"; | 459 | reg-names = "mpu", "dma"; |
| 457 | interrupts = <0 23 0x4>; | 460 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| 458 | interrupt-names = "common"; | 461 | interrupt-names = "common"; |
| 459 | ti,buffer-size = <128>; | 462 | ti,buffer-size = <128>; |
| 460 | ti,hwmods = "mcbsp3"; | 463 | ti,hwmods = "mcbsp3"; |
| @@ -467,7 +470,7 @@ | |||
| 467 | compatible = "ti,omap4-mcbsp"; | 470 | compatible = "ti,omap4-mcbsp"; |
| 468 | reg = <0x48096000 0xff>; /* L4 Interconnect */ | 471 | reg = <0x48096000 0xff>; /* L4 Interconnect */ |
| 469 | reg-names = "mpu"; | 472 | reg-names = "mpu"; |
| 470 | interrupts = <0 16 0x4>; | 473 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| 471 | interrupt-names = "common"; | 474 | interrupt-names = "common"; |
| 472 | ti,buffer-size = <128>; | 475 | ti,buffer-size = <128>; |
| 473 | ti,hwmods = "mcbsp4"; | 476 | ti,hwmods = "mcbsp4"; |
| @@ -479,7 +482,7 @@ | |||
| 479 | keypad: keypad@4a31c000 { | 482 | keypad: keypad@4a31c000 { |
| 480 | compatible = "ti,omap4-keypad"; | 483 | compatible = "ti,omap4-keypad"; |
| 481 | reg = <0x4a31c000 0x80>; | 484 | reg = <0x4a31c000 0x80>; |
| 482 | interrupts = <0 120 0x4>; | 485 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 483 | reg-names = "mpu"; | 486 | reg-names = "mpu"; |
| 484 | ti,hwmods = "kbd"; | 487 | ti,hwmods = "kbd"; |
| 485 | }; | 488 | }; |
| @@ -487,7 +490,7 @@ | |||
| 487 | emif1: emif@4c000000 { | 490 | emif1: emif@4c000000 { |
| 488 | compatible = "ti,emif-4d"; | 491 | compatible = "ti,emif-4d"; |
| 489 | reg = <0x4c000000 0x100>; | 492 | reg = <0x4c000000 0x100>; |
| 490 | interrupts = <0 110 0x4>; | 493 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 491 | ti,hwmods = "emif1"; | 494 | ti,hwmods = "emif1"; |
| 492 | phy-type = <1>; | 495 | phy-type = <1>; |
| 493 | hw-caps-read-idle-ctrl; | 496 | hw-caps-read-idle-ctrl; |
| @@ -498,7 +501,7 @@ | |||
| 498 | emif2: emif@4d000000 { | 501 | emif2: emif@4d000000 { |
| 499 | compatible = "ti,emif-4d"; | 502 | compatible = "ti,emif-4d"; |
| 500 | reg = <0x4d000000 0x100>; | 503 | reg = <0x4d000000 0x100>; |
| 501 | interrupts = <0 111 0x4>; | 504 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| 502 | ti,hwmods = "emif2"; | 505 | ti,hwmods = "emif2"; |
| 503 | phy-type = <1>; | 506 | phy-type = <1>; |
| 504 | hw-caps-read-idle-ctrl; | 507 | hw-caps-read-idle-ctrl; |
| @@ -523,7 +526,7 @@ | |||
| 523 | timer1: timer@4a318000 { | 526 | timer1: timer@4a318000 { |
| 524 | compatible = "ti,omap3430-timer"; | 527 | compatible = "ti,omap3430-timer"; |
| 525 | reg = <0x4a318000 0x80>; | 528 | reg = <0x4a318000 0x80>; |
| 526 | interrupts = <0 37 0x4>; | 529 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 527 | ti,hwmods = "timer1"; | 530 | ti,hwmods = "timer1"; |
| 528 | ti,timer-alwon; | 531 | ti,timer-alwon; |
| 529 | }; | 532 | }; |
| @@ -531,21 +534,21 @@ | |||
| 531 | timer2: timer@48032000 { | 534 | timer2: timer@48032000 { |
| 532 | compatible = "ti,omap3430-timer"; | 535 | compatible = "ti,omap3430-timer"; |
| 533 | reg = <0x48032000 0x80>; | 536 | reg = <0x48032000 0x80>; |
| 534 | interrupts = <0 38 0x4>; | 537 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 535 | ti,hwmods = "timer2"; | 538 | ti,hwmods = "timer2"; |
| 536 | }; | 539 | }; |
| 537 | 540 | ||
| 538 | timer3: timer@48034000 { | 541 | timer3: timer@48034000 { |
| 539 | compatible = "ti,omap4430-timer"; | 542 | compatible = "ti,omap4430-timer"; |
| 540 | reg = <0x48034000 0x80>; | 543 | reg = <0x48034000 0x80>; |
| 541 | interrupts = <0 39 0x4>; | 544 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| 542 | ti,hwmods = "timer3"; | 545 | ti,hwmods = "timer3"; |
| 543 | }; | 546 | }; |
| 544 | 547 | ||
| 545 | timer4: timer@48036000 { | 548 | timer4: timer@48036000 { |
| 546 | compatible = "ti,omap4430-timer"; | 549 | compatible = "ti,omap4430-timer"; |
| 547 | reg = <0x48036000 0x80>; | 550 | reg = <0x48036000 0x80>; |
| 548 | interrupts = <0 40 0x4>; | 551 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| 549 | ti,hwmods = "timer4"; | 552 | ti,hwmods = "timer4"; |
| 550 | }; | 553 | }; |
| 551 | 554 | ||
| @@ -553,7 +556,7 @@ | |||
| 553 | compatible = "ti,omap4430-timer"; | 556 | compatible = "ti,omap4430-timer"; |
| 554 | reg = <0x40138000 0x80>, | 557 | reg = <0x40138000 0x80>, |
| 555 | <0x49038000 0x80>; | 558 | <0x49038000 0x80>; |
| 556 | interrupts = <0 41 0x4>; | 559 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| 557 | ti,hwmods = "timer5"; | 560 | ti,hwmods = "timer5"; |
| 558 | ti,timer-dsp; | 561 | ti,timer-dsp; |
| 559 | }; | 562 | }; |
| @@ -562,7 +565,7 @@ | |||
| 562 | compatible = "ti,omap4430-timer"; | 565 | compatible = "ti,omap4430-timer"; |
| 563 | reg = <0x4013a000 0x80>, | 566 | reg = <0x4013a000 0x80>, |
| 564 | <0x4903a000 0x80>; | 567 | <0x4903a000 0x80>; |
| 565 | interrupts = <0 42 0x4>; | 568 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| 566 | ti,hwmods = "timer6"; | 569 | ti,hwmods = "timer6"; |
| 567 | ti,timer-dsp; | 570 | ti,timer-dsp; |
| 568 | }; | 571 | }; |
| @@ -571,7 +574,7 @@ | |||
| 571 | compatible = "ti,omap4430-timer"; | 574 | compatible = "ti,omap4430-timer"; |
| 572 | reg = <0x4013c000 0x80>, | 575 | reg = <0x4013c000 0x80>, |
| 573 | <0x4903c000 0x80>; | 576 | <0x4903c000 0x80>; |
| 574 | interrupts = <0 43 0x4>; | 577 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| 575 | ti,hwmods = "timer7"; | 578 | ti,hwmods = "timer7"; |
| 576 | ti,timer-dsp; | 579 | ti,timer-dsp; |
| 577 | }; | 580 | }; |
| @@ -580,7 +583,7 @@ | |||
| 580 | compatible = "ti,omap4430-timer"; | 583 | compatible = "ti,omap4430-timer"; |
| 581 | reg = <0x4013e000 0x80>, | 584 | reg = <0x4013e000 0x80>, |
| 582 | <0x4903e000 0x80>; | 585 | <0x4903e000 0x80>; |
| 583 | interrupts = <0 44 0x4>; | 586 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| 584 | ti,hwmods = "timer8"; | 587 | ti,hwmods = "timer8"; |
| 585 | ti,timer-pwm; | 588 | ti,timer-pwm; |
| 586 | ti,timer-dsp; | 589 | ti,timer-dsp; |
| @@ -589,7 +592,7 @@ | |||
| 589 | timer9: timer@4803e000 { | 592 | timer9: timer@4803e000 { |
| 590 | compatible = "ti,omap4430-timer"; | 593 | compatible = "ti,omap4430-timer"; |
| 591 | reg = <0x4803e000 0x80>; | 594 | reg = <0x4803e000 0x80>; |
| 592 | interrupts = <0 45 0x4>; | 595 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 593 | ti,hwmods = "timer9"; | 596 | ti,hwmods = "timer9"; |
| 594 | ti,timer-pwm; | 597 | ti,timer-pwm; |
| 595 | }; | 598 | }; |
| @@ -597,7 +600,7 @@ | |||
| 597 | timer10: timer@48086000 { | 600 | timer10: timer@48086000 { |
| 598 | compatible = "ti,omap3430-timer"; | 601 | compatible = "ti,omap3430-timer"; |
| 599 | reg = <0x48086000 0x80>; | 602 | reg = <0x48086000 0x80>; |
| 600 | interrupts = <0 46 0x4>; | 603 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 601 | ti,hwmods = "timer10"; | 604 | ti,hwmods = "timer10"; |
| 602 | ti,timer-pwm; | 605 | ti,timer-pwm; |
| 603 | }; | 606 | }; |
| @@ -605,7 +608,7 @@ | |||
| 605 | timer11: timer@48088000 { | 608 | timer11: timer@48088000 { |
| 606 | compatible = "ti,omap4430-timer"; | 609 | compatible = "ti,omap4430-timer"; |
| 607 | reg = <0x48088000 0x80>; | 610 | reg = <0x48088000 0x80>; |
| 608 | interrupts = <0 47 0x4>; | 611 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| 609 | ti,hwmods = "timer11"; | 612 | ti,hwmods = "timer11"; |
| 610 | ti,timer-pwm; | 613 | ti,timer-pwm; |
| 611 | }; | 614 | }; |
| @@ -613,7 +616,7 @@ | |||
| 613 | usbhstll: usbhstll@4a062000 { | 616 | usbhstll: usbhstll@4a062000 { |
| 614 | compatible = "ti,usbhs-tll"; | 617 | compatible = "ti,usbhs-tll"; |
| 615 | reg = <0x4a062000 0x1000>; | 618 | reg = <0x4a062000 0x1000>; |
| 616 | interrupts = <0 78 0x4>; | 619 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
| 617 | ti,hwmods = "usb_tll_hs"; | 620 | ti,hwmods = "usb_tll_hs"; |
| 618 | }; | 621 | }; |
| 619 | 622 | ||
| @@ -629,14 +632,14 @@ | |||
| 629 | compatible = "ti,ohci-omap3", "usb-ohci"; | 632 | compatible = "ti,ohci-omap3", "usb-ohci"; |
| 630 | reg = <0x4a064800 0x400>; | 633 | reg = <0x4a064800 0x400>; |
| 631 | interrupt-parent = <&gic>; | 634 | interrupt-parent = <&gic>; |
| 632 | interrupts = <0 76 0x4>; | 635 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 633 | }; | 636 | }; |
| 634 | 637 | ||
| 635 | usbhsehci: ehci@4a064c00 { | 638 | usbhsehci: ehci@4a064c00 { |
| 636 | compatible = "ti,ehci-omap", "usb-ehci"; | 639 | compatible = "ti,ehci-omap", "usb-ehci"; |
| 637 | reg = <0x4a064c00 0x400>; | 640 | reg = <0x4a064c00 0x400>; |
| 638 | interrupt-parent = <&gic>; | 641 | interrupt-parent = <&gic>; |
| 639 | interrupts = <0 77 0x4>; | 642 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 640 | }; | 643 | }; |
| 641 | }; | 644 | }; |
| 642 | 645 | ||
| @@ -651,7 +654,7 @@ | |||
| 651 | usb_otg_hs: usb_otg_hs@4a0ab000 { | 654 | usb_otg_hs: usb_otg_hs@4a0ab000 { |
| 652 | compatible = "ti,omap4-musb"; | 655 | compatible = "ti,omap4-musb"; |
| 653 | reg = <0x4a0ab000 0x7ff>; | 656 | reg = <0x4a0ab000 0x7ff>; |
| 654 | interrupts = <0 92 0x4>, <0 93 0x4>; | 657 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 655 | interrupt-names = "mc", "dma"; | 658 | interrupt-names = "mc", "dma"; |
| 656 | ti,hwmods = "usb_otg_hs"; | 659 | ti,hwmods = "usb_otg_hs"; |
| 657 | usb-phy = <&usb2_phy>; | 660 | usb-phy = <&usb2_phy>; |
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi index cccf39af4925..bcf455efe18d 100644 --- a/arch/arm/boot/dts/omap443x.dtsi +++ b/arch/arm/boot/dts/omap443x.dtsi | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | /include/ "omap4.dtsi" | 11 | #include "omap4.dtsi" |
| 12 | 12 | ||
| 13 | / { | 13 | / { |
| 14 | cpus { | 14 | cpus { |
| @@ -24,4 +24,10 @@ | |||
| 24 | clock-latency = <300000>; /* From legacy driver */ | 24 | clock-latency = <300000>; /* From legacy driver */ |
| 25 | }; | 25 | }; |
| 26 | }; | 26 | }; |
| 27 | |||
| 28 | bandgap { | ||
| 29 | reg = <0x4a002260 0x4 | ||
| 30 | 0x4a00232C 0x4>; | ||
| 31 | compatible = "ti,omap4430-bandgap"; | ||
| 32 | }; | ||
| 27 | }; | 33 | }; |
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index 2cf227c86099..c2f0f39b5a24 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | * version 2. This program is licensed "as is" without any warranty of any | 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. | 8 | * kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | /include/ "omap4.dtsi" | 10 | #include "omap4.dtsi" |
| 11 | 11 | ||
| 12 | / { | 12 | / { |
| 13 | cpus { | 13 | cpus { |
| @@ -25,8 +25,17 @@ | |||
| 25 | 25 | ||
| 26 | pmu { | 26 | pmu { |
| 27 | compatible = "arm,cortex-a9-pmu"; | 27 | compatible = "arm,cortex-a9-pmu"; |
| 28 | interrupts = <0 54 0x4>, | 28 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| 29 | <0 55 0x4>; | 29 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| 30 | ti,hwmods = "debugss"; | 30 | ti,hwmods = "debugss"; |
| 31 | }; | 31 | }; |
| 32 | |||
| 33 | bandgap { | ||
| 34 | reg = <0x4a002260 0x4 | ||
| 35 | 0x4a00232C 0x4 | ||
| 36 | 0x4a002378 0x18>; | ||
| 37 | compatible = "ti,omap4460-bandgap"; | ||
| 38 | interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */ | ||
| 39 | gpios = <&gpio3 22 0>; /* tshut */ | ||
| 40 | }; | ||
| 32 | }; | 41 | }; |
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts deleted file mode 100644 index 982acd19477d..000000000000 --- a/arch/arm/boot/dts/omap5-evm.dts +++ /dev/null | |||
| @@ -1,261 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | /dts-v1/; | ||
| 9 | |||
| 10 | /include/ "omap5.dtsi" | ||
| 11 | /include/ "samsung_k3pe0e000b.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "TI OMAP5 EVM board"; | ||
| 15 | compatible = "ti,omap5-evm", "ti,omap5"; | ||
| 16 | |||
| 17 | memory { | ||
| 18 | device_type = "memory"; | ||
| 19 | reg = <0x80000000 0x7F000000>; /* 2032 MB */ | ||
| 20 | }; | ||
| 21 | |||
| 22 | vmmcsd_fixed: fixedregulator-mmcsd { | ||
| 23 | compatible = "regulator-fixed"; | ||
| 24 | regulator-name = "vmmcsd_fixed"; | ||
| 25 | regulator-min-microvolt = <3000000>; | ||
| 26 | regulator-max-microvolt = <3000000>; | ||
| 27 | }; | ||
| 28 | |||
| 29 | }; | ||
| 30 | |||
| 31 | &omap5_pmx_core { | ||
| 32 | pinctrl-names = "default"; | ||
| 33 | pinctrl-0 = < | ||
| 34 | &twl6040_pins | ||
| 35 | &mcpdm_pins | ||
| 36 | &dmic_pins | ||
| 37 | &mcbsp1_pins | ||
| 38 | &mcbsp2_pins | ||
| 39 | >; | ||
| 40 | |||
| 41 | twl6040_pins: pinmux_twl6040_pins { | ||
| 42 | pinctrl-single,pins = < | ||
| 43 | 0x18a 0x6 /* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */ | ||
| 44 | >; | ||
| 45 | }; | ||
| 46 | |||
| 47 | mcpdm_pins: pinmux_mcpdm_pins { | ||
| 48 | pinctrl-single,pins = < | ||
| 49 | 0x142 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */ | ||
| 50 | 0x15c 0x108 /* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */ | ||
| 51 | 0x15e 0x108 /* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */ | ||
| 52 | 0x160 0x118 /* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */ | ||
| 53 | 0x162 0x108 /* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */ | ||
| 54 | >; | ||
| 55 | }; | ||
| 56 | |||
| 57 | dmic_pins: pinmux_dmic_pins { | ||
| 58 | pinctrl-single,pins = < | ||
| 59 | 0x144 0x100 /* abedmic_din1.abedmic_din1 INPUT | MODE0 */ | ||
| 60 | 0x146 0x100 /* abedmic_din2.abedmic_din2 INPUT | MODE0 */ | ||
| 61 | 0x148 0x100 /* abedmic_din3.abedmic_din3 INPUT | MODE0 */ | ||
| 62 | 0x14a 0 /* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */ | ||
| 63 | >; | ||
| 64 | }; | ||
| 65 | |||
| 66 | mcbsp1_pins: pinmux_mcbsp1_pins { | ||
| 67 | pinctrl-single,pins = < | ||
| 68 | 0x14c 0x101 /* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */ | ||
| 69 | 0x14e 0x9 /* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */ | ||
| 70 | 0x150 0x101 /* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */ | ||
| 71 | 0x152 0x109 /* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */ | ||
| 72 | >; | ||
| 73 | }; | ||
| 74 | |||
| 75 | mcbsp2_pins: pinmux_mcbsp2_pins { | ||
| 76 | pinctrl-single,pins = < | ||
| 77 | 0x154 0x108 /* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */ | ||
| 78 | 0x156 0x8 /* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */ | ||
| 79 | 0x158 0x100 /* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */ | ||
| 80 | 0x15a 0x100 /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */ | ||
| 81 | >; | ||
| 82 | }; | ||
| 83 | |||
| 84 | i2c1_pins: pinmux_i2c1_pins { | ||
| 85 | pinctrl-single,pins = < | ||
| 86 | 0x1b2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */ | ||
| 87 | 0x1b4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */ | ||
| 88 | >; | ||
| 89 | }; | ||
| 90 | |||
| 91 | i2c2_pins: pinmux_i2c2_pins { | ||
| 92 | pinctrl-single,pins = < | ||
| 93 | 0x178 0x100 /* i2c2_scl INPUTENABLE | MODE0 */ | ||
| 94 | 0x17a 0x100 /* i2c2_sda INPUTENABLE | MODE0 */ | ||
| 95 | >; | ||
| 96 | }; | ||
| 97 | |||
| 98 | i2c3_pins: pinmux_i2c3_pins { | ||
| 99 | pinctrl-single,pins = < | ||
| 100 | 0x13a 0x100 /* i2c3_scl INPUTENABLE | MODE0 */ | ||
| 101 | 0x13c 0x100 /* i2c3_sda INPUTENABLE | MODE0 */ | ||
| 102 | >; | ||
| 103 | }; | ||
| 104 | |||
| 105 | i2c4_pins: pinmux_i2c4_pins { | ||
| 106 | pinctrl-single,pins = < | ||
| 107 | 0xb8 0x100 /* i2c4_scl INPUTENABLE | MODE0 */ | ||
| 108 | 0xba 0x100 /* i2c4_sda INPUTENABLE | MODE0 */ | ||
| 109 | >; | ||
| 110 | }; | ||
| 111 | |||
| 112 | i2c5_pins: pinmux_i2c5_pins { | ||
| 113 | pinctrl-single,pins = < | ||
| 114 | 0x184 0x100 /* i2c5_scl INPUTENABLE | MODE0 */ | ||
| 115 | 0x186 0x100 /* i2c5_sda INPUTENABLE | MODE0 */ | ||
| 116 | >; | ||
| 117 | }; | ||
| 118 | |||
| 119 | mcspi2_pins: pinmux_mcspi2_pins { | ||
| 120 | pinctrl-single,pins = < | ||
| 121 | 0xbc 0x100 /* MCSPI2_CLK INPUTENABLE | MODE0 */ | ||
| 122 | 0xbe 0x100 /* MCSPI2_SIMO INPUTENABLE | MODE0 */ | ||
| 123 | 0xc0 0x118 /* MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/ | ||
| 124 | 0xc2 0x0 /* MCSPI2_CS MODE0*/ | ||
| 125 | >; | ||
| 126 | }; | ||
| 127 | |||
| 128 | mcspi3_pins: pinmux_mcspi3_pins { | ||
| 129 | pinctrl-single,pins = < | ||
| 130 | 0x78 0x101 /* MCSPI2_SOMI INPUTENABLE | MODE1 */ | ||
| 131 | 0x7a 0x101 /* MCSPI2_CS INPUTENABLE | MODE1 */ | ||
| 132 | 0x7c 0x101 /* MCSPI2_SIMO INPUTENABLE | MODE1 */ | ||
| 133 | 0x7e 0x101 /* MCSPI2_CLK INPUTENABLE | MODE1 */ | ||
| 134 | >; | ||
| 135 | }; | ||
| 136 | |||
| 137 | mcspi4_pins: pinmux_mcspi4_pins { | ||
| 138 | pinctrl-single,pins = < | ||
| 139 | 0x164 0x101 /* MCSPI2_CLK INPUTENABLE | MODE1 */ | ||
| 140 | 0x168 0x101 /* MCSPI2_SIMO INPUTENABLE | MODE1 */ | ||
| 141 | 0x16a 0x101 /* MCSPI2_SOMI INPUTENABLE | MODE1 */ | ||
| 142 | 0x16c 0x101 /* MCSPI2_CS INPUTENABLE | MODE1 */ | ||
| 143 | >; | ||
| 144 | }; | ||
| 145 | }; | ||
| 146 | |||
| 147 | &mmc1 { | ||
| 148 | vmmc-supply = <&vmmcsd_fixed>; | ||
| 149 | bus-width = <4>; | ||
| 150 | }; | ||
| 151 | |||
| 152 | &mmc2 { | ||
| 153 | vmmc-supply = <&vmmcsd_fixed>; | ||
| 154 | bus-width = <8>; | ||
| 155 | ti,non-removable; | ||
| 156 | }; | ||
| 157 | |||
| 158 | &mmc3 { | ||
| 159 | bus-width = <4>; | ||
| 160 | ti,non-removable; | ||
| 161 | }; | ||
| 162 | |||
| 163 | &mmc4 { | ||
| 164 | status = "disabled"; | ||
| 165 | }; | ||
| 166 | |||
| 167 | &mmc5 { | ||
| 168 | status = "disabled"; | ||
| 169 | }; | ||
| 170 | |||
| 171 | &i2c1 { | ||
| 172 | pinctrl-names = "default"; | ||
| 173 | pinctrl-0 = <&i2c1_pins>; | ||
| 174 | |||
| 175 | clock-frequency = <400000>; | ||
| 176 | }; | ||
| 177 | |||
| 178 | &i2c2 { | ||
| 179 | pinctrl-names = "default"; | ||
| 180 | pinctrl-0 = <&i2c2_pins>; | ||
| 181 | |||
| 182 | clock-frequency = <400000>; | ||
| 183 | |||
| 184 | /* Pressure Sensor */ | ||
| 185 | bmp085@77 { | ||
| 186 | compatible = "bosch,bmp085"; | ||
| 187 | reg = <0x77>; | ||
| 188 | }; | ||
| 189 | }; | ||
| 190 | |||
| 191 | &i2c3 { | ||
| 192 | pinctrl-names = "default"; | ||
| 193 | pinctrl-0 = <&i2c3_pins>; | ||
| 194 | |||
| 195 | clock-frequency = <400000>; | ||
| 196 | }; | ||
| 197 | |||
| 198 | &i2c4 { | ||
| 199 | pinctrl-names = "default"; | ||
| 200 | pinctrl-0 = <&i2c4_pins>; | ||
| 201 | |||
| 202 | clock-frequency = <400000>; | ||
| 203 | |||
| 204 | /* Temperature Sensor */ | ||
| 205 | tmp102@48{ | ||
| 206 | compatible = "ti,tmp102"; | ||
| 207 | reg = <0x48>; | ||
| 208 | }; | ||
| 209 | }; | ||
| 210 | |||
| 211 | &i2c5 { | ||
| 212 | pinctrl-names = "default"; | ||
| 213 | pinctrl-0 = <&i2c5_pins>; | ||
| 214 | |||
| 215 | clock-frequency = <400000>; | ||
| 216 | }; | ||
| 217 | |||
| 218 | &keypad { | ||
| 219 | keypad,num-rows = <8>; | ||
| 220 | keypad,num-columns = <8>; | ||
| 221 | linux,keymap = <0x02020073 /* VOLUP */ | ||
| 222 | 0x02030072 /* VOLDOWM */ | ||
| 223 | 0x020400e7 /* SEND */ | ||
| 224 | 0x02050066 /* HOME */ | ||
| 225 | 0x0206006b /* END */ | ||
| 226 | 0x020700d9>; /* SEARCH */ | ||
| 227 | linux,input-no-autorepeat; | ||
| 228 | }; | ||
| 229 | |||
| 230 | &mcbsp3 { | ||
| 231 | status = "disabled"; | ||
| 232 | }; | ||
| 233 | |||
| 234 | &emif1 { | ||
| 235 | cs1-used; | ||
| 236 | device-handle = <&samsung_K3PE0E000B>; | ||
| 237 | }; | ||
| 238 | |||
| 239 | &emif2 { | ||
| 240 | cs1-used; | ||
| 241 | device-handle = <&samsung_K3PE0E000B>; | ||
| 242 | }; | ||
| 243 | |||
| 244 | &mcspi1 { | ||
| 245 | |||
| 246 | }; | ||
| 247 | |||
| 248 | &mcspi2 { | ||
| 249 | pinctrl-names = "default"; | ||
| 250 | pinctrl-0 = <&mcspi2_pins>; | ||
| 251 | }; | ||
| 252 | |||
| 253 | &mcspi3 { | ||
| 254 | pinctrl-names = "default"; | ||
| 255 | pinctrl-0 = <&mcspi3_pins>; | ||
| 256 | }; | ||
| 257 | |||
| 258 | &mcspi4 { | ||
| 259 | pinctrl-names = "default"; | ||
| 260 | pinctrl-0 = <&mcspi4_pins>; | ||
| 261 | }; | ||
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts new file mode 100644 index 000000000000..08b72678abff --- /dev/null +++ b/arch/arm/boot/dts/omap5-uevm.dts | |||
| @@ -0,0 +1,485 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | /dts-v1/; | ||
| 9 | |||
| 10 | #include "omap5.dtsi" | ||
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "TI OMAP5 uEVM board"; | ||
| 16 | compatible = "ti,omap5-uevm", "ti,omap5"; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | device_type = "memory"; | ||
| 20 | reg = <0x80000000 0x7F000000>; /* 2032 MB */ | ||
| 21 | }; | ||
| 22 | |||
| 23 | vmmcsd_fixed: fixedregulator-mmcsd { | ||
| 24 | compatible = "regulator-fixed"; | ||
| 25 | regulator-name = "vmmcsd_fixed"; | ||
| 26 | regulator-min-microvolt = <3000000>; | ||
| 27 | regulator-max-microvolt = <3000000>; | ||
| 28 | }; | ||
| 29 | |||
| 30 | /* HS USB Port 2 RESET */ | ||
| 31 | hsusb2_reset: hsusb2_reset_reg { | ||
| 32 | compatible = "regulator-fixed"; | ||
| 33 | regulator-name = "hsusb2_reset"; | ||
| 34 | regulator-min-microvolt = <3300000>; | ||
| 35 | regulator-max-microvolt = <3300000>; | ||
| 36 | gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */ | ||
| 37 | startup-delay-us = <70000>; | ||
| 38 | enable-active-high; | ||
| 39 | }; | ||
| 40 | |||
| 41 | /* HS USB Host PHY on PORT 2 */ | ||
| 42 | hsusb2_phy: hsusb2_phy { | ||
| 43 | compatible = "usb-nop-xceiv"; | ||
| 44 | reset-supply = <&hsusb2_reset>; | ||
| 45 | /** | ||
| 46 | * FIXME | ||
| 47 | * Put the right clock phandle here when available | ||
| 48 | * clocks = <&auxclk1>; | ||
| 49 | * clock-names = "main_clk"; | ||
| 50 | */ | ||
| 51 | clock-frequency = <19200000>; | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* HS USB Port 3 RESET */ | ||
| 55 | hsusb3_reset: hsusb3_reset_reg { | ||
| 56 | compatible = "regulator-fixed"; | ||
| 57 | regulator-name = "hsusb3_reset"; | ||
| 58 | regulator-min-microvolt = <3300000>; | ||
| 59 | regulator-max-microvolt = <3300000>; | ||
| 60 | gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */ | ||
| 61 | startup-delay-us = <70000>; | ||
| 62 | enable-active-high; | ||
| 63 | }; | ||
| 64 | |||
| 65 | /* HS USB Host PHY on PORT 3 */ | ||
| 66 | hsusb3_phy: hsusb3_phy { | ||
| 67 | compatible = "usb-nop-xceiv"; | ||
| 68 | reset-supply = <&hsusb3_reset>; | ||
| 69 | }; | ||
| 70 | |||
| 71 | leds { | ||
| 72 | compatible = "gpio-leds"; | ||
| 73 | led@1 { | ||
| 74 | label = "omap5:blue:usr1"; | ||
| 75 | gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ | ||
| 76 | linux,default-trigger = "heartbeat"; | ||
| 77 | default-state = "off"; | ||
| 78 | }; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | |||
| 82 | &omap5_pmx_core { | ||
| 83 | pinctrl-names = "default"; | ||
| 84 | pinctrl-0 = < | ||
| 85 | &twl6040_pins | ||
| 86 | &mcpdm_pins | ||
| 87 | &dmic_pins | ||
| 88 | &mcbsp1_pins | ||
| 89 | &mcbsp2_pins | ||
| 90 | &usbhost_pins | ||
| 91 | &led_gpio_pins | ||
| 92 | >; | ||
| 93 | |||
| 94 | twl6040_pins: pinmux_twl6040_pins { | ||
| 95 | pinctrl-single,pins = < | ||
| 96 | 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */ | ||
| 97 | >; | ||
| 98 | }; | ||
| 99 | |||
| 100 | mcpdm_pins: pinmux_mcpdm_pins { | ||
| 101 | pinctrl-single,pins = < | ||
| 102 | 0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ | ||
| 103 | 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ | ||
| 104 | 0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ | ||
| 105 | 0x160 (PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ | ||
| 106 | 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ | ||
| 107 | >; | ||
| 108 | }; | ||
| 109 | |||
| 110 | dmic_pins: pinmux_dmic_pins { | ||
| 111 | pinctrl-single,pins = < | ||
| 112 | 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */ | ||
| 113 | 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */ | ||
| 114 | 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */ | ||
| 115 | 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */ | ||
| 116 | >; | ||
| 117 | }; | ||
| 118 | |||
| 119 | mcbsp1_pins: pinmux_mcbsp1_pins { | ||
| 120 | pinctrl-single,pins = < | ||
| 121 | 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ | ||
| 122 | 0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ | ||
| 123 | 0x150 (PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ | ||
| 124 | 0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ | ||
| 125 | >; | ||
| 126 | }; | ||
| 127 | |||
| 128 | mcbsp2_pins: pinmux_mcbsp2_pins { | ||
| 129 | pinctrl-single,pins = < | ||
| 130 | 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ | ||
| 131 | 0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ | ||
| 132 | 0x158 (PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ | ||
| 133 | 0x15a (PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ | ||
| 134 | >; | ||
| 135 | }; | ||
| 136 | |||
| 137 | i2c1_pins: pinmux_i2c1_pins { | ||
| 138 | pinctrl-single,pins = < | ||
| 139 | 0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ | ||
| 140 | 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ | ||
| 141 | >; | ||
| 142 | }; | ||
| 143 | |||
| 144 | i2c5_pins: pinmux_i2c5_pins { | ||
| 145 | pinctrl-single,pins = < | ||
| 146 | 0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */ | ||
| 147 | 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */ | ||
| 148 | >; | ||
| 149 | }; | ||
| 150 | |||
| 151 | mcspi2_pins: pinmux_mcspi2_pins { | ||
| 152 | pinctrl-single,pins = < | ||
| 153 | 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ | ||
| 154 | 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ | ||
| 155 | 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ | ||
| 156 | 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */ | ||
| 157 | >; | ||
| 158 | }; | ||
| 159 | |||
| 160 | mcspi3_pins: pinmux_mcspi3_pins { | ||
| 161 | pinctrl-single,pins = < | ||
| 162 | 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ | ||
| 163 | 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ | ||
| 164 | 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ | ||
| 165 | 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ | ||
| 166 | >; | ||
| 167 | }; | ||
| 168 | |||
| 169 | mcspi4_pins: pinmux_mcspi4_pins { | ||
| 170 | pinctrl-single,pins = < | ||
| 171 | 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */ | ||
| 172 | 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */ | ||
| 173 | 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */ | ||
| 174 | 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */ | ||
| 175 | >; | ||
| 176 | }; | ||
| 177 | |||
| 178 | usbhost_pins: pinmux_usbhost_pins { | ||
| 179 | pinctrl-single,pins = < | ||
| 180 | 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ | ||
| 181 | 0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ | ||
| 182 | |||
| 183 | 0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ | ||
| 184 | 0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ | ||
| 185 | |||
| 186 | 0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ | ||
| 187 | 0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ | ||
| 188 | >; | ||
| 189 | }; | ||
| 190 | |||
| 191 | led_gpio_pins: pinmux_led_gpio_pins { | ||
| 192 | pinctrl-single,pins = < | ||
| 193 | 0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ | ||
| 194 | >; | ||
| 195 | }; | ||
| 196 | |||
| 197 | uart1_pins: pinmux_uart1_pins { | ||
| 198 | pinctrl-single,pins = < | ||
| 199 | 0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ | ||
| 200 | 0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ | ||
| 201 | 0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ | ||
| 202 | 0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ | ||
| 203 | >; | ||
| 204 | }; | ||
| 205 | |||
| 206 | uart3_pins: pinmux_uart3_pins { | ||
| 207 | pinctrl-single,pins = < | ||
| 208 | 0x19a (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ | ||
| 209 | 0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ | ||
| 210 | >; | ||
| 211 | }; | ||
| 212 | |||
| 213 | uart5_pins: pinmux_uart5_pins { | ||
| 214 | pinctrl-single,pins = < | ||
| 215 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ | ||
| 216 | 0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ | ||
| 217 | 0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ | ||
| 218 | 0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ | ||
| 219 | >; | ||
| 220 | }; | ||
| 221 | |||
| 222 | }; | ||
| 223 | |||
| 224 | &omap5_pmx_wkup { | ||
| 225 | pinctrl-names = "default"; | ||
| 226 | pinctrl-0 = < | ||
| 227 | &usbhost_wkup_pins | ||
| 228 | >; | ||
| 229 | |||
| 230 | usbhost_wkup_pins: pinmux_usbhost_wkup_pins { | ||
| 231 | pinctrl-single,pins = < | ||
| 232 | 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ | ||
| 233 | >; | ||
| 234 | }; | ||
| 235 | }; | ||
| 236 | |||
| 237 | &mmc1 { | ||
| 238 | vmmc-supply = <&vmmcsd_fixed>; | ||
| 239 | bus-width = <4>; | ||
| 240 | }; | ||
| 241 | |||
| 242 | &mmc2 { | ||
| 243 | vmmc-supply = <&vmmcsd_fixed>; | ||
| 244 | bus-width = <8>; | ||
| 245 | ti,non-removable; | ||
| 246 | }; | ||
| 247 | |||
| 248 | &mmc3 { | ||
| 249 | bus-width = <4>; | ||
| 250 | ti,non-removable; | ||
| 251 | }; | ||
| 252 | |||
| 253 | &mmc4 { | ||
| 254 | status = "disabled"; | ||
| 255 | }; | ||
| 256 | |||
| 257 | &mmc5 { | ||
| 258 | status = "disabled"; | ||
| 259 | }; | ||
| 260 | |||
| 261 | &i2c1 { | ||
| 262 | pinctrl-names = "default"; | ||
| 263 | pinctrl-0 = <&i2c1_pins>; | ||
| 264 | |||
| 265 | clock-frequency = <400000>; | ||
| 266 | |||
| 267 | palmas: palmas@48 { | ||
| 268 | compatible = "ti,palmas"; | ||
| 269 | interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ | ||
| 270 | interrupt-parent = <&gic>; | ||
| 271 | reg = <0x48>; | ||
| 272 | interrupt-controller; | ||
| 273 | #interrupt-cells = <2>; | ||
| 274 | |||
| 275 | palmas_pmic { | ||
| 276 | compatible = "ti,palmas-pmic"; | ||
| 277 | interrupt-parent = <&palmas>; | ||
| 278 | interrupts = <14 IRQ_TYPE_NONE>; | ||
| 279 | interrupt-name = "short-irq"; | ||
| 280 | |||
| 281 | ti,ldo6-vibrator; | ||
| 282 | |||
| 283 | regulators { | ||
| 284 | smps123_reg: smps123 { | ||
| 285 | regulator-name = "smps123"; | ||
| 286 | regulator-min-microvolt = < 600000>; | ||
| 287 | regulator-max-microvolt = <1500000>; | ||
| 288 | regulator-always-on; | ||
| 289 | regulator-boot-on; | ||
| 290 | }; | ||
| 291 | |||
| 292 | smps45_reg: smps45 { | ||
| 293 | regulator-name = "smps45"; | ||
| 294 | regulator-min-microvolt = < 600000>; | ||
| 295 | regulator-max-microvolt = <1310000>; | ||
| 296 | regulator-always-on; | ||
| 297 | regulator-boot-on; | ||
| 298 | }; | ||
| 299 | |||
| 300 | smps6_reg: smps6 { | ||
| 301 | regulator-name = "smps6"; | ||
| 302 | regulator-min-microvolt = <1200000>; | ||
| 303 | regulator-max-microvolt = <1200000>; | ||
| 304 | regulator-always-on; | ||
| 305 | regulator-boot-on; | ||
| 306 | }; | ||
| 307 | |||
| 308 | smps7_reg: smps7 { | ||
| 309 | regulator-name = "smps7"; | ||
| 310 | regulator-min-microvolt = <1800000>; | ||
| 311 | regulator-max-microvolt = <1800000>; | ||
| 312 | regulator-always-on; | ||
| 313 | regulator-boot-on; | ||
| 314 | }; | ||
| 315 | |||
| 316 | smps8_reg: smps8 { | ||
| 317 | regulator-name = "smps8"; | ||
| 318 | regulator-min-microvolt = < 600000>; | ||
| 319 | regulator-max-microvolt = <1310000>; | ||
| 320 | regulator-always-on; | ||
| 321 | regulator-boot-on; | ||
| 322 | }; | ||
| 323 | |||
| 324 | smps9_reg: smps9 { | ||
| 325 | regulator-name = "smps9"; | ||
| 326 | regulator-min-microvolt = <2100000>; | ||
| 327 | regulator-max-microvolt = <2100000>; | ||
| 328 | regulator-always-on; | ||
| 329 | regulator-boot-on; | ||
| 330 | ti,smps-range = <0x80>; | ||
| 331 | }; | ||
| 332 | |||
| 333 | smps10_reg: smps10 { | ||
| 334 | regulator-name = "smps10"; | ||
| 335 | regulator-min-microvolt = <5000000>; | ||
| 336 | regulator-max-microvolt = <5000000>; | ||
| 337 | regulator-always-on; | ||
| 338 | regulator-boot-on; | ||
| 339 | }; | ||
| 340 | |||
| 341 | ldo1_reg: ldo1 { | ||
| 342 | regulator-name = "ldo1"; | ||
| 343 | regulator-min-microvolt = <2800000>; | ||
| 344 | regulator-max-microvolt = <2800000>; | ||
| 345 | regulator-always-on; | ||
| 346 | regulator-boot-on; | ||
| 347 | }; | ||
| 348 | |||
| 349 | ldo2_reg: ldo2 { | ||
| 350 | regulator-name = "ldo2"; | ||
| 351 | regulator-min-microvolt = <2900000>; | ||
| 352 | regulator-max-microvolt = <2900000>; | ||
| 353 | regulator-always-on; | ||
| 354 | regulator-boot-on; | ||
| 355 | }; | ||
| 356 | |||
| 357 | ldo3_reg: ldo3 { | ||
| 358 | regulator-name = "ldo3"; | ||
| 359 | regulator-min-microvolt = <3000000>; | ||
| 360 | regulator-max-microvolt = <3000000>; | ||
| 361 | regulator-always-on; | ||
| 362 | regulator-boot-on; | ||
| 363 | }; | ||
| 364 | |||
| 365 | ldo4_reg: ldo4 { | ||
| 366 | regulator-name = "ldo4"; | ||
| 367 | regulator-min-microvolt = <2200000>; | ||
| 368 | regulator-max-microvolt = <2200000>; | ||
| 369 | regulator-always-on; | ||
| 370 | regulator-boot-on; | ||
| 371 | }; | ||
| 372 | |||
| 373 | ldo5_reg: ldo5 { | ||
| 374 | regulator-name = "ldo5"; | ||
| 375 | regulator-min-microvolt = <1800000>; | ||
| 376 | regulator-max-microvolt = <1800000>; | ||
| 377 | regulator-always-on; | ||
| 378 | regulator-boot-on; | ||
| 379 | }; | ||
| 380 | |||
| 381 | ldo6_reg: ldo6 { | ||
| 382 | regulator-name = "ldo6"; | ||
| 383 | regulator-min-microvolt = <1500000>; | ||
| 384 | regulator-max-microvolt = <1500000>; | ||
| 385 | regulator-always-on; | ||
| 386 | regulator-boot-on; | ||
| 387 | }; | ||
| 388 | |||
| 389 | ldo7_reg: ldo7 { | ||
| 390 | regulator-name = "ldo7"; | ||
| 391 | regulator-min-microvolt = <1500000>; | ||
| 392 | regulator-max-microvolt = <1500000>; | ||
| 393 | regulator-always-on; | ||
| 394 | regulator-boot-on; | ||
| 395 | }; | ||
| 396 | |||
| 397 | ldo8_reg: ldo8 { | ||
| 398 | regulator-name = "ldo8"; | ||
| 399 | regulator-min-microvolt = <1500000>; | ||
| 400 | regulator-max-microvolt = <1500000>; | ||
| 401 | regulator-always-on; | ||
| 402 | regulator-boot-on; | ||
| 403 | }; | ||
| 404 | |||
| 405 | ldo9_reg: ldo9 { | ||
| 406 | regulator-name = "ldo9"; | ||
| 407 | regulator-min-microvolt = <1800000>; | ||
| 408 | regulator-max-microvolt = <3300000>; | ||
| 409 | regulator-always-on; | ||
| 410 | regulator-boot-on; | ||
| 411 | }; | ||
| 412 | |||
| 413 | ldoln_reg: ldoln { | ||
| 414 | regulator-name = "ldoln"; | ||
| 415 | regulator-min-microvolt = <1800000>; | ||
| 416 | regulator-max-microvolt = <1800000>; | ||
| 417 | regulator-always-on; | ||
| 418 | regulator-boot-on; | ||
| 419 | }; | ||
| 420 | |||
| 421 | ldousb_reg: ldousb { | ||
| 422 | regulator-name = "ldousb"; | ||
| 423 | regulator-min-microvolt = <3250000>; | ||
| 424 | regulator-max-microvolt = <3250000>; | ||
| 425 | regulator-always-on; | ||
| 426 | regulator-boot-on; | ||
| 427 | }; | ||
| 428 | }; | ||
| 429 | }; | ||
| 430 | }; | ||
| 431 | }; | ||
| 432 | |||
| 433 | &i2c5 { | ||
| 434 | pinctrl-names = "default"; | ||
| 435 | pinctrl-0 = <&i2c5_pins>; | ||
| 436 | |||
| 437 | clock-frequency = <400000>; | ||
| 438 | }; | ||
| 439 | |||
| 440 | &mcbsp3 { | ||
| 441 | status = "disabled"; | ||
| 442 | }; | ||
| 443 | |||
| 444 | &usbhshost { | ||
| 445 | port2-mode = "ehci-hsic"; | ||
| 446 | port3-mode = "ehci-hsic"; | ||
| 447 | }; | ||
| 448 | |||
| 449 | &usbhsehci { | ||
| 450 | phys = <0 &hsusb2_phy &hsusb3_phy>; | ||
| 451 | }; | ||
| 452 | |||
| 453 | &mcspi1 { | ||
| 454 | |||
| 455 | }; | ||
| 456 | |||
| 457 | &mcspi2 { | ||
| 458 | pinctrl-names = "default"; | ||
| 459 | pinctrl-0 = <&mcspi2_pins>; | ||
| 460 | }; | ||
| 461 | |||
| 462 | &mcspi3 { | ||
| 463 | pinctrl-names = "default"; | ||
| 464 | pinctrl-0 = <&mcspi3_pins>; | ||
| 465 | }; | ||
| 466 | |||
| 467 | &mcspi4 { | ||
| 468 | pinctrl-names = "default"; | ||
| 469 | pinctrl-0 = <&mcspi4_pins>; | ||
| 470 | }; | ||
| 471 | |||
| 472 | &uart1 { | ||
| 473 | pinctrl-names = "default"; | ||
| 474 | pinctrl-0 = <&uart1_pins>; | ||
| 475 | }; | ||
| 476 | |||
| 477 | &uart3 { | ||
| 478 | pinctrl-names = "default"; | ||
| 479 | pinctrl-0 = <&uart3_pins>; | ||
| 480 | }; | ||
| 481 | |||
| 482 | &uart5 { | ||
| 483 | pinctrl-names = "default"; | ||
| 484 | pinctrl-0 = <&uart5_pins>; | ||
| 485 | }; | ||
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 635cae283011..e643620417a9 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi | |||
| @@ -7,15 +7,11 @@ | |||
| 7 | * Based on "omap4.dtsi" | 7 | * Based on "omap4.dtsi" |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | /* | 10 | #include <dt-bindings/gpio/gpio.h> |
| 11 | * Carveout for multimedia usecases | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 12 | * It should be the last 48MB of the first 512MB memory part | 12 | #include <dt-bindings/pinctrl/omap.h> |
| 13 | * In theory, it should not even exist. That zone should be reserved | ||
| 14 | * dynamically during the .reserve callback. | ||
| 15 | */ | ||
| 16 | /memreserve/ 0x9d000000 0x03000000; | ||
| 17 | 13 | ||
| 18 | /include/ "skeleton.dtsi" | 14 | #include "skeleton.dtsi" |
| 19 | 15 | ||
| 20 | / { | 16 | / { |
| 21 | #address-cells = <1>; | 17 | #address-cells = <1>; |
| @@ -34,21 +30,28 @@ | |||
| 34 | }; | 30 | }; |
| 35 | 31 | ||
| 36 | cpus { | 32 | cpus { |
| 33 | #address-cells = <1>; | ||
| 34 | #size-cells = <0>; | ||
| 35 | |||
| 37 | cpu@0 { | 36 | cpu@0 { |
| 37 | device_type = "cpu"; | ||
| 38 | compatible = "arm,cortex-a15"; | 38 | compatible = "arm,cortex-a15"; |
| 39 | reg = <0x0>; | ||
| 39 | }; | 40 | }; |
| 40 | cpu@1 { | 41 | cpu@1 { |
| 42 | device_type = "cpu"; | ||
| 41 | compatible = "arm,cortex-a15"; | 43 | compatible = "arm,cortex-a15"; |
| 44 | reg = <0x1>; | ||
| 42 | }; | 45 | }; |
| 43 | }; | 46 | }; |
| 44 | 47 | ||
| 45 | timer { | 48 | timer { |
| 46 | compatible = "arm,armv7-timer"; | 49 | compatible = "arm,armv7-timer"; |
| 47 | /* PPI secure/nonsecure IRQ, active low level-sensitive */ | 50 | /* PPI secure/nonsecure IRQ */ |
| 48 | interrupts = <1 13 0x308>, | 51 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 49 | <1 14 0x308>, | 52 | <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 50 | <1 11 0x308>, | 53 | <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>, |
| 51 | <1 10 0x308>; | 54 | <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>; |
| 52 | clock-frequency = <6144000>; | 55 | clock-frequency = <6144000>; |
| 53 | }; | 56 | }; |
| 54 | 57 | ||
| @@ -90,8 +93,8 @@ | |||
| 90 | reg = <0x44000000 0x2000>, | 93 | reg = <0x44000000 0x2000>, |
| 91 | <0x44800000 0x3000>, | 94 | <0x44800000 0x3000>, |
| 92 | <0x45000000 0x4000>; | 95 | <0x45000000 0x4000>; |
| 93 | interrupts = <0 9 0x4>, | 96 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 94 | <0 10 0x4>; | 97 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| 95 | 98 | ||
| 96 | counter32k: counter@4ae04000 { | 99 | counter32k: counter@4ae04000 { |
| 97 | compatible = "ti,omap-counter32k"; | 100 | compatible = "ti,omap-counter32k"; |
| @@ -119,10 +122,10 @@ | |||
| 119 | sdma: dma-controller@4a056000 { | 122 | sdma: dma-controller@4a056000 { |
| 120 | compatible = "ti,omap4430-sdma"; | 123 | compatible = "ti,omap4430-sdma"; |
| 121 | reg = <0x4a056000 0x1000>; | 124 | reg = <0x4a056000 0x1000>; |
| 122 | interrupts = <0 12 0x4>, | 125 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 123 | <0 13 0x4>, | 126 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 124 | <0 14 0x4>, | 127 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 125 | <0 15 0x4>; | 128 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 126 | #dma-cells = <1>; | 129 | #dma-cells = <1>; |
| 127 | #dma-channels = <32>; | 130 | #dma-channels = <32>; |
| 128 | #dma-requests = <127>; | 131 | #dma-requests = <127>; |
| @@ -131,7 +134,7 @@ | |||
| 131 | gpio1: gpio@4ae10000 { | 134 | gpio1: gpio@4ae10000 { |
| 132 | compatible = "ti,omap4-gpio"; | 135 | compatible = "ti,omap4-gpio"; |
| 133 | reg = <0x4ae10000 0x200>; | 136 | reg = <0x4ae10000 0x200>; |
| 134 | interrupts = <0 29 0x4>; | 137 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| 135 | ti,hwmods = "gpio1"; | 138 | ti,hwmods = "gpio1"; |
| 136 | ti,gpio-always-on; | 139 | ti,gpio-always-on; |
| 137 | gpio-controller; | 140 | gpio-controller; |
| @@ -143,7 +146,7 @@ | |||
| 143 | gpio2: gpio@48055000 { | 146 | gpio2: gpio@48055000 { |
| 144 | compatible = "ti,omap4-gpio"; | 147 | compatible = "ti,omap4-gpio"; |
| 145 | reg = <0x48055000 0x200>; | 148 | reg = <0x48055000 0x200>; |
| 146 | interrupts = <0 30 0x4>; | 149 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 147 | ti,hwmods = "gpio2"; | 150 | ti,hwmods = "gpio2"; |
| 148 | gpio-controller; | 151 | gpio-controller; |
| 149 | #gpio-cells = <2>; | 152 | #gpio-cells = <2>; |
| @@ -154,7 +157,7 @@ | |||
| 154 | gpio3: gpio@48057000 { | 157 | gpio3: gpio@48057000 { |
| 155 | compatible = "ti,omap4-gpio"; | 158 | compatible = "ti,omap4-gpio"; |
| 156 | reg = <0x48057000 0x200>; | 159 | reg = <0x48057000 0x200>; |
| 157 | interrupts = <0 31 0x4>; | 160 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 158 | ti,hwmods = "gpio3"; | 161 | ti,hwmods = "gpio3"; |
| 159 | gpio-controller; | 162 | gpio-controller; |
| 160 | #gpio-cells = <2>; | 163 | #gpio-cells = <2>; |
| @@ -165,7 +168,7 @@ | |||
| 165 | gpio4: gpio@48059000 { | 168 | gpio4: gpio@48059000 { |
| 166 | compatible = "ti,omap4-gpio"; | 169 | compatible = "ti,omap4-gpio"; |
| 167 | reg = <0x48059000 0x200>; | 170 | reg = <0x48059000 0x200>; |
| 168 | interrupts = <0 32 0x4>; | 171 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 169 | ti,hwmods = "gpio4"; | 172 | ti,hwmods = "gpio4"; |
| 170 | gpio-controller; | 173 | gpio-controller; |
| 171 | #gpio-cells = <2>; | 174 | #gpio-cells = <2>; |
| @@ -176,7 +179,7 @@ | |||
| 176 | gpio5: gpio@4805b000 { | 179 | gpio5: gpio@4805b000 { |
| 177 | compatible = "ti,omap4-gpio"; | 180 | compatible = "ti,omap4-gpio"; |
| 178 | reg = <0x4805b000 0x200>; | 181 | reg = <0x4805b000 0x200>; |
| 179 | interrupts = <0 33 0x4>; | 182 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| 180 | ti,hwmods = "gpio5"; | 183 | ti,hwmods = "gpio5"; |
| 181 | gpio-controller; | 184 | gpio-controller; |
| 182 | #gpio-cells = <2>; | 185 | #gpio-cells = <2>; |
| @@ -187,7 +190,7 @@ | |||
| 187 | gpio6: gpio@4805d000 { | 190 | gpio6: gpio@4805d000 { |
| 188 | compatible = "ti,omap4-gpio"; | 191 | compatible = "ti,omap4-gpio"; |
| 189 | reg = <0x4805d000 0x200>; | 192 | reg = <0x4805d000 0x200>; |
| 190 | interrupts = <0 34 0x4>; | 193 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| 191 | ti,hwmods = "gpio6"; | 194 | ti,hwmods = "gpio6"; |
| 192 | gpio-controller; | 195 | gpio-controller; |
| 193 | #gpio-cells = <2>; | 196 | #gpio-cells = <2>; |
| @@ -198,7 +201,7 @@ | |||
| 198 | gpio7: gpio@48051000 { | 201 | gpio7: gpio@48051000 { |
| 199 | compatible = "ti,omap4-gpio"; | 202 | compatible = "ti,omap4-gpio"; |
| 200 | reg = <0x48051000 0x200>; | 203 | reg = <0x48051000 0x200>; |
| 201 | interrupts = <0 35 0x4>; | 204 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 202 | ti,hwmods = "gpio7"; | 205 | ti,hwmods = "gpio7"; |
| 203 | gpio-controller; | 206 | gpio-controller; |
| 204 | #gpio-cells = <2>; | 207 | #gpio-cells = <2>; |
| @@ -209,7 +212,7 @@ | |||
| 209 | gpio8: gpio@48053000 { | 212 | gpio8: gpio@48053000 { |
| 210 | compatible = "ti,omap4-gpio"; | 213 | compatible = "ti,omap4-gpio"; |
| 211 | reg = <0x48053000 0x200>; | 214 | reg = <0x48053000 0x200>; |
| 212 | interrupts = <0 121 0x4>; | 215 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| 213 | ti,hwmods = "gpio8"; | 216 | ti,hwmods = "gpio8"; |
| 214 | gpio-controller; | 217 | gpio-controller; |
| 215 | #gpio-cells = <2>; | 218 | #gpio-cells = <2>; |
| @@ -222,7 +225,7 @@ | |||
| 222 | reg = <0x50000000 0x1000>; | 225 | reg = <0x50000000 0x1000>; |
| 223 | #address-cells = <2>; | 226 | #address-cells = <2>; |
| 224 | #size-cells = <1>; | 227 | #size-cells = <1>; |
| 225 | interrupts = <0 20 0x4>; | 228 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 226 | gpmc,num-cs = <8>; | 229 | gpmc,num-cs = <8>; |
| 227 | gpmc,num-waitpins = <4>; | 230 | gpmc,num-waitpins = <4>; |
| 228 | ti,hwmods = "gpmc"; | 231 | ti,hwmods = "gpmc"; |
| @@ -231,7 +234,7 @@ | |||
| 231 | i2c1: i2c@48070000 { | 234 | i2c1: i2c@48070000 { |
| 232 | compatible = "ti,omap4-i2c"; | 235 | compatible = "ti,omap4-i2c"; |
| 233 | reg = <0x48070000 0x100>; | 236 | reg = <0x48070000 0x100>; |
| 234 | interrupts = <0 56 0x4>; | 237 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| 235 | #address-cells = <1>; | 238 | #address-cells = <1>; |
| 236 | #size-cells = <0>; | 239 | #size-cells = <0>; |
| 237 | ti,hwmods = "i2c1"; | 240 | ti,hwmods = "i2c1"; |
| @@ -240,7 +243,7 @@ | |||
| 240 | i2c2: i2c@48072000 { | 243 | i2c2: i2c@48072000 { |
| 241 | compatible = "ti,omap4-i2c"; | 244 | compatible = "ti,omap4-i2c"; |
| 242 | reg = <0x48072000 0x100>; | 245 | reg = <0x48072000 0x100>; |
| 243 | interrupts = <0 57 0x4>; | 246 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| 244 | #address-cells = <1>; | 247 | #address-cells = <1>; |
| 245 | #size-cells = <0>; | 248 | #size-cells = <0>; |
| 246 | ti,hwmods = "i2c2"; | 249 | ti,hwmods = "i2c2"; |
| @@ -249,7 +252,7 @@ | |||
| 249 | i2c3: i2c@48060000 { | 252 | i2c3: i2c@48060000 { |
| 250 | compatible = "ti,omap4-i2c"; | 253 | compatible = "ti,omap4-i2c"; |
| 251 | reg = <0x48060000 0x100>; | 254 | reg = <0x48060000 0x100>; |
| 252 | interrupts = <0 61 0x4>; | 255 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| 253 | #address-cells = <1>; | 256 | #address-cells = <1>; |
| 254 | #size-cells = <0>; | 257 | #size-cells = <0>; |
| 255 | ti,hwmods = "i2c3"; | 258 | ti,hwmods = "i2c3"; |
| @@ -258,7 +261,7 @@ | |||
| 258 | i2c4: i2c@4807a000 { | 261 | i2c4: i2c@4807a000 { |
| 259 | compatible = "ti,omap4-i2c"; | 262 | compatible = "ti,omap4-i2c"; |
| 260 | reg = <0x4807a000 0x100>; | 263 | reg = <0x4807a000 0x100>; |
| 261 | interrupts = <0 62 0x4>; | 264 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| 262 | #address-cells = <1>; | 265 | #address-cells = <1>; |
| 263 | #size-cells = <0>; | 266 | #size-cells = <0>; |
| 264 | ti,hwmods = "i2c4"; | 267 | ti,hwmods = "i2c4"; |
| @@ -267,7 +270,7 @@ | |||
| 267 | i2c5: i2c@4807c000 { | 270 | i2c5: i2c@4807c000 { |
| 268 | compatible = "ti,omap4-i2c"; | 271 | compatible = "ti,omap4-i2c"; |
| 269 | reg = <0x4807c000 0x100>; | 272 | reg = <0x4807c000 0x100>; |
| 270 | interrupts = <0 60 0x4>; | 273 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| 271 | #address-cells = <1>; | 274 | #address-cells = <1>; |
| 272 | #size-cells = <0>; | 275 | #size-cells = <0>; |
| 273 | ti,hwmods = "i2c5"; | 276 | ti,hwmods = "i2c5"; |
| @@ -276,7 +279,7 @@ | |||
| 276 | mcspi1: spi@48098000 { | 279 | mcspi1: spi@48098000 { |
| 277 | compatible = "ti,omap4-mcspi"; | 280 | compatible = "ti,omap4-mcspi"; |
| 278 | reg = <0x48098000 0x200>; | 281 | reg = <0x48098000 0x200>; |
| 279 | interrupts = <0 65 0x4>; | 282 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 280 | #address-cells = <1>; | 283 | #address-cells = <1>; |
| 281 | #size-cells = <0>; | 284 | #size-cells = <0>; |
| 282 | ti,hwmods = "mcspi1"; | 285 | ti,hwmods = "mcspi1"; |
| @@ -296,7 +299,7 @@ | |||
| 296 | mcspi2: spi@4809a000 { | 299 | mcspi2: spi@4809a000 { |
| 297 | compatible = "ti,omap4-mcspi"; | 300 | compatible = "ti,omap4-mcspi"; |
| 298 | reg = <0x4809a000 0x200>; | 301 | reg = <0x4809a000 0x200>; |
| 299 | interrupts = <0 66 0x4>; | 302 | interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| 300 | #address-cells = <1>; | 303 | #address-cells = <1>; |
| 301 | #size-cells = <0>; | 304 | #size-cells = <0>; |
| 302 | ti,hwmods = "mcspi2"; | 305 | ti,hwmods = "mcspi2"; |
| @@ -311,7 +314,7 @@ | |||
| 311 | mcspi3: spi@480b8000 { | 314 | mcspi3: spi@480b8000 { |
| 312 | compatible = "ti,omap4-mcspi"; | 315 | compatible = "ti,omap4-mcspi"; |
| 313 | reg = <0x480b8000 0x200>; | 316 | reg = <0x480b8000 0x200>; |
| 314 | interrupts = <0 91 0x4>; | 317 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| 315 | #address-cells = <1>; | 318 | #address-cells = <1>; |
| 316 | #size-cells = <0>; | 319 | #size-cells = <0>; |
| 317 | ti,hwmods = "mcspi3"; | 320 | ti,hwmods = "mcspi3"; |
| @@ -323,7 +326,7 @@ | |||
| 323 | mcspi4: spi@480ba000 { | 326 | mcspi4: spi@480ba000 { |
| 324 | compatible = "ti,omap4-mcspi"; | 327 | compatible = "ti,omap4-mcspi"; |
| 325 | reg = <0x480ba000 0x200>; | 328 | reg = <0x480ba000 0x200>; |
| 326 | interrupts = <0 48 0x4>; | 329 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| 327 | #address-cells = <1>; | 330 | #address-cells = <1>; |
| 328 | #size-cells = <0>; | 331 | #size-cells = <0>; |
| 329 | ti,hwmods = "mcspi4"; | 332 | ti,hwmods = "mcspi4"; |
| @@ -335,7 +338,7 @@ | |||
| 335 | uart1: serial@4806a000 { | 338 | uart1: serial@4806a000 { |
| 336 | compatible = "ti,omap4-uart"; | 339 | compatible = "ti,omap4-uart"; |
| 337 | reg = <0x4806a000 0x100>; | 340 | reg = <0x4806a000 0x100>; |
| 338 | interrupts = <0 72 0x4>; | 341 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| 339 | ti,hwmods = "uart1"; | 342 | ti,hwmods = "uart1"; |
| 340 | clock-frequency = <48000000>; | 343 | clock-frequency = <48000000>; |
| 341 | }; | 344 | }; |
| @@ -343,7 +346,7 @@ | |||
| 343 | uart2: serial@4806c000 { | 346 | uart2: serial@4806c000 { |
| 344 | compatible = "ti,omap4-uart"; | 347 | compatible = "ti,omap4-uart"; |
| 345 | reg = <0x4806c000 0x100>; | 348 | reg = <0x4806c000 0x100>; |
| 346 | interrupts = <0 73 0x4>; | 349 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 347 | ti,hwmods = "uart2"; | 350 | ti,hwmods = "uart2"; |
| 348 | clock-frequency = <48000000>; | 351 | clock-frequency = <48000000>; |
| 349 | }; | 352 | }; |
| @@ -351,7 +354,7 @@ | |||
| 351 | uart3: serial@48020000 { | 354 | uart3: serial@48020000 { |
| 352 | compatible = "ti,omap4-uart"; | 355 | compatible = "ti,omap4-uart"; |
| 353 | reg = <0x48020000 0x100>; | 356 | reg = <0x48020000 0x100>; |
| 354 | interrupts = <0 74 0x4>; | 357 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 355 | ti,hwmods = "uart3"; | 358 | ti,hwmods = "uart3"; |
| 356 | clock-frequency = <48000000>; | 359 | clock-frequency = <48000000>; |
| 357 | }; | 360 | }; |
| @@ -359,7 +362,7 @@ | |||
| 359 | uart4: serial@4806e000 { | 362 | uart4: serial@4806e000 { |
| 360 | compatible = "ti,omap4-uart"; | 363 | compatible = "ti,omap4-uart"; |
| 361 | reg = <0x4806e000 0x100>; | 364 | reg = <0x4806e000 0x100>; |
| 362 | interrupts = <0 70 0x4>; | 365 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 363 | ti,hwmods = "uart4"; | 366 | ti,hwmods = "uart4"; |
| 364 | clock-frequency = <48000000>; | 367 | clock-frequency = <48000000>; |
| 365 | }; | 368 | }; |
| @@ -367,7 +370,7 @@ | |||
| 367 | uart5: serial@48066000 { | 370 | uart5: serial@48066000 { |
| 368 | compatible = "ti,omap4-uart"; | 371 | compatible = "ti,omap4-uart"; |
| 369 | reg = <0x48066000 0x100>; | 372 | reg = <0x48066000 0x100>; |
| 370 | interrupts = <0 105 0x4>; | 373 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| 371 | ti,hwmods = "uart5"; | 374 | ti,hwmods = "uart5"; |
| 372 | clock-frequency = <48000000>; | 375 | clock-frequency = <48000000>; |
| 373 | }; | 376 | }; |
| @@ -375,7 +378,7 @@ | |||
| 375 | uart6: serial@48068000 { | 378 | uart6: serial@48068000 { |
| 376 | compatible = "ti,omap4-uart"; | 379 | compatible = "ti,omap4-uart"; |
| 377 | reg = <0x48068000 0x100>; | 380 | reg = <0x48068000 0x100>; |
| 378 | interrupts = <0 106 0x4>; | 381 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 379 | ti,hwmods = "uart6"; | 382 | ti,hwmods = "uart6"; |
| 380 | clock-frequency = <48000000>; | 383 | clock-frequency = <48000000>; |
| 381 | }; | 384 | }; |
| @@ -383,7 +386,7 @@ | |||
| 383 | mmc1: mmc@4809c000 { | 386 | mmc1: mmc@4809c000 { |
| 384 | compatible = "ti,omap4-hsmmc"; | 387 | compatible = "ti,omap4-hsmmc"; |
| 385 | reg = <0x4809c000 0x400>; | 388 | reg = <0x4809c000 0x400>; |
| 386 | interrupts = <0 83 0x4>; | 389 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 387 | ti,hwmods = "mmc1"; | 390 | ti,hwmods = "mmc1"; |
| 388 | ti,dual-volt; | 391 | ti,dual-volt; |
| 389 | ti,needs-special-reset; | 392 | ti,needs-special-reset; |
| @@ -394,7 +397,7 @@ | |||
| 394 | mmc2: mmc@480b4000 { | 397 | mmc2: mmc@480b4000 { |
| 395 | compatible = "ti,omap4-hsmmc"; | 398 | compatible = "ti,omap4-hsmmc"; |
| 396 | reg = <0x480b4000 0x400>; | 399 | reg = <0x480b4000 0x400>; |
| 397 | interrupts = <0 86 0x4>; | 400 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 398 | ti,hwmods = "mmc2"; | 401 | ti,hwmods = "mmc2"; |
| 399 | ti,needs-special-reset; | 402 | ti,needs-special-reset; |
| 400 | dmas = <&sdma 47>, <&sdma 48>; | 403 | dmas = <&sdma 47>, <&sdma 48>; |
| @@ -404,7 +407,7 @@ | |||
| 404 | mmc3: mmc@480ad000 { | 407 | mmc3: mmc@480ad000 { |
| 405 | compatible = "ti,omap4-hsmmc"; | 408 | compatible = "ti,omap4-hsmmc"; |
| 406 | reg = <0x480ad000 0x400>; | 409 | reg = <0x480ad000 0x400>; |
| 407 | interrupts = <0 94 0x4>; | 410 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 408 | ti,hwmods = "mmc3"; | 411 | ti,hwmods = "mmc3"; |
| 409 | ti,needs-special-reset; | 412 | ti,needs-special-reset; |
| 410 | dmas = <&sdma 77>, <&sdma 78>; | 413 | dmas = <&sdma 77>, <&sdma 78>; |
| @@ -414,7 +417,7 @@ | |||
| 414 | mmc4: mmc@480d1000 { | 417 | mmc4: mmc@480d1000 { |
| 415 | compatible = "ti,omap4-hsmmc"; | 418 | compatible = "ti,omap4-hsmmc"; |
| 416 | reg = <0x480d1000 0x400>; | 419 | reg = <0x480d1000 0x400>; |
| 417 | interrupts = <0 96 0x4>; | 420 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 418 | ti,hwmods = "mmc4"; | 421 | ti,hwmods = "mmc4"; |
| 419 | ti,needs-special-reset; | 422 | ti,needs-special-reset; |
| 420 | dmas = <&sdma 57>, <&sdma 58>; | 423 | dmas = <&sdma 57>, <&sdma 58>; |
| @@ -424,7 +427,7 @@ | |||
| 424 | mmc5: mmc@480d5000 { | 427 | mmc5: mmc@480d5000 { |
| 425 | compatible = "ti,omap4-hsmmc"; | 428 | compatible = "ti,omap4-hsmmc"; |
| 426 | reg = <0x480d5000 0x400>; | 429 | reg = <0x480d5000 0x400>; |
| 427 | interrupts = <0 59 0x4>; | 430 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 428 | ti,hwmods = "mmc5"; | 431 | ti,hwmods = "mmc5"; |
| 429 | ti,needs-special-reset; | 432 | ti,needs-special-reset; |
| 430 | dmas = <&sdma 59>, <&sdma 60>; | 433 | dmas = <&sdma 59>, <&sdma 60>; |
| @@ -442,7 +445,7 @@ | |||
| 442 | reg = <0x40132000 0x7f>, /* MPU private access */ | 445 | reg = <0x40132000 0x7f>, /* MPU private access */ |
| 443 | <0x49032000 0x7f>; /* L3 Interconnect */ | 446 | <0x49032000 0x7f>; /* L3 Interconnect */ |
| 444 | reg-names = "mpu", "dma"; | 447 | reg-names = "mpu", "dma"; |
| 445 | interrupts = <0 112 0x4>; | 448 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| 446 | ti,hwmods = "mcpdm"; | 449 | ti,hwmods = "mcpdm"; |
| 447 | dmas = <&sdma 65>, | 450 | dmas = <&sdma 65>, |
| 448 | <&sdma 66>; | 451 | <&sdma 66>; |
| @@ -454,7 +457,7 @@ | |||
| 454 | reg = <0x4012e000 0x7f>, /* MPU private access */ | 457 | reg = <0x4012e000 0x7f>, /* MPU private access */ |
| 455 | <0x4902e000 0x7f>; /* L3 Interconnect */ | 458 | <0x4902e000 0x7f>; /* L3 Interconnect */ |
| 456 | reg-names = "mpu", "dma"; | 459 | reg-names = "mpu", "dma"; |
| 457 | interrupts = <0 114 0x4>; | 460 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| 458 | ti,hwmods = "dmic"; | 461 | ti,hwmods = "dmic"; |
| 459 | dmas = <&sdma 67>; | 462 | dmas = <&sdma 67>; |
| 460 | dma-names = "up_link"; | 463 | dma-names = "up_link"; |
| @@ -465,7 +468,7 @@ | |||
| 465 | reg = <0x40122000 0xff>, /* MPU private access */ | 468 | reg = <0x40122000 0xff>, /* MPU private access */ |
| 466 | <0x49022000 0xff>; /* L3 Interconnect */ | 469 | <0x49022000 0xff>; /* L3 Interconnect */ |
| 467 | reg-names = "mpu", "dma"; | 470 | reg-names = "mpu", "dma"; |
| 468 | interrupts = <0 17 0x4>; | 471 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| 469 | interrupt-names = "common"; | 472 | interrupt-names = "common"; |
| 470 | ti,buffer-size = <128>; | 473 | ti,buffer-size = <128>; |
| 471 | ti,hwmods = "mcbsp1"; | 474 | ti,hwmods = "mcbsp1"; |
| @@ -479,7 +482,7 @@ | |||
| 479 | reg = <0x40124000 0xff>, /* MPU private access */ | 482 | reg = <0x40124000 0xff>, /* MPU private access */ |
| 480 | <0x49024000 0xff>; /* L3 Interconnect */ | 483 | <0x49024000 0xff>; /* L3 Interconnect */ |
| 481 | reg-names = "mpu", "dma"; | 484 | reg-names = "mpu", "dma"; |
| 482 | interrupts = <0 22 0x4>; | 485 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| 483 | interrupt-names = "common"; | 486 | interrupt-names = "common"; |
| 484 | ti,buffer-size = <128>; | 487 | ti,buffer-size = <128>; |
| 485 | ti,hwmods = "mcbsp2"; | 488 | ti,hwmods = "mcbsp2"; |
| @@ -493,7 +496,7 @@ | |||
| 493 | reg = <0x40126000 0xff>, /* MPU private access */ | 496 | reg = <0x40126000 0xff>, /* MPU private access */ |
| 494 | <0x49026000 0xff>; /* L3 Interconnect */ | 497 | <0x49026000 0xff>; /* L3 Interconnect */ |
| 495 | reg-names = "mpu", "dma"; | 498 | reg-names = "mpu", "dma"; |
| 496 | interrupts = <0 23 0x4>; | 499 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| 497 | interrupt-names = "common"; | 500 | interrupt-names = "common"; |
| 498 | ti,buffer-size = <128>; | 501 | ti,buffer-size = <128>; |
| 499 | ti,hwmods = "mcbsp3"; | 502 | ti,hwmods = "mcbsp3"; |
| @@ -505,7 +508,7 @@ | |||
| 505 | timer1: timer@4ae18000 { | 508 | timer1: timer@4ae18000 { |
| 506 | compatible = "ti,omap5430-timer"; | 509 | compatible = "ti,omap5430-timer"; |
| 507 | reg = <0x4ae18000 0x80>; | 510 | reg = <0x4ae18000 0x80>; |
| 508 | interrupts = <0 37 0x4>; | 511 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 509 | ti,hwmods = "timer1"; | 512 | ti,hwmods = "timer1"; |
| 510 | ti,timer-alwon; | 513 | ti,timer-alwon; |
| 511 | }; | 514 | }; |
| @@ -513,21 +516,21 @@ | |||
| 513 | timer2: timer@48032000 { | 516 | timer2: timer@48032000 { |
| 514 | compatible = "ti,omap5430-timer"; | 517 | compatible = "ti,omap5430-timer"; |
| 515 | reg = <0x48032000 0x80>; | 518 | reg = <0x48032000 0x80>; |
| 516 | interrupts = <0 38 0x4>; | 519 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 517 | ti,hwmods = "timer2"; | 520 | ti,hwmods = "timer2"; |
| 518 | }; | 521 | }; |
| 519 | 522 | ||
| 520 | timer3: timer@48034000 { | 523 | timer3: timer@48034000 { |
| 521 | compatible = "ti,omap5430-timer"; | 524 | compatible = "ti,omap5430-timer"; |
| 522 | reg = <0x48034000 0x80>; | 525 | reg = <0x48034000 0x80>; |
| 523 | interrupts = <0 39 0x4>; | 526 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| 524 | ti,hwmods = "timer3"; | 527 | ti,hwmods = "timer3"; |
| 525 | }; | 528 | }; |
| 526 | 529 | ||
| 527 | timer4: timer@48036000 { | 530 | timer4: timer@48036000 { |
| 528 | compatible = "ti,omap5430-timer"; | 531 | compatible = "ti,omap5430-timer"; |
| 529 | reg = <0x48036000 0x80>; | 532 | reg = <0x48036000 0x80>; |
| 530 | interrupts = <0 40 0x4>; | 533 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| 531 | ti,hwmods = "timer4"; | 534 | ti,hwmods = "timer4"; |
| 532 | }; | 535 | }; |
| 533 | 536 | ||
| @@ -535,7 +538,7 @@ | |||
| 535 | compatible = "ti,omap5430-timer"; | 538 | compatible = "ti,omap5430-timer"; |
| 536 | reg = <0x40138000 0x80>, | 539 | reg = <0x40138000 0x80>, |
| 537 | <0x49038000 0x80>; | 540 | <0x49038000 0x80>; |
| 538 | interrupts = <0 41 0x4>; | 541 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| 539 | ti,hwmods = "timer5"; | 542 | ti,hwmods = "timer5"; |
| 540 | ti,timer-dsp; | 543 | ti,timer-dsp; |
| 541 | ti,timer-pwm; | 544 | ti,timer-pwm; |
| @@ -545,7 +548,7 @@ | |||
| 545 | compatible = "ti,omap5430-timer"; | 548 | compatible = "ti,omap5430-timer"; |
| 546 | reg = <0x4013a000 0x80>, | 549 | reg = <0x4013a000 0x80>, |
| 547 | <0x4903a000 0x80>; | 550 | <0x4903a000 0x80>; |
| 548 | interrupts = <0 42 0x4>; | 551 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| 549 | ti,hwmods = "timer6"; | 552 | ti,hwmods = "timer6"; |
| 550 | ti,timer-dsp; | 553 | ti,timer-dsp; |
| 551 | ti,timer-pwm; | 554 | ti,timer-pwm; |
| @@ -555,7 +558,7 @@ | |||
| 555 | compatible = "ti,omap5430-timer"; | 558 | compatible = "ti,omap5430-timer"; |
| 556 | reg = <0x4013c000 0x80>, | 559 | reg = <0x4013c000 0x80>, |
| 557 | <0x4903c000 0x80>; | 560 | <0x4903c000 0x80>; |
| 558 | interrupts = <0 43 0x4>; | 561 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| 559 | ti,hwmods = "timer7"; | 562 | ti,hwmods = "timer7"; |
| 560 | ti,timer-dsp; | 563 | ti,timer-dsp; |
| 561 | }; | 564 | }; |
| @@ -564,7 +567,7 @@ | |||
| 564 | compatible = "ti,omap5430-timer"; | 567 | compatible = "ti,omap5430-timer"; |
| 565 | reg = <0x4013e000 0x80>, | 568 | reg = <0x4013e000 0x80>, |
| 566 | <0x4903e000 0x80>; | 569 | <0x4903e000 0x80>; |
| 567 | interrupts = <0 44 0x4>; | 570 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| 568 | ti,hwmods = "timer8"; | 571 | ti,hwmods = "timer8"; |
| 569 | ti,timer-dsp; | 572 | ti,timer-dsp; |
| 570 | ti,timer-pwm; | 573 | ti,timer-pwm; |
| @@ -573,7 +576,7 @@ | |||
| 573 | timer9: timer@4803e000 { | 576 | timer9: timer@4803e000 { |
| 574 | compatible = "ti,omap5430-timer"; | 577 | compatible = "ti,omap5430-timer"; |
| 575 | reg = <0x4803e000 0x80>; | 578 | reg = <0x4803e000 0x80>; |
| 576 | interrupts = <0 45 0x4>; | 579 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 577 | ti,hwmods = "timer9"; | 580 | ti,hwmods = "timer9"; |
| 578 | ti,timer-pwm; | 581 | ti,timer-pwm; |
| 579 | }; | 582 | }; |
| @@ -581,7 +584,7 @@ | |||
| 581 | timer10: timer@48086000 { | 584 | timer10: timer@48086000 { |
| 582 | compatible = "ti,omap5430-timer"; | 585 | compatible = "ti,omap5430-timer"; |
| 583 | reg = <0x48086000 0x80>; | 586 | reg = <0x48086000 0x80>; |
| 584 | interrupts = <0 46 0x4>; | 587 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 585 | ti,hwmods = "timer10"; | 588 | ti,hwmods = "timer10"; |
| 586 | ti,timer-pwm; | 589 | ti,timer-pwm; |
| 587 | }; | 590 | }; |
| @@ -589,7 +592,7 @@ | |||
| 589 | timer11: timer@48088000 { | 592 | timer11: timer@48088000 { |
| 590 | compatible = "ti,omap5430-timer"; | 593 | compatible = "ti,omap5430-timer"; |
| 591 | reg = <0x48088000 0x80>; | 594 | reg = <0x48088000 0x80>; |
| 592 | interrupts = <0 47 0x4>; | 595 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| 593 | ti,hwmods = "timer11"; | 596 | ti,hwmods = "timer11"; |
| 594 | ti,timer-pwm; | 597 | ti,timer-pwm; |
| 595 | }; | 598 | }; |
| @@ -597,7 +600,7 @@ | |||
| 597 | wdt2: wdt@4ae14000 { | 600 | wdt2: wdt@4ae14000 { |
| 598 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; | 601 | compatible = "ti,omap5-wdt", "ti,omap3-wdt"; |
| 599 | reg = <0x4ae14000 0x80>; | 602 | reg = <0x4ae14000 0x80>; |
| 600 | interrupts = <0 80 0x4>; | 603 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| 601 | ti,hwmods = "wd_timer2"; | 604 | ti,hwmods = "wd_timer2"; |
| 602 | }; | 605 | }; |
| 603 | 606 | ||
| @@ -606,7 +609,7 @@ | |||
| 606 | ti,hwmods = "emif1"; | 609 | ti,hwmods = "emif1"; |
| 607 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | 610 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
| 608 | reg = <0x4c000000 0x400>; | 611 | reg = <0x4c000000 0x400>; |
| 609 | interrupts = <0 110 0x4>; | 612 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 610 | hw-caps-read-idle-ctrl; | 613 | hw-caps-read-idle-ctrl; |
| 611 | hw-caps-ll-interface; | 614 | hw-caps-ll-interface; |
| 612 | hw-caps-temp-alert; | 615 | hw-caps-temp-alert; |
| @@ -617,7 +620,7 @@ | |||
| 617 | ti,hwmods = "emif2"; | 620 | ti,hwmods = "emif2"; |
| 618 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | 621 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ |
| 619 | reg = <0x4d000000 0x400>; | 622 | reg = <0x4d000000 0x400>; |
| 620 | interrupts = <0 111 0x4>; | 623 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| 621 | hw-caps-read-idle-ctrl; | 624 | hw-caps-read-idle-ctrl; |
| 622 | hw-caps-ll-interface; | 625 | hw-caps-ll-interface; |
| 623 | hw-caps-temp-alert; | 626 | hw-caps-temp-alert; |
| @@ -635,7 +638,7 @@ | |||
| 635 | compatible = "ti,dwc3"; | 638 | compatible = "ti,dwc3"; |
| 636 | ti,hwmods = "usb_otg_ss"; | 639 | ti,hwmods = "usb_otg_ss"; |
| 637 | reg = <0x4a020000 0x1000>; | 640 | reg = <0x4a020000 0x1000>; |
| 638 | interrupts = <0 93 4>; | 641 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 639 | #address-cells = <1>; | 642 | #address-cells = <1>; |
| 640 | #size-cells = <1>; | 643 | #size-cells = <1>; |
| 641 | utmi-mode = <2>; | 644 | utmi-mode = <2>; |
| @@ -643,7 +646,7 @@ | |||
| 643 | dwc3@4a030000 { | 646 | dwc3@4a030000 { |
| 644 | compatible = "synopsys,dwc3"; | 647 | compatible = "synopsys,dwc3"; |
| 645 | reg = <0x4a030000 0x1000>; | 648 | reg = <0x4a030000 0x1000>; |
| 646 | interrupts = <0 92 4>; | 649 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 647 | usb-phy = <&usb2_phy>, <&usb3_phy>; | 650 | usb-phy = <&usb2_phy>, <&usb3_phy>; |
| 648 | tx-fifo-resize; | 651 | tx-fifo-resize; |
| 649 | }; | 652 | }; |
| @@ -670,5 +673,44 @@ | |||
| 670 | ctrl-module = <&omap_control_usb>; | 673 | ctrl-module = <&omap_control_usb>; |
| 671 | }; | 674 | }; |
| 672 | }; | 675 | }; |
| 676 | |||
| 677 | usbhstll: usbhstll@4a062000 { | ||
| 678 | compatible = "ti,usbhs-tll"; | ||
| 679 | reg = <0x4a062000 0x1000>; | ||
| 680 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | ||
| 681 | ti,hwmods = "usb_tll_hs"; | ||
| 682 | }; | ||
| 683 | |||
| 684 | usbhshost: usbhshost@4a064000 { | ||
| 685 | compatible = "ti,usbhs-host"; | ||
| 686 | reg = <0x4a064000 0x800>; | ||
| 687 | ti,hwmods = "usb_host_hs"; | ||
| 688 | #address-cells = <1>; | ||
| 689 | #size-cells = <1>; | ||
| 690 | ranges; | ||
| 691 | |||
| 692 | usbhsohci: ohci@4a064800 { | ||
| 693 | compatible = "ti,ohci-omap3", "usb-ohci"; | ||
| 694 | reg = <0x4a064800 0x400>; | ||
| 695 | interrupt-parent = <&gic>; | ||
| 696 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | ||
| 697 | }; | ||
| 698 | |||
| 699 | usbhsehci: ehci@4a064c00 { | ||
| 700 | compatible = "ti,ehci-omap", "usb-ehci"; | ||
| 701 | reg = <0x4a064c00 0x400>; | ||
| 702 | interrupt-parent = <&gic>; | ||
| 703 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | ||
| 704 | }; | ||
| 705 | }; | ||
| 706 | |||
| 707 | bandgap@4a0021e0 { | ||
| 708 | reg = <0x4a0021e0 0xc | ||
| 709 | 0x4a00232c 0xc | ||
| 710 | 0x4a002380 0x2c | ||
| 711 | 0x4a0023C0 0x3c>; | ||
| 712 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; | ||
| 713 | compatible = "ti,omap5430-bandgap"; | ||
| 714 | }; | ||
| 673 | }; | 715 | }; |
| 674 | }; | 716 | }; |
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi index f0a8c2068ea7..533919e96eae 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi | |||
| @@ -18,13 +18,13 @@ | |||
| 18 | #size-cells = <1>; | 18 | #size-cells = <1>; |
| 19 | 19 | ||
| 20 | cpus { | 20 | cpus { |
| 21 | #address-cells = <1>; | 21 | #address-cells = <0>; |
| 22 | #size-cells = <0>; | 22 | #size-cells = <0>; |
| 23 | 23 | ||
| 24 | cpu@0 { | 24 | cpu { |
| 25 | compatible = "arm,1176jz-s"; | 25 | compatible = "arm,arm1176jz-s"; |
| 26 | device_type = "cpu"; | ||
| 26 | clock-frequency = <400000000>; | 27 | clock-frequency = <400000000>; |
| 27 | reg = <0>; | ||
| 28 | d-cache-line-size = <32>; | 28 | d-cache-line-size = <32>; |
| 29 | d-cache-size = <32768>; | 29 | d-cache-size = <32768>; |
| 30 | i-cache-line-size = <32>; | 30 | i-cache-line-size = <32>; |
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi index daa962d191e6..ab3e80085511 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi | |||
| @@ -18,13 +18,13 @@ | |||
| 18 | #size-cells = <1>; | 18 | #size-cells = <1>; |
| 19 | 19 | ||
| 20 | cpus { | 20 | cpus { |
| 21 | #address-cells = <1>; | 21 | #address-cells = <0>; |
| 22 | #size-cells = <0>; | 22 | #size-cells = <0>; |
| 23 | 23 | ||
| 24 | cpu@0 { | 24 | cpu { |
| 25 | compatible = "arm,1176jz-s"; | 25 | compatible = "arm,arm1176jz-s"; |
| 26 | device_type = "cpu"; | ||
| 26 | cpu-clock = <&arm_clk>, "cpu"; | 27 | cpu-clock = <&arm_clk>, "cpu"; |
| 27 | reg = <0>; | ||
| 28 | d-cache-line-size = <32>; | 28 | d-cache-line-size = <32>; |
| 29 | d-cache-size = <32768>; | 29 | d-cache-size = <32768>; |
| 30 | i-cache-line-size = <32>; | 30 | i-cache-line-size = <32>; |
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 3329719a9412..02edd8965f8a 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi | |||
| @@ -18,6 +18,8 @@ | |||
| 18 | #size-cells = <0>; | 18 | #size-cells = <0>; |
| 19 | 19 | ||
| 20 | cpu@0 { | 20 | cpu@0 { |
| 21 | compatible = "arm,cortex-a9"; | ||
| 22 | device_type = "cpu"; | ||
| 21 | reg = <0x0>; | 23 | reg = <0x0>; |
| 22 | d-cache-line-size = <32>; | 24 | d-cache-line-size = <32>; |
| 23 | i-cache-line-size = <32>; | 25 | i-cache-line-size = <32>; |
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index f18aad35e8b3..a5e90f078aa9 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi | |||
| @@ -23,8 +23,11 @@ | |||
| 23 | }; | 23 | }; |
| 24 | 24 | ||
| 25 | cpus { | 25 | cpus { |
| 26 | cpu@0 { | 26 | #address-cells = <0>; |
| 27 | compatible = "arm,xscale"; | 27 | #size-cells = <0>; |
| 28 | cpu { | ||
| 29 | compatible = "marvell,xscale"; | ||
| 30 | device_type = "cpu"; | ||
| 28 | }; | 31 | }; |
| 29 | }; | 32 | }; |
| 30 | 33 | ||
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index fde2a337d1ff..4ff2019c0e30 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi | |||
| @@ -37,12 +37,6 @@ | |||
| 37 | <0 0xf1004000 0 0x2000>, | 37 | <0 0xf1004000 0 0x2000>, |
| 38 | <0 0xf1006000 0 0x2000>; | 38 | <0 0xf1006000 0 0x2000>; |
| 39 | interrupts = <1 9 0xf04>; | 39 | interrupts = <1 9 0xf04>; |
| 40 | |||
| 41 | gic-cpuif@4 { | ||
| 42 | compatible = "arm,gic-cpuif"; | ||
| 43 | cpuif-id = <4>; | ||
| 44 | cpu = <&cpu0>; | ||
| 45 | }; | ||
| 46 | }; | 40 | }; |
| 47 | 41 | ||
| 48 | timer { | 42 | timer { |
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts new file mode 100644 index 000000000000..09ea22c26359 --- /dev/null +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * Reference Device Tree Source for the armadillo 800 eva board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Renesas Solutions Corp. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public License | ||
| 7 | * version 2. This program is licensed "as is" without any warranty of any | ||
| 8 | * kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /dts-v1/; | ||
| 12 | /include/ "r8a7740.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "armadillo 800 eva reference"; | ||
| 16 | compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740"; | ||
| 17 | |||
| 18 | chosen { | ||
| 19 | bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"; | ||
| 20 | }; | ||
| 21 | |||
| 22 | memory { | ||
| 23 | device_type = "memory"; | ||
| 24 | reg = <0x40000000 0x20000000>; | ||
| 25 | }; | ||
| 26 | |||
| 27 | reg_3p3v: regulator@0 { | ||
| 28 | compatible = "regulator-fixed"; | ||
| 29 | regulator-name = "fixed-3.3V"; | ||
| 30 | regulator-min-microvolt = <3300000>; | ||
| 31 | regulator-max-microvolt = <3300000>; | ||
| 32 | regulator-always-on; | ||
| 33 | regulator-boot-on; | ||
| 34 | }; | ||
| 35 | |||
| 36 | }; | ||
| 37 | |||
| 38 | &i2c0 { | ||
| 39 | touchscreen: st1232@55 { | ||
| 40 | compatible = "sitronix,st1232"; | ||
| 41 | reg = <0x55>; | ||
| 42 | interrupt-parent = <&irqpin1>; | ||
| 43 | interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ | ||
| 44 | }; | ||
| 45 | }; | ||
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 798fa35c0005..24e930643821 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi | |||
| @@ -14,8 +14,129 @@ | |||
| 14 | compatible = "renesas,r8a7740"; | 14 | compatible = "renesas,r8a7740"; |
| 15 | 15 | ||
| 16 | cpus { | 16 | cpus { |
| 17 | #address-cells = <1>; | ||
| 18 | #size-cells = <0>; | ||
| 17 | cpu@0 { | 19 | cpu@0 { |
| 18 | compatible = "arm,cortex-a9"; | 20 | compatible = "arm,cortex-a9"; |
| 21 | device_type = "cpu"; | ||
| 22 | reg = <0x0>; | ||
| 19 | }; | 23 | }; |
| 20 | }; | 24 | }; |
| 25 | |||
| 26 | gic: interrupt-controller@c2800000 { | ||
| 27 | compatible = "arm,cortex-a9-gic"; | ||
| 28 | #interrupt-cells = <3>; | ||
| 29 | #address-cells = <1>; | ||
| 30 | interrupt-controller; | ||
| 31 | reg = <0xc2800000 0x1000>, | ||
| 32 | <0xc2000000 0x1000>; | ||
| 33 | }; | ||
| 34 | |||
| 35 | /* irqpin0: IRQ0 - IRQ7 */ | ||
| 36 | irqpin0: irqpin@e6900000 { | ||
| 37 | compatible = "renesas,intc-irqpin"; | ||
| 38 | #interrupt-cells = <2>; | ||
| 39 | interrupt-controller; | ||
| 40 | reg = <0xe6900000 4>, | ||
| 41 | <0xe6900010 4>, | ||
| 42 | <0xe6900020 1>, | ||
| 43 | <0xe6900040 1>, | ||
| 44 | <0xe6900060 1>; | ||
| 45 | interrupt-parent = <&gic>; | ||
| 46 | interrupts = <0 149 0x4 | ||
| 47 | 0 149 0x4 | ||
| 48 | 0 149 0x4 | ||
| 49 | 0 149 0x4 | ||
| 50 | 0 149 0x4 | ||
| 51 | 0 149 0x4 | ||
| 52 | 0 149 0x4 | ||
| 53 | 0 149 0x4>; | ||
| 54 | }; | ||
| 55 | |||
| 56 | /* irqpin1: IRQ8 - IRQ15 */ | ||
| 57 | irqpin1: irqpin@e6900004 { | ||
| 58 | compatible = "renesas,intc-irqpin"; | ||
| 59 | #interrupt-cells = <2>; | ||
| 60 | interrupt-controller; | ||
| 61 | reg = <0xe6900004 4>, | ||
| 62 | <0xe6900014 4>, | ||
| 63 | <0xe6900024 1>, | ||
| 64 | <0xe6900044 1>, | ||
| 65 | <0xe6900064 1>; | ||
| 66 | interrupt-parent = <&gic>; | ||
| 67 | interrupts = <0 149 0x4 | ||
| 68 | 0 149 0x4 | ||
| 69 | 0 149 0x4 | ||
| 70 | 0 149 0x4 | ||
| 71 | 0 149 0x4 | ||
| 72 | 0 149 0x4 | ||
| 73 | 0 149 0x4 | ||
| 74 | 0 149 0x4>; | ||
| 75 | }; | ||
| 76 | |||
| 77 | /* irqpin2: IRQ16 - IRQ23 */ | ||
| 78 | irqpin2: irqpin@e6900008 { | ||
| 79 | compatible = "renesas,intc-irqpin"; | ||
| 80 | #interrupt-cells = <2>; | ||
| 81 | interrupt-controller; | ||
| 82 | reg = <0xe6900008 4>, | ||
| 83 | <0xe6900018 4>, | ||
| 84 | <0xe6900028 1>, | ||
| 85 | <0xe6900048 1>, | ||
| 86 | <0xe6900068 1>; | ||
| 87 | interrupt-parent = <&gic>; | ||
| 88 | interrupts = <0 149 0x4 | ||
| 89 | 0 149 0x4 | ||
| 90 | 0 149 0x4 | ||
| 91 | 0 149 0x4 | ||
| 92 | 0 149 0x4 | ||
| 93 | 0 149 0x4 | ||
| 94 | 0 149 0x4 | ||
| 95 | 0 149 0x4>; | ||
| 96 | }; | ||
| 97 | |||
| 98 | /* irqpin3: IRQ24 - IRQ31 */ | ||
| 99 | irqpin3: irqpin@e690000c { | ||
| 100 | compatible = "renesas,intc-irqpin"; | ||
| 101 | #interrupt-cells = <2>; | ||
| 102 | interrupt-controller; | ||
| 103 | reg = <0xe690000c 4>, | ||
| 104 | <0xe690001c 4>, | ||
| 105 | <0xe690002c 1>, | ||
| 106 | <0xe690004c 1>, | ||
| 107 | <0xe690006c 1>; | ||
| 108 | interrupt-parent = <&gic>; | ||
| 109 | interrupts = <0 149 0x4 | ||
| 110 | 0 149 0x4 | ||
| 111 | 0 149 0x4 | ||
| 112 | 0 149 0x4 | ||
| 113 | 0 149 0x4 | ||
| 114 | 0 149 0x4 | ||
| 115 | 0 149 0x4 | ||
| 116 | 0 149 0x4>; | ||
| 117 | }; | ||
| 118 | |||
| 119 | i2c0: i2c@fff20000 { | ||
| 120 | #address-cells = <1>; | ||
| 121 | #size-cells = <0>; | ||
| 122 | compatible = "renesas,rmobile-iic"; | ||
| 123 | reg = <0xfff20000 0x425>; | ||
| 124 | interrupt-parent = <&gic>; | ||
| 125 | interrupts = <0 201 0x4 | ||
| 126 | 0 202 0x4 | ||
| 127 | 0 203 0x4 | ||
| 128 | 0 204 0x4>; | ||
| 129 | }; | ||
| 130 | |||
| 131 | i2c1: i2c@e6c20000 { | ||
| 132 | #address-cells = <1>; | ||
| 133 | #size-cells = <0>; | ||
| 134 | compatible = "renesas,rmobile-iic"; | ||
| 135 | reg = <0xe6c20000 0x425>; | ||
| 136 | interrupt-parent = <&gic>; | ||
| 137 | interrupts = <0 70 0x4 | ||
| 138 | 0 71 0x4 | ||
| 139 | 0 72 0x4 | ||
| 140 | 0 73 0x4>; | ||
| 141 | }; | ||
| 21 | }; | 142 | }; |
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index fe5c6f213271..7f146c6bf756 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi | |||
| @@ -48,6 +48,23 @@ | |||
| 48 | <0xf0000100 0x100>; | 48 | <0xf0000100 0x100>; |
| 49 | }; | 49 | }; |
| 50 | 50 | ||
| 51 | irqpin0: irqpin@fe780010 { | ||
| 52 | compatible = "renesas,intc-irqpin"; | ||
| 53 | #interrupt-cells = <2>; | ||
| 54 | interrupt-controller; | ||
| 55 | reg = <0xfe78001c 4>, | ||
| 56 | <0xfe780010 4>, | ||
| 57 | <0xfe780024 4>, | ||
| 58 | <0xfe780044 4>, | ||
| 59 | <0xfe780064 4>; | ||
| 60 | interrupt-parent = <&gic>; | ||
| 61 | interrupts = <0 27 0x4 | ||
| 62 | 0 28 0x4 | ||
| 63 | 0 29 0x4 | ||
| 64 | 0 30 0x4>; | ||
| 65 | sense-bitfield-width = <2>; | ||
| 66 | }; | ||
| 67 | |||
| 51 | i2c0: i2c@0xffc70000 { | 68 | i2c0: i2c@0xffc70000 { |
| 52 | #address-cells = <1>; | 69 | #address-cells = <1>; |
| 53 | #size-cells = <0>; | 70 | #size-cells = <0>; |
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 7a1711027e41..339d9b11721c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi | |||
| @@ -36,12 +36,6 @@ | |||
| 36 | <0 0xf1004000 0 0x2000>, | 36 | <0 0xf1004000 0 0x2000>, |
| 37 | <0 0xf1006000 0 0x2000>; | 37 | <0 0xf1006000 0 0x2000>; |
| 38 | interrupts = <1 9 0xf04>; | 38 | interrupts = <1 9 0xf04>; |
| 39 | |||
| 40 | gic-cpuif@4 { | ||
| 41 | compatible = "arm,gic-cpuif"; | ||
| 42 | cpuif-id = <4>; | ||
| 43 | cpu = <&cpu0>; | ||
| 44 | }; | ||
| 45 | }; | 39 | }; |
| 46 | 40 | ||
| 47 | timer { | 41 | timer { |
diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi new file mode 100644 index 000000000000..527e3193817f --- /dev/null +++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi | |||
| @@ -0,0 +1,173 @@ | |||
| 1 | /* | ||
| 2 | * Samsung S3C2416 pinctrl settings | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | &pinctrl_0 { | ||
| 12 | /* | ||
| 13 | * Pin banks | ||
| 14 | */ | ||
| 15 | |||
| 16 | gpa: gpa { | ||
| 17 | gpio-controller; | ||
| 18 | #gpio-cells = <2>; | ||
| 19 | }; | ||
| 20 | |||
| 21 | gpb: gpb { | ||
| 22 | gpio-controller; | ||
| 23 | #gpio-cells = <2>; | ||
| 24 | }; | ||
| 25 | |||
| 26 | gpc: gpc { | ||
| 27 | gpio-controller; | ||
| 28 | #gpio-cells = <2>; | ||
| 29 | }; | ||
| 30 | |||
| 31 | gpd: gpd { | ||
| 32 | gpio-controller; | ||
| 33 | #gpio-cells = <2>; | ||
| 34 | }; | ||
| 35 | |||
| 36 | gpe: gpe { | ||
| 37 | gpio-controller; | ||
| 38 | #gpio-cells = <2>; | ||
| 39 | }; | ||
| 40 | |||
| 41 | gpf: gpf { | ||
| 42 | gpio-controller; | ||
| 43 | #gpio-cells = <2>; | ||
| 44 | interrupt-controller; | ||
| 45 | #interrupt-cells = <2>; | ||
| 46 | }; | ||
| 47 | |||
| 48 | gpg: gpg { | ||
| 49 | gpio-controller; | ||
| 50 | #gpio-cells = <2>; | ||
| 51 | interrupt-controller; | ||
| 52 | #interrupt-cells = <2>; | ||
| 53 | }; | ||
| 54 | |||
| 55 | gph: gph { | ||
| 56 | gpio-controller; | ||
| 57 | #gpio-cells = <2>; | ||
| 58 | }; | ||
| 59 | |||
| 60 | gpj: gpj { | ||
| 61 | gpio-controller; | ||
| 62 | #gpio-cells = <2>; | ||
| 63 | }; | ||
| 64 | |||
| 65 | gpk: gpk { | ||
| 66 | gpio-controller; | ||
| 67 | #gpio-cells = <2>; | ||
| 68 | }; | ||
| 69 | |||
| 70 | gpl: gpl { | ||
| 71 | gpio-controller; | ||
| 72 | #gpio-cells = <2>; | ||
| 73 | }; | ||
| 74 | |||
| 75 | gpm: gpm { | ||
| 76 | gpio-controller; | ||
| 77 | #gpio-cells = <2>; | ||
| 78 | }; | ||
| 79 | |||
| 80 | /* | ||
| 81 | * Pin groups | ||
| 82 | */ | ||
| 83 | |||
| 84 | uart0_data: uart0-data { | ||
| 85 | samsung,pins = "gph-0", "gph-1"; | ||
| 86 | samsung,pin-function = <2>; | ||
| 87 | }; | ||
| 88 | |||
| 89 | uart0_fctl: uart0-fctl { | ||
| 90 | samsung,pins = "gph-8", "gph-9"; | ||
| 91 | samsung,pin-function = <2>; | ||
| 92 | }; | ||
| 93 | |||
| 94 | uart1_data: uart1-data { | ||
| 95 | samsung,pins = "gph-2", "gph-3"; | ||
| 96 | samsung,pin-function = <2>; | ||
| 97 | }; | ||
| 98 | |||
| 99 | uart1_fctl: uart1-fctl { | ||
| 100 | samsung,pins = "gph-10", "gph-11"; | ||
| 101 | samsung,pin-function = <2>; | ||
| 102 | }; | ||
| 103 | |||
| 104 | uart2_data: uart2-data { | ||
| 105 | samsung,pins = "gph-4", "gph-5"; | ||
| 106 | samsung,pin-function = <2>; | ||
| 107 | }; | ||
| 108 | |||
| 109 | uart2_fctl: uart2-fctl { | ||
| 110 | samsung,pins = "gph-6", "gph-7"; | ||
| 111 | samsung,pin-function = <2>; | ||
| 112 | }; | ||
| 113 | |||
| 114 | uart3_data: uart3-data { | ||
| 115 | samsung,pins = "gph-6", "gph-7"; | ||
| 116 | samsung,pin-function = <2>; | ||
| 117 | }; | ||
| 118 | |||
| 119 | extuart_clk: extuart-clk { | ||
| 120 | samsung,pins = "gph-12"; | ||
| 121 | samsung,pin-function = <2>; | ||
| 122 | }; | ||
| 123 | |||
| 124 | i2c0_bus: i2c0-bus { | ||
| 125 | samsung,pins = "gpe-14", "gpe-15"; | ||
| 126 | samsung,pin-function = <2>; | ||
| 127 | }; | ||
| 128 | |||
| 129 | spi0_bus: spi0-bus { | ||
| 130 | samsung,pins = "gpe-11", "gpe-12", "gpe-13"; | ||
| 131 | samsung,pin-function = <2>; | ||
| 132 | }; | ||
| 133 | |||
| 134 | sd0_clk: sd0-clk { | ||
| 135 | samsung,pins = "gpe-5"; | ||
| 136 | samsung,pin-function = <2>; | ||
| 137 | }; | ||
| 138 | |||
| 139 | sd0_cmd: sd0-cmd { | ||
| 140 | samsung,pins = "gpe-6"; | ||
| 141 | samsung,pin-function = <2>; | ||
| 142 | }; | ||
| 143 | |||
| 144 | sd0_bus1: sd0-bus1 { | ||
| 145 | samsung,pins = "gpe-7"; | ||
| 146 | samsung,pin-function = <2>; | ||
| 147 | }; | ||
| 148 | |||
| 149 | sd0_bus4: sd0-bus4 { | ||
| 150 | samsung,pins = "gpe-8", "gpe-9", "gpe-10"; | ||
| 151 | samsung,pin-function = <2>; | ||
| 152 | }; | ||
| 153 | |||
| 154 | sd1_cmd: sd1-cmd { | ||
| 155 | samsung,pins = "gpl-8"; | ||
| 156 | samsung,pin-function = <2>; | ||
| 157 | }; | ||
| 158 | |||
| 159 | sd1_clk: sd1-clk { | ||
| 160 | samsung,pins = "gpl-9"; | ||
| 161 | samsung,pin-function = <2>; | ||
| 162 | }; | ||
| 163 | |||
| 164 | sd1_bus1: sd1-bus1 { | ||
| 165 | samsung,pins = "gpl-0"; | ||
| 166 | samsung,pin-function = <2>; | ||
| 167 | }; | ||
| 168 | |||
| 169 | sd1_bus4: sd1-bus4 { | ||
| 170 | samsung,pins = "gpl-1", "gpl-2", "gpl-3"; | ||
| 171 | samsung,pin-function = <2>; | ||
| 172 | }; | ||
| 173 | }; | ||
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts new file mode 100644 index 000000000000..ad1dd09c10eb --- /dev/null +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts | |||
| @@ -0,0 +1,72 @@ | |||
| 1 | /* | ||
| 2 | * SAMSUNG SMDK2416 board device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /dts-v1/; | ||
| 12 | /include/ "s3c2416.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "SMDK2416"; | ||
| 16 | compatible = "samsung,s3c2416"; | ||
| 17 | |||
| 18 | memory { | ||
| 19 | reg = <0x30000000 0x4000000>; | ||
| 20 | }; | ||
| 21 | |||
| 22 | serial@50000000 { | ||
| 23 | status = "okay"; | ||
| 24 | pinctrl-names = "default"; | ||
| 25 | pinctrl-0 = <&uart0_data>, <&uart0_fctl>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | serial@50004000 { | ||
| 29 | status = "okay"; | ||
| 30 | pinctrl-names = "default"; | ||
| 31 | pinctrl-0 = <&uart1_data>, <&uart1_fctl>; | ||
| 32 | }; | ||
| 33 | |||
| 34 | serial@50008000 { | ||
| 35 | status = "okay"; | ||
| 36 | pinctrl-names = "default"; | ||
| 37 | pinctrl-0 = <&uart2_data>; | ||
| 38 | }; | ||
| 39 | |||
| 40 | serial@5000C000 { | ||
| 41 | status = "okay"; | ||
| 42 | pinctrl-names = "default"; | ||
| 43 | pinctrl-0 = <&uart3_data>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | watchdog@53000000 { | ||
| 47 | status = "okay"; | ||
| 48 | }; | ||
| 49 | |||
| 50 | rtc@57000000 { | ||
| 51 | status = "okay"; | ||
| 52 | }; | ||
| 53 | |||
| 54 | sdhci@4AC00000 { | ||
| 55 | pinctrl-names = "default"; | ||
| 56 | pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, | ||
| 57 | <&sd0_bus1>, <&sd0_bus4>; | ||
| 58 | bus-width = <4>; | ||
| 59 | cd-gpios = <&gpf 1 0>; | ||
| 60 | cd-inverted; | ||
| 61 | status = "okay"; | ||
| 62 | }; | ||
| 63 | |||
| 64 | sdhci@4A800000 { | ||
| 65 | pinctrl-names = "default"; | ||
| 66 | pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, | ||
| 67 | <&sd1_bus1>, <&sd1_bus4>; | ||
| 68 | bus-width = <4>; | ||
| 69 | broken-cd; | ||
| 70 | status = "okay"; | ||
| 71 | }; | ||
| 72 | }; | ||
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi new file mode 100644 index 000000000000..6809324934a3 --- /dev/null +++ b/arch/arm/boot/dts/s3c2416.dtsi | |||
| @@ -0,0 +1,79 @@ | |||
| 1 | /* | ||
| 2 | * Samsung's S3C2416 SoC device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /include/ "s3c24xx.dtsi" | ||
| 12 | /include/ "s3c2416-pinctrl.dtsi" | ||
| 13 | |||
| 14 | / { | ||
| 15 | model = "Samsung S3C2416 SoC"; | ||
| 16 | compatible = "samsung,s3c2416"; | ||
| 17 | |||
| 18 | cpus { | ||
| 19 | #address-cells = <1>; | ||
| 20 | #size-cells = <0>; | ||
| 21 | |||
| 22 | cpu { | ||
| 23 | compatible = "arm,arm926ejs"; | ||
| 24 | }; | ||
| 25 | }; | ||
| 26 | |||
| 27 | interrupt-controller@4a000000 { | ||
| 28 | compatible = "samsung,s3c2416-irq"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | pinctrl@56000000 { | ||
| 32 | compatible = "samsung,s3c2416-pinctrl"; | ||
| 33 | }; | ||
| 34 | |||
| 35 | serial@50000000 { | ||
| 36 | compatible = "samsung,s3c2440-uart"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | serial@50004000 { | ||
| 40 | compatible = "samsung,s3c2440-uart"; | ||
| 41 | }; | ||
| 42 | |||
| 43 | serial@50008000 { | ||
| 44 | compatible = "samsung,s3c2440-uart"; | ||
| 45 | }; | ||
| 46 | |||
| 47 | serial@5000C000 { | ||
| 48 | compatible = "samsung,s3c2440-uart"; | ||
| 49 | reg = <0x5000C000 0x4000>; | ||
| 50 | interrupts = <1 18 24 4>, <1 18 25 4>; | ||
| 51 | status = "disabled"; | ||
| 52 | }; | ||
| 53 | |||
| 54 | sdhci@4AC00000 { | ||
| 55 | compatible = "samsung,s3c6410-sdhci"; | ||
| 56 | reg = <0x4AC00000 0x100>; | ||
| 57 | interrupts = <0 0 21 3>; | ||
| 58 | status = "disabled"; | ||
| 59 | }; | ||
| 60 | |||
| 61 | sdhci@4A800000 { | ||
| 62 | compatible = "samsung,s3c6410-sdhci"; | ||
| 63 | reg = <0x4A800000 0x100>; | ||
| 64 | interrupts = <0 0 20 3>; | ||
| 65 | status = "disabled"; | ||
| 66 | }; | ||
| 67 | |||
| 68 | watchdog@53000000 { | ||
| 69 | interrupts = <1 9 27 3>; | ||
| 70 | }; | ||
| 71 | |||
| 72 | rtc@57000000 { | ||
| 73 | compatible = "samsung,s3c2416-rtc"; | ||
| 74 | }; | ||
| 75 | |||
| 76 | i2c@54000000 { | ||
| 77 | compatible = "samsung,s3c2440-i2c"; | ||
| 78 | }; | ||
| 79 | }; | ||
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi new file mode 100644 index 000000000000..cab46ff5fb4d --- /dev/null +++ b/arch/arm/boot/dts/s3c24xx.dtsi | |||
| @@ -0,0 +1,92 @@ | |||
| 1 | /* | ||
| 2 | * Samsung's S3C24XX family device tree source | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /include/ "skeleton.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | compatible = "samsung,s3c24xx"; | ||
| 15 | interrupt-parent = <&intc>; | ||
| 16 | |||
| 17 | aliases { | ||
| 18 | pinctrl0 = &pinctrl_0; | ||
| 19 | }; | ||
| 20 | |||
| 21 | intc:interrupt-controller@4a000000 { | ||
| 22 | compatible = "samsung,s3c2410-irq"; | ||
| 23 | reg = <0x4a000000 0x100>; | ||
| 24 | interrupt-controller; | ||
| 25 | #interrupt-cells = <4>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | pinctrl_0: pinctrl@56000000 { | ||
| 29 | reg = <0x56000000 0x1000>; | ||
| 30 | |||
| 31 | wakeup-interrupt-controller { | ||
| 32 | compatible = "samsung,s3c2410-wakeup-eint"; | ||
| 33 | interrupts = <0 0 0 3>, | ||
| 34 | <0 0 1 3>, | ||
| 35 | <0 0 2 3>, | ||
| 36 | <0 0 3 3>, | ||
| 37 | <0 0 4 4>, | ||
| 38 | <0 0 5 4>; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | |||
| 42 | timer@51000000 { | ||
| 43 | compatible = "samsung,s3c2410-pwm"; | ||
| 44 | reg = <0x51000000 0x1000>; | ||
| 45 | interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; | ||
| 46 | #pwm-cells = <4>; | ||
| 47 | }; | ||
| 48 | |||
| 49 | serial@50000000 { | ||
| 50 | compatible = "samsung,s3c2410-uart"; | ||
| 51 | reg = <0x50000000 0x4000>; | ||
| 52 | interrupts = <1 28 0 4>, <1 28 1 4>; | ||
| 53 | status = "disabled"; | ||
| 54 | }; | ||
| 55 | |||
| 56 | serial@50004000 { | ||
| 57 | compatible = "samsung,s3c2410-uart"; | ||
| 58 | reg = <0x50004000 0x4000>; | ||
| 59 | interrupts = <1 23 3 4>, <1 23 4 4>; | ||
| 60 | status = "disabled"; | ||
| 61 | }; | ||
| 62 | |||
| 63 | serial@50008000 { | ||
| 64 | compatible = "samsung,s3c2410-uart"; | ||
| 65 | reg = <0x50008000 0x4000>; | ||
| 66 | interrupts = <1 15 6 4>, <1 15 7 4>; | ||
| 67 | status = "disabled"; | ||
| 68 | }; | ||
| 69 | |||
| 70 | watchdog@53000000 { | ||
| 71 | compatible = "samsung,s3c2410-wdt"; | ||
| 72 | reg = <0x53000000 0x100>; | ||
| 73 | interrupts = <0 0 9 3>; | ||
| 74 | status = "disabled"; | ||
| 75 | }; | ||
| 76 | |||
| 77 | rtc@57000000 { | ||
| 78 | compatible = "samsung,s3c2410-rtc"; | ||
| 79 | reg = <0x57000000 0x100>; | ||
| 80 | interrupts = <0 0 30 3>, <0 0 8 3>; | ||
| 81 | status = "disabled"; | ||
| 82 | }; | ||
| 83 | |||
| 84 | i2c@54000000 { | ||
| 85 | compatible = "samsung,s3c2410-i2c"; | ||
| 86 | reg = <0x54000000 0x100>; | ||
| 87 | interrupts = <0 0 27 3>; | ||
| 88 | #address-cells = <1>; | ||
| 89 | #size-cells = <0>; | ||
| 90 | status = "disabled"; | ||
| 91 | }; | ||
| 92 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index d5922935523f..a1d5e25a6698 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include "skeleton.dtsi" | 11 | #include "skeleton.dtsi" |
| 12 | #include <dt-bindings/dma/at91.h> | ||
| 12 | #include <dt-bindings/pinctrl/at91.h> | 13 | #include <dt-bindings/pinctrl/at91.h> |
| 13 | #include <dt-bindings/interrupt-controller/irq.h> | 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 14 | #include <dt-bindings/gpio/gpio.h> | 15 | #include <dt-bindings/gpio/gpio.h> |
| @@ -38,8 +39,12 @@ | |||
| 38 | ssc1 = &ssc1; | 39 | ssc1 = &ssc1; |
| 39 | }; | 40 | }; |
| 40 | cpus { | 41 | cpus { |
| 42 | #address-cells = <1>; | ||
| 43 | #size-cells = <0>; | ||
| 41 | cpu@0 { | 44 | cpu@0 { |
| 45 | device_type = "cpu"; | ||
| 42 | compatible = "arm,cortex-a5"; | 46 | compatible = "arm,cortex-a5"; |
| 47 | reg = <0x0>; | ||
| 43 | }; | 48 | }; |
| 44 | }; | 49 | }; |
| 45 | 50 | ||
| @@ -63,7 +68,7 @@ | |||
| 63 | compatible = "atmel,hsmci"; | 68 | compatible = "atmel,hsmci"; |
| 64 | reg = <0xf0000000 0x600>; | 69 | reg = <0xf0000000 0x600>; |
| 65 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; | 70 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
| 66 | dmas = <&dma0 2 0>; | 71 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; |
| 67 | dma-names = "rxtx"; | 72 | dma-names = "rxtx"; |
| 68 | pinctrl-names = "default"; | 73 | pinctrl-names = "default"; |
| 69 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; | 74 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; |
| @@ -75,9 +80,12 @@ | |||
| 75 | spi0: spi@f0004000 { | 80 | spi0: spi@f0004000 { |
| 76 | #address-cells = <1>; | 81 | #address-cells = <1>; |
| 77 | #size-cells = <0>; | 82 | #size-cells = <0>; |
| 78 | compatible = "atmel,at91sam9x5-spi"; | 83 | compatible = "atmel,at91rm9200-spi"; |
| 79 | reg = <0xf0004000 0x100>; | 84 | reg = <0xf0004000 0x100>; |
| 80 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; | 85 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; |
| 86 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, | ||
| 87 | <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; | ||
| 88 | dma-names = "tx", "rx"; | ||
| 81 | pinctrl-names = "default"; | 89 | pinctrl-names = "default"; |
| 82 | pinctrl-0 = <&pinctrl_spi0>; | 90 | pinctrl-0 = <&pinctrl_spi0>; |
| 83 | status = "disabled"; | 91 | status = "disabled"; |
| @@ -111,8 +119,8 @@ | |||
| 111 | compatible = "atmel,at91sam9x5-i2c"; | 119 | compatible = "atmel,at91sam9x5-i2c"; |
| 112 | reg = <0xf0014000 0x4000>; | 120 | reg = <0xf0014000 0x4000>; |
| 113 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; | 121 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; |
| 114 | dmas = <&dma0 2 7>, | 122 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, |
| 115 | <&dma0 2 8>; | 123 | <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; |
| 116 | dma-names = "tx", "rx"; | 124 | dma-names = "tx", "rx"; |
| 117 | pinctrl-names = "default"; | 125 | pinctrl-names = "default"; |
| 118 | pinctrl-0 = <&pinctrl_i2c0>; | 126 | pinctrl-0 = <&pinctrl_i2c0>; |
| @@ -125,8 +133,8 @@ | |||
| 125 | compatible = "atmel,at91sam9x5-i2c"; | 133 | compatible = "atmel,at91sam9x5-i2c"; |
| 126 | reg = <0xf0018000 0x4000>; | 134 | reg = <0xf0018000 0x4000>; |
| 127 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; | 135 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; |
| 128 | dmas = <&dma0 2 9>, | 136 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, |
| 129 | <&dma0 2 10>; | 137 | <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; |
| 130 | dma-names = "tx", "rx"; | 138 | dma-names = "tx", "rx"; |
| 131 | pinctrl-names = "default"; | 139 | pinctrl-names = "default"; |
| 132 | pinctrl-0 = <&pinctrl_i2c1>; | 140 | pinctrl-0 = <&pinctrl_i2c1>; |
| @@ -173,7 +181,7 @@ | |||
| 173 | compatible = "atmel,hsmci"; | 181 | compatible = "atmel,hsmci"; |
| 174 | reg = <0xf8000000 0x600>; | 182 | reg = <0xf8000000 0x600>; |
| 175 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; | 183 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; |
| 176 | dmas = <&dma1 2 0>; | 184 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; |
| 177 | dma-names = "rxtx"; | 185 | dma-names = "rxtx"; |
| 178 | pinctrl-names = "default"; | 186 | pinctrl-names = "default"; |
| 179 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; | 187 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; |
| @@ -186,7 +194,7 @@ | |||
| 186 | compatible = "atmel,hsmci"; | 194 | compatible = "atmel,hsmci"; |
| 187 | reg = <0xf8004000 0x600>; | 195 | reg = <0xf8004000 0x600>; |
| 188 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; | 196 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>; |
| 189 | dmas = <&dma1 2 1>; | 197 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>; |
| 190 | dma-names = "rxtx"; | 198 | dma-names = "rxtx"; |
| 191 | pinctrl-names = "default"; | 199 | pinctrl-names = "default"; |
| 192 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; | 200 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; |
| @@ -198,9 +206,12 @@ | |||
| 198 | spi1: spi@f8008000 { | 206 | spi1: spi@f8008000 { |
| 199 | #address-cells = <1>; | 207 | #address-cells = <1>; |
| 200 | #size-cells = <0>; | 208 | #size-cells = <0>; |
| 201 | compatible = "atmel,at91sam9x5-spi"; | 209 | compatible = "atmel,at91rm9200-spi"; |
| 202 | reg = <0xf8008000 0x100>; | 210 | reg = <0xf8008000 0x100>; |
| 203 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; | 211 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; |
| 212 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, | ||
| 213 | <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; | ||
| 214 | dma-names = "tx", "rx"; | ||
| 204 | pinctrl-names = "default"; | 215 | pinctrl-names = "default"; |
| 205 | pinctrl-0 = <&pinctrl_spi1>; | 216 | pinctrl-0 = <&pinctrl_spi1>; |
| 206 | status = "disabled"; | 217 | status = "disabled"; |
| @@ -299,8 +310,8 @@ | |||
| 299 | compatible = "atmel,at91sam9x5-i2c"; | 310 | compatible = "atmel,at91sam9x5-i2c"; |
| 300 | reg = <0xf801c000 0x4000>; | 311 | reg = <0xf801c000 0x4000>; |
| 301 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; | 312 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; |
| 302 | dmas = <&dma1 2 11>, | 313 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, |
| 303 | <&dma1 2 12>; | 314 | <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; |
| 304 | dma-names = "tx", "rx"; | 315 | dma-names = "tx", "rx"; |
| 305 | #address-cells = <1>; | 316 | #address-cells = <1>; |
| 306 | #size-cells = <0>; | 317 | #size-cells = <0>; |
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi index 677fc603f8b3..7bf020ecadf5 100644 --- a/arch/arm/boot/dts/sh7372.dtsi +++ b/arch/arm/boot/dts/sh7372.dtsi | |||
| @@ -14,8 +14,13 @@ | |||
| 14 | compatible = "renesas,sh7372"; | 14 | compatible = "renesas,sh7372"; |
| 15 | 15 | ||
| 16 | cpus { | 16 | cpus { |
| 17 | #address-cells = <1>; | ||
| 18 | #size-cells = <0>; | ||
| 19 | |||
| 17 | cpu@0 { | 20 | cpu@0 { |
| 18 | compatible = "arm,cortex-a8"; | 21 | compatible = "arm,cortex-a8"; |
| 22 | device_type = "cpu"; | ||
| 23 | reg = <0x0>; | ||
| 19 | }; | 24 | }; |
| 20 | }; | 25 | }; |
| 21 | }; | 26 | }; |
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 5972abb55f9c..b6f759e830ed 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | |||
| @@ -18,6 +18,19 @@ | |||
| 18 | model = "KZM-A9-GT"; | 18 | model = "KZM-A9-GT"; |
| 19 | compatible = "renesas,kzm9g-reference", "renesas,sh73a0"; | 19 | compatible = "renesas,kzm9g-reference", "renesas,sh73a0"; |
| 20 | 20 | ||
| 21 | cpus { | ||
| 22 | cpu@0 { | ||
| 23 | cpu0-supply = <&vdd_dvfs>; | ||
| 24 | operating-points = < | ||
| 25 | /* kHz uV */ | ||
| 26 | 1196000 1315000 | ||
| 27 | 598000 1175000 | ||
| 28 | 398667 1065000 | ||
| 29 | >; | ||
| 30 | voltage-tolerance = <1>; /* 1% */ | ||
| 31 | }; | ||
| 32 | }; | ||
| 33 | |||
| 21 | chosen { | 34 | chosen { |
| 22 | bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"; | 35 | bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"; |
| 23 | }; | 36 | }; |
| @@ -59,6 +72,79 @@ | |||
| 59 | }; | 72 | }; |
| 60 | }; | 73 | }; |
| 61 | 74 | ||
| 75 | &i2c0 { | ||
| 76 | as3711@40 { | ||
| 77 | compatible = "ams,as3711"; | ||
| 78 | reg = <0x40>; | ||
| 79 | |||
| 80 | regulators { | ||
| 81 | vdd_dvfs: sd1 { | ||
| 82 | regulator-name = "1.315V CPU"; | ||
| 83 | regulator-min-microvolt = <1050000>; | ||
| 84 | regulator-max-microvolt = <1350000>; | ||
| 85 | regulator-always-on; | ||
| 86 | regulator-boot-on; | ||
| 87 | }; | ||
| 88 | sd2 { | ||
| 89 | regulator-name = "1.8V"; | ||
| 90 | regulator-min-microvolt = <1800000>; | ||
| 91 | regulator-max-microvolt = <1800000>; | ||
| 92 | regulator-always-on; | ||
| 93 | regulator-boot-on; | ||
| 94 | }; | ||
| 95 | sd4 { | ||
| 96 | regulator-name = "1.215V"; | ||
| 97 | regulator-min-microvolt = <1215000>; | ||
| 98 | regulator-max-microvolt = <1235000>; | ||
| 99 | regulator-always-on; | ||
| 100 | regulator-boot-on; | ||
| 101 | }; | ||
| 102 | ldo2 { | ||
| 103 | regulator-name = "2.8V CPU"; | ||
| 104 | regulator-min-microvolt = <2800000>; | ||
| 105 | regulator-max-microvolt = <2800000>; | ||
| 106 | regulator-always-on; | ||
| 107 | regulator-boot-on; | ||
| 108 | }; | ||
| 109 | ldo3 { | ||
| 110 | regulator-name = "3.0V CPU"; | ||
| 111 | regulator-min-microvolt = <3000000>; | ||
| 112 | regulator-max-microvolt = <3000000>; | ||
| 113 | regulator-always-on; | ||
| 114 | regulator-boot-on; | ||
| 115 | }; | ||
| 116 | ldo4 { | ||
| 117 | regulator-name = "2.8V"; | ||
| 118 | regulator-min-microvolt = <2800000>; | ||
| 119 | regulator-max-microvolt = <2800000>; | ||
| 120 | regulator-always-on; | ||
| 121 | regulator-boot-on; | ||
| 122 | }; | ||
| 123 | ldo5 { | ||
| 124 | regulator-name = "2.8V #2"; | ||
| 125 | regulator-min-microvolt = <2800000>; | ||
| 126 | regulator-max-microvolt = <2800000>; | ||
| 127 | regulator-always-on; | ||
| 128 | regulator-boot-on; | ||
| 129 | }; | ||
| 130 | ldo7 { | ||
| 131 | regulator-name = "1.15V CPU"; | ||
| 132 | regulator-min-microvolt = <1150000>; | ||
| 133 | regulator-max-microvolt = <1150000>; | ||
| 134 | regulator-always-on; | ||
| 135 | regulator-boot-on; | ||
| 136 | }; | ||
| 137 | ldo8 { | ||
| 138 | regulator-name = "1.15V CPU #2"; | ||
| 139 | regulator-min-microvolt = <1150000>; | ||
| 140 | regulator-max-microvolt = <1150000>; | ||
| 141 | regulator-always-on; | ||
| 142 | regulator-boot-on; | ||
| 143 | }; | ||
| 144 | }; | ||
| 145 | }; | ||
| 146 | }; | ||
| 147 | |||
| 62 | &mmcif { | 148 | &mmcif { |
| 63 | bus-width = <8>; | 149 | bus-width = <8>; |
| 64 | vmmc-supply = <®_1p8v>; | 150 | vmmc-supply = <®_1p8v>; |
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index ec40bf78289e..b97750256003 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi | |||
| @@ -119,7 +119,7 @@ | |||
| 119 | 0 32 0x4>; | 119 | 0 32 0x4>; |
| 120 | }; | 120 | }; |
| 121 | 121 | ||
| 122 | i2c0: i2c@0xe6820000 { | 122 | i2c0: i2c@e6820000 { |
| 123 | #address-cells = <1>; | 123 | #address-cells = <1>; |
| 124 | #size-cells = <0>; | 124 | #size-cells = <0>; |
| 125 | compatible = "renesas,rmobile-iic"; | 125 | compatible = "renesas,rmobile-iic"; |
| @@ -131,7 +131,7 @@ | |||
| 131 | 0 170 0x4>; | 131 | 0 170 0x4>; |
| 132 | }; | 132 | }; |
| 133 | 133 | ||
| 134 | i2c1: i2c@0xe6822000 { | 134 | i2c1: i2c@e6822000 { |
| 135 | #address-cells = <1>; | 135 | #address-cells = <1>; |
| 136 | #size-cells = <0>; | 136 | #size-cells = <0>; |
| 137 | compatible = "renesas,rmobile-iic"; | 137 | compatible = "renesas,rmobile-iic"; |
| @@ -143,7 +143,7 @@ | |||
| 143 | 0 54 0x4>; | 143 | 0 54 0x4>; |
| 144 | }; | 144 | }; |
| 145 | 145 | ||
| 146 | i2c2: i2c@0xe6824000 { | 146 | i2c2: i2c@e6824000 { |
| 147 | #address-cells = <1>; | 147 | #address-cells = <1>; |
| 148 | #size-cells = <0>; | 148 | #size-cells = <0>; |
| 149 | compatible = "renesas,rmobile-iic"; | 149 | compatible = "renesas,rmobile-iic"; |
| @@ -155,7 +155,7 @@ | |||
| 155 | 0 174 0x4>; | 155 | 0 174 0x4>; |
| 156 | }; | 156 | }; |
| 157 | 157 | ||
| 158 | i2c3: i2c@0xe6826000 { | 158 | i2c3: i2c@e6826000 { |
| 159 | #address-cells = <1>; | 159 | #address-cells = <1>; |
| 160 | #size-cells = <0>; | 160 | #size-cells = <0>; |
| 161 | compatible = "renesas,rmobile-iic"; | 161 | compatible = "renesas,rmobile-iic"; |
| @@ -167,7 +167,7 @@ | |||
| 167 | 0 186 0x4>; | 167 | 0 186 0x4>; |
| 168 | }; | 168 | }; |
| 169 | 169 | ||
| 170 | i2c4: i2c@0xe6828000 { | 170 | i2c4: i2c@e6828000 { |
| 171 | #address-cells = <1>; | 171 | #address-cells = <1>; |
| 172 | #size-cells = <0>; | 172 | #size-cells = <0>; |
| 173 | compatible = "renesas,rmobile-iic"; | 173 | compatible = "renesas,rmobile-iic"; |
| @@ -179,7 +179,7 @@ | |||
| 179 | 0 190 0x4>; | 179 | 0 190 0x4>; |
| 180 | }; | 180 | }; |
| 181 | 181 | ||
| 182 | mmcif: mmcif@0x10010000 { | 182 | mmcif: mmcif@e6bd0000 { |
| 183 | compatible = "renesas,sh-mmcif"; | 183 | compatible = "renesas,sh-mmcif"; |
| 184 | reg = <0xe6bd0000 0x100>; | 184 | reg = <0xe6bd0000 0x100>; |
| 185 | interrupt-parent = <&gic>; | 185 | interrupt-parent = <&gic>; |
| @@ -189,7 +189,7 @@ | |||
| 189 | status = "disabled"; | 189 | status = "disabled"; |
| 190 | }; | 190 | }; |
| 191 | 191 | ||
| 192 | sdhi0: sdhi@0xee100000 { | 192 | sdhi0: sdhi@ee100000 { |
| 193 | compatible = "renesas,r8a7740-sdhi"; | 193 | compatible = "renesas,r8a7740-sdhi"; |
| 194 | reg = <0xee100000 0x100>; | 194 | reg = <0xee100000 0x100>; |
| 195 | interrupt-parent = <&gic>; | 195 | interrupt-parent = <&gic>; |
| @@ -201,7 +201,7 @@ | |||
| 201 | }; | 201 | }; |
| 202 | 202 | ||
| 203 | /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ | 203 | /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ |
| 204 | sdhi1: sdhi@0xee120000 { | 204 | sdhi1: sdhi@ee120000 { |
| 205 | compatible = "renesas,r8a7740-sdhi"; | 205 | compatible = "renesas,r8a7740-sdhi"; |
| 206 | reg = <0xee120000 0x100>; | 206 | reg = <0xee120000 0x100>; |
| 207 | interrupt-parent = <&gic>; | 207 | interrupt-parent = <&gic>; |
| @@ -212,7 +212,7 @@ | |||
| 212 | status = "disabled"; | 212 | status = "disabled"; |
| 213 | }; | 213 | }; |
| 214 | 214 | ||
| 215 | sdhi2: sdhi@0xee140000 { | 215 | sdhi2: sdhi@ee140000 { |
| 216 | compatible = "renesas,r8a7740-sdhi"; | 216 | compatible = "renesas,r8a7740-sdhi"; |
| 217 | reg = <0xee140000 0x100>; | 217 | reg = <0xee140000 0x100>; |
| 218 | interrupt-parent = <&gic>; | 218 | interrupt-parent = <&gic>; |
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index db5db24fd544..fb9dce529da6 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | /dts-v1/; | 12 | /dts-v1/; |
| 13 | /include/ "dbx5x0.dtsi" | 13 | #include "dbx5x0.dtsi" |
| 14 | 14 | ||
| 15 | / { | 15 | / { |
| 16 | model = "Calao Systems Snowball platform with device tree"; | 16 | model = "Calao Systems Snowball platform with device tree"; |
| @@ -82,7 +82,7 @@ | |||
| 82 | }; | 82 | }; |
| 83 | }; | 83 | }; |
| 84 | 84 | ||
| 85 | soc-u9500 { | 85 | soc { |
| 86 | 86 | ||
| 87 | sound { | 87 | sound { |
| 88 | compatible = "stericsson,snd-soc-mop500"; | 88 | compatible = "stericsson,snd-soc-mop500"; |
| @@ -99,40 +99,13 @@ | |||
| 99 | status = "okay"; | 99 | status = "okay"; |
| 100 | }; | 100 | }; |
| 101 | 101 | ||
| 102 | prcmu@80157000 { | ||
| 103 | thermal@801573c0 { | ||
| 104 | num-trips = <4>; | ||
| 105 | |||
| 106 | trip0-temp = <70000>; | ||
| 107 | trip0-type = "active"; | ||
| 108 | trip0-cdev-num = <1>; | ||
| 109 | trip0-cdev-name0 = "thermal-cpufreq-0"; | ||
| 110 | |||
| 111 | trip1-temp = <75000>; | ||
| 112 | trip1-type = "active"; | ||
| 113 | trip1-cdev-num = <1>; | ||
| 114 | trip1-cdev-name0 = "thermal-cpufreq-0"; | ||
| 115 | |||
| 116 | trip2-temp = <80000>; | ||
| 117 | trip2-type = "active"; | ||
| 118 | trip2-cdev-num = <1>; | ||
| 119 | trip2-cdev-name0 = "thermal-cpufreq-0"; | ||
| 120 | |||
| 121 | trip3-temp = <85000>; | ||
| 122 | trip3-type = "critical"; | ||
| 123 | trip3-cdev-num = <0>; | ||
| 124 | |||
| 125 | status = "okay"; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 | |||
| 129 | external-bus@50000000 { | 102 | external-bus@50000000 { |
| 130 | status = "okay"; | 103 | status = "okay"; |
| 131 | 104 | ||
| 132 | ethernet@0 { | 105 | ethernet@0 { |
| 133 | compatible = "smsc,lan9115"; | 106 | compatible = "smsc,lan9115"; |
| 134 | reg = <0 0x10000>; | 107 | reg = <0 0x10000>; |
| 135 | interrupts = <12 0x1>; | 108 | interrupts = <12 IRQ_TYPE_EDGE_RISING>; |
| 136 | interrupt-parent = <&gpio4>; | 109 | interrupt-parent = <&gpio4>; |
| 137 | vdd33a-supply = <&en_3v3_reg>; | 110 | vdd33a-supply = <&en_3v3_reg>; |
| 138 | vddvario-supply = <&db8500_vape_reg>; | 111 | vddvario-supply = <&db8500_vape_reg>; |
| @@ -146,13 +119,21 @@ | |||
| 146 | }; | 119 | }; |
| 147 | }; | 120 | }; |
| 148 | 121 | ||
| 122 | vmmci: regulator-gpio { | ||
| 123 | gpios = <&gpio6 25 0x4>; | ||
| 124 | enable-gpio = <&gpio7 4 0x4>; | ||
| 125 | |||
| 126 | status = "okay"; | ||
| 127 | }; | ||
| 128 | |||
| 149 | // External Micro SD slot | 129 | // External Micro SD slot |
| 150 | sdi0_per1@80126000 { | 130 | sdi0_per1@80126000 { |
| 151 | arm,primecell-periphid = <0x10480180>; | 131 | arm,primecell-periphid = <0x10480180>; |
| 152 | max-frequency = <50000000>; | 132 | max-frequency = <100000000>; |
| 153 | bus-width = <4>; | 133 | bus-width = <4>; |
| 154 | mmc-cap-mmc-highspeed; | 134 | mmc-cap-mmc-highspeed; |
| 155 | vmmc-supply = <&ab8500_ldo_aux3_reg>; | 135 | vmmc-supply = <&ab8500_ldo_aux3_reg>; |
| 136 | vqmmc-supply = <&vmmci>; | ||
| 156 | 137 | ||
| 157 | cd-gpios = <&gpio6 26 0x4>; // 218 | 138 | cd-gpios = <&gpio6 26 0x4>; // 218 |
| 158 | cd-inverted; | 139 | cd-inverted; |
| @@ -163,7 +144,7 @@ | |||
| 163 | // On-board eMMC | 144 | // On-board eMMC |
| 164 | sdi4_per2@80114000 { | 145 | sdi4_per2@80114000 { |
| 165 | arm,primecell-periphid = <0x10480180>; | 146 | arm,primecell-periphid = <0x10480180>; |
| 166 | max-frequency = <50000000>; | 147 | max-frequency = <100000000>; |
| 167 | bus-width = <8>; | 148 | bus-width = <8>; |
| 168 | mmc-cap-mmc-highspeed; | 149 | mmc-cap-mmc-highspeed; |
| 169 | vmmc-supply = <&ab8500_ldo_aux2_reg>; | 150 | vmmc-supply = <&ab8500_ldo_aux2_reg>; |
| @@ -197,15 +178,15 @@ | |||
| 197 | }; | 178 | }; |
| 198 | 179 | ||
| 199 | i2c@80128000 { | 180 | i2c@80128000 { |
| 200 | lp5521@0x33 { | 181 | lp5521@33 { |
| 201 | // compatible = "lp5521"; | 182 | // compatible = "lp5521"; |
| 202 | reg = <0x33>; | 183 | reg = <0x33>; |
| 203 | }; | 184 | }; |
| 204 | lp5521@0x34 { | 185 | lp5521@34 { |
| 205 | // compatible = "lp5521"; | 186 | // compatible = "lp5521"; |
| 206 | reg = <0x34>; | 187 | reg = <0x34>; |
| 207 | }; | 188 | }; |
| 208 | bh1780@0x29 { | 189 | bh1780@29 { |
| 209 | // compatible = "rohm,bh1780gli"; | 190 | // compatible = "rohm,bh1780gli"; |
| 210 | reg = <0x33>; | 191 | reg = <0x33>; |
| 211 | }; | 192 | }; |
| @@ -298,6 +279,31 @@ | |||
| 298 | }; | 279 | }; |
| 299 | }; | 280 | }; |
| 300 | 281 | ||
| 282 | thermal@801573c0 { | ||
| 283 | num-trips = <4>; | ||
| 284 | |||
| 285 | trip0-temp = <70000>; | ||
| 286 | trip0-type = "active"; | ||
| 287 | trip0-cdev-num = <1>; | ||
| 288 | trip0-cdev-name0 = "thermal-cpufreq-0"; | ||
| 289 | |||
| 290 | trip1-temp = <75000>; | ||
| 291 | trip1-type = "active"; | ||
| 292 | trip1-cdev-num = <1>; | ||
| 293 | trip1-cdev-name0 = "thermal-cpufreq-0"; | ||
| 294 | |||
| 295 | trip2-temp = <80000>; | ||
| 296 | trip2-type = "active"; | ||
| 297 | trip2-cdev-num = <1>; | ||
| 298 | trip2-cdev-name0 = "thermal-cpufreq-0"; | ||
| 299 | |||
| 300 | trip3-temp = <85000>; | ||
| 301 | trip3-type = "critical"; | ||
| 302 | trip3-cdev-num = <0>; | ||
| 303 | |||
| 304 | status = "okay"; | ||
| 305 | }; | ||
| 306 | |||
| 301 | ab8500 { | 307 | ab8500 { |
| 302 | ab8500-gpio { | 308 | ab8500-gpio { |
| 303 | compatible = "stericsson,ab8500-gpio"; | 309 | compatible = "stericsson,ab8500-gpio"; |
| @@ -316,7 +322,7 @@ | |||
| 316 | regulator-name = "V-MMC-SD"; | 322 | regulator-name = "V-MMC-SD"; |
| 317 | }; | 323 | }; |
| 318 | 324 | ||
| 319 | ab8500_ldo_initcore_reg: ab8500_ldo_initcore { | 325 | ab8500_ldo_intcore_reg: ab8500_ldo_intcore { |
| 320 | regulator-name = "V-INTCORE"; | 326 | regulator-name = "V-INTCORE"; |
| 321 | }; | 327 | }; |
| 322 | 328 | ||
| @@ -336,7 +342,7 @@ | |||
| 336 | regulator-name = "V-AMIC1"; | 342 | regulator-name = "V-AMIC1"; |
| 337 | }; | 343 | }; |
| 338 | 344 | ||
| 339 | ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { | 345 | ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { |
| 340 | regulator-name = "V-AMIC2"; | 346 | regulator-name = "V-AMIC2"; |
| 341 | }; | 347 | }; |
| 342 | 348 | ||
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 16a6e13e08b4..bee62a2cf6d6 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | 23 | ||
| 24 | aliases { | 24 | aliases { |
| 25 | ethernet0 = &gmac0; | 25 | ethernet0 = &gmac0; |
| 26 | ethernet1 = &gmac1; | ||
| 26 | serial0 = &uart0; | 27 | serial0 = &uart0; |
| 27 | serial1 = &uart1; | 28 | serial1 = &uart1; |
| 28 | timer0 = &timer0; | 29 | timer0 = &timer0; |
| @@ -94,6 +95,12 @@ | |||
| 94 | compatible = "fixed-clock"; | 95 | compatible = "fixed-clock"; |
| 95 | }; | 96 | }; |
| 96 | 97 | ||
| 98 | f2s_periph_ref_clk: f2s_periph_ref_clk { | ||
| 99 | #clock-cells = <0>; | ||
| 100 | compatible = "fixed-clock"; | ||
| 101 | clock-frequency = <10000000>; | ||
| 102 | }; | ||
| 103 | |||
| 97 | main_pll: main_pll { | 104 | main_pll: main_pll { |
| 98 | #address-cells = <1>; | 105 | #address-cells = <1>; |
| 99 | #size-cells = <0>; | 106 | #size-cells = <0>; |
| @@ -235,16 +242,222 @@ | |||
| 235 | reg = <0xD4>; | 242 | reg = <0xD4>; |
| 236 | }; | 243 | }; |
| 237 | }; | 244 | }; |
| 245 | |||
| 246 | mpu_periph_clk: mpu_periph_clk { | ||
| 247 | #clock-cells = <0>; | ||
| 248 | compatible = "altr,socfpga-gate-clk"; | ||
| 249 | clocks = <&mpuclk>; | ||
| 250 | fixed-divider = <4>; | ||
| 251 | }; | ||
| 252 | |||
| 253 | mpu_l2_ram_clk: mpu_l2_ram_clk { | ||
| 254 | #clock-cells = <0>; | ||
| 255 | compatible = "altr,socfpga-gate-clk"; | ||
| 256 | clocks = <&mpuclk>; | ||
| 257 | fixed-divider = <2>; | ||
| 258 | }; | ||
| 259 | |||
| 260 | l4_main_clk: l4_main_clk { | ||
| 261 | #clock-cells = <0>; | ||
| 262 | compatible = "altr,socfpga-gate-clk"; | ||
| 263 | clocks = <&mainclk>; | ||
| 264 | clk-gate = <0x60 0>; | ||
| 265 | }; | ||
| 266 | |||
| 267 | l3_main_clk: l3_main_clk { | ||
| 268 | #clock-cells = <0>; | ||
| 269 | compatible = "altr,socfpga-gate-clk"; | ||
| 270 | clocks = <&mainclk>; | ||
| 271 | }; | ||
| 272 | |||
| 273 | l3_mp_clk: l3_mp_clk { | ||
| 274 | #clock-cells = <0>; | ||
| 275 | compatible = "altr,socfpga-gate-clk"; | ||
| 276 | clocks = <&mainclk>; | ||
| 277 | div-reg = <0x64 0 2>; | ||
| 278 | clk-gate = <0x60 1>; | ||
| 279 | }; | ||
| 280 | |||
| 281 | l3_sp_clk: l3_sp_clk { | ||
| 282 | #clock-cells = <0>; | ||
| 283 | compatible = "altr,socfpga-gate-clk"; | ||
| 284 | clocks = <&mainclk>; | ||
| 285 | div-reg = <0x64 2 2>; | ||
| 286 | }; | ||
| 287 | |||
| 288 | l4_mp_clk: l4_mp_clk { | ||
| 289 | #clock-cells = <0>; | ||
| 290 | compatible = "altr,socfpga-gate-clk"; | ||
| 291 | clocks = <&mainclk>, <&per_base_clk>; | ||
| 292 | div-reg = <0x64 4 3>; | ||
| 293 | clk-gate = <0x60 2>; | ||
| 294 | }; | ||
| 295 | |||
| 296 | l4_sp_clk: l4_sp_clk { | ||
| 297 | #clock-cells = <0>; | ||
| 298 | compatible = "altr,socfpga-gate-clk"; | ||
| 299 | clocks = <&mainclk>, <&per_base_clk>; | ||
| 300 | div-reg = <0x64 7 3>; | ||
| 301 | clk-gate = <0x60 3>; | ||
| 302 | }; | ||
| 303 | |||
| 304 | dbg_at_clk: dbg_at_clk { | ||
| 305 | #clock-cells = <0>; | ||
| 306 | compatible = "altr,socfpga-gate-clk"; | ||
| 307 | clocks = <&dbg_base_clk>; | ||
| 308 | div-reg = <0x68 0 2>; | ||
| 309 | clk-gate = <0x60 4>; | ||
| 310 | }; | ||
| 311 | |||
| 312 | dbg_clk: dbg_clk { | ||
| 313 | #clock-cells = <0>; | ||
| 314 | compatible = "altr,socfpga-gate-clk"; | ||
| 315 | clocks = <&dbg_base_clk>; | ||
| 316 | div-reg = <0x68 2 2>; | ||
| 317 | clk-gate = <0x60 5>; | ||
| 318 | }; | ||
| 319 | |||
| 320 | dbg_trace_clk: dbg_trace_clk { | ||
| 321 | #clock-cells = <0>; | ||
| 322 | compatible = "altr,socfpga-gate-clk"; | ||
| 323 | clocks = <&dbg_base_clk>; | ||
| 324 | div-reg = <0x6C 0 3>; | ||
| 325 | clk-gate = <0x60 6>; | ||
| 326 | }; | ||
| 327 | |||
| 328 | dbg_timer_clk: dbg_timer_clk { | ||
| 329 | #clock-cells = <0>; | ||
| 330 | compatible = "altr,socfpga-gate-clk"; | ||
| 331 | clocks = <&dbg_base_clk>; | ||
| 332 | clk-gate = <0x60 7>; | ||
| 333 | }; | ||
| 334 | |||
| 335 | cfg_clk: cfg_clk { | ||
| 336 | #clock-cells = <0>; | ||
| 337 | compatible = "altr,socfpga-gate-clk"; | ||
| 338 | clocks = <&cfg_s2f_usr0_clk>; | ||
| 339 | clk-gate = <0x60 8>; | ||
| 340 | }; | ||
| 341 | |||
| 342 | s2f_user0_clk: s2f_user0_clk { | ||
| 343 | #clock-cells = <0>; | ||
| 344 | compatible = "altr,socfpga-gate-clk"; | ||
| 345 | clocks = <&cfg_s2f_usr0_clk>; | ||
| 346 | clk-gate = <0x60 9>; | ||
| 347 | }; | ||
| 348 | |||
| 349 | emac_0_clk: emac_0_clk { | ||
| 350 | #clock-cells = <0>; | ||
| 351 | compatible = "altr,socfpga-gate-clk"; | ||
| 352 | clocks = <&emac0_clk>; | ||
| 353 | clk-gate = <0xa0 0>; | ||
| 354 | }; | ||
| 355 | |||
| 356 | emac_1_clk: emac_1_clk { | ||
| 357 | #clock-cells = <0>; | ||
| 358 | compatible = "altr,socfpga-gate-clk"; | ||
| 359 | clocks = <&emac1_clk>; | ||
| 360 | clk-gate = <0xa0 1>; | ||
| 361 | }; | ||
| 362 | |||
| 363 | usb_mp_clk: usb_mp_clk { | ||
| 364 | #clock-cells = <0>; | ||
| 365 | compatible = "altr,socfpga-gate-clk"; | ||
| 366 | clocks = <&per_base_clk>; | ||
| 367 | clk-gate = <0xa0 2>; | ||
| 368 | div-reg = <0xa4 0 3>; | ||
| 369 | }; | ||
| 370 | |||
| 371 | spi_m_clk: spi_m_clk { | ||
| 372 | #clock-cells = <0>; | ||
| 373 | compatible = "altr,socfpga-gate-clk"; | ||
| 374 | clocks = <&per_base_clk>; | ||
| 375 | clk-gate = <0xa0 3>; | ||
| 376 | div-reg = <0xa4 3 3>; | ||
| 377 | }; | ||
| 378 | |||
| 379 | can0_clk: can0_clk { | ||
| 380 | #clock-cells = <0>; | ||
| 381 | compatible = "altr,socfpga-gate-clk"; | ||
| 382 | clocks = <&per_base_clk>; | ||
| 383 | clk-gate = <0xa0 4>; | ||
| 384 | div-reg = <0xa4 6 3>; | ||
| 385 | }; | ||
| 386 | |||
| 387 | can1_clk: can1_clk { | ||
| 388 | #clock-cells = <0>; | ||
| 389 | compatible = "altr,socfpga-gate-clk"; | ||
| 390 | clocks = <&per_base_clk>; | ||
| 391 | clk-gate = <0xa0 5>; | ||
| 392 | div-reg = <0xa4 9 3>; | ||
| 393 | }; | ||
| 394 | |||
| 395 | gpio_db_clk: gpio_db_clk { | ||
| 396 | #clock-cells = <0>; | ||
| 397 | compatible = "altr,socfpga-gate-clk"; | ||
| 398 | clocks = <&per_base_clk>; | ||
| 399 | clk-gate = <0xa0 6>; | ||
| 400 | div-reg = <0xa8 0 24>; | ||
| 401 | }; | ||
| 402 | |||
| 403 | s2f_user1_clk: s2f_user1_clk { | ||
| 404 | #clock-cells = <0>; | ||
| 405 | compatible = "altr,socfpga-gate-clk"; | ||
| 406 | clocks = <&s2f_usr1_clk>; | ||
| 407 | clk-gate = <0xa0 7>; | ||
| 408 | }; | ||
| 409 | |||
| 410 | sdmmc_clk: sdmmc_clk { | ||
| 411 | #clock-cells = <0>; | ||
| 412 | compatible = "altr,socfpga-gate-clk"; | ||
| 413 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | ||
| 414 | clk-gate = <0xa0 8>; | ||
| 415 | }; | ||
| 416 | |||
| 417 | nand_x_clk: nand_x_clk { | ||
| 418 | #clock-cells = <0>; | ||
| 419 | compatible = "altr,socfpga-gate-clk"; | ||
| 420 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | ||
| 421 | clk-gate = <0xa0 9>; | ||
| 422 | }; | ||
| 423 | |||
| 424 | nand_clk: nand_clk { | ||
| 425 | #clock-cells = <0>; | ||
| 426 | compatible = "altr,socfpga-gate-clk"; | ||
| 427 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | ||
| 428 | clk-gate = <0xa0 10>; | ||
| 429 | fixed-divider = <4>; | ||
| 430 | }; | ||
| 431 | |||
| 432 | qspi_clk: qspi_clk { | ||
| 433 | #clock-cells = <0>; | ||
| 434 | compatible = "altr,socfpga-gate-clk"; | ||
| 435 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; | ||
| 436 | clk-gate = <0xa0 11>; | ||
| 437 | }; | ||
| 238 | }; | 438 | }; |
| 239 | }; | 439 | }; |
| 240 | 440 | ||
| 241 | gmac0: stmmac@ff700000 { | 441 | gmac0: ethernet@ff700000 { |
| 242 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | 442 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
| 243 | reg = <0xff700000 0x2000>; | 443 | reg = <0xff700000 0x2000>; |
| 244 | interrupts = <0 115 4>; | 444 | interrupts = <0 115 4>; |
| 245 | interrupt-names = "macirq"; | 445 | interrupt-names = "macirq"; |
| 246 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | 446 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ |
| 247 | phy-mode = "gmii"; | 447 | clocks = <&emac0_clk>; |
| 448 | clock-names = "stmmaceth"; | ||
| 449 | status = "disabled"; | ||
| 450 | }; | ||
| 451 | |||
| 452 | gmac1: ethernet@ff702000 { | ||
| 453 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | ||
| 454 | reg = <0xff702000 0x2000>; | ||
| 455 | interrupts = <0 120 4>; | ||
| 456 | interrupt-names = "macirq"; | ||
| 457 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | ||
| 458 | clocks = <&emac1_clk>; | ||
| 459 | clock-names = "stmmaceth"; | ||
| 460 | status = "disabled"; | ||
| 248 | }; | 461 | }; |
| 249 | 462 | ||
| 250 | L2: l2-cache@fffef000 { | 463 | L2: l2-cache@fffef000 { |
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts index 2495958f1016..973999d2c697 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5.dts | |||
| @@ -32,6 +32,13 @@ | |||
| 32 | reg = <0x0 0x40000000>; /* 1GB */ | 32 | reg = <0x0 0x40000000>; /* 1GB */ |
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | aliases { | ||
| 36 | /* this allow the ethaddr uboot environmnet variable contents | ||
| 37 | * to be added to the gmac1 device tree blob. | ||
| 38 | */ | ||
| 39 | ethernet0 = &gmac1; | ||
| 40 | }; | ||
| 41 | |||
| 35 | soc { | 42 | soc { |
| 36 | clkmgr@ffd04000 { | 43 | clkmgr@ffd04000 { |
| 37 | clocks { | 44 | clocks { |
| @@ -41,6 +48,12 @@ | |||
| 41 | }; | 48 | }; |
| 42 | }; | 49 | }; |
| 43 | 50 | ||
| 51 | ethernet@ff702000 { | ||
| 52 | phy-mode = "rgmii"; | ||
| 53 | phy-addr = <0xffffffff>; /* probe for phy addr */ | ||
| 54 | status = "okay"; | ||
| 55 | }; | ||
| 56 | |||
| 44 | timer0@ffc08000 { | 57 | timer0@ffc08000 { |
| 45 | clock-frequency = <100000000>; | 58 | clock-frequency = <100000000>; |
| 46 | }; | 59 | }; |
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 0bf035d607f0..d1ec0cab2dee 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts | |||
| @@ -41,6 +41,11 @@ | |||
| 41 | }; | 41 | }; |
| 42 | }; | 42 | }; |
| 43 | 43 | ||
| 44 | ethernet@ff700000 { | ||
| 45 | phy-mode = "gmii"; | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 44 | timer0@ffc08000 { | 49 | timer0@ffc08000 { |
| 45 | clock-frequency = <7000000>; | 50 | clock-frequency = <7000000>; |
| 46 | }; | 51 | }; |
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index 45597fd91050..4382547df58a 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi | |||
| @@ -22,12 +22,14 @@ | |||
| 22 | 22 | ||
| 23 | cpu@0 { | 23 | cpu@0 { |
| 24 | compatible = "arm,cortex-a9"; | 24 | compatible = "arm,cortex-a9"; |
| 25 | device_type = "cpu"; | ||
| 25 | reg = <0>; | 26 | reg = <0>; |
| 26 | next-level-cache = <&L2>; | 27 | next-level-cache = <&L2>; |
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | cpu@1 { | 30 | cpu@1 { |
| 30 | compatible = "arm,cortex-a9"; | 31 | compatible = "arm,cortex-a9"; |
| 32 | device_type = "cpu"; | ||
| 31 | reg = <1>; | 33 | reg = <1>; |
| 32 | next-level-cache = <&L2>; | 34 | next-level-cache = <&L2>; |
| 33 | }; | 35 | }; |
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi index c2a852d43c48..f0e3fcf8e323 100644 --- a/arch/arm/boot/dts/spear3xx.dtsi +++ b/arch/arm/boot/dts/spear3xx.dtsi | |||
| @@ -17,8 +17,12 @@ | |||
| 17 | interrupt-parent = <&vic>; | 17 | interrupt-parent = <&vic>; |
| 18 | 18 | ||
| 19 | cpus { | 19 | cpus { |
| 20 | cpu@0 { | 20 | #address-cells = <0>; |
| 21 | compatible = "arm,arm926ejs"; | 21 | #size-cells = <0>; |
| 22 | |||
| 23 | cpu { | ||
| 24 | compatible = "arm,arm926ej-s"; | ||
| 25 | device_type = "cpu"; | ||
| 22 | }; | 26 | }; |
| 23 | }; | 27 | }; |
| 24 | 28 | ||
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index 19f99dc4115e..9f60a7b6a42b 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi | |||
| @@ -15,8 +15,12 @@ | |||
| 15 | compatible = "st,spear600"; | 15 | compatible = "st,spear600"; |
| 16 | 16 | ||
| 17 | cpus { | 17 | cpus { |
| 18 | cpu@0 { | 18 | #address-cells = <0>; |
| 19 | compatible = "arm,arm926ejs"; | 19 | #size-cells = <0>; |
| 20 | |||
| 21 | cpu { | ||
| 22 | compatible = "arm,arm926ej-s"; | ||
| 23 | device_type = "cpu"; | ||
| 20 | }; | 24 | }; |
| 21 | }; | 25 | }; |
| 22 | 26 | ||
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts index 6f82d9368948..16c3888b7b15 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts | |||
| @@ -22,6 +22,49 @@ | |||
| 22 | }; | 22 | }; |
| 23 | }; | 23 | }; |
| 24 | 24 | ||
| 25 | src@101e0000 { | ||
| 26 | /* These chrystal drivers are not used on this board */ | ||
| 27 | disable-sxtalo; | ||
| 28 | disable-mxtalo; | ||
| 29 | }; | ||
| 30 | |||
| 31 | pinctrl { | ||
| 32 | /* Hog CD pins */ | ||
| 33 | pinctrl-names = "default"; | ||
| 34 | pinctrl-0 = <&cd_default_mode>; | ||
| 35 | |||
| 36 | mmcsd-cd { | ||
| 37 | cd_default_mode: cd_default { | ||
| 38 | cd_default_cfg1 { | ||
| 39 | /* CD input GPIO */ | ||
| 40 | ste,pins = "GPIO111_H21"; | ||
| 41 | ste,input = <0>; | ||
| 42 | }; | ||
| 43 | cd_default_cfg2 { | ||
| 44 | /* CD GPIO biasing */ | ||
| 45 | ste,pins = "GPIO112_J21"; | ||
| 46 | ste,output = <0>; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | user-led { | ||
| 51 | user_led_default_mode: user_led_default { | ||
| 52 | user_led_default_cfg { | ||
| 53 | ste,pins = "GPIO2_C5"; | ||
| 54 | ste,output = <1>; | ||
| 55 | }; | ||
| 56 | }; | ||
| 57 | }; | ||
| 58 | user-button { | ||
| 59 | user_button_default_mode: user_button_default { | ||
| 60 | user_button_default_cfg { | ||
| 61 | ste,pins = "GPIO3_A4"; | ||
| 62 | ste,input = <0>; | ||
| 63 | }; | ||
| 64 | }; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | |||
| 25 | /* Custom board node with GPIO pins to active etc */ | 68 | /* Custom board node with GPIO pins to active etc */ |
| 26 | usb-s8815 { | 69 | usb-s8815 { |
| 27 | /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */ | 70 | /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */ |
| @@ -33,4 +76,30 @@ | |||
| 33 | gpios = <&gpio3 16 0x1>; | 76 | gpios = <&gpio3 16 0x1>; |
| 34 | }; | 77 | }; |
| 35 | }; | 78 | }; |
| 79 | |||
| 80 | /* The user LED on the board is set up to be used for heartbeat */ | ||
| 81 | leds { | ||
| 82 | compatible = "gpio-leds"; | ||
| 83 | user-led { | ||
| 84 | label = "user_led"; | ||
| 85 | gpios = <&gpio0 2 0x1>; | ||
| 86 | default-state = "off"; | ||
| 87 | linux,default-trigger = "heartbeat"; | ||
| 88 | pinctrl-names = "default"; | ||
| 89 | pinctrl-0 = <&user_led_default_mode>; | ||
| 90 | }; | ||
| 91 | }; | ||
| 92 | |||
| 93 | /* User key mapped in as "escape" */ | ||
| 94 | gpio-keys { | ||
| 95 | compatible = "gpio-keys"; | ||
| 96 | user-button { | ||
| 97 | label = "user_button"; | ||
| 98 | gpios = <&gpio0 3 0x1>; | ||
| 99 | linux,code = <1>; /* KEY_ESC */ | ||
| 100 | gpio-key,wakeup; | ||
| 101 | pinctrl-names = "default"; | ||
| 102 | pinctrl-0 = <&user_button_default_mode>; | ||
| 103 | }; | ||
| 104 | }; | ||
| 36 | }; | 105 | }; |
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 4a4aab395141..a3acfa7b3dc9 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | |||
| @@ -21,18 +21,23 @@ | |||
| 21 | cache-level = <2>; | 21 | cache-level = <2>; |
| 22 | }; | 22 | }; |
| 23 | 23 | ||
| 24 | mtu0 { | 24 | mtu0: mtu@101e2000 { |
| 25 | /* Nomadik system timer */ | 25 | /* Nomadik system timer */ |
| 26 | compatible = "st,nomadik-mtu"; | ||
| 26 | reg = <0x101e2000 0x1000>; | 27 | reg = <0x101e2000 0x1000>; |
| 27 | interrupt-parent = <&vica>; | 28 | interrupt-parent = <&vica>; |
| 28 | interrupts = <4>; | 29 | interrupts = <4>; |
| 30 | clocks = <&timclk>, <&pclk>; | ||
| 31 | clock-names = "timclk", "apb_pclk"; | ||
| 29 | }; | 32 | }; |
| 30 | 33 | ||
| 31 | mtu1 { | 34 | mtu1: mtu@101e3000 { |
| 32 | /* Secondary timer */ | 35 | /* Secondary timer */ |
| 33 | reg = <0x101e3000 0x1000>; | 36 | reg = <0x101e3000 0x1000>; |
| 34 | interrupt-parent = <&vica>; | 37 | interrupt-parent = <&vica>; |
| 35 | interrupts = <5>; | 38 | interrupts = <5>; |
| 39 | clocks = <&timclk>, <&pclk>; | ||
| 40 | clock-names = "timclk", "apb_pclk"; | ||
| 36 | }; | 41 | }; |
| 37 | 42 | ||
| 38 | gpio0: gpio@101e4000 { | 43 | gpio0: gpio@101e4000 { |
| @@ -45,6 +50,7 @@ | |||
| 45 | gpio-controller; | 50 | gpio-controller; |
| 46 | #gpio-cells = <2>; | 51 | #gpio-cells = <2>; |
| 47 | gpio-bank = <0>; | 52 | gpio-bank = <0>; |
| 53 | clocks = <&pclk>; | ||
| 48 | }; | 54 | }; |
| 49 | 55 | ||
| 50 | gpio1: gpio@101e5000 { | 56 | gpio1: gpio@101e5000 { |
| @@ -57,6 +63,7 @@ | |||
| 57 | gpio-controller; | 63 | gpio-controller; |
| 58 | #gpio-cells = <2>; | 64 | #gpio-cells = <2>; |
| 59 | gpio-bank = <1>; | 65 | gpio-bank = <1>; |
| 66 | clocks = <&pclk>; | ||
| 60 | }; | 67 | }; |
| 61 | 68 | ||
| 62 | gpio2: gpio@101e6000 { | 69 | gpio2: gpio@101e6000 { |
| @@ -69,6 +76,7 @@ | |||
| 69 | gpio-controller; | 76 | gpio-controller; |
| 70 | #gpio-cells = <2>; | 77 | #gpio-cells = <2>; |
| 71 | gpio-bank = <2>; | 78 | gpio-bank = <2>; |
| 79 | clocks = <&pclk>; | ||
| 72 | }; | 80 | }; |
| 73 | 81 | ||
| 74 | gpio3: gpio@101e7000 { | 82 | gpio3: gpio@101e7000 { |
| @@ -81,10 +89,544 @@ | |||
| 81 | gpio-controller; | 89 | gpio-controller; |
| 82 | #gpio-cells = <2>; | 90 | #gpio-cells = <2>; |
| 83 | gpio-bank = <3>; | 91 | gpio-bank = <3>; |
| 92 | clocks = <&pclk>; | ||
| 84 | }; | 93 | }; |
| 85 | 94 | ||
| 86 | pinctrl { | 95 | pinctrl { |
| 87 | compatible = "stericsson,nmk-pinctrl-stn8815"; | 96 | compatible = "stericsson,stn8815-pinctrl"; |
| 97 | /* Pin configurations */ | ||
| 98 | uart0 { | ||
| 99 | uart0_default_mux: uart0_mux { | ||
| 100 | u0_default_mux { | ||
| 101 | ste,function = "u0"; | ||
| 102 | ste,pins = "u0_a_1"; | ||
| 103 | }; | ||
| 104 | }; | ||
| 105 | }; | ||
| 106 | uart1 { | ||
| 107 | uart1_default_mux: uart1_mux { | ||
| 108 | u1_default_mux { | ||
| 109 | ste,function = "u1"; | ||
| 110 | ste,pins = "u1_a_1"; | ||
| 111 | }; | ||
| 112 | }; | ||
| 113 | }; | ||
| 114 | mmcsd { | ||
| 115 | mmcsd_default_mux: mmcsd_mux { | ||
| 116 | mmcsd_default_mux { | ||
| 117 | ste,function = "mmcsd"; | ||
| 118 | ste,pins = "mmcsd_a_1"; | ||
| 119 | }; | ||
| 120 | }; | ||
| 121 | mmcsd_default_mode: mmcsd_default { | ||
| 122 | mmcsd_default_cfg1 { | ||
| 123 | /* MCCLK */ | ||
| 124 | ste,pins = "GPIO8_B10"; | ||
| 125 | ste,output = <0>; | ||
| 126 | }; | ||
| 127 | mmcsd_default_cfg2 { | ||
| 128 | /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */ | ||
| 129 | ste,pins = "GPIO10_C11", "GPIO15_A12", | ||
| 130 | "GPIO16_C13"; | ||
| 131 | ste,output = <1>; | ||
| 132 | }; | ||
| 133 | mmcsd_default_cfg3 { | ||
| 134 | /* MCCMD, MCDAT3-0, MCMSFBCLK */ | ||
| 135 | ste,pins = "GPIO9_A10", "GPIO11_B11", | ||
| 136 | "GPIO12_A11", "GPIO13_C12", | ||
| 137 | "GPIO14_B12", "GPIO24_C15"; | ||
| 138 | ste,input = <1>; | ||
| 139 | }; | ||
| 140 | }; | ||
| 141 | }; | ||
| 142 | i2c0 { | ||
| 143 | i2c0_default_mode: i2c0_default { | ||
| 144 | i2c0_default_cfg { | ||
| 145 | ste,pins = "GPIO62_D3", "GPIO63_D2"; | ||
| 146 | ste,input = <1>; | ||
| 147 | }; | ||
| 148 | }; | ||
| 149 | }; | ||
| 150 | i2c1 { | ||
| 151 | i2c1_default_mode: i2c1_default { | ||
| 152 | i2c1_default_cfg { | ||
| 153 | ste,pins = "GPIO53_L4", "GPIO54_L3"; | ||
| 154 | ste,input = <1>; | ||
| 155 | }; | ||
| 156 | }; | ||
| 157 | }; | ||
| 158 | i2c2 { | ||
| 159 | i2c2_default_mode: i2c2_default { | ||
| 160 | i2c2_default_cfg { | ||
| 161 | ste,pins = "GPIO73_C21", "GPIO74_C20"; | ||
| 162 | ste,input = <1>; | ||
| 163 | }; | ||
| 164 | }; | ||
| 165 | }; | ||
| 166 | }; | ||
| 167 | |||
| 168 | src: src@101e0000 { | ||
| 169 | compatible = "stericsson,nomadik-src"; | ||
| 170 | reg = <0x101e0000 0x1000>; | ||
| 171 | disable-sxtalo; | ||
| 172 | disable-mxtalo; | ||
| 173 | |||
| 174 | /* | ||
| 175 | * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz | ||
| 176 | * that is parent of TIMCLK, PLL1 and PLL2 | ||
| 177 | */ | ||
| 178 | mxtal: mxtal@19.2M { | ||
| 179 | #clock-cells = <0>; | ||
| 180 | compatible = "fixed-clock"; | ||
| 181 | clock-frequency = <19200000>; | ||
| 182 | }; | ||
| 183 | |||
| 184 | /* | ||
| 185 | * The 2.4 MHz TIMCLK reference clock is active at | ||
| 186 | * boot time, this is actually the MXTALCLK @19.2 MHz | ||
| 187 | * divided by 8. This clock is used by the timers and | ||
| 188 | * watchdog. See page 105 ff. | ||
| 189 | */ | ||
| 190 | timclk: timclk@2.4M { | ||
| 191 | #clock-cells = <0>; | ||
| 192 | compatible = "fixed-factor-clock"; | ||
| 193 | clock-div = <8>; | ||
| 194 | clock-mult = <1>; | ||
| 195 | clocks = <&mxtal>; | ||
| 196 | }; | ||
| 197 | |||
| 198 | /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ | ||
| 199 | pll1: pll1@0 { | ||
| 200 | #clock-cells = <0>; | ||
| 201 | compatible = "st,nomadik-pll-clock"; | ||
| 202 | pll-id = <1>; | ||
| 203 | clocks = <&mxtal>; | ||
| 204 | }; | ||
| 205 | |||
| 206 | /* HCLK divides the PLL1 with 1,2,3 or 4 */ | ||
| 207 | hclk: hclk@0 { | ||
| 208 | #clock-cells = <0>; | ||
| 209 | compatible = "st,nomadik-hclk-clock"; | ||
| 210 | clocks = <&pll1>; | ||
| 211 | }; | ||
| 212 | /* The PCLK domain uses HCLK right off */ | ||
| 213 | pclk: pclk@0 { | ||
| 214 | #clock-cells = <0>; | ||
| 215 | compatible = "fixed-factor-clock"; | ||
| 216 | clock-div = <1>; | ||
| 217 | clock-mult = <1>; | ||
| 218 | clocks = <&hclk>; | ||
| 219 | }; | ||
| 220 | |||
| 221 | /* PLL2 is usually 864 MHz and divided into a few fixed rates */ | ||
| 222 | pll2: pll2@0 { | ||
| 223 | #clock-cells = <0>; | ||
| 224 | compatible = "st,nomadik-pll-clock"; | ||
| 225 | pll-id = <2>; | ||
| 226 | clocks = <&mxtal>; | ||
| 227 | }; | ||
| 228 | clk216: clk216@216M { | ||
| 229 | #clock-cells = <0>; | ||
| 230 | compatible = "fixed-factor-clock"; | ||
| 231 | clock-div = <4>; | ||
| 232 | clock-mult = <1>; | ||
| 233 | clocks = <&pll2>; | ||
| 234 | }; | ||
| 235 | clk108: clk108@108M { | ||
| 236 | #clock-cells = <0>; | ||
| 237 | compatible = "fixed-factor-clock"; | ||
| 238 | clock-div = <2>; | ||
| 239 | clock-mult = <1>; | ||
| 240 | clocks = <&clk216>; | ||
| 241 | }; | ||
| 242 | clk72: clk72@72M { | ||
| 243 | #clock-cells = <0>; | ||
| 244 | compatible = "fixed-factor-clock"; | ||
| 245 | /* The data sheet does not say how this is derived */ | ||
| 246 | clock-div = <12>; | ||
| 247 | clock-mult = <1>; | ||
| 248 | clocks = <&pll2>; | ||
| 249 | }; | ||
| 250 | clk48: clk48@48M { | ||
| 251 | #clock-cells = <0>; | ||
| 252 | compatible = "fixed-factor-clock"; | ||
| 253 | /* The data sheet does not say how this is derived */ | ||
| 254 | clock-div = <18>; | ||
| 255 | clock-mult = <1>; | ||
| 256 | clocks = <&pll2>; | ||
| 257 | }; | ||
| 258 | clk27: clk27@27M { | ||
| 259 | #clock-cells = <0>; | ||
| 260 | compatible = "fixed-factor-clock"; | ||
| 261 | clock-div = <4>; | ||
| 262 | clock-mult = <1>; | ||
| 263 | clocks = <&clk108>; | ||
| 264 | }; | ||
| 265 | |||
| 266 | /* This apparently exists as well */ | ||
| 267 | ulpiclk: ulpiclk@60M { | ||
| 268 | #clock-cells = <0>; | ||
| 269 | compatible = "fixed-clock"; | ||
| 270 | clock-frequency = <60000000>; | ||
| 271 | }; | ||
| 272 | |||
| 273 | /* | ||
| 274 | * IP AMBA bus clocks, driving the bus side of the | ||
| 275 | * peripheral clocking, clock gates. | ||
| 276 | */ | ||
| 277 | |||
| 278 | hclkdma0: hclkdma0@48M { | ||
| 279 | #clock-cells = <0>; | ||
| 280 | compatible = "st,nomadik-src-clock"; | ||
| 281 | clock-id = <0>; | ||
| 282 | clocks = <&hclk>; | ||
| 283 | }; | ||
| 284 | hclksmc: hclksmc@48M { | ||
| 285 | #clock-cells = <0>; | ||
| 286 | compatible = "st,nomadik-src-clock"; | ||
| 287 | clock-id = <1>; | ||
| 288 | clocks = <&hclk>; | ||
| 289 | }; | ||
| 290 | hclksdram: hclksdram@48M { | ||
| 291 | #clock-cells = <0>; | ||
| 292 | compatible = "st,nomadik-src-clock"; | ||
| 293 | clock-id = <2>; | ||
| 294 | clocks = <&hclk>; | ||
| 295 | }; | ||
| 296 | hclkdma1: hclkdma1@48M { | ||
| 297 | #clock-cells = <0>; | ||
| 298 | compatible = "st,nomadik-src-clock"; | ||
| 299 | clock-id = <3>; | ||
| 300 | clocks = <&hclk>; | ||
| 301 | }; | ||
| 302 | hclkclcd: hclkclcd@48M { | ||
| 303 | #clock-cells = <0>; | ||
| 304 | compatible = "st,nomadik-src-clock"; | ||
| 305 | clock-id = <4>; | ||
| 306 | clocks = <&hclk>; | ||
| 307 | }; | ||
| 308 | pclkirda: pclkirda@48M { | ||
| 309 | #clock-cells = <0>; | ||
| 310 | compatible = "st,nomadik-src-clock"; | ||
| 311 | clock-id = <5>; | ||
| 312 | clocks = <&pclk>; | ||
| 313 | }; | ||
| 314 | pclkssp: pclkssp@48M { | ||
| 315 | #clock-cells = <0>; | ||
| 316 | compatible = "st,nomadik-src-clock"; | ||
| 317 | clock-id = <6>; | ||
| 318 | clocks = <&pclk>; | ||
| 319 | }; | ||
| 320 | pclkuart0: pclkuart0@48M { | ||
| 321 | #clock-cells = <0>; | ||
| 322 | compatible = "st,nomadik-src-clock"; | ||
| 323 | clock-id = <7>; | ||
| 324 | clocks = <&pclk>; | ||
| 325 | }; | ||
| 326 | pclksdi: pclksdi@48M { | ||
| 327 | #clock-cells = <0>; | ||
| 328 | compatible = "st,nomadik-src-clock"; | ||
| 329 | clock-id = <8>; | ||
| 330 | clocks = <&pclk>; | ||
| 331 | }; | ||
| 332 | pclki2c0: pclki2c0@48M { | ||
| 333 | #clock-cells = <0>; | ||
| 334 | compatible = "st,nomadik-src-clock"; | ||
| 335 | clock-id = <9>; | ||
| 336 | clocks = <&pclk>; | ||
| 337 | }; | ||
| 338 | pclki2c1: pclki2c1@48M { | ||
| 339 | #clock-cells = <0>; | ||
| 340 | compatible = "st,nomadik-src-clock"; | ||
| 341 | clock-id = <10>; | ||
| 342 | clocks = <&pclk>; | ||
| 343 | }; | ||
| 344 | pclkuart1: pclkuart1@48M { | ||
| 345 | #clock-cells = <0>; | ||
| 346 | compatible = "st,nomadik-src-clock"; | ||
| 347 | clock-id = <11>; | ||
| 348 | clocks = <&pclk>; | ||
| 349 | }; | ||
| 350 | pclkmsp0: pclkmsp0@48M { | ||
| 351 | #clock-cells = <0>; | ||
| 352 | compatible = "st,nomadik-src-clock"; | ||
| 353 | clock-id = <12>; | ||
| 354 | clocks = <&pclk>; | ||
| 355 | }; | ||
| 356 | hclkusb: hclkusb@48M { | ||
| 357 | #clock-cells = <0>; | ||
| 358 | compatible = "st,nomadik-src-clock"; | ||
| 359 | clock-id = <13>; | ||
| 360 | clocks = <&hclk>; | ||
| 361 | }; | ||
| 362 | hclkdif: hclkdif@48M { | ||
| 363 | #clock-cells = <0>; | ||
| 364 | compatible = "st,nomadik-src-clock"; | ||
| 365 | clock-id = <14>; | ||
| 366 | clocks = <&hclk>; | ||
| 367 | }; | ||
| 368 | hclksaa: hclksaa@48M { | ||
| 369 | #clock-cells = <0>; | ||
| 370 | compatible = "st,nomadik-src-clock"; | ||
| 371 | clock-id = <15>; | ||
| 372 | clocks = <&hclk>; | ||
| 373 | }; | ||
| 374 | hclksva: hclksva@48M { | ||
| 375 | #clock-cells = <0>; | ||
| 376 | compatible = "st,nomadik-src-clock"; | ||
| 377 | clock-id = <16>; | ||
| 378 | clocks = <&hclk>; | ||
| 379 | }; | ||
| 380 | pclkhsi: pclkhsi@48M { | ||
| 381 | #clock-cells = <0>; | ||
| 382 | compatible = "st,nomadik-src-clock"; | ||
| 383 | clock-id = <17>; | ||
| 384 | clocks = <&pclk>; | ||
| 385 | }; | ||
| 386 | pclkxti: pclkxti@48M { | ||
| 387 | #clock-cells = <0>; | ||
| 388 | compatible = "st,nomadik-src-clock"; | ||
| 389 | clock-id = <18>; | ||
| 390 | clocks = <&pclk>; | ||
| 391 | }; | ||
| 392 | pclkuart2: pclkuart2@48M { | ||
| 393 | #clock-cells = <0>; | ||
| 394 | compatible = "st,nomadik-src-clock"; | ||
| 395 | clock-id = <19>; | ||
| 396 | clocks = <&pclk>; | ||
| 397 | }; | ||
| 398 | pclkmsp1: pclkmsp1@48M { | ||
| 399 | #clock-cells = <0>; | ||
| 400 | compatible = "st,nomadik-src-clock"; | ||
| 401 | clock-id = <20>; | ||
| 402 | clocks = <&pclk>; | ||
| 403 | }; | ||
| 404 | pclkmsp2: pclkmsp2@48M { | ||
| 405 | #clock-cells = <0>; | ||
| 406 | compatible = "st,nomadik-src-clock"; | ||
| 407 | clock-id = <21>; | ||
| 408 | clocks = <&pclk>; | ||
| 409 | }; | ||
| 410 | pclkowm: pclkowm@48M { | ||
| 411 | #clock-cells = <0>; | ||
| 412 | compatible = "st,nomadik-src-clock"; | ||
| 413 | clock-id = <22>; | ||
| 414 | clocks = <&pclk>; | ||
| 415 | }; | ||
| 416 | hclkhpi: hclkhpi@48M { | ||
| 417 | #clock-cells = <0>; | ||
| 418 | compatible = "st,nomadik-src-clock"; | ||
| 419 | clock-id = <23>; | ||
| 420 | clocks = <&hclk>; | ||
| 421 | }; | ||
| 422 | pclkske: pclkske@48M { | ||
| 423 | #clock-cells = <0>; | ||
| 424 | compatible = "st,nomadik-src-clock"; | ||
| 425 | clock-id = <24>; | ||
| 426 | clocks = <&pclk>; | ||
| 427 | }; | ||
| 428 | pclkhsem: pclkhsem@48M { | ||
| 429 | #clock-cells = <0>; | ||
| 430 | compatible = "st,nomadik-src-clock"; | ||
| 431 | clock-id = <25>; | ||
| 432 | clocks = <&pclk>; | ||
| 433 | }; | ||
| 434 | hclk3d: hclk3d@48M { | ||
| 435 | #clock-cells = <0>; | ||
| 436 | compatible = "st,nomadik-src-clock"; | ||
| 437 | clock-id = <26>; | ||
| 438 | clocks = <&hclk>; | ||
| 439 | }; | ||
| 440 | hclkhash: hclkhash@48M { | ||
| 441 | #clock-cells = <0>; | ||
| 442 | compatible = "st,nomadik-src-clock"; | ||
| 443 | clock-id = <27>; | ||
| 444 | clocks = <&hclk>; | ||
| 445 | }; | ||
| 446 | hclkcryp: hclkcryp@48M { | ||
| 447 | #clock-cells = <0>; | ||
| 448 | compatible = "st,nomadik-src-clock"; | ||
| 449 | clock-id = <28>; | ||
| 450 | clocks = <&hclk>; | ||
| 451 | }; | ||
| 452 | pclkmshc: pclkmshc@48M { | ||
| 453 | #clock-cells = <0>; | ||
| 454 | compatible = "st,nomadik-src-clock"; | ||
| 455 | clock-id = <29>; | ||
| 456 | clocks = <&pclk>; | ||
| 457 | }; | ||
| 458 | hclkusbm: hclkusbm@48M { | ||
| 459 | #clock-cells = <0>; | ||
| 460 | compatible = "st,nomadik-src-clock"; | ||
| 461 | clock-id = <30>; | ||
| 462 | clocks = <&hclk>; | ||
| 463 | }; | ||
| 464 | hclkrng: hclkrng@48M { | ||
| 465 | #clock-cells = <0>; | ||
| 466 | compatible = "st,nomadik-src-clock"; | ||
| 467 | clock-id = <31>; | ||
| 468 | clocks = <&hclk>; | ||
| 469 | }; | ||
| 470 | |||
| 471 | /* IP kernel clocks */ | ||
| 472 | clcdclk: clcdclk@0 { | ||
| 473 | #clock-cells = <0>; | ||
| 474 | compatible = "st,nomadik-src-clock"; | ||
| 475 | clock-id = <36>; | ||
| 476 | clocks = <&clk72 &clk48>; | ||
| 477 | }; | ||
| 478 | irdaclk: irdaclk@48M { | ||
| 479 | #clock-cells = <0>; | ||
| 480 | compatible = "st,nomadik-src-clock"; | ||
| 481 | clock-id = <37>; | ||
| 482 | clocks = <&clk48>; | ||
| 483 | }; | ||
| 484 | sspiclk: sspiclk@48M { | ||
| 485 | #clock-cells = <0>; | ||
| 486 | compatible = "st,nomadik-src-clock"; | ||
| 487 | clock-id = <38>; | ||
| 488 | clocks = <&clk48>; | ||
| 489 | }; | ||
| 490 | uart0clk: uart0clk@48M { | ||
| 491 | #clock-cells = <0>; | ||
| 492 | compatible = "st,nomadik-src-clock"; | ||
| 493 | clock-id = <39>; | ||
| 494 | clocks = <&clk48>; | ||
| 495 | }; | ||
| 496 | sdiclk: sdiclk@48M { | ||
| 497 | /* Also called MCCLK in some documents */ | ||
| 498 | #clock-cells = <0>; | ||
| 499 | compatible = "st,nomadik-src-clock"; | ||
| 500 | clock-id = <40>; | ||
| 501 | clocks = <&clk48>; | ||
| 502 | }; | ||
| 503 | i2c0clk: i2c0clk@48M { | ||
| 504 | #clock-cells = <0>; | ||
| 505 | compatible = "st,nomadik-src-clock"; | ||
| 506 | clock-id = <41>; | ||
| 507 | clocks = <&clk48>; | ||
| 508 | }; | ||
| 509 | i2c1clk: i2c1clk@48M { | ||
| 510 | #clock-cells = <0>; | ||
| 511 | compatible = "st,nomadik-src-clock"; | ||
| 512 | clock-id = <42>; | ||
| 513 | clocks = <&clk48>; | ||
| 514 | }; | ||
| 515 | uart1clk: uart1clk@48M { | ||
| 516 | #clock-cells = <0>; | ||
| 517 | compatible = "st,nomadik-src-clock"; | ||
| 518 | clock-id = <43>; | ||
| 519 | clocks = <&clk48>; | ||
| 520 | }; | ||
| 521 | mspclk0: mspclk0@48M { | ||
| 522 | #clock-cells = <0>; | ||
| 523 | compatible = "st,nomadik-src-clock"; | ||
| 524 | clock-id = <44>; | ||
| 525 | clocks = <&clk48>; | ||
| 526 | }; | ||
| 527 | usbclk: usbclk@48M { | ||
| 528 | #clock-cells = <0>; | ||
| 529 | compatible = "st,nomadik-src-clock"; | ||
| 530 | clock-id = <45>; | ||
| 531 | clocks = <&clk48>; /* 48 MHz not ULPI */ | ||
| 532 | }; | ||
| 533 | difclk: difclk@72M { | ||
| 534 | #clock-cells = <0>; | ||
| 535 | compatible = "st,nomadik-src-clock"; | ||
| 536 | clock-id = <46>; | ||
| 537 | clocks = <&clk72>; | ||
| 538 | }; | ||
| 539 | ipi2cclk: ipi2cclk@48M { | ||
| 540 | #clock-cells = <0>; | ||
| 541 | compatible = "st,nomadik-src-clock"; | ||
| 542 | clock-id = <47>; | ||
| 543 | clocks = <&clk48>; /* Guess */ | ||
| 544 | }; | ||
| 545 | ipbmcclk: ipbmcclk@48M { | ||
| 546 | #clock-cells = <0>; | ||
| 547 | compatible = "st,nomadik-src-clock"; | ||
| 548 | clock-id = <48>; | ||
| 549 | clocks = <&clk48>; /* Guess */ | ||
| 550 | }; | ||
| 551 | hsiclkrx: hsiclkrx@216M { | ||
| 552 | #clock-cells = <0>; | ||
| 553 | compatible = "st,nomadik-src-clock"; | ||
| 554 | clock-id = <49>; | ||
| 555 | clocks = <&clk216>; | ||
| 556 | }; | ||
| 557 | hsiclktx: hsiclktx@108M { | ||
| 558 | #clock-cells = <0>; | ||
| 559 | compatible = "st,nomadik-src-clock"; | ||
| 560 | clock-id = <50>; | ||
| 561 | clocks = <&clk108>; | ||
| 562 | }; | ||
| 563 | uart2clk: uart2clk@48M { | ||
| 564 | #clock-cells = <0>; | ||
| 565 | compatible = "st,nomadik-src-clock"; | ||
| 566 | clock-id = <51>; | ||
| 567 | clocks = <&clk48>; | ||
| 568 | }; | ||
| 569 | mspclk1: mspclk1@48M { | ||
| 570 | #clock-cells = <0>; | ||
| 571 | compatible = "st,nomadik-src-clock"; | ||
| 572 | clock-id = <52>; | ||
| 573 | clocks = <&clk48>; | ||
| 574 | }; | ||
| 575 | mspclk2: mspclk2@48M { | ||
| 576 | #clock-cells = <0>; | ||
| 577 | compatible = "st,nomadik-src-clock"; | ||
| 578 | clock-id = <53>; | ||
| 579 | clocks = <&clk48>; | ||
| 580 | }; | ||
| 581 | owmclk: owmclk@48M { | ||
| 582 | #clock-cells = <0>; | ||
| 583 | compatible = "st,nomadik-src-clock"; | ||
| 584 | clock-id = <54>; | ||
| 585 | clocks = <&clk48>; /* Guess */ | ||
| 586 | }; | ||
| 587 | skeclk: skeclk@48M { | ||
| 588 | #clock-cells = <0>; | ||
| 589 | compatible = "st,nomadik-src-clock"; | ||
| 590 | clock-id = <56>; | ||
| 591 | clocks = <&clk48>; /* Guess */ | ||
| 592 | }; | ||
| 593 | x3dclk: x3dclk@48M { | ||
| 594 | #clock-cells = <0>; | ||
| 595 | compatible = "st,nomadik-src-clock"; | ||
| 596 | clock-id = <58>; | ||
| 597 | clocks = <&clk48>; /* Guess */ | ||
| 598 | }; | ||
| 599 | pclkmsp3: pclkmsp3@48M { | ||
| 600 | #clock-cells = <0>; | ||
| 601 | compatible = "st,nomadik-src-clock"; | ||
| 602 | clock-id = <59>; | ||
| 603 | clocks = <&pclk>; | ||
| 604 | }; | ||
| 605 | mspclk3: mspclk3@48M { | ||
| 606 | #clock-cells = <0>; | ||
| 607 | compatible = "st,nomadik-src-clock"; | ||
| 608 | clock-id = <60>; | ||
| 609 | clocks = <&clk48>; | ||
| 610 | }; | ||
| 611 | mshcclk: mshcclk@48M { | ||
| 612 | #clock-cells = <0>; | ||
| 613 | compatible = "st,nomadik-src-clock"; | ||
| 614 | clock-id = <61>; | ||
| 615 | clocks = <&clk48>; /* Guess */ | ||
| 616 | }; | ||
| 617 | usbmclk: usbmclk@48M { | ||
| 618 | #clock-cells = <0>; | ||
| 619 | compatible = "st,nomadik-src-clock"; | ||
| 620 | clock-id = <62>; | ||
| 621 | /* Stated as "48 MHz not ULPI clock" */ | ||
| 622 | clocks = <&clk48>; | ||
| 623 | }; | ||
| 624 | rngcclk: rngcclk@48M { | ||
| 625 | #clock-cells = <0>; | ||
| 626 | compatible = "st,nomadik-src-clock"; | ||
| 627 | clock-id = <63>; | ||
| 628 | clocks = <&clk48>; /* Guess */ | ||
| 629 | }; | ||
| 88 | }; | 630 | }; |
| 89 | 631 | ||
| 90 | /* A NAND flash of 128 MiB */ | 632 | /* A NAND flash of 128 MiB */ |
| @@ -97,6 +639,7 @@ | |||
| 97 | <0x41000000 0x2000>, /* NAND Base ADDR */ | 639 | <0x41000000 0x2000>, /* NAND Base ADDR */ |
| 98 | <0x40800000 0x2000>; /* NAND Base CMD */ | 640 | <0x40800000 0x2000>; /* NAND Base CMD */ |
| 99 | reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; | 641 | reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; |
| 642 | clocks = <&hclksmc>; | ||
| 100 | status = "okay"; | 643 | status = "okay"; |
| 101 | 644 | ||
| 102 | partition@0 { | 645 | partition@0 { |
| @@ -144,6 +687,8 @@ | |||
| 144 | <&gpio1 30 0>; /* scl */ | 687 | <&gpio1 30 0>; /* scl */ |
| 145 | #address-cells = <1>; | 688 | #address-cells = <1>; |
| 146 | #size-cells = <0>; | 689 | #size-cells = <0>; |
| 690 | pinctrl-names = "default"; | ||
| 691 | pinctrl-0 = <&i2c0_default_mode>; | ||
| 147 | 692 | ||
| 148 | stw4811@2d { | 693 | stw4811@2d { |
| 149 | compatible = "st,stw4811"; | 694 | compatible = "st,stw4811"; |
| @@ -158,6 +703,8 @@ | |||
| 158 | <&gpio1 21 0>; /* scl */ | 703 | <&gpio1 21 0>; /* scl */ |
| 159 | #address-cells = <1>; | 704 | #address-cells = <1>; |
| 160 | #size-cells = <0>; | 705 | #size-cells = <0>; |
| 706 | pinctrl-names = "default"; | ||
| 707 | pinctrl-0 = <&i2c1_default_mode>; | ||
| 161 | 708 | ||
| 162 | camera@2d { | 709 | camera@2d { |
| 163 | compatible = "st,camera"; | 710 | compatible = "st,camera"; |
| @@ -180,6 +727,9 @@ | |||
| 180 | <&gpio2 9 0>; /* scl */ | 727 | <&gpio2 9 0>; /* scl */ |
| 181 | #address-cells = <1>; | 728 | #address-cells = <1>; |
| 182 | #size-cells = <0>; | 729 | #size-cells = <0>; |
| 730 | pinctrl-names = "default"; | ||
| 731 | pinctrl-0 = <&i2c2_default_mode>; | ||
| 732 | |||
| 183 | stw4811@2d { | 733 | stw4811@2d { |
| 184 | compatible = "st,stw4811-usb"; | 734 | compatible = "st,stw4811-usb"; |
| 185 | reg = <0x2d>; | 735 | reg = <0x2d>; |
| @@ -211,6 +761,10 @@ | |||
| 211 | reg = <0x101fd000 0x1000>; | 761 | reg = <0x101fd000 0x1000>; |
| 212 | interrupt-parent = <&vica>; | 762 | interrupt-parent = <&vica>; |
| 213 | interrupts = <12>; | 763 | interrupts = <12>; |
| 764 | clocks = <&uart0clk>, <&pclkuart0>; | ||
| 765 | clock-names = "uartclk", "apb_pclk"; | ||
| 766 | pinctrl-names = "default"; | ||
| 767 | pinctrl-0 = <&uart0_default_mux>; | ||
| 214 | }; | 768 | }; |
| 215 | 769 | ||
| 216 | uart1: uart@101fb000 { | 770 | uart1: uart@101fb000 { |
| @@ -218,6 +772,10 @@ | |||
| 218 | reg = <0x101fb000 0x1000>; | 772 | reg = <0x101fb000 0x1000>; |
| 219 | interrupt-parent = <&vica>; | 773 | interrupt-parent = <&vica>; |
| 220 | interrupts = <17>; | 774 | interrupts = <17>; |
| 775 | clocks = <&uart1clk>, <&pclkuart1>; | ||
| 776 | clock-names = "uartclk", "apb_pclk"; | ||
| 777 | pinctrl-names = "default"; | ||
| 778 | pinctrl-0 = <&uart1_default_mux>; | ||
| 221 | }; | 779 | }; |
| 222 | 780 | ||
| 223 | uart2: uart@101f2000 { | 781 | uart2: uart@101f2000 { |
| @@ -225,17 +783,23 @@ | |||
| 225 | reg = <0x101f2000 0x1000>; | 783 | reg = <0x101f2000 0x1000>; |
| 226 | interrupt-parent = <&vica>; | 784 | interrupt-parent = <&vica>; |
| 227 | interrupts = <28>; | 785 | interrupts = <28>; |
| 786 | clocks = <&uart2clk>, <&pclkuart2>; | ||
| 787 | clock-names = "uartclk", "apb_pclk"; | ||
| 228 | status = "disabled"; | 788 | status = "disabled"; |
| 229 | }; | 789 | }; |
| 230 | 790 | ||
| 231 | rng: rng@101b0000 { | 791 | rng: rng@101b0000 { |
| 232 | compatible = "arm,primecell"; | 792 | compatible = "arm,primecell"; |
| 233 | reg = <0x101b0000 0x1000>; | 793 | reg = <0x101b0000 0x1000>; |
| 794 | clocks = <&rngcclk>, <&hclkrng>; | ||
| 795 | clock-names = "rng", "apb_pclk"; | ||
| 234 | }; | 796 | }; |
| 235 | 797 | ||
| 236 | rtc: rtc@101e8000 { | 798 | rtc: rtc@101e8000 { |
| 237 | compatible = "arm,pl031", "arm,primecell"; | 799 | compatible = "arm,pl031", "arm,primecell"; |
| 238 | reg = <0x101e8000 0x1000>; | 800 | reg = <0x101e8000 0x1000>; |
| 801 | clocks = <&pclk>; | ||
| 802 | clock-names = "apb_pclk"; | ||
| 239 | interrupt-parent = <&vica>; | 803 | interrupt-parent = <&vica>; |
| 240 | interrupts = <10>; | 804 | interrupts = <10>; |
| 241 | }; | 805 | }; |
| @@ -243,6 +807,8 @@ | |||
| 243 | mmcsd: sdi@101f6000 { | 807 | mmcsd: sdi@101f6000 { |
| 244 | compatible = "arm,pl18x", "arm,primecell"; | 808 | compatible = "arm,pl18x", "arm,primecell"; |
| 245 | reg = <0x101f6000 0x1000>; | 809 | reg = <0x101f6000 0x1000>; |
| 810 | clocks = <&sdiclk>, <&pclksdi>; | ||
| 811 | clock-names = "mclk", "apb_pclk"; | ||
| 246 | interrupt-parent = <&vica>; | 812 | interrupt-parent = <&vica>; |
| 247 | interrupts = <22>; | 813 | interrupts = <22>; |
| 248 | max-frequency = <48000000>; | 814 | max-frequency = <48000000>; |
| @@ -251,6 +817,8 @@ | |||
| 251 | mmc-cap-sd-highspeed; | 817 | mmc-cap-sd-highspeed; |
| 252 | cd-gpios = <&gpio3 15 0x1>; | 818 | cd-gpios = <&gpio3 15 0x1>; |
| 253 | cd-inverted; | 819 | cd-inverted; |
| 820 | pinctrl-names = "default"; | ||
| 821 | pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; | ||
| 254 | }; | 822 | }; |
| 255 | }; | 823 | }; |
| 256 | }; | 824 | }; |
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi index 615392a75676..524e33240ad4 100644 --- a/arch/arm/boot/dts/stuib.dtsi +++ b/arch/arm/boot/dts/stuib.dtsi | |||
| @@ -9,13 +9,15 @@ | |||
| 9 | * http://www.gnu.org/copyleft/gpl.html | 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <dt-bindings/interrupt-controller/irq.h> | ||
| 13 | |||
| 12 | / { | 14 | / { |
| 13 | soc-u9500 { | 15 | soc { |
| 14 | i2c@80004000 { | 16 | i2c@80004000 { |
| 15 | stmpe1601: stmpe1601@40 { | 17 | stmpe1601: stmpe1601@40 { |
| 16 | compatible = "st,stmpe1601"; | 18 | compatible = "st,stmpe1601"; |
| 17 | reg = <0x40>; | 19 | reg = <0x40>; |
| 18 | interrupts = <26 0x2>; | 20 | interrupts = <26 IRQ_TYPE_EDGE_FALLING>; |
| 19 | interrupt-parent = <&gpio6>; | 21 | interrupt-parent = <&gpio6>; |
| 20 | interrupt-controller; | 22 | interrupt-controller; |
| 21 | 23 | ||
| @@ -52,26 +54,26 @@ | |||
| 52 | }; | 54 | }; |
| 53 | 55 | ||
| 54 | i2c@80110000 { | 56 | i2c@80110000 { |
| 55 | bu21013_tp@0x5c { | 57 | bu21013_tp@5c { |
| 56 | compatible = "rhom,bu21013_tp"; | 58 | compatible = "rohm,bu21013_tp"; |
| 57 | reg = <0x5c>; | 59 | reg = <0x5c>; |
| 58 | touch-gpio = <&gpio2 20 0x4>; | 60 | touch-gpio = <&gpio2 20 0x4>; |
| 59 | avdd-supply = <&ab8500_ldo_aux1_reg>; | 61 | avdd-supply = <&ab8500_ldo_aux1_reg>; |
| 60 | 62 | ||
| 61 | rhom,touch-max-x = <384>; | 63 | rohm,touch-max-x = <384>; |
| 62 | rhom,touch-max-y = <704>; | 64 | rohm,touch-max-y = <704>; |
| 63 | rhom,flip-y; | 65 | rohm,flip-y; |
| 64 | }; | 66 | }; |
| 65 | 67 | ||
| 66 | bu21013_tp@0x5d { | 68 | bu21013_tp@5d { |
| 67 | compatible = "rhom,bu21013_tp"; | 69 | compatible = "rohm,bu21013_tp"; |
| 68 | reg = <0x5d>; | 70 | reg = <0x5d>; |
| 69 | touch-gpio = <&gpio2 20 0x4>; | 71 | touch-gpio = <&gpio2 20 0x4>; |
| 70 | avdd-supply = <&ab8500_ldo_aux1_reg>; | 72 | avdd-supply = <&ab8500_ldo_aux1_reg>; |
| 71 | 73 | ||
| 72 | rhom,touch-max-x = <384>; | 74 | rohm,touch-max-x = <384>; |
| 73 | rhom,touch-max-y = <704>; | 75 | rohm,touch-max-y = <704>; |
| 74 | rhom,flip-y; | 76 | rohm,flip-y; |
| 75 | }; | 77 | }; |
| 76 | }; | 78 | }; |
| 77 | }; | 79 | }; |
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index b70fe0db6bb7..0e22a285dfe0 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts | |||
| @@ -41,6 +41,18 @@ | |||
| 41 | pinctrl-0 = <&uart0_pins_a>; | 41 | pinctrl-0 = <&uart0_pins_a>; |
| 42 | status = "okay"; | 42 | status = "okay"; |
| 43 | }; | 43 | }; |
| 44 | |||
| 45 | i2c0: i2c@01c2ac00 { | ||
| 46 | pinctrl-names = "default"; | ||
| 47 | pinctrl-0 = <&i2c0_pins_a>; | ||
| 48 | status = "okay"; | ||
| 49 | }; | ||
| 50 | |||
| 51 | i2c1: i2c@01c2b000 { | ||
| 52 | pinctrl-names = "default"; | ||
| 53 | pinctrl-0 = <&i2c1_pins_a>; | ||
| 54 | status = "okay"; | ||
| 55 | }; | ||
| 44 | }; | 56 | }; |
| 45 | 57 | ||
| 46 | leds { | 58 | leds { |
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index e7ef619a70a2..82e03d22f913 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi | |||
| @@ -16,8 +16,12 @@ | |||
| 16 | interrupt-parent = <&intc>; | 16 | interrupt-parent = <&intc>; |
| 17 | 17 | ||
| 18 | cpus { | 18 | cpus { |
| 19 | #address-cells = <1>; | ||
| 20 | #size-cells = <0>; | ||
| 19 | cpu@0 { | 21 | cpu@0 { |
| 22 | device_type = "cpu"; | ||
| 20 | compatible = "arm,cortex-a8"; | 23 | compatible = "arm,cortex-a8"; |
| 24 | reg = <0x0>; | ||
| 21 | }; | 25 | }; |
| 22 | }; | 26 | }; |
| 23 | 27 | ||
| @@ -173,8 +177,10 @@ | |||
| 173 | pio: pinctrl@01c20800 { | 177 | pio: pinctrl@01c20800 { |
| 174 | compatible = "allwinner,sun4i-a10-pinctrl"; | 178 | compatible = "allwinner,sun4i-a10-pinctrl"; |
| 175 | reg = <0x01c20800 0x400>; | 179 | reg = <0x01c20800 0x400>; |
| 180 | interrupts = <28>; | ||
| 176 | clocks = <&apb0_gates 5>; | 181 | clocks = <&apb0_gates 5>; |
| 177 | gpio-controller; | 182 | gpio-controller; |
| 183 | interrupt-controller; | ||
| 178 | #address-cells = <1>; | 184 | #address-cells = <1>; |
| 179 | #size-cells = <0>; | 185 | #size-cells = <0>; |
| 180 | #gpio-cells = <3>; | 186 | #gpio-cells = <3>; |
| @@ -199,6 +205,27 @@ | |||
| 199 | allwinner,drive = <0>; | 205 | allwinner,drive = <0>; |
| 200 | allwinner,pull = <0>; | 206 | allwinner,pull = <0>; |
| 201 | }; | 207 | }; |
| 208 | |||
| 209 | i2c0_pins_a: i2c0@0 { | ||
| 210 | allwinner,pins = "PB0", "PB1"; | ||
| 211 | allwinner,function = "i2c0"; | ||
| 212 | allwinner,drive = <0>; | ||
| 213 | allwinner,pull = <0>; | ||
| 214 | }; | ||
| 215 | |||
| 216 | i2c1_pins_a: i2c1@0 { | ||
| 217 | allwinner,pins = "PB18", "PB19"; | ||
| 218 | allwinner,function = "i2c1"; | ||
| 219 | allwinner,drive = <0>; | ||
| 220 | allwinner,pull = <0>; | ||
| 221 | }; | ||
| 222 | |||
| 223 | i2c2_pins_a: i2c2@0 { | ||
| 224 | allwinner,pins = "PB20", "PB21"; | ||
| 225 | allwinner,function = "i2c2"; | ||
| 226 | allwinner,drive = <0>; | ||
| 227 | allwinner,pull = <0>; | ||
| 228 | }; | ||
| 202 | }; | 229 | }; |
| 203 | 230 | ||
| 204 | timer@01c20c00 { | 231 | timer@01c20c00 { |
| @@ -292,5 +319,32 @@ | |||
| 292 | clocks = <&apb1_gates 23>; | 319 | clocks = <&apb1_gates 23>; |
| 293 | status = "disabled"; | 320 | status = "disabled"; |
| 294 | }; | 321 | }; |
| 322 | |||
| 323 | i2c0: i2c@01c2ac00 { | ||
| 324 | compatible = "allwinner,sun4i-i2c"; | ||
| 325 | reg = <0x01c2ac00 0x400>; | ||
| 326 | interrupts = <7>; | ||
| 327 | clocks = <&apb1_gates 0>; | ||
| 328 | clock-frequency = <100000>; | ||
| 329 | status = "disabled"; | ||
| 330 | }; | ||
| 331 | |||
| 332 | i2c1: i2c@01c2b000 { | ||
| 333 | compatible = "allwinner,sun4i-i2c"; | ||
| 334 | reg = <0x01c2b000 0x400>; | ||
| 335 | interrupts = <8>; | ||
| 336 | clocks = <&apb1_gates 1>; | ||
| 337 | clock-frequency = <100000>; | ||
| 338 | status = "disabled"; | ||
| 339 | }; | ||
| 340 | |||
| 341 | i2c2: i2c@01c2b400 { | ||
| 342 | compatible = "allwinner,sun4i-i2c"; | ||
| 343 | reg = <0x01c2b400 0x400>; | ||
| 344 | interrupts = <9>; | ||
| 345 | clocks = <&apb1_gates 2>; | ||
| 346 | clock-frequency = <100000>; | ||
| 347 | status = "disabled"; | ||
| 348 | }; | ||
| 295 | }; | 349 | }; |
| 296 | }; | 350 | }; |
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts new file mode 100644 index 000000000000..64dc0c42c43a --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | |||
| @@ -0,0 +1,76 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Maxime Ripard | ||
| 3 | * | ||
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | /dts-v1/; | ||
| 15 | /include/ "sun5i-a10s.dtsi" | ||
| 16 | |||
| 17 | / { | ||
| 18 | model = "Olimex A10s-Olinuxino Micro"; | ||
| 19 | compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; | ||
| 20 | |||
| 21 | soc@01c20000 { | ||
| 22 | emac: ethernet@01c0b000 { | ||
| 23 | pinctrl-names = "default"; | ||
| 24 | pinctrl-0 = <&emac_pins_a>; | ||
| 25 | phy = <&phy1>; | ||
| 26 | status = "okay"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | mdio@01c0b080 { | ||
| 30 | status = "okay"; | ||
| 31 | |||
| 32 | phy1: ethernet-phy@1 { | ||
| 33 | reg = <1>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | pinctrl@01c20800 { | ||
| 38 | led_pins_olinuxino: led_pins@0 { | ||
| 39 | allwinner,pins = "PE3"; | ||
| 40 | allwinner,function = "gpio_out"; | ||
| 41 | allwinner,drive = <1>; | ||
| 42 | allwinner,pull = <0>; | ||
| 43 | }; | ||
| 44 | }; | ||
| 45 | |||
| 46 | uart0: serial@01c28000 { | ||
| 47 | pinctrl-names = "default"; | ||
| 48 | pinctrl-0 = <&uart0_pins_a>; | ||
| 49 | status = "okay"; | ||
| 50 | }; | ||
| 51 | |||
| 52 | uart2: serial@01c28800 { | ||
| 53 | pinctrl-names = "default"; | ||
| 54 | pinctrl-0 = <&uart2_pins_a>; | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | |||
| 58 | uart3: serial@01c28c00 { | ||
| 59 | pinctrl-names = "default"; | ||
| 60 | pinctrl-0 = <&uart3_pins_a>; | ||
| 61 | status = "okay"; | ||
| 62 | }; | ||
| 63 | }; | ||
| 64 | |||
| 65 | leds { | ||
| 66 | compatible = "gpio-leds"; | ||
| 67 | pinctrl-names = "default"; | ||
| 68 | pinctrl-0 = <&led_pins_olinuxino>; | ||
| 69 | |||
| 70 | green { | ||
| 71 | label = "a10s-olinuxino-micro:green:usr"; | ||
| 72 | gpios = <&pio 4 3 0>; | ||
| 73 | default-state = "on"; | ||
| 74 | }; | ||
| 75 | }; | ||
| 76 | }; | ||
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi new file mode 100644 index 000000000000..2307ce827ae0 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi | |||
| @@ -0,0 +1,286 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Maxime Ripard | ||
| 3 | * | ||
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | ||
| 5 | * | ||
| 6 | * The code contained herein is licensed under the GNU General Public | ||
| 7 | * License. You may obtain a copy of the GNU General Public License | ||
| 8 | * Version 2 or later at the following locations: | ||
| 9 | * | ||
| 10 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 11 | * http://www.gnu.org/copyleft/gpl.html | ||
| 12 | */ | ||
| 13 | |||
| 14 | /include/ "skeleton.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | interrupt-parent = <&intc>; | ||
| 18 | |||
| 19 | cpus { | ||
| 20 | cpu@0 { | ||
| 21 | compatible = "arm,cortex-a8"; | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | |||
| 25 | memory { | ||
| 26 | reg = <0x40000000 0x20000000>; | ||
| 27 | }; | ||
| 28 | |||
| 29 | clocks { | ||
| 30 | #address-cells = <1>; | ||
| 31 | #size-cells = <1>; | ||
| 32 | ranges; | ||
| 33 | |||
| 34 | /* | ||
| 35 | * This is a dummy clock, to be used as placeholder on | ||
| 36 | * other mux clocks when a specific parent clock is not | ||
| 37 | * yet implemented. It should be dropped when the driver | ||
| 38 | * is complete. | ||
| 39 | */ | ||
| 40 | dummy: dummy { | ||
| 41 | #clock-cells = <0>; | ||
| 42 | compatible = "fixed-clock"; | ||
| 43 | clock-frequency = <0>; | ||
| 44 | }; | ||
| 45 | |||
| 46 | osc24M: osc24M@01c20050 { | ||
| 47 | #clock-cells = <0>; | ||
| 48 | compatible = "allwinner,sun4i-osc-clk"; | ||
| 49 | reg = <0x01c20050 0x4>; | ||
| 50 | clock-frequency = <24000000>; | ||
| 51 | }; | ||
| 52 | |||
| 53 | osc32k: osc32k { | ||
| 54 | #clock-cells = <0>; | ||
| 55 | compatible = "fixed-clock"; | ||
| 56 | clock-frequency = <32768>; | ||
| 57 | }; | ||
| 58 | |||
| 59 | pll1: pll1@01c20000 { | ||
| 60 | #clock-cells = <0>; | ||
| 61 | compatible = "allwinner,sun4i-pll1-clk"; | ||
| 62 | reg = <0x01c20000 0x4>; | ||
| 63 | clocks = <&osc24M>; | ||
| 64 | }; | ||
| 65 | |||
| 66 | /* dummy is 200M */ | ||
| 67 | cpu: cpu@01c20054 { | ||
| 68 | #clock-cells = <0>; | ||
| 69 | compatible = "allwinner,sun4i-cpu-clk"; | ||
| 70 | reg = <0x01c20054 0x4>; | ||
| 71 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | ||
| 72 | }; | ||
| 73 | |||
| 74 | axi: axi@01c20054 { | ||
| 75 | #clock-cells = <0>; | ||
| 76 | compatible = "allwinner,sun4i-axi-clk"; | ||
| 77 | reg = <0x01c20054 0x4>; | ||
| 78 | clocks = <&cpu>; | ||
| 79 | }; | ||
| 80 | |||
| 81 | axi_gates: axi_gates@01c2005c { | ||
| 82 | #clock-cells = <1>; | ||
| 83 | compatible = "allwinner,sun4i-axi-gates-clk"; | ||
| 84 | reg = <0x01c2005c 0x4>; | ||
| 85 | clocks = <&axi>; | ||
| 86 | clock-output-names = "axi_dram"; | ||
| 87 | }; | ||
| 88 | |||
| 89 | ahb: ahb@01c20054 { | ||
| 90 | #clock-cells = <0>; | ||
| 91 | compatible = "allwinner,sun4i-ahb-clk"; | ||
| 92 | reg = <0x01c20054 0x4>; | ||
| 93 | clocks = <&axi>; | ||
| 94 | }; | ||
| 95 | |||
| 96 | ahb_gates: ahb_gates@01c20060 { | ||
| 97 | #clock-cells = <1>; | ||
| 98 | compatible = "allwinner,sun4i-ahb-gates-clk"; | ||
| 99 | reg = <0x01c20060 0x8>; | ||
| 100 | clocks = <&ahb>; | ||
| 101 | clock-output-names = "ahb_usb0", "ahb_ehci0", | ||
| 102 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | ||
| 103 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | ||
| 104 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | ||
| 105 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | ||
| 106 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | ||
| 107 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | ||
| 108 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | ||
| 109 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | ||
| 110 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | ||
| 111 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | ||
| 112 | }; | ||
| 113 | |||
| 114 | apb0: apb0@01c20054 { | ||
| 115 | #clock-cells = <0>; | ||
| 116 | compatible = "allwinner,sun4i-apb0-clk"; | ||
| 117 | reg = <0x01c20054 0x4>; | ||
| 118 | clocks = <&ahb>; | ||
| 119 | }; | ||
| 120 | |||
| 121 | apb0_gates: apb0_gates@01c20068 { | ||
| 122 | #clock-cells = <1>; | ||
| 123 | compatible = "allwinner,sun4i-apb0-gates-clk"; | ||
| 124 | reg = <0x01c20068 0x4>; | ||
| 125 | clocks = <&apb0>; | ||
| 126 | clock-output-names = "apb0_codec", "apb0_spdif", | ||
| 127 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | ||
| 128 | "apb0_ir1", "apb0_keypad"; | ||
| 129 | }; | ||
| 130 | |||
| 131 | /* dummy is pll62 */ | ||
| 132 | apb1_mux: apb1_mux@01c20058 { | ||
| 133 | #clock-cells = <0>; | ||
| 134 | compatible = "allwinner,sun4i-apb1-mux-clk"; | ||
| 135 | reg = <0x01c20058 0x4>; | ||
| 136 | clocks = <&osc24M>, <&dummy>, <&osc32k>; | ||
| 137 | }; | ||
| 138 | |||
| 139 | apb1: apb1@01c20058 { | ||
| 140 | #clock-cells = <0>; | ||
| 141 | compatible = "allwinner,sun4i-apb1-clk"; | ||
| 142 | reg = <0x01c20058 0x4>; | ||
| 143 | clocks = <&apb1_mux>; | ||
| 144 | }; | ||
| 145 | |||
| 146 | apb1_gates: apb1_gates@01c2006c { | ||
| 147 | #clock-cells = <1>; | ||
| 148 | compatible = "allwinner,sun4i-apb1-gates-clk"; | ||
| 149 | reg = <0x01c2006c 0x4>; | ||
| 150 | clocks = <&apb1>; | ||
| 151 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | ||
| 152 | "apb1_i2c2", "apb1_can", "apb1_scr", | ||
| 153 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | ||
| 154 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | ||
| 155 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | ||
| 156 | "apb1_uart7"; | ||
| 157 | }; | ||
| 158 | }; | ||
| 159 | |||
| 160 | soc@01c20000 { | ||
| 161 | compatible = "simple-bus"; | ||
| 162 | #address-cells = <1>; | ||
| 163 | #size-cells = <1>; | ||
| 164 | reg = <0x01c20000 0x300000>; | ||
| 165 | ranges; | ||
| 166 | |||
| 167 | emac: ethernet@01c0b000 { | ||
| 168 | compatible = "allwinner,sun4i-emac"; | ||
| 169 | reg = <0x01c0b000 0x1000>; | ||
| 170 | interrupts = <55>; | ||
| 171 | clocks = <&ahb_gates 17>; | ||
| 172 | status = "disabled"; | ||
| 173 | }; | ||
| 174 | |||
| 175 | mdio@01c0b080 { | ||
| 176 | compatible = "allwinner,sun4i-mdio"; | ||
| 177 | reg = <0x01c0b080 0x14>; | ||
| 178 | status = "disabled"; | ||
| 179 | #address-cells = <1>; | ||
| 180 | #size-cells = <0>; | ||
| 181 | }; | ||
| 182 | |||
| 183 | intc: interrupt-controller@01c20400 { | ||
| 184 | compatible = "allwinner,sun4i-ic"; | ||
| 185 | reg = <0x01c20400 0x400>; | ||
| 186 | interrupt-controller; | ||
| 187 | #interrupt-cells = <1>; | ||
| 188 | }; | ||
| 189 | |||
| 190 | pio: pinctrl@01c20800 { | ||
| 191 | compatible = "allwinner,sun5i-a10s-pinctrl"; | ||
| 192 | reg = <0x01c20800 0x400>; | ||
| 193 | interrupts = <28>; | ||
| 194 | clocks = <&apb0_gates 5>; | ||
| 195 | gpio-controller; | ||
| 196 | interrupt-controller; | ||
| 197 | #address-cells = <1>; | ||
| 198 | #size-cells = <0>; | ||
| 199 | #gpio-cells = <3>; | ||
| 200 | |||
| 201 | uart0_pins_a: uart0@0 { | ||
| 202 | allwinner,pins = "PB19", "PB20"; | ||
| 203 | allwinner,function = "uart0"; | ||
| 204 | allwinner,drive = <0>; | ||
| 205 | allwinner,pull = <0>; | ||
| 206 | }; | ||
| 207 | |||
| 208 | uart2_pins_a: uart2@0 { | ||
| 209 | allwinner,pins = "PC18", "PC19"; | ||
| 210 | allwinner,function = "uart2"; | ||
| 211 | allwinner,drive = <0>; | ||
| 212 | allwinner,pull = <0>; | ||
| 213 | }; | ||
| 214 | |||
| 215 | uart3_pins_a: uart3@0 { | ||
| 216 | allwinner,pins = "PG9", "PG10"; | ||
| 217 | allwinner,function = "uart3"; | ||
| 218 | allwinner,drive = <0>; | ||
| 219 | allwinner,pull = <0>; | ||
| 220 | }; | ||
| 221 | |||
| 222 | emac_pins_a: emac0@0 { | ||
| 223 | allwinner,pins = "PA0", "PA1", "PA2", | ||
| 224 | "PA3", "PA4", "PA5", "PA6", | ||
| 225 | "PA7", "PA8", "PA9", "PA10", | ||
| 226 | "PA11", "PA12", "PA13", "PA14", | ||
| 227 | "PA15", "PA16"; | ||
| 228 | allwinner,function = "emac"; | ||
| 229 | allwinner,drive = <0>; | ||
| 230 | allwinner,pull = <0>; | ||
| 231 | }; | ||
| 232 | }; | ||
| 233 | |||
| 234 | timer@01c20c00 { | ||
| 235 | compatible = "allwinner,sun4i-timer"; | ||
| 236 | reg = <0x01c20c00 0x90>; | ||
| 237 | interrupts = <22>; | ||
| 238 | clocks = <&osc24M>; | ||
| 239 | }; | ||
| 240 | |||
| 241 | wdt: watchdog@01c20c90 { | ||
| 242 | compatible = "allwinner,sun4i-wdt"; | ||
| 243 | reg = <0x01c20c90 0x10>; | ||
| 244 | }; | ||
| 245 | |||
| 246 | uart0: serial@01c28000 { | ||
| 247 | compatible = "snps,dw-apb-uart"; | ||
| 248 | reg = <0x01c28000 0x400>; | ||
| 249 | interrupts = <1>; | ||
| 250 | reg-shift = <2>; | ||
| 251 | reg-io-width = <4>; | ||
| 252 | clocks = <&apb1_gates 16>; | ||
| 253 | status = "disabled"; | ||
| 254 | }; | ||
| 255 | |||
| 256 | uart1: serial@01c28400 { | ||
| 257 | compatible = "snps,dw-apb-uart"; | ||
| 258 | reg = <0x01c28400 0x400>; | ||
| 259 | interrupts = <2>; | ||
| 260 | reg-shift = <2>; | ||
| 261 | reg-io-width = <4>; | ||
| 262 | clocks = <&apb1_gates 17>; | ||
| 263 | status = "disabled"; | ||
| 264 | }; | ||
| 265 | |||
| 266 | uart2: serial@01c28800 { | ||
| 267 | compatible = "snps,dw-apb-uart"; | ||
| 268 | reg = <0x01c28800 0x400>; | ||
| 269 | interrupts = <3>; | ||
| 270 | reg-shift = <2>; | ||
| 271 | reg-io-width = <4>; | ||
| 272 | clocks = <&apb1_gates 18>; | ||
| 273 | status = "disabled"; | ||
| 274 | }; | ||
| 275 | |||
| 276 | uart3: serial@01c28c00 { | ||
| 277 | compatible = "snps,dw-apb-uart"; | ||
| 278 | reg = <0x01c28c00 0x400>; | ||
| 279 | interrupts = <4>; | ||
| 280 | reg-shift = <2>; | ||
| 281 | reg-io-width = <4>; | ||
| 282 | clocks = <&apb1_gates 19>; | ||
| 283 | status = "disabled"; | ||
| 284 | }; | ||
| 285 | }; | ||
| 286 | }; | ||
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 3ca55067f868..80497e376706 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts | |||
| @@ -37,6 +37,24 @@ | |||
| 37 | pinctrl-0 = <&uart1_pins_b>; | 37 | pinctrl-0 = <&uart1_pins_b>; |
| 38 | status = "okay"; | 38 | status = "okay"; |
| 39 | }; | 39 | }; |
| 40 | |||
| 41 | i2c0: i2c@01c2ac00 { | ||
| 42 | pinctrl-names = "default"; | ||
| 43 | pinctrl-0 = <&i2c0_pins_a>; | ||
| 44 | status = "okay"; | ||
| 45 | }; | ||
| 46 | |||
| 47 | i2c1: i2c@01c2b000 { | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | pinctrl-0 = <&i2c1_pins_a>; | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | i2c2: i2c@01c2b400 { | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | pinctrl-0 = <&i2c2_pins_a>; | ||
| 56 | status = "okay"; | ||
| 57 | }; | ||
| 40 | }; | 58 | }; |
| 41 | 59 | ||
| 42 | leds { | 60 | leds { |
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 31fa38f8cc98..7363211daf84 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi | |||
| @@ -17,8 +17,12 @@ | |||
| 17 | interrupt-parent = <&intc>; | 17 | interrupt-parent = <&intc>; |
| 18 | 18 | ||
| 19 | cpus { | 19 | cpus { |
| 20 | #address-cells = <1>; | ||
| 21 | #size-cells = <0>; | ||
| 20 | cpu@0 { | 22 | cpu@0 { |
| 23 | device_type = "cpu"; | ||
| 21 | compatible = "arm,cortex-a8"; | 24 | compatible = "arm,cortex-a8"; |
| 25 | reg = <0x0>; | ||
| 22 | }; | 26 | }; |
| 23 | }; | 27 | }; |
| 24 | 28 | ||
| @@ -95,20 +99,15 @@ | |||
| 95 | 99 | ||
| 96 | ahb_gates: ahb_gates@01c20060 { | 100 | ahb_gates: ahb_gates@01c20060 { |
| 97 | #clock-cells = <1>; | 101 | #clock-cells = <1>; |
| 98 | compatible = "allwinner,sun4i-ahb-gates-clk"; | 102 | compatible = "allwinner,sun5i-a13-ahb-gates-clk"; |
| 99 | reg = <0x01c20060 0x8>; | 103 | reg = <0x01c20060 0x8>; |
| 100 | clocks = <&ahb>; | 104 | clocks = <&ahb>; |
| 101 | clock-output-names = "ahb_usb0", "ahb_ehci0", | 105 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
| 102 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | 106 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", |
| 103 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | 107 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", |
| 104 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | 108 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer", |
| 105 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | 109 | "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be", |
| 106 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | 110 | "ahb_de_fe", "ahb_iep", "ahb_mali400"; |
| 107 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | ||
| 108 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | ||
| 109 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | ||
| 110 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | ||
| 111 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | ||
| 112 | }; | 111 | }; |
| 113 | 112 | ||
| 114 | apb0: apb0@01c20054 { | 113 | apb0: apb0@01c20054 { |
| @@ -120,15 +119,13 @@ | |||
| 120 | 119 | ||
| 121 | apb0_gates: apb0_gates@01c20068 { | 120 | apb0_gates: apb0_gates@01c20068 { |
| 122 | #clock-cells = <1>; | 121 | #clock-cells = <1>; |
| 123 | compatible = "allwinner,sun4i-apb0-gates-clk"; | 122 | compatible = "allwinner,sun5i-a13-apb0-gates-clk"; |
| 124 | reg = <0x01c20068 0x4>; | 123 | reg = <0x01c20068 0x4>; |
| 125 | clocks = <&apb0>; | 124 | clocks = <&apb0>; |
| 126 | clock-output-names = "apb0_codec", "apb0_spdif", | 125 | clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; |
| 127 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | ||
| 128 | "apb0_ir1", "apb0_keypad"; | ||
| 129 | }; | 126 | }; |
| 130 | 127 | ||
| 131 | /* dummy is pll62 */ | 128 | /* dummy is pll6 */ |
| 132 | apb1_mux: apb1_mux@01c20058 { | 129 | apb1_mux: apb1_mux@01c20058 { |
| 133 | #clock-cells = <0>; | 130 | #clock-cells = <0>; |
| 134 | compatible = "allwinner,sun4i-apb1-mux-clk"; | 131 | compatible = "allwinner,sun4i-apb1-mux-clk"; |
| @@ -145,15 +142,11 @@ | |||
| 145 | 142 | ||
| 146 | apb1_gates: apb1_gates@01c2006c { | 143 | apb1_gates: apb1_gates@01c2006c { |
| 147 | #clock-cells = <1>; | 144 | #clock-cells = <1>; |
| 148 | compatible = "allwinner,sun4i-apb1-gates-clk"; | 145 | compatible = "allwinner,sun5i-a13-apb1-gates-clk"; |
| 149 | reg = <0x01c2006c 0x4>; | 146 | reg = <0x01c2006c 0x4>; |
| 150 | clocks = <&apb1>; | 147 | clocks = <&apb1>; |
| 151 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | 148 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
| 152 | "apb1_i2c2", "apb1_can", "apb1_scr", | 149 | "apb1_i2c2", "apb1_uart1", "apb1_uart3"; |
| 153 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | ||
| 154 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | ||
| 155 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | ||
| 156 | "apb1_uart7"; | ||
| 157 | }; | 150 | }; |
| 158 | }; | 151 | }; |
| 159 | 152 | ||
| @@ -174,8 +167,10 @@ | |||
| 174 | pio: pinctrl@01c20800 { | 167 | pio: pinctrl@01c20800 { |
| 175 | compatible = "allwinner,sun5i-a13-pinctrl"; | 168 | compatible = "allwinner,sun5i-a13-pinctrl"; |
| 176 | reg = <0x01c20800 0x400>; | 169 | reg = <0x01c20800 0x400>; |
| 170 | interrupts = <28>; | ||
| 177 | clocks = <&apb0_gates 5>; | 171 | clocks = <&apb0_gates 5>; |
| 178 | gpio-controller; | 172 | gpio-controller; |
| 173 | interrupt-controller; | ||
| 179 | #address-cells = <1>; | 174 | #address-cells = <1>; |
| 180 | #size-cells = <0>; | 175 | #size-cells = <0>; |
| 181 | #gpio-cells = <3>; | 176 | #gpio-cells = <3>; |
| @@ -193,6 +188,27 @@ | |||
| 193 | allwinner,drive = <0>; | 188 | allwinner,drive = <0>; |
| 194 | allwinner,pull = <0>; | 189 | allwinner,pull = <0>; |
| 195 | }; | 190 | }; |
| 191 | |||
| 192 | i2c0_pins_a: i2c0@0 { | ||
| 193 | allwinner,pins = "PB0", "PB1"; | ||
| 194 | allwinner,function = "i2c0"; | ||
| 195 | allwinner,drive = <0>; | ||
| 196 | allwinner,pull = <0>; | ||
| 197 | }; | ||
| 198 | |||
| 199 | i2c1_pins_a: i2c1@0 { | ||
| 200 | allwinner,pins = "PB15", "PB16"; | ||
| 201 | allwinner,function = "i2c1"; | ||
| 202 | allwinner,drive = <0>; | ||
| 203 | allwinner,pull = <0>; | ||
| 204 | }; | ||
| 205 | |||
| 206 | i2c2_pins_a: i2c2@0 { | ||
| 207 | allwinner,pins = "PB17", "PB18"; | ||
| 208 | allwinner,function = "i2c2"; | ||
| 209 | allwinner,drive = <0>; | ||
| 210 | allwinner,pull = <0>; | ||
| 211 | }; | ||
| 196 | }; | 212 | }; |
| 197 | 213 | ||
| 198 | timer@01c20c00 { | 214 | timer@01c20c00 { |
| @@ -226,5 +242,32 @@ | |||
| 226 | clocks = <&apb1_gates 19>; | 242 | clocks = <&apb1_gates 19>; |
| 227 | status = "disabled"; | 243 | status = "disabled"; |
| 228 | }; | 244 | }; |
| 245 | |||
| 246 | i2c0: i2c@01c2ac00 { | ||
| 247 | compatible = "allwinner,sun4i-i2c"; | ||
| 248 | reg = <0x01c2ac00 0x400>; | ||
| 249 | interrupts = <7>; | ||
| 250 | clocks = <&apb1_gates 0>; | ||
| 251 | clock-frequency = <100000>; | ||
| 252 | status = "disabled"; | ||
| 253 | }; | ||
| 254 | |||
| 255 | i2c1: i2c@01c2b000 { | ||
| 256 | compatible = "allwinner,sun4i-i2c"; | ||
| 257 | reg = <0x01c2b000 0x400>; | ||
| 258 | interrupts = <8>; | ||
| 259 | clocks = <&apb1_gates 1>; | ||
| 260 | clock-frequency = <100000>; | ||
| 261 | status = "disabled"; | ||
| 262 | }; | ||
| 263 | |||
| 264 | i2c2: i2c@01c2b400 { | ||
| 265 | compatible = "allwinner,sun4i-i2c"; | ||
| 266 | reg = <0x01c2b400 0x400>; | ||
| 267 | interrupts = <9>; | ||
| 268 | clocks = <&apb1_gates 2>; | ||
| 269 | clock-frequency = <100000>; | ||
| 270 | status = "disabled"; | ||
| 271 | }; | ||
| 229 | }; | 272 | }; |
| 230 | }; | 273 | }; |
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 72c1f27af7f3..cb640eb6c932 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra114.dtsi" | 3 | #include "tegra114.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "NVIDIA Tegra114 Dalmore evaluation board"; | 6 | model = "NVIDIA Tegra114 Dalmore evaluation board"; |
| @@ -727,6 +727,16 @@ | |||
| 727 | battery-name = "battery"; | 727 | battery-name = "battery"; |
| 728 | sbs,i2c-retry-count = <2>; | 728 | sbs,i2c-retry-count = <2>; |
| 729 | sbs,poll-retry-count = <100>; | 729 | sbs,poll-retry-count = <100>; |
| 730 | power-supplies = <&charger>; | ||
| 731 | }; | ||
| 732 | |||
| 733 | rt5640: rt5640 { | ||
| 734 | compatible = "realtek,rt5640"; | ||
| 735 | reg = <0x1c>; | ||
| 736 | interrupt-parent = <&gpio>; | ||
| 737 | interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>; | ||
| 738 | realtek,ldo1-en-gpios = | ||
| 739 | <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; | ||
| 730 | }; | 740 | }; |
| 731 | }; | 741 | }; |
| 732 | 742 | ||
| @@ -748,7 +758,7 @@ | |||
| 748 | compatible = "ti,tps65090"; | 758 | compatible = "ti,tps65090"; |
| 749 | reg = <0x48>; | 759 | reg = <0x48>; |
| 750 | interrupt-parent = <&gpio>; | 760 | interrupt-parent = <&gpio>; |
| 751 | interrupts = <72 0x04>; /* gpio PJ0 */ | 761 | interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>; |
| 752 | 762 | ||
| 753 | vsys1-supply = <&vdd_ac_bat_reg>; | 763 | vsys1-supply = <&vdd_ac_bat_reg>; |
| 754 | vsys2-supply = <&vdd_ac_bat_reg>; | 764 | vsys2-supply = <&vdd_ac_bat_reg>; |
| @@ -763,6 +773,11 @@ | |||
| 763 | vsys-l1-supply = <&vdd_ac_bat_reg>; | 773 | vsys-l1-supply = <&vdd_ac_bat_reg>; |
| 764 | vsys-l2-supply = <&vdd_ac_bat_reg>; | 774 | vsys-l2-supply = <&vdd_ac_bat_reg>; |
| 765 | 775 | ||
| 776 | charger: charger { | ||
| 777 | compatible = "ti,tps65090-charger"; | ||
| 778 | ti,enable-low-current-chrg; | ||
| 779 | }; | ||
| 780 | |||
| 766 | regulators { | 781 | regulators { |
| 767 | tps65090_dcdc1_reg: dcdc1 { | 782 | tps65090_dcdc1_reg: dcdc1 { |
| 768 | regulator-name = "vdd-sys-5v0"; | 783 | regulator-name = "vdd-sys-5v0"; |
| @@ -823,12 +838,28 @@ | |||
| 823 | }; | 838 | }; |
| 824 | }; | 839 | }; |
| 825 | 840 | ||
| 841 | spi@7000da00 { | ||
| 842 | status = "okay"; | ||
| 843 | spi-max-frequency = <25000000>; | ||
| 844 | spi-flash@0 { | ||
| 845 | compatible = "winbond,w25q32dw"; | ||
| 846 | reg = <0>; | ||
| 847 | spi-max-frequency = <20000000>; | ||
| 848 | }; | ||
| 849 | }; | ||
| 850 | |||
| 826 | pmc { | 851 | pmc { |
| 827 | nvidia,invert-interrupt; | 852 | nvidia,invert-interrupt; |
| 828 | }; | 853 | }; |
| 829 | 854 | ||
| 855 | ahub { | ||
| 856 | i2s@70080400 { | ||
| 857 | status = "okay"; | ||
| 858 | }; | ||
| 859 | }; | ||
| 860 | |||
| 830 | sdhci@78000400 { | 861 | sdhci@78000400 { |
| 831 | cd-gpios = <&gpio 170 1>; /* gpio PV2 */ | 862 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 832 | bus-width = <4>; | 863 | bus-width = <4>; |
| 833 | status = "okay"; | 864 | status = "okay"; |
| 834 | }; | 865 | }; |
| @@ -873,7 +904,7 @@ | |||
| 873 | regulator-min-microvolt = <1800000>; | 904 | regulator-min-microvolt = <1800000>; |
| 874 | regulator-max-microvolt = <1800000>; | 905 | regulator-max-microvolt = <1800000>; |
| 875 | enable-active-high; | 906 | enable-active-high; |
| 876 | gpio = <&gpio 61 0>; /* GPIO PH5 */ | 907 | gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; |
| 877 | }; | 908 | }; |
| 878 | 909 | ||
| 879 | lcd_bl_en_reg: regulator@2 { | 910 | lcd_bl_en_reg: regulator@2 { |
| @@ -883,7 +914,7 @@ | |||
| 883 | regulator-min-microvolt = <5000000>; | 914 | regulator-min-microvolt = <5000000>; |
| 884 | regulator-max-microvolt = <5000000>; | 915 | regulator-max-microvolt = <5000000>; |
| 885 | enable-active-high; | 916 | enable-active-high; |
| 886 | gpio = <&gpio 58 0>; /* GPIO PH2 */ | 917 | gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| 887 | }; | 918 | }; |
| 888 | 919 | ||
| 889 | usb1_vbus_reg: regulator@3 { | 920 | usb1_vbus_reg: regulator@3 { |
| @@ -893,7 +924,7 @@ | |||
| 893 | regulator-min-microvolt = <5000000>; | 924 | regulator-min-microvolt = <5000000>; |
| 894 | regulator-max-microvolt = <5000000>; | 925 | regulator-max-microvolt = <5000000>; |
| 895 | enable-active-high; | 926 | enable-active-high; |
| 896 | gpio = <&gpio 108 0>; /* GPIO PN4 */ | 927 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; |
| 897 | gpio-open-drain; | 928 | gpio-open-drain; |
| 898 | vin-supply = <&tps65090_dcdc1_reg>; | 929 | vin-supply = <&tps65090_dcdc1_reg>; |
| 899 | }; | 930 | }; |
| @@ -905,7 +936,7 @@ | |||
| 905 | regulator-min-microvolt = <5000000>; | 936 | regulator-min-microvolt = <5000000>; |
| 906 | regulator-max-microvolt = <5000000>; | 937 | regulator-max-microvolt = <5000000>; |
| 907 | enable-active-high; | 938 | enable-active-high; |
| 908 | gpio = <&gpio 86 0>; /* GPIO PK6 */ | 939 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
| 909 | gpio-open-drain; | 940 | gpio-open-drain; |
| 910 | vin-supply = <&tps65090_dcdc1_reg>; | 941 | vin-supply = <&tps65090_dcdc1_reg>; |
| 911 | }; | 942 | }; |
| @@ -917,8 +948,32 @@ | |||
| 917 | regulator-min-microvolt = <5000000>; | 948 | regulator-min-microvolt = <5000000>; |
| 918 | regulator-max-microvolt = <5000000>; | 949 | regulator-max-microvolt = <5000000>; |
| 919 | enable-active-high; | 950 | enable-active-high; |
| 920 | gpio = <&gpio 81 0>; /* GPIO PK1 */ | 951 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; |
| 921 | vin-supply = <&tps65090_dcdc1_reg>; | 952 | vin-supply = <&tps65090_dcdc1_reg>; |
| 922 | }; | 953 | }; |
| 923 | }; | 954 | }; |
| 955 | |||
| 956 | sound { | ||
| 957 | compatible = "nvidia,tegra-audio-rt5640-dalmore", | ||
| 958 | "nvidia,tegra-audio-rt5640"; | ||
| 959 | nvidia,model = "NVIDIA Tegra Dalmore"; | ||
| 960 | |||
| 961 | nvidia,audio-routing = | ||
| 962 | "Headphones", "HPOR", | ||
| 963 | "Headphones", "HPOL", | ||
| 964 | "Speakers", "SPORP", | ||
| 965 | "Speakers", "SPORN", | ||
| 966 | "Speakers", "SPOLP", | ||
| 967 | "Speakers", "SPOLN"; | ||
| 968 | |||
| 969 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
| 970 | nvidia,audio-codec = <&rt5640>; | ||
| 971 | |||
| 972 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; | ||
| 973 | |||
| 974 | clocks = <&tegra_car TEGRA114_CLK_PLL_A>, | ||
| 975 | <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, | ||
| 976 | <&tegra_car TEGRA114_CLK_EXTERN1>; | ||
| 977 | clock-names = "pll_a", "pll_a_out0", "mclk"; | ||
| 978 | }; | ||
| 924 | }; | 979 | }; |
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts index 6bbc8efae9c0..d5f8d3e0bde2 100644 --- a/arch/arm/boot/dts/tegra114-pluto.dts +++ b/arch/arm/boot/dts/tegra114-pluto.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra114.dtsi" | 3 | #include "tegra114.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "NVIDIA Tegra114 Pluto evaluation board"; | 6 | model = "NVIDIA Tegra114 Pluto evaluation board"; |
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 629415ffd8dc..abf6c40d28c6 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi | |||
| @@ -1,4 +1,8 @@ | |||
| 1 | /include/ "skeleton.dtsi" | 1 | #include <dt-bindings/clock/tegra114-car.h> |
| 2 | #include <dt-bindings/gpio/tegra-gpio.h> | ||
| 3 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 4 | |||
| 5 | #include "skeleton.dtsi" | ||
| 2 | 6 | ||
| 3 | / { | 7 | / { |
| 4 | compatible = "nvidia,tegra114"; | 8 | compatible = "nvidia,tegra114"; |
| @@ -19,19 +23,20 @@ | |||
| 19 | <0x50042000 0x1000>, | 23 | <0x50042000 0x1000>, |
| 20 | <0x50044000 0x2000>, | 24 | <0x50044000 0x2000>, |
| 21 | <0x50046000 0x2000>; | 25 | <0x50046000 0x2000>; |
| 22 | interrupts = <1 9 0xf04>; | 26 | interrupts = <GIC_PPI 9 |
| 27 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | ||
| 23 | }; | 28 | }; |
| 24 | 29 | ||
| 25 | timer@60005000 { | 30 | timer@60005000 { |
| 26 | compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; | 31 | compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; |
| 27 | reg = <0x60005000 0x400>; | 32 | reg = <0x60005000 0x400>; |
| 28 | interrupts = <0 0 0x04 | 33 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 29 | 0 1 0x04 | 34 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 30 | 0 41 0x04 | 35 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 31 | 0 42 0x04 | 36 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 32 | 0 121 0x04 | 37 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 33 | 0 122 0x04>; | 38 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
| 34 | clocks = <&tegra_car 5>; | 39 | clocks = <&tegra_car TEGRA114_CLK_TIMER>; |
| 35 | }; | 40 | }; |
| 36 | 41 | ||
| 37 | tegra_car: clock { | 42 | tegra_car: clock { |
| @@ -43,39 +48,39 @@ | |||
| 43 | apbdma: dma { | 48 | apbdma: dma { |
| 44 | compatible = "nvidia,tegra114-apbdma"; | 49 | compatible = "nvidia,tegra114-apbdma"; |
| 45 | reg = <0x6000a000 0x1400>; | 50 | reg = <0x6000a000 0x1400>; |
| 46 | interrupts = <0 104 0x04 | 51 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 47 | 0 105 0x04 | 52 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 48 | 0 106 0x04 | 53 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 49 | 0 107 0x04 | 54 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 50 | 0 108 0x04 | 55 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 51 | 0 109 0x04 | 56 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 52 | 0 110 0x04 | 57 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 53 | 0 111 0x04 | 58 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 54 | 0 112 0x04 | 59 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 55 | 0 113 0x04 | 60 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 56 | 0 114 0x04 | 61 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 57 | 0 115 0x04 | 62 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 58 | 0 116 0x04 | 63 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 59 | 0 117 0x04 | 64 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 60 | 0 118 0x04 | 65 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 61 | 0 119 0x04 | 66 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 62 | 0 128 0x04 | 67 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 63 | 0 129 0x04 | 68 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 64 | 0 130 0x04 | 69 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 65 | 0 131 0x04 | 70 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 66 | 0 132 0x04 | 71 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 67 | 0 133 0x04 | 72 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 68 | 0 134 0x04 | 73 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 69 | 0 135 0x04 | 74 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 70 | 0 136 0x04 | 75 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 71 | 0 137 0x04 | 76 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 72 | 0 138 0x04 | 77 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 73 | 0 139 0x04 | 78 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 74 | 0 140 0x04 | 79 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 75 | 0 141 0x04 | 80 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | 0 142 0x04 | 81 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 77 | 0 143 0x04>; | 82 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| 78 | clocks = <&tegra_car 34>; | 83 | clocks = <&tegra_car TEGRA114_CLK_APBDMA>; |
| 79 | }; | 84 | }; |
| 80 | 85 | ||
| 81 | ahb: ahb { | 86 | ahb: ahb { |
| @@ -86,14 +91,14 @@ | |||
| 86 | gpio: gpio { | 91 | gpio: gpio { |
| 87 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; | 92 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; |
| 88 | reg = <0x6000d000 0x1000>; | 93 | reg = <0x6000d000 0x1000>; |
| 89 | interrupts = <0 32 0x04 | 94 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 90 | 0 33 0x04 | 95 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 91 | 0 34 0x04 | 96 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 92 | 0 35 0x04 | 97 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 93 | 0 55 0x04 | 98 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 94 | 0 87 0x04 | 99 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 95 | 0 89 0x04 | 100 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 96 | 0 125 0x04>; | 101 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| 97 | #gpio-cells = <2>; | 102 | #gpio-cells = <2>; |
| 98 | gpio-controller; | 103 | gpio-controller; |
| 99 | #interrupt-cells = <2>; | 104 | #interrupt-cells = <2>; |
| @@ -118,57 +123,57 @@ | |||
| 118 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | 123 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 119 | reg = <0x70006000 0x40>; | 124 | reg = <0x70006000 0x40>; |
| 120 | reg-shift = <2>; | 125 | reg-shift = <2>; |
| 121 | interrupts = <0 36 0x04>; | 126 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 122 | nvidia,dma-request-selector = <&apbdma 8>; | 127 | nvidia,dma-request-selector = <&apbdma 8>; |
| 123 | status = "disabled"; | 128 | status = "disabled"; |
| 124 | clocks = <&tegra_car 6>; | 129 | clocks = <&tegra_car TEGRA114_CLK_UARTA>; |
| 125 | }; | 130 | }; |
| 126 | 131 | ||
| 127 | uartb: serial@70006040 { | 132 | uartb: serial@70006040 { |
| 128 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | 133 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 129 | reg = <0x70006040 0x40>; | 134 | reg = <0x70006040 0x40>; |
| 130 | reg-shift = <2>; | 135 | reg-shift = <2>; |
| 131 | interrupts = <0 37 0x04>; | 136 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 132 | nvidia,dma-request-selector = <&apbdma 9>; | 137 | nvidia,dma-request-selector = <&apbdma 9>; |
| 133 | status = "disabled"; | 138 | status = "disabled"; |
| 134 | clocks = <&tegra_car 192>; | 139 | clocks = <&tegra_car TEGRA114_CLK_UARTB>; |
| 135 | }; | 140 | }; |
| 136 | 141 | ||
| 137 | uartc: serial@70006200 { | 142 | uartc: serial@70006200 { |
| 138 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | 143 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 139 | reg = <0x70006200 0x100>; | 144 | reg = <0x70006200 0x100>; |
| 140 | reg-shift = <2>; | 145 | reg-shift = <2>; |
| 141 | interrupts = <0 46 0x04>; | 146 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 142 | nvidia,dma-request-selector = <&apbdma 10>; | 147 | nvidia,dma-request-selector = <&apbdma 10>; |
| 143 | status = "disabled"; | 148 | status = "disabled"; |
| 144 | clocks = <&tegra_car 55>; | 149 | clocks = <&tegra_car TEGRA114_CLK_UARTC>; |
| 145 | }; | 150 | }; |
| 146 | 151 | ||
| 147 | uartd: serial@70006300 { | 152 | uartd: serial@70006300 { |
| 148 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; | 153 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 149 | reg = <0x70006300 0x100>; | 154 | reg = <0x70006300 0x100>; |
| 150 | reg-shift = <2>; | 155 | reg-shift = <2>; |
| 151 | interrupts = <0 90 0x04>; | 156 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| 152 | nvidia,dma-request-selector = <&apbdma 19>; | 157 | nvidia,dma-request-selector = <&apbdma 19>; |
| 153 | status = "disabled"; | 158 | status = "disabled"; |
| 154 | clocks = <&tegra_car 65>; | 159 | clocks = <&tegra_car TEGRA114_CLK_UARTD>; |
| 155 | }; | 160 | }; |
| 156 | 161 | ||
| 157 | pwm: pwm { | 162 | pwm: pwm { |
| 158 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; | 163 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; |
| 159 | reg = <0x7000a000 0x100>; | 164 | reg = <0x7000a000 0x100>; |
| 160 | #pwm-cells = <2>; | 165 | #pwm-cells = <2>; |
| 161 | clocks = <&tegra_car 17>; | 166 | clocks = <&tegra_car TEGRA114_CLK_PWM>; |
| 162 | status = "disabled"; | 167 | status = "disabled"; |
| 163 | }; | 168 | }; |
| 164 | 169 | ||
| 165 | i2c@7000c000 { | 170 | i2c@7000c000 { |
| 166 | compatible = "nvidia,tegra114-i2c"; | 171 | compatible = "nvidia,tegra114-i2c"; |
| 167 | reg = <0x7000c000 0x100>; | 172 | reg = <0x7000c000 0x100>; |
| 168 | interrupts = <0 38 0x04>; | 173 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 169 | #address-cells = <1>; | 174 | #address-cells = <1>; |
| 170 | #size-cells = <0>; | 175 | #size-cells = <0>; |
| 171 | clocks = <&tegra_car 12>; | 176 | clocks = <&tegra_car TEGRA114_CLK_I2C1>; |
| 172 | clock-names = "div-clk"; | 177 | clock-names = "div-clk"; |
| 173 | status = "disabled"; | 178 | status = "disabled"; |
| 174 | }; | 179 | }; |
| @@ -176,10 +181,10 @@ | |||
| 176 | i2c@7000c400 { | 181 | i2c@7000c400 { |
| 177 | compatible = "nvidia,tegra114-i2c"; | 182 | compatible = "nvidia,tegra114-i2c"; |
| 178 | reg = <0x7000c400 0x100>; | 183 | reg = <0x7000c400 0x100>; |
| 179 | interrupts = <0 84 0x04>; | 184 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 180 | #address-cells = <1>; | 185 | #address-cells = <1>; |
| 181 | #size-cells = <0>; | 186 | #size-cells = <0>; |
| 182 | clocks = <&tegra_car 54>; | 187 | clocks = <&tegra_car TEGRA114_CLK_I2C2>; |
| 183 | clock-names = "div-clk"; | 188 | clock-names = "div-clk"; |
| 184 | status = "disabled"; | 189 | status = "disabled"; |
| 185 | }; | 190 | }; |
| @@ -187,10 +192,10 @@ | |||
| 187 | i2c@7000c500 { | 192 | i2c@7000c500 { |
| 188 | compatible = "nvidia,tegra114-i2c"; | 193 | compatible = "nvidia,tegra114-i2c"; |
| 189 | reg = <0x7000c500 0x100>; | 194 | reg = <0x7000c500 0x100>; |
| 190 | interrupts = <0 92 0x04>; | 195 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 191 | #address-cells = <1>; | 196 | #address-cells = <1>; |
| 192 | #size-cells = <0>; | 197 | #size-cells = <0>; |
| 193 | clocks = <&tegra_car 67>; | 198 | clocks = <&tegra_car TEGRA114_CLK_I2C3>; |
| 194 | clock-names = "div-clk"; | 199 | clock-names = "div-clk"; |
| 195 | status = "disabled"; | 200 | status = "disabled"; |
| 196 | }; | 201 | }; |
| @@ -198,10 +203,10 @@ | |||
| 198 | i2c@7000c700 { | 203 | i2c@7000c700 { |
| 199 | compatible = "nvidia,tegra114-i2c"; | 204 | compatible = "nvidia,tegra114-i2c"; |
| 200 | reg = <0x7000c700 0x100>; | 205 | reg = <0x7000c700 0x100>; |
| 201 | interrupts = <0 120 0x04>; | 206 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 202 | #address-cells = <1>; | 207 | #address-cells = <1>; |
| 203 | #size-cells = <0>; | 208 | #size-cells = <0>; |
| 204 | clocks = <&tegra_car 103>; | 209 | clocks = <&tegra_car TEGRA114_CLK_I2C4>; |
| 205 | clock-names = "div-clk"; | 210 | clock-names = "div-clk"; |
| 206 | status = "disabled"; | 211 | status = "disabled"; |
| 207 | }; | 212 | }; |
| @@ -209,10 +214,10 @@ | |||
| 209 | i2c@7000d000 { | 214 | i2c@7000d000 { |
| 210 | compatible = "nvidia,tegra114-i2c"; | 215 | compatible = "nvidia,tegra114-i2c"; |
| 211 | reg = <0x7000d000 0x100>; | 216 | reg = <0x7000d000 0x100>; |
| 212 | interrupts = <0 53 0x04>; | 217 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 213 | #address-cells = <1>; | 218 | #address-cells = <1>; |
| 214 | #size-cells = <0>; | 219 | #size-cells = <0>; |
| 215 | clocks = <&tegra_car 47>; | 220 | clocks = <&tegra_car TEGRA114_CLK_I2C5>; |
| 216 | clock-names = "div-clk"; | 221 | clock-names = "div-clk"; |
| 217 | status = "disabled"; | 222 | status = "disabled"; |
| 218 | }; | 223 | }; |
| @@ -220,11 +225,11 @@ | |||
| 220 | spi@7000d400 { | 225 | spi@7000d400 { |
| 221 | compatible = "nvidia,tegra114-spi"; | 226 | compatible = "nvidia,tegra114-spi"; |
| 222 | reg = <0x7000d400 0x200>; | 227 | reg = <0x7000d400 0x200>; |
| 223 | interrupts = <0 59 0x04>; | 228 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 224 | nvidia,dma-request-selector = <&apbdma 15>; | 229 | nvidia,dma-request-selector = <&apbdma 15>; |
| 225 | #address-cells = <1>; | 230 | #address-cells = <1>; |
| 226 | #size-cells = <0>; | 231 | #size-cells = <0>; |
| 227 | clocks = <&tegra_car 41>; | 232 | clocks = <&tegra_car TEGRA114_CLK_SBC1>; |
| 228 | clock-names = "spi"; | 233 | clock-names = "spi"; |
| 229 | status = "disabled"; | 234 | status = "disabled"; |
| 230 | }; | 235 | }; |
| @@ -232,11 +237,11 @@ | |||
| 232 | spi@7000d600 { | 237 | spi@7000d600 { |
| 233 | compatible = "nvidia,tegra114-spi"; | 238 | compatible = "nvidia,tegra114-spi"; |
| 234 | reg = <0x7000d600 0x200>; | 239 | reg = <0x7000d600 0x200>; |
| 235 | interrupts = <0 82 0x04>; | 240 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 236 | nvidia,dma-request-selector = <&apbdma 16>; | 241 | nvidia,dma-request-selector = <&apbdma 16>; |
| 237 | #address-cells = <1>; | 242 | #address-cells = <1>; |
| 238 | #size-cells = <0>; | 243 | #size-cells = <0>; |
| 239 | clocks = <&tegra_car 44>; | 244 | clocks = <&tegra_car TEGRA114_CLK_SBC2>; |
| 240 | clock-names = "spi"; | 245 | clock-names = "spi"; |
| 241 | status = "disabled"; | 246 | status = "disabled"; |
| 242 | }; | 247 | }; |
| @@ -244,11 +249,11 @@ | |||
| 244 | spi@7000d800 { | 249 | spi@7000d800 { |
| 245 | compatible = "nvidia,tegra114-spi"; | 250 | compatible = "nvidia,tegra114-spi"; |
| 246 | reg = <0x7000d800 0x200>; | 251 | reg = <0x7000d800 0x200>; |
| 247 | interrupts = <0 83 0x04>; | 252 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 248 | nvidia,dma-request-selector = <&apbdma 17>; | 253 | nvidia,dma-request-selector = <&apbdma 17>; |
| 249 | #address-cells = <1>; | 254 | #address-cells = <1>; |
| 250 | #size-cells = <0>; | 255 | #size-cells = <0>; |
| 251 | clocks = <&tegra_car 46>; | 256 | clocks = <&tegra_car TEGRA114_CLK_SBC3>; |
| 252 | clock-names = "spi"; | 257 | clock-names = "spi"; |
| 253 | status = "disabled"; | 258 | status = "disabled"; |
| 254 | }; | 259 | }; |
| @@ -256,11 +261,11 @@ | |||
| 256 | spi@7000da00 { | 261 | spi@7000da00 { |
| 257 | compatible = "nvidia,tegra114-spi"; | 262 | compatible = "nvidia,tegra114-spi"; |
| 258 | reg = <0x7000da00 0x200>; | 263 | reg = <0x7000da00 0x200>; |
| 259 | interrupts = <0 93 0x04>; | 264 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 260 | nvidia,dma-request-selector = <&apbdma 18>; | 265 | nvidia,dma-request-selector = <&apbdma 18>; |
| 261 | #address-cells = <1>; | 266 | #address-cells = <1>; |
| 262 | #size-cells = <0>; | 267 | #size-cells = <0>; |
| 263 | clocks = <&tegra_car 68>; | 268 | clocks = <&tegra_car TEGRA114_CLK_SBC4>; |
| 264 | clock-names = "spi"; | 269 | clock-names = "spi"; |
| 265 | status = "disabled"; | 270 | status = "disabled"; |
| 266 | }; | 271 | }; |
| @@ -268,11 +273,11 @@ | |||
| 268 | spi@7000dc00 { | 273 | spi@7000dc00 { |
| 269 | compatible = "nvidia,tegra114-spi"; | 274 | compatible = "nvidia,tegra114-spi"; |
| 270 | reg = <0x7000dc00 0x200>; | 275 | reg = <0x7000dc00 0x200>; |
| 271 | interrupts = <0 94 0x04>; | 276 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 272 | nvidia,dma-request-selector = <&apbdma 27>; | 277 | nvidia,dma-request-selector = <&apbdma 27>; |
| 273 | #address-cells = <1>; | 278 | #address-cells = <1>; |
| 274 | #size-cells = <0>; | 279 | #size-cells = <0>; |
| 275 | clocks = <&tegra_car 104>; | 280 | clocks = <&tegra_car TEGRA114_CLK_SBC5>; |
| 276 | clock-names = "spi"; | 281 | clock-names = "spi"; |
| 277 | status = "disabled"; | 282 | status = "disabled"; |
| 278 | }; | 283 | }; |
| @@ -280,11 +285,11 @@ | |||
| 280 | spi@7000de00 { | 285 | spi@7000de00 { |
| 281 | compatible = "nvidia,tegra114-spi"; | 286 | compatible = "nvidia,tegra114-spi"; |
| 282 | reg = <0x7000de00 0x200>; | 287 | reg = <0x7000de00 0x200>; |
| 283 | interrupts = <0 79 0x04>; | 288 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 284 | nvidia,dma-request-selector = <&apbdma 28>; | 289 | nvidia,dma-request-selector = <&apbdma 28>; |
| 285 | #address-cells = <1>; | 290 | #address-cells = <1>; |
| 286 | #size-cells = <0>; | 291 | #size-cells = <0>; |
| 287 | clocks = <&tegra_car 105>; | 292 | clocks = <&tegra_car TEGRA114_CLK_SBC6>; |
| 288 | clock-names = "spi"; | 293 | clock-names = "spi"; |
| 289 | status = "disabled"; | 294 | status = "disabled"; |
| 290 | }; | 295 | }; |
| @@ -292,22 +297,22 @@ | |||
| 292 | rtc { | 297 | rtc { |
| 293 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; | 298 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
| 294 | reg = <0x7000e000 0x100>; | 299 | reg = <0x7000e000 0x100>; |
| 295 | interrupts = <0 2 0x04>; | 300 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 296 | clocks = <&tegra_car 4>; | 301 | clocks = <&tegra_car TEGRA114_CLK_RTC>; |
| 297 | }; | 302 | }; |
| 298 | 303 | ||
| 299 | kbc { | 304 | kbc { |
| 300 | compatible = "nvidia,tegra114-kbc"; | 305 | compatible = "nvidia,tegra114-kbc"; |
| 301 | reg = <0x7000e200 0x100>; | 306 | reg = <0x7000e200 0x100>; |
| 302 | interrupts = <0 85 0x04>; | 307 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 303 | clocks = <&tegra_car 36>; | 308 | clocks = <&tegra_car TEGRA114_CLK_KBC>; |
| 304 | status = "disabled"; | 309 | status = "disabled"; |
| 305 | }; | 310 | }; |
| 306 | 311 | ||
| 307 | pmc { | 312 | pmc { |
| 308 | compatible = "nvidia,tegra114-pmc"; | 313 | compatible = "nvidia,tegra114-pmc"; |
| 309 | reg = <0x7000e400 0x400>; | 314 | reg = <0x7000e400 0x400>; |
| 310 | clocks = <&tegra_car 261>, <&clk32k_in>; | 315 | clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; |
| 311 | clock-names = "pclk", "clk32k_in"; | 316 | clock-names = "pclk", "clk32k_in"; |
| 312 | }; | 317 | }; |
| 313 | 318 | ||
| @@ -322,35 +327,106 @@ | |||
| 322 | nvidia,ahb = <&ahb>; | 327 | nvidia,ahb = <&ahb>; |
| 323 | }; | 328 | }; |
| 324 | 329 | ||
| 330 | ahub { | ||
| 331 | compatible = "nvidia,tegra114-ahub"; | ||
| 332 | reg = <0x70080000 0x200>, | ||
| 333 | <0x70080200 0x100>, | ||
| 334 | <0x70081000 0x200>; | ||
| 335 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | ||
| 336 | nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>, | ||
| 337 | <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>, | ||
| 338 | <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, | ||
| 339 | <&apbdma 29>; | ||
| 340 | clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, | ||
| 341 | <&tegra_car TEGRA114_CLK_APBIF>, | ||
| 342 | <&tegra_car TEGRA114_CLK_I2S0>, | ||
| 343 | <&tegra_car TEGRA114_CLK_I2S1>, | ||
| 344 | <&tegra_car TEGRA114_CLK_I2S2>, | ||
| 345 | <&tegra_car TEGRA114_CLK_I2S3>, | ||
| 346 | <&tegra_car TEGRA114_CLK_I2S4>, | ||
| 347 | <&tegra_car TEGRA114_CLK_DAM0>, | ||
| 348 | <&tegra_car TEGRA114_CLK_DAM1>, | ||
| 349 | <&tegra_car TEGRA114_CLK_DAM2>, | ||
| 350 | <&tegra_car TEGRA114_CLK_SPDIF_IN>, | ||
| 351 | <&tegra_car TEGRA114_CLK_AMX>, | ||
| 352 | <&tegra_car TEGRA114_CLK_ADX>; | ||
| 353 | clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | ||
| 354 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | ||
| 355 | "spdif_in", "amx", "adx"; | ||
| 356 | ranges; | ||
| 357 | #address-cells = <1>; | ||
| 358 | #size-cells = <1>; | ||
| 359 | |||
| 360 | tegra_i2s0: i2s@70080300 { | ||
| 361 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | ||
| 362 | reg = <0x70080300 0x100>; | ||
| 363 | nvidia,ahub-cif-ids = <4 4>; | ||
| 364 | clocks = <&tegra_car TEGRA114_CLK_I2S0>; | ||
| 365 | status = "disabled"; | ||
| 366 | }; | ||
| 367 | |||
| 368 | tegra_i2s1: i2s@70080400 { | ||
| 369 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | ||
| 370 | reg = <0x70080400 0x100>; | ||
| 371 | nvidia,ahub-cif-ids = <5 5>; | ||
| 372 | clocks = <&tegra_car TEGRA114_CLK_I2S1>; | ||
| 373 | status = "disabled"; | ||
| 374 | }; | ||
| 375 | |||
| 376 | tegra_i2s2: i2s@70080500 { | ||
| 377 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | ||
| 378 | reg = <0x70080500 0x100>; | ||
| 379 | nvidia,ahub-cif-ids = <6 6>; | ||
| 380 | clocks = <&tegra_car TEGRA114_CLK_I2S2>; | ||
| 381 | status = "disabled"; | ||
| 382 | }; | ||
| 383 | |||
| 384 | tegra_i2s3: i2s@70080600 { | ||
| 385 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | ||
| 386 | reg = <0x70080600 0x100>; | ||
| 387 | nvidia,ahub-cif-ids = <7 7>; | ||
| 388 | clocks = <&tegra_car TEGRA114_CLK_I2S3>; | ||
| 389 | status = "disabled"; | ||
| 390 | }; | ||
| 391 | |||
| 392 | tegra_i2s4: i2s@70080700 { | ||
| 393 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; | ||
| 394 | reg = <0x70080700 0x100>; | ||
| 395 | nvidia,ahub-cif-ids = <8 8>; | ||
| 396 | clocks = <&tegra_car TEGRA114_CLK_I2S4>; | ||
| 397 | status = "disabled"; | ||
| 398 | }; | ||
| 399 | }; | ||
| 400 | |||
| 325 | sdhci@78000000 { | 401 | sdhci@78000000 { |
| 326 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | 402 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 327 | reg = <0x78000000 0x200>; | 403 | reg = <0x78000000 0x200>; |
| 328 | interrupts = <0 14 0x04>; | 404 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 329 | clocks = <&tegra_car 14>; | 405 | clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; |
| 330 | status = "disable"; | 406 | status = "disable"; |
| 331 | }; | 407 | }; |
| 332 | 408 | ||
| 333 | sdhci@78000200 { | 409 | sdhci@78000200 { |
| 334 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | 410 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 335 | reg = <0x78000200 0x200>; | 411 | reg = <0x78000200 0x200>; |
| 336 | interrupts = <0 15 0x04>; | 412 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 337 | clocks = <&tegra_car 9>; | 413 | clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; |
| 338 | status = "disable"; | 414 | status = "disable"; |
| 339 | }; | 415 | }; |
| 340 | 416 | ||
| 341 | sdhci@78000400 { | 417 | sdhci@78000400 { |
| 342 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | 418 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 343 | reg = <0x78000400 0x200>; | 419 | reg = <0x78000400 0x200>; |
| 344 | interrupts = <0 19 0x04>; | 420 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 345 | clocks = <&tegra_car 69>; | 421 | clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; |
| 346 | status = "disable"; | 422 | status = "disable"; |
| 347 | }; | 423 | }; |
| 348 | 424 | ||
| 349 | sdhci@78000600 { | 425 | sdhci@78000600 { |
| 350 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; | 426 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 351 | reg = <0x78000600 0x200>; | 427 | reg = <0x78000600 0x200>; |
| 352 | interrupts = <0 31 0x04>; | 428 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 353 | clocks = <&tegra_car 15>; | 429 | clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; |
| 354 | status = "disable"; | 430 | status = "disable"; |
| 355 | }; | 431 | }; |
| 356 | 432 | ||
| @@ -385,9 +461,14 @@ | |||
| 385 | 461 | ||
| 386 | timer { | 462 | timer { |
| 387 | compatible = "arm,armv7-timer"; | 463 | compatible = "arm,armv7-timer"; |
| 388 | interrupts = <1 13 0xf08>, | 464 | interrupts = |
| 389 | <1 14 0xf08>, | 465 | <GIC_PPI 13 |
| 390 | <1 11 0xf08>, | 466 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 391 | <1 10 0xf08>; | 467 | <GIC_PPI 14 |
| 468 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
| 469 | <GIC_PPI 11 | ||
| 470 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | ||
| 471 | <GIC_PPI 10 | ||
| 472 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | ||
| 392 | }; | 473 | }; |
| 393 | }; | 474 | }; |
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index c12af78e479c..2fcb3f2ca160 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /include/ "tegra20.dtsi" | 1 | #include "tegra20.dtsi" |
| 2 | 2 | ||
| 3 | / { | 3 | / { |
| 4 | model = "Toradex Colibri T20 512MB"; | 4 | model = "Toradex Colibri T20 512MB"; |
| @@ -14,7 +14,8 @@ | |||
| 14 | pll-supply = <&hdmi_pll_reg>; | 14 | pll-supply = <&hdmi_pll_reg>; |
| 15 | 15 | ||
| 16 | nvidia,ddc-i2c-bus = <&i2c_ddc>; | 16 | nvidia,ddc-i2c-bus = <&i2c_ddc>; |
| 17 | nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ | 17 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 18 | GPIO_ACTIVE_HIGH>; | ||
| 18 | }; | 19 | }; |
| 19 | }; | 20 | }; |
| 20 | 21 | ||
| @@ -217,7 +218,7 @@ | |||
| 217 | pmic: tps6586x@34 { | 218 | pmic: tps6586x@34 { |
| 218 | compatible = "ti,tps6586x"; | 219 | compatible = "ti,tps6586x"; |
| 219 | reg = <0x34>; | 220 | reg = <0x34>; |
| 220 | interrupts = <0 86 0x4>; | 221 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 221 | 222 | ||
| 222 | ti,system-power-controller; | 223 | ti,system-power-controller; |
| 223 | 224 | ||
| @@ -443,21 +444,25 @@ | |||
| 443 | 444 | ||
| 444 | ac97: ac97 { | 445 | ac97: ac97 { |
| 445 | status = "okay"; | 446 | status = "okay"; |
| 446 | nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ | 447 | nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 447 | nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */ | 448 | GPIO_ACTIVE_HIGH>; |
| 449 | nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) | ||
| 450 | GPIO_ACTIVE_HIGH>; | ||
| 448 | }; | 451 | }; |
| 449 | 452 | ||
| 450 | usb@c5004000 { | 453 | usb@c5004000 { |
| 451 | status = "okay"; | 454 | status = "okay"; |
| 452 | nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ | 455 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 456 | GPIO_ACTIVE_LOW>; | ||
| 453 | }; | 457 | }; |
| 454 | 458 | ||
| 455 | usb-phy@c5004000 { | 459 | usb-phy@c5004000 { |
| 456 | nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ | 460 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 461 | GPIO_ACTIVE_LOW>; | ||
| 457 | }; | 462 | }; |
| 458 | 463 | ||
| 459 | sdhci@c8000600 { | 464 | sdhci@c8000600 { |
| 460 | cd-gpios = <&gpio 23 1>; /* gpio PC7 */ | 465 | cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; |
| 461 | }; | 466 | }; |
| 462 | 467 | ||
| 463 | clocks { | 468 | clocks { |
| @@ -487,7 +492,9 @@ | |||
| 487 | 492 | ||
| 488 | nvidia,ac97-controller = <&ac97>; | 493 | nvidia,ac97-controller = <&ac97>; |
| 489 | 494 | ||
| 490 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; | 495 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 496 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | ||
| 497 | <&tegra_car TEGRA20_CLK_CDEV1>; | ||
| 491 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 498 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 492 | }; | 499 | }; |
| 493 | 500 | ||
| @@ -514,7 +521,7 @@ | |||
| 514 | enable-active-high; | 521 | enable-active-high; |
| 515 | regulator-boot-on; | 522 | regulator-boot-on; |
| 516 | regulator-always-on; | 523 | regulator-always-on; |
| 517 | gpio = <&gpio 217 0>; | 524 | gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; |
| 518 | }; | 525 | }; |
| 519 | }; | 526 | }; |
| 520 | }; | 527 | }; |
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index ec5293758753..d9f89cd879a7 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra20.dtsi" | 3 | #include "tegra20.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "NVIDIA Tegra20 Harmony evaluation board"; | 6 | model = "NVIDIA Tegra20 Harmony evaluation board"; |
| @@ -18,7 +18,8 @@ | |||
| 18 | pll-supply = <&hdmi_pll_reg>; | 18 | pll-supply = <&hdmi_pll_reg>; |
| 19 | 19 | ||
| 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 21 | nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ | 21 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 22 | GPIO_ACTIVE_HIGH>; | ||
| 22 | }; | 23 | }; |
| 23 | }; | 24 | }; |
| 24 | 25 | ||
| @@ -262,7 +263,7 @@ | |||
| 262 | compatible = "wlf,wm8903"; | 263 | compatible = "wlf,wm8903"; |
| 263 | reg = <0x1a>; | 264 | reg = <0x1a>; |
| 264 | interrupt-parent = <&gpio>; | 265 | interrupt-parent = <&gpio>; |
| 265 | interrupts = <187 0x04>; | 266 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
| 266 | 267 | ||
| 267 | gpio-controller; | 268 | gpio-controller; |
| 268 | #gpio-cells = <2>; | 269 | #gpio-cells = <2>; |
| @@ -290,7 +291,7 @@ | |||
| 290 | pmic: tps6586x@34 { | 291 | pmic: tps6586x@34 { |
| 291 | compatible = "ti,tps6586x"; | 292 | compatible = "ti,tps6586x"; |
| 292 | reg = <0x34>; | 293 | reg = <0x34>; |
| 293 | interrupts = <0 86 0x4>; | 294 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 294 | 295 | ||
| 295 | ti,system-power-controller; | 296 | ti,system-power-controller; |
| 296 | 297 | ||
| @@ -434,12 +435,14 @@ | |||
| 434 | 435 | ||
| 435 | usb@c5004000 { | 436 | usb@c5004000 { |
| 436 | status = "okay"; | 437 | status = "okay"; |
| 437 | nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ | 438 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 439 | GPIO_ACTIVE_LOW>; | ||
| 438 | }; | 440 | }; |
| 439 | 441 | ||
| 440 | usb-phy@c5004000 { | 442 | usb-phy@c5004000 { |
| 441 | status = "okay"; | 443 | status = "okay"; |
| 442 | nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ | 444 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 445 | GPIO_ACTIVE_LOW>; | ||
| 443 | }; | 446 | }; |
| 444 | 447 | ||
| 445 | usb@c5008000 { | 448 | usb@c5008000 { |
| @@ -452,17 +455,17 @@ | |||
| 452 | 455 | ||
| 453 | sdhci@c8000200 { | 456 | sdhci@c8000200 { |
| 454 | status = "okay"; | 457 | status = "okay"; |
| 455 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ | 458 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 456 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 459 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; |
| 457 | power-gpios = <&gpio 155 0>; /* gpio PT3 */ | 460 | power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; |
| 458 | bus-width = <4>; | 461 | bus-width = <4>; |
| 459 | }; | 462 | }; |
| 460 | 463 | ||
| 461 | sdhci@c8000600 { | 464 | sdhci@c8000600 { |
| 462 | status = "okay"; | 465 | status = "okay"; |
| 463 | cd-gpios = <&gpio 58 1>; /* gpio PH2 */ | 466 | cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; |
| 464 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ | 467 | wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; |
| 465 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | 468 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; |
| 466 | bus-width = <8>; | 469 | bus-width = <8>; |
| 467 | }; | 470 | }; |
| 468 | 471 | ||
| @@ -484,7 +487,7 @@ | |||
| 484 | 487 | ||
| 485 | power { | 488 | power { |
| 486 | label = "Power"; | 489 | label = "Power"; |
| 487 | gpios = <&gpio 170 1>; /* gpio PV2, active low */ | 490 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 488 | linux,code = <116>; /* KEY_POWER */ | 491 | linux,code = <116>; /* KEY_POWER */ |
| 489 | gpio-key,wakeup; | 492 | gpio-key,wakeup; |
| 490 | }; | 493 | }; |
| @@ -627,7 +630,7 @@ | |||
| 627 | regulator-name = "vdd_1v5"; | 630 | regulator-name = "vdd_1v5"; |
| 628 | regulator-min-microvolt = <1500000>; | 631 | regulator-min-microvolt = <1500000>; |
| 629 | regulator-max-microvolt = <1500000>; | 632 | regulator-max-microvolt = <1500000>; |
| 630 | gpio = <&pmic 0 0>; | 633 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
| 631 | }; | 634 | }; |
| 632 | 635 | ||
| 633 | regulator@2 { | 636 | regulator@2 { |
| @@ -636,7 +639,7 @@ | |||
| 636 | regulator-name = "vdd_1v2"; | 639 | regulator-name = "vdd_1v2"; |
| 637 | regulator-min-microvolt = <1200000>; | 640 | regulator-min-microvolt = <1200000>; |
| 638 | regulator-max-microvolt = <1200000>; | 641 | regulator-max-microvolt = <1200000>; |
| 639 | gpio = <&pmic 1 0>; | 642 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
| 640 | enable-active-high; | 643 | enable-active-high; |
| 641 | }; | 644 | }; |
| 642 | 645 | ||
| @@ -646,7 +649,7 @@ | |||
| 646 | regulator-name = "vdd_1v05"; | 649 | regulator-name = "vdd_1v05"; |
| 647 | regulator-min-microvolt = <1050000>; | 650 | regulator-min-microvolt = <1050000>; |
| 648 | regulator-max-microvolt = <1050000>; | 651 | regulator-max-microvolt = <1050000>; |
| 649 | gpio = <&pmic 2 0>; | 652 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; |
| 650 | enable-active-high; | 653 | enable-active-high; |
| 651 | /* Hack until board-harmony-pcie.c is removed */ | 654 | /* Hack until board-harmony-pcie.c is removed */ |
| 652 | status = "disabled"; | 655 | status = "disabled"; |
| @@ -658,7 +661,7 @@ | |||
| 658 | regulator-name = "vdd_pnl"; | 661 | regulator-name = "vdd_pnl"; |
| 659 | regulator-min-microvolt = <2800000>; | 662 | regulator-min-microvolt = <2800000>; |
| 660 | regulator-max-microvolt = <2800000>; | 663 | regulator-max-microvolt = <2800000>; |
| 661 | gpio = <&gpio 22 0>; /* gpio PC6 */ | 664 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; |
| 662 | enable-active-high; | 665 | enable-active-high; |
| 663 | }; | 666 | }; |
| 664 | 667 | ||
| @@ -668,7 +671,7 @@ | |||
| 668 | regulator-name = "vdd_bl"; | 671 | regulator-name = "vdd_bl"; |
| 669 | regulator-min-microvolt = <2800000>; | 672 | regulator-min-microvolt = <2800000>; |
| 670 | regulator-max-microvolt = <2800000>; | 673 | regulator-max-microvolt = <2800000>; |
| 671 | gpio = <&gpio 176 0>; /* gpio PW0 */ | 674 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; |
| 672 | enable-active-high; | 675 | enable-active-high; |
| 673 | }; | 676 | }; |
| 674 | }; | 677 | }; |
| @@ -691,12 +694,17 @@ | |||
| 691 | nvidia,i2s-controller = <&tegra_i2s1>; | 694 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 692 | nvidia,audio-codec = <&wm8903>; | 695 | nvidia,audio-codec = <&wm8903>; |
| 693 | 696 | ||
| 694 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | 697 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 695 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | 698 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) |
| 696 | nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ | 699 | GPIO_ACTIVE_HIGH>; |
| 697 | nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ | 700 | nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) |
| 698 | 701 | GPIO_ACTIVE_HIGH>; | |
| 699 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; | 702 | nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) |
| 703 | GPIO_ACTIVE_HIGH>; | ||
| 704 | |||
| 705 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, | ||
| 706 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | ||
| 707 | <&tegra_car TEGRA20_CLK_CDEV1>; | ||
| 700 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 708 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 701 | }; | 709 | }; |
| 702 | }; | 710 | }; |
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts index 9f64f7086881..f2222bd74eab 100644 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ b/arch/arm/boot/dts/tegra20-iris-512.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra20-colibri-512.dtsi" | 3 | #include "tegra20-colibri-512.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "Toradex Colibri T20 512MB on Iris"; | 6 | model = "Toradex Colibri T20 512MB on Iris"; |
| @@ -80,7 +80,7 @@ | |||
| 80 | regulator-max-microvolt = <5000000>; | 80 | regulator-max-microvolt = <5000000>; |
| 81 | regulator-boot-on; | 81 | regulator-boot-on; |
| 82 | regulator-always-on; | 82 | regulator-always-on; |
| 83 | gpio = <&gpio 178 0>; | 83 | gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; |
| 84 | }; | 84 | }; |
| 85 | 85 | ||
| 86 | vcc_sd_reg: regulator@1 { | 86 | vcc_sd_reg: regulator@1 { |
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index ace23437da89..7580578903cf 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra20-tamonten.dtsi" | 3 | #include "tegra20-tamonten.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "Avionic Design Medcom-Wide board"; | 6 | model = "Avionic Design Medcom-Wide board"; |
| @@ -15,7 +15,7 @@ | |||
| 15 | compatible = "wlf,wm8903"; | 15 | compatible = "wlf,wm8903"; |
| 16 | reg = <0x1a>; | 16 | reg = <0x1a>; |
| 17 | interrupt-parent = <&gpio>; | 17 | interrupt-parent = <&gpio>; |
| 18 | interrupts = <187 0x04>; | 18 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
| 19 | 19 | ||
| 20 | gpio-controller; | 20 | gpio-controller; |
| 21 | #gpio-cells = <2>; | 21 | #gpio-cells = <2>; |
| @@ -56,10 +56,12 @@ | |||
| 56 | nvidia,i2s-controller = <&tegra_i2s1>; | 56 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 57 | nvidia,audio-codec = <&wm8903>; | 57 | nvidia,audio-codec = <&wm8903>; |
| 58 | 58 | ||
| 59 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | 59 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 60 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | 60 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; |
| 61 | 61 | ||
| 62 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; | 62 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 63 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | ||
| 64 | <&tegra_car TEGRA20_CLK_CDEV1>; | ||
| 63 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 65 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 64 | }; | 66 | }; |
| 65 | }; | 67 | }; |
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 1c17ffaff1ad..cfd12763b1b2 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra20.dtsi" | 3 | #include "tegra20.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "Toshiba AC100 / Dynabook AZ"; | 6 | model = "Toshiba AC100 / Dynabook AZ"; |
| @@ -18,7 +18,8 @@ | |||
| 18 | pll-supply = <&hdmi_pll_reg>; | 18 | pll-supply = <&hdmi_pll_reg>; |
| 19 | 19 | ||
| 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 21 | nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ | 21 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 22 | GPIO_ACTIVE_HIGH>; | ||
| 22 | }; | 23 | }; |
| 23 | }; | 24 | }; |
| 24 | 25 | ||
| @@ -270,13 +271,14 @@ | |||
| 270 | nvec { | 271 | nvec { |
| 271 | compatible = "nvidia,nvec"; | 272 | compatible = "nvidia,nvec"; |
| 272 | reg = <0x7000c500 0x100>; | 273 | reg = <0x7000c500 0x100>; |
| 273 | interrupts = <0 92 0x04>; | 274 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 274 | #address-cells = <1>; | 275 | #address-cells = <1>; |
| 275 | #size-cells = <0>; | 276 | #size-cells = <0>; |
| 276 | clock-frequency = <80000>; | 277 | clock-frequency = <80000>; |
| 277 | request-gpios = <&gpio 170 0>; /* gpio PV2 */ | 278 | request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
| 278 | slave-addr = <138>; | 279 | slave-addr = <138>; |
| 279 | clocks = <&tegra_car 67>, <&tegra_car 124>; | 280 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
| 281 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | ||
| 280 | clock-names = "div-clk", "fast-clk"; | 282 | clock-names = "div-clk", "fast-clk"; |
| 281 | }; | 283 | }; |
| 282 | 284 | ||
| @@ -287,7 +289,7 @@ | |||
| 287 | pmic: tps6586x@34 { | 289 | pmic: tps6586x@34 { |
| 288 | compatible = "ti,tps6586x"; | 290 | compatible = "ti,tps6586x"; |
| 289 | reg = <0x34>; | 291 | reg = <0x34>; |
| 290 | interrupts = <0 86 0x4>; | 292 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 291 | 293 | ||
| 292 | #gpio-cells = <2>; | 294 | #gpio-cells = <2>; |
| 293 | gpio-controller; | 295 | gpio-controller; |
| @@ -433,12 +435,14 @@ | |||
| 433 | 435 | ||
| 434 | usb@c5004000 { | 436 | usb@c5004000 { |
| 435 | status = "okay"; | 437 | status = "okay"; |
| 436 | nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ | 438 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 439 | GPIO_ACTIVE_LOW>; | ||
| 437 | }; | 440 | }; |
| 438 | 441 | ||
| 439 | usb-phy@c5004000 { | 442 | usb-phy@c5004000 { |
| 440 | status = "okay"; | 443 | status = "okay"; |
| 441 | nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ | 444 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 445 | GPIO_ACTIVE_LOW>; | ||
| 442 | }; | 446 | }; |
| 443 | 447 | ||
| 444 | usb@c5008000 { | 448 | usb@c5008000 { |
| @@ -451,9 +455,9 @@ | |||
| 451 | 455 | ||
| 452 | sdhci@c8000000 { | 456 | sdhci@c8000000 { |
| 453 | status = "okay"; | 457 | status = "okay"; |
| 454 | cd-gpios = <&gpio 173 1>; /* gpio PV5 */ | 458 | cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; |
| 455 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 459 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; |
| 456 | power-gpios = <&gpio 169 0>; /* gpio PV1 */ | 460 | power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; |
| 457 | bus-width = <4>; | 461 | bus-width = <4>; |
| 458 | }; | 462 | }; |
| 459 | 463 | ||
| @@ -481,7 +485,7 @@ | |||
| 481 | 485 | ||
| 482 | power { | 486 | power { |
| 483 | label = "Power"; | 487 | label = "Power"; |
| 484 | gpios = <&gpio 79 1>; /* gpio PJ7, active low */ | 488 | gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; |
| 485 | linux,code = <116>; /* KEY_POWER */ | 489 | linux,code = <116>; /* KEY_POWER */ |
| 486 | gpio-key,wakeup; | 490 | gpio-key,wakeup; |
| 487 | }; | 491 | }; |
| @@ -492,7 +496,7 @@ | |||
| 492 | 496 | ||
| 493 | wifi { | 497 | wifi { |
| 494 | label = "wifi-led"; | 498 | label = "wifi-led"; |
| 495 | gpios = <&gpio 24 0>; /* gpio PD0 */ | 499 | gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; |
| 496 | linux,default-trigger = "rfkill0"; | 500 | linux,default-trigger = "rfkill0"; |
| 497 | }; | 501 | }; |
| 498 | }; | 502 | }; |
| @@ -529,9 +533,12 @@ | |||
| 529 | 533 | ||
| 530 | nvidia,audio-codec = <&alc5632>; | 534 | nvidia,audio-codec = <&alc5632>; |
| 531 | nvidia,i2s-controller = <&tegra_i2s1>; | 535 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 532 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | 536 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) |
| 537 | GPIO_ACTIVE_HIGH>; | ||
| 533 | 538 | ||
| 534 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; | 539 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 540 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | ||
| 541 | <&tegra_car TEGRA20_CLK_CDEV1>; | ||
| 535 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 542 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 536 | }; | 543 | }; |
| 537 | }; | 544 | }; |
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index 1a17cc30bb9d..d7a358a6a647 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra20-tamonten.dtsi" | 3 | #include "tegra20-tamonten.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "Avionic Design Plutux board"; | 6 | model = "Avionic Design Plutux board"; |
| @@ -17,7 +17,7 @@ | |||
| 17 | compatible = "wlf,wm8903"; | 17 | compatible = "wlf,wm8903"; |
| 18 | reg = <0x1a>; | 18 | reg = <0x1a>; |
| 19 | interrupt-parent = <&gpio>; | 19 | interrupt-parent = <&gpio>; |
| 20 | interrupts = <187 0x04>; | 20 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
| 21 | 21 | ||
| 22 | gpio-controller; | 22 | gpio-controller; |
| 23 | #gpio-cells = <2>; | 23 | #gpio-cells = <2>; |
| @@ -50,10 +50,12 @@ | |||
| 50 | nvidia,i2s-controller = <&tegra_i2s1>; | 50 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 51 | nvidia,audio-codec = <&wm8903>; | 51 | nvidia,audio-codec = <&wm8903>; |
| 52 | 52 | ||
| 53 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | 53 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 54 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | 54 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; |
| 55 | 55 | ||
| 56 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; | 56 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 57 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | ||
| 58 | <&tegra_car TEGRA20_CLK_CDEV1>; | ||
| 57 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 59 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 58 | }; | 60 | }; |
| 59 | }; | 61 | }; |
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 009dafecf88b..ab177b406b78 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra20.dtsi" | 3 | #include "tegra20.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "NVIDIA Seaboard"; | 6 | model = "NVIDIA Seaboard"; |
| @@ -18,7 +18,8 @@ | |||
| 18 | pll-supply = <&hdmi_pll_reg>; | 18 | pll-supply = <&hdmi_pll_reg>; |
| 19 | 19 | ||
| 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 21 | nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ | 21 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 22 | GPIO_ACTIVE_HIGH>; | ||
| 22 | }; | 23 | }; |
| 23 | }; | 24 | }; |
| 24 | 25 | ||
| @@ -313,7 +314,7 @@ | |||
| 313 | compatible = "wlf,wm8903"; | 314 | compatible = "wlf,wm8903"; |
| 314 | reg = <0x1a>; | 315 | reg = <0x1a>; |
| 315 | interrupt-parent = <&gpio>; | 316 | interrupt-parent = <&gpio>; |
| 316 | interrupts = <187 0x04>; | 317 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
| 317 | 318 | ||
| 318 | gpio-controller; | 319 | gpio-controller; |
| 319 | #gpio-cells = <2>; | 320 | #gpio-cells = <2>; |
| @@ -328,14 +329,14 @@ | |||
| 328 | compatible = "isil,isl29018"; | 329 | compatible = "isil,isl29018"; |
| 329 | reg = <0x44>; | 330 | reg = <0x44>; |
| 330 | interrupt-parent = <&gpio>; | 331 | interrupt-parent = <&gpio>; |
| 331 | interrupts = <202 0x04>; /* GPIO PZ2 */ | 332 | interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; |
| 332 | }; | 333 | }; |
| 333 | 334 | ||
| 334 | gyrometer@68 { | 335 | gyrometer@68 { |
| 335 | compatible = "invn,mpu3050"; | 336 | compatible = "invn,mpu3050"; |
| 336 | reg = <0x68>; | 337 | reg = <0x68>; |
| 337 | interrupt-parent = <&gpio>; | 338 | interrupt-parent = <&gpio>; |
| 338 | interrupts = <204 0x04>; /* gpio PZ4 */ | 339 | interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>; |
| 339 | }; | 340 | }; |
| 340 | }; | 341 | }; |
| 341 | 342 | ||
| @@ -388,7 +389,7 @@ | |||
| 388 | pmic: tps6586x@34 { | 389 | pmic: tps6586x@34 { |
| 389 | compatible = "ti,tps6586x"; | 390 | compatible = "ti,tps6586x"; |
| 390 | reg = <0x34>; | 391 | reg = <0x34>; |
| 391 | interrupts = <0 86 0x4>; | 392 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 392 | 393 | ||
| 393 | ti,system-power-controller; | 394 | ti,system-power-controller; |
| 394 | 395 | ||
| @@ -511,7 +512,7 @@ | |||
| 511 | compatible = "ak,ak8975"; | 512 | compatible = "ak,ak8975"; |
| 512 | reg = <0xc>; | 513 | reg = <0xc>; |
| 513 | interrupt-parent = <&gpio>; | 514 | interrupt-parent = <&gpio>; |
| 514 | interrupts = <109 0x04>; /* gpio PN5 */ | 515 | interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; |
| 515 | }; | 516 | }; |
| 516 | }; | 517 | }; |
| 517 | 518 | ||
| @@ -565,7 +566,7 @@ | |||
| 565 | 566 | ||
| 566 | usb@c5000000 { | 567 | usb@c5000000 { |
| 567 | status = "okay"; | 568 | status = "okay"; |
| 568 | nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */ | 569 | nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; |
| 569 | dr_mode = "otg"; | 570 | dr_mode = "otg"; |
| 570 | }; | 571 | }; |
| 571 | 572 | ||
| @@ -577,12 +578,14 @@ | |||
| 577 | 578 | ||
| 578 | usb@c5004000 { | 579 | usb@c5004000 { |
| 579 | status = "okay"; | 580 | status = "okay"; |
| 580 | nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ | 581 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 582 | GPIO_ACTIVE_LOW>; | ||
| 581 | }; | 583 | }; |
| 582 | 584 | ||
| 583 | usb-phy@c5004000 { | 585 | usb-phy@c5004000 { |
| 584 | status = "okay"; | 586 | status = "okay"; |
| 585 | nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ | 587 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 588 | GPIO_ACTIVE_LOW>; | ||
| 586 | }; | 589 | }; |
| 587 | 590 | ||
| 588 | usb@c5008000 { | 591 | usb@c5008000 { |
| @@ -595,16 +598,16 @@ | |||
| 595 | 598 | ||
| 596 | sdhci@c8000000 { | 599 | sdhci@c8000000 { |
| 597 | status = "okay"; | 600 | status = "okay"; |
| 598 | power-gpios = <&gpio 86 0>; /* gpio PK6 */ | 601 | power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
| 599 | bus-width = <4>; | 602 | bus-width = <4>; |
| 600 | keep-power-in-suspend; | 603 | keep-power-in-suspend; |
| 601 | }; | 604 | }; |
| 602 | 605 | ||
| 603 | sdhci@c8000400 { | 606 | sdhci@c8000400 { |
| 604 | status = "okay"; | 607 | status = "okay"; |
| 605 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ | 608 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 606 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 609 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; |
| 607 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | 610 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; |
| 608 | bus-width = <4>; | 611 | bus-width = <4>; |
| 609 | }; | 612 | }; |
| 610 | 613 | ||
| @@ -632,14 +635,14 @@ | |||
| 632 | 635 | ||
| 633 | power { | 636 | power { |
| 634 | label = "Power"; | 637 | label = "Power"; |
| 635 | gpios = <&gpio 170 1>; /* gpio PV2, active low */ | 638 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 636 | linux,code = <116>; /* KEY_POWER */ | 639 | linux,code = <116>; /* KEY_POWER */ |
| 637 | gpio-key,wakeup; | 640 | gpio-key,wakeup; |
| 638 | }; | 641 | }; |
| 639 | 642 | ||
| 640 | lid { | 643 | lid { |
| 641 | label = "Lid"; | 644 | label = "Lid"; |
| 642 | gpios = <&gpio 23 0>; /* gpio PC7 */ | 645 | gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; |
| 643 | linux,input-type = <5>; /* EV_SW */ | 646 | linux,input-type = <5>; /* EV_SW */ |
| 644 | linux,code = <0>; /* SW_LID */ | 647 | linux,code = <0>; /* SW_LID */ |
| 645 | debounce-interval = <1>; | 648 | debounce-interval = <1>; |
| @@ -806,7 +809,7 @@ | |||
| 806 | regulator-name = "vdd_1v5"; | 809 | regulator-name = "vdd_1v5"; |
| 807 | regulator-min-microvolt = <1500000>; | 810 | regulator-min-microvolt = <1500000>; |
| 808 | regulator-max-microvolt = <1500000>; | 811 | regulator-max-microvolt = <1500000>; |
| 809 | gpio = <&pmic 0 0>; | 812 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
| 810 | }; | 813 | }; |
| 811 | 814 | ||
| 812 | regulator@2 { | 815 | regulator@2 { |
| @@ -815,7 +818,7 @@ | |||
| 815 | regulator-name = "vdd_1v2"; | 818 | regulator-name = "vdd_1v2"; |
| 816 | regulator-min-microvolt = <1200000>; | 819 | regulator-min-microvolt = <1200000>; |
| 817 | regulator-max-microvolt = <1200000>; | 820 | regulator-max-microvolt = <1200000>; |
| 818 | gpio = <&pmic 1 0>; | 821 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
| 819 | enable-active-high; | 822 | enable-active-high; |
| 820 | }; | 823 | }; |
| 821 | 824 | ||
| @@ -847,10 +850,12 @@ | |||
| 847 | nvidia,i2s-controller = <&tegra_i2s1>; | 850 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 848 | nvidia,audio-codec = <&wm8903>; | 851 | nvidia,audio-codec = <&wm8903>; |
| 849 | 852 | ||
| 850 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | 853 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 851 | nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ | 854 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; |
| 852 | 855 | ||
| 853 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; | 856 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 857 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | ||
| 858 | <&tegra_car TEGRA20_CLK_CDEV1>; | ||
| 854 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 859 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 855 | }; | 860 | }; |
| 856 | }; | 861 | }; |
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index fc2f7d6e70b2..c54faae7cfb3 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /include/ "tegra20.dtsi" | 1 | #include "tegra20.dtsi" |
| 2 | 2 | ||
| 3 | / { | 3 | / { |
| 4 | model = "Avionic Design Tamonten SOM"; | 4 | model = "Avionic Design Tamonten SOM"; |
| @@ -14,7 +14,8 @@ | |||
| 14 | pll-supply = <&hdmi_pll_reg>; | 14 | pll-supply = <&hdmi_pll_reg>; |
| 15 | 15 | ||
| 16 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | 16 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 17 | nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ | 17 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 18 | GPIO_ACTIVE_HIGH>; | ||
| 18 | }; | 19 | }; |
| 19 | }; | 20 | }; |
| 20 | 21 | ||
| @@ -321,7 +322,7 @@ | |||
| 321 | pmic: tps6586x@34 { | 322 | pmic: tps6586x@34 { |
| 322 | compatible = "ti,tps6586x"; | 323 | compatible = "ti,tps6586x"; |
| 323 | reg = <0x34>; | 324 | reg = <0x34>; |
| 324 | interrupts = <0 86 0x4>; | 325 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 325 | 326 | ||
| 326 | ti,system-power-controller; | 327 | ti,system-power-controller; |
| 327 | 328 | ||
| @@ -475,8 +476,8 @@ | |||
| 475 | }; | 476 | }; |
| 476 | 477 | ||
| 477 | sdhci@c8000600 { | 478 | sdhci@c8000600 { |
| 478 | cd-gpios = <&gpio 58 1>; /* gpio PH2 */ | 479 | cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; |
| 479 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ | 480 | wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; |
| 480 | bus-width = <4>; | 481 | bus-width = <4>; |
| 481 | status = "okay"; | 482 | status = "okay"; |
| 482 | }; | 483 | }; |
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 742f0b38d21d..c572c43751b1 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra20-tamonten.dtsi" | 3 | #include "tegra20-tamonten.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "Avionic Design Tamonten Evaluation Carrier"; | 6 | model = "Avionic Design Tamonten Evaluation Carrier"; |
| @@ -17,7 +17,7 @@ | |||
| 17 | compatible = "wlf,wm8903"; | 17 | compatible = "wlf,wm8903"; |
| 18 | reg = <0x1a>; | 18 | reg = <0x1a>; |
| 19 | interrupt-parent = <&gpio>; | 19 | interrupt-parent = <&gpio>; |
| 20 | interrupts = <187 0x04>; | 20 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
| 21 | 21 | ||
| 22 | gpio-controller; | 22 | gpio-controller; |
| 23 | #gpio-cells = <2>; | 23 | #gpio-cells = <2>; |
| @@ -50,10 +50,13 @@ | |||
| 50 | nvidia,i2s-controller = <&tegra_i2s1>; | 50 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 51 | nvidia,audio-codec = <&wm8903>; | 51 | nvidia,audio-codec = <&wm8903>; |
| 52 | 52 | ||
| 53 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | 53 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 54 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | 54 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) |
| 55 | GPIO_ACTIVE_HIGH>; | ||
| 55 | 56 | ||
| 56 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; | 57 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 58 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | ||
| 59 | <&tegra_car TEGRA20_CLK_CDEV1>; | ||
| 57 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 60 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 58 | }; | 61 | }; |
| 59 | }; | 62 | }; |
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 0e65c00ec732..170159910455 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra20.dtsi" | 3 | #include "tegra20.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "Compulab TrimSlice board"; | 6 | model = "Compulab TrimSlice board"; |
| @@ -18,7 +18,8 @@ | |||
| 18 | pll-supply = <&hdmi_pll_reg>; | 18 | pll-supply = <&hdmi_pll_reg>; |
| 19 | 19 | ||
| 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 21 | nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ | 21 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 22 | GPIO_ACTIVE_HIGH>; | ||
| 22 | }; | 23 | }; |
| 23 | }; | 24 | }; |
| 24 | 25 | ||
| @@ -311,7 +312,7 @@ | |||
| 311 | 312 | ||
| 312 | usb@c5000000 { | 313 | usb@c5000000 { |
| 313 | status = "okay"; | 314 | status = "okay"; |
| 314 | nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */ | 315 | nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
| 315 | }; | 316 | }; |
| 316 | 317 | ||
| 317 | usb-phy@c5000000 { | 318 | usb-phy@c5000000 { |
| @@ -321,12 +322,14 @@ | |||
| 321 | 322 | ||
| 322 | usb@c5004000 { | 323 | usb@c5004000 { |
| 323 | status = "okay"; | 324 | status = "okay"; |
| 324 | nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ | 325 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 326 | GPIO_ACTIVE_LOW>; | ||
| 325 | }; | 327 | }; |
| 326 | 328 | ||
| 327 | usb-phy@c5004000 { | 329 | usb-phy@c5004000 { |
| 328 | status = "okay"; | 330 | status = "okay"; |
| 329 | nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */ | 331 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 332 | GPIO_ACTIVE_LOW>; | ||
| 330 | }; | 333 | }; |
| 331 | 334 | ||
| 332 | usb@c5008000 { | 335 | usb@c5008000 { |
| @@ -344,8 +347,8 @@ | |||
| 344 | 347 | ||
| 345 | sdhci@c8000600 { | 348 | sdhci@c8000600 { |
| 346 | status = "okay"; | 349 | status = "okay"; |
| 347 | cd-gpios = <&gpio 121 1>; /* gpio PP1 */ | 350 | cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; |
| 348 | wp-gpios = <&gpio 122 0>; /* gpio PP2 */ | 351 | wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; |
| 349 | bus-width = <4>; | 352 | bus-width = <4>; |
| 350 | }; | 353 | }; |
| 351 | 354 | ||
| @@ -367,7 +370,7 @@ | |||
| 367 | 370 | ||
| 368 | power { | 371 | power { |
| 369 | label = "Power"; | 372 | label = "Power"; |
| 370 | gpios = <&gpio 190 1>; /* gpio PX6, active low */ | 373 | gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; |
| 371 | linux,code = <116>; /* KEY_POWER */ | 374 | linux,code = <116>; /* KEY_POWER */ |
| 372 | gpio-key,wakeup; | 375 | gpio-key,wakeup; |
| 373 | }; | 376 | }; |
| @@ -375,7 +378,7 @@ | |||
| 375 | 378 | ||
| 376 | poweroff { | 379 | poweroff { |
| 377 | compatible = "gpio-poweroff"; | 380 | compatible = "gpio-poweroff"; |
| 378 | gpios = <&gpio 191 1>; /* gpio PX7, active low */ | 381 | gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; |
| 379 | }; | 382 | }; |
| 380 | 383 | ||
| 381 | regulators { | 384 | regulators { |
| @@ -416,7 +419,9 @@ | |||
| 416 | nvidia,i2s-controller = <&tegra_i2s1>; | 419 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 417 | nvidia,audio-codec = <&codec>; | 420 | nvidia,audio-codec = <&codec>; |
| 418 | 421 | ||
| 419 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; | 422 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 423 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | ||
| 424 | <&tegra_car TEGRA20_CLK_CDEV1>; | ||
| 420 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 425 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 421 | }; | 426 | }; |
| 422 | }; | 427 | }; |
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index e00f89e645f9..7f8c28d1121f 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra20.dtsi" | 3 | #include "tegra20.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "NVIDIA Tegra20 Ventana evaluation board"; | 6 | model = "NVIDIA Tegra20 Ventana evaluation board"; |
| @@ -18,7 +18,8 @@ | |||
| 18 | pll-supply = <&hdmi_pll_reg>; | 18 | pll-supply = <&hdmi_pll_reg>; |
| 19 | 19 | ||
| 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 21 | nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ | 21 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 22 | GPIO_ACTIVE_HIGH>; | ||
| 22 | }; | 23 | }; |
| 23 | }; | 24 | }; |
| 24 | 25 | ||
| @@ -310,7 +311,7 @@ | |||
| 310 | compatible = "wlf,wm8903"; | 311 | compatible = "wlf,wm8903"; |
| 311 | reg = <0x1a>; | 312 | reg = <0x1a>; |
| 312 | interrupt-parent = <&gpio>; | 313 | interrupt-parent = <&gpio>; |
| 313 | interrupts = <187 0x04>; | 314 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
| 314 | 315 | ||
| 315 | gpio-controller; | 316 | gpio-controller; |
| 316 | #gpio-cells = <2>; | 317 | #gpio-cells = <2>; |
| @@ -325,7 +326,7 @@ | |||
| 325 | compatible = "isil,isl29018"; | 326 | compatible = "isil,isl29018"; |
| 326 | reg = <0x44>; | 327 | reg = <0x44>; |
| 327 | interrupt-parent = <&gpio>; | 328 | interrupt-parent = <&gpio>; |
| 328 | interrupts = <202 0x04>; /*gpio PZ2 */ | 329 | interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; |
| 329 | }; | 330 | }; |
| 330 | }; | 331 | }; |
| 331 | 332 | ||
| @@ -371,7 +372,7 @@ | |||
| 371 | pmic: tps6586x@34 { | 372 | pmic: tps6586x@34 { |
| 372 | compatible = "ti,tps6586x"; | 373 | compatible = "ti,tps6586x"; |
| 373 | reg = <0x34>; | 374 | reg = <0x34>; |
| 374 | interrupts = <0 86 0x4>; | 375 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 375 | 376 | ||
| 376 | ti,system-power-controller; | 377 | ti,system-power-controller; |
| 377 | 378 | ||
| @@ -511,12 +512,14 @@ | |||
| 511 | 512 | ||
| 512 | usb@c5004000 { | 513 | usb@c5004000 { |
| 513 | status = "okay"; | 514 | status = "okay"; |
| 514 | nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ | 515 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 516 | GPIO_ACTIVE_LOW>; | ||
| 515 | }; | 517 | }; |
| 516 | 518 | ||
| 517 | usb-phy@c5004000 { | 519 | usb-phy@c5004000 { |
| 518 | status = "okay"; | 520 | status = "okay"; |
| 519 | nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ | 521 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 522 | GPIO_ACTIVE_LOW>; | ||
| 520 | }; | 523 | }; |
| 521 | 524 | ||
| 522 | usb@c5008000 { | 525 | usb@c5008000 { |
| @@ -529,16 +532,16 @@ | |||
| 529 | 532 | ||
| 530 | sdhci@c8000000 { | 533 | sdhci@c8000000 { |
| 531 | status = "okay"; | 534 | status = "okay"; |
| 532 | power-gpios = <&gpio 86 0>; /* gpio PK6 */ | 535 | power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
| 533 | bus-width = <4>; | 536 | bus-width = <4>; |
| 534 | keep-power-in-suspend; | 537 | keep-power-in-suspend; |
| 535 | }; | 538 | }; |
| 536 | 539 | ||
| 537 | sdhci@c8000400 { | 540 | sdhci@c8000400 { |
| 538 | status = "okay"; | 541 | status = "okay"; |
| 539 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ | 542 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 540 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 543 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; |
| 541 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | 544 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; |
| 542 | bus-width = <4>; | 545 | bus-width = <4>; |
| 543 | }; | 546 | }; |
| 544 | 547 | ||
| @@ -566,7 +569,7 @@ | |||
| 566 | 569 | ||
| 567 | power { | 570 | power { |
| 568 | label = "Power"; | 571 | label = "Power"; |
| 569 | gpios = <&gpio 170 1>; /* gpio PV2, active low */ | 572 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 570 | linux,code = <116>; /* KEY_POWER */ | 573 | linux,code = <116>; /* KEY_POWER */ |
| 571 | gpio-key,wakeup; | 574 | gpio-key,wakeup; |
| 572 | }; | 575 | }; |
| @@ -592,7 +595,7 @@ | |||
| 592 | regulator-name = "vdd_1v5"; | 595 | regulator-name = "vdd_1v5"; |
| 593 | regulator-min-microvolt = <1500000>; | 596 | regulator-min-microvolt = <1500000>; |
| 594 | regulator-max-microvolt = <1500000>; | 597 | regulator-max-microvolt = <1500000>; |
| 595 | gpio = <&pmic 0 0>; | 598 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
| 596 | }; | 599 | }; |
| 597 | 600 | ||
| 598 | regulator@2 { | 601 | regulator@2 { |
| @@ -601,7 +604,7 @@ | |||
| 601 | regulator-name = "vdd_1v2"; | 604 | regulator-name = "vdd_1v2"; |
| 602 | regulator-min-microvolt = <1200000>; | 605 | regulator-min-microvolt = <1200000>; |
| 603 | regulator-max-microvolt = <1200000>; | 606 | regulator-max-microvolt = <1200000>; |
| 604 | gpio = <&pmic 1 0>; | 607 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
| 605 | enable-active-high; | 608 | enable-active-high; |
| 606 | }; | 609 | }; |
| 607 | 610 | ||
| @@ -611,7 +614,7 @@ | |||
| 611 | regulator-name = "vdd_pnl"; | 614 | regulator-name = "vdd_pnl"; |
| 612 | regulator-min-microvolt = <2800000>; | 615 | regulator-min-microvolt = <2800000>; |
| 613 | regulator-max-microvolt = <2800000>; | 616 | regulator-max-microvolt = <2800000>; |
| 614 | gpio = <&gpio 22 0>; /* gpio PC6 */ | 617 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; |
| 615 | enable-active-high; | 618 | enable-active-high; |
| 616 | }; | 619 | }; |
| 617 | 620 | ||
| @@ -621,7 +624,7 @@ | |||
| 621 | regulator-name = "vdd_bl"; | 624 | regulator-name = "vdd_bl"; |
| 622 | regulator-min-microvolt = <2800000>; | 625 | regulator-min-microvolt = <2800000>; |
| 623 | regulator-max-microvolt = <2800000>; | 626 | regulator-max-microvolt = <2800000>; |
| 624 | gpio = <&gpio 176 0>; /* gpio PW0 */ | 627 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; |
| 625 | enable-active-high; | 628 | enable-active-high; |
| 626 | }; | 629 | }; |
| 627 | }; | 630 | }; |
| @@ -644,12 +647,16 @@ | |||
| 644 | nvidia,i2s-controller = <&tegra_i2s1>; | 647 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 645 | nvidia,audio-codec = <&wm8903>; | 648 | nvidia,audio-codec = <&wm8903>; |
| 646 | 649 | ||
| 647 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | 650 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 648 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | 651 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; |
| 649 | nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */ | 652 | nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) |
| 650 | nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ | 653 | GPIO_ACTIVE_HIGH>; |
| 654 | nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) | ||
| 655 | GPIO_ACTIVE_HIGH>; | ||
| 651 | 656 | ||
| 652 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; | 657 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 658 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | ||
| 659 | <&tegra_car TEGRA20_CLK_CDEV1>; | ||
| 653 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 660 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 654 | }; | 661 | }; |
| 655 | }; | 662 | }; |
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 3c24c9b92b44..ea078ab8edeb 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra20.dtsi" | 3 | #include "tegra20.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "NVIDIA Tegra20 Whistler evaluation board"; | 6 | model = "NVIDIA Tegra20 Whistler evaluation board"; |
| @@ -18,7 +18,8 @@ | |||
| 18 | pll-supply = <&hdmi_pll_reg>; | 18 | pll-supply = <&hdmi_pll_reg>; |
| 19 | 19 | ||
| 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | 20 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 21 | nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */ | 21 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 22 | GPIO_ACTIVE_HIGH>; | ||
| 22 | }; | 23 | }; |
| 23 | }; | 24 | }; |
| 24 | 25 | ||
| @@ -281,7 +282,7 @@ | |||
| 281 | max8907@3c { | 282 | max8907@3c { |
| 282 | compatible = "maxim,max8907"; | 283 | compatible = "maxim,max8907"; |
| 283 | reg = <0x3c>; | 284 | reg = <0x3c>; |
| 284 | interrupts = <0 86 0x4>; | 285 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 285 | 286 | ||
| 286 | maxim,system-power-controller; | 287 | maxim,system-power-controller; |
| 287 | 288 | ||
| @@ -508,7 +509,7 @@ | |||
| 508 | 509 | ||
| 509 | usb@c5000000 { | 510 | usb@c5000000 { |
| 510 | status = "okay"; | 511 | status = "okay"; |
| 511 | nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ | 512 | nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>; |
| 512 | }; | 513 | }; |
| 513 | 514 | ||
| 514 | usb-phy@c5000000 { | 515 | usb-phy@c5000000 { |
| @@ -518,7 +519,7 @@ | |||
| 518 | 519 | ||
| 519 | usb@c5008000 { | 520 | usb@c5008000 { |
| 520 | status = "okay"; | 521 | status = "okay"; |
| 521 | nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ | 522 | nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>; |
| 522 | }; | 523 | }; |
| 523 | 524 | ||
| 524 | usb-phy@c5008000 { | 525 | usb-phy@c5008000 { |
| @@ -528,8 +529,8 @@ | |||
| 528 | 529 | ||
| 529 | sdhci@c8000400 { | 530 | sdhci@c8000400 { |
| 530 | status = "okay"; | 531 | status = "okay"; |
| 531 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ | 532 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 532 | wp-gpios = <&gpio 173 0>; /* gpio PV5 */ | 533 | wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; |
| 533 | bus-width = <8>; | 534 | bus-width = <8>; |
| 534 | }; | 535 | }; |
| 535 | 536 | ||
| @@ -612,7 +613,9 @@ | |||
| 612 | nvidia,i2s-controller = <&tegra_i2s1>; | 613 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 613 | nvidia,audio-codec = <&codec>; | 614 | nvidia,audio-codec = <&codec>; |
| 614 | 615 | ||
| 615 | clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>; | 616 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 617 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | ||
| 618 | <&tegra_car TEGRA20_CLK_CDEV1>; | ||
| 616 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 619 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 617 | }; | 620 | }; |
| 618 | }; | 621 | }; |
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 96d6d8a3aa72..9653fd8288d2 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
| @@ -1,4 +1,8 @@ | |||
| 1 | /include/ "skeleton.dtsi" | 1 | #include <dt-bindings/clock/tegra20-car.h> |
| 2 | #include <dt-bindings/gpio/tegra-gpio.h> | ||
| 3 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 4 | |||
| 5 | #include "skeleton.dtsi" | ||
| 2 | 6 | ||
| 3 | / { | 7 | / { |
| 4 | compatible = "nvidia,tegra20"; | 8 | compatible = "nvidia,tegra20"; |
| @@ -15,9 +19,9 @@ | |||
| 15 | host1x { | 19 | host1x { |
| 16 | compatible = "nvidia,tegra20-host1x", "simple-bus"; | 20 | compatible = "nvidia,tegra20-host1x", "simple-bus"; |
| 17 | reg = <0x50000000 0x00024000>; | 21 | reg = <0x50000000 0x00024000>; |
| 18 | interrupts = <0 65 0x04 /* mpcore syncpt */ | 22 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 19 | 0 67 0x04>; /* mpcore general */ | 23 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ |
| 20 | clocks = <&tegra_car 28>; | 24 | clocks = <&tegra_car TEGRA20_CLK_HOST1X>; |
| 21 | 25 | ||
| 22 | #address-cells = <1>; | 26 | #address-cells = <1>; |
| 23 | #size-cells = <1>; | 27 | #size-cells = <1>; |
| @@ -27,49 +31,50 @@ | |||
| 27 | mpe { | 31 | mpe { |
| 28 | compatible = "nvidia,tegra20-mpe"; | 32 | compatible = "nvidia,tegra20-mpe"; |
| 29 | reg = <0x54040000 0x00040000>; | 33 | reg = <0x54040000 0x00040000>; |
| 30 | interrupts = <0 68 0x04>; | 34 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
| 31 | clocks = <&tegra_car 60>; | 35 | clocks = <&tegra_car TEGRA20_CLK_MPE>; |
| 32 | }; | 36 | }; |
| 33 | 37 | ||
| 34 | vi { | 38 | vi { |
| 35 | compatible = "nvidia,tegra20-vi"; | 39 | compatible = "nvidia,tegra20-vi"; |
| 36 | reg = <0x54080000 0x00040000>; | 40 | reg = <0x54080000 0x00040000>; |
| 37 | interrupts = <0 69 0x04>; | 41 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 38 | clocks = <&tegra_car 100>; | 42 | clocks = <&tegra_car TEGRA20_CLK_VI>; |
| 39 | }; | 43 | }; |
| 40 | 44 | ||
| 41 | epp { | 45 | epp { |
| 42 | compatible = "nvidia,tegra20-epp"; | 46 | compatible = "nvidia,tegra20-epp"; |
| 43 | reg = <0x540c0000 0x00040000>; | 47 | reg = <0x540c0000 0x00040000>; |
| 44 | interrupts = <0 70 0x04>; | 48 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 45 | clocks = <&tegra_car 19>; | 49 | clocks = <&tegra_car TEGRA20_CLK_EPP>; |
| 46 | }; | 50 | }; |
| 47 | 51 | ||
| 48 | isp { | 52 | isp { |
| 49 | compatible = "nvidia,tegra20-isp"; | 53 | compatible = "nvidia,tegra20-isp"; |
| 50 | reg = <0x54100000 0x00040000>; | 54 | reg = <0x54100000 0x00040000>; |
| 51 | interrupts = <0 71 0x04>; | 55 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 52 | clocks = <&tegra_car 23>; | 56 | clocks = <&tegra_car TEGRA20_CLK_ISP>; |
| 53 | }; | 57 | }; |
| 54 | 58 | ||
| 55 | gr2d { | 59 | gr2d { |
| 56 | compatible = "nvidia,tegra20-gr2d"; | 60 | compatible = "nvidia,tegra20-gr2d"; |
| 57 | reg = <0x54140000 0x00040000>; | 61 | reg = <0x54140000 0x00040000>; |
| 58 | interrupts = <0 72 0x04>; | 62 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| 59 | clocks = <&tegra_car 21>; | 63 | clocks = <&tegra_car TEGRA20_CLK_GR2D>; |
| 60 | }; | 64 | }; |
| 61 | 65 | ||
| 62 | gr3d { | 66 | gr3d { |
| 63 | compatible = "nvidia,tegra20-gr3d"; | 67 | compatible = "nvidia,tegra20-gr3d"; |
| 64 | reg = <0x54180000 0x00040000>; | 68 | reg = <0x54180000 0x00040000>; |
| 65 | clocks = <&tegra_car 24>; | 69 | clocks = <&tegra_car TEGRA20_CLK_GR3D>; |
| 66 | }; | 70 | }; |
| 67 | 71 | ||
| 68 | dc@54200000 { | 72 | dc@54200000 { |
| 69 | compatible = "nvidia,tegra20-dc"; | 73 | compatible = "nvidia,tegra20-dc"; |
| 70 | reg = <0x54200000 0x00040000>; | 74 | reg = <0x54200000 0x00040000>; |
| 71 | interrupts = <0 73 0x04>; | 75 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 72 | clocks = <&tegra_car 27>, <&tegra_car 121>; | 76 | clocks = <&tegra_car TEGRA20_CLK_DISP1>, |
| 77 | <&tegra_car TEGRA20_CLK_PLL_P>; | ||
| 73 | clock-names = "disp1", "parent"; | 78 | clock-names = "disp1", "parent"; |
| 74 | 79 | ||
| 75 | rgb { | 80 | rgb { |
| @@ -80,8 +85,9 @@ | |||
| 80 | dc@54240000 { | 85 | dc@54240000 { |
| 81 | compatible = "nvidia,tegra20-dc"; | 86 | compatible = "nvidia,tegra20-dc"; |
| 82 | reg = <0x54240000 0x00040000>; | 87 | reg = <0x54240000 0x00040000>; |
| 83 | interrupts = <0 74 0x04>; | 88 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 84 | clocks = <&tegra_car 26>, <&tegra_car 121>; | 89 | clocks = <&tegra_car TEGRA20_CLK_DISP2>, |
| 90 | <&tegra_car TEGRA20_CLK_PLL_P>; | ||
| 85 | clock-names = "disp2", "parent"; | 91 | clock-names = "disp2", "parent"; |
| 86 | 92 | ||
| 87 | rgb { | 93 | rgb { |
| @@ -92,8 +98,9 @@ | |||
| 92 | hdmi { | 98 | hdmi { |
| 93 | compatible = "nvidia,tegra20-hdmi"; | 99 | compatible = "nvidia,tegra20-hdmi"; |
| 94 | reg = <0x54280000 0x00040000>; | 100 | reg = <0x54280000 0x00040000>; |
| 95 | interrupts = <0 75 0x04>; | 101 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 96 | clocks = <&tegra_car 51>, <&tegra_car 117>; | 102 | clocks = <&tegra_car TEGRA20_CLK_HDMI>, |
| 103 | <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; | ||
| 97 | clock-names = "hdmi", "parent"; | 104 | clock-names = "hdmi", "parent"; |
| 98 | status = "disabled"; | 105 | status = "disabled"; |
| 99 | }; | 106 | }; |
| @@ -101,15 +108,15 @@ | |||
| 101 | tvo { | 108 | tvo { |
| 102 | compatible = "nvidia,tegra20-tvo"; | 109 | compatible = "nvidia,tegra20-tvo"; |
| 103 | reg = <0x542c0000 0x00040000>; | 110 | reg = <0x542c0000 0x00040000>; |
| 104 | interrupts = <0 76 0x04>; | 111 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 105 | clocks = <&tegra_car 102>; | 112 | clocks = <&tegra_car TEGRA20_CLK_TVO>; |
| 106 | status = "disabled"; | 113 | status = "disabled"; |
| 107 | }; | 114 | }; |
| 108 | 115 | ||
| 109 | dsi { | 116 | dsi { |
| 110 | compatible = "nvidia,tegra20-dsi"; | 117 | compatible = "nvidia,tegra20-dsi"; |
| 111 | reg = <0x54300000 0x00040000>; | 118 | reg = <0x54300000 0x00040000>; |
| 112 | clocks = <&tegra_car 48>; | 119 | clocks = <&tegra_car TEGRA20_CLK_DSI>; |
| 113 | status = "disabled"; | 120 | status = "disabled"; |
| 114 | }; | 121 | }; |
| 115 | }; | 122 | }; |
| @@ -117,8 +124,9 @@ | |||
| 117 | timer@50004600 { | 124 | timer@50004600 { |
| 118 | compatible = "arm,cortex-a9-twd-timer"; | 125 | compatible = "arm,cortex-a9-twd-timer"; |
| 119 | reg = <0x50040600 0x20>; | 126 | reg = <0x50040600 0x20>; |
| 120 | interrupts = <1 13 0x304>; | 127 | interrupts = <GIC_PPI 13 |
| 121 | clocks = <&tegra_car 132>; | 128 | (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
| 129 | clocks = <&tegra_car TEGRA20_CLK_TWD>; | ||
| 122 | }; | 130 | }; |
| 123 | 131 | ||
| 124 | intc: interrupt-controller { | 132 | intc: interrupt-controller { |
| @@ -141,11 +149,11 @@ | |||
| 141 | timer@60005000 { | 149 | timer@60005000 { |
| 142 | compatible = "nvidia,tegra20-timer"; | 150 | compatible = "nvidia,tegra20-timer"; |
| 143 | reg = <0x60005000 0x60>; | 151 | reg = <0x60005000 0x60>; |
| 144 | interrupts = <0 0 0x04 | 152 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 145 | 0 1 0x04 | 153 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 146 | 0 41 0x04 | 154 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 147 | 0 42 0x04>; | 155 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| 148 | clocks = <&tegra_car 5>; | 156 | clocks = <&tegra_car TEGRA20_CLK_TIMER>; |
| 149 | }; | 157 | }; |
| 150 | 158 | ||
| 151 | tegra_car: clock { | 159 | tegra_car: clock { |
| @@ -157,23 +165,23 @@ | |||
| 157 | apbdma: dma { | 165 | apbdma: dma { |
| 158 | compatible = "nvidia,tegra20-apbdma"; | 166 | compatible = "nvidia,tegra20-apbdma"; |
| 159 | reg = <0x6000a000 0x1200>; | 167 | reg = <0x6000a000 0x1200>; |
| 160 | interrupts = <0 104 0x04 | 168 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 161 | 0 105 0x04 | 169 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 162 | 0 106 0x04 | 170 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 163 | 0 107 0x04 | 171 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 164 | 0 108 0x04 | 172 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 165 | 0 109 0x04 | 173 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 166 | 0 110 0x04 | 174 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 167 | 0 111 0x04 | 175 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 168 | 0 112 0x04 | 176 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 169 | 0 113 0x04 | 177 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 170 | 0 114 0x04 | 178 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 171 | 0 115 0x04 | 179 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 172 | 0 116 0x04 | 180 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 173 | 0 117 0x04 | 181 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 174 | 0 118 0x04 | 182 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 175 | 0 119 0x04>; | 183 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| 176 | clocks = <&tegra_car 34>; | 184 | clocks = <&tegra_car TEGRA20_CLK_APBDMA>; |
| 177 | }; | 185 | }; |
| 178 | 186 | ||
| 179 | ahb { | 187 | ahb { |
| @@ -184,13 +192,13 @@ | |||
| 184 | gpio: gpio { | 192 | gpio: gpio { |
| 185 | compatible = "nvidia,tegra20-gpio"; | 193 | compatible = "nvidia,tegra20-gpio"; |
| 186 | reg = <0x6000d000 0x1000>; | 194 | reg = <0x6000d000 0x1000>; |
| 187 | interrupts = <0 32 0x04 | 195 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 188 | 0 33 0x04 | 196 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 189 | 0 34 0x04 | 197 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 190 | 0 35 0x04 | 198 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 191 | 0 55 0x04 | 199 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 192 | 0 87 0x04 | 200 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 193 | 0 89 0x04>; | 201 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| 194 | #gpio-cells = <2>; | 202 | #gpio-cells = <2>; |
| 195 | gpio-controller; | 203 | gpio-controller; |
| 196 | #interrupt-cells = <2>; | 204 | #interrupt-cells = <2>; |
| @@ -213,27 +221,27 @@ | |||
| 213 | tegra_ac97: ac97 { | 221 | tegra_ac97: ac97 { |
| 214 | compatible = "nvidia,tegra20-ac97"; | 222 | compatible = "nvidia,tegra20-ac97"; |
| 215 | reg = <0x70002000 0x200>; | 223 | reg = <0x70002000 0x200>; |
| 216 | interrupts = <0 81 0x04>; | 224 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| 217 | nvidia,dma-request-selector = <&apbdma 12>; | 225 | nvidia,dma-request-selector = <&apbdma 12>; |
| 218 | clocks = <&tegra_car 3>; | 226 | clocks = <&tegra_car TEGRA20_CLK_AC97>; |
| 219 | status = "disabled"; | 227 | status = "disabled"; |
| 220 | }; | 228 | }; |
| 221 | 229 | ||
| 222 | tegra_i2s1: i2s@70002800 { | 230 | tegra_i2s1: i2s@70002800 { |
| 223 | compatible = "nvidia,tegra20-i2s"; | 231 | compatible = "nvidia,tegra20-i2s"; |
| 224 | reg = <0x70002800 0x200>; | 232 | reg = <0x70002800 0x200>; |
| 225 | interrupts = <0 13 0x04>; | 233 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 226 | nvidia,dma-request-selector = <&apbdma 2>; | 234 | nvidia,dma-request-selector = <&apbdma 2>; |
| 227 | clocks = <&tegra_car 11>; | 235 | clocks = <&tegra_car TEGRA20_CLK_I2S1>; |
| 228 | status = "disabled"; | 236 | status = "disabled"; |
| 229 | }; | 237 | }; |
| 230 | 238 | ||
| 231 | tegra_i2s2: i2s@70002a00 { | 239 | tegra_i2s2: i2s@70002a00 { |
| 232 | compatible = "nvidia,tegra20-i2s"; | 240 | compatible = "nvidia,tegra20-i2s"; |
| 233 | reg = <0x70002a00 0x200>; | 241 | reg = <0x70002a00 0x200>; |
| 234 | interrupts = <0 3 0x04>; | 242 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| 235 | nvidia,dma-request-selector = <&apbdma 1>; | 243 | nvidia,dma-request-selector = <&apbdma 1>; |
| 236 | clocks = <&tegra_car 18>; | 244 | clocks = <&tegra_car TEGRA20_CLK_I2S2>; |
| 237 | status = "disabled"; | 245 | status = "disabled"; |
| 238 | }; | 246 | }; |
| 239 | 247 | ||
| @@ -248,9 +256,9 @@ | |||
| 248 | compatible = "nvidia,tegra20-uart"; | 256 | compatible = "nvidia,tegra20-uart"; |
| 249 | reg = <0x70006000 0x40>; | 257 | reg = <0x70006000 0x40>; |
| 250 | reg-shift = <2>; | 258 | reg-shift = <2>; |
| 251 | interrupts = <0 36 0x04>; | 259 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 252 | nvidia,dma-request-selector = <&apbdma 8>; | 260 | nvidia,dma-request-selector = <&apbdma 8>; |
| 253 | clocks = <&tegra_car 6>; | 261 | clocks = <&tegra_car TEGRA20_CLK_UARTA>; |
| 254 | status = "disabled"; | 262 | status = "disabled"; |
| 255 | }; | 263 | }; |
| 256 | 264 | ||
| @@ -258,9 +266,9 @@ | |||
| 258 | compatible = "nvidia,tegra20-uart"; | 266 | compatible = "nvidia,tegra20-uart"; |
| 259 | reg = <0x70006040 0x40>; | 267 | reg = <0x70006040 0x40>; |
| 260 | reg-shift = <2>; | 268 | reg-shift = <2>; |
| 261 | interrupts = <0 37 0x04>; | 269 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 262 | nvidia,dma-request-selector = <&apbdma 9>; | 270 | nvidia,dma-request-selector = <&apbdma 9>; |
| 263 | clocks = <&tegra_car 96>; | 271 | clocks = <&tegra_car TEGRA20_CLK_UARTB>; |
| 264 | status = "disabled"; | 272 | status = "disabled"; |
| 265 | }; | 273 | }; |
| 266 | 274 | ||
| @@ -268,9 +276,9 @@ | |||
| 268 | compatible = "nvidia,tegra20-uart"; | 276 | compatible = "nvidia,tegra20-uart"; |
| 269 | reg = <0x70006200 0x100>; | 277 | reg = <0x70006200 0x100>; |
| 270 | reg-shift = <2>; | 278 | reg-shift = <2>; |
| 271 | interrupts = <0 46 0x04>; | 279 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 272 | nvidia,dma-request-selector = <&apbdma 10>; | 280 | nvidia,dma-request-selector = <&apbdma 10>; |
| 273 | clocks = <&tegra_car 55>; | 281 | clocks = <&tegra_car TEGRA20_CLK_UARTC>; |
| 274 | status = "disabled"; | 282 | status = "disabled"; |
| 275 | }; | 283 | }; |
| 276 | 284 | ||
| @@ -278,9 +286,9 @@ | |||
| 278 | compatible = "nvidia,tegra20-uart"; | 286 | compatible = "nvidia,tegra20-uart"; |
| 279 | reg = <0x70006300 0x100>; | 287 | reg = <0x70006300 0x100>; |
| 280 | reg-shift = <2>; | 288 | reg-shift = <2>; |
| 281 | interrupts = <0 90 0x04>; | 289 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| 282 | nvidia,dma-request-selector = <&apbdma 19>; | 290 | nvidia,dma-request-selector = <&apbdma 19>; |
| 283 | clocks = <&tegra_car 65>; | 291 | clocks = <&tegra_car TEGRA20_CLK_UARTD>; |
| 284 | status = "disabled"; | 292 | status = "disabled"; |
| 285 | }; | 293 | }; |
| 286 | 294 | ||
| @@ -288,9 +296,9 @@ | |||
| 288 | compatible = "nvidia,tegra20-uart"; | 296 | compatible = "nvidia,tegra20-uart"; |
| 289 | reg = <0x70006400 0x100>; | 297 | reg = <0x70006400 0x100>; |
| 290 | reg-shift = <2>; | 298 | reg-shift = <2>; |
| 291 | interrupts = <0 91 0x04>; | 299 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| 292 | nvidia,dma-request-selector = <&apbdma 20>; | 300 | nvidia,dma-request-selector = <&apbdma 20>; |
| 293 | clocks = <&tegra_car 66>; | 301 | clocks = <&tegra_car TEGRA20_CLK_UARTE>; |
| 294 | status = "disabled"; | 302 | status = "disabled"; |
| 295 | }; | 303 | }; |
| 296 | 304 | ||
| @@ -298,24 +306,25 @@ | |||
| 298 | compatible = "nvidia,tegra20-pwm"; | 306 | compatible = "nvidia,tegra20-pwm"; |
| 299 | reg = <0x7000a000 0x100>; | 307 | reg = <0x7000a000 0x100>; |
| 300 | #pwm-cells = <2>; | 308 | #pwm-cells = <2>; |
| 301 | clocks = <&tegra_car 17>; | 309 | clocks = <&tegra_car TEGRA20_CLK_PWM>; |
| 302 | status = "disabled"; | 310 | status = "disabled"; |
| 303 | }; | 311 | }; |
| 304 | 312 | ||
| 305 | rtc { | 313 | rtc { |
| 306 | compatible = "nvidia,tegra20-rtc"; | 314 | compatible = "nvidia,tegra20-rtc"; |
| 307 | reg = <0x7000e000 0x100>; | 315 | reg = <0x7000e000 0x100>; |
| 308 | interrupts = <0 2 0x04>; | 316 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 309 | clocks = <&tegra_car 4>; | 317 | clocks = <&tegra_car TEGRA20_CLK_RTC>; |
| 310 | }; | 318 | }; |
| 311 | 319 | ||
| 312 | i2c@7000c000 { | 320 | i2c@7000c000 { |
| 313 | compatible = "nvidia,tegra20-i2c"; | 321 | compatible = "nvidia,tegra20-i2c"; |
| 314 | reg = <0x7000c000 0x100>; | 322 | reg = <0x7000c000 0x100>; |
| 315 | interrupts = <0 38 0x04>; | 323 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 316 | #address-cells = <1>; | 324 | #address-cells = <1>; |
| 317 | #size-cells = <0>; | 325 | #size-cells = <0>; |
| 318 | clocks = <&tegra_car 12>, <&tegra_car 124>; | 326 | clocks = <&tegra_car TEGRA20_CLK_I2C1>, |
| 327 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | ||
| 319 | clock-names = "div-clk", "fast-clk"; | 328 | clock-names = "div-clk", "fast-clk"; |
| 320 | status = "disabled"; | 329 | status = "disabled"; |
| 321 | }; | 330 | }; |
| @@ -323,21 +332,22 @@ | |||
| 323 | spi@7000c380 { | 332 | spi@7000c380 { |
| 324 | compatible = "nvidia,tegra20-sflash"; | 333 | compatible = "nvidia,tegra20-sflash"; |
| 325 | reg = <0x7000c380 0x80>; | 334 | reg = <0x7000c380 0x80>; |
| 326 | interrupts = <0 39 0x04>; | 335 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| 327 | nvidia,dma-request-selector = <&apbdma 11>; | 336 | nvidia,dma-request-selector = <&apbdma 11>; |
| 328 | #address-cells = <1>; | 337 | #address-cells = <1>; |
| 329 | #size-cells = <0>; | 338 | #size-cells = <0>; |
| 330 | clocks = <&tegra_car 43>; | 339 | clocks = <&tegra_car TEGRA20_CLK_SPI>; |
| 331 | status = "disabled"; | 340 | status = "disabled"; |
| 332 | }; | 341 | }; |
| 333 | 342 | ||
| 334 | i2c@7000c400 { | 343 | i2c@7000c400 { |
| 335 | compatible = "nvidia,tegra20-i2c"; | 344 | compatible = "nvidia,tegra20-i2c"; |
| 336 | reg = <0x7000c400 0x100>; | 345 | reg = <0x7000c400 0x100>; |
| 337 | interrupts = <0 84 0x04>; | 346 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 338 | #address-cells = <1>; | 347 | #address-cells = <1>; |
| 339 | #size-cells = <0>; | 348 | #size-cells = <0>; |
| 340 | clocks = <&tegra_car 54>, <&tegra_car 124>; | 349 | clocks = <&tegra_car TEGRA20_CLK_I2C2>, |
| 350 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | ||
| 341 | clock-names = "div-clk", "fast-clk"; | 351 | clock-names = "div-clk", "fast-clk"; |
| 342 | status = "disabled"; | 352 | status = "disabled"; |
| 343 | }; | 353 | }; |
| @@ -345,10 +355,11 @@ | |||
| 345 | i2c@7000c500 { | 355 | i2c@7000c500 { |
| 346 | compatible = "nvidia,tegra20-i2c"; | 356 | compatible = "nvidia,tegra20-i2c"; |
| 347 | reg = <0x7000c500 0x100>; | 357 | reg = <0x7000c500 0x100>; |
| 348 | interrupts = <0 92 0x04>; | 358 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 349 | #address-cells = <1>; | 359 | #address-cells = <1>; |
| 350 | #size-cells = <0>; | 360 | #size-cells = <0>; |
| 351 | clocks = <&tegra_car 67>, <&tegra_car 124>; | 361 | clocks = <&tegra_car TEGRA20_CLK_I2C3>, |
| 362 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | ||
| 352 | clock-names = "div-clk", "fast-clk"; | 363 | clock-names = "div-clk", "fast-clk"; |
| 353 | status = "disabled"; | 364 | status = "disabled"; |
| 354 | }; | 365 | }; |
| @@ -356,10 +367,11 @@ | |||
| 356 | i2c@7000d000 { | 367 | i2c@7000d000 { |
| 357 | compatible = "nvidia,tegra20-i2c-dvc"; | 368 | compatible = "nvidia,tegra20-i2c-dvc"; |
| 358 | reg = <0x7000d000 0x200>; | 369 | reg = <0x7000d000 0x200>; |
| 359 | interrupts = <0 53 0x04>; | 370 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 360 | #address-cells = <1>; | 371 | #address-cells = <1>; |
| 361 | #size-cells = <0>; | 372 | #size-cells = <0>; |
| 362 | clocks = <&tegra_car 47>, <&tegra_car 124>; | 373 | clocks = <&tegra_car TEGRA20_CLK_DVC>, |
| 374 | <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; | ||
| 363 | clock-names = "div-clk", "fast-clk"; | 375 | clock-names = "div-clk", "fast-clk"; |
| 364 | status = "disabled"; | 376 | status = "disabled"; |
| 365 | }; | 377 | }; |
| @@ -367,59 +379,59 @@ | |||
| 367 | spi@7000d400 { | 379 | spi@7000d400 { |
| 368 | compatible = "nvidia,tegra20-slink"; | 380 | compatible = "nvidia,tegra20-slink"; |
| 369 | reg = <0x7000d400 0x200>; | 381 | reg = <0x7000d400 0x200>; |
| 370 | interrupts = <0 59 0x04>; | 382 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 371 | nvidia,dma-request-selector = <&apbdma 15>; | 383 | nvidia,dma-request-selector = <&apbdma 15>; |
| 372 | #address-cells = <1>; | 384 | #address-cells = <1>; |
| 373 | #size-cells = <0>; | 385 | #size-cells = <0>; |
| 374 | clocks = <&tegra_car 41>; | 386 | clocks = <&tegra_car TEGRA20_CLK_SBC1>; |
| 375 | status = "disabled"; | 387 | status = "disabled"; |
| 376 | }; | 388 | }; |
| 377 | 389 | ||
| 378 | spi@7000d600 { | 390 | spi@7000d600 { |
| 379 | compatible = "nvidia,tegra20-slink"; | 391 | compatible = "nvidia,tegra20-slink"; |
| 380 | reg = <0x7000d600 0x200>; | 392 | reg = <0x7000d600 0x200>; |
| 381 | interrupts = <0 82 0x04>; | 393 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 382 | nvidia,dma-request-selector = <&apbdma 16>; | 394 | nvidia,dma-request-selector = <&apbdma 16>; |
| 383 | #address-cells = <1>; | 395 | #address-cells = <1>; |
| 384 | #size-cells = <0>; | 396 | #size-cells = <0>; |
| 385 | clocks = <&tegra_car 44>; | 397 | clocks = <&tegra_car TEGRA20_CLK_SBC2>; |
| 386 | status = "disabled"; | 398 | status = "disabled"; |
| 387 | }; | 399 | }; |
| 388 | 400 | ||
| 389 | spi@7000d800 { | 401 | spi@7000d800 { |
| 390 | compatible = "nvidia,tegra20-slink"; | 402 | compatible = "nvidia,tegra20-slink"; |
| 391 | reg = <0x7000d800 0x200>; | 403 | reg = <0x7000d800 0x200>; |
| 392 | interrupts = <0 83 0x04>; | 404 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 393 | nvidia,dma-request-selector = <&apbdma 17>; | 405 | nvidia,dma-request-selector = <&apbdma 17>; |
| 394 | #address-cells = <1>; | 406 | #address-cells = <1>; |
| 395 | #size-cells = <0>; | 407 | #size-cells = <0>; |
| 396 | clocks = <&tegra_car 46>; | 408 | clocks = <&tegra_car TEGRA20_CLK_SBC3>; |
| 397 | status = "disabled"; | 409 | status = "disabled"; |
| 398 | }; | 410 | }; |
| 399 | 411 | ||
| 400 | spi@7000da00 { | 412 | spi@7000da00 { |
| 401 | compatible = "nvidia,tegra20-slink"; | 413 | compatible = "nvidia,tegra20-slink"; |
| 402 | reg = <0x7000da00 0x200>; | 414 | reg = <0x7000da00 0x200>; |
| 403 | interrupts = <0 93 0x04>; | 415 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 404 | nvidia,dma-request-selector = <&apbdma 18>; | 416 | nvidia,dma-request-selector = <&apbdma 18>; |
| 405 | #address-cells = <1>; | 417 | #address-cells = <1>; |
| 406 | #size-cells = <0>; | 418 | #size-cells = <0>; |
| 407 | clocks = <&tegra_car 68>; | 419 | clocks = <&tegra_car TEGRA20_CLK_SBC4>; |
| 408 | status = "disabled"; | 420 | status = "disabled"; |
| 409 | }; | 421 | }; |
| 410 | 422 | ||
| 411 | kbc { | 423 | kbc { |
| 412 | compatible = "nvidia,tegra20-kbc"; | 424 | compatible = "nvidia,tegra20-kbc"; |
| 413 | reg = <0x7000e200 0x100>; | 425 | reg = <0x7000e200 0x100>; |
| 414 | interrupts = <0 85 0x04>; | 426 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 415 | clocks = <&tegra_car 36>; | 427 | clocks = <&tegra_car TEGRA20_CLK_KBC>; |
| 416 | status = "disabled"; | 428 | status = "disabled"; |
| 417 | }; | 429 | }; |
| 418 | 430 | ||
| 419 | pmc { | 431 | pmc { |
| 420 | compatible = "nvidia,tegra20-pmc"; | 432 | compatible = "nvidia,tegra20-pmc"; |
| 421 | reg = <0x7000e400 0x400>; | 433 | reg = <0x7000e400 0x400>; |
| 422 | clocks = <&tegra_car 110>, <&clk32k_in>; | 434 | clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; |
| 423 | clock-names = "pclk", "clk32k_in"; | 435 | clock-names = "pclk", "clk32k_in"; |
| 424 | }; | 436 | }; |
| 425 | 437 | ||
| @@ -427,7 +439,7 @@ | |||
| 427 | compatible = "nvidia,tegra20-mc"; | 439 | compatible = "nvidia,tegra20-mc"; |
| 428 | reg = <0x7000f000 0x024 | 440 | reg = <0x7000f000 0x024 |
| 429 | 0x7000f03c 0x3c4>; | 441 | 0x7000f03c 0x3c4>; |
| 430 | interrupts = <0 77 0x04>; | 442 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 431 | }; | 443 | }; |
| 432 | 444 | ||
| 433 | iommu { | 445 | iommu { |
| @@ -446,10 +458,10 @@ | |||
| 446 | usb@c5000000 { | 458 | usb@c5000000 { |
| 447 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | 459 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
| 448 | reg = <0xc5000000 0x4000>; | 460 | reg = <0xc5000000 0x4000>; |
| 449 | interrupts = <0 20 0x04>; | 461 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 450 | phy_type = "utmi"; | 462 | phy_type = "utmi"; |
| 451 | nvidia,has-legacy-mode; | 463 | nvidia,has-legacy-mode; |
| 452 | clocks = <&tegra_car 22>; | 464 | clocks = <&tegra_car TEGRA20_CLK_USBD>; |
| 453 | nvidia,needs-double-reset; | 465 | nvidia,needs-double-reset; |
| 454 | nvidia,phy = <&phy1>; | 466 | nvidia,phy = <&phy1>; |
| 455 | status = "disabled"; | 467 | status = "disabled"; |
| @@ -459,10 +471,10 @@ | |||
| 459 | compatible = "nvidia,tegra20-usb-phy"; | 471 | compatible = "nvidia,tegra20-usb-phy"; |
| 460 | reg = <0xc5000000 0x4000 0xc5000000 0x4000>; | 472 | reg = <0xc5000000 0x4000 0xc5000000 0x4000>; |
| 461 | phy_type = "utmi"; | 473 | phy_type = "utmi"; |
| 462 | clocks = <&tegra_car 22>, | 474 | clocks = <&tegra_car TEGRA20_CLK_USBD>, |
| 463 | <&tegra_car 127>, | 475 | <&tegra_car TEGRA20_CLK_PLL_U>, |
| 464 | <&tegra_car 106>, | 476 | <&tegra_car TEGRA20_CLK_CLK_M>, |
| 465 | <&tegra_car 22>; | 477 | <&tegra_car TEGRA20_CLK_USBD>; |
| 466 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; | 478 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
| 467 | nvidia,has-legacy-mode; | 479 | nvidia,has-legacy-mode; |
| 468 | hssync_start_delay = <9>; | 480 | hssync_start_delay = <9>; |
| @@ -478,9 +490,9 @@ | |||
| 478 | usb@c5004000 { | 490 | usb@c5004000 { |
| 479 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | 491 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
| 480 | reg = <0xc5004000 0x4000>; | 492 | reg = <0xc5004000 0x4000>; |
| 481 | interrupts = <0 21 0x04>; | 493 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| 482 | phy_type = "ulpi"; | 494 | phy_type = "ulpi"; |
| 483 | clocks = <&tegra_car 58>; | 495 | clocks = <&tegra_car TEGRA20_CLK_USB2>; |
| 484 | nvidia,phy = <&phy2>; | 496 | nvidia,phy = <&phy2>; |
| 485 | status = "disabled"; | 497 | status = "disabled"; |
| 486 | }; | 498 | }; |
| @@ -489,9 +501,9 @@ | |||
| 489 | compatible = "nvidia,tegra20-usb-phy"; | 501 | compatible = "nvidia,tegra20-usb-phy"; |
| 490 | reg = <0xc5004000 0x4000>; | 502 | reg = <0xc5004000 0x4000>; |
| 491 | phy_type = "ulpi"; | 503 | phy_type = "ulpi"; |
| 492 | clocks = <&tegra_car 58>, | 504 | clocks = <&tegra_car TEGRA20_CLK_USB2>, |
| 493 | <&tegra_car 127>, | 505 | <&tegra_car TEGRA20_CLK_PLL_U>, |
| 494 | <&tegra_car 93>; | 506 | <&tegra_car TEGRA20_CLK_CDEV2>; |
| 495 | clock-names = "reg", "pll_u", "ulpi-link"; | 507 | clock-names = "reg", "pll_u", "ulpi-link"; |
| 496 | status = "disabled"; | 508 | status = "disabled"; |
| 497 | }; | 509 | }; |
| @@ -499,9 +511,9 @@ | |||
| 499 | usb@c5008000 { | 511 | usb@c5008000 { |
| 500 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | 512 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
| 501 | reg = <0xc5008000 0x4000>; | 513 | reg = <0xc5008000 0x4000>; |
| 502 | interrupts = <0 97 0x04>; | 514 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 503 | phy_type = "utmi"; | 515 | phy_type = "utmi"; |
| 504 | clocks = <&tegra_car 59>; | 516 | clocks = <&tegra_car TEGRA20_CLK_USB3>; |
| 505 | nvidia,phy = <&phy3>; | 517 | nvidia,phy = <&phy3>; |
| 506 | status = "disabled"; | 518 | status = "disabled"; |
| 507 | }; | 519 | }; |
| @@ -510,10 +522,10 @@ | |||
| 510 | compatible = "nvidia,tegra20-usb-phy"; | 522 | compatible = "nvidia,tegra20-usb-phy"; |
| 511 | reg = <0xc5008000 0x4000 0xc5000000 0x4000>; | 523 | reg = <0xc5008000 0x4000 0xc5000000 0x4000>; |
| 512 | phy_type = "utmi"; | 524 | phy_type = "utmi"; |
| 513 | clocks = <&tegra_car 59>, | 525 | clocks = <&tegra_car TEGRA20_CLK_USB3>, |
| 514 | <&tegra_car 127>, | 526 | <&tegra_car TEGRA20_CLK_PLL_U>, |
| 515 | <&tegra_car 106>, | 527 | <&tegra_car TEGRA20_CLK_CLK_M>, |
| 516 | <&tegra_car 22>; | 528 | <&tegra_car TEGRA20_CLK_USBD>; |
| 517 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; | 529 | clock-names = "reg", "pll_u", "timer", "utmi-pads"; |
| 518 | hssync_start_delay = <9>; | 530 | hssync_start_delay = <9>; |
| 519 | idle_wait_delay = <17>; | 531 | idle_wait_delay = <17>; |
| @@ -528,32 +540,32 @@ | |||
| 528 | sdhci@c8000000 { | 540 | sdhci@c8000000 { |
| 529 | compatible = "nvidia,tegra20-sdhci"; | 541 | compatible = "nvidia,tegra20-sdhci"; |
| 530 | reg = <0xc8000000 0x200>; | 542 | reg = <0xc8000000 0x200>; |
| 531 | interrupts = <0 14 0x04>; | 543 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 532 | clocks = <&tegra_car 14>; | 544 | clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; |
| 533 | status = "disabled"; | 545 | status = "disabled"; |
| 534 | }; | 546 | }; |
| 535 | 547 | ||
| 536 | sdhci@c8000200 { | 548 | sdhci@c8000200 { |
| 537 | compatible = "nvidia,tegra20-sdhci"; | 549 | compatible = "nvidia,tegra20-sdhci"; |
| 538 | reg = <0xc8000200 0x200>; | 550 | reg = <0xc8000200 0x200>; |
| 539 | interrupts = <0 15 0x04>; | 551 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 540 | clocks = <&tegra_car 9>; | 552 | clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; |
| 541 | status = "disabled"; | 553 | status = "disabled"; |
| 542 | }; | 554 | }; |
| 543 | 555 | ||
| 544 | sdhci@c8000400 { | 556 | sdhci@c8000400 { |
| 545 | compatible = "nvidia,tegra20-sdhci"; | 557 | compatible = "nvidia,tegra20-sdhci"; |
| 546 | reg = <0xc8000400 0x200>; | 558 | reg = <0xc8000400 0x200>; |
| 547 | interrupts = <0 19 0x04>; | 559 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 548 | clocks = <&tegra_car 69>; | 560 | clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; |
| 549 | status = "disabled"; | 561 | status = "disabled"; |
| 550 | }; | 562 | }; |
| 551 | 563 | ||
| 552 | sdhci@c8000600 { | 564 | sdhci@c8000600 { |
| 553 | compatible = "nvidia,tegra20-sdhci"; | 565 | compatible = "nvidia,tegra20-sdhci"; |
| 554 | reg = <0xc8000600 0x200>; | 566 | reg = <0xc8000600 0x200>; |
| 555 | interrupts = <0 31 0x04>; | 567 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 556 | clocks = <&tegra_car 15>; | 568 | clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; |
| 557 | status = "disabled"; | 569 | status = "disabled"; |
| 558 | }; | 570 | }; |
| 559 | 571 | ||
| @@ -576,7 +588,7 @@ | |||
| 576 | 588 | ||
| 577 | pmu { | 589 | pmu { |
| 578 | compatible = "arm,cortex-a9-pmu"; | 590 | compatible = "arm,cortex-a9-pmu"; |
| 579 | interrupts = <0 56 0x04 | 591 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| 580 | 0 57 0x04>; | 592 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| 581 | }; | 593 | }; |
| 582 | }; | 594 | }; |
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index b732f7c13a66..87c5f7b7c271 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts | |||
| @@ -1,13 +1,13 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra30.dtsi" | 3 | #include "tegra30.dtsi" |
| 4 | 4 | ||
| 5 | / { | 5 | / { |
| 6 | model = "NVIDIA Tegra30 Beaver evaluation board"; | 6 | model = "NVIDIA Tegra30 Beaver evaluation board"; |
| 7 | compatible = "nvidia,beaver", "nvidia,tegra30"; | 7 | compatible = "nvidia,beaver", "nvidia,tegra30"; |
| 8 | 8 | ||
| 9 | memory { | 9 | memory { |
| 10 | reg = <0x80000000 0x80000000>; | 10 | reg = <0x80000000 0x7ff00000>; |
| 11 | }; | 11 | }; |
| 12 | 12 | ||
| 13 | pinmux { | 13 | pinmux { |
| @@ -116,6 +116,15 @@ | |||
| 116 | status = "okay"; | 116 | status = "okay"; |
| 117 | clock-frequency = <100000>; | 117 | clock-frequency = <100000>; |
| 118 | 118 | ||
| 119 | rt5640: rt5640 { | ||
| 120 | compatible = "realtek,rt5640"; | ||
| 121 | reg = <0x1c>; | ||
| 122 | interrupt-parent = <&gpio>; | ||
| 123 | interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>; | ||
| 124 | realtek,ldo1-en-gpios = | ||
| 125 | <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; | ||
| 126 | }; | ||
| 127 | |||
| 119 | tps62361 { | 128 | tps62361 { |
| 120 | compatible = "ti,tps62361"; | 129 | compatible = "ti,tps62361"; |
| 121 | reg = <0x60>; | 130 | reg = <0x60>; |
| @@ -133,7 +142,7 @@ | |||
| 133 | compatible = "ti,tps65911"; | 142 | compatible = "ti,tps65911"; |
| 134 | reg = <0x2d>; | 143 | reg = <0x2d>; |
| 135 | 144 | ||
| 136 | interrupts = <0 86 0x4>; | 145 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 137 | #interrupt-cells = <2>; | 146 | #interrupt-cells = <2>; |
| 138 | interrupt-controller; | 147 | interrupt-controller; |
| 139 | 148 | ||
| @@ -264,9 +273,9 @@ | |||
| 264 | 273 | ||
| 265 | sdhci@78000000 { | 274 | sdhci@78000000 { |
| 266 | status = "okay"; | 275 | status = "okay"; |
| 267 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ | 276 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 268 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ | 277 | wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; |
| 269 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ | 278 | power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; |
| 270 | bus-width = <4>; | 279 | bus-width = <4>; |
| 271 | }; | 280 | }; |
| 272 | 281 | ||
| @@ -312,7 +321,7 @@ | |||
| 312 | regulator-boot-on; | 321 | regulator-boot-on; |
| 313 | regulator-always-on; | 322 | regulator-always-on; |
| 314 | enable-active-high; | 323 | enable-active-high; |
| 315 | gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ | 324 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
| 316 | }; | 325 | }; |
| 317 | 326 | ||
| 318 | ddr_reg: regulator@2 { | 327 | ddr_reg: regulator@2 { |
| @@ -324,7 +333,7 @@ | |||
| 324 | regulator-always-on; | 333 | regulator-always-on; |
| 325 | regulator-boot-on; | 334 | regulator-boot-on; |
| 326 | enable-active-high; | 335 | enable-active-high; |
| 327 | gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */ | 336 | gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; |
| 328 | vin-supply = <&vdd_5v_in_reg>; | 337 | vin-supply = <&vdd_5v_in_reg>; |
| 329 | }; | 338 | }; |
| 330 | 339 | ||
| @@ -337,7 +346,7 @@ | |||
| 337 | regulator-always-on; | 346 | regulator-always-on; |
| 338 | regulator-boot-on; | 347 | regulator-boot-on; |
| 339 | enable-active-high; | 348 | enable-active-high; |
| 340 | gpio = <&gpio 30 0>; /* gpio PD6 */ | 349 | gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; |
| 341 | vin-supply = <&vdd_5v_in_reg>; | 350 | vin-supply = <&vdd_5v_in_reg>; |
| 342 | }; | 351 | }; |
| 343 | 352 | ||
| @@ -348,7 +357,7 @@ | |||
| 348 | regulator-min-microvolt = <5000000>; | 357 | regulator-min-microvolt = <5000000>; |
| 349 | regulator-max-microvolt = <5000000>; | 358 | regulator-max-microvolt = <5000000>; |
| 350 | enable-active-high; | 359 | enable-active-high; |
| 351 | gpio = <&gpio 68 0>; /* GPIO PI4 */ | 360 | gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; |
| 352 | gpio-open-drain; | 361 | gpio-open-drain; |
| 353 | vin-supply = <&vdd_5v_in_reg>; | 362 | vin-supply = <&vdd_5v_in_reg>; |
| 354 | }; | 363 | }; |
| @@ -360,7 +369,7 @@ | |||
| 360 | regulator-min-microvolt = <5000000>; | 369 | regulator-min-microvolt = <5000000>; |
| 361 | regulator-max-microvolt = <5000000>; | 370 | regulator-max-microvolt = <5000000>; |
| 362 | enable-active-high; | 371 | enable-active-high; |
| 363 | gpio = <&gpio 63 0>; /* GPIO PH7 */ | 372 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; |
| 364 | gpio-open-drain; | 373 | gpio-open-drain; |
| 365 | vin-supply = <&vdd_5v_in_reg>; | 374 | vin-supply = <&vdd_5v_in_reg>; |
| 366 | }; | 375 | }; |
| @@ -374,7 +383,7 @@ | |||
| 374 | regulator-always-on; | 383 | regulator-always-on; |
| 375 | regulator-boot-on; | 384 | regulator-boot-on; |
| 376 | enable-active-high; | 385 | enable-active-high; |
| 377 | gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */ | 386 | gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; |
| 378 | vin-supply = <&vdd_5v_in_reg>; | 387 | vin-supply = <&vdd_5v_in_reg>; |
| 379 | }; | 388 | }; |
| 380 | 389 | ||
| @@ -387,8 +396,41 @@ | |||
| 387 | regulator-always-on; | 396 | regulator-always-on; |
| 388 | regulator-boot-on; | 397 | regulator-boot-on; |
| 389 | enable-active-high; | 398 | enable-active-high; |
| 390 | gpio = <&gpio 95 0>; /* gpio PL7 */ | 399 | gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; |
| 391 | vin-supply = <&sys_3v3_reg>; | 400 | vin-supply = <&sys_3v3_reg>; |
| 392 | }; | 401 | }; |
| 393 | }; | 402 | }; |
| 403 | |||
| 404 | gpio-leds { | ||
| 405 | compatible = "gpio-leds"; | ||
| 406 | |||
| 407 | gpled1 { | ||
| 408 | label = "LED1"; /* CR5A1 (blue) */ | ||
| 409 | gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; | ||
| 410 | }; | ||
| 411 | gpled2 { | ||
| 412 | label = "LED2"; /* CR4A2 (green) */ | ||
| 413 | gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; | ||
| 414 | }; | ||
| 415 | }; | ||
| 416 | |||
| 417 | sound { | ||
| 418 | compatible = "nvidia,tegra-audio-rt5640-beaver", | ||
| 419 | "nvidia,tegra-audio-rt5640"; | ||
| 420 | nvidia,model = "NVIDIA Tegra Beaver"; | ||
| 421 | |||
| 422 | nvidia,audio-routing = | ||
| 423 | "Headphones", "HPOR", | ||
| 424 | "Headphones", "HPOL"; | ||
| 425 | |||
| 426 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
| 427 | nvidia,audio-codec = <&rt5640>; | ||
| 428 | |||
| 429 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; | ||
| 430 | |||
| 431 | clocks = <&tegra_car TEGRA30_CLK_PLL_A>, | ||
| 432 | <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, | ||
| 433 | <&tegra_car TEGRA30_CLK_EXTERN1>; | ||
| 434 | clock-names = "pll_a", "pll_a_out0", "mclk"; | ||
| 435 | }; | ||
| 394 | }; | 436 | }; |
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index e392bd2dab9b..1082c5ed90d1 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra30-cardhu.dtsi" | 3 | #include "tegra30-cardhu.dtsi" |
| 4 | 4 | ||
| 5 | /* This dts file support the cardhu A02 version of board */ | 5 | /* This dts file support the cardhu A02 version of board */ |
| 6 | 6 | ||
| @@ -22,7 +22,7 @@ | |||
| 22 | regulator-always-on; | 22 | regulator-always-on; |
| 23 | regulator-boot-on; | 23 | regulator-boot-on; |
| 24 | enable-active-high; | 24 | enable-active-high; |
| 25 | gpio = <&pmic 6 0>; | 25 | gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; |
| 26 | }; | 26 | }; |
| 27 | 27 | ||
| 28 | sys_3v3_reg: regulator@101 { | 28 | sys_3v3_reg: regulator@101 { |
| @@ -34,7 +34,7 @@ | |||
| 34 | regulator-always-on; | 34 | regulator-always-on; |
| 35 | regulator-boot-on; | 35 | regulator-boot-on; |
| 36 | enable-active-high; | 36 | enable-active-high; |
| 37 | gpio = <&pmic 7 0>; | 37 | gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; |
| 38 | }; | 38 | }; |
| 39 | 39 | ||
| 40 | usb1_vbus_reg: regulator@102 { | 40 | usb1_vbus_reg: regulator@102 { |
| @@ -44,7 +44,7 @@ | |||
| 44 | regulator-min-microvolt = <5000000>; | 44 | regulator-min-microvolt = <5000000>; |
| 45 | regulator-max-microvolt = <5000000>; | 45 | regulator-max-microvolt = <5000000>; |
| 46 | enable-active-high; | 46 | enable-active-high; |
| 47 | gpio = <&gpio 68 0>; /* GPIO PI4 */ | 47 | gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; |
| 48 | gpio-open-drain; | 48 | gpio-open-drain; |
| 49 | vin-supply = <&vdd_5v0_reg>; | 49 | vin-supply = <&vdd_5v0_reg>; |
| 50 | }; | 50 | }; |
| @@ -56,7 +56,7 @@ | |||
| 56 | regulator-min-microvolt = <5000000>; | 56 | regulator-min-microvolt = <5000000>; |
| 57 | regulator-max-microvolt = <5000000>; | 57 | regulator-max-microvolt = <5000000>; |
| 58 | enable-active-high; | 58 | enable-active-high; |
| 59 | gpio = <&gpio 63 0>; /* GPIO PH7 */ | 59 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; |
| 60 | gpio-open-drain; | 60 | gpio-open-drain; |
| 61 | vin-supply = <&vdd_5v0_reg>; | 61 | vin-supply = <&vdd_5v0_reg>; |
| 62 | }; | 62 | }; |
| @@ -68,7 +68,7 @@ | |||
| 68 | regulator-min-microvolt = <5000000>; | 68 | regulator-min-microvolt = <5000000>; |
| 69 | regulator-max-microvolt = <5000000>; | 69 | regulator-max-microvolt = <5000000>; |
| 70 | enable-active-high; | 70 | enable-active-high; |
| 71 | gpio = <&pmic 2 0>; | 71 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; |
| 72 | }; | 72 | }; |
| 73 | 73 | ||
| 74 | vdd_bl_reg: regulator@105 { | 74 | vdd_bl_reg: regulator@105 { |
| @@ -80,13 +80,13 @@ | |||
| 80 | regulator-always-on; | 80 | regulator-always-on; |
| 81 | regulator-boot-on; | 81 | regulator-boot-on; |
| 82 | enable-active-high; | 82 | enable-active-high; |
| 83 | gpio = <&gpio 83 0>; /* GPIO PK3 */ | 83 | gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; |
| 84 | }; | 84 | }; |
| 85 | }; | 85 | }; |
| 86 | 86 | ||
| 87 | sdhci@78000400 { | 87 | sdhci@78000400 { |
| 88 | status = "okay"; | 88 | status = "okay"; |
| 89 | power-gpios = <&gpio 28 0>; /* gpio PD4 */ | 89 | power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; |
| 90 | bus-width = <4>; | 90 | bus-width = <4>; |
| 91 | keep-power-in-suspend; | 91 | keep-power-in-suspend; |
| 92 | }; | 92 | }; |
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index d0db6c7e774f..bf012bddaafb 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /dts-v1/; | 1 | /dts-v1/; |
| 2 | 2 | ||
| 3 | /include/ "tegra30-cardhu.dtsi" | 3 | #include "tegra30-cardhu.dtsi" |
| 4 | 4 | ||
| 5 | /* This dts file support the cardhu A04 and later versions of board */ | 5 | /* This dts file support the cardhu A04 and later versions of board */ |
| 6 | 6 | ||
| @@ -22,7 +22,7 @@ | |||
| 22 | regulator-always-on; | 22 | regulator-always-on; |
| 23 | regulator-boot-on; | 23 | regulator-boot-on; |
| 24 | enable-active-high; | 24 | enable-active-high; |
| 25 | gpio = <&pmic 7 0>; | 25 | gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; |
| 26 | }; | 26 | }; |
| 27 | 27 | ||
| 28 | sys_3v3_reg: regulator@101 { | 28 | sys_3v3_reg: regulator@101 { |
| @@ -34,7 +34,7 @@ | |||
| 34 | regulator-always-on; | 34 | regulator-always-on; |
| 35 | regulator-boot-on; | 35 | regulator-boot-on; |
| 36 | enable-active-high; | 36 | enable-active-high; |
| 37 | gpio = <&pmic 6 0>; | 37 | gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; |
| 38 | }; | 38 | }; |
| 39 | 39 | ||
| 40 | usb1_vbus_reg: regulator@102 { | 40 | usb1_vbus_reg: regulator@102 { |
| @@ -44,7 +44,7 @@ | |||
| 44 | regulator-min-microvolt = <5000000>; | 44 | regulator-min-microvolt = <5000000>; |
| 45 | regulator-max-microvolt = <5000000>; | 45 | regulator-max-microvolt = <5000000>; |
| 46 | enable-active-high; | 46 | enable-active-high; |
| 47 | gpio = <&gpio 238 0>; /* GPIO PDD6 */ | 47 | gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>; |
| 48 | gpio-open-drain; | 48 | gpio-open-drain; |
| 49 | vin-supply = <&vdd_5v0_reg>; | 49 | vin-supply = <&vdd_5v0_reg>; |
| 50 | }; | 50 | }; |
| @@ -56,7 +56,7 @@ | |||
| 56 | regulator-min-microvolt = <5000000>; | 56 | regulator-min-microvolt = <5000000>; |
| 57 | regulator-max-microvolt = <5000000>; | 57 | regulator-max-microvolt = <5000000>; |
| 58 | enable-active-high; | 58 | enable-active-high; |
| 59 | gpio = <&gpio 236 0>; /* GPIO PDD4 */ | 59 | gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; |
| 60 | gpio-open-drain; | 60 | gpio-open-drain; |
| 61 | vin-supply = <&vdd_5v0_reg>; | 61 | vin-supply = <&vdd_5v0_reg>; |
| 62 | }; | 62 | }; |
| @@ -68,7 +68,7 @@ | |||
| 68 | regulator-min-microvolt = <5000000>; | 68 | regulator-min-microvolt = <5000000>; |
| 69 | regulator-max-microvolt = <5000000>; | 69 | regulator-max-microvolt = <5000000>; |
| 70 | enable-active-high; | 70 | enable-active-high; |
| 71 | gpio = <&pmic 8 0>; | 71 | gpio = <&pmic 8 GPIO_ACTIVE_HIGH>; |
| 72 | }; | 72 | }; |
| 73 | 73 | ||
| 74 | vdd_bl_reg: regulator@105 { | 74 | vdd_bl_reg: regulator@105 { |
| @@ -80,7 +80,7 @@ | |||
| 80 | regulator-always-on; | 80 | regulator-always-on; |
| 81 | regulator-boot-on; | 81 | regulator-boot-on; |
| 82 | enable-active-high; | 82 | enable-active-high; |
| 83 | gpio = <&gpio 234 0>; /* GPIO PDD2 */ | 83 | gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>; |
| 84 | }; | 84 | }; |
| 85 | 85 | ||
| 86 | vdd_bl2_reg: regulator@106 { | 86 | vdd_bl2_reg: regulator@106 { |
| @@ -92,13 +92,13 @@ | |||
| 92 | regulator-always-on; | 92 | regulator-always-on; |
| 93 | regulator-boot-on; | 93 | regulator-boot-on; |
| 94 | enable-active-high; | 94 | enable-active-high; |
| 95 | gpio = <&gpio 232 0>; /* GPIO PDD0 */ | 95 | gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; |
| 96 | }; | 96 | }; |
| 97 | }; | 97 | }; |
| 98 | 98 | ||
| 99 | sdhci@78000400 { | 99 | sdhci@78000400 { |
| 100 | status = "okay"; | 100 | status = "okay"; |
| 101 | power-gpios = <&gpio 27 0>; /* gpio PD3 */ | 101 | power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; |
| 102 | bus-width = <4>; | 102 | bus-width = <4>; |
| 103 | keep-power-in-suspend; | 103 | keep-power-in-suspend; |
| 104 | }; | 104 | }; |
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 01b4c26fad96..f65b53d32416 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /include/ "tegra30.dtsi" | 1 | #include "tegra30.dtsi" |
| 2 | 2 | ||
| 3 | /** | 3 | /** |
| 4 | * This file contains common DT entry for all fab version of Cardhu. | 4 | * This file contains common DT entry for all fab version of Cardhu. |
| @@ -146,7 +146,7 @@ | |||
| 146 | compatible = "isil,isl29028"; | 146 | compatible = "isil,isl29028"; |
| 147 | reg = <0x44>; | 147 | reg = <0x44>; |
| 148 | interrupt-parent = <&gpio>; | 148 | interrupt-parent = <&gpio>; |
| 149 | interrupts = <88 0x04>; /*gpio PL0 */ | 149 | interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>; |
| 150 | }; | 150 | }; |
| 151 | }; | 151 | }; |
| 152 | 152 | ||
| @@ -163,7 +163,7 @@ | |||
| 163 | compatible = "wlf,wm8903"; | 163 | compatible = "wlf,wm8903"; |
| 164 | reg = <0x1a>; | 164 | reg = <0x1a>; |
| 165 | interrupt-parent = <&gpio>; | 165 | interrupt-parent = <&gpio>; |
| 166 | interrupts = <179 0x04>; /* gpio PW3 */ | 166 | interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>; |
| 167 | 167 | ||
| 168 | gpio-controller; | 168 | gpio-controller; |
| 169 | #gpio-cells = <2>; | 169 | #gpio-cells = <2>; |
| @@ -190,7 +190,7 @@ | |||
| 190 | compatible = "ti,tps65911"; | 190 | compatible = "ti,tps65911"; |
| 191 | reg = <0x2d>; | 191 | reg = <0x2d>; |
| 192 | 192 | ||
| 193 | interrupts = <0 86 0x4>; | 193 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 194 | #interrupt-cells = <2>; | 194 | #interrupt-cells = <2>; |
| 195 | interrupt-controller; | 195 | interrupt-controller; |
| 196 | 196 | ||
| @@ -318,9 +318,9 @@ | |||
| 318 | 318 | ||
| 319 | sdhci@78000000 { | 319 | sdhci@78000000 { |
| 320 | status = "okay"; | 320 | status = "okay"; |
| 321 | cd-gpios = <&gpio 69 1>; /* gpio PI5 */ | 321 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 322 | wp-gpios = <&gpio 155 0>; /* gpio PT3 */ | 322 | wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; |
| 323 | power-gpios = <&gpio 31 0>; /* gpio PD7 */ | 323 | power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; |
| 324 | bus-width = <4>; | 324 | bus-width = <4>; |
| 325 | }; | 325 | }; |
| 326 | 326 | ||
| @@ -364,7 +364,7 @@ | |||
| 364 | regulator-min-microvolt = <1800000>; | 364 | regulator-min-microvolt = <1800000>; |
| 365 | regulator-max-microvolt = <1800000>; | 365 | regulator-max-microvolt = <1800000>; |
| 366 | enable-active-high; | 366 | enable-active-high; |
| 367 | gpio = <&gpio 220 0>; /* gpio PBB4 */ | 367 | gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; |
| 368 | vin-supply = <&vio_reg>; | 368 | vin-supply = <&vio_reg>; |
| 369 | }; | 369 | }; |
| 370 | 370 | ||
| @@ -377,7 +377,7 @@ | |||
| 377 | regulator-boot-on; | 377 | regulator-boot-on; |
| 378 | regulator-always-on; | 378 | regulator-always-on; |
| 379 | enable-active-high; | 379 | enable-active-high; |
| 380 | gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */ | 380 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
| 381 | }; | 381 | }; |
| 382 | 382 | ||
| 383 | emmc_3v3_reg: regulator@3 { | 383 | emmc_3v3_reg: regulator@3 { |
| @@ -389,7 +389,7 @@ | |||
| 389 | regulator-always-on; | 389 | regulator-always-on; |
| 390 | regulator-boot-on; | 390 | regulator-boot-on; |
| 391 | enable-active-high; | 391 | enable-active-high; |
| 392 | gpio = <&gpio 25 0>; /* gpio PD1 */ | 392 | gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; |
| 393 | vin-supply = <&sys_3v3_reg>; | 393 | vin-supply = <&sys_3v3_reg>; |
| 394 | }; | 394 | }; |
| 395 | 395 | ||
| @@ -400,7 +400,7 @@ | |||
| 400 | regulator-min-microvolt = <3300000>; | 400 | regulator-min-microvolt = <3300000>; |
| 401 | regulator-max-microvolt = <3300000>; | 401 | regulator-max-microvolt = <3300000>; |
| 402 | enable-active-high; | 402 | enable-active-high; |
| 403 | gpio = <&gpio 30 0>; /* gpio PD6 */ | 403 | gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>; |
| 404 | }; | 404 | }; |
| 405 | 405 | ||
| 406 | pex_hvdd_3v3_reg: regulator@5 { | 406 | pex_hvdd_3v3_reg: regulator@5 { |
| @@ -410,7 +410,7 @@ | |||
| 410 | regulator-min-microvolt = <3300000>; | 410 | regulator-min-microvolt = <3300000>; |
| 411 | regulator-max-microvolt = <3300000>; | 411 | regulator-max-microvolt = <3300000>; |
| 412 | enable-active-high; | 412 | enable-active-high; |
| 413 | gpio = <&gpio 95 0>; /* gpio PL7 */ | 413 | gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; |
| 414 | vin-supply = <&sys_3v3_reg>; | 414 | vin-supply = <&sys_3v3_reg>; |
| 415 | }; | 415 | }; |
| 416 | 416 | ||
| @@ -421,7 +421,7 @@ | |||
| 421 | regulator-min-microvolt = <2800000>; | 421 | regulator-min-microvolt = <2800000>; |
| 422 | regulator-max-microvolt = <2800000>; | 422 | regulator-max-microvolt = <2800000>; |
| 423 | enable-active-high; | 423 | enable-active-high; |
| 424 | gpio = <&gpio 142 0>; /* gpio PR6 */ | 424 | gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; |
| 425 | vin-supply = <&sys_3v3_reg>; | 425 | vin-supply = <&sys_3v3_reg>; |
| 426 | }; | 426 | }; |
| 427 | 427 | ||
| @@ -432,7 +432,7 @@ | |||
| 432 | regulator-min-microvolt = <2800000>; | 432 | regulator-min-microvolt = <2800000>; |
| 433 | regulator-max-microvolt = <2800000>; | 433 | regulator-max-microvolt = <2800000>; |
| 434 | enable-active-high; | 434 | enable-active-high; |
| 435 | gpio = <&gpio 143 0>; /* gpio PR7 */ | 435 | gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; |
| 436 | vin-supply = <&sys_3v3_reg>; | 436 | vin-supply = <&sys_3v3_reg>; |
| 437 | }; | 437 | }; |
| 438 | 438 | ||
| @@ -443,7 +443,7 @@ | |||
| 443 | regulator-min-microvolt = <3300000>; | 443 | regulator-min-microvolt = <3300000>; |
| 444 | regulator-max-microvolt = <3300000>; | 444 | regulator-max-microvolt = <3300000>; |
| 445 | enable-active-high; | 445 | enable-active-high; |
| 446 | gpio = <&gpio 144 0>; /* gpio PS0 */ | 446 | gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; |
| 447 | vin-supply = <&sys_3v3_reg>; | 447 | vin-supply = <&sys_3v3_reg>; |
| 448 | }; | 448 | }; |
| 449 | 449 | ||
| @@ -456,7 +456,7 @@ | |||
| 456 | regulator-always-on; | 456 | regulator-always-on; |
| 457 | regulator-boot-on; | 457 | regulator-boot-on; |
| 458 | enable-active-high; | 458 | enable-active-high; |
| 459 | gpio = <&gpio 24 0>; /* gpio PD0 */ | 459 | gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; |
| 460 | vin-supply = <&sys_3v3_reg>; | 460 | vin-supply = <&sys_3v3_reg>; |
| 461 | }; | 461 | }; |
| 462 | 462 | ||
| @@ -467,7 +467,7 @@ | |||
| 467 | regulator-min-microvolt = <3300000>; | 467 | regulator-min-microvolt = <3300000>; |
| 468 | regulator-max-microvolt = <3300000>; | 468 | regulator-max-microvolt = <3300000>; |
| 469 | enable-active-high; | 469 | enable-active-high; |
| 470 | gpio = <&gpio 94 0>; /* gpio PL6 */ | 470 | gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; |
| 471 | vin-supply = <&sys_3v3_reg>; | 471 | vin-supply = <&sys_3v3_reg>; |
| 472 | }; | 472 | }; |
| 473 | 473 | ||
| @@ -480,7 +480,7 @@ | |||
| 480 | regulator-always-on; | 480 | regulator-always-on; |
| 481 | regulator-boot-on; | 481 | regulator-boot-on; |
| 482 | enable-active-high; | 482 | enable-active-high; |
| 483 | gpio = <&gpio 92 0>; /* gpio PL4 */ | 483 | gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; |
| 484 | vin-supply = <&sys_3v3_reg>; | 484 | vin-supply = <&sys_3v3_reg>; |
| 485 | }; | 485 | }; |
| 486 | 486 | ||
| @@ -491,7 +491,7 @@ | |||
| 491 | regulator-min-microvolt = <5000000>; | 491 | regulator-min-microvolt = <5000000>; |
| 492 | regulator-max-microvolt = <5000000>; | 492 | regulator-max-microvolt = <5000000>; |
| 493 | enable-active-high; | 493 | enable-active-high; |
| 494 | gpio = <&gpio 152 0>; /* GPIO PT0 */ | 494 | gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; |
| 495 | gpio-open-drain; | 495 | gpio-open-drain; |
| 496 | vin-supply = <&vdd_5v0_reg>; | 496 | vin-supply = <&vdd_5v0_reg>; |
| 497 | }; | 497 | }; |
| @@ -515,10 +515,13 @@ | |||
| 515 | nvidia,i2s-controller = <&tegra_i2s1>; | 515 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 516 | nvidia,audio-codec = <&wm8903>; | 516 | nvidia,audio-codec = <&wm8903>; |
| 517 | 517 | ||
| 518 | nvidia,spkr-en-gpios = <&wm8903 2 0>; | 518 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 519 | nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ | 519 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) |
| 520 | GPIO_ACTIVE_HIGH>; | ||
| 520 | 521 | ||
| 521 | clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>; | 522 | clocks = <&tegra_car TEGRA30_CLK_PLL_A>, |
| 523 | <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, | ||
| 524 | <&tegra_car TEGRA30_CLK_EXTERN1>; | ||
| 522 | clock-names = "pll_a", "pll_a_out0", "mclk"; | 525 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 523 | }; | 526 | }; |
| 524 | }; | 527 | }; |
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 15ded605142a..d8783f0fae63 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
| @@ -1,4 +1,8 @@ | |||
| 1 | /include/ "skeleton.dtsi" | 1 | #include <dt-bindings/clock/tegra30-car.h> |
| 2 | #include <dt-bindings/gpio/tegra-gpio.h> | ||
| 3 | #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| 4 | |||
| 5 | #include "skeleton.dtsi" | ||
| 2 | 6 | ||
| 3 | / { | 7 | / { |
| 4 | compatible = "nvidia,tegra30"; | 8 | compatible = "nvidia,tegra30"; |
| @@ -15,9 +19,9 @@ | |||
| 15 | host1x { | 19 | host1x { |
| 16 | compatible = "nvidia,tegra30-host1x", "simple-bus"; | 20 | compatible = "nvidia,tegra30-host1x", "simple-bus"; |
| 17 | reg = <0x50000000 0x00024000>; | 21 | reg = <0x50000000 0x00024000>; |
| 18 | interrupts = <0 65 0x04 /* mpcore syncpt */ | 22 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 19 | 0 67 0x04>; /* mpcore general */ | 23 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ |
| 20 | clocks = <&tegra_car 28>; | 24 | clocks = <&tegra_car TEGRA30_CLK_HOST1X>; |
| 21 | 25 | ||
| 22 | #address-cells = <1>; | 26 | #address-cells = <1>; |
| 23 | #size-cells = <1>; | 27 | #size-cells = <1>; |
| @@ -27,36 +31,36 @@ | |||
| 27 | mpe { | 31 | mpe { |
| 28 | compatible = "nvidia,tegra30-mpe"; | 32 | compatible = "nvidia,tegra30-mpe"; |
| 29 | reg = <0x54040000 0x00040000>; | 33 | reg = <0x54040000 0x00040000>; |
| 30 | interrupts = <0 68 0x04>; | 34 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
| 31 | clocks = <&tegra_car 60>; | 35 | clocks = <&tegra_car TEGRA30_CLK_MPE>; |
| 32 | }; | 36 | }; |
| 33 | 37 | ||
| 34 | vi { | 38 | vi { |
| 35 | compatible = "nvidia,tegra30-vi"; | 39 | compatible = "nvidia,tegra30-vi"; |
| 36 | reg = <0x54080000 0x00040000>; | 40 | reg = <0x54080000 0x00040000>; |
| 37 | interrupts = <0 69 0x04>; | 41 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 38 | clocks = <&tegra_car 164>; | 42 | clocks = <&tegra_car TEGRA30_CLK_VI>; |
| 39 | }; | 43 | }; |
| 40 | 44 | ||
| 41 | epp { | 45 | epp { |
| 42 | compatible = "nvidia,tegra30-epp"; | 46 | compatible = "nvidia,tegra30-epp"; |
| 43 | reg = <0x540c0000 0x00040000>; | 47 | reg = <0x540c0000 0x00040000>; |
| 44 | interrupts = <0 70 0x04>; | 48 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 45 | clocks = <&tegra_car 19>; | 49 | clocks = <&tegra_car TEGRA30_CLK_EPP>; |
| 46 | }; | 50 | }; |
| 47 | 51 | ||
| 48 | isp { | 52 | isp { |
| 49 | compatible = "nvidia,tegra30-isp"; | 53 | compatible = "nvidia,tegra30-isp"; |
| 50 | reg = <0x54100000 0x00040000>; | 54 | reg = <0x54100000 0x00040000>; |
| 51 | interrupts = <0 71 0x04>; | 55 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 52 | clocks = <&tegra_car 23>; | 56 | clocks = <&tegra_car TEGRA30_CLK_ISP>; |
| 53 | }; | 57 | }; |
| 54 | 58 | ||
| 55 | gr2d { | 59 | gr2d { |
| 56 | compatible = "nvidia,tegra30-gr2d"; | 60 | compatible = "nvidia,tegra30-gr2d"; |
| 57 | reg = <0x54140000 0x00040000>; | 61 | reg = <0x54140000 0x00040000>; |
| 58 | interrupts = <0 72 0x04>; | 62 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| 59 | clocks = <&tegra_car 21>; | 63 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; |
| 60 | }; | 64 | }; |
| 61 | 65 | ||
| 62 | gr3d { | 66 | gr3d { |
| @@ -69,8 +73,9 @@ | |||
| 69 | dc@54200000 { | 73 | dc@54200000 { |
| 70 | compatible = "nvidia,tegra30-dc"; | 74 | compatible = "nvidia,tegra30-dc"; |
| 71 | reg = <0x54200000 0x00040000>; | 75 | reg = <0x54200000 0x00040000>; |
| 72 | interrupts = <0 73 0x04>; | 76 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 73 | clocks = <&tegra_car 27>, <&tegra_car 179>; | 77 | clocks = <&tegra_car TEGRA30_CLK_DISP1>, |
| 78 | <&tegra_car TEGRA30_CLK_PLL_P>; | ||
| 74 | clock-names = "disp1", "parent"; | 79 | clock-names = "disp1", "parent"; |
| 75 | 80 | ||
| 76 | rgb { | 81 | rgb { |
| @@ -81,8 +86,9 @@ | |||
| 81 | dc@54240000 { | 86 | dc@54240000 { |
| 82 | compatible = "nvidia,tegra30-dc"; | 87 | compatible = "nvidia,tegra30-dc"; |
| 83 | reg = <0x54240000 0x00040000>; | 88 | reg = <0x54240000 0x00040000>; |
| 84 | interrupts = <0 74 0x04>; | 89 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 85 | clocks = <&tegra_car 26>, <&tegra_car 179>; | 90 | clocks = <&tegra_car TEGRA30_CLK_DISP2>, |
| 91 | <&tegra_car TEGRA30_CLK_PLL_P>; | ||
| 86 | clock-names = "disp2", "parent"; | 92 | clock-names = "disp2", "parent"; |
| 87 | 93 | ||
| 88 | rgb { | 94 | rgb { |
| @@ -93,8 +99,9 @@ | |||
| 93 | hdmi { | 99 | hdmi { |
| 94 | compatible = "nvidia,tegra30-hdmi"; | 100 | compatible = "nvidia,tegra30-hdmi"; |
| 95 | reg = <0x54280000 0x00040000>; | 101 | reg = <0x54280000 0x00040000>; |
| 96 | interrupts = <0 75 0x04>; | 102 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 97 | clocks = <&tegra_car 51>, <&tegra_car 189>; | 103 | clocks = <&tegra_car TEGRA30_CLK_HDMI>, |
| 104 | <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; | ||
| 98 | clock-names = "hdmi", "parent"; | 105 | clock-names = "hdmi", "parent"; |
| 99 | status = "disabled"; | 106 | status = "disabled"; |
| 100 | }; | 107 | }; |
| @@ -102,15 +109,15 @@ | |||
| 102 | tvo { | 109 | tvo { |
| 103 | compatible = "nvidia,tegra30-tvo"; | 110 | compatible = "nvidia,tegra30-tvo"; |
| 104 | reg = <0x542c0000 0x00040000>; | 111 | reg = <0x542c0000 0x00040000>; |
| 105 | interrupts = <0 76 0x04>; | 112 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 106 | clocks = <&tegra_car 169>; | 113 | clocks = <&tegra_car TEGRA30_CLK_TVO>; |
| 107 | status = "disabled"; | 114 | status = "disabled"; |
| 108 | }; | 115 | }; |
| 109 | 116 | ||
| 110 | dsi { | 117 | dsi { |
| 111 | compatible = "nvidia,tegra30-dsi"; | 118 | compatible = "nvidia,tegra30-dsi"; |
| 112 | reg = <0x54300000 0x00040000>; | 119 | reg = <0x54300000 0x00040000>; |
| 113 | clocks = <&tegra_car 48>; | 120 | clocks = <&tegra_car TEGRA30_CLK_DSIA>; |
| 114 | status = "disabled"; | 121 | status = "disabled"; |
| 115 | }; | 122 | }; |
| 116 | }; | 123 | }; |
| @@ -118,8 +125,9 @@ | |||
| 118 | timer@50004600 { | 125 | timer@50004600 { |
| 119 | compatible = "arm,cortex-a9-twd-timer"; | 126 | compatible = "arm,cortex-a9-twd-timer"; |
| 120 | reg = <0x50040600 0x20>; | 127 | reg = <0x50040600 0x20>; |
| 121 | interrupts = <1 13 0xf04>; | 128 | interrupts = <GIC_PPI 13 |
| 122 | clocks = <&tegra_car 214>; | 129 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 130 | clocks = <&tegra_car TEGRA30_CLK_TWD>; | ||
| 123 | }; | 131 | }; |
| 124 | 132 | ||
| 125 | intc: interrupt-controller { | 133 | intc: interrupt-controller { |
| @@ -142,13 +150,13 @@ | |||
| 142 | timer@60005000 { | 150 | timer@60005000 { |
| 143 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; | 151 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; |
| 144 | reg = <0x60005000 0x400>; | 152 | reg = <0x60005000 0x400>; |
| 145 | interrupts = <0 0 0x04 | 153 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 146 | 0 1 0x04 | 154 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 147 | 0 41 0x04 | 155 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 148 | 0 42 0x04 | 156 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 149 | 0 121 0x04 | 157 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 150 | 0 122 0x04>; | 158 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
| 151 | clocks = <&tegra_car 5>; | 159 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; |
| 152 | }; | 160 | }; |
| 153 | 161 | ||
| 154 | tegra_car: clock { | 162 | tegra_car: clock { |
| @@ -160,39 +168,39 @@ | |||
| 160 | apbdma: dma { | 168 | apbdma: dma { |
| 161 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; | 169 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
| 162 | reg = <0x6000a000 0x1400>; | 170 | reg = <0x6000a000 0x1400>; |
| 163 | interrupts = <0 104 0x04 | 171 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 164 | 0 105 0x04 | 172 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 165 | 0 106 0x04 | 173 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 166 | 0 107 0x04 | 174 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 167 | 0 108 0x04 | 175 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 168 | 0 109 0x04 | 176 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 169 | 0 110 0x04 | 177 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 170 | 0 111 0x04 | 178 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 171 | 0 112 0x04 | 179 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 172 | 0 113 0x04 | 180 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 173 | 0 114 0x04 | 181 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 174 | 0 115 0x04 | 182 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 175 | 0 116 0x04 | 183 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 176 | 0 117 0x04 | 184 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 177 | 0 118 0x04 | 185 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 178 | 0 119 0x04 | 186 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 179 | 0 128 0x04 | 187 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 180 | 0 129 0x04 | 188 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 181 | 0 130 0x04 | 189 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 182 | 0 131 0x04 | 190 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 183 | 0 132 0x04 | 191 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 184 | 0 133 0x04 | 192 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 185 | 0 134 0x04 | 193 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 186 | 0 135 0x04 | 194 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 187 | 0 136 0x04 | 195 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 188 | 0 137 0x04 | 196 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 189 | 0 138 0x04 | 197 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 190 | 0 139 0x04 | 198 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 191 | 0 140 0x04 | 199 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 192 | 0 141 0x04 | 200 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 193 | 0 142 0x04 | 201 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 194 | 0 143 0x04>; | 202 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| 195 | clocks = <&tegra_car 34>; | 203 | clocks = <&tegra_car TEGRA30_CLK_APBDMA>; |
| 196 | }; | 204 | }; |
| 197 | 205 | ||
| 198 | ahb: ahb { | 206 | ahb: ahb { |
| @@ -203,14 +211,14 @@ | |||
| 203 | gpio: gpio { | 211 | gpio: gpio { |
| 204 | compatible = "nvidia,tegra30-gpio"; | 212 | compatible = "nvidia,tegra30-gpio"; |
| 205 | reg = <0x6000d000 0x1000>; | 213 | reg = <0x6000d000 0x1000>; |
| 206 | interrupts = <0 32 0x04 | 214 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 207 | 0 33 0x04 | 215 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 208 | 0 34 0x04 | 216 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 209 | 0 35 0x04 | 217 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 210 | 0 55 0x04 | 218 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 211 | 0 87 0x04 | 219 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 212 | 0 89 0x04 | 220 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 213 | 0 125 0x04>; | 221 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| 214 | #gpio-cells = <2>; | 222 | #gpio-cells = <2>; |
| 215 | gpio-controller; | 223 | gpio-controller; |
| 216 | #interrupt-cells = <2>; | 224 | #interrupt-cells = <2>; |
| @@ -235,9 +243,9 @@ | |||
| 235 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | 243 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 236 | reg = <0x70006000 0x40>; | 244 | reg = <0x70006000 0x40>; |
| 237 | reg-shift = <2>; | 245 | reg-shift = <2>; |
| 238 | interrupts = <0 36 0x04>; | 246 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 239 | nvidia,dma-request-selector = <&apbdma 8>; | 247 | nvidia,dma-request-selector = <&apbdma 8>; |
| 240 | clocks = <&tegra_car 6>; | 248 | clocks = <&tegra_car TEGRA30_CLK_UARTA>; |
| 241 | status = "disabled"; | 249 | status = "disabled"; |
| 242 | }; | 250 | }; |
| 243 | 251 | ||
| @@ -245,9 +253,9 @@ | |||
| 245 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | 253 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 246 | reg = <0x70006040 0x40>; | 254 | reg = <0x70006040 0x40>; |
| 247 | reg-shift = <2>; | 255 | reg-shift = <2>; |
| 248 | interrupts = <0 37 0x04>; | 256 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 249 | nvidia,dma-request-selector = <&apbdma 9>; | 257 | nvidia,dma-request-selector = <&apbdma 9>; |
| 250 | clocks = <&tegra_car 160>; | 258 | clocks = <&tegra_car TEGRA30_CLK_UARTB>; |
| 251 | status = "disabled"; | 259 | status = "disabled"; |
| 252 | }; | 260 | }; |
| 253 | 261 | ||
| @@ -255,9 +263,9 @@ | |||
| 255 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | 263 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 256 | reg = <0x70006200 0x100>; | 264 | reg = <0x70006200 0x100>; |
| 257 | reg-shift = <2>; | 265 | reg-shift = <2>; |
| 258 | interrupts = <0 46 0x04>; | 266 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 259 | nvidia,dma-request-selector = <&apbdma 10>; | 267 | nvidia,dma-request-selector = <&apbdma 10>; |
| 260 | clocks = <&tegra_car 55>; | 268 | clocks = <&tegra_car TEGRA30_CLK_UARTC>; |
| 261 | status = "disabled"; | 269 | status = "disabled"; |
| 262 | }; | 270 | }; |
| 263 | 271 | ||
| @@ -265,9 +273,9 @@ | |||
| 265 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | 273 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 266 | reg = <0x70006300 0x100>; | 274 | reg = <0x70006300 0x100>; |
| 267 | reg-shift = <2>; | 275 | reg-shift = <2>; |
| 268 | interrupts = <0 90 0x04>; | 276 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| 269 | nvidia,dma-request-selector = <&apbdma 19>; | 277 | nvidia,dma-request-selector = <&apbdma 19>; |
| 270 | clocks = <&tegra_car 65>; | 278 | clocks = <&tegra_car TEGRA30_CLK_UARTD>; |
| 271 | status = "disabled"; | 279 | status = "disabled"; |
| 272 | }; | 280 | }; |
| 273 | 281 | ||
| @@ -275,9 +283,9 @@ | |||
| 275 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | 283 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 276 | reg = <0x70006400 0x100>; | 284 | reg = <0x70006400 0x100>; |
| 277 | reg-shift = <2>; | 285 | reg-shift = <2>; |
| 278 | interrupts = <0 91 0x04>; | 286 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| 279 | nvidia,dma-request-selector = <&apbdma 20>; | 287 | nvidia,dma-request-selector = <&apbdma 20>; |
| 280 | clocks = <&tegra_car 66>; | 288 | clocks = <&tegra_car TEGRA30_CLK_UARTE>; |
| 281 | status = "disabled"; | 289 | status = "disabled"; |
| 282 | }; | 290 | }; |
| 283 | 291 | ||
| @@ -285,24 +293,25 @@ | |||
| 285 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; | 293 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
| 286 | reg = <0x7000a000 0x100>; | 294 | reg = <0x7000a000 0x100>; |
| 287 | #pwm-cells = <2>; | 295 | #pwm-cells = <2>; |
| 288 | clocks = <&tegra_car 17>; | 296 | clocks = <&tegra_car TEGRA30_CLK_PWM>; |
| 289 | status = "disabled"; | 297 | status = "disabled"; |
| 290 | }; | 298 | }; |
| 291 | 299 | ||
| 292 | rtc { | 300 | rtc { |
| 293 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; | 301 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
| 294 | reg = <0x7000e000 0x100>; | 302 | reg = <0x7000e000 0x100>; |
| 295 | interrupts = <0 2 0x04>; | 303 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 296 | clocks = <&tegra_car 4>; | 304 | clocks = <&tegra_car TEGRA30_CLK_RTC>; |
| 297 | }; | 305 | }; |
| 298 | 306 | ||
| 299 | i2c@7000c000 { | 307 | i2c@7000c000 { |
| 300 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; | 308 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 301 | reg = <0x7000c000 0x100>; | 309 | reg = <0x7000c000 0x100>; |
| 302 | interrupts = <0 38 0x04>; | 310 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 303 | #address-cells = <1>; | 311 | #address-cells = <1>; |
| 304 | #size-cells = <0>; | 312 | #size-cells = <0>; |
| 305 | clocks = <&tegra_car 12>, <&tegra_car 182>; | 313 | clocks = <&tegra_car TEGRA30_CLK_I2C1>, |
| 314 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | ||
| 306 | clock-names = "div-clk", "fast-clk"; | 315 | clock-names = "div-clk", "fast-clk"; |
| 307 | status = "disabled"; | 316 | status = "disabled"; |
| 308 | }; | 317 | }; |
| @@ -310,10 +319,11 @@ | |||
| 310 | i2c@7000c400 { | 319 | i2c@7000c400 { |
| 311 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; | 320 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 312 | reg = <0x7000c400 0x100>; | 321 | reg = <0x7000c400 0x100>; |
| 313 | interrupts = <0 84 0x04>; | 322 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 314 | #address-cells = <1>; | 323 | #address-cells = <1>; |
| 315 | #size-cells = <0>; | 324 | #size-cells = <0>; |
| 316 | clocks = <&tegra_car 54>, <&tegra_car 182>; | 325 | clocks = <&tegra_car TEGRA30_CLK_I2C2>, |
| 326 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | ||
| 317 | clock-names = "div-clk", "fast-clk"; | 327 | clock-names = "div-clk", "fast-clk"; |
| 318 | status = "disabled"; | 328 | status = "disabled"; |
| 319 | }; | 329 | }; |
| @@ -321,10 +331,11 @@ | |||
| 321 | i2c@7000c500 { | 331 | i2c@7000c500 { |
| 322 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; | 332 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 323 | reg = <0x7000c500 0x100>; | 333 | reg = <0x7000c500 0x100>; |
| 324 | interrupts = <0 92 0x04>; | 334 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 325 | #address-cells = <1>; | 335 | #address-cells = <1>; |
| 326 | #size-cells = <0>; | 336 | #size-cells = <0>; |
| 327 | clocks = <&tegra_car 67>, <&tegra_car 182>; | 337 | clocks = <&tegra_car TEGRA30_CLK_I2C3>, |
| 338 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | ||
| 328 | clock-names = "div-clk", "fast-clk"; | 339 | clock-names = "div-clk", "fast-clk"; |
| 329 | status = "disabled"; | 340 | status = "disabled"; |
| 330 | }; | 341 | }; |
| @@ -332,10 +343,11 @@ | |||
| 332 | i2c@7000c700 { | 343 | i2c@7000c700 { |
| 333 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; | 344 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 334 | reg = <0x7000c700 0x100>; | 345 | reg = <0x7000c700 0x100>; |
| 335 | interrupts = <0 120 0x04>; | 346 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 336 | #address-cells = <1>; | 347 | #address-cells = <1>; |
| 337 | #size-cells = <0>; | 348 | #size-cells = <0>; |
| 338 | clocks = <&tegra_car 103>, <&tegra_car 182>; | 349 | clocks = <&tegra_car TEGRA30_CLK_I2C4>, |
| 350 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | ||
| 339 | clock-names = "div-clk", "fast-clk"; | 351 | clock-names = "div-clk", "fast-clk"; |
| 340 | status = "disabled"; | 352 | status = "disabled"; |
| 341 | }; | 353 | }; |
| @@ -343,10 +355,11 @@ | |||
| 343 | i2c@7000d000 { | 355 | i2c@7000d000 { |
| 344 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; | 356 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 345 | reg = <0x7000d000 0x100>; | 357 | reg = <0x7000d000 0x100>; |
| 346 | interrupts = <0 53 0x04>; | 358 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 347 | #address-cells = <1>; | 359 | #address-cells = <1>; |
| 348 | #size-cells = <0>; | 360 | #size-cells = <0>; |
| 349 | clocks = <&tegra_car 47>, <&tegra_car 182>; | 361 | clocks = <&tegra_car TEGRA30_CLK_I2C5>, |
| 362 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | ||
| 350 | clock-names = "div-clk", "fast-clk"; | 363 | clock-names = "div-clk", "fast-clk"; |
| 351 | status = "disabled"; | 364 | status = "disabled"; |
| 352 | }; | 365 | }; |
| @@ -354,81 +367,81 @@ | |||
| 354 | spi@7000d400 { | 367 | spi@7000d400 { |
| 355 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | 368 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 356 | reg = <0x7000d400 0x200>; | 369 | reg = <0x7000d400 0x200>; |
| 357 | interrupts = <0 59 0x04>; | 370 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 358 | nvidia,dma-request-selector = <&apbdma 15>; | 371 | nvidia,dma-request-selector = <&apbdma 15>; |
| 359 | #address-cells = <1>; | 372 | #address-cells = <1>; |
| 360 | #size-cells = <0>; | 373 | #size-cells = <0>; |
| 361 | clocks = <&tegra_car 41>; | 374 | clocks = <&tegra_car TEGRA30_CLK_SBC1>; |
| 362 | status = "disabled"; | 375 | status = "disabled"; |
| 363 | }; | 376 | }; |
| 364 | 377 | ||
| 365 | spi@7000d600 { | 378 | spi@7000d600 { |
| 366 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | 379 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 367 | reg = <0x7000d600 0x200>; | 380 | reg = <0x7000d600 0x200>; |
| 368 | interrupts = <0 82 0x04>; | 381 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 369 | nvidia,dma-request-selector = <&apbdma 16>; | 382 | nvidia,dma-request-selector = <&apbdma 16>; |
| 370 | #address-cells = <1>; | 383 | #address-cells = <1>; |
| 371 | #size-cells = <0>; | 384 | #size-cells = <0>; |
| 372 | clocks = <&tegra_car 44>; | 385 | clocks = <&tegra_car TEGRA30_CLK_SBC2>; |
| 373 | status = "disabled"; | 386 | status = "disabled"; |
| 374 | }; | 387 | }; |
| 375 | 388 | ||
| 376 | spi@7000d800 { | 389 | spi@7000d800 { |
| 377 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | 390 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 378 | reg = <0x7000d800 0x200>; | 391 | reg = <0x7000d800 0x200>; |
| 379 | interrupts = <0 83 0x04>; | 392 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 380 | nvidia,dma-request-selector = <&apbdma 17>; | 393 | nvidia,dma-request-selector = <&apbdma 17>; |
| 381 | #address-cells = <1>; | 394 | #address-cells = <1>; |
| 382 | #size-cells = <0>; | 395 | #size-cells = <0>; |
| 383 | clocks = <&tegra_car 46>; | 396 | clocks = <&tegra_car TEGRA30_CLK_SBC3>; |
| 384 | status = "disabled"; | 397 | status = "disabled"; |
| 385 | }; | 398 | }; |
| 386 | 399 | ||
| 387 | spi@7000da00 { | 400 | spi@7000da00 { |
| 388 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | 401 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 389 | reg = <0x7000da00 0x200>; | 402 | reg = <0x7000da00 0x200>; |
| 390 | interrupts = <0 93 0x04>; | 403 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 391 | nvidia,dma-request-selector = <&apbdma 18>; | 404 | nvidia,dma-request-selector = <&apbdma 18>; |
| 392 | #address-cells = <1>; | 405 | #address-cells = <1>; |
| 393 | #size-cells = <0>; | 406 | #size-cells = <0>; |
| 394 | clocks = <&tegra_car 68>; | 407 | clocks = <&tegra_car TEGRA30_CLK_SBC4>; |
| 395 | status = "disabled"; | 408 | status = "disabled"; |
| 396 | }; | 409 | }; |
| 397 | 410 | ||
| 398 | spi@7000dc00 { | 411 | spi@7000dc00 { |
| 399 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | 412 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 400 | reg = <0x7000dc00 0x200>; | 413 | reg = <0x7000dc00 0x200>; |
| 401 | interrupts = <0 94 0x04>; | 414 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 402 | nvidia,dma-request-selector = <&apbdma 27>; | 415 | nvidia,dma-request-selector = <&apbdma 27>; |
| 403 | #address-cells = <1>; | 416 | #address-cells = <1>; |
| 404 | #size-cells = <0>; | 417 | #size-cells = <0>; |
| 405 | clocks = <&tegra_car 104>; | 418 | clocks = <&tegra_car TEGRA30_CLK_SBC5>; |
| 406 | status = "disabled"; | 419 | status = "disabled"; |
| 407 | }; | 420 | }; |
| 408 | 421 | ||
| 409 | spi@7000de00 { | 422 | spi@7000de00 { |
| 410 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | 423 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
| 411 | reg = <0x7000de00 0x200>; | 424 | reg = <0x7000de00 0x200>; |
| 412 | interrupts = <0 79 0x04>; | 425 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 413 | nvidia,dma-request-selector = <&apbdma 28>; | 426 | nvidia,dma-request-selector = <&apbdma 28>; |
| 414 | #address-cells = <1>; | 427 | #address-cells = <1>; |
| 415 | #size-cells = <0>; | 428 | #size-cells = <0>; |
| 416 | clocks = <&tegra_car 105>; | 429 | clocks = <&tegra_car TEGRA30_CLK_SBC6>; |
| 417 | status = "disabled"; | 430 | status = "disabled"; |
| 418 | }; | 431 | }; |
| 419 | 432 | ||
| 420 | kbc { | 433 | kbc { |
| 421 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; | 434 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; |
| 422 | reg = <0x7000e200 0x100>; | 435 | reg = <0x7000e200 0x100>; |
| 423 | interrupts = <0 85 0x04>; | 436 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 424 | clocks = <&tegra_car 36>; | 437 | clocks = <&tegra_car TEGRA30_CLK_KBC>; |
| 425 | status = "disabled"; | 438 | status = "disabled"; |
| 426 | }; | 439 | }; |
| 427 | 440 | ||
| 428 | pmc { | 441 | pmc { |
| 429 | compatible = "nvidia,tegra30-pmc"; | 442 | compatible = "nvidia,tegra30-pmc"; |
| 430 | reg = <0x7000e400 0x400>; | 443 | reg = <0x7000e400 0x400>; |
| 431 | clocks = <&tegra_car 218>, <&clk32k_in>; | 444 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; |
| 432 | clock-names = "pclk", "clk32k_in"; | 445 | clock-names = "pclk", "clk32k_in"; |
| 433 | }; | 446 | }; |
| 434 | 447 | ||
| @@ -438,7 +451,7 @@ | |||
| 438 | 0x7000f03c 0x1b4 | 451 | 0x7000f03c 0x1b4 |
| 439 | 0x7000f200 0x028 | 452 | 0x7000f200 0x028 |
| 440 | 0x7000f284 0x17c>; | 453 | 0x7000f284 0x17c>; |
| 441 | interrupts = <0 77 0x04>; | 454 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 442 | }; | 455 | }; |
| 443 | 456 | ||
| 444 | iommu { | 457 | iommu { |
| @@ -455,12 +468,19 @@ | |||
| 455 | compatible = "nvidia,tegra30-ahub"; | 468 | compatible = "nvidia,tegra30-ahub"; |
| 456 | reg = <0x70080000 0x200 | 469 | reg = <0x70080000 0x200 |
| 457 | 0x70080200 0x100>; | 470 | 0x70080200 0x100>; |
| 458 | interrupts = <0 103 0x04>; | 471 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 459 | nvidia,dma-request-selector = <&apbdma 1>; | 472 | nvidia,dma-request-selector = <&apbdma 1>; |
| 460 | clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, | 473 | clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, |
| 461 | <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, | 474 | <&tegra_car TEGRA30_CLK_APBIF>, |
| 462 | <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, | 475 | <&tegra_car TEGRA30_CLK_I2S0>, |
| 463 | <&tegra_car 110>, <&tegra_car 162>; | 476 | <&tegra_car TEGRA30_CLK_I2S1>, |
| 477 | <&tegra_car TEGRA30_CLK_I2S2>, | ||
| 478 | <&tegra_car TEGRA30_CLK_I2S3>, | ||
| 479 | <&tegra_car TEGRA30_CLK_I2S4>, | ||
| 480 | <&tegra_car TEGRA30_CLK_DAM0>, | ||
| 481 | <&tegra_car TEGRA30_CLK_DAM1>, | ||
| 482 | <&tegra_car TEGRA30_CLK_DAM2>, | ||
| 483 | <&tegra_car TEGRA30_CLK_SPDIF_IN>; | ||
| 464 | clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | 484 | clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 465 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | 485 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 466 | "spdif_in"; | 486 | "spdif_in"; |
| @@ -472,7 +492,7 @@ | |||
| 472 | compatible = "nvidia,tegra30-i2s"; | 492 | compatible = "nvidia,tegra30-i2s"; |
| 473 | reg = <0x70080300 0x100>; | 493 | reg = <0x70080300 0x100>; |
| 474 | nvidia,ahub-cif-ids = <4 4>; | 494 | nvidia,ahub-cif-ids = <4 4>; |
| 475 | clocks = <&tegra_car 30>; | 495 | clocks = <&tegra_car TEGRA30_CLK_I2S0>; |
| 476 | status = "disabled"; | 496 | status = "disabled"; |
| 477 | }; | 497 | }; |
| 478 | 498 | ||
| @@ -480,7 +500,7 @@ | |||
| 480 | compatible = "nvidia,tegra30-i2s"; | 500 | compatible = "nvidia,tegra30-i2s"; |
| 481 | reg = <0x70080400 0x100>; | 501 | reg = <0x70080400 0x100>; |
| 482 | nvidia,ahub-cif-ids = <5 5>; | 502 | nvidia,ahub-cif-ids = <5 5>; |
| 483 | clocks = <&tegra_car 11>; | 503 | clocks = <&tegra_car TEGRA30_CLK_I2S1>; |
| 484 | status = "disabled"; | 504 | status = "disabled"; |
| 485 | }; | 505 | }; |
| 486 | 506 | ||
| @@ -488,7 +508,7 @@ | |||
| 488 | compatible = "nvidia,tegra30-i2s"; | 508 | compatible = "nvidia,tegra30-i2s"; |
| 489 | reg = <0x70080500 0x100>; | 509 | reg = <0x70080500 0x100>; |
| 490 | nvidia,ahub-cif-ids = <6 6>; | 510 | nvidia,ahub-cif-ids = <6 6>; |
| 491 | clocks = <&tegra_car 18>; | 511 | clocks = <&tegra_car TEGRA30_CLK_I2S2>; |
| 492 | status = "disabled"; | 512 | status = "disabled"; |
| 493 | }; | 513 | }; |
| 494 | 514 | ||
| @@ -496,7 +516,7 @@ | |||
| 496 | compatible = "nvidia,tegra30-i2s"; | 516 | compatible = "nvidia,tegra30-i2s"; |
| 497 | reg = <0x70080600 0x100>; | 517 | reg = <0x70080600 0x100>; |
| 498 | nvidia,ahub-cif-ids = <7 7>; | 518 | nvidia,ahub-cif-ids = <7 7>; |
| 499 | clocks = <&tegra_car 101>; | 519 | clocks = <&tegra_car TEGRA30_CLK_I2S3>; |
| 500 | status = "disabled"; | 520 | status = "disabled"; |
| 501 | }; | 521 | }; |
| 502 | 522 | ||
| @@ -504,7 +524,7 @@ | |||
| 504 | compatible = "nvidia,tegra30-i2s"; | 524 | compatible = "nvidia,tegra30-i2s"; |
| 505 | reg = <0x70080700 0x100>; | 525 | reg = <0x70080700 0x100>; |
| 506 | nvidia,ahub-cif-ids = <8 8>; | 526 | nvidia,ahub-cif-ids = <8 8>; |
| 507 | clocks = <&tegra_car 102>; | 527 | clocks = <&tegra_car TEGRA30_CLK_I2S4>; |
| 508 | status = "disabled"; | 528 | status = "disabled"; |
| 509 | }; | 529 | }; |
| 510 | }; | 530 | }; |
| @@ -512,32 +532,32 @@ | |||
| 512 | sdhci@78000000 { | 532 | sdhci@78000000 { |
| 513 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 533 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 514 | reg = <0x78000000 0x200>; | 534 | reg = <0x78000000 0x200>; |
| 515 | interrupts = <0 14 0x04>; | 535 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 516 | clocks = <&tegra_car 14>; | 536 | clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; |
| 517 | status = "disabled"; | 537 | status = "disabled"; |
| 518 | }; | 538 | }; |
| 519 | 539 | ||
| 520 | sdhci@78000200 { | 540 | sdhci@78000200 { |
| 521 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 541 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 522 | reg = <0x78000200 0x200>; | 542 | reg = <0x78000200 0x200>; |
| 523 | interrupts = <0 15 0x04>; | 543 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 524 | clocks = <&tegra_car 9>; | 544 | clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; |
| 525 | status = "disabled"; | 545 | status = "disabled"; |
| 526 | }; | 546 | }; |
| 527 | 547 | ||
| 528 | sdhci@78000400 { | 548 | sdhci@78000400 { |
| 529 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 549 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 530 | reg = <0x78000400 0x200>; | 550 | reg = <0x78000400 0x200>; |
| 531 | interrupts = <0 19 0x04>; | 551 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 532 | clocks = <&tegra_car 69>; | 552 | clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; |
| 533 | status = "disabled"; | 553 | status = "disabled"; |
| 534 | }; | 554 | }; |
| 535 | 555 | ||
| 536 | sdhci@78000600 { | 556 | sdhci@78000600 { |
| 537 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 557 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 538 | reg = <0x78000600 0x200>; | 558 | reg = <0x78000600 0x200>; |
| 539 | interrupts = <0 31 0x04>; | 559 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 540 | clocks = <&tegra_car 15>; | 560 | clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; |
| 541 | status = "disabled"; | 561 | status = "disabled"; |
| 542 | }; | 562 | }; |
| 543 | 563 | ||
| @@ -572,9 +592,9 @@ | |||
| 572 | 592 | ||
| 573 | pmu { | 593 | pmu { |
| 574 | compatible = "arm,cortex-a9-pmu"; | 594 | compatible = "arm,cortex-a9-pmu"; |
| 575 | interrupts = <0 144 0x04 | 595 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| 576 | 0 145 0x04 | 596 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| 577 | 0 146 0x04 | 597 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| 578 | 0 147 0x04>; | 598 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
| 579 | }; | 599 | }; |
| 580 | }; | 600 | }; |
diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi new file mode 100644 index 000000000000..c353ef0a6ac7 --- /dev/null +++ b/arch/arm/boot/dts/twl4030_omap3.dtsi | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Linaro, Ltd. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | &twl { | ||
| 10 | pinctrl-names = "default"; | ||
| 11 | pinctrl-0 = <&twl4030_pins>; | ||
| 12 | }; | ||
| 13 | |||
| 14 | &omap3_pmx_core { | ||
| 15 | /* | ||
| 16 | * On most OMAP3 platforms, the twl4030 IRQ line is connected | ||
| 17 | * to the SYS_NIRQ line on OMAP. Therefore, configure the | ||
| 18 | * defaults for the SYS_NIRQ pin here. | ||
| 19 | */ | ||
| 20 | twl4030_pins: pinmux_twl4030_pins { | ||
| 21 | pinctrl-single,pins = < | ||
| 22 | 0x1b0 (PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */ | ||
| 23 | >; | ||
| 24 | }; | ||
| 25 | }; | ||
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts index a604107eb474..de0c24f5210a 100644 --- a/arch/arm/boot/dts/usb_a9260.dts +++ b/arch/arm/boot/dts/usb_a9260.dts | |||
| @@ -20,4 +20,13 @@ | |||
| 20 | memory { | 20 | memory { |
| 21 | reg = <0x20000000 0x4000000>; | 21 | reg = <0x20000000 0x4000000>; |
| 22 | }; | 22 | }; |
| 23 | |||
| 24 | ahb { | ||
| 25 | apb { | ||
| 26 | shdwc@fffffd10 { | ||
| 27 | atmel,wakeup-counter = <10>; | ||
| 28 | atmel,wakeup-rtt-timer; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | }; | ||
| 23 | }; | 32 | }; |
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index f8ec36cb036b..290e60383baf 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts | |||
| @@ -47,6 +47,20 @@ | |||
| 47 | status = "okay"; | 47 | status = "okay"; |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | spi0: spi@fffa4000 { | ||
| 51 | cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; | ||
| 52 | status = "okay"; | ||
| 53 | mtd_dataflash@0 { | ||
| 54 | compatible = "atmel,at45", "atmel,dataflash"; | ||
| 55 | reg = <0>; | ||
| 56 | spi-max-frequency = <15000000>; | ||
| 57 | }; | ||
| 58 | }; | ||
| 59 | |||
| 60 | shdwc@fffffd10 { | ||
| 61 | atmel,wakeup-counter = <10>; | ||
| 62 | atmel,wakeup-rtt-timer; | ||
| 63 | }; | ||
| 50 | }; | 64 | }; |
| 51 | 65 | ||
| 52 | nand0: nand@40000000 { | 66 | nand0: nand@40000000 { |
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts index c979c06cf697..ec77cf8f9695 100644 --- a/arch/arm/boot/dts/usb_a9g20.dts +++ b/arch/arm/boot/dts/usb_a9g20.dts | |||
| @@ -6,25 +6,9 @@ | |||
| 6 | * Licensed under GPLv2 or later. | 6 | * Licensed under GPLv2 or later. |
| 7 | */ | 7 | */ |
| 8 | /dts-v1/; | 8 | /dts-v1/; |
| 9 | #include "at91sam9g20.dtsi" | 9 | #include "usb_a9g20_common.dtsi" |
| 10 | #include "usb_a9260_common.dtsi" | ||
| 11 | 10 | ||
| 12 | / { | 11 | / { |
| 13 | model = "Calao USB A9G20"; | 12 | model = "Calao USB A9G20"; |
| 14 | compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; | 13 | compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; |
| 15 | |||
| 16 | chosen { | ||
| 17 | bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; | ||
| 18 | }; | ||
| 19 | |||
| 20 | memory { | ||
| 21 | reg = <0x20000000 0x4000000>; | ||
| 22 | }; | ||
| 23 | |||
| 24 | i2c@0 { | ||
| 25 | rv3029c2@56 { | ||
| 26 | compatible = "rv3029c2"; | ||
| 27 | reg = <0x56>; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | }; | 14 | }; |
diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi new file mode 100644 index 000000000000..0b3b36182fe5 --- /dev/null +++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | /* | ||
| 2 | * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include "at91sam9g20.dtsi" | ||
| 10 | #include "usb_a9260_common.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | chosen { | ||
| 14 | bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; | ||
| 15 | }; | ||
| 16 | |||
| 17 | memory { | ||
| 18 | reg = <0x20000000 0x4000000>; | ||
| 19 | }; | ||
| 20 | |||
| 21 | i2c@0 { | ||
| 22 | rv3029c2@56 { | ||
| 23 | compatible = "rv3029c2"; | ||
| 24 | reg = <0x56>; | ||
| 25 | }; | ||
| 26 | }; | ||
| 27 | }; | ||
diff --git a/arch/arm/boot/dts/usb_a9g20_lpw.dts b/arch/arm/boot/dts/usb_a9g20_lpw.dts new file mode 100644 index 000000000000..f8cb1b9a01c5 --- /dev/null +++ b/arch/arm/boot/dts/usb_a9g20_lpw.dts | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | /dts-v1/; | ||
| 9 | #include "usb_a9g20_common.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | model = "Calao USB A9G20 Low Power"; | ||
| 13 | compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; | ||
| 14 | |||
| 15 | ahb { | ||
| 16 | apb { | ||
| 17 | spi1: spi@fffcc000 { | ||
| 18 | cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; | ||
| 19 | status = "okay"; | ||
| 20 | mmc-slot@0 { | ||
| 21 | compatible = "mmc-spi-slot"; | ||
| 22 | reg = <0>; | ||
| 23 | voltage-ranges = <3200 3400>; | ||
| 24 | spi-max-frequency = <25000000>; | ||
| 25 | interrupt-parent = <&pioC>; | ||
| 26 | interrupts = <4 IRQ_TYPE_EDGE_BOTH>; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | }; | ||
diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/vf610-pinfunc.h new file mode 100644 index 000000000000..1ee681f7ce2f --- /dev/null +++ b/arch/arm/boot/dts/vf610-pinfunc.h | |||
| @@ -0,0 +1,810 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DTS_VF610_PINFUNC_H | ||
| 11 | #define __DTS_VF610_PINFUNC_H | ||
| 12 | |||
| 13 | /* | ||
| 14 | * The pin function ID for VF610 is a tuple of: | ||
| 15 | * <mux_reg input_reg mux_mode input_val> | ||
| 16 | */ | ||
| 17 | |||
| 18 | #define ALT0 0x0 | ||
| 19 | #define ALT1 0x1 | ||
| 20 | #define ALT2 0x2 | ||
| 21 | #define ALT3 0x3 | ||
| 22 | #define ALT4 0x4 | ||
| 23 | #define ALT5 0x5 | ||
| 24 | #define ALT6 0x6 | ||
| 25 | #define ALT7 0x7 | ||
| 26 | |||
| 27 | |||
| 28 | #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 | ||
| 29 | #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 | ||
| 30 | #define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 | ||
| 31 | #define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0 | ||
| 32 | #define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0 | ||
| 33 | #define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0 | ||
| 34 | #define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0 | ||
| 35 | #define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0 | ||
| 36 | #define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0 | ||
| 37 | #define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0 | ||
| 38 | #define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0 | ||
| 39 | #define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0 | ||
| 40 | #define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1 | ||
| 41 | #define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0 | ||
| 42 | #define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0 | ||
| 43 | #define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0 | ||
| 44 | #define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0 | ||
| 45 | #define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0 | ||
| 46 | #define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0 | ||
| 47 | #define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0 | ||
| 48 | #define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0 | ||
| 49 | #define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0 | ||
| 50 | #define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0 | ||
| 51 | #define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0 | ||
| 52 | #define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0 | ||
| 53 | #define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0 | ||
| 54 | #define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0 | ||
| 55 | #define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1 | ||
| 56 | #define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0 | ||
| 57 | #define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0 | ||
| 58 | #define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0 | ||
| 59 | #define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0 | ||
| 60 | #define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0 | ||
| 61 | #define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0 | ||
| 62 | #define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0 | ||
| 63 | #define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0 | ||
| 64 | #define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0 | ||
| 65 | #define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0 | ||
| 66 | #define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0 | ||
| 67 | #define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0 | ||
| 68 | #define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0 | ||
| 69 | #define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0 | ||
| 70 | #define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0 | ||
| 71 | #define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0 | ||
| 72 | #define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0 | ||
| 73 | #define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0 | ||
| 74 | #define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0 | ||
| 75 | #define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0 | ||
| 76 | #define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0 | ||
| 77 | #define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0 | ||
| 78 | #define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0 | ||
| 79 | #define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0 | ||
| 80 | #define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0 | ||
| 81 | #define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0 | ||
| 82 | #define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0 | ||
| 83 | #define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0 | ||
| 84 | #define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0 | ||
| 85 | #define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0 | ||
| 86 | #define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0 | ||
| 87 | #define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0 | ||
| 88 | #define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0 | ||
| 89 | #define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0 | ||
| 90 | #define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0 | ||
| 91 | #define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0 | ||
| 92 | #define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0 | ||
| 93 | #define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0 | ||
| 94 | #define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0 | ||
| 95 | #define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0 | ||
| 96 | #define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0 | ||
| 97 | #define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0 | ||
| 98 | #define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0 | ||
| 99 | #define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0 | ||
| 100 | #define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0 | ||
| 101 | #define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0 | ||
| 102 | #define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0 | ||
| 103 | #define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0 | ||
| 104 | #define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0 | ||
| 105 | #define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0 | ||
| 106 | #define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0 | ||
| 107 | #define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0 | ||
| 108 | #define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0 | ||
| 109 | #define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0 | ||
| 110 | #define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0 | ||
| 111 | #define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0 | ||
| 112 | #define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0 | ||
| 113 | #define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0 | ||
| 114 | #define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0 | ||
| 115 | #define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0 | ||
| 116 | #define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0 | ||
| 117 | #define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0 | ||
| 118 | #define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0 | ||
| 119 | #define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0 | ||
| 120 | #define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0 | ||
| 121 | #define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0 | ||
| 122 | #define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0 | ||
| 123 | #define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0 | ||
| 124 | #define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0 | ||
| 125 | #define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0 | ||
| 126 | #define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0 | ||
| 127 | #define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0 | ||
| 128 | #define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0 | ||
| 129 | #define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0 | ||
| 130 | #define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0 | ||
| 131 | #define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0 | ||
| 132 | #define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0 | ||
| 133 | #define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0 | ||
| 134 | #define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0 | ||
| 135 | #define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0 | ||
| 136 | #define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0 | ||
| 137 | #define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0 | ||
| 138 | #define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0 | ||
| 139 | #define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0 | ||
| 140 | #define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0 | ||
| 141 | #define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0 | ||
| 142 | #define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0 | ||
| 143 | #define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0 | ||
| 144 | #define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0 | ||
| 145 | #define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0 | ||
| 146 | #define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0 | ||
| 147 | #define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0 | ||
| 148 | #define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0 | ||
| 149 | #define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0 | ||
| 150 | #define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0 | ||
| 151 | #define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1 | ||
| 152 | #define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0 | ||
| 153 | #define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0 | ||
| 154 | #define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0 | ||
| 155 | #define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0 | ||
| 156 | #define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0 | ||
| 157 | #define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0 | ||
| 158 | #define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1 | ||
| 159 | #define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0 | ||
| 160 | #define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0 | ||
| 161 | #define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0 | ||
| 162 | #define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0 | ||
| 163 | #define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0 | ||
| 164 | #define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1 | ||
| 165 | #define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0 | ||
| 166 | #define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0 | ||
| 167 | #define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0 | ||
| 168 | #define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0 | ||
| 169 | #define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0 | ||
| 170 | #define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0 | ||
| 171 | #define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0 | ||
| 172 | #define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1 | ||
| 173 | #define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0 | ||
| 174 | #define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0 | ||
| 175 | #define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0 | ||
| 176 | #define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0 | ||
| 177 | #define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0 | ||
| 178 | #define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0 | ||
| 179 | #define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0 | ||
| 180 | #define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1 | ||
| 181 | #define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0 | ||
| 182 | #define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0 | ||
| 183 | #define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0 | ||
| 184 | #define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0 | ||
| 185 | #define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0 | ||
| 186 | #define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0 | ||
| 187 | #define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0 | ||
| 188 | #define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0 | ||
| 189 | #define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0 | ||
| 190 | #define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0 | ||
| 191 | #define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0 | ||
| 192 | #define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0 | ||
| 193 | #define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0 | ||
| 194 | #define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0 | ||
| 195 | #define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0 | ||
| 196 | #define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0 | ||
| 197 | #define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0 | ||
| 198 | #define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0 | ||
| 199 | #define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0 | ||
| 200 | #define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0 | ||
| 201 | #define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0 | ||
| 202 | #define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0 | ||
| 203 | #define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0 | ||
| 204 | #define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0 | ||
| 205 | #define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0 | ||
| 206 | #define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0 | ||
| 207 | #define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0 | ||
| 208 | #define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0 | ||
| 209 | #define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0 | ||
| 210 | #define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0 | ||
| 211 | #define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0 | ||
| 212 | #define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0 | ||
| 213 | #define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0 | ||
| 214 | #define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0 | ||
| 215 | #define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0 | ||
| 216 | #define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0 | ||
| 217 | #define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0 | ||
| 218 | #define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0 | ||
| 219 | #define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0 | ||
| 220 | #define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0 | ||
| 221 | #define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0 | ||
| 222 | #define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1 | ||
| 223 | #define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1 | ||
| 224 | #define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0 | ||
| 225 | #define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0 | ||
| 226 | #define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0 | ||
| 227 | #define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1 | ||
| 228 | #define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0 | ||
| 229 | #define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0 | ||
| 230 | #define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0 | ||
| 231 | #define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0 | ||
| 232 | #define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2 | ||
| 233 | #define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0 | ||
| 234 | #define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1 | ||
| 235 | #define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0 | ||
| 236 | #define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0 | ||
| 237 | #define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0 | ||
| 238 | #define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0 | ||
| 239 | #define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0 | ||
| 240 | #define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0 | ||
| 241 | #define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0 | ||
| 242 | #define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0 | ||
| 243 | #define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0 | ||
| 244 | #define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0 | ||
| 245 | #define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0 | ||
| 246 | #define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0 | ||
| 247 | #define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0 | ||
| 248 | #define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0 | ||
| 249 | #define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0 | ||
| 250 | #define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0 | ||
| 251 | #define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0 | ||
| 252 | #define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0 | ||
| 253 | #define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0 | ||
| 254 | #define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0 | ||
| 255 | #define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0 | ||
| 256 | #define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1 | ||
| 257 | #define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0 | ||
| 258 | #define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0 | ||
| 259 | #define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0 | ||
| 260 | #define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0 | ||
| 261 | #define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1 | ||
| 262 | #define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0 | ||
| 263 | #define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0 | ||
| 264 | #define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0 | ||
| 265 | #define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0 | ||
| 266 | #define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1 | ||
| 267 | #define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0 | ||
| 268 | #define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0 | ||
| 269 | #define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0 | ||
| 270 | #define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1 | ||
| 271 | #define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0 | ||
| 272 | #define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0 | ||
| 273 | #define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0 | ||
| 274 | #define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2 | ||
| 275 | #define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0 | ||
| 276 | #define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0 | ||
| 277 | #define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0 | ||
| 278 | #define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0 | ||
| 279 | #define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0 | ||
| 280 | #define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0 | ||
| 281 | #define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0 | ||
| 282 | #define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0 | ||
| 283 | #define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0 | ||
| 284 | #define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0 | ||
| 285 | #define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0 | ||
| 286 | #define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0 | ||
| 287 | #define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0 | ||
| 288 | #define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0 | ||
| 289 | #define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0 | ||
| 290 | #define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0 | ||
| 291 | #define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1 | ||
| 292 | #define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0 | ||
| 293 | #define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0 | ||
| 294 | #define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1 | ||
| 295 | #define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0 | ||
| 296 | #define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0 | ||
| 297 | #define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0 | ||
| 298 | #define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0 | ||
| 299 | #define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0 | ||
| 300 | #define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0 | ||
| 301 | #define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0 | ||
| 302 | #define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1 | ||
| 303 | #define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0 | ||
| 304 | #define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0 | ||
| 305 | #define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0 | ||
| 306 | #define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0 | ||
| 307 | #define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0 | ||
| 308 | #define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0 | ||
| 309 | #define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0 | ||
| 310 | #define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1 | ||
| 311 | #define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0 | ||
| 312 | #define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0 | ||
| 313 | #define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0 | ||
| 314 | #define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0 | ||
| 315 | #define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0 | ||
| 316 | #define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0 | ||
| 317 | #define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1 | ||
| 318 | #define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0 | ||
| 319 | #define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0 | ||
| 320 | #define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0 | ||
| 321 | #define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0 | ||
| 322 | #define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0 | ||
| 323 | #define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0 | ||
| 324 | #define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0 | ||
| 325 | #define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0 | ||
| 326 | #define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0 | ||
| 327 | #define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0 | ||
| 328 | #define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0 | ||
| 329 | #define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0 | ||
| 330 | #define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0 | ||
| 331 | #define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0 | ||
| 332 | #define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1 | ||
| 333 | #define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0 | ||
| 334 | #define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0 | ||
| 335 | #define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0 | ||
| 336 | #define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0 | ||
| 337 | #define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0 | ||
| 338 | #define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0 | ||
| 339 | #define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0 | ||
| 340 | #define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0 | ||
| 341 | #define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0 | ||
| 342 | #define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0 | ||
| 343 | #define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0 | ||
| 344 | #define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0 | ||
| 345 | #define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0 | ||
| 346 | #define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0 | ||
| 347 | #define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0 | ||
| 348 | #define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0 | ||
| 349 | #define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0 | ||
| 350 | #define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0 | ||
| 351 | #define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0 | ||
| 352 | #define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0 | ||
| 353 | #define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0 | ||
| 354 | #define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0 | ||
| 355 | #define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0 | ||
| 356 | #define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0 | ||
| 357 | #define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0 | ||
| 358 | #define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1 | ||
| 359 | #define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1 | ||
| 360 | #define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0 | ||
| 361 | #define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0 | ||
| 362 | #define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0 | ||
| 363 | #define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1 | ||
| 364 | #define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1 | ||
| 365 | #define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0 | ||
| 366 | #define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0 | ||
| 367 | #define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0 | ||
| 368 | #define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1 | ||
| 369 | #define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 | ||
| 370 | #define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 | ||
| 371 | #define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 | ||
| 372 | #define VF610_PAD_PTC12__ENET_RMII_RXD1 0x0E4 0x000 ALT1 0x0 | ||
| 373 | #define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 | ||
| 374 | #define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 | ||
| 375 | #define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 | ||
| 376 | #define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0 | ||
| 377 | #define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0 | ||
| 378 | #define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1 | ||
| 379 | #define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2 | ||
| 380 | #define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0 | ||
| 381 | #define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0 | ||
| 382 | #define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0 | ||
| 383 | #define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1 | ||
| 384 | #define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0 | ||
| 385 | #define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2 | ||
| 386 | #define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0 | ||
| 387 | #define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0 | ||
| 388 | #define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0 | ||
| 389 | #define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0 | ||
| 390 | #define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1 | ||
| 391 | #define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0 | ||
| 392 | #define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0 | ||
| 393 | #define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0 | ||
| 394 | #define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0 | ||
| 395 | #define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0 | ||
| 396 | #define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0 | ||
| 397 | #define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1 | ||
| 398 | #define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0 | ||
| 399 | #define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2 | ||
| 400 | #define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0 | ||
| 401 | #define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0 | ||
| 402 | #define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0 | ||
| 403 | #define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0 | ||
| 404 | #define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0 | ||
| 405 | #define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0 | ||
| 406 | #define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1 | ||
| 407 | #define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0 | ||
| 408 | #define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0 | ||
| 409 | #define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0 | ||
| 410 | #define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0 | ||
| 411 | #define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0 | ||
| 412 | #define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0 | ||
| 413 | #define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0 | ||
| 414 | #define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0 | ||
| 415 | #define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0 | ||
| 416 | #define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0 | ||
| 417 | #define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0 | ||
| 418 | #define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0 | ||
| 419 | #define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0 | ||
| 420 | #define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0 | ||
| 421 | #define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0 | ||
| 422 | #define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0 | ||
| 423 | #define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0 | ||
| 424 | #define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0 | ||
| 425 | #define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0 | ||
| 426 | #define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0 | ||
| 427 | #define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0 | ||
| 428 | #define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0 | ||
| 429 | #define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0 | ||
| 430 | #define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1 | ||
| 431 | #define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0 | ||
| 432 | #define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0 | ||
| 433 | #define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0 | ||
| 434 | #define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0 | ||
| 435 | #define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0 | ||
| 436 | #define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0 | ||
| 437 | #define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1 | ||
| 438 | #define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0 | ||
| 439 | #define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0 | ||
| 440 | #define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0 | ||
| 441 | #define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0 | ||
| 442 | #define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0 | ||
| 443 | #define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0 | ||
| 444 | #define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0 | ||
| 445 | #define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0 | ||
| 446 | #define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0 | ||
| 447 | #define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0 | ||
| 448 | #define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0 | ||
| 449 | #define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0 | ||
| 450 | #define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0 | ||
| 451 | #define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0 | ||
| 452 | #define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0 | ||
| 453 | #define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0 | ||
| 454 | #define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0 | ||
| 455 | #define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0 | ||
| 456 | #define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0 | ||
| 457 | #define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0 | ||
| 458 | #define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0 | ||
| 459 | #define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0 | ||
| 460 | #define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0 | ||
| 461 | #define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1 | ||
| 462 | #define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0 | ||
| 463 | #define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1 | ||
| 464 | #define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0 | ||
| 465 | #define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0 | ||
| 466 | #define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0 | ||
| 467 | #define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0 | ||
| 468 | #define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0 | ||
| 469 | #define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1 | ||
| 470 | #define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0 | ||
| 471 | #define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1 | ||
| 472 | #define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0 | ||
| 473 | #define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0 | ||
| 474 | #define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0 | ||
| 475 | #define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0 | ||
| 476 | #define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0 | ||
| 477 | #define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0 | ||
| 478 | #define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0 | ||
| 479 | #define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0 | ||
| 480 | #define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0 | ||
| 481 | #define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0 | ||
| 482 | #define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0 | ||
| 483 | #define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0 | ||
| 484 | #define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0 | ||
| 485 | #define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0 | ||
| 486 | #define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0 | ||
| 487 | #define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0 | ||
| 488 | #define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0 | ||
| 489 | #define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0 | ||
| 490 | #define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0 | ||
| 491 | #define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2 | ||
| 492 | #define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0 | ||
| 493 | #define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0 | ||
| 494 | #define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0 | ||
| 495 | #define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0 | ||
| 496 | #define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0 | ||
| 497 | #define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0 | ||
| 498 | #define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2 | ||
| 499 | #define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0 | ||
| 500 | #define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0 | ||
| 501 | #define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0 | ||
| 502 | #define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0 | ||
| 503 | #define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0 | ||
| 504 | #define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0 | ||
| 505 | #define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2 | ||
| 506 | #define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0 | ||
| 507 | #define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0 | ||
| 508 | #define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0 | ||
| 509 | #define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0 | ||
| 510 | #define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0 | ||
| 511 | #define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2 | ||
| 512 | #define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0 | ||
| 513 | #define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0 | ||
| 514 | #define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0 | ||
| 515 | #define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2 | ||
| 516 | #define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0 | ||
| 517 | #define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0 | ||
| 518 | #define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0 | ||
| 519 | #define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0 | ||
| 520 | #define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0 | ||
| 521 | #define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2 | ||
| 522 | #define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0 | ||
| 523 | #define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0 | ||
| 524 | #define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0 | ||
| 525 | #define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0 | ||
| 526 | #define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0 | ||
| 527 | #define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0 | ||
| 528 | #define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0 | ||
| 529 | #define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0 | ||
| 530 | #define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0 | ||
| 531 | #define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0 | ||
| 532 | #define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0 | ||
| 533 | #define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0 | ||
| 534 | #define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1 | ||
| 535 | #define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0 | ||
| 536 | #define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0 | ||
| 537 | #define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0 | ||
| 538 | #define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0 | ||
| 539 | #define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0 | ||
| 540 | #define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0 | ||
| 541 | #define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0 | ||
| 542 | #define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0 | ||
| 543 | #define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0 | ||
| 544 | #define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0 | ||
| 545 | #define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0 | ||
| 546 | #define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0 | ||
| 547 | #define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1 | ||
| 548 | #define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0 | ||
| 549 | #define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0 | ||
| 550 | #define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0 | ||
| 551 | #define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0 | ||
| 552 | #define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1 | ||
| 553 | #define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0 | ||
| 554 | #define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0 | ||
| 555 | #define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0 | ||
| 556 | #define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0 | ||
| 557 | #define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0 | ||
| 558 | #define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0 | ||
| 559 | #define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0 | ||
| 560 | #define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0 | ||
| 561 | #define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0 | ||
| 562 | #define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0 | ||
| 563 | #define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1 | ||
| 564 | #define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0 | ||
| 565 | #define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0 | ||
| 566 | #define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0 | ||
| 567 | #define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0 | ||
| 568 | #define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0 | ||
| 569 | #define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0 | ||
| 570 | #define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0 | ||
| 571 | #define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0 | ||
| 572 | #define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0 | ||
| 573 | #define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0 | ||
| 574 | #define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0 | ||
| 575 | #define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0 | ||
| 576 | #define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0 | ||
| 577 | #define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0 | ||
| 578 | #define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0 | ||
| 579 | #define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0 | ||
| 580 | #define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0 | ||
| 581 | #define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0 | ||
| 582 | #define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0 | ||
| 583 | #define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0 | ||
| 584 | #define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0 | ||
| 585 | #define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0 | ||
| 586 | #define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0 | ||
| 587 | #define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0 | ||
| 588 | #define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0 | ||
| 589 | #define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0 | ||
| 590 | #define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0 | ||
| 591 | #define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0 | ||
| 592 | #define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0 | ||
| 593 | #define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0 | ||
| 594 | #define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2 | ||
| 595 | #define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1 | ||
| 596 | #define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0 | ||
| 597 | #define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0 | ||
| 598 | #define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0 | ||
| 599 | #define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0 | ||
| 600 | #define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0 | ||
| 601 | #define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0 | ||
| 602 | #define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2 | ||
| 603 | #define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1 | ||
| 604 | #define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0 | ||
| 605 | #define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0 | ||
| 606 | #define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0 | ||
| 607 | #define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0 | ||
| 608 | #define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0 | ||
| 609 | #define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0 | ||
| 610 | #define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0 | ||
| 611 | #define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1 | ||
| 612 | #define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0 | ||
| 613 | #define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0 | ||
| 614 | #define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0 | ||
| 615 | #define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0 | ||
| 616 | #define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0 | ||
| 617 | #define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2 | ||
| 618 | #define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0 | ||
| 619 | #define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0 | ||
| 620 | #define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0 | ||
| 621 | #define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0 | ||
| 622 | #define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0 | ||
| 623 | #define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0 | ||
| 624 | #define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0 | ||
| 625 | #define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0 | ||
| 626 | #define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0 | ||
| 627 | #define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0 | ||
| 628 | #define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0 | ||
| 629 | #define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0 | ||
| 630 | #define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0 | ||
| 631 | #define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0 | ||
| 632 | #define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0 | ||
| 633 | #define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0 | ||
| 634 | #define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0 | ||
| 635 | #define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0 | ||
| 636 | #define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0 | ||
| 637 | #define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0 | ||
| 638 | #define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0 | ||
| 639 | #define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0 | ||
| 640 | #define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0 | ||
| 641 | #define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0 | ||
| 642 | #define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0 | ||
| 643 | #define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0 | ||
| 644 | #define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0 | ||
| 645 | #define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0 | ||
| 646 | #define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0 | ||
| 647 | #define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0 | ||
| 648 | #define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0 | ||
| 649 | #define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0 | ||
| 650 | #define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0 | ||
| 651 | #define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0 | ||
| 652 | #define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0 | ||
| 653 | #define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0 | ||
| 654 | #define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0 | ||
| 655 | #define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0 | ||
| 656 | #define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0 | ||
| 657 | #define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0 | ||
| 658 | #define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0 | ||
| 659 | #define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0 | ||
| 660 | #define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0 | ||
| 661 | #define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0 | ||
| 662 | #define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0 | ||
| 663 | #define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0 | ||
| 664 | #define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0 | ||
| 665 | #define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0 | ||
| 666 | #define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0 | ||
| 667 | #define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0 | ||
| 668 | #define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0 | ||
| 669 | #define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0 | ||
| 670 | #define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0 | ||
| 671 | #define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0 | ||
| 672 | #define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0 | ||
| 673 | #define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1 | ||
| 674 | #define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0 | ||
| 675 | #define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0 | ||
| 676 | #define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0 | ||
| 677 | #define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0 | ||
| 678 | #define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0 | ||
| 679 | #define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0 | ||
| 680 | #define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0 | ||
| 681 | #define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0 | ||
| 682 | #define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0 | ||
| 683 | #define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0 | ||
| 684 | #define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0 | ||
| 685 | #define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0 | ||
| 686 | #define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0 | ||
| 687 | #define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0 | ||
| 688 | #define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0 | ||
| 689 | #define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0 | ||
| 690 | #define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0 | ||
| 691 | #define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0 | ||
| 692 | #define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0 | ||
| 693 | #define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0 | ||
| 694 | #define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0 | ||
| 695 | #define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0 | ||
| 696 | #define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0 | ||
| 697 | #define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0 | ||
| 698 | #define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0 | ||
| 699 | #define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0 | ||
| 700 | #define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0 | ||
| 701 | #define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0 | ||
| 702 | #define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0 | ||
| 703 | #define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0 | ||
| 704 | #define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0 | ||
| 705 | #define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0 | ||
| 706 | #define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0 | ||
| 707 | #define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0 | ||
| 708 | #define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0 | ||
| 709 | #define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0 | ||
| 710 | #define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0 | ||
| 711 | #define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0 | ||
| 712 | #define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0 | ||
| 713 | #define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0 | ||
| 714 | #define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0 | ||
| 715 | #define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0 | ||
| 716 | #define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0 | ||
| 717 | #define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0 | ||
| 718 | #define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0 | ||
| 719 | #define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0 | ||
| 720 | #define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0 | ||
| 721 | #define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0 | ||
| 722 | #define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0 | ||
| 723 | #define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0 | ||
| 724 | #define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0 | ||
| 725 | #define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0 | ||
| 726 | #define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0 | ||
| 727 | #define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0 | ||
| 728 | #define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0 | ||
| 729 | #define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0 | ||
| 730 | #define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0 | ||
| 731 | #define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0 | ||
| 732 | #define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0 | ||
| 733 | #define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0 | ||
| 734 | #define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0 | ||
| 735 | #define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0 | ||
| 736 | #define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0 | ||
| 737 | #define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0 | ||
| 738 | #define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0 | ||
| 739 | #define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0 | ||
| 740 | #define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0 | ||
| 741 | #define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0 | ||
| 742 | #define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0 | ||
| 743 | #define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0 | ||
| 744 | #define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0 | ||
| 745 | #define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0 | ||
| 746 | #define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0 | ||
| 747 | #define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0 | ||
| 748 | #define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0 | ||
| 749 | #define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0 | ||
| 750 | #define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0 | ||
| 751 | #define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0 | ||
| 752 | #define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0 | ||
| 753 | #define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0 | ||
| 754 | #define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0 | ||
| 755 | #define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0 | ||
| 756 | #define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0 | ||
| 757 | #define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0 | ||
| 758 | #define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0 | ||
| 759 | #define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0 | ||
| 760 | #define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0 | ||
| 761 | #define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0 | ||
| 762 | #define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0 | ||
| 763 | #define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0 | ||
| 764 | #define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0 | ||
| 765 | #define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0 | ||
| 766 | #define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0 | ||
| 767 | #define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3 | ||
| 768 | #define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0 | ||
| 769 | #define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0 | ||
| 770 | #define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0 | ||
| 771 | #define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0 | ||
| 772 | #define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3 | ||
| 773 | #define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0 | ||
| 774 | #define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0 | ||
| 775 | #define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0 | ||
| 776 | #define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0 | ||
| 777 | #define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0 | ||
| 778 | #define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0 | ||
| 779 | #define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0 | ||
| 780 | #define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0 | ||
| 781 | #define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0 | ||
| 782 | #define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0 | ||
| 783 | #define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0 | ||
| 784 | #define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0 | ||
| 785 | #define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0 | ||
| 786 | #define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0 | ||
| 787 | #define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0 | ||
| 788 | #define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0 | ||
| 789 | #define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0 | ||
| 790 | #define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0 | ||
| 791 | #define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0 | ||
| 792 | #define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0 | ||
| 793 | #define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0 | ||
| 794 | #define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0 | ||
| 795 | #define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0 | ||
| 796 | #define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0 | ||
| 797 | #define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0 | ||
| 798 | #define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0 | ||
| 799 | #define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0 | ||
| 800 | #define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3 | ||
| 801 | #define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0 | ||
| 802 | #define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0 | ||
| 803 | #define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0 | ||
| 804 | #define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0 | ||
| 805 | #define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3 | ||
| 806 | #define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0 | ||
| 807 | #define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0 | ||
| 808 | #define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1 | ||
| 809 | |||
| 810 | #endif | ||
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts new file mode 100644 index 000000000000..b3905f5bcaf9 --- /dev/null +++ b/arch/arm/boot/dts/vf610-twr.dts | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | #include "vf610.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "VF610 Tower Board"; | ||
| 15 | compatible = "fsl,vf610-twr", "fsl,vf610"; | ||
| 16 | |||
| 17 | chosen { | ||
| 18 | bootargs = "console=ttyLP1,115200"; | ||
| 19 | }; | ||
| 20 | |||
| 21 | memory { | ||
| 22 | reg = <0x80000000 0x8000000>; | ||
| 23 | }; | ||
| 24 | |||
| 25 | clocks { | ||
| 26 | audio_ext { | ||
| 27 | compatible = "fixed-clock"; | ||
| 28 | clock-frequency = <24576000>; | ||
| 29 | }; | ||
| 30 | |||
| 31 | enet_ext { | ||
| 32 | compatible = "fixed-clock"; | ||
| 33 | clock-frequency = <50000000>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 36 | |||
| 37 | }; | ||
| 38 | |||
| 39 | &fec0 { | ||
| 40 | phy-mode = "rmii"; | ||
| 41 | pinctrl-names = "default"; | ||
| 42 | pinctrl-0 = <&pinctrl_fec0_1>; | ||
| 43 | status = "okay"; | ||
| 44 | }; | ||
| 45 | |||
| 46 | &fec1 { | ||
| 47 | phy-mode = "rmii"; | ||
| 48 | pinctrl-names = "default"; | ||
| 49 | pinctrl-0 = <&pinctrl_fec1_1>; | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | &uart1 { | ||
| 54 | pinctrl-names = "default"; | ||
| 55 | pinctrl-0 = <&pinctrl_uart1_1>; | ||
| 56 | status = "okay"; | ||
| 57 | }; | ||
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi new file mode 100644 index 000000000000..e1eb7dadda80 --- /dev/null +++ b/arch/arm/boot/dts/vf610.dtsi | |||
| @@ -0,0 +1,464 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include "skeleton.dtsi" | ||
| 11 | #include "vf610-pinfunc.h" | ||
| 12 | #include <dt-bindings/clock/vf610-clock.h> | ||
| 13 | |||
| 14 | / { | ||
| 15 | aliases { | ||
| 16 | serial0 = &uart0; | ||
| 17 | serial1 = &uart1; | ||
| 18 | serial2 = &uart2; | ||
| 19 | serial3 = &uart3; | ||
| 20 | serial4 = &uart4; | ||
| 21 | serial5 = &uart5; | ||
| 22 | gpio0 = &gpio1; | ||
| 23 | gpio1 = &gpio2; | ||
| 24 | gpio2 = &gpio3; | ||
| 25 | gpio3 = &gpio4; | ||
| 26 | gpio4 = &gpio5; | ||
| 27 | }; | ||
| 28 | |||
| 29 | cpus { | ||
| 30 | #address-cells = <1>; | ||
| 31 | #size-cells = <0>; | ||
| 32 | |||
| 33 | cpu@0 { | ||
| 34 | compatible = "arm,cortex-a5"; | ||
| 35 | device_type = "cpu"; | ||
| 36 | reg = <0x0>; | ||
| 37 | next-level-cache = <&L2>; | ||
| 38 | }; | ||
| 39 | }; | ||
| 40 | |||
| 41 | clocks { | ||
| 42 | #address-cells = <1>; | ||
| 43 | #size-cells = <0>; | ||
| 44 | |||
| 45 | sxosc { | ||
| 46 | compatible = "fixed-clock"; | ||
| 47 | clock-frequency = <32768>; | ||
| 48 | }; | ||
| 49 | |||
| 50 | fxosc { | ||
| 51 | compatible = "fixed-clock"; | ||
| 52 | clock-frequency = <24000000>; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 56 | soc { | ||
| 57 | #address-cells = <1>; | ||
| 58 | #size-cells = <1>; | ||
| 59 | compatible = "simple-bus"; | ||
| 60 | interrupt-parent = <&intc>; | ||
| 61 | ranges; | ||
| 62 | |||
| 63 | aips0: aips-bus@40000000 { | ||
| 64 | compatible = "fsl,aips-bus", "simple-bus"; | ||
| 65 | #address-cells = <1>; | ||
| 66 | #size-cells = <1>; | ||
| 67 | interrupt-parent = <&intc>; | ||
| 68 | reg = <0x40000000 0x70000>; | ||
| 69 | ranges; | ||
| 70 | |||
| 71 | intc: interrupt-controller@40002000 { | ||
| 72 | compatible = "arm,cortex-a9-gic"; | ||
| 73 | #interrupt-cells = <3>; | ||
| 74 | #address-cells = <1>; | ||
| 75 | #size-cells = <1>; | ||
| 76 | interrupt-controller; | ||
| 77 | reg = <0x40003000 0x1000>, | ||
| 78 | <0x40002100 0x100>; | ||
| 79 | }; | ||
| 80 | |||
| 81 | L2: l2-cache@40006000 { | ||
| 82 | compatible = "arm,pl310-cache"; | ||
| 83 | reg = <0x40006000 0x1000>; | ||
| 84 | cache-unified; | ||
| 85 | cache-level = <2>; | ||
| 86 | arm,data-latency = <1 1 1>; | ||
| 87 | arm,tag-latency = <2 2 2>; | ||
| 88 | }; | ||
| 89 | |||
| 90 | uart0: serial@40027000 { | ||
| 91 | compatible = "fsl,vf610-lpuart"; | ||
| 92 | reg = <0x40027000 0x1000>; | ||
| 93 | interrupts = <0 61 0x00>; | ||
| 94 | clocks = <&clks VF610_CLK_UART0>; | ||
| 95 | clock-names = "ipg"; | ||
| 96 | status = "disabled"; | ||
| 97 | }; | ||
| 98 | |||
| 99 | uart1: serial@40028000 { | ||
| 100 | compatible = "fsl,vf610-lpuart"; | ||
| 101 | reg = <0x40028000 0x1000>; | ||
| 102 | interrupts = <0 62 0x04>; | ||
| 103 | clocks = <&clks VF610_CLK_UART1>; | ||
| 104 | clock-names = "ipg"; | ||
| 105 | status = "disabled"; | ||
| 106 | }; | ||
| 107 | |||
| 108 | uart2: serial@40029000 { | ||
| 109 | compatible = "fsl,vf610-lpuart"; | ||
| 110 | reg = <0x40029000 0x1000>; | ||
| 111 | interrupts = <0 63 0x04>; | ||
| 112 | clocks = <&clks VF610_CLK_UART2>; | ||
| 113 | clock-names = "ipg"; | ||
| 114 | status = "disabled"; | ||
| 115 | }; | ||
| 116 | |||
| 117 | uart3: serial@4002a000 { | ||
| 118 | compatible = "fsl,vf610-lpuart"; | ||
| 119 | reg = <0x4002a000 0x1000>; | ||
| 120 | interrupts = <0 64 0x04>; | ||
| 121 | clocks = <&clks VF610_CLK_UART3>; | ||
| 122 | clock-names = "ipg"; | ||
| 123 | status = "disabled"; | ||
| 124 | }; | ||
| 125 | |||
| 126 | sai2: sai@40031000 { | ||
| 127 | compatible = "fsl,vf610-sai"; | ||
| 128 | reg = <0x40031000 0x1000>; | ||
| 129 | interrupts = <0 86 0x04>; | ||
| 130 | clocks = <&clks VF610_CLK_SAI2>; | ||
| 131 | clock-names = "sai"; | ||
| 132 | status = "disabled"; | ||
| 133 | }; | ||
| 134 | |||
| 135 | pit: pit@40037000 { | ||
| 136 | compatible = "fsl,vf610-pit"; | ||
| 137 | reg = <0x40037000 0x1000>; | ||
| 138 | interrupts = <0 39 0x04>; | ||
| 139 | clocks = <&clks VF610_CLK_PIT>; | ||
| 140 | clock-names = "pit"; | ||
| 141 | }; | ||
| 142 | |||
| 143 | wdog@4003e000 { | ||
| 144 | compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; | ||
| 145 | reg = <0x4003e000 0x1000>; | ||
| 146 | clocks = <&clks VF610_CLK_WDT>; | ||
| 147 | clock-names = "wdog"; | ||
| 148 | }; | ||
| 149 | |||
| 150 | qspi0: quadspi@40044000 { | ||
| 151 | #address-cells = <1>; | ||
| 152 | #size-cells = <0>; | ||
| 153 | compatible = "fsl,vf610-qspi"; | ||
| 154 | reg = <0x40044000 0x1000>; | ||
| 155 | interrupts = <0 24 0x04>; | ||
| 156 | clocks = <&clks VF610_CLK_QSPI0_EN>, | ||
| 157 | <&clks VF610_CLK_QSPI0>; | ||
| 158 | clock-names = "qspi_en", "qspi"; | ||
| 159 | status = "disabled"; | ||
| 160 | }; | ||
| 161 | |||
| 162 | iomuxc: iomuxc@40048000 { | ||
| 163 | compatible = "fsl,vf610-iomuxc"; | ||
| 164 | reg = <0x40048000 0x1000>; | ||
| 165 | #gpio-range-cells = <3>; | ||
| 166 | |||
| 167 | /* functions and groups pins */ | ||
| 168 | |||
| 169 | dcu0 { | ||
| 170 | pinctrl_dcu0_1: dcu0grp_1 { | ||
| 171 | fsl,pins = < | ||
| 172 | VF610_PAD_PTB8__GPIO_30 0x42 | ||
| 173 | VF610_PAD_PTE0__DCU0_HSYNC 0x42 | ||
| 174 | VF610_PAD_PTE1__DCU0_VSYNC 0x42 | ||
| 175 | VF610_PAD_PTE2__DCU0_PCLK 0x42 | ||
| 176 | VF610_PAD_PTE4__DCU0_DE 0x42 | ||
| 177 | VF610_PAD_PTE5__DCU0_R0 0x42 | ||
| 178 | VF610_PAD_PTE6__DCU0_R1 0x42 | ||
| 179 | VF610_PAD_PTE7__DCU0_R2 0x42 | ||
| 180 | VF610_PAD_PTE8__DCU0_R3 0x42 | ||
| 181 | VF610_PAD_PTE9__DCU0_R4 0x42 | ||
| 182 | VF610_PAD_PTE10__DCU0_R5 0x42 | ||
| 183 | VF610_PAD_PTE11__DCU0_R6 0x42 | ||
| 184 | VF610_PAD_PTE12__DCU0_R7 0x42 | ||
| 185 | VF610_PAD_PTE13__DCU0_G0 0x42 | ||
| 186 | VF610_PAD_PTE14__DCU0_G1 0x42 | ||
| 187 | VF610_PAD_PTE15__DCU0_G2 0x42 | ||
| 188 | VF610_PAD_PTE16__DCU0_G3 0x42 | ||
| 189 | VF610_PAD_PTE17__DCU0_G4 0x42 | ||
| 190 | VF610_PAD_PTE18__DCU0_G5 0x42 | ||
| 191 | VF610_PAD_PTE19__DCU0_G6 0x42 | ||
| 192 | VF610_PAD_PTE20__DCU0_G7 0x42 | ||
| 193 | VF610_PAD_PTE21__DCU0_B0 0x42 | ||
| 194 | VF610_PAD_PTE22__DCU0_B1 0x42 | ||
| 195 | VF610_PAD_PTE23__DCU0_B2 0x42 | ||
| 196 | VF610_PAD_PTE24__DCU0_B3 0x42 | ||
| 197 | VF610_PAD_PTE25__DCU0_B4 0x42 | ||
| 198 | VF610_PAD_PTE26__DCU0_B5 0x42 | ||
| 199 | VF610_PAD_PTE27__DCU0_B6 0x42 | ||
| 200 | VF610_PAD_PTE28__DCU0_B7 0x42 | ||
| 201 | >; | ||
| 202 | }; | ||
| 203 | }; | ||
| 204 | |||
| 205 | dspi0 { | ||
| 206 | pinctrl_dspi0_1: dspi0grp_1 { | ||
| 207 | fsl,pins = < | ||
| 208 | VF610_PAD_PTB19__DSPI0_CS0 0x1182 | ||
| 209 | VF610_PAD_PTB20__DSPI0_SIN 0x1181 | ||
| 210 | VF610_PAD_PTB21__DSPI0_SOUT 0x1182 | ||
| 211 | VF610_PAD_PTB22__DSPI0_SCK 0x1182 | ||
| 212 | >; | ||
| 213 | }; | ||
| 214 | }; | ||
| 215 | |||
| 216 | esdhc1 { | ||
| 217 | pinctrl_esdhc1_1: esdhc1grp_1 { | ||
| 218 | fsl,pins = < | ||
| 219 | VF610_PAD_PTA24__ESDHC1_CLK 0x31ef | ||
| 220 | VF610_PAD_PTA25__ESDHC1_CMD 0x31ef | ||
| 221 | VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef | ||
| 222 | VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef | ||
| 223 | VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef | ||
| 224 | VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef | ||
| 225 | VF610_PAD_PTA7__GPIO_134 0x219d | ||
| 226 | >; | ||
| 227 | }; | ||
| 228 | }; | ||
| 229 | |||
| 230 | fec0 { | ||
| 231 | pinctrl_fec0_1: fec0grp_1 { | ||
| 232 | fsl,pins = < | ||
| 233 | VF610_PAD_PTA6__RMII_CLKIN 0x30d1 | ||
| 234 | VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 | ||
| 235 | VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 | ||
| 236 | VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 | ||
| 237 | VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 | ||
| 238 | VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 | ||
| 239 | VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 | ||
| 240 | VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 | ||
| 241 | VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 | ||
| 242 | VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 | ||
| 243 | >; | ||
| 244 | }; | ||
| 245 | }; | ||
| 246 | |||
| 247 | fec1 { | ||
| 248 | pinctrl_fec1_1: fec1grp_1 { | ||
| 249 | fsl,pins = < | ||
| 250 | VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 | ||
| 251 | VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 | ||
| 252 | VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 | ||
| 253 | VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 | ||
| 254 | VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 | ||
| 255 | VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 | ||
| 256 | VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 | ||
| 257 | VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 | ||
| 258 | VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 | ||
| 259 | >; | ||
| 260 | }; | ||
| 261 | }; | ||
| 262 | |||
| 263 | i2c0 { | ||
| 264 | pinctrl_i2c0_1: i2c0grp_1 { | ||
| 265 | fsl,pins = < | ||
| 266 | VF610_PAD_PTB14__I2C0_SCL 0x30d3 | ||
| 267 | VF610_PAD_PTB15__I2C0_SDA 0x30d3 | ||
| 268 | >; | ||
| 269 | }; | ||
| 270 | }; | ||
| 271 | |||
| 272 | pwm0 { | ||
| 273 | pinctrl_pwm0_1: pwm0grp_1 { | ||
| 274 | fsl,pins = < | ||
| 275 | VF610_PAD_PTB0__FTM0_CH0 0x1582 | ||
| 276 | VF610_PAD_PTB1__FTM0_CH1 0x1582 | ||
| 277 | VF610_PAD_PTB2__FTM0_CH2 0x1582 | ||
| 278 | VF610_PAD_PTB3__FTM0_CH3 0x1582 | ||
| 279 | VF610_PAD_PTB6__FTM0_CH6 0x1582 | ||
| 280 | VF610_PAD_PTB7__FTM0_CH7 0x1582 | ||
| 281 | >; | ||
| 282 | }; | ||
| 283 | }; | ||
| 284 | |||
| 285 | qspi0 { | ||
| 286 | pinctrl_qspi0_1: qspi0grp_1 { | ||
| 287 | fsl,pins = < | ||
| 288 | VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b | ||
| 289 | VF610_PAD_PTD1__QSPI0_A_CS0 0x307f | ||
| 290 | VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073 | ||
| 291 | VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073 | ||
| 292 | VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073 | ||
| 293 | VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b | ||
| 294 | VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b | ||
| 295 | VF610_PAD_PTD8__QSPI0_B_CS0 0x307f | ||
| 296 | VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073 | ||
| 297 | VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073 | ||
| 298 | VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073 | ||
| 299 | VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b | ||
| 300 | >; | ||
| 301 | }; | ||
| 302 | }; | ||
| 303 | |||
| 304 | sai2 { | ||
| 305 | pinctrl_sai2_1: sai2grp_1 { | ||
| 306 | fsl,pins = < | ||
| 307 | VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed | ||
| 308 | VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee | ||
| 309 | VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed | ||
| 310 | VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed | ||
| 311 | VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed | ||
| 312 | VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed | ||
| 313 | VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed | ||
| 314 | >; | ||
| 315 | }; | ||
| 316 | }; | ||
| 317 | |||
| 318 | uart1 { | ||
| 319 | pinctrl_uart1_1: uart1grp_1 { | ||
| 320 | fsl,pins = < | ||
| 321 | VF610_PAD_PTB4__UART1_TX 0x21a2 | ||
| 322 | VF610_PAD_PTB5__UART1_RX 0x21a1 | ||
| 323 | >; | ||
| 324 | }; | ||
| 325 | }; | ||
| 326 | |||
| 327 | usbvbus { | ||
| 328 | pinctrl_usbvbus_1: usbvbusgrp_1 { | ||
| 329 | fsl,pins = < | ||
| 330 | VF610_PAD_PTA24__USB1_VBUS_EN 0x219c | ||
| 331 | VF610_PAD_PTA16__USB0_VBUS_EN 0x219c | ||
| 332 | >; | ||
| 333 | }; | ||
| 334 | }; | ||
| 335 | |||
| 336 | }; | ||
| 337 | |||
| 338 | gpio1: gpio@40049000 { | ||
| 339 | compatible = "fsl,vf610-gpio"; | ||
| 340 | reg = <0x40049000 0x1000 0x400ff000 0x40>; | ||
| 341 | interrupts = <0 107 0x04>; | ||
| 342 | gpio-controller; | ||
| 343 | #gpio-cells = <2>; | ||
| 344 | interrupt-controller; | ||
| 345 | #interrupt-cells = <2>; | ||
| 346 | gpio-ranges = <&iomuxc 0 0 32>; | ||
| 347 | }; | ||
| 348 | |||
| 349 | gpio2: gpio@4004a000 { | ||
| 350 | compatible = "fsl,vf610-gpio"; | ||
| 351 | reg = <0x4004a000 0x1000 0x400ff040 0x40>; | ||
| 352 | interrupts = <0 108 0x04>; | ||
| 353 | gpio-controller; | ||
| 354 | #gpio-cells = <2>; | ||
| 355 | interrupt-controller; | ||
| 356 | #interrupt-cells = <2>; | ||
| 357 | gpio-ranges = <&iomuxc 0 32 32>; | ||
| 358 | }; | ||
| 359 | |||
| 360 | gpio3: gpio@4004b000 { | ||
| 361 | compatible = "fsl,vf610-gpio"; | ||
| 362 | reg = <0x4004b000 0x1000 0x400ff080 0x40>; | ||
| 363 | interrupts = <0 109 0x04>; | ||
| 364 | gpio-controller; | ||
| 365 | #gpio-cells = <2>; | ||
| 366 | interrupt-controller; | ||
| 367 | #interrupt-cells = <2>; | ||
| 368 | gpio-ranges = <&iomuxc 0 64 32>; | ||
| 369 | }; | ||
| 370 | |||
| 371 | gpio4: gpio@4004c000 { | ||
| 372 | compatible = "fsl,vf610-gpio"; | ||
| 373 | reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; | ||
| 374 | interrupts = <0 110 0x04>; | ||
| 375 | gpio-controller; | ||
| 376 | #gpio-cells = <2>; | ||
| 377 | interrupt-controller; | ||
| 378 | #interrupt-cells = <2>; | ||
| 379 | gpio-ranges = <&iomuxc 0 96 32>; | ||
| 380 | }; | ||
| 381 | |||
| 382 | gpio5: gpio@4004d000 { | ||
| 383 | compatible = "fsl,vf610-gpio"; | ||
| 384 | reg = <0x4004d000 0x1000 0x400ff100 0x40>; | ||
| 385 | interrupts = <0 111 0x04>; | ||
| 386 | gpio-controller; | ||
| 387 | #gpio-cells = <2>; | ||
| 388 | interrupt-controller; | ||
| 389 | #interrupt-cells = <2>; | ||
| 390 | gpio-ranges = <&iomuxc 0 128 7>; | ||
| 391 | }; | ||
| 392 | |||
| 393 | anatop@40050000 { | ||
| 394 | compatible = "fsl,vf610-anatop"; | ||
| 395 | reg = <0x40050000 0x1000>; | ||
| 396 | }; | ||
| 397 | |||
| 398 | i2c0: i2c@40066000 { | ||
| 399 | #address-cells = <1>; | ||
| 400 | #size-cells = <0>; | ||
| 401 | compatible = "fsl,vf610-i2c"; | ||
| 402 | reg = <0x40066000 0x1000>; | ||
| 403 | interrupts =<0 71 0x04>; | ||
| 404 | clocks = <&clks VF610_CLK_I2C0>; | ||
| 405 | clock-names = "ipg"; | ||
| 406 | status = "disabled"; | ||
| 407 | }; | ||
| 408 | |||
| 409 | clks: ccm@4006b000 { | ||
| 410 | compatible = "fsl,vf610-ccm"; | ||
| 411 | reg = <0x4006b000 0x1000>; | ||
| 412 | #clock-cells = <1>; | ||
| 413 | }; | ||
| 414 | }; | ||
| 415 | |||
| 416 | aips1: aips-bus@40080000 { | ||
| 417 | compatible = "fsl,aips-bus", "simple-bus"; | ||
| 418 | #address-cells = <1>; | ||
| 419 | #size-cells = <1>; | ||
| 420 | reg = <0x40080000 0x80000>; | ||
| 421 | ranges; | ||
| 422 | |||
| 423 | uart4: serial@400a9000 { | ||
| 424 | compatible = "fsl,vf610-lpuart"; | ||
| 425 | reg = <0x400a9000 0x1000>; | ||
| 426 | interrupts = <0 65 0x04>; | ||
| 427 | clocks = <&clks VF610_CLK_UART4>; | ||
| 428 | clock-names = "ipg"; | ||
| 429 | status = "disabled"; | ||
| 430 | }; | ||
| 431 | |||
| 432 | uart5: serial@400aa000 { | ||
| 433 | compatible = "fsl,vf610-lpuart"; | ||
| 434 | reg = <0x400aa000 0x1000>; | ||
| 435 | interrupts = <0 66 0x04>; | ||
| 436 | clocks = <&clks VF610_CLK_UART5>; | ||
| 437 | clock-names = "ipg"; | ||
| 438 | status = "disabled"; | ||
| 439 | }; | ||
| 440 | |||
| 441 | fec0: ethernet@400d0000 { | ||
| 442 | compatible = "fsl,mvf600-fec"; | ||
| 443 | reg = <0x400d0000 0x1000>; | ||
| 444 | interrupts = <0 78 0x04>; | ||
| 445 | clocks = <&clks VF610_CLK_ENET>, | ||
| 446 | <&clks VF610_CLK_ENET>, | ||
| 447 | <&clks VF610_CLK_ENET>; | ||
| 448 | clock-names = "ipg", "ahb", "ptp"; | ||
| 449 | status = "disabled"; | ||
| 450 | }; | ||
| 451 | |||
| 452 | fec1: ethernet@400d1000 { | ||
| 453 | compatible = "fsl,mvf600-fec"; | ||
| 454 | reg = <0x400d1000 0x1000>; | ||
| 455 | interrupts = <0 79 0x04>; | ||
| 456 | clocks = <&clks VF610_CLK_ENET>, | ||
| 457 | <&clks VF610_CLK_ENET>, | ||
| 458 | <&clks VF610_CLK_ENET>; | ||
| 459 | clock-names = "ipg", "ahb", "ptp"; | ||
| 460 | status = "disabled"; | ||
| 461 | }; | ||
| 462 | }; | ||
| 463 | }; | ||
| 464 | }; | ||
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts index 877b33afa7ed..87f33310e2bc 100644 --- a/arch/arm/boot/dts/vt8500-bv07.dts +++ b/arch/arm/boot/dts/vt8500-bv07.dts | |||
| @@ -30,3 +30,7 @@ | |||
| 30 | }; | 30 | }; |
| 31 | }; | 31 | }; |
| 32 | }; | 32 | }; |
| 33 | |||
| 34 | &uart0 { | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi index 4a4b96f6827e..51d0e912c8f5 100644 --- a/arch/arm/boot/dts/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500.dtsi | |||
| @@ -11,6 +11,23 @@ | |||
| 11 | / { | 11 | / { |
| 12 | compatible = "via,vt8500"; | 12 | compatible = "via,vt8500"; |
| 13 | 13 | ||
| 14 | cpus { | ||
| 15 | #address-cells = <0>; | ||
| 16 | #size-cells = <0>; | ||
| 17 | |||
| 18 | cpu { | ||
| 19 | device_type = "cpu"; | ||
| 20 | compatible = "arm,arm926ej-s"; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | aliases { | ||
| 25 | serial0 = &uart0; | ||
| 26 | serial1 = &uart1; | ||
| 27 | serial2 = &uart2; | ||
| 28 | serial3 = &uart3; | ||
| 29 | }; | ||
| 30 | |||
| 14 | soc { | 31 | soc { |
| 15 | #address-cells = <1>; | 32 | #address-cells = <1>; |
| 16 | #size-cells = <1>; | 33 | #size-cells = <1>; |
| @@ -111,32 +128,36 @@ | |||
| 111 | reg = <0xd8050400 0x100>; | 128 | reg = <0xd8050400 0x100>; |
| 112 | }; | 129 | }; |
| 113 | 130 | ||
| 114 | uart@d8200000 { | 131 | uart0: serial@d8200000 { |
| 115 | compatible = "via,vt8500-uart"; | 132 | compatible = "via,vt8500-uart"; |
| 116 | reg = <0xd8200000 0x1040>; | 133 | reg = <0xd8200000 0x1040>; |
| 117 | interrupts = <32>; | 134 | interrupts = <32>; |
| 118 | clocks = <&clkuart0>; | 135 | clocks = <&clkuart0>; |
| 136 | status = "disabled"; | ||
| 119 | }; | 137 | }; |
| 120 | 138 | ||
| 121 | uart@d82b0000 { | 139 | uart1: serial@d82b0000 { |
| 122 | compatible = "via,vt8500-uart"; | 140 | compatible = "via,vt8500-uart"; |
| 123 | reg = <0xd82b0000 0x1040>; | 141 | reg = <0xd82b0000 0x1040>; |
| 124 | interrupts = <33>; | 142 | interrupts = <33>; |
| 125 | clocks = <&clkuart1>; | 143 | clocks = <&clkuart1>; |
| 144 | status = "disabled"; | ||
| 126 | }; | 145 | }; |
| 127 | 146 | ||
| 128 | uart@d8210000 { | 147 | uart2: serial@d8210000 { |
| 129 | compatible = "via,vt8500-uart"; | 148 | compatible = "via,vt8500-uart"; |
| 130 | reg = <0xd8210000 0x1040>; | 149 | reg = <0xd8210000 0x1040>; |
| 131 | interrupts = <47>; | 150 | interrupts = <47>; |
| 132 | clocks = <&clkuart2>; | 151 | clocks = <&clkuart2>; |
| 152 | status = "disabled"; | ||
| 133 | }; | 153 | }; |
| 134 | 154 | ||
| 135 | uart@d82c0000 { | 155 | uart3: serial@d82c0000 { |
| 136 | compatible = "via,vt8500-uart"; | 156 | compatible = "via,vt8500-uart"; |
| 137 | reg = <0xd82c0000 0x1040>; | 157 | reg = <0xd82c0000 0x1040>; |
| 138 | interrupts = <50>; | 158 | interrupts = <50>; |
| 139 | clocks = <&clkuart3>; | 159 | clocks = <&clkuart3>; |
| 160 | status = "disabled"; | ||
| 140 | }; | 161 | }; |
| 141 | 162 | ||
| 142 | rtc@d8100000 { | 163 | rtc@d8100000 { |
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts index edd2cec3d37f..e3e6b9eb09d0 100644 --- a/arch/arm/boot/dts/wm8505-ref.dts +++ b/arch/arm/boot/dts/wm8505-ref.dts | |||
| @@ -30,3 +30,7 @@ | |||
| 30 | }; | 30 | }; |
| 31 | }; | 31 | }; |
| 32 | }; | 32 | }; |
| 33 | |||
| 34 | &uart0 { | ||
| 35 | status = "okay"; | ||
| 36 | }; | ||
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index b2bf359e852f..a1a854b8a454 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi | |||
| @@ -12,11 +12,24 @@ | |||
| 12 | compatible = "wm,wm8505"; | 12 | compatible = "wm,wm8505"; |
| 13 | 13 | ||
| 14 | cpus { | 14 | cpus { |
| 15 | cpu@0 { | 15 | #address-cells = <0>; |
| 16 | compatible = "arm,arm926ejs"; | 16 | #size-cells = <0>; |
| 17 | |||
| 18 | cpu { | ||
| 19 | device_type = "cpu"; | ||
| 20 | compatible = "arm,arm926ej-s"; | ||
| 17 | }; | 21 | }; |
| 18 | }; | 22 | }; |
| 19 | 23 | ||
| 24 | aliases { | ||
| 25 | serial0 = &uart0; | ||
| 26 | serial1 = &uart1; | ||
| 27 | serial2 = &uart2; | ||
| 28 | serial3 = &uart3; | ||
| 29 | serial4 = &uart4; | ||
| 30 | serial5 = &uart5; | ||
| 31 | }; | ||
| 32 | |||
| 20 | soc { | 33 | soc { |
| 21 | #address-cells = <1>; | 34 | #address-cells = <1>; |
| 22 | #size-cells = <1>; | 35 | #size-cells = <1>; |
| @@ -68,6 +81,13 @@ | |||
| 68 | clock-frequency = <25000000>; | 81 | clock-frequency = <25000000>; |
| 69 | }; | 82 | }; |
| 70 | 83 | ||
| 84 | plla: plla { | ||
| 85 | #clock-cells = <0>; | ||
| 86 | compatible = "via,vt8500-pll-clock"; | ||
| 87 | clocks = <&ref25>; | ||
| 88 | reg = <0x200>; | ||
| 89 | }; | ||
| 90 | |||
| 71 | pllb: pllb { | 91 | pllb: pllb { |
| 72 | #clock-cells = <0>; | 92 | #clock-cells = <0>; |
| 73 | compatible = "via,vt8500-pll-clock"; | 93 | compatible = "via,vt8500-pll-clock"; |
| @@ -75,6 +95,48 @@ | |||
| 75 | reg = <0x204>; | 95 | reg = <0x204>; |
| 76 | }; | 96 | }; |
| 77 | 97 | ||
| 98 | pllc: pllc { | ||
| 99 | #clock-cells = <0>; | ||
| 100 | compatible = "via,vt8500-pll-clock"; | ||
| 101 | clocks = <&ref25>; | ||
| 102 | reg = <0x208>; | ||
| 103 | }; | ||
| 104 | |||
| 105 | plld: plld { | ||
| 106 | #clock-cells = <0>; | ||
| 107 | compatible = "via,vt8500-pll-clock"; | ||
| 108 | clocks = <&ref25>; | ||
| 109 | reg = <0x20c>; | ||
| 110 | }; | ||
| 111 | |||
| 112 | clkarm: arm { | ||
| 113 | #clock-cells = <0>; | ||
| 114 | compatible = "via,vt8500-device-clock"; | ||
| 115 | clocks = <&plla>; | ||
| 116 | divisor-reg = <0x300>; | ||
| 117 | }; | ||
| 118 | |||
| 119 | clkahb: ahb { | ||
| 120 | #clock-cells = <0>; | ||
| 121 | compatible = "via,vt8500-device-clock"; | ||
| 122 | clocks = <&pllb>; | ||
| 123 | divisor-reg = <0x304>; | ||
| 124 | }; | ||
| 125 | |||
| 126 | clkapb: apb { | ||
| 127 | #clock-cells = <0>; | ||
| 128 | compatible = "via,vt8500-device-clock"; | ||
| 129 | clocks = <&pllb>; | ||
| 130 | divisor-reg = <0x350>; | ||
| 131 | }; | ||
| 132 | |||
| 133 | clkddr: ddr { | ||
| 134 | #clock-cells = <0>; | ||
| 135 | compatible = "via,vt8500-device-clock"; | ||
| 136 | clocks = <&plld>; | ||
| 137 | divisor-reg = <0x310>; | ||
| 138 | }; | ||
| 139 | |||
| 78 | clkuart0: uart0 { | 140 | clkuart0: uart0 { |
| 79 | #clock-cells = <0>; | 141 | #clock-cells = <0>; |
| 80 | compatible = "via,vt8500-device-clock"; | 142 | compatible = "via,vt8500-device-clock"; |
| @@ -163,46 +225,52 @@ | |||
| 163 | reg = <0xd8050400 0x100>; | 225 | reg = <0xd8050400 0x100>; |
| 164 | }; | 226 | }; |
| 165 | 227 | ||
| 166 | uart@d8200000 { | 228 | uart0: serial@d8200000 { |
| 167 | compatible = "via,vt8500-uart"; | 229 | compatible = "via,vt8500-uart"; |
| 168 | reg = <0xd8200000 0x1040>; | 230 | reg = <0xd8200000 0x1040>; |
| 169 | interrupts = <32>; | 231 | interrupts = <32>; |
| 170 | clocks = <&clkuart0>; | 232 | clocks = <&clkuart0>; |
| 233 | status = "disabled"; | ||
| 171 | }; | 234 | }; |
| 172 | 235 | ||
| 173 | uart@d82b0000 { | 236 | uart1: serial@d82b0000 { |
| 174 | compatible = "via,vt8500-uart"; | 237 | compatible = "via,vt8500-uart"; |
| 175 | reg = <0xd82b0000 0x1040>; | 238 | reg = <0xd82b0000 0x1040>; |
| 176 | interrupts = <33>; | 239 | interrupts = <33>; |
| 177 | clocks = <&clkuart1>; | 240 | clocks = <&clkuart1>; |
| 241 | status = "disabled"; | ||
| 178 | }; | 242 | }; |
| 179 | 243 | ||
| 180 | uart@d8210000 { | 244 | uart2: serial@d8210000 { |
| 181 | compatible = "via,vt8500-uart"; | 245 | compatible = "via,vt8500-uart"; |
| 182 | reg = <0xd8210000 0x1040>; | 246 | reg = <0xd8210000 0x1040>; |
| 183 | interrupts = <47>; | 247 | interrupts = <47>; |
| 184 | clocks = <&clkuart2>; | 248 | clocks = <&clkuart2>; |
| 249 | status = "disabled"; | ||
| 185 | }; | 250 | }; |
| 186 | 251 | ||
| 187 | uart@d82c0000 { | 252 | uart3: serial@d82c0000 { |
| 188 | compatible = "via,vt8500-uart"; | 253 | compatible = "via,vt8500-uart"; |
| 189 | reg = <0xd82c0000 0x1040>; | 254 | reg = <0xd82c0000 0x1040>; |
| 190 | interrupts = <50>; | 255 | interrupts = <50>; |
| 191 | clocks = <&clkuart3>; | 256 | clocks = <&clkuart3>; |
| 257 | status = "disabled"; | ||
| 192 | }; | 258 | }; |
| 193 | 259 | ||
| 194 | uart@d8370000 { | 260 | uart4: serial@d8370000 { |
| 195 | compatible = "via,vt8500-uart"; | 261 | compatible = "via,vt8500-uart"; |
| 196 | reg = <0xd8370000 0x1040>; | 262 | reg = <0xd8370000 0x1040>; |
| 197 | interrupts = <31>; | 263 | interrupts = <31>; |
| 198 | clocks = <&clkuart4>; | 264 | clocks = <&clkuart4>; |
| 265 | status = "disabled"; | ||
| 199 | }; | 266 | }; |
| 200 | 267 | ||
| 201 | uart@d8380000 { | 268 | uart5: serial@d8380000 { |
| 202 | compatible = "via,vt8500-uart"; | 269 | compatible = "via,vt8500-uart"; |
| 203 | reg = <0xd8380000 0x1040>; | 270 | reg = <0xd8380000 0x1040>; |
| 204 | interrupts = <30>; | 271 | interrupts = <30>; |
| 205 | clocks = <&clkuart5>; | 272 | clocks = <&clkuart5>; |
| 273 | status = "disabled"; | ||
| 206 | }; | 274 | }; |
| 207 | 275 | ||
| 208 | rtc@d8100000 { | 276 | rtc@d8100000 { |
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts index 61671a0d9ede..dd0d1b602388 100644 --- a/arch/arm/boot/dts/wm8650-mid.dts +++ b/arch/arm/boot/dts/wm8650-mid.dts | |||
| @@ -32,3 +32,6 @@ | |||
| 32 | }; | 32 | }; |
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | &uart0 { | ||
| 36 | status = "okay"; | ||
| 37 | }; | ||
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi index dd8464eeb40d..7525982262ac 100644 --- a/arch/arm/boot/dts/wm8650.dtsi +++ b/arch/arm/boot/dts/wm8650.dtsi | |||
| @@ -11,6 +11,21 @@ | |||
| 11 | / { | 11 | / { |
| 12 | compatible = "wm,wm8650"; | 12 | compatible = "wm,wm8650"; |
| 13 | 13 | ||
| 14 | cpus { | ||
| 15 | #address-cells = <0>; | ||
| 16 | #size-cells = <0>; | ||
| 17 | |||
| 18 | cpu { | ||
| 19 | device_type = "cpu"; | ||
| 20 | compatible = "arm,arm926ej-s"; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | aliases { | ||
| 25 | serial0 = &uart0; | ||
| 26 | serial1 = &uart1; | ||
| 27 | }; | ||
| 28 | |||
| 14 | soc { | 29 | soc { |
| 15 | #address-cells = <1>; | 30 | #address-cells = <1>; |
| 16 | #size-cells = <1>; | 31 | #size-cells = <1>; |
| @@ -77,6 +92,55 @@ | |||
| 77 | reg = <0x204>; | 92 | reg = <0x204>; |
| 78 | }; | 93 | }; |
| 79 | 94 | ||
| 95 | pllc: pllc { | ||
| 96 | #clock-cells = <0>; | ||
| 97 | compatible = "wm,wm8650-pll-clock"; | ||
| 98 | clocks = <&ref25>; | ||
| 99 | reg = <0x208>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | plld: plld { | ||
| 103 | #clock-cells = <0>; | ||
| 104 | compatible = "wm,wm8650-pll-clock"; | ||
| 105 | clocks = <&ref25>; | ||
| 106 | reg = <0x20c>; | ||
| 107 | }; | ||
| 108 | |||
| 109 | plle: plle { | ||
| 110 | #clock-cells = <0>; | ||
| 111 | compatible = "wm,wm8650-pll-clock"; | ||
| 112 | clocks = <&ref25>; | ||
| 113 | reg = <0x210>; | ||
| 114 | }; | ||
| 115 | |||
| 116 | clkarm: arm { | ||
| 117 | #clock-cells = <0>; | ||
| 118 | compatible = "via,vt8500-device-clock"; | ||
| 119 | clocks = <&plla>; | ||
| 120 | divisor-reg = <0x300>; | ||
| 121 | }; | ||
| 122 | |||
| 123 | clkahb: ahb { | ||
| 124 | #clock-cells = <0>; | ||
| 125 | compatible = "via,vt8500-device-clock"; | ||
| 126 | clocks = <&pllb>; | ||
| 127 | divisor-reg = <0x304>; | ||
| 128 | }; | ||
| 129 | |||
| 130 | clkapb: apb { | ||
| 131 | #clock-cells = <0>; | ||
| 132 | compatible = "via,vt8500-device-clock"; | ||
| 133 | clocks = <&pllb>; | ||
| 134 | divisor-reg = <0x320>; | ||
| 135 | }; | ||
| 136 | |||
| 137 | clkddr: ddr { | ||
| 138 | #clock-cells = <0>; | ||
| 139 | compatible = "via,vt8500-device-clock"; | ||
| 140 | clocks = <&plld>; | ||
| 141 | divisor-reg = <0x310>; | ||
| 142 | }; | ||
| 143 | |||
| 80 | clkuart0: uart0 { | 144 | clkuart0: uart0 { |
| 81 | #clock-cells = <0>; | 145 | #clock-cells = <0>; |
| 82 | compatible = "via,vt8500-device-clock"; | 146 | compatible = "via,vt8500-device-clock"; |
| @@ -93,14 +157,7 @@ | |||
| 93 | enable-bit = <2>; | 157 | enable-bit = <2>; |
| 94 | }; | 158 | }; |
| 95 | 159 | ||
| 96 | arm: arm { | 160 | clksdhc: sdhc { |
| 97 | #clock-cells = <0>; | ||
| 98 | compatible = "via,vt8500-device-clock"; | ||
| 99 | clocks = <&plla>; | ||
| 100 | divisor-reg = <0x300>; | ||
| 101 | }; | ||
| 102 | |||
| 103 | sdhc: sdhc { | ||
| 104 | #clock-cells = <0>; | 161 | #clock-cells = <0>; |
| 105 | compatible = "via,vt8500-device-clock"; | 162 | compatible = "via,vt8500-device-clock"; |
| 106 | clocks = <&pllb>; | 163 | clocks = <&pllb>; |
| @@ -140,18 +197,20 @@ | |||
| 140 | reg = <0xd8050400 0x100>; | 197 | reg = <0xd8050400 0x100>; |
| 141 | }; | 198 | }; |
| 142 | 199 | ||
| 143 | uart@d8200000 { | 200 | uart0: serial@d8200000 { |
| 144 | compatible = "via,vt8500-uart"; | 201 | compatible = "via,vt8500-uart"; |
| 145 | reg = <0xd8200000 0x1040>; | 202 | reg = <0xd8200000 0x1040>; |
| 146 | interrupts = <32>; | 203 | interrupts = <32>; |
| 147 | clocks = <&clkuart0>; | 204 | clocks = <&clkuart0>; |
| 205 | status = "disabled"; | ||
| 148 | }; | 206 | }; |
| 149 | 207 | ||
| 150 | uart@d82b0000 { | 208 | uart1: serial@d82b0000 { |
| 151 | compatible = "via,vt8500-uart"; | 209 | compatible = "via,vt8500-uart"; |
| 152 | reg = <0xd82b0000 0x1040>; | 210 | reg = <0xd82b0000 0x1040>; |
| 153 | interrupts = <33>; | 211 | interrupts = <33>; |
| 154 | clocks = <&clkuart1>; | 212 | clocks = <&clkuart1>; |
| 213 | status = "disabled"; | ||
| 155 | }; | 214 | }; |
| 156 | 215 | ||
| 157 | rtc@d8100000 { | 216 | rtc@d8100000 { |
diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts new file mode 100644 index 000000000000..37e4a408bf39 --- /dev/null +++ b/arch/arm/boot/dts/wm8750-apc8750.dts | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /* | ||
| 2 | * wm8750-apc8750.dts | ||
| 3 | * - Device tree file for VIA APC8750 | ||
| 4 | * | ||
| 5 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | /include/ "wm8750.dtsi" | ||
| 12 | |||
| 13 | / { | ||
| 14 | model = "VIA APC8750"; | ||
| 15 | }; | ||
| 16 | |||
| 17 | &pinctrl { | ||
| 18 | pinctrl-names = "default"; | ||
| 19 | pinctrl-0 = <&i2c>; | ||
| 20 | |||
| 21 | i2c: i2c { | ||
| 22 | wm,pins = <168 169 170 171>; | ||
| 23 | wm,function = <2>; /* alt */ | ||
| 24 | wm,pull = <2>; /* pull-up */ | ||
| 25 | }; | ||
| 26 | }; | ||
| 27 | |||
| 28 | &uart0 { | ||
| 29 | status = "okay"; | ||
| 30 | }; | ||
diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi new file mode 100644 index 000000000000..557a9c2ace49 --- /dev/null +++ b/arch/arm/boot/dts/wm8750.dtsi | |||
| @@ -0,0 +1,347 @@ | |||
| 1 | /* | ||
| 2 | * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later | ||
| 7 | */ | ||
| 8 | |||
| 9 | /include/ "skeleton.dtsi" | ||
| 10 | |||
| 11 | / { | ||
| 12 | compatible = "wm,wm8750"; | ||
| 13 | |||
| 14 | cpus { | ||
| 15 | #address-cells = <0>; | ||
| 16 | #size-cells = <0>; | ||
| 17 | |||
| 18 | cpu { | ||
| 19 | device_type = "cpu"; | ||
| 20 | compatible = "arm,arm1176ej-s"; | ||
| 21 | }; | ||
| 22 | }; | ||
| 23 | |||
| 24 | aliases { | ||
| 25 | serial0 = &uart0; | ||
| 26 | serial1 = &uart1; | ||
| 27 | serial2 = &uart2; | ||
| 28 | serial3 = &uart3; | ||
| 29 | serial4 = &uart4; | ||
| 30 | serial5 = &uart5; | ||
| 31 | i2c0 = &i2c_0; | ||
| 32 | i2c1 = &i2c_1; | ||
| 33 | }; | ||
| 34 | |||
| 35 | soc { | ||
| 36 | #address-cells = <1>; | ||
| 37 | #size-cells = <1>; | ||
| 38 | compatible = "simple-bus"; | ||
| 39 | ranges; | ||
| 40 | interrupt-parent = <&intc0>; | ||
| 41 | |||
| 42 | intc0: interrupt-controller@d8140000 { | ||
| 43 | compatible = "via,vt8500-intc"; | ||
| 44 | interrupt-controller; | ||
| 45 | reg = <0xd8140000 0x10000>; | ||
| 46 | #interrupt-cells = <1>; | ||
| 47 | }; | ||
| 48 | |||
| 49 | /* Secondary IC cascaded to intc0 */ | ||
| 50 | intc1: interrupt-controller@d8150000 { | ||
| 51 | compatible = "via,vt8500-intc"; | ||
| 52 | interrupt-controller; | ||
| 53 | #interrupt-cells = <1>; | ||
| 54 | reg = <0xD8150000 0x10000>; | ||
| 55 | interrupts = <56 57 58 59 60 61 62 63>; | ||
| 56 | }; | ||
| 57 | |||
| 58 | pinctrl: pinctrl@d8110000 { | ||
| 59 | compatible = "wm,wm8750-pinctrl"; | ||
| 60 | reg = <0xd8110000 0x10000>; | ||
| 61 | interrupt-controller; | ||
| 62 | #interrupt-cells = <2>; | ||
| 63 | gpio-controller; | ||
| 64 | #gpio-cells = <2>; | ||
| 65 | }; | ||
| 66 | |||
| 67 | pmc@d8130000 { | ||
| 68 | compatible = "via,vt8500-pmc"; | ||
| 69 | reg = <0xd8130000 0x1000>; | ||
| 70 | |||
| 71 | clocks { | ||
| 72 | #address-cells = <1>; | ||
| 73 | #size-cells = <0>; | ||
| 74 | |||
| 75 | ref24: ref24M { | ||
| 76 | #clock-cells = <0>; | ||
| 77 | compatible = "fixed-clock"; | ||
| 78 | clock-frequency = <24000000>; | ||
| 79 | }; | ||
| 80 | |||
| 81 | ref25: ref25M { | ||
| 82 | #clock-cells = <0>; | ||
| 83 | compatible = "fixed-clock"; | ||
| 84 | clock-frequency = <25000000>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | plla: plla { | ||
| 88 | #clock-cells = <0>; | ||
| 89 | compatible = "wm,wm8750-pll-clock"; | ||
| 90 | clocks = <&ref25>; | ||
| 91 | reg = <0x200>; | ||
| 92 | }; | ||
| 93 | |||
| 94 | pllb: pllb { | ||
| 95 | #clock-cells = <0>; | ||
| 96 | compatible = "wm,wm8750-pll-clock"; | ||
| 97 | clocks = <&ref25>; | ||
| 98 | reg = <0x204>; | ||
| 99 | }; | ||
| 100 | |||
| 101 | pllc: pllc { | ||
| 102 | #clock-cells = <0>; | ||
| 103 | compatible = "wm,wm8750-pll-clock"; | ||
| 104 | clocks = <&ref25>; | ||
| 105 | reg = <0x208>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | plld: plld { | ||
| 109 | #clock-cells = <0>; | ||
| 110 | compatible = "wm,wm8750-pll-clock"; | ||
| 111 | clocks = <&ref25>; | ||
| 112 | reg = <0x20C>; | ||
| 113 | }; | ||
| 114 | |||
| 115 | plle: plle { | ||
| 116 | #clock-cells = <0>; | ||
| 117 | compatible = "wm,wm8750-pll-clock"; | ||
| 118 | clocks = <&ref25>; | ||
| 119 | reg = <0x210>; | ||
| 120 | }; | ||
| 121 | |||
| 122 | clkarm: arm { | ||
| 123 | #clock-cells = <0>; | ||
| 124 | compatible = "via,vt8500-device-clock"; | ||
| 125 | clocks = <&plla>; | ||
| 126 | divisor-reg = <0x300>; | ||
| 127 | }; | ||
| 128 | |||
| 129 | clkahb: ahb { | ||
| 130 | #clock-cells = <0>; | ||
| 131 | compatible = "via,vt8500-device-clock"; | ||
| 132 | clocks = <&pllb>; | ||
| 133 | divisor-reg = <0x304>; | ||
| 134 | }; | ||
| 135 | |||
| 136 | clkapb: apb { | ||
| 137 | #clock-cells = <0>; | ||
| 138 | compatible = "via,vt8500-device-clock"; | ||
| 139 | clocks = <&pllb>; | ||
| 140 | divisor-reg = <0x320>; | ||
| 141 | }; | ||
| 142 | |||
| 143 | clkddr: ddr { | ||
| 144 | #clock-cells = <0>; | ||
| 145 | compatible = "via,vt8500-device-clock"; | ||
| 146 | clocks = <&plld>; | ||
| 147 | divisor-reg = <0x310>; | ||
| 148 | }; | ||
| 149 | |||
| 150 | clkuart0: uart0 { | ||
| 151 | #clock-cells = <0>; | ||
| 152 | compatible = "via,vt8500-device-clock"; | ||
| 153 | clocks = <&ref24>; | ||
| 154 | enable-reg = <0x254>; | ||
| 155 | enable-bit = <24>; | ||
| 156 | }; | ||
| 157 | |||
| 158 | clkuart1: uart1 { | ||
| 159 | #clock-cells = <0>; | ||
| 160 | compatible = "via,vt8500-device-clock"; | ||
| 161 | clocks = <&ref24>; | ||
| 162 | enable-reg = <0x254>; | ||
| 163 | enable-bit = <25>; | ||
| 164 | }; | ||
| 165 | |||
| 166 | clkuart2: uart2 { | ||
| 167 | #clock-cells = <0>; | ||
| 168 | compatible = "via,vt8500-device-clock"; | ||
| 169 | clocks = <&ref24>; | ||
| 170 | enable-reg = <0x254>; | ||
| 171 | enable-bit = <26>; | ||
| 172 | }; | ||
| 173 | |||
| 174 | clkuart3: uart3 { | ||
| 175 | #clock-cells = <0>; | ||
| 176 | compatible = "via,vt8500-device-clock"; | ||
| 177 | clocks = <&ref24>; | ||
| 178 | enable-reg = <0x254>; | ||
| 179 | enable-bit = <27>; | ||
| 180 | }; | ||
| 181 | |||
| 182 | clkuart4: uart4 { | ||
| 183 | #clock-cells = <0>; | ||
| 184 | compatible = "via,vt8500-device-clock"; | ||
| 185 | clocks = <&ref24>; | ||
| 186 | enable-reg = <0x254>; | ||
| 187 | enable-bit = <28>; | ||
| 188 | }; | ||
| 189 | |||
| 190 | clkuart5: uart5 { | ||
| 191 | #clock-cells = <0>; | ||
| 192 | compatible = "via,vt8500-device-clock"; | ||
| 193 | clocks = <&ref24>; | ||
| 194 | enable-reg = <0x254>; | ||
| 195 | enable-bit = <29>; | ||
| 196 | }; | ||
| 197 | |||
| 198 | clkpwm: pwm { | ||
| 199 | #clock-cells = <0>; | ||
| 200 | compatible = "via,vt8500-device-clock"; | ||
| 201 | clocks = <&pllb>; | ||
| 202 | divisor-reg = <0x350>; | ||
| 203 | enable-reg = <0x250>; | ||
| 204 | enable-bit = <17>; | ||
| 205 | }; | ||
| 206 | |||
| 207 | clksdhc: sdhc { | ||
| 208 | #clock-cells = <0>; | ||
| 209 | compatible = "via,vt8500-device-clock"; | ||
| 210 | clocks = <&pllb>; | ||
| 211 | divisor-reg = <0x330>; | ||
| 212 | divisor-mask = <0x3f>; | ||
| 213 | enable-reg = <0x250>; | ||
| 214 | enable-bit = <0>; | ||
| 215 | }; | ||
| 216 | |||
| 217 | clki2c0: i2c0clk { | ||
| 218 | #clock-cells = <0>; | ||
| 219 | compatible = "via,vt8500-device-clock"; | ||
| 220 | clocks = <&pllb>; | ||
| 221 | divisor-reg = <0x3A0>; | ||
| 222 | enable-reg = <0x250>; | ||
| 223 | enable-bit = <8>; | ||
| 224 | }; | ||
| 225 | |||
| 226 | clki2c1: i2c1clk { | ||
| 227 | #clock-cells = <0>; | ||
| 228 | compatible = "via,vt8500-device-clock"; | ||
| 229 | clocks = <&pllb>; | ||
| 230 | divisor-reg = <0x3A4>; | ||
| 231 | enable-reg = <0x250>; | ||
| 232 | enable-bit = <9>; | ||
| 233 | }; | ||
| 234 | }; | ||
| 235 | }; | ||
| 236 | |||
| 237 | pwm: pwm@d8220000 { | ||
| 238 | #pwm-cells = <3>; | ||
| 239 | compatible = "via,vt8500-pwm"; | ||
| 240 | reg = <0xd8220000 0x100>; | ||
| 241 | clocks = <&clkpwm>; | ||
| 242 | }; | ||
| 243 | |||
| 244 | timer@d8130100 { | ||
| 245 | compatible = "via,vt8500-timer"; | ||
| 246 | reg = <0xd8130100 0x28>; | ||
| 247 | interrupts = <36>; | ||
| 248 | }; | ||
| 249 | |||
| 250 | ehci@d8007900 { | ||
| 251 | compatible = "via,vt8500-ehci"; | ||
| 252 | reg = <0xd8007900 0x200>; | ||
| 253 | interrupts = <26>; | ||
| 254 | }; | ||
| 255 | |||
| 256 | uhci@d8007b00 { | ||
| 257 | compatible = "platform-uhci"; | ||
| 258 | reg = <0xd8007b00 0x200>; | ||
| 259 | interrupts = <26>; | ||
| 260 | }; | ||
| 261 | |||
| 262 | uhci@d8008d00 { | ||
| 263 | compatible = "platform-uhci"; | ||
| 264 | reg = <0xd8008d00 0x200>; | ||
| 265 | interrupts = <26>; | ||
| 266 | }; | ||
| 267 | |||
| 268 | uart0: serial@d8200000 { | ||
| 269 | compatible = "via,vt8500-uart"; | ||
| 270 | reg = <0xd8200000 0x1040>; | ||
| 271 | interrupts = <32>; | ||
| 272 | clocks = <&clkuart0>; | ||
| 273 | status = "disabled"; | ||
| 274 | }; | ||
| 275 | |||
| 276 | uart1: serial@d82b0000 { | ||
| 277 | compatible = "via,vt8500-uart"; | ||
| 278 | reg = <0xd82b0000 0x1040>; | ||
| 279 | interrupts = <33>; | ||
| 280 | clocks = <&clkuart1>; | ||
| 281 | status = "disabled"; | ||
| 282 | }; | ||
| 283 | |||
| 284 | uart2: serial@d8210000 { | ||
| 285 | compatible = "via,vt8500-uart"; | ||
| 286 | reg = <0xd8210000 0x1040>; | ||
| 287 | interrupts = <47>; | ||
| 288 | clocks = <&clkuart2>; | ||
| 289 | status = "disabled"; | ||
| 290 | }; | ||
| 291 | |||
| 292 | uart3: serial@d82c0000 { | ||
| 293 | compatible = "via,vt8500-uart"; | ||
| 294 | reg = <0xd82c0000 0x1040>; | ||
| 295 | interrupts = <50>; | ||
| 296 | clocks = <&clkuart3>; | ||
| 297 | status = "disabled"; | ||
| 298 | }; | ||
| 299 | |||
| 300 | uart4: serial@d8370000 { | ||
| 301 | compatible = "via,vt8500-uart"; | ||
| 302 | reg = <0xd8370000 0x1040>; | ||
| 303 | interrupts = <30>; | ||
| 304 | clocks = <&clkuart4>; | ||
| 305 | status = "disabled"; | ||
| 306 | }; | ||
| 307 | |||
| 308 | uart5: serial@d8380000 { | ||
| 309 | compatible = "via,vt8500-uart"; | ||
| 310 | reg = <0xd8380000 0x1040>; | ||
| 311 | interrupts = <43>; | ||
| 312 | clocks = <&clkuart5>; | ||
| 313 | status = "disabled"; | ||
| 314 | }; | ||
| 315 | |||
| 316 | rtc@d8100000 { | ||
| 317 | compatible = "via,vt8500-rtc"; | ||
| 318 | reg = <0xd8100000 0x10000>; | ||
| 319 | interrupts = <48>; | ||
| 320 | }; | ||
| 321 | |||
| 322 | sdhc@d800a000 { | ||
| 323 | compatible = "wm,wm8505-sdhc"; | ||
| 324 | reg = <0xd800a000 0x1000>; | ||
| 325 | interrupts = <20 21>; | ||
| 326 | clocks = <&clksdhc>; | ||
| 327 | bus-width = <4>; | ||
| 328 | sdon-inverted; | ||
| 329 | }; | ||
| 330 | |||
| 331 | i2c_0: i2c@d8280000 { | ||
| 332 | compatible = "wm,wm8505-i2c"; | ||
| 333 | reg = <0xd8280000 0x1000>; | ||
| 334 | interrupts = <19>; | ||
| 335 | clocks = <&clki2c0>; | ||
| 336 | clock-frequency = <400000>; | ||
| 337 | }; | ||
| 338 | |||
| 339 | i2c_1: i2c@d8320000 { | ||
| 340 | compatible = "wm,wm8505-i2c"; | ||
| 341 | reg = <0xd8320000 0x1000>; | ||
| 342 | interrupts = <18>; | ||
| 343 | clocks = <&clki2c1>; | ||
| 344 | clock-frequency = <400000>; | ||
| 345 | }; | ||
| 346 | }; | ||
| 347 | }; | ||
diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts index 32d22532cd6c..90e913fb64be 100644 --- a/arch/arm/boot/dts/wm8850-w70v2.dts +++ b/arch/arm/boot/dts/wm8850-w70v2.dts | |||
| @@ -41,3 +41,7 @@ | |||
| 41 | }; | 41 | }; |
| 42 | }; | 42 | }; |
| 43 | }; | 43 | }; |
| 44 | |||
| 45 | &uart0 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi index fc790d0aee66..d98386dd2882 100644 --- a/arch/arm/boot/dts/wm8850.dtsi +++ b/arch/arm/boot/dts/wm8850.dtsi | |||
| @@ -11,6 +11,17 @@ | |||
| 11 | / { | 11 | / { |
| 12 | compatible = "wm,wm8850"; | 12 | compatible = "wm,wm8850"; |
| 13 | 13 | ||
| 14 | cpus { | ||
| 15 | #address-cells = <1>; | ||
| 16 | #size-cells = <0>; | ||
| 17 | |||
| 18 | cpu@0 { | ||
| 19 | device_type = "cpu"; | ||
| 20 | compatible = "arm,cortex-a9"; | ||
| 21 | reg = <0x0>; | ||
| 22 | }; | ||
| 23 | }; | ||
| 24 | |||
| 14 | aliases { | 25 | aliases { |
| 15 | serial0 = &uart0; | 26 | serial0 = &uart0; |
| 16 | serial1 = &uart1; | 27 | serial1 = &uart1; |
| @@ -72,18 +83,81 @@ | |||
| 72 | 83 | ||
| 73 | plla: plla { | 84 | plla: plla { |
| 74 | #clock-cells = <0>; | 85 | #clock-cells = <0>; |
| 75 | compatible = "wm,wm8750-pll-clock"; | 86 | compatible = "wm,wm8850-pll-clock"; |
| 76 | clocks = <&ref25>; | 87 | clocks = <&ref24>; |
| 77 | reg = <0x200>; | 88 | reg = <0x200>; |
| 78 | }; | 89 | }; |
| 79 | 90 | ||
| 80 | pllb: pllb { | 91 | pllb: pllb { |
| 81 | #clock-cells = <0>; | 92 | #clock-cells = <0>; |
| 82 | compatible = "wm,wm8750-pll-clock"; | 93 | compatible = "wm,wm8850-pll-clock"; |
| 83 | clocks = <&ref25>; | 94 | clocks = <&ref24>; |
| 84 | reg = <0x204>; | 95 | reg = <0x204>; |
| 85 | }; | 96 | }; |
| 86 | 97 | ||
| 98 | pllc: pllc { | ||
| 99 | #clock-cells = <0>; | ||
| 100 | compatible = "wm,wm8850-pll-clock"; | ||
| 101 | clocks = <&ref24>; | ||
| 102 | reg = <0x208>; | ||
| 103 | }; | ||
| 104 | |||
| 105 | plld: plld { | ||
| 106 | #clock-cells = <0>; | ||
| 107 | compatible = "wm,wm8850-pll-clock"; | ||
| 108 | clocks = <&ref24>; | ||
| 109 | reg = <0x20c>; | ||
| 110 | }; | ||
| 111 | |||
| 112 | plle: plle { | ||
| 113 | #clock-cells = <0>; | ||
| 114 | compatible = "wm,wm8850-pll-clock"; | ||
| 115 | clocks = <&ref24>; | ||
| 116 | reg = <0x210>; | ||
| 117 | }; | ||
| 118 | |||
| 119 | pllf: pllf { | ||
| 120 | #clock-cells = <0>; | ||
| 121 | compatible = "wm,wm8850-pll-clock"; | ||
| 122 | clocks = <&ref24>; | ||
| 123 | reg = <0x214>; | ||
| 124 | }; | ||
| 125 | |||
| 126 | pllg: pllg { | ||
| 127 | #clock-cells = <0>; | ||
| 128 | compatible = "wm,wm8850-pll-clock"; | ||
| 129 | clocks = <&ref24>; | ||
| 130 | reg = <0x218>; | ||
| 131 | }; | ||
| 132 | |||
| 133 | clkarm: arm { | ||
| 134 | #clock-cells = <0>; | ||
| 135 | compatible = "via,vt8500-device-clock"; | ||
| 136 | clocks = <&plla>; | ||
| 137 | divisor-reg = <0x300>; | ||
| 138 | }; | ||
| 139 | |||
| 140 | clkahb: ahb { | ||
| 141 | #clock-cells = <0>; | ||
| 142 | compatible = "via,vt8500-device-clock"; | ||
| 143 | clocks = <&pllb>; | ||
| 144 | divisor-reg = <0x304>; | ||
| 145 | }; | ||
| 146 | |||
| 147 | clkapb: apb { | ||
| 148 | #clock-cells = <0>; | ||
| 149 | compatible = "via,vt8500-device-clock"; | ||
| 150 | clocks = <&pllb>; | ||
| 151 | divisor-reg = <0x320>; | ||
| 152 | }; | ||
| 153 | |||
| 154 | clkddr: ddr { | ||
| 155 | #clock-cells = <0>; | ||
| 156 | compatible = "via,vt8500-device-clock"; | ||
| 157 | clocks = <&plld>; | ||
| 158 | divisor-reg = <0x310>; | ||
| 159 | }; | ||
| 160 | |||
| 87 | clkuart0: uart0 { | 161 | clkuart0: uart0 { |
| 88 | #clock-cells = <0>; | 162 | #clock-cells = <0>; |
| 89 | compatible = "via,vt8500-device-clock"; | 163 | compatible = "via,vt8500-device-clock"; |
| @@ -178,32 +252,36 @@ | |||
| 178 | interrupts = <26>; | 252 | interrupts = <26>; |
| 179 | }; | 253 | }; |
| 180 | 254 | ||
| 181 | uart0: uart@d8200000 { | 255 | uart0: serial@d8200000 { |
| 182 | compatible = "via,vt8500-uart"; | 256 | compatible = "via,vt8500-uart"; |
| 183 | reg = <0xd8200000 0x1040>; | 257 | reg = <0xd8200000 0x1040>; |
| 184 | interrupts = <32>; | 258 | interrupts = <32>; |
| 185 | clocks = <&clkuart0>; | 259 | clocks = <&clkuart0>; |
| 260 | status = "disabled"; | ||
| 186 | }; | 261 | }; |
| 187 | 262 | ||
| 188 | uart1: uart@d82b0000 { | 263 | uart1: serial@d82b0000 { |
| 189 | compatible = "via,vt8500-uart"; | 264 | compatible = "via,vt8500-uart"; |
| 190 | reg = <0xd82b0000 0x1040>; | 265 | reg = <0xd82b0000 0x1040>; |
| 191 | interrupts = <33>; | 266 | interrupts = <33>; |
| 192 | clocks = <&clkuart1>; | 267 | clocks = <&clkuart1>; |
| 268 | status = "disabled"; | ||
| 193 | }; | 269 | }; |
| 194 | 270 | ||
| 195 | uart2: uart@d8210000 { | 271 | uart2: serial@d8210000 { |
| 196 | compatible = "via,vt8500-uart"; | 272 | compatible = "via,vt8500-uart"; |
| 197 | reg = <0xd8210000 0x1040>; | 273 | reg = <0xd8210000 0x1040>; |
| 198 | interrupts = <47>; | 274 | interrupts = <47>; |
| 199 | clocks = <&clkuart2>; | 275 | clocks = <&clkuart2>; |
| 276 | status = "disabled"; | ||
| 200 | }; | 277 | }; |
| 201 | 278 | ||
| 202 | uart3: uart@d82c0000 { | 279 | uart3: serial@d82c0000 { |
| 203 | compatible = "via,vt8500-uart"; | 280 | compatible = "via,vt8500-uart"; |
| 204 | reg = <0xd82c0000 0x1040>; | 281 | reg = <0xd82c0000 0x1040>; |
| 205 | interrupts = <50>; | 282 | interrupts = <50>; |
| 206 | clocks = <&clkuart3>; | 283 | clocks = <&clkuart3>; |
| 284 | status = "disabled"; | ||
| 207 | }; | 285 | }; |
| 208 | 286 | ||
| 209 | rtc@d8100000 { | 287 | rtc@d8100000 { |
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 0dbee2c23905..6f54a64850eb 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi | |||
| @@ -49,6 +49,7 @@ | |||
| 49 | 49 | ||
| 50 | uart0: uart@e0000000 { | 50 | uart0: uart@e0000000 { |
| 51 | compatible = "xlnx,xuartps"; | 51 | compatible = "xlnx,xuartps"; |
| 52 | status = "disabled"; | ||
| 52 | clocks = <&clkc 23>, <&clkc 40>; | 53 | clocks = <&clkc 23>, <&clkc 40>; |
| 53 | clock-names = "ref_clk", "aper_clk"; | 54 | clock-names = "ref_clk", "aper_clk"; |
| 54 | reg = <0xE0000000 0x1000>; | 55 | reg = <0xE0000000 0x1000>; |
| @@ -57,6 +58,7 @@ | |||
| 57 | 58 | ||
| 58 | uart1: uart@e0001000 { | 59 | uart1: uart@e0001000 { |
| 59 | compatible = "xlnx,xuartps"; | 60 | compatible = "xlnx,xuartps"; |
| 61 | status = "disabled"; | ||
| 60 | clocks = <&clkc 24>, <&clkc 41>; | 62 | clocks = <&clkc 24>, <&clkc 41>; |
| 61 | clock-names = "ref_clk", "aper_clk"; | 63 | clock-names = "ref_clk", "aper_clk"; |
| 62 | reg = <0xE0001000 0x1000>; | 64 | reg = <0xE0001000 0x1000>; |
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index e25a307438ad..21aea99a067b 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts | |||
| @@ -24,7 +24,11 @@ | |||
| 24 | }; | 24 | }; |
| 25 | 25 | ||
| 26 | chosen { | 26 | chosen { |
| 27 | bootargs = "console=ttyPS1,115200 earlyprintk"; | 27 | bootargs = "console=ttyPS0,115200 earlyprintk"; |
| 28 | }; | 28 | }; |
| 29 | 29 | ||
| 30 | }; | 30 | }; |
| 31 | |||
| 32 | &uart1 { | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts new file mode 100644 index 000000000000..79009e0b74b9 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zc706.dts | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Xilinx | ||
| 3 | * Copyright (C) 2012 National Instruments Corp. | ||
| 4 | * Copyright (C) 2013 Xilinx | ||
| 5 | * | ||
| 6 | * This software is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2, as published by the Free Software Foundation, and | ||
| 8 | * may be copied, distributed, and modified under those terms. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | /dts-v1/; | ||
| 16 | /include/ "zynq-7000.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "Zynq ZC706 Development Board"; | ||
| 20 | compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; | ||
| 21 | |||
| 22 | memory { | ||
| 23 | device_type = "memory"; | ||
| 24 | reg = <0 0x40000000>; | ||
| 25 | }; | ||
| 26 | |||
| 27 | chosen { | ||
| 28 | bootargs = "console=ttyPS0,115200 earlyprintk"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | }; | ||
| 32 | |||
| 33 | &uart1 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts new file mode 100644 index 000000000000..d6acf2b1cdf4 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zed.dts | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Xilinx | ||
| 3 | * Copyright (C) 2012 National Instruments Corp. | ||
| 4 | * Copyright (C) 2013 Xilinx | ||
| 5 | * | ||
| 6 | * This software is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2, as published by the Free Software Foundation, and | ||
| 8 | * may be copied, distributed, and modified under those terms. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | /dts-v1/; | ||
| 16 | /include/ "zynq-7000.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "Zynq Zed Development Board"; | ||
| 20 | compatible = "xlnx,zynq-7000"; | ||
| 21 | |||
| 22 | memory { | ||
| 23 | device_type = "memory"; | ||
| 24 | reg = <0 0x20000000>; | ||
| 25 | }; | ||
| 26 | |||
| 27 | chosen { | ||
| 28 | bootargs = "console=ttyPS0,115200 earlyprintk"; | ||
| 29 | }; | ||
| 30 | |||
| 31 | }; | ||
| 32 | |||
| 33 | &uart1 { | ||
| 34 | status = "okay"; | ||
| 35 | }; | ||
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index a8800d361805..75fd842d4071 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig | |||
| @@ -161,6 +161,7 @@ CONFIG_USB_ATMEL_USBA=y | |||
| 161 | CONFIG_USB_G_SERIAL=y | 161 | CONFIG_USB_G_SERIAL=y |
| 162 | CONFIG_MMC=y | 162 | CONFIG_MMC=y |
| 163 | CONFIG_MMC_ATMELMCI=y | 163 | CONFIG_MMC_ATMELMCI=y |
| 164 | CONFIG_MMC_SPI=y | ||
| 164 | CONFIG_NEW_LEDS=y | 165 | CONFIG_NEW_LEDS=y |
| 165 | CONFIG_LEDS_CLASS=y | 166 | CONFIG_LEDS_CLASS=y |
| 166 | CONFIG_LEDS_GPIO=y | 167 | CONFIG_LEDS_GPIO=y |
| @@ -169,6 +170,7 @@ CONFIG_LEDS_TRIGGER_TIMER=y | |||
| 169 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 170 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 170 | CONFIG_LEDS_TRIGGER_GPIO=y | 171 | CONFIG_LEDS_TRIGGER_GPIO=y |
| 171 | CONFIG_RTC_CLASS=y | 172 | CONFIG_RTC_CLASS=y |
| 173 | CONFIG_RTC_DRV_RV3029C2=y | ||
| 172 | CONFIG_RTC_DRV_AT91RM9200=y | 174 | CONFIG_RTC_DRV_AT91RM9200=y |
| 173 | CONFIG_RTC_DRV_AT91SAM9=y | 175 | CONFIG_RTC_DRV_AT91SAM9=y |
| 174 | CONFIG_DMADEVICES=y | 176 | CONFIG_DMADEVICES=y |
diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig index f50c404f0d3f..69b6928d3d9d 100644 --- a/arch/arm/configs/at91sam9260_9g20_defconfig +++ b/arch/arm/configs/at91sam9260_9g20_defconfig | |||
| @@ -15,7 +15,6 @@ CONFIG_MACH_AT91SAM9260EK=y | |||
| 15 | CONFIG_MACH_CAM60=y | 15 | CONFIG_MACH_CAM60=y |
| 16 | CONFIG_MACH_SAM9_L9260=y | 16 | CONFIG_MACH_SAM9_L9260=y |
| 17 | CONFIG_MACH_AFEB9260=y | 17 | CONFIG_MACH_AFEB9260=y |
| 18 | CONFIG_MACH_USB_A9260=y | ||
| 19 | CONFIG_MACH_QIL_A9260=y | 18 | CONFIG_MACH_QIL_A9260=y |
| 20 | CONFIG_MACH_CPU9260=y | 19 | CONFIG_MACH_CPU9260=y |
| 21 | CONFIG_MACH_FLEXIBITY=y | 20 | CONFIG_MACH_FLEXIBITY=y |
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig index 9d72ab684829..e40026364e57 100644 --- a/arch/arm/configs/at91sam9263_defconfig +++ b/arch/arm/configs/at91sam9263_defconfig | |||
| @@ -15,7 +15,6 @@ CONFIG_MODULE_UNLOAD=y | |||
| 15 | CONFIG_ARCH_AT91=y | 15 | CONFIG_ARCH_AT91=y |
| 16 | CONFIG_ARCH_AT91SAM9263=y | 16 | CONFIG_ARCH_AT91SAM9263=y |
| 17 | CONFIG_MACH_AT91SAM9263EK=y | 17 | CONFIG_MACH_AT91SAM9263EK=y |
| 18 | CONFIG_MACH_USB_A9263=y | ||
| 19 | CONFIG_MTD_AT91_DATAFLASH_CARD=y | 18 | CONFIG_MTD_AT91_DATAFLASH_CARD=y |
| 20 | # CONFIG_ARM_THUMB is not set | 19 | # CONFIG_ARM_THUMB is not set |
| 21 | CONFIG_AEABI=y | 20 | CONFIG_AEABI=y |
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index b01e7632ed2e..35f8cf299fa2 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig | |||
| @@ -81,6 +81,7 @@ CONFIG_PPP_SYNC_TTY=m | |||
| 81 | # CONFIG_INPUT_MOUSEDEV is not set | 81 | # CONFIG_INPUT_MOUSEDEV is not set |
| 82 | CONFIG_INPUT_EVDEV=y | 82 | CONFIG_INPUT_EVDEV=y |
| 83 | # CONFIG_KEYBOARD_ATKBD is not set | 83 | # CONFIG_KEYBOARD_ATKBD is not set |
| 84 | CONFIG_KEYBOARD_GPIO=y | ||
| 84 | # CONFIG_MOUSE_PS2 is not set | 85 | # CONFIG_MOUSE_PS2 is not set |
| 85 | # CONFIG_SERIO is not set | 86 | # CONFIG_SERIO is not set |
| 86 | # CONFIG_LEGACY_PTYS is not set | 87 | # CONFIG_LEGACY_PTYS is not set |
| @@ -96,6 +97,11 @@ CONFIG_DEBUG_GPIO=y | |||
| 96 | CONFIG_MMC=y | 97 | CONFIG_MMC=y |
| 97 | CONFIG_MMC_CLKGATE=y | 98 | CONFIG_MMC_CLKGATE=y |
| 98 | CONFIG_MMC_ARMMMCI=y | 99 | CONFIG_MMC_ARMMMCI=y |
| 100 | CONFIG_NEW_LEDS=y | ||
| 101 | CONFIG_LEDS_CLASS=y | ||
| 102 | CONFIG_LEDS_GPIO=y | ||
| 103 | CONFIG_LEDS_TRIGGERS=y | ||
| 104 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 99 | CONFIG_RTC_CLASS=y | 105 | CONFIG_RTC_CLASS=y |
| 100 | CONFIG_RTC_DRV_PL031=y | 106 | CONFIG_RTC_DRV_PL031=y |
| 101 | CONFIG_DMADEVICES=y | 107 | CONFIG_DMADEVICES=y |
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt index 3a78bdcd0a43..ca900be144ce 100644 --- a/arch/arm/mach-at91/Kconfig.non_dt +++ b/arch/arm/mach-at91/Kconfig.non_dt | |||
| @@ -176,12 +176,6 @@ config MACH_AFEB9260 | |||
| 176 | <svn://194.85.238.22/home/users/george/svn/arm9eb> | 176 | <svn://194.85.238.22/home/users/george/svn/arm9eb> |
| 177 | <http://groups.google.com/group/arm9fpga-evolution-board> | 177 | <http://groups.google.com/group/arm9fpga-evolution-board> |
| 178 | 178 | ||
| 179 | config MACH_USB_A9260 | ||
| 180 | bool "CALAO USB-A9260" | ||
| 181 | help | ||
| 182 | Select this if you are using a Calao Systems USB-A9260. | ||
| 183 | <http://www.calao-systems.com> | ||
| 184 | |||
| 185 | config MACH_QIL_A9260 | 179 | config MACH_QIL_A9260 |
| 186 | bool "CALAO QIL-A9260 board" | 180 | bool "CALAO QIL-A9260 board" |
| 187 | help | 181 | help |
| @@ -257,13 +251,6 @@ config MACH_GSIA18S | |||
| 257 | produced by GeoSIG Ltd company. This is an internet accelerograph. | 251 | produced by GeoSIG Ltd company. This is an internet accelerograph. |
| 258 | <http://www.geosig.com> | 252 | <http://www.geosig.com> |
| 259 | 253 | ||
| 260 | config MACH_USB_A9G20 | ||
| 261 | bool "CALAO USB-A9G20" | ||
| 262 | depends on ARCH_AT91SAM9G20 | ||
| 263 | help | ||
| 264 | Select this if you are using a Calao Systems USB-A9G20. | ||
| 265 | <http://www.calao-systems.com> | ||
| 266 | |||
| 267 | config MACH_SNAPPER_9260 | 254 | config MACH_SNAPPER_9260 |
| 268 | bool "Bluewater Systems Snapper 9260/9G20 module" | 255 | bool "Bluewater Systems Snapper 9260/9G20 module" |
| 269 | help | 256 | help |
| @@ -309,12 +296,6 @@ config MACH_AT91SAM9263EK | |||
| 309 | Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. | 296 | Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. |
| 310 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> | 297 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> |
| 311 | 298 | ||
| 312 | config MACH_USB_A9263 | ||
| 313 | bool "CALAO USB-A9263" | ||
| 314 | help | ||
| 315 | Select this if you are using a Calao Systems USB-A9263. | ||
| 316 | <http://www.calao-systems.com> | ||
| 317 | |||
| 318 | endif | 299 | endif |
| 319 | 300 | ||
| 320 | # ---------------------------------------------------------- | 301 | # ---------------------------------------------------------- |
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 07e89b4db7e7..3b0a9538093c 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
| @@ -52,7 +52,6 @@ obj-$(CONFIG_MACH_RSI_EWS) += board-rsi-ews.o | |||
| 52 | obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o | 52 | obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o |
| 53 | obj-$(CONFIG_MACH_CAM60) += board-cam60.o | 53 | obj-$(CONFIG_MACH_CAM60) += board-cam60.o |
| 54 | obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o | 54 | obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o |
| 55 | obj-$(CONFIG_MACH_USB_A9260) += board-usb-a926x.o | ||
| 56 | obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o | 55 | obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o |
| 57 | obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o | 56 | obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o |
| 58 | obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o | 57 | obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o |
| @@ -64,7 +63,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o | |||
| 64 | 63 | ||
| 65 | # AT91SAM9263 board-specific support | 64 | # AT91SAM9263 board-specific support |
| 66 | obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o | 65 | obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o |
| 67 | obj-$(CONFIG_MACH_USB_A9263) += board-usb-a926x.o | ||
| 68 | 66 | ||
| 69 | # AT91SAM9RL board-specific support | 67 | # AT91SAM9RL board-specific support |
| 70 | obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o | 68 | obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o |
| @@ -77,7 +75,6 @@ obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o | |||
| 77 | obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o | 75 | obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o |
| 78 | obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o | 76 | obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o |
| 79 | obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o | 77 | obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o |
| 80 | obj-$(CONFIG_MACH_USB_A9G20) += board-usb-a926x.o | ||
| 81 | 78 | ||
| 82 | # AT91SAM9260/AT91SAM9G20 board-specific support | 79 | # AT91SAM9260/AT91SAM9G20 board-specific support |
| 83 | obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o | 80 | obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o |
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index fda502691686..474ee04d24b9 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
| @@ -266,6 +266,8 @@ static struct clk_lookup periph_clocks_lookups[] = { | |||
| 266 | CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk), | 266 | CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk), |
| 267 | CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk), | 267 | CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk), |
| 268 | CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk), | 268 | CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk), |
| 269 | CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk), | ||
| 270 | CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk), | ||
| 269 | /* fake hclk clock */ | 271 | /* fake hclk clock */ |
| 270 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), | 272 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), |
| 271 | CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), | 273 | CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), |
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index e631fec040ce..2abee6626aac 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c | |||
| @@ -249,6 +249,8 @@ static struct clk_lookup periph_clocks_lookups[] = { | |||
| 249 | CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), | 249 | CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), |
| 250 | CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk), | 250 | CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk), |
| 251 | CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), | 251 | CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), |
| 252 | CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk), | ||
| 253 | CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk), | ||
| 252 | }; | 254 | }; |
| 253 | 255 | ||
| 254 | /* | 256 | /* |
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c deleted file mode 100644 index 2487d944a1bc..000000000000 --- a/arch/arm/mach-at91/board-usb-a926x.c +++ /dev/null | |||
| @@ -1,384 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-at91/board-usb-a926x.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 SAN People | ||
| 5 | * Copyright (C) 2007 Atmel Corporation. | ||
| 6 | * Copyright (C) 2007 Calao-systems | ||
| 7 | * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 22 | */ | ||
| 23 | |||
| 24 | #include <linux/types.h> | ||
| 25 | #include <linux/init.h> | ||
| 26 | #include <linux/mm.h> | ||
| 27 | #include <linux/module.h> | ||
| 28 | #include <linux/platform_device.h> | ||
| 29 | #include <linux/spi/spi.h> | ||
| 30 | #include <linux/gpio_keys.h> | ||
| 31 | #include <linux/gpio.h> | ||
| 32 | #include <linux/input.h> | ||
| 33 | #include <linux/spi/mmc_spi.h> | ||
| 34 | |||
| 35 | #include <asm/setup.h> | ||
| 36 | #include <asm/mach-types.h> | ||
| 37 | #include <asm/irq.h> | ||
| 38 | |||
| 39 | #include <asm/mach/arch.h> | ||
| 40 | #include <asm/mach/map.h> | ||
| 41 | #include <asm/mach/irq.h> | ||
| 42 | |||
| 43 | #include <mach/hardware.h> | ||
| 44 | #include <mach/at91sam9_smc.h> | ||
| 45 | |||
| 46 | #include "at91_aic.h" | ||
| 47 | #include "at91_shdwc.h" | ||
| 48 | #include "board.h" | ||
| 49 | #include "sam9_smc.h" | ||
| 50 | #include "generic.h" | ||
| 51 | |||
| 52 | |||
| 53 | static void __init ek_init_early(void) | ||
| 54 | { | ||
| 55 | /* Initialize processor: 12.00 MHz crystal */ | ||
| 56 | at91_initialize(12000000); | ||
| 57 | } | ||
| 58 | |||
| 59 | /* | ||
| 60 | * USB Host port | ||
| 61 | */ | ||
| 62 | static struct at91_usbh_data __initdata ek_usbh_data = { | ||
| 63 | .ports = 2, | ||
| 64 | .vbus_pin = {-EINVAL, -EINVAL}, | ||
| 65 | .overcurrent_pin= {-EINVAL, -EINVAL}, | ||
| 66 | }; | ||
| 67 | |||
| 68 | /* | ||
| 69 | * USB Device port | ||
| 70 | */ | ||
| 71 | static struct at91_udc_data __initdata ek_udc_data = { | ||
| 72 | .vbus_pin = AT91_PIN_PB11, | ||
| 73 | .pullup_pin = -EINVAL, /* pull-up driven by UDC */ | ||
| 74 | }; | ||
| 75 | |||
| 76 | static void __init ek_add_device_udc(void) | ||
| 77 | { | ||
| 78 | if (machine_is_usb_a9260() || machine_is_usb_a9g20()) | ||
| 79 | ek_udc_data.vbus_pin = AT91_PIN_PC5; | ||
| 80 | |||
| 81 | at91_add_device_udc(&ek_udc_data); | ||
| 82 | } | ||
| 83 | |||
| 84 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | ||
| 85 | #define MMC_SPI_CARD_DETECT_INT AT91_PIN_PC4 | ||
| 86 | static int at91_mmc_spi_init(struct device *dev, | ||
| 87 | irqreturn_t (*detect_int)(int, void *), void *data) | ||
| 88 | { | ||
| 89 | /* Configure Interrupt pin as input, no pull-up */ | ||
| 90 | at91_set_gpio_input(MMC_SPI_CARD_DETECT_INT, 0); | ||
| 91 | return request_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), detect_int, | ||
| 92 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | ||
| 93 | "mmc-spi-detect", data); | ||
| 94 | } | ||
| 95 | |||
| 96 | static void at91_mmc_spi_exit(struct device *dev, void *data) | ||
| 97 | { | ||
| 98 | free_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), data); | ||
| 99 | } | ||
| 100 | |||
| 101 | static struct mmc_spi_platform_data at91_mmc_spi_pdata = { | ||
| 102 | .init = at91_mmc_spi_init, | ||
| 103 | .exit = at91_mmc_spi_exit, | ||
| 104 | .detect_delay = 100, /* msecs */ | ||
| 105 | }; | ||
| 106 | #endif | ||
| 107 | |||
| 108 | /* | ||
| 109 | * SPI devices. | ||
| 110 | */ | ||
| 111 | static struct spi_board_info usb_a9263_spi_devices[] = { | ||
| 112 | { /* DataFlash chip */ | ||
| 113 | .modalias = "mtd_dataflash", | ||
| 114 | .chip_select = 0, | ||
| 115 | .max_speed_hz = 15 * 1000 * 1000, | ||
| 116 | .bus_num = 0, | ||
| 117 | } | ||
| 118 | }; | ||
| 119 | |||
| 120 | static struct spi_board_info usb_a9g20_spi_devices[] = { | ||
| 121 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) | ||
| 122 | { | ||
| 123 | .modalias = "mmc_spi", | ||
| 124 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
| 125 | .bus_num = 1, | ||
| 126 | .chip_select = 0, | ||
| 127 | .platform_data = &at91_mmc_spi_pdata, | ||
| 128 | .mode = SPI_MODE_3, | ||
| 129 | }, | ||
| 130 | #endif | ||
| 131 | }; | ||
| 132 | |||
| 133 | static void __init ek_add_device_spi(void) | ||
| 134 | { | ||
| 135 | if (machine_is_usb_a9263()) | ||
| 136 | at91_add_device_spi(usb_a9263_spi_devices, ARRAY_SIZE(usb_a9263_spi_devices)); | ||
| 137 | else if (machine_is_usb_a9g20()) | ||
| 138 | at91_add_device_spi(usb_a9g20_spi_devices, ARRAY_SIZE(usb_a9g20_spi_devices)); | ||
| 139 | } | ||
| 140 | |||
| 141 | /* | ||
| 142 | * MACB Ethernet device | ||
| 143 | */ | ||
| 144 | static struct macb_platform_data __initdata ek_macb_data = { | ||
| 145 | .phy_irq_pin = AT91_PIN_PE31, | ||
| 146 | .is_rmii = 1, | ||
| 147 | }; | ||
| 148 | |||
| 149 | static void __init ek_add_device_eth(void) | ||
| 150 | { | ||
| 151 | if (machine_is_usb_a9260() || machine_is_usb_a9g20()) | ||
| 152 | ek_macb_data.phy_irq_pin = AT91_PIN_PA31; | ||
| 153 | |||
| 154 | at91_add_device_eth(&ek_macb_data); | ||
| 155 | } | ||
| 156 | |||
| 157 | /* | ||
| 158 | * NAND flash | ||
| 159 | */ | ||
| 160 | static struct mtd_partition __initdata ek_nand_partition[] = { | ||
| 161 | { | ||
| 162 | .name = "barebox", | ||
| 163 | .offset = 0, | ||
| 164 | .size = 3 * SZ_128K, | ||
| 165 | }, { | ||
| 166 | .name = "bareboxenv", | ||
| 167 | .offset = MTDPART_OFS_NXTBLK, | ||
| 168 | .size = SZ_128K, | ||
| 169 | }, { | ||
| 170 | .name = "bareboxenv2", | ||
| 171 | .offset = MTDPART_OFS_NXTBLK, | ||
| 172 | .size = SZ_128K, | ||
| 173 | }, { | ||
| 174 | .name = "oftree", | ||
| 175 | .offset = MTDPART_OFS_NXTBLK, | ||
| 176 | .size = SZ_128K, | ||
| 177 | }, { | ||
| 178 | .name = "kernel", | ||
| 179 | .offset = MTDPART_OFS_NXTBLK, | ||
| 180 | .size = 4 * SZ_1M, | ||
| 181 | }, { | ||
| 182 | .name = "rootfs", | ||
| 183 | .offset = MTDPART_OFS_NXTBLK, | ||
| 184 | .size = 120 * SZ_1M, | ||
| 185 | }, { | ||
| 186 | .name = "data", | ||
| 187 | .offset = MTDPART_OFS_NXTBLK, | ||
| 188 | .size = MTDPART_SIZ_FULL, | ||
| 189 | } | ||
| 190 | }; | ||
| 191 | |||
| 192 | static struct atmel_nand_data __initdata ek_nand_data = { | ||
| 193 | .ale = 21, | ||
| 194 | .cle = 22, | ||
| 195 | .det_pin = -EINVAL, | ||
| 196 | .rdy_pin = AT91_PIN_PA22, | ||
| 197 | .enable_pin = AT91_PIN_PD15, | ||
| 198 | .ecc_mode = NAND_ECC_SOFT, | ||
| 199 | .on_flash_bbt = 1, | ||
| 200 | .parts = ek_nand_partition, | ||
| 201 | .num_parts = ARRAY_SIZE(ek_nand_partition), | ||
| 202 | }; | ||
| 203 | |||
| 204 | static struct sam9_smc_config __initdata usb_a9260_nand_smc_config = { | ||
| 205 | .ncs_read_setup = 0, | ||
| 206 | .nrd_setup = 1, | ||
| 207 | .ncs_write_setup = 0, | ||
| 208 | .nwe_setup = 1, | ||
| 209 | |||
| 210 | .ncs_read_pulse = 3, | ||
| 211 | .nrd_pulse = 3, | ||
| 212 | .ncs_write_pulse = 3, | ||
| 213 | .nwe_pulse = 3, | ||
| 214 | |||
| 215 | .read_cycle = 5, | ||
| 216 | .write_cycle = 5, | ||
| 217 | |||
| 218 | .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, | ||
| 219 | .tdf_cycles = 2, | ||
| 220 | }; | ||
| 221 | |||
| 222 | static struct sam9_smc_config __initdata usb_a9g20_nand_smc_config = { | ||
| 223 | .ncs_read_setup = 0, | ||
| 224 | .nrd_setup = 2, | ||
| 225 | .ncs_write_setup = 0, | ||
| 226 | .nwe_setup = 2, | ||
| 227 | |||
| 228 | .ncs_read_pulse = 4, | ||
| 229 | .nrd_pulse = 4, | ||
| 230 | .ncs_write_pulse = 4, | ||
| 231 | .nwe_pulse = 4, | ||
| 232 | |||
| 233 | .read_cycle = 7, | ||
| 234 | .write_cycle = 7, | ||
| 235 | |||
| 236 | .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, | ||
| 237 | .tdf_cycles = 3, | ||
| 238 | }; | ||
| 239 | |||
| 240 | static void __init ek_add_device_nand(void) | ||
| 241 | { | ||
| 242 | if (machine_is_usb_a9260() || machine_is_usb_a9g20()) { | ||
| 243 | ek_nand_data.rdy_pin = AT91_PIN_PC13; | ||
| 244 | ek_nand_data.enable_pin = AT91_PIN_PC14; | ||
| 245 | } | ||
| 246 | |||
| 247 | /* configure chip-select 3 (NAND) */ | ||
| 248 | if (machine_is_usb_a9g20()) | ||
| 249 | sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config); | ||
| 250 | else | ||
| 251 | sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config); | ||
| 252 | |||
| 253 | at91_add_device_nand(&ek_nand_data); | ||
| 254 | } | ||
| 255 | |||
| 256 | |||
| 257 | /* | ||
| 258 | * GPIO Buttons | ||
| 259 | */ | ||
| 260 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 261 | static struct gpio_keys_button ek_buttons[] = { | ||
| 262 | { /* USER PUSH BUTTON */ | ||
| 263 | .code = KEY_ENTER, | ||
| 264 | .gpio = AT91_PIN_PB10, | ||
| 265 | .active_low = 1, | ||
| 266 | .desc = "user_pb", | ||
| 267 | .wakeup = 1, | ||
| 268 | } | ||
| 269 | }; | ||
| 270 | |||
| 271 | static struct gpio_keys_platform_data ek_button_data = { | ||
| 272 | .buttons = ek_buttons, | ||
| 273 | .nbuttons = ARRAY_SIZE(ek_buttons), | ||
| 274 | }; | ||
| 275 | |||
| 276 | static struct platform_device ek_button_device = { | ||
| 277 | .name = "gpio-keys", | ||
| 278 | .id = -1, | ||
| 279 | .num_resources = 0, | ||
| 280 | .dev = { | ||
| 281 | .platform_data = &ek_button_data, | ||
| 282 | } | ||
| 283 | }; | ||
| 284 | |||
| 285 | static void __init ek_add_device_buttons(void) | ||
| 286 | { | ||
| 287 | at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */ | ||
| 288 | at91_set_deglitch(AT91_PIN_PB10, 1); | ||
| 289 | |||
| 290 | platform_device_register(&ek_button_device); | ||
| 291 | } | ||
| 292 | #else | ||
| 293 | static void __init ek_add_device_buttons(void) {} | ||
| 294 | #endif | ||
| 295 | |||
| 296 | /* | ||
| 297 | * LEDs | ||
| 298 | */ | ||
| 299 | static struct gpio_led ek_leds[] = { | ||
| 300 | { /* user_led (green) */ | ||
| 301 | .name = "user_led", | ||
| 302 | .gpio = AT91_PIN_PB21, | ||
| 303 | .active_low = 1, | ||
| 304 | .default_trigger = "heartbeat", | ||
| 305 | } | ||
| 306 | }; | ||
| 307 | |||
| 308 | static struct i2c_board_info __initdata ek_i2c_devices[] = { | ||
| 309 | { | ||
| 310 | I2C_BOARD_INFO("rv3029c2", 0x56), | ||
| 311 | }, | ||
| 312 | }; | ||
| 313 | |||
| 314 | static void __init ek_add_device_leds(void) | ||
| 315 | { | ||
| 316 | if (machine_is_usb_a9260() || machine_is_usb_a9g20()) | ||
| 317 | ek_leds[0].active_low = 0; | ||
| 318 | |||
| 319 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); | ||
| 320 | } | ||
| 321 | |||
| 322 | static void __init ek_board_init(void) | ||
| 323 | { | ||
| 324 | /* Serial */ | ||
| 325 | /* DBGU on ttyS0. (Rx & Tx only) */ | ||
| 326 | at91_register_uart(0, 0, 0); | ||
| 327 | at91_add_device_serial(); | ||
| 328 | /* USB Host */ | ||
| 329 | at91_add_device_usbh(&ek_usbh_data); | ||
| 330 | /* USB Device */ | ||
| 331 | ek_add_device_udc(); | ||
| 332 | /* SPI */ | ||
| 333 | ek_add_device_spi(); | ||
| 334 | /* Ethernet */ | ||
| 335 | ek_add_device_eth(); | ||
| 336 | /* NAND */ | ||
| 337 | ek_add_device_nand(); | ||
| 338 | /* Push Buttons */ | ||
| 339 | ek_add_device_buttons(); | ||
| 340 | /* LEDs */ | ||
| 341 | ek_add_device_leds(); | ||
| 342 | |||
| 343 | if (machine_is_usb_a9g20()) { | ||
| 344 | /* I2C */ | ||
| 345 | at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); | ||
| 346 | } else { | ||
| 347 | /* I2C */ | ||
| 348 | at91_add_device_i2c(NULL, 0); | ||
| 349 | /* shutdown controller, wakeup button (5 msec low) */ | ||
| 350 | at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | ||
| 351 | | AT91_SHDW_WKMODE0_LOW | ||
| 352 | | AT91_SHDW_RTTWKEN); | ||
| 353 | } | ||
| 354 | } | ||
| 355 | |||
| 356 | MACHINE_START(USB_A9263, "CALAO USB_A9263") | ||
| 357 | /* Maintainer: calao-systems */ | ||
| 358 | .init_time = at91sam926x_pit_init, | ||
| 359 | .map_io = at91_map_io, | ||
| 360 | .handle_irq = at91_aic_handle_irq, | ||
| 361 | .init_early = ek_init_early, | ||
| 362 | .init_irq = at91_init_irq_default, | ||
| 363 | .init_machine = ek_board_init, | ||
| 364 | MACHINE_END | ||
| 365 | |||
| 366 | MACHINE_START(USB_A9260, "CALAO USB_A9260") | ||
| 367 | /* Maintainer: calao-systems */ | ||
| 368 | .init_time = at91sam926x_pit_init, | ||
| 369 | .map_io = at91_map_io, | ||
| 370 | .handle_irq = at91_aic_handle_irq, | ||
| 371 | .init_early = ek_init_early, | ||
| 372 | .init_irq = at91_init_irq_default, | ||
| 373 | .init_machine = ek_board_init, | ||
| 374 | MACHINE_END | ||
| 375 | |||
| 376 | MACHINE_START(USB_A9G20, "CALAO USB_A92G0") | ||
| 377 | /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */ | ||
| 378 | .init_time = at91sam926x_pit_init, | ||
| 379 | .map_io = at91_map_io, | ||
| 380 | .handle_irq = at91_aic_handle_irq, | ||
| 381 | .init_early = ek_init_early, | ||
| 382 | .init_irq = at91_init_irq_default, | ||
| 383 | .init_machine = ek_board_init, | ||
| 384 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 04b1bad68350..9afac26fa1cc 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c | |||
| @@ -327,8 +327,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, | |||
| 327 | clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); | 327 | clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); |
| 328 | clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); | 328 | clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); |
| 329 | clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2"); | 329 | clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2"); |
| 330 | clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL); | ||
| 331 | clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL); | ||
| 332 | clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); | 330 | clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); |
| 333 | clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0"); | 331 | clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0"); |
| 334 | clk_register_clkdev(clk[iim_gate], "iim", NULL); | 332 | clk_register_clkdev(clk[iim_gate], "iim", NULL); |
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 74e7b94c22e7..98c58944015a 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c | |||
| @@ -24,26 +24,10 @@ | |||
| 24 | #include "hardware.h" | 24 | #include "hardware.h" |
| 25 | #include "mx53.h" | 25 | #include "mx53.h" |
| 26 | 26 | ||
| 27 | static void __init imx53_qsb_init(void) | ||
| 28 | { | ||
| 29 | struct clk *clk; | ||
| 30 | |||
| 31 | clk = clk_get_sys(NULL, "ssi_ext1"); | ||
| 32 | if (IS_ERR(clk)) { | ||
| 33 | pr_err("failed to get clk ssi_ext1\n"); | ||
| 34 | return; | ||
| 35 | } | ||
| 36 | |||
| 37 | clk_register_clkdev(clk, NULL, "0-000a"); | ||
| 38 | } | ||
| 39 | |||
| 40 | static void __init imx53_dt_init(void) | 27 | static void __init imx53_dt_init(void) |
| 41 | { | 28 | { |
| 42 | mxc_arch_reset_init_dt(); | 29 | mxc_arch_reset_init_dt(); |
| 43 | 30 | ||
| 44 | if (of_machine_is_compatible("fsl,imx53-qsb")) | ||
| 45 | imx53_qsb_init(); | ||
| 46 | |||
| 47 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 31 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 48 | } | 32 | } |
| 49 | 33 | ||
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 3a66635e7d17..616fe0210da1 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig | |||
| @@ -23,6 +23,7 @@ config ARCH_MXS | |||
| 23 | select GENERIC_CLOCKEVENTS | 23 | select GENERIC_CLOCKEVENTS |
| 24 | select HAVE_CLK_PREPARE | 24 | select HAVE_CLK_PREPARE |
| 25 | select PINCTRL | 25 | select PINCTRL |
| 26 | select SOC_BUS | ||
| 26 | select SOC_IMX23 | 27 | select SOC_IMX23 |
| 27 | select SOC_IMX28 | 28 | select SOC_IMX28 |
| 28 | select STMP_DEVICE | 29 | select STMP_DEVICE |
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index d67ecc1c8847..7fa611c1b287 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c | |||
| @@ -19,13 +19,13 @@ | |||
| 19 | #include <linux/err.h> | 19 | #include <linux/err.h> |
| 20 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
| 21 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| 22 | #include <linux/irqchip.h> | ||
| 23 | #include <linux/irqchip/mxs.h> | 22 | #include <linux/irqchip/mxs.h> |
| 24 | #include <linux/micrel_phy.h> | 23 | #include <linux/micrel_phy.h> |
| 25 | #include <linux/of_address.h> | 24 | #include <linux/of_address.h> |
| 26 | #include <linux/of_platform.h> | 25 | #include <linux/of_platform.h> |
| 27 | #include <linux/phy.h> | 26 | #include <linux/phy.h> |
| 28 | #include <linux/pinctrl/consumer.h> | 27 | #include <linux/pinctrl/consumer.h> |
| 28 | #include <linux/sys_soc.h> | ||
| 29 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 30 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
| 31 | #include <asm/mach/time.h> | 31 | #include <asm/mach/time.h> |
| @@ -39,12 +39,28 @@ | |||
| 39 | #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 | 39 | #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 |
| 40 | #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 | 40 | #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 |
| 41 | 41 | ||
| 42 | #define HW_DIGCTL_CHIPID 0x310 | ||
| 43 | #define HW_DIGCTL_CHIPID_MASK (0xffff << 16) | ||
| 44 | #define HW_DIGCTL_REV_MASK 0xff | ||
| 45 | #define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16) | ||
| 46 | #define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16) | ||
| 47 | |||
| 48 | #define MXS_CHIP_REVISION_1_0 0x10 | ||
| 49 | #define MXS_CHIP_REVISION_1_1 0x11 | ||
| 50 | #define MXS_CHIP_REVISION_1_2 0x12 | ||
| 51 | #define MXS_CHIP_REVISION_1_3 0x13 | ||
| 52 | #define MXS_CHIP_REVISION_1_4 0x14 | ||
| 53 | #define MXS_CHIP_REV_UNKNOWN 0xff | ||
| 54 | |||
| 42 | #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) | 55 | #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) |
| 43 | 56 | ||
| 44 | #define MXS_SET_ADDR 0x4 | 57 | #define MXS_SET_ADDR 0x4 |
| 45 | #define MXS_CLR_ADDR 0x8 | 58 | #define MXS_CLR_ADDR 0x8 |
| 46 | #define MXS_TOG_ADDR 0xc | 59 | #define MXS_TOG_ADDR 0xc |
| 47 | 60 | ||
| 61 | static u32 chipid; | ||
| 62 | static u32 socid; | ||
| 63 | |||
| 48 | static inline void __mxs_setl(u32 mask, void __iomem *reg) | 64 | static inline void __mxs_setl(u32 mask, void __iomem *reg) |
| 49 | { | 65 | { |
| 50 | __raw_writel(mask, reg + MXS_SET_ADDR); | 66 | __raw_writel(mask, reg + MXS_SET_ADDR); |
| @@ -352,29 +368,123 @@ static void __init tx28_post_init(void) | |||
| 352 | pinctrl_put(pctl); | 368 | pinctrl_put(pctl); |
| 353 | } | 369 | } |
| 354 | 370 | ||
| 355 | static void __init cfa10049_init(void) | 371 | static void __init crystalfontz_init(void) |
| 356 | { | 372 | { |
| 357 | update_fec_mac_prop(OUI_CRYSTALFONTZ); | 373 | update_fec_mac_prop(OUI_CRYSTALFONTZ); |
| 358 | } | 374 | } |
| 359 | 375 | ||
| 360 | static void __init cfa10037_init(void) | 376 | static const char __init *mxs_get_soc_id(void) |
| 361 | { | 377 | { |
| 362 | update_fec_mac_prop(OUI_CRYSTALFONTZ); | 378 | struct device_node *np; |
| 379 | void __iomem *digctl_base; | ||
| 380 | |||
| 381 | np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl"); | ||
| 382 | digctl_base = of_iomap(np, 0); | ||
| 383 | WARN_ON(!digctl_base); | ||
| 384 | |||
| 385 | chipid = readl(digctl_base + HW_DIGCTL_CHIPID); | ||
| 386 | socid = chipid & HW_DIGCTL_CHIPID_MASK; | ||
| 387 | |||
| 388 | iounmap(digctl_base); | ||
| 389 | of_node_put(np); | ||
| 390 | |||
| 391 | switch (socid) { | ||
| 392 | case HW_DIGCTL_CHIPID_MX23: | ||
| 393 | return "i.MX23"; | ||
| 394 | case HW_DIGCTL_CHIPID_MX28: | ||
| 395 | return "i.MX28"; | ||
| 396 | default: | ||
| 397 | return "Unknown"; | ||
| 398 | } | ||
| 399 | } | ||
| 400 | |||
| 401 | static u32 __init mxs_get_cpu_rev(void) | ||
| 402 | { | ||
| 403 | u32 rev = chipid & HW_DIGCTL_REV_MASK; | ||
| 404 | |||
| 405 | switch (socid) { | ||
| 406 | case HW_DIGCTL_CHIPID_MX23: | ||
| 407 | switch (rev) { | ||
| 408 | case 0x0: | ||
| 409 | return MXS_CHIP_REVISION_1_0; | ||
| 410 | case 0x1: | ||
| 411 | return MXS_CHIP_REVISION_1_1; | ||
| 412 | case 0x2: | ||
| 413 | return MXS_CHIP_REVISION_1_2; | ||
| 414 | case 0x3: | ||
| 415 | return MXS_CHIP_REVISION_1_3; | ||
| 416 | case 0x4: | ||
| 417 | return MXS_CHIP_REVISION_1_4; | ||
| 418 | default: | ||
| 419 | return MXS_CHIP_REV_UNKNOWN; | ||
| 420 | } | ||
| 421 | case HW_DIGCTL_CHIPID_MX28: | ||
| 422 | switch (rev) { | ||
| 423 | case 0x0: | ||
| 424 | return MXS_CHIP_REVISION_1_1; | ||
| 425 | case 0x1: | ||
| 426 | return MXS_CHIP_REVISION_1_2; | ||
| 427 | default: | ||
| 428 | return MXS_CHIP_REV_UNKNOWN; | ||
| 429 | } | ||
| 430 | default: | ||
| 431 | return MXS_CHIP_REV_UNKNOWN; | ||
| 432 | } | ||
| 433 | } | ||
| 434 | |||
| 435 | static const char __init *mxs_get_revision(void) | ||
| 436 | { | ||
| 437 | u32 rev = mxs_get_cpu_rev(); | ||
| 438 | |||
| 439 | if (rev != MXS_CHIP_REV_UNKNOWN) | ||
| 440 | return kasprintf(GFP_KERNEL, "TO%d.%d", (rev >> 4) & 0xf, | ||
| 441 | rev & 0xf); | ||
| 442 | else | ||
| 443 | return kasprintf(GFP_KERNEL, "%s", "Unknown"); | ||
| 363 | } | 444 | } |
| 364 | 445 | ||
| 365 | static void __init mxs_machine_init(void) | 446 | static void __init mxs_machine_init(void) |
| 366 | { | 447 | { |
| 448 | struct device_node *root; | ||
| 449 | struct device *parent; | ||
| 450 | struct soc_device *soc_dev; | ||
| 451 | struct soc_device_attribute *soc_dev_attr; | ||
| 452 | int ret; | ||
| 453 | |||
| 454 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | ||
| 455 | if (!soc_dev_attr) | ||
| 456 | return; | ||
| 457 | |||
| 458 | root = of_find_node_by_path("/"); | ||
| 459 | ret = of_property_read_string(root, "model", &soc_dev_attr->machine); | ||
| 460 | if (ret) | ||
| 461 | return; | ||
| 462 | |||
| 463 | soc_dev_attr->family = "Freescale MXS Family"; | ||
| 464 | soc_dev_attr->soc_id = mxs_get_soc_id(); | ||
| 465 | soc_dev_attr->revision = mxs_get_revision(); | ||
| 466 | |||
| 467 | soc_dev = soc_device_register(soc_dev_attr); | ||
| 468 | if (IS_ERR(soc_dev)) { | ||
| 469 | kfree(soc_dev_attr->revision); | ||
| 470 | kfree(soc_dev_attr); | ||
| 471 | return; | ||
| 472 | } | ||
| 473 | |||
| 474 | parent = soc_device_to_device(soc_dev); | ||
| 475 | |||
| 367 | if (of_machine_is_compatible("fsl,imx28-evk")) | 476 | if (of_machine_is_compatible("fsl,imx28-evk")) |
| 368 | imx28_evk_init(); | 477 | imx28_evk_init(); |
| 369 | else if (of_machine_is_compatible("bluegiga,apx4devkit")) | 478 | else if (of_machine_is_compatible("bluegiga,apx4devkit")) |
| 370 | apx4devkit_init(); | 479 | apx4devkit_init(); |
| 371 | else if (of_machine_is_compatible("crystalfontz,cfa10037")) | 480 | else if (of_machine_is_compatible("crystalfontz,cfa10037") || |
| 372 | cfa10037_init(); | 481 | of_machine_is_compatible("crystalfontz,cfa10049") || |
| 373 | else if (of_machine_is_compatible("crystalfontz,cfa10049")) | 482 | of_machine_is_compatible("crystalfontz,cfa10055") || |
| 374 | cfa10049_init(); | 483 | of_machine_is_compatible("crystalfontz,cfa10057")) |
| 484 | crystalfontz_init(); | ||
| 375 | 485 | ||
| 376 | of_platform_populate(NULL, of_default_bus_match_table, | 486 | of_platform_populate(NULL, of_default_bus_match_table, |
| 377 | mxs_auxdata_lookup, NULL); | 487 | mxs_auxdata_lookup, parent); |
| 378 | 488 | ||
| 379 | if (of_machine_is_compatible("karo,tx28")) | 489 | if (of_machine_is_compatible("karo,tx28")) |
| 380 | tx28_post_init(); | 490 | tx28_post_init(); |
| @@ -434,7 +544,6 @@ static const char *mxs_dt_compat[] __initdata = { | |||
| 434 | }; | 544 | }; |
| 435 | 545 | ||
| 436 | DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") | 546 | DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)") |
| 437 | .init_irq = irqchip_init, | ||
| 438 | .handle_irq = icoll_handle_irq, | 547 | .handle_irq = icoll_handle_irq, |
| 439 | .init_time = mxs_timer_init, | 548 | .init_time = mxs_timer_init, |
| 440 | .init_machine = mxs_machine_init, | 549 | .init_machine = mxs_machine_init, |
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index 9b9d105f194c..5981c3db9b41 100644 --- a/arch/arm/mach-nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig | |||
| @@ -6,6 +6,7 @@ config ARCH_NOMADIK | |||
| 6 | select ARM_VIC | 6 | select ARM_VIC |
| 7 | select CLKSRC_NOMADIK_MTU | 7 | select CLKSRC_NOMADIK_MTU |
| 8 | select CLKSRC_NOMADIK_MTU_SCHED_CLOCK | 8 | select CLKSRC_NOMADIK_MTU_SCHED_CLOCK |
| 9 | select CLKSRC_OF | ||
| 9 | select COMMON_CLK | 10 | select COMMON_CLK |
| 10 | select CPU_ARM926T | 11 | select CPU_ARM926T |
| 11 | select GENERIC_CLOCKEVENTS | 12 | select GENERIC_CLOCKEVENTS |
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 46cce9baa129..2df209ed1a07 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c | |||
| @@ -26,9 +26,7 @@ | |||
| 26 | #include <linux/irq.h> | 26 | #include <linux/irq.h> |
| 27 | #include <linux/dma-mapping.h> | 27 | #include <linux/dma-mapping.h> |
| 28 | #include <linux/platform_data/clk-nomadik.h> | 28 | #include <linux/platform_data/clk-nomadik.h> |
| 29 | #include <linux/platform_data/pinctrl-nomadik.h> | 29 | #include <linux/clocksource.h> |
| 30 | #include <linux/pinctrl/machine.h> | ||
| 31 | #include <linux/platform_data/clocksource-nomadik-mtu.h> | ||
| 32 | #include <linux/of_irq.h> | 30 | #include <linux/of_irq.h> |
| 33 | #include <linux/of_gpio.h> | 31 | #include <linux/of_gpio.h> |
| 34 | #include <linux/of_address.h> | 32 | #include <linux/of_address.h> |
| @@ -90,48 +88,6 @@ | |||
| 90 | #define NOMADIK_L2CC_BASE 0x10210000 /* L2 Cache controller */ | 88 | #define NOMADIK_L2CC_BASE 0x10210000 /* L2 Cache controller */ |
| 91 | #define NOMADIK_UART1_VBASE 0xF01FB000 | 89 | #define NOMADIK_UART1_VBASE 0xF01FB000 |
| 92 | 90 | ||
| 93 | static unsigned long out_low[] = { PIN_OUTPUT_LOW }; | ||
| 94 | static unsigned long out_high[] = { PIN_OUTPUT_HIGH }; | ||
| 95 | static unsigned long in_nopull[] = { PIN_INPUT_NOPULL }; | ||
| 96 | static unsigned long in_pullup[] = { PIN_INPUT_PULLUP }; | ||
| 97 | |||
| 98 | static struct pinctrl_map __initdata nhk8815_pinmap[] = { | ||
| 99 | PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"), | ||
| 100 | PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"), | ||
| 101 | /* Hog in MMC/SD card mux */ | ||
| 102 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"), | ||
| 103 | /* MCCLK */ | ||
| 104 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low), | ||
| 105 | /* MCCMD */ | ||
| 106 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup), | ||
| 107 | /* MCCMDDIR */ | ||
| 108 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high), | ||
| 109 | /* MCDAT3-0 */ | ||
| 110 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup), | ||
| 111 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup), | ||
| 112 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup), | ||
| 113 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup), | ||
| 114 | /* MCDAT0DIR */ | ||
| 115 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high), | ||
| 116 | /* MCDAT31DIR */ | ||
| 117 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high), | ||
| 118 | /* MCMSFBCLK */ | ||
| 119 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup), | ||
| 120 | /* CD input GPIO */ | ||
| 121 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull), | ||
| 122 | /* CD bias drive */ | ||
| 123 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low), | ||
| 124 | /* I2C0 */ | ||
| 125 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO62_D3", in_pullup), | ||
| 126 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO63_D2", in_pullup), | ||
| 127 | /* I2C1 */ | ||
| 128 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO53_L4", in_pullup), | ||
| 129 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO54_L3", in_pullup), | ||
| 130 | /* I2C2 */ | ||
| 131 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO73_C21", in_pullup), | ||
| 132 | PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO74_C20", in_pullup), | ||
| 133 | }; | ||
| 134 | |||
| 135 | /* This is needed for LL-debug/earlyprintk/debug-macro.S */ | 91 | /* This is needed for LL-debug/earlyprintk/debug-macro.S */ |
| 136 | static struct map_desc cpu8815_io_desc[] __initdata = { | 92 | static struct map_desc cpu8815_io_desc[] __initdata = { |
| 137 | { | 93 | { |
| @@ -171,7 +127,7 @@ static void __init cpu8815_timer_init_of(void) | |||
| 171 | /* We need this to be up now */ | 127 | /* We need this to be up now */ |
| 172 | nomadik_clk_init(); | 128 | nomadik_clk_init(); |
| 173 | 129 | ||
| 174 | mtu = of_find_node_by_path("/mtu0"); | 130 | mtu = of_find_node_by_path("/mtu@101e2000"); |
| 175 | if (!mtu) | 131 | if (!mtu) |
| 176 | return; | 132 | return; |
| 177 | base = of_iomap(mtu, 0); | 133 | base = of_iomap(mtu, 0); |
| @@ -187,7 +143,7 @@ static void __init cpu8815_timer_init_of(void) | |||
| 187 | src_cr |= SRC_CR_INIT_VAL; | 143 | src_cr |= SRC_CR_INIT_VAL; |
| 188 | writel(src_cr, base); | 144 | writel(src_cr, base); |
| 189 | 145 | ||
| 190 | nmdk_timer_init(base, irq); | 146 | clocksource_of_init(); |
| 191 | } | 147 | } |
| 192 | 148 | ||
| 193 | static struct fsmc_nand_timings cpu8815_nand_timings = { | 149 | static struct fsmc_nand_timings cpu8815_nand_timings = { |
| @@ -279,28 +235,10 @@ device_initcall(cpu8815_mmcsd_init); | |||
| 279 | 235 | ||
| 280 | /* These are mostly to get the right device names for the clock lookups */ | 236 | /* These are mostly to get the right device names for the clock lookups */ |
| 281 | static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = { | 237 | static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = { |
| 282 | OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO0_BASE, | ||
| 283 | "gpio.0", NULL), | ||
| 284 | OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO1_BASE, | ||
| 285 | "gpio.1", NULL), | ||
| 286 | OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO2_BASE, | ||
| 287 | "gpio.2", NULL), | ||
| 288 | OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO3_BASE, | ||
| 289 | "gpio.3", NULL), | ||
| 290 | OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0, | ||
| 291 | "pinctrl-stn8815", NULL), | ||
| 292 | OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART0_BASE, | ||
| 293 | "uart0", NULL), | ||
| 294 | OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART1_BASE, | ||
| 295 | "uart1", NULL), | ||
| 296 | OF_DEV_AUXDATA("arm,primecell", NOMADIK_RNG_BASE, | ||
| 297 | "rng", NULL), | ||
| 298 | OF_DEV_AUXDATA("arm,primecell", NOMADIK_RTC_BASE, | ||
| 299 | "rtc-pl031", NULL), | ||
| 300 | OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE, | 238 | OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE, |
| 301 | "fsmc-nand", &cpu8815_nand_data), | 239 | NULL, &cpu8815_nand_data), |
| 302 | OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE, | 240 | OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE, |
| 303 | "mmci", &mmcsd_plat_data), | 241 | NULL, &mmcsd_plat_data), |
| 304 | { /* sentinel */ }, | 242 | { /* sentinel */ }, |
| 305 | }; | 243 | }; |
| 306 | 244 | ||
| @@ -310,7 +248,6 @@ static void __init cpu8815_init_of(void) | |||
| 310 | /* At full speed latency must be >=2, so 0x249 in low bits */ | 248 | /* At full speed latency must be >=2, so 0x249 in low bits */ |
| 311 | l2x0_of_init(0x00730249, 0xfe000fff); | 249 | l2x0_of_init(0x00730249, 0xfe000fff); |
| 312 | #endif | 250 | #endif |
| 313 | pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap)); | ||
| 314 | of_platform_populate(NULL, of_default_bus_match_table, | 251 | of_platform_populate(NULL, of_default_bus_match_table, |
| 315 | cpu8815_auxdata_lookup, NULL); | 252 | cpu8815_auxdata_lookup, NULL); |
| 316 | } | 253 | } |
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 0346de56436c..ba6534d7f155 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c | |||
| @@ -431,15 +431,11 @@ DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); | |||
| 431 | * - Driver code is not yet migrated to use hwmod/runtime pm | 431 | * - Driver code is not yet migrated to use hwmod/runtime pm |
| 432 | * - Modules outside kernel access (to disable them by default) | 432 | * - Modules outside kernel access (to disable them by default) |
| 433 | * | 433 | * |
| 434 | * - debugss | ||
| 435 | * - mmu (gfx domain) | 434 | * - mmu (gfx domain) |
| 436 | * - cefuse | 435 | * - cefuse |
| 437 | * - usbotg_fck (its additional clock and not really a modulemode) | 436 | * - usbotg_fck (its additional clock and not really a modulemode) |
| 438 | * - ieee5000 | 437 | * - ieee5000 |
| 439 | */ | 438 | */ |
| 440 | DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, | ||
| 441 | AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, | ||
| 442 | 0x0, NULL); | ||
| 443 | 439 | ||
| 444 | DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, | 440 | DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0, |
| 445 | AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, | 441 | AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, |
| @@ -890,6 +886,42 @@ DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm", | |||
| 890 | NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); | 886 | NULL, pwmss_clk_parents, ehrpwm_tbclk_ops); |
| 891 | 887 | ||
| 892 | /* | 888 | /* |
| 889 | * debugss optional clocks | ||
| 890 | */ | ||
| 891 | DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck, | ||
| 892 | 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, | ||
| 893 | AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL); | ||
| 894 | |||
| 895 | DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck, | ||
| 896 | 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, | ||
| 897 | AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL); | ||
| 898 | |||
| 899 | static const char *stm_pmd_clock_mux_ck_parents[] = { | ||
| 900 | "dbg_sysclk_ck", "dbg_clka_ck", | ||
| 901 | }; | ||
| 902 | |||
| 903 | DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, | ||
| 904 | AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT, | ||
| 905 | AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL); | ||
| 906 | |||
| 907 | DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0, | ||
| 908 | AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, | ||
| 909 | AM33XX_TRC_PMD_CLKSEL_SHIFT, | ||
| 910 | AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL); | ||
| 911 | |||
| 912 | DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck", | ||
| 913 | &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, | ||
| 914 | AM33XX_STM_PMD_CLKDIVSEL_SHIFT, | ||
| 915 | AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, | ||
| 916 | NULL); | ||
| 917 | |||
| 918 | DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck", | ||
| 919 | &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, | ||
| 920 | AM33XX_TRC_PMD_CLKDIVSEL_SHIFT, | ||
| 921 | AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, | ||
| 922 | NULL); | ||
| 923 | |||
| 924 | /* | ||
| 893 | * clkdev | 925 | * clkdev |
| 894 | */ | 926 | */ |
| 895 | static struct omap_clk am33xx_clks[] = { | 927 | static struct omap_clk am33xx_clks[] = { |
| @@ -926,7 +958,6 @@ static struct omap_clk am33xx_clks[] = { | |||
| 926 | CLK("481cc000.d_can", NULL, &dcan0_fck), | 958 | CLK("481cc000.d_can", NULL, &dcan0_fck), |
| 927 | CLK(NULL, "dcan1_fck", &dcan1_fck), | 959 | CLK(NULL, "dcan1_fck", &dcan1_fck), |
| 928 | CLK("481d0000.d_can", NULL, &dcan1_fck), | 960 | CLK("481d0000.d_can", NULL, &dcan1_fck), |
| 929 | CLK(NULL, "debugss_ick", &debugss_ick), | ||
| 930 | CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk), | 961 | CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk), |
| 931 | CLK(NULL, "mcasp0_fck", &mcasp0_fck), | 962 | CLK(NULL, "mcasp0_fck", &mcasp0_fck), |
| 932 | CLK(NULL, "mcasp1_fck", &mcasp1_fck), | 963 | CLK(NULL, "mcasp1_fck", &mcasp1_fck), |
| @@ -969,6 +1000,13 @@ static struct omap_clk am33xx_clks[] = { | |||
| 969 | CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), | 1000 | CLK(NULL, "clkout2_div_ck", &clkout2_div_ck), |
| 970 | CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), | 1001 | CLK(NULL, "timer_32k_ck", &clkdiv32k_ick), |
| 971 | CLK(NULL, "timer_sys_ck", &sys_clkin_ck), | 1002 | CLK(NULL, "timer_sys_ck", &sys_clkin_ck), |
| 1003 | CLK(NULL, "dbg_sysclk_ck", &dbg_sysclk_ck), | ||
| 1004 | CLK(NULL, "dbg_clka_ck", &dbg_clka_ck), | ||
| 1005 | CLK(NULL, "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck), | ||
| 1006 | CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck), | ||
| 1007 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck), | ||
| 1008 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck), | ||
| 1009 | CLK(NULL, "clkout2_ck", &clkout2_ck), | ||
| 972 | CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk), | 1010 | CLK("48300200.ehrpwm", "tbclk", &ehrpwm0_tbclk), |
| 973 | CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk), | 1011 | CLK("48302200.ehrpwm", "tbclk", &ehrpwm1_tbclk), |
| 974 | CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk), | 1012 | CLK("48304200.ehrpwm", "tbclk", &ehrpwm2_tbclk), |
| @@ -982,6 +1020,7 @@ static const char *enable_init_clks[] = { | |||
| 982 | "l4hs_gclk", | 1020 | "l4hs_gclk", |
| 983 | "l4fw_gclk", | 1021 | "l4fw_gclk", |
| 984 | "l4ls_gclk", | 1022 | "l4ls_gclk", |
| 1023 | "clkout2_ck", /* Required for external peripherals like, Audio codecs */ | ||
| 985 | }; | 1024 | }; |
| 986 | 1025 | ||
| 987 | int __init am33xx_clk_init(void) | 1026 | int __init am33xx_clk_init(void) |
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index f8d1912f103e..0adb2b85f830 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig | |||
| @@ -492,6 +492,18 @@ config MACH_SMDK2416 | |||
| 492 | help | 492 | help |
| 493 | Say Y here if you are using an SMDK2416 | 493 | Say Y here if you are using an SMDK2416 |
| 494 | 494 | ||
| 495 | config MACH_S3C2416_DT | ||
| 496 | bool "Samsung S3C2416 machine using devicetree" | ||
| 497 | select CLKSRC_OF | ||
| 498 | select USE_OF | ||
| 499 | select PINCTRL | ||
| 500 | select PINCTRL_S3C24XX | ||
| 501 | help | ||
| 502 | Machine support for Samsung S3C2416 machines with device tree enabled. | ||
| 503 | Select this if a fdt blob is available for the S3C2416 SoC based board. | ||
| 504 | Note: This is under development and not all peripherals can be supported | ||
| 505 | with this machine file. | ||
| 506 | |||
| 495 | endif # CPU_S3C2416 | 507 | endif # CPU_S3C2416 |
| 496 | 508 | ||
| 497 | if CPU_S3C2440 | 509 | if CPU_S3C2440 |
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile index 6f46ecfc8396..6de730bada4d 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c24xx/Makefile | |||
| @@ -85,6 +85,7 @@ obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o | |||
| 85 | obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o | 85 | obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o |
| 86 | 86 | ||
| 87 | obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o | 87 | obj-$(CONFIG_MACH_SMDK2416) += mach-smdk2416.o |
| 88 | obj-$(CONFIG_MACH_S3C2416_DT) += mach-s3c2416-dt.o | ||
| 88 | 89 | ||
| 89 | obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o | 90 | obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o |
| 90 | obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o | 91 | obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o |
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c new file mode 100644 index 000000000000..f50454a34f72 --- /dev/null +++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c | |||
| @@ -0,0 +1,91 @@ | |||
| 1 | /* | ||
| 2 | * Samsung's S3C2416 flattened device tree enabled machine | ||
| 3 | * | ||
| 4 | * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> | ||
| 5 | * | ||
| 6 | * based on mach-exynos/mach-exynos4-dt.c | ||
| 7 | * | ||
| 8 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
| 9 | * http://www.samsung.com | ||
| 10 | * Copyright (c) 2010-2011 Linaro Ltd. | ||
| 11 | * www.linaro.org | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify | ||
| 14 | * it under the terms of the GNU General Public License version 2 as | ||
| 15 | * published by the Free Software Foundation. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/clocksource.h> | ||
| 19 | #include <linux/irqchip.h> | ||
| 20 | #include <linux/of_platform.h> | ||
| 21 | #include <linux/serial_core.h> | ||
| 22 | |||
| 23 | #include <asm/mach/arch.h> | ||
| 24 | #include <mach/map.h> | ||
| 25 | |||
| 26 | #include <plat/cpu.h> | ||
| 27 | #include <plat/pm.h> | ||
| 28 | #include <plat/regs-serial.h> | ||
| 29 | |||
| 30 | #include "common.h" | ||
| 31 | |||
| 32 | /* | ||
| 33 | * The following lookup table is used to override device names when devices | ||
| 34 | * are registered from device tree. This is temporarily added to enable | ||
| 35 | * device tree support addition for the S3C2416 architecture. | ||
| 36 | * | ||
| 37 | * For drivers that require platform data to be provided from the machine | ||
| 38 | * file, a platform data pointer can also be supplied along with the | ||
| 39 | * devices names. Usually, the platform data elements that cannot be parsed | ||
| 40 | * from the device tree by the drivers (example: function pointers) are | ||
| 41 | * supplied. But it should be noted that this is a temporary mechanism and | ||
| 42 | * at some point, the drivers should be capable of parsing all the platform | ||
| 43 | * data from the device tree. | ||
| 44 | */ | ||
| 45 | static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = { | ||
| 46 | OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART, | ||
| 47 | "s3c2440-uart.0", NULL), | ||
| 48 | OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000, | ||
| 49 | "s3c2440-uart.1", NULL), | ||
| 50 | OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000, | ||
| 51 | "s3c2440-uart.2", NULL), | ||
| 52 | OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000, | ||
| 53 | "s3c2440-uart.3", NULL), | ||
| 54 | OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0, | ||
| 55 | "s3c-sdhci.0", NULL), | ||
| 56 | OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1, | ||
| 57 | "s3c-sdhci.1", NULL), | ||
| 58 | OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC, | ||
| 59 | "s3c2440-i2c.0", NULL), | ||
| 60 | {}, | ||
| 61 | }; | ||
| 62 | |||
| 63 | static void __init s3c2416_dt_map_io(void) | ||
| 64 | { | ||
| 65 | s3c24xx_init_io(NULL, 0); | ||
| 66 | s3c24xx_init_clocks(12000000); | ||
| 67 | } | ||
| 68 | |||
| 69 | static void __init s3c2416_dt_machine_init(void) | ||
| 70 | { | ||
| 71 | of_platform_populate(NULL, of_default_bus_match_table, | ||
| 72 | s3c2416_auxdata_lookup, NULL); | ||
| 73 | |||
| 74 | s3c_pm_init(); | ||
| 75 | } | ||
| 76 | |||
| 77 | static char const *s3c2416_dt_compat[] __initdata = { | ||
| 78 | "samsung,s3c2416", | ||
| 79 | "samsung,s3c2450", | ||
| 80 | NULL | ||
| 81 | }; | ||
| 82 | |||
| 83 | DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)") | ||
| 84 | /* Maintainer: Heiko Stuebner <heiko@sntech.de> */ | ||
| 85 | .dt_compat = s3c2416_dt_compat, | ||
| 86 | .map_io = s3c2416_dt_map_io, | ||
| 87 | .init_irq = irqchip_init, | ||
| 88 | .init_machine = s3c2416_dt_machine_init, | ||
| 89 | .init_time = clocksource_of_init, | ||
| 90 | .restart = s3c2416_restart, | ||
| 91 | MACHINE_END | ||
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 65e1547678b0..db27e8eef192 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig | |||
| @@ -105,6 +105,20 @@ config MACH_ARMADILLO800EVA | |||
| 105 | select SND_SOC_WM8978 if SND_SIMPLE_CARD | 105 | select SND_SOC_WM8978 if SND_SIMPLE_CARD |
| 106 | select USE_OF | 106 | select USE_OF |
| 107 | 107 | ||
| 108 | config MACH_ARMADILLO800EVA_REFERENCE | ||
| 109 | bool "Armadillo-800 EVA board - Reference Device Tree Implementation" | ||
| 110 | depends on ARCH_R8A7740 | ||
| 111 | select ARCH_REQUIRE_GPIOLIB | ||
| 112 | select REGULATOR_FIXED_VOLTAGE if REGULATOR | ||
| 113 | select SND_SOC_WM8978 if SND_SIMPLE_CARD | ||
| 114 | select USE_OF | ||
| 115 | ---help--- | ||
| 116 | Use reference implementation of Aramdillo800 EVA board support | ||
| 117 | which makes a greater use of device tree at the expense | ||
| 118 | of not supporting a number of devices. | ||
| 119 | |||
| 120 | This is intended to aid developers | ||
| 121 | |||
| 108 | config MACH_BOCKW | 122 | config MACH_BOCKW |
| 109 | bool "BOCK-W platform" | 123 | bool "BOCK-W platform" |
| 110 | depends on ARCH_R8A7778 | 124 | depends on ARCH_R8A7778 |
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 76f1639c5945..6165a517f580 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile | |||
| @@ -44,6 +44,7 @@ obj-$(CONFIG_MACH_MARZEN) += board-marzen.o | |||
| 44 | obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o | 44 | obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o |
| 45 | obj-$(CONFIG_MACH_LAGER) += board-lager.o | 45 | obj-$(CONFIG_MACH_LAGER) += board-lager.o |
| 46 | obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o | 46 | obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o |
| 47 | obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o | ||
| 47 | obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o | 48 | obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o |
| 48 | obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o | 49 | obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o |
| 49 | obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o | 50 | obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o |
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c new file mode 100644 index 000000000000..03b85fec2ddb --- /dev/null +++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c | |||
| @@ -0,0 +1,213 @@ | |||
| 1 | /* | ||
| 2 | * armadillo 800 eva board support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Renesas Solutions Corp. | ||
| 5 | * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; version 2 of the License. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 19 | * | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/err.h> | ||
| 24 | #include <linux/kernel.h> | ||
| 25 | #include <linux/gpio.h> | ||
| 26 | #include <linux/io.h> | ||
| 27 | #include <linux/pinctrl/machine.h> | ||
| 28 | #include <mach/common.h> | ||
| 29 | #include <mach/r8a7740.h> | ||
| 30 | #include <asm/mach/arch.h> | ||
| 31 | #include <asm/hardware/cache-l2x0.h> | ||
| 32 | |||
| 33 | /* | ||
| 34 | * CON1 Camera Module | ||
| 35 | * CON2 Extension Bus | ||
| 36 | * CON3 HDMI Output | ||
| 37 | * CON4 Composite Video Output | ||
| 38 | * CON5 H-UDI JTAG | ||
| 39 | * CON6 ARM JTAG | ||
| 40 | * CON7 SD1 | ||
| 41 | * CON8 SD2 | ||
| 42 | * CON9 RTC BackUp | ||
| 43 | * CON10 Monaural Mic Input | ||
| 44 | * CON11 Stereo Headphone Output | ||
| 45 | * CON12 Audio Line Output(L) | ||
| 46 | * CON13 Audio Line Output(R) | ||
| 47 | * CON14 AWL13 Module | ||
| 48 | * CON15 Extension | ||
| 49 | * CON16 LCD1 | ||
| 50 | * CON17 LCD2 | ||
| 51 | * CON19 Power Input | ||
| 52 | * CON20 USB1 | ||
| 53 | * CON21 USB2 | ||
| 54 | * CON22 Serial | ||
| 55 | * CON23 LAN | ||
| 56 | * CON24 USB3 | ||
| 57 | * LED1 Camera LED(Yellow) | ||
| 58 | * LED2 Power LED (Green) | ||
| 59 | * ED3-LED6 User LED(Yellow) | ||
| 60 | * LED7 LAN link LED(Green) | ||
| 61 | * LED8 LAN activity LED(Yellow) | ||
| 62 | */ | ||
| 63 | |||
| 64 | /* | ||
| 65 | * DipSwitch | ||
| 66 | * | ||
| 67 | * SW1 | ||
| 68 | * | ||
| 69 | * -12345678-+---------------+---------------------------- | ||
| 70 | * 1 | boot | hermit | ||
| 71 | * 0 | boot | OS auto boot | ||
| 72 | * -12345678-+---------------+---------------------------- | ||
| 73 | * 00 | boot device | eMMC | ||
| 74 | * 10 | boot device | SDHI0 (CON7) | ||
| 75 | * 01 | boot device | - | ||
| 76 | * 11 | boot device | Extension Buss (CS0) | ||
| 77 | * -12345678-+---------------+---------------------------- | ||
| 78 | * 0 | Extension Bus | D8-D15 disable, eMMC enable | ||
| 79 | * 1 | Extension Bus | D8-D15 enable, eMMC disable | ||
| 80 | * -12345678-+---------------+---------------------------- | ||
| 81 | * 0 | SDHI1 | COM8 disable, COM14 enable | ||
| 82 | * 1 | SDHI1 | COM8 enable, COM14 disable | ||
| 83 | * -12345678-+---------------+---------------------------- | ||
| 84 | * 0 | USB0 | COM20 enable, COM24 disable | ||
| 85 | * 1 | USB0 | COM20 disable, COM24 enable | ||
| 86 | * -12345678-+---------------+---------------------------- | ||
| 87 | * 00 | JTAG | SH-X2 | ||
| 88 | * 10 | JTAG | ARM | ||
| 89 | * 01 | JTAG | - | ||
| 90 | * 11 | JTAG | Boundary Scan | ||
| 91 | *-----------+---------------+---------------------------- | ||
| 92 | */ | ||
| 93 | |||
| 94 | /* | ||
| 95 | * FSI-WM8978 | ||
| 96 | * | ||
| 97 | * this command is required when playback. | ||
| 98 | * | ||
| 99 | * # amixer set "Headphone" 50 | ||
| 100 | * | ||
| 101 | * this command is required when capture. | ||
| 102 | * | ||
| 103 | * # amixer set "Input PGA" 15 | ||
| 104 | * # amixer set "Left Input Mixer MicP" on | ||
| 105 | * # amixer set "Left Input Mixer MicN" on | ||
| 106 | * # amixer set "Right Input Mixer MicN" on | ||
| 107 | * # amixer set "Right Input Mixer MicP" on | ||
| 108 | */ | ||
| 109 | |||
| 110 | /* | ||
| 111 | * USB function | ||
| 112 | * | ||
| 113 | * When you use USB Function, | ||
| 114 | * set SW1.6 ON, and connect cable to CN24. | ||
| 115 | * | ||
| 116 | * USBF needs workaround on R8A7740 chip. | ||
| 117 | * These are a little bit complex. | ||
| 118 | * see | ||
| 119 | * usbhsf_power_ctrl() | ||
| 120 | */ | ||
| 121 | |||
| 122 | static const struct pinctrl_map eva_pinctrl_map[] = { | ||
| 123 | /* SCIFA1 */ | ||
| 124 | PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740", | ||
| 125 | "scifa1_data", "scifa1"), | ||
| 126 | }; | ||
| 127 | |||
| 128 | static void __init eva_clock_init(void) | ||
| 129 | { | ||
| 130 | struct clk *system = clk_get(NULL, "system_clk"); | ||
| 131 | struct clk *xtal1 = clk_get(NULL, "extal1"); | ||
| 132 | struct clk *usb24s = clk_get(NULL, "usb24s"); | ||
| 133 | struct clk *fsibck = clk_get(NULL, "fsibck"); | ||
| 134 | |||
| 135 | if (IS_ERR(system) || | ||
| 136 | IS_ERR(xtal1) || | ||
| 137 | IS_ERR(usb24s) || | ||
| 138 | IS_ERR(fsibck)) { | ||
| 139 | pr_err("armadillo800eva board clock init failed\n"); | ||
| 140 | goto clock_error; | ||
| 141 | } | ||
| 142 | |||
| 143 | /* armadillo 800 eva extal1 is 24MHz */ | ||
| 144 | clk_set_rate(xtal1, 24000000); | ||
| 145 | |||
| 146 | /* usb24s use extal1 (= system) clock (= 24MHz) */ | ||
| 147 | clk_set_parent(usb24s, system); | ||
| 148 | |||
| 149 | /* FSIBCK is 12.288MHz, and it is parent of FSI-B */ | ||
| 150 | clk_set_rate(fsibck, 12288000); | ||
| 151 | |||
| 152 | clock_error: | ||
| 153 | if (!IS_ERR(system)) | ||
| 154 | clk_put(system); | ||
| 155 | if (!IS_ERR(xtal1)) | ||
| 156 | clk_put(xtal1); | ||
| 157 | if (!IS_ERR(usb24s)) | ||
| 158 | clk_put(usb24s); | ||
| 159 | if (!IS_ERR(fsibck)) | ||
| 160 | clk_put(fsibck); | ||
| 161 | } | ||
| 162 | |||
| 163 | /* | ||
| 164 | * board init | ||
| 165 | */ | ||
| 166 | static void __init eva_init(void) | ||
| 167 | { | ||
| 168 | |||
| 169 | r8a7740_clock_init(MD_CK0 | MD_CK2); | ||
| 170 | eva_clock_init(); | ||
| 171 | |||
| 172 | pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); | ||
| 173 | r8a7740_pinmux_init(); | ||
| 174 | |||
| 175 | r8a7740_meram_workaround(); | ||
| 176 | |||
| 177 | /* | ||
| 178 | * Touchscreen | ||
| 179 | * TODO: Move reset GPIO over to .dts when we can reference it | ||
| 180 | */ | ||
| 181 | gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ | ||
| 182 | |||
| 183 | #ifdef CONFIG_CACHE_L2X0 | ||
| 184 | /* Early BRESP enable, Shared attribute override enable, 32K*8way */ | ||
| 185 | l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff); | ||
| 186 | #endif | ||
| 187 | |||
| 188 | r8a7740_add_standard_devices_dt(); | ||
| 189 | r8a7740_pm_init(); | ||
| 190 | } | ||
| 191 | |||
| 192 | #define RESCNT2 IOMEM(0xe6188020) | ||
| 193 | static void eva_restart(char mode, const char *cmd) | ||
| 194 | { | ||
| 195 | /* Do soft power on reset */ | ||
| 196 | writel((1 << 31), RESCNT2); | ||
| 197 | } | ||
| 198 | |||
| 199 | static const char *eva_boards_compat_dt[] __initdata = { | ||
| 200 | "renesas,armadillo800eva-reference", | ||
| 201 | NULL, | ||
| 202 | }; | ||
| 203 | |||
| 204 | DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference") | ||
| 205 | .map_io = r8a7740_map_io, | ||
| 206 | .init_early = r8a7740_init_delay, | ||
| 207 | .init_irq = r8a7740_init_irq_of, | ||
| 208 | .init_machine = eva_init, | ||
| 209 | .init_time = shmobile_timer_init, | ||
| 210 | .init_late = shmobile_init_late, | ||
| 211 | .dt_compat = eva_boards_compat_dt, | ||
| 212 | .restart = eva_restart, | ||
| 213 | MACHINE_END | ||
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h index 9c9a66ccaf6f..b34d19b5ca5c 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h | |||
| @@ -45,10 +45,13 @@ enum { | |||
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| 47 | extern void r8a7740_meram_workaround(void); | 47 | extern void r8a7740_meram_workaround(void); |
| 48 | extern void r8a7740_init_delay(void); | ||
| 48 | extern void r8a7740_init_irq(void); | 49 | extern void r8a7740_init_irq(void); |
| 50 | extern void r8a7740_init_irq_of(void); | ||
| 49 | extern void r8a7740_map_io(void); | 51 | extern void r8a7740_map_io(void); |
| 50 | extern void r8a7740_add_early_devices(void); | 52 | extern void r8a7740_add_early_devices(void); |
| 51 | extern void r8a7740_add_standard_devices(void); | 53 | extern void r8a7740_add_standard_devices(void); |
| 54 | extern void r8a7740_add_standard_devices_dt(void); | ||
| 52 | extern void r8a7740_clock_init(u8 md_ck); | 55 | extern void r8a7740_clock_init(u8 md_ck); |
| 53 | extern void r8a7740_pinmux_init(void); | 56 | extern void r8a7740_pinmux_init(void); |
| 54 | extern void r8a7740_pm_init(void); | 57 | extern void r8a7740_pm_init(void); |
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c index b741c8409a5a..8871f7717dc8 100644 --- a/arch/arm/mach-shmobile/intc-r8a7740.c +++ b/arch/arm/mach-shmobile/intc-r8a7740.c | |||
| @@ -20,19 +20,15 @@ | |||
| 20 | 20 | ||
| 21 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/irqchip.h> | ||
| 23 | #include <linux/irqchip/arm-gic.h> | 24 | #include <linux/irqchip/arm-gic.h> |
| 24 | 25 | ||
| 25 | void __init r8a7740_init_irq(void) | 26 | static void __init r8a7740_init_irq_common(void) |
| 26 | { | 27 | { |
| 27 | void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); | ||
| 28 | void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); | ||
| 29 | void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); | 28 | void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10); |
| 30 | void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); | 29 | void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10); |
| 31 | void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); | 30 | void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4); |
| 32 | 31 | ||
| 33 | /* initialize the Generic Interrupt Controller PL390 r0p0 */ | ||
| 34 | gic_init(0, 29, gic_dist_base, gic_cpu_base); | ||
| 35 | |||
| 36 | /* route signals to GIC */ | 32 | /* route signals to GIC */ |
| 37 | iowrite32(0x0, pfc_inta_ctrl); | 33 | iowrite32(0x0, pfc_inta_ctrl); |
| 38 | 34 | ||
| @@ -54,3 +50,19 @@ void __init r8a7740_init_irq(void) | |||
| 54 | iounmap(intc_msk_base); | 50 | iounmap(intc_msk_base); |
| 55 | iounmap(pfc_inta_ctrl); | 51 | iounmap(pfc_inta_ctrl); |
| 56 | } | 52 | } |
| 53 | |||
| 54 | void __init r8a7740_init_irq_of(void) | ||
| 55 | { | ||
| 56 | irqchip_init(); | ||
| 57 | r8a7740_init_irq_common(); | ||
| 58 | } | ||
| 59 | |||
| 60 | void __init r8a7740_init_irq(void) | ||
| 61 | { | ||
| 62 | void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000); | ||
| 63 | void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000); | ||
| 64 | |||
| 65 | /* initialize the Generic Interrupt Controller PL390 r0p0 */ | ||
| 66 | gic_init(0, 29, gic_dist_base, gic_cpu_base); | ||
| 67 | r8a7740_init_irq_common(); | ||
| 68 | } | ||
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 3a6b6fe7b6c0..00c5a707238b 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c | |||
| @@ -517,11 +517,7 @@ static struct platform_device ipmmu_device = { | |||
| 517 | .num_resources = ARRAY_SIZE(ipmmu_resources), | 517 | .num_resources = ARRAY_SIZE(ipmmu_resources), |
| 518 | }; | 518 | }; |
| 519 | 519 | ||
| 520 | static struct platform_device *r8a7740_early_devices[] __initdata = { | 520 | static struct platform_device *r8a7740_devices_dt[] __initdata = { |
| 521 | &irqpin0_device, | ||
| 522 | &irqpin1_device, | ||
| 523 | &irqpin2_device, | ||
| 524 | &irqpin3_device, | ||
| 525 | &scif0_device, | 521 | &scif0_device, |
| 526 | &scif1_device, | 522 | &scif1_device, |
| 527 | &scif2_device, | 523 | &scif2_device, |
| @@ -532,6 +528,13 @@ static struct platform_device *r8a7740_early_devices[] __initdata = { | |||
| 532 | &scif7_device, | 528 | &scif7_device, |
| 533 | &scifb_device, | 529 | &scifb_device, |
| 534 | &cmt10_device, | 530 | &cmt10_device, |
| 531 | }; | ||
| 532 | |||
| 533 | static struct platform_device *r8a7740_early_devices[] __initdata = { | ||
| 534 | &irqpin0_device, | ||
| 535 | &irqpin1_device, | ||
| 536 | &irqpin2_device, | ||
| 537 | &irqpin3_device, | ||
| 535 | &tmu00_device, | 538 | &tmu00_device, |
| 536 | &tmu01_device, | 539 | &tmu01_device, |
| 537 | &tmu02_device, | 540 | &tmu02_device, |
| @@ -951,6 +954,8 @@ void __init r8a7740_add_standard_devices(void) | |||
| 951 | /* add devices */ | 954 | /* add devices */ |
| 952 | platform_add_devices(r8a7740_early_devices, | 955 | platform_add_devices(r8a7740_early_devices, |
| 953 | ARRAY_SIZE(r8a7740_early_devices)); | 956 | ARRAY_SIZE(r8a7740_early_devices)); |
| 957 | platform_add_devices(r8a7740_devices_dt, | ||
| 958 | ARRAY_SIZE(r8a7740_devices_dt)); | ||
| 954 | platform_add_devices(r8a7740_late_devices, | 959 | platform_add_devices(r8a7740_late_devices, |
| 955 | ARRAY_SIZE(r8a7740_late_devices)); | 960 | ARRAY_SIZE(r8a7740_late_devices)); |
| 956 | 961 | ||
| @@ -972,6 +977,8 @@ void __init r8a7740_add_early_devices(void) | |||
| 972 | { | 977 | { |
| 973 | early_platform_add_devices(r8a7740_early_devices, | 978 | early_platform_add_devices(r8a7740_early_devices, |
| 974 | ARRAY_SIZE(r8a7740_early_devices)); | 979 | ARRAY_SIZE(r8a7740_early_devices)); |
| 980 | early_platform_add_devices(r8a7740_devices_dt, | ||
| 981 | ARRAY_SIZE(r8a7740_devices_dt)); | ||
| 975 | 982 | ||
| 976 | /* setup early console here as well */ | 983 | /* setup early console here as well */ |
| 977 | shmobile_setup_console(); | 984 | shmobile_setup_console(); |
| @@ -979,33 +986,29 @@ void __init r8a7740_add_early_devices(void) | |||
| 979 | 986 | ||
| 980 | #ifdef CONFIG_USE_OF | 987 | #ifdef CONFIG_USE_OF |
| 981 | 988 | ||
| 982 | void __init r8a7740_add_early_devices_dt(void) | ||
| 983 | { | ||
| 984 | shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ | ||
| 985 | |||
| 986 | early_platform_add_devices(r8a7740_early_devices, | ||
| 987 | ARRAY_SIZE(r8a7740_early_devices)); | ||
| 988 | |||
| 989 | /* setup early console here as well */ | ||
| 990 | shmobile_setup_console(); | ||
| 991 | } | ||
| 992 | |||
| 993 | static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = { | 989 | static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = { |
| 994 | { } | 990 | { } |
| 995 | }; | 991 | }; |
| 996 | 992 | ||
| 997 | void __init r8a7740_add_standard_devices_dt(void) | 993 | void __init r8a7740_add_standard_devices_dt(void) |
| 998 | { | 994 | { |
| 999 | /* clocks are setup late during boot in the case of DT */ | 995 | platform_add_devices(r8a7740_devices_dt, |
| 1000 | r8a7740_clock_init(0); | 996 | ARRAY_SIZE(r8a7740_devices_dt)); |
| 1001 | |||
| 1002 | platform_add_devices(r8a7740_early_devices, | ||
| 1003 | ARRAY_SIZE(r8a7740_early_devices)); | ||
| 1004 | |||
| 1005 | of_platform_populate(NULL, of_default_bus_match_table, | 997 | of_platform_populate(NULL, of_default_bus_match_table, |
| 1006 | r8a7740_auxdata_lookup, NULL); | 998 | r8a7740_auxdata_lookup, NULL); |
| 1007 | } | 999 | } |
| 1008 | 1000 | ||
| 1001 | void __init r8a7740_init_delay(void) | ||
| 1002 | { | ||
| 1003 | shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ | ||
| 1004 | }; | ||
| 1005 | |||
| 1006 | static void __init r8a7740_generic_init(void) | ||
| 1007 | { | ||
| 1008 | r8a7740_clock_init(0); | ||
| 1009 | r8a7740_add_standard_devices_dt(); | ||
| 1010 | } | ||
| 1011 | |||
| 1009 | static const char *r8a7740_boards_compat_dt[] __initdata = { | 1012 | static const char *r8a7740_boards_compat_dt[] __initdata = { |
| 1010 | "renesas,r8a7740", | 1013 | "renesas,r8a7740", |
| 1011 | NULL, | 1014 | NULL, |
| @@ -1013,9 +1016,10 @@ static const char *r8a7740_boards_compat_dt[] __initdata = { | |||
| 1013 | 1016 | ||
| 1014 | DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") | 1017 | DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)") |
| 1015 | .map_io = r8a7740_map_io, | 1018 | .map_io = r8a7740_map_io, |
| 1016 | .init_early = r8a7740_add_early_devices_dt, | 1019 | .init_early = r8a7740_init_delay, |
| 1017 | .init_irq = r8a7740_init_irq, | 1020 | .init_irq = r8a7740_init_irq_of, |
| 1018 | .init_machine = r8a7740_add_standard_devices_dt, | 1021 | .init_machine = r8a7740_generic_init, |
| 1022 | .init_time = shmobile_timer_init, | ||
| 1019 | .dt_compat = r8a7740_boards_compat_dt, | 1023 | .dt_compat = r8a7740_boards_compat_dt, |
| 1020 | MACHINE_END | 1024 | MACHINE_END |
| 1021 | 1025 | ||
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 46cca52890bc..7669a49fb6fb 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c | |||
| @@ -274,11 +274,16 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { | |||
| 274 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), | 274 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), |
| 275 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), | 275 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), |
| 276 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), | 276 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), |
| 277 | OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL), | ||
| 277 | OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", | 278 | OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", |
| 278 | &db8500_prcmu_pdata), | 279 | &db8500_prcmu_pdata), |
| 279 | OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL), | 280 | OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL), |
| 281 | OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL), | ||
| 282 | OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL), | ||
| 283 | OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0", | ||
| 284 | NULL), | ||
| 280 | /* Requires device name bindings. */ | 285 | /* Requires device name bindings. */ |
| 281 | OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE, | 286 | OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE, |
| 282 | "pinctrl-db8500", NULL), | 287 | "pinctrl-db8500", NULL), |
| 283 | /* Requires clock name and DMA bindings. */ | 288 | /* Requires clock name and DMA bindings. */ |
| 284 | OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, | 289 | OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, |
| @@ -292,6 +297,16 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { | |||
| 292 | {}, | 297 | {}, |
| 293 | }; | 298 | }; |
| 294 | 299 | ||
| 300 | static struct of_dev_auxdata u8540_auxdata_lookup[] __initdata = { | ||
| 301 | /* Requires DMA bindings. */ | ||
| 302 | OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL), | ||
| 303 | OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL), | ||
| 304 | OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL), | ||
| 305 | OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", | ||
| 306 | &db8500_prcmu_pdata), | ||
| 307 | {}, | ||
| 308 | }; | ||
| 309 | |||
| 295 | static const struct of_device_id u8500_local_bus_nodes[] = { | 310 | static const struct of_device_id u8500_local_bus_nodes[] = { |
| 296 | /* only create devices below soc node */ | 311 | /* only create devices below soc node */ |
| 297 | { .compatible = "stericsson,db8500", }, | 312 | { .compatible = "stericsson,db8500", }, |
| @@ -318,8 +333,13 @@ static void __init u8500_init_machine(void) | |||
| 318 | /* TODO: Export SoC, USB, cpu-freq and DMA40 */ | 333 | /* TODO: Export SoC, USB, cpu-freq and DMA40 */ |
| 319 | parent = u8500_of_init_devices(); | 334 | parent = u8500_of_init_devices(); |
| 320 | 335 | ||
| 321 | /* automatically probe child nodes of db8500 device */ | 336 | /* automatically probe child nodes of dbx5x0 devices */ |
| 322 | of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); | 337 | if (of_machine_is_compatible("st-ericsson,u8540")) |
| 338 | of_platform_populate(NULL, u8500_local_bus_nodes, | ||
| 339 | u8540_auxdata_lookup, parent); | ||
| 340 | else | ||
| 341 | of_platform_populate(NULL, u8500_local_bus_nodes, | ||
| 342 | u8500_auxdata_lookup, parent); | ||
| 323 | } | 343 | } |
| 324 | 344 | ||
| 325 | static const char * stericsson_dt_platform_compat[] = { | 345 | static const char * stericsson_dt_platform_compat[] = { |
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 4c0199b88a04..4130e65a0e3f 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c | |||
| @@ -97,7 +97,6 @@ static void zynq_system_reset(char mode, const char *cmd) | |||
| 97 | } | 97 | } |
| 98 | 98 | ||
| 99 | static const char * const zynq_dt_match[] = { | 99 | static const char * const zynq_dt_match[] = { |
| 100 | "xlnx,zynq-zc702", | ||
| 101 | "xlnx,zynq-7000", | 100 | "xlnx,zynq-7000", |
| 102 | NULL | 101 | NULL |
| 103 | }; | 102 | }; |
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 5286e2d333b0..1f70e84b442c 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig | |||
| @@ -4,6 +4,15 @@ | |||
| 4 | 4 | ||
| 5 | menu "Bus devices" | 5 | menu "Bus devices" |
| 6 | 6 | ||
| 7 | config IMX_WEIM | ||
| 8 | bool "Freescale EIM DRIVER" | ||
| 9 | depends on ARCH_MXC | ||
| 10 | help | ||
| 11 | Driver for i.MX6 WEIM controller. | ||
| 12 | The WEIM(Wireless External Interface Module) works like a bus. | ||
| 13 | You can attach many different devices on it, such as NOR, onenand. | ||
| 14 | But now, we only support the Parallel NOR. | ||
| 15 | |||
| 7 | config MVEBU_MBUS | 16 | config MVEBU_MBUS |
| 8 | bool | 17 | bool |
| 9 | depends on PLAT_ORION | 18 | depends on PLAT_ORION |
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 670cea443802..8947bdd0de8b 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | # Makefile for the bus drivers. | 2 | # Makefile for the bus drivers. |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-$(CONFIG_IMX_WEIM) += imx-weim.o | ||
| 5 | obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o | 6 | obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o |
| 6 | obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o | 7 | obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o |
| 7 | 8 | ||
diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c new file mode 100644 index 000000000000..349f14e886b7 --- /dev/null +++ b/drivers/bus/imx-weim.c | |||
| @@ -0,0 +1,138 @@ | |||
| 1 | /* | ||
| 2 | * EIM driver for Freescale's i.MX chips | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <linux/module.h> | ||
| 11 | #include <linux/clk.h> | ||
| 12 | #include <linux/io.h> | ||
| 13 | #include <linux/of_device.h> | ||
| 14 | |||
| 15 | struct imx_weim { | ||
| 16 | void __iomem *base; | ||
| 17 | struct clk *clk; | ||
| 18 | }; | ||
| 19 | |||
| 20 | static const struct of_device_id weim_id_table[] = { | ||
| 21 | { .compatible = "fsl,imx6q-weim", }, | ||
| 22 | {} | ||
| 23 | }; | ||
| 24 | MODULE_DEVICE_TABLE(of, weim_id_table); | ||
| 25 | |||
| 26 | #define CS_TIMING_LEN 6 | ||
| 27 | #define CS_REG_RANGE 0x18 | ||
| 28 | |||
| 29 | /* Parse and set the timing for this device. */ | ||
| 30 | static int | ||
| 31 | weim_timing_setup(struct platform_device *pdev, struct device_node *np) | ||
| 32 | { | ||
| 33 | struct imx_weim *weim = platform_get_drvdata(pdev); | ||
| 34 | u32 value[CS_TIMING_LEN]; | ||
| 35 | u32 cs_idx; | ||
| 36 | int ret; | ||
| 37 | int i; | ||
| 38 | |||
| 39 | /* get the CS index from this child node's "reg" property. */ | ||
| 40 | ret = of_property_read_u32(np, "reg", &cs_idx); | ||
| 41 | if (ret) | ||
| 42 | return ret; | ||
| 43 | |||
| 44 | /* The weim has four chip selects. */ | ||
| 45 | if (cs_idx > 3) | ||
| 46 | return -EINVAL; | ||
| 47 | |||
| 48 | ret = of_property_read_u32_array(np, "fsl,weim-cs-timing", | ||
| 49 | value, CS_TIMING_LEN); | ||
| 50 | if (ret) | ||
| 51 | return ret; | ||
| 52 | |||
| 53 | /* set the timing for WEIM */ | ||
| 54 | for (i = 0; i < CS_TIMING_LEN; i++) | ||
| 55 | writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4); | ||
| 56 | return 0; | ||
| 57 | } | ||
| 58 | |||
| 59 | static int weim_parse_dt(struct platform_device *pdev) | ||
| 60 | { | ||
| 61 | struct device_node *child; | ||
| 62 | int ret; | ||
| 63 | |||
| 64 | for_each_child_of_node(pdev->dev.of_node, child) { | ||
| 65 | if (!child->name) | ||
| 66 | continue; | ||
| 67 | |||
| 68 | ret = weim_timing_setup(pdev, child); | ||
| 69 | if (ret) { | ||
| 70 | dev_err(&pdev->dev, "%s set timing failed.\n", | ||
| 71 | child->full_name); | ||
| 72 | return ret; | ||
| 73 | } | ||
| 74 | } | ||
| 75 | |||
| 76 | ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); | ||
| 77 | if (ret) | ||
| 78 | dev_err(&pdev->dev, "%s fail to create devices.\n", | ||
| 79 | pdev->dev.of_node->full_name); | ||
| 80 | return ret; | ||
| 81 | } | ||
| 82 | |||
| 83 | static int weim_probe(struct platform_device *pdev) | ||
| 84 | { | ||
| 85 | struct imx_weim *weim; | ||
| 86 | struct resource *res; | ||
| 87 | int ret = -EINVAL; | ||
| 88 | |||
| 89 | weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL); | ||
| 90 | if (!weim) { | ||
| 91 | ret = -ENOMEM; | ||
| 92 | goto weim_err; | ||
| 93 | } | ||
| 94 | platform_set_drvdata(pdev, weim); | ||
| 95 | |||
| 96 | /* get the resource */ | ||
| 97 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 98 | weim->base = devm_ioremap_resource(&pdev->dev, res); | ||
| 99 | if (IS_ERR(weim->base)) { | ||
| 100 | ret = PTR_ERR(weim->base); | ||
| 101 | goto weim_err; | ||
| 102 | } | ||
| 103 | |||
| 104 | /* get the clock */ | ||
| 105 | weim->clk = devm_clk_get(&pdev->dev, NULL); | ||
| 106 | if (IS_ERR(weim->clk)) | ||
| 107 | goto weim_err; | ||
| 108 | |||
| 109 | ret = clk_prepare_enable(weim->clk); | ||
| 110 | if (ret) | ||
| 111 | goto weim_err; | ||
| 112 | |||
| 113 | /* parse the device node */ | ||
| 114 | ret = weim_parse_dt(pdev); | ||
| 115 | if (ret) { | ||
| 116 | clk_disable_unprepare(weim->clk); | ||
| 117 | goto weim_err; | ||
| 118 | } | ||
| 119 | |||
| 120 | dev_info(&pdev->dev, "WEIM driver registered.\n"); | ||
| 121 | return 0; | ||
| 122 | |||
| 123 | weim_err: | ||
| 124 | return ret; | ||
| 125 | } | ||
| 126 | |||
| 127 | static struct platform_driver weim_driver = { | ||
| 128 | .driver = { | ||
| 129 | .name = "imx-weim", | ||
| 130 | .of_match_table = weim_id_table, | ||
| 131 | }, | ||
| 132 | .probe = weim_probe, | ||
| 133 | }; | ||
| 134 | |||
| 135 | module_platform_driver(weim_driver); | ||
| 136 | MODULE_AUTHOR("Freescale Semiconductor Inc."); | ||
| 137 | MODULE_DESCRIPTION("i.MX EIM Controller Driver"); | ||
| 138 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 6b4c70f7d23d..6d819a37f647 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c | |||
| @@ -1,48 +1,566 @@ | |||
| 1 | /* | ||
| 2 | * Nomadik clock implementation | ||
| 3 | * Copyright (C) 2013 ST-Ericsson AB | ||
| 4 | * License terms: GNU General Public License (GPL) version 2 | ||
| 5 | * Author: Linus Walleij <linus.walleij@linaro.org> | ||
| 6 | */ | ||
| 7 | |||
| 8 | #define pr_fmt(fmt) "Nomadik SRC clocks: " fmt | ||
| 9 | |||
| 10 | #include <linux/bitops.h> | ||
| 1 | #include <linux/clk.h> | 11 | #include <linux/clk.h> |
| 2 | #include <linux/clkdev.h> | 12 | #include <linux/clkdev.h> |
| 3 | #include <linux/err.h> | 13 | #include <linux/err.h> |
| 4 | #include <linux/io.h> | 14 | #include <linux/io.h> |
| 5 | #include <linux/clk-provider.h> | 15 | #include <linux/clk-provider.h> |
| 16 | #include <linux/of.h> | ||
| 17 | #include <linux/of_address.h> | ||
| 18 | #include <linux/debugfs.h> | ||
| 19 | #include <linux/seq_file.h> | ||
| 20 | #include <linux/spinlock.h> | ||
| 21 | #include <linux/reboot.h> | ||
| 6 | 22 | ||
| 7 | /* | 23 | /* |
| 8 | * The Nomadik clock tree is described in the STN8815A12 DB V4.2 | 24 | * The Nomadik clock tree is described in the STN8815A12 DB V4.2 |
| 9 | * reference manual for the chip, page 94 ff. | 25 | * reference manual for the chip, page 94 ff. |
| 26 | * Clock IDs are in the STn8815 Reference Manual table 3, page 27. | ||
| 10 | */ | 27 | */ |
| 11 | 28 | ||
| 12 | void __init nomadik_clk_init(void) | 29 | #define SRC_CR 0x00U |
| 30 | #define SRC_XTALCR 0x0CU | ||
| 31 | #define SRC_XTALCR_XTALTIMEN BIT(20) | ||
| 32 | #define SRC_XTALCR_SXTALDIS BIT(19) | ||
| 33 | #define SRC_XTALCR_MXTALSTAT BIT(2) | ||
| 34 | #define SRC_XTALCR_MXTALEN BIT(1) | ||
| 35 | #define SRC_XTALCR_MXTALOVER BIT(0) | ||
| 36 | #define SRC_PLLCR 0x10U | ||
| 37 | #define SRC_PLLCR_PLLTIMEN BIT(29) | ||
| 38 | #define SRC_PLLCR_PLL2EN BIT(28) | ||
| 39 | #define SRC_PLLCR_PLL1STAT BIT(2) | ||
| 40 | #define SRC_PLLCR_PLL1EN BIT(1) | ||
| 41 | #define SRC_PLLCR_PLL1OVER BIT(0) | ||
| 42 | #define SRC_PLLFR 0x14U | ||
| 43 | #define SRC_PCKEN0 0x24U | ||
| 44 | #define SRC_PCKDIS0 0x28U | ||
| 45 | #define SRC_PCKENSR0 0x2CU | ||
| 46 | #define SRC_PCKSR0 0x30U | ||
| 47 | #define SRC_PCKEN1 0x34U | ||
| 48 | #define SRC_PCKDIS1 0x38U | ||
| 49 | #define SRC_PCKENSR1 0x3CU | ||
| 50 | #define SRC_PCKSR1 0x40U | ||
| 51 | |||
| 52 | /* Lock protecting the SRC_CR register */ | ||
| 53 | static DEFINE_SPINLOCK(src_lock); | ||
| 54 | /* Base address of the SRC */ | ||
| 55 | static void __iomem *src_base; | ||
| 56 | |||
| 57 | /** | ||
| 58 | * struct clk_pll1 - Nomadik PLL1 clock | ||
| 59 | * @hw: corresponding clock hardware entry | ||
| 60 | * @id: PLL instance: 1 or 2 | ||
| 61 | */ | ||
| 62 | struct clk_pll { | ||
| 63 | struct clk_hw hw; | ||
| 64 | int id; | ||
| 65 | }; | ||
| 66 | |||
| 67 | /** | ||
| 68 | * struct clk_src - Nomadik src clock | ||
| 69 | * @hw: corresponding clock hardware entry | ||
| 70 | * @id: the clock ID | ||
| 71 | * @group1: true if the clock is in group1, else it is in group0 | ||
| 72 | * @clkbit: bit 0...31 corresponding to the clock in each clock register | ||
| 73 | */ | ||
| 74 | struct clk_src { | ||
| 75 | struct clk_hw hw; | ||
| 76 | int id; | ||
| 77 | bool group1; | ||
| 78 | u32 clkbit; | ||
| 79 | }; | ||
| 80 | |||
| 81 | #define to_pll(_hw) container_of(_hw, struct clk_pll, hw) | ||
| 82 | #define to_src(_hw) container_of(_hw, struct clk_src, hw) | ||
| 83 | |||
| 84 | static int pll_clk_enable(struct clk_hw *hw) | ||
| 85 | { | ||
| 86 | struct clk_pll *pll = to_pll(hw); | ||
| 87 | u32 val; | ||
| 88 | |||
| 89 | spin_lock(&src_lock); | ||
| 90 | val = readl(src_base + SRC_PLLCR); | ||
| 91 | if (pll->id == 1) { | ||
| 92 | if (val & SRC_PLLCR_PLL1OVER) { | ||
| 93 | val |= SRC_PLLCR_PLL1EN; | ||
| 94 | writel(val, src_base + SRC_PLLCR); | ||
| 95 | } | ||
| 96 | } else if (pll->id == 2) { | ||
| 97 | val |= SRC_PLLCR_PLL2EN; | ||
| 98 | writel(val, src_base + SRC_PLLCR); | ||
| 99 | } | ||
| 100 | spin_unlock(&src_lock); | ||
| 101 | return 0; | ||
| 102 | } | ||
| 103 | |||
| 104 | static void pll_clk_disable(struct clk_hw *hw) | ||
| 105 | { | ||
| 106 | struct clk_pll *pll = to_pll(hw); | ||
| 107 | u32 val; | ||
| 108 | |||
| 109 | spin_lock(&src_lock); | ||
| 110 | val = readl(src_base + SRC_PLLCR); | ||
| 111 | if (pll->id == 1) { | ||
| 112 | if (val & SRC_PLLCR_PLL1OVER) { | ||
| 113 | val &= ~SRC_PLLCR_PLL1EN; | ||
| 114 | writel(val, src_base + SRC_PLLCR); | ||
| 115 | } | ||
| 116 | } else if (pll->id == 2) { | ||
| 117 | val &= ~SRC_PLLCR_PLL2EN; | ||
| 118 | writel(val, src_base + SRC_PLLCR); | ||
| 119 | } | ||
| 120 | spin_unlock(&src_lock); | ||
| 121 | } | ||
| 122 | |||
| 123 | static int pll_clk_is_enabled(struct clk_hw *hw) | ||
| 124 | { | ||
| 125 | struct clk_pll *pll = to_pll(hw); | ||
| 126 | u32 val; | ||
| 127 | |||
| 128 | val = readl(src_base + SRC_PLLCR); | ||
| 129 | if (pll->id == 1) { | ||
| 130 | if (val & SRC_PLLCR_PLL1OVER) | ||
| 131 | return !!(val & SRC_PLLCR_PLL1EN); | ||
| 132 | } else if (pll->id == 2) { | ||
| 133 | return !!(val & SRC_PLLCR_PLL2EN); | ||
| 134 | } | ||
| 135 | return 1; | ||
| 136 | } | ||
| 137 | |||
| 138 | static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, | ||
| 139 | unsigned long parent_rate) | ||
| 140 | { | ||
| 141 | struct clk_pll *pll = to_pll(hw); | ||
| 142 | u32 val; | ||
| 143 | |||
| 144 | val = readl(src_base + SRC_PLLFR); | ||
| 145 | |||
| 146 | if (pll->id == 1) { | ||
| 147 | u8 mul; | ||
| 148 | u8 div; | ||
| 149 | |||
| 150 | mul = (val >> 8) & 0x3FU; | ||
| 151 | mul += 2; | ||
| 152 | div = val & 0x07U; | ||
| 153 | return (parent_rate * mul) >> div; | ||
| 154 | } | ||
| 155 | |||
| 156 | if (pll->id == 2) { | ||
| 157 | u8 mul; | ||
| 158 | |||
| 159 | mul = (val >> 24) & 0x3FU; | ||
| 160 | mul += 2; | ||
| 161 | return (parent_rate * mul); | ||
| 162 | } | ||
| 163 | |||
| 164 | /* Unknown PLL */ | ||
| 165 | return 0; | ||
| 166 | } | ||
| 167 | |||
| 168 | |||
| 169 | static const struct clk_ops pll_clk_ops = { | ||
| 170 | .enable = pll_clk_enable, | ||
| 171 | .disable = pll_clk_disable, | ||
| 172 | .is_enabled = pll_clk_is_enabled, | ||
| 173 | .recalc_rate = pll_clk_recalc_rate, | ||
| 174 | }; | ||
| 175 | |||
| 176 | static struct clk * __init | ||
| 177 | pll_clk_register(struct device *dev, const char *name, | ||
| 178 | const char *parent_name, u32 id) | ||
| 13 | { | 179 | { |
| 14 | struct clk *clk; | 180 | struct clk *clk; |
| 181 | struct clk_pll *pll; | ||
| 182 | struct clk_init_data init; | ||
| 15 | 183 | ||
| 16 | clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); | 184 | if (id != 1 && id != 2) { |
| 17 | clk_register_clkdev(clk, "apb_pclk", NULL); | 185 | pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__); |
| 18 | clk_register_clkdev(clk, NULL, "gpio.0"); | 186 | return ERR_PTR(-EINVAL); |
| 19 | clk_register_clkdev(clk, NULL, "gpio.1"); | 187 | } |
| 20 | clk_register_clkdev(clk, NULL, "gpio.2"); | ||
| 21 | clk_register_clkdev(clk, NULL, "gpio.3"); | ||
| 22 | clk_register_clkdev(clk, NULL, "rng"); | ||
| 23 | clk_register_clkdev(clk, NULL, "fsmc-nand"); | ||
| 24 | 188 | ||
| 25 | /* | 189 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); |
| 26 | * The 2.4 MHz TIMCLK reference clock is active at boot time, this is | 190 | if (!pll) { |
| 27 | * actually the MXTALCLK @19.2 MHz divided by 8. This clock is used | 191 | pr_err("%s: could not allocate PLL clk\n", __func__); |
| 28 | * by the timers and watchdog. See page 105 ff. | 192 | return ERR_PTR(-ENOMEM); |
| 29 | */ | 193 | } |
| 30 | clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT, | 194 | |
| 31 | 2400000); | 195 | init.name = name; |
| 32 | clk_register_clkdev(clk, NULL, "mtu0"); | 196 | init.ops = &pll_clk_ops; |
| 33 | clk_register_clkdev(clk, NULL, "mtu1"); | 197 | init.parent_names = (parent_name ? &parent_name : NULL); |
| 198 | init.num_parents = (parent_name ? 1 : 0); | ||
| 199 | pll->hw.init = &init; | ||
| 200 | pll->id = id; | ||
| 201 | |||
| 202 | pr_debug("register PLL1 clock \"%s\"\n", name); | ||
| 203 | |||
| 204 | clk = clk_register(dev, &pll->hw); | ||
| 205 | if (IS_ERR(clk)) | ||
| 206 | kfree(pll); | ||
| 207 | |||
| 208 | return clk; | ||
| 209 | } | ||
| 210 | |||
| 211 | /* | ||
| 212 | * The Nomadik SRC clocks are gated, but not in the sense that | ||
| 213 | * you read-modify-write a register. Instead there are separate | ||
| 214 | * clock enable and clock disable registers. Writing a '1' bit in | ||
| 215 | * the enable register for a certain clock ungates that clock without | ||
| 216 | * affecting the other clocks. The disable register works the opposite | ||
| 217 | * way. | ||
| 218 | */ | ||
| 219 | |||
| 220 | static int src_clk_enable(struct clk_hw *hw) | ||
| 221 | { | ||
| 222 | struct clk_src *sclk = to_src(hw); | ||
| 223 | u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0; | ||
| 224 | u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; | ||
| 225 | |||
| 226 | writel(sclk->clkbit, src_base + enreg); | ||
| 227 | /* spin until enabled */ | ||
| 228 | while (!(readl(src_base + sreg) & sclk->clkbit)) | ||
| 229 | cpu_relax(); | ||
| 230 | return 0; | ||
| 231 | } | ||
| 232 | |||
| 233 | static void src_clk_disable(struct clk_hw *hw) | ||
| 234 | { | ||
| 235 | struct clk_src *sclk = to_src(hw); | ||
| 236 | u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0; | ||
| 237 | u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; | ||
| 238 | |||
| 239 | writel(sclk->clkbit, src_base + disreg); | ||
| 240 | /* spin until disabled */ | ||
| 241 | while (readl(src_base + sreg) & sclk->clkbit) | ||
| 242 | cpu_relax(); | ||
| 243 | } | ||
| 244 | |||
| 245 | static int src_clk_is_enabled(struct clk_hw *hw) | ||
| 246 | { | ||
| 247 | struct clk_src *sclk = to_src(hw); | ||
| 248 | u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; | ||
| 249 | u32 val = readl(src_base + sreg); | ||
| 34 | 250 | ||
| 251 | return !!(val & sclk->clkbit); | ||
| 252 | } | ||
| 253 | |||
| 254 | static unsigned long | ||
| 255 | src_clk_recalc_rate(struct clk_hw *hw, | ||
| 256 | unsigned long parent_rate) | ||
| 257 | { | ||
| 258 | return parent_rate; | ||
| 259 | } | ||
| 260 | |||
| 261 | static const struct clk_ops src_clk_ops = { | ||
| 262 | .enable = src_clk_enable, | ||
| 263 | .disable = src_clk_disable, | ||
| 264 | .is_enabled = src_clk_is_enabled, | ||
| 265 | .recalc_rate = src_clk_recalc_rate, | ||
| 266 | }; | ||
| 267 | |||
| 268 | static struct clk * __init | ||
| 269 | src_clk_register(struct device *dev, const char *name, | ||
| 270 | const char *parent_name, u8 id) | ||
| 271 | { | ||
| 272 | struct clk *clk; | ||
| 273 | struct clk_src *sclk; | ||
| 274 | struct clk_init_data init; | ||
| 275 | |||
| 276 | sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); | ||
| 277 | if (!sclk) { | ||
| 278 | pr_err("could not allocate SRC clock %s\n", | ||
| 279 | name); | ||
| 280 | return ERR_PTR(-ENOMEM); | ||
| 281 | } | ||
| 282 | init.name = name; | ||
| 283 | init.ops = &src_clk_ops; | ||
| 284 | /* Do not force-disable the static SDRAM controller */ | ||
| 285 | if (id == 2) | ||
| 286 | init.flags = CLK_IGNORE_UNUSED; | ||
| 287 | else | ||
| 288 | init.flags = 0; | ||
| 289 | init.parent_names = (parent_name ? &parent_name : NULL); | ||
| 290 | init.num_parents = (parent_name ? 1 : 0); | ||
| 291 | sclk->hw.init = &init; | ||
| 292 | sclk->id = id; | ||
| 293 | sclk->group1 = (id > 31); | ||
| 294 | sclk->clkbit = BIT(id & 0x1f); | ||
| 295 | |||
| 296 | pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n", | ||
| 297 | name, id, sclk->group1, sclk->clkbit); | ||
| 298 | |||
| 299 | clk = clk_register(dev, &sclk->hw); | ||
| 300 | if (IS_ERR(clk)) | ||
| 301 | kfree(sclk); | ||
| 302 | |||
| 303 | return clk; | ||
| 304 | } | ||
| 305 | |||
| 306 | #ifdef CONFIG_DEBUG_FS | ||
| 307 | |||
| 308 | static u32 src_pcksr0_boot; | ||
| 309 | static u32 src_pcksr1_boot; | ||
| 310 | |||
| 311 | static const char * const src_clk_names[] = { | ||
| 312 | "HCLKDMA0 ", | ||
| 313 | "HCLKSMC ", | ||
| 314 | "HCLKSDRAM ", | ||
| 315 | "HCLKDMA1 ", | ||
| 316 | "HCLKCLCD ", | ||
| 317 | "PCLKIRDA ", | ||
| 318 | "PCLKSSP ", | ||
| 319 | "PCLKUART0 ", | ||
| 320 | "PCLKSDI ", | ||
| 321 | "PCLKI2C0 ", | ||
| 322 | "PCLKI2C1 ", | ||
| 323 | "PCLKUART1 ", | ||
| 324 | "PCLMSP0 ", | ||
| 325 | "HCLKUSB ", | ||
| 326 | "HCLKDIF ", | ||
| 327 | "HCLKSAA ", | ||
| 328 | "HCLKSVA ", | ||
| 329 | "PCLKHSI ", | ||
| 330 | "PCLKXTI ", | ||
| 331 | "PCLKUART2 ", | ||
| 332 | "PCLKMSP1 ", | ||
| 333 | "PCLKMSP2 ", | ||
| 334 | "PCLKOWM ", | ||
| 335 | "HCLKHPI ", | ||
| 336 | "PCLKSKE ", | ||
| 337 | "PCLKHSEM ", | ||
| 338 | "HCLK3D ", | ||
| 339 | "HCLKHASH ", | ||
| 340 | "HCLKCRYP ", | ||
| 341 | "PCLKMSHC ", | ||
| 342 | "HCLKUSBM ", | ||
| 343 | "HCLKRNG ", | ||
| 344 | "RESERVED ", | ||
| 345 | "RESERVED ", | ||
| 346 | "RESERVED ", | ||
| 347 | "RESERVED ", | ||
| 348 | "CLDCLK ", | ||
| 349 | "IRDACLK ", | ||
| 350 | "SSPICLK ", | ||
| 351 | "UART0CLK ", | ||
| 352 | "SDICLK ", | ||
| 353 | "I2C0CLK ", | ||
| 354 | "I2C1CLK ", | ||
| 355 | "UART1CLK ", | ||
| 356 | "MSPCLK0 ", | ||
| 357 | "USBCLK ", | ||
| 358 | "DIFCLK ", | ||
| 359 | "IPI2CCLK ", | ||
| 360 | "IPBMCCLK ", | ||
| 361 | "HSICLKRX ", | ||
| 362 | "HSICLKTX ", | ||
| 363 | "UART2CLK ", | ||
| 364 | "MSPCLK1 ", | ||
| 365 | "MSPCLK2 ", | ||
| 366 | "OWMCLK ", | ||
| 367 | "RESERVED ", | ||
| 368 | "SKECLK ", | ||
| 369 | "RESERVED ", | ||
| 370 | "3DCLK ", | ||
| 371 | "PCLKMSP3 ", | ||
| 372 | "MSPCLK3 ", | ||
| 373 | "MSHCCLK ", | ||
| 374 | "USBMCLK ", | ||
| 375 | "RNGCCLK ", | ||
| 376 | }; | ||
| 377 | |||
| 378 | static int nomadik_src_clk_show(struct seq_file *s, void *what) | ||
| 379 | { | ||
| 380 | int i; | ||
| 381 | u32 src_pcksr0 = readl(src_base + SRC_PCKSR0); | ||
| 382 | u32 src_pcksr1 = readl(src_base + SRC_PCKSR1); | ||
| 383 | u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0); | ||
| 384 | u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1); | ||
| 385 | |||
| 386 | seq_printf(s, "Clock: Boot: Now: Request: ASKED:\n"); | ||
| 387 | for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) { | ||
| 388 | u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot; | ||
| 389 | u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1; | ||
| 390 | u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1; | ||
| 391 | u32 mask = BIT(i & 0x1f); | ||
| 392 | |||
| 393 | seq_printf(s, "%s %s %s %s\n", | ||
| 394 | src_clk_names[i], | ||
| 395 | (pcksrb & mask) ? "on " : "off", | ||
| 396 | (pcksr & mask) ? "on " : "off", | ||
| 397 | (pckreq & mask) ? "on " : "off"); | ||
| 398 | } | ||
| 399 | return 0; | ||
| 400 | } | ||
| 401 | |||
| 402 | static int nomadik_src_clk_open(struct inode *inode, struct file *file) | ||
| 403 | { | ||
| 404 | return single_open(file, nomadik_src_clk_show, NULL); | ||
| 405 | } | ||
| 406 | |||
| 407 | static const struct file_operations nomadik_src_clk_debugfs_ops = { | ||
| 408 | .open = nomadik_src_clk_open, | ||
| 409 | .read = seq_read, | ||
| 410 | .llseek = seq_lseek, | ||
| 411 | .release = single_release, | ||
| 412 | }; | ||
| 413 | |||
| 414 | static int __init nomadik_src_clk_init_debugfs(void) | ||
| 415 | { | ||
| 416 | src_pcksr0_boot = readl(src_base + SRC_PCKSR0); | ||
| 417 | src_pcksr1_boot = readl(src_base + SRC_PCKSR1); | ||
| 418 | debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO, | ||
| 419 | NULL, NULL, &nomadik_src_clk_debugfs_ops); | ||
| 420 | return 0; | ||
| 421 | } | ||
| 422 | |||
| 423 | module_init(nomadik_src_clk_init_debugfs); | ||
| 424 | |||
| 425 | #endif | ||
| 426 | |||
| 427 | static void __init of_nomadik_pll_setup(struct device_node *np) | ||
| 428 | { | ||
| 429 | struct clk *clk = ERR_PTR(-EINVAL); | ||
| 430 | const char *clk_name = np->name; | ||
| 431 | const char *parent_name; | ||
| 432 | u32 pll_id; | ||
| 433 | |||
| 434 | if (of_property_read_u32(np, "pll-id", &pll_id)) { | ||
| 435 | pr_err("%s: PLL \"%s\" missing pll-id property\n", | ||
| 436 | __func__, clk_name); | ||
| 437 | return; | ||
| 438 | } | ||
| 439 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 440 | clk = pll_clk_register(NULL, clk_name, parent_name, pll_id); | ||
| 441 | if (!IS_ERR(clk)) | ||
| 442 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 443 | } | ||
| 444 | |||
| 445 | static void __init of_nomadik_hclk_setup(struct device_node *np) | ||
| 446 | { | ||
| 447 | struct clk *clk = ERR_PTR(-EINVAL); | ||
| 448 | const char *clk_name = np->name; | ||
| 449 | const char *parent_name; | ||
| 450 | |||
| 451 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 35 | /* | 452 | /* |
| 36 | * At boot time, PLL2 is set to generate a set of fixed clocks, | 453 | * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4. |
| 37 | * one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD | ||
| 38 | * I2C, IrDA, USB and SSP blocks. | ||
| 39 | */ | 454 | */ |
| 40 | clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT, | 455 | clk = clk_register_divider(NULL, clk_name, parent_name, |
| 41 | 48000000); | 456 | 0, src_base + SRC_CR, |
| 42 | clk_register_clkdev(clk, NULL, "uart0"); | 457 | 13, 2, |
| 43 | clk_register_clkdev(clk, NULL, "uart1"); | 458 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
| 44 | clk_register_clkdev(clk, NULL, "mmci"); | 459 | &src_lock); |
| 45 | clk_register_clkdev(clk, NULL, "ssp"); | 460 | if (!IS_ERR(clk)) |
| 46 | clk_register_clkdev(clk, NULL, "nmk-i2c.0"); | 461 | of_clk_add_provider(np, of_clk_src_simple_get, clk); |
| 47 | clk_register_clkdev(clk, NULL, "nmk-i2c.1"); | 462 | } |
| 463 | |||
| 464 | static void __init of_nomadik_src_clk_setup(struct device_node *np) | ||
| 465 | { | ||
| 466 | struct clk *clk = ERR_PTR(-EINVAL); | ||
| 467 | const char *clk_name = np->name; | ||
| 468 | const char *parent_name; | ||
| 469 | u32 clk_id; | ||
| 470 | |||
| 471 | if (of_property_read_u32(np, "clock-id", &clk_id)) { | ||
| 472 | pr_err("%s: SRC clock \"%s\" missing clock-id property\n", | ||
| 473 | __func__, clk_name); | ||
| 474 | return; | ||
| 475 | } | ||
| 476 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 477 | clk = src_clk_register(NULL, clk_name, parent_name, clk_id); | ||
| 478 | if (!IS_ERR(clk)) | ||
| 479 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 480 | } | ||
| 481 | |||
| 482 | static const __initconst struct of_device_id nomadik_src_match[] = { | ||
| 483 | { .compatible = "stericsson,nomadik-src" }, | ||
| 484 | { /* sentinel */ } | ||
| 485 | }; | ||
| 486 | |||
| 487 | static const __initconst struct of_device_id nomadik_src_clk_match[] = { | ||
| 488 | { | ||
| 489 | .compatible = "fixed-clock", | ||
| 490 | .data = of_fixed_clk_setup, | ||
| 491 | }, | ||
| 492 | { | ||
| 493 | .compatible = "fixed-factor-clock", | ||
| 494 | .data = of_fixed_factor_clk_setup, | ||
| 495 | }, | ||
| 496 | { | ||
| 497 | .compatible = "st,nomadik-pll-clock", | ||
| 498 | .data = of_nomadik_pll_setup, | ||
| 499 | }, | ||
| 500 | { | ||
| 501 | .compatible = "st,nomadik-hclk-clock", | ||
| 502 | .data = of_nomadik_hclk_setup, | ||
| 503 | }, | ||
| 504 | { | ||
| 505 | .compatible = "st,nomadik-src-clock", | ||
| 506 | .data = of_nomadik_src_clk_setup, | ||
| 507 | }, | ||
| 508 | { /* sentinel */ } | ||
| 509 | }; | ||
| 510 | |||
| 511 | static int nomadik_clk_reboot_handler(struct notifier_block *this, | ||
| 512 | unsigned long code, | ||
| 513 | void *unused) | ||
| 514 | { | ||
| 515 | u32 val; | ||
| 516 | |||
| 517 | /* The main chrystal need to be enabled for reboot to work */ | ||
| 518 | val = readl(src_base + SRC_XTALCR); | ||
| 519 | val &= ~SRC_XTALCR_MXTALOVER; | ||
| 520 | val |= SRC_XTALCR_MXTALEN; | ||
| 521 | pr_crit("force-enabling MXTALO\n"); | ||
| 522 | writel(val, src_base + SRC_XTALCR); | ||
| 523 | return NOTIFY_OK; | ||
| 524 | } | ||
| 525 | |||
| 526 | static struct notifier_block nomadik_clk_reboot_notifier = { | ||
| 527 | .notifier_call = nomadik_clk_reboot_handler, | ||
| 528 | }; | ||
| 529 | |||
| 530 | void __init nomadik_clk_init(void) | ||
| 531 | { | ||
| 532 | struct device_node *np; | ||
| 533 | u32 val; | ||
| 534 | |||
| 535 | np = of_find_matching_node(NULL, nomadik_src_match); | ||
| 536 | if (!np) { | ||
| 537 | pr_crit("no matching node for SRC, aborting clock init\n"); | ||
| 538 | return; | ||
| 539 | } | ||
| 540 | src_base = of_iomap(np, 0); | ||
| 541 | if (!src_base) { | ||
| 542 | pr_err("%s: must have src parent node with REGS (%s)\n", | ||
| 543 | __func__, np->name); | ||
| 544 | return; | ||
| 545 | } | ||
| 546 | val = readl(src_base + SRC_XTALCR); | ||
| 547 | pr_info("SXTALO is %s\n", | ||
| 548 | (val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled"); | ||
| 549 | pr_info("MXTAL is %s\n", | ||
| 550 | (val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled"); | ||
| 551 | if (of_property_read_bool(np, "disable-sxtalo")) { | ||
| 552 | /* The machine uses an external oscillator circuit */ | ||
| 553 | val |= SRC_XTALCR_SXTALDIS; | ||
| 554 | pr_info("disabling SXTALO\n"); | ||
| 555 | } | ||
| 556 | if (of_property_read_bool(np, "disable-mxtalo")) { | ||
| 557 | /* Disable this too: also run by external oscillator */ | ||
| 558 | val |= SRC_XTALCR_MXTALOVER; | ||
| 559 | val &= ~SRC_XTALCR_MXTALEN; | ||
| 560 | pr_info("disabling MXTALO\n"); | ||
| 561 | } | ||
| 562 | writel(val, src_base + SRC_XTALCR); | ||
| 563 | register_reboot_notifier(&nomadik_clk_reboot_notifier); | ||
| 564 | |||
| 565 | of_clk_init(nomadik_src_clk_match); | ||
| 48 | } | 566 | } |
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 3c1f88868f29..addc738a06fb 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c | |||
| @@ -151,7 +151,7 @@ enum exynos4_clks { | |||
| 151 | sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, | 151 | sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, |
| 152 | sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, | 152 | sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, |
| 153 | sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp, | 153 | sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp, |
| 154 | sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, | 154 | sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d, |
| 155 | 155 | ||
| 156 | /* gate clocks */ | 156 | /* gate clocks */ |
| 157 | fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, | 157 | fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, |
| @@ -484,6 +484,9 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { | |||
| 484 | MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), | 484 | MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), |
| 485 | MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), | 485 | MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), |
| 486 | MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), | 486 | MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), |
| 487 | MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), | ||
| 488 | MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), | ||
| 489 | MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), | ||
| 487 | }; | 490 | }; |
| 488 | 491 | ||
| 489 | /* list of divider clocks supported in all exynos4 soc's */ | 492 | /* list of divider clocks supported in all exynos4 soc's */ |
| @@ -552,7 +555,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = { | |||
| 552 | /* list of divider clocks supported in exynos4210 soc */ | 555 | /* list of divider clocks supported in exynos4210 soc */ |
| 553 | struct samsung_div_clock exynos4210_div_clks[] __initdata = { | 556 | struct samsung_div_clock exynos4210_div_clks[] __initdata = { |
| 554 | DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), | 557 | DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), |
| 555 | DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4), | 558 | DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), |
| 556 | DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), | 559 | DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), |
| 557 | DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), | 560 | DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), |
| 558 | DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), | 561 | DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), |
| @@ -582,6 +585,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = { | |||
| 582 | DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), | 585 | DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), |
| 583 | DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3), | 586 | DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3), |
| 584 | DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3), | 587 | DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3), |
| 588 | DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), | ||
| 585 | }; | 589 | }; |
| 586 | 590 | ||
| 587 | /* list of gate clocks supported in all exynos4 soc's */ | 591 | /* list of gate clocks supported in all exynos4 soc's */ |
| @@ -909,6 +913,7 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { | |||
| 909 | CLK_IGNORE_UNUSED, 0), | 913 | CLK_IGNORE_UNUSED, 0), |
| 910 | GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, | 914 | GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, |
| 911 | CLK_IGNORE_UNUSED, 0), | 915 | CLK_IGNORE_UNUSED, 0), |
| 916 | GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), | ||
| 912 | }; | 917 | }; |
| 913 | 918 | ||
| 914 | /* | 919 | /* |
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c index e405531e1cc5..b9415b622f55 100644 --- a/drivers/clocksource/nomadik-mtu.c +++ b/drivers/clocksource/nomadik-mtu.c | |||
| @@ -13,6 +13,9 @@ | |||
| 13 | #include <linux/io.h> | 13 | #include <linux/io.h> |
| 14 | #include <linux/clockchips.h> | 14 | #include <linux/clockchips.h> |
| 15 | #include <linux/clocksource.h> | 15 | #include <linux/clocksource.h> |
| 16 | #include <linux/of_address.h> | ||
| 17 | #include <linux/of_irq.h> | ||
| 18 | #include <linux/of_platform.h> | ||
| 16 | #include <linux/clk.h> | 19 | #include <linux/clk.h> |
| 17 | #include <linux/jiffies.h> | 20 | #include <linux/jiffies.h> |
| 18 | #include <linux/delay.h> | 21 | #include <linux/delay.h> |
| @@ -188,22 +191,15 @@ static struct irqaction nmdk_timer_irq = { | |||
| 188 | .dev_id = &nmdk_clkevt, | 191 | .dev_id = &nmdk_clkevt, |
| 189 | }; | 192 | }; |
| 190 | 193 | ||
| 191 | void __init nmdk_timer_init(void __iomem *base, int irq) | 194 | static void __init __nmdk_timer_init(void __iomem *base, int irq, |
| 195 | struct clk *pclk, struct clk *clk) | ||
| 192 | { | 196 | { |
| 193 | unsigned long rate; | 197 | unsigned long rate; |
| 194 | struct clk *clk0, *pclk0; | ||
| 195 | 198 | ||
| 196 | mtu_base = base; | 199 | mtu_base = base; |
| 197 | 200 | ||
| 198 | pclk0 = clk_get_sys("mtu0", "apb_pclk"); | 201 | BUG_ON(clk_prepare_enable(pclk)); |
| 199 | BUG_ON(IS_ERR(pclk0)); | 202 | BUG_ON(clk_prepare_enable(clk)); |
| 200 | BUG_ON(clk_prepare(pclk0) < 0); | ||
| 201 | BUG_ON(clk_enable(pclk0) < 0); | ||
| 202 | |||
| 203 | clk0 = clk_get_sys("mtu0", NULL); | ||
| 204 | BUG_ON(IS_ERR(clk0)); | ||
| 205 | BUG_ON(clk_prepare(clk0) < 0); | ||
| 206 | BUG_ON(clk_enable(clk0) < 0); | ||
| 207 | 203 | ||
| 208 | /* | 204 | /* |
| 209 | * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz | 205 | * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz |
| @@ -213,7 +209,7 @@ void __init nmdk_timer_init(void __iomem *base, int irq) | |||
| 213 | * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer | 209 | * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer |
| 214 | * with 16 gives too low timer resolution. | 210 | * with 16 gives too low timer resolution. |
| 215 | */ | 211 | */ |
| 216 | rate = clk_get_rate(clk0); | 212 | rate = clk_get_rate(clk); |
| 217 | if (rate > 32000000) { | 213 | if (rate > 32000000) { |
| 218 | rate /= 16; | 214 | rate /= 16; |
| 219 | clk_prescale = MTU_CRn_PRESCALE_16; | 215 | clk_prescale = MTU_CRn_PRESCALE_16; |
| @@ -247,3 +243,43 @@ void __init nmdk_timer_init(void __iomem *base, int irq) | |||
| 247 | mtu_delay_timer.freq = rate; | 243 | mtu_delay_timer.freq = rate; |
| 248 | register_current_timer_delay(&mtu_delay_timer); | 244 | register_current_timer_delay(&mtu_delay_timer); |
| 249 | } | 245 | } |
| 246 | |||
| 247 | void __init nmdk_timer_init(void __iomem *base, int irq) | ||
| 248 | { | ||
| 249 | struct clk *clk0, *pclk0; | ||
| 250 | |||
| 251 | pclk0 = clk_get_sys("mtu0", "apb_pclk"); | ||
| 252 | BUG_ON(IS_ERR(pclk0)); | ||
| 253 | clk0 = clk_get_sys("mtu0", NULL); | ||
| 254 | BUG_ON(IS_ERR(clk0)); | ||
| 255 | |||
| 256 | __nmdk_timer_init(base, irq, pclk0, clk0); | ||
| 257 | } | ||
| 258 | |||
| 259 | static void __init nmdk_timer_of_init(struct device_node *node) | ||
| 260 | { | ||
| 261 | struct clk *pclk; | ||
| 262 | struct clk *clk; | ||
| 263 | void __iomem *base; | ||
| 264 | int irq; | ||
| 265 | |||
| 266 | base = of_iomap(node, 0); | ||
| 267 | if (!base) | ||
| 268 | panic("Can't remap registers"); | ||
| 269 | |||
| 270 | pclk = of_clk_get_by_name(node, "apb_pclk"); | ||
| 271 | if (IS_ERR(pclk)) | ||
| 272 | panic("could not get apb_pclk"); | ||
| 273 | |||
| 274 | clk = of_clk_get_by_name(node, "timclk"); | ||
| 275 | if (IS_ERR(clk)) | ||
| 276 | panic("could not get timclk"); | ||
| 277 | |||
| 278 | irq = irq_of_parse_and_map(node, 0); | ||
| 279 | if (irq <= 0) | ||
| 280 | panic("Can't parse IRQ"); | ||
| 281 | |||
| 282 | __nmdk_timer_init(base, irq, pclk, clk); | ||
| 283 | } | ||
| 284 | CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu", | ||
| 285 | nmdk_timer_of_init); | ||
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c index 32f480622b97..8c2777cf02f6 100644 --- a/drivers/crypto/ux500/cryp/cryp_core.c +++ b/drivers/crypto/ux500/cryp/cryp_core.c | |||
| @@ -1743,6 +1743,11 @@ static int ux500_cryp_resume(struct device *dev) | |||
| 1743 | 1743 | ||
| 1744 | static SIMPLE_DEV_PM_OPS(ux500_cryp_pm, ux500_cryp_suspend, ux500_cryp_resume); | 1744 | static SIMPLE_DEV_PM_OPS(ux500_cryp_pm, ux500_cryp_suspend, ux500_cryp_resume); |
| 1745 | 1745 | ||
| 1746 | static const struct of_device_id ux500_cryp_match[] = { | ||
| 1747 | { .compatible = "stericsson,ux500-cryp" }, | ||
| 1748 | { }, | ||
| 1749 | }; | ||
| 1750 | |||
| 1746 | static struct platform_driver cryp_driver = { | 1751 | static struct platform_driver cryp_driver = { |
| 1747 | .probe = ux500_cryp_probe, | 1752 | .probe = ux500_cryp_probe, |
| 1748 | .remove = ux500_cryp_remove, | 1753 | .remove = ux500_cryp_remove, |
| @@ -1750,6 +1755,7 @@ static struct platform_driver cryp_driver = { | |||
| 1750 | .driver = { | 1755 | .driver = { |
| 1751 | .owner = THIS_MODULE, | 1756 | .owner = THIS_MODULE, |
| 1752 | .name = "cryp1", | 1757 | .name = "cryp1", |
| 1758 | .of_match_table = ux500_cryp_match, | ||
| 1753 | .pm = &ux500_cryp_pm, | 1759 | .pm = &ux500_cryp_pm, |
| 1754 | } | 1760 | } |
| 1755 | }; | 1761 | }; |
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index cf5508967539..3b8f661d0edf 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c | |||
| @@ -1961,6 +1961,11 @@ static int ux500_hash_resume(struct device *dev) | |||
| 1961 | 1961 | ||
| 1962 | static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume); | 1962 | static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume); |
| 1963 | 1963 | ||
| 1964 | static const struct of_device_id ux500_hash_match[] = { | ||
| 1965 | { .compatible = "stericsson,ux500-hash" }, | ||
| 1966 | { }, | ||
| 1967 | }; | ||
| 1968 | |||
| 1964 | static struct platform_driver hash_driver = { | 1969 | static struct platform_driver hash_driver = { |
| 1965 | .probe = ux500_hash_probe, | 1970 | .probe = ux500_hash_probe, |
| 1966 | .remove = ux500_hash_remove, | 1971 | .remove = ux500_hash_remove, |
| @@ -1968,6 +1973,7 @@ static struct platform_driver hash_driver = { | |||
| 1968 | .driver = { | 1973 | .driver = { |
| 1969 | .owner = THIS_MODULE, | 1974 | .owner = THIS_MODULE, |
| 1970 | .name = "hash1", | 1975 | .name = "hash1", |
| 1976 | .of_match_table = ux500_hash_match, | ||
| 1971 | .pm = &ux500_hash_pm, | 1977 | .pm = &ux500_hash_pm, |
| 1972 | } | 1978 | } |
| 1973 | }; | 1979 | }; |
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 5a68e5accec1..82cec63a9011 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | */ | 18 | */ |
| 19 | 19 | ||
| 20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
| 21 | #include <linux/of.h> | ||
| 21 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
| 22 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
| 23 | #include <linux/interrupt.h> | 24 | #include <linux/interrupt.h> |
| @@ -347,8 +348,14 @@ static int intc_irqpin_probe(struct platform_device *pdev) | |||
| 347 | } | 348 | } |
| 348 | 349 | ||
| 349 | /* deal with driver instance configuration */ | 350 | /* deal with driver instance configuration */ |
| 350 | if (pdata) | 351 | if (pdata) { |
| 351 | memcpy(&p->config, pdata, sizeof(*pdata)); | 352 | memcpy(&p->config, pdata, sizeof(*pdata)); |
| 353 | } else { | ||
| 354 | of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width", | ||
| 355 | &p->config.sense_bitfield_width); | ||
| 356 | p->config.control_parent = of_property_read_bool(pdev->dev.of_node, | ||
| 357 | "control-parent"); | ||
| 358 | } | ||
| 352 | if (!p->config.sense_bitfield_width) | 359 | if (!p->config.sense_bitfield_width) |
| 353 | p->config.sense_bitfield_width = 4; /* default to 4 bits */ | 360 | p->config.sense_bitfield_width = 4; /* default to 4 bits */ |
| 354 | 361 | ||
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 34281754b629..8a4f9c5c0b8e 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c | |||
| @@ -2104,15 +2104,15 @@ static struct pinctrl_desc nmk_pinctrl_desc = { | |||
| 2104 | 2104 | ||
| 2105 | static const struct of_device_id nmk_pinctrl_match[] = { | 2105 | static const struct of_device_id nmk_pinctrl_match[] = { |
| 2106 | { | 2106 | { |
| 2107 | .compatible = "stericsson,nmk-pinctrl-stn8815", | 2107 | .compatible = "stericsson,stn8815-pinctrl", |
| 2108 | .data = (void *)PINCTRL_NMK_STN8815, | 2108 | .data = (void *)PINCTRL_NMK_STN8815, |
| 2109 | }, | 2109 | }, |
| 2110 | { | 2110 | { |
| 2111 | .compatible = "stericsson,nmk-pinctrl", | 2111 | .compatible = "stericsson,db8500-pinctrl", |
| 2112 | .data = (void *)PINCTRL_NMK_DB8500, | 2112 | .data = (void *)PINCTRL_NMK_DB8500, |
| 2113 | }, | 2113 | }, |
| 2114 | { | 2114 | { |
| 2115 | .compatible = "stericsson,nmk-pinctrl-db8540", | 2115 | .compatible = "stericsson,db8540-pinctrl", |
| 2116 | .data = (void *)PINCTRL_NMK_DB8540, | 2116 | .data = (void *)PINCTRL_NMK_DB8540, |
| 2117 | }, | 2117 | }, |
| 2118 | {}, | 2118 | {}, |
diff --git a/drivers/regulator/ab8500.c b/drivers/regulator/ab8500.c index f6656b8c28b6..a19045ee0ec4 100644 --- a/drivers/regulator/ab8500.c +++ b/drivers/regulator/ab8500.c | |||
| @@ -2901,7 +2901,7 @@ static struct of_regulator_match ab8500_regulator_match[] = { | |||
| 2901 | { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, }, | 2901 | { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, }, |
| 2902 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, }, | 2902 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, }, |
| 2903 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, }, | 2903 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, }, |
| 2904 | { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, }, | 2904 | { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, }, |
| 2905 | { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, }, | 2905 | { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, }, |
| 2906 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, }, | 2906 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, }, |
| 2907 | }; | 2907 | }; |
| @@ -2917,7 +2917,7 @@ static struct of_regulator_match ab8505_regulator_match[] = { | |||
| 2917 | { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, }, | 2917 | { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, }, |
| 2918 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, }, | 2918 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, }, |
| 2919 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, }, | 2919 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, }, |
| 2920 | { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, }, | 2920 | { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, }, |
| 2921 | { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, }, | 2921 | { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, }, |
| 2922 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, }, | 2922 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, }, |
| 2923 | }; | 2923 | }; |
| @@ -2933,7 +2933,7 @@ static struct of_regulator_match ab8540_regulator_match[] = { | |||
| 2933 | { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, }, | 2933 | { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, }, |
| 2934 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, }, | 2934 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, }, |
| 2935 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, }, | 2935 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, }, |
| 2936 | { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, }, | 2936 | { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, }, |
| 2937 | { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, }, | 2937 | { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, }, |
| 2938 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, }, | 2938 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, }, |
| 2939 | { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, }, | 2939 | { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, }, |
| @@ -2948,7 +2948,7 @@ static struct of_regulator_match ab9540_regulator_match[] = { | |||
| 2948 | { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, }, | 2948 | { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, }, |
| 2949 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, }, | 2949 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, }, |
| 2950 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, }, | 2950 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, }, |
| 2951 | { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, }, | 2951 | { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, }, |
| 2952 | { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, }, | 2952 | { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, }, |
| 2953 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, }, | 2953 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, }, |
| 2954 | }; | 2954 | }; |
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h new file mode 100644 index 000000000000..614aec417902 --- /dev/null +++ b/include/dt-bindings/clock/tegra114-car.h | |||
| @@ -0,0 +1,342 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for binding nvidia,tegra114-car. | ||
| 3 | * | ||
| 4 | * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB | ||
| 5 | * registers. These IDs often match those in the CAR's RST_DEVICES registers, | ||
| 6 | * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In | ||
| 7 | * this case, those clocks are assigned IDs above 160 in order to highlight | ||
| 8 | * this issue. Implementations that interpret these clock IDs as bit values | ||
| 9 | * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to | ||
| 10 | * explicitly handle these special cases. | ||
| 11 | * | ||
| 12 | * The balance of the clocks controlled by the CAR are assigned IDs of 160 and | ||
| 13 | * above. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H | ||
| 17 | #define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H | ||
| 18 | |||
| 19 | /* 0 */ | ||
| 20 | /* 1 */ | ||
| 21 | /* 2 */ | ||
| 22 | /* 3 */ | ||
| 23 | #define TEGRA114_CLK_RTC 4 | ||
| 24 | #define TEGRA114_CLK_TIMER 5 | ||
| 25 | #define TEGRA114_CLK_UARTA 6 | ||
| 26 | /* 7 (register bit affects uartb and vfir) */ | ||
| 27 | /* 8 */ | ||
| 28 | #define TEGRA114_CLK_SDMMC2 9 | ||
| 29 | /* 10 (register bit affects spdif_in and spdif_out) */ | ||
| 30 | #define TEGRA114_CLK_I2S1 11 | ||
| 31 | #define TEGRA114_CLK_I2C1 12 | ||
| 32 | #define TEGRA114_CLK_NDFLASH 13 | ||
| 33 | #define TEGRA114_CLK_SDMMC1 14 | ||
| 34 | #define TEGRA114_CLK_SDMMC4 15 | ||
| 35 | /* 16 */ | ||
| 36 | #define TEGRA114_CLK_PWM 17 | ||
| 37 | #define TEGRA114_CLK_I2S2 18 | ||
| 38 | #define TEGRA114_CLK_EPP 19 | ||
| 39 | /* 20 (register bit affects vi and vi_sensor) */ | ||
| 40 | #define TEGRA114_CLK_GR_2D 21 | ||
| 41 | #define TEGRA114_CLK_USBD 22 | ||
| 42 | #define TEGRA114_CLK_ISP 23 | ||
| 43 | #define TEGRA114_CLK_GR_3D 24 | ||
| 44 | /* 25 */ | ||
| 45 | #define TEGRA114_CLK_DISP2 26 | ||
| 46 | #define TEGRA114_CLK_DISP1 27 | ||
| 47 | #define TEGRA114_CLK_HOST1X 28 | ||
| 48 | #define TEGRA114_CLK_VCP 29 | ||
| 49 | #define TEGRA114_CLK_I2S0 30 | ||
| 50 | /* 31 */ | ||
| 51 | |||
| 52 | /* 32 */ | ||
| 53 | /* 33 */ | ||
| 54 | #define TEGRA114_CLK_APBDMA 34 | ||
| 55 | /* 35 */ | ||
| 56 | #define TEGRA114_CLK_KBC 36 | ||
| 57 | /* 37 */ | ||
| 58 | /* 38 */ | ||
| 59 | /* 39 (register bit affects fuse and fuse_burn) */ | ||
| 60 | #define TEGRA114_CLK_KFUSE 40 | ||
| 61 | #define TEGRA114_CLK_SBC1 41 | ||
| 62 | #define TEGRA114_CLK_NOR 42 | ||
| 63 | /* 43 */ | ||
| 64 | #define TEGRA114_CLK_SBC2 44 | ||
| 65 | /* 45 */ | ||
| 66 | #define TEGRA114_CLK_SBC3 46 | ||
| 67 | #define TEGRA114_CLK_I2C5 47 | ||
| 68 | #define TEGRA114_CLK_DSIA 48 | ||
| 69 | /* 49 */ | ||
| 70 | #define TEGRA114_CLK_MIPI 50 | ||
| 71 | #define TEGRA114_CLK_HDMI 51 | ||
| 72 | #define TEGRA114_CLK_CSI 52 | ||
| 73 | /* 53 */ | ||
| 74 | #define TEGRA114_CLK_I2C2 54 | ||
| 75 | #define TEGRA114_CLK_UARTC 55 | ||
| 76 | #define TEGRA114_CLK_MIPI_CAL 56 | ||
| 77 | #define TEGRA114_CLK_EMC 57 | ||
| 78 | #define TEGRA114_CLK_USB2 58 | ||
| 79 | #define TEGRA114_CLK_USB3 59 | ||
| 80 | /* 60 */ | ||
| 81 | #define TEGRA114_CLK_VDE 61 | ||
| 82 | #define TEGRA114_CLK_BSEA 62 | ||
| 83 | #define TEGRA114_CLK_BSEV 63 | ||
| 84 | |||
| 85 | /* 64 */ | ||
| 86 | #define TEGRA114_CLK_UARTD 65 | ||
| 87 | /* 66 */ | ||
| 88 | #define TEGRA114_CLK_I2C3 67 | ||
| 89 | #define TEGRA114_CLK_SBC4 68 | ||
| 90 | #define TEGRA114_CLK_SDMMC3 69 | ||
| 91 | /* 70 */ | ||
| 92 | #define TEGRA114_CLK_OWR 71 | ||
| 93 | /* 72 */ | ||
| 94 | #define TEGRA114_CLK_CSITE 73 | ||
| 95 | /* 74 */ | ||
| 96 | /* 75 */ | ||
| 97 | #define TEGRA114_CLK_LA 76 | ||
| 98 | #define TEGRA114_CLK_TRACE 77 | ||
| 99 | #define TEGRA114_CLK_SOC_THERM 78 | ||
| 100 | #define TEGRA114_CLK_DTV 79 | ||
| 101 | #define TEGRA114_CLK_NDSPEED 80 | ||
| 102 | #define TEGRA114_CLK_I2CSLOW 81 | ||
| 103 | #define TEGRA114_CLK_DSIB 82 | ||
| 104 | #define TEGRA114_CLK_TSEC 83 | ||
| 105 | /* 84 */ | ||
| 106 | /* 85 */ | ||
| 107 | /* 86 */ | ||
| 108 | /* 87 */ | ||
| 109 | /* 88 */ | ||
| 110 | #define TEGRA114_CLK_XUSB_HOST 89 | ||
| 111 | /* 90 */ | ||
| 112 | #define TEGRA114_CLK_MSENC 91 | ||
| 113 | #define TEGRA114_CLK_CSUS 92 | ||
| 114 | /* 93 */ | ||
| 115 | /* 94 */ | ||
| 116 | /* 95 (bit affects xusb_dev and xusb_dev_src) */ | ||
| 117 | |||
| 118 | /* 96 */ | ||
| 119 | /* 97 */ | ||
| 120 | /* 98 */ | ||
| 121 | #define TEGRA114_CLK_MSELECT 99 | ||
| 122 | #define TEGRA114_CLK_TSENSOR 100 | ||
| 123 | #define TEGRA114_CLK_I2S3 101 | ||
| 124 | #define TEGRA114_CLK_I2S4 102 | ||
| 125 | #define TEGRA114_CLK_I2C4 103 | ||
| 126 | #define TEGRA114_CLK_SBC5 104 | ||
| 127 | #define TEGRA114_CLK_SBC6 105 | ||
| 128 | #define TEGRA114_CLK_D_AUDIO 106 | ||
| 129 | #define TEGRA114_CLK_APBIF 107 | ||
| 130 | #define TEGRA114_CLK_DAM0 108 | ||
| 131 | #define TEGRA114_CLK_DAM1 109 | ||
| 132 | #define TEGRA114_CLK_DAM2 110 | ||
| 133 | #define TEGRA114_CLK_HDA2CODEC_2X 111 | ||
| 134 | /* 112 */ | ||
| 135 | #define TEGRA114_CLK_AUDIO0_2X 113 | ||
| 136 | #define TEGRA114_CLK_AUDIO1_2X 114 | ||
| 137 | #define TEGRA114_CLK_AUDIO2_2X 115 | ||
| 138 | #define TEGRA114_CLK_AUDIO3_2X 116 | ||
| 139 | #define TEGRA114_CLK_AUDIO4_2X 117 | ||
| 140 | #define TEGRA114_CLK_SPDIF_2X 118 | ||
| 141 | #define TEGRA114_CLK_ACTMON 119 | ||
| 142 | #define TEGRA114_CLK_EXTERN1 120 | ||
| 143 | #define TEGRA114_CLK_EXTERN2 121 | ||
| 144 | #define TEGRA114_CLK_EXTERN3 122 | ||
| 145 | /* 123 */ | ||
| 146 | /* 124 */ | ||
| 147 | #define TEGRA114_CLK_HDA 125 | ||
| 148 | /* 126 */ | ||
| 149 | #define TEGRA114_CLK_SE 127 | ||
| 150 | |||
| 151 | #define TEGRA114_CLK_HDA2HDMI 128 | ||
| 152 | /* 129 */ | ||
| 153 | /* 130 */ | ||
| 154 | /* 131 */ | ||
| 155 | /* 132 */ | ||
| 156 | /* 133 */ | ||
| 157 | /* 134 */ | ||
| 158 | /* 135 */ | ||
| 159 | /* 136 */ | ||
| 160 | /* 137 */ | ||
| 161 | /* 138 */ | ||
| 162 | /* 139 */ | ||
| 163 | /* 140 */ | ||
| 164 | /* 141 */ | ||
| 165 | /* 142 */ | ||
| 166 | /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ | ||
| 167 | /* xusb_host_src and xusb_ss_src) */ | ||
| 168 | #define TEGRA114_CLK_CILAB 144 | ||
| 169 | #define TEGRA114_CLK_CILCD 145 | ||
| 170 | #define TEGRA114_CLK_CILE 146 | ||
| 171 | #define TEGRA114_CLK_DSIALP 147 | ||
| 172 | #define TEGRA114_CLK_DSIBLP 148 | ||
| 173 | /* 149 */ | ||
| 174 | #define TEGRA114_CLK_DDS 150 | ||
| 175 | /* 151 */ | ||
| 176 | #define TEGRA114_CLK_DP2 152 | ||
| 177 | #define TEGRA114_CLK_AMX 153 | ||
| 178 | #define TEGRA114_CLK_ADX 154 | ||
| 179 | /* 155 (bit affects dfll_ref and dfll_soc) */ | ||
| 180 | #define TEGRA114_CLK_XUSB_SS 156 | ||
| 181 | /* 157 */ | ||
| 182 | /* 158 */ | ||
| 183 | /* 159 */ | ||
| 184 | |||
| 185 | /* 160 */ | ||
| 186 | /* 161 */ | ||
| 187 | /* 162 */ | ||
| 188 | /* 163 */ | ||
| 189 | /* 164 */ | ||
| 190 | /* 165 */ | ||
| 191 | /* 166 */ | ||
| 192 | /* 167 */ | ||
| 193 | /* 168 */ | ||
| 194 | /* 169 */ | ||
| 195 | /* 170 */ | ||
| 196 | /* 171 */ | ||
| 197 | /* 172 */ | ||
| 198 | /* 173 */ | ||
| 199 | /* 174 */ | ||
| 200 | /* 175 */ | ||
| 201 | /* 176 */ | ||
| 202 | /* 177 */ | ||
| 203 | /* 178 */ | ||
| 204 | /* 179 */ | ||
| 205 | /* 180 */ | ||
| 206 | /* 181 */ | ||
| 207 | /* 182 */ | ||
| 208 | /* 183 */ | ||
| 209 | /* 184 */ | ||
| 210 | /* 185 */ | ||
| 211 | /* 186 */ | ||
| 212 | /* 187 */ | ||
| 213 | /* 188 */ | ||
| 214 | /* 189 */ | ||
| 215 | /* 190 */ | ||
| 216 | /* 191 */ | ||
| 217 | |||
| 218 | #define TEGRA114_CLK_UARTB 192 | ||
| 219 | #define TEGRA114_CLK_VFIR 193 | ||
| 220 | #define TEGRA114_CLK_SPDIF_IN 194 | ||
| 221 | #define TEGRA114_CLK_SPDIF_OUT 195 | ||
| 222 | #define TEGRA114_CLK_VI 196 | ||
| 223 | #define TEGRA114_CLK_VI_SENSOR 197 | ||
| 224 | #define TEGRA114_CLK_FUSE 198 | ||
| 225 | #define TEGRA114_CLK_FUSE_BURN 199 | ||
| 226 | #define TEGRA114_CLK_CLK_32K 200 | ||
| 227 | #define TEGRA114_CLK_CLK_M 201 | ||
| 228 | #define TEGRA114_CLK_CLK_M_DIV2 202 | ||
| 229 | #define TEGRA114_CLK_CLK_M_DIV4 203 | ||
| 230 | #define TEGRA114_CLK_PLL_REF 204 | ||
| 231 | #define TEGRA114_CLK_PLL_C 205 | ||
| 232 | #define TEGRA114_CLK_PLL_C_OUT1 206 | ||
| 233 | #define TEGRA114_CLK_PLL_C2 207 | ||
| 234 | #define TEGRA114_CLK_PLL_C3 208 | ||
| 235 | #define TEGRA114_CLK_PLL_M 209 | ||
| 236 | #define TEGRA114_CLK_PLL_M_OUT1 210 | ||
| 237 | #define TEGRA114_CLK_PLL_P 211 | ||
| 238 | #define TEGRA114_CLK_PLL_P_OUT1 212 | ||
| 239 | #define TEGRA114_CLK_PLL_P_OUT2 213 | ||
| 240 | #define TEGRA114_CLK_PLL_P_OUT3 214 | ||
| 241 | #define TEGRA114_CLK_PLL_P_OUT4 215 | ||
| 242 | #define TEGRA114_CLK_PLL_A 216 | ||
| 243 | #define TEGRA114_CLK_PLL_A_OUT0 217 | ||
| 244 | #define TEGRA114_CLK_PLL_D 218 | ||
| 245 | #define TEGRA114_CLK_PLL_D_OUT0 219 | ||
| 246 | #define TEGRA114_CLK_PLL_D2 220 | ||
| 247 | #define TEGRA114_CLK_PLL_D2_OUT0 221 | ||
| 248 | #define TEGRA114_CLK_PLL_U 222 | ||
| 249 | #define TEGRA114_CLK_PLL_U_480M 223 | ||
| 250 | |||
| 251 | #define TEGRA114_CLK_PLL_U_60M 224 | ||
| 252 | #define TEGRA114_CLK_PLL_U_48M 225 | ||
| 253 | #define TEGRA114_CLK_PLL_U_12M 226 | ||
| 254 | #define TEGRA114_CLK_PLL_X 227 | ||
| 255 | #define TEGRA114_CLK_PLL_X_OUT0 228 | ||
| 256 | #define TEGRA114_CLK_PLL_RE_VCO 229 | ||
| 257 | #define TEGRA114_CLK_PLL_RE_OUT 230 | ||
| 258 | #define TEGRA114_CLK_PLL_E_OUT0 231 | ||
| 259 | #define TEGRA114_CLK_SPDIF_IN_SYNC 232 | ||
| 260 | #define TEGRA114_CLK_I2S0_SYNC 233 | ||
| 261 | #define TEGRA114_CLK_I2S1_SYNC 234 | ||
| 262 | #define TEGRA114_CLK_I2S2_SYNC 235 | ||
| 263 | #define TEGRA114_CLK_I2S3_SYNC 236 | ||
| 264 | #define TEGRA114_CLK_I2S4_SYNC 237 | ||
| 265 | #define TEGRA114_CLK_VIMCLK_SYNC 238 | ||
| 266 | #define TEGRA114_CLK_AUDIO0 239 | ||
| 267 | #define TEGRA114_CLK_AUDIO1 240 | ||
| 268 | #define TEGRA114_CLK_AUDIO2 241 | ||
| 269 | #define TEGRA114_CLK_AUDIO3 242 | ||
| 270 | #define TEGRA114_CLK_AUDIO4 243 | ||
| 271 | #define TEGRA114_CLK_SPDIF 244 | ||
| 272 | #define TEGRA114_CLK_CLK_OUT_1 245 | ||
| 273 | #define TEGRA114_CLK_CLK_OUT_2 246 | ||
| 274 | #define TEGRA114_CLK_CLK_OUT_3 247 | ||
| 275 | #define TEGRA114_CLK_BLINK 248 | ||
| 276 | /* 249 */ | ||
| 277 | /* 250 */ | ||
| 278 | /* 251 */ | ||
| 279 | #define TEGRA114_CLK_XUSB_HOST_SRC 252 | ||
| 280 | #define TEGRA114_CLK_XUSB_FALCON_SRC 253 | ||
| 281 | #define TEGRA114_CLK_XUSB_FS_SRC 254 | ||
| 282 | #define TEGRA114_CLK_XUSB_SS_SRC 255 | ||
| 283 | |||
| 284 | #define TEGRA114_CLK_XUSB_DEV_SRC 256 | ||
| 285 | #define TEGRA114_CLK_XUSB_DEV 257 | ||
| 286 | #define TEGRA114_CLK_XUSB_HS_SRC 258 | ||
| 287 | #define TEGRA114_CLK_SCLK 259 | ||
| 288 | #define TEGRA114_CLK_HCLK 260 | ||
| 289 | #define TEGRA114_CLK_PCLK 261 | ||
| 290 | #define TEGRA114_CLK_CCLK_G 262 | ||
| 291 | #define TEGRA114_CLK_CCLK_LP 263 | ||
| 292 | /* 264 */ | ||
| 293 | /* 265 */ | ||
| 294 | /* 266 */ | ||
| 295 | /* 267 */ | ||
| 296 | /* 268 */ | ||
| 297 | /* 269 */ | ||
| 298 | /* 270 */ | ||
| 299 | /* 271 */ | ||
| 300 | /* 272 */ | ||
| 301 | /* 273 */ | ||
| 302 | /* 274 */ | ||
| 303 | /* 275 */ | ||
| 304 | /* 276 */ | ||
| 305 | /* 277 */ | ||
| 306 | /* 278 */ | ||
| 307 | /* 279 */ | ||
| 308 | /* 280 */ | ||
| 309 | /* 281 */ | ||
| 310 | /* 282 */ | ||
| 311 | /* 283 */ | ||
| 312 | /* 284 */ | ||
| 313 | /* 285 */ | ||
| 314 | /* 286 */ | ||
| 315 | /* 287 */ | ||
| 316 | |||
| 317 | /* 288 */ | ||
| 318 | /* 289 */ | ||
| 319 | /* 290 */ | ||
| 320 | /* 291 */ | ||
| 321 | /* 292 */ | ||
| 322 | /* 293 */ | ||
| 323 | /* 294 */ | ||
| 324 | /* 295 */ | ||
| 325 | /* 296 */ | ||
| 326 | /* 297 */ | ||
| 327 | /* 298 */ | ||
| 328 | /* 299 */ | ||
| 329 | #define TEGRA114_CLK_AUDIO0_MUX 300 | ||
| 330 | #define TEGRA114_CLK_AUDIO1_MUX 301 | ||
| 331 | #define TEGRA114_CLK_AUDIO2_MUX 302 | ||
| 332 | #define TEGRA114_CLK_AUDIO3_MUX 303 | ||
| 333 | #define TEGRA114_CLK_AUDIO4_MUX 304 | ||
| 334 | #define TEGRA114_CLK_SPDIF_MUX 305 | ||
| 335 | #define TEGRA114_CLK_CLK_OUT_1_MUX 306 | ||
| 336 | #define TEGRA114_CLK_CLK_OUT_2_MUX 307 | ||
| 337 | #define TEGRA114_CLK_CLK_OUT_3_MUX 308 | ||
| 338 | #define TEGRA114_CLK_DSIA_MUX 309 | ||
| 339 | #define TEGRA114_CLK_DSIB_MUX 310 | ||
| 340 | #define TEGRA114_CLK_CLK_MAX 311 | ||
| 341 | |||
| 342 | #endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ | ||
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h new file mode 100644 index 000000000000..a1ae9a8fdd6c --- /dev/null +++ b/include/dt-bindings/clock/tegra20-car.h | |||
| @@ -0,0 +1,158 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for binding nvidia,tegra20-car. | ||
| 3 | * | ||
| 4 | * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB | ||
| 5 | * registers. These IDs often match those in the CAR's RST_DEVICES registers, | ||
| 6 | * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In | ||
| 7 | * this case, those clocks are assigned IDs above 95 in order to highlight | ||
| 8 | * this issue. Implementations that interpret these clock IDs as bit values | ||
| 9 | * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to | ||
| 10 | * explicitly handle these special cases. | ||
| 11 | * | ||
| 12 | * The balance of the clocks controlled by the CAR are assigned IDs of 96 and | ||
| 13 | * above. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H | ||
| 17 | #define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H | ||
| 18 | |||
| 19 | #define TEGRA20_CLK_CPU 0 | ||
| 20 | /* 1 */ | ||
| 21 | /* 2 */ | ||
| 22 | #define TEGRA20_CLK_AC97 3 | ||
| 23 | #define TEGRA20_CLK_RTC 4 | ||
| 24 | #define TEGRA20_CLK_TIMER 5 | ||
| 25 | #define TEGRA20_CLK_UARTA 6 | ||
| 26 | /* 7 (register bit affects uart2 and vfir) */ | ||
| 27 | #define TEGRA20_CLK_GPIO 8 | ||
| 28 | #define TEGRA20_CLK_SDMMC2 9 | ||
| 29 | /* 10 (register bit affects spdif_in and spdif_out) */ | ||
| 30 | #define TEGRA20_CLK_I2S1 11 | ||
| 31 | #define TEGRA20_CLK_I2C1 12 | ||
| 32 | #define TEGRA20_CLK_NDFLASH 13 | ||
| 33 | #define TEGRA20_CLK_SDMMC1 14 | ||
| 34 | #define TEGRA20_CLK_SDMMC4 15 | ||
| 35 | #define TEGRA20_CLK_TWC 16 | ||
| 36 | #define TEGRA20_CLK_PWM 17 | ||
| 37 | #define TEGRA20_CLK_I2S2 18 | ||
| 38 | #define TEGRA20_CLK_EPP 19 | ||
| 39 | /* 20 (register bit affects vi and vi_sensor) */ | ||
| 40 | #define TEGRA20_CLK_GR2D 21 | ||
| 41 | #define TEGRA20_CLK_USBD 22 | ||
| 42 | #define TEGRA20_CLK_ISP 23 | ||
| 43 | #define TEGRA20_CLK_GR3D 24 | ||
| 44 | #define TEGRA20_CLK_IDE 25 | ||
| 45 | #define TEGRA20_CLK_DISP2 26 | ||
| 46 | #define TEGRA20_CLK_DISP1 27 | ||
| 47 | #define TEGRA20_CLK_HOST1X 28 | ||
| 48 | #define TEGRA20_CLK_VCP 29 | ||
| 49 | /* 30 */ | ||
| 50 | #define TEGRA20_CLK_CACHE2 31 | ||
| 51 | |||
| 52 | #define TEGRA20_CLK_MEM 32 | ||
| 53 | #define TEGRA20_CLK_AHBDMA 33 | ||
| 54 | #define TEGRA20_CLK_APBDMA 34 | ||
| 55 | /* 35 */ | ||
| 56 | #define TEGRA20_CLK_KBC 36 | ||
| 57 | #define TEGRA20_CLK_STAT_MON 37 | ||
| 58 | #define TEGRA20_CLK_PMC 38 | ||
| 59 | #define TEGRA20_CLK_FUSE 39 | ||
| 60 | #define TEGRA20_CLK_KFUSE 40 | ||
| 61 | #define TEGRA20_CLK_SBC1 41 | ||
| 62 | #define TEGRA20_CLK_NOR 42 | ||
| 63 | #define TEGRA20_CLK_SPI 43 | ||
| 64 | #define TEGRA20_CLK_SBC2 44 | ||
| 65 | #define TEGRA20_CLK_XIO 45 | ||
| 66 | #define TEGRA20_CLK_SBC3 46 | ||
| 67 | #define TEGRA20_CLK_DVC 47 | ||
| 68 | #define TEGRA20_CLK_DSI 48 | ||
| 69 | /* 49 (register bit affects tvo and cve) */ | ||
| 70 | #define TEGRA20_CLK_MIPI 50 | ||
| 71 | #define TEGRA20_CLK_HDMI 51 | ||
| 72 | #define TEGRA20_CLK_CSI 52 | ||
| 73 | #define TEGRA20_CLK_TVDAC 53 | ||
| 74 | #define TEGRA20_CLK_I2C2 54 | ||
| 75 | #define TEGRA20_CLK_UARTC 55 | ||
| 76 | /* 56 */ | ||
| 77 | #define TEGRA20_CLK_EMC 57 | ||
| 78 | #define TEGRA20_CLK_USB2 58 | ||
| 79 | #define TEGRA20_CLK_USB3 59 | ||
| 80 | #define TEGRA20_CLK_MPE 60 | ||
| 81 | #define TEGRA20_CLK_VDE 61 | ||
| 82 | #define TEGRA20_CLK_BSEA 62 | ||
| 83 | #define TEGRA20_CLK_BSEV 63 | ||
| 84 | |||
| 85 | #define TEGRA20_CLK_SPEEDO 64 | ||
| 86 | #define TEGRA20_CLK_UARTD 65 | ||
| 87 | #define TEGRA20_CLK_UARTE 66 | ||
| 88 | #define TEGRA20_CLK_I2C3 67 | ||
| 89 | #define TEGRA20_CLK_SBC4 68 | ||
| 90 | #define TEGRA20_CLK_SDMMC3 69 | ||
| 91 | #define TEGRA20_CLK_PEX 70 | ||
| 92 | #define TEGRA20_CLK_OWR 71 | ||
| 93 | #define TEGRA20_CLK_AFI 72 | ||
| 94 | #define TEGRA20_CLK_CSITE 73 | ||
| 95 | #define TEGRA20_CLK_PCIE_XCLK 74 | ||
| 96 | #define TEGRA20_CLK_AVPUCQ 75 | ||
| 97 | #define TEGRA20_CLK_LA 76 | ||
| 98 | /* 77 */ | ||
| 99 | /* 78 */ | ||
| 100 | /* 79 */ | ||
| 101 | /* 80 */ | ||
| 102 | /* 81 */ | ||
| 103 | /* 82 */ | ||
| 104 | /* 83 */ | ||
| 105 | #define TEGRA20_CLK_IRAMA 84 | ||
| 106 | #define TEGRA20_CLK_IRAMB 85 | ||
| 107 | #define TEGRA20_CLK_IRAMC 86 | ||
| 108 | #define TEGRA20_CLK_IRAMD 87 | ||
| 109 | #define TEGRA20_CLK_CRAM2 88 | ||
| 110 | #define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ | ||
| 111 | #define TEGRA20_CLK_CLK_D 90 | ||
| 112 | /* 91 */ | ||
| 113 | #define TEGRA20_CLK_CSUS 92 | ||
| 114 | #define TEGRA20_CLK_CDEV2 93 | ||
| 115 | #define TEGRA20_CLK_CDEV1 94 | ||
| 116 | /* 95 */ | ||
| 117 | |||
| 118 | #define TEGRA20_CLK_UARTB 96 | ||
| 119 | #define TEGRA20_CLK_VFIR 97 | ||
| 120 | #define TEGRA20_CLK_SPDIF_IN 98 | ||
| 121 | #define TEGRA20_CLK_SPDIF_OUT 99 | ||
| 122 | #define TEGRA20_CLK_VI 100 | ||
| 123 | #define TEGRA20_CLK_VI_SENSOR 101 | ||
| 124 | #define TEGRA20_CLK_TVO 102 | ||
| 125 | #define TEGRA20_CLK_CVE 103 | ||
| 126 | #define TEGRA20_CLK_OSC 104 | ||
| 127 | #define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ | ||
| 128 | #define TEGRA20_CLK_CLK_M 106 | ||
| 129 | #define TEGRA20_CLK_SCLK 107 | ||
| 130 | #define TEGRA20_CLK_CCLK 108 | ||
| 131 | #define TEGRA20_CLK_HCLK 109 | ||
| 132 | #define TEGRA20_CLK_PCLK 110 | ||
| 133 | #define TEGRA20_CLK_BLINK 111 | ||
| 134 | #define TEGRA20_CLK_PLL_A 112 | ||
| 135 | #define TEGRA20_CLK_PLL_A_OUT0 113 | ||
| 136 | #define TEGRA20_CLK_PLL_C 114 | ||
| 137 | #define TEGRA20_CLK_PLL_C_OUT1 115 | ||
| 138 | #define TEGRA20_CLK_PLL_D 116 | ||
| 139 | #define TEGRA20_CLK_PLL_D_OUT0 117 | ||
| 140 | #define TEGRA20_CLK_PLL_E 118 | ||
| 141 | #define TEGRA20_CLK_PLL_M 119 | ||
| 142 | #define TEGRA20_CLK_PLL_M_OUT1 120 | ||
| 143 | #define TEGRA20_CLK_PLL_P 121 | ||
| 144 | #define TEGRA20_CLK_PLL_P_OUT1 122 | ||
| 145 | #define TEGRA20_CLK_PLL_P_OUT2 123 | ||
| 146 | #define TEGRA20_CLK_PLL_P_OUT3 124 | ||
| 147 | #define TEGRA20_CLK_PLL_P_OUT4 125 | ||
| 148 | #define TEGRA20_CLK_PLL_S 126 | ||
| 149 | #define TEGRA20_CLK_PLL_U 127 | ||
| 150 | |||
| 151 | #define TEGRA20_CLK_PLL_X 128 | ||
| 152 | #define TEGRA20_CLK_COP 129 /* a/k/a avp */ | ||
| 153 | #define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ | ||
| 154 | #define TEGRA20_CLK_PLL_REF 131 | ||
| 155 | #define TEGRA20_CLK_TWD 132 | ||
| 156 | #define TEGRA20_CLK_CLK_MAX 133 | ||
| 157 | |||
| 158 | #endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */ | ||
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h new file mode 100644 index 000000000000..e40fae8f9a8d --- /dev/null +++ b/include/dt-bindings/clock/tegra30-car.h | |||
| @@ -0,0 +1,265 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for binding nvidia,tegra30-car. | ||
| 3 | * | ||
| 4 | * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB | ||
| 5 | * registers. These IDs often match those in the CAR's RST_DEVICES registers, | ||
| 6 | * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In | ||
| 7 | * this case, those clocks are assigned IDs above 160 in order to highlight | ||
| 8 | * this issue. Implementations that interpret these clock IDs as bit values | ||
| 9 | * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to | ||
| 10 | * explicitly handle these special cases. | ||
| 11 | * | ||
| 12 | * The balance of the clocks controlled by the CAR are assigned IDs of 160 and | ||
| 13 | * above. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H | ||
| 17 | #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H | ||
| 18 | |||
| 19 | #define TEGRA30_CLK_CPU 0 | ||
| 20 | /* 1 */ | ||
| 21 | /* 2 */ | ||
| 22 | /* 3 */ | ||
| 23 | #define TEGRA30_CLK_RTC 4 | ||
| 24 | #define TEGRA30_CLK_TIMER 5 | ||
| 25 | #define TEGRA30_CLK_UARTA 6 | ||
| 26 | /* 7 (register bit affects uartb and vfir) */ | ||
| 27 | #define TEGRA30_CLK_GPIO 8 | ||
| 28 | #define TEGRA30_CLK_SDMMC2 9 | ||
| 29 | /* 10 (register bit affects spdif_in and spdif_out) */ | ||
| 30 | #define TEGRA30_CLK_I2S1 11 | ||
| 31 | #define TEGRA30_CLK_I2C1 12 | ||
| 32 | #define TEGRA30_CLK_NDFLASH 13 | ||
| 33 | #define TEGRA30_CLK_SDMMC1 14 | ||
| 34 | #define TEGRA30_CLK_SDMMC4 15 | ||
| 35 | /* 16 */ | ||
| 36 | #define TEGRA30_CLK_PWM 17 | ||
| 37 | #define TEGRA30_CLK_I2S2 18 | ||
| 38 | #define TEGRA30_CLK_EPP 19 | ||
| 39 | /* 20 (register bit affects vi and vi_sensor) */ | ||
| 40 | #define TEGRA30_CLK_GR2D 21 | ||
| 41 | #define TEGRA30_CLK_USBD 22 | ||
| 42 | #define TEGRA30_CLK_ISP 23 | ||
| 43 | #define TEGRA30_CLK_GR3D 24 | ||
| 44 | /* 25 */ | ||
| 45 | #define TEGRA30_CLK_DISP2 26 | ||
| 46 | #define TEGRA30_CLK_DISP1 27 | ||
| 47 | #define TEGRA30_CLK_HOST1X 28 | ||
| 48 | #define TEGRA30_CLK_VCP 29 | ||
| 49 | #define TEGRA30_CLK_I2S0 30 | ||
| 50 | #define TEGRA30_CLK_COP_CACHE 31 | ||
| 51 | |||
| 52 | #define TEGRA30_CLK_MC 32 | ||
| 53 | #define TEGRA30_CLK_AHBDMA 33 | ||
| 54 | #define TEGRA30_CLK_APBDMA 34 | ||
| 55 | /* 35 */ | ||
| 56 | #define TEGRA30_CLK_KBC 36 | ||
| 57 | #define TEGRA30_CLK_STATMON 37 | ||
| 58 | #define TEGRA30_CLK_PMC 38 | ||
| 59 | /* 39 (register bit affects fuse and fuse_burn) */ | ||
| 60 | #define TEGRA30_CLK_KFUSE 40 | ||
| 61 | #define TEGRA30_CLK_SBC1 41 | ||
| 62 | #define TEGRA30_CLK_NOR 42 | ||
| 63 | /* 43 */ | ||
| 64 | #define TEGRA30_CLK_SBC2 44 | ||
| 65 | /* 45 */ | ||
| 66 | #define TEGRA30_CLK_SBC3 46 | ||
| 67 | #define TEGRA30_CLK_I2C5 47 | ||
| 68 | #define TEGRA30_CLK_DSIA 48 | ||
| 69 | /* 49 (register bit affects cve and tvo) */ | ||
| 70 | #define TEGRA30_CLK_MIPI 50 | ||
| 71 | #define TEGRA30_CLK_HDMI 51 | ||
| 72 | #define TEGRA30_CLK_CSI 52 | ||
| 73 | #define TEGRA30_CLK_TVDAC 53 | ||
| 74 | #define TEGRA30_CLK_I2C2 54 | ||
| 75 | #define TEGRA30_CLK_UARTC 55 | ||
| 76 | /* 56 */ | ||
| 77 | #define TEGRA30_CLK_EMC 57 | ||
| 78 | #define TEGRA30_CLK_USB2 58 | ||
| 79 | #define TEGRA30_CLK_USB3 59 | ||
| 80 | #define TEGRA30_CLK_MPE 60 | ||
| 81 | #define TEGRA30_CLK_VDE 61 | ||
| 82 | #define TEGRA30_CLK_BSEA 62 | ||
| 83 | #define TEGRA30_CLK_BSEV 63 | ||
| 84 | |||
| 85 | #define TEGRA30_CLK_SPEEDO 64 | ||
| 86 | #define TEGRA30_CLK_UARTD 65 | ||
| 87 | #define TEGRA30_CLK_UARTE 66 | ||
| 88 | #define TEGRA30_CLK_I2C3 67 | ||
| 89 | #define TEGRA30_CLK_SBC4 68 | ||
| 90 | #define TEGRA30_CLK_SDMMC3 69 | ||
| 91 | #define TEGRA30_CLK_PCIE 70 | ||
| 92 | #define TEGRA30_CLK_OWR 71 | ||
| 93 | #define TEGRA30_CLK_AFI 72 | ||
| 94 | #define TEGRA30_CLK_CSITE 73 | ||
| 95 | #define TEGRA30_CLK_PCIEX 74 | ||
| 96 | #define TEGRA30_CLK_AVPUCQ 75 | ||
| 97 | #define TEGRA30_CLK_LA 76 | ||
| 98 | /* 77 */ | ||
| 99 | /* 78 */ | ||
| 100 | #define TEGRA30_CLK_DTV 79 | ||
| 101 | #define TEGRA30_CLK_NDSPEED 80 | ||
| 102 | #define TEGRA30_CLK_I2CSLOW 81 | ||
| 103 | #define TEGRA30_CLK_DSIB 82 | ||
| 104 | /* 83 */ | ||
| 105 | #define TEGRA30_CLK_IRAMA 84 | ||
| 106 | #define TEGRA30_CLK_IRAMB 85 | ||
| 107 | #define TEGRA30_CLK_IRAMC 86 | ||
| 108 | #define TEGRA30_CLK_IRAMD 87 | ||
| 109 | #define TEGRA30_CLK_CRAM2 88 | ||
| 110 | /* 89 */ | ||
| 111 | #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ | ||
| 112 | /* 91 */ | ||
| 113 | #define TEGRA30_CLK_CSUS 92 | ||
| 114 | #define TEGRA30_CLK_CDEV2 93 | ||
| 115 | #define TEGRA30_CLK_CDEV1 94 | ||
| 116 | /* 95 */ | ||
| 117 | |||
| 118 | #define TEGRA30_CLK_CPU_G 96 | ||
| 119 | #define TEGRA30_CLK_CPU_LP 97 | ||
| 120 | #define TEGRA30_CLK_GR3D2 98 | ||
| 121 | #define TEGRA30_CLK_MSELECT 99 | ||
| 122 | #define TEGRA30_CLK_TSENSOR 100 | ||
| 123 | #define TEGRA30_CLK_I2S3 101 | ||
| 124 | #define TEGRA30_CLK_I2S4 102 | ||
| 125 | #define TEGRA30_CLK_I2C4 103 | ||
| 126 | #define TEGRA30_CLK_SBC5 104 | ||
| 127 | #define TEGRA30_CLK_SBC6 105 | ||
| 128 | #define TEGRA30_CLK_D_AUDIO 106 | ||
| 129 | #define TEGRA30_CLK_APBIF 107 | ||
| 130 | #define TEGRA30_CLK_DAM0 108 | ||
| 131 | #define TEGRA30_CLK_DAM1 109 | ||
| 132 | #define TEGRA30_CLK_DAM2 110 | ||
| 133 | #define TEGRA30_CLK_HDA2CODEC_2X 111 | ||
| 134 | #define TEGRA30_CLK_ATOMICS 112 | ||
| 135 | #define TEGRA30_CLK_AUDIO0_2X 113 | ||
| 136 | #define TEGRA30_CLK_AUDIO1_2X 114 | ||
| 137 | #define TEGRA30_CLK_AUDIO2_2X 115 | ||
| 138 | #define TEGRA30_CLK_AUDIO3_2X 116 | ||
| 139 | #define TEGRA30_CLK_AUDIO4_2X 117 | ||
| 140 | #define TEGRA30_CLK_SPDIF_2X 118 | ||
| 141 | #define TEGRA30_CLK_ACTMON 119 | ||
| 142 | #define TEGRA30_CLK_EXTERN1 120 | ||
| 143 | #define TEGRA30_CLK_EXTERN2 121 | ||
| 144 | #define TEGRA30_CLK_EXTERN3 122 | ||
| 145 | #define TEGRA30_CLK_SATA_OOB 123 | ||
| 146 | #define TEGRA30_CLK_SATA 124 | ||
| 147 | #define TEGRA30_CLK_HDA 125 | ||
| 148 | /* 126 */ | ||
| 149 | #define TEGRA30_CLK_SE 127 | ||
| 150 | |||
| 151 | #define TEGRA30_CLK_HDA2HDMI 128 | ||
| 152 | #define TEGRA30_CLK_SATA_COLD 129 | ||
| 153 | /* 130 */ | ||
| 154 | /* 131 */ | ||
| 155 | /* 132 */ | ||
| 156 | /* 133 */ | ||
| 157 | /* 134 */ | ||
| 158 | /* 135 */ | ||
| 159 | /* 136 */ | ||
| 160 | /* 137 */ | ||
| 161 | /* 138 */ | ||
| 162 | /* 139 */ | ||
| 163 | /* 140 */ | ||
| 164 | /* 141 */ | ||
| 165 | /* 142 */ | ||
| 166 | /* 143 */ | ||
| 167 | /* 144 */ | ||
| 168 | /* 145 */ | ||
| 169 | /* 146 */ | ||
| 170 | /* 147 */ | ||
| 171 | /* 148 */ | ||
| 172 | /* 149 */ | ||
| 173 | /* 150 */ | ||
| 174 | /* 151 */ | ||
| 175 | /* 152 */ | ||
| 176 | /* 153 */ | ||
| 177 | /* 154 */ | ||
| 178 | /* 155 */ | ||
| 179 | /* 156 */ | ||
| 180 | /* 157 */ | ||
| 181 | /* 158 */ | ||
| 182 | /* 159 */ | ||
| 183 | |||
| 184 | #define TEGRA30_CLK_UARTB 160 | ||
| 185 | #define TEGRA30_CLK_VFIR 161 | ||
| 186 | #define TEGRA30_CLK_SPDIF_IN 162 | ||
| 187 | #define TEGRA30_CLK_SPDIF_OUT 163 | ||
| 188 | #define TEGRA30_CLK_VI 164 | ||
| 189 | #define TEGRA30_CLK_VI_SENSOR 165 | ||
| 190 | #define TEGRA30_CLK_FUSE 166 | ||
| 191 | #define TEGRA30_CLK_FUSE_BURN 167 | ||
| 192 | #define TEGRA30_CLK_CVE 168 | ||
| 193 | #define TEGRA30_CLK_TVO 169 | ||
| 194 | #define TEGRA30_CLK_CLK_32K 170 | ||
| 195 | #define TEGRA30_CLK_CLK_M 171 | ||
| 196 | #define TEGRA30_CLK_CLK_M_DIV2 172 | ||
| 197 | #define TEGRA30_CLK_CLK_M_DIV4 173 | ||
| 198 | #define TEGRA30_CLK_PLL_REF 174 | ||
| 199 | #define TEGRA30_CLK_PLL_C 175 | ||
| 200 | #define TEGRA30_CLK_PLL_C_OUT1 176 | ||
| 201 | #define TEGRA30_CLK_PLL_M 177 | ||
| 202 | #define TEGRA30_CLK_PLL_M_OUT1 178 | ||
| 203 | #define TEGRA30_CLK_PLL_P 179 | ||
| 204 | #define TEGRA30_CLK_PLL_P_OUT1 180 | ||
| 205 | #define TEGRA30_CLK_PLL_P_OUT2 181 | ||
| 206 | #define TEGRA30_CLK_PLL_P_OUT3 182 | ||
| 207 | #define TEGRA30_CLK_PLL_P_OUT4 183 | ||
| 208 | #define TEGRA30_CLK_PLL_A 184 | ||
| 209 | #define TEGRA30_CLK_PLL_A_OUT0 185 | ||
| 210 | #define TEGRA30_CLK_PLL_D 186 | ||
| 211 | #define TEGRA30_CLK_PLL_D_OUT0 187 | ||
| 212 | #define TEGRA30_CLK_PLL_D2 188 | ||
| 213 | #define TEGRA30_CLK_PLL_D2_OUT0 189 | ||
| 214 | #define TEGRA30_CLK_PLL_U 190 | ||
| 215 | #define TEGRA30_CLK_PLL_X 191 | ||
| 216 | |||
| 217 | #define TEGRA30_CLK_PLL_X_OUT0 192 | ||
| 218 | #define TEGRA30_CLK_PLL_E 193 | ||
| 219 | #define TEGRA30_CLK_SPDIF_IN_SYNC 194 | ||
| 220 | #define TEGRA30_CLK_I2S0_SYNC 195 | ||
| 221 | #define TEGRA30_CLK_I2S1_SYNC 196 | ||
| 222 | #define TEGRA30_CLK_I2S2_SYNC 197 | ||
| 223 | #define TEGRA30_CLK_I2S3_SYNC 198 | ||
| 224 | #define TEGRA30_CLK_I2S4_SYNC 199 | ||
| 225 | #define TEGRA30_CLK_VIMCLK_SYNC 200 | ||
| 226 | #define TEGRA30_CLK_AUDIO0 201 | ||
| 227 | #define TEGRA30_CLK_AUDIO1 202 | ||
| 228 | #define TEGRA30_CLK_AUDIO2 203 | ||
| 229 | #define TEGRA30_CLK_AUDIO3 204 | ||
| 230 | #define TEGRA30_CLK_AUDIO4 205 | ||
| 231 | #define TEGRA30_CLK_SPDIF 206 | ||
| 232 | #define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ | ||
| 233 | #define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ | ||
| 234 | #define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ | ||
| 235 | #define TEGRA30_CLK_SCLK 210 | ||
| 236 | #define TEGRA30_CLK_BLINK 211 | ||
| 237 | #define TEGRA30_CLK_CCLK_G 212 | ||
| 238 | #define TEGRA30_CLK_CCLK_LP 213 | ||
| 239 | #define TEGRA30_CLK_TWD 214 | ||
| 240 | #define TEGRA30_CLK_CML0 215 | ||
| 241 | #define TEGRA30_CLK_CML1 216 | ||
| 242 | #define TEGRA30_CLK_HCLK 217 | ||
| 243 | #define TEGRA30_CLK_PCLK 218 | ||
| 244 | /* 219 */ | ||
| 245 | /* 220 */ | ||
| 246 | /* 221 */ | ||
| 247 | /* 222 */ | ||
| 248 | /* 223 */ | ||
| 249 | |||
| 250 | /* 288 */ | ||
| 251 | /* 289 */ | ||
| 252 | /* 290 */ | ||
| 253 | /* 291 */ | ||
| 254 | /* 292 */ | ||
| 255 | /* 293 */ | ||
| 256 | /* 294 */ | ||
| 257 | /* 295 */ | ||
| 258 | /* 296 */ | ||
| 259 | /* 297 */ | ||
| 260 | /* 298 */ | ||
| 261 | /* 299 */ | ||
| 262 | #define TEGRA30_CLK_CLK_OUT_1_MUX 300 | ||
| 263 | #define TEGRA30_CLK_CLK_MAX 301 | ||
| 264 | |||
| 265 | #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ | ||
diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h new file mode 100644 index 000000000000..e835037a77b4 --- /dev/null +++ b/include/dt-bindings/dma/at91.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | /* | ||
| 2 | * This header provides macros for at91 dma bindings. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | ||
| 5 | * | ||
| 6 | * GPLv2 only | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __DT_BINDINGS_AT91_DMA_H__ | ||
| 10 | #define __DT_BINDINGS_AT91_DMA_H__ | ||
| 11 | |||
| 12 | /* | ||
| 13 | * Source and/or destination peripheral ID | ||
| 14 | */ | ||
| 15 | #define AT91_DMA_CFG_PER_ID_MASK (0xff) | ||
| 16 | #define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) | ||
| 17 | |||
| 18 | /* | ||
| 19 | * FIFO configuration: it defines when a request is serviced. | ||
| 20 | */ | ||
| 21 | #define AT91_DMA_CFG_FIFOCFG_OFFSET (8) | ||
| 22 | #define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) | ||
| 23 | #define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ | ||
| 24 | #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ | ||
| 25 | #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ | ||
| 26 | |||
| 27 | #endif /* __DT_BINDINGS_AT91_DMA_H__ */ | ||
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h new file mode 100644 index 000000000000..4d179c00f081 --- /dev/null +++ b/include/dt-bindings/gpio/tegra-gpio.h | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for binding nvidia,tegra*-gpio. | ||
| 3 | * | ||
| 4 | * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below | ||
| 5 | * provide names for this. | ||
| 6 | * | ||
| 7 | * The second cell contains standard flag values specified in gpio.h. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H | ||
| 11 | #define _DT_BINDINGS_GPIO_TEGRA_GPIO_H | ||
| 12 | |||
| 13 | #include <dt-bindings/gpio/gpio.h> | ||
| 14 | |||
| 15 | #define TEGRA_GPIO_BANK_ID_A 0 | ||
| 16 | #define TEGRA_GPIO_BANK_ID_B 1 | ||
| 17 | #define TEGRA_GPIO_BANK_ID_C 2 | ||
| 18 | #define TEGRA_GPIO_BANK_ID_D 3 | ||
| 19 | #define TEGRA_GPIO_BANK_ID_E 4 | ||
| 20 | #define TEGRA_GPIO_BANK_ID_F 5 | ||
| 21 | #define TEGRA_GPIO_BANK_ID_G 6 | ||
| 22 | #define TEGRA_GPIO_BANK_ID_H 7 | ||
| 23 | #define TEGRA_GPIO_BANK_ID_I 8 | ||
| 24 | #define TEGRA_GPIO_BANK_ID_J 9 | ||
| 25 | #define TEGRA_GPIO_BANK_ID_K 10 | ||
| 26 | #define TEGRA_GPIO_BANK_ID_L 11 | ||
| 27 | #define TEGRA_GPIO_BANK_ID_M 12 | ||
| 28 | #define TEGRA_GPIO_BANK_ID_N 13 | ||
| 29 | #define TEGRA_GPIO_BANK_ID_O 14 | ||
| 30 | #define TEGRA_GPIO_BANK_ID_P 15 | ||
| 31 | #define TEGRA_GPIO_BANK_ID_Q 16 | ||
| 32 | #define TEGRA_GPIO_BANK_ID_R 17 | ||
| 33 | #define TEGRA_GPIO_BANK_ID_S 18 | ||
| 34 | #define TEGRA_GPIO_BANK_ID_T 19 | ||
| 35 | #define TEGRA_GPIO_BANK_ID_U 20 | ||
| 36 | #define TEGRA_GPIO_BANK_ID_V 21 | ||
| 37 | #define TEGRA_GPIO_BANK_ID_W 22 | ||
| 38 | #define TEGRA_GPIO_BANK_ID_X 23 | ||
| 39 | #define TEGRA_GPIO_BANK_ID_Y 24 | ||
| 40 | #define TEGRA_GPIO_BANK_ID_Z 25 | ||
| 41 | #define TEGRA_GPIO_BANK_ID_AA 26 | ||
| 42 | #define TEGRA_GPIO_BANK_ID_BB 27 | ||
| 43 | #define TEGRA_GPIO_BANK_ID_CC 28 | ||
| 44 | #define TEGRA_GPIO_BANK_ID_DD 29 | ||
| 45 | #define TEGRA_GPIO_BANK_ID_EE 30 | ||
| 46 | |||
| 47 | #define TEGRA_GPIO(bank, offset) \ | ||
| 48 | ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) | ||
| 49 | |||
| 50 | #endif | ||
diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h new file mode 100644 index 000000000000..469e0325e6f4 --- /dev/null +++ b/include/dt-bindings/pinctrl/am33xx.h | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants specific to AM33XX pinctrl bindings. | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef _DT_BINDINGS_PINCTRL_AM33XX_H | ||
| 6 | #define _DT_BINDINGS_PINCTRL_AM33XX_H | ||
| 7 | |||
| 8 | #include <include/dt-bindings/pinctrl/omap.h> | ||
| 9 | |||
| 10 | /* am33xx specific mux bit defines */ | ||
| 11 | #undef PULL_ENA | ||
| 12 | #undef INPUT_EN | ||
| 13 | |||
| 14 | #define PULL_DISABLE (1 << 3) | ||
| 15 | #define INPUT_EN (1 << 5) | ||
| 16 | #define SLEWCTRL_FAST (1 << 6) | ||
| 17 | |||
| 18 | /* update macro depending on INPUT_EN and PULL_ENA */ | ||
| 19 | #undef PIN_OUTPUT | ||
| 20 | #undef PIN_OUTPUT_PULLUP | ||
| 21 | #undef PIN_OUTPUT_PULLDOWN | ||
| 22 | #undef PIN_INPUT | ||
| 23 | #undef PIN_INPUT_PULLUP | ||
| 24 | #undef PIN_INPUT_PULLDOWN | ||
| 25 | |||
| 26 | #define PIN_OUTPUT (PULL_DISABLE) | ||
| 27 | #define PIN_OUTPUT_PULLUP (PULL_UP) | ||
| 28 | #define PIN_OUTPUT_PULLDOWN 0 | ||
| 29 | #define PIN_INPUT (INPUT_EN | PULL_DISABLE) | ||
| 30 | #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) | ||
| 31 | #define PIN_INPUT_PULLDOWN (INPUT_EN) | ||
| 32 | |||
| 33 | /* undef non-existing modes */ | ||
| 34 | #undef PIN_OFF_NONE | ||
| 35 | #undef PIN_OFF_OUTPUT_HIGH | ||
| 36 | #undef PIN_OFF_OUTPUT_LOW | ||
| 37 | #undef PIN_OFF_INPUT_PULLUP | ||
| 38 | #undef PIN_OFF_INPUT_PULLDOWN | ||
| 39 | #undef PIN_OFF_WAKEUPENABLE | ||
| 40 | |||
| 41 | #endif | ||
| 42 | |||
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h new file mode 100644 index 000000000000..edbd250809cb --- /dev/null +++ b/include/dt-bindings/pinctrl/omap.h | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for OMAP pinctrl bindings. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Nokia | ||
| 5 | * Copyright (C) 2009-2010 Texas Instruments | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef _DT_BINDINGS_PINCTRL_OMAP_H | ||
| 9 | #define _DT_BINDINGS_PINCTRL_OMAP_H | ||
| 10 | |||
| 11 | /* 34xx mux mode options for each pin. See TRM for options */ | ||
| 12 | #define MUX_MODE0 0 | ||
| 13 | #define MUX_MODE1 1 | ||
| 14 | #define MUX_MODE2 2 | ||
| 15 | #define MUX_MODE3 3 | ||
| 16 | #define MUX_MODE4 4 | ||
| 17 | #define MUX_MODE5 5 | ||
| 18 | #define MUX_MODE6 6 | ||
| 19 | #define MUX_MODE7 7 | ||
| 20 | |||
| 21 | /* 24xx/34xx mux bit defines */ | ||
| 22 | #define PULL_ENA (1 << 3) | ||
| 23 | #define PULL_UP (1 << 4) | ||
| 24 | #define ALTELECTRICALSEL (1 << 5) | ||
| 25 | |||
| 26 | /* 34xx specific mux bit defines */ | ||
| 27 | #define INPUT_EN (1 << 8) | ||
| 28 | #define OFF_EN (1 << 9) | ||
| 29 | #define OFFOUT_EN (1 << 10) | ||
| 30 | #define OFFOUT_VAL (1 << 11) | ||
| 31 | #define OFF_PULL_EN (1 << 12) | ||
| 32 | #define OFF_PULL_UP (1 << 13) | ||
| 33 | #define WAKEUP_EN (1 << 14) | ||
| 34 | |||
| 35 | /* 44xx specific mux bit defines */ | ||
| 36 | #define WAKEUP_EVENT (1 << 15) | ||
| 37 | |||
| 38 | /* Active pin states */ | ||
| 39 | #define PIN_OUTPUT 0 | ||
| 40 | #define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) | ||
| 41 | #define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) | ||
| 42 | #define PIN_INPUT INPUT_EN | ||
| 43 | #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) | ||
| 44 | #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) | ||
| 45 | |||
| 46 | /* Off mode states */ | ||
| 47 | #define PIN_OFF_NONE 0 | ||
| 48 | #define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) | ||
| 49 | #define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) | ||
| 50 | #define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP) | ||
| 51 | #define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) | ||
| 52 | #define PIN_OFF_WAKEUPENABLE WAKEUP_EN | ||
| 53 | |||
| 54 | #endif | ||
| 55 | |||