aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-s3c2410/dma.c14
-rw-r--r--arch/arm/mach-s3c2412/dma.c18
-rw-r--r--arch/arm/mach-s3c2440/dma.c17
-rw-r--r--arch/arm/mach-s3c2443/dma.c27
4 files changed, 0 insertions, 76 deletions
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 0d8e043804c2..dbe43df8cfec 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -47,38 +47,26 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID, 47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
48 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, 48 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
49 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, 49 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
50 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
51 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
52 }, 50 },
53 [DMACH_SPI0] = { 51 [DMACH_SPI0] = {
54 .name = "spi0", 52 .name = "spi0",
55 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, 53 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
56 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
57 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
58 }, 54 },
59 [DMACH_SPI1] = { 55 [DMACH_SPI1] = {
60 .name = "spi1", 56 .name = "spi1",
61 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, 57 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
62 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
63 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
64 }, 58 },
65 [DMACH_UART0] = { 59 [DMACH_UART0] = {
66 .name = "uart0", 60 .name = "uart0",
67 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, 61 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
68 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
69 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
70 }, 62 },
71 [DMACH_UART1] = { 63 [DMACH_UART1] = {
72 .name = "uart1", 64 .name = "uart1",
73 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, 65 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
74 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
75 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
76 }, 66 },
77 [DMACH_UART2] = { 67 [DMACH_UART2] = {
78 .name = "uart2", 68 .name = "uart2",
79 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, 69 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
80 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
81 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
82 }, 70 },
83 [DMACH_TIMER] = { 71 [DMACH_TIMER] = {
84 .name = "timer", 72 .name = "timer",
@@ -90,12 +78,10 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
90 .name = "i2s-sdi", 78 .name = "i2s-sdi",
91 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, 79 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
92 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, 80 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
93 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
94 }, 81 },
95 [DMACH_I2S_OUT] = { 82 [DMACH_I2S_OUT] = {
96 .name = "i2s-sdo", 83 .name = "i2s-sdo",
97 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, 84 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
98 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
99 }, 85 },
100 [DMACH_USB_EP1] = { 86 [DMACH_USB_EP1] = {
101 .name = "usb-ep1", 87 .name = "usb-ep1",
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 7abecfca0b7e..c61e3261615d 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -50,64 +50,46 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
50 .name = "sdi", 50 .name = "sdi",
51 .channels = MAP(S3C2412_DMAREQSEL_SDI), 51 .channels = MAP(S3C2412_DMAREQSEL_SDI),
52 .channels_rx = MAP(S3C2412_DMAREQSEL_SDI), 52 .channels_rx = MAP(S3C2412_DMAREQSEL_SDI),
53 .hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA,
54 .hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA,
55 }, 53 },
56 [DMACH_SPI0] = { 54 [DMACH_SPI0] = {
57 .name = "spi0", 55 .name = "spi0",
58 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX), 56 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
59 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX), 57 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX),
60 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
61 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
62 }, 58 },
63 [DMACH_SPI1] = { 59 [DMACH_SPI1] = {
64 .name = "spi1", 60 .name = "spi1",
65 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX), 61 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
66 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX), 62 .channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX),
67 .hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
68 .hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT,
69 }, 63 },
70 [DMACH_UART0] = { 64 [DMACH_UART0] = {
71 .name = "uart0", 65 .name = "uart0",
72 .channels = MAP(S3C2412_DMAREQSEL_UART0_0), 66 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
73 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0), 67 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0),
74 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
75 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
76 }, 68 },
77 [DMACH_UART1] = { 69 [DMACH_UART1] = {
78 .name = "uart1", 70 .name = "uart1",
79 .channels = MAP(S3C2412_DMAREQSEL_UART1_0), 71 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
80 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0), 72 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0),
81 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
82 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
83 }, 73 },
84 [DMACH_UART2] = { 74 [DMACH_UART2] = {
85 .name = "uart2", 75 .name = "uart2",
86 .channels = MAP(S3C2412_DMAREQSEL_UART2_0), 76 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
87 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0), 77 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0),
88 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
89 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
90 }, 78 },
91 [DMACH_UART0_SRC2] = { 79 [DMACH_UART0_SRC2] = {
92 .name = "uart0", 80 .name = "uart0",
93 .channels = MAP(S3C2412_DMAREQSEL_UART0_1), 81 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
94 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1), 82 .channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1),
95 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
96 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
97 }, 83 },
98 [DMACH_UART1_SRC2] = { 84 [DMACH_UART1_SRC2] = {
99 .name = "uart1", 85 .name = "uart1",
100 .channels = MAP(S3C2412_DMAREQSEL_UART1_1), 86 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
101 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1), 87 .channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1),
102 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
103 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
104 }, 88 },
105 [DMACH_UART2_SRC2] = { 89 [DMACH_UART2_SRC2] = {
106 .name = "uart2", 90 .name = "uart2",
107 .channels = MAP(S3C2412_DMAREQSEL_UART2_1), 91 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
108 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1), 92 .channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1),
109 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
110 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
111 }, 93 },
112 [DMACH_TIMER] = { 94 [DMACH_TIMER] = {
113 .name = "timer", 95 .name = "timer",
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 3b0529f54e9c..0e73f8f9d132 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -48,38 +48,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
48 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID, 48 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
49 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID, 49 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
50 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID, 50 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
51 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
52 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
53 }, 51 },
54 [DMACH_SPI0] = { 52 [DMACH_SPI0] = {
55 .name = "spi0", 53 .name = "spi0",
56 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID, 54 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
57 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
58 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
59 }, 55 },
60 [DMACH_SPI1] = { 56 [DMACH_SPI1] = {
61 .name = "spi1", 57 .name = "spi1",
62 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID, 58 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
63 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
64 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
65 }, 59 },
66 [DMACH_UART0] = { 60 [DMACH_UART0] = {
67 .name = "uart0", 61 .name = "uart0",
68 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID, 62 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
69 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
70 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
71 }, 63 },
72 [DMACH_UART1] = { 64 [DMACH_UART1] = {
73 .name = "uart1", 65 .name = "uart1",
74 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID, 66 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
75 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
76 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
77 }, 67 },
78 [DMACH_UART2] = { 68 [DMACH_UART2] = {
79 .name = "uart2", 69 .name = "uart2",
80 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID, 70 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
81 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
82 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
83 }, 71 },
84 [DMACH_TIMER] = { 72 [DMACH_TIMER] = {
85 .name = "timer", 73 .name = "timer",
@@ -91,31 +79,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
91 .name = "i2s-sdi", 79 .name = "i2s-sdi",
92 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID, 80 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
93 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID, 81 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
94 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
95 }, 82 },
96 [DMACH_I2S_OUT] = { 83 [DMACH_I2S_OUT] = {
97 .name = "i2s-sdo", 84 .name = "i2s-sdo",
98 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID, 85 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
99 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID, 86 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
100 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
101 }, 87 },
102 [DMACH_PCM_IN] = { 88 [DMACH_PCM_IN] = {
103 .name = "pcm-in", 89 .name = "pcm-in",
104 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID, 90 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
105 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID, 91 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
106 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
107 }, 92 },
108 [DMACH_PCM_OUT] = { 93 [DMACH_PCM_OUT] = {
109 .name = "pcm-out", 94 .name = "pcm-out",
110 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID, 95 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
111 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID, 96 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
112 .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
113 }, 97 },
114 [DMACH_MIC_IN] = { 98 [DMACH_MIC_IN] = {
115 .name = "mic-in", 99 .name = "mic-in",
116 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID, 100 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
117 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID, 101 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
118 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
119 }, 102 },
120 [DMACH_USB_EP1] = { 103 [DMACH_USB_EP1] = {
121 .name = "usb-ep1", 104 .name = "usb-ep1",
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index 3f658685ec16..fe52151d2e84 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -54,68 +54,46 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
54 [DMACH_SDI] = { 54 [DMACH_SDI] = {
55 .name = "sdi", 55 .name = "sdi",
56 .channels = MAP(S3C2443_DMAREQSEL_SDI), 56 .channels = MAP(S3C2443_DMAREQSEL_SDI),
57 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
58 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
59 }, 57 },
60 [DMACH_SPI0] = { 58 [DMACH_SPI0] = {
61 .name = "spi0", 59 .name = "spi0",
62 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX), 60 .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
63 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
64 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
65 }, 61 },
66 [DMACH_SPI1] = { 62 [DMACH_SPI1] = {
67 .name = "spi1", 63 .name = "spi1",
68 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX), 64 .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
69 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
70 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
71 }, 65 },
72 [DMACH_UART0] = { 66 [DMACH_UART0] = {
73 .name = "uart0", 67 .name = "uart0",
74 .channels = MAP(S3C2443_DMAREQSEL_UART0_0), 68 .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
75 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
76 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
77 }, 69 },
78 [DMACH_UART1] = { 70 [DMACH_UART1] = {
79 .name = "uart1", 71 .name = "uart1",
80 .channels = MAP(S3C2443_DMAREQSEL_UART1_0), 72 .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
81 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
82 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
83 }, 73 },
84 [DMACH_UART2] = { 74 [DMACH_UART2] = {
85 .name = "uart2", 75 .name = "uart2",
86 .channels = MAP(S3C2443_DMAREQSEL_UART2_0), 76 .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
87 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
88 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
89 }, 77 },
90 [DMACH_UART3] = { 78 [DMACH_UART3] = {
91 .name = "uart3", 79 .name = "uart3",
92 .channels = MAP(S3C2443_DMAREQSEL_UART3_0), 80 .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
93 .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
94 .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
95 }, 81 },
96 [DMACH_UART0_SRC2] = { 82 [DMACH_UART0_SRC2] = {
97 .name = "uart0", 83 .name = "uart0",
98 .channels = MAP(S3C2443_DMAREQSEL_UART0_1), 84 .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
99 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
100 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
101 }, 85 },
102 [DMACH_UART1_SRC2] = { 86 [DMACH_UART1_SRC2] = {
103 .name = "uart1", 87 .name = "uart1",
104 .channels = MAP(S3C2443_DMAREQSEL_UART1_1), 88 .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
105 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
106 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
107 }, 89 },
108 [DMACH_UART2_SRC2] = { 90 [DMACH_UART2_SRC2] = {
109 .name = "uart2", 91 .name = "uart2",
110 .channels = MAP(S3C2443_DMAREQSEL_UART2_1), 92 .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
111 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
112 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
113 }, 93 },
114 [DMACH_UART3_SRC2] = { 94 [DMACH_UART3_SRC2] = {
115 .name = "uart3", 95 .name = "uart3",
116 .channels = MAP(S3C2443_DMAREQSEL_UART3_1), 96 .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
117 .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
118 .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
119 }, 97 },
120 [DMACH_TIMER] = { 98 [DMACH_TIMER] = {
121 .name = "timer", 99 .name = "timer",
@@ -124,27 +102,22 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
124 [DMACH_I2S_IN] = { 102 [DMACH_I2S_IN] = {
125 .name = "i2s-sdi", 103 .name = "i2s-sdi",
126 .channels = MAP(S3C2443_DMAREQSEL_I2SRX), 104 .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
127 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
128 }, 105 },
129 [DMACH_I2S_OUT] = { 106 [DMACH_I2S_OUT] = {
130 .name = "i2s-sdo", 107 .name = "i2s-sdo",
131 .channels = MAP(S3C2443_DMAREQSEL_I2STX), 108 .channels = MAP(S3C2443_DMAREQSEL_I2STX),
132 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
133 }, 109 },
134 [DMACH_PCM_IN] = { 110 [DMACH_PCM_IN] = {
135 .name = "pcm-in", 111 .name = "pcm-in",
136 .channels = MAP(S3C2443_DMAREQSEL_PCMIN), 112 .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
137 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
138 }, 113 },
139 [DMACH_PCM_OUT] = { 114 [DMACH_PCM_OUT] = {
140 .name = "pcm-out", 115 .name = "pcm-out",
141 .channels = MAP(S3C2443_DMAREQSEL_PCMOUT), 116 .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
142 .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
143 }, 117 },
144 [DMACH_MIC_IN] = { 118 [DMACH_MIC_IN] = {
145 .name = "mic-in", 119 .name = "mic-in",
146 .channels = MAP(S3C2443_DMAREQSEL_MICIN), 120 .channels = MAP(S3C2443_DMAREQSEL_MICIN),
147 .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
148 }, 121 },
149}; 122};
150 123
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 23:11:55 -0500