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-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.c520
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.h51
2 files changed, 543 insertions, 28 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index 8f590ea9ece0..d0f9e5aa2151 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -34,9 +34,13 @@ DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
34DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30"); 34DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
35DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51"); 35DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
36DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4"); 36DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
37DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8");
37DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17"); 38DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
39DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47");
38DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22"); 40DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
41DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22");
39DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31"); 42DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
43DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60");
40DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7"); 44DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7");
41DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15"); 45DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15");
42DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23"); 46DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23");
@@ -367,6 +371,7 @@ static struct event_constraint snbep_uncore_cbox_constraints[] = {
367 UNCORE_EVENT_CONSTRAINT(0x04, 0x3), 371 UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
368 UNCORE_EVENT_CONSTRAINT(0x05, 0x3), 372 UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
369 UNCORE_EVENT_CONSTRAINT(0x07, 0x3), 373 UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
374 UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
370 UNCORE_EVENT_CONSTRAINT(0x11, 0x1), 375 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
371 UNCORE_EVENT_CONSTRAINT(0x12, 0x3), 376 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
372 UNCORE_EVENT_CONSTRAINT(0x13, 0x3), 377 UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
@@ -416,6 +421,14 @@ static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
416 UNCORE_EVENT_CONSTRAINT(0x24, 0x3), 421 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
417 UNCORE_EVENT_CONSTRAINT(0x25, 0x3), 422 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
418 UNCORE_EVENT_CONSTRAINT(0x26, 0x3), 423 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
424 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
425 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
426 UNCORE_EVENT_CONSTRAINT(0x2a, 0x3),
427 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
428 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
429 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
430 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
431 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
419 UNCORE_EVENT_CONSTRAINT(0x30, 0x3), 432 UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
420 UNCORE_EVENT_CONSTRAINT(0x31, 0x3), 433 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
421 UNCORE_EVENT_CONSTRAINT(0x32, 0x3), 434 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
@@ -423,6 +436,8 @@ static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
423 UNCORE_EVENT_CONSTRAINT(0x34, 0x3), 436 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
424 UNCORE_EVENT_CONSTRAINT(0x36, 0x3), 437 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
425 UNCORE_EVENT_CONSTRAINT(0x37, 0x3), 438 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
439 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
440 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
426 EVENT_CONSTRAINT_END 441 EVENT_CONSTRAINT_END
427}; 442};
428 443
@@ -772,55 +787,63 @@ static struct intel_uncore_type snbep_uncore_r3qpi = {
772 SNBEP_UNCORE_PCI_COMMON_INIT(), 787 SNBEP_UNCORE_PCI_COMMON_INIT(),
773}; 788};
774 789
790enum {
791 SNBEP_PCI_UNCORE_HA,
792 SNBEP_PCI_UNCORE_IMC,
793 SNBEP_PCI_UNCORE_QPI,
794 SNBEP_PCI_UNCORE_R2PCIE,
795 SNBEP_PCI_UNCORE_R3QPI,
796};
797
775static struct intel_uncore_type *snbep_pci_uncores[] = { 798static struct intel_uncore_type *snbep_pci_uncores[] = {
776 &snbep_uncore_ha, 799 [SNBEP_PCI_UNCORE_HA] = &snbep_uncore_ha,
777 &snbep_uncore_imc, 800 [SNBEP_PCI_UNCORE_IMC] = &snbep_uncore_imc,
778 &snbep_uncore_qpi, 801 [SNBEP_PCI_UNCORE_QPI] = &snbep_uncore_qpi,
779 &snbep_uncore_r2pcie, 802 [SNBEP_PCI_UNCORE_R2PCIE] = &snbep_uncore_r2pcie,
780 &snbep_uncore_r3qpi, 803 [SNBEP_PCI_UNCORE_R3QPI] = &snbep_uncore_r3qpi,
781 NULL, 804 NULL,
782}; 805};
783 806
784static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = { 807static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = {
785 { /* Home Agent */ 808 { /* Home Agent */
786 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA), 809 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
787 .driver_data = (unsigned long)&snbep_uncore_ha, 810 .driver_data = SNBEP_PCI_UNCORE_HA,
788 }, 811 },
789 { /* MC Channel 0 */ 812 { /* MC Channel 0 */
790 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0), 813 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
791 .driver_data = (unsigned long)&snbep_uncore_imc, 814 .driver_data = SNBEP_PCI_UNCORE_IMC,
792 }, 815 },
793 { /* MC Channel 1 */ 816 { /* MC Channel 1 */
794 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1), 817 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
795 .driver_data = (unsigned long)&snbep_uncore_imc, 818 .driver_data = SNBEP_PCI_UNCORE_IMC,
796 }, 819 },
797 { /* MC Channel 2 */ 820 { /* MC Channel 2 */
798 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2), 821 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
799 .driver_data = (unsigned long)&snbep_uncore_imc, 822 .driver_data = SNBEP_PCI_UNCORE_IMC,
800 }, 823 },
801 { /* MC Channel 3 */ 824 { /* MC Channel 3 */
802 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3), 825 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
803 .driver_data = (unsigned long)&snbep_uncore_imc, 826 .driver_data = SNBEP_PCI_UNCORE_IMC,
804 }, 827 },
805 { /* QPI Port 0 */ 828 { /* QPI Port 0 */
806 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0), 829 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
807 .driver_data = (unsigned long)&snbep_uncore_qpi, 830 .driver_data = SNBEP_PCI_UNCORE_QPI,
808 }, 831 },
809 { /* QPI Port 1 */ 832 { /* QPI Port 1 */
810 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1), 833 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
811 .driver_data = (unsigned long)&snbep_uncore_qpi, 834 .driver_data = SNBEP_PCI_UNCORE_QPI,
812 }, 835 },
813 { /* P2PCIe */ 836 { /* R2PCIe */
814 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE), 837 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
815 .driver_data = (unsigned long)&snbep_uncore_r2pcie, 838 .driver_data = SNBEP_PCI_UNCORE_R2PCIE,
816 }, 839 },
817 { /* R3QPI Link 0 */ 840 { /* R3QPI Link 0 */
818 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0), 841 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
819 .driver_data = (unsigned long)&snbep_uncore_r3qpi, 842 .driver_data = SNBEP_PCI_UNCORE_R3QPI,
820 }, 843 },
821 { /* R3QPI Link 1 */ 844 { /* R3QPI Link 1 */
822 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1), 845 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
823 .driver_data = (unsigned long)&snbep_uncore_r3qpi, 846 .driver_data = SNBEP_PCI_UNCORE_R3QPI,
824 }, 847 },
825 { /* end: all zeroes */ } 848 { /* end: all zeroes */ }
826}; 849};
@@ -833,7 +856,7 @@ static struct pci_driver snbep_uncore_pci_driver = {
833/* 856/*
834 * build pci bus to socket mapping 857 * build pci bus to socket mapping
835 */ 858 */
836static int snbep_pci2phy_map_init(void) 859static int snbep_pci2phy_map_init(int devid)
837{ 860{
838 struct pci_dev *ubox_dev = NULL; 861 struct pci_dev *ubox_dev = NULL;
839 int i, bus, nodeid; 862 int i, bus, nodeid;
@@ -842,9 +865,7 @@ static int snbep_pci2phy_map_init(void)
842 865
843 while (1) { 866 while (1) {
844 /* find the UBOX device */ 867 /* find the UBOX device */
845 ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 868 ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, ubox_dev);
846 PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX,
847 ubox_dev);
848 if (!ubox_dev) 869 if (!ubox_dev)
849 break; 870 break;
850 bus = ubox_dev->bus->number; 871 bus = ubox_dev->bus->number;
@@ -867,7 +888,7 @@ static int snbep_pci2phy_map_init(void)
867 break; 888 break;
868 } 889 }
869 } 890 }
870 }; 891 }
871 892
872 if (ubox_dev) 893 if (ubox_dev)
873 pci_dev_put(ubox_dev); 894 pci_dev_put(ubox_dev);
@@ -876,6 +897,440 @@ static int snbep_pci2phy_map_init(void)
876} 897}
877/* end of Sandy Bridge-EP uncore support */ 898/* end of Sandy Bridge-EP uncore support */
878 899
900/* IvyTown uncore support */
901static void ivt_uncore_msr_init_box(struct intel_uncore_box *box)
902{
903 unsigned msr = uncore_msr_box_ctl(box);
904 if (msr)
905 wrmsrl(msr, IVT_PMON_BOX_CTL_INT);
906}
907
908static void ivt_uncore_pci_init_box(struct intel_uncore_box *box)
909{
910 struct pci_dev *pdev = box->pci_dev;
911
912 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, IVT_PMON_BOX_CTL_INT);
913}
914
915#define IVT_UNCORE_MSR_OPS_COMMON_INIT() \
916 .init_box = ivt_uncore_msr_init_box, \
917 .disable_box = snbep_uncore_msr_disable_box, \
918 .enable_box = snbep_uncore_msr_enable_box, \
919 .disable_event = snbep_uncore_msr_disable_event, \
920 .enable_event = snbep_uncore_msr_enable_event, \
921 .read_counter = uncore_msr_read_counter
922
923static struct intel_uncore_ops ivt_uncore_msr_ops = {
924 IVT_UNCORE_MSR_OPS_COMMON_INIT(),
925};
926
927static struct intel_uncore_ops ivt_uncore_pci_ops = {
928 .init_box = ivt_uncore_pci_init_box,
929 .disable_box = snbep_uncore_pci_disable_box,
930 .enable_box = snbep_uncore_pci_enable_box,
931 .disable_event = snbep_uncore_pci_disable_event,
932 .enable_event = snbep_uncore_pci_enable_event,
933 .read_counter = snbep_uncore_pci_read_counter,
934};
935
936#define IVT_UNCORE_PCI_COMMON_INIT() \
937 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
938 .event_ctl = SNBEP_PCI_PMON_CTL0, \
939 .event_mask = IVT_PMON_RAW_EVENT_MASK, \
940 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
941 .ops = &ivt_uncore_pci_ops, \
942 .format_group = &ivt_uncore_format_group
943
944static struct attribute *ivt_uncore_formats_attr[] = {
945 &format_attr_event.attr,
946 &format_attr_umask.attr,
947 &format_attr_edge.attr,
948 &format_attr_inv.attr,
949 &format_attr_thresh8.attr,
950 NULL,
951};
952
953static struct attribute *ivt_uncore_ubox_formats_attr[] = {
954 &format_attr_event.attr,
955 &format_attr_umask.attr,
956 &format_attr_edge.attr,
957 &format_attr_inv.attr,
958 &format_attr_thresh5.attr,
959 NULL,
960};
961
962static struct attribute *ivt_uncore_cbox_formats_attr[] = {
963 &format_attr_event.attr,
964 &format_attr_umask.attr,
965 &format_attr_edge.attr,
966 &format_attr_tid_en.attr,
967 &format_attr_thresh8.attr,
968 &format_attr_filter_tid.attr,
969 &format_attr_filter_link.attr,
970 &format_attr_filter_state2.attr,
971 &format_attr_filter_nid2.attr,
972 &format_attr_filter_opc2.attr,
973 NULL,
974};
975
976static struct attribute *ivt_uncore_pcu_formats_attr[] = {
977 &format_attr_event_ext.attr,
978 &format_attr_occ_sel.attr,
979 &format_attr_edge.attr,
980 &format_attr_thresh5.attr,
981 &format_attr_occ_invert.attr,
982 &format_attr_occ_edge.attr,
983 &format_attr_filter_band0.attr,
984 &format_attr_filter_band1.attr,
985 &format_attr_filter_band2.attr,
986 &format_attr_filter_band3.attr,
987 NULL,
988};
989
990static struct attribute *ivt_uncore_qpi_formats_attr[] = {
991 &format_attr_event_ext.attr,
992 &format_attr_umask.attr,
993 &format_attr_edge.attr,
994 &format_attr_thresh8.attr,
995 NULL,
996};
997
998static struct attribute_group ivt_uncore_format_group = {
999 .name = "format",
1000 .attrs = ivt_uncore_formats_attr,
1001};
1002
1003static struct attribute_group ivt_uncore_ubox_format_group = {
1004 .name = "format",
1005 .attrs = ivt_uncore_ubox_formats_attr,
1006};
1007
1008static struct attribute_group ivt_uncore_cbox_format_group = {
1009 .name = "format",
1010 .attrs = ivt_uncore_cbox_formats_attr,
1011};
1012
1013static struct attribute_group ivt_uncore_pcu_format_group = {
1014 .name = "format",
1015 .attrs = ivt_uncore_pcu_formats_attr,
1016};
1017
1018static struct attribute_group ivt_uncore_qpi_format_group = {
1019 .name = "format",
1020 .attrs = ivt_uncore_qpi_formats_attr,
1021};
1022
1023static struct intel_uncore_type ivt_uncore_ubox = {
1024 .name = "ubox",
1025 .num_counters = 2,
1026 .num_boxes = 1,
1027 .perf_ctr_bits = 44,
1028 .fixed_ctr_bits = 48,
1029 .perf_ctr = SNBEP_U_MSR_PMON_CTR0,
1030 .event_ctl = SNBEP_U_MSR_PMON_CTL0,
1031 .event_mask = IVT_U_MSR_PMON_RAW_EVENT_MASK,
1032 .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
1033 .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
1034 .ops = &ivt_uncore_msr_ops,
1035 .format_group = &ivt_uncore_ubox_format_group,
1036};
1037
1038static struct extra_reg ivt_uncore_cbox_extra_regs[] = {
1039 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
1040 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
1041 SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2),
1042 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
1043 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
1044 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
1045 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
1046 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10),
1047 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
1048 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
1049 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
1050 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
1051 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
1052 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
1053 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
1054 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
1055 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
1056 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
1057 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
1058 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
1059 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
1060 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1061 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1062 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
1063 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
1064 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
1065 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
1066 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
1067 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
1068 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
1069 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
1070 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
1071 EVENT_EXTRA_END
1072};
1073
1074static u64 ivt_cbox_filter_mask(int fields)
1075{
1076 u64 mask = 0;
1077
1078 if (fields & 0x1)
1079 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_TID;
1080 if (fields & 0x2)
1081 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_LINK;
1082 if (fields & 0x4)
1083 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_STATE;
1084 if (fields & 0x8)
1085 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_NID;
1086 if (fields & 0x10)
1087 mask |= IVT_CB0_MSR_PMON_BOX_FILTER_OPC;
1088
1089 return mask;
1090}
1091
1092static struct event_constraint *
1093ivt_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1094{
1095 return __snbep_cbox_get_constraint(box, event, ivt_cbox_filter_mask);
1096}
1097
1098static int ivt_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1099{
1100 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1101 struct extra_reg *er;
1102 int idx = 0;
1103
1104 for (er = ivt_uncore_cbox_extra_regs; er->msr; er++) {
1105 if (er->event != (event->hw.config & er->config_mask))
1106 continue;
1107 idx |= er->idx;
1108 }
1109
1110 if (idx) {
1111 reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
1112 SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
1113 reg1->config = event->attr.config1 & ivt_cbox_filter_mask(idx);
1114 reg1->idx = idx;
1115 }
1116 return 0;
1117}
1118
1119static void ivt_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1120{
1121 struct hw_perf_event *hwc = &event->hw;
1122 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1123
1124 if (reg1->idx != EXTRA_REG_NONE) {
1125 u64 filter = uncore_shared_reg_config(box, 0);
1126 wrmsrl(reg1->reg, filter & 0xffffffff);
1127 wrmsrl(reg1->reg + 6, filter >> 32);
1128 }
1129
1130 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
1131}
1132
1133static struct intel_uncore_ops ivt_uncore_cbox_ops = {
1134 .init_box = ivt_uncore_msr_init_box,
1135 .disable_box = snbep_uncore_msr_disable_box,
1136 .enable_box = snbep_uncore_msr_enable_box,
1137 .disable_event = snbep_uncore_msr_disable_event,
1138 .enable_event = ivt_cbox_enable_event,
1139 .read_counter = uncore_msr_read_counter,
1140 .hw_config = ivt_cbox_hw_config,
1141 .get_constraint = ivt_cbox_get_constraint,
1142 .put_constraint = snbep_cbox_put_constraint,
1143};
1144
1145static struct intel_uncore_type ivt_uncore_cbox = {
1146 .name = "cbox",
1147 .num_counters = 4,
1148 .num_boxes = 15,
1149 .perf_ctr_bits = 44,
1150 .event_ctl = SNBEP_C0_MSR_PMON_CTL0,
1151 .perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
1152 .event_mask = IVT_CBO_MSR_PMON_RAW_EVENT_MASK,
1153 .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
1154 .msr_offset = SNBEP_CBO_MSR_OFFSET,
1155 .num_shared_regs = 1,
1156 .constraints = snbep_uncore_cbox_constraints,
1157 .ops = &ivt_uncore_cbox_ops,
1158 .format_group = &ivt_uncore_cbox_format_group,
1159};
1160
1161static struct intel_uncore_ops ivt_uncore_pcu_ops = {
1162 IVT_UNCORE_MSR_OPS_COMMON_INIT(),
1163 .hw_config = snbep_pcu_hw_config,
1164 .get_constraint = snbep_pcu_get_constraint,
1165 .put_constraint = snbep_pcu_put_constraint,
1166};
1167
1168static struct intel_uncore_type ivt_uncore_pcu = {
1169 .name = "pcu",
1170 .num_counters = 4,
1171 .num_boxes = 1,
1172 .perf_ctr_bits = 48,
1173 .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
1174 .event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
1175 .event_mask = IVT_PCU_MSR_PMON_RAW_EVENT_MASK,
1176 .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
1177 .num_shared_regs = 1,
1178 .ops = &ivt_uncore_pcu_ops,
1179 .format_group = &ivt_uncore_pcu_format_group,
1180};
1181
1182static struct intel_uncore_type *ivt_msr_uncores[] = {
1183 &ivt_uncore_ubox,
1184 &ivt_uncore_cbox,
1185 &ivt_uncore_pcu,
1186 NULL,
1187};
1188
1189static struct intel_uncore_type ivt_uncore_ha = {
1190 .name = "ha",
1191 .num_counters = 4,
1192 .num_boxes = 2,
1193 .perf_ctr_bits = 48,
1194 IVT_UNCORE_PCI_COMMON_INIT(),
1195};
1196
1197static struct intel_uncore_type ivt_uncore_imc = {
1198 .name = "imc",
1199 .num_counters = 4,
1200 .num_boxes = 8,
1201 .perf_ctr_bits = 48,
1202 .fixed_ctr_bits = 48,
1203 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
1204 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
1205 IVT_UNCORE_PCI_COMMON_INIT(),
1206};
1207
1208static struct intel_uncore_type ivt_uncore_qpi = {
1209 .name = "qpi",
1210 .num_counters = 4,
1211 .num_boxes = 3,
1212 .perf_ctr_bits = 48,
1213 .perf_ctr = SNBEP_PCI_PMON_CTR0,
1214 .event_ctl = SNBEP_PCI_PMON_CTL0,
1215 .event_mask = IVT_QPI_PCI_PMON_RAW_EVENT_MASK,
1216 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
1217 .ops = &ivt_uncore_pci_ops,
1218 .format_group = &ivt_uncore_qpi_format_group,
1219};
1220
1221static struct intel_uncore_type ivt_uncore_r2pcie = {
1222 .name = "r2pcie",
1223 .num_counters = 4,
1224 .num_boxes = 1,
1225 .perf_ctr_bits = 44,
1226 .constraints = snbep_uncore_r2pcie_constraints,
1227 IVT_UNCORE_PCI_COMMON_INIT(),
1228};
1229
1230static struct intel_uncore_type ivt_uncore_r3qpi = {
1231 .name = "r3qpi",
1232 .num_counters = 3,
1233 .num_boxes = 2,
1234 .perf_ctr_bits = 44,
1235 .constraints = snbep_uncore_r3qpi_constraints,
1236 IVT_UNCORE_PCI_COMMON_INIT(),
1237};
1238
1239enum {
1240 IVT_PCI_UNCORE_HA,
1241 IVT_PCI_UNCORE_IMC,
1242 IVT_PCI_UNCORE_QPI,
1243 IVT_PCI_UNCORE_R2PCIE,
1244 IVT_PCI_UNCORE_R3QPI,
1245};
1246
1247static struct intel_uncore_type *ivt_pci_uncores[] = {
1248 [IVT_PCI_UNCORE_HA] = &ivt_uncore_ha,
1249 [IVT_PCI_UNCORE_IMC] = &ivt_uncore_imc,
1250 [IVT_PCI_UNCORE_QPI] = &ivt_uncore_qpi,
1251 [IVT_PCI_UNCORE_R2PCIE] = &ivt_uncore_r2pcie,
1252 [IVT_PCI_UNCORE_R3QPI] = &ivt_uncore_r3qpi,
1253 NULL,
1254};
1255
1256static DEFINE_PCI_DEVICE_TABLE(ivt_uncore_pci_ids) = {
1257 { /* Home Agent 0 */
1258 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe30),
1259 .driver_data = IVT_PCI_UNCORE_HA,
1260 },
1261 { /* Home Agent 1 */
1262 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe38),
1263 .driver_data = IVT_PCI_UNCORE_HA,
1264 },
1265 { /* MC0 Channel 0 */
1266 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb4),
1267 .driver_data = IVT_PCI_UNCORE_IMC,
1268 },
1269 { /* MC0 Channel 1 */
1270 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb5),
1271 .driver_data = IVT_PCI_UNCORE_IMC,
1272 },
1273 { /* MC0 Channel 3 */
1274 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb0),
1275 .driver_data = IVT_PCI_UNCORE_IMC,
1276 },
1277 { /* MC0 Channel 4 */
1278 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb1),
1279 .driver_data = IVT_PCI_UNCORE_IMC,
1280 },
1281 { /* MC1 Channel 0 */
1282 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef4),
1283 .driver_data = IVT_PCI_UNCORE_IMC,
1284 },
1285 { /* MC1 Channel 1 */
1286 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef5),
1287 .driver_data = IVT_PCI_UNCORE_IMC,
1288 },
1289 { /* MC1 Channel 3 */
1290 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef0),
1291 .driver_data = IVT_PCI_UNCORE_IMC,
1292 },
1293 { /* MC1 Channel 4 */
1294 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1),
1295 .driver_data = IVT_PCI_UNCORE_IMC,
1296 },
1297 { /* QPI0 Port 0 */
1298 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32),
1299 .driver_data = IVT_PCI_UNCORE_QPI,
1300 },
1301 { /* QPI0 Port 1 */
1302 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe33),
1303 .driver_data = IVT_PCI_UNCORE_QPI,
1304 },
1305 { /* QPI1 Port 2 */
1306 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3a),
1307 .driver_data = IVT_PCI_UNCORE_QPI,
1308 },
1309 { /* R2PCIe */
1310 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe34),
1311 .driver_data = IVT_PCI_UNCORE_R2PCIE,
1312 },
1313 { /* R3QPI0 Link 0 */
1314 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe36),
1315 .driver_data = IVT_PCI_UNCORE_R3QPI,
1316 },
1317 { /* R3QPI0 Link 1 */
1318 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe37),
1319 .driver_data = IVT_PCI_UNCORE_R3QPI,
1320 },
1321 { /* R3QPI1 Link 2 */
1322 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e),
1323 .driver_data = IVT_PCI_UNCORE_R3QPI,
1324 },
1325 { /* end: all zeroes */ }
1326};
1327
1328static struct pci_driver ivt_uncore_pci_driver = {
1329 .name = "ivt_uncore",
1330 .id_table = ivt_uncore_pci_ids,
1331};
1332/* end of IvyTown uncore support */
1333
879/* Sandy Bridge uncore support */ 1334/* Sandy Bridge uncore support */
880static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event) 1335static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
881{ 1336{
@@ -2766,6 +3221,8 @@ static void uncore_pci_remove(struct pci_dev *pdev)
2766 if (WARN_ON_ONCE(phys_id != box->phys_id)) 3221 if (WARN_ON_ONCE(phys_id != box->phys_id))
2767 return; 3222 return;
2768 3223
3224 pci_set_drvdata(pdev, NULL);
3225
2769 raw_spin_lock(&uncore_box_lock); 3226 raw_spin_lock(&uncore_box_lock);
2770 list_del(&box->list); 3227 list_del(&box->list);
2771 raw_spin_unlock(&uncore_box_lock); 3228 raw_spin_unlock(&uncore_box_lock);
@@ -2784,11 +3241,7 @@ static void uncore_pci_remove(struct pci_dev *pdev)
2784static int uncore_pci_probe(struct pci_dev *pdev, 3241static int uncore_pci_probe(struct pci_dev *pdev,
2785 const struct pci_device_id *id) 3242 const struct pci_device_id *id)
2786{ 3243{
2787 struct intel_uncore_type *type; 3244 return uncore_pci_add(pci_uncores[id->driver_data], pdev);
2788
2789 type = (struct intel_uncore_type *)id->driver_data;
2790
2791 return uncore_pci_add(type, pdev);
2792} 3245}
2793 3246
2794static int __init uncore_pci_init(void) 3247static int __init uncore_pci_init(void)
@@ -2797,12 +3250,19 @@ static int __init uncore_pci_init(void)
2797 3250
2798 switch (boot_cpu_data.x86_model) { 3251 switch (boot_cpu_data.x86_model) {
2799 case 45: /* Sandy Bridge-EP */ 3252 case 45: /* Sandy Bridge-EP */
2800 ret = snbep_pci2phy_map_init(); 3253 ret = snbep_pci2phy_map_init(0x3ce0);
2801 if (ret) 3254 if (ret)
2802 return ret; 3255 return ret;
2803 pci_uncores = snbep_pci_uncores; 3256 pci_uncores = snbep_pci_uncores;
2804 uncore_pci_driver = &snbep_uncore_pci_driver; 3257 uncore_pci_driver = &snbep_uncore_pci_driver;
2805 break; 3258 break;
3259 case 62: /* IvyTown */
3260 ret = snbep_pci2phy_map_init(0x0e1e);
3261 if (ret)
3262 return ret;
3263 pci_uncores = ivt_pci_uncores;
3264 uncore_pci_driver = &ivt_uncore_pci_driver;
3265 break;
2806 default: 3266 default:
2807 return 0; 3267 return 0;
2808 } 3268 }
@@ -3103,6 +3563,12 @@ static int __init uncore_cpu_init(void)
3103 nhmex_uncore_cbox.num_boxes = max_cores; 3563 nhmex_uncore_cbox.num_boxes = max_cores;
3104 msr_uncores = nhmex_msr_uncores; 3564 msr_uncores = nhmex_msr_uncores;
3105 break; 3565 break;
3566 case 62: /* IvyTown */
3567 if (ivt_uncore_cbox.num_boxes > max_cores)
3568 ivt_uncore_cbox.num_boxes = max_cores;
3569 msr_uncores = ivt_msr_uncores;
3570 break;
3571
3106 default: 3572 default:
3107 return 0; 3573 return 0;
3108 } 3574 }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index f14a3413a85d..f9528917f6e8 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -76,7 +76,7 @@
76#define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00 76#define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00
77#define SNBEP_PMON_CTL_RST (1 << 17) 77#define SNBEP_PMON_CTL_RST (1 << 17)
78#define SNBEP_PMON_CTL_EDGE_DET (1 << 18) 78#define SNBEP_PMON_CTL_EDGE_DET (1 << 18)
79#define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21) /* only for QPI */ 79#define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21)
80#define SNBEP_PMON_CTL_EN (1 << 22) 80#define SNBEP_PMON_CTL_EN (1 << 22)
81#define SNBEP_PMON_CTL_INVERT (1 << 23) 81#define SNBEP_PMON_CTL_INVERT (1 << 23)
82#define SNBEP_PMON_CTL_TRESH_MASK 0xff000000 82#define SNBEP_PMON_CTL_TRESH_MASK 0xff000000
@@ -171,6 +171,55 @@
171#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc 171#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
172#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd 172#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
173 173
174/* IVT event control */
175#define IVT_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \
176 SNBEP_PMON_BOX_CTL_RST_CTRS)
177#define IVT_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
178 SNBEP_PMON_CTL_UMASK_MASK | \
179 SNBEP_PMON_CTL_EDGE_DET | \
180 SNBEP_PMON_CTL_TRESH_MASK)
181/* IVT Ubox */
182#define IVT_U_MSR_PMON_GLOBAL_CTL 0xc00
183#define IVT_U_PMON_GLOBAL_FRZ_ALL (1 << 31)
184#define IVT_U_PMON_GLOBAL_UNFRZ_ALL (1 << 29)
185
186#define IVT_U_MSR_PMON_RAW_EVENT_MASK \
187 (SNBEP_PMON_CTL_EV_SEL_MASK | \
188 SNBEP_PMON_CTL_UMASK_MASK | \
189 SNBEP_PMON_CTL_EDGE_DET | \
190 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
191/* IVT Cbo */
192#define IVT_CBO_MSR_PMON_RAW_EVENT_MASK (IVT_PMON_RAW_EVENT_MASK | \
193 SNBEP_CBO_PMON_CTL_TID_EN)
194
195#define IVT_CB0_MSR_PMON_BOX_FILTER_TID (0x1fULL << 0)
196#define IVT_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 5)
197#define IVT_CB0_MSR_PMON_BOX_FILTER_STATE (0x3fULL << 17)
198#define IVT_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32)
199#define IVT_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52)
200#define IVT_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
201#define IVT_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
202#define IVT_CB0_MSR_PMON_BOX_FILTER_IOSC (0x1ULL << 63)
203
204/* IVT home agent */
205#define IVT_HA_PCI_PMON_CTL_Q_OCC_RST (1 << 16)
206#define IVT_HA_PCI_PMON_RAW_EVENT_MASK \
207 (IVT_PMON_RAW_EVENT_MASK | \
208 IVT_HA_PCI_PMON_CTL_Q_OCC_RST)
209/* IVT PCU */
210#define IVT_PCU_MSR_PMON_RAW_EVENT_MASK \
211 (SNBEP_PMON_CTL_EV_SEL_MASK | \
212 SNBEP_PMON_CTL_EV_SEL_EXT | \
213 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
214 SNBEP_PMON_CTL_EDGE_DET | \
215 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
216 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
217 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
218/* IVT QPI */
219#define IVT_QPI_PCI_PMON_RAW_EVENT_MASK \
220 (IVT_PMON_RAW_EVENT_MASK | \
221 SNBEP_PMON_CTL_EV_SEL_EXT)
222
174/* NHM-EX event control */ 223/* NHM-EX event control */
175#define NHMEX_PMON_CTL_EV_SEL_MASK 0x000000ff 224#define NHMEX_PMON_CTL_EV_SEL_MASK 0x000000ff
176#define NHMEX_PMON_CTL_UMASK_MASK 0x0000ff00 225#define NHMEX_PMON_CTL_UMASK_MASK 0x0000ff00
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 10:27:37 -0500