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-rw-r--r--Documentation/ABI/testing/sysfs-bus-iio-frequency-ad952337
-rw-r--r--drivers/iio/Kconfig1
-rw-r--r--drivers/iio/Makefile1
-rw-r--r--drivers/iio/frequency/Kconfig23
-rw-r--r--drivers/iio/frequency/Makefile5
-rw-r--r--drivers/iio/frequency/ad9523.c1057
-rw-r--r--include/linux/iio/frequency/ad9523.h195
7 files changed, 1319 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-iio-frequency-ad9523 b/Documentation/ABI/testing/sysfs-bus-iio-frequency-ad9523
new file mode 100644
index 000000000000..2ce9c3f68eee
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-iio-frequency-ad9523
@@ -0,0 +1,37 @@
1What: /sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present
2What: /sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present
3What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present
4What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present
5What: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present
6What: /sys/bus/iio/devices/iio:deviceX/vcxo_clk_present
7KernelVersion: 3.4.0
8Contact: linux-iio@vger.kernel.org
9Description:
10 Reading returns either '1' or '0'.
11 '1' means that the clock in question is present.
12 '0' means that the clock is missing.
13
14What: /sys/bus/iio/devices/iio:deviceX/pllY_locked
15KernelVersion: 3.4.0
16Contact: linux-iio@vger.kernel.org
17Description:
18 Reading returns either '1' or '0'. '1' means that the
19 pllY is locked.
20
21What: /sys/bus/iio/devices/iio:deviceX/store_eeprom
22KernelVersion: 3.4.0
23Contact: linux-iio@vger.kernel.org
24Description:
25 Writing '1' stores the current device configuration into
26 on-chip EEPROM. After power-up or chip reset the device will
27 automatically load the saved configuration.
28
29What: /sys/bus/iio/devices/iio:deviceX/sync_dividers
30KernelVersion: 3.4.0
31Contact: linux-iio@vger.kernel.org
32Description:
33 Writing '1' triggers the clock distribution synchronization
34 functionality. All dividers are reset and the channels start
35 with their predefined phase offsets (out_altvoltageY_phase).
36 Writing this file has the effect as driving the external
37 /SYNC pin low.
diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
index cacc74d70241..64c88e5cda4d 100644
--- a/drivers/iio/Kconfig
+++ b/drivers/iio/Kconfig
@@ -51,5 +51,6 @@ config IIO_CONSUMERS_PER_TRIGGER
51source "drivers/iio/adc/Kconfig" 51source "drivers/iio/adc/Kconfig"
52source "drivers/iio/amplifiers/Kconfig" 52source "drivers/iio/amplifiers/Kconfig"
53source "drivers/iio/light/Kconfig" 53source "drivers/iio/light/Kconfig"
54source "drivers/iio/frequency/Kconfig"
54 55
55endif # IIO 56endif # IIO
diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
index 060b674d278c..bd801c0bbc2f 100644
--- a/drivers/iio/Makefile
+++ b/drivers/iio/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_IIO_KFIFO_BUF) += kfifo_buf.o
12obj-y += adc/ 12obj-y += adc/
13obj-y += amplifiers/ 13obj-y += amplifiers/
14obj-y += light/ 14obj-y += light/
15obj-y += frequency/
diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig
new file mode 100644
index 000000000000..0458c92464a3
--- /dev/null
+++ b/drivers/iio/frequency/Kconfig
@@ -0,0 +1,23 @@
1#
2# Frequency
3# Direct Digital Synthesis drivers (DDS)
4# Clock Distribution device drivers
5# Phase-Locked Loop (PLL) frequency synthesizers
6#
7
8menu "Frequency Synthesizers DDS/PLL"
9
10menu "Clock Generator/Distribution"
11
12config AD9523
13 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
14 depends on SPI
15 help
16 Say yes here to build support for Analog Devices AD9523 Low Jitter
17 Clock Generator. The driver provides direct access via sysfs.
18
19 To compile this driver as a module, choose M here: the
20 module will be called ad9523.
21
22endmenu
23endmenu
diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile
new file mode 100644
index 000000000000..1b5b22417da1
--- /dev/null
+++ b/drivers/iio/frequency/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile iio/frequency
3#
4
5obj-$(CONFIG_AD9523) += ad9523.o
diff --git a/drivers/iio/frequency/ad9523.c b/drivers/iio/frequency/ad9523.c
new file mode 100644
index 000000000000..7272924484c1
--- /dev/null
+++ b/drivers/iio/frequency/ad9523.c
@@ -0,0 +1,1057 @@
1/*
2 * AD9523 SPI Low Jitter Clock Generator
3 *
4 * Copyright 2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9#include <linux/device.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/sysfs.h>
13#include <linux/spi/spi.h>
14#include <linux/regulator/consumer.h>
15#include <linux/err.h>
16#include <linux/module.h>
17#include <linux/delay.h>
18
19#include <linux/iio/iio.h>
20#include <linux/iio/sysfs.h>
21#include <linux/iio/frequency/ad9523.h>
22
23#define AD9523_READ (1 << 15)
24#define AD9523_WRITE (0 << 15)
25#define AD9523_CNT(x) (((x) - 1) << 13)
26#define AD9523_ADDR(x) ((x) & 0xFFF)
27
28#define AD9523_R1B (1 << 16)
29#define AD9523_R2B (2 << 16)
30#define AD9523_R3B (3 << 16)
31#define AD9523_TRANSF_LEN(x) ((x) >> 16)
32
33#define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0)
34#define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2)
35#define AD9523_PART_REGISTER (AD9523_R1B | 0x3)
36#define AD9523_READBACK_CTRL (AD9523_R1B | 0x4)
37
38#define AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B | 0x6)
39
40#define AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B | 0x11)
41#define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13)
42#define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14)
43#define AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B | 0x17)
44#define AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B | 0x19)
45#define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A)
46#define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B)
47#define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C)
48#define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D)
49
50#define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0)
51#define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1)
52#define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2)
53#define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3)
54#define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4)
55#define AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B | 0xF6)
56#define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7)
57
58#define AD9523_CHANNEL_CLOCK_DIST(ch) (AD9523_R3B | (0x192 + 3 * ch))
59
60#define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA)
61#define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB)
62
63#define AD9523_READBACK_0 (AD9523_R1B | 0x22C)
64#define AD9523_READBACK_1 (AD9523_R1B | 0x22D)
65
66#define AD9523_STATUS_SIGNALS (AD9523_R3B | 0x232)
67#define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233)
68#define AD9523_IO_UPDATE (AD9523_R1B | 0x234)
69
70#define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00)
71#define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01)
72#define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02)
73#define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03)
74
75/* AD9523_SERIAL_PORT_CONFIG */
76
77#define AD9523_SER_CONF_SDO_ACTIVE (1 << 7)
78#define AD9523_SER_CONF_SOFT_RESET (1 << 5)
79
80/* AD9523_READBACK_CTRL */
81#define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0)
82
83/* AD9523_PLL1_CHARGE_PUMP_CTRL */
84#define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x) (((x) / 500) & 0x7F)
85#define AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)
86#define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)
87#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)
88#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)
89#define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)
90#define AD9523_PLL1_BACKLASH_PW_MIN (0 << 10)
91#define AD9523_PLL1_BACKLASH_PW_LOW (1 << 10)
92#define AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10)
93#define AD9523_PLL1_BACKLASH_PW_MAX (3 << 10)
94
95/* AD9523_PLL1_INPUT_RECEIVERS_CTRL */
96#define AD9523_PLL1_REF_TEST_RCV_EN (1 << 7)
97#define AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6)
98#define AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5)
99#define AD9523_PLL1_REFB_RCV_EN (1 << 4)
100#define AD9523_PLL1_REFA_RCV_EN (1 << 3)
101#define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2)
102#define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)
103#define AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0)
104
105/* AD9523_PLL1_REF_CTRL */
106#define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7)
107#define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6)
108#define AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5)
109#define AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5)
110#define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4)
111#define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3)
112#define AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2)
113#define AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1)
114#define AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0)
115
116/* AD9523_PLL1_MISC_CTRL */
117#define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7)
118#define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6)
119#define AD9523_PLL1_REF_MODE(x) ((x) << 2)
120#define AD9523_PLL1_BYPASS_REFB_DIV (1 << 1)
121#define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0)
122
123/* AD9523_PLL1_LOOP_FILTER_CTRL */
124#define AD9523_PLL1_LOOP_FILTER_RZERO(x) ((x) & 0xF)
125
126/* AD9523_PLL2_CHARGE_PUMP */
127#define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x) ((x) / 3500)
128
129/* AD9523_PLL2_FEEDBACK_DIVIDER_AB */
130#define AD9523_PLL2_FB_NDIV_A_CNT(x) (((x) & 0x3) << 6)
131#define AD9523_PLL2_FB_NDIV_B_CNT(x) (((x) & 0x3F) << 0)
132#define AD9523_PLL2_FB_NDIV(a, b) (4 * (b) + (a))
133
134/* AD9523_PLL2_CTRL */
135#define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)
136#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)
137#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)
138#define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)
139#define AD9523_PLL2_BACKLASH_PW_MIN (0 << 2)
140#define AD9523_PLL2_BACKLASH_PW_LOW (1 << 2)
141#define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2)
142#define AD9523_PLL2_BACKLASH_PW_MAX (3 << 1)
143#define AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4)
144#define AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5)
145#define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)
146
147/* AD9523_PLL2_VCO_CTRL */
148#define AD9523_PLL2_VCO_CALIBRATE (1 << 1)
149#define AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2)
150#define AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3)
151#define AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4)
152
153/* AD9523_PLL2_VCO_DIVIDER */
154#define AD9523_PLL2_VCO_DIV_M1(x) ((((x) - 3) & 0x3) << 0)
155#define AD9523_PLL2_VCO_DIV_M2(x) ((((x) - 3) & 0x3) << 4)
156#define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2)
157#define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6)
158
159/* AD9523_PLL2_LOOP_FILTER_CTRL */
160#define AD9523_PLL2_LOOP_FILTER_CPOLE1(x) (((x) & 0x7) << 0)
161#define AD9523_PLL2_LOOP_FILTER_RZERO(x) (((x) & 0x7) << 3)
162#define AD9523_PLL2_LOOP_FILTER_RPOLE2(x) (((x) & 0x7) << 6)
163#define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)
164
165/* AD9523_PLL2_R2_DIVIDER */
166#define AD9523_PLL2_R2_DIVIDER_VAL(x) (((x) & 0x1F) << 0)
167
168/* AD9523_CHANNEL_CLOCK_DIST */
169#define AD9523_CLK_DIST_DIV_PHASE(x) (((x) & 0x3F) << 18)
170#define AD9523_CLK_DIST_DIV_PHASE_REV(x) ((ret >> 18) & 0x3F)
171#define AD9523_CLK_DIST_DIV(x) ((((x) - 1) & 0x3FF) << 8)
172#define AD9523_CLK_DIST_DIV_REV(x) (((ret >> 8) & 0x3FF) + 1)
173#define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7)
174#define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6)
175#define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5)
176#define AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4)
177#define AD9523_CLK_DIST_DRIVER_MODE(x) (((x) & 0xF) << 0)
178
179/* AD9523_PLL1_OUTPUT_CTRL */
180#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7)
181#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6)
182#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5)
183#define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4)
184#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0)
185#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0)
186#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0)
187#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0)
188#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0)
189
190/* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */
191#define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7)
192#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6)
193#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5)
194#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4)
195#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3)
196#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2)
197#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1)
198#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0)
199
200/* AD9523_READBACK_0 */
201#define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7)
202#define AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6)
203#define AD9523_READBACK_0_STAT_VCXO (1 << 5)
204#define AD9523_READBACK_0_STAT_REF_TEST (1 << 4)
205#define AD9523_READBACK_0_STAT_REFB (1 << 3)
206#define AD9523_READBACK_0_STAT_REFA (1 << 2)
207#define AD9523_READBACK_0_STAT_PLL2_LD (1 << 1)
208#define AD9523_READBACK_0_STAT_PLL1_LD (1 << 0)
209
210/* AD9523_READBACK_1 */
211#define AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3)
212#define AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2)
213#define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0)
214
215/* AD9523_STATUS_SIGNALS */
216#define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16)
217#define AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302)
218/* AD9523_POWER_DOWN_CTRL */
219#define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2)
220#define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1)
221#define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0)
222
223/* AD9523_IO_UPDATE */
224#define AD9523_IO_UPDATE_EN (1 << 0)
225
226/* AD9523_EEPROM_DATA_XFER_STATUS */
227#define AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0)
228
229/* AD9523_EEPROM_ERROR_READBACK */
230#define AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0)
231
232/* AD9523_EEPROM_CTRL1 */
233#define AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1)
234#define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0)
235
236/* AD9523_EEPROM_CTRL2 */
237#define AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0)
238
239#define AD9523_NUM_CHAN 14
240#define AD9523_NUM_CHAN_ALT_CLK_SRC 10
241
242/* Helpers to avoid excess line breaks */
243#define AD_IFE(_pde, _a, _b) ((pdata->_pde) ? _a : _b)
244#define AD_IF(_pde, _a) AD_IFE(_pde, _a, 0)
245
246enum {
247 AD9523_STAT_PLL1_LD,
248 AD9523_STAT_PLL2_LD,
249 AD9523_STAT_REFA,
250 AD9523_STAT_REFB,
251 AD9523_STAT_REF_TEST,
252 AD9523_STAT_VCXO,
253 AD9523_STAT_PLL2_FB_CLK,
254 AD9523_STAT_PLL2_REF_CLK,
255 AD9523_SYNC,
256 AD9523_EEPROM,
257};
258
259enum {
260 AD9523_VCO1,
261 AD9523_VCO2,
262 AD9523_VCXO,
263 AD9523_NUM_CLK_SRC,
264};
265
266struct ad9523_state {
267 struct spi_device *spi;
268 struct regulator *reg;
269 struct ad9523_platform_data *pdata;
270 struct iio_chan_spec ad9523_channels[AD9523_NUM_CHAN];
271
272 unsigned long vcxo_freq;
273 unsigned long vco_freq;
274 unsigned long vco_out_freq[AD9523_NUM_CLK_SRC];
275 unsigned char vco_out_map[AD9523_NUM_CHAN_ALT_CLK_SRC];
276
277 /*
278 * DMA (thus cache coherency maintenance) requires the
279 * transfer buffers to live in their own cache lines.
280 */
281 union {
282 __be32 d32;
283 u8 d8[4];
284 } data[2] ____cacheline_aligned;
285};
286
287static int ad9523_read(struct iio_dev *indio_dev, unsigned addr)
288{
289 struct ad9523_state *st = iio_priv(indio_dev);
290 struct spi_message m;
291 int ret;
292
293 /* We encode the register size 1..3 bytes into the register address.
294 * On transfer we get the size from the register datum, and make sure
295 * the result is properly aligned.
296 */
297
298 struct spi_transfer t[] = {
299 {
300 .tx_buf = &st->data[0].d8[2],
301 .len = 2,
302 }, {
303 .rx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],
304 .len = AD9523_TRANSF_LEN(addr),
305 },
306 };
307
308 spi_message_init(&m);
309 spi_message_add_tail(&t[0], &m);
310 spi_message_add_tail(&t[1], &m);
311
312 st->data[0].d32 = cpu_to_be32(AD9523_READ |
313 AD9523_CNT(AD9523_TRANSF_LEN(addr)) |
314 AD9523_ADDR(addr));
315
316 ret = spi_sync(st->spi, &m);
317 if (ret < 0)
318 dev_err(&indio_dev->dev, "read failed (%d)", ret);
319 else
320 ret = be32_to_cpu(st->data[1].d32) & (0xFFFFFF >>
321 (8 * (3 - AD9523_TRANSF_LEN(addr))));
322
323 return ret;
324};
325
326static int ad9523_write(struct iio_dev *indio_dev, unsigned addr, unsigned val)
327{
328 struct ad9523_state *st = iio_priv(indio_dev);
329 struct spi_message m;
330 int ret;
331 struct spi_transfer t[] = {
332 {
333 .tx_buf = &st->data[0].d8[2],
334 .len = 2,
335 }, {
336 .tx_buf = &st->data[1].d8[4 - AD9523_TRANSF_LEN(addr)],
337 .len = AD9523_TRANSF_LEN(addr),
338 },
339 };
340
341 spi_message_init(&m);
342 spi_message_add_tail(&t[0], &m);
343 spi_message_add_tail(&t[1], &m);
344
345 st->data[0].d32 = cpu_to_be32(AD9523_WRITE |
346 AD9523_CNT(AD9523_TRANSF_LEN(addr)) |
347 AD9523_ADDR(addr));
348 st->data[1].d32 = cpu_to_be32(val);
349
350 ret = spi_sync(st->spi, &m);
351
352 if (ret < 0)
353 dev_err(&indio_dev->dev, "write failed (%d)", ret);
354
355 return ret;
356}
357
358static int ad9523_io_update(struct iio_dev *indio_dev)
359{
360 return ad9523_write(indio_dev, AD9523_IO_UPDATE, AD9523_IO_UPDATE_EN);
361}
362
363static int ad9523_vco_out_map(struct iio_dev *indio_dev,
364 unsigned ch, bool out)
365{
366 struct ad9523_state *st = iio_priv(indio_dev);
367 int ret;
368 unsigned mask;
369
370 switch (ch) {
371 case 0 ... 3:
372 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
373 if (ret < 0)
374 break;
375 mask = AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 << ch;
376 if (out) {
377 ret |= mask;
378 out = 2;
379 } else {
380 ret &= ~mask;
381 }
382 ret = ad9523_write(indio_dev,
383 AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
384 break;
385 case 4 ... 6:
386 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CTRL);
387 if (ret < 0)
388 break;
389 mask = AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 << (ch - 4);
390 if (out)
391 ret |= mask;
392 else
393 ret &= ~mask;
394 ret = ad9523_write(indio_dev, AD9523_PLL1_OUTPUT_CTRL, ret);
395 break;
396 case 7 ... 9:
397 ret = ad9523_read(indio_dev, AD9523_PLL1_OUTPUT_CHANNEL_CTRL);
398 if (ret < 0)
399 break;
400 mask = AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 << (ch - 7);
401 if (out)
402 ret |= mask;
403 else
404 ret &= ~mask;
405 ret = ad9523_write(indio_dev,
406 AD9523_PLL1_OUTPUT_CHANNEL_CTRL, ret);
407 break;
408 default:
409 return 0;
410 }
411
412 st->vco_out_map[ch] = out;
413
414 return ret;
415}
416
417static int ad9523_set_clock_provider(struct iio_dev *indio_dev,
418 unsigned ch, unsigned long freq)
419{
420 struct ad9523_state *st = iio_priv(indio_dev);
421 long tmp1, tmp2;
422 bool use_alt_clk_src;
423
424 switch (ch) {
425 case 0 ... 3:
426 use_alt_clk_src = (freq == st->vco_out_freq[AD9523_VCXO]);
427 break;
428 case 4 ... 9:
429 tmp1 = st->vco_out_freq[AD9523_VCO1] / freq;
430 tmp2 = st->vco_out_freq[AD9523_VCO2] / freq;
431 tmp1 *= freq;
432 tmp2 *= freq;
433 use_alt_clk_src = (abs(tmp1 - freq) > abs(tmp2 - freq));
434 break;
435 default:
436 /* Ch 10..14: No action required, return success */
437 return 0;
438 }
439
440 return ad9523_vco_out_map(indio_dev, ch, use_alt_clk_src);
441}
442
443static int ad9523_store_eeprom(struct iio_dev *indio_dev)
444{
445 int ret, tmp;
446
447 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1,
448 AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS);
449 if (ret < 0)
450 return ret;
451 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL2,
452 AD9523_EEPROM_CTRL2_REG2EEPROM);
453 if (ret < 0)
454 return ret;
455
456 tmp = 4;
457 do {
458 msleep(16);
459 ret = ad9523_read(indio_dev,
460 AD9523_EEPROM_DATA_XFER_STATUS);
461 if (ret < 0)
462 return ret;
463 } while ((ret & AD9523_EEPROM_DATA_XFER_IN_PROGRESS) && tmp--);
464
465 ret = ad9523_write(indio_dev, AD9523_EEPROM_CTRL1, 0);
466 if (ret < 0)
467 return ret;
468
469 ret = ad9523_read(indio_dev, AD9523_EEPROM_ERROR_READBACK);
470 if (ret < 0)
471 return ret;
472
473 if (ret & AD9523_EEPROM_ERROR_READBACK_FAIL) {
474 dev_err(&indio_dev->dev, "Verify EEPROM failed");
475 ret = -EIO;
476 }
477
478 return ret;
479}
480
481static int ad9523_sync(struct iio_dev *indio_dev)
482{
483 int ret, tmp;
484
485 ret = ad9523_read(indio_dev, AD9523_STATUS_SIGNALS);
486 if (ret < 0)
487 return ret;
488
489 tmp = ret;
490 tmp |= AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;
491
492 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
493 if (ret < 0)
494 return ret;
495
496 ad9523_io_update(indio_dev);
497 tmp &= ~AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL;
498
499 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS, tmp);
500 if (ret < 0)
501 return ret;
502
503 return ad9523_io_update(indio_dev);
504}
505
506static ssize_t ad9523_store(struct device *dev,
507 struct device_attribute *attr,
508 const char *buf, size_t len)
509{
510 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
511 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
512 bool state;
513 int ret;
514
515 ret = strtobool(buf, &state);
516 if (ret < 0)
517 return ret;
518
519 if (!state)
520 return 0;
521
522 mutex_lock(&indio_dev->mlock);
523 switch ((u32)this_attr->address) {
524 case AD9523_SYNC:
525 ret = ad9523_sync(indio_dev);
526 break;
527 case AD9523_EEPROM:
528 ret = ad9523_store_eeprom(indio_dev);
529 break;
530 default:
531 ret = -ENODEV;
532 }
533 mutex_unlock(&indio_dev->mlock);
534
535 return ret ? ret : len;
536}
537
538static ssize_t ad9523_show(struct device *dev,
539 struct device_attribute *attr,
540 char *buf)
541{
542 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
543 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
544 int ret;
545
546 mutex_lock(&indio_dev->mlock);
547 ret = ad9523_read(indio_dev, AD9523_READBACK_0);
548 if (ret >= 0) {
549 ret = sprintf(buf, "%d\n", !!(ret & (1 <<
550 (u32)this_attr->address)));
551 }
552 mutex_unlock(&indio_dev->mlock);
553
554 return ret;
555}
556
557static IIO_DEVICE_ATTR(pll1_locked, S_IRUGO,
558 ad9523_show,
559 NULL,
560 AD9523_STAT_PLL1_LD);
561
562static IIO_DEVICE_ATTR(pll2_locked, S_IRUGO,
563 ad9523_show,
564 NULL,
565 AD9523_STAT_PLL2_LD);
566
567static IIO_DEVICE_ATTR(pll1_reference_clk_a_present, S_IRUGO,
568 ad9523_show,
569 NULL,
570 AD9523_STAT_REFA);
571
572static IIO_DEVICE_ATTR(pll1_reference_clk_b_present, S_IRUGO,
573 ad9523_show,
574 NULL,
575 AD9523_STAT_REFB);
576
577static IIO_DEVICE_ATTR(pll1_reference_clk_test_present, S_IRUGO,
578 ad9523_show,
579 NULL,
580 AD9523_STAT_REF_TEST);
581
582static IIO_DEVICE_ATTR(vcxo_clk_present, S_IRUGO,
583 ad9523_show,
584 NULL,
585 AD9523_STAT_VCXO);
586
587static IIO_DEVICE_ATTR(pll2_feedback_clk_present, S_IRUGO,
588 ad9523_show,
589 NULL,
590 AD9523_STAT_PLL2_FB_CLK);
591
592static IIO_DEVICE_ATTR(pll2_reference_clk_present, S_IRUGO,
593 ad9523_show,
594 NULL,
595 AD9523_STAT_PLL2_REF_CLK);
596
597static IIO_DEVICE_ATTR(sync_dividers, S_IWUSR,
598 NULL,
599 ad9523_store,
600 AD9523_SYNC);
601
602static IIO_DEVICE_ATTR(store_eeprom, S_IWUSR,
603 NULL,
604 ad9523_store,
605 AD9523_EEPROM);
606
607static struct attribute *ad9523_attributes[] = {
608 &iio_dev_attr_sync_dividers.dev_attr.attr,
609 &iio_dev_attr_store_eeprom.dev_attr.attr,
610 &iio_dev_attr_pll2_feedback_clk_present.dev_attr.attr,
611 &iio_dev_attr_pll2_reference_clk_present.dev_attr.attr,
612 &iio_dev_attr_pll1_reference_clk_a_present.dev_attr.attr,
613 &iio_dev_attr_pll1_reference_clk_b_present.dev_attr.attr,
614 &iio_dev_attr_pll1_reference_clk_test_present.dev_attr.attr,
615 &iio_dev_attr_vcxo_clk_present.dev_attr.attr,
616 &iio_dev_attr_pll1_locked.dev_attr.attr,
617 &iio_dev_attr_pll2_locked.dev_attr.attr,
618 NULL,
619};
620
621static const struct attribute_group ad9523_attribute_group = {
622 .attrs = ad9523_attributes,
623};
624
625static int ad9523_read_raw(struct iio_dev *indio_dev,
626 struct iio_chan_spec const *chan,
627 int *val,
628 int *val2,
629 long m)
630{
631 struct ad9523_state *st = iio_priv(indio_dev);
632 unsigned code;
633 int ret;
634
635 mutex_lock(&indio_dev->mlock);
636 ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
637 mutex_unlock(&indio_dev->mlock);
638
639 if (ret < 0)
640 return ret;
641
642 switch (m) {
643 case IIO_CHAN_INFO_RAW:
644 *val = !(ret & AD9523_CLK_DIST_PWR_DOWN_EN);
645 return IIO_VAL_INT;
646 case IIO_CHAN_INFO_FREQUENCY:
647 *val = st->vco_out_freq[st->vco_out_map[chan->channel]] /
648 AD9523_CLK_DIST_DIV_REV(ret);
649 return IIO_VAL_INT;
650 case IIO_CHAN_INFO_PHASE:
651 code = (AD9523_CLK_DIST_DIV_PHASE_REV(ret) * 3141592) /
652 AD9523_CLK_DIST_DIV_REV(ret);
653 *val = code / 1000000;
654 *val2 = (code % 1000000) * 10;
655 return IIO_VAL_INT_PLUS_MICRO;
656 default:
657 return -EINVAL;
658 }
659};
660
661static int ad9523_write_raw(struct iio_dev *indio_dev,
662 struct iio_chan_spec const *chan,
663 int val,
664 int val2,
665 long mask)
666{
667 struct ad9523_state *st = iio_priv(indio_dev);
668 unsigned reg;
669 int ret, tmp, code;
670
671 mutex_lock(&indio_dev->mlock);
672 ret = ad9523_read(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel));
673 if (ret < 0)
674 goto out;
675
676 reg = ret;
677
678 switch (mask) {
679 case IIO_CHAN_INFO_RAW:
680 if (val)
681 reg &= ~AD9523_CLK_DIST_PWR_DOWN_EN;
682 else
683 reg |= AD9523_CLK_DIST_PWR_DOWN_EN;
684 break;
685 case IIO_CHAN_INFO_FREQUENCY:
686 if (val <= 0) {
687 ret = -EINVAL;
688 goto out;
689 }
690 ret = ad9523_set_clock_provider(indio_dev, chan->channel, val);
691 if (ret < 0)
692 goto out;
693 tmp = st->vco_out_freq[st->vco_out_map[chan->channel]] / val;
694 tmp = clamp(tmp, 1, 1024);
695 reg &= ~(0x3FF << 8);
696 reg |= AD9523_CLK_DIST_DIV(tmp);
697 break;
698 case IIO_CHAN_INFO_PHASE:
699 code = val * 1000000 + val2 % 1000000;
700 tmp = (code * AD9523_CLK_DIST_DIV_REV(ret)) / 3141592;
701 tmp = clamp(tmp, 0, 63);
702 reg &= ~AD9523_CLK_DIST_DIV_PHASE(~0);
703 reg |= AD9523_CLK_DIST_DIV_PHASE(tmp);
704 break;
705 default:
706 ret = -EINVAL;
707 goto out;
708 }
709
710 ret = ad9523_write(indio_dev, AD9523_CHANNEL_CLOCK_DIST(chan->channel),
711 reg);
712 if (ret < 0)
713 goto out;
714
715 ad9523_io_update(indio_dev);
716out:
717 mutex_unlock(&indio_dev->mlock);
718 return ret;
719}
720
721static int ad9523_reg_access(struct iio_dev *indio_dev,
722 unsigned reg, unsigned writeval,
723 unsigned *readval)
724{
725 int ret;
726
727 mutex_lock(&indio_dev->mlock);
728 if (readval == NULL) {
729 ret = ad9523_write(indio_dev, reg | AD9523_R1B, writeval);
730 ad9523_io_update(indio_dev);
731 } else {
732 ret = ad9523_read(indio_dev, reg | AD9523_R1B);
733 if (ret < 0)
734 return ret;
735 *readval = ret;
736 ret = 0;
737 }
738 mutex_unlock(&indio_dev->mlock);
739
740 return ret;
741}
742
743static const struct iio_info ad9523_info = {
744 .read_raw = &ad9523_read_raw,
745 .write_raw = &ad9523_write_raw,
746 .debugfs_reg_access = &ad9523_reg_access,
747 .attrs = &ad9523_attribute_group,
748 .driver_module = THIS_MODULE,
749};
750
751static int ad9523_setup(struct iio_dev *indio_dev)
752{
753 struct ad9523_state *st = iio_priv(indio_dev);
754 struct ad9523_platform_data *pdata = st->pdata;
755 struct ad9523_channel_spec *chan;
756 unsigned long active_mask = 0;
757 int ret, i;
758
759 ret = ad9523_write(indio_dev, AD9523_SERIAL_PORT_CONFIG,
760 AD9523_SER_CONF_SOFT_RESET |
761 (st->spi->mode & SPI_3WIRE ? 0 :
762 AD9523_SER_CONF_SDO_ACTIVE));
763 if (ret < 0)
764 return ret;
765
766 ret = ad9523_write(indio_dev, AD9523_READBACK_CTRL,
767 AD9523_READBACK_CTRL_READ_BUFFERED);
768 if (ret < 0)
769 return ret;
770
771 ret = ad9523_io_update(indio_dev);
772 if (ret < 0)
773 return ret;
774
775 /*
776 * PLL1 Setup
777 */
778 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_A_DIVIDER,
779 pdata->refa_r_div);
780 if (ret < 0)
781 return ret;
782
783 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_B_DIVIDER,
784 pdata->refb_r_div);
785 if (ret < 0)
786 return ret;
787
788 ret = ad9523_write(indio_dev, AD9523_PLL1_FEEDBACK_DIVIDER,
789 pdata->pll1_feedback_div);
790 if (ret < 0)
791 return ret;
792
793 ret = ad9523_write(indio_dev, AD9523_PLL1_CHARGE_PUMP_CTRL,
794 AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(pdata->
795 pll1_charge_pump_current_nA) |
796 AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL |
797 AD9523_PLL1_BACKLASH_PW_MIN);
798 if (ret < 0)
799 return ret;
800
801 ret = ad9523_write(indio_dev, AD9523_PLL1_INPUT_RECEIVERS_CTRL,
802 AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_RCV_EN) |
803 AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_RCV_EN) |
804 AD_IF(osc_in_diff_en, AD9523_PLL1_OSC_IN_DIFF_EN) |
805 AD_IF(osc_in_cmos_neg_inp_en,
806 AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN) |
807 AD_IF(refa_diff_rcv_en, AD9523_PLL1_REFA_DIFF_RCV_EN) |
808 AD_IF(refb_diff_rcv_en, AD9523_PLL1_REFB_DIFF_RCV_EN));
809 if (ret < 0)
810 return ret;
811
812 ret = ad9523_write(indio_dev, AD9523_PLL1_REF_CTRL,
813 AD_IF(zd_in_diff_en, AD9523_PLL1_ZD_IN_DIFF_EN) |
814 AD_IF(zd_in_cmos_neg_inp_en,
815 AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN) |
816 AD_IF(zero_delay_mode_internal_en,
817 AD9523_PLL1_ZERO_DELAY_MODE_INT) |
818 AD_IF(osc_in_feedback_en, AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN) |
819 AD_IF(refa_cmos_neg_inp_en, AD9523_PLL1_REFA_CMOS_NEG_INP_EN) |
820 AD_IF(refb_cmos_neg_inp_en, AD9523_PLL1_REFB_CMOS_NEG_INP_EN));
821 if (ret < 0)
822 return ret;
823
824 ret = ad9523_write(indio_dev, AD9523_PLL1_MISC_CTRL,
825 AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN |
826 AD9523_PLL1_REF_MODE(pdata->ref_mode));
827 if (ret < 0)
828 return ret;
829
830 ret = ad9523_write(indio_dev, AD9523_PLL1_LOOP_FILTER_CTRL,
831 AD9523_PLL1_LOOP_FILTER_RZERO(pdata->pll1_loop_filter_rzero));
832 if (ret < 0)
833 return ret;
834 /*
835 * PLL2 Setup
836 */
837
838 ret = ad9523_write(indio_dev, AD9523_PLL2_CHARGE_PUMP,
839 AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(pdata->
840 pll2_charge_pump_current_nA));
841 if (ret < 0)
842 return ret;
843
844 ret = ad9523_write(indio_dev, AD9523_PLL2_FEEDBACK_DIVIDER_AB,
845 AD9523_PLL2_FB_NDIV_A_CNT(pdata->pll2_ndiv_a_cnt) |
846 AD9523_PLL2_FB_NDIV_B_CNT(pdata->pll2_ndiv_b_cnt));
847 if (ret < 0)
848 return ret;
849
850 ret = ad9523_write(indio_dev, AD9523_PLL2_CTRL,
851 AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL |
852 AD9523_PLL2_BACKLASH_CTRL_EN |
853 AD_IF(pll2_freq_doubler_en, AD9523_PLL2_FREQ_DOUBLER_EN));
854 if (ret < 0)
855 return ret;
856
857 st->vco_freq = (pdata->vcxo_freq * (pdata->pll2_freq_doubler_en ? 2 : 1)
858 / pdata->pll2_r2_div) * AD9523_PLL2_FB_NDIV(pdata->
859 pll2_ndiv_a_cnt, pdata->pll2_ndiv_b_cnt);
860
861 ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_CTRL,
862 AD9523_PLL2_VCO_CALIBRATE);
863 if (ret < 0)
864 return ret;
865
866 ret = ad9523_write(indio_dev, AD9523_PLL2_VCO_DIVIDER,
867 AD9523_PLL2_VCO_DIV_M1(pdata->pll2_vco_diff_m1) |
868 AD9523_PLL2_VCO_DIV_M2(pdata->pll2_vco_diff_m2) |
869 AD_IFE(pll2_vco_diff_m1, 0,
870 AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN) |
871 AD_IFE(pll2_vco_diff_m2, 0,
872 AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN));
873 if (ret < 0)
874 return ret;
875
876 if (pdata->pll2_vco_diff_m1)
877 st->vco_out_freq[AD9523_VCO1] =
878 st->vco_freq / pdata->pll2_vco_diff_m1;
879
880 if (pdata->pll2_vco_diff_m2)
881 st->vco_out_freq[AD9523_VCO2] =
882 st->vco_freq / pdata->pll2_vco_diff_m2;
883
884 st->vco_out_freq[AD9523_VCXO] = pdata->vcxo_freq;
885
886 ret = ad9523_write(indio_dev, AD9523_PLL2_R2_DIVIDER,
887 AD9523_PLL2_R2_DIVIDER_VAL(pdata->pll2_r2_div));
888 if (ret < 0)
889 return ret;
890
891 ret = ad9523_write(indio_dev, AD9523_PLL2_LOOP_FILTER_CTRL,
892 AD9523_PLL2_LOOP_FILTER_CPOLE1(pdata->cpole1) |
893 AD9523_PLL2_LOOP_FILTER_RZERO(pdata->rzero) |
894 AD9523_PLL2_LOOP_FILTER_RPOLE2(pdata->rpole2) |
895 AD_IF(rzero_bypass_en,
896 AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN));
897 if (ret < 0)
898 return ret;
899
900 for (i = 0; i < pdata->num_channels; i++) {
901 chan = &pdata->channels[i];
902 if (chan->channel_num < AD9523_NUM_CHAN) {
903 __set_bit(chan->channel_num, &active_mask);
904 ret = ad9523_write(indio_dev,
905 AD9523_CHANNEL_CLOCK_DIST(chan->channel_num),
906 AD9523_CLK_DIST_DRIVER_MODE(chan->driver_mode) |
907 AD9523_CLK_DIST_DIV(chan->channel_divider) |
908 AD9523_CLK_DIST_DIV_PHASE(chan->divider_phase) |
909 (chan->sync_ignore_en ?
910 AD9523_CLK_DIST_IGNORE_SYNC_EN : 0) |
911 (chan->divider_output_invert_en ?
912 AD9523_CLK_DIST_INV_DIV_OUTPUT_EN : 0) |
913 (chan->low_power_mode_en ?
914 AD9523_CLK_DIST_LOW_PWR_MODE_EN : 0) |
915 (chan->output_dis ?
916 AD9523_CLK_DIST_PWR_DOWN_EN : 0));
917 if (ret < 0)
918 return ret;
919
920 ret = ad9523_vco_out_map(indio_dev, chan->channel_num,
921 chan->use_alt_clock_src);
922 if (ret < 0)
923 return ret;
924
925 st->ad9523_channels[i].type = IIO_ALTVOLTAGE;
926 st->ad9523_channels[i].output = 1;
927 st->ad9523_channels[i].indexed = 1;
928 st->ad9523_channels[i].channel = chan->channel_num;
929 st->ad9523_channels[i].extend_name =
930 chan->extended_name;
931 st->ad9523_channels[i].info_mask =
932 IIO_CHAN_INFO_RAW_SEPARATE_BIT |
933 IIO_CHAN_INFO_PHASE_SEPARATE_BIT |
934 IIO_CHAN_INFO_FREQUENCY_SEPARATE_BIT;
935 }
936 }
937
938 for_each_clear_bit(i, &active_mask, AD9523_NUM_CHAN)
939 ad9523_write(indio_dev,
940 AD9523_CHANNEL_CLOCK_DIST(i),
941 AD9523_CLK_DIST_DRIVER_MODE(TRISTATE) |
942 AD9523_CLK_DIST_PWR_DOWN_EN);
943
944 ret = ad9523_write(indio_dev, AD9523_POWER_DOWN_CTRL, 0);
945 if (ret < 0)
946 return ret;
947
948 ret = ad9523_write(indio_dev, AD9523_STATUS_SIGNALS,
949 AD9523_STATUS_MONITOR_01_PLL12_LOCKED);
950 if (ret < 0)
951 return ret;
952
953 ret = ad9523_io_update(indio_dev);
954 if (ret < 0)
955 return ret;
956
957 return 0;
958}
959
960static int __devinit ad9523_probe(struct spi_device *spi)
961{
962 struct ad9523_platform_data *pdata = spi->dev.platform_data;
963 struct iio_dev *indio_dev;
964 struct ad9523_state *st;
965 int ret;
966
967 if (!pdata) {
968 dev_err(&spi->dev, "no platform data?\n");
969 return -EINVAL;
970 }
971
972 indio_dev = iio_device_alloc(sizeof(*st));
973 if (indio_dev == NULL)
974 return -ENOMEM;
975
976 st = iio_priv(indio_dev);
977
978 st->reg = regulator_get(&spi->dev, "vcc");
979 if (!IS_ERR(st->reg)) {
980 ret = regulator_enable(st->reg);
981 if (ret)
982 goto error_put_reg;
983 }
984
985 spi_set_drvdata(spi, indio_dev);
986 st->spi = spi;
987 st->pdata = pdata;
988
989 indio_dev->dev.parent = &spi->dev;
990 indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
991 spi_get_device_id(spi)->name;
992 indio_dev->info = &ad9523_info;
993 indio_dev->modes = INDIO_DIRECT_MODE;
994 indio_dev->channels = st->ad9523_channels;
995 indio_dev->num_channels = pdata->num_channels;
996
997 ret = ad9523_setup(indio_dev);
998 if (ret < 0)
999 goto error_disable_reg;
1000
1001 ret = iio_device_register(indio_dev);
1002 if (ret)
1003 goto error_disable_reg;
1004
1005 dev_info(&spi->dev, "probed %s\n", indio_dev->name);
1006
1007 return 0;
1008
1009error_disable_reg:
1010 if (!IS_ERR(st->reg))
1011 regulator_disable(st->reg);
1012error_put_reg:
1013 if (!IS_ERR(st->reg))
1014 regulator_put(st->reg);
1015
1016 iio_device_free(indio_dev);
1017
1018 return ret;
1019}
1020
1021static int __devexit ad9523_remove(struct spi_device *spi)
1022{
1023 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1024 struct ad9523_state *st = iio_priv(indio_dev);
1025
1026 iio_device_unregister(indio_dev);
1027
1028 if (!IS_ERR(st->reg)) {
1029 regulator_disable(st->reg);
1030 regulator_put(st->reg);
1031 }
1032
1033 iio_device_free(indio_dev);
1034
1035 return 0;
1036}
1037
1038static const struct spi_device_id ad9523_id[] = {
1039 {"ad9523-1", 9523},
1040 {}
1041};
1042MODULE_DEVICE_TABLE(spi, ad9523_id);
1043
1044static struct spi_driver ad9523_driver = {
1045 .driver = {
1046 .name = "ad9523",
1047 .owner = THIS_MODULE,
1048 },
1049 .probe = ad9523_probe,
1050 .remove = __devexit_p(ad9523_remove),
1051 .id_table = ad9523_id,
1052};
1053module_spi_driver(ad9523_driver);
1054
1055MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1056MODULE_DESCRIPTION("Analog Devices AD9523 CLOCKDIST/PLL");
1057MODULE_LICENSE("GPL v2");
diff --git a/include/linux/iio/frequency/ad9523.h b/include/linux/iio/frequency/ad9523.h
new file mode 100644
index 000000000000..12ce3ee427fd
--- /dev/null
+++ b/include/linux/iio/frequency/ad9523.h
@@ -0,0 +1,195 @@
1/*
2 * AD9523 SPI Low Jitter Clock Generator
3 *
4 * Copyright 2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9#ifndef IIO_FREQUENCY_AD9523_H_
10#define IIO_FREQUENCY_AD9523_H_
11
12enum outp_drv_mode {
13 TRISTATE,
14 LVPECL_8mA,
15 LVDS_4mA,
16 LVDS_7mA,
17 HSTL0_16mA,
18 HSTL1_8mA,
19 CMOS_CONF1,
20 CMOS_CONF2,
21 CMOS_CONF3,
22 CMOS_CONF4,
23 CMOS_CONF5,
24 CMOS_CONF6,
25 CMOS_CONF7,
26 CMOS_CONF8,
27 CMOS_CONF9
28};
29
30enum ref_sel_mode {
31 NONEREVERTIVE_STAY_ON_REFB,
32 REVERT_TO_REFA,
33 SELECT_REFA,
34 SELECT_REFB,
35 EXT_REF_SEL
36};
37
38/**
39 * struct ad9523_channel_spec - Output channel configuration
40 *
41 * @channel_num: Output channel number.
42 * @divider_output_invert_en: Invert the polarity of the output clock.
43 * @sync_ignore_en: Ignore chip-level SYNC signal.
44 * @low_power_mode_en: Reduce power used in the differential output modes.
45 * @use_alt_clock_src: Channel divider uses alternative clk source.
46 * @output_dis: Disables, powers down the entire channel.
47 * @driver_mode: Output driver mode (logic level family).
48 * @divider_phase: Divider initial phase after a SYNC. Range 0..63
49 LSB = 1/2 of a period of the divider input clock.
50 * @channel_divider: 10-bit channel divider.
51 * @extended_name: Optional descriptive channel name.
52 */
53
54struct ad9523_channel_spec {
55 unsigned channel_num;
56 bool divider_output_invert_en;
57 bool sync_ignore_en;
58 bool low_power_mode_en;
59 /* CH0..CH3 VCXO, CH4..CH9 VCO2 */
60 bool use_alt_clock_src;
61 bool output_dis;
62 enum outp_drv_mode driver_mode;
63 unsigned char divider_phase;
64 unsigned short channel_divider;
65 char extended_name[16];
66};
67
68enum pll1_rzero_resistor {
69 RZERO_883_OHM,
70 RZERO_677_OHM,
71 RZERO_341_OHM,
72 RZERO_135_OHM,
73 RZERO_10_OHM,
74 RZERO_USE_EXT_RES = 8,
75};
76
77enum rpole2_resistor {
78 RPOLE2_900_OHM,
79 RPOLE2_450_OHM,
80 RPOLE2_300_OHM,
81 RPOLE2_225_OHM,
82};
83
84enum rzero_resistor {
85 RZERO_3250_OHM,
86 RZERO_2750_OHM,
87 RZERO_2250_OHM,
88 RZERO_2100_OHM,
89 RZERO_3000_OHM,
90 RZERO_2500_OHM,
91 RZERO_2000_OHM,
92 RZERO_1850_OHM,
93};
94
95enum cpole1_capacitor {
96 CPOLE1_0_PF,
97 CPOLE1_8_PF,
98 CPOLE1_16_PF,
99 CPOLE1_24_PF,
100 _CPOLE1_24_PF, /* place holder */
101 CPOLE1_32_PF,
102 CPOLE1_40_PF,
103 CPOLE1_48_PF,
104};
105
106/**
107 * struct ad9523_platform_data - platform specific information
108 *
109 * @vcxo_freq: External VCXO frequency in Hz
110 * @refa_diff_rcv_en: REFA differential/single-ended input selection.
111 * @refb_diff_rcv_en: REFB differential/single-ended input selection.
112 * @zd_in_diff_en: Zero Delay differential/single-ended input selection.
113 * @osc_in_diff_en: OSC differential/ single-ended input selection.
114 * @refa_cmos_neg_inp_en: REFA single-ended neg./pos. input enable.
115 * @refb_cmos_neg_inp_en: REFB single-ended neg./pos. input enable.
116 * @zd_in_cmos_neg_inp_en: Zero Delay single-ended neg./pos. input enable.
117 * @osc_in_cmos_neg_inp_en: OSC single-ended neg./pos. input enable.
118 * @refa_r_div: PLL1 10-bit REFA R divider.
119 * @refb_r_div: PLL1 10-bit REFB R divider.
120 * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
121 * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
122 * @zero_delay_mode_internal_en: Internal, external Zero Delay mode selection.
123 * @osc_in_feedback_en: PLL1 feedback path, local feedback from
124 * the OSC_IN receiver or zero delay mode
125 * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
126 * @ref_mode: Reference selection mode.
127 * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
128 * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
129 * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
130 * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
131 * @pll2_r2_div: PLL2 R2 divider, range 0..31.
132 * @pll2_vco_diff_m1: VCO1 divider, range 3..5.
133 * @pll2_vco_diff_m2: VCO2 divider, range 3..5.
134 * @rpole2: PLL2 loop filter Rpole resistor value.
135 * @rzero: PLL2 loop filter Rzero resistor value.
136 * @cpole1: PLL2 loop filter Cpole capacitor value.
137 * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
138 * @num_channels: Array size of struct ad9523_channel_spec.
139 * @channels: Pointer to channel array.
140 * @name: Optional alternative iio device name.
141 */
142
143struct ad9523_platform_data {
144 unsigned long vcxo_freq;
145
146 /* Differential/ Single-Ended Input Configuration */
147 bool refa_diff_rcv_en;
148 bool refb_diff_rcv_en;
149 bool zd_in_diff_en;
150 bool osc_in_diff_en;
151
152 /*
153 * Valid if differential input disabled
154 * if false defaults to pos input
155 */
156 bool refa_cmos_neg_inp_en;
157 bool refb_cmos_neg_inp_en;
158 bool zd_in_cmos_neg_inp_en;
159 bool osc_in_cmos_neg_inp_en;
160
161 /* PLL1 Setting */
162 unsigned short refa_r_div;
163 unsigned short refb_r_div;
164 unsigned short pll1_feedback_div;
165 unsigned short pll1_charge_pump_current_nA;
166 bool zero_delay_mode_internal_en;
167 bool osc_in_feedback_en;
168 enum pll1_rzero_resistor pll1_loop_filter_rzero;
169
170 /* Reference */
171 enum ref_sel_mode ref_mode;
172
173 /* PLL2 Setting */
174 unsigned int pll2_charge_pump_current_nA;
175 unsigned char pll2_ndiv_a_cnt;
176 unsigned char pll2_ndiv_b_cnt;
177 bool pll2_freq_doubler_en;
178 unsigned char pll2_r2_div;
179 unsigned char pll2_vco_diff_m1; /* 3..5 */
180 unsigned char pll2_vco_diff_m2; /* 3..5 */
181
182 /* Loop Filter PLL2 */
183 enum rpole2_resistor rpole2;
184 enum rzero_resistor rzero;
185 enum cpole1_capacitor cpole1;
186 bool rzero_bypass_en;
187
188 /* Output Channel Configuration */
189 int num_channels;
190 struct ad9523_channel_spec *channels;
191
192 char name[SPI_NAME_SIZE];
193};
194
195#endif /* IIO_FREQUENCY_AD9523_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 00:47:56 -0400