aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 2d811d975ca8..2030f3d9fac7 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -37,8 +37,6 @@
37 37
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
39static struct clk r_clk = { 39static struct clk r_clk = {
40 .name = "rclk",
41 .id = -1,
42 .rate = 32768, 40 .rate = 32768,
43}; 41};
44 42
@@ -47,8 +45,6 @@ static struct clk r_clk = {
47 * from the platform code. 45 * from the platform code.
48 */ 46 */
49struct clk extal_clk = { 47struct clk extal_clk = {
50 .name = "extal",
51 .id = -1,
52 .rate = 33333333, 48 .rate = 33333333,
53}; 49};
54 50
@@ -70,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
70}; 66};
71 67
72static struct clk dll_clk = { 68static struct clk dll_clk = {
73 .name = "dll_clk",
74 .id = -1,
75 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
76 .parent = &r_clk, 70 .parent = &r_clk,
77 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -95,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
95}; 89};
96 90
97static struct clk pll_clk = { 91static struct clk pll_clk = {
98 .name = "pll_clk",
99 .id = -1,
100 .ops = &pll_clk_ops, 92 .ops = &pll_clk_ops,
101 .flags = CLK_ENABLE_ON_INIT, 93 .flags = CLK_ENABLE_ON_INIT,
102}; 94};
@@ -186,6 +178,12 @@ static struct clk mstp_clks[HWBLK_NR] = {
186#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 178#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
187 179
188static struct clk_lookup lookups[] = { 180static struct clk_lookup lookups[] = {
181 /* main clocks */
182 CLKDEV_CON_ID("rclk", &r_clk),
183 CLKDEV_CON_ID("extal", &extal_clk),
184 CLKDEV_CON_ID("dll_clk", &dll_clk),
185 CLKDEV_CON_ID("pll_clk", &pll_clk),
186
189 /* DIV4 clocks */ 187 /* DIV4 clocks */
190 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 188 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
191 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 189 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),