101 files changed, 3510 insertions, 1575 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
new file mode 100644
index 000000000000..3a4e5901ce31
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
@@ -0,0 +1,79 @@
+OMAP Control Module bindings
+Control Module contains miscellaneous features under it based on SoC type.
+Pincontrol is one common feature, and it has a specialized support
+described in [1]. Typically some clock nodes are also under control module.
+Syscon is used to share register level access to drivers external to
+control module driver itself.
+See [2] for documentation about clock/clockdomain nodes.
+[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+[2] Documentation/devicetree/bindings/clock/ti/*
+Required properties:
+- compatible:   Must be one of:
+                "ti,am3-scm"
+                "ti,am4-scm"
+                "ti,dm814-scrm"
+                "ti,dm816-scrm"
+                "ti,omap2-scm"
+                "ti,omap3-scm"
+                "ti,omap4-scm-core"
+                "ti,omap4-scm-padconf-core"
+                "ti,omap5-scm-core"
+                "ti,omap5-scm-padconf-core"
+                "ti,dra7-scm-core"
+- reg:          Contains Control Module register address range
+                (base address and length)
+Optional properties:
+- clocks:       clocks for this module
+- clockdomains: clockdomains for this module
+Examples:
+scm: scm@2000 {
+        compatible = "ti,omap3-scm", "simple-bus";
+        reg = <0x2000 0x2000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0 0x2000 0x2000>;
+        omap3_pmx_core: pinmux@30 {
+                compatible = "ti,omap3-padconf",
+                             "pinctrl-single";
+                reg = <0x30 0x230>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                pinctrl-single,register-width = <16>;
+                pinctrl-single,function-mask = <0xff1f>;
+        };
+        scm_conf: scm_conf@270 {
+                compatible = "syscon";
+                reg = <0x270 0x330>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                scm_clocks: clocks {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+        scm_clockdomains: clockdomains {
+        };
+}
+&scm_clocks {
+        mcbsp5_mux_fck: mcbsp5_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <4>;
+                reg = <0x02d8>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt
new file mode 100644
index 000000000000..b4f8a16e7e3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/l4.txt
@@ -0,0 +1,26 @@
+L4 interconnect bindings
+These bindings describe the OMAP SoCs L4 interconnect bus.
+Required properties:
+- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
+               Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
+               Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
+               Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
+               Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
+               Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
+               Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
+               Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
+               Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus
+               Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
+               Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
+- ranges : contains the IO map range for the bus
+Examples:
+l4: l4@48000000 {
+        compatible "ti,omap2-l4", "simple-bus";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0 0x48000000 0x100000>;
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt
index 79074dac684a..3eb6d7afff14 100644
--- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -10,14 +10,10 @@ documentation about the individual clock/clockdomain nodes.
 Required properties:
 - compatible:   Must be one of:
                "ti,am3-prcm"
-                "ti,am3-scrm"
                "ti,am4-prcm"
-                "ti,am4-scrm"
                "ti,omap2-prcm"
-                "ti,omap2-scrm"
                "ti,omap3-prm"
                "ti,omap3-cm"
-                "ti,omap3-scrm"
                "ti,omap4-cm1"
                "ti,omap4-prm"
                "ti,omap4-cm2"
@@ -29,6 +25,8 @@ Required properties:
                "ti,dra7-prm"
                "ti,dra7-cm-core-aon"
                "ti,dra7-cm-core"
+                "ti,dm814-prcm"
+                "ti,dm816-prcm"
 - reg:          Contains PRCM module register address range
                (base address and length)
 - clocks:       clocks for this module
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a384cce5c31d..86217db2937a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -307,9 +307,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
        imx6q-wandboard.dtb \
        imx6q-wandboard-revb1.dtb
 dtb-$(CONFIG_SOC_IMX6SL) += \
-        imx6sl-evk.dtb
+        imx6sl-evk.dtb \
+        imx6sl-warp.dtb
 dtb-$(CONFIG_SOC_IMX6SX) += \
        imx6sx-sabreauto.dtb \
+        imx6sx-sdb-reva.dtb \
        imx6sx-sdb.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
        ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 071b56aa0c7e..afb4b3a7bab4 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -7,7 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-&scrm_clocks {
+&scm_clocks {
        sys_clkin_ck: sys_clkin_ck {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index acd37057bca9..21fcc440fc1a 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,20 +83,6 @@
                };
        };
-        am33xx_control_module: control_module@4a002000 {
-                compatible = "syscon";
-                reg = <0x44e10000 0x7fc>;
-        };
-        am33xx_pinmux: pinmux@44e10800 {
-                compatible = "pinctrl-single";
-                reg = <0x44e10800 0x0238>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-single,register-width = <32>;
-                pinctrl-single,function-mask = <0x7f>;
-        };
        /*
         * XXX: Use a flat representation of the AM33XX interconnect.
         * The real AM33XX interconnect network is quite complex. Since
@@ -111,37 +97,58 @@
                ranges;
                ti,hwmods = "l3_main";
-                prcm: prcm@44e00000 {
+                l4_wkup: l4_wkup@44c00000 {
-                        compatible = "ti,am3-prcm";
+                        compatible = "ti,am3-l4-wkup", "simple-bus";
-                        reg = <0x44e00000 0x4000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
-                        prcm_clocks: clocks {
+                        ranges = <0 0x44c00000 0x280000>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        prcm_clockdomains: clockdomains {
+                        prcm: prcm@200000 {
-                        };
+                                compatible = "ti,am3-prcm";
-                };
+                                reg = <0x200000 0x4000>;
-                scrm: scrm@44e10000 {
+                                prcm_clocks: clocks {
-                        compatible = "ti,am3-scrm";
+                                        #address-cells = <1>;
-                        reg = <0x44e10000 0x2000>;
+                                        #size-cells = <0>;
+                                };
-                        scrm_clocks: clocks {
+                                prcm_clockdomains: clockdomains {
-                                #address-cells = <1>;
+                                };
-                                #size-cells = <0>;
                        };
-                        scrm_clockdomains: clockdomains {
+                        scm: scm@210000 {
+                                compatible = "ti,am3-scm", "simple-bus";
+                                reg = <0x210000 0x2000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x210000 0x2000>;
+                                am33xx_pinmux: pinmux@800 {
+                                        compatible = "pinctrl-single";
+                                        reg = <0x800 0x238>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pinctrl-single,register-width = <32>;
+                                        pinctrl-single,function-mask = <0x7f>;
+                                };
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+                                scm_clockdomains: clockdomains {
+                                };
                        };
                };
-                cm: syscon@44e10000 {
-                        compatible = "ti,am33xx-controlmodule", "syscon";
-                        reg = <0x44e10000 0x800>;
-                };
                intc: interrupt-controller@48200000 {
                        compatible = "ti,am33xx-intc";
                        interrupt-controller;
@@ -350,7 +357,7 @@
                        reg = <0x481cc000 0x2000>;
                        clocks = <&dcan0_fck>;
                        clock-names = "fck";
-                        syscon-raminit = <&am33xx_control_module 0x644 0>;
+                        syscon-raminit = <&scm_conf 0x644 0>;
                        interrupts = <52>;
                        status = "disabled";
                };
@@ -361,7 +368,7 @@
                        reg = <0x481d0000 0x2000>;
                        clocks = <&dcan1_fck>;
                        clock-names = "fck";
-                        syscon-raminit = <&am33xx_control_module 0x644 1>;
+                        syscon-raminit = <&scm_conf 0x644 1>;
                        interrupts = <55>;
                        status = "disabled";
                };
@@ -720,7 +727,7 @@
                         */
                        interrupts = <40 41 42 43>;
                        ranges;
-                        syscon = <&cm>;
+                        syscon = <&scm_conf>;
                        status = "disabled";
                        davinci_mdio: mdio@4a101000 {
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index c90724bded10..f164dce08755 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -31,7 +31,7 @@
                        status = "disabled";
                        reg = <0x5c000000 0x30000>;
                        interrupts = <67 68 69 70>;
-                        syscon = <&omap3_scm_general>;
+                        syscon = <&scm_conf>;
                        ti,davinci-ctrl-reg-offset = <0x10000>;
                        ti,davinci-ctrl-mod-reg-offset = <0>;
                        ti,davinci-ctrl-ram-offset = <0x20000>;
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
index df489d310b50..518b8fde88b0 100644
--- a/arch/arm/boot/dts/am35xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -7,7 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-&scrm_clocks {
+&scm_clocks {
        emac_ick: emac_ick {
                #clock-cells = <0>;
                compatible = "ti,am35xx-gate-clock";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 1b7bda8c14b1..c80a3e233792 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -66,22 +66,6 @@
                cache-level = <2>;
        };
-        am43xx_control_module: control_module@4a002000 {
-                compatible = "syscon";
-                reg = <0x44e10000 0x7f4>;
-        };
-        am43xx_pinmux: pinmux@44e10800 {
-                compatible = "ti,am437-padconf", "pinctrl-single";
-                reg = <0x44e10800 0x31c>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                #interrupt-cells = <1>;
-                interrupt-controller;
-                pinctrl-single,register-width = <32>;
-                pinctrl-single,function-mask = <0xffffffff>;
-        };
        ocp {
                compatible = "ti,am4372-l3-noc", "simple-bus";
                #address-cells = <1>;
@@ -93,29 +77,58 @@
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                prcm: prcm@44df0000 {
+                l4_wkup: l4_wkup@44c00000 {
-                        compatible = "ti,am4-prcm";
+                        compatible = "ti,am4-l4-wkup", "simple-bus";
-                        reg = <0x44df0000 0x11000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
-                        prcm_clocks: clocks {
+                        ranges = <0 0x44c00000 0x287000>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        prcm_clockdomains: clockdomains {
+                        prcm: prcm@1f0000 {
-                        };
+                                compatible = "ti,am4-prcm";
-                };
+                                reg = <0x1f0000 0x11000>;
-                scrm: scrm@44e10000 {
+                                prcm_clocks: clocks {
-                        compatible = "ti,am4-scrm";
+                                        #address-cells = <1>;
-                        reg = <0x44e10000 0x2000>;
+                                        #size-cells = <0>;
+                                };
-                        scrm_clocks: clocks {
+                                prcm_clockdomains: clockdomains {
-                                #address-cells = <1>;
+                                };
-                                #size-cells = <0>;
                        };
-                        scrm_clockdomains: clockdomains {
+                        scm: scm@210000 {
+                                compatible = "ti,am4-scm", "simple-bus";
+                                reg = <0x210000 0x4000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x210000 0x4000>;
+                                am43xx_pinmux: pinmux@800 {
+                                        compatible = "ti,am437-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x800 0x31c>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <32>;
+                                        pinctrl-single,function-mask = <0xffffffff>;
+                                };
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+                                scm_clockdomains: clockdomains {
+                                };
                        };
                };
@@ -942,7 +955,7 @@
                        clocks = <&dcan0_fck>;
                        clock-names = "fck";
                        reg = <0x481cc000 0x2000>;
-                        syscon-raminit = <&am43xx_control_module 0x644 0>;
+                        syscon-raminit = <&scm_conf 0x644 0>;
                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
@@ -953,7 +966,7 @@
                        clocks = <&dcan1_fck>;
                        clock-names = "fck";
                        reg = <0x481d0000 0x2000>;
-                        syscon-raminit = <&am43xx_control_module 0x644 1>;
+                        syscon-raminit = <&scm_conf 0x644 1>;
                        interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 1d7109196872..795d68af6df9 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -69,7 +69,48 @@
                };
        };
-        am43xx_pinmux: pinmux@44e10800 {
+        matrix_keypad: matrix_keypad@0 {
+                compatible = "gpio-matrix-keypad";
+                debounce-delay-ms = <5>;
+                col-scan-delay-us = <2>;
+                row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
+                             &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
+                             &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
+                             &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
+                col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
+                             &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
+                             &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
+                             &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
+                linux,keymap = <0x00000201      /* P1 */
+                        0x01000204      /* P4 */
+                        0x02000207      /* P7 */
+                        0x0300020a      /* NUMERIC_STAR */
+                        0x00010202      /* P2 */
+                        0x01010205      /* P5 */
+                        0x02010208      /* P8 */
+                        0x03010200      /* P0 */
+                        0x00020203      /* P3 */
+                        0x01020206      /* P6 */
+                        0x02020209      /* P9 */
+                        0x0302020b      /* NUMERIC_POUND */
+                        0x00030067      /* UP */
+                        0x0103006a      /* RIGHT */
+                        0x0203006c      /* DOWN */
+                        0x03030069>;    /* LEFT */
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+                brightness-levels = <0 51 53 56 62 75 101 152 255>;
+                default-brightness-level = <8>;
+        };
+};
+&am43xx_pinmux {
                cpsw_default: cpsw_default {
                        pinctrl-single,pins = <
                                /* Slave 1 */
@@ -279,47 +320,6 @@
                                0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
                        >;
                };
-        };
-        matrix_keypad: matrix_keypad@0 {
-                        compatible = "gpio-matrix-keypad";
-                        debounce-delay-ms = <5>;
-                        col-scan-delay-us = <2>;
-                        row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
-                                     &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
-                                     &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
-                                     &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
-                        col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
-                                     &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
-                                     &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
-                                     &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
-                        linux,keymap = <0x00000201      /* P1 */
-                                0x01000204      /* P4 */
-                                0x02000207      /* P7 */
-                                0x0300020a      /* NUMERIC_STAR */
-                                0x00010202      /* P2 */
-                                0x01010205      /* P5 */
-                                0x02010208      /* P8 */
-                                0x03010200      /* P0 */
-                                0x00020203      /* P3 */
-                                0x01020206      /* P6 */
-                                0x02020209      /* P9 */
-                                0x0302020b      /* NUMERIC_POUND */
-                                0x00030067      /* UP */
-                                0x0103006a      /* RIGHT */
-                                0x0203006c      /* DOWN */
-                                0x03030069>;    /* LEFT */
-                };
-        backlight {
-                compatible = "pwm-backlight";
-                pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
-                brightness-levels = <0 51 53 56 62 75 101 152 255>;
-                default-brightness-level = <8>;
-        };
 };
 &mmc1 {
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index cfb49686ab6a..d0c0dfa4ec48 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -7,7 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-&scrm_clocks {
+&scm_clocks {
        sys_clkin_ck: sys_clkin_ck {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 082882c616e8..5332b57b4950 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -102,17 +102,101 @@
                interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                                      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                prm: prm@4ae06000 {
+                l4_cfg: l4@4a000000 {
-                        compatible = "ti,dra7-prm";
+                        compatible = "ti,dra7-l4-cfg", "simple-bus";
-                        reg = <0x4ae06000 0x3000>;
+                        #address-cells = <1>;
-                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4a000000 0x22c000>;
-                        prm_clocks: clocks {
+                        scm: scm@2000 {
+                                compatible = "ti,dra7-scm-core", "simple-bus";
+                                reg = <0x2000 0x2000>;
                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x2000>;
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x1400>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0xe00 0x4>;
+                                                syscon = <&scm_conf>;
+                                                pbias_mmc_reg: pbias_mmc_omap5 {
+                                                        regulator-name = "pbias_mmc_omap5";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
+                                dra7_pmx_core: pinmux@1400 {
+                                        compatible = "ti,dra7-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x1400 0x0464>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <32>;
+                                        pinctrl-single,function-mask = <0x3fffffff>;
+                                };
+                        };
+                        cm_core_aon: cm_core_aon@5000 {
+                                compatible = "ti,dra7-cm-core-aon";
+                                reg = <0x5000 0x2000>;
+                                cm_core_aon_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                                cm_core_aon_clockdomains: clockdomains {
+                                };
                        };
-                        prm_clockdomains: clockdomains {
+                        cm_core: cm_core@8000 {
+                                compatible = "ti,dra7-cm-core";
+                                reg = <0x8000 0x3000>;
+                                cm_core_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                                cm_core_clockdomains: clockdomains {
+                                };
+                        };
+                };
+                l4_wkup: l4@4ae00000 {
+                        compatible = "ti,dra7-l4-wkup", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4ae00000 0x3f000>;
+                        counter32k: counter@4000 {
+                                compatible = "ti,omap-counter32k";
+                                reg = <0x4000 0x40>;
+                                ti,hwmods = "counter_32k";
+                        };
+                        prm: prm@6000 {
+                                compatible = "ti,dra7-prm";
+                                reg = <0x6000 0x3000>;
+                                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                                prm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                                prm_clockdomains: clockdomains {
+                                };
                        };
                };
@@ -197,38 +281,6 @@
                                #thermal-sensor-cells = <1>;
                };
-                cm_core_aon: cm_core_aon@4a005000 {
-                        compatible = "ti,dra7-cm-core-aon";
-                        reg = <0x4a005000 0x2000>;
-                        cm_core_aon_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        cm_core_aon_clockdomains: clockdomains {
-                        };
-                };
-                cm_core: cm_core@4a008000 {
-                        compatible = "ti,dra7-cm-core";
-                        reg = <0x4a008000 0x3000>;
-                        cm_core_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        cm_core_clockdomains: clockdomains {
-                        };
-                };
-                counter32k: counter@4ae04000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x4ae04000 0x40>;
-                        ti,hwmods = "counter_32k";
-                };
                dra7_ctrl_core: ctrl_core@4a002000 {
                        compatible = "syscon";
                        reg = <0x4a002000 0x6d0>;
@@ -239,28 +291,6 @@
                        reg = <0x4a002e00 0x7c>;
                };
-                pbias_regulator: pbias_regulator {
-                        compatible = "ti,pbias-omap";
-                        reg = <0 0x4>;
-                        syscon = <&dra7_ctrl_general>;
-                        pbias_mmc_reg: pbias_mmc_omap5 {
-                                regulator-name = "pbias_mmc_omap5";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3000000>;
-                        };
-                };
-                dra7_pmx_core: pinmux@4a003400 {
-                        compatible = "ti,dra7-padconf", "pinctrl-single";
-                        reg = <0x4a003400 0x0464>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <32>;
-                        pinctrl-single,function-mask = <0x3fffffff>;
-                };
                sdma: dma-controller@4a056000 {
                        compatible = "ti,omap4430-sdma";
                        reg = <0x4a056000 0x1000>;
@@ -1424,7 +1454,7 @@
                        compatible = "ti,dra7-d_can";
                        ti,hwmods = "dcan1";
                        reg = <0x4ae3c000 0x2000>;
-                        syscon-raminit = <&dra7_ctrl_core 0x558 0>;
+                        syscon-raminit = <&scm_conf 0x558 0>;
                        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&dcan1_sys_clk_mux>;
                        status = "disabled";
@@ -1434,7 +1464,7 @@
                        compatible = "ti,dra7-d_can";
                        ti,hwmods = "dcan2";
                        reg = <0x48480000 0x2000>;
-                        syscon-raminit = <&dra7_ctrl_core 0x558 1>;
+                        syscon-raminit = <&scm_conf 0x558 1>;
                        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&sys_clkin1>;
                        status = "disabled";
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 9c21b1583762..dd45e6971bc3 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -75,6 +75,27 @@
                mux-int-port = <1>;
                mux-ext-port = <4>;
        };
+        wvga: display {
+                model = "CLAA057VC01CW";
+                bits-per-pixel = <16>;
+                fsl,pcr = <0xfa208b80>;
+                bus-width = <18>;
+                native-mode = <&wvga_timings>;
+                display-timings {
+                        wvga_timings: 640x480 {
+                                hactive = <640>;
+                                vactive = <480>;
+                                hback-porch = <45>;
+                                hfront-porch = <114>;
+                                hsync-len = <1>;
+                                vback-porch = <33>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock-frequency = <25200000>;
+                        };
+                };
+        };
 };
 &audmux {
@@ -190,6 +211,33 @@
                        >;
                };
+                pinctrl_lcd: lcdgrp {
+                        fsl,pins = <
+                                MX25_PAD_LD0__LD0               0xe0
+                                MX25_PAD_LD1__LD1               0xe0
+                                MX25_PAD_LD2__LD2               0xe0
+                                MX25_PAD_LD3__LD3               0xe0
+                                MX25_PAD_LD4__LD4               0xe0
+                                MX25_PAD_LD5__LD5               0xe0
+                                MX25_PAD_LD6__LD6               0xe0
+                                MX25_PAD_LD7__LD7               0xe0
+                                MX25_PAD_LD8__LD8               0xe0
+                                MX25_PAD_LD9__LD9               0xe0
+                                MX25_PAD_LD10__LD10             0xe0
+                                MX25_PAD_LD11__LD11             0xe0
+                                MX25_PAD_LD12__LD12             0xe0
+                                MX25_PAD_LD13__LD13             0xe0
+                                MX25_PAD_LD14__LD14             0xe0
+                                MX25_PAD_LD15__LD15             0xe0
+                                MX25_PAD_GPIO_E__LD16           0xe0
+                                MX25_PAD_GPIO_F__LD17           0xe0
+                                MX25_PAD_HSYNC__HSYNC           0xe0
+                                MX25_PAD_VSYNC__VSYNC           0xe0
+                                MX25_PAD_LSCLK__LSCLK           0xe0
+                                MX25_PAD_OE_ACD__OE_ACD         0xe0
+                                MX25_PAD_CONTRAST__CONTRAST     0xe0
+                        >;
+                };
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
@@ -202,6 +250,16 @@
        };
 };
+&lcdc {
+        display = <&wvga>;
+        fsl,lpccr = <0x00a903ff>;
+        fsl,lscr1 = <0x00120300>;
+        fsl,dmacr = <0x00020010>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcd>;
+        status = "okay";
+};
 &nfc {
        nand-on-flash-bbt;
        status = "okay";
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 88eebb15da6a..7c4b9f2f9aad 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -17,48 +17,69 @@
 * <mux_reg conf_reg input_reg mux_mode input_val>
 */
+#define MX25_PAD_TDO__TDO                       0x000 0x3e8 0x000 0x00 0x000
 #define MX25_PAD_A10__A10                       0x008 0x000 0x000 0x00 0x000
 #define MX25_PAD_A10__GPIO_4_0                  0x008 0x000 0x000 0x05 0x000
 #define MX25_PAD_A13__A13                       0x00c 0x22C 0x000 0x00 0x000
 #define MX25_PAD_A13__GPIO_4_1                  0x00c 0x22C 0x000 0x05 0x000
+#define MX25_PAD_A13__LCDC_CLS                  0x00c 0x22C 0x000 0x07 0x000
 #define MX25_PAD_A14__A14                       0x010 0x230 0x000 0x10 0x000
 #define MX25_PAD_A14__GPIO_2_0                  0x010 0x230 0x000 0x15 0x000
+#define MX25_PAD_A14__SIM1_CLK1                 0x010 0x230 0x000 0x16 0x000
+#define MX25_PAD_A14__LCDC_SPL                  0x010 0x230 0x000 0x17 0x000
 #define MX25_PAD_A15__A15                       0x014 0x234 0x000 0x10 0x000
 #define MX25_PAD_A15__GPIO_2_1                  0x014 0x234 0x000 0x15 0x000
+#define MX25_PAD_A15__SIM1_RST1                 0x014 0x234 0x000 0x16 0x000
+#define MX25_PAD_A15__LCDC_PS                   0x014 0x234 0x000 0x17 0x000
 #define MX25_PAD_A16__A16                       0x018 0x000 0x000 0x10 0x000
 #define MX25_PAD_A16__GPIO_2_2                  0x018 0x000 0x000 0x15 0x000
+#define MX25_PAD_A16__SIM1_VEN1                 0x018 0x000 0x000 0x16 0x000
+#define MX25_PAD_A16__LCDC_REV                  0x018 0x000 0x000 0x17 0x000
 #define MX25_PAD_A17__A17                       0x01c 0x238 0x000 0x10 0x000
 #define MX25_PAD_A17__GPIO_2_3                  0x01c 0x238 0x000 0x15 0x000
+#define MX25_PAD_A17__SIM1_TX                   0x01c 0x238 0x554 0x16 0x000
+#define MX25_PAD_A17__FEC_TX_ERR                0x01c 0x238 0x000 0x17 0x000
 #define MX25_PAD_A18__A18                       0x020 0x23c 0x000 0x10 0x000
 #define MX25_PAD_A18__GPIO_2_4                  0x020 0x23c 0x000 0x15 0x000
+#define MX25_PAD_A18__SIM1_PD1                  0x020 0x23c 0x550 0x16 0x000
 #define MX25_PAD_A18__FEC_COL                   0x020 0x23c 0x504 0x17 0x000
 #define MX25_PAD_A19__A19                       0x024 0x240 0x000 0x10 0x000
-#define MX25_PAD_A19__FEC_RX_ER                 0x024 0x240 0x518 0x17 0x000
 #define MX25_PAD_A19__GPIO_2_5                  0x024 0x240 0x000 0x15 0x000
+#define MX25_PAD_A19__SIM1_RX1                  0x024 0x240 0x54c 0x16 0x000
+#define MX25_PAD_A19__FEC_RX_ERR                0x024 0x240 0x518 0x17 0x000
 #define MX25_PAD_A20__A20                       0x028 0x244 0x000 0x10 0x000
 #define MX25_PAD_A20__GPIO_2_6                  0x028 0x244 0x000 0x15 0x000
+#define MX25_PAD_A20__SIM2_CLK1                 0x028 0x244 0x000 0x16 0x000
 #define MX25_PAD_A20__FEC_RDATA2                0x028 0x244 0x50c 0x17 0x000
 #define MX25_PAD_A21__A21                       0x02c 0x248 0x000 0x10 0x000
 #define MX25_PAD_A21__GPIO_2_7                  0x02c 0x248 0x000 0x15 0x000
+#define MX25_PAD_A21__SIM2_RST1                 0x02c 0x248 0x000 0x16 0x000
 #define MX25_PAD_A21__FEC_RDATA3                0x02c 0x248 0x510 0x17 0x000
 #define MX25_PAD_A22__A22                       0x030 0x000 0x000 0x10 0x000
 #define MX25_PAD_A22__GPIO_2_8                  0x030 0x000 0x000 0x15 0x000
+#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x17 0x000
+#define MX25_PAD_A22__SIM2_VEN1                 0x030 0x000 0x000 0x16 0x000
+#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x17 0x000
 #define MX25_PAD_A23__A23                       0x034 0x24c 0x000 0x10 0x000
 #define MX25_PAD_A23__GPIO_2_9                  0x034 0x24c 0x000 0x15 0x000
+#define MX25_PAD_A23__SIM2_TX1                  0x034 0x24c 0x560 0x16 0x000
+#define MX25_PAD_A23__FEC_TDATA3                0x034 0x24c 0x000 0x17 0x000
 #define MX25_PAD_A24__A24                       0x038 0x250 0x000 0x10 0x000
 #define MX25_PAD_A24__GPIO_2_10                 0x038 0x250 0x000 0x15 0x000
+#define MX25_PAD_A24__SIM2_PD1                  0x038 0x250 0x55c 0x16 0x000
 #define MX25_PAD_A24__FEC_RX_CLK                0x038 0x250 0x514 0x17 0x000
 #define MX25_PAD_A25__A25                       0x03c 0x254 0x000 0x10 0x000
@@ -133,20 +154,25 @@
 #define MX25_PAD_D15__D15                       0x088 0x280 0x000 0x00 0x000
 #define MX25_PAD_D15__LD16                      0x088 0x280 0x000 0x01 0x000
 #define MX25_PAD_D15__GPIO_4_5                  0x088 0x280 0x000 0x05 0x000
+#define MX25_PAD_D15__SDHC1_DAT7                0x088 0x280 0x4d8 0x06 0x000
 #define MX25_PAD_D14__D14                       0x08c 0x284 0x000 0x00 0x000
 #define MX25_PAD_D14__LD17                      0x08c 0x284 0x000 0x01 0x000
 #define MX25_PAD_D14__GPIO_4_6                  0x08c 0x284 0x000 0x05 0x000
+#define MX25_PAD_D14__SDHC1_DAT6                0x08c 0x284 0x4d4 0x06 0x000
 #define MX25_PAD_D13__D13                       0x090 0x288 0x000 0x00 0x000
 #define MX25_PAD_D13__LD18                      0x090 0x288 0x000 0x01 0x000
 #define MX25_PAD_D13__GPIO_4_7                  0x090 0x288 0x000 0x05 0x000
+#define MX25_PAD_D13__SDHC1_DAT5                0x090 0x288 0x4d0 0x06 0x000
 #define MX25_PAD_D12__D12                       0x094 0x28c 0x000 0x00 0x000
 #define MX25_PAD_D12__GPIO_4_8                  0x094 0x28c 0x000 0x05 0x000
+#define MX25_PAD_D12__SDHC1_DAT4                0x094 0x28c 0x4cc 0x06 0x000
 #define MX25_PAD_D11__D11                       0x098 0x290 0x000 0x00 0x000
 #define MX25_PAD_D11__GPIO_4_9                  0x098 0x290 0x000 0x05 0x000
+#define MX25_PAD_D11__USBOTG_PWR                0x098 0x290 0x000 0x06 0x000
 #define MX25_PAD_D10__D10                       0x09c 0x294 0x000 0x00 0x000
 #define MX25_PAD_D10__GPIO_4_10                 0x09c 0x294 0x000 0x05 0x000
@@ -212,26 +238,33 @@
 #define MX25_PAD_LD8__LD8                       0x0e8 0x2e0 0x000 0x10 0x000
 #define MX25_PAD_LD8__FEC_TX_ERR                0x0e8 0x2e0 0x000 0x15 0x000
+#define MX25_PAD_LD8__SDHC2_CMD                 0x0e8 0x2e0 0x4e0 0x06 0x000
 #define MX25_PAD_LD9__LD9                       0x0ec 0x2e4 0x000 0x10 0x000
 #define MX25_PAD_LD9__FEC_COL                   0x0ec 0x2e4 0x504 0x15 0x001
+#define MX25_PAD_LD9__SDHC2_CLK                 0x0ec 0x2e4 0x4dc 0x06 0x000
 #define MX25_PAD_LD10__LD10                     0x0f0 0x2e8 0x000 0x10 0x000
-#define MX25_PAD_LD10__FEC_RX_ER                0x0f0 0x2e8 0x518 0x15 0x001
+#define MX25_PAD_LD10__FEC_RX_ERR               0x0f0 0x2e8 0x518 0x15 0x001
 #define MX25_PAD_LD11__LD11                     0x0f4 0x2ec 0x000 0x10 0x000
 #define MX25_PAD_LD11__FEC_RDATA2               0x0f4 0x2ec 0x50c 0x15 0x001
+#define MX25_PAD_LD11__SDHC2_DAT1               0x0f4 0x2ec 0x4e8 0x06 0x000
 #define MX25_PAD_LD12__LD12                     0x0f8 0x2f0 0x000 0x10 0x000
+#define MX25_PAD_LD12__CSPI2_MOSI               0x0f8 0x2f0 0x4a0 0x02 0x000
 #define MX25_PAD_LD12__FEC_RDATA3               0x0f8 0x2f0 0x510 0x15 0x001
 #define MX25_PAD_LD13__LD13                     0x0fc 0x2f4 0x000 0x10 0x000
+#define MX25_PAD_LD13__CSPI2_MISO               0x0fc 0x2f4 0x49c 0x02 0x000
 #define MX25_PAD_LD13__FEC_TDATA2               0x0fc 0x2f4 0x000 0x15 0x000
 #define MX25_PAD_LD14__LD14                     0x100 0x2f8 0x000 0x10 0x000
+#define MX25_PAD_LD14__CSPI2_SCLK               0x100 0x2f8 0x494 0x02 0x000
 #define MX25_PAD_LD14__FEC_TDATA3               0x100 0x2f8 0x000 0x15 0x000
 #define MX25_PAD_LD15__LD15                     0x104 0x2fc 0x000 0x10 0x000
+#define MX25_PAD_LD15__CSPI2_RDY                0x104 0x2fc 0x498 0x02 0x000
 #define MX25_PAD_LD15__FEC_RX_CLK               0x104 0x2fc 0x514 0x15 0x001
 #define MX25_PAD_HSYNC__HSYNC                   0x108 0x300 0x000 0x10 0x000
@@ -244,6 +277,7 @@
 #define MX25_PAD_LSCLK__GPIO_1_24               0x110 0x308 0x000 0x15 0x000
 #define MX25_PAD_OE_ACD__OE_ACD                 0x114 0x30c 0x000 0x10 0x000
+#define MX25_PAD_OE_ACD__CSPI2_SS0              0x114 0x30c 0x4a4 0x02 0x000
 #define MX25_PAD_OE_ACD__GPIO_1_25              0x114 0x30c 0x000 0x15 0x000
 #define MX25_PAD_CONTRAST__CONTRAST             0x118 0x310 0x000 0x10 0x000
@@ -257,26 +291,31 @@
 #define MX25_PAD_CSI_D2__CSI_D2                 0x120 0x318 0x000 0x10 0x000
 #define MX25_PAD_CSI_D2__UART5_RXD_MUX          0x120 0x318 0x578 0x11 0x001
+#define MX25_PAD_CSI_D2__SIM1_CLK0              0x120 0x318 0x000 0x04 0x000
 #define MX25_PAD_CSI_D2__GPIO_1_27              0x120 0x318 0x000 0x15 0x000
 #define MX25_PAD_CSI_D2__CSPI3_MOSI             0x120 0x318 0x000 0x17 0x000
 #define MX25_PAD_CSI_D3__CSI_D3                 0x124 0x31c 0x000 0x10 0x000
 #define MX25_PAD_CSI_D3__UART5_TXD_MUX          0x124 0x31c 0x000 0x11 0x000
+#define MX25_PAD_CSI_D3__SIM1_RST0              0x124 0x31c 0x000 0x04 0x000
 #define MX25_PAD_CSI_D3__GPIO_1_28              0x124 0x31c 0x000 0x15 0x000
 #define MX25_PAD_CSI_D3__CSPI3_MISO             0x124 0x31c 0x4b4 0x17 0x001
 #define MX25_PAD_CSI_D4__CSI_D4                 0x128 0x320 0x000 0x10 0x000
 #define MX25_PAD_CSI_D4__UART5_RTS              0x128 0x320 0x574 0x11 0x001
+#define MX25_PAD_CSI_D4__SIM1_VEN0              0x128 0x320 0x000 0x04 0x000
 #define MX25_PAD_CSI_D4__GPIO_1_29              0x128 0x320 0x000 0x15 0x000
 #define MX25_PAD_CSI_D4__CSPI3_SCLK             0x128 0x320 0x000 0x17 0x000
 #define MX25_PAD_CSI_D5__CSI_D5                 0x12c 0x324 0x000 0x10 0x000
-#define MX25_PAD_CSI_D5__UART5_CTS              0x12c 0x324 0x000 0x11 0x001
+#define MX25_PAD_CSI_D5__UART5_CTS              0x12c 0x324 0x000 0x11 0x000
+#define MX25_PAD_CSI_D5__SIM1_TX0               0x12c 0x324 0x000 0x04 0x000
 #define MX25_PAD_CSI_D5__GPIO_1_30              0x12c 0x324 0x000 0x15 0x000
 #define MX25_PAD_CSI_D5__CSPI3_RDY              0x12c 0x324 0x000 0x17 0x000
 #define MX25_PAD_CSI_D6__CSI_D6                 0x130 0x328 0x000 0x10 0x000
 #define MX25_PAD_CSI_D6__SDHC2_CMD              0x130 0x328 0x4e0 0x12 0x001
+#define MX25_PAD_CSI_D6__SIM1_PD0               0x130 0x328 0x000 0x04 0x000
 #define MX25_PAD_CSI_D6__GPIO_1_31              0x130 0x328 0x000 0x15 0x000
 #define MX25_PAD_CSI_D7__CSI_D7                 0x134 0x32c 0x000 0x10 0x000
@@ -284,32 +323,32 @@
 #define MX25_PAD_CSI_D7__GPIO_1_6               0x134 0x32c 0x000 0x15 0x000
 #define MX25_PAD_CSI_D8__CSI_D8                 0x138 0x330 0x000 0x10 0x000
-#define MX25_PAD_CSI_D8__AUD6_RXC               0x138 0x330 0x000 0x12 0x001
+#define MX25_PAD_CSI_D8__AUD6_RXC               0x138 0x330 0x000 0x12 0x000
 #define MX25_PAD_CSI_D8__GPIO_1_7               0x138 0x330 0x000 0x15 0x000
 #define MX25_PAD_CSI_D8__CSPI3_SS2              0x138 0x330 0x4c4 0x17 0x000
 #define MX25_PAD_CSI_D9__CSI_D9                 0x13c 0x334 0x000 0x10 0x000
-#define MX25_PAD_CSI_D9__AUD6_RXFS              0x13c 0x334 0x000 0x12 0x001
+#define MX25_PAD_CSI_D9__AUD6_RXFS              0x13c 0x334 0x000 0x12 0x000
 #define MX25_PAD_CSI_D9__GPIO_4_21              0x13c 0x334 0x000 0x15 0x000
 #define MX25_PAD_CSI_D9__CSPI3_SS3              0x13c 0x334 0x4c8 0x17 0x000
 #define MX25_PAD_CSI_MCLK__CSI_MCLK             0x140 0x338 0x000 0x10 0x000
-#define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x11 0x001
+#define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x11 0x000
 #define MX25_PAD_CSI_MCLK__SDHC2_DAT0           0x140 0x338 0x4e4 0x12 0x001
 #define MX25_PAD_CSI_MCLK__GPIO_1_8             0x140 0x338 0x000 0x15 0x000
 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC           0x144 0x33c 0x000 0x10 0x000
-#define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x11 0x001
+#define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x11 0x000
 #define MX25_PAD_CSI_VSYNC__SDHC2_DAT1          0x144 0x33c 0x4e8 0x12 0x001
 #define MX25_PAD_CSI_VSYNC__GPIO_1_9            0x144 0x33c 0x000 0x15 0x000
 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC           0x148 0x340 0x000 0x10 0x000
-#define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x11 0x001
+#define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x11 0x000
 #define MX25_PAD_CSI_HSYNC__SDHC2_DAT2          0x148 0x340 0x4ec 0x12 0x001
 #define MX25_PAD_CSI_HSYNC__GPIO_1_10           0x148 0x340 0x000 0x15 0x000
 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK         0x14c 0x344 0x000 0x10 0x000
-#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x11 0x001
+#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x11 0x000
 #define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3         0x14c 0x344 0x4f0 0x12 0x001
 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11          0x14c 0x344 0x000 0x15 0x000
@@ -369,8 +408,8 @@
 #define MX25_PAD_UART2_RTS__CC1                 0x188 0x380 0x000 0x13 0x000
 #define MX25_PAD_UART2_RTS__GPIO_4_28           0x188 0x380 0x000 0x15 0x000
-#define MX25_PAD_UART2_CTS__FEC_RX_ER           0x18c 0x384 0x518 0x12 0x002
 #define MX25_PAD_UART2_CTS__UART2_CTS           0x18c 0x384 0x000 0x10 0x000
+#define MX25_PAD_UART2_CTS__FEC_RX_ERR          0x18c 0x384 0x518 0x12 0x002
 #define MX25_PAD_UART2_CTS__GPIO_4_29           0x18c 0x384 0x000 0x15 0x000
 #define MX25_PAD_SD1_CMD__SD1_CMD               0x190 0x388 0x000 0x10 0x000
@@ -392,11 +431,11 @@
 #define MX25_PAD_SD1_DATA1__GPIO_2_26           0x19c 0x394 0x000 0x15 0x000
 #define MX25_PAD_SD1_DATA2__SD1_DATA2           0x1a0 0x398 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x15 0x002
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x12 0x002
 #define MX25_PAD_SD1_DATA2__GPIO_2_27           0x1a0 0x398 0x000 0x15 0x000
 #define MX25_PAD_SD1_DATA3__SD1_DATA3           0x1a4 0x39c 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x10 0x002
+#define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x12 0x002
 #define MX25_PAD_SD1_DATA3__GPIO_2_28           0x1a4 0x39c 0x000 0x15 0x000
 #define MX25_PAD_KPP_ROW0__KPP_ROW0             0x1a8 0x3a0 0x000 0x10 0x000
@@ -410,7 +449,7 @@
 #define MX25_PAD_KPP_ROW2__GPIO_2_31            0x1b0 0x3a8 0x000 0x15 0x000
 #define MX25_PAD_KPP_ROW3__KPP_ROW3             0x1b4 0x3ac 0x000 0x10 0x000
-#define MX25_PAD_KPP_ROW3__CSI_LD1              0x1b4 0x3ac 0x48c 0x13 0x002
+#define MX25_PAD_KPP_ROW3__CSI_D1               0x1b4 0x3ac 0x48c 0x13 0x002
 #define MX25_PAD_KPP_ROW3__GPIO_3_0             0x1b4 0x3ac 0x000 0x15 0x000
 #define MX25_PAD_KPP_COL0__KPP_COL0             0x1b8 0x3b0 0x000 0x10 0x000
@@ -455,9 +494,18 @@
 #define MX25_PAD_FEC_RDATA0__GPIO_3_10          0x1dc 0x3d4 0x000 0x15 0x000
 #define MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x1e0 0x3d8 0x000 0x10 0x000
+/*
+ * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
+ * 01/2011) this is CAN1_TX but that's wrong.
+ */
+#define MX25_PAD_FEC_RDATA1__CAN2_TX            0x1e0 0x3d8 0x000 0x14 0x000
 #define MX25_PAD_FEC_RDATA1__GPIO_3_11          0x1e0 0x3d8 0x000 0x15 0x000
 #define MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x1e4 0x3dc 0x000 0x10 0x000
+/*
+ * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
+ * 01/2011) this is CAN1_RX but that's wrong.
+ */
 #define MX25_PAD_FEC_RX_DV__CAN2_RX             0x1e4 0x3dc 0x484 0x14 0x000
 #define MX25_PAD_FEC_RX_DV__GPIO_3_12           0x1e4 0x3dc 0x000 0x15 0x000
@@ -471,30 +519,34 @@
 #define MX25_PAD_DE_B__DE_B                     0x1f0 0x3ec 0x000 0x10 0x000
 #define MX25_PAD_DE_B__GPIO_2_20                0x1f0 0x3ec 0x000 0x15 0x000
-#define MX25_PAD_TDO__TDO                       0x000 0x3e8 0x000 0x00 0x000
 #define MX25_PAD_GPIO_A__GPIO_A                 0x1f4 0x3f0 0x000 0x10 0x000
 #define MX25_PAD_GPIO_A__CAN1_TX                0x1f4 0x3f0 0x000 0x16 0x000
 #define MX25_PAD_GPIO_A__USBOTG_PWR             0x1f4 0x3f0 0x000 0x12 0x000
 #define MX25_PAD_GPIO_B__GPIO_B                 0x1f8 0x3f4 0x000 0x10 0x000
-#define MX25_PAD_GPIO_B__CAN1_RX                0x1f8 0x3f4 0x480 0x16 0x001
 #define MX25_PAD_GPIO_B__USBOTG_OC              0x1f8 0x3f4 0x57c 0x12 0x001
+#define MX25_PAD_GPIO_B__CAN1_RX                0x1f8 0x3f4 0x480 0x16 0x001
 #define MX25_PAD_GPIO_C__GPIO_C                 0x1fc 0x3f8 0x000 0x10 0x000
+#define MX25_PAD_GPIO_C__PWM4_PWMO              0x1fc 0x3f8 0x000 0x11 0x000
+#define MX25_PAD_GPIO_C__I2C2_SCL               0x1fc 0x3f8 0x51c 0x12 0x001
+#define MX25_PAD_GPIO_C__KPP_COL4               0x1fc 0x3f8 0x52c 0x13 0x001
 #define MX25_PAD_GPIO_C__CAN2_TX                0x1fc 0x3f8 0x000 0x16 0x000
 #define MX25_PAD_GPIO_D__GPIO_D                 0x200 0x3fc 0x000 0x10 0x000
+#define MX25_PAD_GPIO_D__I2C2_SDA               0x200 0x3fc 0x520 0x12 0x001
 #define MX25_PAD_GPIO_D__CAN2_RX                0x200 0x3fc 0x484 0x16 0x001
 #define MX25_PAD_GPIO_E__GPIO_E                 0x204 0x400 0x000 0x10 0x000
 #define MX25_PAD_GPIO_E__I2C3_CLK               0x204 0x400 0x524 0x11 0x002
 #define MX25_PAD_GPIO_E__LD16                   0x204 0x400 0x000 0x12 0x000
 #define MX25_PAD_GPIO_E__AUD7_TXD               0x204 0x400 0x000 0x14 0x000
+#define MX25_PAD_GPIO_E__UART4_RXD              0x204 0x400 0x570 0x16 0x002
 #define MX25_PAD_GPIO_F__GPIO_F                 0x208 0x404 0x000 0x10 0x000
 #define MX25_PAD_GPIO_F__LD17                   0x208 0x404 0x000 0x12 0x000
 #define MX25_PAD_GPIO_F__AUD7_TXC               0x208 0x404 0x000 0x14 0x000
+#define MX25_PAD_GPIO_F__UART4_TXD              0x208 0x404 0x000 0x16 0x000
 #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK         0x20c 0x000 0x000 0x10 0x000
 #define MX25_PAD_EXT_ARMCLK__GPIO_3_15          0x20c 0x000 0x000 0x15 0x000
@@ -505,6 +557,7 @@
 #define MX25_PAD_VSTBY_REQ__VSTBY_REQ           0x214 0x408 0x000 0x10 0x000
 #define MX25_PAD_VSTBY_REQ__AUD7_TXFS           0x214 0x408 0x000 0x14 0x000
 #define MX25_PAD_VSTBY_REQ__GPIO_3_17           0x214 0x408 0x000 0x15 0x000
 #define MX25_PAD_VSTBY_ACK__VSTBY_ACK           0x218 0x40c 0x000 0x10 0x000
 #define MX25_PAD_VSTBY_ACK__GPIO_3_18           0x218 0x40c 0x000 0x15 0x000
@@ -517,6 +570,7 @@
 #define MX25_PAD_BOOT_MODE0__BOOT_MODE0         0x224 0x000 0x000 0x00 0x000
 #define MX25_PAD_BOOT_MODE0__GPIO_4_30          0x224 0x000 0x000 0x05 0x000
 #define MX25_PAD_BOOT_MODE1__BOOT_MODE1         0x228 0x000 0x000 0x00 0x000
 #define MX25_PAD_BOOT_MODE1__GPIO_4_31          0x228 0x000 0x000 0x05 0x000
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 4b063b68db44..6951b66d1ab7 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -488,6 +488,7 @@
                                interrupts = <54>;
                                clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
                                fsl,usbmisc = <&usbmisc 1>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -497,6 +498,7 @@
                                interrupts = <55>;
                                clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
                                fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 7198fe3798c6..070e59cbdd8b 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -78,7 +78,7 @@
                        phy-mode = "rmii";
                        pinctrl-names = "default";
                        pinctrl-0 = <&mac0_pins_a>;
-                        phy-reset-gpios = <&gpio4 13 0>;
+                        phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
                        status = "okay";
                };
        };
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 1f38a052ad4b..7ac4f1af16ac 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -110,6 +110,13 @@
                                        };
                                };
                        };
+                        can0: can@80032000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can0_pins_a>;
+                                xceiver-supply = <&reg_can0_vcc>;
+                                status = "okay";
+                        };
                };
                apbx@80040000 {
@@ -130,6 +137,13 @@
                                status = "okay";
                        };
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
                        usbphy0: usbphy@8007c000 {
                                status = "okay";
                        };
@@ -143,7 +157,8 @@
        ahb@80080000 {
                usb0: usb@80080000 {
                        pinctrl-names = "default";
-                        pinctrl-0 = <&usb0_otg_apf28dev>;
+                        pinctrl-0 = <&usb0_otg_apf28dev
+                                        &usb0_id_pins_b>;
                        vbus-supply = <&reg_usb0_vbus>;
                        status = "okay";
                };
@@ -156,7 +171,7 @@
                        phy-mode = "rmii";
                        pinctrl-names = "default";
                        pinctrl-0 = <&mac1_pins_a>;
-                        phy-reset-gpios = <&gpio0 23 0>;
+                        phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
                        status = "okay";
                };
        };
@@ -175,6 +190,14 @@
                        gpio = <&gpio1 23 1>;
                        enable-active-high;
                };
+                reg_can0_vcc: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "can0_vcc";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
        };
        leds {
@@ -200,8 +223,9 @@
                user-button {
                        label = "User button";
-                        gpios = <&gpio0 17 0>;
+                        gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
                        linux,code = <0x100>;
+                        gpio-key,wakeup;
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 47f68ac868d4..25e25f82fbae 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -829,6 +829,19 @@
                                        fsl,pull-up = <MXS_PULL_DISABLE>;
                                };
+                                spi3_pins_b: spi3@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                MX28_PAD_SSP3_SCK__SSP3_SCK
+                                                MX28_PAD_SSP3_MOSI__SSP3_CMD
+                                                MX28_PAD_SSP3_MISO__SSP3_D0
+                                                MX28_PAD_SSP3_SS0__SSP3_D3
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_8mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_ENABLE>;
+                                };
                                usb0_pins_a: usb0@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
@@ -1197,6 +1210,7 @@
                        interrupts = <92>;
                        clocks = <&clks 61>;
                        fsl,usbphy = <&usbphy1>;
+                        dr_mode = "host";
                        status = "disabled";
                };
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 6932928f3b45..b6478e97d6a7 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -318,6 +318,7 @@
                                clocks = <&clks 73>;
                                fsl,usbmisc = <&usbmisc 1>;
                                fsl,usbphy = <&usbphy1>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 620b0f030591..e2457138311f 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -197,6 +197,7 @@
                                reg = <0x53f80200 0x0200>;
                                interrupts = <14>;
                                clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -205,6 +206,7 @@
                                reg = <0x53f80400 0x0200>;
                                interrupts = <16>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -213,6 +215,7 @@
                                reg = <0x53f80600 0x0200>;
                                interrupts = <17>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index c0116cffc513..f46fe9bf0bcb 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -265,6 +265,7 @@
                                interrupts = <14>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 1>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -274,6 +275,7 @@
                                interrupts = <16>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -283,6 +285,7 @@
                                interrupts = <17>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 3>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index ff4fa7ecacd8..c3e3ca9362fb 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -309,6 +309,7 @@
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 1>;
                                fsl,usbphy = <&usbphy1>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -318,6 +319,7 @@
                                interrupts = <16>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -327,6 +329,7 @@
                                interrupts = <17>;
                                clocks = <&clks IMX5_CLK_USBOH3_GATE>;
                                fsl,usbmisc = <&usbmisc 3>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index 9cd06e5e59f0..d4c4a22db488 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -83,3 +83,7 @@
 &ipu1_di0_disp0 {
        remote-endpoint = <&display0_in>;
 };
+&pwm1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
index b413e24288dc..15203f0e9725 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -72,3 +72,7 @@
 &ipu1_di0_disp0 {
        remote-endpoint = <&display0_in>;
 };
+&pwm3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-cubox-i.dts b/arch/arm/boot/dts/imx6dl-cubox-i.dts
index 58aa8f2b0f26..e0b7fe8e18f8 100644
--- a/arch/arm/boot/dts/imx6dl-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6dl-cubox-i.dts
@@ -1,5 +1,43 @@
 /*
 * Copyright (C) 2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index 44a0e6736bb1..7369d2d7da3e 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -1,6 +1,44 @@
 /*
 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
 * Based on dt work by Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts
index 9efd8b0c8011..670bd8c4c847 100644
--- a/arch/arm/boot/dts/imx6q-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6q-cubox-i.dts
@@ -1,5 +1,43 @@
 /*
 * Copyright (C) 2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts
index c2bf8476ce45..0f6044553a24 100644
--- a/arch/arm/boot/dts/imx6q-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6q-hummingboard.dts
@@ -1,6 +1,44 @@
 /*
 * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
 * Based on dt work by Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 93ec79bb6b35..399103b8e2c9 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -294,19 +294,21 @@
 };
 &mipi_dsi {
-        port@2 {
+        ports {
-                reg = <2>;
+                port@2 {
+                        reg = <2>;
-                mipi_mux_2: endpoint {
+                        mipi_mux_2: endpoint {
-                        remote-endpoint = <&ipu2_di0_mipi>;
+                                remote-endpoint = <&ipu2_di0_mipi>;
+                        };
                };
-        };
-        port@3 {
+                port@3 {
-                reg = <3>;
+                        reg = <3>;
-                mipi_mux_3: endpoint {
+                        mipi_mux_3: endpoint {
-                        remote-endpoint = <&ipu2_di1_mipi>;
+                                remote-endpoint = <&ipu2_di1_mipi>;
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index 6a524ca011e7..d033bb182060 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -1,8 +1,48 @@
 /*
 * Copyright (C) 2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 #include "imx6qdl-microsom.dtsi"
 #include "imx6qdl-microsom-ar8035.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 / {
        ir_recv: ir-receiver {
@@ -66,6 +106,18 @@
                spdif-controller = <&spdif>;
                spdif-out;
        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pinctrl_gpio_key>;
+                pinctrl-names = "default";
+                button_0 {
+                        label = "Button 0";
+                        gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
+                        linux,code = <BTN_0>;
+                };
+        };
 };
 &hdmi {
@@ -170,9 +222,19 @@
                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
                        >;
                };
+                pinctrl_gpio_key: gpio-key {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_DA8__GPIO3_IO08  0x17059
+                        >;
+                };
        };
 };
+&pwm1 {
+        status = "okay";
+};
 &spdif {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_cubox_i_spdif>;
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
index 62841e85a91e..151a3db2aea9 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -1,5 +1,43 @@
 /*
 * Copyright (C) 2013,2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 #include "imx6qdl-microsom.dtsi"
 #include "imx6qdl-microsom-ar8035.dtsi"
@@ -50,6 +88,19 @@
                };
        };
+        sound-sgtl5000 {
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                compatible = "fsl,imx-audio-sgtl5000";
+                model = "On-board Codec";
+                mux-ext-port = <5>;
+                mux-int-port = <1>;
+                ssi-controller = <&ssi1>;
+        };
        sound-spdif {
                compatible = "fsl,imx-audio-spdif";
                model = "On-board SPDIF";
@@ -59,6 +110,10 @@
        };
 };
+&audmux {
+        status = "okay";
+};
 &can1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
@@ -75,16 +130,24 @@
 &i2c1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
-        /*
-         * Not fitted on Carrier-1 board... yet
        status = "okay";
+        /* Pro baseboard model */
        rtc: pcf8523@68 {
                compatible = "nxp,pcf8523";
                reg = <0x68>;
        };
-         */
+        /* Pro baseboard model */
+        sgtl5000: sgtl5000@0a {
+                clocks = <&clks IMX6QDL_CLK_CKO>;
+                compatible = "fsl,sgtl5000";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>;
+                reg = <0x0a>;
+                VDDA-supply = <&reg_3p3v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
 };
 &i2c2 {
@@ -129,6 +192,20 @@
                        >;
                };
+                pinctrl_hummingboard_pwm1: pwm1grp {
+                        fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>;
+                };
+                pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
+                                MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
+                                MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
+                                MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
+                                MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
+                        >;
+                };
                pinctrl_hummingboard_spdif: hummingboard-spdif {
                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
                };
@@ -168,12 +245,28 @@
        };
 };
+&pwm1 {
+         pinctrl-names = "default";
+         pinctrl-0 = <&pinctrl_hummingboard_pwm1>;
+         status = "okay";
+};
+&pwm2 {
+         pinctrl-names = "default";
+         status = "okay";
+};
 &spdif {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hummingboard_spdif>;
        status = "okay";
 };
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
 &usbh1 {
        disable-over-current;
        vbus-supply = <&reg_usbh1_vbus>;
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index db9f45b2c573..4a1820309cdb 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -3,6 +3,44 @@
 *
 * This describes the hookup for an AR8035 to the iMX6 on the SolidRun
 * MicroSOM.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 &fec {
        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
index 79eac6849d4c..349f82be816e 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -1,5 +1,43 @@
 /*
 * Copyright (C) 2013,2014 Russell King
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */
 &iomuxc {
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 009abd69385d..46b2fed7c319 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -182,6 +182,34 @@
        };
 };
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+        max7310_a: gpio@30 {
+                compatible = "maxim,max7310";
+                reg = <0x30>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        max7310_b: gpio@32 {
+                compatible = "maxim,max7310";
+                reg = <0x32>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        max7310_c: gpio@34 {
+                compatible = "maxim,max7310";
+                reg = <0x34>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
 &iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hog>;
@@ -265,6 +293,13 @@
                        >;
                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
+                                MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+                        >;
+                };
                pinctrl_pwm3: pwm1grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index d6c69ec44314..f74a8ded515f 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -53,6 +53,7 @@
                interrupt-controller;
                reg = <0x00a01000 0x1000>,
                      <0x00a00100 0x100>;
+                interrupt-parent = <&intc>;
        };
        clocks {
@@ -82,7 +83,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
+                interrupt-parent = <&gpc>;
                ranges;
                dma_apbh: dma-apbh@00110000 {
@@ -122,6 +123,7 @@
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0x00a00600 0x20>;
                        interrupts = <1 13 0xf01>;
+                        interrupt-parent = <&intc>;
                        clocks = <&clks IMX6QDL_CLK_TWD>;
                };
@@ -357,6 +359,7 @@
                                clocks = <&clks IMX6QDL_CLK_IPG>,
                                         <&clks IMX6QDL_CLK_PWM1>;
                                clock-names = "ipg", "per";
+                                status = "disabled";
                        };
                        pwm2: pwm@02084000 {
@@ -367,6 +370,7 @@
                                clocks = <&clks IMX6QDL_CLK_IPG>,
                                         <&clks IMX6QDL_CLK_PWM2>;
                                clock-names = "ipg", "per";
+                                status = "disabled";
                        };
                        pwm3: pwm@02088000 {
@@ -377,6 +381,7 @@
                                clocks = <&clks IMX6QDL_CLK_IPG>,
                                         <&clks IMX6QDL_CLK_PWM3>;
                                clock-names = "ipg", "per";
+                                status = "disabled";
                        };
                        pwm4: pwm@0208c000 {
@@ -387,6 +392,7 @@
                                clocks = <&clks IMX6QDL_CLK_IPG>,
                                         <&clks IMX6QDL_CLK_PWM4>;
                                clock-names = "ipg", "per";
+                                status = "disabled";
                        };
                        can1: flexcan@02090000 {
@@ -598,7 +604,7 @@
                                        regulator-name = "vddpu";
                                        regulator-min-microvolt = <725000>;
                                        regulator-max-microvolt = <1450000>;
-                                        regulator-always-on;
+                                        regulator-enable-ramp-delay = <150>;
                                        anatop-reg-offset = <0x140>;
                                        anatop-vol-bit-shift = <9>;
                                        anatop-vol-bit-width = <5>;
@@ -658,7 +664,7 @@
                                #size-cells = <1>;
                                ranges = <0 0x020cc000 0x4000>;
-                                snvs-rtc-lp@34 {
+                                snvs_rtc: snvs-rtc-lp@34 {
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        reg = <0x34 0x58>;
                                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -693,8 +699,19 @@
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
+                                interrupt-controller;
+                                #interrupt-cells = <3>;
                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 90 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
+                                pu-supply = <&reg_pu>;
+                                clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+                                         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+                                         <&clks IMX6QDL_CLK_GPU2D_CORE>,
+                                         <&clks IMX6QDL_CLK_GPU2D_AXI>,
+                                         <&clks IMX6QDL_CLK_OPENVG_AXI>,
+                                         <&clks IMX6QDL_CLK_VPU_AXI>;
+                                #power-domain-cells = <1>;
                        };
                        gpr: iomuxc-gpr@020e0000 {
@@ -845,6 +862,7 @@
                                clocks = <&clks IMX6QDL_CLK_USBOH3>;
                                fsl,usbphy = <&usbphy2>;
                                fsl,usbmisc = <&usbmisc 1>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -854,6 +872,7 @@
                                interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6QDL_CLK_USBOH3>;
                                fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -863,6 +882,7 @@
                                interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6QDL_CLK_USBOH3>;
                                fsl,usbmisc = <&usbmisc 3>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
@@ -1022,19 +1042,24 @@
                                reg = <0x021e0000 0x4000>;
                                status = "disabled";
-                                port@0 {
+                                ports {
-                                        reg = <0>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        port@0 {
+                                                reg = <0>;
-                                        mipi_mux_0: endpoint {
+                                                mipi_mux_0: endpoint {
-                                                remote-endpoint = <&ipu1_di0_mipi>;
+                                                        remote-endpoint = <&ipu1_di0_mipi>;
+                                                };
                                        };
-                                };
-                                port@1 {
+                                        port@1 {
-                                        reg = <1>;
+                                                reg = <1>;
-                                        mipi_mux_1: endpoint {
+                                                mipi_mux_1: endpoint {
-                                                remote-endpoint = <&ipu1_di1_mipi>;
+                                                        remote-endpoint = <&ipu1_di1_mipi>;
+                                                };
                                        };
                                };
                        };
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
new file mode 100644
index 000000000000..64f7decf1fdc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -0,0 +1,262 @@
+/*
+ * Copyright 2014, 2015 O.S. Systems Software LTDA.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6sl.dtsi"
+/ {
+        model = "WaRP Board";
+        compatible = "warp,imx6sl-warp", "fsl,imx6sl";
+        memory {
+                reg = <0x80000000 0x20000000>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_usb_otg1_vbus: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "usb_otg1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio4 0 0>;
+                        enable-active-high;
+                };
+                reg_usb_otg2_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "usb_otg2_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio4 2 0>;
+                        enable-active-high;
+                };
+                reg_1p8v: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "1P8V";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+        };
+        usdhc3_pwrseq: usdhc3_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>,       /* WL_REG_ON */
+                              <&gpio3 25 GPIO_ACTIVE_LOW>,      /* BT_REG_ON */
+                              <&gpio4 4 GPIO_ACTIVE_LOW>,       /* BT_WAKE */
+                              <&gpio4 6 GPIO_ACTIVE_LOW>;       /* BT_RST_N */
+        };
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "okay";
+};
+&usbotg1 {
+        vbus-supply = <&reg_usb_otg1_vbus>;
+        dr_mode = "host";
+        disable-over-current;
+        status = "okay";
+};
+&usbotg2 {
+        vbus-supply = <&reg_usb_otg2_vbus>;
+        disable-over-current;
+        status = "okay";
+};
+&usdhc2 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+        bus-width = <4>;
+        non-removable;
+        keep-power-in-suspend;
+        enable-sdio-wakeup;
+        mmc-pwrseq = <&usdhc3_pwrseq>;
+        status = "okay";
+};
+&iomuxc {
+        imx6sl-warp {
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6SL_PAD_UART1_RXD__UART1_RX_DATA      0x41b0b1
+                                MX6SL_PAD_UART1_TXD__UART1_TX_DATA      0x41b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6SL_PAD_EPDC_D12__UART2_RX_DATA       0x41b0b1
+                                MX6SL_PAD_EPDC_D13__UART2_TX_DATA       0x41b0b1
+                                MX6SL_PAD_EPDC_D14__UART2_RTS_B         0x4130B1
+                                MX6SL_PAD_EPDC_D15__UART2_CTS_B         0x4130B1
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX6SL_PAD_AUD_RXC__UART3_RX_DATA        0x41b0b1
+                                MX6SL_PAD_AUD_RXC__UART3_TX_DATA        0x41b0b1
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x417059
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x410059
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x417059
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x417059
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x417059
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x417059
+                                MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x417059
+                                MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x417059
+                                MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x417059
+                                MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x417059
+                        >;
+                };
+                pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x4170b9
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x4100b9
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x4170b9
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x4170b9
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x4170b9
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x4170b9
+                                MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x4170b9
+                                MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x4170b9
+                                MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x4170b9
+                                MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x4170b9
+                        >;
+                };
+                pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD2_CMD__SD2_CMD              0x4170f9
+                                MX6SL_PAD_SD2_CLK__SD2_CLK              0x4100f9
+                                MX6SL_PAD_SD2_DAT0__SD2_DATA0           0x4170f9
+                                MX6SL_PAD_SD2_DAT1__SD2_DATA1           0x4170f9
+                                MX6SL_PAD_SD2_DAT2__SD2_DATA2           0x4170f9
+                                MX6SL_PAD_SD2_DAT3__SD2_DATA3           0x4170f9
+                                MX6SL_PAD_SD2_DAT4__SD2_DATA4           0x4170f9
+                                MX6SL_PAD_SD2_DAT5__SD2_DATA5           0x4170f9
+                                MX6SL_PAD_SD2_DAT6__SD2_DATA6           0x4170f9
+                                MX6SL_PAD_SD2_DAT7__SD2_DATA7           0x4170f9
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x417059
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x410059
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x417059
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x417059
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x417059
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x417059
+                        >;
+                };
+                pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x4170b9
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x4100b9
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x4170b9
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x4170b9
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x4170b9
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x4170b9
+                        >;
+                };
+                pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                        fsl,pins = <
+                                MX6SL_PAD_SD3_CMD__SD3_CMD              0x4170f9
+                                MX6SL_PAD_SD3_CLK__SD3_CLK              0x4100f9
+                                MX6SL_PAD_SD3_DAT0__SD3_DATA0           0x4170f9
+                                MX6SL_PAD_SD3_DAT1__SD3_DATA1           0x4170f9
+                                MX6SL_PAD_SD3_DAT2__SD3_DATA2           0x4170f9
+                                MX6SL_PAD_SD3_DAT3__SD3_DATA3           0x4170f9
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 36ab8e054cee..a78e715e3982 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -72,6 +72,7 @@
                interrupt-controller;
                reg = <0x00a01000 0x1000>,
                      <0x00a00100 0x100>;
+                interrupt-parent = <&intc>;
        };
        clocks {
@@ -95,7 +96,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
+                interrupt-parent = <&gpc>;
                ranges;
                ocram: sram@00900000 {
@@ -568,7 +569,7 @@
                                #size-cells = <1>;
                                ranges = <0 0x020cc000 0x4000>;
-                                snvs-rtc-lp@34 {
+                                snvs_rtc: snvs-rtc-lp@34 {
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        reg = <0x34 0x58>;
                                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
@@ -603,7 +604,14 @@
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
+                                interrupt-controller;
+                                #interrupt-cells = <3>;
                                interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
+                                pu-supply = <&reg_pu>;
+                                clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
+                                         <&clks IMX6SL_CLK_GPU2D_PODF>;
+                                #power-domain-cells = <1>;
                        };
                        gpr: iomuxc-gpr@020e0000 {
@@ -699,6 +707,7 @@
                                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks IMX6SL_CLK_USBOH3>;
                                fsl,usbmisc = <&usbmisc 2>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
new file mode 100644
index 000000000000..c76b87cba275
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "imx6sx-sdb.dtsi"
+/ {
+        model = "Freescale i.MX6 SoloX SDB RevA Board";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        pmic: pfuze100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                                regulator-always-on;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+&qspi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_qspi2>;
+        status = "okay";
+        flash0: s25fl128s@0 {
+                reg = <0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl128s";
+                spi-max-frequency = <66000000>;
+        };
+        flash1: s25fl128s@1 {
+                reg = <1>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl128s";
+                spi-max-frequency = <66000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 32f07d6b4042..0bfc4e7865b2 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -1,197 +1,40 @@
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-/dts-v1/;
+#include "imx6sx-sdb.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include "imx6sx.dtsi"
 / {
-        model = "Freescale i.MX6 SoloX SDB Board";
+        model = "Freescale i.MX6 SoloX SDB RevB Board";
-        compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
-        chosen {
-                stdout-path = &uart1;
-        };
-        memory {
-                reg = <0x80000000 0x40000000>;
-        };
-        backlight {
-                compatible = "pwm-backlight";
-                pwms = <&pwm3 0 5000000>;
-                brightness-levels = <0 4 8 16 32 64 128 255>;
-                default-brightness-level = <6>;
-        };
-        gpio-keys {
-                compatible = "gpio-keys";
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_gpio_keys>;
-                volume-up {
-                        label = "Volume Up";
-                        gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_VOLUMEUP>;
-                };
-                volume-down {
-                        label = "Volume Down";
-                        gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_VOLUMEDOWN>;
-                };
-        };
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                vcc_sd3: regulator@0 {
-                        compatible = "regulator-fixed";
-                        reg = <0>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_vcc_sd3>;
-                        regulator-name = "VCC_SD3";
-                        regulator-min-microvolt = <3000000>;
-                        regulator-max-microvolt = <3000000>;
-                        gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-                reg_usb_otg1_vbus: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_usb_otg1>;
-                        regulator-name = "usb_otg1_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-                reg_usb_otg2_vbus: regulator@2 {
-                        compatible = "regulator-fixed";
-                        reg = <2>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_usb_otg2>;
-                        regulator-name = "usb_otg2_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-                reg_psu_5v: regulator@3 {
-                        compatible = "regulator-fixed";
-                        reg = <3>;
-                        regulator-name = "PSU-5V0";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                };
-                reg_lcd_3v3: regulator@4 {
-                        compatible = "regulator-fixed";
-                        reg = <4>;
-                        regulator-name = "lcd-3v3";
-                        gpio = <&gpio3 27 0>;
-                        enable-active-high;
-                };
-                reg_peri_3v3: regulator@5 {
-                        compatible = "regulator-fixed";
-                        reg = <5>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_peri_3v3>;
-                        regulator-name = "peri_3v3";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        regulator-always-on;
-                };
-                reg_enet_3v3: regulator@6 {
-                        compatible = "regulator-fixed";
-                        reg = <6>;
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_enet_3v3>;
-                        regulator-name = "enet_3v3";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
-                };
-        };
-        sound {
-                compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
-                model = "wm8962-audio";
-                ssi-controller = <&ssi2>;
-                audio-codec = <&codec>;
-                audio-routing =
-                        "Headphone Jack", "HPOUTL",
-                        "Headphone Jack", "HPOUTR",
-                        "Ext Spk", "SPKOUTL",
-                        "Ext Spk", "SPKOUTR",
-                        "AMIC", "MICBIAS",
-                        "IN3R", "AMIC";
-                mux-int-port = <2>;
-                mux-ext-port = <6>;
-        };
-};
-&audmux {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux>;
-        status = "okay";
 };
-&fec1 {
+&cpu0 {
-        pinctrl-names = "default";
+        operating-points = <
-        pinctrl-0 = <&pinctrl_enet1>;
+                /* kHz    uV */
-        phy-supply = <&reg_enet_3v3>;
+                996000  1250000
-        phy-mode = "rgmii";
+                792000  1175000
-        phy-handle = <&ethphy1>;
+                396000  1175000
-        status = "okay";
+                >;
+        fsl,soc-operating-points = <
-        mdio {
+                /* ARM kHz      SOC uV */
-                #address-cells = <1>;
+                996000  1250000
-                #size-cells = <0>;
+                792000  1175000
+                396000  1175000
-                ethphy1: ethernet-phy@1 {
+        >;
-                        reg = <1>;
-                };
-                ethphy2: ethernet-phy@2 {
-                        reg = <2>;
-                };
-        };
 };
-&fec2 {
+&i2c1 {
+        clock-frequency = <100000>;
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet2>;
+        pinctrl-0 = <&pinctrl_i2c1>;
-        phy-mode = "rgmii";
-        phy-handle = <&ethphy2>;
        status = "okay";
-};
-&i2c1 {
-        clock-frequency = <100000>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c1>;
-        status = "okay";
        pmic: pfuze100@08 {
-                compatible = "fsl,pfuze100";
+                compatible = "fsl,pfuze200";
                reg = <0x08>;
                regulators {
@@ -203,14 +46,6 @@
                                regulator-ramp-delay = <6250>;
                        };
-                        sw1c_reg: sw1c {
-                                regulator-min-microvolt = <300000>;
-                                regulator-max-microvolt = <1875000>;
-                                regulator-boot-on;
-                                regulator-always-on;
-                                regulator-ramp-delay = <6250>;
-                        };
                        sw2_reg: sw2 {
                                regulator-min-microvolt = <800000>;
                                regulator-max-microvolt = <3300000>;
@@ -232,11 +67,6 @@
                                regulator-always-on;
                        };
-                        sw4_reg: sw4 {
-                                regulator-min-microvolt = <800000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
                        swbst_reg: swbst {
                                regulator-min-microvolt = <5000000>;
                                regulator-max-microvolt = <5150000>;
@@ -292,401 +122,24 @@
        };
 };
-&i2c4 {
-        clock-frequency = <100000>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c4>;
-        status = "okay";
-        codec: wm8962@1a {
-                compatible = "wlf,wm8962";
-                reg = <0x1a>;
-                clocks = <&clks IMX6SX_CLK_AUDIO>;
-                DCVDD-supply = <&vgen4_reg>;
-                DBVDD-supply = <&vgen4_reg>;
-                AVDD-supply = <&vgen4_reg>;
-                CPVDD-supply = <&vgen4_reg>;
-                MICVDD-supply = <&vgen3_reg>;
-                PLLVDD-supply = <&vgen4_reg>;
-                SPKVDD1-supply = <&reg_psu_5v>;
-                SPKVDD2-supply = <&reg_psu_5v>;
-        };
-};
-&lcdif1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_lcd>;
-        lcd-supply = <&reg_lcd_3v3>;
-        display = <&display0>;
-        status = "okay";
-        display0: display0 {
-                bits-per-pixel = <16>;
-                bus-width = <24>;
-                display-timings {
-                        native-mode = <&timing0>;
-                        timing0: timing0 {
-                                clock-frequency = <33500000>;
-                                hactive = <800>;
-                                vactive = <480>;
-                                hback-porch = <89>;
-                                hfront-porch = <164>;
-                                vback-porch = <23>;
-                                vfront-porch = <10>;
-                                hsync-len = <10>;
-                                vsync-len = <10>;
-                                hsync-active = <0>;
-                                vsync-active = <0>;
-                                de-active = <1>;
-                                pixelclk-active = <0>;
-                        };
-                };
-        };
-};
-&pwm3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm3>;
-        status = "okay";
-};
-&snvs_poweroff {
-        status = "okay";
-};
 &qspi2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_qspi2>;
        status = "okay";
-        flash0: s25fl128s@0 {
+        flash0: n25q256a@0 {
-                reg = <0>;
                #address-cells = <1>;
                #size-cells = <1>;
-                compatible = "spansion,s25fl128s";
+                compatible = "micron,n25q256a";
-                spi-max-frequency = <66000000>;
+                spi-max-frequency = <29000000>;
+                reg = <0>;
        };
-        flash1: s25fl128s@1 {
+        flash1: n25q256a@1 {
-                reg = <1>;
                #address-cells = <1>;
                #size-cells = <1>;
-                compatible = "spansion,s25fl128s";
+                compatible = "micron,n25q256a";
-                spi-max-frequency = <66000000>;
+                spi-max-frequency = <29000000>;
-        };
+                reg = <1>;
-};
-&ssi2 {
-        status = "okay";
-};
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
-};
-&uart5 { /* for bluetooth */
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart5>;
-        fsl,uart-has-rtscts;
-        status = "okay";
-};
-&usbotg1 {
-        vbus-supply = <&reg_usb_otg1_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usb_otg1_id>;
-        status = "okay";
-};
-&usbotg2 {
-        vbus-supply = <&reg_usb_otg2_vbus>;
-        dr_mode = "host";
-        status = "okay";
-};
-&usdhc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2>;
-        non-removable;
-        no-1-8-v;
-        keep-power-in-suspend;
-        enable-sdio-wakeup;
-        status = "okay";
-};
-&usdhc3 {
-        pinctrl-names = "default", "state_100mhz", "state_200mhz";
-        pinctrl-0 = <&pinctrl_usdhc3>;
-        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
-        bus-width = <8>;
-        cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
-        wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
-        keep-power-in-suspend;
-        enable-sdio-wakeup;
-        vmmc-supply = <&vcc_sd3>;
-        status = "okay";
-};
-&usdhc4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc4>;
-        cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
-        wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
-        status = "okay";
-};
-&iomuxc {
-        imx6x-sdb {
-                pinctrl_audmux: audmuxgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
-                                MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
-                                MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
-                                MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
-                                MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
-                        >;
-                };
-                pinctrl_enet1: enet1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
-                                MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
-                                MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b1
-                                MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
-                                MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
-                                MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
-                                MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
-                                MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
-                                MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
-                                MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
-                                MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
-                                MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
-                                MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
-                                MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
-                                MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
-                        >;
-                };
-                pinctrl_enet_3v3: enet3v3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
-                        >;
-                };
-                pinctrl_enet2: enet2grp {
-                        fsl,pins = <
-                                MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
-                                MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
-                                MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
-                                MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
-                                MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
-                                MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
-                                MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
-                                MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
-                                MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
-                                MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
-                                MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
-                                MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
-                        >;
-                };
-                pinctrl_gpio_keys: gpio_keysgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
-                                MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
-                        >;
-                };
-                pinctrl_i2c1: i2c1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
-                                MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
-                        >;
-                };
-                pinctrl_i2c4: i2c4grp {
-                        fsl,pins = <
-                                MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
-                                MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
-                        >;
-                };
-                pinctrl_lcd: lcdgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
-                                MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
-                                MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
-                                MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
-                                MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
-                                MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
-                                MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
-                        >;
-                };
-                pinctrl_peri_3v3: peri3v3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
-                        >;
-                };
-                pinctrl_pwm3: pwm3grp-1 {
-                        fsl,pins = <
-                                MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
-                        >;
-                };
-                pinctrl_qspi2: qspi2grp {
-                        fsl,pins = <
-                                MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
-                                MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
-                                MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
-                                MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
-                                MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
-                                MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
-                                MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
-                                MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
-                                MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
-                                MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
-                                MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
-                                MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
-                        >;
-                };
-                pinctrl_vcc_sd3: vccsd3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
-                        >;
-                };
-                pinctrl_uart1: uart1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
-                                MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
-                        >;
-                };
-                pinctrl_uart5: uart5grp {
-                        fsl,pins = <
-                                MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
-                                MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
-                                MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
-                                MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
-                        >;
-                };
-                pinctrl_usb_otg1: usbotg1grp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
-                        >;
-                };
-                pinctrl_usb_otg1_id: usbotg1idgrp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
-                        >;
-                };
-                pinctrl_usb_otg2: usbot2ggrp {
-                        fsl,pins = <
-                                MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
-                        >;
-                };
-                pinctrl_usdhc2: usdhc2grp {
-                        fsl,pins = <
-                                MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
-                                MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
-                                MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
-                                MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
-                                MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
-                                MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
-                        >;
-                };
-                pinctrl_usdhc3: usdhc3grp {
-                        fsl,pins = <
-                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
-                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
-                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
-                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
-                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
-                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
-                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
-                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
-                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
-                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
-                                MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
-                                MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
-                        >;
-                };
-                pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
-                        fsl,pins = <
-                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
-                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
-                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
-                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
-                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
-                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
-                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
-                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
-                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
-                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
-                        >;
-                };
-                pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
-                        fsl,pins = <
-                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
-                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
-                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
-                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
-                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
-                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
-                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
-                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
-                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
-                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
-                        >;
-                };
-                pinctrl_usdhc4: usdhc4grp {
-                        fsl,pins = <
-                                MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
-                                MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
-                                MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
-                                MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
-                                MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
-                                MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
-                                MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
-                                MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
-                        >;
-                };
        };
 };
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
new file mode 100644
index 000000000000..cef04cef3a80
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -0,0 +1,562 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sx.dtsi"
+/ {
+        model = "Freescale i.MX6 SoloX SDB Board";
+        compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
+        chosen {
+                stdout-path = &uart1;
+        };
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm3 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEUP>;
+                };
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEDOWN>;
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vcc_sd3: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_vcc_sd3>;
+                        regulator-name = "VCC_SD3";
+                        regulator-min-microvolt = <3000000>;
+                        regulator-max-microvolt = <3000000>;
+                        gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_usb_otg1_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb_otg1>;
+                        regulator-name = "usb_otg1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_usb_otg2_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb_otg2>;
+                        regulator-name = "usb_otg2_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_psu_5v: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "PSU-5V0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                };
+                reg_lcd_3v3: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "lcd-3v3";
+                        gpio = <&gpio3 27 0>;
+                        enable-active-high;
+                };
+                reg_peri_3v3: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_peri_3v3>;
+                        regulator-name = "peri_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        regulator-always-on;
+                };
+                reg_enet_3v3: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_enet_3v3>;
+                        regulator-name = "enet_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+                };
+        };
+        sound {
+                compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
+                model = "wm8962-audio";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "Ext Spk", "SPKOUTL",
+                        "Ext Spk", "SPKOUTR",
+                        "AMIC", "MICBIAS",
+                        "IN3R", "AMIC";
+                mux-int-port = <2>;
+                mux-ext-port = <6>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&fec1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet1>;
+        phy-supply = <&reg_enet_3v3>;
+        phy-mode = "rgmii";
+        phy-handle = <&ethphy1>;
+        status = "okay";
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ethphy1: ethernet-phy@1 {
+                        reg = <1>;
+                };
+                ethphy2: ethernet-phy@2 {
+                        reg = <2>;
+                };
+        };
+};
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2>;
+        phy-mode = "rgmii";
+        phy-handle = <&ethphy2>;
+        status = "okay";
+};
+&i2c4 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c4>;
+        status = "okay";
+        codec: wm8962@1a {
+                compatible = "wlf,wm8962";
+                reg = <0x1a>;
+                clocks = <&clks IMX6SX_CLK_AUDIO>;
+                DCVDD-supply = <&vgen4_reg>;
+                DBVDD-supply = <&vgen4_reg>;
+                AVDD-supply = <&vgen4_reg>;
+                CPVDD-supply = <&vgen4_reg>;
+                MICVDD-supply = <&vgen3_reg>;
+                PLLVDD-supply = <&vgen4_reg>;
+                SPKVDD1-supply = <&reg_psu_5v>;
+                SPKVDD2-supply = <&reg_psu_5v>;
+        };
+};
+&lcdif1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcd>;
+        lcd-supply = <&reg_lcd_3v3>;
+        display = <&display0>;
+        status = "okay";
+        display0: display0 {
+                bits-per-pixel = <16>;
+                bus-width = <24>;
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <33500000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <89>;
+                                hfront-porch = <164>;
+                                vback-porch = <23>;
+                                vfront-porch = <10>;
+                                hsync-len = <10>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+        status = "okay";
+};
+&snvs_poweroff {
+        status = "okay";
+};
+&ssi2 {
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart5 { /* for bluetooth */
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&usbotg1 {
+        vbus-supply = <&reg_usb_otg1_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usb_otg1_id>;
+        status = "okay";
+};
+&usbotg2 {
+        vbus-supply = <&reg_usb_otg2_vbus>;
+        dr_mode = "host";
+        status = "okay";
+};
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        non-removable;
+        no-1-8-v;
+        keep-power-in-suspend;
+        enable-sdio-wakeup;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+        bus-width = <8>;
+        cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+        keep-power-in-suspend;
+        enable-sdio-wakeup;
+        vmmc-supply = <&vcc_sd3>;
+        status = "okay";
+};
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+&iomuxc {
+        imx6x-sdb {
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130b0
+                                MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130b0
+                                MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120b0
+                                MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130b0
+                                MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130b0
+                        >;
+                };
+                pinctrl_enet1: enet1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
+                                MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
+                                MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b1
+                                MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
+                                MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
+                                MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
+                                MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
+                                MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
+                                MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
+                                MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
+                                MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
+                                MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
+                                MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
+                                MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
+                                MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M       0x91
+                        >;
+                };
+                pinctrl_enet_3v3: enet3v3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_ENET2_COL__GPIO2_IO_6         0x80000000
+                        >;
+                };
+                pinctrl_enet2: enet2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
+                                MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
+                                MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
+                                MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
+                                MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
+                                MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
+                                MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
+                                MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
+                                MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
+                                MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
+                                MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
+                                MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
+                        >;
+                };
+                pinctrl_gpio_keys: gpio_keysgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
+                                MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
+                                MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c4: i2c4grp {
+                        fsl,pins = <
+                                MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
+                                MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
+                        >;
+                };
+                pinctrl_lcd: lcdgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
+                                MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
+                                MX6SX_PAD_LCD1_CLK__LCDIF1_CLK  0x4001b0b0
+                                MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
+                                MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
+                                MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
+                                MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
+                        >;
+                };
+                pinctrl_peri_3v3: peri3v3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16     0x80000000
+                        >;
+                };
+                pinctrl_pwm3: pwm3grp-1 {
+                        fsl,pins = <
+                                MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
+                        >;
+                };
+                pinctrl_qspi2: qspi2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
+                                MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
+                                MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
+                                MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
+                                MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
+                                MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
+                                MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
+                                MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
+                                MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
+                                MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
+                                MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
+                                MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
+                        >;
+                };
+                pinctrl_vcc_sd3: vccsd3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_KEY_COL1__GPIO2_IO_11         0x17059
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO04__UART1_TX          0x1b0b1
+                                MX6SX_PAD_GPIO1_IO05__UART1_RX          0x1b0b1
+                        >;
+                };
+                pinctrl_uart5: uart5grp {
+                        fsl,pins = <
+                                MX6SX_PAD_KEY_ROW3__UART5_RX            0x1b0b1
+                                MX6SX_PAD_KEY_COL3__UART5_TX            0x1b0b1
+                                MX6SX_PAD_KEY_ROW2__UART5_CTS_B         0x1b0b1
+                                MX6SX_PAD_KEY_COL2__UART5_RTS_B         0x1b0b1
+                        >;
+                };
+                pinctrl_usb_otg1: usbotg1grp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9        0x10b0
+                        >;
+                };
+                pinctrl_usb_otg1_id: usbotg1idgrp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID    0x17059
+                        >;
+                };
+                pinctrl_usb_otg2: usbot2ggrp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12       0x10b0
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6SX_PAD_SD2_CMD__USDHC2_CMD           0x17059
+                                MX6SX_PAD_SD2_CLK__USDHC2_CLK           0x10059
+                                MX6SX_PAD_SD2_DATA0__USDHC2_DATA0       0x17059
+                                MX6SX_PAD_SD2_DATA1__USDHC2_DATA1       0x17059
+                                MX6SX_PAD_SD2_DATA2__USDHC2_DATA2       0x17059
+                                MX6SX_PAD_SD2_DATA3__USDHC2_DATA3       0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x17059
+                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x10059
+                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x17059
+                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x17059
+                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x17059
+                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x17059
+                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x17059
+                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x17059
+                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x17059
+                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x17059
+                                MX6SX_PAD_KEY_COL0__GPIO2_IO_10         0x17059 /* CD */
+                                MX6SX_PAD_KEY_ROW0__GPIO2_IO_15         0x17059 /* WP */
+                        >;
+                };
+                pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+                        fsl,pins = <
+                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170b9
+                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100b9
+                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170b9
+                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170b9
+                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170b9
+                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170b9
+                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170b9
+                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170b9
+                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170b9
+                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170b9
+                        >;
+                };
+                pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+                        fsl,pins = <
+                                MX6SX_PAD_SD3_CMD__USDHC3_CMD           0x170f9
+                                MX6SX_PAD_SD3_CLK__USDHC3_CLK           0x100f9
+                                MX6SX_PAD_SD3_DATA0__USDHC3_DATA0       0x170f9
+                                MX6SX_PAD_SD3_DATA1__USDHC3_DATA1       0x170f9
+                                MX6SX_PAD_SD3_DATA2__USDHC3_DATA2       0x170f9
+                                MX6SX_PAD_SD3_DATA3__USDHC3_DATA3       0x170f9
+                                MX6SX_PAD_SD3_DATA4__USDHC3_DATA4       0x170f9
+                                MX6SX_PAD_SD3_DATA5__USDHC3_DATA5       0x170f9
+                                MX6SX_PAD_SD3_DATA6__USDHC3_DATA6       0x170f9
+                                MX6SX_PAD_SD3_DATA7__USDHC3_DATA7       0x170f9
+                        >;
+                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6SX_PAD_SD4_CMD__USDHC4_CMD           0x17059
+                                MX6SX_PAD_SD4_CLK__USDHC4_CLK           0x10059
+                                MX6SX_PAD_SD4_DATA0__USDHC4_DATA0       0x17059
+                                MX6SX_PAD_SD4_DATA1__USDHC4_DATA1       0x17059
+                                MX6SX_PAD_SD4_DATA2__USDHC4_DATA2       0x17059
+                                MX6SX_PAD_SD4_DATA3__USDHC4_DATA3       0x17059
+                                MX6SX_PAD_SD4_DATA7__GPIO6_IO_21        0x17059 /* CD */
+                                MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7a24fee1e7ae..708175d59b9c 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -88,6 +88,7 @@
                interrupt-controller;
                reg = <0x00a01000 0x1000>,
                      <0x00a00100 0x100>;
+                interrupt-parent = <&intc>;
        };
        clocks {
@@ -131,7 +132,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
+                interrupt-parent = <&gpc>;
                ranges;
                pmu {
@@ -666,7 +667,7 @@
                                #size-cells = <1>;
                                ranges = <0 0x020cc000 0x4000>;
-                                snvs-rtc-lp@34 {
+                                snvs_rtc: snvs-rtc-lp@34 {
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        reg = <0x34 0x58>;
                                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -700,7 +701,10 @@
                        gpc: gpc@020dc000 {
                                compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
                                reg = <0x020dc000 0x4000>;
+                                interrupt-controller;
+                                #interrupt-cells = <3>;
                                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
                        };
                        iomuxc: iomuxc@020e0000 {
@@ -763,6 +767,7 @@
                                fsl,usbmisc = <&usbmisc 2>;
                                phy_type = "hsic";
                                fsl,anatop = <&anatop>;
+                                dr_mode = "host";
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index e2b2e93d7b61..5b9a376cc31e 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,47 +14,65 @@
        compatible = "ti,omap2420", "ti,omap2";
        ocp {
-                prcm: prcm@48008000 {
+                l4: l4@48000000 {
-                        compatible = "ti,omap2-prcm";
+                        compatible = "ti,omap2-l4", "simple-bus";
-                        reg = <0x48008000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x48000000 0x100000>;
-                        prcm_clocks: clocks {
+                        prcm: prcm@8000 {
-                                #address-cells = <1>;
+                                compatible = "ti,omap2-prcm";
-                                #size-cells = <0>;
+                                reg = <0x8000 0x1000>;
-                        };
-                        prcm_clockdomains: clockdomains {
+                                prcm_clocks: clocks {
-                        };
+                                        #address-cells = <1>;
-                };
+                                        #size-cells = <0>;
+                                };
-                scrm: scrm@48000000 {
+                                prcm_clockdomains: clockdomains {
-                        compatible = "ti,omap2-scrm";
+                                };
-                        reg = <0x48000000 0x1000>;
+                        };
-                        scrm_clocks: clocks {
+                        scm: scm@0 {
+                                compatible = "ti,omap2-scm", "simple-bus";
+                                reg = <0x0 0x1000>;
                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x0 0x1000>;
+                                omap2420_pmx: pinmux@30 {
+                                        compatible = "ti,omap2420-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x30 0x0113>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pinctrl-single,register-width = <8>;
+                                        pinctrl-single,function-mask = <0x3f>;
+                                };
+                                scm_conf: scm_conf@270 {
+                                        compatible = "syscon";
+                                        reg = <0x270 0x100>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+                                scm_clockdomains: clockdomains {
+                                };
                        };
-                        scrm_clockdomains: clockdomains {
+                        counter32k: counter@4000 {
+                                compatible = "ti,omap-counter32k";
+                                reg = <0x4000 0x20>;
+                                ti,hwmods = "counter_32k";
                        };
                };
-                counter32k: counter@48004000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x48004000 0x20>;
-                        ti,hwmods = "counter_32k";
-                };
-                omap2420_pmx: pinmux@48000030 {
-                        compatible = "ti,omap2420-padconf", "pinctrl-single";
-                        reg = <0x48000030 0x0113>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        pinctrl-single,register-width = <8>;
-                        pinctrl-single,function-mask = <0x3f>;
-                };
                gpio1: gpio@48018000 {
                        compatible = "ti,omap2-gpio";
                        reg = <0x48018000 0x200>;
diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi
index 805f75df1cf2..93fed68839b9 100644
--- a/arch/arm/boot/dts/omap2430-clocks.dtsi
+++ b/arch/arm/boot/dts/omap2430-clocks.dtsi
@@ -8,12 +8,12 @@
 * published by the Free Software Foundation.
 */
-&scrm_clocks {
+&scm_clocks {
        mcbsp3_mux_fck: mcbsp3_mux_fck {
                #clock-cells = <0>;
                compatible = "ti,composite-mux-clock";
                clocks = <&func_96m_ck>, <&mcbsp_clks>;
-                reg = <0x02e8>;
+                reg = <0x78>;
        };
        mcbsp3_fck: mcbsp3_fck {
@@ -27,7 +27,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&func_96m_ck>, <&mcbsp_clks>;
                ti,bit-shift = <2>;
-                reg = <0x02e8>;
+                reg = <0x78>;
        };
        mcbsp4_fck: mcbsp4_fck {
@@ -41,7 +41,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&func_96m_ck>, <&mcbsp_clks>;
                ti,bit-shift = <4>;
-                reg = <0x02e8>;
+                reg = <0x78>;
        };
        mcbsp5_fck: mcbsp5_fck {
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 0dc8de2782b1..11a7963be003 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,60 +14,73 @@
        compatible = "ti,omap2430", "ti,omap2";
        ocp {
-                prcm: prcm@49006000 {
+                l4_wkup: l4_wkup@49000000 {
-                        compatible = "ti,omap2-prcm";
+                        compatible = "ti,omap2-l4-wkup", "simple-bus";
-                        reg = <0x49006000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x49000000 0x31000>;
-                        prcm_clocks: clocks {
+                        prcm: prcm@6000 {
-                                #address-cells = <1>;
+                                compatible = "ti,omap2-prcm";
-                                #size-cells = <0>;
+                                reg = <0x6000 0x1000>;
-                        };
-                        prcm_clockdomains: clockdomains {
+                                prcm_clocks: clocks {
-                        };
+                                        #address-cells = <1>;
-                };
+                                        #size-cells = <0>;
+                                };
-                scrm: scrm@49002000 {
-                        compatible = "ti,omap2-scrm";
-                        reg = <0x49002000 0x1000>;
-                        scrm_clocks: clocks {
+                                prcm_clockdomains: clockdomains {
-                                #address-cells = <1>;
+                                };
-                                #size-cells = <0>;
                        };
-                        scrm_clockdomains: clockdomains {
+                        scm: scm@2000 {
+                                compatible = "ti,omap2-scm", "simple-bus";
+                                reg = <0x2000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x1000>;
+                                omap2430_pmx: pinmux@30 {
+                                        compatible = "ti,omap2430-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x30 0x0154>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        pinctrl-single,register-width = <8>;
+                                        pinctrl-single,function-mask = <0x3f>;
+                                };
+                                scm_conf: scm_conf@270 {
+                                        compatible = "syscon";
+                                        reg = <0x270 0x240>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0x230 0x4>;
+                                                syscon = <&scm_conf>;
+                                                pbias_mmc_reg: pbias_mmc_omap2430 {
+                                                        regulator-name = "pbias_mmc_omap2430";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
+                                scm_clockdomains: clockdomains {
+                                };
                        };
-                };
-                counter32k: counter@49020000 {
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x49020000 0x20>;
-                        ti,hwmods = "counter_32k";
-                };
-                omap2430_pmx: pinmux@49002030 {
-                        compatible = "ti,omap2430-padconf", "pinctrl-single";
-                        reg = <0x49002030 0x0154>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        pinctrl-single,register-width = <8>;
-                        pinctrl-single,function-mask = <0x3f>;
-                };
-                omap2_scm_general: tisyscon@49002270 {
-                        compatible = "syscon";
-                        reg = <0x49002270 0x240>;
-                };
-                pbias_regulator: pbias_regulator {
+                        counter32k: counter@20000 {
-                        compatible = "ti,pbias-omap";
+                                compatible = "ti,omap-counter32k";
-                        reg = <0x230 0x4>;
+                                reg = <0x20000 0x20>;
-                        syscon = <&omap2_scm_general>;
+                                ti,hwmods = "counter_32k";
-                        pbias_mmc_reg: pbias_mmc_omap2430 {
-                                regulator-name = "pbias_mmc_omap2430";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3000000>;
                        };
                };
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi
index a1365ca926eb..63965b876973 100644
--- a/arch/arm/boot/dts/omap24xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi
@@ -7,13 +7,13 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-&scrm_clocks {
+&scm_clocks {
        mcbsp1_mux_fck: mcbsp1_mux_fck {
                #clock-cells = <0>;
                compatible = "ti,composite-mux-clock";
                clocks = <&func_96m_ck>, <&mcbsp_clks>;
                ti,bit-shift = <2>;
-                reg = <0x0274>;
+                reg = <0x4>;
        };
        mcbsp1_fck: mcbsp1_fck {
@@ -27,7 +27,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&func_96m_ck>, <&mcbsp_clks>;
                ti,bit-shift = <6>;
-                reg = <0x0274>;
+                reg = <0x4>;
        };
        mcbsp2_fck: mcbsp2_fck {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 3fdc84fddb70..d18a90f5eca3 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -87,6 +87,60 @@
                ranges;
                ti,hwmods = "l3_main";
+                l4_core: l4@48000000 {
+                        compatible = "ti,omap3-l4-core", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x48000000 0x1000000>;
+                        scm: scm@2000 {
+                                compatible = "ti,omap3-scm", "simple-bus";
+                                reg = <0x2000 0x2000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x2000>;
+                                omap3_pmx_core: pinmux@30 {
+                                        compatible = "ti,omap3-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x30 0x238>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0xff1f>;
+                                };
+                                scm_conf: scm_conf@270 {
+                                        compatible = "syscon";
+                                        reg = <0x270 0x330>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        scm_clocks: clocks {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+                                scm_clockdomains: clockdomains {
+                                };
+                                omap3_pmx_wkup: pinmux@a00 {
+                                        compatible = "ti,omap3-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0xa00 0x5c>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0xff1f>;
+                                };
+                        };
+                };
                aes: aes@480c5000 {
                        compatible = "ti,omap3-aes";
                        ti,hwmods = "aes";
@@ -123,19 +177,6 @@
                        };
                };
-                scrm: scrm@48002000 {
-                        compatible = "ti,omap3-scrm";
-                        reg = <0x48002000 0x2000>;
-                        scrm_clocks: clocks {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        scrm_clockdomains: clockdomains {
-                        };
-                };
                counter32k: counter@48320000 {
                        compatible = "ti,omap-counter32k";
                        reg = <0x48320000 0x20>;
@@ -161,37 +202,10 @@
                        dma-requests = <96>;
                };
-                omap3_pmx_core: pinmux@48002030 {
-                        compatible = "ti,omap3-padconf", "pinctrl-single";
-                        reg = <0x48002030 0x0238>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0xff1f>;
-                };
-                omap3_pmx_wkup: pinmux@48002a00 {
-                        compatible = "ti,omap3-padconf", "pinctrl-single";
-                        reg = <0x48002a00 0x5c>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0xff1f>;
-                };
-                omap3_scm_general: tisyscon@48002270 {
-                        compatible = "syscon";
-                        reg = <0x48002270 0x2f0>;
-                };
                pbias_regulator: pbias_regulator {
                        compatible = "ti,pbias-omap";
                        reg = <0x2b0 0x4>;
-                        syscon = <&omap3_scm_general>;
+                        syscon = <&scm_conf>;
                        pbias_mmc_reg: pbias_mmc_omap2430 {
                                regulator-name = "pbias_mmc_omap2430";
                                regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 7bc8c0f72ddb..4f6b2d5b1902 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -46,7 +46,7 @@
                               0x480bd800 0x017c>;
                        interrupts = <24>;
                        iommus = <&mmu_isp>;
-                        syscon = <&omap3_scm_general 0xdc>;
+                        syscon = <&scm_conf 0xdc>;
                        ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
                        #clock-cells = <1>;
                        ports {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 3502fe00ec7d..86253de5a97a 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -78,7 +78,7 @@
                               0x480bd800 0x0600>;
                        interrupts = <24>;
                        iommus = <&mmu_isp>;
-                        syscon = <&omap3_scm_general 0x2f0>;
+                        syscon = <&scm_conf 0x2f0>;
                        ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
                        #clock-cells = <1>;
                        ports {
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 5c375003bad1..bbba5bdc4bc9 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -79,13 +79,14 @@
                clock-div = <1>;
        };
 };
-&scrm_clocks {
+&scm_clocks {
        mcbsp5_mux_fck: mcbsp5_mux_fck {
                #clock-cells = <0>;
                compatible = "ti,composite-mux-clock";
                clocks = <&core_96m_fck>, <&mcbsp_clks>;
                ti,bit-shift = <4>;
-                reg = <0x02d8>;
+                reg = <0x68>;
        };
        mcbsp5_fck: mcbsp5_fck {
@@ -99,7 +100,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&core_96m_fck>, <&mcbsp_clks>;
                ti,bit-shift = <2>;
-                reg = <0x0274>;
+                reg = <0x04>;
        };
        mcbsp1_fck: mcbsp1_fck {
@@ -113,7 +114,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&per_96m_fck>, <&mcbsp_clks>;
                ti,bit-shift = <6>;
-                reg = <0x0274>;
+                reg = <0x04>;
        };
        mcbsp2_fck: mcbsp2_fck {
@@ -126,7 +127,7 @@
                #clock-cells = <0>;
                compatible = "ti,composite-mux-clock";
                clocks = <&per_96m_fck>, <&mcbsp_clks>;
-                reg = <0x02d8>;
+                reg = <0x68>;
        };
        mcbsp3_fck: mcbsp3_fck {
@@ -140,7 +141,7 @@
                compatible = "ti,composite-mux-clock";
                clocks = <&per_96m_fck>, <&mcbsp_clks>;
                ti,bit-shift = <2>;
-                reg = <0x02d8>;
+                reg = <0x68>;
        };
        mcbsp4_fck: mcbsp4_fck {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index f2091d1c9c36..f884d6adb71e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -124,99 +124,141 @@
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                cm1: cm1@4a004000 {
+                l4_cfg: l4@4a000000 {
-                        compatible = "ti,omap4-cm1";
+                        compatible = "ti,omap4-l4-cfg", "simple-bus";
-                        reg = <0x4a004000 0x2000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
-                        cm1_clocks: clocks {
+                        ranges = <0 0x4a000000 0x1000000>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                        };
-                        cm1_clockdomains: clockdomains {
+                        cm1: cm1@4000 {
-                        };
+                                compatible = "ti,omap4-cm1";
-                };
+                                reg = <0x4000 0x2000>;
-                prm: prm@4a306000 {
+                                cm1_clocks: clocks {
-                        compatible = "ti,omap4-prm";
+                                        #address-cells = <1>;
-                        reg = <0x4a306000 0x3000>;
+                                        #size-cells = <0>;
-                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                };
-                        prm_clocks: clocks {
+                                cm1_clockdomains: clockdomains {
-                                #address-cells = <1>;
+                                };
-                                #size-cells = <0>;
                        };
-                        prm_clockdomains: clockdomains {
+                        cm2: cm2@8000 {
-                        };
+                                compatible = "ti,omap4-cm2";
-                };
+                                reg = <0x8000 0x3000>;
-                cm2: cm2@4a008000 {
+                                cm2_clocks: clocks {
-                        compatible = "ti,omap4-cm2";
+                                        #address-cells = <1>;
-                        reg = <0x4a008000 0x3000>;
+                                        #size-cells = <0>;
+                                };
-                        cm2_clocks: clocks {
+                                cm2_clockdomains: clockdomains {
-                                #address-cells = <1>;
+                                };
-                                #size-cells = <0>;
                        };
-                        cm2_clockdomains: clockdomains {
+                        omap4_scm_core: scm@2000 {
+                                compatible = "ti,omap4-scm-core", "simple-bus";
+                                reg = <0x2000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x1000>;
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                };
                        };
-                };
-                scrm: scrm@4a30a000 {
-                        compatible = "ti,omap4-scrm";
-                        reg = <0x4a30a000 0x2000>;
-                        scrm_clocks: clocks {
+                        omap4_padconf_core: scm@100000 {
+                                compatible = "ti,omap4-scm-padconf-core",
+                                             "simple-bus";
                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x100000 0x1000>;
+                                omap4_pmx_core: pinmux@40 {
+                                        compatible = "ti,omap4-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x40 0x0196>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0x7fff>;
+                                };
+                                omap4_padconf_global: omap4_padconf_global@5a0 {
+                                        compatible = "syscon";
+                                        reg = <0x5a0 0x170>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0x60 0x4>;
+                                                syscon = <&omap4_padconf_global>;
+                                                pbias_mmc_reg: pbias_mmc_omap4 {
+                                                        regulator-name = "pbias_mmc_omap4";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
                        };
-                        scrm_clockdomains: clockdomains {
+                        l4_wkup: l4@300000 {
-                        };
+                                compatible = "ti,omap4-l4-wkup", "simple-bus";
-                };
+                                #address-cells = <1>;
+                                #size-cells = <1>;
-                counter32k: counter@4a304000 {
+                                ranges = <0 0x300000 0x40000>;
-                        compatible = "ti,omap-counter32k";
-                        reg = <0x4a304000 0x20>;
+                                counter32k: counter@4000 {
-                        ti,hwmods = "counter_32k";
+                                        compatible = "ti,omap-counter32k";
-                };
+                                        reg = <0x4000 0x20>;
+                                        ti,hwmods = "counter_32k";
-                omap4_pmx_core: pinmux@4a100040 {
+                                };
-                        compatible = "ti,omap4-padconf", "pinctrl-single";
-                        reg = <0x4a100040 0x0196>;
+                                prm: prm@6000 {
-                        #address-cells = <1>;
+                                        compatible = "ti,omap4-prm";
-                        #size-cells = <0>;
+                                        reg = <0x6000 0x3000>;
-                        #interrupt-cells = <1>;
+                                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
+                                        prm_clocks: clocks {
-                        pinctrl-single,function-mask = <0x7fff>;
+                                                #address-cells = <1>;
-                };
+                                                #size-cells = <0>;
-                omap4_pmx_wkup: pinmux@4a31e040 {
+                                        };
-                        compatible = "ti,omap4-padconf", "pinctrl-single";
-                        reg = <0x4a31e040 0x0038>;
+                                        prm_clockdomains: clockdomains {
-                        #address-cells = <1>;
+                                        };
-                        #size-cells = <0>;
+                                };
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
+                                scrm: scrm@a000 {
-                        pinctrl-single,register-width = <16>;
+                                        compatible = "ti,omap4-scrm";
-                        pinctrl-single,function-mask = <0x7fff>;
+                                        reg = <0xa000 0x2000>;
-                };
+                                        scrm_clocks: clocks {
-                omap4_padconf_global: tisyscon@4a1005a0 {
+                                                #address-cells = <1>;
-                        compatible = "syscon";
+                                                #size-cells = <0>;
-                        reg = <0x4a1005a0 0x170>;
+                                        };
-                };
+                                        scrm_clockdomains: clockdomains {
-                pbias_regulator: pbias_regulator {
+                                        };
-                        compatible = "ti,pbias-omap";
+                                };
-                        reg = <0x60 0x4>;
-                        syscon = <&omap4_padconf_global>;
+                                omap4_pmx_wkup: pinmux@1e040 {
-                        pbias_mmc_reg: pbias_mmc_omap4 {
+                                        compatible = "ti,omap4-padconf",
-                                regulator-name = "pbias_mmc_omap4";
+                                                     "pinctrl-single";
-                                regulator-min-microvolt = <1800000>;
+                                        reg = <0x1e040 0x0038>;
-                                regulator-max-microvolt = <3000000>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0x7fff>;
+                                };
                        };
                };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 77b5f70d0ebc..efe5f737f39b 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -139,99 +139,141 @@
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                prm: prm@4ae06000 {
+                l4_cfg: l4@4a000000 {
-                        compatible = "ti,omap5-prm";
+                        compatible = "ti,omap5-l4-cfg", "simple-bus";
-                        reg = <0x4ae06000 0x3000>;
+                        #address-cells = <1>;
-                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4a000000 0x22a000>;
-                        prm_clocks: clocks {
+                        scm_core: scm@2000 {
+                                compatible = "ti,omap5-scm-core", "simple-bus";
+                                reg = <0x2000 0x1000>;
                                #address-cells = <1>;
-                                #size-cells = <0>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2000 0x800>;
+                                scm_conf: scm_conf@0 {
+                                        compatible = "syscon";
+                                        reg = <0x0 0x800>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                };
                        };
-                        prm_clockdomains: clockdomains {
+                        scm_padconf_core: scm@2800 {
+                                compatible = "ti,omap5-scm-padconf-core",
+                                             "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x2800 0x800>;
+                                omap5_pmx_core: pinmux@40 {
+                                        compatible = "ti,omap5-padconf",
+                                                     "pinctrl-single";
+                                        reg = <0x40 0x01b6>;
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        #interrupt-cells = <1>;
+                                        interrupt-controller;
+                                        pinctrl-single,register-width = <16>;
+                                        pinctrl-single,function-mask = <0x7fff>;
+                                };
+                                omap5_padconf_global: omap5_padconf_global@5a0 {
+                                        compatible = "syscon";
+                                        reg = <0x5a0 0xec>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        pbias_regulator: pbias_regulator {
+                                                compatible = "ti,pbias-omap";
+                                                reg = <0x60 0x4>;
+                                                syscon = <&omap5_padconf_global>;
+                                                pbias_mmc_reg: pbias_mmc_omap5 {
+                                                        regulator-name = "pbias_mmc_omap5";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <3000000>;
+                                                };
+                                        };
+                                };
                        };
-                };
-                cm_core_aon: cm_core_aon@4a004000 {
+                        cm_core_aon: cm_core_aon@4000 {
-                        compatible = "ti,omap5-cm-core-aon";
+                                compatible = "ti,omap5-cm-core-aon";
-                        reg = <0x4a004000 0x2000>;
+                                reg = <0x4000 0x2000>;
-                        cm_core_aon_clocks: clocks {
+                                cm_core_aon_clocks: clocks {
-                                #address-cells = <1>;
+                                        #address-cells = <1>;
-                                #size-cells = <0>;
+                                        #size-cells = <0>;
-                        };
+                                };
-                        cm_core_aon_clockdomains: clockdomains {
+                                cm_core_aon_clockdomains: clockdomains {
+                                };
                        };
-                };
-                scrm: scrm@4ae0a000 {
+                        cm_core: cm_core@8000 {
-                        compatible = "ti,omap5-scrm";
+                                compatible = "ti,omap5-cm-core";
-                        reg = <0x4ae0a000 0x2000>;
+                                reg = <0x8000 0x3000>;
-                        scrm_clocks: clocks {
+                                cm_core_clocks: clocks {
-                                #address-cells = <1>;
+                                        #address-cells = <1>;
-                                #size-cells = <0>;
+                                        #size-cells = <0>;
-                        };
+                                };
-                        scrm_clockdomains: clockdomains {
+                                cm_core_clockdomains: clockdomains {
+                                };
                        };
                };
-                cm_core: cm_core@4a008000 {
+                l4_wkup: l4@4ae00000 {
-                        compatible = "ti,omap5-cm-core";
+                        compatible = "ti,omap5-l4-wkup", "simple-bus";
-                        reg = <0x4a008000 0x3000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x4ae00000 0x2b000>;
-                        cm_core_clocks: clocks {
+                        counter32k: counter@4000 {
-                                #address-cells = <1>;
+                                compatible = "ti,omap-counter32k";
-                                #size-cells = <0>;
+                                reg = <0x4000 0x40>;
+                                ti,hwmods = "counter_32k";
                        };
-                        cm_core_clockdomains: clockdomains {
+                        prm: prm@6000 {
+                                compatible = "ti,omap5-prm";
+                                reg = <0x6000 0x3000>;
+                                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                prm_clocks: clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                };
+                                prm_clockdomains: clockdomains {
+                                };
                        };
-                };
-                counter32k: counter@4ae04000 {
+                        scrm: scrm@a000 {
-                        compatible = "ti,omap-counter32k";
+                                compatible = "ti,omap5-scrm";
-                        reg = <0x4ae04000 0x40>;
+                                reg = <0xa000 0x2000>;
-                        ti,hwmods = "counter_32k";
-                };
-                omap5_pmx_core: pinmux@4a002840 {
+                                scrm_clocks: clocks {
-                        compatible = "ti,omap5-padconf", "pinctrl-single";
+                                        #address-cells = <1>;
-                        reg = <0x4a002840 0x01b6>;
+                                        #size-cells = <0>;
-                        #address-cells = <1>;
+                                };
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0x7fff>;
-                };
-                omap5_pmx_wkup: pinmux@4ae0c840 {
-                        compatible = "ti,omap5-padconf", "pinctrl-single";
-                        reg = <0x4ae0c840 0x0038>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        pinctrl-single,register-width = <16>;
-                        pinctrl-single,function-mask = <0x7fff>;
-                };
-                omap5_padconf_global: tisyscon@4a002da0 {
+                                scrm_clockdomains: clockdomains {
-                        compatible = "syscon";
+                                };
-                        reg = <0x4A002da0 0xec>;
+                        };
-                };
-                pbias_regulator: pbias_regulator {
+                        omap5_pmx_wkup: pinmux@c840 {
-                        compatible = "ti,pbias-omap";
+                                compatible = "ti,omap5-padconf",
-                        reg = <0x60 0x4>;
+                                             "pinctrl-single";
-                        syscon = <&omap5_padconf_global>;
+                                reg = <0xc840 0x0038>;
-                        pbias_mmc_reg: pbias_mmc_omap5 {
+                                #address-cells = <1>;
-                                regulator-name = "pbias_mmc_omap5";
+                                #size-cells = <0>;
-                                regulator-min-microvolt = <1800000>;
+                                #interrupt-cells = <1>;
-                                regulator-max-microvolt = <3000000>;
+                                interrupt-controller;
+                                pinctrl-single,register-width = <16>;
+                                pinctrl-single,function-mask = <0x7fff>;
                        };
                };
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 36cafbfa1bfa..606753eb72c8 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -12,6 +12,12 @@
                bootargs = "console=ttyLP0,115200";
        };
+        clk16m: clk16m {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <16000000>;
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -47,6 +53,21 @@
        status  = "okay";
 };
+&dspi1 {
+        status = "okay";
+        mcp2515can: can@0 {
+                compatible = "microchip,mcp2515";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_can_int>;
+                reg = <0>;
+                clocks = <&clk16m>;
+                spi-max-frequency = <10000000>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <11 GPIO_ACTIVE_LOW>;
+        };
+};
 &esdhc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_esdhc1>;
@@ -94,3 +115,13 @@
 &usbh1 {
        vbus-supply = <&usbh_vbus_reg>;
 };
+&iomuxc {
+        vf610-colibri {
+                pinctrl_can_int: can_int {
+                        fsl,pins = <
+                                VF610_PAD_PTB21__GPIO_43        0x22ed
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 5c2b7320856d..fbef0828e930 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -23,6 +23,12 @@
        status = "okay";
 };
+&dspi1 {
+        bus-num = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_dspi1>;
+};
 &edma0 {
        status = "okay";
 };
@@ -107,6 +113,15 @@
                        >;
                };
+                pinctrl_dspi1: dspi1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTD5__DSPI1_CS0               0x33e2
+                                VF610_PAD_PTD6__DSPI1_SIN               0x33e1
+                                VF610_PAD_PTD7__DSPI1_SOUT              0x33e2
+                                VF610_PAD_PTD8__DSPI1_SCK               0x33e2
+                        >;
+                };
                pinctrl_esdhc1: esdhc1grp {
                        fsl,pins = <
                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 1dbf8d2d1ddf..e976d2fa1527 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -24,14 +24,13 @@
        };
        soc {
-                interrupt-parent = <&intc>;
                aips-bus@40000000 {
                        intc: interrupt-controller@40002000 {
                                compatible = "arm,cortex-a9-gic";
                                #interrupt-cells = <3>;
                                interrupt-controller;
+                                interrupt-parent = <&intc>;
                                reg = <0x40003000 0x1000>,
                                      <0x40002100 0x100>;
                        };
@@ -40,145 +39,17 @@
                                compatible = "arm,cortex-a9-global-timer";
                                reg = <0x40002200 0x20>;
                                interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-parent = <&intc>;
                                clocks = <&clks VF610_CLK_PLATFORM_BUS>;
                        };
                };
        };
 };
-&adc0 {
+&mscm_ir {
-        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-parent = <&intc>;
-};
-&adc1 {
-        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-};
-&can0 {
-        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-};
-&can1 {
-        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-};
-&dspi0 {
-        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-};
-&edma0 {
-        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-                        <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-        interrupt-names = "edma-tx", "edma-err";
-};
-&edma1 {
-        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-                        <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-        interrupt-names = "edma-tx", "edma-err";
-};
-&esdhc1 {
-        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-};
-&fec0 {
-        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-};
-&fec1 {
-        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-};
-&ftm {
-        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-};
-&gpio0 {
-        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-};
-&gpio1 {
-        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-};
-&gpio2 {
-        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-};
-&gpio3 {
-        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-};
-&gpio4 {
-        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-};
-&i2c0 {
-        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-};
-&pit {
-        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-};
-&qspi0 {
-        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-};
-&sai2 {
-        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-};
-&snvsrtc {
-        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
-};
-&src {
-        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart0 {
-        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart1 {
-        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart2 {
-        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart3 {
-        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart4 {
-        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-};
-&uart5 {
-        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-};
-&usbdev0 {
-        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-};
-&usbh1 {
-        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-};
-&usbphy0 {
-        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-};
-&usbphy1 {
-        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 };
 &wdoga5 {
-        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index a29c7ce15eaf..4aa335166be7 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -54,6 +54,7 @@
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
+                interrupt-parent = <&mscm_ir>;
                ranges;
                aips0: aips-bus@40000000 {
@@ -62,6 +63,19 @@
                        #size-cells = <1>;
                        ranges;
+                        mscm_cpucfg: cpucfg@40001000 {
+                                compatible = "fsl,vf610-mscm-cpucfg", "syscon";
+                                reg = <0x40001000 0x800>;
+                        };
+                        mscm_ir: interrupt-controller@40001800 {
+                                compatible = "fsl,vf610-mscm-ir";
+                                reg = <0x40001800 0x400>;
+                                fsl,cpucfg = <&mscm_cpucfg>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
                        edma0: dma-controller@40018000 {
                                #dma-cells = <2>;
                                compatible = "fsl,vf610-edma";
@@ -69,6 +83,9 @@
                                        <0x40024000 0x1000>,
                                        <0x40025000 0x1000>;
                                dma-channels = <32>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
+                                                <9 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "edma-tx", "edma-err";
                                clock-names = "dmamux0", "dmamux1";
                                clocks = <&clks VF610_CLK_DMAMUX0>,
                                        <&clks VF610_CLK_DMAMUX1>;
@@ -78,6 +95,7 @@
                        can0: flexcan@40020000 {
                                compatible = "fsl,vf610-flexcan";
                                reg = <0x40020000 0x4000>;
+                                interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_FLEXCAN0>,
                                         <&clks VF610_CLK_FLEXCAN0>;
                                clock-names = "ipg", "per";
@@ -87,6 +105,7 @@
                        uart0: serial@40027000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x40027000 0x1000>;
+                                interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART0>;
                                clock-names = "ipg";
                                dmas = <&edma0 0 2>,
@@ -98,6 +117,7 @@
                        uart1: serial@40028000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x40028000 0x1000>;
+                                interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART1>;
                                clock-names = "ipg";
                                dmas = <&edma0 0 4>,
@@ -109,6 +129,7 @@
                        uart2: serial@40029000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x40029000 0x1000>;
+                                interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART2>;
                                clock-names = "ipg";
                                dmas = <&edma0 0 6>,
@@ -120,6 +141,7 @@
                        uart3: serial@4002a000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x4002a000 0x1000>;
+                                interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART3>;
                                clock-names = "ipg";
                                dmas = <&edma0 0 8>,
@@ -133,15 +155,29 @@
                                #size-cells = <0>;
                                compatible = "fsl,vf610-dspi";
                                reg = <0x4002c000 0x1000>;
+                                interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_DSPI0>;
                                clock-names = "dspi";
                                spi-num-chipselects = <5>;
                                status = "disabled";
                        };
+                        dspi1: dspi1@4002d000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-dspi";
+                                reg = <0x4002d000 0x1000>;
+                                interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks VF610_CLK_DSPI1>;
+                                clock-names = "dspi";
+                                spi-num-chipselects = <5>;
+                                status = "disabled";
+                        };
                        sai2: sai@40031000 {
                                compatible = "fsl,vf610-sai";
                                reg = <0x40031000 0x1000>;
+                                interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_SAI2>;
                                clock-names = "sai";
                                dma-names = "tx", "rx";
@@ -153,6 +189,7 @@
                        pit: pit@40037000 {
                                compatible = "fsl,vf610-pit";
                                reg = <0x40037000 0x1000>;
+                                interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_PIT>;
                                clock-names = "pit";
                        };
@@ -186,6 +223,7 @@
                        adc0: adc@4003b000 {
                                compatible = "fsl,vf610-adc";
                                reg = <0x4003b000 0x1000>;
+                                interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_ADC0>;
                                clock-names = "adc";
                                status = "disabled";
@@ -194,6 +232,7 @@
                        wdoga5: wdog@4003e000 {
                                compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
                                reg = <0x4003e000 0x1000>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_WDT>;
                                clock-names = "wdog";
                                status = "disabled";
@@ -204,6 +243,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,vf610-qspi";
                                reg = <0x40044000 0x1000>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_QSPI0_EN>,
                                        <&clks VF610_CLK_QSPI0>;
                                clock-names = "qspi_en", "qspi";
@@ -213,7 +253,6 @@
                        iomuxc: iomuxc@40048000 {
                                compatible = "fsl,vf610-iomuxc";
                                reg = <0x40048000 0x1000>;
-                                #gpio-range-cells = <3>;
                        };
                        gpio0: gpio@40049000 {
@@ -221,6 +260,7 @@
                                reg = <0x40049000 0x1000 0x400ff000 0x40>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                                interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                gpio-ranges = <&iomuxc 0 0 32>;
@@ -231,6 +271,7 @@
                                reg = <0x4004a000 0x1000 0x400ff040 0x40>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                                interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                gpio-ranges = <&iomuxc 0 32 32>;
@@ -241,6 +282,7 @@
                                reg = <0x4004b000 0x1000 0x400ff080 0x40>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                                interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                gpio-ranges = <&iomuxc 0 64 32>;
@@ -251,6 +293,7 @@
                                reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                                interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                gpio-ranges = <&iomuxc 0 96 32>;
@@ -261,6 +304,7 @@
                                reg = <0x4004d000 0x1000 0x400ff100 0x40>;
                                gpio-controller;
                                #gpio-cells = <2>;
+                                interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                gpio-ranges = <&iomuxc 0 128 7>;
@@ -274,6 +318,7 @@
                        usbphy0: usbphy@40050800 {
                                compatible = "fsl,vf610-usbphy";
                                reg = <0x40050800 0x400>;
+                                interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_USBPHY0>;
                                fsl,anatop = <&anatop>;
                                status = "disabled";
@@ -282,6 +327,7 @@
                        usbphy1: usbphy@40050c00 {
                                compatible = "fsl,vf610-usbphy";
                                reg = <0x40050c00 0x400>;
+                                interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_USBPHY1>;
                                fsl,anatop = <&anatop>;
                                status = "disabled";
@@ -292,6 +338,7 @@
                                #size-cells = <0>;
                                compatible = "fsl,vf610-i2c";
                                reg = <0x40066000 0x1000>;
+                                interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_I2C0>;
                                clock-names = "ipg";
                                dmas = <&edma0 0 50>,
@@ -311,6 +358,7 @@
                        usbdev0: usb@40034000 {
                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
                                reg = <0x40034000 0x800>;
+                                interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_USBC0>;
                                fsl,usbphy = <&usbphy0>;
                                fsl,usbmisc = <&usbmisc0 0>;
@@ -329,6 +377,7 @@
                        src: src@4006e000 {
                                compatible = "fsl,vf610-src", "syscon";
                                reg = <0x4006e000 0x1000>;
+                                interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
@@ -345,6 +394,9 @@
                                        <0x400a1000 0x1000>,
                                        <0x400a2000 0x1000>;
                                dma-channels = <32>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+                                                <11 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "edma-tx", "edma-err";
                                clock-names = "dmamux0", "dmamux1";
                                clocks = <&clks VF610_CLK_DMAMUX2>,
                                        <&clks VF610_CLK_DMAMUX3>;
@@ -360,6 +412,7 @@
                                snvsrtc: snvs-rtc-lp@34 {
                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
                                        reg = <0x34 0x58>;
+                                        interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clks VF610_CLK_SNVS>;
                                        clock-names = "snvs-rtc";
                                };
@@ -368,6 +421,7 @@
                        uart4: serial@400a9000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x400a9000 0x1000>;
+                                interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART4>;
                                clock-names = "ipg";
                                status = "disabled";
@@ -376,6 +430,7 @@
                        uart5: serial@400aa000 {
                                compatible = "fsl,vf610-lpuart";
                                reg = <0x400aa000 0x1000>;
+                                interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_UART5>;
                                clock-names = "ipg";
                                status = "disabled";
@@ -384,6 +439,7 @@
                        adc1: adc@400bb000 {
                                compatible = "fsl,vf610-adc";
                                reg = <0x400bb000 0x1000>;
+                                interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_ADC1>;
                                clock-names = "adc";
                                status = "disabled";
@@ -392,6 +448,7 @@
                        esdhc1: esdhc@400b2000 {
                                compatible = "fsl,imx53-esdhc";
                                reg = <0x400b2000 0x1000>;
+                                interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_IPG_BUS>,
                                        <&clks VF610_CLK_PLATFORM_BUS>,
                                        <&clks VF610_CLK_ESDHC1>;
@@ -402,6 +459,7 @@
                        usbh1: usb@400b4000 {
                                compatible = "fsl,vf610-usb", "fsl,imx27-usb";
                                reg = <0x400b4000 0x800>;
+                                interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_USBC1>;
                                fsl,usbphy = <&usbphy1>;
                                fsl,usbmisc = <&usbmisc1 0>;
@@ -420,6 +478,7 @@
                        ftm: ftm@400b8000 {
                                compatible = "fsl,ftm-timer";
                                reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+                                interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
                                clock-names = "ftm-evt", "ftm-src",
                                        "ftm-evt-counter-en", "ftm-src-counter-en";
                                clocks = <&clks VF610_CLK_FTM2>,
@@ -432,6 +491,7 @@
                        fec0: ethernet@400d0000 {
                                compatible = "fsl,mvf600-fec";
                                reg = <0x400d0000 0x1000>;
+                                interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_ENET0>,
                                        <&clks VF610_CLK_ENET0>,
                                        <&clks VF610_CLK_ENET>;
@@ -442,6 +502,7 @@
                        fec1: ethernet@400d1000 {
                                compatible = "fsl,mvf600-fec";
                                reg = <0x400d1000 0x1000>;
+                                interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_ENET1>,
                                        <&clks VF610_CLK_ENET1>,
                                        <&clks VF610_CLK_ENET>;
@@ -452,6 +513,7 @@
                        can1: flexcan@400d4000 {
                                compatible = "fsl,vf610-flexcan";
                                reg = <0x400d4000 0x4000>;
+                                interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clks VF610_CLK_FLEXCAN1>,
                                         <&clks VF610_CLK_FLEXCAN1>;
                                clock-names = "ipg", "per";
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 771ecfe96c14..0f04e30b726d 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -66,6 +66,7 @@ unsigned int imx_get_soc_revision(void);
 void imx_init_revision_from_anatop(void);
 struct device *imx_soc_device_init(void);
 void imx6_enable_rbc(bool enable);
+void imx_gpc_check_dt(void);
 void imx_gpc_set_arm_power_in_lpm(bool power_off);
 void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
 void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
@@ -101,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
 static inline void imx_smp_prepare(void) {}
 #endif
 void imx_src_init(void);
-void imx_gpc_init(void);
 void imx_gpc_pre_suspend(bool arm_power_off);
 void imx_gpc_post_resume(void);
 void imx_gpc_mask_all(void);
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 029f59ce2712..4d60005e9277 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -36,6 +36,7 @@
 #define GPC_PGC_SW_SHIFT        0x0
 #define IMR_NUM                 4
+#define GPC_MAX_IRQS            (IMR_NUM * 32)
 #define GPU_VPU_PUP_REQ         BIT(1)
 #define GPU_VPU_PDN_REQ         BIT(0)
@@ -99,17 +100,17 @@ void imx_gpc_post_resume(void)
 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
 {
-        unsigned int idx = d->hwirq / 32 - 1;
+        unsigned int idx = d->hwirq / 32;
        u32 mask;
-        /* Sanity check for SPI irq */
-        if (d->hwirq < 32)
-                return -EINVAL;
        mask = 1 << d->hwirq % 32;
        gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
                                  gpc_wake_irqs[idx] & ~mask;
+        /*
+         * Do *not* call into the parent, as the GIC doesn't have any
+         * wake-up facility...
+         */
        return 0;
 }
@@ -139,7 +140,7 @@ void imx_gpc_hwirq_unmask(unsigned int hwirq)
        void __iomem *reg;
        u32 val;
-        reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+        reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
        val = readl_relaxed(reg);
        val &= ~(1 << hwirq % 32);
        writel_relaxed(val, reg);
@@ -150,7 +151,7 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
        void __iomem *reg;
        u32 val;
-        reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
+        reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
        val = readl_relaxed(reg);
        val |= 1 << (hwirq % 32);
        writel_relaxed(val, reg);
@@ -158,39 +159,130 @@ void imx_gpc_hwirq_mask(unsigned int hwirq)
 static void imx_gpc_irq_unmask(struct irq_data *d)
 {
-        /* Sanity check for SPI irq */
-        if (d->hwirq < 32)
-                return;
        imx_gpc_hwirq_unmask(d->hwirq);
+        irq_chip_unmask_parent(d);
 }
 static void imx_gpc_irq_mask(struct irq_data *d)
 {
-        /* Sanity check for SPI irq */
-        if (d->hwirq < 32)
-                return;
        imx_gpc_hwirq_mask(d->hwirq);
+        irq_chip_mask_parent(d);
+}
+static struct irq_chip imx_gpc_chip = {
+        .name                   = "GPC",
+        .irq_eoi                = irq_chip_eoi_parent,
+        .irq_mask               = imx_gpc_irq_mask,
+        .irq_unmask             = imx_gpc_irq_unmask,
+        .irq_retrigger          = irq_chip_retrigger_hierarchy,
+        .irq_set_wake           = imx_gpc_irq_set_wake,
+#ifdef CONFIG_SMP
+        .irq_set_affinity       = irq_chip_set_affinity_parent,
+#endif
+};
+static int imx_gpc_domain_xlate(struct irq_domain *domain,
+                                struct device_node *controller,
+                                const u32 *intspec,
+                                unsigned int intsize,
+                                unsigned long *out_hwirq,
+                                unsigned int *out_type)
+{
+        if (domain->of_node != controller)
+                return -EINVAL; /* Shouldn't happen, really... */
+        if (intsize != 3)
+                return -EINVAL; /* Not GIC compliant */
+        if (intspec[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+        *out_hwirq = intspec[1];
+        *out_type = intspec[2];
+        return 0;
 }
-void __init imx_gpc_init(void)
+static int imx_gpc_domain_alloc(struct irq_domain *domain,
+                                  unsigned int irq,
+                                  unsigned int nr_irqs, void *data)
 {
-        struct device_node *np;
+        struct of_phandle_args *args = data;
+        struct of_phandle_args parent_args;
+        irq_hw_number_t hwirq;
        int i;
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
+        if (args->args_count != 3)
-        gpc_base = of_iomap(np, 0);
+                return -EINVAL; /* Not GIC compliant */
-        WARN_ON(!gpc_base);
+        if (args->args[0] != 0)
+                return -EINVAL; /* No PPI should point to this domain */
+        hwirq = args->args[1];
+        if (hwirq >= GPC_MAX_IRQS)
+                return -EINVAL; /* Can't deal with this */
+        for (i = 0; i < nr_irqs; i++)
+                irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i,
+                                              &imx_gpc_chip, NULL);
+        parent_args = *args;
+        parent_args.np = domain->parent->of_node;
+        return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args);
+}
+static struct irq_domain_ops imx_gpc_domain_ops = {
+        .xlate  = imx_gpc_domain_xlate,
+        .alloc  = imx_gpc_domain_alloc,
+        .free   = irq_domain_free_irqs_common,
+};
+static int __init imx_gpc_init(struct device_node *node,
+                               struct device_node *parent)
+{
+        struct irq_domain *parent_domain, *domain;
+        int i;
+        if (!parent) {
+                pr_err("%s: no parent, giving up\n", node->full_name);
+                return -ENODEV;
+        }
+        parent_domain = irq_find_host(parent);
+        if (!parent_domain) {
+                pr_err("%s: unable to obtain parent domain\n", node->full_name);
+                return -ENXIO;
+        }
+        gpc_base = of_iomap(node, 0);
+        if (WARN_ON(!gpc_base))
+                return -ENOMEM;
+        domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS,
+                                          node, &imx_gpc_domain_ops,
+                                          NULL);
+        if (!domain) {
+                iounmap(gpc_base);
+                return -ENOMEM;
+        }
        /* Initially mask all interrupts */
        for (i = 0; i < IMR_NUM; i++)
                writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
-        /* Register GPC as the secondary interrupt controller behind GIC */
+        return 0;
-        gic_arch_extn.irq_mask = imx_gpc_irq_mask;
+}
-        gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
-        gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
+/*
+ * We cannot use the IRQCHIP_DECLARE macro that lives in
+ * drivers/irqchip, so we're forced to roll our own. Not very nice.
+ */
+OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
+void __init imx_gpc_check_dt(void)
+{
+        struct device_node *np;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
+        if (WARN_ON(!np ||
+                    !of_find_property(np, "interrupt-controller", NULL)))
+                pr_warn("Outdated DT detected, system is about to crash!!!\n");
 }
 #ifdef CONFIG_PM_GENERIC_DOMAINS
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9de3412af406..3ab61549ce0f 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -388,10 +388,10 @@ static void __init imx6q_map_io(void)
 static void __init imx6q_init_irq(void)
 {
+        imx_gpc_check_dt();
        imx_init_revision_from_anatop();
        imx_init_l2cache();
        imx_src_init();
-        imx_gpc_init();
        irqchip_init();
 }
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 24bfaaf944c8..12a1b098fc6a 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -61,10 +61,10 @@ static void __init imx6sl_init_machine(void)
 static void __init imx6sl_init_irq(void)
 {
+        imx_gpc_check_dt();
        imx_init_revision_from_anatop();
        imx_init_l2cache();
        imx_src_init();
-        imx_gpc_init();
        irqchip_init();
 }
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
index 66988eb6a3a4..f17b7004c24b 100644
--- a/arch/arm/mach-imx/mach-imx6sx.c
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -81,10 +81,10 @@ static void __init imx6sx_init_machine(void)
 static void __init imx6sx_init_irq(void)
 {
+        imx_gpc_check_dt();
        imx_init_revision_from_anatop();
        imx_init_l2cache();
        imx_src_init();
-        imx_gpc_init();
        irqchip_init();
 }
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 46fd695203c7..6a7c6fc780cc 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -310,10 +310,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
         *    Low-Power mode.
         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
         *    is set (set bits 0-1 of CCM_CLPCR).
+         *
+         * Note that IRQ #32 is GIC SPI #0.
         */
-        imx_gpc_hwirq_unmask(32);
+        imx_gpc_hwirq_unmask(0);
        writel_relaxed(val, ccm_base + CLPCR);
-        imx_gpc_hwirq_mask(32);
+        imx_gpc_hwirq_mask(0);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 3e4b4ae8c75b..6468f15f060c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -81,6 +81,7 @@ config ARCH_OMAP2PLUS
        select GENERIC_IRQ_CHIP
        select MACH_OMAP_GENERIC
        select MEMORY
+        select MFD_SYSCON
        select OMAP_DM_TIMER
        select OMAP_GPMC
        select PINCTRL
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 6124db5c37ae..a699d7169307 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,6 +23,9 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
+#include <linux/regmap.h>
+#include <linux/of_address.h>
+#include <linux/bootmem.h>
 #include <asm/cpu.h>
 #include <trace/events/power.h>
@@ -72,30 +75,110 @@ struct ti_clk_features ti_clk_features;
 static bool clkdm_control = true;
 static LIST_HEAD(clk_hw_omap_clocks);
-void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+struct clk_iomap {
+        struct regmap *regmap;
+        void __iomem *mem;
+};
+static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
+static void clk_memmap_writel(u32 val, void __iomem *reg)
+{
+        struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+        struct clk_iomap *io = clk_memmaps[r->index];
+        if (io->regmap)
+                regmap_write(io->regmap, r->offset, val);
+        else
+                writel_relaxed(val, io->mem + r->offset);
+}
+static u32 clk_memmap_readl(void __iomem *reg)
+{
+        u32 val;
+        struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+        struct clk_iomap *io = clk_memmaps[r->index];
+        if (io->regmap)
+                regmap_read(io->regmap, r->offset, &val);
+        else
+                val = readl_relaxed(io->mem + r->offset);
+        return val;
+}
 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
 {
-        if (clk->flags & MEMMAP_ADDRESSING) {
+        if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
-                struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
-                writel_relaxed(val, clk_memmaps[r->index] + r->offset);
-        } else {
                writel_relaxed(val, reg);
-        }
+        else
+                clk_memmap_writel(val, reg);
 }
 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
 {
-        u32 val;
+        if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
+                return readl_relaxed(reg);
+        else
+                return clk_memmap_readl(reg);
+}
-        if (clk->flags & MEMMAP_ADDRESSING) {
+static struct ti_clk_ll_ops omap_clk_ll_ops = {
-                struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+        .clk_readl = clk_memmap_readl,
-                val = readl_relaxed(clk_memmaps[r->index] + r->offset);
+        .clk_writel = clk_memmap_writel,
-        } else {
+};
-                val = readl_relaxed(reg);
-        }
-        return val;
+/**
+ * omap2_clk_provider_init - initialize a clock provider
+ * @match_table: DT device table to match for devices to init
+ * @np: device node pointer for the this clock provider
+ * @index: index for the clock provider
+ + @syscon: syscon regmap pointer
+ * @mem: iomem pointer for the clock provider memory area, only used if
+ *       syscon is not provided
+ *
+ * Initializes a clock provider module (CM/PRM etc.), registering
+ * the memory mapping at specified index and initializing the
+ * low level driver infrastructure. Returns 0 in success.
+ */
+int __init omap2_clk_provider_init(struct device_node *np, int index,
+                                   struct regmap *syscon, void __iomem *mem)
+{
+        struct clk_iomap *io;
+        ti_clk_ll_ops = &omap_clk_ll_ops;
+        io = kzalloc(sizeof(*io), GFP_KERNEL);
+        io->regmap = syscon;
+        io->mem = mem;
+        clk_memmaps[index] = io;
+        ti_dt_clk_init_provider(np, index);
+        return 0;
+}
+/**
+ * omap2_clk_legacy_provider_init - initialize a legacy clock provider
+ * @index: index for the clock provider
+ * @mem: iomem pointer for the clock provider memory area
+ *
+ * Initializes a legacy clock provider memory mapping.
+ */
+void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
+{
+        struct clk_iomap *io;
+        ti_clk_ll_ops = &omap_clk_ll_ops;
+        io = memblock_virt_alloc(sizeof(*io), 0);
+        io->mem = mem;
+        clk_memmaps[index] = io;
 }
 /*
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a56742f96000..652ed0ab86ec 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -271,10 +271,14 @@ extern const struct clksel_rate div_1_3_rates[];
 extern const struct clksel_rate div_1_4_rates[];
 extern const struct clksel_rate div31_1to31_rates[];
-extern void __iomem *clk_memmaps[];
 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
+struct regmap;
+int __init omap2_clk_provider_init(struct device_node *np, int index,
+                                   struct regmap *syscon, void __iomem *mem);
+void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
 void __init ti_clk_init_features(void);
 #endif
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 6222e87a79b6..1fe3e6b833d2 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -70,6 +70,8 @@ int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
 extern int cm_register(struct cm_ll_data *cld);
 extern int cm_unregister(struct cm_ll_data *cld);
+int omap_cm_init(void);
+int omap2_cm_base_init(void);
 # endif
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index ef62ac9dcd05..3e5fd3587eb1 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -393,7 +393,7 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
        .wait_module_ready      = &omap2xxx_cm_wait_module_ready,
 };
-int __init omap2xxx_cm_init(void)
+int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
 {
        return cm_register(&omap2xxx_cm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/cm2xxx.h b/arch/arm/mach-omap2/cm2xxx.h
index 83b6c597b0e1..7b8c79c0ce27 100644
--- a/arch/arm/mach-omap2/cm2xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx.h
@@ -63,7 +63,7 @@ extern u32 omap2xxx_cm_get_core_pll_config(void);
 extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
                                         u32 mdm);
-extern int __init omap2xxx_cm_init(void);
+int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
 #endif
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index cc5aac784278..7b181f929525 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -352,7 +352,7 @@ static struct cm_ll_data am33xx_cm_ll_data = {
        .module_disable         = &am33xx_cm_module_disable,
 };
-int __init am33xx_cm_init(void)
+int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
 {
        return cm_register(&am33xx_cm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 046b4b2bc9d9..a91f7d282455 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -19,6 +19,7 @@
 #include "cm.h"
 #include "cm-regbits-33xx.h"
+#include "prcm-common.h"
 /* CM base address */
 #define AM33XX_CM_BASE          0x44e00000
@@ -374,6 +375,6 @@
 #ifndef __ASSEMBLER__
-int am33xx_cm_init(void);
+int am33xx_cm_init(const struct omap_prcm_init_data *data);
 #endif /* ASSEMBLER */
 #endif
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index ebead8f035f9..187fa4386718 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -671,8 +671,9 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
        .wait_module_ready      = &omap3xxx_cm_wait_module_ready,
 };
-int __init omap3xxx_cm_init(void)
+int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
 {
+        omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
        return cm_register(&omap3xxx_cm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 734a8581c0c4..bc444e2080a1 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -72,7 +72,7 @@ extern void omap3_cm_save_context(void);
 extern void omap3_cm_restore_context(void);
 extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
-extern int __init omap3xxx_cm_init(void);
+int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data);
 #endif
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 728d06a4af19..309a4c913448 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -23,7 +23,6 @@
 #define OMAP4_CM_CLKSTCTRL                              0x0000
 #define OMAP4_CM_STATICDEP                              0x0004
-void omap_cm_base_init(void);
+int omap4_cm_init(const struct omap_prcm_init_data *data);
-int omap4_cm_init(void);
 #endif
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 8fe02fcedc48..23e8bcec34e3 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -15,10 +15,14 @@
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/bug.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include "cm2xxx.h"
 #include "cm3xxx.h"
+#include "cm33xx.h"
 #include "cm44xx.h"
+#include "clock.h"
 /*
 * cm_ll_data: function pointers to SoC-specific implementations of
@@ -33,6 +37,9 @@ void __iomem *cm_base;
 /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
 void __iomem *cm2_base;
+#define CM_NO_CLOCKS            0x1
+#define CM_SINGLE_INSTANCE      0x2
 /**
 * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
 * @cm: CM base virtual address
@@ -212,3 +219,152 @@ int cm_unregister(struct cm_ll_data *cld)
        return 0;
 }
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+        defined(CONFIG_SOC_DRA7XX)
+static struct omap_prcm_init_data cm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .init = omap4_cm_init,
+};
+static struct omap_prcm_init_data cm2_data __initdata = {
+        .index = TI_CLKM_CM2,
+        .init = omap4_cm_init,
+};
+#endif
+#ifdef CONFIG_ARCH_OMAP2
+static struct omap_prcm_init_data omap2_prcm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .init = omap2xxx_cm_init,
+        .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
+};
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+static struct omap_prcm_init_data omap3_cm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .init = omap3xxx_cm_init,
+        .flags = CM_SINGLE_INSTANCE,
+        /*
+         * IVA2 offset is a negative value, must offset the cm_base address
+         * by this to get it to positive side on the iomap
+         */
+        .offset = -OMAP3430_IVA2_MOD,
+};
+#endif
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
+static struct omap_prcm_init_data am3_prcm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
+        .init = am33xx_cm_init,
+};
+#endif
+#ifdef CONFIG_SOC_AM43XX
+static struct omap_prcm_init_data am4_prcm_data __initdata = {
+        .index = TI_CLKM_CM,
+        .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
+        .init = omap4_cm_init,
+};
+#endif
+static const struct of_device_id omap_cm_dt_match_table[] __initconst = {
+#ifdef CONFIG_ARCH_OMAP2
+        { .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+        { .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+        { .compatible = "ti,omap4-cm1", .data = &cm_data },
+        { .compatible = "ti,omap4-cm2", .data = &cm2_data },
+#endif
+#ifdef CONFIG_SOC_OMAP5
+        { .compatible = "ti,omap5-cm-core-aon", .data = &cm_data },
+        { .compatible = "ti,omap5-cm-core", .data = &cm2_data },
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+        { .compatible = "ti,dra7-cm-core-aon", .data = &cm_data },
+        { .compatible = "ti,dra7-cm-core", .data = &cm2_data },
+#endif
+#ifdef CONFIG_SOC_AM33XX
+        { .compatible = "ti,am3-prcm", .data = &am3_prcm_data },
+#endif
+#ifdef CONFIG_SOC_AM43XX
+        { .compatible = "ti,am4-prcm", .data = &am4_prcm_data },
+#endif
+#ifdef CONFIG_SOC_TI81XX
+        { .compatible = "ti,dm814-prcm", .data = &am3_prcm_data },
+        { .compatible = "ti,dm816-prcm", .data = &am3_prcm_data },
+#endif
+        { }
+};
+/**
+ * omap2_cm_base_init - initialize iomappings for the CM drivers
+ *
+ * Detects and initializes the iomappings for the CM driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_cm_base_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        struct omap_prcm_init_data *data;
+        void __iomem *mem;
+        for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
+                data = (struct omap_prcm_init_data *)match->data;
+                mem = of_iomap(np, 0);
+                if (!mem)
+                        return -ENOMEM;
+                if (data->index == TI_CLKM_CM)
+                        cm_base = mem + data->offset;
+                if (data->index == TI_CLKM_CM2)
+                        cm2_base = mem + data->offset;
+                data->mem = mem;
+                data->np = np;
+                if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
+                                   (cm_base && cm2_base)))
+                        data->init(data);
+        }
+        return 0;
+}
+/**
+ * omap_cm_init - low level init for the CM drivers
+ *
+ * Initializes the low level clock infrastructure for CM drivers.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_cm_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        const struct omap_prcm_init_data *data;
+        int ret;
+        for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
+                data = match->data;
+                if (data->flags & CM_NO_CLOCKS)
+                        continue;
+                ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
+                if (ret)
+                        return ret;
+        }
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 95a8cff66aff..2c0e07ed6b99 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -63,7 +63,7 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
 * Populates the base addresses of the _cm_bases
 * array used for read/write of cm module registers.
 */
-void omap_cm_base_init(void)
+static void omap_cm_base_init(void)
 {
        _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
        _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
@@ -514,8 +514,10 @@ static struct cm_ll_data omap4xxx_cm_ll_data = {
        .module_disable         = &omap4_cminst_module_disable,
 };
-int __init omap4_cm_init(void)
+int __init omap4_cm_init(const struct omap_prcm_init_data *data)
 {
+        omap_cm_base_init();
        return cm_register(&omap4xxx_cm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index da041b4ab29c..af95a624fe71 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -14,6 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
 #include "soc.h"
 #include "iomap.h"
@@ -25,13 +28,15 @@
 #include "sdrc.h"
 #include "pm.h"
 #include "control.h"
+#include "clock.h"
 /* Used by omap3_ctrl_save_padconf() */
 #define START_PADCONF_SAVE              0x2
 #define PADCONF_SAVE_DONE               0x1
 static void __iomem *omap2_ctrl_base;
-static void __iomem *omap4_ctrl_pad_base;
+static s16 omap2_ctrl_offset;
+static struct regmap *omap2_ctrl_syscon;
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 struct omap3_scratchpad {
@@ -133,66 +138,79 @@ struct omap3_control_regs {
 static struct omap3_control_regs control_context;
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
-#define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
+void __init omap2_set_globals_control(void __iomem *ctrl)
-#define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
-void __init omap2_set_globals_control(void __iomem *ctrl,
-                                      void __iomem *ctrl_pad)
 {
        omap2_ctrl_base = ctrl;
-        omap4_ctrl_pad_base = ctrl_pad;
-}
-void __iomem *omap_ctrl_base_get(void)
-{
-        return omap2_ctrl_base;
 }
 u8 omap_ctrl_readb(u16 offset)
 {
-        return readb_relaxed(OMAP_CTRL_REGADDR(offset));
+        u32 val;
+        u8 byte_offset = offset & 0x3;
+        val = omap_ctrl_readl(offset);
+        return (val >> (byte_offset * 8)) & 0xff;
 }
 u16 omap_ctrl_readw(u16 offset)
 {
-        return readw_relaxed(OMAP_CTRL_REGADDR(offset));
+        u32 val;
+        u16 byte_offset = offset & 0x2;
+        val = omap_ctrl_readl(offset);
+        return (val >> (byte_offset * 8)) & 0xffff;
 }
 u32 omap_ctrl_readl(u16 offset)
 {
-        return readl_relaxed(OMAP_CTRL_REGADDR(offset));
+        u32 val;
+        offset &= 0xfffc;
+        if (!omap2_ctrl_syscon)
+                val = readl_relaxed(omap2_ctrl_base + offset);
+        else
+                regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
+                            &val);
+        return val;
 }
 void omap_ctrl_writeb(u8 val, u16 offset)
 {
-        writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
+        u32 tmp;
+        u8 byte_offset = offset & 0x3;
+        tmp = omap_ctrl_readl(offset);
+        tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
+        tmp |= val << (byte_offset * 8);
+        omap_ctrl_writel(tmp, offset);
 }
 void omap_ctrl_writew(u16 val, u16 offset)
 {
-        writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
+        u32 tmp;
-}
+        u8 byte_offset = offset & 0x2;
-void omap_ctrl_writel(u32 val, u16 offset)
+        tmp = omap_ctrl_readl(offset);
-{
-        writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
-}
-/*
+        tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
- * On OMAP4 control pad are not addressable from control
+        tmp |= val << (byte_offset * 8);
- * core base. So the common omap_ctrl_read/write APIs breaks
- * Hence export separate APIs to manage the omap4 pad control
- * registers. This APIs will work only for OMAP4
- */
-u32 omap4_ctrl_pad_readl(u16 offset)
+        omap_ctrl_writel(tmp, offset);
-{
-        return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
 }
-void omap4_ctrl_pad_writel(u32 val, u16 offset)
+void omap_ctrl_writel(u32 val, u16 offset)
 {
-        writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
+        offset &= 0xfffc;
+        if (!omap2_ctrl_syscon)
+                writel_relaxed(val, omap2_ctrl_base + offset);
+        else
+                regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
+                             val);
 }
 #ifdef CONFIG_ARCH_OMAP3
@@ -611,3 +629,120 @@ void __init omap3_ctrl_init(void)
        omap3_ctrl_setup_d2d_padconf();
 }
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
+struct control_init_data {
+        int index;
+        s16 offset;
+};
+static struct control_init_data ctrl_data = {
+        .index = TI_CLKM_CTRL,
+};
+static const struct control_init_data omap2_ctrl_data = {
+        .index = TI_CLKM_CTRL,
+        .offset = -OMAP2_CONTROL_GENERAL,
+};
+static const struct of_device_id omap_scrm_dt_match_table[] = {
+        { .compatible = "ti,am3-scm", .data = &ctrl_data },
+        { .compatible = "ti,am4-scm", .data = &ctrl_data },
+        { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
+        { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
+        { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
+        { .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
+        { .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
+        { .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
+        { }
+};
+/**
+ * omap2_control_base_init - initialize iomappings for the control driver
+ *
+ * Detects and initializes the iomappings for the control driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_control_base_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        struct control_init_data *data;
+        for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
+                data = (struct control_init_data *)match->data;
+                omap2_ctrl_base = of_iomap(np, 0);
+                if (!omap2_ctrl_base)
+                        return -ENOMEM;
+                omap2_ctrl_offset = data->offset;
+        }
+        return 0;
+}
+/**
+ * omap_control_init - low level init for the control driver
+ *
+ * Initializes the low level clock infrastructure for control driver.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_control_init(void)
+{
+        struct device_node *np, *scm_conf;
+        const struct of_device_id *match;
+        const struct omap_prcm_init_data *data;
+        int ret;
+        struct regmap *syscon;
+        for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
+                data = match->data;
+                /*
+                 * Check if we have scm_conf node, if yes, use this to
+                 * access clock registers.
+                 */
+                scm_conf = of_get_child_by_name(np, "scm_conf");
+                if (scm_conf) {
+                        syscon = syscon_node_to_regmap(scm_conf);
+                        if (IS_ERR(syscon))
+                                return PTR_ERR(syscon);
+                        omap2_ctrl_syscon = syscon;
+                        if (of_get_child_by_name(scm_conf, "clocks")) {
+                                ret = omap2_clk_provider_init(scm_conf,
+                                                              data->index,
+                                                              syscon, NULL);
+                                if (ret)
+                                        return ret;
+                        }
+                        iounmap(omap2_ctrl_base);
+                        omap2_ctrl_base = NULL;
+                } else {
+                        /* No scm_conf found, direct access */
+                        ret = omap2_clk_provider_init(np, data->index, NULL,
+                                                      omap2_ctrl_base);
+                        if (ret)
+                                return ret;
+                }
+        }
+        return 0;
+}
+/**
+ * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
+ *
+ * Legacy iomap init for clock provider. Needed only by legacy boot mode,
+ * where the base addresses are not parsed from DT, but still required
+ * by the clock driver to be setup properly.
+ */
+void __init omap3_control_legacy_iomap_init(void)
+{
+        omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
+}
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b8a487181210..80d2b7d8e36e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -440,15 +440,12 @@
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_ARCH_OMAP2PLUS
-extern void __iomem *omap_ctrl_base_get(void);
 extern u8 omap_ctrl_readb(u16 offset);
 extern u16 omap_ctrl_readw(u16 offset);
 extern u32 omap_ctrl_readl(u16 offset);
-extern u32 omap4_ctrl_pad_readl(u16 offset);
 extern void omap_ctrl_writeb(u8 val, u16 offset);
 extern void omap_ctrl_writew(u16 val, u16 offset);
 extern void omap_ctrl_writel(u32 val, u16 offset);
-extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
 extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
@@ -464,10 +461,11 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
 void omap3_ctrl_init(void);
-extern void omap2_set_globals_control(void __iomem *ctrl,
+int omap2_control_base_init(void);
-                                      void __iomem *ctrl_pad);
+int omap_control_init(void);
+void omap2_set_globals_control(void __iomem *ctrl);
+void __init omap3_control_legacy_iomap_init(void);
 #else
-#define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
 #define omap_ctrl_readw(x)              0
 #define omap_ctrl_readl(x)              0
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 7a050f9c37ff..f492ae147c6a 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -26,6 +26,8 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/slab.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 #include <video/omapdss.h>
 #include "omap_hwmod.h"
@@ -104,6 +106,10 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
        { "dss_hdmi", "omapdss_hdmi", -1 },
 };
+#define OMAP4_DSIPHY_SYSCON_OFFSET              0x78
+static struct regmap *omap4_dsi_mux_syscon;
 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 {
        u32 enable_mask, enable_shift;
@@ -124,7 +130,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
                return -ENODEV;
        }
-        reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
+        regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
        reg &= ~enable_mask;
        reg &= ~pipd_mask;
@@ -132,7 +138,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
        reg |= (lanes << enable_shift) & enable_mask;
        reg |= (lanes << pipd_shift) & pipd_mask;
-        omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
+        regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
        return 0;
 }
@@ -665,5 +671,10 @@ int __init omapdss_init_of(void)
                return r;
        }
+        /* add DSI info for omap4 */
+        node = of_find_node_by_name(NULL, "omap4_padconf_global");
+        if (node)
+                omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
        return 0;
 }
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 25f1beea453e..e3f713ffb06b 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -52,7 +52,10 @@ EXPORT_SYMBOL(omap_rev);
 int omap_type(void)
 {
-        u32 val = 0;
+        static u32 val = OMAP2_DEVICETYPE_MASK;
+        if (val < OMAP2_DEVICETYPE_MASK)
+                return val;
        if (cpu_is_omap24xx()) {
                val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 1eeff6be260d..820dde8b5b04 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -382,13 +382,9 @@ void __init omap2420_init_early(void)
        omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
        omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
                               OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
        omap2xxx_check_revision();
-        omap2xxx_prm_init();
+        omap2_prcm_base_init();
-        omap2xxx_cm_init();
        omap2xxx_voltagedomains_init();
        omap242x_powerdomains_init();
        omap242x_clockdomains_init();
@@ -412,13 +408,9 @@ void __init omap2430_init_early(void)
        omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
        omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
                               OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
        omap2xxx_check_revision();
-        omap2xxx_prm_init();
+        omap2_prcm_base_init();
-        omap2xxx_cm_init();
        omap2xxx_voltagedomains_init();
        omap243x_powerdomains_init();
        omap243x_clockdomains_init();
@@ -446,21 +438,30 @@ void __init omap3_init_early(void)
        omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
        omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
                               OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
+        /* XXX: remove these once OMAP3 is DT only */
-                                  NULL);
+        if (!of_have_populated_dt()) {
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
+                omap2_set_globals_control(
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
+                        OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
+                omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
+                omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
+                                     NULL);
+        }
+        omap2_control_base_init();
        omap3xxx_check_revision();
        omap3xxx_check_features();
-        omap3xxx_prm_init();
+        omap2_prcm_base_init();
-        omap3xxx_cm_init();
+        /* XXX: remove these once OMAP3 is DT only */
+        if (!of_have_populated_dt()) {
+                omap3xxx_prm_init(NULL);
+                omap3xxx_cm_init(NULL);
+        }
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
        omap3xxx_clockdomains_init();
        omap3xxx_hwmod_init();
        omap_hwmod_init_postsetup();
        if (!of_have_populated_dt()) {
-                omap3_prcm_legacy_iomaps_init();
+                omap3_control_legacy_iomap_init();
                if (soc_is_am35xx())
                        omap_clk_soc_init = am35xx_clk_legacy_init;
                else if (cpu_is_omap3630())
@@ -547,14 +548,10 @@ void __init ti814x_init_early(void)
 {
        omap2_set_globals_tap(TI814X_CLASS,
                              OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
        omap3xxx_check_revision();
        ti81xx_check_features();
-        am33xx_prm_init();
+        omap2_prcm_base_init();
-        am33xx_cm_init();
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
        ti81xx_clockdomains_init();
@@ -568,14 +565,10 @@ void __init ti816x_init_early(void)
 {
        omap2_set_globals_tap(TI816X_CLASS,
                              OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
        omap3xxx_check_revision();
        ti81xx_check_features();
-        am33xx_prm_init();
+        omap2_prcm_base_init();
-        am33xx_cm_init();
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
        ti81xx_clockdomains_init();
@@ -591,14 +584,10 @@ void __init am33xx_init_early(void)
 {
        omap2_set_globals_tap(AM335X_CLASS,
                              AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
-        omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
-        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
        omap3xxx_check_revision();
        am33xx_check_features();
-        am33xx_prm_init();
+        omap2_prcm_base_init();
-        am33xx_cm_init();
        am33xx_powerdomains_init();
        am33xx_clockdomains_init();
        am33xx_hwmod_init();
@@ -617,16 +606,10 @@ void __init am43xx_init_early(void)
 {
        omap2_set_globals_tap(AM335X_CLASS,
                              AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
-        omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+        omap2_control_base_init();
-                                  NULL);
-        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
-        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
-        omap_prm_base_init();
-        omap_cm_base_init();
        omap3xxx_check_revision();
        am33xx_check_features();
-        omap44xx_prm_init();
+        omap2_prcm_base_init();
-        omap4_cm_init();
        am43xx_powerdomains_init();
        am43xx_clockdomains_init();
        am43xx_hwmod_init();
@@ -646,19 +629,12 @@ void __init omap4430_init_early(void)
 {
        omap2_set_globals_tap(OMAP443X_CLASS,
                              OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
-                                  OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
-                             OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
        omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
-        omap_prm_base_init();
+        omap2_control_base_init();
-        omap_cm_base_init();
        omap4xxx_check_revision();
        omap4xxx_check_features();
-        omap4_cm_init();
+        omap2_prcm_base_init();
        omap4_pm_init_early();
-        omap44xx_prm_init();
        omap44xx_voltagedomains_init();
        omap44xx_powerdomains_init();
        omap44xx_clockdomains_init();
@@ -681,18 +657,11 @@ void __init omap5_init_early(void)
 {
        omap2_set_globals_tap(OMAP54XX_CLASS,
                              OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
-                                  OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
-                             OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
        omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+        omap2_control_base_init();
        omap4_pm_init_early();
-        omap_prm_base_init();
+        omap2_prcm_base_init();
-        omap_cm_base_init();
-        omap44xx_prm_init();
        omap5xxx_check_revision();
-        omap4_cm_init();
        omap54xx_voltagedomains_init();
        omap54xx_powerdomains_init();
        omap54xx_clockdomains_init();
@@ -713,18 +682,11 @@ void __init omap5_init_late(void)
 void __init dra7xx_init_early(void)
 {
        omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
-        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
-                                  OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
-        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
-        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
-                             OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
        omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+        omap2_control_base_init();
        omap4_pm_init_early();
-        omap_prm_base_init();
+        omap2_prcm_base_init();
-        omap_cm_base_init();
-        omap44xx_prm_init();
        dra7xxx_check_revision();
-        omap4_cm_init();
        dra7xx_powerdomains_init();
        dra7xx_clockdomains_init();
        dra7xx_hwmod_init();
@@ -762,7 +724,11 @@ int __init omap_clk_init(void)
        ti_clk_init_features();
        if (of_have_populated_dt()) {
-                ret = of_prcm_init();
+                ret = omap_control_init();
+                if (ret)
+                        return ret;
+                ret = omap_prcm_init();
                if (ret)
                        return ret;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index fe01c5a03aa2..b1aad7e1426c 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
        /* Clear old wake-up events */
        /* REVISIT: These write to reserved bits? */
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
-        omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
+        omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
        pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
        pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
@@ -104,18 +104,16 @@ no_sleep:
        clk_enable(osc_ck);
        /* clear CORE wake-up events */
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
-        omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+        omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
        /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
-        omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
+        omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
        /* MPU domain wake events */
-        omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
+        omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
-                                    0x1);
-        omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
+        omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
-                                    0x20);
        pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
        pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
@@ -143,9 +141,9 @@ static void omap2_enter_mpu_retention(void)
         * it is in retention mode. */
        if (omap2_allow_mpu_retention()) {
                /* REVISIT: These write to reserved bits? */
-                omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
+                omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
-                omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
+                omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
-                omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
+                omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
                /* Try to enter MPU retention */
                pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 88721df6001d..87b98bf92366 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -137,9 +137,8 @@ static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 {
        int c;
-        c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
+        c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
-                                        ~(OMAP3430_ST_IO_MASK |
+                                    OMAP3430_ST_IO_CHAIN_MASK);
-                                          OMAP3430_ST_IO_CHAIN_MASK));
        return c ? IRQ_HANDLED : IRQ_NONE;
 }
@@ -153,14 +152,13 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
         * these are handled in a separate handler to avoid acking
         * IO events before parsing in mux code
         */
-        c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
+        c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
-                                        OMAP3430_ST_IO_MASK |
+                                                   OMAP3430_ST_IO_CHAIN_MASK));
-                                        OMAP3430_ST_IO_CHAIN_MASK);
+        c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
-        c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0);
+        c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
-        c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0);
+                c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
-                c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
+                c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
        }
        return c ? IRQ_HANDLED : IRQ_NONE;
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6163d66102a3..6ae0b3a1781e 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -518,6 +518,26 @@ struct omap_prcm_irq_setup {
        .priority = _priority                           \
        }
+/**
+ * struct omap_prcm_init_data - PRCM driver init data
+ * @index: clock memory mapping index to be used
+ * @mem: IO mem pointer for this module
+ * @offset: module base address offset from the IO base
+ * @flags: PRCM module init flags
+ * @device_inst_offset: device instance offset within the module address space
+ * @init: low level PRCM init function for this module
+ * @np: device node for this PRCM module
+ */
+struct omap_prcm_init_data {
+        int index;
+        void __iomem *mem;
+        s16 offset;
+        u16 flags;
+        s32 device_inst_offset;
+        int (*init)(const struct omap_prcm_init_data *data);
+        struct device_node *np;
+};
 extern void omap_prcm_irq_cleanup(void);
 extern int omap_prcm_register_chain_handler(
        struct omap_prcm_irq_setup *irq_setup);
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index b9061a6a2db8..233bc84fbc0e 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -19,8 +19,9 @@
 extern void __iomem *prm_base;
 extern u16 prm_features;
 extern void omap2_set_globals_prm(void __iomem *prm);
-int of_prcm_init(void);
+int omap_prcm_init(void);
-void omap3_prcm_legacy_iomaps_init(void);
+int omap2_prm_base_init(void);
+int omap2_prcm_base_init(void);
 # endif
 /*
@@ -28,9 +29,11 @@ void omap3_prcm_legacy_iomaps_init(void);
 *
 * PRM_HAS_IO_WAKEUP: has IO wakeup capability
 * PRM_HAS_VOLTAGE: has voltage domains
+ * PRM_IRQ_DEFAULT: use default irq number for PRM irq
 */
-#define PRM_HAS_IO_WAKEUP       (1 << 0)
+#define PRM_HAS_IO_WAKEUP       BIT(0)
-#define PRM_HAS_VOLTAGE         (1 << 1)
+#define PRM_HAS_VOLTAGE         BIT(1)
+#define PRM_IRQ_DEFAULT         BIT(2)
 /*
 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@@ -146,6 +149,9 @@ struct prm_ll_data {
        int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
                                     u16 offset);
        void (*reset_system)(void);
+        int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
+        u32 (*vp_check_txdone)(u8 vp_id);
+        void (*vp_clear_txdone)(u8 vp_id);
 };
 extern int prm_register(struct prm_ll_data *pld);
@@ -161,6 +167,19 @@ extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
 void omap_prm_reset_system(void);
 void omap_prm_reconfigure_io_chain(void);
+int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
+/*
+ * Voltage Processor (VP) identifiers
+ */
+#define OMAP3_VP_VDD_MPU_ID     0
+#define OMAP3_VP_VDD_CORE_ID    1
+#define OMAP4_VP_VDD_CORE_ID    0
+#define OMAP4_VP_VDD_IVA_ID     1
+#define OMAP4_VP_VDD_MPU_ID     2
+u32 omap_prm_vp_check_txdone(u8 vp_id);
+void omap_prm_vp_clear_txdone(u8 vp_id);
 #endif
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index af0f15278fc2..752018ce129c 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -123,13 +123,14 @@ static void omap2xxx_prm_dpll_reset(void)
 * Clears wakeup status bits for a given module, so that the device can
 * re-enter idle.
 */
-void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
+static int omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
 {
        u32 wkst;
        wkst = omap2_prm_read_mod_reg(module, regs);
        wkst &= wkst_mask;
        omap2_prm_write_mod_reg(wkst, module, regs);
+        return 0;
 }
 int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
@@ -216,9 +217,10 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
        .deassert_hardreset = &omap2_prm_deassert_hardreset,
        .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
        .reset_system = &omap2xxx_prm_dpll_reset,
+        .clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
 };
-int __init omap2xxx_prm_init(void)
+int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
 {
        return prm_register(&omap2xxx_prm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 1d51643062f7..9008a9e55a1a 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -124,9 +124,7 @@
 extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
 extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
-void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
+int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
-extern int __init omap2xxx_prm_init(void);
 #endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 02f628601b09..dcb5001d77da 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -378,7 +378,7 @@ static struct prm_ll_data am33xx_prm_ll_data = {
        .reset_system                   = am33xx_prm_global_warm_sw_reset,
 };
-int __init am33xx_prm_init(void)
+int __init am33xx_prm_init(const struct omap_prcm_init_data *data)
 {
        return prm_register(&am33xx_prm_ll_data);
 }
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 98ac41f271da..2bc4ec52ba78 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -118,7 +118,7 @@
 #define AM33XX_PM_CEFUSE_PWRSTST                AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
 #ifndef __ASSEMBLER__
-int am33xx_prm_init(void);
+int am33xx_prm_init(const struct omap_prcm_init_data *data);
 #endif /* ASSEMBLER */
 #endif
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 5713bbdf83bc..62680aad2126 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -29,6 +29,7 @@
 #include "prm-regbits-34xx.h"
 #include "cm3xxx.h"
 #include "cm-regbits-34xx.h"
+#include "clock.h"
 static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
 static void omap3xxx_prm_ocp_barrier(void);
@@ -96,7 +97,7 @@ static struct omap3_vp omap3_vp[] = {
 #define MAX_VP_ID ARRAY_SIZE(omap3_vp);
-u32 omap3_prm_vp_check_txdone(u8 vp_id)
+static u32 omap3_prm_vp_check_txdone(u8 vp_id)
 {
        struct omap3_vp *vp = &omap3_vp[vp_id];
        u32 irqstatus;
@@ -106,7 +107,7 @@ u32 omap3_prm_vp_check_txdone(u8 vp_id)
        return irqstatus & vp->tranxdone_status;
 }
-void omap3_prm_vp_clear_txdone(u8 vp_id)
+static void omap3_prm_vp_clear_txdone(u8 vp_id)
 {
        struct omap3_vp *vp = &omap3_vp[vp_id];
@@ -217,7 +218,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
 * @module: PRM module to clear wakeups from
 * @regs: register set to clear, 1 or 3
- * @ignore_bits: wakeup status bits to ignore
+ * @wkst_mask: wkst bits to clear
 *
 * The purpose of this function is to clear any wake-up events latched
 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
@@ -226,7 +227,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
 * that any peripheral wake-up events occurring while attempting to
 * clear the PM_WKST_x are detected and cleared.
 */
-int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
+static int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
 {
        u32 wkst, fclk, iclk, clken;
        u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@@ -238,7 +239,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
        wkst = omap2_prm_read_mod_reg(module, wkst_off);
        wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
-        wkst &= ~ignore_bits;
+        wkst &= wkst_mask;
        if (wkst) {
                iclk = omap2_cm_read_mod_reg(module, iclk_off);
                fclk = omap2_cm_read_mod_reg(module, fclk_off);
@@ -254,7 +255,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
                        omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
                        omap2_prm_write_mod_reg(wkst, module, wkst_off);
                        wkst = omap2_prm_read_mod_reg(module, wkst_off);
-                        wkst &= ~ignore_bits;
+                        wkst &= wkst_mask;
                        c++;
                }
                omap2_cm_write_mod_reg(iclk, module, iclk_off);
@@ -664,10 +665,15 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
        .deassert_hardreset = &omap2_prm_deassert_hardreset,
        .is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
        .reset_system = &omap3xxx_prm_dpll3_reset,
+        .clear_mod_irqs = &omap3xxx_prm_clear_mod_irqs,
+        .vp_check_txdone = &omap3_prm_vp_check_txdone,
+        .vp_clear_txdone = &omap3_prm_vp_clear_txdone,
 };
-int __init omap3xxx_prm_init(void)
+int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
 {
+        omap2_clk_legacy_provider_init(TI_CLKM_PRM,
+                                       prm_base + OMAP3430_IVA2_MOD);
        if (omap3_has_io_wakeup())
                prm_features |= PRM_HAS_IO_WAKEUP;
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index ed8a3d8b739a..5f095eec339c 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -132,10 +132,6 @@
 #ifndef __ASSEMBLER__
-/* OMAP3-specific VP functions */
-u32 omap3_prm_vp_check_txdone(u8 vp_id);
-void omap3_prm_vp_clear_txdone(u8 vp_id);
 /*
 * OMAP3 access functions for voltage controller (VC) and
 * voltage proccessor (VP) in the PRM.
@@ -144,8 +140,7 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-extern int __init omap3xxx_prm_init(void);
+int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
-int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
 void omap3xxx_prm_iva_idle(void);
 void omap3_prm_reset_modem(void);
 int omap3xxx_prm_clear_global_cold_reset(void);
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index d6d6bc39e05c..4541700f743a 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -138,7 +138,7 @@ static struct omap4_vp omap4_vp[] = {
        },
 };
-u32 omap4_prm_vp_check_txdone(u8 vp_id)
+static u32 omap4_prm_vp_check_txdone(u8 vp_id)
 {
        struct omap4_vp *vp = &omap4_vp[vp_id];
        u32 irqstatus;
@@ -149,7 +149,7 @@ u32 omap4_prm_vp_check_txdone(u8 vp_id)
        return irqstatus & vp->tranxdone_status;
 }
-void omap4_prm_vp_clear_txdone(u8 vp_id)
+static void omap4_prm_vp_clear_txdone(u8 vp_id)
 {
        struct omap4_vp *vp = &omap4_vp[vp_id];
@@ -699,29 +699,31 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
        .deassert_hardreset     = omap4_prminst_deassert_hardreset,
        .is_hardreset_asserted  = omap4_prminst_is_hardreset_asserted,
        .reset_system           = omap4_prminst_global_warm_sw_reset,
+        .vp_check_txdone        = omap4_prm_vp_check_txdone,
+        .vp_clear_txdone        = omap4_prm_vp_clear_txdone,
 };
-int __init omap44xx_prm_init(void)
+static const struct omap_prcm_init_data *prm_init_data;
+int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
 {
-        if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
+        omap_prm_base_init();
+        prm_init_data = data;
+        if (data->flags & PRM_HAS_IO_WAKEUP)
                prm_features |= PRM_HAS_IO_WAKEUP;
-        if (!soc_is_dra7xx())
+        if (data->flags & PRM_HAS_VOLTAGE)
                prm_features |= PRM_HAS_VOLTAGE;
+        omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
        return prm_register(&omap44xx_prm_ll_data);
 }
-static const struct of_device_id omap_prm_dt_match_table[] = {
-        { .compatible = "ti,omap4-prm" },
-        { .compatible = "ti,omap5-prm" },
-        { .compatible = "ti,dra7-prm" },
-        { }
-};
 static int omap44xx_prm_late_init(void)
 {
-        struct device_node *np;
        int irq_num;
        if (!(prm_features & PRM_HAS_IO_WAKEUP))
@@ -731,31 +733,23 @@ static int omap44xx_prm_late_init(void)
        if (!of_have_populated_dt())
                return 0;
-        np = of_find_matching_node(NULL, omap_prm_dt_match_table);
+        irq_num = of_irq_get(prm_init_data->np, 0);
+        /*
-        if (!np) {
+         * Already have OMAP4 IRQ num. For all other platforms, we need
-                /* Default loaded up with OMAP4 values */
+         * IRQ numbers from DT
-                if (!cpu_is_omap44xx())
+         */
-                        return 0;
+        if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
-        } else {
+                if (irq_num == -EPROBE_DEFER)
-                irq_num = of_irq_get(np, 0);
+                        return irq_num;
-                /*
-                 * Already have OMAP4 IRQ num. For all other platforms, we need
+                /* Have nothing to do */
-                 * IRQ numbers from DT
+                return 0;
-                 */
+        }
-                if (irq_num < 0 && !cpu_is_omap44xx()) {
-                        if (irq_num == -EPROBE_DEFER)
+        /* Once OMAP4 DT is filled as well */
-                                return irq_num;
+        if (irq_num >= 0) {
+                omap4_prcm_irq_setup.irq = irq_num;
-                        /* Have nothing to do */
+                omap4_prcm_irq_setup.xlate_irq = NULL;
-                        return 0;
-                }
-                /* Once OMAP4 DT is filled as well */
-                if (irq_num >= 0) {
-                        omap4_prcm_irq_setup.irq = irq_num;
-                        omap4_prcm_irq_setup.xlate_irq = NULL;
-                }
        }
        omap44xx_prm_enable_io_wakeup();
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7db2422faa16..efd6035d0871 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -26,7 +26,6 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 #include "prm44xx_54xx.h"
-#include "prcm-common.h"
 #include "prm.h"
 #define OMAP4430_PRM_BASE               0x4a306000
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 714329565b90..3f139ebc8398 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -23,13 +23,11 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+#include "prcm-common.h"
 /* Function prototypes */
 #ifndef __ASSEMBLER__
-/* OMAP4/OMAP5-specific VP functions */
-u32 omap4_prm_vp_check_txdone(u8 vp_id);
-void omap4_prm_vp_clear_txdone(u8 vp_id);
 /*
 * OMAP4/OMAP5 access functions for voltage controller (VC) and
 * voltage proccessor (VP) in the PRM.
@@ -38,7 +36,7 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-extern int __init omap44xx_prm_init(void);
+int __init omap44xx_prm_init(const struct omap_prcm_init_data *data);
 #endif
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
index e4411010309c..1eb22ff087dc 100644
--- a/arch/arm/mach-omap2/prm54xx.h
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -22,7 +22,6 @@
 #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
 #include "prm44xx_54xx.h"
-#include "prcm-common.h"
 #include "prm.h"
 #define OMAP54XX_PRM_BASE               0x4ae06000
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index 4bb50fbf29be..cc1e6a2b97f6 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -22,8 +22,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
-#include "prm44xx_54xx.h"
 #include "prcm-common.h"
+#include "prm44xx_54xx.h"
 #include "prm.h"
 #define DRA7XX_PRM_BASE         0x4ae06000
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index bfaa7ba595cc..7add7994dbfc 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -32,7 +32,11 @@
 #include "prm2xxx_3xxx.h"
 #include "prm2xxx.h"
 #include "prm3xxx.h"
+#include "prm33xx.h"
 #include "prm44xx.h"
+#include "prm54xx.h"
+#include "prm7xx.h"
+#include "prcm43xx.h"
 #include "common.h"
 #include "clock.h"
 #include "cm.h"
@@ -534,6 +538,61 @@ void omap_prm_reset_system(void)
 }
 /**
+ * omap_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
+ * @module: PRM module to clear wakeups from
+ * @regs: register to clear
+ * @wkst_mask: wkst bits to clear
+ *
+ * Clears any wakeup events for the module and register set defined.
+ * Uses SoC specific implementation to do the actual wakeup status
+ * clearing.
+ */
+int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
+{
+        if (!prm_ll_data->clear_mod_irqs) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return -EINVAL;
+        }
+        return prm_ll_data->clear_mod_irqs(module, regs, wkst_mask);
+}
+/**
+ * omap_prm_vp_check_txdone - check voltage processor TX done status
+ *
+ * Checks if voltage processor transmission has been completed.
+ * Returns non-zero if a transmission has completed, 0 otherwise.
+ */
+u32 omap_prm_vp_check_txdone(u8 vp_id)
+{
+        if (!prm_ll_data->vp_check_txdone) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return 0;
+        }
+        return prm_ll_data->vp_check_txdone(vp_id);
+}
+/**
+ * omap_prm_vp_clear_txdone - clears voltage processor TX done status
+ *
+ * Clears the status bit for completed voltage processor transmission
+ * returned by prm_vp_check_txdone.
+ */
+void omap_prm_vp_clear_txdone(u8 vp_id)
+{
+        if (!prm_ll_data->vp_clear_txdone) {
+                WARN_ONCE(1, "prm: %s: no mapping function defined\n",
+                          __func__);
+                return;
+        }
+        prm_ll_data->vp_clear_txdone(vp_id);
+}
+/**
 * prm_register - register per-SoC low-level data with the PRM
 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
 *
@@ -578,78 +637,175 @@ int prm_unregister(struct prm_ll_data *pld)
        return 0;
 }
-static const struct of_device_id omap_prcm_dt_match_table[] = {
+#ifdef CONFIG_ARCH_OMAP2
-        { .compatible = "ti,am3-prcm" },
+static struct omap_prcm_init_data omap2_prm_data __initdata = {
-        { .compatible = "ti,am3-scrm" },
+        .index = TI_CLKM_PRM,
-        { .compatible = "ti,am4-prcm" },
+        .init = omap2xxx_prm_init,
-        { .compatible = "ti,am4-scrm" },
-        { .compatible = "ti,dm814-prcm" },
-        { .compatible = "ti,dm814-scrm" },
-        { .compatible = "ti,dm816-prcm" },
-        { .compatible = "ti,dm816-scrm" },
-        { .compatible = "ti,omap2-prcm" },
-        { .compatible = "ti,omap2-scrm" },
-        { .compatible = "ti,omap3-prm" },
-        { .compatible = "ti,omap3-cm" },
-        { .compatible = "ti,omap3-scrm" },
-        { .compatible = "ti,omap4-cm1" },
-        { .compatible = "ti,omap4-prm" },
-        { .compatible = "ti,omap4-cm2" },
-        { .compatible = "ti,omap4-scrm" },
-        { .compatible = "ti,omap5-prm" },
-        { .compatible = "ti,omap5-cm-core-aon" },
-        { .compatible = "ti,omap5-scrm" },
-        { .compatible = "ti,omap5-cm-core" },
-        { .compatible = "ti,dra7-prm" },
-        { .compatible = "ti,dra7-cm-core-aon" },
-        { .compatible = "ti,dra7-cm-core" },
-        { }
 };
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+static struct omap_prcm_init_data omap3_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap3xxx_prm_init,
-static struct clk_hw_omap memmap_dummy_ck = {
+        /*
-        .flags = MEMMAP_ADDRESSING,
+         * IVA2 offset is a negative value, must offset the prm_base
+         * address by this to get it to positive
+         */
+        .offset = -OMAP3430_IVA2_MOD,
 };
+#endif
-static u32 prm_clk_readl(void __iomem *reg)
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
-{
+static struct omap_prcm_init_data am3_prm_data __initdata = {
-        return omap2_clk_readl(&memmap_dummy_ck, reg);
+        .index = TI_CLKM_PRM,
-}
+        .init = am33xx_prm_init,
+};
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+static struct omap_prcm_init_data omap4_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap44xx_prm_init,
+        .device_inst_offset = OMAP4430_PRM_DEVICE_INST,
+        .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE | PRM_IRQ_DEFAULT,
+};
+#endif
+#ifdef CONFIG_SOC_OMAP5
+static struct omap_prcm_init_data omap5_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap44xx_prm_init,
+        .device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
+        .flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
+};
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+static struct omap_prcm_init_data dra7_prm_data __initdata = {
+        .index = TI_CLKM_PRM,
+        .init = omap44xx_prm_init,
+        .device_inst_offset = DRA7XX_PRM_DEVICE_INST,
+        .flags = PRM_HAS_IO_WAKEUP,
+};
+#endif
-static void prm_clk_writel(u32 val, void __iomem *reg)
+#ifdef CONFIG_SOC_AM43XX
-{
+static struct omap_prcm_init_data am4_prm_data __initdata = {
-        omap2_clk_writel(val, &memmap_dummy_ck, reg);
+        .index = TI_CLKM_PRM,
-}
+        .init = omap44xx_prm_init,
+        .device_inst_offset = AM43XX_PRM_DEVICE_INST,
+};
+#endif
-static struct ti_clk_ll_ops omap_clk_ll_ops = {
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
-        .clk_readl = prm_clk_readl,
+static struct omap_prcm_init_data scrm_data __initdata = {
-        .clk_writel = prm_clk_writel,
+        .index = TI_CLKM_SCRM,
+};
+#endif
+static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
+#ifdef CONFIG_SOC_AM33XX
+        { .compatible = "ti,am3-prcm", .data = &am3_prm_data },
+#endif
+#ifdef CONFIG_SOC_AM43XX
+        { .compatible = "ti,am4-prcm", .data = &am4_prm_data },
+#endif
+#ifdef CONFIG_SOC_TI81XX
+        { .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
+        { .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP2
+        { .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+        { .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+        { .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
+        { .compatible = "ti,omap4-scrm", .data = &scrm_data },
+#endif
+#ifdef CONFIG_SOC_OMAP5
+        { .compatible = "ti,omap5-prm", .data = &omap5_prm_data },
+        { .compatible = "ti,omap5-scrm", .data = &scrm_data },
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+        { .compatible = "ti,dra7-prm", .data = &dra7_prm_data },
+#endif
+        { }
 };
-int __init of_prcm_init(void)
+/**
+ * omap2_prm_base_init - initialize iomappings for the PRM driver
+ *
+ * Detects and initializes the iomappings for the PRM driver, based
+ * on the DT data. Returns 0 in success, negative error value
+ * otherwise.
+ */
+int __init omap2_prm_base_init(void)
 {
        struct device_node *np;
+        const struct of_device_id *match;
+        struct omap_prcm_init_data *data;
        void __iomem *mem;
-        int memmap_index = 0;
-        ti_clk_ll_ops = &omap_clk_ll_ops;
+        for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
+                data = (struct omap_prcm_init_data *)match->data;
-        for_each_matching_node(np, omap_prcm_dt_match_table) {
                mem = of_iomap(np, 0);
-                clk_memmaps[memmap_index] = mem;
+                if (!mem)
-                ti_dt_clk_init_provider(np, memmap_index);
+                        return -ENOMEM;
-                memmap_index++;
+                if (data->index == TI_CLKM_PRM)
+                        prm_base = mem + data->offset;
+                data->mem = mem;
+                data->np = np;
+                if (data->init)
+                        data->init(data);
        }
        return 0;
 }
-void __init omap3_prcm_legacy_iomaps_init(void)
+int __init omap2_prcm_base_init(void)
 {
-        ti_clk_ll_ops = &omap_clk_ll_ops;
+        int ret;
-        clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
+        ret = omap2_prm_base_init();
-        clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
+        if (ret)
-        clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
+                return ret;
+        return omap2_cm_base_init();
+}
+/**
+ * omap_prcm_init - low level init for the PRCM drivers
+ *
+ * Initializes the low level clock infrastructure for PRCM drivers.
+ * Returns 0 in success, negative error value in failure.
+ */
+int __init omap_prcm_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *match;
+        const struct omap_prcm_init_data *data;
+        int ret;
+        for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
+                data = match->data;
+                ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
+                if (ret)
+                        return ret;
+        }
+        omap_cm_init();
+        return 0;
 }
 static int __init prm_late_init(void)
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 8adf7b1a1dce..c4859c4d3646 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -47,22 +47,14 @@ void omap_prm_base_init(void)
 s32 omap4_prmst_get_prm_dev_inst(void)
 {
-        if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
-                return prm_dev_inst;
-        /* This cannot be done way early at boot.. as things are not setup */
-        if (cpu_is_omap44xx())
-                prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
-        else if (soc_is_omap54xx())
-                prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
-        else if (soc_is_dra7xx())
-                prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
-        else if (soc_is_am43xx())
-                prm_dev_inst = AM43XX_PRM_DEVICE_INST;
        return prm_dev_inst;
 }
+void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
+{
+        prm_dev_inst = dev_inst;
+}
 /* Read a register in a PRM instance */
 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
 {
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index fb1c9d7a2f9d..0c03d0731d7f 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -14,6 +14,7 @@
 #define PRM_INSTANCE_UNKNOWN    -1
 extern s32 omap4_prmst_get_prm_dev_inst(void);
+void omap4_prminst_set_prm_dev_inst(s32 dev_inst);
 /*
 * In an ideal world, we would not export these low-level functions,
diff --git a/arch/arm/mach-omap2/vp.h b/arch/arm/mach-omap2/vp.h
index 0fdf7080e4a6..7e0829682bd0 100644
--- a/arch/arm/mach-omap2/vp.h
+++ b/arch/arm/mach-omap2/vp.h
@@ -21,15 +21,6 @@
 struct voltagedomain;
-/*
- * Voltage Processor (VP) identifiers
- */
-#define OMAP3_VP_VDD_MPU_ID 0
-#define OMAP3_VP_VDD_CORE_ID 1
-#define OMAP4_VP_VDD_CORE_ID 0
-#define OMAP4_VP_VDD_IVA_ID 1
-#define OMAP4_VP_VDD_MPU_ID 2
 /* XXX document */
 #define VP_IDLE_TIMEOUT         200
 #define VP_TRANXDONE_TIMEOUT    300
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index 1914e026245e..b0590fe6ab01 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -28,8 +28,8 @@
 #include "prm2xxx_3xxx.h"
 static const struct omap_vp_ops omap3_vp_ops = {
-        .check_txdone = omap3_prm_vp_check_txdone,
+        .check_txdone = omap_prm_vp_check_txdone,
-        .clear_txdone = omap3_prm_vp_clear_txdone,
+        .clear_txdone = omap_prm_vp_clear_txdone,
 };
 /*
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
index e62f6b018beb..2448bb9a8716 100644
--- a/arch/arm/mach-omap2/vp44xx_data.c
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -28,8 +28,8 @@
 #include "vp.h"
 static const struct omap_vp_ops omap4_vp_ops = {
-        .check_txdone = omap4_prm_vp_check_txdone,
+        .check_txdone = omap_prm_vp_check_txdone,
-        .clear_txdone = omap4_prm_vp_clear_txdone,
+        .clear_txdone = omap_prm_vp_clear_txdone,
 };
 /*
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 67844003493d..79b76e13d904 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -215,14 +215,14 @@ struct ti_dt_clk {
                .node_name = name,      \
        }
-/* Maximum number of clock memmaps */
-#define CLK_MAX_MEMMAPS                 4
 /* Static memmap indices */
 enum {
        TI_CLKM_CM = 0,
+        TI_CLKM_CM2,
        TI_CLKM_PRM,
        TI_CLKM_SCRM,
+        TI_CLKM_CTRL,
+        CLK_MAX_MEMMAPS
 };
 typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);