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-rw-r--r--arch/m32r/platforms/m32104ut/setup.c46
1 files changed, 21 insertions, 25 deletions
diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c
index 962f38e58acc..4a693d02c1e1 100644
--- a/arch/m32r/platforms/m32104ut/setup.c
+++ b/arch/m32r/platforms/m32104ut/setup.c
@@ -39,39 +39,30 @@ static void enable_m32104ut_irq(unsigned int irq)
39 outl(data, port); 39 outl(data, port);
40} 40}
41 41
42static void mask_and_ack_m32104ut(unsigned int irq) 42static void mask_m32104ut_irq(struct irq_data *data)
43{ 43{
44 disable_m32104ut_irq(irq); 44 disable_m32104ut_irq(data->irq);
45} 45}
46 46
47static void end_m32104ut_irq(unsigned int irq) 47static void unmask_m32104ut_irq(struct irq_data *data)
48{ 48{
49 enable_m32104ut_irq(irq); 49 enable_m32104ut_irq(data->irq);
50} 50}
51 51
52static unsigned int startup_m32104ut_irq(unsigned int irq) 52static void shutdown_m32104ut_irq(struct irq_data *data)
53{ 53{
54 enable_m32104ut_irq(irq); 54 unsigned int irq = data->irq;
55 return (0); 55 unsigned long port = irq2port(irq);
56}
57
58static void shutdown_m32104ut_irq(unsigned int irq)
59{
60 unsigned long port;
61 56
62 port = irq2port(irq);
63 outl(M32R_ICUCR_ILEVEL7, port); 57 outl(M32R_ICUCR_ILEVEL7, port);
64} 58}
65 59
66static struct irq_chip m32104ut_irq_type = 60static struct irq_chip m32104ut_irq_type =
67{ 61{
68 .name = "M32104UT-IRQ", 62 .name = "M32104UT-IRQ",
69 .startup = startup_m32104ut_irq, 63 .irq_shutdown = shutdown_m32104ut_irq,
70 .shutdown = shutdown_m32104ut_irq, 64 .irq_unmask = unmask_m32104ut_irq,
71 .enable = enable_m32104ut_irq, 65 .irq_mask = mask_m32104ut_irq,
72 .disable = disable_m32104ut_irq,
73 .ack = mask_and_ack_m32104ut,
74 .end = end_m32104ut_irq
75}; 66};
76 67
77void __init init_IRQ(void) 68void __init init_IRQ(void)
@@ -85,24 +76,29 @@ void __init init_IRQ(void)
85 76
86#if defined(CONFIG_SMC91X) 77#if defined(CONFIG_SMC91X)
87 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ 78 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
88 set_irq_chip(M32R_IRQ_INT0, &m32104ut_irq_type); 79 set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
89 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ 80 handle_level_irq);
81 /* "H" level sense */
82 cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11;
90 disable_m32104ut_irq(M32R_IRQ_INT0); 83 disable_m32104ut_irq(M32R_IRQ_INT0);
91#endif /* CONFIG_SMC91X */ 84#endif /* CONFIG_SMC91X */
92 85
93 /* MFT2 : system timer */ 86 /* MFT2 : system timer */
94 set_irq_chip(M32R_IRQ_MFT2, &m32104ut_irq_type); 87 set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
88 handle_level_irq);
95 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 89 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
96 disable_m32104ut_irq(M32R_IRQ_MFT2); 90 disable_m32104ut_irq(M32R_IRQ_MFT2);
97 91
98#ifdef CONFIG_SERIAL_M32R_SIO 92#ifdef CONFIG_SERIAL_M32R_SIO
99 /* SIO0_R : uart receive data */ 93 /* SIO0_R : uart receive data */
100 set_irq_chip(M32R_IRQ_SIO0_R, &m32104ut_irq_type); 94 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
95 handle_level_irq);
101 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; 96 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
102 disable_m32104ut_irq(M32R_IRQ_SIO0_R); 97 disable_m32104ut_irq(M32R_IRQ_SIO0_R);
103 98
104 /* SIO0_S : uart send data */ 99 /* SIO0_S : uart send data */
105 set_irq_chip(M32R_IRQ_SIO0_S, &m32104ut_irq_type); 100 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
101 handle_level_irq);
106 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; 102 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
107 disable_m32104ut_irq(M32R_IRQ_SIO0_S); 103 disable_m32104ut_irq(M32R_IRQ_SIO0_S);
108#endif /* CONFIG_SERIAL_M32R_SIO */ 104#endif /* CONFIG_SERIAL_M32R_SIO */