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-rw-r--r--drivers/clk/ux500/clk-prcmu.c14
-rw-r--r--drivers/clk/ux500/clk.h5
2 files changed, 19 insertions, 0 deletions
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index 1d779ad12169..930cdfeb47ab 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -153,6 +153,11 @@ static struct clk_ops clk_prcmu_gate_ops = {
153 .recalc_rate = clk_prcmu_recalc_rate, 153 .recalc_rate = clk_prcmu_recalc_rate,
154}; 154};
155 155
156static struct clk_ops clk_prcmu_rate_ops = {
157 .is_enabled = clk_prcmu_is_enabled,
158 .recalc_rate = clk_prcmu_recalc_rate,
159};
160
156static struct clk_ops clk_prcmu_opp_gate_ops = { 161static struct clk_ops clk_prcmu_opp_gate_ops = {
157 .prepare = clk_prcmu_opp_prepare, 162 .prepare = clk_prcmu_opp_prepare,
158 .unprepare = clk_prcmu_opp_unprepare, 163 .unprepare = clk_prcmu_opp_unprepare,
@@ -228,6 +233,15 @@ struct clk *clk_reg_prcmu_gate(const char *name,
228 &clk_prcmu_gate_ops); 233 &clk_prcmu_gate_ops);
229} 234}
230 235
236struct clk *clk_reg_prcmu_rate(const char *name,
237 const char *parent_name,
238 u8 cg_sel,
239 unsigned long flags)
240{
241 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
242 &clk_prcmu_rate_ops);
243}
244
231struct clk *clk_reg_prcmu_opp_gate(const char *name, 245struct clk *clk_reg_prcmu_opp_gate(const char *name,
232 const char *parent_name, 246 const char *parent_name,
233 u8 cg_sel, 247 u8 cg_sel,
diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h
index 32085aa98865..836d7d16751e 100644
--- a/drivers/clk/ux500/clk.h
+++ b/drivers/clk/ux500/clk.h
@@ -35,6 +35,11 @@ struct clk *clk_reg_prcmu_gate(const char *name,
35 u8 cg_sel, 35 u8 cg_sel,
36 unsigned long flags); 36 unsigned long flags);
37 37
38struct clk *clk_reg_prcmu_rate(const char *name,
39 const char *parent_name,
40 u8 cg_sel,
41 unsigned long flags);
42
38struct clk *clk_reg_prcmu_opp_gate(const char *name, 43struct clk *clk_reg_prcmu_opp_gate(const char *name,
39 const char *parent_name, 44 const char *parent_name,
40 u8 cg_sel, 45 u8 cg_sel,