253 files changed, 16905 insertions, 7306 deletions

diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
index 5ddb2e9efaaa..4b87ea1194e3 100644
--- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -35,36 +35,83 @@ Required properties:
 
 Timing properties for child nodes. All are optional and default to 0.
 
- - gpmc,sync-clk:       Minimum clock period for synchronous mode, in picoseconds
-
- Chip-select signal timings corresponding to GPMC_CONFIG2:
- - gpmc,cs-on:          Assertion time
- - gpmc,cs-rd-off:      Read deassertion time
- - gpmc,cs-wr-off:      Write deassertion time
-
- ADV signal timings corresponding to GPMC_CONFIG3:
- - gpmc,adv-on:         Assertion time
- - gpmc,adv-rd-off:     Read deassertion time
- - gpmc,adv-wr-off:     Write deassertion time
-
- WE signals timings corresponding to GPMC_CONFIG4:
- - gpmc,we-on:          Assertion time
- - gpmc,we-off:         Deassertion time
-
- OE signals timings corresponding to GPMC_CONFIG4:
- - gpmc,oe-on:          Assertion time
- - gpmc,oe-off:         Deassertion time
-
- Access time and cycle time timings corresponding to GPMC_CONFIG5:
- - gpmc,page-burst-access: Multiple access word delay
- - gpmc,access:         Start-cycle to first data valid delay
- - gpmc,rd-cycle:       Total read cycle time
- - gpmc,wr-cycle:       Total write cycle time
+ - gpmc,sync-clk-ps:    Minimum clock period for synchronous mode, in picoseconds
+
+ Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
+ - gpmc,cs-on-ns:       Assertion time
+ - gpmc,cs-rd-off-ns:   Read deassertion time
+ - gpmc,cs-wr-off-ns:   Write deassertion time
+
+ ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
+ - gpmc,adv-on-ns:      Assertion time
+ - gpmc,adv-rd-off-ns:  Read deassertion time
+ - gpmc,adv-wr-off-ns:  Write deassertion time
+
+ WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
+ - gpmc,we-on-ns        Assertion time
+ - gpmc,we-off-ns:      Deassertion time
+
+ OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
+ - gpmc,oe-on-ns:       Assertion time
+ - gpmc,oe-off-ns:      Deassertion time
+
+ Access time and cycle time timings (in nanoseconds) corresponding to
+ GPMC_CONFIG5:
+ - gpmc,page-burst-access-ns:   Multiple access word delay
+ - gpmc,access-ns:              Start-cycle to first data valid delay
+ - gpmc,rd-cycle-ns:            Total read cycle time
+ - gpmc,wr-cycle-ns:            Total write cycle time
+ - gpmc,bus-turnaround-ns:      Turn-around time between successive accesses
+ - gpmc,cycle2cycle-delay-ns:   Delay between chip-select pulses
+ - gpmc,clk-activation-ns:      GPMC clock activation time
+ - gpmc,wait-monitoring-ns:     Start of wait monitoring with regard to valid
+                                data
+
+Boolean timing parameters. If property is present parameter enabled and
+disabled if omitted:
+ - gpmc,adv-extra-delay:        ADV signal is delayed by half GPMC clock
+ - gpmc,cs-extra-delay:         CS signal is delayed by half GPMC clock
+ - gpmc,cycle2cycle-diffcsen:   Add "cycle2cycle-delay" between successive
+                                accesses to a different CS
+ - gpmc,cycle2cycle-samecsen:   Add "cycle2cycle-delay" between successive
+                                accesses to the same CS
+ - gpmc,oe-extra-delay:         OE signal is delayed by half GPMC clock
+ - gpmc,we-extra-delay:         WE signal is delayed by half GPMC clock
+ - gpmc,time-para-granularity:  Multiply all access times by 2
 
 The following are only applicable to OMAP3+ and AM335x:
- - gpmc,wr-access
- - gpmc,wr-data-mux-bus
-
+ - gpmc,wr-access-ns:           In synchronous write mode, for single or
+                                burst accesses, defines the number of
+                                GPMC_FCLK cycles from start access time
+                                to the GPMC_CLK rising edge used by the
+                                memory device for the first data capture.
+ - gpmc,wr-data-mux-bus-ns:     In address-data multiplex mode, specifies
+                                the time when the first data is driven on
+                                the address-data bus.
+
+GPMC chip-select settings properties for child nodes. All are optional.
+
+- gpmc,burst-length     Page/burst length. Must be 4, 8 or 16.
+- gpmc,burst-wrap       Enables wrap bursting
+- gpmc,burst-read       Enables read page/burst mode
+- gpmc,burst-write      Enables write page/burst mode
+- gpmc,device-nand      Device is NAND
+- gpmc,device-width     Total width of device(s) connected to a GPMC
+                        chip-select in bytes. The GPMC supports 8-bit
+                        and 16-bit devices and so this property must be
+                        1 or 2.
+- gpmc,mux-add-data     Address and data multiplexing configuration.
+                        Valid values are 1 for address-address-data
+                        multiplexing mode and 2 for address-data
+                        multiplexing mode.
+- gpmc,sync-read        Enables synchronous read. Defaults to asynchronous
+                        is this is not set.
+- gpmc,sync-write       Enables synchronous writes. Defaults to asynchronous
+                        is this is not set.
+- gpmc,wait-pin         Wait-pin used by client. Must be less than
+                        "gpmc,num-waitpins".
+- gpmc,wait-on-read     Enables wait monitoring on reads.
+- gpmc,wait-on-write    Enables wait monitoring on writes.
 
 Example for an AM33xx board:
 
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
new file mode 100644
index 000000000000..ea5e26f16aec
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -0,0 +1,288 @@
+* Samsung Exynos4 Clock Controller
+
+The Exynos4 clock controller generates and supplies clock to various controllers
+within the Exynos4 SoC. The clock binding described here is applicable to all
+SoC's in the Exynos4 family.
+
+Required Properties:
+
+- comptible: should be one of the following.
+  - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
+  - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+
+                 [Core Clocks]
+
+  Clock               ID      SoC (if specific)
+  -----------------------------------------------
+
+  xxti                1
+  xusbxti             2
+  fin_pll             3
+  fout_apll           4
+  fout_mpll           5
+  fout_epll           6
+  fout_vpll           7
+  sclk_apll           8
+  sclk_mpll           9
+  sclk_epll           10
+  sclk_vpll           11
+  arm_clk             12
+  aclk200             13
+  aclk100             14
+  aclk160             15
+  aclk133             16
+  mout_mpll_user_t    17      Exynos4x12
+  mout_mpll_user_c    18      Exynos4x12
+  mout_core           19
+  mout_apll           20
+
+
+            [Clock Gate for Special Clocks]
+
+  Clock               ID      SoC (if specific)
+  -----------------------------------------------
+
+  sclk_fimc0          128
+  sclk_fimc1          129
+  sclk_fimc2          130
+  sclk_fimc3          131
+  sclk_cam0           132
+  sclk_cam1           133
+  sclk_csis0          134
+  sclk_csis1          135
+  sclk_hdmi           136
+  sclk_mixer          137
+  sclk_dac            138
+  sclk_pixel          139
+  sclk_fimd0          140
+  sclk_mdnie0         141     Exynos4412
+  sclk_mdnie_pwm0 12  142     Exynos4412
+  sclk_mipi0          143
+  sclk_audio0         144
+  sclk_mmc0           145
+  sclk_mmc1           146
+  sclk_mmc2           147
+  sclk_mmc3           148
+  sclk_mmc4           149
+  sclk_sata           150     Exynos4210
+  sclk_uart0          151
+  sclk_uart1          152
+  sclk_uart2          153
+  sclk_uart3          154
+  sclk_uart4          155
+  sclk_audio1         156
+  sclk_audio2         157
+  sclk_spdif          158
+  sclk_spi0           159
+  sclk_spi1           160
+  sclk_spi2           161
+  sclk_slimbus        162
+  sclk_fimd1          163     Exynos4210
+  sclk_mipi1          164     Exynos4210
+  sclk_pcm1           165
+  sclk_pcm2           166
+  sclk_i2s1           167
+  sclk_i2s2           168
+  sclk_mipihsi        169     Exynos4412
+  sclk_mfc            170
+  sclk_pcm0           171
+  sclk_g3d            172
+  sclk_pwm_isp        173     Exynos4x12
+  sclk_spi0_isp       174     Exynos4x12
+  sclk_spi1_isp       175     Exynos4x12
+  sclk_uart_isp       176     Exynos4x12
+
+              [Peripheral Clock Gates]
+
+  Clock               ID      SoC (if specific)
+  -----------------------------------------------
+
+  fimc0               256
+  fimc1               257
+  fimc2               258
+  fimc3               259
+  csis0               260
+  csis1               261
+  jpeg                262
+  smmu_fimc0          263
+  smmu_fimc1          264
+  smmu_fimc2          265
+  smmu_fimc3          266
+  smmu_jpeg           267
+  vp                  268
+  mixer               269
+  tvenc               270     Exynos4210
+  hdmi                271
+  smmu_tv             272
+  mfc                 273
+  smmu_mfcl           274
+  smmu_mfcr           275
+  g3d                 276
+  g2d                 277     Exynos4210
+  rotator             278     Exynos4210
+  mdma                279     Exynos4210
+  smmu_g2d            280     Exynos4210
+  smmu_rotator        281     Exynos4210
+  smmu_mdma           282     Exynos4210
+  fimd0               283
+  mie0                284
+  mdnie0              285     Exynos4412
+  dsim0               286
+  smmu_fimd0          287
+  fimd1               288     Exynos4210
+  mie1                289     Exynos4210
+  dsim1               290     Exynos4210
+  smmu_fimd1          291     Exynos4210
+  pdma0               292
+  pdma1               293
+  pcie_phy            294
+  sata_phy            295     Exynos4210
+  tsi                 296
+  sdmmc0              297
+  sdmmc1              298
+  sdmmc2              299
+  sdmmc3              300
+  sdmmc4              301
+  sata                302     Exynos4210
+  sromc               303
+  usb_host            304
+  usb_device          305
+  pcie                306
+  onenand             307
+  nfcon               308
+  smmu_pcie           309
+  gps                 310
+  smmu_gps            311
+  uart0               312
+  uart1               313
+  uart2               314
+  uart3               315
+  uart4               316
+  i2c0                317
+  i2c1                318
+  i2c2                319
+  i2c3                320
+  i2c4                321
+  i2c5                322
+  i2c6                323
+  i2c7                324
+  i2c_hdmi            325
+  tsadc               326
+  spi0                327
+  spi1                328
+  spi2                329
+  i2s1                330
+  i2s2                331
+  pcm0                332
+  i2s0                333
+  pcm1                334
+  pcm2                335
+  pwm                 336
+  slimbus             337
+  spdif               338
+  ac97                339
+  modemif             340
+  chipid              341
+  sysreg              342
+  hdmi_cec            343
+  mct                 344
+  wdt                 345
+  rtc                 346
+  keyif               347
+  audss               348
+  mipi_hsi            349     Exynos4210
+  mdma2               350     Exynos4210
+  pixelasyncm0        351
+  pixelasyncm1        352
+  fimc_lite0          353     Exynos4x12
+  fimc_lite1          354     Exynos4x12
+  ppmuispx            355     Exynos4x12
+  ppmuispmx           356     Exynos4x12
+  fimc_isp            357     Exynos4x12
+  fimc_drc            358     Exynos4x12
+  fimc_fd             359     Exynos4x12
+  mcuisp              360     Exynos4x12
+  gicisp              361     Exynos4x12
+  smmu_isp            362     Exynos4x12
+  smmu_drc            363     Exynos4x12
+  smmu_fd             364     Exynos4x12
+  smmu_lite0          365     Exynos4x12
+  smmu_lite1          366     Exynos4x12
+  mcuctl_isp          367     Exynos4x12
+  mpwm_isp            368     Exynos4x12
+  i2c0_isp            369     Exynos4x12
+  i2c1_isp            370     Exynos4x12
+  mtcadc_isp          371     Exynos4x12
+  pwm_isp             372     Exynos4x12
+  wdt_isp             373     Exynos4x12
+  uart_isp            374     Exynos4x12
+  asyncaxim           375     Exynos4x12
+  smmu_ispcx          376     Exynos4x12
+  spi0_isp            377     Exynos4x12
+  spi1_isp            378     Exynos4x12
+  pwm_isp_sclk        379     Exynos4x12
+  spi0_isp_sclk       380     Exynos4x12
+  spi1_isp_sclk       381     Exynos4x12
+  uart_isp_sclk       382     Exynos4x12
+
+                [Mux Clocks]
+
+  Clock                 ID      SoC (if specific)
+  -----------------------------------------------
+
+  mout_fimc0            384
+  mout_fimc1            385
+  mout_fimc2            386
+  mout_fimc3            387
+  mout_cam0             388
+  mout_cam1             389
+  mout_csis0            390
+  mout_csis1            391
+  mout_g3d0             392
+  mout_g3d1             393
+  mout_g3d              394
+  aclk400_mcuisp        395     Exynos4x12
+
+                [Div Clocks]
+
+  Clock                 ID      SoC (if specific)
+  -----------------------------------------------
+
+  div_isp0              450     Exynos4x12
+  div_isp1              451     Exynos4x12
+  div_mcuisp0           452     Exynos4x12
+  div_mcuisp1           453     Exynos4x12
+  div_aclk200           454     Exynos4x12
+  div_aclk400_mcuisp    455     Exynos4x12
+
+
+Example 1: An example of a clock controller node is listed below.
+
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4210-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+           controller. Refer to the standard clock bindings for information
+           about 'clocks' and 'clock-names' property.
+
+        serial@13820000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13820000 0x100>;
+                interrupts = <0 54 0>;
+                clocks = <&clock 314>, <&clock 153>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
new file mode 100644
index 000000000000..781a6276adf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -0,0 +1,177 @@
+* Samsung Exynos5250 Clock Controller
+
+The Exynos5250 clock controller generates and supplies clock to various
+controllers within the Exynos5250 SoC.
+
+Required Properties:
+
+- comptible: should be one of the following.
+  - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume.
+
+
+       [Core Clocks]
+
+  Clock                 ID
+  ----------------------------
+
+  fin_pll               1
+
+  [Clock Gate for Special Clocks]
+
+  Clock                 ID
+  ----------------------------
+
+  sclk_cam_bayer        128
+  sclk_cam0             129
+  sclk_cam1             130
+  sclk_gscl_wa          131
+  sclk_gscl_wb          132
+  sclk_fimd1            133
+  sclk_mipi1            134
+  sclk_dp               135
+  sclk_hdmi             136
+  sclk_pixel            137
+  sclk_audio0           138
+  sclk_mmc0             139
+  sclk_mmc1             140
+  sclk_mmc2             141
+  sclk_mmc3             142
+  sclk_sata             143
+  sclk_usb3             144
+  sclk_jpeg             145
+  sclk_uart0            146
+  sclk_uart1            147
+  sclk_uart2            148
+  sclk_uart3            149
+  sclk_pwm              150
+  sclk_audio1           151
+  sclk_audio2           152
+  sclk_spdif            153
+  sclk_spi0             154
+  sclk_spi1             155
+  sclk_spi2             156
+
+
+   [Peripheral Clock Gates]
+
+  Clock                 ID
+  ----------------------------
+
+  gscl0                 256
+  gscl1                 257
+  gscl2                 258
+  gscl3                 259
+  gscl_wa               260
+  gscl_wb               261
+  smmu_gscl0            262
+  smmu_gscl1            263
+  smmu_gscl2            264
+  smmu_gscl3            265
+  mfc                   266
+  smmu_mfcl             267
+  smmu_mfcr             268
+  rotator               269
+  jpeg                  270
+  mdma1                 271
+  smmu_rotator          272
+  smmu_jpeg             273
+  smmu_mdma1            274
+  pdma0                 275
+  pdma1                 276
+  sata                  277
+  usbotg                278
+  mipi_hsi              279
+  sdmmc0                280
+  sdmmc1                281
+  sdmmc2                282
+  sdmmc3                283
+  sromc                 284
+  usb2                  285
+  usb3                  286
+  sata_phyctrl          287
+  sata_phyi2c           288
+  uart0                 289
+  uart1                 290
+  uart2                 291
+  uart3                 292
+  uart4                 293
+  i2c0                  294
+  i2c1                  295
+  i2c2                  296
+  i2c3                  297
+  i2c4                  298
+  i2c5                  299
+  i2c6                  300
+  i2c7                  301
+  i2c_hdmi              302
+  adc                   303
+  spi0                  304
+  spi1                  305
+  spi2                  306
+  i2s1                  307
+  i2s2                  308
+  pcm1                  309
+  pcm2                  310
+  pwm                   311
+  spdif                 312
+  ac97                  313
+  hsi2c0                314
+  hsi2c1                315
+  hs12c2                316
+  hs12c3                317
+  chipid                318
+  sysreg                319
+  pmu                   320
+  cmu_top               321
+  cmu_core              322
+  cmu_mem               323
+  tzpc0                 324
+  tzpc1                 325
+  tzpc2                 326
+  tzpc3                 327
+  tzpc4                 328
+  tzpc5                 329
+  tzpc6                 330
+  tzpc7                 331
+  tzpc8                 332
+  tzpc9                 333
+  hdmi_cec              334
+  mct                   335
+  wdt                   336
+  rtc                   337
+  tmu                   338
+  fimd1                 339
+  mie1                  340
+  dsim0                 341
+  dp                    342
+  mixer                 343
+  hdmi                  345
+
+Example 1: An example of a clock controller node is listed below.
+
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5250-clock";
+                reg = <0x10010000 0x30000>;
+                #clock-cells = <1>;
+        };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+           controller. Refer to the standard clock bindings for information
+           about 'clocks' and 'clock-names' property.
+
+        serial@13820000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13820000 0x100>;
+                interrupts = <0 54 0>;
+                clocks = <&clock 314>, <&clock 153>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
new file mode 100644
index 000000000000..4499e9966bc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
@@ -0,0 +1,61 @@
+* Samsung Exynos5440 Clock Controller
+
+The Exynos5440 clock controller generates and supplies clock to various
+controllers within the Exynos5440 SoC.
+
+Required Properties:
+
+- comptible: should be "samsung,exynos5440-clock".
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume.
+
+
+       [Core Clocks]
+
+  Clock                 ID
+  ----------------------------
+
+  xtal                  1
+  arm_clk               2
+
+   [Peripheral Clock Gates]
+
+  Clock                 ID
+  ----------------------------
+
+  spi_baud              16
+  pb0_250               17
+  pr0_250               18
+  pr1_250               19
+  b_250                 20
+  b_125                 21
+  b_200                 22
+  sata                  23
+  usb                   24
+  gmac0                 25
+  cs250                 26
+  pb0_250_o             27
+  pr0_250_o             28
+  pr1_250_o             29
+  b_250_o               30
+  b_125_o               31
+  b_200_o               32
+  sata_o                33
+  usb_o                 34
+  gmac0_o               35
+  cs250_o               36
+
+Example: An example of a clock controller node is listed below.
+
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5440-clock";
+                reg = <0x160000 0x10000>;
+                #clock-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
new file mode 100644
index 000000000000..d6cb083b90a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -0,0 +1,303 @@
+NVIDIA Tegra114 Clock And Reset Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
+for muxing and gating Tegra's clocks, and setting their rates.
+
+Required properties :
+- compatible : Should be "nvidia,tegra114-car"
+- reg : Should contain CAR registers location and length
+- clocks : Should contain phandle and clock specifiers for two clocks:
+  the 32 KHz "32k_in", and the board-specific oscillator "osc".
+- #clock-cells : Should be 1.
+  In clock consumers, this cell represents the clock ID exposed by the CAR.
+
+  The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  registers. These IDs often match those in the CAR's RST_DEVICES registers,
+  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+  this case, those clocks are assigned IDs above 160 in order to highlight
+  this issue. Implementations that interpret these clock IDs as bit values
+  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+  explicitly handle these special cases.
+
+  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+  above.
+
+  0     unassigned
+  1     unassigned
+  2     unassigned
+  3     unassigned
+  4     rtc
+  5     timer
+  6     uarta
+  7     unassigned      (register bit affects uartb and vfir)
+  8     unassigned
+  9     sdmmc2
+  10    unassigned      (register bit affects spdif_in and spdif_out)
+  11    i2s1
+  12    i2c1
+  13    ndflash
+  14    sdmmc1
+  15    sdmmc4
+  16    unassigned
+  17    pwm
+  18    i2s2
+  19    epp
+  20    unassigned      (register bit affects vi and vi_sensor)
+  21    2d
+  22    usbd
+  23    isp
+  24    3d
+  25    unassigned
+  26    disp2
+  27    disp1
+  28    host1x
+  29    vcp
+  30    i2s0
+  31    unassigned
+
+  32    unassigned
+  33    unassigned
+  34    apbdma
+  35    unassigned
+  36    kbc
+  37    unassigned
+  38    unassigned
+  39    unassigned      (register bit affects fuse and fuse_burn)
+  40    kfuse
+  41    sbc1
+  42    nor
+  43    unassigned
+  44    sbc2
+  45    unassigned
+  46    sbc3
+  47    i2c5
+  48    dsia
+  49    unassigned
+  50    mipi
+  51    hdmi
+  52    csi
+  53    unassigned
+  54    i2c2
+  55    uartc
+  56    mipi-cal
+  57    emc
+  58    usb2
+  59    usb3
+  60    msenc
+  61    vde
+  62    bsea
+  63    bsev
+
+  64    unassigned
+  65    uartd
+  66    unassigned
+  67    i2c3
+  68    sbc4
+  69    sdmmc3
+  70    unassigned
+  71    owr
+  72    afi
+  73    csite
+  74    unassigned
+  75    unassigned
+  76    la
+  77    trace
+  78    soc_therm
+  79    dtv
+  80    ndspeed
+  81    i2cslow
+  82    dsib
+  83    tsec
+  84    unassigned
+  85    unassigned
+  86    unassigned
+  87    unassigned
+  88    unassigned
+  89    xusb_host
+  90    unassigned
+  91    msenc
+  92    csus
+  93    unassigned
+  94    unassigned
+  95    unassigned      (bit affects xusb_dev and xusb_dev_src)
+
+  96    unassigned
+  97    unassigned
+  98    unassigned
+  99    mselect
+  100   tsensor
+  101   i2s3
+  102   i2s4
+  103   i2c4
+  104   sbc5
+  105   sbc6
+  106   d_audio
+  107   apbif
+  108   dam0
+  109   dam1
+  110   dam2
+  111   hda2codec_2x
+  112   unassigned
+  113   audio0_2x
+  114   audio1_2x
+  115   audio2_2x
+  116   audio3_2x
+  117   audio4_2x
+  118   spdif_2x
+  119   actmon
+  120   extern1
+  121   extern2
+  122   extern3
+  123   unassigned
+  124   unassigned
+  125   hda
+  126   unassigned
+  127   se
+
+  128   hda2hdmi
+  129   unassigned
+  130   unassigned
+  131   unassigned
+  132   unassigned
+  133   unassigned
+  134   unassigned
+  135   unassigned
+  136   unassigned
+  137   unassigned
+  138   unassigned
+  139   unassigned
+  140   unassigned
+  141   unassigned
+  142   unassigned
+  143   unassigned      (bit affects xusb_falcon_src, xusb_fs_src,
+                         xusb_host_src and xusb_ss_src)
+  144   cilab
+  145   cilcd
+  146   cile
+  147   dsialp
+  148   dsiblp
+  149   unassigned
+  150   dds
+  151   unassigned
+  152   dp2
+  153   amx
+  154   adx
+  155   unassigned      (bit affects dfll_ref and dfll_soc)
+  156   xusb_ss
+
+  192   uartb
+  193   vfir
+  194   spdif_in
+  195   spdif_out
+  196   vi
+  197   vi_sensor
+  198   fuse
+  199   fuse_burn
+  200   clk_32k
+  201   clk_m
+  202   clk_m_div2
+  203   clk_m_div4
+  204   pll_ref
+  205   pll_c
+  206   pll_c_out1
+  207   pll_c2
+  208   pll_c3
+  209   pll_m
+  210   pll_m_out1
+  211   pll_p
+  212   pll_p_out1
+  213   pll_p_out2
+  214   pll_p_out3
+  215   pll_p_out4
+  216   pll_a
+  217   pll_a_out0
+  218   pll_d
+  219   pll_d_out0
+  220   pll_d2
+  221   pll_d2_out0
+  222   pll_u
+  223   pll_u_480M
+  224   pll_u_60M
+  225   pll_u_48M
+  226   pll_u_12M
+  227   pll_x
+  228   pll_x_out0
+  229   pll_re_vco
+  230   pll_re_out
+  231   pll_e_out0
+  232   spdif_in_sync
+  233   i2s0_sync
+  234   i2s1_sync
+  235   i2s2_sync
+  236   i2s3_sync
+  237   i2s4_sync
+  238   vimclk_sync
+  239   audio0
+  240   audio1
+  241   audio2
+  242   audio3
+  243   audio4
+  244   spdif
+  245   clk_out_1
+  246   clk_out_2
+  247   clk_out_3
+  248   blink
+  252   xusb_host_src
+  253   xusb_falcon_src
+  254   xusb_fs_src
+  255   xusb_ss_src
+  256   xusb_dev_src
+  257   xusb_dev
+  258   xusb_hs_src
+  259   sclk
+  260   hclk
+  261   pclk
+  262   cclk_g
+  263   cclk_lp
+  264   dfll_ref
+  265   dfll_soc
+
+Example SoC include file:
+
+/ {
+        tegra_car: clock {
+                compatible = "nvidia,tegra114-car";
+                reg = <0x60006000 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        usb@c5004000 {
+                clocks = <&tegra_car 58>; /* usb2 */
+        };
+};
+
+Example board file:
+
+/ {
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                osc: clock@0 {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <12000000>;
+                };
+
+                clk_32k: clock@1 {
+                        compatible = "fixed-clock";
+                        reg = <1>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
+        &tegra_car {
+                clocks = <&clk_32k> <&osc>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index 0921fac73528..e885680f6b45 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -120,8 +120,8 @@ Required properties :
   90    clk_d
   91    unassigned
   92    sus
-  93    cdev1
-  94    cdev2
+  93    cdev2
+  94    cdev1
   95    unassigned
 
   96    uart2
diff --git a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
deleted file mode 100644
index f4dc5233167e..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-VIA/Wondermedia VT8500 GPIO Controller
------------------------------------------------------
-
-Required properties:
-- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
-        or "wm,wm8650-gpio" depending on your SoC
-- reg : Should contain 1 register range (address and length)
-- #gpio-cells : should be <3>.
-        1) bank
-        2) pin number
-        3) flags - should be 0
-
-Example:
-
-        gpio: gpio-controller@d8110000 {
-                compatible = "via,vt8500-gpio";
-                gpio-controller;
-                reg = <0xd8110000 0x10000>;
-                #gpio-cells = <3>;
-        };
-
-        vibrate {
-                gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
-        };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
new file mode 100644
index 000000000000..c54c5a9a2a90
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
@@ -0,0 +1,53 @@
+Samsung S3C24XX Interrupt Controllers
+
+The S3C24XX SoCs contain a custom set of interrupt controllers providing a
+varying number of interrupt sources. The set consists of a main- and sub-
+controller and on newer SoCs even a second main controller.
+
+Required properties:
+- compatible: Compatible property value should be "samsung,s3c2410-irq"
+  for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
+
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+
+- interrupt-controller : Identifies the node as an interrupt controller
+
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 4 and interrupt descriptor shall
+  have the following format:
+      <ctrl_num parent_irq ctrl_irq type>
+
+  ctrl_num contains the controller to use:
+      - 0 ... main controller
+      - 1 ... sub controller
+      - 2 ... second main controller on s3c2416 and s3c2450
+  parent_irq contains the parent bit in the main controller and will be
+             ignored in main controllers
+  ctrl_irq contains the interrupt bit of the controller
+  type contains the trigger type to use
+
+Example:
+
+        interrupt-controller@4a000000 {
+                compatible = "samsung,s3c2410-irq";
+                reg = <0x4a000000 0x100>;
+                interrupt-controller;
+                #interrupt-cells=<4>;
+        };
+
+        [...]
+
+        serial@50000000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50000000 0x4000>;
+                interrupt-parent = <&subintc>;
+                interrupts = <1 28 0 4>, <1 28 1 4>;
+        };
+
+        rtc@57000000 {
+                compatible = "samsung,s3c2410-rtc";
+                reg = <0x57000000 0x100>;
+                interrupt-parent = <&intc>;
+                interrupts = <0 30 0 3>, <0 8 0 3>;
+        };
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index 67ec3d4ccc7f..bf0182d8da25 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -21,3 +21,24 @@ Required properties:
 
   - samsung,mfc-l : Base address of the second memory bank used by MFC
                     for DMA contiguous memory allocation and its size.
+
+Optional properties:
+  - samsung,power-domain : power-domain property defined with a phandle
+                           to respective power domain.
+
+Example:
+SoC specific DT entry:
+
+mfc: codec@13400000 {
+        compatible = "samsung,mfc-v5";
+        reg = <0x13400000 0x10000>;
+        interrupts = <0 94 0>;
+        samsung,power-domain = <&pd_mfc>;
+};
+
+Board specific DT entry:
+
+codec@13400000 {
+        samsung,mfc-r = <0x43000000 0x800000>;
+        samsung,mfc-l = <0x51000000 0x800000>;
+};
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nor.txt b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt
new file mode 100644
index 000000000000..420b3ab18890
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nor.txt
@@ -0,0 +1,98 @@
+Device tree bindings for NOR flash connect to TI GPMC
+
+NOR flash connected to the TI GPMC (found on OMAP boards) are represented as
+child nodes of the GPMC controller with a name of "nor".
+
+All timing relevant properties as well as generic GPMC child properties are
+explained in a separate documents. Please refer to
+Documentation/devicetree/bindings/bus/ti-gpmc.txt
+
+Required properties:
+- bank-width:           Width of NOR flash in bytes. GPMC supports 8-bit and
+                        16-bit devices and so must be either 1 or 2 bytes.
+- compatible:           Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+- gpmc,cs-on-ns:                Chip-select assertion time
+- gpmc,cs-rd-off-ns:    Chip-select de-assertion time for reads
+- gpmc,cs-wr-off-ns:    Chip-select de-assertion time for writes
+- gpmc,oe-on-ns:        Output-enable assertion time
+- gpmc,oe-off-ns:       Output-enable de-assertion time
+- gpmc,we-on-ns         Write-enable assertion time
+- gpmc,we-off-ns:       Write-enable de-assertion time
+- gpmc,access-ns:       Start cycle to first data capture (read access)
+- gpmc,rd-cycle-ns:     Total read cycle time
+- gpmc,wr-cycle-ns:     Total write cycle time
+- linux,mtd-name:       Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+- reg:                  Chip-select, base address (relative to chip-select)
+                        and size of NOR flash. Note that base address will be
+                        typically 0 as this is the start of the chip-select.
+
+Optional properties:
+- gpmc,XXX              Additional GPMC timings and settings parameters. See
+                        Documentation/devicetree/bindings/bus/ti-gpmc.txt
+
+Optional properties for partiton table parsing:
+- #address-cells: should be set to 1
+- #size-cells: should be set to 1
+
+Example:
+
+gpmc: gpmc@6e000000 {
+        compatible = "ti,omap3430-gpmc", "simple-bus";
+        ti,hwmods = "gpmc";
+        reg = <0x6e000000 0x1000>;
+        interrupts = <20>;
+        gpmc,num-cs = <8>;
+        gpmc,num-waitpins = <4>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+
+        ranges = <0 0 0x10000000 0x08000000>;
+
+        nor@0,0 {
+                compatible = "cfi-flash";
+                linux,mtd-name= "intel,pf48f6000m0y1be";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0 0 0x08000000>;
+                bank-width = <2>;
+
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <186>;
+                gpmc,cs-wr-off-ns = <186>;
+                gpmc,adv-on-ns = <12>;
+                gpmc,adv-rd-off-ns = <48>;
+                gpmc,adv-wr-off-ns = <48>;
+                gpmc,oe-on-ns = <54>;
+                gpmc,oe-off-ns = <168>;
+                gpmc,we-on-ns = <54>;
+                gpmc,we-off-ns = <168>;
+                gpmc,rd-cycle-ns = <186>;
+                gpmc,wr-cycle-ns = <186>;
+                gpmc,access-ns = <114>;
+                gpmc,page-burst-access-ns = <6>;
+                gpmc,bus-turnaround-ns = <12>;
+                gpmc,cycle2cycle-delay-ns = <18>;
+                gpmc,wr-data-mux-bus-ns = <90>;
+                gpmc,wr-access-ns = <186>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+
+                partition@0 {
+                        label = "bootloader-nor";
+                        reg = <0 0x40000>;
+                };
+                partition@0x40000 {
+                        label = "params-nor";
+                        reg = <0x40000 0x40000>;
+                };
+                partition@0x80000 {
+                        label = "kernel-nor";
+                        reg = <0x80000 0x200000>;
+                };
+                partition@0x280000 {
+                        label = "filesystem-nor";
+                        reg = <0x240000 0x7d80000>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
index deec9da224a2..b7529424ac88 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
@@ -10,6 +10,8 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt
 Required properties:
 
  - reg:                 The CS line the peripheral is connected to
+ - gpmc,device-width    Width of the ONENAND device connected to the GPMC
+                        in bytes. Must be 1 or 2.
 
 Optional properties:
 
@@ -34,6 +36,7 @@ Example for an OMAP3430 board:
 
                 onenand@0 {
                         reg = <0 0 0>; /* CS0, offset 0 */
+                        gpmc,device-width = <2>;
 
                         #address-cells = <1>;
                         #size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/net/gpmc-eth.txt b/Documentation/devicetree/bindings/net/gpmc-eth.txt
new file mode 100644
index 000000000000..24cb4e46f675
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/gpmc-eth.txt
@@ -0,0 +1,97 @@
+Device tree bindings for Ethernet chip connected to TI GPMC
+
+Besides being used to interface with external memory devices, the
+General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
+such as ethernet controllers to processors using the TI GPMC as a data bus.
+
+Ethernet controllers connected to TI GPMC are represented as child nodes of
+the GPMC controller with an "ethernet" name.
+
+All timing relevant properties as well as generic GPMC child properties are
+explained in a separate documents. Please refer to
+Documentation/devicetree/bindings/bus/ti-gpmc.txt
+
+For the properties relevant to the ethernet controller connected to the GPMC
+refer to the binding documentation of the device. For example, the documentation
+for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt
+
+Child nodes need to specify the GPMC bus address width using the "bank-width"
+property but is possible that an ethernet controller also has a property to
+specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
+address width, it supports devices with 32-bit word registers.
+For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
+OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
+
+Required properties:
+- bank-width:           Address width of the device in bytes. GPMC supports 8-bit
+                        and 16-bit devices and so must be either 1 or 2 bytes.
+- compatible:           Compatible string property for the ethernet child device.
+- gpmc,cs-on:           Chip-select assertion time
+- gpmc,cs-rd-off:       Chip-select de-assertion time for reads
+- gpmc,cs-wr-off:       Chip-select de-assertion time for writes
+- gpmc,oe-on:           Output-enable assertion time
+- gpmc,oe-off           Output-enable de-assertion time
+- gpmc,we-on:           Write-enable assertion time
+- gpmc,we-off:          Write-enable de-assertion time
+- gpmc,access:          Start cycle to first data capture (read access)
+- gpmc,rd-cycle:        Total read cycle time
+- gpmc,wr-cycle:        Total write cycle time
+- reg:                  Chip-select, base address (relative to chip-select)
+                        and size of the memory mapped for the device.
+                        Note that base address will be typically 0 as this
+                        is the start of the chip-select.
+
+Optional properties:
+- gpmc,XXX              Additional GPMC timings and settings parameters. See
+                        Documentation/devicetree/bindings/bus/ti-gpmc.txt
+
+Example:
+
+gpmc: gpmc@6e000000 {
+        compatible = "ti,omap3430-gpmc";
+        ti,hwmods = "gpmc";
+        reg = <0x6e000000 0x1000>;
+        interrupts = <20>;
+        gpmc,num-cs = <8>;
+        gpmc,num-waitpins = <4>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+
+        ranges = <5 0 0x2c000000 0x1000000>;
+
+        ethernet@5,0 {
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                reg = <5 0 0xff>;
+                bank-width = <2>;
+
+                gpmc,mux-add-data;
+                gpmc,cs-on = <0>;
+                gpmc,cs-rd-off = <186>;
+                gpmc,cs-wr-off = <186>;
+                gpmc,adv-on = <12>;
+                gpmc,adv-rd-off = <48>;
+                gpmc,adv-wr-off = <48>;
+                gpmc,oe-on = <54>;
+                gpmc,oe-off = <168>;
+                gpmc,we-on = <54>;
+                gpmc,we-off = <168>;
+                gpmc,rd-cycle = <186>;
+                gpmc,wr-cycle = <186>;
+                gpmc,access = <114>;
+                gpmc,page-burst-access = <6>;
+                gpmc,bus-turnaround = <12>;
+                gpmc,cycle2cycle-delay = <18>;
+                gpmc,wr-data-mux-bus = <90>;
+                gpmc,wr-access = <186>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+
+                interrupt-parent = <&gpio6>;
+                interrupts = <16>;
+                vmmc-supply = <&vddvario>;
+                vmmc_aux-supply = <&vdd33a>;
+                reg-io-width = <4>;
+
+                smsc,save-mac-address;
+        };
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
new file mode 100644
index 000000000000..b3aa90f0ce44
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
@@ -0,0 +1,57 @@
+VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
+
+These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
+either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
+
+Required properties:
+- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
+        "wm8750-pinctrl" or "wm,wm8850-pinctrl"
+- reg: Should contain the physical address of the module's registers.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be two.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells : Should be two. The first cell is the pin number and the
+  second cell is used to specify optional parameters.
+        bit 0 - active low
+
+Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Each pin configuration node lists the pin(s) to which it applies, and one or
+more of the mux functions to select on those pin(s), and pull-up/down
+configuration. Each subnode only affects those parameters that are explicitly
+listed. In other words, a subnode that lists only a mux function implies no
+information about any pull configuration. Similarly, a subnode that lists only
+a pull parameter implies no information about the mux function.
+
+Required subnode-properties:
+- wm,pins: An array of cells. Each cell contains the ID of a pin.
+
+Optional subnode-properties:
+- wm,function: Integer, containing the function to mux to the pin(s):
+  0: GPIO in
+  1: GPIO out
+  2: alternate
+
+- wm,pull: Integer, representing the pull-down/up to apply to the pin(s):
+  0: none
+  1: down
+  2: up
+
+Each of wm,function and wm,pull may contain either a single value which
+will be applied to all pins in wm,pins, or one value for each entry in
+wm,pins.
+
+Example:
+
+        pinctrl: pinctrl {
+                compatible = "wm,wm8505-pinctrl";
+                reg = <0xD8110000 0x10000>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
diff --git a/Documentation/devicetree/bindings/reset/reset.txt b/Documentation/devicetree/bindings/reset/reset.txt
new file mode 100644
index 000000000000..31db6ff84908
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/reset.txt
@@ -0,0 +1,75 @@
+= Reset Signal Device Tree Bindings =
+
+This binding is intended to represent the hardware reset signals present
+internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
+standalone chips are most likely better represented as GPIOs, although there
+are likely to be exceptions to this rule.
+
+Hardware blocks typically receive a reset signal. This signal is generated by
+a reset provider (e.g. power management or clock module) and received by a
+reset consumer (the module being reset, or a module managing when a sub-
+ordinate module is reset). This binding exists to represent the provider and
+consumer, and provide a way to couple the two together.
+
+A reset signal is represented by the phandle of the provider, plus a reset
+specifier - a list of DT cells that represents the reset signal within the
+provider. The length (number of cells) and semantics of the reset specifier
+are dictated by the binding of the reset provider, although common schemes
+are described below.
+
+A word on where to place reset signal consumers in device tree: It is possible
+in hardware for a reset signal to affect multiple logically separate HW blocks
+at once. In this case, it would be unwise to represent this reset signal in
+the DT node of each affected HW block, since if activated, an unrelated block
+may be reset. Instead, reset signals should be represented in the DT node
+where it makes most sense to control it; this may be a bus node if all
+children of the bus are affected by the reset signal, or an individual HW
+block node for dedicated reset signals. The intent of this binding is to give
+appropriate software access to the reset signals in order to manage the HW,
+rather than to slavishly enumerate the reset signal that affects each HW
+block.
+
+= Reset providers =
+
+Required properties:
+#reset-cells:   Number of cells in a reset specifier; Typically 0 for nodes
+                with a single reset output and 1 for nodes with multiple
+                reset outputs.
+
+For example:
+
+        rst: reset-controller {
+                #reset-cells = <1>;
+        };
+
+= Reset consumers =
+
+Required properties:
+resets:         List of phandle and reset specifier pairs, one pair
+                for each reset signal that affects the device, or that the
+                device manages. Note: if the reset provider specifies '0' for
+                #reset-cells, then only the phandle portion of the pair will
+                appear.
+
+Optional properties:
+reset-names:    List of reset signal name strings sorted in the same order as
+                the resets property. Consumers drivers will use reset-names to
+                match reset signal names with reset specifiers.
+
+For example:
+
+        device {
+                resets = <&rst 20>;
+                reset-names = "reset";
+        };
+
+This represents a device with a single reset signal named "reset".
+
+        bus {
+                resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>;
+                reset-names = "i2s1", "i2s2", "dma", "mixer";
+        };
+
+This represents a bus that controls the reset signal of each of four sub-
+ordinate devices. Consider for example a bus that fails to operate unless no
+child device has reset asserted.
diff --git a/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
new file mode 100644
index 000000000000..993695c659e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
@@ -0,0 +1,17 @@
+Cadence TTC - Triple Timer Counter
+
+Required properties:
+- compatible : Should be "cdns,ttc".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 3 interrupts; one per timer channel.
+- clocks: phandle to the source clock
+
+Example:
+
+ttc0: ttc0@f8001000 {
+        interrupt-parent = <&intc>;
+        interrupts = < 0 10 4 0 11 4 0 12 4 >;
+        compatible = "cdns,ttc";
+        reg = <0xF8001000 0x1000>;
+        clocks = <&cpu_clk 3>;
+};
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
new file mode 100644
index 000000000000..cb47bfbcaeea
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -0,0 +1,68 @@
+Samsung's Multi Core Timer (MCT)
+
+The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
+global timer and CPU local timers. The global timer is a 64-bit free running
+up-counter and can generate 4 interrupts when the counter reaches one of the
+four preset counter values. The CPU local timers are 32-bit free running
+down-counters and generate an interrupt when the counter expires. There is
+one CPU local timer instantiated in MCT for every CPU in the system.
+
+Required properties:
+
+- compatible: should be "samsung,exynos4210-mct".
+  (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
+  (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
+
+- reg: base address of the mct controller and length of the address space
+  it occupies.
+
+- interrupts: the list of interrupts generated by the controller. The following
+  should be the order of the interrupts specified. The local timer interrupts
+  should be specified after the four global timer interrupts have been
+  specified.
+
+        0: Global Timer Interrupt 0
+        1: Global Timer Interrupt 1
+        2: Global Timer Interrupt 2
+        3: Global Timer Interrupt 3
+        4: Local Timer Interrupt 0
+        5: Local Timer Interrupt 1
+        6: ..
+        7: ..
+        i: Local Timer Interrupt n
+
+Example 1: In this example, the system uses only the first global timer
+           interrupt generated by MCT and the remaining three global timer
+           interrupts are unused. Two local timer interrupts have been
+           specified.
+
+        mct@10050000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x10050000 0x800>;
+                interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+                             <0 42 0>, <0 48 0>;
+        };
+
+Example 2: In this example, the MCT global and local timer interrupts are
+           connected to two seperate interrupt controllers. Hence, an
+           interrupt-map is created to map the interrupts to the respective
+           interrupt controllers.
+
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 3>,
+                                        <0x4 0 &gic 0 120 0>,
+                                        <0x5 0 &gic 0 121 0>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
new file mode 100644
index 000000000000..f66fcddba46f
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -0,0 +1,40 @@
+Samsung Exynos SoC USB controller
+
+The USB devices interface with USB controllers on Exynos SOCs.
+The device node has following properties.
+
+EHCI
+Required properties:
+ - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
+   EHCI controller in host mode.
+ - reg: physical base address of the controller and length of memory mapped
+   region.
+ - interrupts: interrupt number to the cpu.
+
+Optional properties:
+ - samsung,vbus-gpio:  if present, specifies the GPIO that
+   needs to be pulled up for the bus to be powered.
+
+Example:
+
+        usb@12110000 {
+                compatible = "samsung,exynos4210-ehci";
+                reg = <0x12110000 0x100>;
+                interrupts = <0 71 0>;
+                samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+        };
+
+OHCI
+Required properties:
+ - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
+   OHCI companion controller in host mode.
+ - reg: physical base address of the controller and length of memory mapped
+   region.
+ - interrupts: interrupt number to the cpu.
+
+Example:
+        usb@12120000 {
+                compatible = "samsung,exynos4210-ohci";
+                reg = <0x12120000 0x100>;
+                interrupts = <0 71 0>;
+        };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 62079d434581..1e31dac36a5f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -689,12 +689,15 @@ config ARCH_SA1100
 config ARCH_S3C24XX
         bool "Samsung S3C24XX SoCs"
         select ARCH_HAS_CPUFREQ
-        select ARCH_USES_GETTIMEOFFSET
+        select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
+        select MULTI_IRQ_HANDLER
         select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
         help
@@ -707,10 +710,11 @@ config ARCH_S3C64XX
         bool "Samsung S3C64XX"
         select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
-        select ARCH_USES_GETTIMEOFFSET
         select ARM_VIC
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select CPU_V6
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -744,9 +748,11 @@ config ARCH_S5P64X0
 
 config ARCH_S5PC100
         bool "Samsung S5PC100"
-        select ARCH_USES_GETTIMEOFFSET
+        select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select CPU_V7
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -779,6 +785,7 @@ config ARCH_EXYNOS
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_SPARSEMEM_ENABLE
         select CLKDEV_LOOKUP
+        select COMMON_CLK
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
@@ -1552,7 +1559,8 @@ config ARCH_NR_GPIO
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
         default 512 if SOC_OMAP5
         default 392 if ARCH_U8500
-        default 288 if ARCH_VT8500 || ARCH_SUNXI
+        default 352 if ARCH_VT8500
+        default 288 if ARCH_SUNXI
         default 264 if MACH_H4700
         default 0
         help
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 20358fb43450..55196639211d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -49,7 +49,10 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
+        exynos4412-odroidx.dtb \
         exynos4412-smdk4412.dtb \
+        exynos4412-origen.dtb \
+        exynos5250-arndale.dtb \
         exynos5250-smdk5250.dtb \
         exynos5250-snow.dtb \
         exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index 46c098017036..62eceb4f0d3f 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -24,6 +24,144 @@
                 samsung,i2c-max-bus-freq = <378000>;
                 gpios = <&gpb3 0 2 3 0>,
                         <&gpb3 1 2 3 0>;
+
+                max77686@09 {
+                        compatible = "maxim,max77686";
+                        reg = <0x09>;
+
+                        voltage-regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "P1.0V_LDO_OUT1";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "P1.8V_LDO_OUT2";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "P1.8V_LDO_OUT3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "P1.1V_LDO_OUT7";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "P1.0V_LDO_OUT8";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "P1.8V_LDO_OUT10";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "P3.0V_LDO_OUT12";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "P1.8V_LDO_OUT14";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "P1.0V_LDO_OUT15";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "P1.8V_LDO_OUT16";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "P1.8V_BUCK_OUT5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "P1.35V_BUCK_OUT6";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                };
+
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "P2.0V_BUCK_OUT7";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        regulator-always-on;
+                                };
+
+                                buck8_reg: BUCK8 {
+                                        regulator-name = "P2.85V_BUCK_OUT8";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
         };
 
         i2c@12C70000 {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 1a62bcf18aa3..9ac47d51c407 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -86,6 +86,8 @@
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x10060000 0x100>;
                 interrupts = <0 43 0>;
+                clocks = <&clock 345>;
+                clock-names = "watchdog";
                 status = "disabled";
         };
 
@@ -93,6 +95,8 @@
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x10070000 0x100>;
                 interrupts = <0 44 0>, <0 45 0>;
+                clocks = <&clock 346>;
+                clock-names = "rtc";
                 status = "disabled";
         };
 
@@ -100,6 +104,8 @@
                 compatible = "samsung,s5pv210-keypad";
                 reg = <0x100A0000 0x100>;
                 interrupts = <0 109 0>;
+                clocks = <&clock 347>;
+                clock-names = "keypad";
                 status = "disabled";
         };
 
@@ -107,6 +113,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12510000 0x100>;
                 interrupts = <0 73 0>;
+                clocks = <&clock 297>, <&clock 145>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -114,6 +122,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12520000 0x100>;
                 interrupts = <0 74 0>;
+                clocks = <&clock 298>, <&clock 146>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -121,6 +131,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12530000 0x100>;
                 interrupts = <0 75 0>;
+                clocks = <&clock 299>, <&clock 147>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -128,6 +140,16 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12540000 0x100>;
                 interrupts = <0 76 0>;
+                clocks = <&clock 300>, <&clock 148>;
+                clock-names = "hsmmc", "mmc_busclk.2";
+                status = "disabled";
+        };
+
+        mfc: codec@13400000 {
+                compatible = "samsung,mfc-v5";
+                reg = <0x13400000 0x10000>;
+                interrupts = <0 94 0>;
+                samsung,power-domain = <&pd_mfc>;
                 status = "disabled";
         };
 
@@ -135,6 +157,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13800000 0x100>;
                 interrupts = <0 52 0>;
+                clocks = <&clock 312>, <&clock 151>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -142,6 +166,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13810000 0x100>;
                 interrupts = <0 53 0>;
+                clocks = <&clock 313>, <&clock 152>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -149,6 +175,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13820000 0x100>;
                 interrupts = <0 54 0>;
+                clocks = <&clock 314>, <&clock 153>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -156,6 +184,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13830000 0x100>;
                 interrupts = <0 55 0>;
+                clocks = <&clock 315>, <&clock 154>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -165,6 +195,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13860000 0x100>;
                 interrupts = <0 58 0>;
+                clocks = <&clock 317>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -174,6 +206,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13870000 0x100>;
                 interrupts = <0 59 0>;
+                clocks = <&clock 318>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -183,6 +217,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13880000 0x100>;
                 interrupts = <0 60 0>;
+                clocks = <&clock 319>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -192,6 +228,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13890000 0x100>;
                 interrupts = <0 61 0>;
+                clocks = <&clock 320>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -201,6 +239,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138A0000 0x100>;
                 interrupts = <0 62 0>;
+                clocks = <&clock 321>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -210,6 +250,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138B0000 0x100>;
                 interrupts = <0 63 0>;
+                clocks = <&clock 322>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -219,6 +261,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138C0000 0x100>;
                 interrupts = <0 64 0>;
+                clocks = <&clock 323>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -228,6 +272,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138D0000 0x100>;
                 interrupts = <0 65 0>;
+                clocks = <&clock 324>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -239,6 +285,8 @@
                 rx-dma-channel = <&pdma0 6>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 327>, <&clock 159>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -250,6 +298,8 @@
                 rx-dma-channel = <&pdma1 6>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 328>, <&clock 160>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -261,6 +311,8 @@
                 rx-dma-channel = <&pdma0 8>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 329>, <&clock 161>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -275,6 +327,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12680000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 292>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -284,6 +338,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12690000 0x1000>;
                         interrupts = <0 36 0>;
+                        clocks = <&clock 293>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -293,6 +349,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12850000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 279>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index f2710018e84e..1b30bc8e2654 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -57,6 +57,12 @@
                 status = "okay";
         };
 
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -121,4 +127,16 @@
                         linux,default-trigger = "heartbeat";
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index f63490707f3a..f52c86e2d424 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -43,6 +43,12 @@
                 status = "okay";
         };
 
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -189,4 +195,16 @@
                         };
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <12000000>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index c346b64dff55..9a14484c7bb1 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -289,4 +289,16 @@
                         };
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 2feffc70814c..15143bdbafb8 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -47,6 +47,42 @@
                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
         };
 
+        mct@10050000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &gic 0 69 0>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 0 42 0>,
+                                        <0x5 0 &gic 0 48 0>;
+                };
+        };
+
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4210-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupt-parent = <&combiner>;
+                interrupts = <2 2>, <3 2>;
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4210-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c6ae2005961f..36d4299789ef 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,4 +25,26 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
new file mode 100644
index 000000000000..53bc8bf77984
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -0,0 +1,111 @@
+/*
+ * Hardkernel's Exynos4412 based ODROID-X board device tree source
+ *
+ * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
+ *
+ * Device tree source file for Hardkernel's ODROID-X board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+        model = "Hardkernel ODROID-X board based on Exynos4412";
+        compatible = "hardkernel,odroid-x", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led1 {
+                        label = "led1:heart";
+                        gpios = <&gpc1 0 1>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led2 {
+                        label = "led2:mmc0";
+                        gpios = <&gpc1 2 1>;
+                        default-state = "on";
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        mshc@12550000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        regulator_p3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "p3v3_en";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpa1 1 1>;
+                enable-active-high;
+                regulator-boot-on;
+        };
+
+        rtc@10070000 {
+                status = "okay";
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
new file mode 100644
index 000000000000..1fecf7666dc0
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -0,0 +1,432 @@
+/*
+ * Insignal's Exynos4412 based Origen board device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Insignal's Origen board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+        model = "Insignal Origen evaluation board based on Exynos4412";
+        compatible = "insignal,origen4412", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs ="console=ttySAC2,115200";
+        };
+
+        mmc_reg: voltage-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "VMEM_VDD_2.8V";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpx1 1 0>;
+                enable-active-high;
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
+                pinctrl-names = "default";
+                vmmc-supply = <&mmc_reg>;
+                status = "okay";
+        };
+
+        mshc@12550000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        i2c@13860000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                s5m8767_pmic@66 {
+                        compatible = "samsung,s5m8767-pmic";
+                        reg = <0x66>;
+
+                        s5m8767,pmic-buck-default-dvs-idx = <3>;
+
+                        s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
+                                                         <&gpx2 4 0>,
+                                                         <&gpx2 5 0>;
+
+                        s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
+                                                        <&gpm3 6 0>,
+                                                        <&gpm3 7 0>;
+
+                        s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
+                                                         <1100000>, <1100000>,
+                                                         <1100000>, <1100000>,
+                                                         <1100000>, <1100000>;
+
+                        s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ALIVE";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDDQ_M12";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VDDIOAP_18";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDDQ_PRE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VDD18_2M";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VDD10_MPLL";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD10_XPLL";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VDD10_MIPI";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "VDD33_LCD";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VDD18_MIPI";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD18_ABB1";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "VDD33_UOTG";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "VDDIOPERI_18";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "VDD18_ABB02";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "VDD10_USH";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VDD18_HSIC";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "VDDIOAP_MMC012_28";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo18_reg: LDO18 {
+                                        regulator-name = "VDDIOPERI_28";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo19_reg: LDO19 {
+                                        regulator-name = "DVDD25";
+                                        regulator-min-microvolt = <2500000>;
+                                        regulator-max-microvolt = <2500000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo20_reg: LDO20 {
+                                        regulator-name = "VDD28_CAM";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "VDD28_AF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo22_reg: LDO22 {
+                                        regulator-name = "VDDA28_2M";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo23_reg: LDO23 {
+                                        regulator-name = "VDD28_TF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo24_reg: LDO24 {
+                                        regulator-name = "VDD33_A31";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo25_reg: LDO25 {
+                                        regulator-name = "VDD18_CAM";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo26_reg: LDO26 {
+                                        regulator-name = "VDD18_A31";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo27_reg: LDO27 {
+                                        regulator-name = "GPS_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo28_reg: LDO28 {
+                                        regulator-name = "DVDD12";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <925000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "vdd_m12";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "vdd12_5m";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck9_reg: BUCK9 {
+                                        regulator-name = "vddf28_emmc";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+                        };
+                };
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index f05bf575cc45..874beeaef99d 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -27,6 +27,19 @@
                 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
         };
 
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -42,4 +55,16 @@
         serial@13830000 {
                 status = "okay";
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d7dfe312772a..d75c047e80a9 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,4 +25,30 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x4000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>, <6 0>, <7 0>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>,
+                                        <0x6 0 &gic 1 12 0>,
+                                        <0x7 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 9a8780694909..7496b8d633ea 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -36,6 +36,12 @@
                              <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
         };
 
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4412-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4x12-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
new file mode 100644
index 000000000000..5de019cb0e58
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -0,0 +1,129 @@
+/*
+ * Samsung's Exynos5250 based Arndale board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+        model = "Insignal Arndale evaluation board based on EXYNOS5250";
+        compatible = "insignal,arndale", "samsung,exynos5250";
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC2,115200";
+        };
+
+        i2c@12C60000 {
+                status = "disabled";
+        };
+
+        i2c@12C70000 {
+                status = "disabled";
+        };
+
+        i2c@12C80000 {
+                status = "disabled";
+        };
+
+        i2c@12C90000 {
+                status = "disabled";
+        };
+
+        i2c@12CA0000 {
+                status = "disabled";
+        };
+
+        i2c@12CB0000 {
+                status = "disabled";
+        };
+
+        i2c@12CC0000 {
+                status = "disabled";
+        };
+
+        i2c@12CD0000 {
+                status = "disabled";
+        };
+
+        i2c@121D0000 {
+                status = "disabled";
+        };
+
+        dwmmc_0: dwmmc0@12200000 {
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                        gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+                                <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+                                <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
+                                <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+                                <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
+                };
+        };
+
+        dwmmc_1: dwmmc1@12210000 {
+                status = "disabled";
+        };
+
+        dwmmc_2: dwmmc2@12220000 {
+                num-slots = <1>;
+                supports-highspeed;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                        samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+                        gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+                                <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+                                <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
+                };
+        };
+
+        dwmmc_3: dwmmc3@12230000 {
+                status = "disabled";
+        };
+
+        spi_0: spi@12d20000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@12d30000 {
+                status = "disabled";
+        };
+
+        spi_2: spi@12d40000 {
+                status = "disabled";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 1b8d4106d338..872ae1f93c75 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -231,4 +231,24 @@
                 samsung,i2s-controller = <&i2s0>;
                 samsung,audio-codec = <&wm8994>;
         };
+
+        usb@12110000 {
+                samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+        };
+
+        dp-controller {
+                samsung,color-space = <0>;
+                samsung,dynamic-range = <0>;
+                samsung,ycbcr-coeff = <0>;
+                samsung,color-depth = <1>;
+                samsung,link-rate = <0x0a>;
+                samsung,lane-count = <4>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 17dd951c1cd2..babd9f9b1bf9 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -40,4 +40,15 @@
                                 <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
                 };
         };
+
+        usb@12110000 {
+                samsung,vbus-gpio = <&gpx1 1 1 3 3>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b1ac73e21c80..28758e5dd15c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -46,6 +46,22 @@
                 i2c8 = &i2c_8;
         };
 
+        pd_gsc: gsc-power-domain@0x10044000 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044000 0x20>;
+        };
+
+        pd_mfc: mfc-power-domain@0x10044040 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044040 0x20>;
+        };
+
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5250-clock";
+                reg = <0x10010000 0x30000>;
+                #clock-cells = <1>;
+        };
+
         gic:interrupt-controller@10481000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -69,58 +85,106 @@
                              <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
         };
 
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+                clocks = <&clock 1>, <&clock 335>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 3>,
+                                        <0x1 0 &combiner 23 4>,
+                                        <0x2 0 &combiner 25 2>,
+                                        <0x3 0 &combiner 25 3>,
+                                        <0x4 0 &gic 0 120 0>,
+                                        <0x5 0 &gic 0 121 0>;
+                };
+        };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu";
+                interrupt-parent = <&combiner>;
+                interrupts = <1 2>, <22 4>;
+        };
+
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x101D0000 0x100>;
                 interrupts = <0 42 0>;
+                clocks = <&clock 336>;
+                clock-names = "watchdog";
         };
 
         codec@11000000 {
                 compatible = "samsung,mfc-v6";
                 reg = <0x11000000 0x10000>;
                 interrupts = <0 96 0>;
+                samsung,power-domain = <&pd_mfc>;
         };
 
         rtc {
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x101E0000 0x100>;
                 interrupts = <0 43 0>, <0 44 0>;
+                clocks = <&clock 337>;
+                clock-names = "rtc";
+                status = "disabled";
         };
 
         tmu@10060000 {
                 compatible = "samsung,exynos5250-tmu";
                 reg = <0x10060000 0x100>;
                 interrupts = <0 65 0>;
+                clocks = <&clock 338>;
+                clock-names = "tmu_apbif";
         };
 
         serial@12C00000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C00000 0x100>;
                 interrupts = <0 51 0>;
+                clocks = <&clock 289>, <&clock 146>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C10000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C10000 0x100>;
                 interrupts = <0 52 0>;
+                clocks = <&clock 290>, <&clock 147>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C20000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C20000 0x100>;
                 interrupts = <0 53 0>;
+                clocks = <&clock 291>, <&clock 148>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C30000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C30000 0x100>;
                 interrupts = <0 54 0>;
+                clocks = <&clock 292>, <&clock 149>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         sata@122F0000 {
                 compatible = "samsung,exynos5-sata-ahci";
                 reg = <0x122F0000 0x1ff>;
                 interrupts = <0 115 0>;
+                clocks = <&clock 277>, <&clock 143>;
+                clock-names = "sata", "sclk_sata";
         };
 
         sata-phy@12170000 {
@@ -134,6 +198,8 @@
                 interrupts = <0 56 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 294>;
+                clock-names = "i2c";
         };
 
         i2c_1: i2c@12C70000 {
@@ -142,6 +208,8 @@
                 interrupts = <0 57 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 295>;
+                clock-names = "i2c";
         };
 
         i2c_2: i2c@12C80000 {
@@ -150,6 +218,8 @@
                 interrupts = <0 58 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 296>;
+                clock-names = "i2c";
         };
 
         i2c_3: i2c@12C90000 {
@@ -158,6 +228,8 @@
                 interrupts = <0 59 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 297>;
+                clock-names = "i2c";
         };
 
         i2c_4: i2c@12CA0000 {
@@ -166,6 +238,8 @@
                 interrupts = <0 60 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 298>;
+                clock-names = "i2c";
         };
 
         i2c_5: i2c@12CB0000 {
@@ -174,6 +248,8 @@
                 interrupts = <0 61 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 299>;
+                clock-names = "i2c";
         };
 
         i2c_6: i2c@12CC0000 {
@@ -182,6 +258,8 @@
                 interrupts = <0 62 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 300>;
+                clock-names = "i2c";
         };
 
         i2c_7: i2c@12CD0000 {
@@ -190,6 +268,8 @@
                 interrupts = <0 63 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 301>;
+                clock-names = "i2c";
         };
 
         i2c_8: i2c@12CE0000 {
@@ -198,6 +278,8 @@
                 interrupts = <0 64 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 302>;
+                clock-names = "i2c";
         };
 
         i2c@121D0000 {
@@ -205,6 +287,8 @@
                 reg = <0x121D0000 0x100>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 288>;
+                clock-names = "i2c";
         };
 
         spi_0: spi@12d20000 {
@@ -216,6 +300,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 304>, <&clock 154>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         spi_1: spi@12d30000 {
@@ -227,6 +313,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 305>, <&clock 155>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         spi_2: spi@12d40000 {
@@ -238,6 +326,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 306>, <&clock 156>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         dwmmc_0: dwmmc0@12200000 {
@@ -246,6 +336,8 @@
                 interrupts = <0 75 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 280>, <&clock 139>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_1: dwmmc1@12210000 {
@@ -254,6 +346,8 @@
                 interrupts = <0 76 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 281>, <&clock 140>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_2: dwmmc2@12220000 {
@@ -262,6 +356,8 @@
                 interrupts = <0 77 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 282>, <&clock 141>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_3: dwmmc3@12230000 {
@@ -270,6 +366,8 @@
                 interrupts = <0 78 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 283>, <&clock 142>;
+                clock-names = "biu", "ciu";
         };
 
         i2s0: i2s@03830000 {
@@ -301,6 +399,18 @@
                 dma-names = "tx", "rx";
         };
 
+        usb@12110000 {
+                compatible = "samsung,exynos4210-ehci";
+                reg = <0x12110000 0x100>;
+                interrupts = <0 71 0>;
+        };
+
+        usb@12120000 {
+                compatible = "samsung,exynos4210-ohci";
+                reg = <0x12120000 0x100>;
+                interrupts = <0 71 0>;
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -312,6 +422,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121A0000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 275>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -321,6 +433,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121B0000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 276>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -330,6 +444,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x10800000 0x1000>;
                         interrupts = <0 33 0>;
+                        clocks = <&clock 271>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
@@ -339,6 +455,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x11C10000 0x1000>;
                         interrupts = <0 124 0>;
+                        clocks = <&clock 271>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
@@ -592,34 +710,51 @@
                 };
         };
 
+
         gsc_0:  gsc@0x13e00000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e00000 0x1000>;
                 interrupts = <0 85 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 256>;
+                clock-names = "gscl";
         };
 
         gsc_1:  gsc@0x13e10000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e10000 0x1000>;
                 interrupts = <0 86 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 257>;
+                clock-names = "gscl";
         };
 
         gsc_2:  gsc@0x13e20000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e20000 0x1000>;
                 interrupts = <0 87 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 258>;
+                clock-names = "gscl";
         };
 
         gsc_3:  gsc@0x13e30000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e30000 0x1000>;
                 interrupts = <0 88 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 259>;
+                clock-names = "gscl";
         };
 
         hdmi {
                 compatible = "samsung,exynos5-hdmi";
                 reg = <0x14530000 0x70000>;
                 interrupts = <0 95 0>;
+                clocks = <&clock 333>, <&clock 136>, <&clock 137>,
+                                <&clock 333>, <&clock 333>;
+                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
+                                "sclk_hdmiphy", "hdmiphy";
         };
 
         mixer {
@@ -627,4 +762,18 @@
                 reg = <0x14450000 0x10000>;
                 interrupts = <0 94 0>;
         };
+
+        dp-controller {
+                compatible = "samsung,exynos5-dp";
+                reg = <0x145b0000 0x1000>;
+                interrupts = <10 3>;
+                interrupt-parent = <&combiner>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                dptx-phy {
+                        reg = <0x10040720>;
+                        samsung,enable-mask = <1>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index 81e2c964a900..a21eb4cbe893 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -28,19 +28,10 @@
                 status = "disabled";
         };
 
-        i2c@F0000 {
-                status = "disabled";
-        };
-
-        i2c@100000 {
-                status = "disabled";
-        };
-
-        watchdog {
-                status = "disabled";
-        };
-
-        rtc {
-                status = "disabled";
+        fixed-rate-clocks {
+                xtal {
+                        compatible = "samsung,clock-xtal";
+                        clock-frequency = <50000000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 9a99755920c0..48cc96aa0b5f 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -16,6 +16,12 @@
 
         interrupt-parent = <&gic>;
 
+        clock: clock-controller@0x160000 {
+                compatible = "samsung,exynos5440-clock";
+                reg = <0x160000 0x1000>;
+                #clock-cells = <1>;
+        };
+
         gic:interrupt-controller@2E0000 {
                 compatible = "arm,cortex-a15-gic";
                 #interrupt-cells = <3>;
@@ -24,55 +30,51 @@
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 13 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <0>;
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <1>;
                 };
                 cpu@2 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <2>;
                 };
                 cpu@3 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <3>;
                 };
         };
 
-        common {
-                compatible = "samsung,exynos5440";
-
+        timer {
+                compatible = "arm,cortex-a15-timer",
+                             "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+                clock-frequency = <50000000>;
         };
 
         serial@B0000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0xB0000 0x1000>;
                 interrupts = <0 2 0>;
+                clocks = <&clock 21>, <&clock 21>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@C0000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0xC0000 0x1000>;
                 interrupts = <0 3 0>;
+                clocks = <&clock 21>, <&clock 21>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         spi {
@@ -83,6 +85,8 @@
                 rx-dma-channel = <&pdma0 4>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>, <&clock 16>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         pinctrl {
@@ -110,25 +114,31 @@
         };
 
         i2c@F0000 {
-                compatible = "samsung,s3c2440-i2c";
+                compatible = "samsung,exynos5440-i2c";
                 reg = <0xF0000 0x1000>;
                 interrupts = <0 5 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>;
+                clock-names = "i2c";
         };
 
         i2c@100000 {
-                compatible = "samsung,s3c2440-i2c";
+                compatible = "samsung,exynos5440-i2c";
                 reg = <0x100000 0x1000>;
                 interrupts = <0 6 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>;
+                clock-names = "i2c";
         };
 
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x110000 0x1000>;
                 interrupts = <0 1 0>;
+                clocks = <&clock 21>;
+                clock-names = "watchdog";
         };
 
         amba {
@@ -142,6 +152,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x120000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 21>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -151,6 +163,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 21>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -161,5 +175,8 @@
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x130000 0x1000>;
                 interrupts = <0 17 0>, <0 16 0>;
+                clocks = <&clock 21>;
+                clock-names = "rtc";
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index f624dc85d441..02d23f15fd86 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -38,6 +38,57 @@
                 };
         };
 
+        /* HS USB Port 2 RESET */
+        hsusb2_reset: hsusb2_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 19 0>;   /* gpio_147 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        /* HS USB Port 2 Power */
+        hsusb2_power: hsusb2_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&twl_gpio 18 0>;        /* GPIO LEDA */
+                startup-delay-us = <70000>;
+        };
+
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb2_reset>;
+                vcc-supply = <&hsusb2_power>;
+        };
+};
+
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusbb2_pins
+        >;
+
+        hsusbb2_pins: pinmux_hsusbb2_pins {
+                pinctrl-single,pins = <
+                        0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
+                        0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
+                        0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
+                        0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
+                        0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
+                        0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
+                        0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
+                        0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
+                        0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
+                        0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
+                        0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
+                        0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+                >;
+        };
 };
 
 &i2c1 {
@@ -65,3 +116,23 @@
 &mmc3 {
         status = "disabled";
 };
+
+&usbhshost {
+        port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+        phys = <0 &hsusb2_phy>;
+};
+
+&twl_gpio {
+        ti,use-leds;
+        /* pullups: BIT(1) */
+        ti,pullups = <0x000002>;
+        /*
+         * pulldowns:
+         * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+         * BIT(15), BIT(16), BIT(17)
+         */
+        ti,pulldowns = <0x03a1c4>;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 1acc26148ffc..a14f74bbce7c 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -397,5 +397,36 @@
                         ti,timer-alwon;
                         ti,timer-secure;
                 };
+
+                usbhstll: usbhstll@48062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x48062000 0x1000>;
+                        interrupts = <78>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+
+                usbhshost: usbhshost@48064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x48064000 0x400>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbhsohci: ohci@48064400 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x48064400 0x400>;
+                                interrupt-parent = <&intc>;
+                                interrupts = <76>;
+                        };
+
+                        usbhsehci: ehci@48064800 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x48064800 0x400>;
+                                interrupt-parent = <&intc>;
+                                interrupts = <77>;
+                        };
+                };
+
         };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 739bb79e410e..b7db1a2b6ca7 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -529,5 +529,35 @@
                         ti,hwmods = "timer11";
                         ti,timer-pwm;
                 };
+
+                usbhstll: usbhstll@4a062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x4a062000 0x1000>;
+                        interrupts = <0 78 0x4>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+
+                usbhshost: usbhshost@4a064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x4a064000 0x800>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbhsohci: ohci@4a064800 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x4a064800 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 76 0x4>;
+                        };
+
+                        usbhsehci: ehci@4a064c00 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x4a064c00 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 77 0x4>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 6ebc1b704190..616990dc92db 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -12,7 +12,6 @@
 
         serial@70006300 {
                 status = "okay";
-                clock-frequency = <408000000>;
         };
 
         pmc {
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 5deb8692b350..6bbc8efae9c0 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -12,7 +12,6 @@
 
         serial@70006300 {
                 status = "okay";
-                clock-frequency = <408000000>;
         };
 
         pmc {
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index c0b527d15fda..c1110a9b2a91 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -24,10 +24,11 @@
                               0 42 0x04
                               0 121 0x04
                               0 122 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
-                compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
+                compatible = "nvidia,tegra114-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
         };
@@ -66,6 +67,7 @@
                 reg-shift = <2>;
                 interrupts = <0 36 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 6>;
         };
 
         serial@70006040 {
@@ -74,6 +76,7 @@
                 reg-shift = <2>;
                 interrupts = <0 37 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 192>;
         };
 
         serial@70006200 {
@@ -82,6 +85,7 @@
                 reg-shift = <2>;
                 interrupts = <0 46 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 55>;
         };
 
         serial@70006300 {
@@ -90,12 +94,14 @@
                 reg-shift = <2>;
                 interrupts = <0 90 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 65>;
         };
 
         rtc {
                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         pmc {
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index 68c8dc644383..4a4b96f6827e 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -25,11 +25,13 @@
                         #interrupt-cells = <1>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "via,vt8500-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "via,vt8500-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index 398b8bca791e..b2bf359e852f 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -40,11 +40,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8505-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8505-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index 9313407bbc30..dd8464eeb40d 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -34,11 +34,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8650-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8650-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index 7149cd13e3b9..fc790d0aee66 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -41,11 +41,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8650-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8850-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 9e1c339c4491..748fc347ed18 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -118,56 +118,23 @@
                 };
 
                 ttc0: ttc0@f8001000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "xlnx,ttc";
+                        interrupt-parent = <&intc>;
+                        interrupts = < 0 10 4 0 11 4 0 12 4 >;
+                        compatible = "cdns,ttc";
                         reg = <0xF8001000 0x1000>;
                         clocks = <&cpu_clk 3>;
                         clock-names = "cpu_1x";
                         clock-ranges;
-
-                        ttc0_0: ttc0.0 {
-                                status = "disabled";
-                                reg = <0>;
-                                interrupts = <0 10 4>;
-                        };
-                        ttc0_1: ttc0.1 {
-                                status = "disabled";
-                                reg = <1>;
-                                interrupts = <0 11 4>;
-                        };
-                        ttc0_2: ttc0.2 {
-                                status = "disabled";
-                                reg = <2>;
-                                interrupts = <0 12 4>;
-                        };
                 };
 
                 ttc1: ttc1@f8002000 {
-                        #interrupt-parent = <&intc>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "xlnx,ttc";
+                        interrupt-parent = <&intc>;
+                        interrupts = < 0 37 4 0 38 4 0 39 4 >;
+                        compatible = "cdns,ttc";
                         reg = <0xF8002000 0x1000>;
                         clocks = <&cpu_clk 3>;
                         clock-names = "cpu_1x";
                         clock-ranges;
-
-                        ttc1_0: ttc1.0 {
-                                status = "disabled";
-                                reg = <0>;
-                                interrupts = <0 37 4>;
-                        };
-                        ttc1_1: ttc1.1 {
-                                status = "disabled";
-                                reg = <1>;
-                                interrupts = <0 38 4>;
-                        };
-                        ttc1_2: ttc1.2 {
-                                status = "disabled";
-                                reg = <2>;
-                                interrupts = <0 39 4>;
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index c772942a399a..86f44d5b0265 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -32,13 +32,3 @@
 &ps_clk {
         clock-frequency = <33333330>;
 };
-
-&ttc0_0 {
-        status = "ok";
-        compatible = "xlnx,ttc-counter-clocksource";
-};
-
-&ttc0_1 {
-        status = "ok";
-        compatible = "xlnx,ttc-counter-clockevent";
-};
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index ac7a341bd0ff..25efb5ac30f1 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -169,6 +169,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 92e0f861084a..629ea5fc95cf 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -488,7 +488,6 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
@@ -505,6 +504,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
                 return;
         }
 
+        if (cpu_is_at91sam9g10())
+                at91_lcdc_device.name = "at91sam9g10-lcdfb";
+        else
+                at91_lcdc_device.name = "at91sam9261-lcdfb";
+
 #if defined(CONFIG_FB_ATMEL_STN)
         at91_set_A_periph(AT91_PIN_PB0, 0);     /* LCDVSYNC */
         at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 8e2d9f4a9a45..f44ffd2105a7 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -190,6 +190,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
         CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
         CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index ed666f5cb01d..858c8aac2daf 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -848,7 +848,7 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
+        .name           = "at91sam9263-lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index a6c224fc9542..8b7fce067652 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -228,6 +228,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_ID("hclk", &macb_clk),
         /* One additional fake clock for ohci */
         CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index f0bf68268ca2..acb703e13331 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -981,7 +981,6 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
@@ -997,6 +996,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
         if (!data)
                 return;
 
+        if (cpu_is_at91sam9g45es())
+                at91_lcdc_device.name = "at91sam9g45es-lcdfb";
+        else
+                at91_lcdc_device.name = "at91sam9g45-lcdfb";
+
         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 
         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index c39600764236..f77fae5591bc 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -179,6 +179,7 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index ddf223ff35c4..352468f265a9 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -514,7 +514,7 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
+        .name           = "at91sam9rl-lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f22f69e2d081..d19edff0ea6e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -63,6 +63,7 @@ config SOC_EXYNOS5250
         bool "SAMSUNG EXYNOS5250"
         default y
         depends on ARCH_EXYNOS5
+        select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select S5P_DEV_MFC
@@ -83,12 +84,6 @@ config SOC_EXYNOS5440
         help
           Enable EXYNOS5440 SoC support
 
-config EXYNOS4_MCT
-        bool
-        default y
-        help
-          Use MCT (Multi Core Timer) as kernel timers
-
 config EXYNOS_ATAGS
         bool "ATAGS based boot for EXYNOS (deprecated)"
         depends on !ARCH_MULTIPLATFORM
@@ -285,8 +280,8 @@ config MACH_UNIVERSAL_C210
         select S5P_DEV_ONENAND
         select S5P_DEV_TV
         select S5P_GPIO_INT
-        select S5P_HRT
         select S5P_SETUP_MIPIPHY
+        select SAMSUNG_HRT
         help
           Machine support for Samsung Mobile Universal S5PC210 Reference
           Board.
@@ -414,10 +409,12 @@ config MACH_EXYNOS4_DT
         bool "Samsung Exynos4 Machine using device tree"
         depends on ARCH_EXYNOS4
         select ARM_AMBA
+        select CLKSRC_OF
         select CPU_EXYNOS4210
         select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
         select PINCTRL
         select PINCTRL_EXYNOS
+        select S5P_DEV_MFC
         select USE_OF
         help
           Machine support for Samsung Exynos4 machine with device tree enabled.
@@ -430,6 +427,7 @@ config MACH_EXYNOS5_DT
         default y
         depends on ARCH_EXYNOS5
         select ARM_AMBA
+        select CLKSRC_OF
         select USE_OF
         help
           Machine support for Samsung EXYNOS5 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 435757e57bb4..d2f6b362b6dd 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -13,10 +13,6 @@ obj-				:=
 # Core
 
 obj-$(CONFIG_ARCH_EXYNOS)       += common.o
-obj-$(CONFIG_ARCH_EXYNOS4)      += clock-exynos4.o
-obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
-obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
-obj-$(CONFIG_SOC_EXYNOS5250)    += clock-exynos5.o
 
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
@@ -26,8 +22,6 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= pmu.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
-obj-$(CONFIG_EXYNOS4_MCT)       += mct.o
-
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 
 # machine support
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
deleted file mode 100644
index 8a8468d83c8c..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ /dev/null
@@ -1,1601 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
-        SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TV),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
-        SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
-        SAVE_ITEM(EXYNOS4_CLKDIV_TV),
-        SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
-        SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
-        SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
-        SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
-        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
-        SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
-        SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
-};
-#endif
-
-static struct clk exynos4_clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk exynos4_clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk exynos4_clk_sclk_usbphy0 = {
-        .name           = "sclk_usbphy0",
-        .rate           = 27000000,
-};
-
-static struct clk exynos4_clk_sclk_usbphy1 = {
-        .name           = "sclk_usbphy1",
-};
-
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
-}
-
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
-}
-
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
-}
-
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
-}
-
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
-}
-
-int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
-}
-
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
-}
-
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
-}
-
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
-}
-
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
-}
-
-int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
-}
-
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk exynos4_clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources = &clk_src_apll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &exynos4_clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-
-struct clksrc_clk exynos4_clk_mout_mpll = {
-        .clk    = {
-                .name           = "mout_mpll",
-        },
-        .sources = &clk_src_mpll,
-
-        /* reg_src will be added in each SoCs' clock */
-};
-
-static struct clk *exynos4_clkset_moutcore_list[] = {
-        [0] = &exynos4_clk_mout_apll.clk,
-        [1] = &exynos4_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_moutcore = {
-        .sources        = exynos4_clkset_moutcore_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
-};
-
-static struct clksrc_clk exynos4_clk_moutcore = {
-        .clk    = {
-                .name           = "moutcore",
-        },
-        .sources = &exynos4_clkset_moutcore,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_coreclk = {
-        .clk    = {
-                .name           = "core_clk",
-                .parent         = &exynos4_clk_moutcore.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_armclk = {
-        .clk    = {
-                .name           = "armclk",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corem0 = {
-        .clk    = {
-                .name           = "aclk_corem0",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_cores = {
-        .clk    = {
-                .name           = "aclk_cores",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corem1 = {
-        .clk    = {
-                .name           = "aclk_corem1",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_periphclk = {
-        .clk    = {
-                .name           = "periphclk",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-/* Core list of CMU_CORE side */
-
-static struct clk *exynos4_clkset_corebus_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_corebus = {
-        .sources        = exynos4_clkset_corebus_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_corebus = {
-        .clk    = {
-                .name           = "mout_corebus",
-        },
-        .sources = &exynos4_clkset_mout_corebus,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_dmc = {
-        .clk    = {
-                .name           = "sclk_dmc",
-                .parent         = &exynos4_clk_mout_corebus.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_cored = {
-        .clk    = {
-                .name           = "aclk_cored",
-                .parent         = &exynos4_clk_sclk_dmc.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corep = {
-        .clk    = {
-                .name           = "aclk_corep",
-                .parent         = &exynos4_clk_aclk_cored.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &exynos4_clk_mout_corebus.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &exynos4_clk_aclk_acp.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-struct clk *exynos4_clkset_aclk_top_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_aclk = {
-        .sources        = exynos4_clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
-};
-
-static struct clksrc_clk exynos4_clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_100 = {
-        .clk    = {
-                .name           = "aclk_100",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_160 = {
-        .clk    = {
-                .name           = "aclk_160",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-
-struct clksrc_clk exynos4_clk_aclk_133 = {
-        .clk    = {
-                .name           = "aclk_133",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-
-static struct clk *exynos4_clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &exynos4_clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources exynos4_clkset_vpllsrc = {
-        .sources        = exynos4_clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk exynos4_clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos4_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_vpllsrc,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_sclk_vpll_list[] = {
-        [0] = &exynos4_clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_vpll = {
-        .sources        = exynos4_clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources = &exynos4_clkset_sclk_vpll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-
-static struct clk exynos4_init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1<<24),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "jpeg",
-                .id             = 0,
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "tsi",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.0",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.1",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.2",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.3",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "biu",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "onenand",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "nfcon",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "dac",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "mixer",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "vp",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dacphy",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_dac_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "adc",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "tmu_apbif",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "keypad",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "rtc",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "watchdog",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos4_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "otg",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
-                .name           = "slimbus",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "spdif",
-                .devname        = "samsung-spdif",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.0",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.1",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.2",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.4",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.5",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.6",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.7",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.8",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.10",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }
-};
-
-static struct clk exynos4_init_clocks_on[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk exynos4_clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk exynos4_clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk exynos4_clk_mdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.2",
-        .enable         = exynos4_clk_ip_image_ctrl,
-        .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
-};
-
-static struct clk exynos4_clk_fimd0 = {
-        .name           = "fimd",
-        .devname        = "exynos4-fb.0",
-        .enable         = exynos4_clk_ip_lcd0_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-struct clk *exynos4_clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_xusbxti,
-        [2] = &exynos4_clk_sclk_hdmi27m,
-        [3] = &exynos4_clk_sclk_usbphy0,
-        [4] = &exynos4_clk_sclk_usbphy1,
-        [5] = &exynos4_clk_sclk_hdmiphy,
-        [6] = &exynos4_clk_mout_mpll.clk,
-        [7] = &exynos4_clk_mout_epll.clk,
-        [8] = &exynos4_clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_group = {
-        .sources        = exynos4_clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
-};
-
-static struct clk *exynos4_clkset_mout_g2d0_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_g2d0 = {
-        .sources        = exynos4_clkset_mout_g2d0_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
-};
-
-static struct clk *exynos4_clkset_mout_g2d1_list[] = {
-        [0] = &exynos4_clk_mout_epll.clk,
-        [1] = &exynos4_clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_g2d1 = {
-        .sources        = exynos4_clkset_mout_g2d1_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
-};
-
-static struct clk *exynos4_clkset_mout_mfc0_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
-        .sources        = exynos4_clkset_mout_mfc0_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_mfc0 = {
-        .clk    = {
-                .name           = "mout_mfc0",
-        },
-        .sources = &exynos4_clkset_mout_mfc0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_mfc1_list[] = {
-        [0] = &exynos4_clk_mout_epll.clk,
-        [1] = &exynos4_clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
-        .sources        = exynos4_clkset_mout_mfc1_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_mfc1 = {
-        .clk    = {
-                .name           = "mout_mfc1",
-        },
-        .sources = &exynos4_clkset_mout_mfc1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_mfc_list[] = {
-        [0] = &exynos4_clk_mout_mfc0.clk,
-        [1] = &exynos4_clk_mout_mfc1.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc = {
-        .sources        = exynos4_clkset_mout_mfc_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
-};
-
-static struct clk *exynos4_clkset_sclk_dac_list[] = {
-        [0] = &exynos4_clk_sclk_vpll.clk,
-        [1] = &exynos4_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_dac = {
-        .sources        = exynos4_clkset_sclk_dac_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_dac = {
-        .clk            = {
-                .name           = "sclk_dac",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos4_clkset_sclk_dac,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_pixel = {
-        .clk            = {
-                .name           = "sclk_pixel",
-                .parent         = &exynos4_clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-
-static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
-        [0] = &exynos4_clk_sclk_pixel.clk,
-        [1] = &exynos4_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
-        .sources        = exynos4_clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_hdmi = {
-        .clk            = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_sclk_hdmi,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_sclk_mixer_list[] = {
-        [0] = &exynos4_clk_sclk_dac.clk,
-        [1] = &exynos4_clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_mixer = {
-        .sources        = exynos4_clkset_sclk_mixer_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mixer = {
-        .clk    = {
-                .name           = "sclk_mixer",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos4_clkset_sclk_mixer,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *exynos4_sclk_tv[] = {
-        &exynos4_clk_sclk_dac,
-        &exynos4_clk_sclk_pixel,
-        &exynos4_clk_sclk_hdmi,
-        &exynos4_clk_sclk_mixer,
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc0 = {
-        .clk    = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc1 = {
-        .clk    = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc2 = {
-        .clk    = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc3 = {
-        .clk    = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_pwm",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.2",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.3",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.0",
-                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mfc",
-                        .devname        = "s5p-mfc",
-                },
-                .sources = &exynos4_clkset_mout_mfc,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "ciu",
-                        .parent         = &exynos4_clk_dout_mmc4.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-        }
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart1 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart2 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart3 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.0",
-                .parent         = &exynos4_clk_dout_mmc0.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.1",
-                .parent         = &exynos4_clk_dout_mmc1.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.2",
-                .parent         = &exynos4_clk_dout_mmc2.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.3",
-                .parent         = &exynos4_clk_dout_mmc3.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi0 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.0",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi1 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.1",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi2 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.2",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos4_clk_mdout_spi0.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos4_clk_mdout_spi1.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos4_clk_mdout_spi2.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *exynos4_sysclks[] = {
-        &exynos4_clk_mout_apll,
-        &exynos4_clk_sclk_apll,
-        &exynos4_clk_mout_epll,
-        &exynos4_clk_mout_mpll,
-        &exynos4_clk_moutcore,
-        &exynos4_clk_coreclk,
-        &exynos4_clk_armclk,
-        &exynos4_clk_aclk_corem0,
-        &exynos4_clk_aclk_cores,
-        &exynos4_clk_aclk_corem1,
-        &exynos4_clk_periphclk,
-        &exynos4_clk_mout_corebus,
-        &exynos4_clk_sclk_dmc,
-        &exynos4_clk_aclk_cored,
-        &exynos4_clk_aclk_corep,
-        &exynos4_clk_aclk_acp,
-        &exynos4_clk_pclk_acp,
-        &exynos4_clk_vpllsrc,
-        &exynos4_clk_sclk_vpll,
-        &exynos4_clk_aclk_200,
-        &exynos4_clk_aclk_100,
-        &exynos4_clk_aclk_160,
-        &exynos4_clk_aclk_133,
-        &exynos4_clk_dout_mmc0,
-        &exynos4_clk_dout_mmc1,
-        &exynos4_clk_dout_mmc2,
-        &exynos4_clk_dout_mmc3,
-        &exynos4_clk_dout_mmc4,
-        &exynos4_clk_mout_mfc0,
-        &exynos4_clk_mout_mfc1,
-};
-
-static struct clk *exynos4_clk_cdev[] = {
-        &exynos4_clk_pdma0,
-        &exynos4_clk_pdma1,
-        &exynos4_clk_mdma1,
-        &exynos4_clk_fimd0,
-};
-
-static struct clksrc_clk *exynos4_clksrc_cdev[] = {
-        &exynos4_clk_sclk_uart0,
-        &exynos4_clk_sclk_uart1,
-        &exynos4_clk_sclk_uart2,
-        &exynos4_clk_sclk_uart3,
-        &exynos4_clk_sclk_mmc0,
-        &exynos4_clk_sclk_mmc1,
-        &exynos4_clk_sclk_mmc2,
-        &exynos4_clk_sclk_mmc3,
-        &exynos4_clk_sclk_spi0,
-        &exynos4_clk_sclk_spi1,
-        &exynos4_clk_sclk_spi2,
-        &exynos4_clk_mdout_spi0,
-        &exynos4_clk_mdout_spi1,
-        &exynos4_clk_mdout_spi2,
-};
-
-static struct clk_lookup exynos4_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
-        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
-        CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
-        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
-        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
-        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
-        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
-};
-
-static int xtal_rate;
-
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
-        if (soc_is_exynos4210())
-                return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
-                                        pll_4508);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
-        else
-                return 0;
-}
-
-static struct clk_ops exynos4_fout_apll_ops = {
-        .get_rate = exynos4_fout_apll_get_rate,
-};
-
-static u32 exynos4_vpll_div[][8] = {
-        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
-        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int vpll_con0, vpll_con1 = 0;
-        unsigned int i;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
-        vpll_con0 &= ~(0x1 << 27 |                                      \
-                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
-                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
-                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
-        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
-                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
-                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
-                if (exynos4_vpll_div[i][0] == rate) {
-                        vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][7] << 27;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(exynos4_vpll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
-        __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
-
-        /* Wait for VPLL lock */
-        while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
-                continue;
-
-        clk->rate = rate;
-        return 0;
-}
-
-static struct clk_ops exynos4_vpll_ops = {
-        .get_rate = exynos4_vpll_get_rate,
-        .set_rate = exynos4_vpll_set_rate,
-};
-
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll = 0;
-        unsigned long mpll = 0;
-        unsigned long epll = 0;
-        unsigned long vpll = 0;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long sclk_dmc;
-        unsigned long aclk_200;
-        unsigned long aclk_100;
-        unsigned long aclk_160;
-        unsigned long aclk_133;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        if (soc_is_exynos4210()) {
-                apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
-                                        pll_4508);
-                mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
-                                        pll_4508);
-                epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
-                                        __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
-
-                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
-                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
-                                        __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
-                mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
-                epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
-                                        __raw_readl(EXYNOS4_EPLL_CON1));
-
-                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
-                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
-                                        __raw_readl(EXYNOS4_VPLL_CON1));
-        } else {
-                /* nothing */
-        }
-
-        clk_fout_apll.ops = &exynos4_fout_apll_ops;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.ops = &exynos4_vpll_ops;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                        apll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&exynos4_clk_armclk.clk);
-        sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
-
-        aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
-        aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
-        aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
-        aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
-
-        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
-                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
-                        armclk, sclk_dmc, aclk_200,
-                        aclk_100, aclk_160, aclk_133);
-
-        clk_f.rate = armclk;
-        clk_h.rate = sclk_dmc;
-        clk_p.rate = aclk_100;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
-                s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
-}
-
-static struct clk *exynos4_clks[] __initdata = {
-        &exynos4_clk_sclk_hdmi27m,
-        &exynos4_clk_sclk_hdmiphy,
-        &exynos4_clk_sclk_usbphy0,
-        &exynos4_clk_sclk_usbphy1,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-        return 0;
-}
-
-static void exynos4_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4_clock_syscore_ops = {
-        .suspend        = exynos4_clock_suspend,
-        .resume         = exynos4_clock_resume,
-};
-
-void __init exynos4_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
-                s3c_register_clksrc(exynos4_sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
-                s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
-                s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
-        s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
-
-        s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
-                s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
-
-        s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
-        s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
-        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
-
-        register_syscore_ops(&exynos4_clock_syscore_ops);
-        s3c24xx_register_clock(&dummy_apb_pclk);
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
deleted file mode 100644
index bd12d5f8b63d..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clksrc_clk exynos4_clk_aclk_133;
-extern struct clksrc_clk exynos4_clk_mout_mpll;
-
-extern struct clksrc_sources exynos4_clkset_mout_corebus;
-extern struct clksrc_sources exynos4_clkset_group;
-
-extern struct clk *exynos4_clkset_aclk_top_list[];
-extern struct clk *exynos4_clkset_group_list[];
-
-extern struct clksrc_sources exynos4_clkset_mout_g2d0;
-extern struct clksrc_sources exynos4_clkset_mout_g2d1;
-
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
deleted file mode 100644
index 19af9f783c56..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4210 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4210_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
-};
-#endif
-
-static struct clksrc_clk *sysclks[] = {
-        /* nothing here yet */
-};
-
-static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4210_clkset_mout_g2d_list[] = {
-        [0] = &exynos4210_clk_mout_g2d0.clk,
-        [1] = &exynos4210_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4210_clkset_mout_g2d = {
-        .sources        = exynos4210_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
-};
-
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
-}
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk            = {
-                        .name           = "sclk_sata",
-                        .id             = -1,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_mout_corebus,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.1",
-                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4210_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-        },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sataphy",
-                .id             = -1,
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sata",
-                .id             = -1,
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.11",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4210_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-
-        return 0;
-}
-
-static void exynos4210_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-}
-
-#else
-#define exynos4210_clock_suspend NULL
-#define exynos4210_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4210_clock_syscore_ops = {
-        .suspend        = exynos4210_clock_suspend,
-        .resume         = exynos4210_clock_resume,
-};
-
-void __init exynos4210_register_clocks(void)
-{
-        int ptr;
-
-        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
-        exynos4_clk_mout_mpll.reg_src.shift = 8;
-        exynos4_clk_mout_mpll.reg_src.size = 1;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        register_syscore_ops(&exynos4210_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
deleted file mode 100644
index 529476f8ec71..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4212 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4212_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
-};
-#endif
-
-static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
-}
-
-static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
-}
-
-static struct clk *clk_src_mpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos4_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clk_src_mpll_user = {
-        .sources        = clk_src_mpll_user_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk clk_mout_mpll_user = {
-        .clk = {
-                .name           = "mout_mpll_user",
-        },
-        .sources        = &clk_src_mpll_user,
-        .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
-};
-
-static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
-};
-
-static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
-        [0] = &exynos4x12_clk_mout_g2d0.clk,
-        [1] = &exynos4x12_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
-        .sources        = exynos4x12_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
-};
-
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_mpll_user,
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4x12_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
-        },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = exynos4_clk_ip_dmc_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.12",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (7 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.13",
-                .enable         = exynos4212_clk_ip_isp1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.14",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.15",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "flite",
-                .devname        = "exynos-fimc-lite.0",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "flite",
-                .devname        = "exynos-fimc-lite.1",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_dmc_ctrl,
-                .ctrlbit        = (1 << 23),
-        },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4212_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-
-        return 0;
-}
-
-static void exynos4212_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-}
-
-#else
-#define exynos4212_clock_suspend NULL
-#define exynos4212_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4212_clock_syscore_ops = {
-        .suspend        = exynos4212_clock_suspend,
-        .resume         = exynos4212_clock_resume,
-};
-
-void __init exynos4212_register_clocks(void)
-{
-        int ptr;
-
-        /* usbphy1 is removed */
-        exynos4_clkset_group_list[4] = NULL;
-
-        /* mout_mpll_user is used */
-        exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
-        exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
-
-        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
-        exynos4_clk_mout_mpll.reg_src.shift = 12;
-        exynos4_clk_mout_mpll.reg_src.size = 1;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        register_syscore_ops(&exynos4212_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
deleted file mode 100644
index b0ea31fc9fb8..000000000000
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ /dev/null
@@ -1,1645 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Clock support for EXYNOS5 SoCs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos5_clock_save[] = {
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
-        SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
-        SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
-        SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
-        SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
-        SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
-        SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
-        SAVE_ITEM(EXYNOS5_EPLL_CON0),
-        SAVE_ITEM(EXYNOS5_EPLL_CON1),
-        SAVE_ITEM(EXYNOS5_EPLL_CON2),
-        SAVE_ITEM(EXYNOS5_VPLL_CON0),
-        SAVE_ITEM(EXYNOS5_VPLL_CON1),
-        SAVE_ITEM(EXYNOS5_VPLL_CON2),
-        SAVE_ITEM(EXYNOS5_PWR_CTRL1),
-        SAVE_ITEM(EXYNOS5_PWR_CTRL2),
-};
-#endif
-
-static struct clk exynos5_clk_sclk_dptxphy = {
-        .name           = "sclk_dptx",
-};
-
-static struct clk exynos5_clk_sclk_hdmi24m = {
-        .name           = "sclk_hdmi24m",
-        .rate           = 24000000,
-};
-
-static struct clk exynos5_clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk exynos5_clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk exynos5_clk_sclk_usbphy = {
-        .name           = "sclk_usbphy",
-        .rate           = 48000000,
-};
-
-static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
-}
-
-static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
-}
-
-static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
-}
-
-static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
-}
-
-static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
-}
-
-static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
-}
-
-static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
-}
-
-static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
-}
-
-static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
-}
-
-static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
-}
-
-static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
-}
-
-static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
-}
-
-static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
-}
-
-static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
-}
-
-static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk exynos5_clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources = &clk_src_apll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &exynos5_clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
-        .clk    = {
-                .name           = "mout_bpll_fout",
-        },
-        .sources = &clk_src_bpll_fout,
-        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_bpll_list[] = {
-        [0] = &clk_fin_bpll,
-        [1] = &exynos5_clk_mout_bpll_fout.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_bpll = {
-        .sources        = exynos5_clk_src_bpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll = {
-        .clk    = {
-                .name           = "mout_bpll",
-        },
-        .sources = &exynos5_clk_src_bpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_bpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_bpll.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_bpll_user = {
-        .sources        = exynos5_clk_src_bpll_user_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll_user = {
-        .clk    = {
-                .name           = "mout_bpll_user",
-        },
-        .sources = &exynos5_clk_src_bpll_user,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_cpll = {
-        .clk    = {
-                .name           = "mout_cpll",
-        },
-        .sources = &clk_src_cpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
-        .clk    = {
-                .name           = "mout_mpll_fout",
-        },
-        .sources = &clk_src_mpll_fout,
-        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_mpll_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_mpll_fout.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_mpll = {
-        .sources        = exynos5_clk_src_mpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .sources = &exynos5_clk_src_mpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
-};
-
-static struct clk *exynos_clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &exynos5_clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources exynos5_clkset_vpllsrc = {
-        .sources        = exynos_clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk exynos5_clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos5_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_vpllsrc,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_sclk_vpll_list[] = {
-        [0] = &exynos5_clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources exynos5_clkset_sclk_vpll = {
-        .sources        = exynos5_clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources = &exynos5_clkset_sclk_vpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_pixel = {
-        .clk    = {
-                .name           = "sclk_pixel",
-                .parent         = &exynos5_clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
-};
-
-static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
-        [0] = &exynos5_clk_sclk_pixel.clk,
-        [1] = &exynos5_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
-        .sources        = exynos5_clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk exynos5_clk_sclk_hdmi = {
-        .clk    = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .sources = &exynos5_clkset_sclk_hdmi,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
-};
-
-static struct clksrc_clk *exynos5_sclk_tv[] = {
-        &exynos5_clk_sclk_pixel,
-        &exynos5_clk_sclk_hdmi,
-};
-
-static struct clk *exynos5_clk_src_mpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_mpll_user = {
-        .sources        = exynos5_clk_src_mpll_user_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll_user = {
-        .clk    = {
-                .name           = "mout_mpll_user",
-        },
-        .sources = &exynos5_clk_src_mpll_user,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_mout_cpu_list[] = {
-        [0] = &exynos5_clk_mout_apll.clk,
-        [1] = &exynos5_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_mout_cpu = {
-        .sources        = exynos5_clkset_mout_cpu_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_cpu = {
-        .clk    = {
-                .name           = "mout_cpu",
-        },
-        .sources = &exynos5_clkset_mout_cpu,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_armclk = {
-        .clk    = {
-                .name           = "dout_armclk",
-                .parent         = &exynos5_clk_mout_cpu.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_arm2clk = {
-        .clk    = {
-                .name           = "dout_arm2clk",
-                .parent         = &exynos5_clk_dout_armclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
-};
-
-static struct clk exynos5_clk_armclk = {
-        .name           = "armclk",
-        .parent         = &exynos5_clk_dout_arm2clk.clk,
-};
-
-/* Core list of CMU_CDREX side */
-
-static struct clk *exynos5_clkset_cdrex_list[] = {
-        [0] = &exynos5_clk_mout_mpll.clk,
-        [1] = &exynos5_clk_mout_bpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_cdrex = {
-        .sources        = exynos5_clkset_cdrex_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
-};
-
-static struct clksrc_clk exynos5_clk_cdrex = {
-        .clk    = {
-                .name           = "clk_cdrex",
-        },
-        .sources = &exynos5_clkset_cdrex,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &exynos5_clk_mout_mpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &exynos5_clk_aclk_acp.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-static struct clk *exynos5_clkset_aclk_top_list[] = {
-        [0] = &exynos5_clk_mout_mpll_user.clk,
-        [1] = &exynos5_clk_mout_bpll_user.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk = {
-        .sources        = exynos5_clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_400 = {
-        .clk    = {
-                .name           = "aclk_400",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
-};
-
-static struct clk *exynos5_clkset_aclk_333_166_list[] = {
-        [0] = &exynos5_clk_mout_cpll.clk,
-        [1] = &exynos5_clk_mout_mpll_user.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
-        .sources        = exynos5_clkset_aclk_333_166_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_333 = {
-        .clk    = {
-                .name           = "aclk_333",
-        },
-        .sources = &exynos5_clkset_aclk_333_166,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_166 = {
-        .clk    = {
-                .name           = "aclk_166",
-        },
-        .sources = &exynos5_clkset_aclk_333_166,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_266 = {
-        .clk    = {
-                .name           = "aclk_266",
-                .parent         = &exynos5_clk_mout_mpll_user.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_66_pre = {
-        .clk    = {
-                .name           = "aclk_66_pre",
-                .parent         = &exynos5_clk_mout_mpll_user.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_66 = {
-        .clk    = {
-                .name           = "aclk_66",
-                .parent         = &exynos5_clk_aclk_66_pre.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl_mid",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
-        [0] = &exynos5_clk_sclk_vpll.clk,
-        [1] = &exynos5_clk_mout_cpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
-        .sources        = exynos5_clkset_aclk_300_mid1_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl_mid1",
-        },
-        .sources = &exynos5_clkset_aclk_300_gscl_mid1,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
-        [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
-        [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
-        .sources        = exynos5_clkset_aclk_300_gscl_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl",
-        },
-        .sources = &exynos5_clkset_aclk_300_gscl,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_gscl_300_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_gscl_300 = {
-        .sources        = exynos5_clk_src_gscl_300_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
-        .clk    = {
-                .name           = "aclk_300_gscl",
-        },
-        .sources = &exynos5_clk_src_gscl_300,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
-};
-
-static struct clk exynos5_init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "tmu_apbif",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "rtc",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "watchdog",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "biu",        /* bus interface unit clock */
-                .devname        = "dw_mmc.0",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.1",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.2",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.3",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "sata",
-                .devname        = "exynos5-sata",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "sata-phy",
-                .devname        = "exynos5-sata-phy",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "i2c",
-                .devname        = "exynos5-sata-phy-i2c",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc-v6",
-                .enable         = exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos5-hdmi",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos5-hdmi",
-                .enable         = exynos5_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "mixer",
-                .devname        = "exynos5-mixer",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "dp",
-                .devname        = "exynos-dp",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "jpeg",
-                .enable         = exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "dsim0",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
-                .name           = "spdif",
-                .devname        = "samsung-spdif",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos5_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "usbotg",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "nfcon",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "iop",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
-        }, {
-                .name           = "core_iop",
-                .enable         = exynos5_clk_ip_core_ctrl,
-                .ctrlbit        = ((1 << 21) | (1 << 3)),
-        }, {
-                .name           = "mcu_iop",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.0",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.1",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.2",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.3",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.1",
-                .enable         = &exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.0",
-                .enable         = &exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.2",
-                .enable         = &exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 9)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.3",
-                .enable         = &exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.4",
-                .enable         = &exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 6)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.5",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.6",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.7",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.8",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = &exynos5_clk_ip_isp0_ctrl,
-                .ctrlbit        = (0x3F << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.10",
-                .enable         = &exynos5_clk_ip_isp1_ctrl,
-                .ctrlbit        = (0xF << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.11",
-                .enable         = &exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 8)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.12",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.13",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.14",
-                .enable         = &exynos5_clk_ip_acp_ctrl,
-                .ctrlbit        = (1 << 7)
-        }
-};
-
-static struct clk exynos5_init_clocks_on[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk exynos5_clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk exynos5_clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 2),
-};
-
-static struct clk exynos5_clk_mdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.2",
-        .enable         = exynos5_clk_ip_gen_ctrl,
-        .ctrlbit        = (1 << 4),
-};
-
-static struct clk exynos5_clk_fimd1 = {
-        .name           = "fimd",
-        .devname        = "exynos5-fb.1",
-        .enable         = exynos5_clk_ip_disp1_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk *exynos5_clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = NULL,
-        [2] = &exynos5_clk_sclk_hdmi24m,
-        [3] = &exynos5_clk_sclk_dptxphy,
-        [4] = &exynos5_clk_sclk_usbphy,
-        [5] = &exynos5_clk_sclk_hdmiphy,
-        [6] = &exynos5_clk_mout_mpll_user.clk,
-        [7] = &exynos5_clk_mout_epll.clk,
-        [8] = &exynos5_clk_sclk_vpll.clk,
-        [9] = &exynos5_clk_mout_cpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_group = {
-        .sources        = exynos5_clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
-};
-
-/* Possible clock sources for aclk_266_gscl_sub Mux */
-static struct clk *clk_src_gscl_266_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &exynos5_clk_aclk_266.clk,
-};
-
-static struct clksrc_sources clk_src_gscl_266 = {
-        .sources        = clk_src_gscl_266_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc0 = {
-        .clk            = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc1 = {
-        .clk            = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc2 = {
-        .clk            = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc3 = {
-        .clk            = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart1 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart2 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart3 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "ciu",        /* card interface unit clock */
-                .devname        = "dw_mmc.0",
-                .parent         = &exynos5_clk_dout_mmc0.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.1",
-                .parent         = &exynos5_clk_dout_mmc1.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.2",
-                .parent         = &exynos5_clk_dout_mmc2.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.3",
-                .parent         = &exynos5_clk_dout_mmc3.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi0 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.0",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi1 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.1",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi2 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.2",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos5_clk_mdout_spi0.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos5_clk_mdout_spi1.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos5_clk_mdout_spi2.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
-        .clk    = {
-                .name           = "sclk_fimd",
-                .devname        = "exynos5-fb.1",
-                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "aclk_266_gscl",
-                },
-                .sources = &clk_src_gscl_266,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_g3d",
-                        .devname        = "mali-t604.0",
-                        .enable         = exynos5_clk_block_ctrl,
-                        .ctrlbit        = (1 << 1),
-                },
-                .sources = &exynos5_clkset_aclk,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_sata",
-                        .devname        = "exynos5-sata",
-                        .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos5_clkset_aclk,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_gscl_wrap",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_gscl_wrap",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_jpeg",
-                        .parent         = &exynos5_clk_mout_cpll.clk,
-                },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
-        },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *exynos5_sysclks[] = {
-        &exynos5_clk_mout_apll,
-        &exynos5_clk_sclk_apll,
-        &exynos5_clk_mout_bpll,
-        &exynos5_clk_mout_bpll_fout,
-        &exynos5_clk_mout_bpll_user,
-        &exynos5_clk_mout_cpll,
-        &exynos5_clk_mout_epll,
-        &exynos5_clk_mout_mpll,
-        &exynos5_clk_mout_mpll_fout,
-        &exynos5_clk_mout_mpll_user,
-        &exynos5_clk_vpllsrc,
-        &exynos5_clk_sclk_vpll,
-        &exynos5_clk_mout_cpu,
-        &exynos5_clk_dout_armclk,
-        &exynos5_clk_dout_arm2clk,
-        &exynos5_clk_cdrex,
-        &exynos5_clk_aclk_400,
-        &exynos5_clk_aclk_333,
-        &exynos5_clk_aclk_266,
-        &exynos5_clk_aclk_200,
-        &exynos5_clk_aclk_166,
-        &exynos5_clk_aclk_300_gscl,
-        &exynos5_clk_mout_aclk_300_gscl,
-        &exynos5_clk_mout_aclk_300_gscl_mid,
-        &exynos5_clk_mout_aclk_300_gscl_mid1,
-        &exynos5_clk_aclk_66_pre,
-        &exynos5_clk_aclk_66,
-        &exynos5_clk_dout_mmc0,
-        &exynos5_clk_dout_mmc1,
-        &exynos5_clk_dout_mmc2,
-        &exynos5_clk_dout_mmc3,
-        &exynos5_clk_dout_mmc4,
-        &exynos5_clk_aclk_acp,
-        &exynos5_clk_pclk_acp,
-        &exynos5_clk_sclk_spi0,
-        &exynos5_clk_sclk_spi1,
-        &exynos5_clk_sclk_spi2,
-        &exynos5_clk_mdout_spi0,
-        &exynos5_clk_mdout_spi1,
-        &exynos5_clk_mdout_spi2,
-        &exynos5_clk_sclk_fimd1,
-};
-
-static struct clk *exynos5_clk_cdev[] = {
-        &exynos5_clk_pdma0,
-        &exynos5_clk_pdma1,
-        &exynos5_clk_mdma1,
-        &exynos5_clk_fimd1,
-};
-
-static struct clksrc_clk *exynos5_clksrc_cdev[] = {
-        &exynos5_clk_sclk_uart0,
-        &exynos5_clk_sclk_uart1,
-        &exynos5_clk_sclk_uart2,
-        &exynos5_clk_sclk_uart3,
-        &exynos5_clk_sclk_mmc0,
-        &exynos5_clk_sclk_mmc1,
-        &exynos5_clk_sclk_mmc2,
-        &exynos5_clk_sclk_mmc3,
-};
-
-static struct clk_lookup exynos5_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
-        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
-        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
-        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
-        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
-        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
-        CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
-};
-
-static unsigned long exynos5_epll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static struct clk *exynos5_clks[] __initdata = {
-        &exynos5_clk_sclk_hdmi27m,
-        &exynos5_clk_sclk_hdmiphy,
-        &clk_fout_bpll,
-        &clk_fout_bpll_div2,
-        &clk_fout_cpll,
-        &clk_fout_mpll_div2,
-        &exynos5_clk_armclk,
-};
-
-static u32 epll_div[][6] = {
-        { 192000000, 0, 48, 3, 1, 0 },
-        { 180000000, 0, 45, 3, 1, 0 },
-        {  73728000, 1, 73, 3, 3, 47710 },
-        {  67737600, 1, 90, 4, 3, 20762 },
-        {  49152000, 0, 49, 3, 3, 9961 },
-        {  45158400, 0, 45, 3, 3, 10381 },
-        { 180633600, 0, 45, 3, 1, 10381 },
-};
-
-static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con, epll_con_k;
-        unsigned int i;
-        unsigned int tmp;
-        unsigned int epll_rate;
-        unsigned int locktime;
-        unsigned int lockcnt;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        if (clk->parent)
-                epll_rate = clk_get_rate(clk->parent);
-        else
-                epll_rate = clk_ext_xtal_mux.rate;
-
-        if (epll_rate != 24000000) {
-                pr_err("Invalid Clock : recommended clock is 24MHz.\n");
-                return -EINVAL;
-        }
-
-        epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
-        epll_con &= ~(0x1 << 27 | \
-                        PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
-                        PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
-                        PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                if (epll_div[i][0] == rate) {
-                        epll_con_k = epll_div[i][5] << 0;
-                        epll_con |= epll_div[i][1] << 27;
-                        epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
-                        epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        epll_rate /= 1000000;
-
-        /* 3000 max_cycls : specification data */
-        locktime = 3000 / epll_rate * epll_div[i][3];
-        lockcnt = locktime * 10000 / (10000 / epll_rate);
-
-        __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
-
-        __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
-        __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
-
-        do {
-                tmp = __raw_readl(EXYNOS5_EPLL_CON0);
-        } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops exynos5_epll_ops = {
-        .get_rate = exynos5_epll_get_rate,
-        .set_rate = exynos5_epll_set_rate,
-};
-
-static int xtal_rate;
-
-static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
-{
-        return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
-}
-
-static struct clk_ops exynos5_fout_apll_ops = {
-        .get_rate = exynos5_fout_apll_get_rate,
-};
-
-#ifdef CONFIG_PM
-static int exynos5_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
-
-        return 0;
-}
-
-static void exynos5_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
-}
-#else
-#define exynos5_clock_suspend NULL
-#define exynos5_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos5_clock_syscore_ops = {
-        .suspend        = exynos5_clock_suspend,
-        .resume         = exynos5_clock_resume,
-};
-
-void __init_or_cpufreq exynos5_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll;
-        unsigned long bpll;
-        unsigned long cpll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned long vpll;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long mout_cdrex;
-        unsigned long aclk_400;
-        unsigned long aclk_333;
-        unsigned long aclk_266;
-        unsigned long aclk_200;
-        unsigned long aclk_166;
-        unsigned long aclk_66;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
-        bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
-        cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
-        mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
-        epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
-                        __raw_readl(EXYNOS5_EPLL_CON1));
-
-        vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
-        vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
-                        __raw_readl(EXYNOS5_VPLL_CON1));
-
-        clk_fout_apll.ops = &exynos5_fout_apll_ops;
-        clk_fout_bpll.rate = bpll;
-        clk_fout_bpll_div2.rate = bpll >> 1;
-        clk_fout_cpll.rate = cpll;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_mpll_div2.rate = mpll >> 1;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
-                        "M=%ld, E=%ld V=%ld",
-                        apll, bpll, cpll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&exynos5_clk_armclk);
-        mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
-
-        aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
-        aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
-        aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
-        aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
-        aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
-        aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
-
-        printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
-                        "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
-                        "ACLK166=%ld, ACLK66=%ld\n",
-                        armclk, mout_cdrex, aclk_400,
-                        aclk_333, aclk_266, aclk_200,
-                        aclk_166, aclk_66);
-
-
-        clk_fout_epll.ops = &exynos5_epll_ops;
-
-        if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
-                printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
-                                clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
-
-        clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
-        clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
-
-        clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
-        clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
-                s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
-}
-
-void __init exynos5_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
-                s3c_register_clksrc(exynos5_sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
-                s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
-                s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
-        s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
-
-        s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
-                s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
-
-        s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
-        s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
-        clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
-
-        register_syscore_ops(&exynos5_clock_syscore_ops);
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 15718da30c45..b35c60059bb8 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -24,6 +24,8 @@
 #include <linux/export.h>
 #include <linux/irqdomain.h>
 #include <linux/of_address.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/irqchip/chained_irq.h>
 
@@ -37,9 +39,9 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 #include <mach/regs-gpio.h>
+#include <mach/irqs.h>
 
 #include <plat/cpu.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/sdhci.h>
@@ -65,17 +67,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
 static void exynos5440_map_io(void);
-static void exynos4_init_clocks(int xtal);
-static void exynos5_init_clocks(int xtal);
 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
+unsigned long xxti_f = 0, xusbxti_f = 0;
+
 static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = EXYNOS4210_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4210,
@@ -83,7 +84,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS4212_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4212,
@@ -91,7 +91,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS4412_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4412,
@@ -99,7 +98,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS5250_SOC_ID,
                 .idmask         = EXYNOS5_SOC_MASK,
                 .map_io         = exynos5_map_io,
-                .init_clocks    = exynos5_init_clocks,
                 .init           = exynos_init,
                 .name           = name_exynos5250,
         }, {
@@ -257,11 +255,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
                 .length         = SZ_4K,
@@ -402,43 +395,26 @@ static void __init exynos5_map_io(void)
         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 }
 
-static void __init exynos4_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-
-        if (soc_is_exynos4210())
-                exynos4210_register_clocks();
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                exynos4212_register_clocks();
-
-        exynos4_register_clocks();
-        exynos4_setup_clocks();
-}
-
 static void __init exynos5440_map_io(void)
 {
         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 }
 
-static void __init exynos5_init_clocks(int xtal)
+void __init exynos_init_time(void)
 {
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        /* EXYNOS5440 can support only common clock framework */
-
-        if (soc_is_exynos5440())
-                return;
-
-#ifdef CONFIG_SOC_EXYNOS5250
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-
-        exynos5_register_clocks();
-        exynos5_setup_clocks();
+        if (of_have_populated_dt()) {
+#ifdef CONFIG_OF
+                of_clk_init(NULL);
+                clocksource_of_init();
+#endif
+        } else {
+                /* todo: remove after migrating legacy E4 platforms to dt */
+#ifdef CONFIG_ARCH_EXYNOS4
+                exynos4_clk_init(NULL);
+                exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 #endif
+                mct_init();
+        }
 }
 
 void __init exynos4_init_irq(void)
@@ -824,6 +800,7 @@ static int __init exynos_init_irq_eint(void)
         static const struct of_device_id exynos_pinctrl_ids[] = {
                 { .compatible = "samsung,exynos4210-pinctrl", },
                 { .compatible = "samsung,exynos4x12-pinctrl", },
+                { .compatible = "samsung,exynos5250-pinctrl", },
         };
         struct device_node *pctrl_np, *wkup_np;
         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
@@ -877,3 +854,30 @@ static int __init exynos_init_irq_eint(void)
         return 0;
 }
 arch_initcall(exynos_init_irq_eint);
+
+static struct resource exynos4_pmu_resource[] = {
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+#if defined(CONFIG_SOC_EXYNOS4412)
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
+#endif
+};
+
+static struct platform_device exynos4_device_pmu = {
+        .name           = "arm-pmu",
+        .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
+        .resource       = exynos4_pmu_resource,
+};
+
+static int __init exynos_armpmu_init(void)
+{
+        if (!of_have_populated_dt()) {
+                if (soc_is_exynos4210() || soc_is_exynos4212())
+                        exynos4_device_pmu.num_resources = 2;
+                platform_device_register(&exynos4_device_pmu);
+        }
+
+        return 0;
+}
+arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9339bb8954be..cb89ab886950 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,11 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
-extern void exynos4_timer_init(void);
+#include <linux/of.h>
+
+extern void mct_init(void);
+void exynos_init_time(void);
+extern unsigned long xxti_f, xusbxti_f;
 
 struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
@@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd);
 void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
 
+/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
+void exynos4_clk_init(struct device_node *np);
+void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
+
 #ifdef CONFIG_PM_GENERIC_DOMAINS
 int exynos_pm_late_initcall(void);
 #else
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 8bd5dde5fc78..c72f59d91fce 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,8 +30,6 @@
 
 /* For EXYNOS4 and EXYNOS5 */
 
-#define EXYNOS_IRQ_MCT_LOCALTIMER       IRQ_PPI(12)
-
 #define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
 
 /* For EXYNOS4 SoCs */
@@ -128,7 +126,7 @@
 #define EXYNOS4_IRQ_ADC1                IRQ_SPI(107)
 #define EXYNOS4_IRQ_PEN1                IRQ_SPI(108)
 #define EXYNOS4_IRQ_KEYPAD              IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMU                 IRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU           IRQ_SPI(110)
 #define EXYNOS4_IRQ_GPS                 IRQ_SPI(111)
 #define EXYNOS4_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
 #define EXYNOS4_IRQ_SLIMBUS             IRQ_SPI(113)
@@ -136,6 +134,11 @@
 #define EXYNOS4_IRQ_TSI                 IRQ_SPI(115)
 #define EXYNOS4_IRQ_SATA                IRQ_SPI(116)
 
+#define EXYNOS4_IRQ_PMU                 COMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1            COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2            COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3            COMBINER_IRQ(19, 2)
+
 #define EXYNOS4_IRQ_TMU_TRIG0           COMBINER_IRQ(2, 4)
 #define EXYNOS4_IRQ_TMU_TRIG1           COMBINER_IRQ(3, 4)
 
@@ -168,7 +171,10 @@
 #define EXYNOS4_IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
 #define EXYNOS4_IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
 
-#define EXYNOS4_MAX_COMBINER_NR         16
+#define EXYNOS4210_MAX_COMBINER_NR      16
+#define EXYNOS4212_MAX_COMBINER_NR      18
+#define EXYNOS4412_MAX_COMBINER_NR      20
+#define EXYNOS4_MAX_COMBINER_NR         EXYNOS4412_MAX_COMBINER_NR
 
 #define EXYNOS4_IRQ_GPIO1_NR_GROUPS     16
 #define EXYNOS4_IRQ_GPIO2_NR_GROUPS     9
@@ -233,7 +239,6 @@
 #define IRQ_TC                          EXYNOS4_IRQ_PEN0
 
 #define IRQ_KEYPAD                      EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMU                         EXYNOS4_IRQ_PMU
 
 #define IRQ_FIMD0_FIFO                  EXYNOS4_IRQ_FIMD0_FIFO
 #define IRQ_FIMD0_VSYNC                 EXYNOS4_IRQ_FIMD0_VSYNC
@@ -323,8 +328,6 @@
 #define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
 
-#define EXYNOS5_IRQ_MCT_L0              IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1              IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
@@ -419,8 +422,6 @@
 #define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
 
 #define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
 
 #define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 1df6abbf53b8..7f99b7b187d6 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -65,7 +65,6 @@
 #define EXYNOS5_PA_CMU                  0x10010000
 
 #define EXYNOS4_PA_SYSTIMER             0x10050000
-#define EXYNOS5_PA_SYSTIMER             0x101C0000
 
 #define EXYNOS4_PA_WATCHDOG             0x10060000
 #define EXYNOS5_PA_WATCHDOG             0x101D0000
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
deleted file mode 100644
index 80dd02ad6d61..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-mct.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-mct.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 MCT configutation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_MCT_H
-#define __ASM_ARCH_REGS_MCT_H __FILE__
-
-#include <mach/map.h>
-
-#define EXYNOS4_MCTREG(x)               (S5P_VA_SYSTIMER + (x))
-
-#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
-#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
-#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
-
-#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
-#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
-#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
-
-#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
-
-#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
-#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
-#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
-
-#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
-#define EXYNOS4_MCT_L_MASK              (0xffffff00)
-
-#define MCT_L_TCNTB_OFFSET              (0x00)
-#define MCT_L_ICNTB_OFFSET              (0x08)
-#define MCT_L_TCON_OFFSET               (0x20)
-#define MCT_L_INT_CSTAT_OFFSET          (0x30)
-#define MCT_L_INT_ENB_OFFSET            (0x34)
-#define MCT_L_WSTAT_OFFSET              (0x40)
-
-#define MCT_G_TCON_START                (1 << 8)
-#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
-#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
-
-#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
-#define MCT_L_TCON_INT_START            (1 << 1)
-#define MCT_L_TCON_TIMER_START          (1 << 0)
-
-#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 2126f3503a3f..5f0f55701374 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -178,7 +178,6 @@ static void __init armlex4210_smsc911x_init(void)
 static void __init armlex4210_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(armlex4210_uartcfgs,
                            ARRAY_SIZE(armlex4210_uartcfgs));
 }
@@ -203,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
         .map_io         = armlex4210_map_io,
         .init_machine   = armlex4210_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 3358088c822a..ac27f3cd121f 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -11,121 +11,26 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/of_fdt.h>
 #include <linux/serial_core.h>
+#include <linux/memblock.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
-#include <mach/map.h>
-
-#include <plat/cpu.h>
-#include <plat/regs-serial.h>
+#include <plat/mfc.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the Exynos4 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
-                                "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
-                                "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
-                                "exynos4210-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
-                                "exynos4-sdhci.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
-                                "exynos4-sdhci.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
-                                "exynos4-sdhci.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
-                                "exynos4-sdhci.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
-                                "s3c2440-i2c.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
-                                "s3c2440-i2c.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
-                                "s3c2440-i2c.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
-                                "s3c2440-i2c.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
-                                "s3c2440-i2c.4", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
-                                "s3c2440-i2c.5", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
-                                "s3c2440-i2c.6", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
-                                "s3c2440-i2c.7", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
-                                "exynos4210-spi.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
-                                "exynos4210-spi.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
-                                "exynos4210-spi.2", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
-                                "exynos-tmu", NULL),
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
-                        "exynos-sysmmu.0", NULL), /* MFC_L */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
-                        "exynos-sysmmu.1", NULL), /* MFC_R */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
-                        "exynos-sysmmu.2", NULL), /* TV */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
-                        "exynos-sysmmu.3", NULL), /* JPEG */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
-                        "exynos-sysmmu.4", NULL), /* ROTATOR */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
-                        "exynos-sysmmu.5", NULL), /* FIMC0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
-                        "exynos-sysmmu.6", NULL), /* FIMC1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
-                        "exynos-sysmmu.7", NULL), /* FIMC2 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
-                        "exynos-sysmmu.8", NULL), /* FIMC3 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
-                        "exynos-sysmmu.9", NULL), /* G2D(4210) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
-                        "exynos-sysmmu.9", NULL), /* G2D(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
-                        "exynos-sysmmu.10", NULL), /* FIMD0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
-                        "exynos-sysmmu.11", NULL), /* FIMD1(4210) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
-                        "exynos-sysmmu.12", NULL), /* IS0(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
-                        "exynos-sysmmu.13", NULL), /* IS1(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
-                        "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
-                        "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
-        {},
-};
-
 static void __init exynos4_dt_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
 }
 
 static void __init exynos4_dt_machine_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                                exynos4_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static char const *exynos4_dt_compat[] __initdata = {
@@ -135,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = {
         NULL
 };
 
+static void __init exynos4_reserve(void)
+{
+#ifdef CONFIG_S5P_DEV_MFC
+        struct s5p_mfc_dt_meminfo mfc_mem;
+
+        /* Reserve memory for MFC only if it's available */
+        mfc_mem.compatible = "samsung,mfc-v5";
+        if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
+                s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
+                                mfc_mem.lsize);
+#endif
+}
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
         .smp            = smp_ops(exynos_smp_ops),
@@ -142,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         .map_io         = exynos4_dt_map_io,
         .init_machine   = exynos4_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .dt_compat      = exynos4_dt_compat,
         .restart        = exynos4_restart,
+        .reserve        = exynos4_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index acaeb14db54b..753b94f3fca7 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,151 +11,21 @@
 
 #include <linux/of_platform.h>
 #include <linux/of_fdt.h>
-#include <linux/serial_core.h>
 #include <linux/memblock.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
-#include <mach/map.h>
 #include <mach/regs-pmu.h>
 
 #include <plat/cpu.h>
-#include <plat/regs-serial.h>
 #include <plat/mfc.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the EXYNOS5 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
-                                "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
-                                "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
-                                "exynos4210-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
-                                "s3c2440-i2c.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
-                                "s3c2440-i2c.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
-                                "s3c2440-i2c.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
-                                "s3c2440-i2c.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
-                                "s3c2440-i2c.4", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
-                                "s3c2440-i2c.5", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
-                                "s3c2440-i2c.6", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
-                                "s3c2440-i2c.7", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
-                                "s3c2440-hdmiphy-i2c", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
-                                "dw_mmc.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
-                                "dw_mmc.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
-                                "dw_mmc.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
-                                "dw_mmc.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
-                                "exynos4210-spi.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
-                                "exynos4210-spi.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
-                                "exynos4210-spi.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
-                                "exynos5-sata", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
-                                "exynos5-sata-phy", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
-                                "exynos5-sata-phy-i2c", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
-                                "exynos-gsc.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
-                                "exynos-gsc.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
-                                "exynos-gsc.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
-                                "exynos-gsc.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
-                                "exynos5-hdmi", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
-                                "exynos5-mixer", NULL),
-        OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
-                                "exynos-tmu", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
-                                "samsung-i2s.0", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
-                                "samsung-i2s.1", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
-                                "samsung-i2s.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
-                        "exynos-sysmmu.0", "mfc"), /* MFC_L */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
-                        "exynos-sysmmu.1", "mfc"), /* MFC_R */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
-                        "exynos-sysmmu.2", NULL), /* TV */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
-                        "exynos-sysmmu.3", "jpeg"), /* JPEG */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
-                        "exynos-sysmmu.4", NULL), /* ROTATOR */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
-                        "exynos-sysmmu.5", "gscl"), /* GSCL0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
-                        "exynos-sysmmu.6", "gscl"), /* GSCL1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
-                        "exynos-sysmmu.7", "gscl"), /* GSCL2 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
-                        "exynos-sysmmu.8", "gscl"), /* GSCL3 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
-                        "exynos-sysmmu.9", NULL), /* FIMC-IS0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
-                        "exynos-sysmmu.10", NULL), /* FIMC-IS1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
-                        "exynos-sysmmu.11", NULL), /* FIMD1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
-                        "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
-                        "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
-                        "exynos-sysmmu.14", NULL), /* G2D */
-        {},
-};
-
-static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        {},
-};
-
 static void __init exynos5_dt_map_io(void)
 {
-        unsigned long root = of_get_flat_dt_root();
-
         exynos_init_io(NULL, 0);
-
-        if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
-                s3c24xx_init_clocks(24000000);
 }
 
 static void __init exynos5_dt_machine_init(void)
@@ -182,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
                 }
         }
 
-        if (of_machine_is_compatible("samsung,exynos5250"))
-                of_platform_populate(NULL, of_default_bus_match_table,
-                                     exynos5250_auxdata_lookup, NULL);
-        else if (of_machine_is_compatible("samsung,exynos5440"))
-                of_platform_populate(NULL, of_default_bus_match_table,
-                                     exynos5440_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static char const *exynos5_dt_compat[] __initdata = {
@@ -216,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         .map_io         = exynos5_dt_map_io,
         .init_machine   = exynos5_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .dt_compat      = exynos5_dt_compat,
         .restart        = exynos5_restart,
         .reserve        = exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 2517406e7f56..5c8b2878dbbd 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -1331,8 +1331,9 @@ static struct platform_device *nuri_devices[] __initdata = {
 static void __init nuri_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void __init nuri_reserve(void)
@@ -1381,7 +1382,7 @@ MACHINE_START(NURI, "NURI")
         .map_io         = nuri_map_io,
         .init_machine   = nuri_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &nuri_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index ec42024dd13f..27f03ed5d067 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -755,8 +755,9 @@ static void s5p_tv_setup(void)
 static void __init origen_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void __init origen_power_init(void)
@@ -816,7 +817,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
         .map_io         = origen_map_io,
         .init_machine   = origen_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &origen_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index 5df91236dbb4..2c8af9617920 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -323,7 +323,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
 static void __init smdk4x12_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
 }
 
@@ -377,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
@@ -391,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 9680e1291065..d95b8cf85253 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -372,8 +372,9 @@ static void s5p_tv_setup(void)
 static void __init smdkv310_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+        xxti_f = 12000000;
+        xusbxti_f = 24000000;
 }
 
 static void __init smdkv310_reserve(void)
@@ -424,7 +425,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
@@ -437,7 +438,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index d28c7fbaba2d..327d50d4681d 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -41,7 +41,7 @@
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
 #include <plat/fimc-core.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/camport.h>
 
 #include <mach/map.h>
@@ -1093,9 +1093,10 @@ static struct platform_device *universal_devices[] __initdata = {
 static void __init universal_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void s5p_tv_setup(void)
@@ -1153,7 +1154,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
         .map_io         = universal_map_io,
         .init_machine   = universal_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .reserve        = &universal_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 2612eeaa5889..a4d4664894e1 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -445,16 +445,23 @@ static void enable_board_wakeup_source(void)
                 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 57,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = 61,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 57,
-        .reset_gpio_port[1]  = 61,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -606,6 +613,8 @@ static void __init omap_3430sdp_init(void)
         board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
         sdp3430_display_init();
         enable_board_wakeup_source();
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 67447bd4564f..20d6d8189240 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -53,16 +53,23 @@ static void enable_board_wakeup_source(void)
                 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 126,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = 61,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 126,
-        .reset_gpio_port[1]  = 61,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -199,6 +206,8 @@ static void __init omap_sdp_init(void)
         board_smc91x_init();
         board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
         enable_board_wakeup_source();
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 7d3358b2e593..fc53911d0d13 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -47,15 +47,17 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = GPIO_USB_NRESET,
+                .vcc_gpio = GPIO_USB_POWER,
+                .vcc_polarity = 1,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = GPIO_USB_NRESET,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static struct mtd_partition crane_nand_partitions[] = {
@@ -131,13 +133,7 @@ static void __init am3517_crane_init(void)
                 return;
         }
 
-        ret = gpio_request_one(GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
-                               "usb_ehci_enable");
-        if (ret < 0) {
-                pr_err("Can not request GPIO %d\n", GPIO_USB_POWER);
-                return;
-        }
-
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 }
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 1d6c28872505..c29d2e743688 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -273,6 +273,14 @@ static __init void am3517_evm_mcbsp1_init(void)
         omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 57,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -281,12 +289,6 @@ static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 #else
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
 #endif
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 57,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -348,7 +350,6 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-
 static void __init am3517_evm_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -360,6 +361,8 @@ static void __init am3517_evm_init(void)
 
         /* Configure GPIO for EHCI port */
         omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
         /* DSS */
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index bccd3e51fecb..e0ed8c07fc54 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -418,15 +418,22 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = OMAP_MAX_GPIO_LINES + 6,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = OMAP_MAX_GPIO_LINES + 7,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = OMAP_MAX_GPIO_LINES + 6,
-        .reset_gpio_port[1]  = OMAP_MAX_GPIO_LINES + 7,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static void  __init cm_t35_init_usbh(void)
@@ -443,6 +450,7 @@ static void  __init cm_t35_init_usbh(void)
                 msleep(1);
         }
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index a66da808cc4a..4eb5e6f2f7f5 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -188,15 +188,22 @@ static inline void cm_t3517_init_rtc(void) {}
 #define HSUSB2_RESET_GPIO       (147)
 #define USB_HUB_RESET_GPIO      (152)
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = HSUSB1_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = HSUSB2_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = HSUSB1_RESET_GPIO,
-        .reset_gpio_port[1]  = HSUSB2_RESET_GPIO,
-        .reset_gpio_port[2]  = -EINVAL,
 };
 
 static int __init cm_t3517_init_usbh(void)
@@ -213,6 +220,7 @@ static int __init cm_t3517_init_usbh(void)
                 msleep(1);
         }
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&cm_t3517_ehci_pdata);
 
         return 0;
@@ -324,6 +332,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = cm_t3517_init,
         .init_late      = am35xx_init_late,
-        .init_time      = omap3_gp_gptimer_timer_init,
+        .init_time      = omap3_gptimer_timer_init,
         .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 12d2126a2382..e44b804f75ae 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -436,15 +436,7 @@ static struct platform_device *devkit8000_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index e54a48060198..78813b397209 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -140,7 +140,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
         .init_irq       = omap_intc_of_init,
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
-        .init_time      = omap3_am33xx_gptimer_timer_init,
+        .init_time      = omap3_gptimer_timer_init,
         .dt_compat      = am33xx_boards_compat,
         .restart        = am33xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index e979d48270c9..b54562d1235e 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -527,26 +527,28 @@ static void __init igep_i2c_init(void)
         omap3_pmic_init("twl4030", &igep_twldata);
 }
 
+static struct usbhs_phy_data igep2_phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = IGEP2_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
+static struct usbhs_phy_data igep3_phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = IGEP3_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET,
-        .reset_gpio_port[1] = -EINVAL,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = -EINVAL,
-        .reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -642,8 +644,10 @@ static void __init igep_init(void)
         if (machine_is_igep0020()) {
                 omap_display_init(&igep2_dss_data);
                 igep2_init_smsc911x();
+                usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data));
                 usbhs_init(&igep2_usbhs_bdata);
         } else {
+                usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data));
                 usbhs_init(&igep3_usbhs_bdata);
         }
 }
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index fff141330a63..6de78605c0af 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -33,6 +33,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -277,6 +278,21 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = {
 
 static struct gpio_led gpio_leds[];
 
+/* PHY's VCC regulator might be added later, so flag that we need it */
+static struct nop_usb_xceiv_platform_data hsusb2_phy_data = {
+        .needs_vcc = true,
+};
+
+static struct usbhs_phy_data phy_data[] = {
+        {
+                .port = 2,
+                .reset_gpio = 147,
+                .vcc_gpio = -1,         /* updated in beagle_twl_gpio_setup */
+                .vcc_polarity = 1,      /* updated in beagle_twl_gpio_setup */
+                .platform_data = &hsusb2_phy_data,
+        },
+};
+
 static int beagle_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -318,9 +334,11 @@ static int beagle_twl_gpio_setup(struct device *dev,
         }
         dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio;
 
-        gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
-                        "nEN_USB_PWR");
+        /* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */
+        phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX;
+        phy_data[0].vcc_polarity = beagle_config.usb_pwr_level;
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         return 0;
 }
 
@@ -453,15 +471,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 147,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -543,7 +553,9 @@ static void __init omap3_beagle_init(void)
 
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
         usbhs_init(&usbhs_bdata);
+
         board_nand_init(omap3beagle_nand_partitions,
                         ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
                         NAND_BUSWIDTH_16, NULL);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 233a0d528fcf..4f1bbc3cc29b 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -496,7 +496,7 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
 static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
         REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"),    /* OMAP ISP */
         REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"),    /* OMAP ISP */
-        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
+        REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"),     /* hsusb port 2 */
         REGULATOR_SUPPLY("vaux2", NULL),
 };
 
@@ -539,17 +539,16 @@ static int __init omap3_evm_i2c_init(void)
         return 0;
 }
 
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = -1,       /* set at runtime */
+                .vcc_gpio = -EINVAL,
+        },
+};
 
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        /* PHY reset GPIO will be runtime programmed based on EVM version */
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -725,7 +724,7 @@ static void __init omap3_evm_init(void)
 
                 /* setup EHCI phy reset config */
                 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
-                usbhs_bdata.reset_gpio_port[1] = 21;
+                phy_data[0].reset_gpio = 21;
 
                 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
                 musb_board_data.power = 500;
@@ -733,10 +732,12 @@ static void __init omap3_evm_init(void)
         } else {
                 /* setup EHCI phy reset on MDC */
                 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
-                usbhs_bdata.reset_gpio_port[1] = 135;
+                phy_data[0].reset_gpio = 135;
         }
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(&musb_board_data);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         board_nand_init(omap3evm_nand_partitions,
                         ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 2bba362148a0..1004d2aaa68f 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -346,7 +346,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
 };
 
 static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
-        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
+        REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"),     /* hsusb port 2 */
 };
 
 /* ads7846 on SPI and 2 nub controllers on I2C */
@@ -561,6 +561,14 @@ fail:
         printk(KERN_ERR "wl1251 board initialisation failed\n");
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 16,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_leds_gpio,
         &pandora_keys_gpio,
@@ -569,15 +577,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 16,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -601,7 +601,10 @@ static void __init omap3pandora_init(void)
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
         omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
+
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
         gpmc_nand_init(&pandora_nand_data, NULL);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 495b989f9040..8afbba0923d6 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -357,19 +357,20 @@ static int __init omap3_stalker_i2c_init(void)
 
 #define OMAP3_STALKER_TS_GPIO   175
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 21,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3_stalker_devices[] __initdata = {
         &keys_gpio,
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = -EINVAL,
-        .reset_gpio_port[1] = 21,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -406,6 +407,8 @@ static void __init omap3_stalker_init(void)
         omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
 
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index bcd44fbcd877..7da48bc42bbf 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -305,21 +305,22 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 147,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3_touchbook_devices[] __initdata = {
         &leds_gpio,
         &keys_gpio,
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 147,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static void omap3_touchbook_poweroff(void)
@@ -368,6 +369,8 @@ static void __init omap3_touchbook_init(void)
         omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         board_nand_init(omap3touchbook_nand_partitions,
                         ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index b02c2f00609b..a71ad345f20d 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -31,6 +31,7 @@
 #include <linux/ti_wilink_st.h>
 #include <linux/usb/musb.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 #include <linux/wl12xx.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
@@ -132,6 +133,22 @@ static struct platform_device btwilink_device = {
         .id     = -1,
 };
 
+/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */
+static struct nop_usb_xceiv_platform_data hsusb1_phy_data = {
+        /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
+        .clk_rate = 19200000,
+};
+
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = GPIO_HUB_NRESET,
+                .vcc_gpio = GPIO_HUB_POWER,
+                .vcc_polarity = 1,
+                .platform_data = &hsusb1_phy_data,
+        },
+};
+
 static struct platform_device *panda_devices[] __initdata = {
         &leds_gpio,
         &wl1271_device,
@@ -142,49 +159,19 @@ static struct platform_device *panda_devices[] __initdata = {
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset  = false,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
-};
-
-static struct gpio panda_ehci_gpios[] __initdata = {
-        { GPIO_HUB_POWER,       GPIOF_OUT_INIT_LOW,  "hub_power"  },
-        { GPIO_HUB_NRESET,      GPIOF_OUT_INIT_LOW,  "hub_nreset" },
 };
 
 static void __init omap4_ehci_init(void)
 {
         int ret;
-        struct clk *phy_ref_clk;
 
         /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-        phy_ref_clk = clk_get(NULL, "auxclk3_ck");
-        if (IS_ERR(phy_ref_clk)) {
-                pr_err("Cannot request auxclk3\n");
-                return;
-        }
-        clk_set_rate(phy_ref_clk, 19200000);
-        clk_prepare_enable(phy_ref_clk);
-
-        /* disable the power to the usb hub prior to init and reset phy+hub */
-        ret = gpio_request_array(panda_ehci_gpios,
-                                 ARRAY_SIZE(panda_ehci_gpios));
-        if (ret) {
-                pr_err("Unable to initialize EHCI power/reset\n");
-                return;
-        }
-
-        gpio_export(GPIO_HUB_POWER, 0);
-        gpio_export(GPIO_HUB_NRESET, 0);
-        gpio_set_value(GPIO_HUB_NRESET, 1);
+        ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
+        if (ret)
+                pr_err("Failed to add main_clk alias to auxclk3_ck\n");
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
-
-        /* enable power to hub */
-        gpio_set_value(GPIO_HUB_POWER, 1);
 }
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 630833235cbc..f9101407cd56 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -457,14 +457,16 @@ static int __init overo_spi_init(void)
         return 0;
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = OVERO_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = OVERO_GPIO_USBH_NRESET,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -501,6 +503,8 @@ static void __init overo_init(void)
                         ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         overo_spi_init();
         overo_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 5e4d4c9fe61a..1a3dd865d8eb 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -92,14 +92,16 @@ static struct mtd_partition zoom_nand_partitions[] = {
         },
 };
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = ZOOM3_EHCI_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0]           = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1]           = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2]           = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset              = true,
-        .reset_gpio_port[0]     = -EINVAL,
-        .reset_gpio_port[1]     = ZOOM3_EHCI_RESET_GPIO,
-        .reset_gpio_port[2]     = -EINVAL,
 };
 
 static void __init omap_zoom_init(void)
@@ -109,6 +111,8 @@ static void __init omap_zoom_init(void)
         } else if (machine_is_omap_zoom3()) {
                 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
                 omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT);
+
+                usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
                 usbhs_init(&usbhs_bdata);
         }
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index df00e7580aa7..d555cf2459e1 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -82,8 +82,7 @@ extern void omap2_init_common_infrastructure(void);
 extern void omap2_sync32k_timer_init(void);
 extern void omap3_sync32k_timer_init(void);
 extern void omap3_secure_sync32k_timer_init(void);
-extern void omap3_gp_gptimer_timer_init(void);
-extern void omap3_am33xx_gptimer_timer_init(void);
+extern void omap3_gptimer_timer_init(void);
 extern void omap4_local_timer_init(void);
 extern void omap5_realtime_timer_init(void);
 
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index afc1e8c32d6c..d9c27195caf0 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -74,14 +74,6 @@ static int omap2_nand_gpmc_retime(
         t.cs_wr_off = gpmc_t->cs_wr_off;
         t.wr_cycle = gpmc_t->wr_cycle;
 
-        /* Configure GPMC */
-        if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
-        else
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
-        gpmc_cs_configure(gpmc_nand_data->cs,
-                        GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
-        gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
         err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
         if (err)
                 return err;
@@ -115,14 +107,18 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                    struct gpmc_timings *gpmc_t)
 {
         int err = 0;
+        struct gpmc_settings s;
         struct device *dev = &gpmc_nand_device.dev;
 
+        memset(&s, 0, sizeof(struct gpmc_settings));
+
         gpmc_nand_device.dev.platform_data = gpmc_nand_data;
 
         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
                                 (unsigned long *)&gpmc_nand_resource[0].start);
         if (err < 0) {
-                dev_err(dev, "Cannot request GPMC CS\n");
+                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
+                        gpmc_nand_data->cs, err);
                 return err;
         }
 
@@ -140,11 +136,31 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                         dev_err(dev, "Unable to set gpmc timings: %d\n", err);
                         return err;
                 }
-        }
 
-        /* Enable RD PIN Monitoring Reg */
-        if (gpmc_nand_data->dev_ready) {
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
+                if (gpmc_nand_data->of_node) {
+                        gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
+                } else {
+                        s.device_nand = true;
+
+                        /* Enable RD PIN Monitoring Reg */
+                        if (gpmc_nand_data->dev_ready) {
+                                s.wait_on_read = true;
+                                s.wait_on_write = true;
+                        }
+                }
+
+                if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+                        s.device_width = GPMC_DEVWIDTH_16BIT;
+                else
+                        s.device_width = GPMC_DEVWIDTH_8BIT;
+
+                err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
+                if (err < 0)
+                        goto out_free_cs;
+
+                err = gpmc_configure(GPMC_CONFIG_WP, 0);
+                if (err < 0)
+                        goto out_free_cs;
         }
 
         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 0d75889c0a6f..64b5a8346982 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -47,11 +47,23 @@ static struct platform_device gpmc_onenand_device = {
         .resource       = &gpmc_onenand_resource,
 };
 
-static struct gpmc_timings omap2_onenand_calc_async_timings(void)
+static struct gpmc_settings onenand_async = {
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
+
+static struct gpmc_settings onenand_sync = {
+        .burst_read     = true,
+        .burst_wrap     = true,
+        .burst_len      = GPMC_BURST_16,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+        .wait_pin       = 0,
+};
+
+static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
 {
         struct gpmc_device_timings dev_t;
-        struct gpmc_timings t;
-
         const int t_cer = 15;
         const int t_avdp = 12;
         const int t_aavdh = 7;
@@ -64,7 +76,6 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
         dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
         dev_t.t_avdp_w = dev_t.t_avdp_r;
         dev_t.t_aavdh = t_aavdh * 1000;
@@ -76,19 +87,7 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
         dev_t.t_wpl = t_wpl * 1000;
         dev_t.t_wph = t_wph * 1000;
 
-        gpmc_calc_timings(&t, &dev_t);
-
-        return t;
-}
-
-static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
-{
-        /* Configure GPMC for asynchronous read */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_DEVICESIZE_16 |
-                          GPMC_CONFIG1_MUXADDDATA);
-
-        return gpmc_cs_set_timings(cs, t);
+        gpmc_calc_timings(t, &onenand_async, &dev_t);
 }
 
 static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
@@ -158,12 +157,11 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
         return freq;
 }
 
-static struct gpmc_timings
-omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
-                                int freq)
+static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
+                                            unsigned int flags,
+                                            int freq)
 {
         struct gpmc_device_timings dev_t;
-        struct gpmc_timings t;
         const int t_cer  = 15;
         const int t_avdp = 12;
         const int t_cez  = 20; /* max of t_cez, t_oez */
@@ -172,9 +170,9 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
         int div, gpmc_clk_ns;
 
-        if (cfg->flags & ONENAND_SYNC_READ)
+        if (flags & ONENAND_SYNC_READ)
                 onenand_flags = ONENAND_FLAG_SYNCREAD;
-        else if (cfg->flags & ONENAND_SYNC_READWRITE)
+        else if (flags & ONENAND_SYNC_READWRITE)
                 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
 
         switch (freq) {
@@ -239,10 +237,11 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         /* Set synchronous read timings */
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-        dev_t.sync_read = true;
+        if (onenand_flags & ONENAND_FLAG_SYNCREAD)
+                onenand_sync.sync_read = true;
         if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
-                dev_t.sync_write = true;
+                onenand_sync.sync_write = true;
+                onenand_sync.burst_write = true;
         } else {
                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
                 dev_t.t_wpl = t_wpl * 1000;
@@ -265,32 +264,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         dev_t.cyc_aavdh_oe = 1;
         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
 
-        gpmc_calc_timings(&t, &dev_t);
-
-        return t;
-}
-
-static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
-{
-        unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
-        unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
-
-        /* Configure GPMC for synchronous read */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_WRAPBURST_SUPP |
-                          GPMC_CONFIG1_READMULTIPLE_SUPP |
-                          (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
-                          (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
-                          (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
-                          GPMC_CONFIG1_PAGE_LEN(2) |
-                          (cpu_is_omap34xx() ? 0 :
-                                (GPMC_CONFIG1_WAIT_READ_MON |
-                                 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
-                          GPMC_CONFIG1_DEVICESIZE_16 |
-                          GPMC_CONFIG1_DEVICETYPE_NOR |
-                          GPMC_CONFIG1_MUXADDDATA);
-
-        return gpmc_cs_set_timings(cs, t);
+        gpmc_calc_timings(t, &onenand_sync, &dev_t);
 }
 
 static int omap2_onenand_setup_async(void __iomem *onenand_base)
@@ -298,11 +272,19 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
         struct gpmc_timings t;
         int ret;
 
+        if (gpmc_onenand_data->of_node)
+                gpmc_read_settings_dt(gpmc_onenand_data->of_node,
+                                      &onenand_async);
+
         omap2_onenand_set_async_mode(onenand_base);
 
-        t = omap2_onenand_calc_async_timings();
+        omap2_onenand_calc_async_timings(&t);
+
+        ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
+        if (ret < 0)
+                return ret;
 
-        ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
         if (ret < 0)
                 return ret;
 
@@ -322,9 +304,25 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
                 set_onenand_cfg(onenand_base);
         }
 
-        t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
+        if (gpmc_onenand_data->of_node) {
+                gpmc_read_settings_dt(gpmc_onenand_data->of_node,
+                                      &onenand_sync);
+        } else {
+                /*
+                 * FIXME: Appears to be legacy code from initial ONENAND commit.
+                 * Unclear what boards this is for and if this can be removed.
+                 */
+                if (!cpu_is_omap34xx())
+                        onenand_sync.wait_on_read = true;
+        }
 
-        ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
+        omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
+
+        ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
+        if (ret < 0)
+                return ret;
+
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
         if (ret < 0)
                 return ret;
 
@@ -359,6 +357,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
         int err;
+        struct device *dev = &gpmc_onenand_device.dev;
 
         gpmc_onenand_data = _onenand_data;
         gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
@@ -366,7 +365,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 
         if (cpu_is_omap24xx() &&
                         (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
-                printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
+                dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
                 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
                 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
         }
@@ -379,7 +378,8 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
         err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
                                 (unsigned long *)&gpmc_onenand_resource.start);
         if (err < 0) {
-                pr_err("%s: Cannot request GPMC CS\n", __func__);
+                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
+                        gpmc_onenand_data->cs, err);
                 return;
         }
 
@@ -387,7 +387,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
                                                         ONENAND_IO_SIZE - 1;
 
         if (platform_device_register(&gpmc_onenand_device) < 0) {
-                pr_err("%s: Unable to register OneNAND device\n", __func__);
+                dev_err(dev, "Unable to register OneNAND device\n");
                 gpmc_cs_free(gpmc_onenand_data->cs);
                 return;
         }
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 11d0b756f098..61a063595e66 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -49,6 +49,10 @@ static struct platform_device gpmc_smc91x_device = {
         .resource       = gpmc_smc91x_resources,
 };
 
+static struct gpmc_settings smc91x_settings = {
+        .device_width = GPMC_DEVWIDTH_16BIT,
+};
+
 /*
  * Set the gpmc timings for smc91c96. The timings are taken
  * from the data sheet available at:
@@ -67,18 +71,6 @@ static int smc91c96_gpmc_retime(void)
         const int t7 = 5;       /* Figure 12.4 write */
         const int t8 = 5;       /* Figure 12.4 write */
         const int t20 = 185;    /* Figure 12.2 read and 12.4 write */
-        u32 l;
-
-        l = GPMC_CONFIG1_DEVICESIZE_16;
-        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
-                l |= GPMC_CONFIG1_MUXADDDATA;
-        if (gpmc_cfg->flags & GPMC_READ_MON)
-                l |= GPMC_CONFIG1_WAIT_READ_MON;
-        if (gpmc_cfg->flags & GPMC_WRITE_MON)
-                l |= GPMC_CONFIG1_WAIT_WRITE_MON;
-        if (gpmc_cfg->wait_pin)
-                l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin);
-        gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l);
 
         /*
          * FIXME: Calculate the address and data bus muxed timings.
@@ -104,7 +96,7 @@ static int smc91c96_gpmc_retime(void)
         dev_t.t_cez_w = t4_w * 1000;
         dev_t.t_wr_cycle = (t20 - t3) * 1000;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &smc91x_settings, &dev_t);
 
         return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
 }
@@ -133,6 +125,18 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
         gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
         gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
 
+        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
+                smc91x_settings.mux_add_data = GPMC_MUX_AD;
+        if (gpmc_cfg->flags & GPMC_READ_MON)
+                smc91x_settings.wait_on_read = true;
+        if (gpmc_cfg->flags & GPMC_WRITE_MON)
+                smc91x_settings.wait_on_write = true;
+        if (gpmc_cfg->wait_pin)
+                smc91x_settings.wait_pin = gpmc_cfg->wait_pin;
+        ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings);
+        if (ret < 0)
+                goto free1;
+
         if (gpmc_cfg->retime) {
                 ret = gpmc_cfg->retime();
                 if (ret != 0)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6de31739b45c..ed946df5ad8a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -26,6 +26,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_mtd.h>
 #include <linux/of_device.h>
 #include <linux/mtd/nand.h>
@@ -91,9 +92,7 @@
 #define GPMC_CS_SIZE            0x30
 #define GPMC_BCH_SIZE           0x10
 
-#define GPMC_MEM_START          0x00000000
 #define GPMC_MEM_END            0x3FFFFFFF
-#define BOOT_ROM_SPACE          0x100000        /* 1MB */
 
 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
@@ -107,6 +106,9 @@
 
 #define GPMC_HAS_WR_ACCESS              0x1
 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
+#define GPMC_HAS_MUX_AAD                0x4
+
+#define GPMC_NR_WAITPINS                4
 
 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  */
@@ -153,6 +155,7 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 /* Define chip-selects as reserved by default until probe completes */
 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
+static unsigned int gpmc_nr_waitpins;
 static struct device *gpmc_dev;
 static int gpmc_irq;
 static resource_size_t phys_base, mem_size;
@@ -181,7 +184,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
         __raw_writel(val, reg_addr);
 }
 
-u32 gpmc_cs_read_reg(int cs, int idx)
+static u32 gpmc_cs_read_reg(int cs, int idx)
 {
         void __iomem *reg_addr;
 
@@ -190,7 +193,7 @@ u32 gpmc_cs_read_reg(int cs, int idx)
 }
 
 /* TODO: Add support for gpmc_fck to clock framework and use it */
-unsigned long gpmc_get_fclk_period(void)
+static unsigned long gpmc_get_fclk_period(void)
 {
         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 
@@ -205,7 +208,7 @@ unsigned long gpmc_get_fclk_period(void)
         return rate;
 }
 
-unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
+static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 {
         unsigned long tick_ps;
 
@@ -215,7 +218,7 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 }
 
-unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
+static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 {
         unsigned long tick_ps;
 
@@ -230,13 +233,6 @@ unsigned int gpmc_ticks_to_ns(unsigned int ticks)
         return ticks * gpmc_get_fclk_period() / 1000;
 }
 
-unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
-{
-        unsigned long ticks = gpmc_ns_to_ticks(time_ns);
-
-        return ticks * gpmc_get_fclk_period() / 1000;
-}
-
 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 {
         return ticks * gpmc_get_fclk_period();
@@ -405,11 +401,18 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
         return 0;
 }
 
-static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
+static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
 {
         u32 l;
         u32 mask;
 
+        /*
+         * Ensure that base address is aligned on a
+         * boundary equal to or greater than size.
+         */
+        if (base & (size - 1))
+                return -EINVAL;
+
         mask = (1 << GPMC_SECTION_SHIFT) - size;
         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
         l &= ~0x3f;
@@ -418,6 +421,8 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
         l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
         l |= GPMC_CONFIG7_CSVALID;
         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
+
+        return 0;
 }
 
 static void gpmc_cs_disable_mem(int cs)
@@ -448,22 +453,14 @@ static int gpmc_cs_mem_enabled(int cs)
         return l & GPMC_CONFIG7_CSVALID;
 }
 
-int gpmc_cs_set_reserved(int cs, int reserved)
+static void gpmc_cs_set_reserved(int cs, int reserved)
 {
-        if (cs > GPMC_CS_NUM)
-                return -ENODEV;
-
         gpmc_cs_map &= ~(1 << cs);
         gpmc_cs_map |= (reserved ? 1 : 0) << cs;
-
-        return 0;
 }
 
-int gpmc_cs_reserved(int cs)
+static bool gpmc_cs_reserved(int cs)
 {
-        if (cs > GPMC_CS_NUM)
-                return -ENODEV;
-
         return gpmc_cs_map & (1 << cs);
 }
 
@@ -510,6 +507,39 @@ static int gpmc_cs_delete_mem(int cs)
         return r;
 }
 
+/**
+ * gpmc_cs_remap - remaps a chip-select physical base address
+ * @cs:         chip-select to remap
+ * @base:       physical base address to re-map chip-select to
+ *
+ * Re-maps a chip-select to a new physical base address specified by
+ * "base". Returns 0 on success and appropriate negative error code
+ * on failure.
+ */
+static int gpmc_cs_remap(int cs, u32 base)
+{
+        int ret;
+        u32 old_base, size;
+
+        if (cs > GPMC_CS_NUM)
+                return -ENODEV;
+        gpmc_cs_get_memconf(cs, &old_base, &size);
+        if (base == old_base)
+                return 0;
+        gpmc_cs_disable_mem(cs);
+        ret = gpmc_cs_delete_mem(cs);
+        if (ret < 0)
+                return ret;
+        ret = gpmc_cs_insert_mem(cs, base, size);
+        if (ret < 0)
+                return ret;
+        ret = gpmc_cs_enable_mem(cs, base, size);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
         struct resource *res = &gpmc_cs_mem[cs];
@@ -535,7 +565,12 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
         if (r < 0)
                 goto out;
 
-        gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+        r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+        if (r < 0) {
+                release_resource(res);
+                goto out;
+        }
+
         *base = res->start;
         gpmc_cs_set_reserved(cs, 1);
 out:
@@ -561,16 +596,14 @@ void gpmc_cs_free(int cs)
 EXPORT_SYMBOL(gpmc_cs_free);
 
 /**
- * gpmc_cs_configure - write request to configure gpmc
- * @cs: chip select number
+ * gpmc_configure - write request to configure gpmc
  * @cmd: command type
  * @wval: value to write
  * @return status of the operation
  */
-int gpmc_cs_configure(int cs, int cmd, int wval)
+int gpmc_configure(int cmd, int wval)
 {
-        int err = 0;
-        u32 regval = 0;
+        u32 regval;
 
         switch (cmd) {
         case GPMC_ENABLE_IRQ:
@@ -590,43 +623,14 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
                 gpmc_write_reg(GPMC_CONFIG, regval);
                 break;
 
-        case GPMC_CONFIG_RDY_BSY:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                if (wval)
-                        regval |= WR_RD_PIN_MONITORING;
-                else
-                        regval &= ~WR_RD_PIN_MONITORING;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
-        case GPMC_CONFIG_DEV_SIZE:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                /* clear 2 target bits */
-                regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
-
-                /* set the proper value */
-                regval |= GPMC_CONFIG1_DEVICESIZE(wval);
-
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
-        case GPMC_CONFIG_DEV_TYPE:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                regval |= GPMC_CONFIG1_DEVICETYPE(wval);
-                if (wval == GPMC_DEVICETYPE_NOR)
-                        regval |= GPMC_CONFIG1_MUXADDDATA;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
         default:
-                printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
-                err = -EINVAL;
+                pr_err("%s: command not supported\n", __func__);
+                return -EINVAL;
         }
 
-        return err;
+        return 0;
 }
-EXPORT_SYMBOL(gpmc_cs_configure);
+EXPORT_SYMBOL(gpmc_configure);
 
 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 {
@@ -781,16 +785,16 @@ static void gpmc_mem_exit(void)
 
 }
 
-static int gpmc_mem_init(void)
+static void gpmc_mem_init(void)
 {
-        int cs, rc;
-        unsigned long boot_rom_space = 0;
+        int cs;
 
-        /* never allocate the first page, to facilitate bug detection;
-         * even if we didn't boot from ROM.
+        /*
+         * The first 1MB of GPMC address space is typically mapped to
+         * the internal ROM. Never allocate the first page, to
+         * facilitate bug detection; even if we didn't boot from ROM.
          */
-        boot_rom_space = BOOT_ROM_SPACE;
-        gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
+        gpmc_mem_root.start = SZ_1M;
         gpmc_mem_root.end = GPMC_MEM_END;
 
         /* Reserve all regions that has been set up by bootloader */
@@ -800,16 +804,12 @@ static int gpmc_mem_init(void)
                 if (!gpmc_cs_mem_enabled(cs))
                         continue;
                 gpmc_cs_get_memconf(cs, &base, &size);
-                rc = gpmc_cs_insert_mem(cs, base, size);
-                if (rc < 0) {
-                        while (--cs >= 0)
-                                if (gpmc_cs_mem_enabled(cs))
-                                        gpmc_cs_delete_mem(cs);
-                        return rc;
+                if (gpmc_cs_insert_mem(cs, base, size)) {
+                        pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
+                                __func__, cs, base, base + size);
+                        gpmc_cs_disable_mem(cs);
                 }
         }
-
-        return 0;
 }
 
 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
@@ -825,9 +825,9 @@ static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
 
 /* XXX: can the cycles be avoided ? */
 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                       struct gpmc_device_timings *dev_t,
+                                       bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_rd_off */
@@ -880,9 +880,9 @@ static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                        struct gpmc_device_timings *dev_t,
+                                        bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_wr_off */
@@ -942,9 +942,9 @@ static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                        struct gpmc_device_timings *dev_t,
+                                        bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_rd_off */
@@ -982,9 +982,9 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                         struct gpmc_device_timings *dev_t,
+                                         bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_wr_off */
@@ -1054,7 +1054,8 @@ static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
+                                    struct gpmc_device_timings *dev_t,
+                                    bool sync)
 {
         u32 temp;
 
@@ -1068,7 +1069,7 @@ static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
                                 gpmc_t->cs_on + dev_t->t_ce_avd);
         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
 
-        if (dev_t->sync_write || dev_t->sync_read)
+        if (sync)
                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
 
         return 0;
@@ -1103,21 +1104,29 @@ static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
 }
 
 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
+                      struct gpmc_settings *gpmc_s,
+                      struct gpmc_device_timings *dev_t)
 {
+        bool mux = false, sync = false;
+
+        if (gpmc_s) {
+                mux = gpmc_s->mux_add_data ? true : false;
+                sync = (gpmc_s->sync_read || gpmc_s->sync_write);
+        }
+
         memset(gpmc_t, 0, sizeof(*gpmc_t));
 
-        gpmc_calc_common_timings(gpmc_t, dev_t);
+        gpmc_calc_common_timings(gpmc_t, dev_t, sync);
 
-        if (dev_t->sync_read)
-                gpmc_calc_sync_read_timings(gpmc_t, dev_t);
+        if (gpmc_s && gpmc_s->sync_read)
+                gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
         else
-                gpmc_calc_async_read_timings(gpmc_t, dev_t);
+                gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
 
-        if (dev_t->sync_write)
-                gpmc_calc_sync_write_timings(gpmc_t, dev_t);
+        if (gpmc_s && gpmc_s->sync_write)
+                gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
         else
-                gpmc_calc_async_write_timings(gpmc_t, dev_t);
+                gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
 
         /* TODO: remove, see function definition */
         gpmc_convert_ps_to_ns(gpmc_t);
@@ -1125,6 +1134,90 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
         return 0;
 }
 
+/**
+ * gpmc_cs_program_settings - programs non-timing related settings
+ * @cs:         GPMC chip-select to program
+ * @p:          pointer to GPMC settings structure
+ *
+ * Programs non-timing related settings for a GPMC chip-select, such as
+ * bus-width, burst configuration, etc. Function should be called once
+ * for each chip-select that is being used and must be called before
+ * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
+ * register will be initialised to zero by this function. Returns 0 on
+ * success and appropriate negative error code on failure.
+ */
+int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
+{
+        u32 config1;
+
+        if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
+                pr_err("%s: invalid width %d!", __func__, p->device_width);
+                return -EINVAL;
+        }
+
+        /* Address-data multiplexing not supported for NAND devices */
+        if (p->device_nand && p->mux_add_data) {
+                pr_err("%s: invalid configuration!\n", __func__);
+                return -EINVAL;
+        }
+
+        if ((p->mux_add_data > GPMC_MUX_AD) ||
+            ((p->mux_add_data == GPMC_MUX_AAD) &&
+             !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
+                pr_err("%s: invalid multiplex configuration!\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
+        if (p->burst_read || p->burst_write) {
+                switch (p->burst_len) {
+                case GPMC_BURST_4:
+                case GPMC_BURST_8:
+                case GPMC_BURST_16:
+                        break;
+                default:
+                        pr_err("%s: invalid page/burst-length (%d)\n",
+                               __func__, p->burst_len);
+                        return -EINVAL;
+                }
+        }
+
+        if ((p->wait_on_read || p->wait_on_write) &&
+            (p->wait_pin > gpmc_nr_waitpins)) {
+                pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
+                return -EINVAL;
+        }
+
+        config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
+
+        if (p->sync_read)
+                config1 |= GPMC_CONFIG1_READTYPE_SYNC;
+        if (p->sync_write)
+                config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
+        if (p->wait_on_read)
+                config1 |= GPMC_CONFIG1_WAIT_READ_MON;
+        if (p->wait_on_write)
+                config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
+        if (p->wait_on_read || p->wait_on_write)
+                config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
+        if (p->device_nand)
+                config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
+        if (p->mux_add_data)
+                config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
+        if (p->burst_read)
+                config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
+        if (p->burst_write)
+                config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
+        if (p->burst_read || p->burst_write) {
+                config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
+                config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
+        }
+
+        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
+
+        return 0;
+}
+
 #ifdef CONFIG_OF
 static struct of_device_id gpmc_dt_ids[] = {
         { .compatible = "ti,omap2420-gpmc" },
@@ -1136,70 +1229,110 @@ static struct of_device_id gpmc_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
 
+/**
+ * gpmc_read_settings_dt - read gpmc settings from device-tree
+ * @np:         pointer to device-tree node for a gpmc child device
+ * @p:          pointer to gpmc settings structure
+ *
+ * Reads the GPMC settings for a GPMC child device from device-tree and
+ * stores them in the GPMC settings structure passed. The GPMC settings
+ * structure is initialised to zero by this function and so any
+ * previously stored settings will be cleared.
+ */
+void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
+{
+        memset(p, 0, sizeof(struct gpmc_settings));
+
+        p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
+        p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
+        p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
+        of_property_read_u32(np, "gpmc,device-width", &p->device_width);
+        of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
+
+        if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
+                p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
+                p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
+                p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
+                if (!p->burst_read && !p->burst_write)
+                        pr_warn("%s: page/burst-length set but not used!\n",
+                                __func__);
+        }
+
+        if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
+                p->wait_on_read = of_property_read_bool(np,
+                                                        "gpmc,wait-on-read");
+                p->wait_on_write = of_property_read_bool(np,
+                                                         "gpmc,wait-on-write");
+                if (!p->wait_on_read && !p->wait_on_write)
+                        pr_warn("%s: read/write wait monitoring not enabled!\n",
+                                __func__);
+        }
+}
+
 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
                                                 struct gpmc_timings *gpmc_t)
 {
-        u32 val;
+        struct gpmc_bool_timings *p;
+
+        if (!np || !gpmc_t)
+                return;
 
         memset(gpmc_t, 0, sizeof(*gpmc_t));
 
         /* minimum clock period for syncronous mode */
-        if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
-                gpmc_t->sync_clk = val;
+        of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
 
         /* chip select timtings */
-        if (!of_property_read_u32(np, "gpmc,cs-on", &val))
-                gpmc_t->cs_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
-                gpmc_t->cs_rd_off = val;
-
-        if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
-                gpmc_t->cs_wr_off = val;
+        of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
+        of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
+        of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
 
         /* ADV signal timings */
-        if (!of_property_read_u32(np, "gpmc,adv-on", &val))
-                gpmc_t->adv_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
-                gpmc_t->adv_rd_off = val;
-
-        if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
-                gpmc_t->adv_wr_off = val;
+        of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
+        of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
+        of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
 
         /* WE signal timings */
-        if (!of_property_read_u32(np, "gpmc,we-on", &val))
-                gpmc_t->we_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,we-off", &val))
-                gpmc_t->we_off = val;
+        of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
+        of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
 
         /* OE signal timings */
-        if (!of_property_read_u32(np, "gpmc,oe-on", &val))
-                gpmc_t->oe_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,oe-off", &val))
-                gpmc_t->oe_off = val;
+        of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
+        of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
 
         /* access and cycle timings */
-        if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
-                gpmc_t->page_burst_access = val;
-
-        if (!of_property_read_u32(np, "gpmc,access", &val))
-                gpmc_t->access = val;
-
-        if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
-                gpmc_t->rd_cycle = val;
-
-        if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
-                gpmc_t->wr_cycle = val;
-
-        /* only for OMAP3430 */
-        if (!of_property_read_u32(np, "gpmc,wr-access", &val))
-                gpmc_t->wr_access = val;
-
-        if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
-                gpmc_t->wr_data_mux_bus = val;
+        of_property_read_u32(np, "gpmc,page-burst-access-ns",
+                             &gpmc_t->page_burst_access);
+        of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
+        of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
+        of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
+        of_property_read_u32(np, "gpmc,bus-turnaround-ns",
+                             &gpmc_t->bus_turnaround);
+        of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
+                             &gpmc_t->cycle2cycle_delay);
+        of_property_read_u32(np, "gpmc,wait-monitoring-ns",
+                             &gpmc_t->wait_monitoring);
+        of_property_read_u32(np, "gpmc,clk-activation-ns",
+                             &gpmc_t->clk_activation);
+
+        /* only applicable to OMAP3+ */
+        of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
+        of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
+                             &gpmc_t->wr_data_mux_bus);
+
+        /* bool timing parameters */
+        p = &gpmc_t->bool_timings;
+
+        p->cycle2cyclediffcsen =
+                of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
+        p->cycle2cyclesamecsen =
+                of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
+        p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
+        p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
+        p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
+        p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
+        p->time_para_granularity =
+                of_property_read_bool(np, "gpmc,time-para-granularity");
 }
 
 #ifdef CONFIG_MTD_NAND
@@ -1295,6 +1428,81 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev,
 }
 #endif
 
+/**
+ * gpmc_probe_generic_child - configures the gpmc for a child device
+ * @pdev:       pointer to gpmc platform device
+ * @child:      pointer to device-tree node for child device
+ *
+ * Allocates and configures a GPMC chip-select for a child device.
+ * Returns 0 on success and appropriate negative error code on failure.
+ */
+static int gpmc_probe_generic_child(struct platform_device *pdev,
+                                struct device_node *child)
+{
+        struct gpmc_settings gpmc_s;
+        struct gpmc_timings gpmc_t;
+        struct resource res;
+        unsigned long base;
+        int ret, cs;
+
+        if (of_property_read_u32(child, "reg", &cs) < 0) {
+                dev_err(&pdev->dev, "%s has no 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+
+        if (of_address_to_resource(child, 0, &res) < 0) {
+                dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+
+        ret = gpmc_cs_request(cs, resource_size(&res), &base);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
+                return ret;
+        }
+
+        /*
+         * FIXME: gpmc_cs_request() will map the CS to an arbitary
+         * location in the gpmc address space. When booting with
+         * device-tree we want the NOR flash to be mapped to the
+         * location specified in the device-tree blob. So remap the
+         * CS to this location. Once DT migration is complete should
+         * just make gpmc_cs_request() map a specific address.
+         */
+        ret = gpmc_cs_remap(cs, res.start);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",
+                        cs, res.start);
+                goto err;
+        }
+
+        gpmc_read_settings_dt(child, &gpmc_s);
+
+        ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
+        if (ret < 0)
+                goto err;
+
+        ret = gpmc_cs_program_settings(cs, &gpmc_s);
+        if (ret < 0)
+                goto err;
+
+        gpmc_read_timings_dt(child, &gpmc_t);
+        gpmc_cs_set_timings(cs, &gpmc_t);
+
+        if (of_platform_device_create(child, NULL, &pdev->dev))
+                return 0;
+
+        dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
+        ret = -ENODEV;
+
+err:
+        gpmc_cs_free(cs);
+
+        return ret;
+}
+
 static int gpmc_probe_dt(struct platform_device *pdev)
 {
         int ret;
@@ -1305,6 +1513,13 @@ static int gpmc_probe_dt(struct platform_device *pdev)
         if (!of_id)
                 return 0;
 
+        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
+                                   &gpmc_nr_waitpins);
+        if (ret < 0) {
+                pr_err("%s: number of wait pins not found!\n", __func__);
+                return ret;
+        }
+
         for_each_node_by_name(child, "nand") {
                 ret = gpmc_probe_nand_child(pdev, child);
                 if (ret < 0) {
@@ -1320,6 +1535,23 @@ static int gpmc_probe_dt(struct platform_device *pdev)
                         return ret;
                 }
         }
+
+        for_each_node_by_name(child, "nor") {
+                ret = gpmc_probe_generic_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+
+        for_each_node_by_name(child, "ethernet") {
+                ret = gpmc_probe_generic_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+
         return 0;
 }
 #else
@@ -1364,18 +1596,27 @@ static int gpmc_probe(struct platform_device *pdev)
         gpmc_dev = &pdev->dev;
 
         l = gpmc_read_reg(GPMC_REVISION);
+
+        /*
+         * FIXME: Once device-tree migration is complete the below flags
+         * should be populated based upon the device-tree compatible
+         * string. For now just use the IP revision. OMAP3+ devices have
+         * the wr_access and wr_data_mux_bus register fields. OMAP4+
+         * devices support the addr-addr-data multiplex protocol.
+         *
+         * GPMC IP revisions:
+         * - OMAP24xx                   = 2.0
+         * - OMAP3xxx                   = 5.0
+         * - OMAP44xx/54xx/AM335x       = 6.0
+         */
         if (GPMC_REVISION_MAJOR(l) > 0x4)
                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
+        if (GPMC_REVISION_MAJOR(l) > 0x5)
+                gpmc_capability |= GPMC_HAS_MUX_AAD;
         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
                  GPMC_REVISION_MINOR(l));
 
-        rc = gpmc_mem_init();
-        if (rc < 0) {
-                clk_disable_unprepare(gpmc_l3_clk);
-                clk_put(gpmc_l3_clk);
-                dev_err(gpmc_dev, "failed to reserve memory\n");
-                return rc;
-        }
+        gpmc_mem_init();
 
         if (gpmc_setup_irq() < 0)
                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
@@ -1383,6 +1624,9 @@ static int gpmc_probe(struct platform_device *pdev)
         /* Now the GPMC is initialised, unreserve the chip-selects */
         gpmc_cs_map = 0;
 
+        if (!pdev->dev.of_node)
+                gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+
         rc = gpmc_probe_dt(pdev);
         if (rc < 0) {
                 clk_disable_unprepare(gpmc_l3_clk);
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index fe0a844d5007..707f6d58edd5 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -58,7 +58,7 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
@@ -73,6 +73,13 @@
 #define GPMC_IRQ_FIFOEVENTENABLE        0x01
 #define GPMC_IRQ_COUNT_EVENT            0x02
 
+#define GPMC_BURST_4                    4       /* 4 word burst */
+#define GPMC_BURST_8                    8       /* 8 word burst */
+#define GPMC_BURST_16                   16      /* 16 word burst */
+#define GPMC_DEVWIDTH_8BIT              1       /* 8-bit device width */
+#define GPMC_DEVWIDTH_16BIT             2       /* 16-bit device width */
+#define GPMC_MUX_AAD                    1       /* Addr-Addr-Data multiplex */
+#define GPMC_MUX_AD                     2       /* Addr-Data multiplex */
 
 /* bool type time settings */
 struct gpmc_bool_timings {
@@ -178,10 +185,6 @@ struct gpmc_device_timings {
         u8 cyc_wpl;     /* write deassertion time in cycles */
         u32 cyc_iaa;    /* initial access time in cycles */
 
-        bool mux;       /* address & data muxed */
-        bool sync_write;/* synchronous write */
-        bool sync_read; /* synchronous read */
-
         /* extra delays */
         bool ce_xdelay;
         bool avd_xdelay;
@@ -189,28 +192,40 @@ struct gpmc_device_timings {
         bool we_xdelay;
 };
 
+struct gpmc_settings {
+        bool burst_wrap;        /* enables wrap bursting */
+        bool burst_read;        /* enables read page/burst mode */
+        bool burst_write;       /* enables write page/burst mode */
+        bool device_nand;       /* device is NAND */
+        bool sync_read;         /* enables synchronous reads */
+        bool sync_write;        /* enables synchronous writes */
+        bool wait_on_read;      /* monitor wait on reads */
+        bool wait_on_write;     /* monitor wait on writes */
+        u32 burst_len;          /* page/burst length */
+        u32 device_width;       /* device bus width (8 or 16 bit) */
+        u32 mux_add_data;       /* multiplex address & data */
+        u32 wait_pin;           /* wait-pin to be used */
+};
+
 extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t);
+                             struct gpmc_settings *gpmc_s,
+                             struct gpmc_device_timings *dev_t);
 
 extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
 extern int gpmc_get_client_irq(unsigned irq_config);
 
-extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
-extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
-extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
-extern unsigned long gpmc_get_fclk_period(void);
 
 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
-extern u32 gpmc_cs_read_reg(int cs, int idx);
 extern int gpmc_calc_divider(unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
+extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
-extern int gpmc_cs_set_reserved(int cs, int reserved);
-extern int gpmc_cs_reserved(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern int gpmc_cs_configure(int cs, int cmd, int wval);
+extern int gpmc_configure(int cmd, int wval);
+extern void gpmc_read_settings_dt(struct device_node *np,
+                                  struct gpmc_settings *p);
 
 #endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 63e6384fa72e..f12aa6c15da4 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -57,16 +57,6 @@
 #include "common.h"
 #include "powerdomain.h"
 
-/* Parent clocks, eventually these will come from the clock framework */
-
-#define OMAP2_MPU_SOURCE        "sys_ck"
-#define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
-#define OMAP4_MPU_SOURCE        "sys_clkin_ck"
-#define OMAP5_MPU_SOURCE        "sys_clkin"
-#define OMAP2_32K_SOURCE        "func_32k_ck"
-#define OMAP3_32K_SOURCE        "omap_32k_fck"
-#define OMAP4_32K_SOURCE        "sys_32k_ck"
-
 #define REALTIME_COUNTER_BASE                           0x48243200
 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
@@ -130,7 +120,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 }
 
 static struct clock_event_device clockevent_gpt = {
-        .name           = "gp_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 300,
         .set_next_event = omap2_gp_timer_set_next_event,
@@ -171,6 +160,12 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
                 if (property && !of_get_property(np, property, NULL))
                         continue;
 
+                if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
+                                  of_get_property(np, "ti,timer-dsp", NULL) ||
+                                  of_get_property(np, "ti,timer-pwm", NULL) ||
+                                  of_get_property(np, "ti,timer-secure", NULL)))
+                        continue;
+
                 of_add_property(np, &device_disabled);
                 return np;
         }
@@ -215,16 +210,17 @@ static u32 __init omap_dm_timer_get_errata(void)
 }
 
 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
-                                                int gptimer_id,
-                                                const char *fck_source,
-                                                const char *property,
-                                                int posted)
+                                         const char *fck_source,
+                                         const char *property,
+                                         const char **timer_name,
+                                         int posted)
 {
         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
         const char *oh_name;
         struct device_node *np;
         struct omap_hwmod *oh;
         struct resource irq, mem;
+        struct clk *src;
         int r = 0;
 
         if (of_have_populated_dt()) {
@@ -244,10 +240,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 
                 of_node_put(np);
         } else {
-                if (omap_dm_timer_reserve_systimer(gptimer_id))
+                if (omap_dm_timer_reserve_systimer(timer->id))
                         return -ENODEV;
 
-                sprintf(name, "timer%d", gptimer_id);
+                sprintf(name, "timer%d", timer->id);
                 oh_name = name;
         }
 
@@ -255,6 +251,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         if (!oh)
                 return -ENODEV;
 
+        *timer_name = oh->name;
+
         if (!of_have_populated_dt()) {
                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
                                                    &irq);
@@ -277,24 +275,24 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         /* After the dmtimer is using hwmod these clocks won't be needed */
         timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
         if (IS_ERR(timer->fclk))
-                return -ENODEV;
+                return PTR_ERR(timer->fclk);
 
-        /* FIXME: Need to remove hard-coded test on timer ID */
-        if (gptimer_id != 12) {
-                struct clk *src;
-
-                src = clk_get(NULL, fck_source);
-                if (IS_ERR(src)) {
-                        r = -EINVAL;
-                } else {
-                        r = clk_set_parent(timer->fclk, src);
-                        if (r < 0)
-                                pr_warn("%s: %s cannot set source\n",
-                                        __func__, oh->name);
+        src = clk_get(NULL, fck_source);
+        if (IS_ERR(src))
+                return PTR_ERR(src);
+
+        if (clk_get_parent(timer->fclk) != src) {
+                r = clk_set_parent(timer->fclk, src);
+                if (r < 0) {
+                        pr_warn("%s: %s cannot set source\n", __func__,
+                                oh->name);
                         clk_put(src);
+                        return r;
                 }
         }
 
+        clk_put(src);
+
         omap_hwmod_setup_one(oh_name);
         omap_hwmod_enable(oh);
         __omap_dm_timer_init_regs(timer);
@@ -318,6 +316,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 {
         int res;
 
+        clkev.id = gptimer_id;
         clkev.errata = omap_dm_timer_get_errata();
 
         /*
@@ -327,8 +326,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
          */
         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 
-        res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
-                                     OMAP_TIMER_POSTED);
+        res = omap_dm_timer_init_one(&clkev, fck_source, property,
+                                     &clockevent_gpt.name, OMAP_TIMER_POSTED);
         BUG_ON(res);
 
         omap2_gp_timer_irq.dev_id = &clkev;
@@ -342,8 +341,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
                                         3, /* Timer internal resynch latency */
                                         0xffffffff);
 
-        pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
-                gptimer_id, clkev.rate);
+        pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
+                clkev.rate);
 }
 
 /* Clocksource code */
@@ -360,7 +359,6 @@ static cycle_t clocksource_read_cycles(struct clocksource *cs)
 }
 
 static struct clocksource clocksource_gpt = {
-        .name           = "gp_timer",
         .rating         = 300,
         .read           = clocksource_read_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
@@ -443,13 +441,16 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 }
 
 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
-                                                const char *fck_source)
+                                                  const char *fck_source,
+                                                  const char *property)
 {
         int res;
 
+        clksrc.id = gptimer_id;
         clksrc.errata = omap_dm_timer_get_errata();
 
-        res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
+        res = omap_dm_timer_init_one(&clksrc, fck_source, property,
+                                     &clocksource_gpt.name,
                                      OMAP_TIMER_NONPOSTED);
         BUG_ON(res);
 
@@ -462,8 +463,8 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
                 pr_err("Could not register clocksource %s\n",
                         clocksource_gpt.name);
         else
-                pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
-                        gptimer_id, clksrc.rate);
+                pr_info("OMAP clocksource: %s at %lu Hz\n",
+                        clocksource_gpt.name, clksrc.rate);
 }
 
 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
@@ -488,7 +489,7 @@ static void __init realtime_counter_init(void)
                 pr_err("%s: ioremap failed\n", __func__);
                 return;
         }
-        sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE);
+        sys_clk = clk_get(NULL, "sys_clkin");
         if (IS_ERR(sys_clk)) {
                 pr_err("%s: failed to get system clock handle\n", __func__);
                 iounmap(base);
@@ -545,53 +546,52 @@ static inline void __init realtime_counter_init(void)
 #endif
 
 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
-                               clksrc_nr, clksrc_src)                   \
+                               clksrc_nr, clksrc_src, clksrc_prop)      \
 void __init omap##name##_gptimer_timer_init(void)                       \
 {                                                                       \
-        if (omap_clk_init)                                              \
-                omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
-        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
+        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,         \
+                                        clksrc_prop);                   \
 }
 
 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
-                                clksrc_nr, clksrc_src)                  \
+                                clksrc_nr, clksrc_src, clksrc_prop)     \
 void __init omap##name##_sync32k_timer_init(void)               \
 {                                                                       \
-        if (omap_clk_init)                                              \
-                omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
         if (use_gptimer_clksrc)                                         \
-                omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
+                omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
+                                                clksrc_prop);           \
         else                                                            \
                 omap2_sync32k_clocksource_init();                       \
 }
 
 #ifdef CONFIG_ARCH_OMAP2
-OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP2_MPU_SOURCE);
+OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
+                        2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP2 */
 
 #ifdef CONFIG_ARCH_OMAP3
-OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
-                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
-                       2, OMAP3_MPU_SOURCE);
+OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
+                        2, "timer_sys_ck", NULL);
+OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
+                        2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP3 */
 
-#ifdef CONFIG_SOC_AM33XX
-OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
-                       2, OMAP4_MPU_SOURCE);
-#endif /* CONFIG_SOC_AM33XX */
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
+OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
+                       1, "timer_sys_ck", "ti,timer-alwon");
+#endif
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
+                               2, "sys_clkin_ck", NULL);
+#endif
 
 #ifdef CONFIG_ARCH_OMAP4
-OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP4_MPU_SOURCE);
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 void __init omap4_local_timer_init(void)
@@ -620,13 +620,11 @@ void __init omap4_local_timer_init(void)
 #endif /* CONFIG_ARCH_OMAP4 */
 
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP5_MPU_SOURCE);
 void __init omap5_realtime_timer_init(void)
 {
         int err;
 
-        omap5_sync32k_timer_init();
+        omap4_sync32k_timer_init();
         realtime_counter_init();
 
         err = arch_timer_of_register();
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 5706bdccf45e..aa27d7f5cbb7 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -22,8 +22,12 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/dma-mapping.h>
-
-#include <asm/io.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/string.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/usb/phy.h>
 
 #include "soc.h"
 #include "omap_device.h"
@@ -526,3 +530,155 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
 }
 
 #endif
+
+/* Template for PHY regulators */
+static struct fixed_voltage_config hsusb_reg_config = {
+        /* .supply_name filled later */
+        .microvolts = 3300000,
+        .gpio = -1,             /* updated later */
+        .startup_delay = 70000, /* 70msec */
+        .enable_high = 1,       /* updated later */
+        .enabled_at_boot = 0,   /* keep in RESET */
+        /* .init_data filled later */
+};
+
+static const char *nop_name = "nop_usb_xceiv"; /* NOP PHY driver */
+static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */
+
+/**
+ * usbhs_add_regulator - Add a gpio based fixed voltage regulator device
+ * @name: name for the regulator
+ * @dev_id: device id of the device this regulator supplies power to
+ * @dev_supply: supply name that the device expects
+ * @gpio: GPIO number
+ * @polarity: 1 - Active high, 0 - Active low
+ */
+static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
+                                                int gpio, int polarity)
+{
+        struct regulator_consumer_supply *supplies;
+        struct regulator_init_data *reg_data;
+        struct fixed_voltage_config *config;
+        struct platform_device *pdev;
+        int ret;
+
+        supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
+        if (!supplies)
+                return -ENOMEM;
+
+        supplies->supply = dev_supply;
+        supplies->dev_name = dev_id;
+
+        reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
+        if (!reg_data)
+                return -ENOMEM;
+
+        reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
+        reg_data->consumer_supplies = supplies;
+        reg_data->num_consumer_supplies = 1;
+
+        config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
+                        GFP_KERNEL);
+        if (!config)
+                return -ENOMEM;
+
+        config->supply_name = name;
+        config->gpio = gpio;
+        config->enable_high = polarity;
+        config->init_data = reg_data;
+
+        /* create a regulator device */
+        pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+        if (!pdev)
+                return -ENOMEM;
+
+        pdev->id = PLATFORM_DEVID_AUTO;
+        pdev->name = reg_name;
+        pdev->dev.platform_data = config;
+
+        ret = platform_device_register(pdev);
+        if (ret)
+                pr_err("%s: Failed registering regulator %s for %s\n",
+                                __func__, name, dev_id);
+
+        return ret;
+}
+
+int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
+{
+        char *rail_name;
+        int i, len;
+        struct platform_device *pdev;
+        char *phy_id;
+
+        /* the phy_id will be something like "nop_usb_xceiv.1" */
+        len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */
+
+        for (i = 0; i < num_phys; i++) {
+
+                if (!phy->port) {
+                        pr_err("%s: Invalid port 0. Must start from 1\n",
+                                                __func__);
+                        continue;
+                }
+
+                /* do we need a NOP PHY device ? */
+                if (!gpio_is_valid(phy->reset_gpio) &&
+                        !gpio_is_valid(phy->vcc_gpio))
+                        continue;
+
+                /* create a NOP PHY device */
+                pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+                if (!pdev)
+                        return -ENOMEM;
+
+                pdev->id = phy->port;
+                pdev->name = nop_name;
+                pdev->dev.platform_data = phy->platform_data;
+
+                phy_id = kmalloc(len, GFP_KERNEL);
+                if (!phy_id)
+                        return -ENOMEM;
+
+                scnprintf(phy_id, len, "nop_usb_xceiv.%d\n",
+                                        pdev->id);
+
+                if (platform_device_register(pdev)) {
+                        pr_err("%s: Failed to register device %s\n",
+                                __func__,  phy_id);
+                        continue;
+                }
+
+                usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id);
+
+                /* Do we need RESET regulator ? */
+                if (gpio_is_valid(phy->reset_gpio)) {
+
+                        rail_name = kmalloc(13, GFP_KERNEL);
+                        if (!rail_name)
+                                return -ENOMEM;
+
+                        scnprintf(rail_name, 13, "hsusb%d_reset", phy->port);
+
+                        usbhs_add_regulator(rail_name, phy_id, "reset",
+                                                phy->reset_gpio, 1);
+                }
+
+                /* Do we need VCC regulator ? */
+                if (gpio_is_valid(phy->vcc_gpio)) {
+
+                        rail_name = kmalloc(13, GFP_KERNEL);
+                        if (!rail_name)
+                                return -ENOMEM;
+
+                        scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port);
+
+                        usbhs_add_regulator(rail_name, phy_id, "vcc",
+                                        phy->vcc_gpio, phy->vcc_polarity);
+                }
+
+                phy++;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index c5a3c6f9504e..e832bc7b8e2d 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/err.h>
 #include <linux/string.h>
 #include <linux/types.h>
 #include <linux/errno.h>
@@ -26,6 +27,24 @@
 static u8               async_cs, sync_cs;
 static unsigned         refclk_psec;
 
+static struct gpmc_settings tusb_async = {
+        .wait_on_read   = true,
+        .wait_on_write  = true,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
+
+static struct gpmc_settings tusb_sync = {
+        .burst_read     = true,
+        .burst_write    = true,
+        .sync_read      = true,
+        .sync_write     = true,
+        .wait_on_read   = true,
+        .wait_on_write  = true,
+        .burst_len      = GPMC_BURST_16,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
 
 /* NOTE:  timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
 
@@ -37,8 +56,6 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-
         dev_t.t_ceasu = 8 * 1000;
         dev_t.t_avdasu = t_acsnh_advnh - 7000;
         dev_t.t_ce_avd = 1000;
@@ -52,7 +69,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
         dev_t.t_wpl = 300;
         dev_t.cyc_aavdh_we = 1;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &tusb_async, &dev_t);
 
         return gpmc_cs_set_timings(async_cs, &t);
 }
@@ -65,10 +82,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-        dev_t.sync_read = true;
-        dev_t.sync_write = true;
-
         dev_t.clk = 11100;
         dev_t.t_bacc = 1000;
         dev_t.t_ces = 1000;
@@ -84,7 +97,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
         dev_t.cyc_wpl = 6;
         dev_t.t_ce_rdyz = 7000;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &tusb_sync, &dev_t);
 
         return gpmc_cs_set_timings(sync_cs, &t);
 }
@@ -165,18 +178,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                 return status;
         }
         tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
+        tusb_async.wait_pin = waitpin;
         async_cs = async;
-        gpmc_cs_write_reg(async, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_PAGE_LEN(2)
-                        | GPMC_CONFIG1_WAIT_READ_MON
-                        | GPMC_CONFIG1_WAIT_WRITE_MON
-                        | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
-                        | GPMC_CONFIG1_READTYPE_ASYNC
-                        | GPMC_CONFIG1_WRITETYPE_ASYNC
-                        | GPMC_CONFIG1_DEVICESIZE_16
-                        | GPMC_CONFIG1_DEVICETYPE_NOR
-                        | GPMC_CONFIG1_MUXADDDATA);
 
+        status = gpmc_cs_program_settings(async_cs, &tusb_async);
+        if (status < 0)
+                return status;
 
         /* SYNC region, primarily for DMA */
         status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
@@ -186,21 +193,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                 return status;
         }
         tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
+        tusb_sync.wait_pin = waitpin;
         sync_cs = sync;
-        gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_READMULTIPLE_SUPP
-                        | GPMC_CONFIG1_READTYPE_SYNC
-                        | GPMC_CONFIG1_WRITEMULTIPLE_SUPP
-                        | GPMC_CONFIG1_WRITETYPE_SYNC
-                        | GPMC_CONFIG1_PAGE_LEN(2)
-                        | GPMC_CONFIG1_WAIT_READ_MON
-                        | GPMC_CONFIG1_WAIT_WRITE_MON
-                        | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
-                        | GPMC_CONFIG1_DEVICESIZE_16
-                        | GPMC_CONFIG1_DEVICETYPE_NOR
-                        | GPMC_CONFIG1_MUXADDDATA
-                        /* fclk divider gets set later */
-                        );
+
+        status = gpmc_cs_program_settings(sync_cs, &tusb_sync);
+        if (status < 0)
+                return status;
 
         /* IRQ */
         status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq");
diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h
index 3319f5cf47a3..e7261ebcf7b0 100644
--- a/arch/arm/mach-omap2/usb.h
+++ b/arch/arm/mach-omap2/usb.h
@@ -53,8 +53,17 @@
 #define USBPHY_OTGSESSEND_EN    (1 << 20)
 #define USBPHY_DATA_POLARITY    (1 << 23)
 
+struct usbhs_phy_data {
+        int port;               /* 1 indexed port number */
+        int reset_gpio;
+        int vcc_gpio;
+        bool vcc_polarity;      /* 1 active high, 0 active low */
+        void *platform_data;
+};
+
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
 extern void usbhs_init(struct usbhs_omap_platform_data *pdata);
+extern int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys);
 
 extern void am35x_musb_reset(void);
 extern void am35x_musb_phy_power(u8 on);
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 8d5fa6ece014..f2f7088bfd22 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -30,6 +30,7 @@ config CPU_S3C2410
         select S3C2410_CLOCK
         select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
         select S3C2410_PM if PM
+        select SAMSUNG_HRT
         help
           Support for S3C2410 and S3C2410A family from the S3C24XX line
           of Samsung Mobile CPUs.
@@ -40,6 +41,7 @@ config CPU_S3C2412
         select CPU_LLSERIAL_S3C2440
         select S3C2412_DMA if S3C24XX_DMA
         select S3C2412_PM if PM
+        select SAMSUNG_HRT
         help
           Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
 
@@ -51,6 +53,7 @@ config CPU_S3C2416
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
+        select SAMSUNG_HRT
         help
           Support for the S3C2416 SoC from the S3C24XX line
 
@@ -61,6 +64,7 @@ config CPU_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
         select S3C2440_DMA if S3C24XX_DMA
+        select SAMSUNG_HRT
         help
           Support for S3C2440 Samsung Mobile CPU based systems.
 
@@ -70,6 +74,7 @@ config CPU_S3C2442
         select CPU_LLSERIAL_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
+        select SAMSUNG_HRT
         help
           Support for S3C2442 Samsung Mobile CPU based systems.
 
@@ -84,6 +89,7 @@ config CPU_S3C2443
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
+        select SAMSUNG_HRT
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
@@ -395,6 +401,7 @@ config S3C2412_DMA
 config S3C2412_PM
         bool
         select S3C2412_PM_SLEEP
+        select SAMSUNG_WAKEMASK
         help
           Internal config node to apply S3C2412 power management
 
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index af53d27d5c36..6f46ecfc8396 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,7 +14,7 @@ obj-				:=
 
 # core
 
-obj-y                           += common.o irq.o
+obj-y                           += common.o
 
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
 obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
@@ -22,7 +22,7 @@ obj-$(CONFIG_S3C2410_DMA)	+= dma-s3c2410.o
 obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 
-obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o irq-s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o clock-s3c2412.o
 obj-$(CONFIG_S3C2412_CPUFREQ)   += cpufreq-s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
@@ -31,9 +31,9 @@ obj-$(CONFIG_S3C2412_PM_SLEEP)	+= sleep-s3c2412.o
 obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock-s3c2416.o
 obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
 
-obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o irq-s3c2440.o clock-s3c2440.o
+obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o clock-s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o irq-s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o clock-s3c244x.o
 obj-$(CONFIG_S3C2440_CPUFREQ)   += cpufreq-s3c2440.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index 8a2b4137ddb6..307c3714be55 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -21,6 +21,7 @@ extern void s3c2410_map_io(void);
 extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2410_init_clocks(int xtal);
 extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_init_irq(void);
 #else
 #define s3c2410_init_clocks NULL
 #define s3c2410_init_uarts NULL
@@ -36,6 +37,7 @@ extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void s3c2412_init_clocks(int xtal);
 extern  int s3c2412_baseclk_add(void);
 extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_init_irq(void);
 #else
 #define s3c2412_init_clocks NULL
 #define s3c2412_init_uarts NULL
@@ -73,6 +75,7 @@ extern void s3c244x_restart(char mode, const char *cmd);
 #ifdef CONFIG_CPU_S3C2440
 extern  int s3c2440_init(void);
 extern void s3c2440_map_io(void);
+extern void s3c2440_init_irq(void);
 #else
 #define s3c2440_init NULL
 #define s3c2440_map_io NULL
@@ -81,6 +84,7 @@ extern void s3c2440_map_io(void);
 #ifdef CONFIG_CPU_S3C2442
 extern  int s3c2442_init(void);
 extern void s3c2442_map_io(void);
+extern void s3c2442_init_irq(void);
 #else
 #define s3c2442_init NULL
 #define s3c2442_map_io NULL
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
deleted file mode 100644
index 6a21beeba1da..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-s3c2410/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for S3C2410-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-/* We have a problem that the INTOFFSET register does not always
- * show one interrupt. Occasionally we get two interrupts through
- * the prioritiser, and this causes the INTOFFSET register to show
- * what looks like the logical-or of the two interrupt numbers.
- *
- * Thanks to Klaus, Shannon, et al for helping to debug this problem
-*/
-
-#define INTPND          (0x10)
-#define INTOFFSET       (0x14)
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                mov     \base, #S3C24XX_VA_IRQ
-
-                @@ try the interrupt offset register, since it is there
-
-                ldr     \irqstat, [\base, #INTPND ]
-                teq     \irqstat, #0
-                beq     1002f
-                ldr     \irqnr, [\base, #INTOFFSET ]
-                mov     \tmp, #1
-                tst     \irqstat, \tmp, lsl \irqnr
-                bne     1001f
-
-                @@ the number specified is not a valid irq, so try
-                @@ and work it out for ourselves
-
-                mov     \irqnr, #0              @@ start here
-
-                @@ work out which irq (if any) we got
-
-                movs    \tmp, \irqstat, lsl#16
-                addeq   \irqnr, \irqnr, #16
-                moveq   \irqstat, \irqstat, lsr#16
-                tst     \irqstat, #0xff
-                addeq   \irqnr, \irqnr, #8
-                moveq   \irqstat, \irqstat, lsr#8
-                tst     \irqstat, #0xf
-                addeq   \irqnr, \irqnr, #4
-                moveq   \irqstat, \irqstat, lsr#4
-                tst     \irqstat, #0x3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \irqstat, \irqstat, lsr#2
-                tst     \irqstat, #0x1
-                addeq   \irqnr, \irqnr, #1
-
-                @@ we have the value
-1001:
-                adds    \irqnr, \irqnr, #IRQ_EINT0
-1002:
-                @@ exit here, Z flag unset if IRQ
-
-        .endm
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index 1e73f5fa8659..b6dd4cb5a2ec 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -59,49 +59,53 @@
 #define IRQ_ADCPARENT  S3C2410_IRQ(31)
 
 /* interrupts generated from the external interrupts sources */
-#define IRQ_EINT4      S3C2410_IRQ(32)     /* 48 */
-#define IRQ_EINT5      S3C2410_IRQ(33)
-#define IRQ_EINT6      S3C2410_IRQ(34)
-#define IRQ_EINT7      S3C2410_IRQ(35)
-#define IRQ_EINT8      S3C2410_IRQ(36)
-#define IRQ_EINT9      S3C2410_IRQ(37)
-#define IRQ_EINT10     S3C2410_IRQ(38)
-#define IRQ_EINT11     S3C2410_IRQ(39)
-#define IRQ_EINT12     S3C2410_IRQ(40)
-#define IRQ_EINT13     S3C2410_IRQ(41)
-#define IRQ_EINT14     S3C2410_IRQ(42)
-#define IRQ_EINT15     S3C2410_IRQ(43)
-#define IRQ_EINT16     S3C2410_IRQ(44)
-#define IRQ_EINT17     S3C2410_IRQ(45)
-#define IRQ_EINT18     S3C2410_IRQ(46)
-#define IRQ_EINT19     S3C2410_IRQ(47)
-#define IRQ_EINT20     S3C2410_IRQ(48)     /* 64 */
-#define IRQ_EINT21     S3C2410_IRQ(49)
-#define IRQ_EINT22     S3C2410_IRQ(50)
-#define IRQ_EINT23     S3C2410_IRQ(51)
+#define IRQ_EINT0_2412 S3C2410_IRQ(32)
+#define IRQ_EINT1_2412 S3C2410_IRQ(33)
+#define IRQ_EINT2_2412 S3C2410_IRQ(34)
+#define IRQ_EINT3_2412 S3C2410_IRQ(35)
+#define IRQ_EINT4      S3C2410_IRQ(36)     /* 52 */
+#define IRQ_EINT5      S3C2410_IRQ(37)
+#define IRQ_EINT6      S3C2410_IRQ(38)
+#define IRQ_EINT7      S3C2410_IRQ(39)
+#define IRQ_EINT8      S3C2410_IRQ(40)
+#define IRQ_EINT9      S3C2410_IRQ(41)
+#define IRQ_EINT10     S3C2410_IRQ(42)
+#define IRQ_EINT11     S3C2410_IRQ(43)
+#define IRQ_EINT12     S3C2410_IRQ(44)
+#define IRQ_EINT13     S3C2410_IRQ(45)
+#define IRQ_EINT14     S3C2410_IRQ(46)
+#define IRQ_EINT15     S3C2410_IRQ(47)
+#define IRQ_EINT16     S3C2410_IRQ(48)
+#define IRQ_EINT17     S3C2410_IRQ(49)
+#define IRQ_EINT18     S3C2410_IRQ(50)
+#define IRQ_EINT19     S3C2410_IRQ(51)
+#define IRQ_EINT20     S3C2410_IRQ(52)     /* 68 */
+#define IRQ_EINT21     S3C2410_IRQ(53)
+#define IRQ_EINT22     S3C2410_IRQ(54)
+#define IRQ_EINT23     S3C2410_IRQ(55)
 
 #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
 #define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
 
-#define IRQ_LCD_FIFO   S3C2410_IRQ(52)
-#define IRQ_LCD_FRAME  S3C2410_IRQ(53)
+#define IRQ_LCD_FIFO   S3C2410_IRQ(56)
+#define IRQ_LCD_FRAME  S3C2410_IRQ(57)
 
 /* IRQs for the interal UARTs, and ADC
  * these need to be ordered in number of appearance in the
  * SUBSRC mask register
 */
 
-#define S3C2410_IRQSUB(x)       S3C2410_IRQ((x)+54)
+#define S3C2410_IRQSUB(x)       S3C2410_IRQ((x)+58)
 
-#define IRQ_S3CUART_RX0         S3C2410_IRQSUB(0)       /* 70 */
+#define IRQ_S3CUART_RX0         S3C2410_IRQSUB(0)       /* 74 */
 #define IRQ_S3CUART_TX0         S3C2410_IRQSUB(1)
 #define IRQ_S3CUART_ERR0        S3C2410_IRQSUB(2)
 
-#define IRQ_S3CUART_RX1         S3C2410_IRQSUB(3)       /* 73 */
+#define IRQ_S3CUART_RX1         S3C2410_IRQSUB(3)       /* 77 */
 #define IRQ_S3CUART_TX1         S3C2410_IRQSUB(4)
 #define IRQ_S3CUART_ERR1        S3C2410_IRQSUB(5)
 
-#define IRQ_S3CUART_RX2         S3C2410_IRQSUB(6)       /* 76 */
+#define IRQ_S3CUART_RX2         S3C2410_IRQSUB(6)       /* 80 */
 #define IRQ_S3CUART_TX2         S3C2410_IRQSUB(7)
 #define IRQ_S3CUART_ERR2        S3C2410_IRQSUB(8)
 
@@ -136,7 +140,7 @@
 
 /* second interrupt-register of s3c2416/s3c2450 */
 
-#define S3C2416_IRQ(x)          S3C2410_IRQ((x) + 54 + 29)
+#define S3C2416_IRQ(x)          S3C2410_IRQ((x) + 58 + 29)
 #define IRQ_S3C2416_2D          S3C2416_IRQ(0)
 #define IRQ_S3C2416_IIC1        S3C2416_IRQ(1)
 #define IRQ_S3C2416_RESERVED2   S3C2416_IRQ(2)
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2412.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
deleted file mode 100644
index 67d763178d3f..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2412.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* linux/arch/arm/mach-s3c2412/irq.c
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/irq.h>
-#include <plat/pm.h>
-
-#include "s3c2412-power.h"
-
-#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
-#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
-
-/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
- * having them turn up in both the INT* and the EINT* registers. Whilst
- * both show the status, they both now need to be acked when the IRQs
- * go off.
-*/
-
-static void
-s3c2412_irq_mask(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask | bitval, S3C2410_INTMSK);
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask | bitval, S3C2412_EINTMASK);
-}
-
-static inline void
-s3c2412_irq_ack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-
-        __raw_writel(bitval, S3C2412_EINTPEND);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-
-static inline void
-s3c2412_irq_maskack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask|bitval, S3C2410_INTMSK);
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask | bitval, S3C2412_EINTMASK);
-
-        __raw_writel(bitval, S3C2412_EINTPEND);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-
-static void
-s3c2412_irq_unmask(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask & ~bitval, S3C2410_INTMSK);
-}
-
-static struct irq_chip s3c2412_irq_eint0t4 = {
-        .irq_ack        = s3c2412_irq_ack,
-        .irq_mask       = s3c2412_irq_mask,
-        .irq_unmask     = s3c2412_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake,
-        .irq_set_type   = s3c_irqext_type,
-};
-
-#define INTBIT(x)       (1 << ((x) - S3C2410_IRQSUB(0)))
-
-/* CF and SDI sub interrupts */
-
-static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc  &= ~submsk;
-
-        if (subsrc & INTBIT(IRQ_S3C2412_SDI))
-                generic_handle_irq(IRQ_S3C2412_SDI);
-
-        if (subsrc & INTBIT(IRQ_S3C2412_CF))
-                generic_handle_irq(IRQ_S3C2412_CF);
-}
-
-#define INTMSK_CFSDI    (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
-#define SUBMSK_CFSDI    INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
-
-static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
-}
-
-static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
-}
-
-static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
-}
-
-static struct irq_chip s3c2412_irq_cfsdi = {
-        .name           = "s3c2412-cfsdi",
-        .irq_ack        = s3c2412_irq_cfsdi_ack,
-        .irq_mask       = s3c2412_irq_cfsdi_mask,
-        .irq_unmask     = s3c2412_irq_cfsdi_unmask,
-};
-
-static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
-{
-        unsigned long pwrcfg;
-
-        pwrcfg = __raw_readl(S3C2412_PWRCFG);
-        if (state)
-                pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
-        else
-                pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
-        __raw_writel(pwrcfg, S3C2412_PWRCFG);
-
-        return s3c_irq_chip.irq_set_wake(data, state);
-}
-
-static struct irq_chip s3c2412_irq_rtc_chip;
-
-static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
-                                         handle_edge_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        /* add demux support for CF/SDI */
-
-        irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
-
-        for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        /* change RTC IRQ's set wake method */
-
-        s3c2412_irq_rtc_chip = s3c_irq_chip;
-        s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
-
-        irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
-
-        return 0;
-}
-
-static struct subsys_interface s3c2412_irq_interface = {
-        .name           = "s3c2412_irq",
-        .subsys         = &s3c2412_subsys,
-        .add_dev        = s3c2412_irq_add,
-};
-
-static int s3c2412_irq_init(void)
-{
-        return subsys_interface_register(&s3c2412_irq_interface);
-}
-
-arch_initcall(s3c2412_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2440.c b/arch/arm/mach-s3c24xx/irq-s3c2440.c
deleted file mode 100644
index 4a18cde439cc..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2440.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* linux/arch/arm/mach-s3c2440/irq.c
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-/* WDT/AC97 */
-
-static void s3c_irq_demux_wdtac97(unsigned int irq,
-                                  struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc &= ~submsk;
-        subsrc >>= 13;
-        subsrc &= 3;
-
-        if (subsrc != 0) {
-                if (subsrc & 1) {
-                        generic_handle_irq(IRQ_S3C2440_WDT);
-                }
-                if (subsrc & 2) {
-                        generic_handle_irq(IRQ_S3C2440_AC97);
-                }
-        }
-}
-
-
-#define INTMSK_WDT       (1UL << (IRQ_WDT - IRQ_EINT0))
-
-static void
-s3c_irq_wdtac97_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13);
-}
-
-static void
-s3c_irq_wdtac97_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_WDT);
-}
-
-static void
-s3c_irq_wdtac97_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13);
-}
-
-static struct irq_chip s3c_irq_wdtac97 = {
-        .irq_mask       = s3c_irq_wdtac97_mask,
-        .irq_unmask     = s3c_irq_wdtac97_unmask,
-        .irq_ack        = s3c_irq_wdtac97_ack,
-};
-
-static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        printk("S3C2440: IRQ Support\n");
-
-        /* add new chained handler for wdt, ac7 */
-
-        irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
-
-        for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        return 0;
-}
-
-static struct subsys_interface s3c2440_irq_interface = {
-        .name           = "s3c2440_irq",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c2440_irq_add,
-};
-
-static int s3c2440_irq_init(void)
-{
-        return subsys_interface_register(&s3c2440_irq_interface);
-}
-
-arch_initcall(s3c2440_irq_init);
-
diff --git a/arch/arm/mach-s3c24xx/irq-s3c244x.c b/arch/arm/mach-s3c24xx/irq-s3c244x.c
deleted file mode 100644
index 5fe8e58d3afd..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c244x.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-/* camera irq */
-
-static void s3c_irq_demux_cam(unsigned int irq,
-                              struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc &= ~submsk;
-        subsrc >>= 11;
-        subsrc &= 3;
-
-        if (subsrc != 0) {
-                if (subsrc & 1) {
-                        generic_handle_irq(IRQ_S3C2440_CAM_C);
-                }
-                if (subsrc & 2) {
-                        generic_handle_irq(IRQ_S3C2440_CAM_P);
-                }
-        }
-}
-
-#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
-
-static void
-s3c_irq_cam_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
-}
-
-static void
-s3c_irq_cam_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CAM);
-}
-
-static void
-s3c_irq_cam_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
-}
-
-static struct irq_chip s3c_irq_cam = {
-        .irq_mask       = s3c_irq_cam_mask,
-        .irq_unmask     = s3c_irq_cam_unmask,
-        .irq_ack        = s3c_irq_cam_ack,
-};
-
-static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        set_irq_flags(IRQ_NFCON, IRQF_VALID);
-
-        /* add chained handler for camera */
-
-        irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
-
-        for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c_irq_cam,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        return 0;
-}
-
-static struct subsys_interface s3c2440_irq_interface = {
-        .name           = "s3c2440_irq",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c244x_irq_add,
-};
-
-static int s3c2440_irq_init(void)
-{
-        return subsys_interface_register(&s3c2440_irq_interface);
-}
-
-arch_initcall(s3c2440_irq_init);
-
-static struct subsys_interface s3c2442_irq_interface = {
-        .name           = "s3c2442_irq",
-        .subsys         = &s3c2442_subsys,
-        .add_dev        = s3c244x_irq_add,
-};
-
-
-static int s3c2442_irq_init(void)
-{
-        return subsys_interface_register(&s3c2442_irq_interface);
-}
-
-arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 0e0279e79150..e27b5c91b3db 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -63,6 +63,8 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
 
+#include <plat/samsung-time.h>
+
 #include "common.h"
 
 static struct resource amlm5900_nor_resource =
@@ -160,6 +162,7 @@ static void __init amlm5900_map_io(void)
         s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 #ifdef CONFIG_FB_S3C2410
@@ -235,8 +238,8 @@ static void __init amlm5900_init(void)
 MACHINE_START(AML_M5900, "AML_M5900")
         .atag_offset    = 0x100,
         .map_io         = amlm5900_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = amlm5900_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index bb595f15ce36..c1fb6c37867f 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/samsung-time.h>
 
 #include "anubis.h"
 #include "common.h"
@@ -410,6 +411,7 @@ static void __init anubis_map_io(void)
         s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* check for the newer revision boards with large page nand */
 
@@ -443,7 +445,7 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
         .atag_offset    = 0x100,
         .map_io         = anubis_map_io,
         .init_machine   = anubis_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index b4bc60c78ebb..6dfeeb7ef469 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -48,6 +48,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/mmc-s3cmci.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -192,6 +193,7 @@ static void __init at2440evb_map_io(void)
         s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
         s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init at2440evb_init(void)
@@ -209,7 +211,7 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
         .atag_offset    = 0x100,
         .map_io         = at2440evb_map_io,
         .init_machine   = at2440evb_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index ca6618081041..22d6ae926d91 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -55,6 +55,7 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "bast.h"
 #include "common.h"
@@ -576,6 +577,7 @@ static void __init bast_map_io(void)
         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init bast_init(void)
@@ -603,8 +605,8 @@ MACHINE_START(BAST, "Simtec-BAST")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
         .atag_offset    = 0x100,
         .map_io         = bast_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = bast_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index a25e8c5a7b4c..13d8d073675a 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -81,6 +81,7 @@
 #include <plat/gpio-cfg.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "gta02.h"
@@ -501,6 +502,7 @@ static void __init gta02_map_io(void)
         s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 
@@ -587,8 +589,8 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
         /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
         .atag_offset    = 0x100,
         .map_io         = gta02_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2442_init_irq,
         .init_machine   = gta02_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 79bc0830d740..af4334d6b4d5 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -62,7 +62,7 @@
 #include <plat/pll.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
-
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -646,6 +646,7 @@ static void __init h1940_map_io(void)
         s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* setup PM */
 
@@ -666,11 +667,6 @@ static void __init h1940_reserve(void)
         memblock_reserve(0x30081000, 0x1000);
 }
 
-static void __init h1940_init_irq(void)
-{
-        s3c24xx_init_irq();
-}
-
 static void __init h1940_init(void)
 {
         u32 tmp;
@@ -739,8 +735,8 @@ MACHINE_START(H1940, "IPAQ-H1940")
         .atag_offset    = 0x100,
         .map_io         = h1940_map_io,
         .reserve        = h1940_reserve,
-        .init_irq       = h1940_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = h1940_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index ca08d7df07f7..a45fcd8ccf79 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -52,6 +52,7 @@
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "s3c2412-power.h"
@@ -506,6 +507,7 @@ static void __init jive_map_io(void)
         s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void jive_power_off(void)
@@ -658,9 +660,9 @@ MACHINE_START(JIVE, "JIVE")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .atag_offset    = 0x100,
 
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = jive_map_io,
         .init_machine   = jive_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 2865e5919f2c..a83db46320bc 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -56,6 +56,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include <sound/s3c24xx_uda134x.h>
 
@@ -525,6 +526,7 @@ static void __init mini2440_map_io(void)
         s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /*
@@ -686,7 +688,7 @@ MACHINE_START(MINI2440, "MINI2440")
         .atag_offset    = 0x100,
         .map_io         = mini2440_map_io,
         .init_machine   = mini2440_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 8017c0fc1729..2cb46c37c920 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <linux/platform_data/mmc-s3cmci.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -535,6 +536,7 @@ static void __init n30_map_io(void)
         n30_hwinit();
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /* GPB3 is the line that controls the pull-up for the USB D+ line */
@@ -588,9 +590,9 @@ MACHINE_START(N30, "Acer-N30")
                                 Ben Dooks <ben-linux@fluff.org>
         */
         .atag_offset    = 0x100,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
         .restart        = s3c2410_restart,
 MACHINE_END
@@ -599,9 +601,9 @@ MACHINE_START(N35, "Acer-N35")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>
         */
         .atag_offset    = 0x100,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 144b9f80c4a5..01f4354206f9 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -44,6 +44,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -135,6 +136,7 @@ static void __init nexcoder_map_io(void)
         s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         nexcoder_sensorboard_init();
 }
@@ -150,7 +152,7 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
         .atag_offset    = 0x100,
         .map_io         = nexcoder_map_io,
         .init_machine   = nexcoder_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index ae2cbdf3e3ca..58d6fbe5bf1f 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -45,6 +45,7 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
@@ -384,6 +385,7 @@ static void __init osiris_map_io(void)
         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* check for the newer revision boards with large page nand */
 
@@ -424,8 +426,8 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
         .atag_offset    = 0x100,
         .map_io         = osiris_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .init_machine   = osiris_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index deb0ace585b0..7e16b0740ec1 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -33,6 +33,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "otom.h"
@@ -101,6 +102,7 @@ static void __init otom11_map_io(void)
         s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init otom11_init(void)
@@ -114,7 +116,7 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         .atag_offset    = 0x100,
         .map_io         = otom11_map_io,
         .init_machine   = otom11_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2410_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 84c541602661..f8feaeadb55a 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -59,6 +59,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "common-smdk.h"
@@ -304,6 +305,7 @@ static void __init qt2410_map_io(void)
         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
         s3c24xx_init_clocks(12*1000*1000);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init qt2410_machine_init(void)
@@ -341,8 +343,8 @@ static void __init qt2410_machine_init(void)
 MACHINE_START(QT2410, "QT2410")
         .atag_offset    = 0x100,
         .map_io         = qt2410_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = qt2410_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 43f3ac5a1c7a..44ca018e1f96 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -57,6 +57,7 @@
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -740,6 +741,7 @@ static void __init rx1950_map_io(void)
         s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
         s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* setup PM */
 
@@ -810,8 +812,8 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
         .atag_offset = 0x100,
         .map_io = rx1950_map_io,
         .reserve        = rx1950_reserve,
-        .init_irq = s3c24xx_init_irq,
+        .init_irq       = s3c2442_init_irq,
         .init_machine = rx1950_init_machine,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index f20418a2fb1b..3bc6231d0a1f 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -179,6 +180,7 @@ static void __init rx3715_map_io(void)
         s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
         s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /* H1940 and RX3715 need to reserve this for suspend */
@@ -188,11 +190,6 @@ static void __init rx3715_reserve(void)
         memblock_reserve(0x30081000, 0x1000);
 }
 
-static void __init rx3715_init_irq(void)
-{
-        s3c24xx_init_irq();
-}
-
 static void __init rx3715_init_machine(void)
 {
 #ifdef CONFIG_PM_H1940
@@ -210,8 +207,8 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
         .atag_offset    = 0x100,
         .map_io         = rx3715_map_io,
         .reserve        = rx3715_reserve,
-        .init_irq       = rx3715_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .init_machine   = rx3715_init_machine,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index cd0b1635c47e..a773789e4f38 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -51,6 +51,7 @@
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "common-smdk.h"
@@ -100,6 +101,7 @@ static void __init smdk2410_map_io(void)
         s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2410_init(void)
@@ -114,8 +116,8 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
         /* Maintainer: Jonas Dietsche */
         .atag_offset    = 0x100,
         .map_io         = smdk2410_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = smdk2410_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 79485907950f..8146e920f10d 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -44,6 +44,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "common-smdk.h"
@@ -105,6 +106,7 @@ static void __init smdk2413_map_io(void)
         s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2413_machine_init(void)
@@ -128,10 +130,10 @@ MACHINE_START(S3C2413, "S3C2413")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -140,10 +142,10 @@ MACHINE_START(SMDK2412, "SMDK2412")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -152,9 +154,9 @@ MACHINE_START(SMDK2413, "SMDK2413")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index 037a5da343bd..cb46847c66b4 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -50,6 +50,7 @@
 #include <plat/sdhci.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/s3c-hsudc.h>
+#include <plat/samsung-time.h>
 
 #include <plat/fb.h>
 
@@ -221,6 +222,7 @@ static void __init smdk2416_map_io(void)
         s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2416_machine_init(void)
@@ -253,6 +255,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
         .init_irq       = s3c2416_init_irq,
         .map_io         = smdk2416_map_io,
         .init_machine   = smdk2416_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 29d31314e23c..de2e5d39a847 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -41,6 +41,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "common-smdk.h"
@@ -160,6 +161,7 @@ static void __init smdk2440_map_io(void)
         s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
         s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2440_machine_init(void)
@@ -175,9 +177,9 @@ MACHINE_START(S3C2440, "SMDK2440")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .atag_offset    = 0x100,
 
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .map_io         = smdk2440_map_io,
         .init_machine   = smdk2440_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index b3be4c4dc7bc..9435c3bef18a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -41,6 +41,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "common-smdk.h"
@@ -121,6 +122,7 @@ static void __init smdk2443_map_io(void)
         s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2443_machine_init(void)
@@ -142,6 +144,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
         .init_irq       = s3c2443_init_irq,
         .map_io         = smdk2443_map_io,
         .init_machine   = smdk2443_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 24b3d79e7b2c..7fad8f055cab 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -53,6 +53,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -136,6 +137,7 @@ static void __init tct_hammer_map_io(void)
         s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init tct_hammer_init(void)
@@ -147,8 +149,8 @@ static void __init tct_hammer_init(void)
 MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
         .atag_offset    = 0x100,
         .map_io         = tct_hammer_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = tct_hammer_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index ec42d1e4e465..42e7187fed60 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -45,6 +45,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "bast.h"
 #include "common.h"
@@ -332,6 +333,7 @@ static void __init vr1000_map_io(void)
         s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init vr1000_init(void)
@@ -353,7 +355,7 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
         .atag_offset    = 0x100,
         .map_io         = vr1000_map_io,
         .init_machine   = vr1000_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2410_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 239129c2d8bc..b66588428ec9 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -44,6 +44,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -142,6 +143,7 @@ static void __init vstms_map_io(void)
         s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init vstms_init(void)
@@ -156,9 +158,9 @@ MACHINE_START(VSTMS, "VSTMS")
         .atag_offset    = 0x100,
 
         .fixup          = vstms_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .init_machine   = vstms_init,
         .map_io         = vstms_map_io,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index 4c4bc1c83b77..d75f95e487ee 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -29,6 +29,7 @@
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/wakeup-mask.h>
 
 #include "regs-dsc.h"
 #include "s3c2412-power.h"
@@ -51,8 +52,15 @@ static int s3c2412_cpu_suspend(unsigned long arg)
         return 1; /* Aborting suspend */
 }
 
+/* mapping of interrupts to parts of the wakeup mask */
+static struct samsung_wakeup_mask wake_irqs[] = {
+        { .irq = IRQ_RTC,       .bit = S3C2412_PWRCFG_RTC_MASKIRQ, },
+};
+
 static void s3c2412_pm_prepare(void)
 {
+        samsung_sync_wakemask(S3C2412_PWRCFG,
+                              wake_irqs, ARRAY_SIZE(wake_irqs));
 }
 
 static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 131c86284711..283cb77d4721 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -17,11 +17,13 @@ config PLAT_S3C64XX
 # Configuration options for the S3C6410 CPU
 
 config CPU_S3C6400
+        select SAMSUNG_HRT
         bool
         help
           Enable S3C6400 CPU support
 
 config CPU_S3C6410
+        select SAMSUNG_HRT
         bool
         help
           Enable S3C6410 CPU support
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 728eef3296b2..35e3f54574ef 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <mach/regs-gpio.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -208,6 +209,7 @@ static void __init anw6410_map_io(void)
         s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         anw6410_lcd_mode_set();
 }
@@ -232,6 +234,6 @@ MACHINE_START(ANW6410, "A&W6410")
         .map_io         = anw6410_map_io,
         .init_machine   = anw6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 1acf02bace57..8ad88ace795a 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -64,6 +64,7 @@
 #include <plat/adc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "crag6410.h"
@@ -744,6 +745,7 @@ static void __init crag6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* LCD type and Bypass set by bootloader */
 }
@@ -868,6 +870,6 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
         .map_io         = crag6410_map_io,
         .init_machine   = crag6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 7212eb9cfeb9..5b7f357d8c22 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -41,6 +41,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -248,6 +249,7 @@ static void __init hmt_map_io(void)
         s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init hmt_machine_init(void)
@@ -275,6 +277,6 @@ MACHINE_START(HMT, "Airgoo-HMT")
         .map_io         = hmt_map_io,
         .init_machine   = hmt_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 4b41fcdaa7b6..fc043e3ecdf8 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -41,6 +41,7 @@
 
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -232,6 +233,7 @@ static void __init mini6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
         tmp = __raw_readl(S3C64XX_SPCON);
@@ -354,6 +356,6 @@ MACHINE_START(MINI6410, "MINI6410")
         .map_io         = mini6410_map_io,
         .init_machine   = mini6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 8d3cedd995ff..7e2c3908f1f8 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -43,6 +43,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -87,6 +88,7 @@ static void __init ncp_map_io(void)
         s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init ncp_machine_init(void)
@@ -103,6 +105,6 @@ MACHINE_START(NCP, "NCP")
         .map_io         = ncp_map_io,
         .init_machine   = ncp_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index fa12bd21ad82..8bed37b3d5ac 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -42,6 +42,7 @@
 
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -211,6 +212,7 @@ static void __init real6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
         tmp = __raw_readl(S3C64XX_SPCON);
@@ -333,6 +335,6 @@ MACHINE_START(REAL6410, "REAL6410")
         .map_io         = real6410_map_io,
         .init_machine   = real6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index fc3e9b32e26f..58ac99041274 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -38,6 +38,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 
 #include <video/platform_lcd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -378,6 +379,7 @@ void __init smartq_map_io(void)
         s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         smartq_lcd_mode_set();
 }
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index ca2afcfce573..8aca5daf3d05 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -28,6 +28,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "mach-smartq.h"
@@ -155,6 +156,6 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
         .map_io         = smartq_map_io,
         .init_machine   = smartq5_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 37bb0c632a5e..a052e107c0b4 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -28,6 +28,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "mach-smartq.h"
@@ -171,6 +172,6 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
         .map_io         = smartq_map_io,
         .init_machine   = smartq7_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index a392869c8342..d70c0843aea2 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -35,6 +35,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -66,6 +67,7 @@ static void __init smdk6400_map_io(void)
         s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static struct platform_device *smdk6400_devices[] __initdata = {
@@ -92,6 +94,6 @@ MACHINE_START(SMDK6400, "SMDK6400")
         .map_io         = smdk6400_map_io,
         .init_machine   = smdk6400_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ba7544e2d04d..bd3295a19ad7 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -69,6 +69,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/backlight.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -634,6 +635,7 @@ static void __init smdk6410_map_io(void)
         s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
 
@@ -702,6 +704,6 @@ MACHINE_START(SMDK6410, "SMDK6410")
         .map_io         = smdk6410_map_io,
         .init_machine   = smdk6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index e8742cb7ddd9..5a707bdb9ea0 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -9,16 +9,16 @@ if ARCH_S5P64X0
 
 config CPU_S5P6440
         bool
-        select S5P_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6440 CPU support
 
 config CPU_S5P6450
         bool
-        select S5P_HRT
+        select SAMSUNG_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
         select SAMSUNG_WAKEMASK if PM
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index e23723a5a214..73f71a698a34 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -48,7 +48,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
@@ -229,7 +229,7 @@ static void __init smdk6440_map_io(void)
         s5p64x0_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void s5p6440_set_lcd_interface(void)
@@ -273,6 +273,6 @@ MACHINE_START(SMDK6440, "SMDK6440")
         .init_irq       = s5p6440_init_irq,
         .map_io         = smdk6440_map_io,
         .init_machine   = smdk6440_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index ca10963a959e..18303e12019f 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -48,7 +48,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
@@ -248,7 +248,7 @@ static void __init smdk6450_map_io(void)
         s5p64x0_init_io(NULL, 0);
         s3c24xx_init_clocks(19200000);
         s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void s5p6450_set_lcd_interface(void)
@@ -292,6 +292,6 @@ MACHINE_START(SMDK6450, "SMDK6450")
         .init_irq       = s5p6450_init_irq,
         .map_io         = smdk6450_map_io,
         .init_machine   = smdk6450_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 15170be97a74..2f456a4533ba 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -11,6 +11,7 @@ config CPU_S5PC100
         bool
         select S5P_EXT_INT
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         help
           Enable S5PC100 CPU support
 
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 185a19583898..8c880f76f274 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -51,6 +51,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <linux/platform_data/asoc-s3c.h>
 #include <plat/backlight.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -221,6 +222,7 @@ static void __init smdkc100_map_io(void)
         s5pc100_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdkc100_machine_init(void)
@@ -255,6 +257,6 @@ MACHINE_START(SMDKC100, "SMDKC100")
         .init_irq       = s5pc100_init_irq,
         .map_io         = smdkc100_map_io,
         .init_machine   = smdkc100_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pc100_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 92ad72f0ef98..0963283a7c5d 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -12,10 +12,10 @@ if ARCH_S5PV210
 config CPU_S5PV210
         bool
         select S5P_EXT_INT
-        select S5P_HRT
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         help
           Enable S5PV210 CPU support
 
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 11900a8e88a3..ed2b85485b9d 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -38,7 +38,7 @@
 #include <plat/fb.h>
 #include <plat/fimc-core.h>
 #include <plat/sdhci.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -651,7 +651,7 @@ static void __init aquila_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init aquila_machine_init(void)
@@ -686,6 +686,6 @@ MACHINE_START(AQUILA, "Aquila")
         .init_irq       = s5pv210_init_irq,
         .map_io         = aquila_map_io,
         .init_machine   = aquila_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e373de44a8b6..30b24ad84f49 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -47,7 +47,7 @@
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/clock.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/mfc.h>
 #include <plat/camport.h>
 
@@ -908,7 +908,7 @@ static void __init goni_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init goni_reserve(void)
@@ -973,7 +973,7 @@ MACHINE_START(GONI, "GONI")
         .init_irq       = s5pv210_init_irq,
         .map_io         = goni_map_io,
         .init_machine   = goni_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .reserve        = &goni_reserve,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 28bd0248a3e2..7c0ed07a78a3 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -29,7 +29,7 @@
 #include <linux/platform_data/ata-samsung_cf.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/mfc.h>
 
 #include "common.h"
@@ -120,7 +120,7 @@ static void __init smdkc110_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdkc110_reserve(void)
@@ -153,7 +153,7 @@ MACHINE_START(SMDKC110, "SMDKC110")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkc110_map_io,
         .init_machine   = smdkc110_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
         .reserve        = &smdkc110_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 3c73f36869bb..d50b6f124465 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -44,7 +44,7 @@
 #include <plat/keypad.h>
 #include <plat/pm.h>
 #include <plat/fb.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/mfc.h>
 #include <plat/clock.h>
@@ -285,7 +285,7 @@ static void __init smdkv210_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
 }
 
 static void __init smdkv210_reserve(void)
@@ -329,7 +329,7 @@ MACHINE_START(SMDKV210, "SMDKV210")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkv210_map_io,
         .init_machine   = smdkv210_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
         .reserve        = &smdkv210_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 2d4c5531819c..579afe89842a 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -26,7 +26,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -106,7 +106,7 @@ static void __init torbreck_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init torbreck_machine_init(void)
@@ -130,6 +130,6 @@ MACHINE_START(TORBRECK, "TORBRECK")
         .init_irq       = s5pv210_init_irq,
         .map_io         = torbreck_map_io,
         .init_machine   = torbreck_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 9255546e7bf6..75d413c004b6 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -16,6 +16,7 @@ config ARCH_SH73A0
         select CPU_V7
         select I2C
         select SH_CLK_CPG
+        select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7740
         bool "R-Mobile A1 (R8A77400)"
@@ -31,6 +32,7 @@ config ARCH_R8A7779
         select SH_CLK_CPG
         select USB_ARCH_HAS_EHCI
         select USB_ARCH_HAS_OHCI
+        select RENESAS_INTC_IRQPIN
 
 config ARCH_EMEV2
         bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index a385f570bbfc..95fe396f9604 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -81,7 +81,7 @@ static struct resource smsc9221_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = intcs_evt2irq(0x260), /* IRQ3 */
+                .start  = irq_pin(3), /* IRQ3 */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -115,7 +115,7 @@ static struct resource usb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = intcs_evt2irq(0x220), /* IRQ1 */
+                .start  = irq_pin(1), /* IRQ1 */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -138,7 +138,7 @@ struct usbhs_private {
         struct renesas_usbhs_platform_info info;
 };
 
-#define IRQ15                   intcs_evt2irq(0x03e0)
+#define IRQ15                   irq_pin(15)
 #define USB_PHY_MODE            (1 << 4)
 #define USB_PHY_INT_EN          ((1 << 3) | (1 << 2))
 #define USB_PHY_ON              (1 << 1)
@@ -567,25 +567,25 @@ static struct i2c_board_info i2c0_devices[] = {
         },
         {
                 I2C_BOARD_INFO("ak8975", 0x0c),
-                .irq = intcs_evt2irq(0x3380), /* IRQ28 */
+                .irq = irq_pin(28), /* IRQ28 */
         },
         {
                 I2C_BOARD_INFO("adxl34x", 0x1d),
-                .irq = intcs_evt2irq(0x3340), /* IRQ26 */
+                .irq = irq_pin(26), /* IRQ26 */
         },
 };
 
 static struct i2c_board_info i2c1_devices[] = {
         {
                 I2C_BOARD_INFO("st1232-ts", 0x55),
-                .irq = intcs_evt2irq(0x300), /* IRQ8 */
+                .irq = irq_pin(8), /* IRQ8 */
         },
 };
 
 static struct i2c_board_info i2c3_devices[] = {
         {
                 I2C_BOARD_INFO("pcf8575", 0x20),
-                .irq            = intcs_evt2irq(0x3260), /* IRQ19 */
+                .irq = irq_pin(19), /* IRQ19 */
                 .platform_data = &pcf8575_pdata,
         },
 };
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 62c04c252418..1fef737a4c1a 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -58,6 +58,7 @@ extern void r8a7740_pm_init(void);
 
 extern void r8a7779_init_delay(void);
 extern void r8a7779_init_irq(void);
+extern void r8a7779_init_irq_extpin(int irlm);
 extern void r8a7779_init_irq_dt(void);
 extern void r8a7779_map_io(void);
 extern void r8a7779_earlytimer_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 992ed213cec1..b2074e2acb15 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -12,4 +12,8 @@
 #define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
 #define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
 
+/* External IRQ pins */
+#define IRQPIN_BASE             2000
+#define irq_pin(nr)             ((nr) + IRQPIN_BASE)
+
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index f9cc4bc9c798..b86dc8908724 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -19,13 +19,16 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
-#include <mach/common.h>
+#include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/irqchip.h>
+#include <mach/common.h>
 #include <mach/intc.h>
+#include <mach/irqs.h>
 #include <mach/r8a7779.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,6 +42,54 @@
 #define INT2NTSR0 IOMEM(0xfe700060)
 #define INT2NTSR1 IOMEM(0xfe700064)
 
+static struct renesas_intc_irqpin_config irqpin0_platform_data = {
+        .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
+        .sense_bitfield_width = 2,
+};
+
+static struct resource irqpin0_resources[] = {
+        DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
+        DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
+        DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
+        DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
+        DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
+        DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
+        DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
+        DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
+        DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
+};
+
+static struct platform_device irqpin0_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 0,
+        .resource       = irqpin0_resources,
+        .num_resources  = ARRAY_SIZE(irqpin0_resources),
+        .dev            = {
+                .platform_data  = &irqpin0_platform_data,
+        },
+};
+
+void __init r8a7779_init_irq_extpin(int irlm)
+{
+        void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
+        unsigned long tmp;
+
+        if (icr0) {
+                tmp = ioread32(icr0);
+                if (irlm)
+                        tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
+                else
+                        tmp &= ~(1 << 23); /* IRL mode - not supported */
+                tmp |= (1 << 21); /* LVLMODE = 1 */
+                iowrite32(tmp, icr0);
+                iounmap(icr0);
+
+                if (irlm)
+                        platform_device_register(&irqpin0_device);
+        } else
+                pr_warn("r8a7779: unable to setup external irq pin mode\n");
+}
+
 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 {
         return 0; /* always allow wakeup */
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index a81a1d804e2e..19a26f4579b3 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -260,108 +260,6 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
         return 0; /* always allow wakeup */
 }
 
-#define RELOC_BASE 0x1200
-
-/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */
-#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
-
-INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
-                 INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
-
-static int to_gic_irq(struct irq_data *data)
-{
-        unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
-
-        if (vect >= 0x3200)
-                vect -= 0x3000;
-        else
-                vect -= 0x0200;
-
-        return gic_spi((vect >> 5) + 1);
-}
-
-static int to_intca_reloc_irq(struct irq_data *data)
-{
-        return data->irq + (RELOC_BASE >> 5);
-}
-
-#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
-#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
-
-static void intca_gic_enable(struct irq_data *data)
-{
-        irq_cb(irq_unmask, to_intca_reloc_irq(data));
-        irq_cb(irq_unmask, to_gic_irq(data));
-}
-
-static void intca_gic_disable(struct irq_data *data)
-{
-        irq_cb(irq_mask, to_gic_irq(data));
-        irq_cb(irq_mask, to_intca_reloc_irq(data));
-}
-
-static void intca_gic_mask_ack(struct irq_data *data)
-{
-        irq_cb(irq_mask, to_gic_irq(data));
-        irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
-}
-
-static void intca_gic_eoi(struct irq_data *data)
-{
-        irq_cb(irq_eoi, to_gic_irq(data));
-}
-
-static int intca_gic_set_type(struct irq_data *data, unsigned int type)
-{
-        return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
-}
-
-#ifdef CONFIG_SMP
-static int intca_gic_set_affinity(struct irq_data *data,
-                                  const struct cpumask *cpumask,
-                                  bool force)
-{
-        return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
-}
-#endif
-
-struct irq_chip intca_gic_irq_chip = {
-        .name                   = "INTCA-GIC",
-        .irq_mask               = intca_gic_disable,
-        .irq_unmask             = intca_gic_enable,
-        .irq_mask_ack           = intca_gic_mask_ack,
-        .irq_eoi                = intca_gic_eoi,
-        .irq_enable             = intca_gic_enable,
-        .irq_disable            = intca_gic_disable,
-        .irq_shutdown           = intca_gic_disable,
-        .irq_set_type           = intca_gic_set_type,
-        .irq_set_wake           = sh73a0_set_wake,
-#ifdef CONFIG_SMP
-        .irq_set_affinity       = intca_gic_set_affinity,
-#endif
-};
-
-static int to_intc_vect(int irq)
-{
-        unsigned int irq_pin = irq - gic_spi(1);
-        unsigned int offs;
-
-        if (irq_pin < 16)
-                offs = 0x0200;
-        else
-                offs = 0x3000;
-
-        return offs + (irq_pin << 5);
-}
-
-static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
-{
-        generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
-        return IRQ_HANDLED;
-}
-
-static struct irqaction sh73a0_irq_pin_cascade[32];
-
 #define PINTER0_PHYS 0xe69000a0
 #define PINTER1_PHYS 0xe69000a4
 #define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -422,13 +320,11 @@ void __init sh73a0_init_irq(void)
         void __iomem *gic_dist_base = IOMEM(0xf0001000);
         void __iomem *gic_cpu_base = IOMEM(0xf0000100);
         void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
-        int k, n;
 
         gic_init(0, 29, gic_dist_base, gic_cpu_base);
         gic_arch_extn.irq_set_wake = sh73a0_set_wake;
 
         register_intc_controller(&intcs_desc);
-        register_intc_controller(&intca_irq_pins_desc);
         register_intc_controller(&intc_pint0_desc);
         register_intc_controller(&intc_pint1_desc);
 
@@ -438,19 +334,6 @@ void __init sh73a0_init_irq(void)
         sh73a0_intcs_cascade.dev_id = intevtsa;
         setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
 
-        /* IRQ pins require special handling through INTCA and GIC */
-        for (k = 0; k < 32; k++) {
-                sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
-                sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
-                setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
-
-                n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
-                WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
-                irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
-                                              handle_level_irq, "level");
-                set_irq_flags(n, IRQF_VALID); /* yuck */
-        }
-
         /* PINT pins are sanely tied to the GIC as SPI */
         sh73a0_pint0_cascade.name = "PINT0 cascade";
         sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 2257a915746d..e8cd93a5c550 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -33,6 +33,7 @@
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/platform_data/sh_ipmmu.h>
+#include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <mach/dma-register.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -811,6 +812,127 @@ static struct platform_device ipmmu_device = {
         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
 
+static struct renesas_intc_irqpin_config irqpin0_platform_data = {
+        .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
+};
+
+static struct resource irqpin0_resources[] = {
+        DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
+        DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
+        DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
+        DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
+        DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
+        DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
+        DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
+        DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
+        DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
+        DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
+        DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
+        DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
+        DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
+};
+
+static struct platform_device irqpin0_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 0,
+        .resource       = irqpin0_resources,
+        .num_resources  = ARRAY_SIZE(irqpin0_resources),
+        .dev            = {
+                .platform_data  = &irqpin0_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin1_platform_data = {
+        .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
+        .control_parent = true, /* Disable spurious IRQ10 */
+};
+
+static struct resource irqpin1_resources[] = {
+        DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
+        DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
+        DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
+        DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
+        DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
+        DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
+        DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
+        DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
+        DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
+        DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
+        DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
+        DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
+        DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
+};
+
+static struct platform_device irqpin1_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 1,
+        .resource       = irqpin1_resources,
+        .num_resources  = ARRAY_SIZE(irqpin1_resources),
+        .dev            = {
+                .platform_data  = &irqpin1_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin2_platform_data = {
+        .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
+};
+
+static struct resource irqpin2_resources[] = {
+        DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
+        DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
+        DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
+        DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
+        DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
+        DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
+        DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
+        DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
+        DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
+        DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
+        DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
+        DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
+        DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
+};
+
+static struct platform_device irqpin2_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 2,
+        .resource       = irqpin2_resources,
+        .num_resources  = ARRAY_SIZE(irqpin2_resources),
+        .dev            = {
+                .platform_data  = &irqpin2_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin3_platform_data = {
+        .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
+};
+
+static struct resource irqpin3_resources[] = {
+        DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
+        DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
+        DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
+        DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
+        DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
+        DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
+        DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
+        DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
+        DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
+        DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
+        DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
+        DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
+        DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
+};
+
+static struct platform_device irqpin3_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 3,
+        .resource       = irqpin3_resources,
+        .num_resources  = ARRAY_SIZE(irqpin3_resources),
+        .dev            = {
+                .platform_data  = &irqpin3_platform_data,
+        },
+};
+
 static struct platform_device *sh73a0_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -839,6 +961,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
         &dma0_device,
         &mpdma0_device,
         &pmu_device,
+        &irqpin0_device,
+        &irqpin1_device,
+        &irqpin2_device,
+        &irqpin3_device,
 };
 
 #define SRCR2          IOMEM(0xe61580b0)
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 9cf1ab17afeb..0d1e4128d460 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -34,6 +34,7 @@
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
 #include <linux/usb/tegra_usb_phy.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -85,6 +86,8 @@ static void __init tegra_dt_init(void)
         struct soc_device *soc_dev;
         struct device *parent = NULL;
 
+        tegra_clocks_apply_init_table();
+
         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
         if (!soc_dev_attr)
                 goto out;
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index f3976f9c404a..947bd9eca079 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -46,8 +46,12 @@ BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
@@ -76,9 +80,6 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
 #define DB8500_PIN_HOG(pin,conf) \
         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
-#define DB8500_PIN_SLEEP(pin, conf, dev) \
-        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
-                            pin, conf)
 
 /* These are default states associated with device and changed runtime */
 #define DB8500_MUX(group,func,dev) \
@@ -307,8 +308,23 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
 
         /* Mux in USB pins, drive STP high */
-        DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
-        DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
+        /* USB default state */
+        DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
+        DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
+        /* USB sleep state */
+        DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
+        DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
+        DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
+        DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
+        DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
+        DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
+        DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
+        DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
+        DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
+        DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
+        DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
+        DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
+
         /* Mux in SPI2 pins on the "other C1" altfunction */
         DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
         DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
@@ -316,9 +332,9 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
         DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
         /* SPI2 idle state */
-        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
-        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
-        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
+        DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
+        DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
+        DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
         /* SPI2 sleep state */
         DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
         DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
@@ -745,6 +761,8 @@ static struct pinctrl_map __initdata snowball_pinmap[] = {
         DB8500_PIN_HOG("GPIO21_AB3", out_hi),
         /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
         DB8500_MUX_HOG("sm_b_1", "sm"),
+        /* User LED */
+        DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
         /* Drive RSTn_LAN high */
         DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
         /*  Accelerometer/Magnetometer */
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index e3e94b2fa145..9b252934b206 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -7,6 +7,7 @@ config ARCH_VT8500
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select VT8500_TIMER
+        select PINCTRL
         help
           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 92ceb2436b60..4c8a84637594 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_ARCH_VT8500) += irq.o vt8500.o
+obj-$(CONFIG_ARCH_VT8500) += vt8500.o
diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h
index 77611a6968d6..087787af62f1 100644
--- a/arch/arm/mach-vt8500/common.h
+++ b/arch/arm/mach-vt8500/common.h
@@ -18,13 +18,7 @@
 
 #include <linux/of.h>
 
-int __init vt8500_irq_init(struct device_node *node,
-                                struct device_node *parent);
-
 /* defined in drivers/clk/clk-vt8500.c */
 void __init vtwm_clk_init(void __iomem *pmc_base);
 
-/* defined in irq.c */
-asmlinkage void vt8500_handle_irq(struct pt_regs *regs);
-
 #endif
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 49e80053d828..1dd281efc020 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -20,6 +20,7 @@
 
 #include <linux/clocksource.h>
 #include <linux/io.h>
+#include <linux/irqchip.h>
 #include <linux/pm.h>
 
 #include <asm/mach-types.h>
@@ -166,16 +167,6 @@ void __init vt8500_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const struct of_device_id vt8500_irq_match[] __initconst = {
-        { .compatible = "via,vt8500-intc", .data = vt8500_irq_init, },
-        { /* sentinel */ },
-};
-
-static void __init vt8500_init_irq(void)
-{
-        of_irq_init(vt8500_irq_match);
-};
-
 static const char * const vt8500_dt_compat[] = {
         "via,vt8500",
         "wm,wm8650",
@@ -187,10 +178,9 @@ static const char * const vt8500_dt_compat[] = {
 DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
         .dt_compat      = vt8500_dt_compat,
         .map_io         = vt8500_map_io,
-        .init_irq       = vt8500_init_irq,
+        .init_irq       = irqchip_init,
         .init_machine   = vt8500_init,
         .init_time      = clocksource_of_init,
         .restart        = vt8500_restart,
-        .handle_irq     = vt8500_handle_irq,
 MACHINE_END
 
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 138b5891f4ef..cf3226b041f5 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -11,5 +11,6 @@ config ARCH_ZYNQ
         select MIGHT_HAVE_CACHE_L2X0
         select USE_OF
         select SPARSE_IRQ
+        select CADENCE_TTC_TIMER
         help
           Support for Xilinx Zynq ARM Cortex A9 Platform
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index 397268c1b250..320faedeb484 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -3,4 +3,4 @@
 #
 
 # Common support
-obj-y                           := common.o timer.o
+obj-y                           := common.o
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 5c8983218183..68e0907de5d0 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -20,6 +20,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/clk/zynq.h>
+#include <linux/clocksource.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
@@ -77,7 +78,7 @@ static void __init xilinx_zynq_timer_init(void)
 
         xilinx_zynq_clocks_init(slcr);
 
-        xttcps_timer_init();
+        clocksource_of_init();
 }
 
 /**
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 8b4dbbaa01cf..5050bb10bb12 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,6 +17,4 @@
 #ifndef __MACH_ZYNQ_COMMON_H__
 #define __MACH_ZYNQ_COMMON_H__
 
-void __init xttcps_timer_init(void);
-
 #endif
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
deleted file mode 100644
index f9fbc9c1e7a6..000000000000
--- a/arch/arm/mach-zynq/timer.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * This file contains driver for the Xilinx PS Timer Counter IP.
- *
- *  Copyright (C) 2011 Xilinx
- *
- * based on arch/mips/kernel/time.c timer driver
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/interrupt.h>
-#include <linux/clockchips.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/slab.h>
-#include <linux/clk-provider.h>
-#include "common.h"
-
-/*
- * Timer Register Offset Definitions of Timer 1, Increment base address by 4
- * and use same offsets for Timer 2
- */
-#define XTTCPS_CLK_CNTRL_OFFSET         0x00 /* Clock Control Reg, RW */
-#define XTTCPS_CNT_CNTRL_OFFSET         0x0C /* Counter Control Reg, RW */
-#define XTTCPS_COUNT_VAL_OFFSET         0x18 /* Counter Value Reg, RO */
-#define XTTCPS_INTR_VAL_OFFSET          0x24 /* Interval Count Reg, RW */
-#define XTTCPS_ISR_OFFSET               0x54 /* Interrupt Status Reg, RO */
-#define XTTCPS_IER_OFFSET               0x60 /* Interrupt Enable Reg, RW */
-
-#define XTTCPS_CNT_CNTRL_DISABLE_MASK   0x1
-
-/*
- * Setup the timers to use pre-scaling, using a fixed value for now that will
- * work across most input frequency, but it may need to be more dynamic
- */
-#define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
-#define PRESCALE                2048    /* The exponent must match this */
-#define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
-#define CLK_CNTRL_PRESCALE_EN   1
-#define CNT_CNTRL_RESET         (1<<4)
-
-/**
- * struct xttcps_timer - This definition defines local timer structure
- *
- * @base_addr:  Base address of timer
- **/
-struct xttcps_timer {
-        void __iomem    *base_addr;
-};
-
-struct xttcps_timer_clocksource {
-        struct xttcps_timer     xttc;
-        struct clocksource      cs;
-};
-
-#define to_xttcps_timer_clksrc(x) \
-                container_of(x, struct xttcps_timer_clocksource, cs)
-
-struct xttcps_timer_clockevent {
-        struct xttcps_timer             xttc;
-        struct clock_event_device       ce;
-        struct clk                      *clk;
-};
-
-#define to_xttcps_timer_clkevent(x) \
-                container_of(x, struct xttcps_timer_clockevent, ce)
-
-/**
- * xttcps_set_interval - Set the timer interval value
- *
- * @timer:      Pointer to the timer instance
- * @cycles:     Timer interval ticks
- **/
-static void xttcps_set_interval(struct xttcps_timer *timer,
-                                        unsigned long cycles)
-{
-        u32 ctrl_reg;
-
-        /* Disable the counter, set the counter value  and re-enable counter */
-        ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-
-        __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
-
-        /*
-         * Reset the counter (0x10) so that it starts from 0, one-shot
-         * mode makes this needed for timing to be right.
-         */
-        ctrl_reg |= CNT_CNTRL_RESET;
-        ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-}
-
-/**
- * xttcps_clock_event_interrupt - Clock event timer interrupt handler
- *
- * @irq:        IRQ number of the Timer
- * @dev_id:     void pointer to the xttcps_timer instance
- *
- * returns: Always IRQ_HANDLED - success
- **/
-static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
-{
-        struct xttcps_timer_clockevent *xttce = dev_id;
-        struct xttcps_timer *timer = &xttce->xttc;
-
-        /* Acknowledge the interrupt and call event handler */
-        __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
-
-        xttce->ce.event_handler(&xttce->ce);
-
-        return IRQ_HANDLED;
-}
-
-/**
- * __xttc_clocksource_read - Reads the timer counter register
- *
- * returns: Current timer counter register value
- **/
-static cycle_t __xttc_clocksource_read(struct clocksource *cs)
-{
-        struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
-
-        return (cycle_t)__raw_readl(timer->base_addr +
-                                XTTCPS_COUNT_VAL_OFFSET);
-}
-
-/**
- * xttcps_set_next_event - Sets the time interval for next event
- *
- * @cycles:     Timer interval ticks
- * @evt:        Address of clock event instance
- *
- * returns: Always 0 - success
- **/
-static int xttcps_set_next_event(unsigned long cycles,
-                                        struct clock_event_device *evt)
-{
-        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcps_timer *timer = &xttce->xttc;
-
-        xttcps_set_interval(timer, cycles);
-        return 0;
-}
-
-/**
- * xttcps_set_mode - Sets the mode of timer
- *
- * @mode:       Mode to be set
- * @evt:        Address of clock event instance
- **/
-static void xttcps_set_mode(enum clock_event_mode mode,
-                                        struct clock_event_device *evt)
-{
-        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcps_timer *timer = &xttce->xttc;
-        u32 ctrl_reg;
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                xttcps_set_interval(timer,
-                                     DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
-                                                       PRESCALE * HZ));
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-                break;
-        case CLOCK_EVT_MODE_RESUME:
-                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-                break;
-        }
-}
-
-static void __init zynq_ttc_setup_clocksource(struct device_node *np,
-                                             void __iomem *base)
-{
-        struct xttcps_timer_clocksource *ttccs;
-        struct clk *clk;
-        int err;
-        u32 reg;
-
-        ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
-        if (WARN_ON(!ttccs))
-                return;
-
-        err = of_property_read_u32(np, "reg", &reg);
-        if (WARN_ON(err))
-                return;
-
-        clk = of_clk_get_by_name(np, "cpu_1x");
-        if (WARN_ON(IS_ERR(clk)))
-                return;
-
-        err = clk_prepare_enable(clk);
-        if (WARN_ON(err))
-                return;
-
-        ttccs->xttc.base_addr = base + reg * 4;
-
-        ttccs->cs.name = np->name;
-        ttccs->cs.rating = 200;
-        ttccs->cs.read = __xttc_clocksource_read;
-        ttccs->cs.mask = CLOCKSOURCE_MASK(16);
-        ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
-
-        __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
-        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
-        __raw_writel(CNT_CNTRL_RESET,
-                     ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-
-        err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
-        if (WARN_ON(err))
-                return;
-}
-
-static void __init zynq_ttc_setup_clockevent(struct device_node *np,
-                                            void __iomem *base)
-{
-        struct xttcps_timer_clockevent *ttcce;
-        int err, irq;
-        u32 reg;
-
-        ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
-        if (WARN_ON(!ttcce))
-                return;
-
-        err = of_property_read_u32(np, "reg", &reg);
-        if (WARN_ON(err))
-                return;
-
-        ttcce->xttc.base_addr = base + reg * 4;
-
-        ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
-        if (WARN_ON(IS_ERR(ttcce->clk)))
-                return;
-
-        err = clk_prepare_enable(ttcce->clk);
-        if (WARN_ON(err))
-                return;
-
-        irq = irq_of_parse_and_map(np, 0);
-        if (WARN_ON(!irq))
-                return;
-
-        ttcce->ce.name = np->name;
-        ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-        ttcce->ce.set_next_event = xttcps_set_next_event;
-        ttcce->ce.set_mode = xttcps_set_mode;
-        ttcce->ce.rating = 200;
-        ttcce->ce.irq = irq;
-        ttcce->ce.cpumask = cpu_possible_mask;
-
-        __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
-        __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
-
-        err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
-                          np->name, ttcce);
-        if (WARN_ON(err))
-                return;
-
-        clockevents_config_and_register(&ttcce->ce,
-                                        clk_get_rate(ttcce->clk) / PRESCALE,
-                                        1, 0xfffe);
-}
-
-static const __initconst struct of_device_id zynq_ttc_match[] = {
-        { .compatible = "xlnx,ttc-counter-clocksource",
-                .data = zynq_ttc_setup_clocksource, },
-        { .compatible = "xlnx,ttc-counter-clockevent",
-                .data = zynq_ttc_setup_clockevent, },
-        {}
-};
-
-/**
- * xttcps_timer_init - Initialize the timer
- *
- * Initializes the timer hardware and register the clock source and clock event
- * timers with Linux kernal timer framework
- **/
-void __init xttcps_timer_init(void)
-{
-        struct device_node *np;
-
-        for_each_compatible_node(np, NULL, "xlnx,ttc") {
-                struct device_node *np_chld;
-                void __iomem *base;
-
-                base = of_iomap(np, 0);
-                if (WARN_ON(!base))
-                        return;
-
-                for_each_available_child_of_node(np, np_chld) {
-                        int (*cb)(struct device_node *np, void __iomem *base);
-                        const struct of_device_id *match;
-
-                        match = of_match_node(zynq_ttc_match, np_chld);
-                        if (match) {
-                                cb = match->data;
-                                cb(np_chld, base);
-                        }
-                }
-        }
-}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 91c2d72e689b..54d186106f9f 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -25,7 +25,7 @@ config PLAT_S5P
         select PLAT_SAMSUNG
         select S3C_GPIO_TRACK
         select S5P_GPIO_DRVSTR
-        select SAMSUNG_CLKSRC
+        select SAMSUNG_CLKSRC if !COMMON_CLK
         select SAMSUNG_GPIOLIB_4BIT
         select SAMSUNG_IRQ_VIC_TIMER
         help
@@ -62,7 +62,7 @@ config S3C_LOWLEVEL_UART_PORT
 
 # timer options
 
-config S5P_HRT
+config SAMSUNG_HRT
         bool
         select SAMSUNG_DEV_PWM
         help
@@ -81,7 +81,7 @@ config SAMSUNG_CLKSRC
           used by newer systems such as the S3C64XX.
 
 config S5P_CLOCK
-        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
         help
           Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
 
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 3a7c64d1814a..a23c460299a1 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -12,8 +12,7 @@ obj-				:=
 # Objects we always build independent of SoC choice
 
 obj-y                           += init.o cpu.o
-obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o
-obj-$(CONFIG_S5P_HRT)           += s5p-time.o
+obj-$(CONFIG_SAMSUNG_HRT)       += samsung-time.o
 
 obj-$(CONFIG_SAMSUNG_CLOCK)     += clock.o
 obj-$(CONFIG_SAMSUNG_CLOCK)     += pwm-clock.o
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 33ad3f32c2b9..30c2fe243f76 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1074,7 +1074,7 @@ struct platform_device s5p_device_onenand = {
 
 /* PMU */
 
-#ifdef CONFIG_PLAT_S5P
+#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
 static struct resource s5p_pmu_resource[] = {
         DEFINE_RES_IRQ(IRQ_PMU)
 };
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 37703ef6dfc7..989fefe18be6 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -23,6 +23,9 @@ extern unsigned long samsung_cpu_id;
 #define S3C24XX_CPU_ID          0x32400000
 #define S3C24XX_CPU_MASK        0xFFF00000
 
+#define S3C2412_CPU_ID          0x32412000
+#define S3C2412_CPU_MASK        0xFFFFF000
+
 #define S3C6400_CPU_ID          0x36400000
 #define S3C6410_CPU_ID          0x36410000
 #define S3C64XX_CPU_MASK        0xFFFFF000
@@ -53,6 +56,7 @@ static inline int is_samsung_##name(void)	\
 }
 
 IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
+IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
@@ -74,6 +78,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_s3c24xx()       0
 #endif
 
+#if defined(CONFIG_CPU_S3C2412)
+# define soc_is_s3c2412()       is_samsung_s3c2412()
+#else
+# define soc_is_s3c2412()       0
+#endif
+
 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
 # define soc_is_s3c64xx()       (is_samsung_s3c6400() || is_samsung_s3c6410())
 #else
@@ -173,7 +183,6 @@ extern void s3c_init_cpu(unsigned long idcode,
 
 /* core initialisation functions */
 
-extern void s3c24xx_init_irq(void);
 extern void s5p_init_irq(u32 *vic, u32 num_vic);
 
 extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
@@ -192,10 +201,6 @@ extern void s3c24xx_init_uartdevs(char *name,
                                   struct s3c24xx_uart_resources *res,
                                   struct s3c2410_uartcfg *cfg, int no);
 
-/* timer for 2410/2440 */
-
-extern void s3c24xx_timer_init(void);
-
 extern struct syscore_ops s3c2410_pm_syscore_ops;
 extern struct syscore_ops s3c2412_pm_syscore_ops;
 extern struct syscore_ops s3c2416_pm_syscore_ops;
diff --git a/arch/arm/plat-samsung/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h
deleted file mode 100644
index 9c96f3586ce0..000000000000
--- a/arch/arm/plat-samsung/include/plat/s5p-time.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s5p-time.h
- *
- * Copyright 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Header file for s5p time support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_S5P_TIME_H
-#define __ASM_PLAT_S5P_TIME_H __FILE__
-
-/* S5P HR-Timer Clock mode */
-enum s5p_timer_mode {
-        S5P_PWM0,
-        S5P_PWM1,
-        S5P_PWM2,
-        S5P_PWM3,
-        S5P_PWM4,
-};
-
-struct s5p_timer_source {
-        unsigned int event_id;
-        unsigned int source_id;
-};
-
-/* Be able to sleep for atleast 4 seconds (usually more) */
-#define S5PTIMER_MIN_RANGE      4
-
-#define TCNT_MAX                0xffffffff
-#define NON_PERIODIC            0
-#define PERIODIC                1
-
-extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
-                                        enum s5p_timer_mode source);
-extern  void s5p_timer_init(void);
-#endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h
new file mode 100644
index 000000000000..4cc99bb1f176
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/samsung-time.h
@@ -0,0 +1,53 @@
+/* linux/arch/arm/plat-samsung/include/plat/samsung-time.h
+ *
+ * Copyright 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for samsung s3c and s5p time support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_SAMSUNG_TIME_H
+#define __ASM_PLAT_SAMSUNG_TIME_H __FILE__
+
+/* SAMSUNG HR-Timer Clock mode */
+enum samsung_timer_mode {
+        SAMSUNG_PWM0,
+        SAMSUNG_PWM1,
+        SAMSUNG_PWM2,
+        SAMSUNG_PWM3,
+        SAMSUNG_PWM4,
+};
+
+struct samsung_timer_source {
+        unsigned int event_id;
+        unsigned int source_id;
+};
+
+/* Be able to sleep for atleast 4 seconds (usually more) */
+#define SAMSUNG_TIMER_MIN_RANGE 4
+
+#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S5PC100)
+#define TCNT_MAX                0xffff
+#define TSCALER_DIV             25
+#define TDIV                    50
+#define TSIZE                   16
+#else
+#define TCNT_MAX                0xffffffff
+#define TSCALER_DIV             2
+#define TDIV                    2
+#define TSIZE                   32
+#endif
+
+#define NON_PERIODIC            0
+#define PERIODIC                1
+
+extern void __init samsung_set_timer_source(enum samsung_timer_mode event,
+                                        enum samsung_timer_mode source);
+
+extern void __init samsung_timer_init(void);
+
+#endif /* __ASM_PLAT_SAMSUNG_TIME_H */
diff --git a/arch/arm/plat-samsung/s5p-time.c b/arch/arm/plat-samsung/samsung-time.c
index e92510cf82ee..f899cbc9b288 100644
--- a/arch/arm/plat-samsung/s5p-time.c
+++ b/arch/arm/plat-samsung/samsung-time.c
@@ -2,7 +2,7 @@
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
- * S5P - Common hr-timer support
+ * samsung - Common hr-timer support (s3c and s5p)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -25,41 +25,41 @@
 #include <mach/map.h>
 #include <plat/devs.h>
 #include <plat/regs-timer.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 static struct clk *tin_event;
 static struct clk *tin_source;
 static struct clk *tdiv_event;
 static struct clk *tdiv_source;
 static struct clk *timerclk;
-static struct s5p_timer_source timer_source;
+static struct samsung_timer_source timer_source;
 static unsigned long clock_count_per_tick;
-static void s5p_timer_resume(void);
+static void samsung_timer_resume(void);
 
-static void s5p_time_stop(enum s5p_timer_mode mode)
+static void samsung_time_stop(enum samsung_timer_mode mode)
 {
         unsigned long tcon;
 
         tcon = __raw_readl(S3C2410_TCON);
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon &= ~S3C2410_TCON_T0START;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon &= ~S3C2410_TCON_T1START;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon &= ~S3C2410_TCON_T2START;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon &= ~S3C2410_TCON_T3START;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon &= ~S3C2410_TCON_T4START;
                 break;
 
@@ -70,7 +70,7 @@ static void s5p_time_stop(enum s5p_timer_mode mode)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
+static void samsung_time_setup(enum samsung_timer_mode mode, unsigned long tcnt)
 {
         unsigned long tcon;
 
@@ -79,27 +79,27 @@ static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
         tcnt--;
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon &= ~(0x0f << 0);
                 tcon |= S3C2410_TCON_T0MANUALUPD;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon &= ~(0x0f << 8);
                 tcon |= S3C2410_TCON_T1MANUALUPD;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon &= ~(0x0f << 12);
                 tcon |= S3C2410_TCON_T2MANUALUPD;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon &= ~(0x0f << 16);
                 tcon |= S3C2410_TCON_T3MANUALUPD;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon &= ~(0x07 << 20);
                 tcon |= S3C2410_TCON_T4MANUALUPD;
                 break;
@@ -114,14 +114,14 @@ static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
+static void samsung_time_start(enum samsung_timer_mode mode, bool periodic)
 {
         unsigned long tcon;
 
         tcon  = __raw_readl(S3C2410_TCON);
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon |= S3C2410_TCON_T0START;
                 tcon &= ~S3C2410_TCON_T0MANUALUPD;
 
@@ -131,7 +131,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T0RELOAD;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon |= S3C2410_TCON_T1START;
                 tcon &= ~S3C2410_TCON_T1MANUALUPD;
 
@@ -141,7 +141,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T1RELOAD;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon |= S3C2410_TCON_T2START;
                 tcon &= ~S3C2410_TCON_T2MANUALUPD;
 
@@ -151,7 +151,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T2RELOAD;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon |= S3C2410_TCON_T3START;
                 tcon &= ~S3C2410_TCON_T3MANUALUPD;
 
@@ -161,7 +161,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T3RELOAD;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon |= S3C2410_TCON_T4START;
                 tcon &= ~S3C2410_TCON_T4MANUALUPD;
 
@@ -178,24 +178,24 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static int s5p_set_next_event(unsigned long cycles,
+static int samsung_set_next_event(unsigned long cycles,
                                 struct clock_event_device *evt)
 {
-        s5p_time_setup(timer_source.event_id, cycles);
-        s5p_time_start(timer_source.event_id, NON_PERIODIC);
+        samsung_time_setup(timer_source.event_id, cycles);
+        samsung_time_start(timer_source.event_id, NON_PERIODIC);
 
         return 0;
 }
 
-static void s5p_set_mode(enum clock_event_mode mode,
+static void samsung_set_mode(enum clock_event_mode mode,
                                 struct clock_event_device *evt)
 {
-        s5p_time_stop(timer_source.event_id);
+        samsung_time_stop(timer_source.event_id);
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                s5p_time_setup(timer_source.event_id, clock_count_per_tick);
-                s5p_time_start(timer_source.event_id, PERIODIC);
+                samsung_time_setup(timer_source.event_id, clock_count_per_tick);
+                samsung_time_start(timer_source.event_id, PERIODIC);
                 break;
 
         case CLOCK_EVT_MODE_ONESHOT:
@@ -206,24 +206,24 @@ static void s5p_set_mode(enum clock_event_mode mode,
                 break;
 
         case CLOCK_EVT_MODE_RESUME:
-                s5p_timer_resume();
+                samsung_timer_resume();
                 break;
         }
 }
 
-static void s5p_timer_resume(void)
+static void samsung_timer_resume(void)
 {
         /* event timer restart */
-        s5p_time_setup(timer_source.event_id, clock_count_per_tick);
-        s5p_time_start(timer_source.event_id, PERIODIC);
+        samsung_time_setup(timer_source.event_id, clock_count_per_tick);
+        samsung_time_start(timer_source.event_id, PERIODIC);
 
         /* source timer restart */
-        s5p_time_setup(timer_source.source_id, TCNT_MAX);
-        s5p_time_start(timer_source.source_id, PERIODIC);
+        samsung_time_setup(timer_source.source_id, TCNT_MAX);
+        samsung_time_start(timer_source.source_id, PERIODIC);
 }
 
-void __init s5p_set_timer_source(enum s5p_timer_mode event,
-                                 enum s5p_timer_mode source)
+void __init samsung_set_timer_source(enum samsung_timer_mode event,
+                                 enum samsung_timer_mode source)
 {
         s3c_device_timer[event].dev.bus = &platform_bus_type;
         s3c_device_timer[source].dev.bus = &platform_bus_type;
@@ -233,14 +233,14 @@ void __init s5p_set_timer_source(enum s5p_timer_mode event,
 }
 
 static struct clock_event_device time_event_device = {
-        .name           = "s5p_event_timer",
+        .name           = "samsung_event_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 200,
-        .set_next_event = s5p_set_next_event,
-        .set_mode       = s5p_set_mode,
+        .set_next_event = samsung_set_next_event,
+        .set_mode       = samsung_set_mode,
 };
 
-static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
+static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
 {
         struct clock_event_device *evt = dev_id;
 
@@ -249,14 +249,14 @@ static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static struct irqaction s5p_clock_event_irq = {
-        .name           = "s5p_time_irq",
+static struct irqaction samsung_clock_event_irq = {
+        .name           = "samsung_time_irq",
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s5p_clock_event_isr,
+        .handler        = samsung_clock_event_isr,
         .dev_id         = &time_event_device,
 };
 
-static void __init s5p_clockevent_init(void)
+static void __init samsung_clockevent_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
@@ -267,8 +267,8 @@ static void __init s5p_clockevent_init(void)
 
         tscaler = clk_get_parent(tdiv_event);
 
-        clk_set_rate(tscaler, pclk / 2);
-        clk_set_rate(tdiv_event, pclk / 2);
+        clk_set_rate(tscaler, pclk / TSCALER_DIV);
+        clk_set_rate(tdiv_event, pclk / TDIV);
         clk_set_parent(tin_event, tdiv_event);
 
         clock_rate = clk_get_rate(tin_event);
@@ -278,22 +278,22 @@ static void __init s5p_clockevent_init(void)
         clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
 
         irq_number = timer_source.event_id + IRQ_TIMER0;
-        setup_irq(irq_number, &s5p_clock_event_irq);
+        setup_irq(irq_number, &samsung_clock_event_irq);
 }
 
-static void __iomem *s5p_timer_reg(void)
+static void __iomem *samsung_timer_reg(void)
 {
         unsigned long offset = 0;
 
         switch (timer_source.source_id) {
-        case S5P_PWM0:
-        case S5P_PWM1:
-        case S5P_PWM2:
-        case S5P_PWM3:
+        case SAMSUNG_PWM0:
+        case SAMSUNG_PWM1:
+        case SAMSUNG_PWM2:
+        case SAMSUNG_PWM3:
                 offset = (timer_source.source_id * 0x0c) + 0x14;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 offset = 0x40;
                 break;
 
@@ -312,9 +312,9 @@ static void __iomem *s5p_timer_reg(void)
  * this wraps around for now, since it is just a relative time
  * stamp. (Inspired by U300 implementation.)
  */
-static u32 notrace s5p_read_sched_clock(void)
+static u32 notrace samsung_read_sched_clock(void)
 {
-        void __iomem *reg = s5p_timer_reg();
+        void __iomem *reg = samsung_timer_reg();
 
         if (!reg)
                 return 0;
@@ -322,29 +322,29 @@ static u32 notrace s5p_read_sched_clock(void)
         return ~__raw_readl(reg);
 }
 
-static void __init s5p_clocksource_init(void)
+static void __init samsung_clocksource_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
 
         pclk = clk_get_rate(timerclk);
 
-        clk_set_rate(tdiv_source, pclk / 2);
+        clk_set_rate(tdiv_source, pclk / TDIV);
         clk_set_parent(tin_source, tdiv_source);
 
         clock_rate = clk_get_rate(tin_source);
 
-        s5p_time_setup(timer_source.source_id, TCNT_MAX);
-        s5p_time_start(timer_source.source_id, PERIODIC);
+        samsung_time_setup(timer_source.source_id, TCNT_MAX);
+        samsung_time_start(timer_source.source_id, PERIODIC);
 
-        setup_sched_clock(s5p_read_sched_clock, 32, clock_rate);
+        setup_sched_clock(samsung_read_sched_clock, TSIZE, clock_rate);
 
-        if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
-                        clock_rate, 250, 32, clocksource_mmio_readl_down))
-                panic("s5p_clocksource_timer: can't register clocksource\n");
+        if (clocksource_mmio_init(samsung_timer_reg(), "samsung_clocksource_timer",
+                        clock_rate, 250, TSIZE, clocksource_mmio_readl_down))
+                panic("samsung_clocksource_timer: can't register clocksource\n");
 }
 
-static void __init s5p_timer_resources(void)
+static void __init samsung_timer_resources(void)
 {
 
         unsigned long event_id = timer_source.event_id;
@@ -386,9 +386,9 @@ static void __init s5p_timer_resources(void)
         clk_enable(tin_source);
 }
 
-void __init s5p_timer_init(void)
+void __init samsung_timer_init(void)
 {
-        s5p_timer_resources();
-        s5p_clockevent_init();
-        s5p_clocksource_init();
+        samsung_timer_resources();
+        samsung_clockevent_init();
+        samsung_clocksource_init();
 }
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
deleted file mode 100644
index 73defd00c3e4..000000000000
--- a/arch/arm/plat-samsung/time.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/* linux/arch/arm/plat-samsung/time.c
- *
- * Copyright (C) 2003-2005 Simtec Electronics
- *      Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/mach-types.h>
-
-#include <asm/irq.h>
-#include <mach/map.h>
-#include <plat/regs-timer.h>
-#include <mach/regs-irq.h>
-#include <asm/mach/time.h>
-#include <mach/tick.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-static unsigned long timer_startval;
-static unsigned long timer_usec_ticks;
-
-#ifndef TICK_MAX
-#define TICK_MAX (0xffff)
-#endif
-
-#define TIMER_USEC_SHIFT 16
-
-/* we use the shifted arithmetic to work out the ratio of timer ticks
- * to usecs, as often the peripheral clock is not a nice even multiple
- * of 1MHz.
- *
- * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
- * for the current HZ value of 200 without producing overflows.
- *
- * Original patch by Dimitry Andric, updated by Ben Dooks
-*/
-
-
-/* timer_mask_usec_ticks
- *
- * given a clock and divisor, make the value to pass into timer_ticks_to_usec
- * to scale the ticks into usecs
-*/
-
-static inline unsigned long
-timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
-{
-        unsigned long den = pclk / 1000;
-
-        return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
-}
-
-/* timer_ticks_to_usec
- *
- * convert timer ticks to usec.
-*/
-
-static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
-{
-        unsigned long res;
-
-        res = ticks * timer_usec_ticks;
-        res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
-
-        return res >> TIMER_USEC_SHIFT;
-}
-
-/***
- * Returns microsecond  since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- * IRQs are disabled before entering here from do_gettimeofday()
- */
-
-static u32 s3c2410_gettimeoffset(void)
-{
-        unsigned long tdone;
-        unsigned long tval;
-
-        /* work out how many ticks have gone since last timer interrupt */
-
-        tval =  __raw_readl(S3C2410_TCNTO(4));
-        tdone = timer_startval - tval;
-
-        /* check to see if there is an interrupt pending */
-
-        if (s3c24xx_ostimer_pending()) {
-                /* re-read the timer, and try and fix up for the missed
-                 * interrupt. Note, the interrupt may go off before the
-                 * timer has re-loaded from wrapping.
-                 */
-
-                tval =  __raw_readl(S3C2410_TCNTO(4));
-                tdone = timer_startval - tval;
-
-                if (tval != 0)
-                        tdone += timer_startval;
-        }
-
-        return timer_ticks_to_usec(tdone) * 1000;
-}
-
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-s3c2410_timer_interrupt(int irq, void *dev_id)
-{
-        timer_tick();
-        return IRQ_HANDLED;
-}
-
-static struct irqaction s3c2410_timer_irq = {
-        .name           = "S3C2410 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s3c2410_timer_interrupt,
-};
-
-#define use_tclk1_12() ( \
-        machine_is_bast()       || \
-        machine_is_vr1000()     || \
-        machine_is_anubis()     || \
-        machine_is_osiris())
-
-static struct clk *tin;
-static struct clk *tdiv;
-static struct clk *timerclk;
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- *
- * Currently we only use timer4, as it is the only timer which has no
- * other function that can be exploited externally
- */
-static void s3c2410_timer_setup (void)
-{
-        unsigned long tcon;
-        unsigned long tcnt;
-        unsigned long tcfg1;
-        unsigned long tcfg0;
-
-        tcnt = TICK_MAX;  /* default value for tcnt */
-
-        /* configure the system for whichever machine is in use */
-
-        if (use_tclk1_12()) {
-                /* timer is at 12MHz, scaler is 1 */
-                timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
-                tcnt = 12000000 / HZ;
-
-                tcfg1 = __raw_readl(S3C2410_TCFG1);
-                tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
-                tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
-                __raw_writel(tcfg1, S3C2410_TCFG1);
-        } else {
-                unsigned long pclk;
-                struct clk *tscaler;
-
-                /* for the h1940 (and others), we use the pclk from the core
-                 * to generate the timer values. since values around 50 to
-                 * 70MHz are not values we can directly generate the timer
-                 * value from, we need to pre-scale and divide before using it.
-                 *
-                 * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
-                 * (8.45 ticks per usec)
-                 */
-
-                pclk = clk_get_rate(timerclk);
-
-                /* configure clock tick */
-
-                timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
-
-                tscaler = clk_get_parent(tdiv);
-
-                clk_set_rate(tscaler, pclk / 3);
-                clk_set_rate(tdiv, pclk / 6);
-                clk_set_parent(tin, tdiv);
-
-                tcnt = clk_get_rate(tin) / HZ;
-        }
-
-        tcon = __raw_readl(S3C2410_TCON);
-        tcfg0 = __raw_readl(S3C2410_TCFG0);
-        tcfg1 = __raw_readl(S3C2410_TCFG1);
-
-        /* timers reload after counting zero, so reduce the count by 1 */
-
-        tcnt--;
-
-        printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
-               tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
-
-        /* check to see if timer is within 16bit range... */
-        if (tcnt > TICK_MAX) {
-                panic("setup_timer: HZ is too small, cannot configure timer!");
-                return;
-        }
-
-        __raw_writel(tcfg1, S3C2410_TCFG1);
-        __raw_writel(tcfg0, S3C2410_TCFG0);
-
-        timer_startval = tcnt;
-        __raw_writel(tcnt, S3C2410_TCNTB(4));
-
-        /* ensure timer is stopped... */
-
-        tcon &= ~(7<<20);
-        tcon |= S3C2410_TCON_T4RELOAD;
-        tcon |= S3C2410_TCON_T4MANUALUPD;
-
-        __raw_writel(tcon, S3C2410_TCON);
-        __raw_writel(tcnt, S3C2410_TCNTB(4));
-        __raw_writel(tcnt, S3C2410_TCMPB(4));
-
-        /* start the timer running */
-        tcon |= S3C2410_TCON_T4START;
-        tcon &= ~S3C2410_TCON_T4MANUALUPD;
-        __raw_writel(tcon, S3C2410_TCON);
-}
-
-static void __init s3c2410_timer_resources(void)
-{
-        struct platform_device tmpdev;
-
-        tmpdev.dev.bus = &platform_bus_type;
-        tmpdev.id = 4;
-
-        timerclk = clk_get(NULL, "timers");
-        if (IS_ERR(timerclk))
-                panic("failed to get clock for system timer");
-
-        clk_enable(timerclk);
-
-        if (!use_tclk1_12()) {
-                tmpdev.id = 4;
-                tmpdev.dev.init_name = "s3c24xx-pwm.4";
-                tin = clk_get(&tmpdev.dev, "pwm-tin");
-                if (IS_ERR(tin))
-                        panic("failed to get pwm-tin clock for system timer");
-
-                tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
-                if (IS_ERR(tdiv))
-                        panic("failed to get pwm-tdiv clock for system timer");
-        }
-
-        clk_enable(tin);
-}
-
-static struct syscore_ops s3c24xx_syscore_ops = {
-        .resume         = s3c2410_timer_setup,
-};
-
-void __init s3c24xx_timer_init(void)
-{
-        arch_gettimeoffset = s3c2410_gettimeoffset;
-
-        s3c2410_timer_resources();
-        s3c2410_timer_setup();
-        setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
-        register_syscore_ops(&s3c24xx_syscore_ops);
-}
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index b323d8d3185b..7c2f6685bf43 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1453,7 +1453,7 @@ static struct resource atmel_lcdfb0_resource[] = {
         },
 };
 DEFINE_DEV_DATA(atmel_lcdfb, 0);
-DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
+DEV_CLK(hclk, atmel_lcdfb0, hsb, 7);
 static struct clk atmel_lcdfb0_pixclk = {
         .name           = "lcdc_clk",
         .dev            = &atmel_lcdfb0_device.dev,
@@ -1530,6 +1530,8 @@ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
         info->default_monspecs = monspecs;
 
+        pdev->name = "at32ap-lcdfb";
+
         platform_device_register(pdev);
         return pdev;
 
@@ -2246,7 +2248,7 @@ static __initdata struct clk *init_clocks[] = {
         &atmel_twi0_pclk,
         &atmel_mci0_pclk,
 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
-        &atmel_lcdfb0_hck1,
+        &atmel_lcdfb0_hclk,
         &atmel_lcdfb0_pixclk,
 #endif
         &ssc0_pclk,
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 8d96238549fa..9953a42809ec 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -164,4 +164,6 @@ source "drivers/irqchip/Kconfig"
 
 source "drivers/ipack/Kconfig"
 
+source "drivers/reset/Kconfig"
+
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 8e57688ebd95..130abc1dfd65 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -37,6 +37,9 @@ obj-$(CONFIG_XEN)		+= xen/
 # regulators early, since some subsystems rely on them to initialize
 obj-$(CONFIG_REGULATOR)         += regulator/
 
+# reset controllers early, since gpu drivers might rely on them to initialize
+obj-$(CONFIG_RESET_CONTROLLER)  += reset/
+
 # tty/ comes before char/ so that the VT console is the boot-time
 # default.
 obj-y                           += tty/
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e7f7fe9b2f09..137d3e730f86 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_U8500)	+= ux500/
 obj-$(CONFIG_ARCH_VT8500)       += clk-vt8500.o
 obj-$(CONFIG_ARCH_ZYNQ)         += clk-zynq.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra/
+obj-$(CONFIG_PLAT_SAMSUNG)      += samsung/
 
 obj-$(CONFIG_X86)               += x86/
 
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 000000000000..b7c232e67425
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,8 @@
+#
+# Samsung Clock specific Makefile
+#
+
+obj-$(CONFIG_COMMON_CLK)        += clk.o clk-pll.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += clk-exynos4.o
+obj-$(CONFIG_SOC_EXYNOS5250)    += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5440)    += clk-exynos5440.o
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 000000000000..71046694d9dd
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,1091 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Exynos4 SoCs.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <plat/cpu.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+/* Exynos4 clock controller register offsets */
+#define SRC_LEFTBUS             0x4200
+#define DIV_LEFTBUS             0x4500
+#define GATE_IP_LEFTBUS         0x4800
+#define E4X12_GATE_IP_IMAGE     0x4930
+#define SRC_RIGHTBUS            0x8200
+#define DIV_RIGHTBUS            0x8500
+#define GATE_IP_RIGHTBUS        0x8800
+#define E4X12_GATE_IP_PERIR     0x8960
+#define EPLL_LOCK               0xc010
+#define VPLL_LOCK               0xc020
+#define EPLL_CON0               0xc110
+#define EPLL_CON1               0xc114
+#define EPLL_CON2               0xc118
+#define VPLL_CON0               0xc120
+#define VPLL_CON1               0xc124
+#define VPLL_CON2               0xc128
+#define SRC_TOP0                0xc210
+#define SRC_TOP1                0xc214
+#define SRC_CAM                 0xc220
+#define SRC_TV                  0xc224
+#define SRC_MFC                 0xcc28
+#define SRC_G3D                 0xc22c
+#define E4210_SRC_IMAGE         0xc230
+#define SRC_LCD0                0xc234
+#define E4210_SRC_LCD1          0xc238
+#define E4X12_SRC_ISP           0xc238
+#define SRC_MAUDIO              0xc23c
+#define SRC_FSYS                0xc240
+#define SRC_PERIL0              0xc250
+#define SRC_PERIL1              0xc254
+#define E4X12_SRC_CAM1          0xc258
+#define SRC_MASK_TOP            0xc310
+#define SRC_MASK_CAM            0xc320
+#define SRC_MASK_TV             0xc324
+#define SRC_MASK_LCD0           0xc334
+#define E4210_SRC_MASK_LCD1     0xc338
+#define E4X12_SRC_MASK_ISP      0xc338
+#define SRC_MASK_MAUDIO         0xc33c
+#define SRC_MASK_FSYS           0xc340
+#define SRC_MASK_PERIL0         0xc350
+#define SRC_MASK_PERIL1         0xc354
+#define DIV_TOP                 0xc510
+#define DIV_CAM                 0xc520
+#define DIV_TV                  0xc524
+#define DIV_MFC                 0xc528
+#define DIV_G3D                 0xc52c
+#define DIV_IMAGE               0xc530
+#define DIV_LCD0                0xc534
+#define E4210_DIV_LCD1          0xc538
+#define E4X12_DIV_ISP           0xc538
+#define DIV_MAUDIO              0xc53c
+#define DIV_FSYS0               0xc540
+#define DIV_FSYS1               0xc544
+#define DIV_FSYS2               0xc548
+#define DIV_FSYS3               0xc54c
+#define DIV_PERIL0              0xc550
+#define DIV_PERIL1              0xc554
+#define DIV_PERIL2              0xc558
+#define DIV_PERIL3              0xc55c
+#define DIV_PERIL4              0xc560
+#define DIV_PERIL5              0xc564
+#define E4X12_DIV_CAM1          0xc568
+#define GATE_SCLK_CAM           0xc820
+#define GATE_IP_CAM             0xc920
+#define GATE_IP_TV              0xc924
+#define GATE_IP_MFC             0xc928
+#define GATE_IP_G3D             0xc92c
+#define E4210_GATE_IP_IMAGE     0xc930
+#define GATE_IP_LCD0            0xc934
+#define E4210_GATE_IP_LCD1      0xc938
+#define E4X12_GATE_IP_ISP       0xc938
+#define E4X12_GATE_IP_MAUDIO    0xc93c
+#define GATE_IP_FSYS            0xc940
+#define GATE_IP_GPS             0xc94c
+#define GATE_IP_PERIL           0xc950
+#define E4210_GATE_IP_PERIR     0xc960
+#define GATE_BLOCK              0xc970
+#define E4X12_MPLL_CON0         0x10108
+#define SRC_DMC                 0x10200
+#define SRC_MASK_DMC            0x10300
+#define DIV_DMC0                0x10500
+#define DIV_DMC1                0x10504
+#define GATE_IP_DMC             0x10900
+#define APLL_CON0               0x14100
+#define E4210_MPLL_CON0         0x14108
+#define SRC_CPU                 0x14200
+#define DIV_CPU0                0x14500
+#define DIV_CPU1                0x14504
+#define GATE_SCLK_CPU           0x14800
+#define GATE_IP_CPU             0x14900
+#define E4X12_DIV_ISP0          0x18300
+#define E4X12_DIV_ISP1          0x18304
+#define E4X12_GATE_ISP0         0x18800
+#define E4X12_GATE_ISP1         0x18804
+
+/* the exynos4 soc type */
+enum exynos4_soc {
+        EXYNOS4210,
+        EXYNOS4X12,
+};
+
+/*
+ * Let each supported clock get a unique id. This id is used to lookup the clock
+ * for device tree based platforms. The clocks are categorized into three
+ * sections: core, sclk gate and bus interface gate clocks.
+ *
+ * When adding a new clock to this list, it is advised to choose a clock
+ * category and add it to the end of that category. That is because the the
+ * device tree source file is referring to these ids and any change in the
+ * sequence number of existing clocks will require corresponding change in the
+ * device tree files. This limitation would go away when pre-processor support
+ * for dtc would be available.
+ */
+enum exynos4_clks {
+        none,
+
+        /* core clocks */
+        xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
+        sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
+        aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
+        mout_apll, /* 20 */
+
+        /* gate for special clocks (sclk) */
+        sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
+        sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
+        sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
+        sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
+        sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
+        sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
+        sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
+        sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
+        sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
+
+        /* gate clocks */
+        fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
+        smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
+        smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
+        smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
+        mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
+        sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
+        onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
+        uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
+        spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
+        spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
+        audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
+        fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
+        gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
+        mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
+        asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
+        spi1_isp_sclk, uart_isp_sclk,
+
+        /* mux clocks */
+        mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
+        mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
+        aclk400_mcuisp,
+
+        /* div clocks */
+        div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200,
+        div_aclk400_mcuisp,
+
+        nr_clks,
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static __initdata unsigned long exynos4210_clk_save[] = {
+        E4210_SRC_IMAGE,
+        E4210_SRC_LCD1,
+        E4210_SRC_MASK_LCD1,
+        E4210_DIV_LCD1,
+        E4210_GATE_IP_IMAGE,
+        E4210_GATE_IP_LCD1,
+        E4210_GATE_IP_PERIR,
+        E4210_MPLL_CON0,
+};
+
+static __initdata unsigned long exynos4x12_clk_save[] = {
+        E4X12_GATE_IP_IMAGE,
+        E4X12_GATE_IP_PERIR,
+        E4X12_SRC_CAM1,
+        E4X12_DIV_ISP,
+        E4X12_DIV_CAM1,
+        E4X12_MPLL_CON0,
+};
+
+static __initdata unsigned long exynos4_clk_regs[] = {
+        SRC_LEFTBUS,
+        DIV_LEFTBUS,
+        GATE_IP_LEFTBUS,
+        SRC_RIGHTBUS,
+        DIV_RIGHTBUS,
+        GATE_IP_RIGHTBUS,
+        EPLL_CON0,
+        EPLL_CON1,
+        EPLL_CON2,
+        VPLL_CON0,
+        VPLL_CON1,
+        VPLL_CON2,
+        SRC_TOP0,
+        SRC_TOP1,
+        SRC_CAM,
+        SRC_TV,
+        SRC_MFC,
+        SRC_G3D,
+        SRC_LCD0,
+        SRC_MAUDIO,
+        SRC_FSYS,
+        SRC_PERIL0,
+        SRC_PERIL1,
+        SRC_MASK_TOP,
+        SRC_MASK_CAM,
+        SRC_MASK_TV,
+        SRC_MASK_LCD0,
+        SRC_MASK_MAUDIO,
+        SRC_MASK_FSYS,
+        SRC_MASK_PERIL0,
+        SRC_MASK_PERIL1,
+        DIV_TOP,
+        DIV_CAM,
+        DIV_TV,
+        DIV_MFC,
+        DIV_G3D,
+        DIV_IMAGE,
+        DIV_LCD0,
+        DIV_MAUDIO,
+        DIV_FSYS0,
+        DIV_FSYS1,
+        DIV_FSYS2,
+        DIV_FSYS3,
+        DIV_PERIL0,
+        DIV_PERIL1,
+        DIV_PERIL2,
+        DIV_PERIL3,
+        DIV_PERIL4,
+        DIV_PERIL5,
+        GATE_SCLK_CAM,
+        GATE_IP_CAM,
+        GATE_IP_TV,
+        GATE_IP_MFC,
+        GATE_IP_G3D,
+        GATE_IP_LCD0,
+        GATE_IP_FSYS,
+        GATE_IP_GPS,
+        GATE_IP_PERIL,
+        GATE_BLOCK,
+        SRC_MASK_DMC,
+        SRC_DMC,
+        DIV_DMC0,
+        DIV_DMC1,
+        GATE_IP_DMC,
+        APLL_CON0,
+        SRC_CPU,
+        DIV_CPU0,
+        DIV_CPU1,
+        GATE_SCLK_CPU,
+        GATE_IP_CPU,
+};
+
+/* list of all parent clock list */
+PNAME(mout_apll_p)      = { "fin_pll", "fout_apll", };
+PNAME(mout_mpll_p)      = { "fin_pll", "fout_mpll", };
+PNAME(mout_epll_p)      = { "fin_pll", "fout_epll", };
+PNAME(mout_vpllsrc_p)   = { "fin_pll", "sclk_hdmi24m", };
+PNAME(mout_vpll_p)      = { "fin_pll", "fout_vpll", };
+PNAME(sclk_evpll_p)     = { "sclk_epll", "sclk_vpll", };
+PNAME(mout_mfc_p)       = { "mout_mfc0", "mout_mfc1", };
+PNAME(mout_g3d_p)       = { "mout_g3d0", "mout_g3d1", };
+PNAME(mout_g2d_p)       = { "mout_g2d0", "mout_g2d1", };
+PNAME(mout_hdmi_p)      = { "sclk_pixel", "sclk_hdmiphy", };
+PNAME(mout_jpeg_p)      = { "mout_jpeg0", "mout_jpeg1", };
+PNAME(mout_spdif_p)     = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
+                                "spdif_extclk", };
+PNAME(mout_onenand_p)  = {"aclk133", "aclk160", };
+PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
+
+/* Exynos 4210-specific parent groups */
+PNAME(sclk_vpll_p4210)  = { "mout_vpllsrc", "fout_vpll", };
+PNAME(mout_core_p4210)  = { "mout_apll", "sclk_mpll", };
+PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
+PNAME(group1_p4210)     = { "xxti", "xusbxti", "sclk_hdmi24m",
+                                "sclk_usbphy0", "none", "sclk_hdmiphy",
+                                "sclk_mpll", "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+                                "sclk_epll", "sclk_vpll" };
+PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+                                "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
+                                "sclk_epll", "sclk_vpll", };
+PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
+PNAME(mout_dac_p4210)   = { "sclk_vpll", "sclk_hdmiphy", };
+
+/* Exynos 4x12-specific parent groups */
+PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
+PNAME(mout_core_p4x12)  = { "mout_apll", "mout_mpll_user_c", };
+PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
+PNAME(group1_p4x12)     = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
+                                "none", "sclk_hdmiphy", "mout_mpll_user_t",
+                                "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti",
+                                "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
+PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti",
+                                "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
+PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
+                                "sclk_usbphy0", "xxti", "xusbxti",
+                                "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
+PNAME(aclk_p4412)       = { "mout_mpll_user_t", "sclk_apll", };
+PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
+PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
+PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
+        FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
+        FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
+};
+
+/* fixed rate clocks generated inside the soc */
+struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
+        FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
+        FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+        FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
+};
+
+struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
+        FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
+};
+
+/* list of mux clocks supported in all exynos4 soc's */
+struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
+        MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+                        CLK_SET_RATE_PARENT, 0),
+        MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
+        MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
+        MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
+        MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
+                        CLK_SET_RATE_PARENT, 0),
+        MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
+                        CLK_SET_RATE_PARENT, 0),
+        MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
+        MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
+        MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
+        MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
+};
+
+/* list of mux clocks supported in exynos4210 soc */
+struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
+        MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
+        MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
+        MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
+        MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
+        MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
+        MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
+        MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
+        MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
+        MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
+        MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
+        MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
+        MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
+        MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
+        MUX_A(mout_core, "mout_core", mout_core_p4210,
+                        SRC_CPU, 16, 1, "mout_core"),
+        MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
+                        SRC_TOP0, 8, 1, "sclk_vpll"),
+        MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
+        MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
+        MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
+        MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
+        MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
+        MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
+        MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
+        MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
+        MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
+        MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
+                        CLK_SET_RATE_PARENT, 0),
+        MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
+        MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
+        MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
+        MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
+        MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
+        MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
+        MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
+        MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
+        MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
+        MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
+        MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
+        MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
+        MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
+        MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
+        MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
+        MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
+        MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
+        MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
+        MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
+};
+
+/* list of mux clocks supported in exynos4x12 soc */
+struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
+        MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
+                        SRC_CPU, 24, 1),
+        MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
+        MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
+        MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
+                        SRC_TOP1, 12, 1),
+        MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
+                        SRC_TOP1, 16, 1),
+        MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
+        MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12,
+                        SRC_TOP1, 24, 1),
+        MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
+        MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
+        MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
+        MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
+        MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
+        MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
+        MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
+        MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
+        MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
+        MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
+        MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
+                        SRC_DMC, 12, 1, "sclk_mpll"),
+        MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
+                        SRC_TOP0, 8, 1, "sclk_vpll"),
+        MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
+        MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
+        MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
+        MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
+        MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
+        MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
+        MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
+        MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
+        MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
+        MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
+        MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
+                        CLK_SET_RATE_PARENT, 0),
+        MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
+        MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
+        MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
+        MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
+        MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
+        MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
+        MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
+        MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
+        MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
+        MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
+        MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
+        MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
+        MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
+        MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
+        MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
+        MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
+        MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
+        MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
+        MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
+        MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
+        MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
+        MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
+        MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
+};
+
+/* list of divider clocks supported in all exynos4 soc's */
+struct samsung_div_clock exynos4_div_clks[] __initdata = {
+        DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
+        DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
+        DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
+        DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
+        DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
+        DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
+        DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
+        DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
+        DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
+        DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
+        DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
+        DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
+        DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
+        DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
+        DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
+        DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+        DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+        DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+        DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
+        DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
+        DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
+        DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
+        DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
+        DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
+        DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
+        DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
+        DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
+        DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
+        DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
+        DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
+        DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
+        DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
+        DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
+        DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
+        DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
+        DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
+        DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
+        DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
+        DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
+        DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
+        DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
+        DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
+        DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
+        DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
+        DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"),
+        DIV_A(sclk_apll, "sclk_apll", "mout_apll",
+                        DIV_CPU0, 24, 3, "sclk_apll"),
+        DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
+                        CLK_SET_RATE_PARENT, 0),
+};
+
+/* list of divider clocks supported in exynos4210 soc */
+struct samsung_div_clock exynos4210_div_clks[] __initdata = {
+        DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
+        DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
+        DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
+        DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
+        DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
+        DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
+                        CLK_SET_RATE_PARENT, 0),
+};
+
+/* list of divider clocks supported in exynos4x12 soc */
+struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
+        DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
+        DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
+        DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
+        DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
+        DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
+        DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
+        DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
+        DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
+                                                DIV_TOP, 24, 3),
+        DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
+        DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
+        DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
+        DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
+        DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
+        DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
+        DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
+        DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
+        DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
+        DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
+        DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
+};
+
+/* list of gate clocks supported in all exynos4 soc's */
+struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
+        /*
+         * After all Exynos4 based platforms are migrated to use device tree,
+         * the device name and clock alias names specified below for some
+         * of the clocks can be removed.
+         */
+        GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
+        GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0),
+        GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
+        GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
+        GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
+        GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
+        GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
+        GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
+        GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0),
+        GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
+        GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
+        GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
+        GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
+        GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
+        GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
+        GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
+        GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
+        GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
+                        SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
+        GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
+        GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
+        GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"),
+        GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"),
+        GATE_A(usb_host, "usb_host", "aclk133",
+                        GATE_IP_FSYS, 12, 0, 0, "usbhost"),
+        GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",
+                        SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+        GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",
+                        SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+        GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",
+                        SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+        GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",
+                        SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
+        GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",
+                        SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
+        GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",
+                        SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
+        GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",
+                        SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
+        GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0",
+                        SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0,
+                        "mmc_busclk.2"),
+        GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1",
+                        SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0,
+                        "mmc_busclk.2"),
+        GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2",
+                        SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0,
+                        "mmc_busclk.2"),
+        GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3",
+                        SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0,
+                        "mmc_busclk.2"),
+        GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4",
+                        SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"),
+        GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",
+                        SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT,
+                        0, "clk_uart_baud0"),
+        GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",
+                        SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT,
+                        0, "clk_uart_baud0"),
+        GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
+                        SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT,
+                        0, "clk_uart_baud0"),
+        GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
+                        SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT,
+                        0, "clk_uart_baud0"),
+        GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
+                        SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT,
+                        0, "clk_uart_baud0"),
+        GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
+                        CLK_SET_RATE_PARENT, 0),
+        GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0",
+                        SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT,
+                        0, "spi_busclk0"),
+        GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",
+                        SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT,
+                        0, "spi_busclk0"),
+        GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",
+                        SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT,
+                        0, "spi_busclk0"),
+        GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160",
+                        GATE_IP_CAM, 0, 0, 0, "fimc"),
+        GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",
+                        GATE_IP_CAM, 1, 0, 0, "fimc"),
+        GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160",
+                        GATE_IP_CAM, 2, 0, 0, "fimc"),
+        GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160",
+                        GATE_IP_CAM, 3, 0, 0, "fimc"),
+        GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160",
+                        GATE_IP_CAM, 4, 0, 0, "fimc"),
+        GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160",
+                        GATE_IP_CAM, 5, 0, 0, "fimc"),
+        GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160",
+                        GATE_IP_CAM, 7, 0, 0, "sysmmu"),
+        GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160",
+                        GATE_IP_CAM, 8, 0, 0, "sysmmu"),
+        GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160",
+                        GATE_IP_CAM, 9, 0, 0, "sysmmu"),
+        GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160",
+                        GATE_IP_CAM, 10, 0, 0, "sysmmu"),
+        GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
+                        GATE_IP_CAM, 11, 0, 0, "sysmmu"),
+        GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
+        GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
+        GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160",
+                        GATE_IP_TV, 4, 0, 0, "sysmmu"),
+        GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"),
+        GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100",
+                        GATE_IP_MFC, 1, 0, 0, "sysmmu"),
+        GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100",
+                        GATE_IP_MFC, 2, 0, 0, "sysmmu"),
+        GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160",
+                        GATE_IP_LCD0, 0, 0, 0, "fimd"),
+        GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160",
+                        GATE_IP_LCD0, 4, 0, 0, "sysmmu"),
+        GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133",
+                        GATE_IP_FSYS, 0, 0, 0, "dma"),
+        GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133",
+                        GATE_IP_FSYS, 1, 0, 0, "dma"),
+        GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133",
+                        GATE_IP_FSYS, 5, 0, 0, "hsmmc"),
+        GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133",
+                        GATE_IP_FSYS, 6, 0, 0, "hsmmc"),
+        GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133",
+                        GATE_IP_FSYS, 7, 0, 0, "hsmmc"),
+        GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133",
+                        GATE_IP_FSYS, 8, 0, 0, "hsmmc"),
+        GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100",
+                        GATE_IP_PERIL, 0, 0, 0, "uart"),
+        GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100",
+                        GATE_IP_PERIL, 1, 0, 0, "uart"),
+        GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100",
+                        GATE_IP_PERIL, 2, 0, 0, "uart"),
+        GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100",
+                        GATE_IP_PERIL, 3, 0, 0, "uart"),
+        GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100",
+                        GATE_IP_PERIL, 4, 0, 0, "uart"),
+        GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100",
+                        GATE_IP_PERIL, 6, 0, 0, "i2c"),
+        GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100",
+                        GATE_IP_PERIL, 7, 0, 0, "i2c"),
+        GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100",
+                        GATE_IP_PERIL, 8, 0, 0, "i2c"),
+        GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100",
+                        GATE_IP_PERIL, 9, 0, 0, "i2c"),
+        GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100",
+                        GATE_IP_PERIL, 10, 0, 0, "i2c"),
+        GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100",
+                        GATE_IP_PERIL, 11, 0, 0, "i2c"),
+        GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100",
+                        GATE_IP_PERIL, 12, 0, 0, "i2c"),
+        GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100",
+                        GATE_IP_PERIL, 13, 0, 0, "i2c"),
+        GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100",
+                        GATE_IP_PERIL, 14, 0, 0, "i2c"),
+        GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100",
+                        GATE_IP_PERIL, 16, 0, 0, "spi"),
+        GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100",
+                        GATE_IP_PERIL, 17, 0, 0, "spi"),
+        GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100",
+                        GATE_IP_PERIL, 18, 0, 0, "spi"),
+        GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100",
+                        GATE_IP_PERIL, 20, 0, 0, "iis"),
+        GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100",
+                        GATE_IP_PERIL, 21, 0, 0, "iis"),
+        GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100",
+                        GATE_IP_PERIL, 22, 0, 0, "pcm"),
+        GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100",
+                        GATE_IP_PERIL, 23, 0, 0, "pcm"),
+        GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100",
+                        GATE_IP_PERIL, 26, 0, 0, "spdif"),
+        GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100",
+                        GATE_IP_PERIL, 27, 0, 0, "ac97"),
+};
+
+/* list of gate clocks supported in exynos4210 soc */
+struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
+        GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
+        GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
+        GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
+        GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
+        GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
+        GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0),
+        GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
+        GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
+        GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
+        GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
+        GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
+        GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
+        GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
+        GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
+        GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
+        GATE(smmu_rotator, "smmu_rotator", "aclk200",
+                        E4210_GATE_IP_IMAGE, 4, 0, 0),
+        GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1",
+                        E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_sata, "sclk_sata", "div_sata",
+                        SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
+        GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
+        GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
+        GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"),
+        GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
+        GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"),
+        GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"),
+        GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
+                        E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
+};
+
+/* list of gate clocks supported in exynos4x12 soc */
+struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
+        GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
+        GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
+        GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
+        GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
+        GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
+        GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
+        GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
+        GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
+        GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
+        GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
+                        SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
+                        SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi",
+                        SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(smmu_rotator, "smmu_rotator", "aclk200",
+                        E4X12_GATE_IP_IMAGE, 4, 0, 0),
+        GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"),
+        GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),
+        GATE_A(keyif, "keyif", "aclk100",
+                        E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),
+        GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp",
+                        E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",
+                        E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre",
+                        E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp",
+                        E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp",
+                        E4X12_GATE_IP_ISP, 0, 0, 0),
+        GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp",
+                        E4X12_GATE_IP_ISP, 1, 0, 0),
+        GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp",
+                        E4X12_GATE_IP_ISP, 2, 0, 0),
+        GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",
+                        E4X12_GATE_IP_ISP, 3, 0, 0),
+        GATE_A(wdt, "watchdog", "aclk100",
+                        E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
+        GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
+                        E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
+        GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
+                        E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
+        GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
+                        CLK_IGNORE_UNUSED, 0),
+        GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
+                        CLK_IGNORE_UNUSED, 0),
+};
+
+#ifdef CONFIG_OF
+static struct of_device_id exynos4_clk_ids[] __initdata = {
+        { .compatible = "samsung,exynos4210-clock",
+                        .data = (void *)EXYNOS4210, },
+        { .compatible = "samsung,exynos4412-clock",
+                        .data = (void *)EXYNOS4X12, },
+        { },
+};
+#endif
+
+/*
+ * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
+ * resides in chipid register space, outside of the clock controller memory
+ * mapped space. So to determine the parent of fin_pll clock, the chipid
+ * controller is first remapped and the value of XOM[0] bit is read to
+ * determine the parent clock.
+ */
+static void __init exynos4_clk_register_finpll(void)
+{
+        struct samsung_fixed_rate_clock fclk;
+        struct device_node *np;
+        struct clk *clk;
+        void __iomem *chipid_base = S5P_VA_CHIPID;
+        unsigned long xom, finpll_f = 24000000;
+        char *parent_name;
+
+        np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
+        if (np)
+                chipid_base = of_iomap(np, 0);
+
+        if (chipid_base) {
+                xom = readl(chipid_base + 8);
+                parent_name = xom & 1 ? "xusbxti" : "xxti";
+                clk = clk_get(NULL, parent_name);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to lookup parent clock %s, assuming "
+                                "fin_pll clock frequency is 24MHz\n", __func__,
+                                parent_name);
+                } else {
+                        finpll_f = clk_get_rate(clk);
+                }
+        } else {
+                pr_err("%s: failed to map chipid registers, assuming "
+                        "fin_pll clock frequency is 24MHz\n", __func__);
+        }
+
+        fclk.id = fin_pll;
+        fclk.name = "fin_pll";
+        fclk.parent_name = NULL;
+        fclk.flags = CLK_IS_ROOT;
+        fclk.fixed_rate = finpll_f;
+        samsung_clk_register_fixed_rate(&fclk, 1);
+
+        if (np)
+                iounmap(chipid_base);
+}
+
+/*
+ * This function allows non-dt platforms to specify the clock speed of the
+ * xxti and xusbxti clocks. These clocks are then registered with the specified
+ * clock speed.
+ */
+void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f,
+                                                unsigned long xusbxti_f)
+{
+        exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f;
+        exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
+        samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks,
+                        ARRAY_SIZE(exynos4_fixed_rate_ext_clks));
+}
+
+static __initdata struct of_device_id ext_clk_match[] = {
+        { .compatible = "samsung,clock-xxti", .data = (void *)0, },
+        { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
+        {},
+};
+
+/* register exynos4 clocks */
+void __init exynos4_clk_init(struct device_node *np)
+{
+        void __iomem *reg_base;
+        struct clk *apll, *mpll, *epll, *vpll;
+        u32 exynos4_soc;
+
+        if (np) {
+                const struct of_device_id *match;
+                match = of_match_node(exynos4_clk_ids, np);
+                exynos4_soc = (u32)match->data;
+
+                reg_base = of_iomap(np, 0);
+                if (!reg_base)
+                        panic("%s: failed to map registers\n", __func__);
+        } else {
+                reg_base = S5P_VA_CMU;
+                if (soc_is_exynos4210())
+                        exynos4_soc = EXYNOS4210;
+                else if (soc_is_exynos4212() || soc_is_exynos4412())
+                        exynos4_soc = EXYNOS4X12;
+                else
+                        panic("%s: unable to determine soc\n", __func__);
+        }
+
+        if (exynos4_soc == EXYNOS4210)
+                samsung_clk_init(np, reg_base, nr_clks,
+                        exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
+                        exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
+        else
+                samsung_clk_init(np, reg_base, nr_clks,
+                        exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
+                        exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
+
+        if (np)
+                samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
+                        ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
+                        ext_clk_match);
+
+        exynos4_clk_register_finpll();
+
+        if (exynos4_soc == EXYNOS4210) {
+                apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
+                                        reg_base + APLL_CON0, pll_4508);
+                mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll",
+                                        reg_base + E4210_MPLL_CON0, pll_4508);
+                epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
+                                        reg_base + EPLL_CON0, pll_4600);
+                vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
+                                        reg_base + VPLL_CON0, pll_4650c);
+        } else {
+                apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
+                                        reg_base + APLL_CON0);
+                mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
+                                        reg_base + E4X12_MPLL_CON0);
+                epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
+                                        reg_base + EPLL_CON0);
+                vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
+                                        reg_base + VPLL_CON0);
+        }
+
+        samsung_clk_add_lookup(apll, fout_apll);
+        samsung_clk_add_lookup(mpll, fout_mpll);
+        samsung_clk_add_lookup(epll, fout_epll);
+        samsung_clk_add_lookup(vpll, fout_vpll);
+
+        samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
+                        ARRAY_SIZE(exynos4_fixed_rate_clks));
+        samsung_clk_register_mux(exynos4_mux_clks,
+                        ARRAY_SIZE(exynos4_mux_clks));
+        samsung_clk_register_div(exynos4_div_clks,
+                        ARRAY_SIZE(exynos4_div_clks));
+        samsung_clk_register_gate(exynos4_gate_clks,
+                        ARRAY_SIZE(exynos4_gate_clks));
+
+        if (exynos4_soc == EXYNOS4210) {
+                samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
+                        ARRAY_SIZE(exynos4210_fixed_rate_clks));
+                samsung_clk_register_mux(exynos4210_mux_clks,
+                        ARRAY_SIZE(exynos4210_mux_clks));
+                samsung_clk_register_div(exynos4210_div_clks,
+                        ARRAY_SIZE(exynos4210_div_clks));
+                samsung_clk_register_gate(exynos4210_gate_clks,
+                        ARRAY_SIZE(exynos4210_gate_clks));
+        } else {
+                samsung_clk_register_mux(exynos4x12_mux_clks,
+                        ARRAY_SIZE(exynos4x12_mux_clks));
+                samsung_clk_register_div(exynos4x12_div_clks,
+                        ARRAY_SIZE(exynos4x12_div_clks));
+                samsung_clk_register_gate(exynos4x12_gate_clks,
+                        ARRAY_SIZE(exynos4x12_gate_clks));
+        }
+
+        pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
+                "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
+                exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
+                _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
+                _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
+                _get_rate("arm_clk"));
+}
+CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
+CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
new file mode 100644
index 000000000000..bb54606ff035
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -0,0 +1,523 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5250 SoC.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <plat/cpu.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+#define SRC_CPU                 0x200
+#define DIV_CPU0                0x500
+#define SRC_CORE1               0x4204
+#define SRC_TOP0                0x10210
+#define SRC_TOP2                0x10218
+#define SRC_GSCL                0x10220
+#define SRC_DISP1_0             0x1022c
+#define SRC_MAU                 0x10240
+#define SRC_FSYS                0x10244
+#define SRC_GEN                 0x10248
+#define SRC_PERIC0              0x10250
+#define SRC_PERIC1              0x10254
+#define SRC_MASK_GSCL           0x10320
+#define SRC_MASK_DISP1_0        0x1032c
+#define SRC_MASK_MAU            0x10334
+#define SRC_MASK_FSYS           0x10340
+#define SRC_MASK_GEN            0x10344
+#define SRC_MASK_PERIC0         0x10350
+#define SRC_MASK_PERIC1         0x10354
+#define DIV_TOP0                0x10510
+#define DIV_TOP1                0x10514
+#define DIV_GSCL                0x10520
+#define DIV_DISP1_0             0x1052c
+#define DIV_GEN                 0x1053c
+#define DIV_MAU                 0x10544
+#define DIV_FSYS0               0x10548
+#define DIV_FSYS1               0x1054c
+#define DIV_FSYS2               0x10550
+#define DIV_PERIC0              0x10558
+#define DIV_PERIC1              0x1055c
+#define DIV_PERIC2              0x10560
+#define DIV_PERIC3              0x10564
+#define DIV_PERIC4              0x10568
+#define DIV_PERIC5              0x1056c
+#define GATE_IP_GSCL            0x10920
+#define GATE_IP_MFC             0x1092c
+#define GATE_IP_GEN             0x10934
+#define GATE_IP_FSYS            0x10944
+#define GATE_IP_PERIC           0x10950
+#define GATE_IP_PERIS           0x10960
+#define SRC_CDREX               0x20200
+#define PLL_DIV2_SEL            0x20a24
+#define GATE_IP_DISP1           0x10928
+
+/*
+ * Let each supported clock get a unique id. This id is used to lookup the clock
+ * for device tree based platforms. The clocks are categorized into three
+ * sections: core, sclk gate and bus interface gate clocks.
+ *
+ * When adding a new clock to this list, it is advised to choose a clock
+ * category and add it to the end of that category. That is because the the
+ * device tree source file is referring to these ids and any change in the
+ * sequence number of existing clocks will require corresponding change in the
+ * device tree files. This limitation would go away when pre-processor support
+ * for dtc would be available.
+ */
+enum exynos5250_clks {
+        none,
+
+        /* core clocks */
+        fin_pll,
+
+        /* gate for special clocks (sclk) */
+        sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
+        sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
+        sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
+        sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
+        sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
+
+        /* gate clocks */
+        gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
+        smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
+        jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
+        usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
+        sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
+        i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
+        spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
+        hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
+        tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
+        wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
+
+        nr_clks,
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static __initdata unsigned long exynos5250_clk_regs[] = {
+        SRC_CPU,
+        DIV_CPU0,
+        SRC_CORE1,
+        SRC_TOP0,
+        SRC_TOP2,
+        SRC_GSCL,
+        SRC_DISP1_0,
+        SRC_MAU,
+        SRC_FSYS,
+        SRC_GEN,
+        SRC_PERIC0,
+        SRC_PERIC1,
+        SRC_MASK_GSCL,
+        SRC_MASK_DISP1_0,
+        SRC_MASK_MAU,
+        SRC_MASK_FSYS,
+        SRC_MASK_GEN,
+        SRC_MASK_PERIC0,
+        SRC_MASK_PERIC1,
+        DIV_TOP0,
+        DIV_TOP1,
+        DIV_GSCL,
+        DIV_DISP1_0,
+        DIV_GEN,
+        DIV_MAU,
+        DIV_FSYS0,
+        DIV_FSYS1,
+        DIV_FSYS2,
+        DIV_PERIC0,
+        DIV_PERIC1,
+        DIV_PERIC2,
+        DIV_PERIC3,
+        DIV_PERIC4,
+        DIV_PERIC5,
+        GATE_IP_GSCL,
+        GATE_IP_MFC,
+        GATE_IP_GEN,
+        GATE_IP_FSYS,
+        GATE_IP_PERIC,
+        GATE_IP_PERIS,
+        SRC_CDREX,
+        PLL_DIV2_SEL,
+        GATE_IP_DISP1,
+};
+
+/* list of all parent clock list */
+PNAME(mout_apll_p)      = { "fin_pll", "fout_apll", };
+PNAME(mout_cpu_p)       = { "mout_apll", "mout_mpll", };
+PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
+PNAME(mout_mpll_p)      = { "fin_pll", "mout_mpll_fout" };
+PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
+PNAME(mout_bpll_p)      = { "fin_pll", "mout_bpll_fout" };
+PNAME(mout_vpllsrc_p)   = { "fin_pll", "sclk_hdmi27m" };
+PNAME(mout_vpll_p)      = { "mout_vpllsrc", "fout_vpll" };
+PNAME(mout_cpll_p)      = { "fin_pll", "fout_cpll" };
+PNAME(mout_epll_p)      = { "fin_pll", "fout_epll" };
+PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" };
+PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" };
+PNAME(mout_aclk166_p)   = { "sclk_cpll", "sclk_mpll_user" };
+PNAME(mout_aclk200_p)   = { "sclk_mpll_user", "sclk_bpll_user" };
+PNAME(mout_hdmi_p)      = { "div_hdmi_pixel", "sclk_hdmiphy" };
+PNAME(mout_usb3_p)      = { "sclk_mpll_user", "sclk_cpll" };
+PNAME(mout_group1_p)    = { "fin_pll", "fin_pll", "sclk_hdmi27m",
+                                "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
+                                "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+                                "sclk_cpll" };
+PNAME(mout_audio0_p)    = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+                                "sclk_uhostphy", "sclk_hdmiphy",
+                                "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+                                "sclk_cpll" };
+PNAME(mout_audio1_p)    = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+                                "sclk_uhostphy", "sclk_hdmiphy",
+                                "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+                                "sclk_cpll" };
+PNAME(mout_audio2_p)    = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
+                                "sclk_uhostphy", "sclk_hdmiphy",
+                                "sclk_mpll_user", "sclk_epll", "sclk_vpll",
+                                "sclk_cpll" };
+PNAME(mout_spdif_p)     = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
+                                "spdif_extclk" };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
+        FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
+};
+
+/* fixed rate clocks generated inside the soc */
+struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
+        FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
+        FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
+        FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
+        FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
+};
+
+struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
+        FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
+        FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
+};
+
+struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
+        MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+        MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+        MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
+        MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
+        MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
+        MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
+        MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
+        MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
+        MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
+        MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
+        MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
+        MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
+        MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
+        MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
+        MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
+        MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
+        MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
+        MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
+        MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
+        MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
+        MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
+        MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
+        MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
+        MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
+        MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
+        MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
+        MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
+        MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
+        MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
+        MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
+        MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
+        MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
+        MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
+        MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
+        MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
+        MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
+        MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
+        MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
+        MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
+        MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
+        MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
+        MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
+        MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
+};
+
+struct samsung_div_clock exynos5250_div_clks[] __initdata = {
+        DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
+        DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
+        DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
+        DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
+        DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
+        DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
+        DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
+        DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
+        DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
+        DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
+        DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
+        DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
+        DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
+        DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
+        DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
+        DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
+        DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
+        DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
+        DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
+        DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
+        DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
+        DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+        DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
+        DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+        DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
+        DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
+        DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
+        DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
+        DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
+        DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
+        DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
+        DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
+        DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
+        DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
+        DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
+        DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
+        DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
+        DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
+        DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
+        DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
+        DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
+        DIV_F(none, "div_mipi1_pre", "div_mipi1",
+                        DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre0", "div_mmc0",
+                        DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre1", "div_mmc1",
+                        DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre2", "div_mmc2",
+                        DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_mmc_pre3", "div_mmc3",
+                        DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_spi_pre0", "div_spi0",
+                        DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_spi_pre1", "div_spi1",
+                        DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
+        DIV_F(none, "div_spi_pre2", "div_spi2",
+                        DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
+};
+
+struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
+        GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
+        GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
+        GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
+        GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
+        GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
+        GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
+        GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
+        GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
+        GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
+        GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
+        GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
+        GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
+        GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
+        GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
+        GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
+        GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
+        GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
+        GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0),
+        GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
+        GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
+        GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
+        GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
+        GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
+        GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
+        GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
+        GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
+        GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
+        GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
+        GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
+        GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
+        GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
+        GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
+        GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
+        GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
+        GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
+        GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
+        GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
+        GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
+        GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
+        GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
+        GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
+        GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
+        GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
+        GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
+        GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
+        GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
+        GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
+        GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
+        GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
+        GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
+        GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
+        GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
+        GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
+        GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
+        GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
+        GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
+        GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
+        GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
+        GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
+        GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
+        GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
+        GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
+        GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
+        GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
+        GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, 0, 0),
+        GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
+        GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
+        GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
+        GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
+        GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
+        GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
+        GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
+        GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
+        GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
+        GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
+        GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
+        GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
+        GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
+        GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
+        GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
+        GATE(cmu_top, "cmu_top", "aclk66",
+                        GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
+        GATE(cmu_core, "cmu_core", "aclk66",
+                        GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(cmu_mem, "cmu_mem", "aclk66",
+                        GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
+        GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
+                        SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_cam0, "sclk_cam0", "div_cam0",
+                        SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_cam1, "sclk_cam1", "div_cam1",
+                        SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
+                        SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
+                        SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
+                        SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
+                        SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_dp, "sclk_dp", "div_dp",
+                        SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
+                        SRC_MASK_DISP1_0, 20, 0, 0),
+        GATE(sclk_audio0, "sclk_audio0", "div_audio0",
+                        SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0",
+                        SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1",
+                        SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2",
+                        SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3",
+                        SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_sata, "sclk_sata", "div_sata",
+                        SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_usb3, "sclk_usb3", "div_usb3",
+                        SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
+                        SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_uart0, "sclk_uart0", "div_uart0",
+                        SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_uart1, "sclk_uart1", "div_uart1",
+                        SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_uart2, "sclk_uart2", "div_uart2",
+                        SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_uart3, "sclk_uart3", "div_uart3",
+                        SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_pwm, "sclk_pwm", "div_pwm",
+                        SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_audio1, "sclk_audio1", "div_audio1",
+                        SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_audio2, "sclk_audio2", "div_audio2",
+                        SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
+                        SRC_MASK_PERIC1, 4, 0, 0),
+        GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
+                        SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
+                        SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+        GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
+                        SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
+        GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
+        GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
+        GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
+        GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
+        GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+        { .compatible = "samsung,clock-xxti", .data = (void *)0, },
+        { },
+};
+
+/* register exynox5250 clocks */
+void __init exynos5250_clk_init(struct device_node *np)
+{
+        void __iomem *reg_base;
+        struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
+
+        if (np) {
+                reg_base = of_iomap(np, 0);
+                if (!reg_base)
+                        panic("%s: failed to map registers\n", __func__);
+        } else {
+                panic("%s: unable to determine soc\n", __func__);
+        }
+
+        samsung_clk_init(np, reg_base, nr_clks,
+                        exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
+                        NULL, 0);
+        samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
+                        ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
+                        ext_clk_match);
+
+        apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
+                        reg_base + 0x100);
+        mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
+                        reg_base + 0x4100);
+        bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
+                        reg_base + 0x20110);
+        gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
+                        reg_base + 0x10150);
+        cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
+                        reg_base + 0x10120);
+        epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
+                        reg_base + 0x10130);
+        vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
+                        reg_base + 0x10140);
+
+        samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
+                        ARRAY_SIZE(exynos5250_fixed_rate_clks));
+        samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
+                        ARRAY_SIZE(exynos5250_fixed_factor_clks));
+        samsung_clk_register_mux(exynos5250_mux_clks,
+                        ARRAY_SIZE(exynos5250_mux_clks));
+        samsung_clk_register_div(exynos5250_div_clks,
+                        ARRAY_SIZE(exynos5250_div_clks));
+        samsung_clk_register_gate(exynos5250_gate_clks,
+                        ARRAY_SIZE(exynos5250_gate_clks));
+
+        pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
+                        _get_rate("armclk"));
+}
+CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
new file mode 100644
index 000000000000..a0a094c06f19
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5440 SoC.
+*/
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <plat/cpu.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+#define CLKEN_OV_VAL            0xf8
+#define CPU_CLK_STATUS          0xfc
+#define MISC_DOUT1              0x558
+
+/*
+ * Let each supported clock get a unique id. This id is used to lookup the clock
+ * for device tree based platforms.
+ */
+enum exynos5440_clks {
+        none, xtal, arm_clk,
+
+        spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
+        usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
+        b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
+
+        nr_clks,
+};
+
+/* parent clock name list */
+PNAME(mout_armclk_p)    = { "cplla", "cpllb" };
+PNAME(mout_spi_p)       = { "div125", "div200" };
+
+/* fixed rate clocks generated outside the soc */
+struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
+        FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
+};
+
+/* fixed rate clocks */
+struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
+        FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
+        FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
+        FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
+        FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
+        FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
+};
+
+/* fixed factor clocks */
+struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
+        FFACTOR(none, "div250", "ppll", 1, 4, 0),
+        FFACTOR(none, "div200", "ppll", 1, 5, 0),
+        FFACTOR(none, "div125", "div250", 1, 2, 0),
+};
+
+/* mux clocks */
+struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
+        MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
+        MUX_A(arm_clk, "arm_clk", mout_armclk_p,
+                        CPU_CLK_STATUS, 0, 1, "armclk"),
+};
+
+/* divider clocks */
+struct samsung_div_clock exynos5440_div_clks[] __initdata = {
+        DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
+};
+
+/* gate clocks */
+struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
+        GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
+        GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
+        GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
+        GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
+        GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
+        GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
+        GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
+        GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
+        GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
+        GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
+        GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
+        GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
+        GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
+        GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
+        GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
+        GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
+        GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
+        GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
+        GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
+        GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
+};
+
+static __initdata struct of_device_id ext_clk_match[] = {
+        { .compatible = "samsung,clock-xtal", .data = (void *)0, },
+        {},
+};
+
+/* register exynos5440 clocks */
+void __init exynos5440_clk_init(struct device_node *np)
+{
+        void __iomem *reg_base;
+
+        reg_base = of_iomap(np, 0);
+        if (!reg_base) {
+                pr_err("%s: failed to map clock controller registers,"
+                        " aborting clock initialization\n", __func__);
+                return;
+        }
+
+        samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
+        samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
+                ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
+
+        samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
+        samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
+
+        samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
+                        ARRAY_SIZE(exynos5440_fixed_rate_clks));
+        samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
+                        ARRAY_SIZE(exynos5440_fixed_factor_clks));
+        samsung_clk_register_mux(exynos5440_mux_clks,
+                        ARRAY_SIZE(exynos5440_mux_clks));
+        samsung_clk_register_div(exynos5440_div_clks,
+                        ARRAY_SIZE(exynos5440_div_clks));
+        samsung_clk_register_gate(exynos5440_gate_clks,
+                        ARRAY_SIZE(exynos5440_gate_clks));
+
+        pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk"));
+        pr_info("exynos5440 clock initialization complete\n");
+}
+CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
new file mode 100644
index 000000000000..89135f6be116
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the pll clocks.
+*/
+
+#include <linux/errno.h>
+#include "clk.h"
+#include "clk-pll.h"
+
+/*
+ * PLL35xx Clock Type
+ */
+
+#define PLL35XX_MDIV_MASK       (0x3FF)
+#define PLL35XX_PDIV_MASK       (0x3F)
+#define PLL35XX_SDIV_MASK       (0x7)
+#define PLL35XX_MDIV_SHIFT      (16)
+#define PLL35XX_PDIV_SHIFT      (8)
+#define PLL35XX_SDIV_SHIFT      (0)
+
+struct samsung_clk_pll35xx {
+        struct clk_hw           hw;
+        const void __iomem      *con_reg;
+};
+
+#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
+
+static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
+        u32 mdiv, pdiv, sdiv, pll_con;
+        u64 fvco = parent_rate;
+
+        pll_con = __raw_readl(pll->con_reg);
+        mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll35xx_clk_ops = {
+        .recalc_rate = samsung_pll35xx_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll35xx(const char *name,
+                        const char *pname, const void __iomem *con_reg)
+{
+        struct samsung_clk_pll35xx *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+                return NULL;
+        }
+
+        init.name = name;
+        init.ops = &samsung_pll35xx_clk_ops;
+        init.flags = CLK_GET_RATE_NOCACHE;
+        init.parent_names = &pname;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+        pll->con_reg = con_reg;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register pll clock %s\n", __func__,
+                                name);
+                kfree(pll);
+        }
+
+        if (clk_register_clkdev(clk, name, NULL))
+                pr_err("%s: failed to register lookup for %s", __func__, name);
+
+        return clk;
+}
+
+/*
+ * PLL36xx Clock Type
+ */
+
+#define PLL36XX_KDIV_MASK       (0xFFFF)
+#define PLL36XX_MDIV_MASK       (0x1FF)
+#define PLL36XX_PDIV_MASK       (0x3F)
+#define PLL36XX_SDIV_MASK       (0x7)
+#define PLL36XX_MDIV_SHIFT      (16)
+#define PLL36XX_PDIV_SHIFT      (8)
+#define PLL36XX_SDIV_SHIFT      (0)
+
+struct samsung_clk_pll36xx {
+        struct clk_hw           hw;
+        const void __iomem      *con_reg;
+};
+
+#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
+
+static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
+        u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
+        u64 fvco = parent_rate;
+
+        pll_con0 = __raw_readl(pll->con_reg);
+        pll_con1 = __raw_readl(pll->con_reg + 4);
+        mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
+        pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
+        sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
+        kdiv = pll_con1 & PLL36XX_KDIV_MASK;
+
+        fvco *= (mdiv << 16) + kdiv;
+        do_div(fvco, (pdiv << sdiv));
+        fvco >>= 16;
+
+        return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll36xx_clk_ops = {
+        .recalc_rate = samsung_pll36xx_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll36xx(const char *name,
+                        const char *pname, const void __iomem *con_reg)
+{
+        struct samsung_clk_pll36xx *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+                return NULL;
+        }
+
+        init.name = name;
+        init.ops = &samsung_pll36xx_clk_ops;
+        init.flags = CLK_GET_RATE_NOCACHE;
+        init.parent_names = &pname;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+        pll->con_reg = con_reg;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register pll clock %s\n", __func__,
+                                name);
+                kfree(pll);
+        }
+
+        if (clk_register_clkdev(clk, name, NULL))
+                pr_err("%s: failed to register lookup for %s", __func__, name);
+
+        return clk;
+}
+
+/*
+ * PLL45xx Clock Type
+ */
+
+#define PLL45XX_MDIV_MASK       (0x3FF)
+#define PLL45XX_PDIV_MASK       (0x3F)
+#define PLL45XX_SDIV_MASK       (0x7)
+#define PLL45XX_MDIV_SHIFT      (16)
+#define PLL45XX_PDIV_SHIFT      (8)
+#define PLL45XX_SDIV_SHIFT      (0)
+
+struct samsung_clk_pll45xx {
+        struct clk_hw           hw;
+        enum pll45xx_type       type;
+        const void __iomem      *con_reg;
+};
+
+#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
+
+static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
+        u32 mdiv, pdiv, sdiv, pll_con;
+        u64 fvco = parent_rate;
+
+        pll_con = __raw_readl(pll->con_reg);
+        mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
+
+        if (pll->type == pll_4508)
+                sdiv = sdiv - 1;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll45xx_clk_ops = {
+        .recalc_rate = samsung_pll45xx_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll45xx(const char *name,
+                        const char *pname, const void __iomem *con_reg,
+                        enum pll45xx_type type)
+{
+        struct samsung_clk_pll45xx *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+                return NULL;
+        }
+
+        init.name = name;
+        init.ops = &samsung_pll45xx_clk_ops;
+        init.flags = CLK_GET_RATE_NOCACHE;
+        init.parent_names = &pname;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+        pll->con_reg = con_reg;
+        pll->type = type;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register pll clock %s\n", __func__,
+                                name);
+                kfree(pll);
+        }
+
+        if (clk_register_clkdev(clk, name, NULL))
+                pr_err("%s: failed to register lookup for %s", __func__, name);
+
+        return clk;
+}
+
+/*
+ * PLL46xx Clock Type
+ */
+
+#define PLL46XX_MDIV_MASK       (0x1FF)
+#define PLL46XX_PDIV_MASK       (0x3F)
+#define PLL46XX_SDIV_MASK       (0x7)
+#define PLL46XX_MDIV_SHIFT      (16)
+#define PLL46XX_PDIV_SHIFT      (8)
+#define PLL46XX_SDIV_SHIFT      (0)
+
+#define PLL46XX_KDIV_MASK       (0xFFFF)
+#define PLL4650C_KDIV_MASK      (0xFFF)
+#define PLL46XX_KDIV_SHIFT      (0)
+
+struct samsung_clk_pll46xx {
+        struct clk_hw           hw;
+        enum pll46xx_type       type;
+        const void __iomem      *con_reg;
+};
+
+#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw)
+
+static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw);
+        u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
+        u64 fvco = parent_rate;
+
+        pll_con0 = __raw_readl(pll->con_reg);
+        pll_con1 = __raw_readl(pll->con_reg + 4);
+        mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+        pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
+        sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
+        kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
+                                        pll_con1 & PLL46XX_KDIV_MASK;
+
+        shift = pll->type == pll_4600 ? 16 : 10;
+        fvco *= (mdiv << shift) + kdiv;
+        do_div(fvco, (pdiv << sdiv));
+        fvco >>= shift;
+
+        return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll46xx_clk_ops = {
+        .recalc_rate = samsung_pll46xx_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll46xx(const char *name,
+                        const char *pname, const void __iomem *con_reg,
+                        enum pll46xx_type type)
+{
+        struct samsung_clk_pll46xx *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+                return NULL;
+        }
+
+        init.name = name;
+        init.ops = &samsung_pll46xx_clk_ops;
+        init.flags = CLK_GET_RATE_NOCACHE;
+        init.parent_names = &pname;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+        pll->con_reg = con_reg;
+        pll->type = type;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register pll clock %s\n", __func__,
+                                name);
+                kfree(pll);
+        }
+
+        if (clk_register_clkdev(clk, name, NULL))
+                pr_err("%s: failed to register lookup for %s", __func__, name);
+
+        return clk;
+}
+
+/*
+ * PLL2550x Clock Type
+ */
+
+#define PLL2550X_R_MASK       (0x1)
+#define PLL2550X_P_MASK       (0x3F)
+#define PLL2550X_M_MASK       (0x3FF)
+#define PLL2550X_S_MASK       (0x7)
+#define PLL2550X_R_SHIFT      (20)
+#define PLL2550X_P_SHIFT      (14)
+#define PLL2550X_M_SHIFT      (4)
+#define PLL2550X_S_SHIFT      (0)
+
+struct samsung_clk_pll2550x {
+        struct clk_hw           hw;
+        const void __iomem      *reg_base;
+        unsigned long           offset;
+};
+
+#define to_clk_pll2550x(_hw) container_of(_hw, struct samsung_clk_pll2550x, hw)
+
+static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw);
+        u32 r, p, m, s, pll_stat;
+        u64 fvco = parent_rate;
+
+        pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
+        r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
+        if (!r)
+                return 0;
+        p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
+        m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
+        s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
+
+        fvco *= m;
+        do_div(fvco, (p << s));
+
+        return (unsigned long)fvco;
+}
+
+static const struct clk_ops samsung_pll2550x_clk_ops = {
+        .recalc_rate = samsung_pll2550x_recalc_rate,
+};
+
+struct clk * __init samsung_clk_register_pll2550x(const char *name,
+                        const char *pname, const void __iomem *reg_base,
+                        const unsigned long offset)
+{
+        struct samsung_clk_pll2550x *pll;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate pll clk %s\n", __func__, name);
+                return NULL;
+        }
+
+        init.name = name;
+        init.ops = &samsung_pll2550x_clk_ops;
+        init.flags = CLK_GET_RATE_NOCACHE;
+        init.parent_names = &pname;
+        init.num_parents = 1;
+
+        pll->hw.init = &init;
+        pll->reg_base = reg_base;
+        pll->offset = offset;
+
+        clk = clk_register(NULL, &pll->hw);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to register pll clock %s\n", __func__,
+                                name);
+                kfree(pll);
+        }
+
+        if (clk_register_clkdev(clk, name, NULL))
+                pr_err("%s: failed to register lookup for %s", __func__, name);
+
+        return clk;
+}
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
new file mode 100644
index 000000000000..f33786e9a78b
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all PLL's in Samsung platforms
+*/
+
+#ifndef __SAMSUNG_CLK_PLL_H
+#define __SAMSUNG_CLK_PLL_H
+
+enum pll45xx_type {
+        pll_4500,
+        pll_4502,
+        pll_4508
+};
+
+enum pll46xx_type {
+        pll_4600,
+        pll_4650,
+        pll_4650c,
+};
+
+extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
+                        const char *pname, const void __iomem *con_reg);
+extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
+                        const char *pname, const void __iomem *con_reg);
+extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
+                        const char *pname, const void __iomem *con_reg,
+                        enum pll45xx_type type);
+extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
+                        const char *pname, const void __iomem *con_reg,
+                        enum pll46xx_type type);
+extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
+                        const char *pname, const void __iomem *reg_base,
+                        const unsigned long offset);
+
+#endif /* __SAMSUNG_CLK_PLL_H */
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
new file mode 100644
index 000000000000..cd3c40ab50f3
--- /dev/null
+++ b/drivers/clk/samsung/clk.c
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file includes utility functions to register clocks to common
+ * clock framework for Samsung platforms.
+*/
+
+#include <linux/syscore_ops.h>
+#include "clk.h"
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+#ifdef CONFIG_OF
+static struct clk_onecell_data clk_data;
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *reg_dump;
+static unsigned long nr_reg_dump;
+
+static int samsung_clk_suspend(void)
+{
+        struct samsung_clk_reg_dump *rd = reg_dump;
+        unsigned long i;
+
+        for (i = 0; i < nr_reg_dump; i++, rd++)
+                rd->value = __raw_readl(reg_base + rd->offset);
+
+        return 0;
+}
+
+static void samsung_clk_resume(void)
+{
+        struct samsung_clk_reg_dump *rd = reg_dump;
+        unsigned long i;
+
+        for (i = 0; i < nr_reg_dump; i++, rd++)
+                __raw_writel(rd->value, reg_base + rd->offset);
+}
+
+static struct syscore_ops samsung_clk_syscore_ops = {
+        .suspend        = samsung_clk_suspend,
+        .resume         = samsung_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+/* setup the essentials required to support clock lookup using ccf */
+void __init samsung_clk_init(struct device_node *np, void __iomem *base,
+                unsigned long nr_clks, unsigned long *rdump,
+                unsigned long nr_rdump, unsigned long *soc_rdump,
+                unsigned long nr_soc_rdump)
+{
+        reg_base = base;
+
+#ifdef CONFIG_PM_SLEEP
+        if (rdump && nr_rdump) {
+                unsigned int idx;
+                reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
+                                * (nr_rdump + nr_soc_rdump), GFP_KERNEL);
+                if (!reg_dump) {
+                        pr_err("%s: memory alloc for register dump failed\n",
+                                        __func__);
+                        return;
+                }
+
+                for (idx = 0; idx < nr_rdump; idx++)
+                        reg_dump[idx].offset = rdump[idx];
+                for (idx = 0; idx < nr_soc_rdump; idx++)
+                        reg_dump[nr_rdump + idx].offset = soc_rdump[idx];
+                nr_reg_dump = nr_rdump + nr_soc_rdump;
+                register_syscore_ops(&samsung_clk_syscore_ops);
+        }
+#endif
+
+        clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
+        if (!clk_table)
+                panic("could not allocate clock lookup table\n");
+
+        if (!np)
+                return;
+
+#ifdef CONFIG_OF
+        clk_data.clks = clk_table;
+        clk_data.clk_num = nr_clks;
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+#endif
+}
+
+/* add a clock instance to the clock lookup table used for dt based lookup */
+void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
+{
+        if (clk_table && id)
+                clk_table[id] = clk;
+}
+
+/* register a list of aliases */
+void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
+                                        unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx, ret;
+
+        if (!clk_table) {
+                pr_err("%s: clock table missing\n", __func__);
+                return;
+        }
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                if (!list->id) {
+                        pr_err("%s: clock id missing for index %d\n", __func__,
+                                idx);
+                        continue;
+                }
+
+                clk = clk_table[list->id];
+                if (!clk) {
+                        pr_err("%s: failed to find clock %d\n", __func__,
+                                list->id);
+                        continue;
+                }
+
+                ret = clk_register_clkdev(clk, list->alias, list->dev_name);
+                if (ret)
+                        pr_err("%s: failed to register lookup %s\n",
+                                        __func__, list->alias);
+        }
+}
+
+/* register a list of fixed clocks */
+void __init samsung_clk_register_fixed_rate(
+                struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx, ret;
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                clk = clk_register_fixed_rate(NULL, list->name,
+                        list->parent_name, list->flags, list->fixed_rate);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n", __func__,
+                                list->name);
+                        continue;
+                }
+
+                samsung_clk_add_lookup(clk, list->id);
+
+                /*
+                 * Unconditionally add a clock lookup for the fixed rate clocks.
+                 * There are not many of these on any of Samsung platforms.
+                 */
+                ret = clk_register_clkdev(clk, list->name, NULL);
+                if (ret)
+                        pr_err("%s: failed to register clock lookup for %s",
+                                __func__, list->name);
+        }
+}
+
+/* register a list of fixed factor clocks */
+void __init samsung_clk_register_fixed_factor(
+                struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx;
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                clk = clk_register_fixed_factor(NULL, list->name,
+                        list->parent_name, list->flags, list->mult, list->div);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n", __func__,
+                                list->name);
+                        continue;
+                }
+
+                samsung_clk_add_lookup(clk, list->id);
+        }
+}
+
+/* register a list of mux clocks */
+void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
+                                        unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx, ret;
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                clk = clk_register_mux(NULL, list->name, list->parent_names,
+                        list->num_parents, list->flags, reg_base + list->offset,
+                        list->shift, list->width, list->mux_flags, &lock);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n", __func__,
+                                list->name);
+                        continue;
+                }
+
+                samsung_clk_add_lookup(clk, list->id);
+
+                /* register a clock lookup only if a clock alias is specified */
+                if (list->alias) {
+                        ret = clk_register_clkdev(clk, list->alias,
+                                                list->dev_name);
+                        if (ret)
+                                pr_err("%s: failed to register lookup %s\n",
+                                                __func__, list->alias);
+                }
+        }
+}
+
+/* register a list of div clocks */
+void __init samsung_clk_register_div(struct samsung_div_clock *list,
+                                        unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx, ret;
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                if (list->table)
+                        clk = clk_register_divider_table(NULL, list->name,
+                                        list->parent_name, list->flags,
+                                        reg_base + list->offset, list->shift,
+                                        list->width, list->div_flags,
+                                        list->table, &lock);
+                else
+                        clk = clk_register_divider(NULL, list->name,
+                                        list->parent_name, list->flags,
+                                        reg_base + list->offset, list->shift,
+                                        list->width, list->div_flags, &lock);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n", __func__,
+                                list->name);
+                        continue;
+                }
+
+                samsung_clk_add_lookup(clk, list->id);
+
+                /* register a clock lookup only if a clock alias is specified */
+                if (list->alias) {
+                        ret = clk_register_clkdev(clk, list->alias,
+                                                list->dev_name);
+                        if (ret)
+                                pr_err("%s: failed to register lookup %s\n",
+                                                __func__, list->alias);
+                }
+        }
+}
+
+/* register a list of gate clocks */
+void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
+                                                unsigned int nr_clk)
+{
+        struct clk *clk;
+        unsigned int idx, ret;
+
+        for (idx = 0; idx < nr_clk; idx++, list++) {
+                clk = clk_register_gate(NULL, list->name, list->parent_name,
+                                list->flags, reg_base + list->offset,
+                                list->bit_idx, list->gate_flags, &lock);
+                if (IS_ERR(clk)) {
+                        pr_err("%s: failed to register clock %s\n", __func__,
+                                list->name);
+                        continue;
+                }
+
+                /* register a clock lookup only if a clock alias is specified */
+                if (list->alias) {
+                        ret = clk_register_clkdev(clk, list->alias,
+                                                        list->dev_name);
+                        if (ret)
+                                pr_err("%s: failed to register lookup %s\n",
+                                        __func__, list->alias);
+                }
+
+                samsung_clk_add_lookup(clk, list->id);
+        }
+}
+
+/*
+ * obtain the clock speed of all external fixed clock sources from device
+ * tree and register it
+ */
+#ifdef CONFIG_OF
+void __init samsung_clk_of_register_fixed_ext(
+                        struct samsung_fixed_rate_clock *fixed_rate_clk,
+                        unsigned int nr_fixed_rate_clk,
+                        struct of_device_id *clk_matches)
+{
+        const struct of_device_id *match;
+        struct device_node *np;
+        u32 freq;
+
+        for_each_matching_node_and_match(np, clk_matches, &match) {
+                if (of_property_read_u32(np, "clock-frequency", &freq))
+                        continue;
+                fixed_rate_clk[(u32)match->data].fixed_rate = freq;
+        }
+        samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk);
+}
+#endif
+
+/* utility function to get the rate of a specified clock */
+unsigned long _get_rate(const char *clk_name)
+{
+        struct clk *clk;
+        unsigned long rate;
+
+        clk = clk_get(NULL, clk_name);
+        if (IS_ERR(clk)) {
+                pr_err("%s: could not find clock %s\n", __func__, clk_name);
+                return 0;
+        }
+        rate = clk_get_rate(clk);
+        clk_put(clk);
+        return rate;
+}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
new file mode 100644
index 000000000000..10b2111f0c0f
--- /dev/null
+++ b/drivers/clk/samsung/clk.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2013 Linaro Ltd.
+ * Author: Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for all Samsung platforms
+*/
+
+#ifndef __SAMSUNG_CLK_H
+#define __SAMSUNG_CLK_H
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <mach/map.h>
+
+/**
+ * struct samsung_clock_alias: information about mux clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_clock_alias {
+        unsigned int            id;
+        const char              *dev_name;
+        const char              *alias;
+};
+
+#define ALIAS(_id, dname, a)    \
+        {                                                       \
+                .id             = _id,                          \
+                .dev_name       = dname,                        \
+                .alias          = a,                            \
+        }
+
+/**
+ * struct samsung_fixed_rate_clock: information about fixed-rate clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-rate clock.
+ * @parent_name: optional parent clock name.
+ * @flags: optional fixed-rate clock flags.
+ * @fixed-rate: fixed clock rate of this clock.
+ */
+struct samsung_fixed_rate_clock {
+        unsigned int            id;
+        char                    *name;
+        const char              *parent_name;
+        unsigned long           flags;
+        unsigned long           fixed_rate;
+};
+
+#define FRATE(_id, cname, pname, f, frate)              \
+        {                                               \
+                .id             = _id,                  \
+                .name           = cname,                \
+                .parent_name    = pname,                \
+                .flags          = f,                    \
+                .fixed_rate     = frate,                \
+        }
+
+/*
+ * struct samsung_fixed_factor_clock: information about fixed-factor clock
+ * @id: platform specific id of the clock.
+ * @name: name of this fixed-factor clock.
+ * @parent_name: parent clock name.
+ * @mult: fixed multiplication factor.
+ * @div: fixed division factor.
+ * @flags: optional fixed-factor clock flags.
+ */
+struct samsung_fixed_factor_clock {
+        unsigned int            id;
+        char                    *name;
+        const char              *parent_name;
+        unsigned long           mult;
+        unsigned long           div;
+        unsigned long           flags;
+};
+
+#define FFACTOR(_id, cname, pname, m, d, f)             \
+        {                                               \
+                .id             = _id,                  \
+                .name           = cname,                \
+                .parent_name    = pname,                \
+                .mult           = m,                    \
+                .div            = d,                    \
+                .flags          = f,                    \
+        }
+
+/**
+ * struct samsung_mux_clock: information about mux clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this mux clock.
+ * @parent_names: array of pointer to parent clock names.
+ * @num_parents: number of parents listed in @parent_names.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the mux.
+ * @shift: starting bit location of the mux control bit-field in @reg.
+ * @width: width of the mux control bit-field in @reg.
+ * @mux_flags: flags for mux-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_mux_clock {
+        unsigned int            id;
+        const char              *dev_name;
+        const char              *name;
+        const char              **parent_names;
+        u8                      num_parents;
+        unsigned long           flags;
+        unsigned long           offset;
+        u8                      shift;
+        u8                      width;
+        u8                      mux_flags;
+        const char              *alias;
+};
+
+#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a)     \
+        {                                                       \
+                .id             = _id,                          \
+                .dev_name       = dname,                        \
+                .name           = cname,                        \
+                .parent_names   = pnames,                       \
+                .num_parents    = ARRAY_SIZE(pnames),           \
+                .flags          = f,                            \
+                .offset         = o,                            \
+                .shift          = s,                            \
+                .width          = w,                            \
+                .mux_flags      = mf,                           \
+                .alias          = a,                            \
+        }
+
+#define MUX(_id, cname, pnames, o, s, w)                        \
+        __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
+
+#define MUX_A(_id, cname, pnames, o, s, w, a)                   \
+        __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
+
+#define MUX_F(_id, cname, pnames, o, s, w, f, mf)               \
+        __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
+
+/**
+ * @id: platform specific id of the clock.
+ * struct samsung_div_clock: information about div clock
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this div clock.
+ * @parent_name: name of the parent clock.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the div.
+ * @shift: starting bit location of the div control bit-field in @reg.
+ * @div_flags: flags for div-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_div_clock {
+        unsigned int            id;
+        const char              *dev_name;
+        const char              *name;
+        const char              *parent_name;
+        unsigned long           flags;
+        unsigned long           offset;
+        u8                      shift;
+        u8                      width;
+        u8                      div_flags;
+        const char              *alias;
+        struct clk_div_table    *table;
+};
+
+#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t)   \
+        {                                                       \
+                .id             = _id,                          \
+                .dev_name       = dname,                        \
+                .name           = cname,                        \
+                .parent_name    = pname,                        \
+                .flags          = f,                            \
+                .offset         = o,                            \
+                .shift          = s,                            \
+                .width          = w,                            \
+                .div_flags      = df,                           \
+                .alias          = a,                            \
+                .table          = t,                            \
+        }
+
+#define DIV(_id, cname, pname, o, s, w)                         \
+        __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
+
+#define DIV_A(_id, cname, pname, o, s, w, a)                    \
+        __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
+
+#define DIV_F(_id, cname, pname, o, s, w, f, df)                \
+        __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
+
+#define DIV_T(_id, cname, pname, o, s, w, t)                    \
+        __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
+
+/**
+ * struct samsung_gate_clock: information about gate clock
+ * @id: platform specific id of the clock.
+ * @dev_name: name of the device to which this clock belongs.
+ * @name: name of this gate clock.
+ * @parent_name: name of the parent clock.
+ * @flags: optional flags for basic clock.
+ * @offset: offset of the register for configuring the gate.
+ * @bit_idx: bit index of the gate control bit-field in @reg.
+ * @gate_flags: flags for gate-type clock.
+ * @alias: optional clock alias name to be assigned to this clock.
+ */
+struct samsung_gate_clock {
+        unsigned int            id;
+        const char              *dev_name;
+        const char              *name;
+        const char              *parent_name;
+        unsigned long           flags;
+        unsigned long           offset;
+        u8                      bit_idx;
+        u8                      gate_flags;
+        const char              *alias;
+};
+
+#define __GATE(_id, dname, cname, pname, o, b, f, gf, a)        \
+        {                                                       \
+                .id             = _id,                          \
+                .dev_name       = dname,                        \
+                .name           = cname,                        \
+                .parent_name    = pname,                        \
+                .flags          = f,                            \
+                .offset         = o,                            \
+                .bit_idx        = b,                            \
+                .gate_flags     = gf,                           \
+                .alias          = a,                            \
+        }
+
+#define GATE(_id, cname, pname, o, b, f, gf)                    \
+        __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
+
+#define GATE_A(_id, cname, pname, o, b, f, gf, a)               \
+        __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
+
+#define GATE_D(_id, dname, cname, pname, o, b, f, gf)           \
+        __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
+
+#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a)       \
+        __GATE(_id, dname, cname, pname, o, b, f, gf, a)
+
+#define PNAME(x) static const char *x[] __initdata
+
+/**
+ * struct samsung_clk_reg_dump: register dump of clock controller registers.
+ * @offset: clock register offset from the controller base address.
+ * @value: the value to be register at offset.
+ */
+struct samsung_clk_reg_dump {
+        u32     offset;
+        u32     value;
+};
+
+extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
+                unsigned long nr_clks, unsigned long *rdump,
+                unsigned long nr_rdump, unsigned long *soc_rdump,
+                unsigned long nr_soc_rdump);
+extern void __init samsung_clk_of_register_fixed_ext(
+                struct samsung_fixed_rate_clock *fixed_rate_clk,
+                unsigned int nr_fixed_rate_clk,
+                struct of_device_id *clk_matches);
+
+extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
+
+extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
+                unsigned int nr_clk);
+extern void __init samsung_clk_register_fixed_rate(
+                struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
+extern void __init samsung_clk_register_fixed_factor(
+                struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
+extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
+                unsigned int nr_clk);
+extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
+                unsigned int nr_clk);
+extern void __init samsung_clk_register_gate(
+                struct samsung_gate_clock *clk_list, unsigned int nr_clk);
+
+extern unsigned long _get_rate(const char *clk_name);
+
+#endif /* __SAMSUNG_CLK_H */
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 2b41b0f4f731..f49fac2d193a 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -9,3 +9,4 @@ obj-y					+= clk-super.o
 
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clk-tegra20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += clk-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += clk-tegra114.o
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 6dd533251e7b..bafee9895a24 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -41,7 +41,9 @@ static DEFINE_SPINLOCK(periph_ref_lock);
 #define write_rst_clr(val, gate) \
         writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
 
-#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
+#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
+
+#define LVL2_CLK_GATE_OVRE 0x554
 
 /* Peripheral gate clock ops */
 static int clk_periph_is_enabled(struct clk_hw *hw)
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
                 }
         }
 
+        if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
+                writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+                writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
+                udelay(1);
+                writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+        }
+
         spin_unlock_irqrestore(&periph_ref_lock, flags);
 
         return 0;
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 788486e6331a..b2309d37a963 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -16,6 +16,7 @@
 
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+#include <linux/export.h>
 #include <linux/slab.h>
 #include <linux/err.h>
 
@@ -128,6 +129,7 @@ void tegra_periph_reset_deassert(struct clk *c)
 
         tegra_periph_reset(gate, 0);
 }
+EXPORT_SYMBOL(tegra_periph_reset_deassert);
 
 void tegra_periph_reset_assert(struct clk *c)
 {
@@ -147,6 +149,7 @@ void tegra_periph_reset_assert(struct clk *c)
 
         tegra_periph_reset(gate, 1);
 }
+EXPORT_SYMBOL(tegra_periph_reset_assert);
 
 const struct clk_ops tegra_clk_periph_ops = {
         .get_parent = clk_periph_get_parent,
@@ -170,14 +173,15 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
 static struct clk *_tegra_clk_register_periph(const char *name,
                         const char **parent_names, int num_parents,
                         struct tegra_clk_periph *periph,
-                        void __iomem *clk_base, u32 offset, bool div)
+                        void __iomem *clk_base, u32 offset, bool div,
+                        unsigned long flags)
 {
         struct clk *clk;
         struct clk_init_data init;
 
         init.name = name;
         init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
-        init.flags = div ? 0 : CLK_SET_RATE_PARENT;
+        init.flags = flags;
         init.parent_names = parent_names;
         init.num_parents = num_parents;
 
@@ -202,10 +206,10 @@ static struct clk *_tegra_clk_register_periph(const char *name,
 struct clk *tegra_clk_register_periph(const char *name,
                 const char **parent_names, int num_parents,
                 struct tegra_clk_periph *periph, void __iomem *clk_base,
-                u32 offset)
+                u32 offset, unsigned long flags)
 {
         return _tegra_clk_register_periph(name, parent_names, num_parents,
-                        periph, clk_base, offset, true);
+                        periph, clk_base, offset, true, flags);
 }
 
 struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -214,5 +218,5 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
                 u32 offset)
 {
         return _tegra_clk_register_periph(name, parent_names, num_parents,
-                        periph, clk_base, offset, false);
+                        periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
 }
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 165f24734c1b..17c2cc086eb4 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -79,6 +79,48 @@
 #define PLLE_SS_CTRL 0x68
 #define PLLE_SS_DISABLE (7 << 10)
 
+#define PLLE_AUX_PLLP_SEL       BIT(2)
+#define PLLE_AUX_ENABLE_SWCTL   BIT(4)
+#define PLLE_AUX_SEQ_ENABLE     BIT(24)
+#define PLLE_AUX_PLLRE_SEL      BIT(28)
+
+#define PLLE_MISC_PLLE_PTS      BIT(8)
+#define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
+#define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
+#define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
+#define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
+#define PLLE_MISC_VREG_CTRL_SHIFT       2
+#define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
+
+#define PLLCX_MISC_STROBE       BIT(31)
+#define PLLCX_MISC_RESET        BIT(30)
+#define PLLCX_MISC_SDM_DIV_SHIFT 28
+#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
+#define PLLCX_MISC_FILT_DIV_SHIFT 26
+#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
+#define PLLCX_MISC_ALPHA_SHIFT 18
+#define PLLCX_MISC_DIV_LOW_RANGE \
+                ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
+                (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
+#define PLLCX_MISC_DIV_HIGH_RANGE \
+                ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
+                (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
+#define PLLCX_MISC_COEF_LOW_RANGE \
+                ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
+#define PLLCX_MISC_KA_SHIFT 2
+#define PLLCX_MISC_KB_SHIFT 9
+#define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
+                            (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
+                            PLLCX_MISC_DIV_LOW_RANGE | \
+                            PLLCX_MISC_RESET)
+#define PLLCX_MISC1_DEFAULT 0x000d2308
+#define PLLCX_MISC2_DEFAULT 0x30211200
+#define PLLCX_MISC3_DEFAULT 0x200
+
+#define PMC_PLLM_WB0_OVERRIDE   0x1dc
+#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
+#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK BIT(27)
+
 #define PMC_SATA_PWRGT 0x1ac
 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
@@ -101,6 +143,24 @@
 #define divn_max(p) (divn_mask(p))
 #define divp_max(p) (1 << (divp_mask(p)))
 
+
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+/* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w */
+#define PLLXC_PDIV_MAX                  14
+
+/* non-monotonic mapping below is not a typo */
+static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
+        /* PDIV: 0, 1, 2, 3, 4, 5, 6,  7,  8,  9, 10, 11, 12, 13, 14 */
+        /* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32
+};
+
+#define PLLCX_PDIV_MAX 7
+static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
+        /* PDIV: 0, 1, 2, 3, 4, 5,  6,  7 */
+        /* p: */ 1, 2, 3, 4, 6, 8, 12, 16
+};
+#endif
+
 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 {
         u32 val;
@@ -108,25 +168,36 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
         if (!(pll->flags & TEGRA_PLL_USE_LOCK))
                 return;
 
+        if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
+                return;
+
         val = pll_readl_misc(pll);
         val |= BIT(pll->params->lock_enable_bit_idx);
         pll_writel_misc(val, pll);
 }
 
-static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
-                                 void __iomem *lock_addr, u32 lock_bit_idx)
+static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 {
         int i;
-        u32 val;
+        u32 val, lock_mask;
+        void __iomem *lock_addr;
 
         if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
                 udelay(pll->params->lock_delay);
                 return 0;
         }
 
+        lock_addr = pll->clk_base;
+        if (pll->flags & TEGRA_PLL_LOCK_MISC)
+                lock_addr += pll->params->misc_reg;
+        else
+                lock_addr += pll->params->base_reg;
+
+        lock_mask = pll->params->lock_mask;
+
         for (i = 0; i < pll->params->lock_delay; i++) {
                 val = readl_relaxed(lock_addr);
-                if (val & BIT(lock_bit_idx)) {
+                if ((val & lock_mask) == lock_mask) {
                         udelay(PLL_POST_LOCK_DELAY);
                         return 0;
                 }
@@ -155,7 +226,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
         return val & PLL_BASE_ENABLE ? 1 : 0;
 }
 
-static int _clk_pll_enable(struct clk_hw *hw)
+static void _clk_pll_enable(struct clk_hw *hw)
 {
         struct tegra_clk_pll *pll = to_clk_pll(hw);
         u32 val;
@@ -163,7 +234,8 @@ static int _clk_pll_enable(struct clk_hw *hw)
         clk_pll_enable_lock(pll);
 
         val = pll_readl_base(pll);
-        val &= ~PLL_BASE_BYPASS;
+        if (pll->flags & TEGRA_PLL_BYPASS)
+                val &= ~PLL_BASE_BYPASS;
         val |= PLL_BASE_ENABLE;
         pll_writel_base(val, pll);
 
@@ -172,11 +244,6 @@ static int _clk_pll_enable(struct clk_hw *hw)
                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
         }
-
-        clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->base_reg,
-                              pll->params->lock_bit_idx);
-
-        return 0;
 }
 
 static void _clk_pll_disable(struct clk_hw *hw)
@@ -185,7 +252,9 @@ static void _clk_pll_disable(struct clk_hw *hw)
         u32 val;
 
         val = pll_readl_base(pll);
-        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+        if (pll->flags & TEGRA_PLL_BYPASS)
+                val &= ~PLL_BASE_BYPASS;
+        val &= ~PLL_BASE_ENABLE;
         pll_writel_base(val, pll);
 
         if (pll->flags & TEGRA_PLLM) {
@@ -204,7 +273,9 @@ static int clk_pll_enable(struct clk_hw *hw)
         if (pll->lock)
                 spin_lock_irqsave(pll->lock, flags);
 
-        ret = _clk_pll_enable(hw);
+        _clk_pll_enable(hw);
+
+        ret = clk_pll_wait_for_lock(pll);
 
         if (pll->lock)
                 spin_unlock_irqrestore(pll->lock, flags);
@@ -241,8 +312,6 @@ static int _get_table_rate(struct clk_hw *hw,
         if (sel->input_rate == 0)
                 return -EINVAL;
 
-        BUG_ON(sel->p < 1);
-
         cfg->input_rate = sel->input_rate;
         cfg->output_rate = sel->output_rate;
         cfg->m = sel->m;
@@ -257,6 +326,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
                       unsigned long rate, unsigned long parent_rate)
 {
         struct tegra_clk_pll *pll = to_clk_pll(hw);
+        struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
         unsigned long cfreq;
         u32 p_div = 0;
 
@@ -290,88 +360,119 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
              cfg->output_rate <<= 1)
                 p_div++;
 
-        cfg->p = 1 << p_div;
         cfg->m = parent_rate / cfreq;
         cfg->n = cfg->output_rate / cfreq;
         cfg->cpcon = OUT_OF_TABLE_CPCON;
 
         if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
-            cfg->p > divp_max(pll) || cfg->output_rate > pll->params->vco_max) {
+            (1 << p_div) > divp_max(pll)
+            || cfg->output_rate > pll->params->vco_max) {
                 pr_err("%s: Failed to set %s rate %lu\n",
                        __func__, __clk_get_name(hw->clk), rate);
                 return -EINVAL;
         }
 
+        if (p_tohw) {
+                p_div = 1 << p_div;
+                while (p_tohw->pdiv) {
+                        if (p_div <= p_tohw->pdiv) {
+                                cfg->p = p_tohw->hw_val;
+                                break;
+                        }
+                        p_tohw++;
+                }
+                if (!p_tohw->pdiv)
+                        return -EINVAL;
+        } else
+                cfg->p = p_div;
+
         return 0;
 }
 
-static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
-                        unsigned long rate)
+static void _update_pll_mnp(struct tegra_clk_pll *pll,
+                            struct tegra_clk_pll_freq_table *cfg)
 {
-        struct tegra_clk_pll *pll = to_clk_pll(hw);
-        unsigned long flags = 0;
-        u32 divp, val, old_base;
-        int state;
-
-        divp = __ffs(cfg->p);
-
-        if (pll->flags & TEGRA_PLLU)
-                divp ^= 1;
+        u32 val;
 
-        if (pll->lock)
-                spin_lock_irqsave(pll->lock, flags);
+        val = pll_readl_base(pll);
 
-        old_base = val = pll_readl_base(pll);
         val &= ~((divm_mask(pll) << pll->divm_shift) |
                  (divn_mask(pll) << pll->divn_shift) |
                  (divp_mask(pll) << pll->divp_shift));
         val |= ((cfg->m << pll->divm_shift) |
                 (cfg->n << pll->divn_shift) |
-                (divp << pll->divp_shift));
-        if (val == old_base) {
-                if (pll->lock)
-                        spin_unlock_irqrestore(pll->lock, flags);
-                return 0;
+                (cfg->p << pll->divp_shift));
+
+        pll_writel_base(val, pll);
+}
+
+static void _get_pll_mnp(struct tegra_clk_pll *pll,
+                         struct tegra_clk_pll_freq_table *cfg)
+{
+        u32 val;
+
+        val = pll_readl_base(pll);
+
+        cfg->m = (val >> pll->divm_shift) & (divm_mask(pll));
+        cfg->n = (val >> pll->divn_shift) & (divn_mask(pll));
+        cfg->p = (val >> pll->divp_shift) & (divp_mask(pll));
+}
+
+static void _update_pll_cpcon(struct tegra_clk_pll *pll,
+                              struct tegra_clk_pll_freq_table *cfg,
+                              unsigned long rate)
+{
+        u32 val;
+
+        val = pll_readl_misc(pll);
+
+        val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
+        val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
+
+        if (pll->flags & TEGRA_PLL_SET_LFCON) {
+                val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
+                if (cfg->n >= PLLDU_LFCON_SET_DIVN)
+                        val |= 1 << PLL_MISC_LFCON_SHIFT;
+        } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
+                val &= ~(1 << PLL_MISC_DCCON_SHIFT);
+                if (rate >= (pll->params->vco_max >> 1))
+                        val |= 1 << PLL_MISC_DCCON_SHIFT;
         }
 
+        pll_writel_misc(val, pll);
+}
+
+static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
+                        unsigned long rate)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        int state, ret = 0;
+
         state = clk_pll_is_enabled(hw);
 
-        if (state) {
+        if (state)
                 _clk_pll_disable(hw);
-                val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
-        }
-        pll_writel_base(val, pll);
 
-        if (pll->flags & TEGRA_PLL_HAS_CPCON) {
-                val = pll_readl_misc(pll);
-                val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
-                val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
-                if (pll->flags & TEGRA_PLL_SET_LFCON) {
-                        val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
-                        if (cfg->n >= PLLDU_LFCON_SET_DIVN)
-                                val |= 0x1 << PLL_MISC_LFCON_SHIFT;
-                } else if (pll->flags & TEGRA_PLL_SET_DCCON) {
-                        val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
-                        if (rate >= (pll->params->vco_max >> 1))
-                                val |= 0x1 << PLL_MISC_DCCON_SHIFT;
-                }
-                pll_writel_misc(val, pll);
-        }
+        _update_pll_mnp(pll, cfg);
 
-        if (pll->lock)
-                spin_unlock_irqrestore(pll->lock, flags);
+        if (pll->flags & TEGRA_PLL_HAS_CPCON)
+                _update_pll_cpcon(pll, cfg, rate);
 
-        if (state)
-                clk_pll_enable(hw);
+        if (state) {
+                _clk_pll_enable(hw);
+                ret = clk_pll_wait_for_lock(pll);
+        }
 
-        return 0;
+        return ret;
 }
 
 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                         unsigned long parent_rate)
 {
         struct tegra_clk_pll *pll = to_clk_pll(hw);
-        struct tegra_clk_pll_freq_table cfg;
+        struct tegra_clk_pll_freq_table cfg, old_cfg;
+        unsigned long flags = 0;
+        int ret = 0;
 
         if (pll->flags & TEGRA_PLL_FIXED) {
                 if (rate != pll->fixed_rate) {
@@ -387,7 +488,18 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
             _calc_rate(hw, &cfg, rate, parent_rate))
                 return -EINVAL;
 
-        return _program_pll(hw, &cfg, rate);
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _get_pll_mnp(pll, &old_cfg);
+
+        if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
+                ret = _program_pll(hw, &cfg, rate);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
 }
 
 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -409,7 +521,7 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
                 return -EINVAL;
 
         output_rate *= cfg.n;
-        do_div(output_rate, cfg.m * cfg.p);
+        do_div(output_rate, cfg.m * (1 << cfg.p));
 
         return output_rate;
 }
@@ -418,11 +530,15 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
                                          unsigned long parent_rate)
 {
         struct tegra_clk_pll *pll = to_clk_pll(hw);
-        u32 val = pll_readl_base(pll);
-        u32 divn = 0, divm = 0, divp = 0;
+        struct tegra_clk_pll_freq_table cfg;
+        struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
+        u32 val;
         u64 rate = parent_rate;
+        int pdiv;
+
+        val = pll_readl_base(pll);
 
-        if (val & PLL_BASE_BYPASS)
+        if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
                 return parent_rate;
 
         if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
@@ -435,16 +551,29 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
                 return pll->fixed_rate;
         }
 
-        divp = (val >> pll->divp_shift) & (divp_mask(pll));
-        if (pll->flags & TEGRA_PLLU)
-                divp ^= 1;
+        _get_pll_mnp(pll, &cfg);
 
-        divn = (val >> pll->divn_shift) & (divn_mask(pll));
-        divm = (val >> pll->divm_shift) & (divm_mask(pll));
-        divm *= (1 << divp);
+        if (p_tohw) {
+                while (p_tohw->pdiv) {
+                        if (cfg.p == p_tohw->hw_val) {
+                                pdiv = p_tohw->pdiv;
+                                break;
+                        }
+                        p_tohw++;
+                }
+
+                if (!p_tohw->pdiv) {
+                        WARN_ON(1);
+                        pdiv = 1;
+                }
+        } else
+                pdiv = 1 << cfg.p;
+
+        cfg.m *= pdiv;
+
+        rate *= cfg.n;
+        do_div(rate, cfg.m);
 
-        rate *= divn;
-        do_div(rate, divm);
         return rate;
 }
 
@@ -538,8 +667,8 @@ static int clk_plle_enable(struct clk_hw *hw)
         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
         pll_writel_base(val, pll);
 
-        clk_pll_wait_for_lock(pll, pll->clk_base + pll->params->misc_reg,
-                              pll->params->lock_bit_idx);
+        clk_pll_wait_for_lock(pll);
+
         return 0;
 }
 
@@ -577,28 +706,531 @@ const struct clk_ops tegra_clk_plle_ops = {
         .enable = clk_plle_enable,
 };
 
-static struct clk *_tegra_clk_register_pll(const char *name,
-                const char *parent_name, void __iomem *clk_base,
-                void __iomem *pmc, unsigned long flags,
-                unsigned long fixed_rate,
-                struct tegra_clk_pll_params *pll_params, u8 pll_flags,
-                struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock,
-                const struct clk_ops *ops)
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+
+static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
+                           unsigned long parent_rate)
+{
+        if (parent_rate > pll_params->cf_max)
+                return 2;
+        else
+                return 1;
+}
+
+static int clk_pll_iddq_enable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+
+        u32 val;
+        int ret;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        val = pll_readl(pll->params->iddq_reg, pll);
+        val &= ~BIT(pll->params->iddq_bit_idx);
+        pll_writel(val, pll->params->iddq_reg, pll);
+        udelay(2);
+
+        _clk_pll_enable(hw);
+
+        ret = clk_pll_wait_for_lock(pll);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return 0;
+}
+
+static void clk_pll_iddq_disable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        u32 val;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _clk_pll_disable(hw);
+
+        val = pll_readl(pll->params->iddq_reg, pll);
+        val |= BIT(pll->params->iddq_bit_idx);
+        pll_writel(val, pll->params->iddq_reg, pll);
+        udelay(2);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+}
+
+static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
+                                struct tegra_clk_pll_freq_table *cfg,
+                                unsigned long rate, unsigned long parent_rate)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned int p;
+
+        if (!rate)
+                return -EINVAL;
+
+        p = DIV_ROUND_UP(pll->params->vco_min, rate);
+        cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
+        cfg->p = p;
+        cfg->output_rate = rate * cfg->p;
+        cfg->n = cfg->output_rate * cfg->m / parent_rate;
+
+        if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
+                return -EINVAL;
+
+        return 0;
+}
+
+static int _pll_ramp_calc_pll(struct clk_hw *hw,
+                              struct tegra_clk_pll_freq_table *cfg,
+                              unsigned long rate, unsigned long parent_rate)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        int err = 0;
+
+        err = _get_table_rate(hw, cfg, rate, parent_rate);
+        if (err < 0)
+                err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
+        else if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
+                        WARN_ON(1);
+                        err = -EINVAL;
+                        goto out;
+        }
+
+        if (!cfg->p || (cfg->p >  pll->params->max_p))
+                err = -EINVAL;
+
+out:
+        return err;
+}
+
+static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        struct tegra_clk_pll_freq_table cfg, old_cfg;
+        unsigned long flags = 0;
+        int ret = 0;
+        u8 old_p;
+
+        ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
+        if (ret < 0)
+                return ret;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _get_pll_mnp(pll, &old_cfg);
+
+        old_p = pllxc_p[old_cfg.p];
+        if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_p != cfg.p) {
+                cfg.p -= 1;
+                ret = _program_pll(hw, &cfg, rate);
+        }
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct tegra_clk_pll_freq_table cfg;
+        int ret = 0;
+        u64 output_rate = *prate;
+
+        ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
+        if (ret < 0)
+                return ret;
+
+        output_rate *= cfg.n;
+        do_div(output_rate, cfg.m * cfg.p);
+
+        return output_rate;
+}
+
+static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct tegra_clk_pll_freq_table cfg;
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        int state, ret = 0;
+        u32 val;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        state = clk_pll_is_enabled(hw);
+        if (state) {
+                if (rate != clk_get_rate(hw->clk)) {
+                        pr_err("%s: Cannot change active PLLM\n", __func__);
+                        ret = -EINVAL;
+                        goto out;
+                }
+                goto out;
+        }
+
+        ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
+        if (ret < 0)
+                goto out;
+
+        cfg.p -= 1;
+
+        val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
+        if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
+                val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
+                val = cfg.p ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) :
+                        (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK);
+                writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
+
+                val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
+                val &= ~(divn_mask(pll) | divm_mask(pll));
+                val |= (cfg.m << pll->divm_shift) | (cfg.n << pll->divn_shift);
+                writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE);
+        } else
+                _update_pll_mnp(pll, &cfg);
+
+
+out:
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static void _pllcx_strobe(struct tegra_clk_pll *pll)
+{
+        u32 val;
+
+        val = pll_readl_misc(pll);
+        val |= PLLCX_MISC_STROBE;
+        pll_writel_misc(val, pll);
+        udelay(2);
+
+        val &= ~PLLCX_MISC_STROBE;
+        pll_writel_misc(val, pll);
+}
+
+static int clk_pllc_enable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        u32 val;
+        int ret = 0;
+        unsigned long flags = 0;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _clk_pll_enable(hw);
+        udelay(2);
+
+        val = pll_readl_misc(pll);
+        val &= ~PLLCX_MISC_RESET;
+        pll_writel_misc(val, pll);
+        udelay(2);
+
+        _pllcx_strobe(pll);
+
+        ret = clk_pll_wait_for_lock(pll);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static void _clk_pllc_disable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        u32 val;
+
+        _clk_pll_disable(hw);
+
+        val = pll_readl_misc(pll);
+        val |= PLLCX_MISC_RESET;
+        pll_writel_misc(val, pll);
+        udelay(2);
+}
+
+static void clk_pllc_disable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _clk_pllc_disable(hw);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+}
+
+static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
+                                        unsigned long input_rate, u32 n)
+{
+        u32 val, n_threshold;
+
+        switch (input_rate) {
+        case 12000000:
+                n_threshold = 70;
+                break;
+        case 13000000:
+        case 26000000:
+                n_threshold = 71;
+                break;
+        case 16800000:
+                n_threshold = 55;
+                break;
+        case 19200000:
+                n_threshold = 48;
+                break;
+        default:
+                pr_err("%s: Unexpected reference rate %lu\n",
+                        __func__, input_rate);
+                return -EINVAL;
+        }
+
+        val = pll_readl_misc(pll);
+        val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
+        val |= n <= n_threshold ?
+                PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
+        pll_writel_misc(val, pll);
+
+        return 0;
+}
+
+static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct tegra_clk_pll_freq_table cfg;
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        int state, ret = 0;
+        u32 val;
+        u16 old_m, old_n;
+        u8 old_p;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
+        if (ret < 0)
+                goto out;
+
+        val = pll_readl_base(pll);
+        old_m = (val >> pll->divm_shift) & (divm_mask(pll));
+        old_n = (val >> pll->divn_shift) & (divn_mask(pll));
+        old_p = pllcx_p[(val >> pll->divp_shift) & (divp_mask(pll))];
+
+        if (cfg.m != old_m) {
+                WARN_ON(1);
+                goto out;
+        }
+
+        if (old_n == cfg.n && old_p == cfg.p)
+                goto out;
+
+        cfg.p -= 1;
+
+        state = clk_pll_is_enabled(hw);
+        if (state)
+                _clk_pllc_disable(hw);
+
+        ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
+        if (ret < 0)
+                goto out;
+
+        _update_pll_mnp(pll, &cfg);
+
+        if (state)
+                ret = clk_pllc_enable(hw);
+
+out:
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static long _pllre_calc_rate(struct tegra_clk_pll *pll,
+                             struct tegra_clk_pll_freq_table *cfg,
+                             unsigned long rate, unsigned long parent_rate)
+{
+        u16 m, n;
+        u64 output_rate = parent_rate;
+
+        m = _pll_fixed_mdiv(pll->params, parent_rate);
+        n = rate * m / parent_rate;
+
+        output_rate *= n;
+        do_div(output_rate, m);
+
+        if (cfg) {
+                cfg->m = m;
+                cfg->n = n;
+        }
+
+        return output_rate;
+}
+static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct tegra_clk_pll_freq_table cfg, old_cfg;
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        int state, ret = 0;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _pllre_calc_rate(pll, &cfg, rate, parent_rate);
+        _get_pll_mnp(pll, &old_cfg);
+        cfg.p = old_cfg.p;
+
+        if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
+                state = clk_pll_is_enabled(hw);
+                if (state)
+                        _clk_pll_disable(hw);
+
+                _update_pll_mnp(pll, &cfg);
+
+                if (state) {
+                        _clk_pll_enable(hw);
+                        ret = clk_pll_wait_for_lock(pll);
+                }
+        }
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+        struct tegra_clk_pll_freq_table cfg;
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        u64 rate = parent_rate;
+
+        _get_pll_mnp(pll, &cfg);
+
+        rate *= cfg.n;
+        do_div(rate, cfg.m);
+
+        return rate;
+}
+
+static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *prate)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+
+        return _pllre_calc_rate(pll, NULL, rate, *prate);
+}
+
+static int clk_plle_tegra114_enable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        struct tegra_clk_pll_freq_table sel;
+        u32 val;
+        int ret;
+        unsigned long flags = 0;
+        unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
+
+        if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate))
+                return -EINVAL;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        val = pll_readl_base(pll);
+        val &= ~BIT(29); /* Disable lock override */
+        pll_writel_base(val, pll);
+
+        val = pll_readl(pll->params->aux_reg, pll);
+        val |= PLLE_AUX_ENABLE_SWCTL;
+        val &= ~PLLE_AUX_SEQ_ENABLE;
+        pll_writel(val, pll->params->aux_reg, pll);
+        udelay(1);
+
+        val = pll_readl_misc(pll);
+        val |= PLLE_MISC_LOCK_ENABLE;
+        val |= PLLE_MISC_IDDQ_SW_CTRL;
+        val &= ~PLLE_MISC_IDDQ_SW_VALUE;
+        val |= PLLE_MISC_PLLE_PTS;
+        val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
+        pll_writel_misc(val, pll);
+        udelay(5);
+
+        val = pll_readl(PLLE_SS_CTRL, pll);
+        val |= PLLE_SS_DISABLE;
+        pll_writel(val, PLLE_SS_CTRL, pll);
+
+        val = pll_readl_base(pll);
+        val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
+        val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT);
+        val |= sel.m << pll->divm_shift;
+        val |= sel.n << pll->divn_shift;
+        val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
+        pll_writel_base(val, pll);
+        udelay(1);
+
+        _clk_pll_enable(hw);
+        ret = clk_pll_wait_for_lock(pll);
+
+        if (ret < 0)
+                goto out;
+
+        /* TODO: enable hw control of xusb brick pll */
+
+out:
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+
+        return ret;
+}
+
+static void clk_plle_tegra114_disable(struct clk_hw *hw)
+{
+        struct tegra_clk_pll *pll = to_clk_pll(hw);
+        unsigned long flags = 0;
+        u32 val;
+
+        if (pll->lock)
+                spin_lock_irqsave(pll->lock, flags);
+
+        _clk_pll_disable(hw);
+
+        val = pll_readl_misc(pll);
+        val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
+        pll_writel_misc(val, pll);
+        udelay(1);
+
+        if (pll->lock)
+                spin_unlock_irqrestore(pll->lock, flags);
+}
+#endif
+
+static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
+                void __iomem *pmc, unsigned long fixed_rate,
+                struct tegra_clk_pll_params *pll_params, u32 pll_flags,
+                struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
 {
         struct tegra_clk_pll *pll;
-        struct clk *clk;
-        struct clk_init_data init;
 
         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
         if (!pll)
                 return ERR_PTR(-ENOMEM);
 
-        init.name = name;
-        init.ops = ops;
-        init.flags = flags;
-        init.parent_names = (parent_name ? &parent_name : NULL);
-        init.num_parents = (parent_name ? 1 : 0);
-
         pll->clk_base = clk_base;
         pll->pmc = pmc;
 
@@ -615,34 +1247,336 @@ static struct clk *_tegra_clk_register_pll(const char *name,
         pll->divm_shift = PLL_BASE_DIVM_SHIFT;
         pll->divm_width = PLL_BASE_DIVM_WIDTH;
 
+        return pll;
+}
+
+static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
+                const char *name, const char *parent_name, unsigned long flags,
+                const struct clk_ops *ops)
+{
+        struct clk_init_data init;
+
+        init.name = name;
+        init.ops = ops;
+        init.flags = flags;
+        init.parent_names = (parent_name ? &parent_name : NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+
         /* Data in .init is copied by clk_register(), so stack variable OK */
         pll->hw.init = &init;
 
-        clk = clk_register(NULL, &pll->hw);
-        if (IS_ERR(clk))
-                kfree(pll);
-
-        return clk;
+        return clk_register(NULL, &pll->hw);
 }
 
 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
                 void __iomem *clk_base, void __iomem *pmc,
                 unsigned long flags, unsigned long fixed_rate,
-                struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+                struct tegra_clk_pll_params *pll_params, u32 pll_flags,
                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
 {
-        return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
-                        flags, fixed_rate, pll_params, pll_flags, freq_table,
-                        lock, &tegra_clk_pll_ops);
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+
+        pll_flags |= TEGRA_PLL_BYPASS;
+        pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_pll_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
 }
 
 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
                 void __iomem *clk_base, void __iomem *pmc,
                 unsigned long flags, unsigned long fixed_rate,
-                struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+                struct tegra_clk_pll_params *pll_params, u32 pll_flags,
                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
 {
-        return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
-                        flags, fixed_rate, pll_params, pll_flags, freq_table,
-                        lock, &tegra_clk_plle_ops);
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+
+        pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
+        pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_plle_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+const struct clk_ops tegra_clk_pllxc_ops = {
+        .is_enabled = clk_pll_is_enabled,
+        .enable = clk_pll_iddq_enable,
+        .disable = clk_pll_iddq_disable,
+        .recalc_rate = clk_pll_recalc_rate,
+        .round_rate = clk_pll_ramp_round_rate,
+        .set_rate = clk_pllxc_set_rate,
+};
+
+const struct clk_ops tegra_clk_pllm_ops = {
+        .is_enabled = clk_pll_is_enabled,
+        .enable = clk_pll_iddq_enable,
+        .disable = clk_pll_iddq_disable,
+        .recalc_rate = clk_pll_recalc_rate,
+        .round_rate = clk_pll_ramp_round_rate,
+        .set_rate = clk_pllm_set_rate,
+};
+
+const struct clk_ops tegra_clk_pllc_ops = {
+        .is_enabled = clk_pll_is_enabled,
+        .enable = clk_pllc_enable,
+        .disable = clk_pllc_disable,
+        .recalc_rate = clk_pll_recalc_rate,
+        .round_rate = clk_pll_ramp_round_rate,
+        .set_rate = clk_pllc_set_rate,
+};
+
+const struct clk_ops tegra_clk_pllre_ops = {
+        .is_enabled = clk_pll_is_enabled,
+        .enable = clk_pll_iddq_enable,
+        .disable = clk_pll_iddq_disable,
+        .recalc_rate = clk_pllre_recalc_rate,
+        .round_rate = clk_pllre_round_rate,
+        .set_rate = clk_pllre_set_rate,
+};
+
+const struct clk_ops tegra_clk_plle_tegra114_ops = {
+        .is_enabled =  clk_pll_is_enabled,
+        .enable = clk_plle_tegra114_enable,
+        .disable = clk_plle_tegra114_disable,
+        .recalc_rate = clk_pll_recalc_rate,
+};
+
+
+struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
+                          void __iomem *clk_base, void __iomem *pmc,
+                          unsigned long flags, unsigned long fixed_rate,
+                          struct tegra_clk_pll_params *pll_params,
+                          u32 pll_flags,
+                          struct tegra_clk_pll_freq_table *freq_table,
+                          spinlock_t *lock)
+{
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+
+        if (!pll_params->pdiv_tohw)
+                return ERR_PTR(-EINVAL);
+
+        pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_pllxc_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
+                          void __iomem *clk_base, void __iomem *pmc,
+                          unsigned long flags, unsigned long fixed_rate,
+                          struct tegra_clk_pll_params *pll_params,
+                          u32 pll_flags,
+                          struct tegra_clk_pll_freq_table *freq_table,
+                          spinlock_t *lock, unsigned long parent_rate)
+{
+        u32 val;
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+
+        pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        /* program minimum rate by default */
+
+        val = pll_readl_base(pll);
+        if (val & PLL_BASE_ENABLE)
+                WARN_ON(val & pll_params->iddq_bit_idx);
+        else {
+                int m;
+
+                m = _pll_fixed_mdiv(pll_params, parent_rate);
+                val = m << PLL_BASE_DIVM_SHIFT;
+                val |= (pll_params->vco_min / parent_rate)
+                                << PLL_BASE_DIVN_SHIFT;
+                pll_writel_base(val, pll);
+        }
+
+        /* disable lock override */
+
+        val = pll_readl_misc(pll);
+        val &= ~BIT(29);
+        pll_writel_misc(val, pll);
+
+        pll_flags |= TEGRA_PLL_LOCK_MISC;
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_pllre_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
+                          void __iomem *clk_base, void __iomem *pmc,
+                          unsigned long flags, unsigned long fixed_rate,
+                          struct tegra_clk_pll_params *pll_params,
+                          u32 pll_flags,
+                          struct tegra_clk_pll_freq_table *freq_table,
+                          spinlock_t *lock)
+{
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+
+        if (!pll_params->pdiv_tohw)
+                return ERR_PTR(-EINVAL);
+
+        pll_flags |= TEGRA_PLL_BYPASS;
+        pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_pllm_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
+                          void __iomem *clk_base, void __iomem *pmc,
+                          unsigned long flags, unsigned long fixed_rate,
+                          struct tegra_clk_pll_params *pll_params,
+                          u32 pll_flags,
+                          struct tegra_clk_pll_freq_table *freq_table,
+                          spinlock_t *lock)
+{
+        struct clk *parent, *clk;
+        struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
+        struct tegra_clk_pll *pll;
+        struct tegra_clk_pll_freq_table cfg;
+        unsigned long parent_rate;
+
+        if (!p_tohw)
+                return ERR_PTR(-EINVAL);
+
+        parent = __clk_lookup(parent_name);
+        if (IS_ERR(parent)) {
+                WARN(1, "parent clk %s of %s must be registered first\n",
+                        name, parent_name);
+                return ERR_PTR(-EINVAL);
+        }
+
+        pll_flags |= TEGRA_PLL_BYPASS;
+        pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags,
+                              freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        parent_rate = __clk_get_rate(parent);
+
+        /*
+         * Most of PLLC register fields are shadowed, and can not be read
+         * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
+         * Initialize PLL to default state: disabled, reset; shadow registers
+         * loaded with default parameters; dividers are preset for half of
+         * minimum VCO rate (the latter assured that shadowed divider settings
+         * are within supported range).
+         */
+
+        cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
+        cfg.n = cfg.m * pll_params->vco_min / parent_rate;
+
+        while (p_tohw->pdiv) {
+                if (p_tohw->pdiv == 2) {
+                        cfg.p = p_tohw->hw_val;
+                        break;
+                }
+                p_tohw++;
+        }
+
+        if (!p_tohw->pdiv) {
+                WARN_ON(1);
+                return ERR_PTR(-EINVAL);
+        }
+
+        pll_writel_base(0, pll);
+        _update_pll_mnp(pll, &cfg);
+
+        pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
+        pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
+        pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
+        pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
+
+        _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_pllc_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+struct clk *tegra_clk_register_plle_tegra114(const char *name,
+                                const char *parent_name,
+                                void __iomem *clk_base, unsigned long flags,
+                                unsigned long fixed_rate,
+                                struct tegra_clk_pll_params *pll_params,
+                                struct tegra_clk_pll_freq_table *freq_table,
+                                spinlock_t *lock)
+{
+        struct tegra_clk_pll *pll;
+        struct clk *clk;
+        u32 val, val_aux;
+
+        pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params,
+                              TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock);
+        if (IS_ERR(pll))
+                return ERR_CAST(pll);
+
+        /* ensure parent is set to pll_re_vco */
+
+        val = pll_readl_base(pll);
+        val_aux = pll_readl(pll_params->aux_reg, pll);
+
+        if (val & PLL_BASE_ENABLE) {
+                if (!(val_aux & PLLE_AUX_PLLRE_SEL))
+                        WARN(1, "pll_e enabled with unsupported parent %s\n",
+                          (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref");
+        } else {
+                val_aux |= PLLE_AUX_PLLRE_SEL;
+                pll_writel(val, pll_params->aux_reg, pll);
+        }
+
+        clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
+                                      &tegra_clk_plle_tegra114_ops);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
 }
+#endif
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
new file mode 100644
index 000000000000..d78e16ee161c
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -0,0 +1,2085 @@
+/*
+ * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/delay.h>
+#include <linux/clk/tegra.h>
+
+#include "clk.h"
+
+#define RST_DEVICES_L                   0x004
+#define RST_DEVICES_H                   0x008
+#define RST_DEVICES_U                   0x00C
+#define RST_DEVICES_V                   0x358
+#define RST_DEVICES_W                   0x35C
+#define RST_DEVICES_X                   0x28C
+#define RST_DEVICES_SET_L               0x300
+#define RST_DEVICES_CLR_L               0x304
+#define RST_DEVICES_SET_H               0x308
+#define RST_DEVICES_CLR_H               0x30c
+#define RST_DEVICES_SET_U               0x310
+#define RST_DEVICES_CLR_U               0x314
+#define RST_DEVICES_SET_V               0x430
+#define RST_DEVICES_CLR_V               0x434
+#define RST_DEVICES_SET_W               0x438
+#define RST_DEVICES_CLR_W               0x43c
+#define RST_DEVICES_NUM                 5
+
+#define CLK_OUT_ENB_L                   0x010
+#define CLK_OUT_ENB_H                   0x014
+#define CLK_OUT_ENB_U                   0x018
+#define CLK_OUT_ENB_V                   0x360
+#define CLK_OUT_ENB_W                   0x364
+#define CLK_OUT_ENB_X                   0x280
+#define CLK_OUT_ENB_SET_L               0x320
+#define CLK_OUT_ENB_CLR_L               0x324
+#define CLK_OUT_ENB_SET_H               0x328
+#define CLK_OUT_ENB_CLR_H               0x32c
+#define CLK_OUT_ENB_SET_U               0x330
+#define CLK_OUT_ENB_CLR_U               0x334
+#define CLK_OUT_ENB_SET_V               0x440
+#define CLK_OUT_ENB_CLR_V               0x444
+#define CLK_OUT_ENB_SET_W               0x448
+#define CLK_OUT_ENB_CLR_W               0x44c
+#define CLK_OUT_ENB_SET_X               0x284
+#define CLK_OUT_ENB_CLR_X               0x288
+#define CLK_OUT_ENB_NUM                 6
+
+#define PLLC_BASE 0x80
+#define PLLC_MISC2 0x88
+#define PLLC_MISC 0x8c
+#define PLLC2_BASE 0x4e8
+#define PLLC2_MISC 0x4ec
+#define PLLC3_BASE 0x4fc
+#define PLLC3_MISC 0x500
+#define PLLM_BASE 0x90
+#define PLLM_MISC 0x9c
+#define PLLP_BASE 0xa0
+#define PLLP_MISC 0xac
+#define PLLX_BASE 0xe0
+#define PLLX_MISC 0xe4
+#define PLLX_MISC2 0x514
+#define PLLX_MISC3 0x518
+#define PLLD_BASE 0xd0
+#define PLLD_MISC 0xdc
+#define PLLD2_BASE 0x4b8
+#define PLLD2_MISC 0x4bc
+#define PLLE_BASE 0xe8
+#define PLLE_MISC 0xec
+#define PLLA_BASE 0xb0
+#define PLLA_MISC 0xbc
+#define PLLU_BASE 0xc0
+#define PLLU_MISC 0xcc
+#define PLLRE_BASE 0x4c4
+#define PLLRE_MISC 0x4c8
+
+#define PLL_MISC_LOCK_ENABLE 18
+#define PLLC_MISC_LOCK_ENABLE 24
+#define PLLDU_MISC_LOCK_ENABLE 22
+#define PLLE_MISC_LOCK_ENABLE 9
+#define PLLRE_MISC_LOCK_ENABLE 30
+
+#define PLLC_IDDQ_BIT 26
+#define PLLX_IDDQ_BIT 3
+#define PLLRE_IDDQ_BIT 16
+
+#define PLL_BASE_LOCK BIT(27)
+#define PLLE_MISC_LOCK BIT(11)
+#define PLLRE_MISC_LOCK BIT(24)
+#define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
+
+#define PLLE_AUX 0x48c
+#define PLLC_OUT 0x84
+#define PLLM_OUT 0x94
+#define PLLP_OUTA 0xa4
+#define PLLP_OUTB 0xa8
+#define PLLA_OUT 0xb4
+
+#define AUDIO_SYNC_CLK_I2S0 0x4a0
+#define AUDIO_SYNC_CLK_I2S1 0x4a4
+#define AUDIO_SYNC_CLK_I2S2 0x4a8
+#define AUDIO_SYNC_CLK_I2S3 0x4ac
+#define AUDIO_SYNC_CLK_I2S4 0x4b0
+#define AUDIO_SYNC_CLK_SPDIF 0x4b4
+
+#define AUDIO_SYNC_DOUBLER 0x49c
+
+#define PMC_CLK_OUT_CNTRL 0x1a8
+#define PMC_DPD_PADS_ORIDE 0x1c
+#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
+#define PMC_CTRL 0
+#define PMC_CTRL_BLINK_ENB 7
+
+#define OSC_CTRL                        0x50
+#define OSC_CTRL_OSC_FREQ_SHIFT         28
+#define OSC_CTRL_PLL_REF_DIV_SHIFT      26
+
+#define PLLXC_SW_MAX_P                  6
+
+#define CCLKG_BURST_POLICY 0x368
+#define CCLKLP_BURST_POLICY 0x370
+#define SCLK_BURST_POLICY 0x028
+#define SYSTEM_CLK_RATE 0x030
+
+#define UTMIP_PLL_CFG2 0x488
+#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
+#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
+
+#define UTMIP_PLL_CFG1 0x484
+#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
+#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
+
+#define UTMIPLL_HW_PWRDN_CFG0                   0x52c
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE   BIT(25)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE        BIT(24)
+#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET       BIT(6)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE     BIT(5)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL      BIT(4)
+#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL  BIT(2)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE     BIT(1)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL        BIT(0)
+
+#define CLK_SOURCE_I2S0 0x1d8
+#define CLK_SOURCE_I2S1 0x100
+#define CLK_SOURCE_I2S2 0x104
+#define CLK_SOURCE_NDFLASH 0x160
+#define CLK_SOURCE_I2S3 0x3bc
+#define CLK_SOURCE_I2S4 0x3c0
+#define CLK_SOURCE_SPDIF_OUT 0x108
+#define CLK_SOURCE_SPDIF_IN 0x10c
+#define CLK_SOURCE_PWM 0x110
+#define CLK_SOURCE_ADX 0x638
+#define CLK_SOURCE_AMX 0x63c
+#define CLK_SOURCE_HDA 0x428
+#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
+#define CLK_SOURCE_SBC1 0x134
+#define CLK_SOURCE_SBC2 0x118
+#define CLK_SOURCE_SBC3 0x11c
+#define CLK_SOURCE_SBC4 0x1b4
+#define CLK_SOURCE_SBC5 0x3c8
+#define CLK_SOURCE_SBC6 0x3cc
+#define CLK_SOURCE_SATA_OOB 0x420
+#define CLK_SOURCE_SATA 0x424
+#define CLK_SOURCE_NDSPEED 0x3f8
+#define CLK_SOURCE_VFIR 0x168
+#define CLK_SOURCE_SDMMC1 0x150
+#define CLK_SOURCE_SDMMC2 0x154
+#define CLK_SOURCE_SDMMC3 0x1bc
+#define CLK_SOURCE_SDMMC4 0x164
+#define CLK_SOURCE_VDE 0x1c8
+#define CLK_SOURCE_CSITE 0x1d4
+#define CLK_SOURCE_LA 0x1f8
+#define CLK_SOURCE_TRACE 0x634
+#define CLK_SOURCE_OWR 0x1cc
+#define CLK_SOURCE_NOR 0x1d0
+#define CLK_SOURCE_MIPI 0x174
+#define CLK_SOURCE_I2C1 0x124
+#define CLK_SOURCE_I2C2 0x198
+#define CLK_SOURCE_I2C3 0x1b8
+#define CLK_SOURCE_I2C4 0x3c4
+#define CLK_SOURCE_I2C5 0x128
+#define CLK_SOURCE_UARTA 0x178
+#define CLK_SOURCE_UARTB 0x17c
+#define CLK_SOURCE_UARTC 0x1a0
+#define CLK_SOURCE_UARTD 0x1c0
+#define CLK_SOURCE_UARTE 0x1c4
+#define CLK_SOURCE_UARTA_DBG 0x178
+#define CLK_SOURCE_UARTB_DBG 0x17c
+#define CLK_SOURCE_UARTC_DBG 0x1a0
+#define CLK_SOURCE_UARTD_DBG 0x1c0
+#define CLK_SOURCE_UARTE_DBG 0x1c4
+#define CLK_SOURCE_3D 0x158
+#define CLK_SOURCE_2D 0x15c
+#define CLK_SOURCE_VI_SENSOR 0x1a8
+#define CLK_SOURCE_VI 0x148
+#define CLK_SOURCE_EPP 0x16c
+#define CLK_SOURCE_MSENC 0x1f0
+#define CLK_SOURCE_TSEC 0x1f4
+#define CLK_SOURCE_HOST1X 0x180
+#define CLK_SOURCE_HDMI 0x18c
+#define CLK_SOURCE_DISP1 0x138
+#define CLK_SOURCE_DISP2 0x13c
+#define CLK_SOURCE_CILAB 0x614
+#define CLK_SOURCE_CILCD 0x618
+#define CLK_SOURCE_CILE 0x61c
+#define CLK_SOURCE_DSIALP 0x620
+#define CLK_SOURCE_DSIBLP 0x624
+#define CLK_SOURCE_TSENSOR 0x3b8
+#define CLK_SOURCE_D_AUDIO 0x3d0
+#define CLK_SOURCE_DAM0 0x3d8
+#define CLK_SOURCE_DAM1 0x3dc
+#define CLK_SOURCE_DAM2 0x3e0
+#define CLK_SOURCE_ACTMON 0x3e8
+#define CLK_SOURCE_EXTERN1 0x3ec
+#define CLK_SOURCE_EXTERN2 0x3f0
+#define CLK_SOURCE_EXTERN3 0x3f4
+#define CLK_SOURCE_I2CSLOW 0x3fc
+#define CLK_SOURCE_SE 0x42c
+#define CLK_SOURCE_MSELECT 0x3b4
+#define CLK_SOURCE_SOC_THERM 0x644
+#define CLK_SOURCE_XUSB_HOST_SRC 0x600
+#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
+#define CLK_SOURCE_XUSB_FS_SRC 0x608
+#define CLK_SOURCE_XUSB_SS_SRC 0x610
+#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
+#define CLK_SOURCE_EMC 0x19c
+
+static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
+
+static void __iomem *clk_base;
+static void __iomem *pmc_base;
+
+static DEFINE_SPINLOCK(pll_d_lock);
+static DEFINE_SPINLOCK(pll_d2_lock);
+static DEFINE_SPINLOCK(pll_u_lock);
+static DEFINE_SPINLOCK(pll_div_lock);
+static DEFINE_SPINLOCK(pll_re_lock);
+static DEFINE_SPINLOCK(clk_doubler_lock);
+static DEFINE_SPINLOCK(clk_out_lock);
+static DEFINE_SPINLOCK(sysrate_lock);
+
+static struct pdiv_map pllxc_p[] = {
+        { .pdiv = 1, .hw_val = 0 },
+        { .pdiv = 2, .hw_val = 1 },
+        { .pdiv = 3, .hw_val = 2 },
+        { .pdiv = 4, .hw_val = 3 },
+        { .pdiv = 5, .hw_val = 4 },
+        { .pdiv = 6, .hw_val = 5 },
+        { .pdiv = 8, .hw_val = 6 },
+        { .pdiv = 10, .hw_val = 7 },
+        { .pdiv = 12, .hw_val = 8 },
+        { .pdiv = 16, .hw_val = 9 },
+        { .pdiv = 12, .hw_val = 10 },
+        { .pdiv = 16, .hw_val = 11 },
+        { .pdiv = 20, .hw_val = 12 },
+        { .pdiv = 24, .hw_val = 13 },
+        { .pdiv = 32, .hw_val = 14 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
+static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
+        { 12000000, 624000000, 104, 0, 2},
+        { 12000000, 600000000, 100, 0, 2},
+        { 13000000, 600000000,  92, 0, 2},      /* actual: 598.0 MHz */
+        { 16800000, 600000000,  71, 0, 2},      /* actual: 596.4 MHz */
+        { 19200000, 600000000,  62, 0, 2},      /* actual: 595.2 MHz */
+        { 26000000, 600000000,  92, 1, 2},      /* actual: 598.0 MHz */
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct tegra_clk_pll_params pll_c_params = {
+        .input_min = 12000000,
+        .input_max = 800000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
+        .vco_min = 600000000,
+        .vco_max = 1400000000,
+        .base_reg = PLLC_BASE,
+        .misc_reg = PLLC_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .iddq_reg = PLLC_MISC,
+        .iddq_bit_idx = PLLC_IDDQ_BIT,
+        .max_p = PLLXC_SW_MAX_P,
+        .dyn_ramp_reg = PLLC_MISC2,
+        .stepa_shift = 17,
+        .stepb_shift = 9,
+        .pdiv_tohw = pllxc_p,
+};
+
+static struct pdiv_map pllc_p[] = {
+        { .pdiv = 1, .hw_val = 0 },
+        { .pdiv = 2, .hw_val = 1 },
+        { .pdiv = 4, .hw_val = 3 },
+        { .pdiv = 8, .hw_val = 5 },
+        { .pdiv = 16, .hw_val = 7 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
+static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
+        {12000000, 600000000, 100, 0, 2},
+        {13000000, 600000000, 92, 0, 2},        /* actual: 598.0 MHz */
+        {16800000, 600000000, 71, 0, 2},        /* actual: 596.4 MHz */
+        {19200000, 600000000, 62, 0, 2},        /* actual: 595.2 MHz */
+        {26000000, 600000000, 92, 1, 2},        /* actual: 598.0 MHz */
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_c2_params = {
+        .input_min = 12000000,
+        .input_max = 48000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000,
+        .vco_min = 600000000,
+        .vco_max = 1200000000,
+        .base_reg = PLLC2_BASE,
+        .misc_reg = PLLC2_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .pdiv_tohw = pllc_p,
+        .ext_misc_reg[0] = 0x4f0,
+        .ext_misc_reg[1] = 0x4f4,
+        .ext_misc_reg[2] = 0x4f8,
+};
+
+static struct tegra_clk_pll_params pll_c3_params = {
+        .input_min = 12000000,
+        .input_max = 48000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000,
+        .vco_min = 600000000,
+        .vco_max = 1200000000,
+        .base_reg = PLLC3_BASE,
+        .misc_reg = PLLC3_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .pdiv_tohw = pllc_p,
+        .ext_misc_reg[0] = 0x504,
+        .ext_misc_reg[1] = 0x508,
+        .ext_misc_reg[2] = 0x50c,
+};
+
+static struct pdiv_map pllm_p[] = {
+        { .pdiv = 1, .hw_val = 0 },
+        { .pdiv = 2, .hw_val = 1 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
+static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
+        {12000000, 800000000, 66, 0, 1},        /* actual: 792.0 MHz */
+        {13000000, 800000000, 61, 0, 1},        /* actual: 793.0 MHz */
+        {16800000, 800000000, 47, 0, 1},        /* actual: 789.6 MHz */
+        {19200000, 800000000, 41, 0, 1},        /* actual: 787.2 MHz */
+        {26000000, 800000000, 61, 1, 1},        /* actual: 793.0 MHz */
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_m_params = {
+        .input_min = 12000000,
+        .input_max = 500000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
+        .vco_min = 400000000,
+        .vco_max = 1066000000,
+        .base_reg = PLLM_BASE,
+        .misc_reg = PLLM_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .max_p = 2,
+        .pdiv_tohw = pllm_p,
+};
+
+static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
+        {12000000, 216000000, 432, 12, 1, 8},
+        {13000000, 216000000, 432, 13, 1, 8},
+        {16800000, 216000000, 360, 14, 1, 8},
+        {19200000, 216000000, 360, 16, 1, 8},
+        {26000000, 216000000, 432, 26, 1, 8},
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_p_params = {
+        .input_min = 2000000,
+        .input_max = 31000000,
+        .cf_min = 1000000,
+        .cf_max = 6000000,
+        .vco_min = 200000000,
+        .vco_max = 700000000,
+        .base_reg = PLLP_BASE,
+        .misc_reg = PLLP_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+};
+
+static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
+        {9600000, 282240000, 147, 5, 0, 4},
+        {9600000, 368640000, 192, 5, 0, 4},
+        {9600000, 240000000, 200, 8, 0, 8},
+
+        {28800000, 282240000, 245, 25, 0, 8},
+        {28800000, 368640000, 320, 25, 0, 8},
+        {28800000, 240000000, 200, 24, 0, 8},
+        {0, 0, 0, 0, 0, 0},
+};
+
+
+static struct tegra_clk_pll_params pll_a_params = {
+        .input_min = 2000000,
+        .input_max = 31000000,
+        .cf_min = 1000000,
+        .cf_max = 6000000,
+        .vco_min = 200000000,
+        .vco_max = 700000000,
+        .base_reg = PLLA_BASE,
+        .misc_reg = PLLA_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+};
+
+static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
+        {12000000, 216000000, 864, 12, 2, 12},
+        {13000000, 216000000, 864, 13, 2, 12},
+        {16800000, 216000000, 720, 14, 2, 12},
+        {19200000, 216000000, 720, 16, 2, 12},
+        {26000000, 216000000, 864, 26, 2, 12},
+
+        {12000000, 594000000, 594, 12, 0, 12},
+        {13000000, 594000000, 594, 13, 0, 12},
+        {16800000, 594000000, 495, 14, 0, 12},
+        {19200000, 594000000, 495, 16, 0, 12},
+        {26000000, 594000000, 594, 26, 0, 12},
+
+        {12000000, 1000000000, 1000, 12, 0, 12},
+        {13000000, 1000000000, 1000, 13, 0, 12},
+        {19200000, 1000000000, 625, 12, 0, 12},
+        {26000000, 1000000000, 1000, 26, 0, 12},
+
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_d_params = {
+        .input_min = 2000000,
+        .input_max = 40000000,
+        .cf_min = 1000000,
+        .cf_max = 6000000,
+        .vco_min = 500000000,
+        .vco_max = 1000000000,
+        .base_reg = PLLD_BASE,
+        .misc_reg = PLLD_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
+        .lock_delay = 1000,
+};
+
+static struct tegra_clk_pll_params pll_d2_params = {
+        .input_min = 2000000,
+        .input_max = 40000000,
+        .cf_min = 1000000,
+        .cf_max = 6000000,
+        .vco_min = 500000000,
+        .vco_max = 1000000000,
+        .base_reg = PLLD2_BASE,
+        .misc_reg = PLLD2_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
+        .lock_delay = 1000,
+};
+
+static struct pdiv_map pllu_p[] = {
+        { .pdiv = 1, .hw_val = 1 },
+        { .pdiv = 2, .hw_val = 0 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
+static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
+        {12000000, 480000000, 960, 12, 0, 12},
+        {13000000, 480000000, 960, 13, 0, 12},
+        {16800000, 480000000, 400, 7, 0, 5},
+        {19200000, 480000000, 200, 4, 0, 3},
+        {26000000, 480000000, 960, 26, 0, 12},
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_u_params = {
+        .input_min = 2000000,
+        .input_max = 40000000,
+        .cf_min = 1000000,
+        .cf_max = 6000000,
+        .vco_min = 480000000,
+        .vco_max = 960000000,
+        .base_reg = PLLU_BASE,
+        .misc_reg = PLLU_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
+        .lock_delay = 1000,
+        .pdiv_tohw = pllu_p,
+};
+
+static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
+        /* 1 GHz */
+        {12000000, 1000000000, 83, 0, 1},       /* actual: 996.0 MHz */
+        {13000000, 1000000000, 76, 0, 1},       /* actual: 988.0 MHz */
+        {16800000, 1000000000, 59, 0, 1},       /* actual: 991.2 MHz */
+        {19200000, 1000000000, 52, 0, 1},       /* actual: 998.4 MHz */
+        {26000000, 1000000000, 76, 1, 1},       /* actual: 988.0 MHz */
+
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_x_params = {
+        .input_min = 12000000,
+        .input_max = 800000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000,     /* s/w policy, h/w capability 50 MHz */
+        .vco_min = 700000000,
+        .vco_max = 2400000000U,
+        .base_reg = PLLX_BASE,
+        .misc_reg = PLLX_MISC,
+        .lock_mask = PLL_BASE_LOCK,
+        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .iddq_reg = PLLX_MISC3,
+        .iddq_bit_idx = PLLX_IDDQ_BIT,
+        .max_p = PLLXC_SW_MAX_P,
+        .dyn_ramp_reg = PLLX_MISC2,
+        .stepa_shift = 16,
+        .stepb_shift = 24,
+        .pdiv_tohw = pllxc_p,
+};
+
+static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
+        /* PLLE special case: use cpcon field to store cml divider value */
+        {336000000, 100000000, 100, 21, 16, 11},
+        {312000000, 100000000, 200, 26, 24, 13},
+        {0, 0, 0, 0, 0, 0},
+};
+
+static struct tegra_clk_pll_params pll_e_params = {
+        .input_min = 12000000,
+        .input_max = 1000000000,
+        .cf_min = 12000000,
+        .cf_max = 75000000,
+        .vco_min = 1600000000,
+        .vco_max = 2400000000U,
+        .base_reg = PLLE_BASE,
+        .misc_reg = PLLE_MISC,
+        .aux_reg = PLLE_AUX,
+        .lock_mask = PLLE_MISC_LOCK,
+        .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+};
+
+static struct tegra_clk_pll_params pll_re_vco_params = {
+        .input_min = 12000000,
+        .input_max = 1000000000,
+        .cf_min = 12000000,
+        .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
+        .vco_min = 300000000,
+        .vco_max = 600000000,
+        .base_reg = PLLRE_BASE,
+        .misc_reg = PLLRE_MISC,
+        .lock_mask = PLLRE_MISC_LOCK,
+        .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
+        .lock_delay = 300,
+        .iddq_reg = PLLRE_MISC,
+        .iddq_bit_idx = PLLRE_IDDQ_BIT,
+};
+
+/* Peripheral clock registers */
+
+static struct tegra_clk_periph_regs periph_l_regs = {
+        .enb_reg = CLK_OUT_ENB_L,
+        .enb_set_reg = CLK_OUT_ENB_SET_L,
+        .enb_clr_reg = CLK_OUT_ENB_CLR_L,
+        .rst_reg = RST_DEVICES_L,
+        .rst_set_reg = RST_DEVICES_SET_L,
+        .rst_clr_reg = RST_DEVICES_CLR_L,
+};
+
+static struct tegra_clk_periph_regs periph_h_regs = {
+        .enb_reg = CLK_OUT_ENB_H,
+        .enb_set_reg = CLK_OUT_ENB_SET_H,
+        .enb_clr_reg = CLK_OUT_ENB_CLR_H,
+        .rst_reg = RST_DEVICES_H,
+        .rst_set_reg = RST_DEVICES_SET_H,
+        .rst_clr_reg = RST_DEVICES_CLR_H,
+};
+
+static struct tegra_clk_periph_regs periph_u_regs = {
+        .enb_reg = CLK_OUT_ENB_U,
+        .enb_set_reg = CLK_OUT_ENB_SET_U,
+        .enb_clr_reg = CLK_OUT_ENB_CLR_U,
+        .rst_reg = RST_DEVICES_U,
+        .rst_set_reg = RST_DEVICES_SET_U,
+        .rst_clr_reg = RST_DEVICES_CLR_U,
+};
+
+static struct tegra_clk_periph_regs periph_v_regs = {
+        .enb_reg = CLK_OUT_ENB_V,
+        .enb_set_reg = CLK_OUT_ENB_SET_V,
+        .enb_clr_reg = CLK_OUT_ENB_CLR_V,
+        .rst_reg = RST_DEVICES_V,
+        .rst_set_reg = RST_DEVICES_SET_V,
+        .rst_clr_reg = RST_DEVICES_CLR_V,
+};
+
+static struct tegra_clk_periph_regs periph_w_regs = {
+        .enb_reg = CLK_OUT_ENB_W,
+        .enb_set_reg = CLK_OUT_ENB_SET_W,
+        .enb_clr_reg = CLK_OUT_ENB_CLR_W,
+        .rst_reg = RST_DEVICES_W,
+        .rst_set_reg = RST_DEVICES_SET_W,
+        .rst_clr_reg = RST_DEVICES_CLR_W,
+};
+
+/* possible OSC frequencies in Hz */
+static unsigned long tegra114_input_freq[] = {
+        [0] = 13000000,
+        [1] = 16800000,
+        [4] = 19200000,
+        [5] = 38400000,
+        [8] = 12000000,
+        [9] = 48000000,
+        [12] = 260000000,
+};
+
+#define MASK(x) (BIT(x) - 1)
+
+#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
+                            _clk_num, _regs, _gate_flags, _clk_id)      \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num,    \
+                        periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
+                        _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
+                            _clk_num, _regs, _gate_flags, _clk_id, flags)\
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num,    \
+                        periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
+                        _parents##_idx, flags)
+
+#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
+                             _clk_num, _regs, _gate_flags, _clk_id)     \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num,    \
+                        periph_clk_enb_refcnt, _gate_flags, _clk_id,    \
+                        _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
+                            _clk_num, _regs, _gate_flags, _clk_id)      \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
+                        _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
+                        _clk_id, _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
+                            _clk_num, _regs, _gate_flags, _clk_id, flags)\
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
+                        _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
+                        _clk_id, _parents##_idx, flags)
+
+#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
+                            _clk_num, _regs, _gate_flags, _clk_id)      \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
+                        _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
+                        _clk_id, _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
+                             _clk_num, _regs, _clk_id)                  \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\
+                        _clk_num, periph_clk_enb_refcnt, 0, _clk_id,    \
+                        _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
+                             _clk_num, _regs, _clk_id)                  \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num,   \
+                        periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
+                              _mux_shift, _mux_mask, _clk_num, _regs,   \
+                              _gate_flags, _clk_id)                     \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
+                        _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs,    \
+                        _clk_num, periph_clk_enb_refcnt, _gate_flags,   \
+                        _clk_id, _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
+                             _clk_num, _regs, _gate_flags, _clk_id)      \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
+                        29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
+                        _clk_num, periph_clk_enb_refcnt, _gate_flags,    \
+                        _clk_id, _parents##_idx, 0)
+
+#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset,  _clk_num,\
+                                 _regs, _gate_flags, _clk_id)           \
+        TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
+                        _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \
+                        periph_clk_enb_refcnt, _gate_flags , _clk_id,   \
+                        mux_d_audio_clk_idx, 0)
+
+enum tegra114_clk {
+        rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
+        ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19,
+        gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27,
+        host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40,
+        sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48,
+        mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56,
+        emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65,
+        i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73,
+        la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80,
+        i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91,
+        csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102,
+        i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1,
+        dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x,
+        audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120,
+        extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128,
+        cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148,
+        dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192,
+        vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k,
+        clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2,
+        pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3,
+        pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0,
+        pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0,
+        pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync,
+        i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0,
+        audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
+        blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
+        xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
+
+        /* Mux clocks */
+
+        audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux,
+        spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux,
+        dsib_mux, clk_max,
+};
+
+struct utmi_clk_param {
+        /* Oscillator Frequency in KHz */
+        u32 osc_frequency;
+        /* UTMIP PLL Enable Delay Count  */
+        u8 enable_delay_count;
+        /* UTMIP PLL Stable count */
+        u8 stable_count;
+        /*  UTMIP PLL Active delay count */
+        u8 active_delay_count;
+        /* UTMIP PLL Xtal frequency count */
+        u8 xtal_freq_count;
+};
+
+static const struct utmi_clk_param utmi_parameters[] = {
+        {.osc_frequency = 13000000, .enable_delay_count = 0x02,
+         .stable_count = 0x33, .active_delay_count = 0x05,
+         .xtal_freq_count = 0x7F},
+        {.osc_frequency = 19200000, .enable_delay_count = 0x03,
+         .stable_count = 0x4B, .active_delay_count = 0x06,
+         .xtal_freq_count = 0xBB},
+        {.osc_frequency = 12000000, .enable_delay_count = 0x02,
+         .stable_count = 0x2F, .active_delay_count = 0x04,
+         .xtal_freq_count = 0x76},
+        {.osc_frequency = 26000000, .enable_delay_count = 0x04,
+         .stable_count = 0x66, .active_delay_count = 0x09,
+         .xtal_freq_count = 0xFE},
+        {.osc_frequency = 16800000, .enable_delay_count = 0x03,
+         .stable_count = 0x41, .active_delay_count = 0x0A,
+         .xtal_freq_count = 0xA4},
+};
+
+/* peripheral mux definitions */
+
+#define MUX_I2S_SPDIF(_id)                                              \
+static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
+                                                           #_id, "pll_p",\
+                                                           "clk_m"};
+MUX_I2S_SPDIF(audio0)
+MUX_I2S_SPDIF(audio1)
+MUX_I2S_SPDIF(audio2)
+MUX_I2S_SPDIF(audio3)
+MUX_I2S_SPDIF(audio4)
+MUX_I2S_SPDIF(audio)
+
+#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
+#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
+#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
+#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
+#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
+#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
+
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+        "pll_p", "pll_c", "pll_m", "clk_m"
+};
+#define mux_pllp_pllc_pllm_clkm_idx NULL
+
+static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
+#define mux_pllp_pllc_pllm_idx NULL
+
+static const char *mux_pllp_pllc_clk32_clkm[] = {
+        "pll_p", "pll_c", "clk_32k", "clk_m"
+};
+#define mux_pllp_pllc_clk32_clkm_idx NULL
+
+static const char *mux_plla_pllc_pllp_clkm[] = {
+        "pll_a_out0", "pll_c", "pll_p", "clk_m"
+};
+#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
+
+static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
+        "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
+};
+static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
+        [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
+};
+
+static const char *mux_pllp_clkm[] = {
+        "pll_p", "clk_m"
+};
+static u32 mux_pllp_clkm_idx[] = {
+        [0] = 0, [1] = 3,
+};
+
+static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
+        "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
+};
+#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
+
+static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+        "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
+        "pll_d2_out0", "clk_m"
+};
+#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
+
+static const char *mux_pllm_pllc_pllp_plla[] = {
+        "pll_m", "pll_c", "pll_p", "pll_a_out0"
+};
+#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
+
+static const char *mux_pllp_pllc_clkm[] = {
+        "pll_p", "pll_c", "pll_m"
+};
+static u32 mux_pllp_pllc_clkm_idx[] = {
+        [0] = 0, [1] = 1, [2] = 3,
+};
+
+static const char *mux_pllp_pllc_clkm_clk32[] = {
+        "pll_p", "pll_c", "clk_m", "clk_32k"
+};
+#define mux_pllp_pllc_clkm_clk32_idx NULL
+
+static const char *mux_plla_clk32_pllp_clkm_plle[] = {
+        "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
+};
+#define mux_plla_clk32_pllp_clkm_plle_idx NULL
+
+static const char *mux_clkm_pllp_pllc_pllre[] = {
+        "clk_m", "pll_p", "pll_c", "pll_re_out"
+};
+static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
+        [0] = 0, [1] = 1, [2] = 3, [3] = 5,
+};
+
+static const char *mux_clkm_48M_pllp_480M[] = {
+        "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
+};
+#define mux_clkm_48M_pllp_480M_idx NULL
+
+static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
+        "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
+};
+static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
+        [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
+};
+
+static const char *mux_plld_out0_plld2_out0[] = {
+        "pll_d_out0", "pll_d2_out0",
+};
+#define mux_plld_out0_plld2_out0_idx NULL
+
+static const char *mux_d_audio_clk[] = {
+        "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
+        "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
+};
+static u32 mux_d_audio_clk_idx[] = {
+        [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
+        [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
+};
+
+static const char *mux_pllmcp_clkm[] = {
+        "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
+};
+
+static const struct clk_div_table pll_re_div_table[] = {
+        { .val = 0, .div = 1 },
+        { .val = 1, .div = 2 },
+        { .val = 2, .div = 3 },
+        { .val = 3, .div = 4 },
+        { .val = 4, .div = 5 },
+        { .val = 5, .div = 6 },
+        { .val = 0, .div = 0 },
+};
+
+static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
+
+static unsigned long osc_freq;
+static unsigned long pll_ref_freq;
+
+static int __init tegra114_osc_clk_init(void __iomem *clk_base)
+{
+        struct clk *clk;
+        u32 val, pll_ref_div;
+
+        val = readl_relaxed(clk_base + OSC_CTRL);
+
+        osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT];
+        if (!osc_freq) {
+                WARN_ON(1);
+                return -EINVAL;
+        }
+
+        /* clk_m */
+        clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
+                                      osc_freq);
+        clk_register_clkdev(clk, "clk_m", NULL);
+        clks[clk_m] = clk;
+
+        /* pll_ref */
+        val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
+        pll_ref_div = 1 << val;
+        clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
+                                        CLK_SET_RATE_PARENT, 1, pll_ref_div);
+        clk_register_clkdev(clk, "pll_ref", NULL);
+        clks[pll_ref] = clk;
+
+        pll_ref_freq = osc_freq / pll_ref_div;
+
+        return 0;
+}
+
+static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
+{
+        struct clk *clk;
+
+        /* clk_32k */
+        clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
+                                      32768);
+        clk_register_clkdev(clk, "clk_32k", NULL);
+        clks[clk_32k] = clk;
+
+        /* clk_m_div2 */
+        clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
+                                        CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "clk_m_div2", NULL);
+        clks[clk_m_div2] = clk;
+
+        /* clk_m_div4 */
+        clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
+                                        CLK_SET_RATE_PARENT, 1, 4);
+        clk_register_clkdev(clk, "clk_m_div4", NULL);
+        clks[clk_m_div4] = clk;
+
+}
+
+static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
+{
+        u32 reg;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
+                if (osc_freq == utmi_parameters[i].osc_frequency)
+                        break;
+        }
+
+        if (i >= ARRAY_SIZE(utmi_parameters)) {
+                pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
+                       osc_freq);
+                return;
+        }
+
+        reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
+
+        /* Program UTMIP PLL stable and active counts */
+        /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
+        reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
+        reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
+
+        reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
+
+        reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
+                                            active_delay_count);
+
+        /* Remove power downs from UTMIP PLL control bits */
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
+
+        writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
+
+        /* Program UTMIP PLL delay and oscillator frequency counts */
+        reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
+        reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
+
+        reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
+                                            enable_delay_count);
+
+        reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
+        reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
+                                           xtal_freq_count);
+
+        /* Remove power downs from UTMIP PLL control bits */
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
+        writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
+
+        /* Setup HW control of UTMIPLL */
+        reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
+        reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
+        reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
+        reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
+        writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
+
+        reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
+        writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
+
+        udelay(1);
+
+        /* Setup SW override of UTMIPLL assuming USB2.0
+           ports are assigned to USB2 */
+        reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
+        reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
+        reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+        writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
+
+        udelay(1);
+
+        /* Enable HW control UTMIPLL */
+        reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
+        reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
+        writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
+}
+
+static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params)
+{
+        pll_params->vco_min =
+                DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq;
+}
+
+static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
+                                      void __iomem *clk_base)
+{
+        u32 val;
+        u32 step_a, step_b;
+
+        switch (pll_ref_freq) {
+        case 12000000:
+        case 13000000:
+        case 26000000:
+                step_a = 0x2B;
+                step_b = 0x0B;
+                break;
+        case 16800000:
+                step_a = 0x1A;
+                step_b = 0x09;
+                break;
+        case 19200000:
+                step_a = 0x12;
+                step_b = 0x08;
+                break;
+        default:
+                pr_err("%s: Unexpected reference rate %lu\n",
+                        __func__, pll_ref_freq);
+                WARN_ON(1);
+                return -EINVAL;
+        }
+
+        val = step_a << pll_params->stepa_shift;
+        val |= step_b << pll_params->stepb_shift;
+        writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
+
+        return 0;
+}
+
+static void __init _init_iddq(struct tegra_clk_pll_params *pll_params,
+                              void __iomem *clk_base)
+{
+        u32 val, val_iddq;
+
+        val = readl_relaxed(clk_base + pll_params->base_reg);
+        val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
+
+        if (val & BIT(30))
+                WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
+        else {
+                val_iddq |= BIT(pll_params->iddq_bit_idx);
+                writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
+        }
+}
+
+static void __init tegra114_pll_init(void __iomem *clk_base,
+                                     void __iomem *pmc)
+{
+        u32 val;
+        struct clk *clk;
+
+        /* PLLC */
+        _clip_vco_min(&pll_c_params);
+        if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) {
+                _init_iddq(&pll_c_params, clk_base);
+                clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
+                                pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK,
+                                pll_c_freq_table, NULL);
+                clk_register_clkdev(clk, "pll_c", NULL);
+                clks[pll_c] = clk;
+
+                /* PLLC_OUT1 */
+                clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
+                                clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
+                                8, 8, 1, NULL);
+                clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
+                                        clk_base + PLLC_OUT, 1, 0,
+                                        CLK_SET_RATE_PARENT, 0, NULL);
+                clk_register_clkdev(clk, "pll_c_out1", NULL);
+                clks[pll_c_out1] = clk;
+        }
+
+        /* PLLC2 */
+        _clip_vco_min(&pll_c2_params);
+        clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0,
+                             &pll_c2_params, TEGRA_PLL_USE_LOCK,
+                             pll_cx_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_c2", NULL);
+        clks[pll_c2] = clk;
+
+        /* PLLC3 */
+        _clip_vco_min(&pll_c3_params);
+        clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0,
+                             &pll_c3_params, TEGRA_PLL_USE_LOCK,
+                             pll_cx_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_c3", NULL);
+        clks[pll_c3] = clk;
+
+        /* PLLP */
+        clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0,
+                            408000000, &pll_p_params,
+                            TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
+                            pll_p_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_p", NULL);
+        clks[pll_p] = clk;
+
+        /* PLLP_OUT1 */
+        clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
+                                clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
+                                TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
+        clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
+                                clk_base + PLLP_OUTA, 1, 0,
+                                CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
+                                &pll_div_lock);
+        clk_register_clkdev(clk, "pll_p_out1", NULL);
+        clks[pll_p_out1] = clk;
+
+        /* PLLP_OUT2 */
+        clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
+                                clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
+                                TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
+                                &pll_div_lock);
+        clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
+                                clk_base + PLLP_OUTA, 17, 16,
+                                CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
+                                &pll_div_lock);
+        clk_register_clkdev(clk, "pll_p_out2", NULL);
+        clks[pll_p_out2] = clk;
+
+        /* PLLP_OUT3 */
+        clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
+                                clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
+                                TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
+        clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
+                                clk_base + PLLP_OUTB, 1, 0,
+                                CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
+                                &pll_div_lock);
+        clk_register_clkdev(clk, "pll_p_out3", NULL);
+        clks[pll_p_out3] = clk;
+
+        /* PLLP_OUT4 */
+        clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
+                                clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
+                                TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
+                                &pll_div_lock);
+        clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
+                                clk_base + PLLP_OUTB, 17, 16,
+                                CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
+                                &pll_div_lock);
+        clk_register_clkdev(clk, "pll_p_out4", NULL);
+        clks[pll_p_out4] = clk;
+
+        /* PLLM */
+        _clip_vco_min(&pll_m_params);
+        clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
+                             CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0,
+                             &pll_m_params, TEGRA_PLL_USE_LOCK,
+                             pll_m_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_m", NULL);
+        clks[pll_m] = clk;
+
+        /* PLLM_OUT1 */
+        clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
+                                clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
+                                8, 8, 1, NULL);
+        clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
+                                clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
+                                CLK_SET_RATE_PARENT, 0, NULL);
+        clk_register_clkdev(clk, "pll_m_out1", NULL);
+        clks[pll_m_out1] = clk;
+
+        /* PLLM_UD */
+        clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
+                                        CLK_SET_RATE_PARENT, 1, 1);
+
+        /* PLLX */
+        _clip_vco_min(&pll_x_params);
+        if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) {
+                _init_iddq(&pll_x_params, clk_base);
+                clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
+                                pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params,
+                                TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL);
+                clk_register_clkdev(clk, "pll_x", NULL);
+                clks[pll_x] = clk;
+        }
+
+        /* PLLX_OUT0 */
+        clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
+                                        CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll_x_out0", NULL);
+        clks[pll_x_out0] = clk;
+
+        /* PLLU */
+        val = readl(clk_base + pll_u_params.base_reg);
+        val &= ~BIT(24); /* disable PLLU_OVERRIDE */
+        writel(val, clk_base + pll_u_params.base_reg);
+
+        clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
+                            0, &pll_u_params, TEGRA_PLLU |
+                            TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
+                            TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock);
+        clk_register_clkdev(clk, "pll_u", NULL);
+        clks[pll_u] = clk;
+
+        tegra114_utmi_param_configure(clk_base);
+
+        /* PLLU_480M */
+        clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
+                                CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
+                                22, 0, &pll_u_lock);
+        clk_register_clkdev(clk, "pll_u_480M", NULL);
+        clks[pll_u_480M] = clk;
+
+        /* PLLU_60M */
+        clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
+                                        CLK_SET_RATE_PARENT, 1, 8);
+        clk_register_clkdev(clk, "pll_u_60M", NULL);
+        clks[pll_u_60M] = clk;
+
+        /* PLLU_48M */
+        clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
+                                        CLK_SET_RATE_PARENT, 1, 10);
+        clk_register_clkdev(clk, "pll_u_48M", NULL);
+        clks[pll_u_48M] = clk;
+
+        /* PLLU_12M */
+        clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
+                                        CLK_SET_RATE_PARENT, 1, 40);
+        clk_register_clkdev(clk, "pll_u_12M", NULL);
+        clks[pll_u_12M] = clk;
+
+        /* PLLD */
+        clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
+                            0, &pll_d_params,
+                            TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
+                            TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock);
+        clk_register_clkdev(clk, "pll_d", NULL);
+        clks[pll_d] = clk;
+
+        /* PLLD_OUT0 */
+        clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
+                                        CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll_d_out0", NULL);
+        clks[pll_d_out0] = clk;
+
+        /* PLLD2 */
+        clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
+                            0, &pll_d2_params,
+                            TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
+                            TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock);
+        clk_register_clkdev(clk, "pll_d2", NULL);
+        clks[pll_d2] = clk;
+
+        /* PLLD2_OUT0 */
+        clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
+                                        CLK_SET_RATE_PARENT, 1, 2);
+        clk_register_clkdev(clk, "pll_d2_out0", NULL);
+        clks[pll_d2_out0] = clk;
+
+        /* PLLA */
+        clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0,
+                            0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
+                            TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_a", NULL);
+        clks[pll_a] = clk;
+
+        /* PLLA_OUT0 */
+        clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
+                                clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
+                                8, 8, 1, NULL);
+        clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
+                                clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
+                                CLK_SET_RATE_PARENT, 0, NULL);
+        clk_register_clkdev(clk, "pll_a_out0", NULL);
+        clks[pll_a_out0] = clk;
+
+        /* PLLRE */
+        _clip_vco_min(&pll_re_vco_params);
+        clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
+                             0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK,
+                             NULL, &pll_re_lock, pll_ref_freq);
+        clk_register_clkdev(clk, "pll_re_vco", NULL);
+        clks[pll_re_vco] = clk;
+
+        clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
+                                         clk_base + PLLRE_BASE, 16, 4, 0,
+                                         pll_re_div_table, &pll_re_lock);
+        clk_register_clkdev(clk, "pll_re_out", NULL);
+        clks[pll_re_out] = clk;
+
+        /* PLLE */
+        clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco",
+                                      clk_base, 0, 100000000, &pll_e_params,
+                                      pll_e_freq_table, NULL);
+        clk_register_clkdev(clk, "pll_e_out0", NULL);
+        clks[pll_e_out0] = clk;
+}
+
+static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
+        "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
+};
+
+static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
+        "clk_m_div4", "extern1",
+};
+
+static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
+        "clk_m_div4", "extern2",
+};
+
+static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
+        "clk_m_div4", "extern3",
+};
+
+static void __init tegra114_audio_clk_init(void __iomem *clk_base)
+{
+        struct clk *clk;
+
+        /* spdif_in_sync */
+        clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
+                                             24000000);
+        clk_register_clkdev(clk, "spdif_in_sync", NULL);
+        clks[spdif_in_sync] = clk;
+
+        /* i2s0_sync */
+        clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "i2s0_sync", NULL);
+        clks[i2s0_sync] = clk;
+
+        /* i2s1_sync */
+        clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "i2s1_sync", NULL);
+        clks[i2s1_sync] = clk;
+
+        /* i2s2_sync */
+        clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "i2s2_sync", NULL);
+        clks[i2s2_sync] = clk;
+
+        /* i2s3_sync */
+        clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "i2s3_sync", NULL);
+        clks[i2s3_sync] = clk;
+
+        /* i2s4_sync */
+        clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "i2s4_sync", NULL);
+        clks[i2s4_sync] = clk;
+
+        /* vimclk_sync */
+        clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
+        clk_register_clkdev(clk, "vimclk_sync", NULL);
+        clks[vimclk_sync] = clk;
+
+        /* audio0 */
+        clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
+                               NULL);
+        clks[audio0_mux] = clk;
+        clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_I2S0, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "audio0", NULL);
+        clks[audio0] = clk;
+
+        /* audio1 */
+        clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
+                               NULL);
+        clks[audio1_mux] = clk;
+        clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_I2S1, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "audio1", NULL);
+        clks[audio1] = clk;
+
+        /* audio2 */
+        clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
+                               NULL);
+        clks[audio2_mux] = clk;
+        clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_I2S2, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "audio2", NULL);
+        clks[audio2] = clk;
+
+        /* audio3 */
+        clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
+                               NULL);
+        clks[audio3_mux] = clk;
+        clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_I2S3, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "audio3", NULL);
+        clks[audio3] = clk;
+
+        /* audio4 */
+        clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
+                               NULL);
+        clks[audio4_mux] = clk;
+        clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_I2S4, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "audio4", NULL);
+        clks[audio4] = clk;
+
+        /* spdif */
+        clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
+                               ARRAY_SIZE(mux_audio_sync_clk), 0,
+                               clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
+                               NULL);
+        clks[spdif_mux] = clk;
+        clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
+                                clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
+                                CLK_GATE_SET_TO_DISABLE, NULL);
+        clk_register_clkdev(clk, "spdif", NULL);
+        clks[spdif] = clk;
+
+        /* audio0_2x */
+        clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 113, &periph_v_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "audio0_2x", NULL);
+        clks[audio0_2x] = clk;
+
+        /* audio1_2x */
+        clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 114, &periph_v_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "audio1_2x", NULL);
+        clks[audio1_2x] = clk;
+
+        /* audio2_2x */
+        clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 115, &periph_v_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "audio2_2x", NULL);
+        clks[audio2_2x] = clk;
+
+        /* audio3_2x */
+        clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 116, &periph_v_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "audio3_2x", NULL);
+        clks[audio3_2x] = clk;
+
+        /* audio4_2x */
+        clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 117, &periph_v_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "audio4_2x", NULL);
+        clks[audio4_2x] = clk;
+
+        /* spdif_2x */
+        clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
+                                        CLK_SET_RATE_PARENT, 2, 1);
+        clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
+                                clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1,
+                                0, &clk_doubler_lock);
+        clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
+                                  TEGRA_PERIPH_NO_RESET, clk_base,
+                                  CLK_SET_RATE_PARENT, 118,
+                                  &periph_v_regs, periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, "spdif_2x", NULL);
+        clks[spdif_2x] = clk;
+}
+
+static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
+{
+        struct clk *clk;
+
+        /* clk_out_1 */
+        clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
+                               ARRAY_SIZE(clk_out1_parents), 0,
+                               pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
+                               &clk_out_lock);
+        clks[clk_out_1_mux] = clk;
+        clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
+                                pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
+                                &clk_out_lock);
+        clk_register_clkdev(clk, "extern1", "clk_out_1");
+        clks[clk_out_1] = clk;
+
+        /* clk_out_2 */
+        clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
+                               ARRAY_SIZE(clk_out1_parents), 0,
+                               pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
+                               &clk_out_lock);
+        clks[clk_out_2_mux] = clk;
+        clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
+                                pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
+                                &clk_out_lock);
+        clk_register_clkdev(clk, "extern2", "clk_out_2");
+        clks[clk_out_2] = clk;
+
+        /* clk_out_3 */
+        clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
+                               ARRAY_SIZE(clk_out1_parents), 0,
+                               pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
+                               &clk_out_lock);
+        clks[clk_out_3_mux] = clk;
+        clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
+                                pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
+                                &clk_out_lock);
+        clk_register_clkdev(clk, "extern3", "clk_out_3");
+        clks[clk_out_3] = clk;
+
+        /* blink */
+        clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
+                                pmc_base + PMC_DPD_PADS_ORIDE,
+                                PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
+        clk = clk_register_gate(NULL, "blink", "blink_override", 0,
+                                pmc_base + PMC_CTRL,
+                                PMC_CTRL_BLINK_ENB, 0, NULL);
+        clk_register_clkdev(clk, "blink", NULL);
+        clks[blink] = clk;
+
+}
+
+static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
+                               "pll_p_out3", "pll_p_out2", "unused",
+                               "clk_32k", "pll_m_out1" };
+
+static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
+                                        "pll_p", "pll_p_out4", "unused",
+                                        "unused", "pll_x" };
+
+static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
+                                         "pll_p", "pll_p_out4", "unused",
+                                         "unused", "pll_x", "pll_x_out0" };
+
+static void __init tegra114_super_clk_init(void __iomem *clk_base)
+{
+        struct clk *clk;
+
+        /* CCLKG */
+        clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
+                                        ARRAY_SIZE(cclk_g_parents),
+                                        CLK_SET_RATE_PARENT,
+                                        clk_base + CCLKG_BURST_POLICY,
+                                        0, 4, 0, 0, NULL);
+        clk_register_clkdev(clk, "cclk_g", NULL);
+        clks[cclk_g] = clk;
+
+        /* CCLKLP */
+        clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
+                                        ARRAY_SIZE(cclk_lp_parents),
+                                        CLK_SET_RATE_PARENT,
+                                        clk_base + CCLKLP_BURST_POLICY,
+                                        0, 4, 8, 9, NULL);
+        clk_register_clkdev(clk, "cclk_lp", NULL);
+        clks[cclk_lp] = clk;
+
+        /* SCLK */
+        clk = tegra_clk_register_super_mux("sclk", sclk_parents,
+                                        ARRAY_SIZE(sclk_parents),
+                                        CLK_SET_RATE_PARENT,
+                                        clk_base + SCLK_BURST_POLICY,
+                                        0, 4, 0, 0, NULL);
+        clk_register_clkdev(clk, "sclk", NULL);
+        clks[sclk] = clk;
+
+        /* HCLK */
+        clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
+                                   clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
+                                   &sysrate_lock);
+        clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT |
+                                CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
+                                7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
+        clk_register_clkdev(clk, "hclk", NULL);
+        clks[hclk] = clk;
+
+        /* PCLK */
+        clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
+                                   clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
+                                   &sysrate_lock);
+        clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
+                                CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
+                                3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
+        clk_register_clkdev(clk, "pclk", NULL);
+        clks[pclk] = clk;
+}
+
+static struct tegra_periph_init_data tegra_periph_clk_list[] = {
+        TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
+        TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
+        TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
+        TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
+        TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
+        TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
+        TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
+        TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm),
+        TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx),
+        TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx),
+        TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda),
+        TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x),
+        TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
+        TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
+        TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
+        TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
+        TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
+        TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
+        TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
+        TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
+        TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
+        TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
+        TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
+        TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
+        TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
+        TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
+        TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED),
+        TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
+        TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace),
+        TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
+        TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
+        TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
+        TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1),
+        TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2),
+        TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3),
+        TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4),
+        TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5),
+        TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
+        TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
+        TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
+        TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
+        TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
+        TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
+        TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
+        TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
+        TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
+        TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_h_regs, TEGRA_PERIPH_WAR_1005168, msenc),
+        TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec),
+        TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
+        TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
+        TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab),
+        TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd),
+        TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile),
+        TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp),
+        TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp),
+        TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
+        TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
+        TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
+        TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
+        TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
+        TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
+        TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se),
+        TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED),
+        TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm),
+        TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src),
+        TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src),
+        TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src),
+        TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src),
+        TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src),
+        TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio),
+        TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0),
+        TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1),
+        TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2),
+};
+
+static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
+        TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1),
+        TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2),
+};
+
+static __init void tegra114_periph_clk_init(void __iomem *clk_base)
+{
+        struct tegra_periph_init_data *data;
+        struct clk *clk;
+        int i;
+        u32 val;
+
+        /* apbdma */
+        clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
+                                  0, 34, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[apbdma] = clk;
+
+        /* rtc */
+        clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
+                                    TEGRA_PERIPH_ON_APB |
+                                    TEGRA_PERIPH_NO_RESET, clk_base,
+                                    0, 4, &periph_l_regs,
+                                    periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, NULL, "rtc-tegra");
+        clks[rtc] = clk;
+
+        /* kbc */
+        clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
+                                    TEGRA_PERIPH_ON_APB |
+                                    TEGRA_PERIPH_NO_RESET, clk_base,
+                                    0, 36, &periph_h_regs,
+                                    periph_clk_enb_refcnt);
+        clks[kbc] = clk;
+
+        /* timer */
+        clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
+                                  0, 5, &periph_l_regs,
+                                  periph_clk_enb_refcnt);
+        clk_register_clkdev(clk, NULL, "timer");
+        clks[timer] = clk;
+
+        /* kfuse */
+        clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base,  0, 40,
+                                  &periph_h_regs, periph_clk_enb_refcnt);
+        clks[kfuse] = clk;
+
+        /* fuse */
+        clk = tegra_clk_register_periph_gate("fuse", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base,  0, 39,
+                                  &periph_h_regs, periph_clk_enb_refcnt);
+        clks[fuse] = clk;
+
+        /* fuse_burn */
+        clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base,  0, 39,
+                                  &periph_h_regs, periph_clk_enb_refcnt);
+        clks[fuse_burn] = clk;
+
+        /* apbif */
+        clk = tegra_clk_register_periph_gate("apbif", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base,  0, 107,
+                                  &periph_v_regs, periph_clk_enb_refcnt);
+        clks[apbif] = clk;
+
+        /* hda2hdmi */
+        clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
+                                    TEGRA_PERIPH_ON_APB, clk_base,  0, 128,
+                                    &periph_w_regs, periph_clk_enb_refcnt);
+        clks[hda2hdmi] = clk;
+
+        /* vcp */
+        clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base,  0,
+                                  29, &periph_l_regs,
+                                  periph_clk_enb_refcnt);
+        clks[vcp] = clk;
+
+        /* bsea */
+        clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base,
+                                  0, 62, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[bsea] = clk;
+
+        /* bsev */
+        clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base,
+                                  0, 63, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[bsev] = clk;
+
+        /* mipi-cal */
+        clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
+                                   0, 56, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[mipi_cal] = clk;
+
+        /* usbd */
+        clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base,
+                                  0, 22, &periph_l_regs,
+                                  periph_clk_enb_refcnt);
+        clks[usbd] = clk;
+
+        /* usb2 */
+        clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base,
+                                  0, 58, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[usb2] = clk;
+
+        /* usb3 */
+        clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base,
+                                  0, 59, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[usb3] = clk;
+
+        /* csi */
+        clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
+                                   0, 52, &periph_h_regs,
+                                  periph_clk_enb_refcnt);
+        clks[csi] = clk;
+
+        /* isp */
+        clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0,
+                                  23, &periph_l_regs,
+                                  periph_clk_enb_refcnt);
+        clks[isp] = clk;
+
+        /* csus */
+        clk = tegra_clk_register_periph_gate("csus", "clk_m",
+                                  TEGRA_PERIPH_NO_RESET, clk_base, 0, 92,
+                                  &periph_u_regs, periph_clk_enb_refcnt);
+        clks[csus] = clk;
+
+        /* dds */
+        clk = tegra_clk_register_periph_gate("dds", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base, 0, 150,
+                                  &periph_w_regs, periph_clk_enb_refcnt);
+        clks[dds] = clk;
+
+        /* dp2 */
+        clk = tegra_clk_register_periph_gate("dp2", "clk_m",
+                                  TEGRA_PERIPH_ON_APB, clk_base, 0, 152,
+                                  &periph_w_regs, periph_clk_enb_refcnt);
+        clks[dp2] = clk;
+
+        /* dtv */
+        clk = tegra_clk_register_periph_gate("dtv", "clk_m",
+                                    TEGRA_PERIPH_ON_APB, clk_base, 0, 79,
+                                    &periph_u_regs, periph_clk_enb_refcnt);
+        clks[dtv] = clk;
+
+        /* dsia */
+        clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
+                               ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+                               clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
+        clks[dsia_mux] = clk;
+        clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
+                                    0, 48, &periph_h_regs,
+                                    periph_clk_enb_refcnt);
+        clks[dsia] = clk;
+
+        /* dsib */
+        clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
+                               ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
+                               clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
+        clks[dsib_mux] = clk;
+        clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
+                                    0, 82, &periph_u_regs,
+                                    periph_clk_enb_refcnt);
+        clks[dsib] = clk;
+
+        /* xusb_hs_src */
+        val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
+        val |= BIT(25); /* always select PLLU_60M */
+        writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
+
+        clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
+                                        1, 1);
+        clks[xusb_hs_src] = clk;
+
+        /* xusb_host */
+        clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
+                                    clk_base, 0, 89, &periph_u_regs,
+                                    periph_clk_enb_refcnt);
+        clks[xusb_host] = clk;
+
+        /* xusb_ss */
+        clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
+                                    clk_base, 0, 156, &periph_w_regs,
+                                    periph_clk_enb_refcnt);
+        clks[xusb_host] = clk;
+
+        /* xusb_dev */
+        clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
+                                    clk_base, 0, 95, &periph_u_regs,
+                                    periph_clk_enb_refcnt);
+        clks[xusb_dev] = clk;
+
+        /* emc */
+        clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
+                               ARRAY_SIZE(mux_pllmcp_clkm), 0,
+                               clk_base + CLK_SOURCE_EMC,
+                               29, 3, 0, NULL);
+        clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
+                                CLK_IGNORE_UNUSED, 57, &periph_h_regs,
+                                periph_clk_enb_refcnt);
+        clks[emc] = clk;
+
+        for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
+                data = &tegra_periph_clk_list[i];
+                clk = tegra_clk_register_periph(data->name, data->parent_names,
+                                data->num_parents, &data->periph,
+                                clk_base, data->offset, data->flags);
+                clks[data->clk_id] = clk;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
+                data = &tegra_periph_nodiv_clk_list[i];
+                clk = tegra_clk_register_periph_nodiv(data->name,
+                                data->parent_names, data->num_parents,
+                                &data->periph, clk_base, data->offset);
+                clks[data->clk_id] = clk;
+        }
+}
+
+static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
+
+static const struct of_device_id pmc_match[] __initconst = {
+        { .compatible = "nvidia,tegra114-pmc" },
+        {},
+};
+
+static __initdata struct tegra_clk_init_table init_table[] = {
+        {uarta, pll_p, 408000000, 0},
+        {uartb, pll_p, 408000000, 0},
+        {uartc, pll_p, 408000000, 0},
+        {uartd, pll_p, 408000000, 0},
+        {pll_a, clk_max, 564480000, 1},
+        {pll_a_out0, clk_max, 11289600, 1},
+        {extern1, pll_a_out0, 0, 1},
+        {clk_out_1_mux, extern1, 0, 1},
+        {clk_out_1, clk_max, 0, 1},
+        {i2s0, pll_a_out0, 11289600, 0},
+        {i2s1, pll_a_out0, 11289600, 0},
+        {i2s2, pll_a_out0, 11289600, 0},
+        {i2s3, pll_a_out0, 11289600, 0},
+        {i2s4, pll_a_out0, 11289600, 0},
+        {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
+};
+
+static void __init tegra114_clock_apply_init_table(void)
+{
+        tegra_init_from_table(init_table, clks, clk_max);
+}
+
+void __init tegra114_clock_init(struct device_node *np)
+{
+        struct device_node *node;
+        int i;
+
+        clk_base = of_iomap(np, 0);
+        if (!clk_base) {
+                pr_err("ioremap tegra114 CAR failed\n");
+                return;
+        }
+
+        node = of_find_matching_node(NULL, pmc_match);
+        if (!node) {
+                pr_err("Failed to find pmc node\n");
+                WARN_ON(1);
+                return;
+        }
+
+        pmc_base = of_iomap(node, 0);
+        if (!pmc_base) {
+                pr_err("Can't map pmc registers\n");
+                WARN_ON(1);
+                return;
+        }
+
+        if (tegra114_osc_clk_init(clk_base) < 0)
+                return;
+
+        tegra114_fixed_clk_init(clk_base);
+        tegra114_pll_init(clk_base, pmc_base);
+        tegra114_periph_clk_init(clk_base);
+        tegra114_audio_clk_init(clk_base);
+        tegra114_pmc_clk_init(pmc_base);
+        tegra114_super_clk_init(clk_base);
+
+        for (i = 0; i < ARRAY_SIZE(clks); i++) {
+                if (IS_ERR(clks[i])) {
+                        pr_err
+                            ("Tegra114 clk %d: register failed with %ld\n",
+                             i, PTR_ERR(clks[i]));
+                }
+                if (!clks[i])
+                        clks[i] = ERR_PTR(-EINVAL);
+        }
+
+        clk_data.clks = clks;
+        clk_data.clk_num = ARRAY_SIZE(clks);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+        tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
+
+        tegra_cpu_car_ops = &tegra114_cpu_car_ops;
+}
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index bf194009e20f..8292a00c3de9 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -86,8 +86,8 @@
 #define PLLE_BASE 0xe8
 #define PLLE_MISC 0xec
 
-#define PLL_BASE_LOCK 27
-#define PLLE_MISC_LOCK 11
+#define PLL_BASE_LOCK BIT(27)
+#define PLLE_MISC_LOCK BIT(11)
 
 #define PLL_MISC_LOCK_ENABLE 18
 #define PLLDU_MISC_LOCK_ENABLE 22
@@ -236,7 +236,7 @@ enum tegra20_clk {
         dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
         usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
         pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
-        iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
+        iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
         uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
         osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
         pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
@@ -248,125 +248,125 @@ static struct clk *clks[clk_max];
 static struct clk_onecell_data clk_data;
 
 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
-        { 12000000, 600000000, 600, 12, 1, 8 },
-        { 13000000, 600000000, 600, 13, 1, 8 },
-        { 19200000, 600000000, 500, 16, 1, 6 },
-        { 26000000, 600000000, 600, 26, 1, 8 },
+        { 12000000, 600000000, 600, 12, 0, 8 },
+        { 13000000, 600000000, 600, 13, 0, 8 },
+        { 19200000, 600000000, 500, 16, 0, 6 },
+        { 26000000, 600000000, 600, 26, 0, 8 },
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
+        { 12000000, 666000000, 666, 12, 0, 8},
+        { 13000000, 666000000, 666, 13, 0, 8},
+        { 19200000, 666000000, 555, 16, 0, 8},
+        { 26000000, 666000000, 666, 26, 0, 8},
+        { 12000000, 600000000, 600, 12, 0, 8},
+        { 13000000, 600000000, 600, 13, 0, 8},
+        { 19200000, 600000000, 375, 12, 0, 6},
+        { 26000000, 600000000, 600, 26, 0, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 19200000, 216000000, 90,   4, 2, 1},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 12000000, 432000000, 432, 12, 1, 8},
-        { 13000000, 432000000, 432, 13, 1, 8},
-        { 19200000, 432000000, 90,   4, 1, 1},
-        { 26000000, 432000000, 432, 26, 1, 8},
+        { 12000000, 216000000, 432, 12, 1, 8},
+        { 13000000, 216000000, 432, 13, 1, 8},
+        { 19200000, 216000000, 90,   4, 1, 1},
+        { 26000000, 216000000, 432, 26, 1, 8},
+        { 12000000, 432000000, 432, 12, 0, 8},
+        { 13000000, 432000000, 432, 13, 0, 8},
+        { 19200000, 432000000, 90,   4, 0, 1},
+        { 26000000, 432000000, 432, 26, 0, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
+        { 28800000, 56448000, 49, 25, 0, 1},
+        { 28800000, 73728000, 64, 25, 0, 1},
+        { 28800000, 24000000,  5,  6, 0, 1},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 19200000, 216000000, 135, 12, 1, 3},
-        { 26000000, 216000000, 216, 26, 1, 4},
+        { 12000000, 216000000, 216, 12, 0, 4},
+        { 13000000, 216000000, 216, 13, 0, 4},
+        { 19200000, 216000000, 135, 12, 0, 3},
+        { 26000000, 216000000, 216, 26, 0, 4},
 
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
+        { 12000000, 594000000, 594, 12, 0, 8},
+        { 13000000, 594000000, 594, 13, 0, 8},
+        { 19200000, 594000000, 495, 16, 0, 8},
+        { 26000000, 594000000, 594, 26, 0, 8},
 
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
+        { 12000000, 1000000000, 1000, 12, 0, 12},
+        { 13000000, 1000000000, 1000, 13, 0, 12},
+        { 19200000, 1000000000, 625,  12, 0, 8},
+        { 26000000, 1000000000, 1000, 26, 0, 12},
 
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 0},
-        { 13000000, 480000000, 960, 13, 2, 0},
-        { 19200000, 480000000, 200, 4,  2, 0},
-        { 26000000, 480000000, 960, 26, 2, 0},
+        { 12000000, 480000000, 960, 12, 0, 0},
+        { 13000000, 480000000, 960, 13, 0, 0},
+        { 19200000, 480000000, 200, 4,  0, 0},
+        { 26000000, 480000000, 960, 26, 0, 0},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
         /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
+        { 12000000, 1000000000, 1000, 12, 0, 12},
+        { 13000000, 1000000000, 1000, 13, 0, 12},
+        { 19200000, 1000000000, 625,  12, 0, 8},
+        { 26000000, 1000000000, 1000, 26, 0, 12},
 
         /* 912 MHz */
-        { 12000000, 912000000,  912,  12, 1, 12},
-        { 13000000, 912000000,  912,  13, 1, 12},
-        { 19200000, 912000000,  760,  16, 1, 8},
-        { 26000000, 912000000,  912,  26, 1, 12},
+        { 12000000, 912000000,  912,  12, 0, 12},
+        { 13000000, 912000000,  912,  13, 0, 12},
+        { 19200000, 912000000,  760,  16, 0, 8},
+        { 26000000, 912000000,  912,  26, 0, 12},
 
         /* 816 MHz */
-        { 12000000, 816000000,  816,  12, 1, 12},
-        { 13000000, 816000000,  816,  13, 1, 12},
-        { 19200000, 816000000,  680,  16, 1, 8},
-        { 26000000, 816000000,  816,  26, 1, 12},
+        { 12000000, 816000000,  816,  12, 0, 12},
+        { 13000000, 816000000,  816,  13, 0, 12},
+        { 19200000, 816000000,  680,  16, 0, 8},
+        { 26000000, 816000000,  816,  26, 0, 12},
 
         /* 760 MHz */
-        { 12000000, 760000000,  760,  12, 1, 12},
-        { 13000000, 760000000,  760,  13, 1, 12},
-        { 19200000, 760000000,  950,  24, 1, 8},
-        { 26000000, 760000000,  760,  26, 1, 12},
+        { 12000000, 760000000,  760,  12, 0, 12},
+        { 13000000, 760000000,  760,  13, 0, 12},
+        { 19200000, 760000000,  950,  24, 0, 8},
+        { 26000000, 760000000,  760,  26, 0, 12},
 
         /* 750 MHz */
-        { 12000000, 750000000,  750,  12, 1, 12},
-        { 13000000, 750000000,  750,  13, 1, 12},
-        { 19200000, 750000000,  625,  16, 1, 8},
-        { 26000000, 750000000,  750,  26, 1, 12},
+        { 12000000, 750000000,  750,  12, 0, 12},
+        { 13000000, 750000000,  750,  13, 0, 12},
+        { 19200000, 750000000,  625,  16, 0, 8},
+        { 26000000, 750000000,  750,  26, 0, 12},
 
         /* 608 MHz */
-        { 12000000, 608000000,  608,  12, 1, 12},
-        { 13000000, 608000000,  608,  13, 1, 12},
-        { 19200000, 608000000,  380,  12, 1, 8},
-        { 26000000, 608000000,  608,  26, 1, 12},
+        { 12000000, 608000000,  608,  12, 0, 12},
+        { 13000000, 608000000,  608,  13, 0, 12},
+        { 19200000, 608000000,  380,  12, 0, 8},
+        { 26000000, 608000000,  608,  26, 0, 12},
 
         /* 456 MHz */
-        { 12000000, 456000000,  456,  12, 1, 12},
-        { 13000000, 456000000,  456,  13, 1, 12},
-        { 19200000, 456000000,  380,  16, 1, 8},
-        { 26000000, 456000000,  456,  26, 1, 12},
+        { 12000000, 456000000,  456,  12, 0, 12},
+        { 13000000, 456000000,  456,  13, 0, 12},
+        { 19200000, 456000000,  380,  16, 0, 8},
+        { 26000000, 456000000,  456,  26, 0, 12},
 
         /* 312 MHz */
-        { 12000000, 312000000,  312,  12, 1, 12},
-        { 13000000, 312000000,  312,  13, 1, 12},
-        { 19200000, 312000000,  260,  16, 1, 8},
-        { 26000000, 312000000,  312,  26, 1, 12},
+        { 12000000, 312000000,  312,  12, 0, 12},
+        { 13000000, 312000000,  312,  13, 0, 12},
+        { 19200000, 312000000,  260,  16, 0, 8},
+        { 26000000, 312000000,  312,  26, 0, 12},
 
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
-        { 12000000, 100000000,  200,  24, 1, 0 },
+        { 12000000, 100000000,  200,  24, 0, 0 },
         { 0, 0, 0, 0, 0, 0 },
 };
 
@@ -380,7 +380,7 @@ static struct tegra_clk_pll_params pll_c_params = {
         .vco_max = 1400000000,
         .base_reg = PLLC_BASE,
         .misc_reg = PLLC_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -394,7 +394,7 @@ static struct tegra_clk_pll_params pll_m_params = {
         .vco_max = 1200000000,
         .base_reg = PLLM_BASE,
         .misc_reg = PLLM_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -408,7 +408,7 @@ static struct tegra_clk_pll_params pll_p_params = {
         .vco_max = 1400000000,
         .base_reg = PLLP_BASE,
         .misc_reg = PLLP_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -422,7 +422,7 @@ static struct tegra_clk_pll_params pll_a_params = {
         .vco_max = 1400000000,
         .base_reg = PLLA_BASE,
         .misc_reg = PLLA_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -436,11 +436,17 @@ static struct tegra_clk_pll_params pll_d_params = {
         .vco_max = 1000000000,
         .base_reg = PLLD_BASE,
         .misc_reg = PLLD_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
 };
 
+static struct pdiv_map pllu_p[] = {
+        { .pdiv = 1, .hw_val = 1 },
+        { .pdiv = 2, .hw_val = 0 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
 static struct tegra_clk_pll_params pll_u_params = {
         .input_min = 2000000,
         .input_max = 40000000,
@@ -450,9 +456,10 @@ static struct tegra_clk_pll_params pll_u_params = {
         .vco_max = 960000000,
         .base_reg = PLLU_BASE,
         .misc_reg = PLLU_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
+        .pdiv_tohw = pllu_p,
 };
 
 static struct tegra_clk_pll_params pll_x_params = {
@@ -464,7 +471,7 @@ static struct tegra_clk_pll_params pll_x_params = {
         .vco_max = 1200000000,
         .base_reg = PLLX_BASE,
         .misc_reg = PLLX_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -478,7 +485,7 @@ static struct tegra_clk_pll_params pll_e_params = {
         .vco_max = 0,
         .base_reg = PLLE_BASE,
         .misc_reg = PLLE_MISC,
-        .lock_bit_idx = PLLE_MISC_LOCK,
+        .lock_mask = PLLE_MISC_LOCK,
         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
         .lock_delay = 0,
 };
@@ -1012,7 +1019,7 @@ static void __init tegra20_periph_clk_init(void)
                 data = &tegra_periph_clk_list[i];
                 clk = tegra_clk_register_periph(data->name, data->parent_names,
                                 data->num_parents, &data->periph,
-                                clk_base, data->offset);
+                                clk_base, data->offset, data->flags);
                 clk_register_clkdev(clk, data->con_id, data->dev_id);
                 clks[data->clk_id] = clk;
         }
@@ -1247,9 +1254,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
         {host1x, pll_c, 150000000, 0},
         {disp1, pll_p, 600000000, 0},
         {disp2, pll_p, 600000000, 0},
+        {gr2d, pll_c, 300000000, 0},
+        {gr3d, pll_c, 300000000, 0},
         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
 };
 
+static void __init tegra20_clock_apply_init_table(void)
+{
+        tegra_init_from_table(init_table, clks, clk_max);
+}
+
 /*
  * Some clocks may be used by different drivers depending on the board
  * configuration.  List those here to register them twice in the clock lookup
@@ -1316,7 +1330,7 @@ void __init tegra20_clock_init(struct device_node *np)
         clk_data.clk_num = ARRAY_SIZE(clks);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        tegra_init_from_table(init_table, clks, clk_max);
+        tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
 
         tegra_cpu_car_ops = &tegra20_cpu_car_ops;
 }
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index f15f147d473c..c6921f538e28 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -115,8 +115,8 @@
 #define PLLDU_MISC_LOCK_ENABLE 22
 #define PLLE_MISC_LOCK_ENABLE 9
 
-#define PLL_BASE_LOCK 27
-#define PLLE_MISC_LOCK 11
+#define PLL_BASE_LOCK BIT(27)
+#define PLLE_MISC_LOCK BIT(11)
 
 #define PLLE_AUX 0x48c
 #define PLLC_OUT 0x84
@@ -329,7 +329,7 @@ enum tegra30_clk {
         usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
         pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
         dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
-        cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
+        cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
         i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
         atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
         spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
@@ -373,164 +373,170 @@ static const struct utmi_clk_param utmi_parameters[] = {
 };
 
 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
-        { 12000000, 1040000000, 520,  6, 1, 8},
-        { 13000000, 1040000000, 480,  6, 1, 8},
-        { 16800000, 1040000000, 495,  8, 1, 8}, /* actual: 1039.5 MHz */
-        { 19200000, 1040000000, 325,  6, 1, 6},
-        { 26000000, 1040000000, 520, 13, 1, 8},
-
-        { 12000000, 832000000, 416,  6, 1, 8},
-        { 13000000, 832000000, 832, 13, 1, 8},
-        { 16800000, 832000000, 396,  8, 1, 8},  /* actual: 831.6 MHz */
-        { 19200000, 832000000, 260,  6, 1, 8},
-        { 26000000, 832000000, 416, 13, 1, 8},
-
-        { 12000000, 624000000, 624, 12, 1, 8},
-        { 13000000, 624000000, 624, 13, 1, 8},
-        { 16800000, 600000000, 520, 14, 1, 8},
-        { 19200000, 624000000, 520, 16, 1, 8},
-        { 26000000, 624000000, 624, 26, 1, 8},
-
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-
-        { 12000000, 520000000, 520, 12, 1, 8},
-        { 13000000, 520000000, 520, 13, 1, 8},
-        { 16800000, 520000000, 495, 16, 1, 8},  /* actual: 519.75 MHz */
-        { 19200000, 520000000, 325, 12, 1, 6},
-        { 26000000, 520000000, 520, 26, 1, 8},
-
-        { 12000000, 416000000, 416, 12, 1, 8},
-        { 13000000, 416000000, 416, 13, 1, 8},
-        { 16800000, 416000000, 396, 16, 1, 8},  /* actual: 415.8 MHz */
-        { 19200000, 416000000, 260, 12, 1, 6},
-        { 26000000, 416000000, 416, 26, 1, 8},
+        { 12000000, 1040000000, 520,  6, 0, 8},
+        { 13000000, 1040000000, 480,  6, 0, 8},
+        { 16800000, 1040000000, 495,  8, 0, 8}, /* actual: 1039.5 MHz */
+        { 19200000, 1040000000, 325,  6, 0, 6},
+        { 26000000, 1040000000, 520, 13, 0, 8},
+
+        { 12000000, 832000000, 416,  6, 0, 8},
+        { 13000000, 832000000, 832, 13, 0, 8},
+        { 16800000, 832000000, 396,  8, 0, 8},  /* actual: 831.6 MHz */
+        { 19200000, 832000000, 260,  6, 0, 8},
+        { 26000000, 832000000, 416, 13, 0, 8},
+
+        { 12000000, 624000000, 624, 12, 0, 8},
+        { 13000000, 624000000, 624, 13, 0, 8},
+        { 16800000, 600000000, 520, 14, 0, 8},
+        { 19200000, 624000000, 520, 16, 0, 8},
+        { 26000000, 624000000, 624, 26, 0, 8},
+
+        { 12000000, 600000000, 600, 12, 0, 8},
+        { 13000000, 600000000, 600, 13, 0, 8},
+        { 16800000, 600000000, 500, 14, 0, 8},
+        { 19200000, 600000000, 375, 12, 0, 6},
+        { 26000000, 600000000, 600, 26, 0, 8},
+
+        { 12000000, 520000000, 520, 12, 0, 8},
+        { 13000000, 520000000, 520, 13, 0, 8},
+        { 16800000, 520000000, 495, 16, 0, 8},  /* actual: 519.75 MHz */
+        { 19200000, 520000000, 325, 12, 0, 6},
+        { 26000000, 520000000, 520, 26, 0, 8},
+
+        { 12000000, 416000000, 416, 12, 0, 8},
+        { 13000000, 416000000, 416, 13, 0, 8},
+        { 16800000, 416000000, 396, 16, 0, 8},  /* actual: 415.8 MHz */
+        { 19200000, 416000000, 260, 12, 0, 6},
+        { 26000000, 416000000, 416, 26, 0, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 16800000, 666000000, 555, 14, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
+        { 12000000, 666000000, 666, 12, 0, 8},
+        { 13000000, 666000000, 666, 13, 0, 8},
+        { 16800000, 666000000, 555, 14, 0, 8},
+        { 19200000, 666000000, 555, 16, 0, 8},
+        { 26000000, 666000000, 666, 26, 0, 8},
+        { 12000000, 600000000, 600, 12, 0, 8},
+        { 13000000, 600000000, 600, 13, 0, 8},
+        { 16800000, 600000000, 500, 14, 0, 8},
+        { 19200000, 600000000, 375, 12, 0, 6},
+        { 26000000, 600000000, 600, 26, 0, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 16800000, 216000000, 360, 14, 2, 8},
-        { 19200000, 216000000, 360, 16, 2, 8},
-        { 26000000, 216000000, 432, 26, 2, 8},
+        { 12000000, 216000000, 432, 12, 1, 8},
+        { 13000000, 216000000, 432, 13, 1, 8},
+        { 16800000, 216000000, 360, 14, 1, 8},
+        { 19200000, 216000000, 360, 16, 1, 8},
+        { 26000000, 216000000, 432, 26, 1, 8},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
-        { 9600000, 564480000, 294, 5, 1, 4},
-        { 9600000, 552960000, 288, 5, 1, 4},
-        { 9600000, 24000000,  5,   2, 1, 1},
+        { 9600000, 564480000, 294, 5, 0, 4},
+        { 9600000, 552960000, 288, 5, 0, 4},
+        { 9600000, 24000000,  5,   2, 0, 1},
 
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
+        { 28800000, 56448000, 49, 25, 0, 1},
+        { 28800000, 73728000, 64, 25, 0, 1},
+        { 28800000, 24000000,  5,  6, 0, 1},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 16800000, 216000000, 180, 14, 1, 4},
-        { 19200000, 216000000, 180, 16, 1, 4},
-        { 26000000, 216000000, 216, 26, 1, 4},
-
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 16800000, 594000000, 495, 14, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
-
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
+        { 12000000, 216000000, 216, 12, 0, 4},
+        { 13000000, 216000000, 216, 13, 0, 4},
+        { 16800000, 216000000, 180, 14, 0, 4},
+        { 19200000, 216000000, 180, 16, 0, 4},
+        { 26000000, 216000000, 216, 26, 0, 4},
+
+        { 12000000, 594000000, 594, 12, 0, 8},
+        { 13000000, 594000000, 594, 13, 0, 8},
+        { 16800000, 594000000, 495, 14, 0, 8},
+        { 19200000, 594000000, 495, 16, 0, 8},
+        { 26000000, 594000000, 594, 26, 0, 8},
+
+        { 12000000, 1000000000, 1000, 12, 0, 12},
+        { 13000000, 1000000000, 1000, 13, 0, 12},
+        { 19200000, 1000000000, 625,  12, 0, 8},
+        { 26000000, 1000000000, 1000, 26, 0, 12},
 
         { 0, 0, 0, 0, 0, 0 },
 };
 
+static struct pdiv_map pllu_p[] = {
+        { .pdiv = 1, .hw_val = 1 },
+        { .pdiv = 2, .hw_val = 0 },
+        { .pdiv = 0, .hw_val = 0 },
+};
+
 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 12},
-        { 13000000, 480000000, 960, 13, 2, 12},
-        { 16800000, 480000000, 400, 7,  2, 5},
-        { 19200000, 480000000, 200, 4,  2, 3},
-        { 26000000, 480000000, 960, 26, 2, 12},
+        { 12000000, 480000000, 960, 12, 0, 12},
+        { 13000000, 480000000, 960, 13, 0, 12},
+        { 16800000, 480000000, 400, 7,  0, 5},
+        { 19200000, 480000000, 200, 4,  0, 3},
+        { 26000000, 480000000, 960, 26, 0, 12},
         { 0, 0, 0, 0, 0, 0 },
 };
 
 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
         /* 1.7 GHz */
-        { 12000000, 1700000000, 850,  6,  1, 8},
-        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
-        { 26000000, 1700000000, 850,  13, 1, 8},
+        { 12000000, 1700000000, 850,  6,  0, 8},
+        { 13000000, 1700000000, 915,  7,  0, 8},        /* actual: 1699.2 MHz */
+        { 16800000, 1700000000, 708,  7,  0, 8},        /* actual: 1699.2 MHz */
+        { 19200000, 1700000000, 885,  10, 0, 8},        /* actual: 1699.2 MHz */
+        { 26000000, 1700000000, 850,  13, 0, 8},
 
         /* 1.6 GHz */
-        { 12000000, 1600000000, 800,  6,  1, 8},
-        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
-        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
-        { 19200000, 1600000000, 500,  6,  1, 8},
-        { 26000000, 1600000000, 800,  13, 1, 8},
+        { 12000000, 1600000000, 800,  6,  0, 8},
+        { 13000000, 1600000000, 738,  6,  0, 8},        /* actual: 1599.0 MHz */
+        { 16800000, 1600000000, 857,  9,  0, 8},        /* actual: 1599.7 MHz */
+        { 19200000, 1600000000, 500,  6,  0, 8},
+        { 26000000, 1600000000, 800,  13, 0, 8},
 
         /* 1.5 GHz */
-        { 12000000, 1500000000, 750,  6,  1, 8},
-        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
-        { 16800000, 1500000000, 625,  7,  1, 8},
-        { 19200000, 1500000000, 625,  8,  1, 8},
-        { 26000000, 1500000000, 750,  13, 1, 8},
+        { 12000000, 1500000000, 750,  6,  0, 8},
+        { 13000000, 1500000000, 923,  8,  0, 8},        /* actual: 1499.8 MHz */
+        { 16800000, 1500000000, 625,  7,  0, 8},
+        { 19200000, 1500000000, 625,  8,  0, 8},
+        { 26000000, 1500000000, 750,  13, 0, 8},
 
         /* 1.4 GHz */
-        { 12000000, 1400000000, 700,  6,  1, 8},
-        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
-        { 16800000, 1400000000, 1000, 12, 1, 8},
-        { 19200000, 1400000000, 875,  12, 1, 8},
-        { 26000000, 1400000000, 700,  13, 1, 8},
+        { 12000000, 1400000000, 700,  6,  0, 8},
+        { 13000000, 1400000000, 969,  9,  0, 8},        /* actual: 1399.7 MHz */
+        { 16800000, 1400000000, 1000, 12, 0, 8},
+        { 19200000, 1400000000, 875,  12, 0, 8},
+        { 26000000, 1400000000, 700,  13, 0, 8},
 
         /* 1.3 GHz */
-        { 12000000, 1300000000, 975,  9,  1, 8},
-        { 13000000, 1300000000, 1000, 10, 1, 8},
-        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 26000000, 1300000000, 650,  13, 1, 8},
+        { 12000000, 1300000000, 975,  9,  0, 8},
+        { 13000000, 1300000000, 1000, 10, 0, 8},
+        { 16800000, 1300000000, 928,  12, 0, 8},        /* actual: 1299.2 MHz */
+        { 19200000, 1300000000, 812,  12, 0, 8},        /* actual: 1299.2 MHz */
+        { 26000000, 1300000000, 650,  13, 0, 8},
 
         /* 1.2 GHz */
-        { 12000000, 1200000000, 1000, 10, 1, 8},
-        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
-        { 16800000, 1200000000, 1000, 14, 1, 8},
-        { 19200000, 1200000000, 1000, 16, 1, 8},
-        { 26000000, 1200000000, 600,  13, 1, 8},
+        { 12000000, 1200000000, 1000, 10, 0, 8},
+        { 13000000, 1200000000, 923,  10, 0, 8},        /* actual: 1199.9 MHz */
+        { 16800000, 1200000000, 1000, 14, 0, 8},
+        { 19200000, 1200000000, 1000, 16, 0, 8},
+        { 26000000, 1200000000, 600,  13, 0, 8},
 
         /* 1.1 GHz */
-        { 12000000, 1100000000, 825,  9,  1, 8},
-        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
-        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
-        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
-        { 26000000, 1100000000, 550,  13, 1, 8},
+        { 12000000, 1100000000, 825,  9,  0, 8},
+        { 13000000, 1100000000, 846,  10, 0, 8},        /* actual: 1099.8 MHz */
+        { 16800000, 1100000000, 982,  15, 0, 8},        /* actual: 1099.8 MHz */
+        { 19200000, 1100000000, 859,  15, 0, 8},        /* actual: 1099.5 MHz */
+        { 26000000, 1100000000, 550,  13, 0, 8},
 
         /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 8},
-        { 13000000, 1000000000, 1000, 13, 1, 8},
-        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 8},
+        { 12000000, 1000000000, 1000, 12, 0, 8},
+        { 13000000, 1000000000, 1000, 13, 0, 8},
+        { 16800000, 1000000000, 833,  14, 0, 8},        /* actual: 999.6 MHz */
+        { 19200000, 1000000000, 625,  12, 0, 8},
+        { 26000000, 1000000000, 1000, 26, 0, 8},
 
         { 0, 0, 0, 0, 0, 0 },
 };
@@ -552,7 +558,7 @@ static struct tegra_clk_pll_params pll_c_params = {
         .vco_max = 1400000000,
         .base_reg = PLLC_BASE,
         .misc_reg = PLLC_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -566,7 +572,7 @@ static struct tegra_clk_pll_params pll_m_params = {
         .vco_max = 1200000000,
         .base_reg = PLLM_BASE,
         .misc_reg = PLLM_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -580,7 +586,7 @@ static struct tegra_clk_pll_params pll_p_params = {
         .vco_max = 1400000000,
         .base_reg = PLLP_BASE,
         .misc_reg = PLLP_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -594,7 +600,7 @@ static struct tegra_clk_pll_params pll_a_params = {
         .vco_max = 1400000000,
         .base_reg = PLLA_BASE,
         .misc_reg = PLLA_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -608,7 +614,7 @@ static struct tegra_clk_pll_params pll_d_params = {
         .vco_max = 1000000000,
         .base_reg = PLLD_BASE,
         .misc_reg = PLLD_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
 };
@@ -622,7 +628,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
         .vco_max = 1000000000,
         .base_reg = PLLD2_BASE,
         .misc_reg = PLLD2_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
 };
@@ -636,9 +642,10 @@ static struct tegra_clk_pll_params pll_u_params = {
         .vco_max = 960000000,
         .base_reg = PLLU_BASE,
         .misc_reg = PLLU_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
         .lock_delay = 1000,
+        .pdiv_tohw = pllu_p,
 };
 
 static struct tegra_clk_pll_params pll_x_params = {
@@ -650,7 +657,7 @@ static struct tegra_clk_pll_params pll_x_params = {
         .vco_max = 1700000000,
         .base_reg = PLLX_BASE,
         .misc_reg = PLLX_MISC,
-        .lock_bit_idx = PLL_BASE_LOCK,
+        .lock_mask = PLL_BASE_LOCK,
         .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -664,7 +671,7 @@ static struct tegra_clk_pll_params pll_e_params = {
         .vco_max = 2400000000U,
         .base_reg = PLLE_BASE,
         .misc_reg = PLLE_MISC,
-        .lock_bit_idx = PLLE_MISC_LOCK,
+        .lock_mask = PLLE_MISC_LOCK,
         .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
         .lock_delay = 300,
 };
@@ -1660,7 +1667,7 @@ static void __init tegra30_periph_clk_init(void)
                 data = &tegra_periph_clk_list[i];
                 clk = tegra_clk_register_periph(data->name, data->parent_names,
                                 data->num_parents, &data->periph,
-                                clk_base, data->offset);
+                                clk_base, data->offset, data->flags);
                 clk_register_clkdev(clk, data->con_id, data->dev_id);
                 clks[data->clk_id] = clk;
         }
@@ -1910,9 +1917,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
         {disp1, pll_p, 600000000, 0},
         {disp2, pll_p, 600000000, 0},
         {twd, clk_max, 0, 1},
+        {gr2d, pll_c, 300000000, 0},
+        {gr3d, pll_c, 300000000, 0},
         {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
 };
 
+static void __init tegra30_clock_apply_init_table(void)
+{
+        tegra_init_from_table(init_table, clks, clk_max);
+}
+
 /*
  * Some clocks may be used by different drivers depending on the board
  * configuration.  List those here to register them twice in the clock lookup
@@ -1986,7 +2000,7 @@ void __init tegra30_clock_init(struct device_node *np)
         clk_data.clk_num = ARRAY_SIZE(clks);
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        tegra_init_from_table(init_table, clks, clk_max);
+        tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
 
         tegra_cpu_car_ops = &tegra30_cpu_car_ops;
 }
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a603b9af0ad3..923ca7ee4694 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -22,7 +22,8 @@
 #include "clk.h"
 
 /* Global data of Tegra CPU CAR ops */
-struct tegra_cpu_car_ops *tegra_cpu_car_ops;
+static struct tegra_cpu_car_ops dummy_car_ops;
+struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
 
 void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
                                 struct clk *clks[], int clk_max)
@@ -76,6 +77,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
 static const struct of_device_id tegra_dt_clk_match[] = {
         { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
         { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
+        { .compatible = "nvidia,tegra114-car", .data = tegra114_clock_init },
         { }
 };
 
@@ -83,3 +85,13 @@ void __init tegra_clocks_init(void)
 {
         of_clk_init(tegra_dt_clk_match);
 }
+
+tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
+
+void __init tegra_clocks_apply_init_table(void)
+{
+        if (!tegra_clk_apply_init_table)
+                return;
+
+        tegra_clk_apply_init_table();
+}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index a09d7dcaf183..e0565620d68e 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -1,4 +1,4 @@
-/*
+        /*
  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -117,6 +117,17 @@ struct tegra_clk_pll_freq_table {
 };
 
 /**
+ * struct pdiv_map - map post divider to hw value
+ *
+ * @pdiv:               post divider
+ * @hw_val:             value to be written to the PLL hw
+ */
+struct pdiv_map {
+        u8 pdiv;
+        u8 hw_val;
+};
+
+/**
  * struct clk_pll_params - PLL parameters
  *
  * @input_min:                  Minimum input frequency
@@ -143,9 +154,18 @@ struct tegra_clk_pll_params {
         u32             base_reg;
         u32             misc_reg;
         u32             lock_reg;
-        u32             lock_bit_idx;
+        u32             lock_mask;
         u32             lock_enable_bit_idx;
+        u32             iddq_reg;
+        u32             iddq_bit_idx;
+        u32             aux_reg;
+        u32             dyn_ramp_reg;
+        u32             ext_misc_reg[3];
+        int             stepa_shift;
+        int             stepb_shift;
         int             lock_delay;
+        int             max_p;
+        struct pdiv_map *pdiv_tohw;
 };
 
 /**
@@ -182,12 +202,16 @@ struct tegra_clk_pll_params {
  * TEGRA_PLL_FIXED - We are not supposed to change output frequency
  *     of some plls.
  * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
+ * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
+ *     base register.
+ * TEGRA_PLL_BYPASS - PLL has bypass bit
+ * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
  */
 struct tegra_clk_pll {
         struct clk_hw   hw;
         void __iomem    *clk_base;
         void __iomem    *pmc;
-        u8              flags;
+        u32             flags;
         unsigned long   fixed_rate;
         spinlock_t      *lock;
         u8              divn_shift;
@@ -210,20 +234,64 @@ struct tegra_clk_pll {
 #define TEGRA_PLLM BIT(5)
 #define TEGRA_PLL_FIXED BIT(6)
 #define TEGRA_PLLE_CONFIGURE BIT(7)
+#define TEGRA_PLL_LOCK_MISC BIT(8)
+#define TEGRA_PLL_BYPASS BIT(9)
+#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
 
 extern const struct clk_ops tegra_clk_pll_ops;
 extern const struct clk_ops tegra_clk_plle_ops;
 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
                 void __iomem *clk_base, void __iomem *pmc,
                 unsigned long flags, unsigned long fixed_rate,
-                struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+                struct tegra_clk_pll_params *pll_params, u32 pll_flags,
                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
+
 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
                 void __iomem *clk_base, void __iomem *pmc,
                 unsigned long flags, unsigned long fixed_rate,
-                struct tegra_clk_pll_params *pll_params, u8 pll_flags,
+                struct tegra_clk_pll_params *pll_params, u32 pll_flags,
                 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
 
+struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
+                            void __iomem *clk_base, void __iomem *pmc,
+                            unsigned long flags, unsigned long fixed_rate,
+                            struct tegra_clk_pll_params *pll_params,
+                            u32 pll_flags,
+                            struct tegra_clk_pll_freq_table *freq_table,
+                            spinlock_t *lock);
+
+struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
+                           void __iomem *clk_base, void __iomem *pmc,
+                           unsigned long flags, unsigned long fixed_rate,
+                           struct tegra_clk_pll_params *pll_params,
+                           u32 pll_flags,
+                           struct tegra_clk_pll_freq_table *freq_table,
+                           spinlock_t *lock);
+
+struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
+                           void __iomem *clk_base, void __iomem *pmc,
+                           unsigned long flags, unsigned long fixed_rate,
+                           struct tegra_clk_pll_params *pll_params,
+                           u32 pll_flags,
+                           struct tegra_clk_pll_freq_table *freq_table,
+                           spinlock_t *lock);
+
+struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
+                           void __iomem *clk_base, void __iomem *pmc,
+                           unsigned long flags, unsigned long fixed_rate,
+                           struct tegra_clk_pll_params *pll_params,
+                           u32 pll_flags,
+                           struct tegra_clk_pll_freq_table *freq_table,
+                           spinlock_t *lock, unsigned long parent_rate);
+
+struct clk *tegra_clk_register_plle_tegra114(const char *name,
+                                const char *parent_name,
+                                void __iomem *clk_base, unsigned long flags,
+                                unsigned long fixed_rate,
+                                struct tegra_clk_pll_params *pll_params,
+                                struct tegra_clk_pll_freq_table *freq_table,
+                                spinlock_t *lock);
+
 /**
  * struct tegra_clk_pll_out - PLL divider down clock
  *
@@ -290,6 +358,7 @@ struct tegra_clk_periph_regs {
  * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
  *     bus to flush the write operation in apb bus. This flag indicates
  *     that this peripheral is in apb bus.
+ * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
  */
 struct tegra_clk_periph_gate {
         u32                     magic;
@@ -309,6 +378,7 @@ struct tegra_clk_periph_gate {
 #define TEGRA_PERIPH_NO_RESET BIT(0)
 #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
 #define TEGRA_PERIPH_ON_APB BIT(2)
+#define TEGRA_PERIPH_WAR_1005168 BIT(3)
 
 void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
 extern const struct clk_ops tegra_clk_periph_gate_ops;
@@ -349,7 +419,7 @@ extern const struct clk_ops tegra_clk_periph_ops;
 struct clk *tegra_clk_register_periph(const char *name,
                 const char **parent_names, int num_parents,
                 struct tegra_clk_periph *periph, void __iomem *clk_base,
-                u32 offset);
+                u32 offset, unsigned long flags);
 struct clk *tegra_clk_register_periph_nodiv(const char *name,
                 const char **parent_names, int num_parents,
                 struct tegra_clk_periph *periph, void __iomem *clk_base,
@@ -392,12 +462,14 @@ struct tegra_periph_init_data {
         u32 offset;
         const char *con_id;
         const char *dev_id;
+        unsigned long flags;
 };
 
 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
                         _mux_shift, _mux_mask, _mux_flags, _div_shift,  \
                         _div_width, _div_frac_width, _div_flags, _regs, \
-                        _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \
+                        _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\
+                        _flags) \
         {                                                               \
                 .name = _name,                                          \
                 .clk_id = _clk_id,                                      \
@@ -412,6 +484,7 @@ struct tegra_periph_init_data {
                 .offset = _offset,                                      \
                 .con_id = _con_id,                                      \
                 .dev_id = _dev_id,                                      \
+                .flags = _flags                                         \
         }
 
 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
@@ -422,7 +495,7 @@ struct tegra_periph_init_data {
                         _mux_shift, BIT(_mux_width) - 1, _mux_flags,    \
                         _div_shift, _div_width, _div_frac_width, _div_flags, \
                         _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
-                        NULL)
+                        NULL, 0)
 
 /**
  * struct clk_super_mux - super clock
@@ -510,4 +583,13 @@ void tegra30_clock_init(struct device_node *np);
 static inline void tegra30_clock_init(struct device_node *np) {}
 #endif /* CONFIG_ARCH_TEGRA_3x_SOC */
 
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+void tegra114_clock_init(struct device_node *np);
+#else
+static inline void tegra114_clock_init(struct device_node *np) {}
+#endif /* CONFIG_ARCH_TEGRA114_SOC */
+
+typedef void (*tegra_clk_apply_init_table_func)(void);
+extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
+
 #endif /* TEGRA_CLK_H */
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 9002185a0a1a..7bc6e51757ee 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -31,6 +31,9 @@ config SUN4I_TIMER
 config VT8500_TIMER
         bool
 
+config CADENCE_TTC_TIMER
+        bool
+
 config CLKSRC_NOMADIK_MTU
         bool
         depends on (ARCH_NOMADIK || ARCH_U8500)
@@ -67,3 +70,8 @@ config CLKSRC_METAG_GENERIC
         def_bool y if METAG
         help
           This option enables support for the Meta per-thread timers.
+
+config CLKSRC_EXYNOS_MCT
+        def_bool y if ARCH_EXYNOS
+        help
+          Support for Multi Core Timer controller on Exynos SoCs.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 682d48d08164..caacdb63aff9 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -23,6 +23,8 @@ obj-$(CONFIG_SUN4I_TIMER)	+= sun4i_timer.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)      += vt8500_timer.o
 obj-$(CONFIG_ARCH_BCM)          += bcm_kona_timer.o
+obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o
+obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)            += arm_arch_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)      += metag_generic.o
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
new file mode 100644
index 000000000000..685bc60e210a
--- /dev/null
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -0,0 +1,436 @@
+/*
+ * This file contains driver for the Cadence Triple Timer Counter Rev 06
+ *
+ *  Copyright (C) 2011-2013 Xilinx
+ *
+ * based on arch/mips/kernel/time.c timer driver
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+
+/*
+ * This driver configures the 2 16-bit count-up timers as follows:
+ *
+ * T1: Timer 1, clocksource for generic timekeeping
+ * T2: Timer 2, clockevent source for hrtimers
+ * T3: Timer 3, <unused>
+ *
+ * The input frequency to the timer module for emulation is 2.5MHz which is
+ * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
+ * the timers are clocked at 78.125KHz (12.8 us resolution).
+
+ * The input frequency to the timer module in silicon is configurable and
+ * obtained from device tree. The pre-scaler of 32 is used.
+ */
+
+/*
+ * Timer Register Offset Definitions of Timer 1, Increment base address by 4
+ * and use same offsets for Timer 2
+ */
+#define TTC_CLK_CNTRL_OFFSET            0x00 /* Clock Control Reg, RW */
+#define TTC_CNT_CNTRL_OFFSET            0x0C /* Counter Control Reg, RW */
+#define TTC_COUNT_VAL_OFFSET            0x18 /* Counter Value Reg, RO */
+#define TTC_INTR_VAL_OFFSET             0x24 /* Interval Count Reg, RW */
+#define TTC_ISR_OFFSET          0x54 /* Interrupt Status Reg, RO */
+#define TTC_IER_OFFSET          0x60 /* Interrupt Enable Reg, RW */
+
+#define TTC_CNT_CNTRL_DISABLE_MASK      0x1
+
+/*
+ * Setup the timers to use pre-scaling, using a fixed value for now that will
+ * work across most input frequency, but it may need to be more dynamic
+ */
+#define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
+#define PRESCALE                2048    /* The exponent must match this */
+#define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
+#define CLK_CNTRL_PRESCALE_EN   1
+#define CNT_CNTRL_RESET         (1 << 4)
+
+/**
+ * struct ttc_timer - This definition defines local timer structure
+ *
+ * @base_addr:  Base address of timer
+ * @clk:        Associated clock source
+ * @clk_rate_change_nb  Notifier block for clock rate changes
+ */
+struct ttc_timer {
+        void __iomem *base_addr;
+        struct clk *clk;
+        struct notifier_block clk_rate_change_nb;
+};
+
+#define to_ttc_timer(x) \
+                container_of(x, struct ttc_timer, clk_rate_change_nb)
+
+struct ttc_timer_clocksource {
+        struct ttc_timer        ttc;
+        struct clocksource      cs;
+};
+
+#define to_ttc_timer_clksrc(x) \
+                container_of(x, struct ttc_timer_clocksource, cs)
+
+struct ttc_timer_clockevent {
+        struct ttc_timer                ttc;
+        struct clock_event_device       ce;
+};
+
+#define to_ttc_timer_clkevent(x) \
+                container_of(x, struct ttc_timer_clockevent, ce)
+
+/**
+ * ttc_set_interval - Set the timer interval value
+ *
+ * @timer:      Pointer to the timer instance
+ * @cycles:     Timer interval ticks
+ **/
+static void ttc_set_interval(struct ttc_timer *timer,
+                                        unsigned long cycles)
+{
+        u32 ctrl_reg;
+
+        /* Disable the counter, set the counter value  and re-enable counter */
+        ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
+        ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
+        __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
+
+        __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
+
+        /*
+         * Reset the counter (0x10) so that it starts from 0, one-shot
+         * mode makes this needed for timing to be right.
+         */
+        ctrl_reg |= CNT_CNTRL_RESET;
+        ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
+        __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
+}
+
+/**
+ * ttc_clock_event_interrupt - Clock event timer interrupt handler
+ *
+ * @irq:        IRQ number of the Timer
+ * @dev_id:     void pointer to the ttc_timer instance
+ *
+ * returns: Always IRQ_HANDLED - success
+ **/
+static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
+{
+        struct ttc_timer_clockevent *ttce = dev_id;
+        struct ttc_timer *timer = &ttce->ttc;
+
+        /* Acknowledge the interrupt and call event handler */
+        __raw_readl(timer->base_addr + TTC_ISR_OFFSET);
+
+        ttce->ce.event_handler(&ttce->ce);
+
+        return IRQ_HANDLED;
+}
+
+/**
+ * __ttc_clocksource_read - Reads the timer counter register
+ *
+ * returns: Current timer counter register value
+ **/
+static cycle_t __ttc_clocksource_read(struct clocksource *cs)
+{
+        struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
+
+        return (cycle_t)__raw_readl(timer->base_addr +
+                                TTC_COUNT_VAL_OFFSET);
+}
+
+/**
+ * ttc_set_next_event - Sets the time interval for next event
+ *
+ * @cycles:     Timer interval ticks
+ * @evt:        Address of clock event instance
+ *
+ * returns: Always 0 - success
+ **/
+static int ttc_set_next_event(unsigned long cycles,
+                                        struct clock_event_device *evt)
+{
+        struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
+        struct ttc_timer *timer = &ttce->ttc;
+
+        ttc_set_interval(timer, cycles);
+        return 0;
+}
+
+/**
+ * ttc_set_mode - Sets the mode of timer
+ *
+ * @mode:       Mode to be set
+ * @evt:        Address of clock event instance
+ **/
+static void ttc_set_mode(enum clock_event_mode mode,
+                                        struct clock_event_device *evt)
+{
+        struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
+        struct ttc_timer *timer = &ttce->ttc;
+        u32 ctrl_reg;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                ttc_set_interval(timer,
+                                DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk),
+                                        PRESCALE * HZ));
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                ctrl_reg = __raw_readl(timer->base_addr +
+                                        TTC_CNT_CNTRL_OFFSET);
+                ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
+                __raw_writel(ctrl_reg,
+                                timer->base_addr + TTC_CNT_CNTRL_OFFSET);
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                ctrl_reg = __raw_readl(timer->base_addr +
+                                        TTC_CNT_CNTRL_OFFSET);
+                ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
+                __raw_writel(ctrl_reg,
+                                timer->base_addr + TTC_CNT_CNTRL_OFFSET);
+                break;
+        }
+}
+
+static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
+                unsigned long event, void *data)
+{
+        struct clk_notifier_data *ndata = data;
+        struct ttc_timer *ttc = to_ttc_timer(nb);
+        struct ttc_timer_clocksource *ttccs = container_of(ttc,
+                        struct ttc_timer_clocksource, ttc);
+
+        switch (event) {
+        case POST_RATE_CHANGE:
+                /*
+                 * Do whatever is necessary to maintain a proper time base
+                 *
+                 * I cannot find a way to adjust the currently used clocksource
+                 * to the new frequency. __clocksource_updatefreq_hz() sounds
+                 * good, but does not work. Not sure what's that missing.
+                 *
+                 * This approach works, but triggers two clocksource switches.
+                 * The first after unregister to clocksource jiffies. And
+                 * another one after the register to the newly registered timer.
+                 *
+                 * Alternatively we could 'waste' another HW timer to ping pong
+                 * between clock sources. That would also use one register and
+                 * one unregister call, but only trigger one clocksource switch
+                 * for the cost of another HW timer used by the OS.
+                 */
+                clocksource_unregister(&ttccs->cs);
+                clocksource_register_hz(&ttccs->cs,
+                                ndata->new_rate / PRESCALE);
+                /* fall through */
+        case PRE_RATE_CHANGE:
+        case ABORT_RATE_CHANGE:
+        default:
+                return NOTIFY_DONE;
+        }
+}
+
+static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
+{
+        struct ttc_timer_clocksource *ttccs;
+        int err;
+
+        ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
+        if (WARN_ON(!ttccs))
+                return;
+
+        ttccs->ttc.clk = clk;
+
+        err = clk_prepare_enable(ttccs->ttc.clk);
+        if (WARN_ON(err)) {
+                kfree(ttccs);
+                return;
+        }
+
+        ttccs->ttc.clk_rate_change_nb.notifier_call =
+                ttc_rate_change_clocksource_cb;
+        ttccs->ttc.clk_rate_change_nb.next = NULL;
+        if (clk_notifier_register(ttccs->ttc.clk,
+                                &ttccs->ttc.clk_rate_change_nb))
+                pr_warn("Unable to register clock notifier.\n");
+
+        ttccs->ttc.base_addr = base;
+        ttccs->cs.name = "ttc_clocksource";
+        ttccs->cs.rating = 200;
+        ttccs->cs.read = __ttc_clocksource_read;
+        ttccs->cs.mask = CLOCKSOURCE_MASK(16);
+        ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
+
+        /*
+         * Setup the clock source counter to be an incrementing counter
+         * with no interrupt and it rolls over at 0xFFFF. Pre-scale
+         * it by 32 also. Let it start running now.
+         */
+        __raw_writel(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
+        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
+                     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
+        __raw_writel(CNT_CNTRL_RESET,
+                     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
+
+        err = clocksource_register_hz(&ttccs->cs,
+                        clk_get_rate(ttccs->ttc.clk) / PRESCALE);
+        if (WARN_ON(err)) {
+                kfree(ttccs);
+                return;
+        }
+}
+
+static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
+                unsigned long event, void *data)
+{
+        struct clk_notifier_data *ndata = data;
+        struct ttc_timer *ttc = to_ttc_timer(nb);
+        struct ttc_timer_clockevent *ttcce = container_of(ttc,
+                        struct ttc_timer_clockevent, ttc);
+
+        switch (event) {
+        case POST_RATE_CHANGE:
+        {
+                unsigned long flags;
+
+                /*
+                 * clockevents_update_freq should be called with IRQ disabled on
+                 * the CPU the timer provides events for. The timer we use is
+                 * common to both CPUs, not sure if we need to run on both
+                 * cores.
+                 */
+                local_irq_save(flags);
+                clockevents_update_freq(&ttcce->ce,
+                                ndata->new_rate / PRESCALE);
+                local_irq_restore(flags);
+
+                /* fall through */
+        }
+        case PRE_RATE_CHANGE:
+        case ABORT_RATE_CHANGE:
+        default:
+                return NOTIFY_DONE;
+        }
+}
+
+static void __init ttc_setup_clockevent(struct clk *clk,
+                                                void __iomem *base, u32 irq)
+{
+        struct ttc_timer_clockevent *ttcce;
+        int err;
+
+        ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
+        if (WARN_ON(!ttcce))
+                return;
+
+        ttcce->ttc.clk = clk;
+
+        err = clk_prepare_enable(ttcce->ttc.clk);
+        if (WARN_ON(err)) {
+                kfree(ttcce);
+                return;
+        }
+
+        ttcce->ttc.clk_rate_change_nb.notifier_call =
+                ttc_rate_change_clockevent_cb;
+        ttcce->ttc.clk_rate_change_nb.next = NULL;
+        if (clk_notifier_register(ttcce->ttc.clk,
+                                &ttcce->ttc.clk_rate_change_nb))
+                pr_warn("Unable to register clock notifier.\n");
+
+        ttcce->ttc.base_addr = base;
+        ttcce->ce.name = "ttc_clockevent";
+        ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+        ttcce->ce.set_next_event = ttc_set_next_event;
+        ttcce->ce.set_mode = ttc_set_mode;
+        ttcce->ce.rating = 200;
+        ttcce->ce.irq = irq;
+        ttcce->ce.cpumask = cpu_possible_mask;
+
+        /*
+         * Setup the clock event timer to be an interval timer which
+         * is prescaled by 32 using the interval interrupt. Leave it
+         * disabled for now.
+         */
+        __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
+        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
+                     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
+        __raw_writel(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
+
+        err = request_irq(irq, ttc_clock_event_interrupt,
+                          IRQF_DISABLED | IRQF_TIMER,
+                          ttcce->ce.name, ttcce);
+        if (WARN_ON(err)) {
+                kfree(ttcce);
+                return;
+        }
+
+        clockevents_config_and_register(&ttcce->ce,
+                        clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe);
+}
+
+/**
+ * ttc_timer_init - Initialize the timer
+ *
+ * Initializes the timer hardware and register the clock source and clock event
+ * timers with Linux kernal timer framework
+ */
+static void __init ttc_timer_init(struct device_node *timer)
+{
+        unsigned int irq;
+        void __iomem *timer_baseaddr;
+        struct clk *clk;
+        static int initialized;
+
+        if (initialized)
+                return;
+
+        initialized = 1;
+
+        /*
+         * Get the 1st Triple Timer Counter (TTC) block from the device tree
+         * and use it. Note that the event timer uses the interrupt and it's the
+         * 2nd TTC hence the irq_of_parse_and_map(,1)
+         */
+        timer_baseaddr = of_iomap(timer, 0);
+        if (!timer_baseaddr) {
+                pr_err("ERROR: invalid timer base address\n");
+                BUG();
+        }
+
+        irq = irq_of_parse_and_map(timer, 1);
+        if (irq <= 0) {
+                pr_err("ERROR: invalid interrupt number\n");
+                BUG();
+        }
+
+        clk = of_clk_get_by_name(timer, "cpu_1x");
+        if (IS_ERR(clk)) {
+                pr_err("ERROR: timer input clock not found\n");
+                BUG();
+        }
+
+        ttc_setup_clocksource(clk, timer_baseaddr);
+        ttc_setup_clockevent(clk, timer_baseaddr + 4, irq);
+
+        pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
+}
+
+CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
diff --git a/drivers/clocksource/em_sti.c b/drivers/clocksource/em_sti.c
index e6a553cb73e8..4329a29a5310 100644
--- a/drivers/clocksource/em_sti.c
+++ b/drivers/clocksource/em_sti.c
@@ -399,7 +399,18 @@ static struct platform_driver em_sti_device_driver = {
         }
 };
 
-module_platform_driver(em_sti_device_driver);
+static int __init em_sti_init(void)
+{
+        return platform_driver_register(&em_sti_device_driver);
+}
+
+static void __exit em_sti_exit(void)
+{
+        platform_driver_unregister(&em_sti_device_driver);
+}
+
+subsys_initcall(em_sti_init);
+module_exit(em_sti_exit);
 
 MODULE_AUTHOR("Magnus Damm");
 MODULE_DESCRIPTION("Renesas Emma Mobile STI Timer Driver");
diff --git a/arch/arm/mach-exynos/mct.c b/drivers/clocksource/exynos_mct.c
index c9d6650f9b5d..661026834b23 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -20,6 +20,9 @@
 #include <linux/delay.h>
 #include <linux/percpu.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/clocksource.h>
 
 #include <asm/arch_timer.h>
 #include <asm/localtimer.h>
@@ -28,9 +31,36 @@
 
 #include <mach/map.h>
 #include <mach/irqs.h>
-#include <mach/regs-mct.h>
 #include <asm/mach/time.h>
 
+#define EXYNOS4_MCTREG(x)               (x)
+#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
+#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
+#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
+#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
+#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
+#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
+#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
+#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
+#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
+#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
+#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK              (0xffffff00)
+
+#define MCT_L_TCNTB_OFFSET              (0x00)
+#define MCT_L_ICNTB_OFFSET              (0x08)
+#define MCT_L_TCON_OFFSET               (0x20)
+#define MCT_L_INT_CSTAT_OFFSET          (0x30)
+#define MCT_L_INT_ENB_OFFSET            (0x34)
+#define MCT_L_WSTAT_OFFSET              (0x40)
+#define MCT_G_TCON_START                (1 << 8)
+#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
+#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
+#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
+#define MCT_L_TCON_INT_START            (1 << 1)
+#define MCT_L_TCON_TIMER_START          (1 << 0)
+
 #define TICK_BASE_CNT   1
 
 enum {
@@ -38,64 +68,75 @@ enum {
         MCT_INT_PPI
 };
 
+enum {
+        MCT_G0_IRQ,
+        MCT_G1_IRQ,
+        MCT_G2_IRQ,
+        MCT_G3_IRQ,
+        MCT_L0_IRQ,
+        MCT_L1_IRQ,
+        MCT_L2_IRQ,
+        MCT_L3_IRQ,
+        MCT_NR_IRQS,
+};
+
+static void __iomem *reg_base;
 static unsigned long clk_rate;
 static unsigned int mct_int_type;
+static int mct_irqs[MCT_NR_IRQS];
 
 struct mct_clock_event_device {
         struct clock_event_device *evt;
-        void __iomem *base;
+        unsigned long base;
         char name[10];
 };
 
-static void exynos4_mct_write(unsigned int value, void *addr)
+static void exynos4_mct_write(unsigned int value, unsigned long offset)
 {
-        void __iomem *stat_addr;
+        unsigned long stat_addr;
         u32 mask;
         u32 i;
 
-        __raw_writel(value, addr);
+        __raw_writel(value, reg_base + offset);
 
-        if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
-                u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
-                switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
-                case (u32) MCT_L_TCON_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+        if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
+                stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
+                switch (offset & EXYNOS4_MCT_L_MASK) {
+                case MCT_L_TCON_OFFSET:
                         mask = 1 << 3;          /* L_TCON write status */
                         break;
-                case (u32) MCT_L_ICNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                case MCT_L_ICNTB_OFFSET:
                         mask = 1 << 1;          /* L_ICNTB write status */
                         break;
-                case (u32) MCT_L_TCNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                case MCT_L_TCNTB_OFFSET:
                         mask = 1 << 0;          /* L_TCNTB write status */
                         break;
                 default:
                         return;
                 }
         } else {
-                switch ((u32) addr) {
-                case (u32) EXYNOS4_MCT_G_TCON:
+                switch (offset) {
+                case EXYNOS4_MCT_G_TCON:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 16;         /* G_TCON write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_COMP0_L:
+                case EXYNOS4_MCT_G_COMP0_L:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 0;          /* G_COMP0_L write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_COMP0_U:
+                case EXYNOS4_MCT_G_COMP0_U:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 1;          /* G_COMP0_U write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+                case EXYNOS4_MCT_G_COMP0_ADD_INCR:
                         stat_addr = EXYNOS4_MCT_G_WSTAT;
                         mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
                         break;
-                case (u32) EXYNOS4_MCT_G_CNT_L:
+                case EXYNOS4_MCT_G_CNT_L:
                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
                         mask = 1 << 0;          /* G_CNT_L write status */
                         break;
-                case (u32) EXYNOS4_MCT_G_CNT_U:
+                case EXYNOS4_MCT_G_CNT_U:
                         stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
                         mask = 1 << 1;          /* G_CNT_U write status */
                         break;
@@ -106,12 +147,12 @@ static void exynos4_mct_write(unsigned int value, void *addr)
 
         /* Wait maximum 1 ms until written values are applied */
         for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
-                if (__raw_readl(stat_addr) & mask) {
-                        __raw_writel(mask, stat_addr);
+                if (__raw_readl(reg_base + stat_addr) & mask) {
+                        __raw_writel(mask, reg_base + stat_addr);
                         return;
                 }
 
-        panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
+        panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
 }
 
 /* Clocksource handling */
@@ -122,7 +163,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
         exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
         exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
 
-        reg = __raw_readl(EXYNOS4_MCT_G_TCON);
+        reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
         reg |= MCT_G_TCON_START;
         exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
 }
@@ -130,12 +171,12 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
 static cycle_t exynos4_frc_read(struct clocksource *cs)
 {
         unsigned int lo, hi;
-        u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+        u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
 
         do {
                 hi = hi2;
-                lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
-                hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
+                lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
+                hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
         } while (hi != hi2);
 
         return ((cycle_t)hi << 32) | lo;
@@ -167,7 +208,7 @@ static void exynos4_mct_comp0_stop(void)
 {
         unsigned int tcon;
 
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+        tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
         tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
 
         exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
@@ -180,7 +221,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode,
         unsigned int tcon;
         cycle_t comp_cycle;
 
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
+        tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
 
         if (mode == CLOCK_EVT_MODE_PERIODIC) {
                 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
@@ -257,11 +298,7 @@ static void exynos4_clockevent_init(void)
         mct_comp_device.cpumask = cpumask_of(0);
         clockevents_config_and_register(&mct_comp_device, clk_rate,
                                         0xf, 0xffffffff);
-
-        if (soc_is_exynos5250())
-                setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
-        else
-                setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
+        setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
 }
 
 #ifdef CONFIG_LOCAL_TIMERS
@@ -273,12 +310,12 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
 {
         unsigned long tmp;
         unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
-        void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
+        unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
 
-        tmp = __raw_readl(addr);
+        tmp = __raw_readl(reg_base + offset);
         if (tmp & mask) {
                 tmp &= ~mask;
-                exynos4_mct_write(tmp, addr);
+                exynos4_mct_write(tmp, offset);
         }
 }
 
@@ -297,7 +334,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
         /* enable MCT tick interrupt */
         exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
 
-        tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
+        tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
         tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
                MCT_L_TCON_INTERVAL_MODE;
         exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
@@ -349,7 +386,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
                 exynos4_mct_tick_stop(mevt);
 
         /* Clear the MCT tick interrupt */
-        if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+        if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
                 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
                 return 1;
         } else {
@@ -385,7 +422,6 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 {
         struct mct_clock_event_device *mevt;
         unsigned int cpu = smp_processor_id();
-        int mct_lx_irq;
 
         mevt = this_cpu_ptr(&percpu_mct_tick);
         mevt->evt = evt;
@@ -406,21 +442,17 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 
         if (mct_int_type == MCT_INT_SPI) {
                 if (cpu == 0) {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
-                                                EXYNOS5_IRQ_MCT_L0;
                         mct_tick0_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick0_event_irq);
+                        evt->irq = mct_irqs[MCT_L0_IRQ];
+                        setup_irq(evt->irq, &mct_tick0_event_irq);
                 } else {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
-                                                EXYNOS5_IRQ_MCT_L1;
                         mct_tick1_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick1_event_irq);
-                        irq_set_affinity(mct_lx_irq, cpumask_of(1));
+                        evt->irq = mct_irqs[MCT_L1_IRQ];
+                        setup_irq(evt->irq, &mct_tick1_event_irq);
+                        irq_set_affinity(evt->irq, cpumask_of(1));
                 }
         } else {
-                enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
+                enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
         }
 
         return 0;
@@ -436,7 +468,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt)
                 else
                         remove_irq(evt->irq, &mct_tick1_event_irq);
         else
-                disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
+                disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
 }
 
 static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
@@ -445,41 +477,92 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
 };
 #endif /* CONFIG_LOCAL_TIMERS */
 
-static void __init exynos4_timer_resources(void)
+static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
 {
-        struct clk *mct_clk;
-        mct_clk = clk_get(NULL, "xtal");
+        struct clk *mct_clk, *tick_clk;
+
+        tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
+                                clk_get(NULL, "fin_pll");
+        if (IS_ERR(tick_clk))
+                panic("%s: unable to determine tick clock rate\n", __func__);
+        clk_rate = clk_get_rate(tick_clk);
 
-        clk_rate = clk_get_rate(mct_clk);
+        mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
+        if (IS_ERR(mct_clk))
+                panic("%s: unable to retrieve mct clock instance\n", __func__);
+        clk_prepare_enable(mct_clk);
+
+        reg_base = base;
+        if (!reg_base)
+                panic("%s: unable to ioremap mct address space\n", __func__);
 
 #ifdef CONFIG_LOCAL_TIMERS
         if (mct_int_type == MCT_INT_PPI) {
                 int err;
 
-                err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
+                err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
                                          exynos4_mct_tick_isr, "MCT",
                                          &percpu_mct_tick);
                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
-                     EXYNOS_IRQ_MCT_LOCALTIMER, err);
+                     mct_irqs[MCT_L0_IRQ], err);
         }
 
         local_timer_register(&exynos4_mct_tick_ops);
 #endif /* CONFIG_LOCAL_TIMERS */
 }
 
-void __init exynos4_timer_init(void)
+void __init mct_init(void)
 {
-        if (soc_is_exynos5440()) {
-                arch_timer_of_register();
-                return;
+        if (soc_is_exynos4210()) {
+                mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
+                mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
+                mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
+                mct_int_type = MCT_INT_SPI;
+        } else {
+                panic("unable to determine mct controller type\n");
         }
 
-        if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
-                mct_int_type = MCT_INT_SPI;
-        else
-                mct_int_type = MCT_INT_PPI;
+        exynos4_timer_resources(NULL, S5P_VA_SYSTIMER);
+        exynos4_clocksource_init();
+        exynos4_clockevent_init();
+}
+
+static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
+{
+        u32 nr_irqs, i;
+
+        mct_int_type = int_type;
 
-        exynos4_timer_resources();
+        /* This driver uses only one global timer interrupt */
+        mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
+
+        /*
+         * Find out the number of local irqs specified. The local
+         * timer irqs are specified after the four global timer
+         * irqs are specified.
+         */
+#ifdef CONFIG_OF
+        nr_irqs = of_irq_count(np);
+#else
+        nr_irqs = 0;
+#endif
+        for (i = MCT_L0_IRQ; i < nr_irqs; i++)
+                mct_irqs[i] = irq_of_parse_and_map(np, i);
+
+        exynos4_timer_resources(np, of_iomap(np, 0));
         exynos4_clocksource_init();
         exynos4_clockevent_init();
 }
+
+
+static void __init mct_init_spi(struct device_node *np)
+{
+        return mct_init_dt(np, MCT_INT_SPI);
+}
+
+static void __init mct_init_ppi(struct device_node *np)
+{
+        return mct_init_dt(np, MCT_INT_PPI);
+}
+CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
+CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 488c14cc8dbf..08d0c418c94a 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -54,62 +54,100 @@ struct sh_cmt_priv {
         struct clocksource cs;
         unsigned long total_cycles;
         bool cs_enabled;
+
+        /* callbacks for CMSTR and CMCSR access */
+        unsigned long (*read_control)(void __iomem *base, unsigned long offs);
+        void (*write_control)(void __iomem *base, unsigned long offs,
+                              unsigned long value);
+
+        /* callbacks for CMCNT and CMCOR access */
+        unsigned long (*read_count)(void __iomem *base, unsigned long offs);
+        void (*write_count)(void __iomem *base, unsigned long offs,
+                            unsigned long value);
 };
 
-static DEFINE_RAW_SPINLOCK(sh_cmt_lock);
+/* Examples of supported CMT timer register layouts and I/O access widths:
+ *
+ * "16-bit counter and 16-bit control" as found on sh7263:
+ * CMSTR 0xfffec000 16-bit
+ * CMCSR 0xfffec002 16-bit
+ * CMCNT 0xfffec004 16-bit
+ * CMCOR 0xfffec006 16-bit
+ *
+ * "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740:
+ * CMSTR 0xffca0000 16-bit
+ * CMCSR 0xffca0060 16-bit
+ * CMCNT 0xffca0064 32-bit
+ * CMCOR 0xffca0068 32-bit
+ */
+
+static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
+{
+        return ioread16(base + (offs << 1));
+}
+
+static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
+{
+        return ioread32(base + (offs << 2));
+}
+
+static void sh_cmt_write16(void __iomem *base, unsigned long offs,
+                           unsigned long value)
+{
+        iowrite16(value, base + (offs << 1));
+}
+
+static void sh_cmt_write32(void __iomem *base, unsigned long offs,
+                           unsigned long value)
+{
+        iowrite32(value, base + (offs << 2));
+}
 
-#define CMSTR -1 /* shared register */
 #define CMCSR 0 /* channel register */
 #define CMCNT 1 /* channel register */
 #define CMCOR 2 /* channel register */
 
-static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
+static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_priv *p)
 {
         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
-        void __iomem *base = p->mapbase;
-        unsigned long offs;
-
-        if (reg_nr == CMSTR) {
-                offs = 0;
-                base -= cfg->channel_offset;
-        } else
-                offs = reg_nr;
-
-        if (p->width == 16)
-                offs <<= 1;
-        else {
-                offs <<= 2;
-                if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
-                        return ioread32(base + offs);
-        }
 
-        return ioread16(base + offs);
+        return p->read_control(p->mapbase - cfg->channel_offset, 0);
 }
 
-static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
-                                unsigned long value)
+static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_priv *p)
+{
+        return p->read_control(p->mapbase, CMCSR);
+}
+
+static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_priv *p)
+{
+        return p->read_count(p->mapbase, CMCNT);
+}
+
+static inline void sh_cmt_write_cmstr(struct sh_cmt_priv *p,
+                                      unsigned long value)
 {
         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
-        void __iomem *base = p->mapbase;
-        unsigned long offs;
-
-        if (reg_nr == CMSTR) {
-                offs = 0;
-                base -= cfg->channel_offset;
-        } else
-                offs = reg_nr;
-
-        if (p->width == 16)
-                offs <<= 1;
-        else {
-                offs <<= 2;
-                if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
-                        iowrite32(value, base + offs);
-                        return;
-                }
-        }
 
-        iowrite16(value, base + offs);
+        p->write_control(p->mapbase - cfg->channel_offset, 0, value);
+}
+
+static inline void sh_cmt_write_cmcsr(struct sh_cmt_priv *p,
+                                      unsigned long value)
+{
+        p->write_control(p->mapbase, CMCSR, value);
+}
+
+static inline void sh_cmt_write_cmcnt(struct sh_cmt_priv *p,
+                                      unsigned long value)
+{
+        p->write_count(p->mapbase, CMCNT, value);
+}
+
+static inline void sh_cmt_write_cmcor(struct sh_cmt_priv *p,
+                                      unsigned long value)
+{
+        p->write_count(p->mapbase, CMCOR, value);
 }
 
 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
@@ -118,15 +156,15 @@ static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
         unsigned long v1, v2, v3;
         int o1, o2;
 
-        o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
+        o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit;
 
         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
         do {
                 o2 = o1;
-                v1 = sh_cmt_read(p, CMCNT);
-                v2 = sh_cmt_read(p, CMCNT);
-                v3 = sh_cmt_read(p, CMCNT);
-                o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
+                v1 = sh_cmt_read_cmcnt(p);
+                v2 = sh_cmt_read_cmcnt(p);
+                v3 = sh_cmt_read_cmcnt(p);
+                o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit;
         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 
@@ -134,6 +172,7 @@ static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
         return v2;
 }
 
+static DEFINE_RAW_SPINLOCK(sh_cmt_lock);
 
 static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
 {
@@ -142,14 +181,14 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
 
         /* start stop register shared by multiple timer channels */
         raw_spin_lock_irqsave(&sh_cmt_lock, flags);
-        value = sh_cmt_read(p, CMSTR);
+        value = sh_cmt_read_cmstr(p);
 
         if (start)
                 value |= 1 << cfg->timer_bit;
         else
                 value &= ~(1 << cfg->timer_bit);
 
-        sh_cmt_write(p, CMSTR, value);
+        sh_cmt_write_cmstr(p, value);
         raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
 }
 
@@ -173,14 +212,14 @@ static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
         /* configure channel, periodic mode and maximum timeout */
         if (p->width == 16) {
                 *rate = clk_get_rate(p->clk) / 512;
-                sh_cmt_write(p, CMCSR, 0x43);
+                sh_cmt_write_cmcsr(p, 0x43);
         } else {
                 *rate = clk_get_rate(p->clk) / 8;
-                sh_cmt_write(p, CMCSR, 0x01a4);
+                sh_cmt_write_cmcsr(p, 0x01a4);
         }
 
-        sh_cmt_write(p, CMCOR, 0xffffffff);
-        sh_cmt_write(p, CMCNT, 0);
+        sh_cmt_write_cmcor(p, 0xffffffff);
+        sh_cmt_write_cmcnt(p, 0);
 
         /*
          * According to the sh73a0 user's manual, as CMCNT can be operated
@@ -194,12 +233,12 @@ static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
          * take RCLKx2 at maximum.
          */
         for (k = 0; k < 100; k++) {
-                if (!sh_cmt_read(p, CMCNT))
+                if (!sh_cmt_read_cmcnt(p))
                         break;
                 udelay(1);
         }
 
-        if (sh_cmt_read(p, CMCNT)) {
+        if (sh_cmt_read_cmcnt(p)) {
                 dev_err(&p->pdev->dev, "cannot clear CMCNT\n");
                 ret = -ETIMEDOUT;
                 goto err1;
@@ -222,7 +261,7 @@ static void sh_cmt_disable(struct sh_cmt_priv *p)
         sh_cmt_start_stop_ch(p, 0);
 
         /* disable interrupts in CMT block */
-        sh_cmt_write(p, CMCSR, 0);
+        sh_cmt_write_cmcsr(p, 0);
 
         /* stop clock */
         clk_disable(p->clk);
@@ -270,7 +309,7 @@ static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
                 if (new_match > p->max_match_value)
                         new_match = p->max_match_value;
 
-                sh_cmt_write(p, CMCOR, new_match);
+                sh_cmt_write_cmcor(p, new_match);
 
                 now = sh_cmt_get_counter(p, &has_wrapped);
                 if (has_wrapped && (new_match > p->match_value)) {
@@ -346,7 +385,7 @@ static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
         struct sh_cmt_priv *p = dev_id;
 
         /* clear flags */
-        sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
+        sh_cmt_write_cmcsr(p, sh_cmt_read_cmcsr(p) & p->clear_bits);
 
         /* update clock source counter to begin with if enabled
          * the wrap flag should be cleared by the timer specific
@@ -625,14 +664,6 @@ static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
                            unsigned long clockevent_rating,
                            unsigned long clocksource_rating)
 {
-        if (p->width == (sizeof(p->max_match_value) * 8))
-                p->max_match_value = ~0;
-        else
-                p->max_match_value = (1 << p->width) - 1;
-
-        p->match_value = p->max_match_value;
-        raw_spin_lock_init(&p->lock);
-
         if (clockevent_rating)
                 sh_cmt_register_clockevent(p, name, clockevent_rating);
 
@@ -657,8 +688,6 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
                 goto err0;
         }
 
-        platform_set_drvdata(pdev, p);
-
         res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
         if (!res) {
                 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
@@ -693,32 +722,51 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
                 goto err1;
         }
 
+        p->read_control = sh_cmt_read16;
+        p->write_control = sh_cmt_write16;
+
         if (resource_size(res) == 6) {
                 p->width = 16;
+                p->read_count = sh_cmt_read16;
+                p->write_count = sh_cmt_write16;
                 p->overflow_bit = 0x80;
                 p->clear_bits = ~0x80;
         } else {
                 p->width = 32;
+                p->read_count = sh_cmt_read32;
+                p->write_count = sh_cmt_write32;
                 p->overflow_bit = 0x8000;
                 p->clear_bits = ~0xc000;
         }
 
+        if (p->width == (sizeof(p->max_match_value) * 8))
+                p->max_match_value = ~0;
+        else
+                p->max_match_value = (1 << p->width) - 1;
+
+        p->match_value = p->max_match_value;
+        raw_spin_lock_init(&p->lock);
+
         ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
                               cfg->clockevent_rating,
                               cfg->clocksource_rating);
         if (ret) {
                 dev_err(&p->pdev->dev, "registration failed\n");
-                goto err1;
+                goto err2;
         }
         p->cs_enabled = false;
 
         ret = setup_irq(irq, &p->irqaction);
         if (ret) {
                 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
-                goto err1;
+                goto err2;
         }
 
+        platform_set_drvdata(pdev, p);
+
         return 0;
+err2:
+        clk_put(p->clk);
 
 err1:
         iounmap(p->mapbase);
@@ -751,7 +799,6 @@ static int sh_cmt_probe(struct platform_device *pdev)
         ret = sh_cmt_setup(p, pdev);
         if (ret) {
                 kfree(p);
-                platform_set_drvdata(pdev, NULL);
                 pm_runtime_idle(&pdev->dev);
                 return ret;
         }
@@ -791,7 +838,7 @@ static void __exit sh_cmt_exit(void)
 }
 
 early_platform_init("earlytimer", &sh_cmt_device_driver);
-module_init(sh_cmt_init);
+subsys_initcall(sh_cmt_init);
 module_exit(sh_cmt_exit);
 
 MODULE_AUTHOR("Magnus Damm");
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
index 83943e27cfac..4aac9ee0d0c0 100644
--- a/drivers/clocksource/sh_mtu2.c
+++ b/drivers/clocksource/sh_mtu2.c
@@ -386,7 +386,7 @@ static void __exit sh_mtu2_exit(void)
 }
 
 early_platform_init("earlytimer", &sh_mtu2_device_driver);
-module_init(sh_mtu2_init);
+subsys_initcall(sh_mtu2_init);
 module_exit(sh_mtu2_exit);
 
 MODULE_AUTHOR("Magnus Damm");
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index b4502edce2a1..78b8dae49628 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -549,7 +549,7 @@ static void __exit sh_tmu_exit(void)
 }
 
 early_platform_init("earlytimer", &sh_tmu_device_driver);
-module_init(sh_tmu_init);
+subsys_initcall(sh_tmu_init);
 module_exit(sh_tmu_exit);
 
 MODULE_AUTHOR("Magnus Damm");
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93aaadf99f28..b166e30b3bc4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -227,12 +227,6 @@ config GPIO_TS5500
           blocks of the TS-5500: DIO1, DIO2 and the LCD port, and the TS-5600
           LCD port.
 
-config GPIO_VT8500
-        bool "VIA/Wondermedia SoC GPIO Support"
-        depends on ARCH_VT8500
-        help
-          Say yes here to support the VT8500/WM8505/WM8650 GPIO controller.
-
 config GPIO_XILINX
         bool "Xilinx GPIO support"
         depends on PPC_OF || MICROBLAZE
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 22e07bc9fcb5..a274d7df3c8c 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -80,7 +80,6 @@ obj-$(CONFIG_GPIO_TWL6040)	+= gpio-twl6040.o
 obj-$(CONFIG_GPIO_UCB1400)      += gpio-ucb1400.o
 obj-$(CONFIG_GPIO_VIPERBOARD)   += gpio-viperboard.o
 obj-$(CONFIG_GPIO_VR41XX)       += gpio-vr41xx.o
-obj-$(CONFIG_GPIO_VT8500)       += gpio-vt8500.o
 obj-$(CONFIG_GPIO_VX855)        += gpio-vx855.o
 obj-$(CONFIG_GPIO_WM831X)       += gpio-wm831x.o
 obj-$(CONFIG_GPIO_WM8350)       += gpio-wm8350.o
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index b3643ff007e4..99e0fa49fcbd 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -1122,8 +1122,12 @@ int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
 #ifdef CONFIG_PLAT_S3C24XX
 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
 {
-        if (offset < 4)
-                return IRQ_EINT0 + offset;
+        if (offset < 4) {
+                if (soc_is_s3c2412())
+                        return IRQ_EINT0_2412 + offset;
+                else
+                        return IRQ_EINT0 + offset;
+        }
 
         if (offset < 8)
                 return IRQ_EINT4 + offset - 4;
@@ -3024,6 +3028,7 @@ static __init int samsung_gpiolib_init(void)
         static const struct of_device_id exynos_pinctrl_ids[] = {
                 { .compatible = "samsung,exynos4210-pinctrl", },
                 { .compatible = "samsung,exynos4x12-pinctrl", },
+                { .compatible = "samsung,exynos5250-pinctrl", },
                 { .compatible = "samsung,exynos5440-pinctrl", },
         };
         for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c
deleted file mode 100644
index 81683ca35ac1..000000000000
--- a/drivers/gpio/gpio-vt8500.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/* drivers/gpio/gpio-vt8500.c
- *
- * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
- * Based on arch/arm/mach-vt8500/gpio.c:
- * - Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/bitops.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_device.h>
-
-/*
-        We handle GPIOs by bank, each bank containing up to 32 GPIOs covered
-        by one set of registers (although not all may be valid).
-
-        Because different SoC's have different register offsets, we pass the
-        register offsets as data in vt8500_gpio_dt_ids[].
-
-        A value of NO_REG is used to indicate that this register is not
-        supported. Only used for ->en at the moment.
-*/
-
-#define NO_REG  0xFFFF
-
-/*
- * struct vt8500_gpio_bank_regoffsets
- * @en: offset to enable register of the bank
- * @dir: offset to direction register of the bank
- * @data_out: offset to the data out register of the bank
- * @data_in: offset to the data in register of the bank
- * @ngpio: highest valid pin in this bank
- */
-
-struct vt8500_gpio_bank_regoffsets {
-        unsigned int    en;
-        unsigned int    dir;
-        unsigned int    data_out;
-        unsigned int    data_in;
-        unsigned char   ngpio;
-};
-
-struct vt8500_gpio_data {
-        unsigned int                            num_banks;
-        struct vt8500_gpio_bank_regoffsets      banks[];
-};
-
-#define VT8500_BANK(__en, __dir, __out, __in, __ngpio)          \
-{                                                               \
-        .en = __en,                                             \
-        .dir = __dir,                                           \
-        .data_out = __out,                                      \
-        .data_in = __in,                                        \
-        .ngpio = __ngpio,                                       \
-}
-
-static struct vt8500_gpio_data vt8500_data = {
-        .num_banks      = 7,
-        .banks  = {
-                VT8500_BANK(NO_REG, 0x3C, 0x5C, 0x7C, 9),
-                VT8500_BANK(0x00, 0x20, 0x40, 0x60, 26),
-                VT8500_BANK(0x04, 0x24, 0x44, 0x64, 28),
-                VT8500_BANK(0x08, 0x28, 0x48, 0x68, 31),
-                VT8500_BANK(0x0C, 0x2C, 0x4C, 0x6C, 19),
-                VT8500_BANK(0x10, 0x30, 0x50, 0x70, 19),
-                VT8500_BANK(0x14, 0x34, 0x54, 0x74, 23),
-        },
-};
-
-static struct vt8500_gpio_data wm8505_data = {
-        .num_banks      = 10,
-        .banks  = {
-                VT8500_BANK(0x64, 0x8C, 0xB4, 0xDC, 22),
-                VT8500_BANK(0x40, 0x68, 0x90, 0xB8, 8),
-                VT8500_BANK(0x44, 0x6C, 0x94, 0xBC, 32),
-                VT8500_BANK(0x48, 0x70, 0x98, 0xC0, 6),
-                VT8500_BANK(0x4C, 0x74, 0x9C, 0xC4, 16),
-                VT8500_BANK(0x50, 0x78, 0xA0, 0xC8, 25),
-                VT8500_BANK(0x54, 0x7C, 0xA4, 0xCC, 5),
-                VT8500_BANK(0x58, 0x80, 0xA8, 0xD0, 5),
-                VT8500_BANK(0x5C, 0x84, 0xAC, 0xD4, 12),
-                VT8500_BANK(0x60, 0x88, 0xB0, 0xD8, 16),
-                VT8500_BANK(0x500, 0x504, 0x508, 0x50C, 6),
-        },
-};
-
-/*
- * No information about which bits are valid so we just make
- * them all available until its figured out.
- */
-static struct vt8500_gpio_data wm8650_data = {
-        .num_banks      = 9,
-        .banks  = {
-                VT8500_BANK(0x40, 0x80, 0xC0, 0x00, 32),
-                VT8500_BANK(0x44, 0x84, 0xC4, 0x04, 32),
-                VT8500_BANK(0x48, 0x88, 0xC8, 0x08, 32),
-                VT8500_BANK(0x4C, 0x8C, 0xCC, 0x0C, 32),
-                VT8500_BANK(0x50, 0x90, 0xD0, 0x10, 32),
-                VT8500_BANK(0x54, 0x94, 0xD4, 0x14, 32),
-                VT8500_BANK(0x58, 0x98, 0xD8, 0x18, 32),
-                VT8500_BANK(0x5C, 0x9C, 0xDC, 0x1C, 32),
-                VT8500_BANK(0x7C, 0xBC, 0xFC, 0x3C, 32),
-                VT8500_BANK(0x500, 0x504, 0x508, 0x50C, 6),
-        },
-};
-
-struct vt8500_gpio_chip {
-        struct gpio_chip                chip;
-
-        const struct vt8500_gpio_bank_regoffsets *regs;
-        void __iomem    *base;
-};
-
-struct vt8500_data {
-        struct vt8500_gpio_chip *chip;
-        void __iomem *iobase;
-        int num_banks;
-};
-
-
-#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
-
-static int vt8500_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
-        u32 val;
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        if (vt8500_chip->regs->en == NO_REG)
-                return 0;
-
-        val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->en);
-        val |= BIT(offset);
-        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->en);
-
-        return 0;
-}
-
-static void vt8500_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        u32 val;
-
-        if (vt8500_chip->regs->en == NO_REG)
-                return;
-
-        val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->en);
-        val &= ~BIT(offset);
-        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->en);
-}
-
-static int vt8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        u32 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->dir);
-        val &= ~BIT(offset);
-        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->dir);
-
-        return 0;
-}
-
-static int vt8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-                                                                int value)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        u32 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->dir);
-        val |= BIT(offset);
-        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->dir);
-
-        if (value) {
-                val = readl_relaxed(vt8500_chip->base +
-                                                vt8500_chip->regs->data_out);
-                val |= BIT(offset);
-                writel_relaxed(val, vt8500_chip->base +
-                                                vt8500_chip->regs->data_out);
-        }
-        return 0;
-}
-
-static int vt8500_gpio_get_value(struct gpio_chip *chip, unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        return (readl_relaxed(vt8500_chip->base + vt8500_chip->regs->data_in) >>
-                                                                offset) & 1;
-}
-
-static void vt8500_gpio_set_value(struct gpio_chip *chip, unsigned offset,
-                                                                int value)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        u32 val = readl_relaxed(vt8500_chip->base +
-                                                vt8500_chip->regs->data_out);
-        if (value)
-                val |= BIT(offset);
-        else
-                val &= ~BIT(offset);
-
-        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->data_out);
-}
-
-static int vt8500_of_xlate(struct gpio_chip *gc,
-                            const struct of_phandle_args *gpiospec, u32 *flags)
-{
-        /* bank if specificed in gpiospec->args[0] */
-        if (flags)
-                *flags = gpiospec->args[2];
-
-        return gpiospec->args[1];
-}
-
-static int vt8500_add_chips(struct platform_device *pdev, void __iomem *base,
-                                const struct vt8500_gpio_data *data)
-{
-        struct vt8500_data *priv;
-        struct vt8500_gpio_chip *vtchip;
-        struct gpio_chip *chip;
-        int i;
-        int pin_cnt = 0;
-
-        priv = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_data), GFP_KERNEL);
-        if (!priv) {
-                dev_err(&pdev->dev, "failed to allocate memory\n");
-                return -ENOMEM;
-        }
-
-        priv->chip = devm_kzalloc(&pdev->dev,
-                        sizeof(struct vt8500_gpio_chip) * data->num_banks,
-                        GFP_KERNEL);
-        if (!priv->chip) {
-                dev_err(&pdev->dev, "failed to allocate chip memory\n");
-                return -ENOMEM;
-        }
-
-        priv->iobase = base;
-        priv->num_banks = data->num_banks;
-        platform_set_drvdata(pdev, priv);
-
-        vtchip = priv->chip;
-
-        for (i = 0; i < data->num_banks; i++) {
-                vtchip[i].base = base;
-                vtchip[i].regs = &data->banks[i];
-
-                chip = &vtchip[i].chip;
-
-                chip->of_xlate = vt8500_of_xlate;
-                chip->of_gpio_n_cells = 3;
-                chip->of_node = pdev->dev.of_node;
-
-                chip->request = vt8500_gpio_request;
-                chip->free = vt8500_gpio_free;
-                chip->direction_input = vt8500_gpio_direction_input;
-                chip->direction_output = vt8500_gpio_direction_output;
-                chip->get = vt8500_gpio_get_value;
-                chip->set = vt8500_gpio_set_value;
-                chip->can_sleep = 0;
-                chip->base = pin_cnt;
-                chip->ngpio = data->banks[i].ngpio;
-
-                pin_cnt += data->banks[i].ngpio;
-
-                gpiochip_add(chip);
-        }
-        return 0;
-}
-
-static struct of_device_id vt8500_gpio_dt_ids[] = {
-        { .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
-        { .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
-        { .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
-        { /* Sentinel */ },
-};
-
-static int vt8500_gpio_probe(struct platform_device *pdev)
-{
-        int ret;
-        void __iomem *gpio_base;
-        struct resource *res;
-        const struct of_device_id *of_id =
-                                of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
-
-        if (!of_id) {
-                dev_err(&pdev->dev, "No matching driver data\n");
-                return -ENODEV;
-        }
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "Unable to get IO resource\n");
-                return -ENODEV;
-        }
-
-        gpio_base = devm_request_and_ioremap(&pdev->dev, res);
-        if (!gpio_base) {
-                dev_err(&pdev->dev, "Unable to map GPIO registers\n");
-                return -ENOMEM;
-        }
-
-        ret = vt8500_add_chips(pdev, gpio_base, of_id->data);
-
-        return ret;
-}
-
-static int vt8500_gpio_remove(struct platform_device *pdev)
-{
-        int i;
-        int ret;
-        struct vt8500_data *priv = platform_get_drvdata(pdev);
-        struct vt8500_gpio_chip *vtchip = priv->chip;
-
-        for (i = 0; i < priv->num_banks; i++) {
-                ret = gpiochip_remove(&vtchip[i].chip);
-                if (ret)
-                        dev_warn(&pdev->dev, "gpiochip_remove returned %d\n",
-                                 ret);
-        }
-
-        return 0;
-}
-
-static struct platform_driver vt8500_gpio_driver = {
-        .probe          = vt8500_gpio_probe,
-        .remove         = vt8500_gpio_remove,
-        .driver         = {
-                .name   = "vt8500-gpio",
-                .owner  = THIS_MODULE,
-                .of_match_table = vt8500_gpio_dt_ids,
-        },
-};
-
-module_platform_driver(vt8500_gpio_driver);
-
-MODULE_DESCRIPTION("VT8500 GPIO Driver");
-MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
-MODULE_LICENSE("GPL v2");
-MODULE_DEVICE_TABLE(of, vt8500_gpio_dt_ids);
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index a350969e5efe..4a33351c25dc 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -25,6 +25,14 @@ config ARM_VIC_NR
           The maximum number of VICs available in the system, for
           power management.
 
+config RENESAS_INTC_IRQPIN
+        bool
+        select IRQ_DOMAIN
+
+config RENESAS_IRQC
+        bool
+        select IRQ_DOMAIN
+
 config VERSATILE_FPGA_IRQ
         bool
         select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 10ef57f35a6e..c28fcccf4a0d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_IRQCHIP)			+= irqchip.o
 obj-$(CONFIG_ARCH_BCM2835)              += irq-bcm2835.o
 obj-$(CONFIG_ARCH_EXYNOS)               += exynos-combiner.o
 obj-$(CONFIG_ARCH_MXS)                  += irq-mxs.o
+obj-$(CONFIG_ARCH_S3C24XX)              += irq-s3c24xx.o
 obj-$(CONFIG_METAG)                     += irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)    += irq-metag.o
 obj-$(CONFIG_ARCH_SUNXI)                += irq-sun4i.o
@@ -10,4 +11,7 @@ obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
 obj-$(CONFIG_ARM_GIC)                   += irq-gic.o
 obj-$(CONFIG_ARM_VIC)                   += irq-vic.o
 obj-$(CONFIG_SIRF_IRQ)                  += irq-sirfsoc.o
+obj-$(CONFIG_RENESAS_INTC_IRQPIN)       += irq-renesas-intc-irqpin.o
+obj-$(CONFIG_RENESAS_IRQC)              += irq-renesas-irqc.o
 obj-$(CONFIG_VERSATILE_FPGA_IRQ)        += irq-versatile-fpga.o
+obj-$(CONFIG_ARCH_VT8500)               += irq-vt8500.o
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index 6a5201351507..02492ab20d22 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -32,6 +32,7 @@ struct combiner_chip_data {
         unsigned int irq_offset;
         unsigned int irq_mask;
         void __iomem *base;
+        unsigned int parent_irq;
 };
 
 static struct irq_domain *combiner_irq_domain;
@@ -88,22 +89,46 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         chained_irq_exit(chip, desc);
 }
 
+#ifdef CONFIG_SMP
+static int combiner_set_affinity(struct irq_data *d,
+                                 const struct cpumask *mask_val, bool force)
+{
+        struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+        struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
+        struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
+
+        if (chip && chip->irq_set_affinity)
+                return chip->irq_set_affinity(data, mask_val, force);
+        else
+                return -EINVAL;
+}
+#endif
+
 static struct irq_chip combiner_chip = {
-        .name           = "COMBINER",
-        .irq_mask       = combiner_mask_irq,
-        .irq_unmask     = combiner_unmask_irq,
+        .name                   = "COMBINER",
+        .irq_mask               = combiner_mask_irq,
+        .irq_unmask             = combiner_unmask_irq,
+#ifdef CONFIG_SMP
+        .irq_set_affinity       = combiner_set_affinity,
+#endif
 };
 
-static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
+static unsigned int max_combiner_nr(void)
 {
-        unsigned int max_nr;
-
         if (soc_is_exynos5250())
-                max_nr = EXYNOS5_MAX_COMBINER_NR;
+                return EXYNOS5_MAX_COMBINER_NR;
+        else if (soc_is_exynos4412())
+                return EXYNOS4412_MAX_COMBINER_NR;
+        else if (soc_is_exynos4212())
+                return EXYNOS4212_MAX_COMBINER_NR;
         else
-                max_nr = EXYNOS4_MAX_COMBINER_NR;
+                return EXYNOS4210_MAX_COMBINER_NR;
+}
 
-        if (combiner_nr >= max_nr)
+static void __init combiner_cascade_irq(unsigned int combiner_nr,
+                                        unsigned int irq)
+{
+        if (combiner_nr >= max_combiner_nr())
                 BUG();
         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
                 BUG();
@@ -111,12 +136,13 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
 }
 
 static void __init combiner_init_one(unsigned int combiner_nr,
-                                     void __iomem *base)
+                                     void __iomem *base, unsigned int irq)
 {
         combiner_data[combiner_nr].base = base;
         combiner_data[combiner_nr].irq_offset = irq_find_mapping(
                 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
+        combiner_data[combiner_nr].parent_irq = irq;
 
         /* Disable all interrupts */
         __raw_writel(combiner_data[combiner_nr].irq_mask,
@@ -167,23 +193,38 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
         .map    = combiner_irq_domain_map,
 };
 
+static unsigned int exynos4x12_combiner_extra_irq(int group)
+{
+        switch (group) {
+        case 16:
+                return IRQ_SPI(107);
+        case 17:
+                return IRQ_SPI(108);
+        case 18:
+                return IRQ_SPI(48);
+        case 19:
+                return IRQ_SPI(42);
+        default:
+                return 0;
+        }
+}
+
 void __init combiner_init(void __iomem *combiner_base,
                           struct device_node *np)
 {
         int i, irq, irq_base;
         unsigned int max_nr, nr_irq;
 
+        max_nr = max_combiner_nr();
+
         if (np) {
                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
-                        pr_warning("%s: number of combiners not specified, "
+                        pr_info("%s: number of combiners not specified, "
                                 "setting default as %d.\n",
-                                __func__, EXYNOS4_MAX_COMBINER_NR);
-                        max_nr = EXYNOS4_MAX_COMBINER_NR;
+                                __func__, max_nr);
                 }
-        } else {
-                max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
-                                                EXYNOS4_MAX_COMBINER_NR;
         }
+
         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 
         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
@@ -200,12 +241,15 @@ void __init combiner_init(void __iomem *combiner_base,
         }
 
         for (i = 0; i < max_nr; i++) {
-                combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
-                irq = IRQ_SPI(i);
+                if (i < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250())
+                        irq = IRQ_SPI(i);
+                else
+                        irq = exynos4x12_combiner_extra_irq(i);
 #ifdef CONFIG_OF
                 if (np)
                         irq = irq_of_parse_and_map(np, i);
 #endif
+                combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
                 combiner_cascade_irq(i, irq);
         }
 }
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
new file mode 100644
index 000000000000..5a68e5accec1
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
@@ -0,0 +1,547 @@
+/*
+ * Renesas INTC External IRQ Pin Driver
+ *
+ *  Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_data/irq-renesas-intc-irqpin.h>
+
+#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
+
+#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
+#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
+#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
+#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
+#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
+#define INTC_IRQPIN_REG_NR 5
+
+/* INTC external IRQ PIN hardware register access:
+ *
+ * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
+ * PRIO is read-write 32-bit with 4-bits per IRQ (**)
+ * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
+ * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
+ * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
+ *
+ * (*) May be accessed by more than one driver instance - lock needed
+ * (**) Read-modify-write access by one driver instance - lock needed
+ * (***) Accessed by one driver instance only - no locking needed
+ */
+
+struct intc_irqpin_iomem {
+        void __iomem *iomem;
+        unsigned long (*read)(void __iomem *iomem);
+        void (*write)(void __iomem *iomem, unsigned long data);
+        int width;
+};
+
+struct intc_irqpin_irq {
+        int hw_irq;
+        int requested_irq;
+        int domain_irq;
+        struct intc_irqpin_priv *p;
+};
+
+struct intc_irqpin_priv {
+        struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
+        struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
+        struct renesas_intc_irqpin_config config;
+        unsigned int number_of_irqs;
+        struct platform_device *pdev;
+        struct irq_chip irq_chip;
+        struct irq_domain *irq_domain;
+        bool shared_irqs;
+        u8 shared_irq_mask;
+};
+
+static unsigned long intc_irqpin_read32(void __iomem *iomem)
+{
+        return ioread32(iomem);
+}
+
+static unsigned long intc_irqpin_read8(void __iomem *iomem)
+{
+        return ioread8(iomem);
+}
+
+static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
+{
+        iowrite32(data, iomem);
+}
+
+static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
+{
+        iowrite8(data, iomem);
+}
+
+static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
+                                             int reg)
+{
+        struct intc_irqpin_iomem *i = &p->iomem[reg];
+
+        return i->read(i->iomem);
+}
+
+static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
+                                     int reg, unsigned long data)
+{
+        struct intc_irqpin_iomem *i = &p->iomem[reg];
+
+        i->write(i->iomem, data);
+}
+
+static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
+                                                   int reg, int hw_irq)
+{
+        return BIT((p->iomem[reg].width - 1) - hw_irq);
+}
+
+static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
+                                               int reg, int hw_irq)
+{
+        intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
+}
+
+static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
+
+static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
+                                          int reg, int shift,
+                                          int width, int value)
+{
+        unsigned long flags;
+        unsigned long tmp;
+
+        raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
+
+        tmp = intc_irqpin_read(p, reg);
+        tmp &= ~(((1 << width) - 1) << shift);
+        tmp |= value << shift;
+        intc_irqpin_write(p, reg, tmp);
+
+        raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
+}
+
+static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
+                                         int irq, int do_mask)
+{
+        int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
+        int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
+
+        intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
+                                      shift, bitfield_width,
+                                      do_mask ? 0 : (1 << bitfield_width) - 1);
+}
+
+static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
+{
+        int bitfield_width = p->config.sense_bitfield_width;
+        int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
+
+        dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
+
+        if (value >= (1 << bitfield_width))
+                return -EINVAL;
+
+        intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
+                                      bitfield_width, value);
+        return 0;
+}
+
+static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
+{
+        dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
+                str, i->requested_irq, i->hw_irq, i->domain_irq);
+}
+
+static void intc_irqpin_irq_enable(struct irq_data *d)
+{
+        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
+        int hw_irq = irqd_to_hwirq(d);
+
+        intc_irqpin_dbg(&p->irq[hw_irq], "enable");
+        intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
+}
+
+static void intc_irqpin_irq_disable(struct irq_data *d)
+{
+        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
+        int hw_irq = irqd_to_hwirq(d);
+
+        intc_irqpin_dbg(&p->irq[hw_irq], "disable");
+        intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
+}
+
+static void intc_irqpin_shared_irq_enable(struct irq_data *d)
+{
+        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
+        int hw_irq = irqd_to_hwirq(d);
+
+        intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
+        intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
+
+        p->shared_irq_mask &= ~BIT(hw_irq);
+}
+
+static void intc_irqpin_shared_irq_disable(struct irq_data *d)
+{
+        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
+        int hw_irq = irqd_to_hwirq(d);
+
+        intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
+        intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
+
+        p->shared_irq_mask |= BIT(hw_irq);
+}
+
+static void intc_irqpin_irq_enable_force(struct irq_data *d)
+{
+        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
+        int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
+
+        intc_irqpin_irq_enable(d);
+
+        /* enable interrupt through parent interrupt controller,
+         * assumes non-shared interrupt with 1:1 mapping
+         * needed for busted IRQs on some SoCs like sh73a0
+         */
+        irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
+}
+
+static void intc_irqpin_irq_disable_force(struct irq_data *d)
+{
+        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
+        int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
+
+        /* disable interrupt through parent interrupt controller,
+         * assumes non-shared interrupt with 1:1 mapping
+         * needed for busted IRQs on some SoCs like sh73a0
+         */
+        irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
+        intc_irqpin_irq_disable(d);
+}
+
+#define INTC_IRQ_SENSE_VALID 0x10
+#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
+
+static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
+        [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
+        [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
+        [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
+        [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
+        [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
+};
+
+static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
+{
+        unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
+        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
+
+        if (!(value & INTC_IRQ_SENSE_VALID))
+                return -EINVAL;
+
+        return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
+                                     value ^ INTC_IRQ_SENSE_VALID);
+}
+
+static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
+{
+        struct intc_irqpin_irq *i = dev_id;
+        struct intc_irqpin_priv *p = i->p;
+        unsigned long bit;
+
+        intc_irqpin_dbg(i, "demux1");
+        bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
+
+        if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
+                intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
+                intc_irqpin_dbg(i, "demux2");
+                generic_handle_irq(i->domain_irq);
+                return IRQ_HANDLED;
+        }
+        return IRQ_NONE;
+}
+
+static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
+{
+        struct intc_irqpin_priv *p = dev_id;
+        unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
+        irqreturn_t status = IRQ_NONE;
+        int k;
+
+        for (k = 0; k < 8; k++) {
+                if (reg_source & BIT(7 - k)) {
+                        if (BIT(k) & p->shared_irq_mask)
+                                continue;
+
+                        status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
+                }
+        }
+
+        return status;
+}
+
+static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
+                                      irq_hw_number_t hw)
+{
+        struct intc_irqpin_priv *p = h->host_data;
+
+        p->irq[hw].domain_irq = virq;
+        p->irq[hw].hw_irq = hw;
+
+        intc_irqpin_dbg(&p->irq[hw], "map");
+        irq_set_chip_data(virq, h->host_data);
+        irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID); /* kill me now */
+        return 0;
+}
+
+static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
+        .map    = intc_irqpin_irq_domain_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
+static int intc_irqpin_probe(struct platform_device *pdev)
+{
+        struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data;
+        struct intc_irqpin_priv *p;
+        struct intc_irqpin_iomem *i;
+        struct resource *io[INTC_IRQPIN_REG_NR];
+        struct resource *irq;
+        struct irq_chip *irq_chip;
+        void (*enable_fn)(struct irq_data *d);
+        void (*disable_fn)(struct irq_data *d);
+        const char *name = dev_name(&pdev->dev);
+        int ref_irq;
+        int ret;
+        int k;
+
+        p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
+        if (!p) {
+                dev_err(&pdev->dev, "failed to allocate driver data\n");
+                ret = -ENOMEM;
+                goto err0;
+        }
+
+        /* deal with driver instance configuration */
+        if (pdata)
+                memcpy(&p->config, pdata, sizeof(*pdata));
+        if (!p->config.sense_bitfield_width)
+                p->config.sense_bitfield_width = 4; /* default to 4 bits */
+
+        p->pdev = pdev;
+        platform_set_drvdata(pdev, p);
+
+        /* get hold of manadatory IOMEM */
+        for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
+                io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
+                if (!io[k]) {
+                        dev_err(&pdev->dev, "not enough IOMEM resources\n");
+                        ret = -EINVAL;
+                        goto err0;
+                }
+        }
+
+        /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
+        for (k = 0; k < INTC_IRQPIN_MAX; k++) {
+                irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
+                if (!irq)
+                        break;
+
+                p->irq[k].p = p;
+                p->irq[k].requested_irq = irq->start;
+        }
+
+        p->number_of_irqs = k;
+        if (p->number_of_irqs < 1) {
+                dev_err(&pdev->dev, "not enough IRQ resources\n");
+                ret = -EINVAL;
+                goto err0;
+        }
+
+        /* ioremap IOMEM and setup read/write callbacks */
+        for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
+                i = &p->iomem[k];
+
+                switch (resource_size(io[k])) {
+                case 1:
+                        i->width = 8;
+                        i->read = intc_irqpin_read8;
+                        i->write = intc_irqpin_write8;
+                        break;
+                case 4:
+                        i->width = 32;
+                        i->read = intc_irqpin_read32;
+                        i->write = intc_irqpin_write32;
+                        break;
+                default:
+                        dev_err(&pdev->dev, "IOMEM size mismatch\n");
+                        ret = -EINVAL;
+                        goto err0;
+                }
+
+                i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start,
+                                                resource_size(io[k]));
+                if (!i->iomem) {
+                        dev_err(&pdev->dev, "failed to remap IOMEM\n");
+                        ret = -ENXIO;
+                        goto err0;
+                }
+        }
+
+        /* mask all interrupts using priority */
+        for (k = 0; k < p->number_of_irqs; k++)
+                intc_irqpin_mask_unmask_prio(p, k, 1);
+
+        /* clear all pending interrupts */
+        intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
+
+        /* scan for shared interrupt lines */
+        ref_irq = p->irq[0].requested_irq;
+        p->shared_irqs = true;
+        for (k = 1; k < p->number_of_irqs; k++) {
+                if (ref_irq != p->irq[k].requested_irq) {
+                        p->shared_irqs = false;
+                        break;
+                }
+        }
+
+        /* use more severe masking method if requested */
+        if (p->config.control_parent) {
+                enable_fn = intc_irqpin_irq_enable_force;
+                disable_fn = intc_irqpin_irq_disable_force;
+        } else if (!p->shared_irqs) {
+                enable_fn = intc_irqpin_irq_enable;
+                disable_fn = intc_irqpin_irq_disable;
+        } else {
+                enable_fn = intc_irqpin_shared_irq_enable;
+                disable_fn = intc_irqpin_shared_irq_disable;
+        }
+
+        irq_chip = &p->irq_chip;
+        irq_chip->name = name;
+        irq_chip->irq_mask = disable_fn;
+        irq_chip->irq_unmask = enable_fn;
+        irq_chip->irq_enable = enable_fn;
+        irq_chip->irq_disable = disable_fn;
+        irq_chip->irq_set_type = intc_irqpin_irq_set_type;
+        irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
+
+        p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
+                                              p->number_of_irqs,
+                                              p->config.irq_base,
+                                              &intc_irqpin_irq_domain_ops, p);
+        if (!p->irq_domain) {
+                ret = -ENXIO;
+                dev_err(&pdev->dev, "cannot initialize irq domain\n");
+                goto err0;
+        }
+
+        if (p->shared_irqs) {
+                /* request one shared interrupt */
+                if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq,
+                                intc_irqpin_shared_irq_handler,
+                                IRQF_SHARED, name, p)) {
+                        dev_err(&pdev->dev, "failed to request low IRQ\n");
+                        ret = -ENOENT;
+                        goto err1;
+                }
+        } else {
+                /* request interrupts one by one */
+                for (k = 0; k < p->number_of_irqs; k++) {
+                        if (devm_request_irq(&pdev->dev,
+                                        p->irq[k].requested_irq,
+                                        intc_irqpin_irq_handler,
+                                        0, name, &p->irq[k])) {
+                                dev_err(&pdev->dev,
+                                        "failed to request low IRQ\n");
+                                ret = -ENOENT;
+                                goto err1;
+                        }
+                }
+        }
+
+        /* unmask all interrupts on prio level */
+        for (k = 0; k < p->number_of_irqs; k++)
+                intc_irqpin_mask_unmask_prio(p, k, 0);
+
+        dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
+
+        /* warn in case of mismatch if irq base is specified */
+        if (p->config.irq_base) {
+                if (p->config.irq_base != p->irq[0].domain_irq)
+                        dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
+                                 p->config.irq_base, p->irq[0].domain_irq);
+        }
+
+        return 0;
+
+err1:
+        irq_domain_remove(p->irq_domain);
+err0:
+        return ret;
+}
+
+static int intc_irqpin_remove(struct platform_device *pdev)
+{
+        struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
+
+        irq_domain_remove(p->irq_domain);
+
+        return 0;
+}
+
+static const struct of_device_id intc_irqpin_dt_ids[] = {
+        { .compatible = "renesas,intc-irqpin", },
+        {},
+};
+MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
+
+static struct platform_driver intc_irqpin_device_driver = {
+        .probe          = intc_irqpin_probe,
+        .remove         = intc_irqpin_remove,
+        .driver         = {
+                .name   = "renesas_intc_irqpin",
+                .of_match_table = intc_irqpin_dt_ids,
+                .owner  = THIS_MODULE,
+        }
+};
+
+static int __init intc_irqpin_init(void)
+{
+        return platform_driver_register(&intc_irqpin_device_driver);
+}
+postcore_initcall(intc_irqpin_init);
+
+static void __exit intc_irqpin_exit(void)
+{
+        platform_driver_unregister(&intc_irqpin_device_driver);
+}
+module_exit(intc_irqpin_exit);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c
new file mode 100644
index 000000000000..927bff373aac
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-irqc.c
@@ -0,0 +1,307 @@
+/*
+ * Renesas IRQC Driver
+ *
+ *  Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_data/irq-renesas-irqc.h>
+
+#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
+
+#define IRQC_REQ_STS 0x00
+#define IRQC_EN_STS 0x04
+#define IRQC_EN_SET 0x08
+#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
+#define DETECT_STATUS 0x100
+#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
+
+struct irqc_irq {
+        int hw_irq;
+        int requested_irq;
+        int domain_irq;
+        struct irqc_priv *p;
+};
+
+struct irqc_priv {
+        void __iomem *iomem;
+        void __iomem *cpu_int_base;
+        struct irqc_irq irq[IRQC_IRQ_MAX];
+        struct renesas_irqc_config config;
+        unsigned int number_of_irqs;
+        struct platform_device *pdev;
+        struct irq_chip irq_chip;
+        struct irq_domain *irq_domain;
+};
+
+static void irqc_dbg(struct irqc_irq *i, char *str)
+{
+        dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
+                str, i->requested_irq, i->hw_irq, i->domain_irq);
+}
+
+static void irqc_irq_enable(struct irq_data *d)
+{
+        struct irqc_priv *p = irq_data_get_irq_chip_data(d);
+        int hw_irq = irqd_to_hwirq(d);
+
+        irqc_dbg(&p->irq[hw_irq], "enable");
+        iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
+}
+
+static void irqc_irq_disable(struct irq_data *d)
+{
+        struct irqc_priv *p = irq_data_get_irq_chip_data(d);
+        int hw_irq = irqd_to_hwirq(d);
+
+        irqc_dbg(&p->irq[hw_irq], "disable");
+        iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
+}
+
+#define INTC_IRQ_SENSE_VALID 0x10
+#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
+
+static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
+        [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01),
+        [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02),
+        [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */
+        [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */
+        [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c),  /* Synchronous */
+};
+
+static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
+{
+        struct irqc_priv *p = irq_data_get_irq_chip_data(d);
+        int hw_irq = irqd_to_hwirq(d);
+        unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
+        unsigned long tmp;
+
+        irqc_dbg(&p->irq[hw_irq], "sense");
+
+        if (!(value & INTC_IRQ_SENSE_VALID))
+                return -EINVAL;
+
+        tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
+        tmp &= ~0x3f;
+        tmp |= value ^ INTC_IRQ_SENSE_VALID;
+        iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
+        return 0;
+}
+
+static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
+{
+        struct irqc_irq *i = dev_id;
+        struct irqc_priv *p = i->p;
+        unsigned long bit = BIT(i->hw_irq);
+
+        irqc_dbg(i, "demux1");
+
+        if (ioread32(p->iomem + DETECT_STATUS) & bit) {
+                iowrite32(bit, p->iomem + DETECT_STATUS);
+                irqc_dbg(i, "demux2");
+                generic_handle_irq(i->domain_irq);
+                return IRQ_HANDLED;
+        }
+        return IRQ_NONE;
+}
+
+static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
+                               irq_hw_number_t hw)
+{
+        struct irqc_priv *p = h->host_data;
+
+        p->irq[hw].domain_irq = virq;
+        p->irq[hw].hw_irq = hw;
+
+        irqc_dbg(&p->irq[hw], "map");
+        irq_set_chip_data(virq, h->host_data);
+        irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID); /* kill me now */
+        return 0;
+}
+
+static struct irq_domain_ops irqc_irq_domain_ops = {
+        .map    = irqc_irq_domain_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
+static int irqc_probe(struct platform_device *pdev)
+{
+        struct renesas_irqc_config *pdata = pdev->dev.platform_data;
+        struct irqc_priv *p;
+        struct resource *io;
+        struct resource *irq;
+        struct irq_chip *irq_chip;
+        const char *name = dev_name(&pdev->dev);
+        int ret;
+        int k;
+
+        p = kzalloc(sizeof(*p), GFP_KERNEL);
+        if (!p) {
+                dev_err(&pdev->dev, "failed to allocate driver data\n");
+                ret = -ENOMEM;
+                goto err0;
+        }
+
+        /* deal with driver instance configuration */
+        if (pdata)
+                memcpy(&p->config, pdata, sizeof(*pdata));
+
+        p->pdev = pdev;
+        platform_set_drvdata(pdev, p);
+
+        /* get hold of manadatory IOMEM */
+        io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!io) {
+                dev_err(&pdev->dev, "not enough IOMEM resources\n");
+                ret = -EINVAL;
+                goto err1;
+        }
+
+        /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
+        for (k = 0; k < IRQC_IRQ_MAX; k++) {
+                irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
+                if (!irq)
+                        break;
+
+                p->irq[k].p = p;
+                p->irq[k].requested_irq = irq->start;
+        }
+
+        p->number_of_irqs = k;
+        if (p->number_of_irqs < 1) {
+                dev_err(&pdev->dev, "not enough IRQ resources\n");
+                ret = -EINVAL;
+                goto err1;
+        }
+
+        /* ioremap IOMEM and setup read/write callbacks */
+        p->iomem = ioremap_nocache(io->start, resource_size(io));
+        if (!p->iomem) {
+                dev_err(&pdev->dev, "failed to remap IOMEM\n");
+                ret = -ENXIO;
+                goto err2;
+        }
+
+        p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
+
+        irq_chip = &p->irq_chip;
+        irq_chip->name = name;
+        irq_chip->irq_mask = irqc_irq_disable;
+        irq_chip->irq_unmask = irqc_irq_enable;
+        irq_chip->irq_enable = irqc_irq_enable;
+        irq_chip->irq_disable = irqc_irq_disable;
+        irq_chip->irq_set_type = irqc_irq_set_type;
+        irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
+
+        p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
+                                              p->number_of_irqs,
+                                              p->config.irq_base,
+                                              &irqc_irq_domain_ops, p);
+        if (!p->irq_domain) {
+                ret = -ENXIO;
+                dev_err(&pdev->dev, "cannot initialize irq domain\n");
+                goto err2;
+        }
+
+        /* request interrupts one by one */
+        for (k = 0; k < p->number_of_irqs; k++) {
+                if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
+                                0, name, &p->irq[k])) {
+                        dev_err(&pdev->dev, "failed to request IRQ\n");
+                        ret = -ENOENT;
+                        goto err3;
+                }
+        }
+
+        dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
+
+        /* warn in case of mismatch if irq base is specified */
+        if (p->config.irq_base) {
+                if (p->config.irq_base != p->irq[0].domain_irq)
+                        dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
+                                 p->config.irq_base, p->irq[0].domain_irq);
+        }
+
+        return 0;
+err3:
+        for (; k >= 0; k--)
+                free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]);
+
+        irq_domain_remove(p->irq_domain);
+err2:
+        iounmap(p->iomem);
+err1:
+        kfree(p);
+err0:
+        return ret;
+}
+
+static int irqc_remove(struct platform_device *pdev)
+{
+        struct irqc_priv *p = platform_get_drvdata(pdev);
+        int k;
+
+        for (k = 0; k < p->number_of_irqs; k++)
+                free_irq(p->irq[k].requested_irq, &p->irq[k]);
+
+        irq_domain_remove(p->irq_domain);
+        iounmap(p->iomem);
+        kfree(p);
+        return 0;
+}
+
+static const struct of_device_id irqc_dt_ids[] = {
+        { .compatible = "renesas,irqc", },
+        {},
+};
+MODULE_DEVICE_TABLE(of, irqc_dt_ids);
+
+static struct platform_driver irqc_device_driver = {
+        .probe          = irqc_probe,
+        .remove         = irqc_remove,
+        .driver         = {
+                .name   = "renesas_irqc",
+                .of_match_table = irqc_dt_ids,
+                .owner  = THIS_MODULE,
+        }
+};
+
+static int __init irqc_init(void)
+{
+        return platform_driver_register(&irqc_device_driver);
+}
+postcore_initcall(irqc_init);
+
+static void __exit irqc_exit(void)
+{
+        platform_driver_unregister(&irqc_device_driver);
+}
+module_exit(irqc_exit);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("Renesas IRQC Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-s3c24xx/irq.c b/drivers/irqchip/irq-s3c24xx.c
index b41c2cb7af4a..bbcc944ed94f 100644
--- a/arch/arm/mach-s3c24xx/irq.c
+++ b/drivers/irqchip/irq-s3c24xx.c
@@ -26,7 +26,11 @@
 #include <linux/device.h>
 #include <linux/irqdomain.h>
 #include <linux/irqchip/chained_irq.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 
 #include <mach/regs-irq.h>
@@ -36,6 +40,8 @@
 #include <plat/regs-irqtype.h>
 #include <plat/pm.h>
 
+#include "irqchip.h"
+
 #define S3C_IRQTYPE_NONE        0
 #define S3C_IRQTYPE_EINT        1
 #define S3C_IRQTYPE_EDGE        2
@@ -43,6 +49,7 @@
 
 struct s3c_irq_data {
         unsigned int type;
+        unsigned long offset;
         unsigned long parent_irq;
 
         /* data gets filled during init */
@@ -69,23 +76,34 @@ struct s3c_irq_intc {
         struct s3c_irq_data     *irqs;
 };
 
+/*
+ * Array holding pointers to the global controller structs
+ * [0] ... main_intc
+ * [1] ... sub_intc
+ * [2] ... main_intc2 on s3c2416
+ */
+static struct s3c_irq_intc *s3c_intc[3];
+
 static void s3c_irq_mask(struct irq_data *data)
 {
-        struct s3c_irq_intc *intc = data->domain->host_data;
+        struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
+        struct s3c_irq_intc *intc = irq_data->intc;
         struct s3c_irq_intc *parent_intc = intc->parent;
-        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
         struct s3c_irq_data *parent_data;
         unsigned long mask;
         unsigned int irqno;
 
         mask = __raw_readl(intc->reg_mask);
-        mask |= (1UL << data->hwirq);
+        mask |= (1UL << irq_data->offset);
         __raw_writel(mask, intc->reg_mask);
 
-        if (parent_intc && irq_data->parent_irq) {
+        if (parent_intc) {
                 parent_data = &parent_intc->irqs[irq_data->parent_irq];
 
-                /* check to see if we need to mask the parent IRQ */
+                /* check to see if we need to mask the parent IRQ
+                 * The parent_irq is always in main_intc, so the hwirq
+                 * for find_mapping does not need an offset in any case.
+                 */
                 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
                         irqno = irq_find_mapping(parent_intc->domain,
                                          irq_data->parent_irq);
@@ -96,17 +114,17 @@ static void s3c_irq_mask(struct irq_data *data)
 
 static void s3c_irq_unmask(struct irq_data *data)
 {
-        struct s3c_irq_intc *intc = data->domain->host_data;
+        struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
+        struct s3c_irq_intc *intc = irq_data->intc;
         struct s3c_irq_intc *parent_intc = intc->parent;
-        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
         unsigned long mask;
         unsigned int irqno;
 
         mask = __raw_readl(intc->reg_mask);
-        mask &= ~(1UL << data->hwirq);
+        mask &= ~(1UL << irq_data->offset);
         __raw_writel(mask, intc->reg_mask);
 
-        if (parent_intc && irq_data->parent_irq) {
+        if (parent_intc) {
                 irqno = irq_find_mapping(parent_intc->domain,
                                          irq_data->parent_irq);
                 s3c_irq_unmask(irq_get_irq_data(irqno));
@@ -115,14 +133,37 @@ static void s3c_irq_unmask(struct irq_data *data)
 
 static inline void s3c_irq_ack(struct irq_data *data)
 {
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        unsigned long bitval = 1UL << data->hwirq;
+        struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
+        struct s3c_irq_intc *intc = irq_data->intc;
+        unsigned long bitval = 1UL << irq_data->offset;
 
         __raw_writel(bitval, intc->reg_pending);
         if (intc->reg_intpnd)
                 __raw_writel(bitval, intc->reg_intpnd);
 }
 
+static int s3c_irq_type(struct irq_data *data, unsigned int type)
+{
+        switch (type) {
+        case IRQ_TYPE_NONE:
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+        case IRQ_TYPE_EDGE_FALLING:
+        case IRQ_TYPE_EDGE_BOTH:
+                irq_set_handler(data->irq, handle_edge_irq);
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+        case IRQ_TYPE_LEVEL_HIGH:
+                irq_set_handler(data->irq, handle_level_irq);
+                break;
+        default:
+                pr_err("No such irq type %d", type);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
 static int s3c_irqext_type_set(void __iomem *gpcon_reg,
                                void __iomem *extint_reg,
                                unsigned long gpcon_offset,
@@ -228,6 +269,7 @@ static struct irq_chip s3c_irq_chip = {
         .irq_ack        = s3c_irq_ack,
         .irq_mask       = s3c_irq_mask,
         .irq_unmask     = s3c_irq_unmask,
+        .irq_set_type   = s3c_irq_type,
         .irq_set_wake   = s3c_irq_wake
 };
 
@@ -236,6 +278,7 @@ static struct irq_chip s3c_irq_level_chip = {
         .irq_mask       = s3c_irq_mask,
         .irq_unmask     = s3c_irq_unmask,
         .irq_ack        = s3c_irq_ack,
+        .irq_set_type   = s3c_irq_type,
 };
 
 static struct irq_chip s3c_irqext_chip = {
@@ -259,12 +302,19 @@ static struct irq_chip s3c_irq_eint0t4 = {
 static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
         struct irq_chip *chip = irq_desc_get_chip(desc);
-        struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
-        struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
+        struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
+        struct s3c_irq_intc *intc = irq_data->intc;
         struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
         unsigned long src;
         unsigned long msk;
         unsigned int n;
+        unsigned int offset;
+
+        /* we're using individual domains for the non-dt case
+         * and one big domain for the dt case where the subintc
+         * starts at hwirq number 32.
+         */
+        offset = (intc->domain->of_node) ? 32 : 0;
 
         chained_irq_enter(chip, desc);
 
@@ -277,12 +327,64 @@ static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
         while (src) {
                 n = __ffs(src);
                 src &= ~(1 << n);
-                generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
+                irq = irq_find_mapping(sub_intc->domain, offset + n);
+                generic_handle_irq(irq);
         }
 
         chained_irq_exit(chip, desc);
 }
 
+static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
+                                      struct pt_regs *regs, int intc_offset)
+{
+        int pnd;
+        int offset;
+        int irq;
+
+        pnd = __raw_readl(intc->reg_intpnd);
+        if (!pnd)
+                return false;
+
+        /* non-dt machines use individual domains */
+        if (!intc->domain->of_node)
+                intc_offset = 0;
+
+        /* We have a problem that the INTOFFSET register does not always
+         * show one interrupt. Occasionally we get two interrupts through
+         * the prioritiser, and this causes the INTOFFSET register to show
+         * what looks like the logical-or of the two interrupt numbers.
+         *
+         * Thanks to Klaus, Shannon, et al for helping to debug this problem
+         */
+        offset = __raw_readl(intc->reg_intpnd + 4);
+
+        /* Find the bit manually, when the offset is wrong.
+         * The pending register only ever contains the one bit of the next
+         * interrupt to handle.
+         */
+        if (!(pnd & (1 << offset)))
+                offset =  __ffs(pnd);
+
+        irq = irq_find_mapping(intc->domain, intc_offset + offset);
+        handle_IRQ(irq, regs);
+        return true;
+}
+
+asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
+{
+        do {
+                if (likely(s3c_intc[0]))
+                        if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
+                                continue;
+
+                if (s3c_intc[2])
+                        if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
+                                continue;
+
+                break;
+        } while (1);
+}
+
 #ifdef CONFIG_FIQ
 /**
  * s3c24xx_set_fiq - set the FIQ routing
@@ -325,25 +427,21 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
         struct s3c_irq_data *parent_irq_data;
         unsigned int irqno;
 
-        if (!intc) {
-                pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
-                return -EINVAL;
-        }
-
-        if (!irq_data) {
-                pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
-                return -EINVAL;
-        }
-
         /* attach controller pointer to irq_data */
         irq_data->intc = intc;
+        irq_data->offset = hw;
+
+        parent_intc = intc->parent;
 
         /* set handler and flags */
         switch (irq_data->type) {
         case S3C_IRQTYPE_NONE:
                 return 0;
         case S3C_IRQTYPE_EINT:
-                if (irq_data->parent_irq)
+                /* On the S3C2412, the EINT0to3 have a parent irq
+                 * but need the s3c_irq_eint0t4 chip
+                 */
+                if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
                         irq_set_chip_and_handler(virq, &s3c_irqext_chip,
                                                  handle_edge_irq);
                 else
@@ -351,8 +449,7 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
                                                  handle_edge_irq);
                 break;
         case S3C_IRQTYPE_EDGE:
-                if (irq_data->parent_irq ||
-                    intc->reg_pending == S3C2416_SRCPND2)
+                if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
                         irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
                                                  handle_edge_irq);
                 else
@@ -360,7 +457,7 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
                                                  handle_edge_irq);
                 break;
         case S3C_IRQTYPE_LEVEL:
-                if (irq_data->parent_irq)
+                if (parent_intc)
                         irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
                                                  handle_level_irq);
                 else
@@ -371,23 +468,19 @@ static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
                 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
                 return -EINVAL;
         }
+
+        irq_set_chip_data(virq, irq_data);
+
         set_irq_flags(virq, IRQF_VALID);
 
-        if (irq_data->parent_irq) {
-                parent_intc = intc->parent;
-                if (!parent_intc) {
-                        pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
-                               hw);
+        if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
+                if (irq_data->parent_irq > 31) {
+                        pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
+                               irq_data->parent_irq);
                         goto err;
                 }
 
                 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
-                if (!irq_data) {
-                        pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
-                               hw);
-                        goto err;
-                }
-
                 parent_irq_data->sub_intc = intc;
                 parent_irq_data->sub_bits |= (1UL << hw);
 
@@ -442,7 +535,7 @@ static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
         }
 }
 
-struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
+static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
                                        struct s3c_irq_data *irq_data,
                                        struct s3c_irq_intc *parent,
                                        unsigned long address)
@@ -451,7 +544,6 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
         void __iomem *base = (void *)0xf6000000; /* static mapping */
         int irq_num;
         int irq_start;
-        int irq_offset;
         int ret;
 
         intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
@@ -475,7 +567,6 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
                 intc->reg_intpnd = base + 0x10;
                 irq_num = 32;
                 irq_start = S3C2410_IRQ(0);
-                irq_offset = 0;
                 break;
         case 0x4a000018:
                 pr_debug("irq: found subintc\n");
@@ -483,7 +574,6 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
                 intc->reg_mask = base + 0x1c;
                 irq_num = 29;
                 irq_start = S3C2410_IRQSUB(0);
-                irq_offset = 0;
                 break;
         case 0x4a000040:
                 pr_debug("irq: found intc2\n");
@@ -492,7 +582,6 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
                 intc->reg_intpnd = base + 0x50;
                 irq_num = 8;
                 irq_start = S3C2416_IRQ(0);
-                irq_offset = 0;
                 break;
         case 0x560000a4:
                 pr_debug("irq: found eintc\n");
@@ -500,9 +589,8 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
 
                 intc->reg_mask = base + 0xa4;
                 intc->reg_pending = base + 0xa8;
-                irq_num = 20;
+                irq_num = 24;
                 irq_start = S3C2410_IRQ(32);
-                irq_offset = 4;
                 break;
         default:
                 pr_err("irq: unsupported controller address\n");
@@ -513,7 +601,7 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
         /* now that all the data is complete, init the irq-domain */
         s3c24xx_clear_intc(intc);
         intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
-                                             irq_offset, &s3c24xx_irq_ops,
+                                             0, &s3c24xx_irq_ops,
                                              intc);
         if (!intc->domain) {
                 pr_err("irq: could not create irq-domain\n");
@@ -521,6 +609,8 @@ struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
                 goto err;
         }
 
+        set_handle_irq(s3c24xx_handle_irq);
+
         return intc;
 
 err:
@@ -528,12 +618,35 @@ err:
         return ERR_PTR(ret);
 }
 
-/* s3c24xx_init_irq
- *
- * Initialise S3C2410 IRQ system
-*/
+static struct s3c_irq_data init_eint[32] = {
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
+};
 
-static struct s3c_irq_data init_base[32] = {
+#ifdef CONFIG_CPU_S3C2410
+static struct s3c_irq_data init_s3c2410base[32] = {
         { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
         { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
         { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
@@ -568,11 +681,80 @@ static struct s3c_irq_data init_base[32] = {
         { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
 };
 
-static struct s3c_irq_data init_eint[32] = {
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+static struct s3c_irq_data init_s3c2410subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+};
+
+void __init s3c2410_init_irq(void)
+{
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
+                                        s3c_intc[0], 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+}
+#endif
+
+#ifdef CONFIG_CPU_S3C2412
+static struct s3c_irq_data init_s3c2412base[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
         { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
         { .type = S3C_IRQTYPE_NONE, }, /* reserved */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+static struct s3c_irq_data init_s3c2412eint[32] = {
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
         { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
         { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
         { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
@@ -595,7 +777,7 @@ static struct s3c_irq_data init_eint[32] = {
         { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
 };
 
-static struct s3c_irq_data init_subint[32] = {
+static struct s3c_irq_data init_s3c2412subint[32] = {
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
@@ -607,25 +789,32 @@ static struct s3c_irq_data init_subint[32] = {
         { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
         { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
         { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+        { .type = S3C_IRQTYPE_NONE, },
+        { .type = S3C_IRQTYPE_NONE, },
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
 };
 
-void __init s3c24xx_init_irq(void)
+void __init s3c2412_init_irq(void)
 {
-        struct s3c_irq_intc *main_intc;
+        pr_info("S3C2412: IRQ Support\n");
 
 #ifdef CONFIG_FIQ
         init_FIQ(FIQ_START);
 #endif
 
-        main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
                 pr_err("irq: could not create main interrupt controller\n");
                 return;
         }
 
-        s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
+        s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
+                                        s3c_intc[0], 0x4a000018);
 }
+#endif
 
 #ifdef CONFIG_CPU_S3C2416
 static struct s3c_irq_data init_s3c2416base[32] = {
@@ -697,37 +886,185 @@ static struct s3c_irq_data init_s3c2416subint[32] = {
 
 static struct s3c_irq_data init_s3c2416_second[32] = {
         { .type = S3C_IRQTYPE_EDGE }, /* 2D */
-        { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
         { .type = S3C_IRQTYPE_NONE }, /* reserved */
         { .type = S3C_IRQTYPE_NONE }, /* reserved */
         { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
-        { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
+        { .type = S3C_IRQTYPE_NONE }, /* reserved */
         { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
-        { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
 };
 
 void __init s3c2416_init_irq(void)
 {
-        struct s3c_irq_intc *main_intc;
-
         pr_info("S3C2416: IRQ Support\n");
 
 #ifdef CONFIG_FIQ
         init_FIQ(FIQ_START);
 #endif
 
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
                 pr_err("irq: could not create main interrupt controller\n");
                 return;
         }
 
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
+                                        s3c_intc[0], 0x4a000018);
+
+        s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
+                                        NULL, 0x4a000040);
+}
+
+#endif
+
+#ifdef CONFIG_CPU_S3C2440
+static struct s3c_irq_data init_s3c2440base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+static struct s3c_irq_data init_s3c2440subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
+};
+
+void __init s3c2440_init_irq(void)
+{
+        pr_info("S3C2440: IRQ Support\n");
 
-        s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+
+        s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
+                                        s3c_intc[0], 0x4a000018);
 }
+#endif
 
+#ifdef CONFIG_CPU_S3C2442
+static struct s3c_irq_data init_s3c2442base[32] = {
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
+        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
+        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
+        { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
+        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
+        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
+        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
+        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
+};
+
+static struct s3c_irq_data init_s3c2442subint[32] = {
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
+        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
+        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
+};
+
+void __init s3c2442_init_irq(void)
+{
+        pr_info("S3C2442: IRQ Support\n");
+
+#ifdef CONFIG_FIQ
+        init_FIQ(FIQ_START);
+#endif
+
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
+                pr_err("irq: could not create main interrupt controller\n");
+                return;
+        }
+
+        s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
+                                        s3c_intc[0], 0x4a000018);
+}
 #endif
 
 #ifdef CONFIG_CPU_S3C2443
@@ -801,21 +1138,219 @@ static struct s3c_irq_data init_s3c2443subint[32] = {
 
 void __init s3c2443_init_irq(void)
 {
-        struct s3c_irq_intc *main_intc;
-
         pr_info("S3C2443: IRQ Support\n");
 
 #ifdef CONFIG_FIQ
         init_FIQ(FIQ_START);
 #endif
 
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
+        s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
+                                        0x4a000000);
+        if (IS_ERR(s3c_intc[0])) {
                 pr_err("irq: could not create main interrupt controller\n");
                 return;
         }
 
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
+        s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
+        s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
+                                        s3c_intc[0], 0x4a000018);
+}
+#endif
+
+#ifdef CONFIG_OF
+static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        unsigned int ctrl_num = hw / 32;
+        unsigned int intc_hw = hw % 32;
+        struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
+        struct s3c_irq_intc *parent_intc = intc->parent;
+        struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
+
+        /* attach controller pointer to irq_data */
+        irq_data->intc = intc;
+        irq_data->offset = intc_hw;
+
+        if (!parent_intc)
+                irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
+        else
+                irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
+                                         handle_edge_irq);
+
+        irq_set_chip_data(virq, irq_data);
+
+        set_irq_flags(virq, IRQF_VALID);
+
+        return 0;
+}
+
+/* Translate our of irq notation
+ * format: <ctrl_num ctrl_irq parent_irq type>
+ */
+static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
+                        const u32 *intspec, unsigned int intsize,
+                        irq_hw_number_t *out_hwirq, unsigned int *out_type)
+{
+        struct s3c_irq_intc *intc;
+        struct s3c_irq_intc *parent_intc;
+        struct s3c_irq_data *irq_data;
+        struct s3c_irq_data *parent_irq_data;
+        int irqno;
+
+        if (WARN_ON(intsize < 4))
+                return -EINVAL;
+
+        if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
+                pr_err("controller number %d invalid\n", intspec[0]);
+                return -EINVAL;
+        }
+        intc = s3c_intc[intspec[0]];
+
+        *out_hwirq = intspec[0] * 32 + intspec[2];
+        *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
+
+        parent_intc = intc->parent;
+        if (parent_intc) {
+                irq_data = &intc->irqs[intspec[2]];
+                irq_data->parent_irq = intspec[1];
+                parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
+                parent_irq_data->sub_intc = intc;
+                parent_irq_data->sub_bits |= (1UL << intspec[2]);
+
+                /* parent_intc is always s3c_intc[0], so no offset */
+                irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
+                if (irqno < 0) {
+                        pr_err("irq: could not map parent interrupt\n");
+                        return irqno;
+                }
+
+                irq_set_chained_handler(irqno, s3c_irq_demux);
+        }
+
+        return 0;
+}
+
+static struct irq_domain_ops s3c24xx_irq_ops_of = {
+        .map = s3c24xx_irq_map_of,
+        .xlate = s3c24xx_irq_xlate_of,
+};
+
+struct s3c24xx_irq_of_ctrl {
+        char                    *name;
+        unsigned long           offset;
+        struct s3c_irq_intc     **handle;
+        struct s3c_irq_intc     **parent;
+        struct irq_domain_ops   *ops;
+};
+
+static int __init s3c_init_intc_of(struct device_node *np,
+                        struct device_node *interrupt_parent,
+                        struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
+{
+        struct s3c_irq_intc *intc;
+        struct s3c24xx_irq_of_ctrl *ctrl;
+        struct irq_domain *domain;
+        void __iomem *reg_base;
+        int i;
+
+        reg_base = of_iomap(np, 0);
+        if (!reg_base) {
+                pr_err("irq-s3c24xx: could not map irq registers\n");
+                return -EINVAL;
+        }
+
+        domain = irq_domain_add_linear(np, num_ctrl * 32,
+                                                     &s3c24xx_irq_ops_of, NULL);
+        if (!domain) {
+                pr_err("irq: could not create irq-domain\n");
+                return -EINVAL;
+        }
+
+        for (i = 0; i < num_ctrl; i++) {
+                ctrl = &s3c_ctrl[i];
+
+                pr_debug("irq: found controller %s\n", ctrl->name);
+
+                intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
+                if (!intc)
+                        return -ENOMEM;
+
+                intc->domain = domain;
+                intc->irqs = kzalloc(sizeof(struct s3c_irq_data) * 32,
+                                     GFP_KERNEL);
+                if (!intc->irqs) {
+                        kfree(intc);
+                        return -ENOMEM;
+                }
+
+                if (ctrl->parent) {
+                        intc->reg_pending = reg_base + ctrl->offset;
+                        intc->reg_mask = reg_base + ctrl->offset + 0x4;
+
+                        if (*(ctrl->parent)) {
+                                intc->parent = *(ctrl->parent);
+                        } else {
+                                pr_warn("irq: parent of %s missing\n",
+                                        ctrl->name);
+                                kfree(intc->irqs);
+                                kfree(intc);
+                                continue;
+                        }
+                } else {
+                        intc->reg_pending = reg_base + ctrl->offset;
+                        intc->reg_mask = reg_base + ctrl->offset + 0x08;
+                        intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
+                }
+
+                s3c24xx_clear_intc(intc);
+                s3c_intc[i] = intc;
+        }
+
+        set_handle_irq(s3c24xx_handle_irq);
+
+        return 0;
+}
+
+static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
+        {
+                .name = "intc",
+                .offset = 0,
+        }, {
+                .name = "subintc",
+                .offset = 0x18,
+                .parent = &s3c_intc[0],
+        }
+};
+
+int __init s3c2410_init_intc_of(struct device_node *np,
+                        struct device_node *interrupt_parent,
+                        struct s3c24xx_irq_of_ctrl *ctrl, int num_ctrl)
+{
+        return s3c_init_intc_of(np, interrupt_parent,
+                                s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
+}
+IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
+
+static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
+        {
+                .name = "intc",
+                .offset = 0,
+        }, {
+                .name = "subintc",
+                .offset = 0x18,
+                .parent = &s3c_intc[0],
+        }, {
+                .name = "intc2",
+                .offset = 0x40,
+        }
+};
+
+int __init s3c2416_init_intc_of(struct device_node *np,
+                        struct device_node *interrupt_parent,
+                        struct s3c24xx_irq_of_ctrl *ctrl, int num_ctrl)
+{
+        return s3c_init_intc_of(np, interrupt_parent,
+                                s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
 }
+IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
 #endif
diff --git a/arch/arm/mach-vt8500/irq.c b/drivers/irqchip/irq-vt8500.c
index b9cf5ce9efbb..d97059550a2c 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/drivers/irqchip/irq-vt8500.c
@@ -37,6 +37,9 @@
 
 #include <asm/irq.h>
 #include <asm/exception.h>
+#include <asm/mach/irq.h>
+
+#include "irqchip.h"
 
 #define VT8500_ICPC_IRQ         0x20
 #define VT8500_ICPC_FIQ         0x24
@@ -225,6 +228,8 @@ int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
                 goto out;
         }
 
+        set_handle_irq(vt8500_handle_irq);
+
         vt8500_init_irq_hw(intc[active_cnt].base);
 
         pr_info("vt8500-irq: Added interrupt controller\n");
@@ -251,3 +256,4 @@ out:
         return 0;
 }
 
+IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 0a2bdd106b23..c76d16c972cc 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -747,6 +747,64 @@ struct device_node *of_find_node_by_phandle(phandle handle)
 EXPORT_SYMBOL(of_find_node_by_phandle);
 
 /**
+ * of_find_property_value_of_size
+ *
+ * @np:         device node from which the property value is to be read.
+ * @propname:   name of the property to be searched.
+ * @len:        requested length of property value
+ *
+ * Search for a property in a device node and valid the requested size.
+ * Returns the property value on success, -EINVAL if the property does not
+ *  exist, -ENODATA if property does not have a value, and -EOVERFLOW if the
+ * property data isn't large enough.
+ *
+ */
+static void *of_find_property_value_of_size(const struct device_node *np,
+                        const char *propname, u32 len)
+{
+        struct property *prop = of_find_property(np, propname, NULL);
+
+        if (!prop)
+                return ERR_PTR(-EINVAL);
+        if (!prop->value)
+                return ERR_PTR(-ENODATA);
+        if (len > prop->length)
+                return ERR_PTR(-EOVERFLOW);
+
+        return prop->value;
+}
+
+/**
+ * of_property_read_u32_index - Find and read a u32 from a multi-value property.
+ *
+ * @np:         device node from which the property value is to be read.
+ * @propname:   name of the property to be searched.
+ * @index:      index of the u32 in the list of values
+ * @out_value:  pointer to return value, modified only if no error.
+ *
+ * Search for a property in a device node and read nth 32-bit value from
+ * it. Returns 0 on success, -EINVAL if the property does not exist,
+ * -ENODATA if property does not have a value, and -EOVERFLOW if the
+ * property data isn't large enough.
+ *
+ * The out_value is modified only if a valid u32 value can be decoded.
+ */
+int of_property_read_u32_index(const struct device_node *np,
+                                       const char *propname,
+                                       u32 index, u32 *out_value)
+{
+        const u32 *val = of_find_property_value_of_size(np, propname,
+                                        ((index + 1) * sizeof(*out_value)));
+
+        if (IS_ERR(val))
+                return PTR_ERR(val);
+
+        *out_value = be32_to_cpup(((__be32 *)val) + index);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(of_property_read_u32_index);
+
+/**
  * of_property_read_u8_array - Find and read an array of u8 from a property.
  *
  * @np:         device node from which the property value is to be read.
@@ -767,17 +825,12 @@ EXPORT_SYMBOL(of_find_node_by_phandle);
 int of_property_read_u8_array(const struct device_node *np,
                         const char *propname, u8 *out_values, size_t sz)
 {
-        struct property *prop = of_find_property(np, propname, NULL);
-        const u8 *val;
+        const u8 *val = of_find_property_value_of_size(np, propname,
+                                                (sz * sizeof(*out_values)));
 
-        if (!prop)
-                return -EINVAL;
-        if (!prop->value)
-                return -ENODATA;
-        if ((sz * sizeof(*out_values)) > prop->length)
-                return -EOVERFLOW;
+        if (IS_ERR(val))
+                return PTR_ERR(val);
 
-        val = prop->value;
         while (sz--)
                 *out_values++ = *val++;
         return 0;
@@ -805,17 +858,12 @@ EXPORT_SYMBOL_GPL(of_property_read_u8_array);
 int of_property_read_u16_array(const struct device_node *np,
                         const char *propname, u16 *out_values, size_t sz)
 {
-        struct property *prop = of_find_property(np, propname, NULL);
-        const __be16 *val;
+        const __be16 *val = of_find_property_value_of_size(np, propname,
+                                                (sz * sizeof(*out_values)));
 
-        if (!prop)
-                return -EINVAL;
-        if (!prop->value)
-                return -ENODATA;
-        if ((sz * sizeof(*out_values)) > prop->length)
-                return -EOVERFLOW;
+        if (IS_ERR(val))
+                return PTR_ERR(val);
 
-        val = prop->value;
         while (sz--)
                 *out_values++ = be16_to_cpup(val++);
         return 0;
@@ -842,17 +890,12 @@ int of_property_read_u32_array(const struct device_node *np,
                                const char *propname, u32 *out_values,
                                size_t sz)
 {
-        struct property *prop = of_find_property(np, propname, NULL);
-        const __be32 *val;
+        const __be32 *val = of_find_property_value_of_size(np, propname,
+                                                (sz * sizeof(*out_values)));
 
-        if (!prop)
-                return -EINVAL;
-        if (!prop->value)
-                return -ENODATA;
-        if ((sz * sizeof(*out_values)) > prop->length)
-                return -EOVERFLOW;
+        if (IS_ERR(val))
+                return PTR_ERR(val);
 
-        val = prop->value;
         while (sz--)
                 *out_values++ = be32_to_cpup(val++);
         return 0;
@@ -875,15 +918,13 @@ EXPORT_SYMBOL_GPL(of_property_read_u32_array);
 int of_property_read_u64(const struct device_node *np, const char *propname,
                          u64 *out_value)
 {
-        struct property *prop = of_find_property(np, propname, NULL);
+        const __be32 *val = of_find_property_value_of_size(np, propname,
+                                                sizeof(*out_value));
 
-        if (!prop)
-                return -EINVAL;
-        if (!prop->value)
-                return -ENODATA;
-        if (sizeof(*out_value) > prop->length)
-                return -EOVERFLOW;
-        *out_value = of_read_number(prop->value, 2);
+        if (IS_ERR(val))
+                return PTR_ERR(val);
+
+        *out_value = of_read_number(val, 2);
         return 0;
 }
 EXPORT_SYMBOL_GPL(of_property_read_u64);
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 51336b2aedc9..8f6692438149 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -224,6 +224,7 @@ config PINCTRL_S3C64XX
 source "drivers/pinctrl/mvebu/Kconfig"
 source "drivers/pinctrl/sh-pfc/Kconfig"
 source "drivers/pinctrl/spear/Kconfig"
+source "drivers/pinctrl/vt8500/Kconfig"
 
 config PINCTRL_XWAY
         bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index b9aaa61facd1..9bdaeb8785ce 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -50,3 +50,4 @@ obj-$(CONFIG_PLAT_ORION)        += mvebu/
 obj-$(CONFIG_ARCH_SHMOBILE)     += sh-pfc/
 obj-$(CONFIG_SUPERH)            += sh-pfc/
 obj-$(CONFIG_PLAT_SPEAR)        += spear/
+obj-$(CONFIG_ARCH_VT8500)       += vt8500/
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index f28d4b08771a..c8f20a3d8f88 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -699,11 +699,6 @@ static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
         return 0;
 }
 
-static inline u32 prop_u32(struct property *p, int i)
-{
-        return be32_to_cpup(((__be32 *)p->value) + i);
-}
-
 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
                 struct device_node *np,
                 struct pinctrl_map **map, unsigned *num_maps)
@@ -761,7 +756,9 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
                 return -ENOMEM;
 
         for (i = 0; i < num_pins; i++) {
-                pin = prop_u32(pins, i);
+                err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
+                if (err)
+                        goto out;
                 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
                         dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
                                 of_node_full_name(np), pin);
@@ -770,14 +767,20 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
                 }
 
                 if (num_funcs) {
-                        func = prop_u32(funcs, (num_funcs > 1) ? i : 0);
+                        err = of_property_read_u32_index(np, "brcm,function",
+                                        (num_funcs > 1) ? i : 0, &func);
+                        if (err)
+                                goto out;
                         err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
                                                         func, &cur_map);
                         if (err)
                                 goto out;
                 }
                 if (num_pulls) {
-                        pull = prop_u32(pulls, (num_pulls > 1) ? i : 0);
+                        err = of_property_read_u32_index(np, "brcm,pull",
+                                        (num_funcs > 1) ? i : 0, &pull);
+                        if (err)
+                                goto out;
                         err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
                                                         pull, &cur_map);
                         if (err)
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index ec1567842a7e..ac742817ebce 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -700,3 +700,111 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
                 .label          = "exynos4x12-gpio-ctrl3",
         },
 };
+
+/* pin banks of exynos5250 pin-controller 0 */
+static struct samsung_pin_bank exynos5250_pin_banks0[] = {
+        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
+        EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
+        EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
+        EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
+        EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
+        EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
+        EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
+        EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
+        EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
+        EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
+        EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
+        EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
+        EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
+        EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
+        EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
+        EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
+        EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
+};
+
+/* pin banks of exynos5250 pin-controller 1 */
+static struct samsung_pin_bank exynos5250_pin_banks1[] = {
+        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
+        EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
+        EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
+        EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
+        EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
+        EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
+        EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
+        EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
+};
+
+/* pin banks of exynos5250 pin-controller 2 */
+static struct samsung_pin_bank exynos5250_pin_banks2[] = {
+        EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
+        EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
+        EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
+        EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
+        EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
+};
+
+/* pin banks of exynos5250 pin-controller 3 */
+static struct samsung_pin_bank exynos5250_pin_banks3[] = {
+        EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
+ * four gpio/pin-mux/pinconfig controllers.
+ */
+struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
+        {
+                /* pin-controller instance 0 data */
+                .pin_banks      = exynos5250_pin_banks0,
+                .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks0),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .weint_con      = EXYNOS_WKUP_ECON_OFFSET,
+                .weint_mask     = EXYNOS_WKUP_EMASK_OFFSET,
+                .weint_pend     = EXYNOS_WKUP_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .eint_wkup_init = exynos_eint_wkup_init,
+                .label          = "exynos5250-gpio-ctrl0",
+        }, {
+                /* pin-controller instance 1 data */
+                .pin_banks      = exynos5250_pin_banks1,
+                .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks1),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .label          = "exynos5250-gpio-ctrl1",
+        }, {
+                /* pin-controller instance 2 data */
+                .pin_banks      = exynos5250_pin_banks2,
+                .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks2),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .label          = "exynos5250-gpio-ctrl2",
+        }, {
+                /* pin-controller instance 3 data */
+                .pin_banks      = exynos5250_pin_banks3,
+                .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks3),
+                .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
+                .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
+                .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
+                .svc            = EXYNOS_SVC_OFFSET,
+                .eint_gpio_init = exynos_eint_gpio_init,
+                .label          = "exynos5250-gpio-ctrl3",
+        },
+};
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 4f54faf2971f..976366899f68 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -970,6 +970,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
                 .data = (void *)exynos4210_pin_ctrl },
         { .compatible = "samsung,exynos4x12-pinctrl",
                 .data = (void *)exynos4x12_pin_ctrl },
+        { .compatible = "samsung,exynos5250-pinctrl",
+                .data = (void *)exynos5250_pin_ctrl },
 #endif
 #ifdef CONFIG_PINCTRL_S3C64XX
         { .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 45f27b41e30c..7c7f9ebcd05b 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -244,6 +244,7 @@ struct samsung_pmx_func {
 /* list of all exported SoC specific data */
 extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
 extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
+extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
 extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
 
 #endif /* __PINCTRL_SAMSUNG_H */
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 709008e94124..6f15c03077a0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2733,9 +2733,9 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
         { },
 };
 
-/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
-#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
-#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
+/* External IRQ pins mapped at IRQPIN_BASE */
+#define EXT_IRQ16L(n) irq_pin(n)
+#define EXT_IRQ16H(n) irq_pin(n)
 
 static struct pinmux_irq pinmux_irqs[] = {
         PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
diff --git a/drivers/pinctrl/vt8500/Kconfig b/drivers/pinctrl/vt8500/Kconfig
new file mode 100644
index 000000000000..55724a73d94a
--- /dev/null
+++ b/drivers/pinctrl/vt8500/Kconfig
@@ -0,0 +1,52 @@
+#
+# VIA/Wondermedia PINCTRL drivers
+#
+
+if ARCH_VT8500
+
+config PINCTRL_WMT
+        bool
+        select PINMUX
+        select GENERIC_PINCONF
+
+config PINCTRL_VT8500
+        bool "VIA VT8500 pin controller driver"
+        depends on ARCH_WM8505
+        select PINCTRL_WMT
+        help
+          Say yes here to support the gpio/pin control module on
+          VIA VT8500 SoCs.
+
+config PINCTRL_WM8505
+        bool "Wondermedia WM8505 pin controller driver"
+        depends on ARCH_WM8505
+        select PINCTRL_WMT
+        help
+          Say yes here to support the gpio/pin control module on
+          Wondermedia WM8505 SoCs.
+
+config PINCTRL_WM8650
+        bool "Wondermedia WM8650 pin controller driver"
+        depends on ARCH_WM8505
+        select PINCTRL_WMT
+        help
+          Say yes here to support the gpio/pin control module on
+          Wondermedia WM8650 SoCs.
+
+config PINCTRL_WM8750
+        bool "Wondermedia WM8750 pin controller driver"
+        depends on ARCH_WM8750
+        select PINCTRL_WMT
+        help
+          Say yes here to support the gpio/pin control module on
+          Wondermedia WM8750 SoCs.
+
+config PINCTRL_WM8850
+        bool "Wondermedia WM8850 pin controller driver"
+        depends on ARCH_WM8850
+        select PINCTRL_WMT
+        help
+          Say yes here to support the gpio/pin control module on
+          Wondermedia WM8850 SoCs.
+
+endif
diff --git a/drivers/pinctrl/vt8500/Makefile b/drivers/pinctrl/vt8500/Makefile
new file mode 100644
index 000000000000..24ec45dd0d80
--- /dev/null
+++ b/drivers/pinctrl/vt8500/Makefile
@@ -0,0 +1,8 @@
+# VIA/Wondermedia pinctrl support
+
+obj-$(CONFIG_PINCTRL_WMT)       += pinctrl-wmt.o
+obj-$(CONFIG_PINCTRL_VT8500)    += pinctrl-vt8500.o
+obj-$(CONFIG_PINCTRL_WM8505)    += pinctrl-wm8505.o
+obj-$(CONFIG_PINCTRL_WM8650)    += pinctrl-wm8650.o
+obj-$(CONFIG_PINCTRL_WM8750)    += pinctrl-wm8750.o
+obj-$(CONFIG_PINCTRL_WM8850)    += pinctrl-wm8850.o
diff --git a/drivers/pinctrl/vt8500/pinctrl-vt8500.c b/drivers/pinctrl/vt8500/pinctrl-vt8500.c
new file mode 100644
index 000000000000..f2fe9f85cfa6
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-vt8500.c
@@ -0,0 +1,501 @@
+/*
+ * Pinctrl data for VIA VT8500 SoC
+ *
+ * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "pinctrl-wmt.h"
+
+/*
+ * Describe the register offsets within the GPIO memory space
+ * The dedicated external GPIO's should always be listed in bank 0
+ * so they are exported in the 0..31 range which is what users
+ * expect.
+ *
+ * Do not reorder these banks as it will change the pin numbering
+ */
+static const struct wmt_pinctrl_bank_registers vt8500_banks[] = {
+        WMT_PINCTRL_BANK(NO_REG, 0x3C, 0x5C, 0x7C, NO_REG, NO_REG),     /* 0 */
+        WMT_PINCTRL_BANK(0x00, 0x20, 0x40, 0x60, NO_REG, NO_REG),       /* 1 */
+        WMT_PINCTRL_BANK(0x04, 0x24, 0x44, 0x64, NO_REG, NO_REG),       /* 2 */
+        WMT_PINCTRL_BANK(0x08, 0x28, 0x48, 0x68, NO_REG, NO_REG),       /* 3 */
+        WMT_PINCTRL_BANK(0x0C, 0x2C, 0x4C, 0x6C, NO_REG, NO_REG),       /* 4 */
+        WMT_PINCTRL_BANK(0x10, 0x30, 0x50, 0x70, NO_REG, NO_REG),       /* 5 */
+        WMT_PINCTRL_BANK(0x14, 0x34, 0x54, 0x74, NO_REG, NO_REG),       /* 6 */
+};
+
+/* Please keep sorted by bank/bit */
+#define WMT_PIN_EXTGPIO0        WMT_PIN(0, 0)
+#define WMT_PIN_EXTGPIO1        WMT_PIN(0, 1)
+#define WMT_PIN_EXTGPIO2        WMT_PIN(0, 2)
+#define WMT_PIN_EXTGPIO3        WMT_PIN(0, 3)
+#define WMT_PIN_EXTGPIO4        WMT_PIN(0, 4)
+#define WMT_PIN_EXTGPIO5        WMT_PIN(0, 5)
+#define WMT_PIN_EXTGPIO6        WMT_PIN(0, 6)
+#define WMT_PIN_EXTGPIO7        WMT_PIN(0, 7)
+#define WMT_PIN_EXTGPIO8        WMT_PIN(0, 8)
+#define WMT_PIN_UART0RTS        WMT_PIN(1, 0)
+#define WMT_PIN_UART0TXD        WMT_PIN(1, 1)
+#define WMT_PIN_UART0CTS        WMT_PIN(1, 2)
+#define WMT_PIN_UART0RXD        WMT_PIN(1, 3)
+#define WMT_PIN_UART1RTS        WMT_PIN(1, 4)
+#define WMT_PIN_UART1TXD        WMT_PIN(1, 5)
+#define WMT_PIN_UART1CTS        WMT_PIN(1, 6)
+#define WMT_PIN_UART1RXD        WMT_PIN(1, 7)
+#define WMT_PIN_SPI0CLK         WMT_PIN(1, 8)
+#define WMT_PIN_SPI0SS          WMT_PIN(1, 9)
+#define WMT_PIN_SPI0MISO        WMT_PIN(1, 10)
+#define WMT_PIN_SPI0MOSI        WMT_PIN(1, 11)
+#define WMT_PIN_SPI1CLK         WMT_PIN(1, 12)
+#define WMT_PIN_SPI1SS          WMT_PIN(1, 13)
+#define WMT_PIN_SPI1MISO        WMT_PIN(1, 14)
+#define WMT_PIN_SPI1MOSI        WMT_PIN(1, 15)
+#define WMT_PIN_SPI2CLK         WMT_PIN(1, 16)
+#define WMT_PIN_SPI2SS          WMT_PIN(1, 17)
+#define WMT_PIN_SPI2MISO        WMT_PIN(1, 18)
+#define WMT_PIN_SPI2MOSI        WMT_PIN(1, 19)
+#define WMT_PIN_SDDATA0         WMT_PIN(2, 0)
+#define WMT_PIN_SDDATA1         WMT_PIN(2, 1)
+#define WMT_PIN_SDDATA2         WMT_PIN(2, 2)
+#define WMT_PIN_SDDATA3         WMT_PIN(2, 3)
+#define WMT_PIN_MMCDATA0        WMT_PIN(2, 4)
+#define WMT_PIN_MMCDATA1        WMT_PIN(2, 5)
+#define WMT_PIN_MMCDATA2        WMT_PIN(2, 6)
+#define WMT_PIN_MMCDATA3        WMT_PIN(2, 7)
+#define WMT_PIN_SDCLK           WMT_PIN(2, 8)
+#define WMT_PIN_SDWP            WMT_PIN(2, 9)
+#define WMT_PIN_SDCMD           WMT_PIN(2, 10)
+#define WMT_PIN_MSDATA0         WMT_PIN(2, 16)
+#define WMT_PIN_MSDATA1         WMT_PIN(2, 17)
+#define WMT_PIN_MSDATA2         WMT_PIN(2, 18)
+#define WMT_PIN_MSDATA3         WMT_PIN(2, 19)
+#define WMT_PIN_MSCLK           WMT_PIN(2, 20)
+#define WMT_PIN_MSBS            WMT_PIN(2, 21)
+#define WMT_PIN_MSINS           WMT_PIN(2, 22)
+#define WMT_PIN_I2C0SCL         WMT_PIN(2, 24)
+#define WMT_PIN_I2C0SDA         WMT_PIN(2, 25)
+#define WMT_PIN_I2C1SCL         WMT_PIN(2, 26)
+#define WMT_PIN_I2C1SDA         WMT_PIN(2, 27)
+#define WMT_PIN_MII0RXD0        WMT_PIN(3, 0)
+#define WMT_PIN_MII0RXD1        WMT_PIN(3, 1)
+#define WMT_PIN_MII0RXD2        WMT_PIN(3, 2)
+#define WMT_PIN_MII0RXD3        WMT_PIN(3, 3)
+#define WMT_PIN_MII0RXCLK       WMT_PIN(3, 4)
+#define WMT_PIN_MII0RXDV        WMT_PIN(3, 5)
+#define WMT_PIN_MII0RXERR       WMT_PIN(3, 6)
+#define WMT_PIN_MII0PHYRST      WMT_PIN(3, 7)
+#define WMT_PIN_MII0TXD0        WMT_PIN(3, 8)
+#define WMT_PIN_MII0TXD1        WMT_PIN(3, 9)
+#define WMT_PIN_MII0TXD2        WMT_PIN(3, 10)
+#define WMT_PIN_MII0TXD3        WMT_PIN(3, 11)
+#define WMT_PIN_MII0TXCLK       WMT_PIN(3, 12)
+#define WMT_PIN_MII0TXEN        WMT_PIN(3, 13)
+#define WMT_PIN_MII0TXERR       WMT_PIN(3, 14)
+#define WMT_PIN_MII0PHYPD       WMT_PIN(3, 15)
+#define WMT_PIN_MII0COL         WMT_PIN(3, 16)
+#define WMT_PIN_MII0CRS         WMT_PIN(3, 17)
+#define WMT_PIN_MII0MDIO        WMT_PIN(3, 18)
+#define WMT_PIN_MII0MDC         WMT_PIN(3, 19)
+#define WMT_PIN_SEECS           WMT_PIN(3, 20)
+#define WMT_PIN_SEECK           WMT_PIN(3, 21)
+#define WMT_PIN_SEEDI           WMT_PIN(3, 22)
+#define WMT_PIN_SEEDO           WMT_PIN(3, 23)
+#define WMT_PIN_IDEDREQ0        WMT_PIN(3, 24)
+#define WMT_PIN_IDEDREQ1        WMT_PIN(3, 25)
+#define WMT_PIN_IDEIOW          WMT_PIN(3, 26)
+#define WMT_PIN_IDEIOR          WMT_PIN(3, 27)
+#define WMT_PIN_IDEDACK         WMT_PIN(3, 28)
+#define WMT_PIN_IDEIORDY        WMT_PIN(3, 29)
+#define WMT_PIN_IDEINTRQ        WMT_PIN(3, 30)
+#define WMT_PIN_VDIN0           WMT_PIN(4, 0)
+#define WMT_PIN_VDIN1           WMT_PIN(4, 1)
+#define WMT_PIN_VDIN2           WMT_PIN(4, 2)
+#define WMT_PIN_VDIN3           WMT_PIN(4, 3)
+#define WMT_PIN_VDIN4           WMT_PIN(4, 4)
+#define WMT_PIN_VDIN5           WMT_PIN(4, 5)
+#define WMT_PIN_VDIN6           WMT_PIN(4, 6)
+#define WMT_PIN_VDIN7           WMT_PIN(4, 7)
+#define WMT_PIN_VDOUT0          WMT_PIN(4, 8)
+#define WMT_PIN_VDOUT1          WMT_PIN(4, 9)
+#define WMT_PIN_VDOUT2          WMT_PIN(4, 10)
+#define WMT_PIN_VDOUT3          WMT_PIN(4, 11)
+#define WMT_PIN_VDOUT4          WMT_PIN(4, 12)
+#define WMT_PIN_VDOUT5          WMT_PIN(4, 13)
+#define WMT_PIN_NANDCLE0        WMT_PIN(4, 14)
+#define WMT_PIN_NANDCLE1        WMT_PIN(4, 15)
+#define WMT_PIN_VDOUT6_7        WMT_PIN(4, 16)
+#define WMT_PIN_VHSYNC          WMT_PIN(4, 17)
+#define WMT_PIN_VVSYNC          WMT_PIN(4, 18)
+#define WMT_PIN_TSDIN0          WMT_PIN(5, 8)
+#define WMT_PIN_TSDIN1          WMT_PIN(5, 9)
+#define WMT_PIN_TSDIN2          WMT_PIN(5, 10)
+#define WMT_PIN_TSDIN3          WMT_PIN(5, 11)
+#define WMT_PIN_TSDIN4          WMT_PIN(5, 12)
+#define WMT_PIN_TSDIN5          WMT_PIN(5, 13)
+#define WMT_PIN_TSDIN6          WMT_PIN(5, 14)
+#define WMT_PIN_TSDIN7          WMT_PIN(5, 15)
+#define WMT_PIN_TSSYNC          WMT_PIN(5, 16)
+#define WMT_PIN_TSVALID         WMT_PIN(5, 17)
+#define WMT_PIN_TSCLK           WMT_PIN(5, 18)
+#define WMT_PIN_LCDD0           WMT_PIN(6, 0)
+#define WMT_PIN_LCDD1           WMT_PIN(6, 1)
+#define WMT_PIN_LCDD2           WMT_PIN(6, 2)
+#define WMT_PIN_LCDD3           WMT_PIN(6, 3)
+#define WMT_PIN_LCDD4           WMT_PIN(6, 4)
+#define WMT_PIN_LCDD5           WMT_PIN(6, 5)
+#define WMT_PIN_LCDD6           WMT_PIN(6, 6)
+#define WMT_PIN_LCDD7           WMT_PIN(6, 7)
+#define WMT_PIN_LCDD8           WMT_PIN(6, 8)
+#define WMT_PIN_LCDD9           WMT_PIN(6, 9)
+#define WMT_PIN_LCDD10          WMT_PIN(6, 10)
+#define WMT_PIN_LCDD11          WMT_PIN(6, 11)
+#define WMT_PIN_LCDD12          WMT_PIN(6, 12)
+#define WMT_PIN_LCDD13          WMT_PIN(6, 13)
+#define WMT_PIN_LCDD14          WMT_PIN(6, 14)
+#define WMT_PIN_LCDD15          WMT_PIN(6, 15)
+#define WMT_PIN_LCDD16          WMT_PIN(6, 16)
+#define WMT_PIN_LCDD17          WMT_PIN(6, 17)
+#define WMT_PIN_LCDCLK          WMT_PIN(6, 18)
+#define WMT_PIN_LCDDEN          WMT_PIN(6, 19)
+#define WMT_PIN_LCDLINE         WMT_PIN(6, 20)
+#define WMT_PIN_LCDFRM          WMT_PIN(6, 21)
+#define WMT_PIN_LCDBIAS         WMT_PIN(6, 22)
+
+static const struct pinctrl_pin_desc vt8500_pins[] = {
+        PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO8, "extgpio8"),
+        PINCTRL_PIN(WMT_PIN_UART0RTS, "uart0_rts"),
+        PINCTRL_PIN(WMT_PIN_UART0TXD, "uart0_txd"),
+        PINCTRL_PIN(WMT_PIN_UART0CTS, "uart0_cts"),
+        PINCTRL_PIN(WMT_PIN_UART0RXD, "uart0_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART1RTS, "uart1_rts"),
+        PINCTRL_PIN(WMT_PIN_UART1TXD, "uart1_txd"),
+        PINCTRL_PIN(WMT_PIN_UART1CTS, "uart1_cts"),
+        PINCTRL_PIN(WMT_PIN_UART1RXD, "uart1_rxd"),
+        PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"),
+        PINCTRL_PIN(WMT_PIN_SPI0SS, "spi0_ss"),
+        PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"),
+        PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"),
+        PINCTRL_PIN(WMT_PIN_SPI1CLK, "spi1_clk"),
+        PINCTRL_PIN(WMT_PIN_SPI1SS, "spi1_ss"),
+        PINCTRL_PIN(WMT_PIN_SPI1MISO, "spi1_miso"),
+        PINCTRL_PIN(WMT_PIN_SPI1MOSI, "spi1_mosi"),
+        PINCTRL_PIN(WMT_PIN_SPI2CLK, "spi2_clk"),
+        PINCTRL_PIN(WMT_PIN_SPI2SS, "spi2_ss"),
+        PINCTRL_PIN(WMT_PIN_SPI2MISO, "spi2_miso"),
+        PINCTRL_PIN(WMT_PIN_SPI2MOSI, "spi2_mosi"),
+        PINCTRL_PIN(WMT_PIN_SDDATA0, "sd_data0"),
+        PINCTRL_PIN(WMT_PIN_SDDATA1, "sd_data1"),
+        PINCTRL_PIN(WMT_PIN_SDDATA2, "sd_data2"),
+        PINCTRL_PIN(WMT_PIN_SDDATA3, "sd_data3"),
+        PINCTRL_PIN(WMT_PIN_MMCDATA0, "mmc_data0"),
+        PINCTRL_PIN(WMT_PIN_MMCDATA1, "mmc_data1"),
+        PINCTRL_PIN(WMT_PIN_MMCDATA2, "mmc_data2"),
+        PINCTRL_PIN(WMT_PIN_MMCDATA3, "mmc_data3"),
+        PINCTRL_PIN(WMT_PIN_SDCLK, "sd_clk"),
+        PINCTRL_PIN(WMT_PIN_SDWP, "sd_wp"),
+        PINCTRL_PIN(WMT_PIN_SDCMD, "sd_cmd"),
+        PINCTRL_PIN(WMT_PIN_MSDATA0, "ms_data0"),
+        PINCTRL_PIN(WMT_PIN_MSDATA1, "ms_data1"),
+        PINCTRL_PIN(WMT_PIN_MSDATA2, "ms_data2"),
+        PINCTRL_PIN(WMT_PIN_MSDATA3, "ms_data3"),
+        PINCTRL_PIN(WMT_PIN_MSCLK, "ms_clk"),
+        PINCTRL_PIN(WMT_PIN_MSBS, "ms_bs"),
+        PINCTRL_PIN(WMT_PIN_MSINS, "ms_ins"),
+        PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"),
+        PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"),
+        PINCTRL_PIN(WMT_PIN_MII0RXD0, "mii0_rxd0"),
+        PINCTRL_PIN(WMT_PIN_MII0RXD1, "mii0_rxd1"),
+        PINCTRL_PIN(WMT_PIN_MII0RXD2, "mii0_rxd2"),
+        PINCTRL_PIN(WMT_PIN_MII0RXD3, "mii0_rxd3"),
+        PINCTRL_PIN(WMT_PIN_MII0RXCLK, "mii0_rxclk"),
+        PINCTRL_PIN(WMT_PIN_MII0RXDV, "mii0_rxdv"),
+        PINCTRL_PIN(WMT_PIN_MII0RXERR, "mii0_rxerr"),
+        PINCTRL_PIN(WMT_PIN_MII0PHYRST, "mii0_phyrst"),
+        PINCTRL_PIN(WMT_PIN_MII0TXD0, "mii0_txd0"),
+        PINCTRL_PIN(WMT_PIN_MII0TXD1, "mii0_txd1"),
+        PINCTRL_PIN(WMT_PIN_MII0TXD2, "mii0_txd2"),
+        PINCTRL_PIN(WMT_PIN_MII0TXD3, "mii0_txd3"),
+        PINCTRL_PIN(WMT_PIN_MII0TXCLK, "mii0_txclk"),
+        PINCTRL_PIN(WMT_PIN_MII0TXEN, "mii0_txen"),
+        PINCTRL_PIN(WMT_PIN_MII0TXERR, "mii0_txerr"),
+        PINCTRL_PIN(WMT_PIN_MII0PHYPD, "mii0_phypd"),
+        PINCTRL_PIN(WMT_PIN_MII0COL, "mii0_col"),
+        PINCTRL_PIN(WMT_PIN_MII0CRS, "mii0_crs"),
+        PINCTRL_PIN(WMT_PIN_MII0MDIO, "mii0_mdio"),
+        PINCTRL_PIN(WMT_PIN_MII0MDC, "mii0_mdc"),
+        PINCTRL_PIN(WMT_PIN_SEECS, "see_cs"),
+        PINCTRL_PIN(WMT_PIN_SEECK, "see_ck"),
+        PINCTRL_PIN(WMT_PIN_SEEDI, "see_di"),
+        PINCTRL_PIN(WMT_PIN_SEEDO, "see_do"),
+        PINCTRL_PIN(WMT_PIN_IDEDREQ0, "ide_dreq0"),
+        PINCTRL_PIN(WMT_PIN_IDEDREQ1, "ide_dreq1"),
+        PINCTRL_PIN(WMT_PIN_IDEIOW, "ide_iow"),
+        PINCTRL_PIN(WMT_PIN_IDEIOR, "ide_ior"),
+        PINCTRL_PIN(WMT_PIN_IDEDACK, "ide_dack"),
+        PINCTRL_PIN(WMT_PIN_IDEIORDY, "ide_iordy"),
+        PINCTRL_PIN(WMT_PIN_IDEINTRQ, "ide_intrq"),
+        PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
+        PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
+        PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
+        PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
+        PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
+        PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
+        PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
+        PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
+        PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
+        PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
+        PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
+        PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
+        PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
+        PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
+        PINCTRL_PIN(WMT_PIN_NANDCLE0, "nand_cle0"),
+        PINCTRL_PIN(WMT_PIN_NANDCLE1, "nand_cle1"),
+        PINCTRL_PIN(WMT_PIN_VDOUT6_7, "vdout6_7"),
+        PINCTRL_PIN(WMT_PIN_VHSYNC, "vhsync"),
+        PINCTRL_PIN(WMT_PIN_VVSYNC, "vvsync"),
+        PINCTRL_PIN(WMT_PIN_TSDIN0, "tsdin0"),
+        PINCTRL_PIN(WMT_PIN_TSDIN1, "tsdin1"),
+        PINCTRL_PIN(WMT_PIN_TSDIN2, "tsdin2"),
+        PINCTRL_PIN(WMT_PIN_TSDIN3, "tsdin3"),
+        PINCTRL_PIN(WMT_PIN_TSDIN4, "tsdin4"),
+        PINCTRL_PIN(WMT_PIN_TSDIN5, "tsdin5"),
+        PINCTRL_PIN(WMT_PIN_TSDIN6, "tsdin6"),
+        PINCTRL_PIN(WMT_PIN_TSDIN7, "tsdin7"),
+        PINCTRL_PIN(WMT_PIN_TSSYNC, "tssync"),
+        PINCTRL_PIN(WMT_PIN_TSVALID, "tsvalid"),
+        PINCTRL_PIN(WMT_PIN_TSCLK, "tsclk"),
+        PINCTRL_PIN(WMT_PIN_LCDD0, "lcd_d0"),
+        PINCTRL_PIN(WMT_PIN_LCDD1, "lcd_d1"),
+        PINCTRL_PIN(WMT_PIN_LCDD2, "lcd_d2"),
+        PINCTRL_PIN(WMT_PIN_LCDD3, "lcd_d3"),
+        PINCTRL_PIN(WMT_PIN_LCDD4, "lcd_d4"),
+        PINCTRL_PIN(WMT_PIN_LCDD5, "lcd_d5"),
+        PINCTRL_PIN(WMT_PIN_LCDD6, "lcd_d6"),
+        PINCTRL_PIN(WMT_PIN_LCDD7, "lcd_d7"),
+        PINCTRL_PIN(WMT_PIN_LCDD8, "lcd_d8"),
+        PINCTRL_PIN(WMT_PIN_LCDD9, "lcd_d9"),
+        PINCTRL_PIN(WMT_PIN_LCDD10, "lcd_d10"),
+        PINCTRL_PIN(WMT_PIN_LCDD11, "lcd_d11"),
+        PINCTRL_PIN(WMT_PIN_LCDD12, "lcd_d12"),
+        PINCTRL_PIN(WMT_PIN_LCDD13, "lcd_d13"),
+        PINCTRL_PIN(WMT_PIN_LCDD14, "lcd_d14"),
+        PINCTRL_PIN(WMT_PIN_LCDD15, "lcd_d15"),
+        PINCTRL_PIN(WMT_PIN_LCDD16, "lcd_d16"),
+        PINCTRL_PIN(WMT_PIN_LCDD17, "lcd_d17"),
+        PINCTRL_PIN(WMT_PIN_LCDCLK, "lcd_clk"),
+        PINCTRL_PIN(WMT_PIN_LCDDEN, "lcd_den"),
+        PINCTRL_PIN(WMT_PIN_LCDLINE, "lcd_line"),
+        PINCTRL_PIN(WMT_PIN_LCDFRM, "lcd_frm"),
+        PINCTRL_PIN(WMT_PIN_LCDBIAS, "lcd_bias"),
+};
+
+/* Order of these names must match the above list */
+static const char * const vt8500_groups[] = {
+        "extgpio0",
+        "extgpio1",
+        "extgpio2",
+        "extgpio3",
+        "extgpio4",
+        "extgpio5",
+        "extgpio6",
+        "extgpio7",
+        "extgpio8",
+        "uart0_rts",
+        "uart0_txd",
+        "uart0_cts",
+        "uart0_rxd",
+        "uart1_rts",
+        "uart1_txd",
+        "uart1_cts",
+        "uart1_rxd",
+        "spi0_clk",
+        "spi0_ss",
+        "spi0_miso",
+        "spi0_mosi",
+        "spi1_clk",
+        "spi1_ss",
+        "spi1_miso",
+        "spi1_mosi",
+        "spi2_clk",
+        "spi2_ss",
+        "spi2_miso",
+        "spi2_mosi",
+        "sd_data0",
+        "sd_data1",
+        "sd_data2",
+        "sd_data3",
+        "mmc_data0",
+        "mmc_data1",
+        "mmc_data2",
+        "mmc_data3",
+        "sd_clk",
+        "sd_wp",
+        "sd_cmd",
+        "ms_data0",
+        "ms_data1",
+        "ms_data2",
+        "ms_data3",
+        "ms_clk",
+        "ms_bs",
+        "ms_ins",
+        "i2c0_scl",
+        "i2c0_sda",
+        "i2c1_scl",
+        "i2c1_sda",
+        "mii0_rxd0",
+        "mii0_rxd1",
+        "mii0_rxd2",
+        "mii0_rxd3",
+        "mii0_rxclk",
+        "mii0_rxdv",
+        "mii0_rxerr",
+        "mii0_phyrst",
+        "mii0_txd0",
+        "mii0_txd1",
+        "mii0_txd2",
+        "mii0_txd3",
+        "mii0_txclk",
+        "mii0_txen",
+        "mii0_txerr",
+        "mii0_phypd",
+        "mii0_col",
+        "mii0_crs",
+        "mii0_mdio",
+        "mii0_mdc",
+        "see_cs",
+        "see_ck",
+        "see_di",
+        "see_do",
+        "ide_dreq0",
+        "ide_dreq1",
+        "ide_iow",
+        "ide_ior",
+        "ide_dack",
+        "ide_iordy",
+        "ide_intrq",
+        "vdin0",
+        "vdin1",
+        "vdin2",
+        "vdin3",
+        "vdin4",
+        "vdin5",
+        "vdin6",
+        "vdin7",
+        "vdout0",
+        "vdout1",
+        "vdout2",
+        "vdout3",
+        "vdout4",
+        "vdout5",
+        "nand_cle0",
+        "nand_cle1",
+        "vdout6_7",
+        "vhsync",
+        "vvsync",
+        "tsdin0",
+        "tsdin1",
+        "tsdin2",
+        "tsdin3",
+        "tsdin4",
+        "tsdin5",
+        "tsdin6",
+        "tsdin7",
+        "tssync",
+        "tsvalid",
+        "tsclk",
+        "lcd_d0",
+        "lcd_d1",
+        "lcd_d2",
+        "lcd_d3",
+        "lcd_d4",
+        "lcd_d5",
+        "lcd_d6",
+        "lcd_d7",
+        "lcd_d8",
+        "lcd_d9",
+        "lcd_d10",
+        "lcd_d11",
+        "lcd_d12",
+        "lcd_d13",
+        "lcd_d14",
+        "lcd_d15",
+        "lcd_d16",
+        "lcd_d17",
+        "lcd_clk",
+        "lcd_den",
+        "lcd_line",
+        "lcd_frm",
+        "lcd_bias",
+};
+
+static int vt8500_pinctrl_probe(struct platform_device *pdev)
+{
+        struct wmt_pinctrl_data *data;
+
+        data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+        if (!data) {
+                dev_err(&pdev->dev, "failed to allocate data\n");
+                return -ENOMEM;
+        }
+
+        data->banks = vt8500_banks;
+        data->nbanks = ARRAY_SIZE(vt8500_banks);
+        data->pins = vt8500_pins;
+        data->npins = ARRAY_SIZE(vt8500_pins);
+        data->groups = vt8500_groups;
+        data->ngroups = ARRAY_SIZE(vt8500_groups);
+
+        return wmt_pinctrl_probe(pdev, data);
+}
+
+static int vt8500_pinctrl_remove(struct platform_device *pdev)
+{
+        return wmt_pinctrl_remove(pdev);
+}
+
+static struct of_device_id wmt_pinctrl_of_match[] = {
+        { .compatible = "via,vt8500-pinctrl" },
+        { /* sentinel */ },
+};
+
+static struct platform_driver wmt_pinctrl_driver = {
+        .probe  = vt8500_pinctrl_probe,
+        .remove = vt8500_pinctrl_remove,
+        .driver = {
+                .name   = "pinctrl-vt8500",
+                .owner  = THIS_MODULE,
+                .of_match_table = wmt_pinctrl_of_match,
+        },
+};
+
+module_platform_driver(wmt_pinctrl_driver);
+
+MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
+MODULE_DESCRIPTION("VIA VT8500 Pincontrol driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8505.c b/drivers/pinctrl/vt8500/pinctrl-wm8505.c
new file mode 100644
index 000000000000..483ba732694e
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8505.c
@@ -0,0 +1,532 @@
+/*
+ * Pinctrl data for Wondermedia WM8505 SoC
+ *
+ * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "pinctrl-wmt.h"
+
+/*
+ * Describe the register offsets within the GPIO memory space
+ * The dedicated external GPIO's should always be listed in bank 0
+ * so they are exported in the 0..31 range which is what users
+ * expect.
+ *
+ * Do not reorder these banks as it will change the pin numbering
+ */
+static const struct wmt_pinctrl_bank_registers wm8505_banks[] = {
+        WMT_PINCTRL_BANK(0x64, 0x8C, 0xB4, 0xDC, NO_REG, NO_REG),       /* 0 */
+        WMT_PINCTRL_BANK(0x40, 0x68, 0x90, 0xB8, NO_REG, NO_REG),       /* 1 */
+        WMT_PINCTRL_BANK(0x44, 0x6C, 0x94, 0xBC, NO_REG, NO_REG),       /* 2 */
+        WMT_PINCTRL_BANK(0x48, 0x70, 0x98, 0xC0, NO_REG, NO_REG),       /* 3 */
+        WMT_PINCTRL_BANK(0x4C, 0x74, 0x9C, 0xC4, NO_REG, NO_REG),       /* 4 */
+        WMT_PINCTRL_BANK(0x50, 0x78, 0xA0, 0xC8, NO_REG, NO_REG),       /* 5 */
+        WMT_PINCTRL_BANK(0x54, 0x7C, 0xA4, 0xD0, NO_REG, NO_REG),       /* 6 */
+        WMT_PINCTRL_BANK(0x58, 0x80, 0xA8, 0xD4, NO_REG, NO_REG),       /* 7 */
+        WMT_PINCTRL_BANK(0x5C, 0x84, 0xAC, 0xD8, NO_REG, NO_REG),       /* 8 */
+        WMT_PINCTRL_BANK(0x60, 0x88, 0xB0, 0xDC, NO_REG, NO_REG),       /* 9 */
+        WMT_PINCTRL_BANK(0x500, 0x504, 0x508, 0x50C, NO_REG, NO_REG),   /* 10 */
+};
+
+/* Please keep sorted by bank/bit */
+#define WMT_PIN_EXTGPIO0        WMT_PIN(0, 0)
+#define WMT_PIN_EXTGPIO1        WMT_PIN(0, 1)
+#define WMT_PIN_EXTGPIO2        WMT_PIN(0, 2)
+#define WMT_PIN_EXTGPIO3        WMT_PIN(0, 3)
+#define WMT_PIN_EXTGPIO4        WMT_PIN(0, 4)
+#define WMT_PIN_EXTGPIO5        WMT_PIN(0, 5)
+#define WMT_PIN_EXTGPIO6        WMT_PIN(0, 6)
+#define WMT_PIN_EXTGPIO7        WMT_PIN(0, 7)
+#define WMT_PIN_WAKEUP0         WMT_PIN(0, 16)
+#define WMT_PIN_WAKEUP1         WMT_PIN(0, 17)
+#define WMT_PIN_WAKEUP2         WMT_PIN(0, 18)
+#define WMT_PIN_WAKEUP3         WMT_PIN(0, 19)
+#define WMT_PIN_SUSGPIO0        WMT_PIN(0, 21)
+#define WMT_PIN_SDDATA0         WMT_PIN(1, 0)
+#define WMT_PIN_SDDATA1         WMT_PIN(1, 1)
+#define WMT_PIN_SDDATA2         WMT_PIN(1, 2)
+#define WMT_PIN_SDDATA3         WMT_PIN(1, 3)
+#define WMT_PIN_MMCDATA0        WMT_PIN(1, 4)
+#define WMT_PIN_MMCDATA1        WMT_PIN(1, 5)
+#define WMT_PIN_MMCDATA2        WMT_PIN(1, 6)
+#define WMT_PIN_MMCDATA3        WMT_PIN(1, 7)
+#define WMT_PIN_VDIN0           WMT_PIN(2, 0)
+#define WMT_PIN_VDIN1           WMT_PIN(2, 1)
+#define WMT_PIN_VDIN2           WMT_PIN(2, 2)
+#define WMT_PIN_VDIN3           WMT_PIN(2, 3)
+#define WMT_PIN_VDIN4           WMT_PIN(2, 4)
+#define WMT_PIN_VDIN5           WMT_PIN(2, 5)
+#define WMT_PIN_VDIN6           WMT_PIN(2, 6)
+#define WMT_PIN_VDIN7           WMT_PIN(2, 7)
+#define WMT_PIN_VDOUT0          WMT_PIN(2, 8)
+#define WMT_PIN_VDOUT1          WMT_PIN(2, 9)
+#define WMT_PIN_VDOUT2          WMT_PIN(2, 10)
+#define WMT_PIN_VDOUT3          WMT_PIN(2, 11)
+#define WMT_PIN_VDOUT4          WMT_PIN(2, 12)
+#define WMT_PIN_VDOUT5          WMT_PIN(2, 13)
+#define WMT_PIN_VDOUT6          WMT_PIN(2, 14)
+#define WMT_PIN_VDOUT7          WMT_PIN(2, 15)
+#define WMT_PIN_VDOUT8          WMT_PIN(2, 16)
+#define WMT_PIN_VDOUT9          WMT_PIN(2, 17)
+#define WMT_PIN_VDOUT10         WMT_PIN(2, 18)
+#define WMT_PIN_VDOUT11         WMT_PIN(2, 19)
+#define WMT_PIN_VDOUT12         WMT_PIN(2, 20)
+#define WMT_PIN_VDOUT13         WMT_PIN(2, 21)
+#define WMT_PIN_VDOUT14         WMT_PIN(2, 22)
+#define WMT_PIN_VDOUT15         WMT_PIN(2, 23)
+#define WMT_PIN_VDOUT16         WMT_PIN(2, 24)
+#define WMT_PIN_VDOUT17         WMT_PIN(2, 25)
+#define WMT_PIN_VDOUT18         WMT_PIN(2, 26)
+#define WMT_PIN_VDOUT19         WMT_PIN(2, 27)
+#define WMT_PIN_VDOUT20         WMT_PIN(2, 28)
+#define WMT_PIN_VDOUT21         WMT_PIN(2, 29)
+#define WMT_PIN_VDOUT22         WMT_PIN(2, 30)
+#define WMT_PIN_VDOUT23         WMT_PIN(2, 31)
+#define WMT_PIN_VHSYNC          WMT_PIN(3, 0)
+#define WMT_PIN_VVSYNC          WMT_PIN(3, 1)
+#define WMT_PIN_VGAHSYNC        WMT_PIN(3, 2)
+#define WMT_PIN_VGAVSYNC        WMT_PIN(3, 3)
+#define WMT_PIN_VDHSYNC         WMT_PIN(3, 4)
+#define WMT_PIN_VDVSYNC         WMT_PIN(3, 5)
+#define WMT_PIN_NORD0           WMT_PIN(4, 0)
+#define WMT_PIN_NORD1           WMT_PIN(4, 1)
+#define WMT_PIN_NORD2           WMT_PIN(4, 2)
+#define WMT_PIN_NORD3           WMT_PIN(4, 3)
+#define WMT_PIN_NORD4           WMT_PIN(4, 4)
+#define WMT_PIN_NORD5           WMT_PIN(4, 5)
+#define WMT_PIN_NORD6           WMT_PIN(4, 6)
+#define WMT_PIN_NORD7           WMT_PIN(4, 7)
+#define WMT_PIN_NORD8           WMT_PIN(4, 8)
+#define WMT_PIN_NORD9           WMT_PIN(4, 9)
+#define WMT_PIN_NORD10          WMT_PIN(4, 10)
+#define WMT_PIN_NORD11          WMT_PIN(4, 11)
+#define WMT_PIN_NORD12          WMT_PIN(4, 12)
+#define WMT_PIN_NORD13          WMT_PIN(4, 13)
+#define WMT_PIN_NORD14          WMT_PIN(4, 14)
+#define WMT_PIN_NORD15          WMT_PIN(4, 15)
+#define WMT_PIN_NORA0           WMT_PIN(5, 0)
+#define WMT_PIN_NORA1           WMT_PIN(5, 1)
+#define WMT_PIN_NORA2           WMT_PIN(5, 2)
+#define WMT_PIN_NORA3           WMT_PIN(5, 3)
+#define WMT_PIN_NORA4           WMT_PIN(5, 4)
+#define WMT_PIN_NORA5           WMT_PIN(5, 5)
+#define WMT_PIN_NORA6           WMT_PIN(5, 6)
+#define WMT_PIN_NORA7           WMT_PIN(5, 7)
+#define WMT_PIN_NORA8           WMT_PIN(5, 8)
+#define WMT_PIN_NORA9           WMT_PIN(5, 9)
+#define WMT_PIN_NORA10          WMT_PIN(5, 10)
+#define WMT_PIN_NORA11          WMT_PIN(5, 11)
+#define WMT_PIN_NORA12          WMT_PIN(5, 12)
+#define WMT_PIN_NORA13          WMT_PIN(5, 13)
+#define WMT_PIN_NORA14          WMT_PIN(5, 14)
+#define WMT_PIN_NORA15          WMT_PIN(5, 15)
+#define WMT_PIN_NORA16          WMT_PIN(5, 16)
+#define WMT_PIN_NORA17          WMT_PIN(5, 17)
+#define WMT_PIN_NORA18          WMT_PIN(5, 18)
+#define WMT_PIN_NORA19          WMT_PIN(5, 19)
+#define WMT_PIN_NORA20          WMT_PIN(5, 20)
+#define WMT_PIN_NORA21          WMT_PIN(5, 21)
+#define WMT_PIN_NORA22          WMT_PIN(5, 22)
+#define WMT_PIN_NORA23          WMT_PIN(5, 23)
+#define WMT_PIN_NORA24          WMT_PIN(5, 24)
+#define WMT_PIN_AC97SDI         WMT_PIN(6, 0)
+#define WMT_PIN_AC97SYNC        WMT_PIN(6, 1)
+#define WMT_PIN_AC97SDO         WMT_PIN(6, 2)
+#define WMT_PIN_AC97BCLK        WMT_PIN(6, 3)
+#define WMT_PIN_AC97RST         WMT_PIN(6, 4)
+#define WMT_PIN_SFDO            WMT_PIN(7, 0)
+#define WMT_PIN_SFCS0           WMT_PIN(7, 1)
+#define WMT_PIN_SFCS1           WMT_PIN(7, 2)
+#define WMT_PIN_SFCLK           WMT_PIN(7, 3)
+#define WMT_PIN_SFDI            WMT_PIN(7, 4)
+#define WMT_PIN_SPI0CLK         WMT_PIN(8, 0)
+#define WMT_PIN_SPI0MISO        WMT_PIN(8, 1)
+#define WMT_PIN_SPI0MOSI        WMT_PIN(8, 2)
+#define WMT_PIN_SPI0SS          WMT_PIN(8, 3)
+#define WMT_PIN_SPI1CLK         WMT_PIN(8, 4)
+#define WMT_PIN_SPI1MISO        WMT_PIN(8, 5)
+#define WMT_PIN_SPI1MOSI        WMT_PIN(8, 6)
+#define WMT_PIN_SPI1SS          WMT_PIN(8, 7)
+#define WMT_PIN_SPI2CLK         WMT_PIN(8, 8)
+#define WMT_PIN_SPI2MISO        WMT_PIN(8, 9)
+#define WMT_PIN_SPI2MOSI        WMT_PIN(8, 10)
+#define WMT_PIN_SPI2SS          WMT_PIN(8, 11)
+#define WMT_PIN_UART0_RTS       WMT_PIN(9, 0)
+#define WMT_PIN_UART0_TXD       WMT_PIN(9, 1)
+#define WMT_PIN_UART0_CTS       WMT_PIN(9, 2)
+#define WMT_PIN_UART0_RXD       WMT_PIN(9, 3)
+#define WMT_PIN_UART1_RTS       WMT_PIN(9, 4)
+#define WMT_PIN_UART1_TXD       WMT_PIN(9, 5)
+#define WMT_PIN_UART1_CTS       WMT_PIN(9, 6)
+#define WMT_PIN_UART1_RXD       WMT_PIN(9, 7)
+#define WMT_PIN_UART2_RTS       WMT_PIN(9, 8)
+#define WMT_PIN_UART2_TXD       WMT_PIN(9, 9)
+#define WMT_PIN_UART2_CTS       WMT_PIN(9, 10)
+#define WMT_PIN_UART2_RXD       WMT_PIN(9, 11)
+#define WMT_PIN_UART3_RTS       WMT_PIN(9, 12)
+#define WMT_PIN_UART3_TXD       WMT_PIN(9, 13)
+#define WMT_PIN_UART3_CTS       WMT_PIN(9, 14)
+#define WMT_PIN_UART3_RXD       WMT_PIN(9, 15)
+#define WMT_PIN_I2C0SCL         WMT_PIN(10, 0)
+#define WMT_PIN_I2C0SDA         WMT_PIN(10, 1)
+#define WMT_PIN_I2C1SCL         WMT_PIN(10, 2)
+#define WMT_PIN_I2C1SDA         WMT_PIN(10, 3)
+#define WMT_PIN_I2C2SCL         WMT_PIN(10, 4)
+#define WMT_PIN_I2C2SDA         WMT_PIN(10, 5)
+
+static const struct pinctrl_pin_desc wm8505_pins[] = {
+        PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP2, "wakeup2"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP3, "wakeup3"),
+        PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"),
+        PINCTRL_PIN(WMT_PIN_SDDATA0, "sd_data0"),
+        PINCTRL_PIN(WMT_PIN_SDDATA1, "sd_data1"),
+        PINCTRL_PIN(WMT_PIN_SDDATA2, "sd_data2"),
+        PINCTRL_PIN(WMT_PIN_SDDATA3, "sd_data3"),
+        PINCTRL_PIN(WMT_PIN_MMCDATA0, "mmc_data0"),
+        PINCTRL_PIN(WMT_PIN_MMCDATA1, "mmc_data1"),
+        PINCTRL_PIN(WMT_PIN_MMCDATA2, "mmc_data2"),
+        PINCTRL_PIN(WMT_PIN_MMCDATA3, "mmc_data3"),
+        PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
+        PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
+        PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
+        PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
+        PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
+        PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
+        PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
+        PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
+        PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
+        PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
+        PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
+        PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
+        PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
+        PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
+        PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"),
+        PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"),
+        PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"),
+        PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"),
+        PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"),
+        PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"),
+        PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"),
+        PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"),
+        PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"),
+        PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"),
+        PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"),
+        PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"),
+        PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"),
+        PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"),
+        PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"),
+        PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"),
+        PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"),
+        PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"),
+        PINCTRL_PIN(WMT_PIN_VHSYNC, "v_hsync"),
+        PINCTRL_PIN(WMT_PIN_VVSYNC, "v_vsync"),
+        PINCTRL_PIN(WMT_PIN_VGAHSYNC, "vga_hsync"),
+        PINCTRL_PIN(WMT_PIN_VGAVSYNC, "vga_vsync"),
+        PINCTRL_PIN(WMT_PIN_VDHSYNC, "vd_hsync"),
+        PINCTRL_PIN(WMT_PIN_VDVSYNC, "vd_vsync"),
+        PINCTRL_PIN(WMT_PIN_NORD0, "nor_d0"),
+        PINCTRL_PIN(WMT_PIN_NORD1, "nor_d1"),
+        PINCTRL_PIN(WMT_PIN_NORD2, "nor_d2"),
+        PINCTRL_PIN(WMT_PIN_NORD3, "nor_d3"),
+        PINCTRL_PIN(WMT_PIN_NORD4, "nor_d4"),
+        PINCTRL_PIN(WMT_PIN_NORD5, "nor_d5"),
+        PINCTRL_PIN(WMT_PIN_NORD6, "nor_d6"),
+        PINCTRL_PIN(WMT_PIN_NORD7, "nor_d7"),
+        PINCTRL_PIN(WMT_PIN_NORD8, "nor_d8"),
+        PINCTRL_PIN(WMT_PIN_NORD9, "nor_d9"),
+        PINCTRL_PIN(WMT_PIN_NORD10, "nor_d10"),
+        PINCTRL_PIN(WMT_PIN_NORD11, "nor_d11"),
+        PINCTRL_PIN(WMT_PIN_NORD12, "nor_d12"),
+        PINCTRL_PIN(WMT_PIN_NORD13, "nor_d13"),
+        PINCTRL_PIN(WMT_PIN_NORD14, "nor_d14"),
+        PINCTRL_PIN(WMT_PIN_NORD15, "nor_d15"),
+        PINCTRL_PIN(WMT_PIN_NORA0, "nor_a0"),
+        PINCTRL_PIN(WMT_PIN_NORA1, "nor_a1"),
+        PINCTRL_PIN(WMT_PIN_NORA2, "nor_a2"),
+        PINCTRL_PIN(WMT_PIN_NORA3, "nor_a3"),
+        PINCTRL_PIN(WMT_PIN_NORA4, "nor_a4"),
+        PINCTRL_PIN(WMT_PIN_NORA5, "nor_a5"),
+        PINCTRL_PIN(WMT_PIN_NORA6, "nor_a6"),
+        PINCTRL_PIN(WMT_PIN_NORA7, "nor_a7"),
+        PINCTRL_PIN(WMT_PIN_NORA8, "nor_a8"),
+        PINCTRL_PIN(WMT_PIN_NORA9, "nor_a9"),
+        PINCTRL_PIN(WMT_PIN_NORA10, "nor_a10"),
+        PINCTRL_PIN(WMT_PIN_NORA11, "nor_a11"),
+        PINCTRL_PIN(WMT_PIN_NORA12, "nor_a12"),
+        PINCTRL_PIN(WMT_PIN_NORA13, "nor_a13"),
+        PINCTRL_PIN(WMT_PIN_NORA14, "nor_a14"),
+        PINCTRL_PIN(WMT_PIN_NORA15, "nor_a15"),
+        PINCTRL_PIN(WMT_PIN_NORA16, "nor_a16"),
+        PINCTRL_PIN(WMT_PIN_NORA17, "nor_a17"),
+        PINCTRL_PIN(WMT_PIN_NORA18, "nor_a18"),
+        PINCTRL_PIN(WMT_PIN_NORA19, "nor_a19"),
+        PINCTRL_PIN(WMT_PIN_NORA20, "nor_a20"),
+        PINCTRL_PIN(WMT_PIN_NORA21, "nor_a21"),
+        PINCTRL_PIN(WMT_PIN_NORA22, "nor_a22"),
+        PINCTRL_PIN(WMT_PIN_NORA23, "nor_a23"),
+        PINCTRL_PIN(WMT_PIN_NORA24, "nor_a24"),
+        PINCTRL_PIN(WMT_PIN_AC97SDI, "ac97_sdi"),
+        PINCTRL_PIN(WMT_PIN_AC97SYNC, "ac97_sync"),
+        PINCTRL_PIN(WMT_PIN_AC97SDO, "ac97_sdo"),
+        PINCTRL_PIN(WMT_PIN_AC97BCLK, "ac97_bclk"),
+        PINCTRL_PIN(WMT_PIN_AC97RST, "ac97_rst"),
+        PINCTRL_PIN(WMT_PIN_SFDO, "sf_do"),
+        PINCTRL_PIN(WMT_PIN_SFCS0, "sf_cs0"),
+        PINCTRL_PIN(WMT_PIN_SFCS1, "sf_cs1"),
+        PINCTRL_PIN(WMT_PIN_SFCLK, "sf_clk"),
+        PINCTRL_PIN(WMT_PIN_SFDI, "sf_di"),
+        PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"),
+        PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"),
+        PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"),
+        PINCTRL_PIN(WMT_PIN_SPI0SS, "spi0_ss"),
+        PINCTRL_PIN(WMT_PIN_SPI1CLK, "spi1_clk"),
+        PINCTRL_PIN(WMT_PIN_SPI1MISO, "spi1_miso"),
+        PINCTRL_PIN(WMT_PIN_SPI1MOSI, "spi1_mosi"),
+        PINCTRL_PIN(WMT_PIN_SPI1SS, "spi1_ss"),
+        PINCTRL_PIN(WMT_PIN_SPI2CLK, "spi2_clk"),
+        PINCTRL_PIN(WMT_PIN_SPI2MISO, "spi2_miso"),
+        PINCTRL_PIN(WMT_PIN_SPI2MOSI, "spi2_mosi"),
+        PINCTRL_PIN(WMT_PIN_SPI2SS, "spi2_ss"),
+        PINCTRL_PIN(WMT_PIN_UART0_RTS, "uart0_rts"),
+        PINCTRL_PIN(WMT_PIN_UART0_TXD, "uart0_txd"),
+        PINCTRL_PIN(WMT_PIN_UART0_CTS, "uart0_cts"),
+        PINCTRL_PIN(WMT_PIN_UART0_RXD, "uart0_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART1_RTS, "uart1_rts"),
+        PINCTRL_PIN(WMT_PIN_UART1_TXD, "uart1_txd"),
+        PINCTRL_PIN(WMT_PIN_UART1_CTS, "uart1_cts"),
+        PINCTRL_PIN(WMT_PIN_UART1_RXD, "uart1_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART2_RTS, "uart2_rts"),
+        PINCTRL_PIN(WMT_PIN_UART2_TXD, "uart2_txd"),
+        PINCTRL_PIN(WMT_PIN_UART2_CTS, "uart2_cts"),
+        PINCTRL_PIN(WMT_PIN_UART2_RXD, "uart2_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART3_RTS, "uart3_rts"),
+        PINCTRL_PIN(WMT_PIN_UART3_TXD, "uart3_txd"),
+        PINCTRL_PIN(WMT_PIN_UART3_CTS, "uart3_cts"),
+        PINCTRL_PIN(WMT_PIN_UART3_RXD, "uart3_rxd"),
+        PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"),
+        PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"),
+        PINCTRL_PIN(WMT_PIN_I2C2SCL, "i2c2_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C2SDA, "i2c2_sda"),
+};
+
+/* Order of these names must match the above list */
+static const char * const wm8505_groups[] = {
+        "extgpio0",
+        "extgpio1",
+        "extgpio2",
+        "extgpio3",
+        "extgpio4",
+        "extgpio5",
+        "extgpio6",
+        "extgpio7",
+        "wakeup0",
+        "wakeup1",
+        "wakeup2",
+        "wakeup3",
+        "susgpio0",
+        "sd_data0",
+        "sd_data1",
+        "sd_data2",
+        "sd_data3",
+        "mmc_data0",
+        "mmc_data1",
+        "mmc_data2",
+        "mmc_data3",
+        "vdin0",
+        "vdin1",
+        "vdin2",
+        "vdin3",
+        "vdin4",
+        "vdin5",
+        "vdin6",
+        "vdin7",
+        "vdout0",
+        "vdout1",
+        "vdout2",
+        "vdout3",
+        "vdout4",
+        "vdout5",
+        "vdout6",
+        "vdout7",
+        "vdout8",
+        "vdout9",
+        "vdout10",
+        "vdout11",
+        "vdout12",
+        "vdout13",
+        "vdout14",
+        "vdout15",
+        "vdout16",
+        "vdout17",
+        "vdout18",
+        "vdout19",
+        "vdout20",
+        "vdout21",
+        "vdout22",
+        "vdout23",
+        "v_hsync",
+        "v_vsync",
+        "vga_hsync",
+        "vga_vsync",
+        "vd_hsync",
+        "vd_vsync",
+        "nor_d0",
+        "nor_d1",
+        "nor_d2",
+        "nor_d3",
+        "nor_d4",
+        "nor_d5",
+        "nor_d6",
+        "nor_d7",
+        "nor_d8",
+        "nor_d9",
+        "nor_d10",
+        "nor_d11",
+        "nor_d12",
+        "nor_d13",
+        "nor_d14",
+        "nor_d15",
+        "nor_a0",
+        "nor_a1",
+        "nor_a2",
+        "nor_a3",
+        "nor_a4",
+        "nor_a5",
+        "nor_a6",
+        "nor_a7",
+        "nor_a8",
+        "nor_a9",
+        "nor_a10",
+        "nor_a11",
+        "nor_a12",
+        "nor_a13",
+        "nor_a14",
+        "nor_a15",
+        "nor_a16",
+        "nor_a17",
+        "nor_a18",
+        "nor_a19",
+        "nor_a20",
+        "nor_a21",
+        "nor_a22",
+        "nor_a23",
+        "nor_a24",
+        "ac97_sdi",
+        "ac97_sync",
+        "ac97_sdo",
+        "ac97_bclk",
+        "ac97_rst",
+        "sf_do",
+        "sf_cs0",
+        "sf_cs1",
+        "sf_clk",
+        "sf_di",
+        "spi0_clk",
+        "spi0_miso",
+        "spi0_mosi",
+        "spi0_ss",
+        "spi1_clk",
+        "spi1_miso",
+        "spi1_mosi",
+        "spi1_ss",
+        "spi2_clk",
+        "spi2_miso",
+        "spi2_mosi",
+        "spi2_ss",
+        "uart0_rts",
+        "uart0_txd",
+        "uart0_cts",
+        "uart0_rxd",
+        "uart1_rts",
+        "uart1_txd",
+        "uart1_cts",
+        "uart1_rxd",
+        "uart2_rts",
+        "uart2_txd",
+        "uart2_cts",
+        "uart2_rxd",
+        "uart3_rts",
+        "uart3_txd",
+        "uart3_cts",
+        "uart3_rxd",
+        "i2c0_scl",
+        "i2c0_sda",
+        "i2c1_scl",
+        "i2c1_sda",
+        "i2c2_scl",
+        "i2c2_sda",
+};
+
+static int wm8505_pinctrl_probe(struct platform_device *pdev)
+{
+        struct wmt_pinctrl_data *data;
+
+        data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+        if (!data) {
+                dev_err(&pdev->dev, "failed to allocate data\n");
+                return -ENOMEM;
+        }
+
+        data->banks = wm8505_banks;
+        data->nbanks = ARRAY_SIZE(wm8505_banks);
+        data->pins = wm8505_pins;
+        data->npins = ARRAY_SIZE(wm8505_pins);
+        data->groups = wm8505_groups;
+        data->ngroups = ARRAY_SIZE(wm8505_groups);
+
+        return wmt_pinctrl_probe(pdev, data);
+}
+
+static int wm8505_pinctrl_remove(struct platform_device *pdev)
+{
+        return wmt_pinctrl_remove(pdev);
+}
+
+static struct of_device_id wmt_pinctrl_of_match[] = {
+        { .compatible = "wm,wm8505-pinctrl" },
+        { /* sentinel */ },
+};
+
+static struct platform_driver wmt_pinctrl_driver = {
+        .probe  = wm8505_pinctrl_probe,
+        .remove = wm8505_pinctrl_remove,
+        .driver = {
+                .name   = "pinctrl-wm8505",
+                .owner  = THIS_MODULE,
+                .of_match_table = wmt_pinctrl_of_match,
+        },
+};
+
+module_platform_driver(wmt_pinctrl_driver);
+
+MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
+MODULE_DESCRIPTION("Wondermedia WM8505 Pincontrol driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8650.c b/drivers/pinctrl/vt8500/pinctrl-wm8650.c
new file mode 100644
index 000000000000..7de57f063153
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8650.c
@@ -0,0 +1,370 @@
+/*
+ * Pinctrl data for Wondermedia WM8650 SoC
+ *
+ * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "pinctrl-wmt.h"
+
+/*
+ * Describe the register offsets within the GPIO memory space
+ * The dedicated external GPIO's should always be listed in bank 0
+ * so they are exported in the 0..31 range which is what users
+ * expect.
+ *
+ * Do not reorder these banks as it will change the pin numbering
+ */
+static const struct wmt_pinctrl_bank_registers wm8650_banks[] = {
+        WMT_PINCTRL_BANK(0x40, 0x80, 0xC0, 0x00, 0x480, 0x4C0),         /* 0 */
+        WMT_PINCTRL_BANK(0x44, 0x84, 0xC4, 0x04, 0x484, 0x4C4),         /* 1 */
+        WMT_PINCTRL_BANK(0x48, 0x88, 0xC8, 0x08, 0x488, 0x4C8),         /* 2 */
+        WMT_PINCTRL_BANK(0x4C, 0x8C, 0xCC, 0x0C, 0x48C, 0x4CC),         /* 3 */
+        WMT_PINCTRL_BANK(0x50, 0x90, 0xD0, 0x10, 0x490, 0x4D0),         /* 4 */
+        WMT_PINCTRL_BANK(0x54, 0x94, 0xD4, 0x14, 0x494, 0x4D4),         /* 5 */
+        WMT_PINCTRL_BANK(0x58, 0x98, 0xD8, 0x18, 0x498, 0x4D8),         /* 6 */
+        WMT_PINCTRL_BANK(0x5C, 0x9C, 0xDC, 0x1C, 0x49C, 0x4DC),         /* 7 */
+};
+
+/* Please keep sorted by bank/bit */
+#define WMT_PIN_EXTGPIO0        WMT_PIN(0, 0)
+#define WMT_PIN_EXTGPIO1        WMT_PIN(0, 1)
+#define WMT_PIN_EXTGPIO2        WMT_PIN(0, 2)
+#define WMT_PIN_EXTGPIO3        WMT_PIN(0, 3)
+#define WMT_PIN_EXTGPIO4        WMT_PIN(0, 4)
+#define WMT_PIN_EXTGPIO5        WMT_PIN(0, 5)
+#define WMT_PIN_EXTGPIO6        WMT_PIN(0, 6)
+#define WMT_PIN_EXTGPIO7        WMT_PIN(0, 7)
+#define WMT_PIN_WAKEUP0         WMT_PIN(0, 16)
+#define WMT_PIN_WAKEUP1         WMT_PIN(0, 17)
+#define WMT_PIN_SUSGPIO0        WMT_PIN(0, 21)
+#define WMT_PIN_SD0CD           WMT_PIN(0, 28)
+#define WMT_PIN_SD1CD           WMT_PIN(0, 29)
+#define WMT_PIN_VDOUT0          WMT_PIN(1, 0)
+#define WMT_PIN_VDOUT1          WMT_PIN(1, 1)
+#define WMT_PIN_VDOUT2          WMT_PIN(1, 2)
+#define WMT_PIN_VDOUT3          WMT_PIN(1, 3)
+#define WMT_PIN_VDOUT4          WMT_PIN(1, 4)
+#define WMT_PIN_VDOUT5          WMT_PIN(1, 5)
+#define WMT_PIN_VDOUT6          WMT_PIN(1, 6)
+#define WMT_PIN_VDOUT7          WMT_PIN(1, 7)
+#define WMT_PIN_VDOUT8          WMT_PIN(1, 8)
+#define WMT_PIN_VDOUT9          WMT_PIN(1, 9)
+#define WMT_PIN_VDOUT10         WMT_PIN(1, 10)
+#define WMT_PIN_VDOUT11         WMT_PIN(1, 11)
+#define WMT_PIN_VDOUT12         WMT_PIN(1, 12)
+#define WMT_PIN_VDOUT13         WMT_PIN(1, 13)
+#define WMT_PIN_VDOUT14         WMT_PIN(1, 14)
+#define WMT_PIN_VDOUT15         WMT_PIN(1, 15)
+#define WMT_PIN_VDOUT16         WMT_PIN(1, 16)
+#define WMT_PIN_VDOUT17         WMT_PIN(1, 17)
+#define WMT_PIN_VDOUT18         WMT_PIN(1, 18)
+#define WMT_PIN_VDOUT19         WMT_PIN(1, 19)
+#define WMT_PIN_VDOUT20         WMT_PIN(1, 20)
+#define WMT_PIN_VDOUT21         WMT_PIN(1, 21)
+#define WMT_PIN_VDOUT22         WMT_PIN(1, 22)
+#define WMT_PIN_VDOUT23         WMT_PIN(1, 23)
+#define WMT_PIN_VDIN0           WMT_PIN(2, 0)
+#define WMT_PIN_VDIN1           WMT_PIN(2, 1)
+#define WMT_PIN_VDIN2           WMT_PIN(2, 2)
+#define WMT_PIN_VDIN3           WMT_PIN(2, 3)
+#define WMT_PIN_VDIN4           WMT_PIN(2, 4)
+#define WMT_PIN_VDIN5           WMT_PIN(2, 5)
+#define WMT_PIN_VDIN6           WMT_PIN(2, 6)
+#define WMT_PIN_VDIN7           WMT_PIN(2, 7)
+#define WMT_PIN_I2C1SCL         WMT_PIN(2, 12)
+#define WMT_PIN_I2C1SDA         WMT_PIN(2, 13)
+#define WMT_PIN_SPI0MOSI        WMT_PIN(2, 24)
+#define WMT_PIN_SPI0MISO        WMT_PIN(2, 25)
+#define WMT_PIN_SPI0SS0         WMT_PIN(2, 26)
+#define WMT_PIN_SPI0CLK         WMT_PIN(2, 27)
+#define WMT_PIN_SD0DATA0        WMT_PIN(3, 8)
+#define WMT_PIN_SD0DATA1        WMT_PIN(3, 9)
+#define WMT_PIN_SD0DATA2        WMT_PIN(3, 10)
+#define WMT_PIN_SD0DATA3        WMT_PIN(3, 11)
+#define WMT_PIN_SD0CLK          WMT_PIN(3, 12)
+#define WMT_PIN_SD0WP           WMT_PIN(3, 13)
+#define WMT_PIN_SD0CMD          WMT_PIN(3, 14)
+#define WMT_PIN_SD1DATA0        WMT_PIN(3, 24)
+#define WMT_PIN_SD1DATA1        WMT_PIN(3, 25)
+#define WMT_PIN_SD1DATA2        WMT_PIN(3, 26)
+#define WMT_PIN_SD1DATA3        WMT_PIN(3, 27)
+#define WMT_PIN_SD1DATA4        WMT_PIN(3, 28)
+#define WMT_PIN_SD1DATA5        WMT_PIN(3, 29)
+#define WMT_PIN_SD1DATA6        WMT_PIN(3, 30)
+#define WMT_PIN_SD1DATA7        WMT_PIN(3, 31)
+#define WMT_PIN_I2C0SCL         WMT_PIN(5, 8)
+#define WMT_PIN_I2C0SDA         WMT_PIN(5, 9)
+#define WMT_PIN_UART0RTS        WMT_PIN(5, 16)
+#define WMT_PIN_UART0TXD        WMT_PIN(5, 17)
+#define WMT_PIN_UART0CTS        WMT_PIN(5, 18)
+#define WMT_PIN_UART0RXD        WMT_PIN(5, 19)
+#define WMT_PIN_UART1RTS        WMT_PIN(5, 20)
+#define WMT_PIN_UART1TXD        WMT_PIN(5, 21)
+#define WMT_PIN_UART1CTS        WMT_PIN(5, 22)
+#define WMT_PIN_UART1RXD        WMT_PIN(5, 23)
+#define WMT_PIN_UART2RTS        WMT_PIN(5, 24)
+#define WMT_PIN_UART2TXD        WMT_PIN(5, 25)
+#define WMT_PIN_UART2CTS        WMT_PIN(5, 26)
+#define WMT_PIN_UART2RXD        WMT_PIN(5, 27)
+#define WMT_PIN_UART3RTS        WMT_PIN(5, 28)
+#define WMT_PIN_UART3TXD        WMT_PIN(5, 29)
+#define WMT_PIN_UART3CTS        WMT_PIN(5, 30)
+#define WMT_PIN_UART3RXD        WMT_PIN(5, 31)
+#define WMT_PIN_KPADROW0        WMT_PIN(6, 16)
+#define WMT_PIN_KPADROW1        WMT_PIN(6, 17)
+#define WMT_PIN_KPADCOL0        WMT_PIN(6, 18)
+#define WMT_PIN_KPADCOL1        WMT_PIN(6, 19)
+#define WMT_PIN_SD1CLK          WMT_PIN(7, 0)
+#define WMT_PIN_SD1CMD          WMT_PIN(7, 1)
+#define WMT_PIN_SD1WP           WMT_PIN(7, 13)
+
+static const struct pinctrl_pin_desc wm8650_pins[] = {
+        PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
+        PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"),
+        PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"),
+        PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"),
+        PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
+        PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
+        PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
+        PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
+        PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
+        PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
+        PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"),
+        PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"),
+        PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"),
+        PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"),
+        PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"),
+        PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"),
+        PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"),
+        PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"),
+        PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"),
+        PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"),
+        PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"),
+        PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"),
+        PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"),
+        PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"),
+        PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"),
+        PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"),
+        PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"),
+        PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"),
+        PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
+        PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
+        PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
+        PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
+        PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
+        PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
+        PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
+        PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
+        PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"),
+        PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"),
+        PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"),
+        PINCTRL_PIN(WMT_PIN_SPI0SS0, "spi0_ss0"),
+        PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA0, "sd0_data0"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA1, "sd0_data1"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA2, "sd0_data2"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA3, "sd0_data3"),
+        PINCTRL_PIN(WMT_PIN_SD0CLK, "sd0_clk"),
+        PINCTRL_PIN(WMT_PIN_SD0WP, "sd0_wp"),
+        PINCTRL_PIN(WMT_PIN_SD0CMD, "sd0_cmd"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA0, "sd1_data0"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA1, "sd1_data1"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA2, "sd1_data2"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA3, "sd1_data3"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA4, "sd1_data4"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA5, "sd1_data5"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA6, "sd1_data6"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA7, "sd1_data7"),
+        PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"),
+        PINCTRL_PIN(WMT_PIN_UART0RTS, "uart0_rts"),
+        PINCTRL_PIN(WMT_PIN_UART0TXD, "uart0_txd"),
+        PINCTRL_PIN(WMT_PIN_UART0CTS, "uart0_cts"),
+        PINCTRL_PIN(WMT_PIN_UART0RXD, "uart0_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART1RTS, "uart1_rts"),
+        PINCTRL_PIN(WMT_PIN_UART1TXD, "uart1_txd"),
+        PINCTRL_PIN(WMT_PIN_UART1CTS, "uart1_cts"),
+        PINCTRL_PIN(WMT_PIN_UART1RXD, "uart1_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART2RTS, "uart2_rts"),
+        PINCTRL_PIN(WMT_PIN_UART2TXD, "uart2_txd"),
+        PINCTRL_PIN(WMT_PIN_UART2CTS, "uart2_cts"),
+        PINCTRL_PIN(WMT_PIN_UART2RXD, "uart2_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART3RTS, "uart3_rts"),
+        PINCTRL_PIN(WMT_PIN_UART3TXD, "uart3_txd"),
+        PINCTRL_PIN(WMT_PIN_UART3CTS, "uart3_cts"),
+        PINCTRL_PIN(WMT_PIN_UART3RXD, "uart3_rxd"),
+        PINCTRL_PIN(WMT_PIN_KPADROW0, "kpadrow0"),
+        PINCTRL_PIN(WMT_PIN_KPADROW1, "kpadrow1"),
+        PINCTRL_PIN(WMT_PIN_KPADCOL0, "kpadcol0"),
+        PINCTRL_PIN(WMT_PIN_KPADCOL1, "kpadcol1"),
+        PINCTRL_PIN(WMT_PIN_SD1CLK, "sd1_clk"),
+        PINCTRL_PIN(WMT_PIN_SD1CMD, "sd1_cmd"),
+        PINCTRL_PIN(WMT_PIN_SD1WP, "sd1_wp"),
+};
+
+/* Order of these names must match the above list */
+static const char * const wm8650_groups[] = {
+        "extgpio0",
+        "extgpio1",
+        "extgpio2",
+        "extgpio3",
+        "extgpio4",
+        "extgpio5",
+        "extgpio6",
+        "extgpio7",
+        "wakeup0",
+        "wakeup1",
+        "susgpio0",
+        "sd0_cd",
+        "sd1_cd",
+        "vdout0",
+        "vdout1",
+        "vdout2",
+        "vdout3",
+        "vdout4",
+        "vdout5",
+        "vdout6",
+        "vdout7",
+        "vdout8",
+        "vdout9",
+        "vdout10",
+        "vdout11",
+        "vdout12",
+        "vdout13",
+        "vdout14",
+        "vdout15",
+        "vdout16",
+        "vdout17",
+        "vdout18",
+        "vdout19",
+        "vdout20",
+        "vdout21",
+        "vdout22",
+        "vdout23",
+        "vdin0",
+        "vdin1",
+        "vdin2",
+        "vdin3",
+        "vdin4",
+        "vdin5",
+        "vdin6",
+        "vdin7",
+        "i2c1_scl",
+        "i2c1_sda",
+        "spi0_mosi",
+        "spi0_miso",
+        "spi0_ss0",
+        "spi0_clk",
+        "sd0_data0",
+        "sd0_data1",
+        "sd0_data2",
+        "sd0_data3",
+        "sd0_clk",
+        "sd0_wp",
+        "sd0_cmd",
+        "sd1_data0",
+        "sd1_data1",
+        "sd1_data2",
+        "sd1_data3",
+        "sd1_data4",
+        "sd1_data5",
+        "sd1_data6",
+        "sd1_data7",
+        "i2c0_scl",
+        "i2c0_sda",
+        "uart0_rts",
+        "uart0_txd",
+        "uart0_cts",
+        "uart0_rxd",
+        "uart1_rts",
+        "uart1_txd",
+        "uart1_cts",
+        "uart1_rxd",
+        "uart2_rts",
+        "uart2_txd",
+        "uart2_cts",
+        "uart2_rxd",
+        "uart3_rts",
+        "uart3_txd",
+        "uart3_cts",
+        "uart3_rxd",
+        "kpadrow0",
+        "kpadrow1",
+        "kpadcol0",
+        "kpadcol1",
+        "sd1_clk",
+        "sd1_cmd",
+        "sd1_wp",
+};
+
+static int wm8650_pinctrl_probe(struct platform_device *pdev)
+{
+        struct wmt_pinctrl_data *data;
+
+        data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+        if (!data) {
+                dev_err(&pdev->dev, "failed to allocate data\n");
+                return -ENOMEM;
+        }
+
+        data->banks = wm8650_banks;
+        data->nbanks = ARRAY_SIZE(wm8650_banks);
+        data->pins = wm8650_pins;
+        data->npins = ARRAY_SIZE(wm8650_pins);
+        data->groups = wm8650_groups;
+        data->ngroups = ARRAY_SIZE(wm8650_groups);
+
+        return wmt_pinctrl_probe(pdev, data);
+}
+
+static int wm8650_pinctrl_remove(struct platform_device *pdev)
+{
+        return wmt_pinctrl_remove(pdev);
+}
+
+static struct of_device_id wmt_pinctrl_of_match[] = {
+        { .compatible = "wm,wm8650-pinctrl" },
+        { /* sentinel */ },
+};
+
+static struct platform_driver wmt_pinctrl_driver = {
+        .probe  = wm8650_pinctrl_probe,
+        .remove = wm8650_pinctrl_remove,
+        .driver = {
+                .name   = "pinctrl-wm8650",
+                .owner  = THIS_MODULE,
+                .of_match_table = wmt_pinctrl_of_match,
+        },
+};
+
+module_platform_driver(wmt_pinctrl_driver);
+
+MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
+MODULE_DESCRIPTION("Wondermedia WM8650 Pincontrol driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8750.c b/drivers/pinctrl/vt8500/pinctrl-wm8750.c
new file mode 100644
index 000000000000..b964cc550568
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8750.c
@@ -0,0 +1,409 @@
+/*
+ * Pinctrl data for Wondermedia WM8750 SoC
+ *
+ * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "pinctrl-wmt.h"
+
+/*
+ * Describe the register offsets within the GPIO memory space
+ * The dedicated external GPIO's should always be listed in bank 0
+ * so they are exported in the 0..31 range which is what users
+ * expect.
+ *
+ * Do not reorder these banks as it will change the pin numbering
+ */
+static const struct wmt_pinctrl_bank_registers wm8750_banks[] = {
+        WMT_PINCTRL_BANK(0x40, 0x80, 0xC0, 0x00, 0x480, 0x4C0), /* 0 */
+        WMT_PINCTRL_BANK(0x44, 0x84, 0xC4, 0x04, 0x484, 0x4C4), /* 1 */
+        WMT_PINCTRL_BANK(0x48, 0x88, 0xC8, 0x08, 0x488, 0x4C8), /* 2 */
+        WMT_PINCTRL_BANK(0x4C, 0x8C, 0xCC, 0x0C, 0x48C, 0x4CC), /* 3 */
+        WMT_PINCTRL_BANK(0x50, 0x90, 0xD0, 0x10, 0x490, 0x4D0), /* 4 */
+        WMT_PINCTRL_BANK(0x54, 0x94, 0xD4, 0x14, 0x494, 0x4D4), /* 5 */
+        WMT_PINCTRL_BANK(0x58, 0x98, 0xD8, 0x18, 0x498, 0x4D8), /* 6 */
+        WMT_PINCTRL_BANK(0x5C, 0x9C, 0xDC, 0x1C, 0x49C, 0x4DC), /* 7 */
+        WMT_PINCTRL_BANK(0x60, 0xA0, 0xE0, 0x20, 0x4A0, 0x4E0), /* 8 */
+        WMT_PINCTRL_BANK(0x70, 0xB0, 0xF0, 0x30, 0x4B0, 0x4F0), /* 9 */
+        WMT_PINCTRL_BANK(0x7C, 0xBC, 0xDC, 0x3C, 0x4BC, 0x4FC), /* 10 */
+};
+
+/* Please keep sorted by bank/bit */
+#define WMT_PIN_EXTGPIO0        WMT_PIN(0, 0)
+#define WMT_PIN_EXTGPIO1        WMT_PIN(0, 1)
+#define WMT_PIN_EXTGPIO2        WMT_PIN(0, 2)
+#define WMT_PIN_EXTGPIO3        WMT_PIN(0, 3)
+#define WMT_PIN_EXTGPIO4        WMT_PIN(0, 4)
+#define WMT_PIN_EXTGPIO5        WMT_PIN(0, 5)
+#define WMT_PIN_EXTGPIO6        WMT_PIN(0, 6)
+#define WMT_PIN_EXTGPIO7        WMT_PIN(0, 7)
+#define WMT_PIN_WAKEUP0         WMT_PIN(0, 16)
+#define WMT_PIN_WAKEUP1         WMT_PIN(0, 16)
+#define WMT_PIN_SD0CD           WMT_PIN(0, 28)
+#define WMT_PIN_VDOUT0          WMT_PIN(1, 0)
+#define WMT_PIN_VDOUT1          WMT_PIN(1, 1)
+#define WMT_PIN_VDOUT2          WMT_PIN(1, 2)
+#define WMT_PIN_VDOUT3          WMT_PIN(1, 3)
+#define WMT_PIN_VDOUT4          WMT_PIN(1, 4)
+#define WMT_PIN_VDOUT5          WMT_PIN(1, 5)
+#define WMT_PIN_VDOUT6          WMT_PIN(1, 6)
+#define WMT_PIN_VDOUT7          WMT_PIN(1, 7)
+#define WMT_PIN_VDOUT8          WMT_PIN(1, 8)
+#define WMT_PIN_VDOUT9          WMT_PIN(1, 9)
+#define WMT_PIN_VDOUT10         WMT_PIN(1, 10)
+#define WMT_PIN_VDOUT11         WMT_PIN(1, 11)
+#define WMT_PIN_VDOUT12         WMT_PIN(1, 12)
+#define WMT_PIN_VDOUT13         WMT_PIN(1, 13)
+#define WMT_PIN_VDOUT14         WMT_PIN(1, 14)
+#define WMT_PIN_VDOUT15         WMT_PIN(1, 15)
+#define WMT_PIN_VDOUT16         WMT_PIN(1, 16)
+#define WMT_PIN_VDOUT17         WMT_PIN(1, 17)
+#define WMT_PIN_VDOUT18         WMT_PIN(1, 18)
+#define WMT_PIN_VDOUT19         WMT_PIN(1, 19)
+#define WMT_PIN_VDOUT20         WMT_PIN(1, 20)
+#define WMT_PIN_VDOUT21         WMT_PIN(1, 21)
+#define WMT_PIN_VDOUT22         WMT_PIN(1, 22)
+#define WMT_PIN_VDOUT23         WMT_PIN(1, 23)
+#define WMT_PIN_VDIN0           WMT_PIN(2, 0)
+#define WMT_PIN_VDIN1           WMT_PIN(2, 1)
+#define WMT_PIN_VDIN2           WMT_PIN(2, 2)
+#define WMT_PIN_VDIN3           WMT_PIN(2, 3)
+#define WMT_PIN_VDIN4           WMT_PIN(2, 4)
+#define WMT_PIN_VDIN5           WMT_PIN(2, 5)
+#define WMT_PIN_VDIN6           WMT_PIN(2, 6)
+#define WMT_PIN_VDIN7           WMT_PIN(2, 7)
+#define WMT_PIN_SPI0_MOSI       WMT_PIN(2, 24)
+#define WMT_PIN_SPI0_MISO       WMT_PIN(2, 25)
+#define WMT_PIN_SPI0_SS         WMT_PIN(2, 26)
+#define WMT_PIN_SPI0_CLK        WMT_PIN(2, 27)
+#define WMT_PIN_SPI0_SSB        WMT_PIN(2, 28)
+#define WMT_PIN_SD0CLK          WMT_PIN(3, 17)
+#define WMT_PIN_SD0CMD          WMT_PIN(3, 18)
+#define WMT_PIN_SD0WP           WMT_PIN(3, 19)
+#define WMT_PIN_SD0DATA0        WMT_PIN(3, 20)
+#define WMT_PIN_SD0DATA1        WMT_PIN(3, 21)
+#define WMT_PIN_SD0DATA2        WMT_PIN(3, 22)
+#define WMT_PIN_SD0DATA3        WMT_PIN(3, 23)
+#define WMT_PIN_SD1DATA0        WMT_PIN(3, 24)
+#define WMT_PIN_SD1DATA1        WMT_PIN(3, 25)
+#define WMT_PIN_SD1DATA2        WMT_PIN(3, 26)
+#define WMT_PIN_SD1DATA3        WMT_PIN(3, 27)
+#define WMT_PIN_SD1DATA4        WMT_PIN(3, 28)
+#define WMT_PIN_SD1DATA5        WMT_PIN(3, 29)
+#define WMT_PIN_SD1DATA6        WMT_PIN(3, 30)
+#define WMT_PIN_SD1DATA7        WMT_PIN(3, 31)
+#define WMT_PIN_I2C0_SCL        WMT_PIN(5, 8)
+#define WMT_PIN_I2C0_SDA        WMT_PIN(5, 9)
+#define WMT_PIN_I2C1_SCL        WMT_PIN(5, 10)
+#define WMT_PIN_I2C1_SDA        WMT_PIN(5, 11)
+#define WMT_PIN_I2C2_SCL        WMT_PIN(5, 12)
+#define WMT_PIN_I2C2_SDA        WMT_PIN(5, 13)
+#define WMT_PIN_UART0_RTS       WMT_PIN(5, 16)
+#define WMT_PIN_UART0_TXD       WMT_PIN(5, 17)
+#define WMT_PIN_UART0_CTS       WMT_PIN(5, 18)
+#define WMT_PIN_UART0_RXD       WMT_PIN(5, 19)
+#define WMT_PIN_UART1_RTS       WMT_PIN(5, 20)
+#define WMT_PIN_UART1_TXD       WMT_PIN(5, 21)
+#define WMT_PIN_UART1_CTS       WMT_PIN(5, 22)
+#define WMT_PIN_UART1_RXD       WMT_PIN(5, 23)
+#define WMT_PIN_UART2_RTS       WMT_PIN(5, 24)
+#define WMT_PIN_UART2_TXD       WMT_PIN(5, 25)
+#define WMT_PIN_UART2_CTS       WMT_PIN(5, 26)
+#define WMT_PIN_UART2_RXD       WMT_PIN(5, 27)
+#define WMT_PIN_UART3_RTS       WMT_PIN(5, 28)
+#define WMT_PIN_UART3_TXD       WMT_PIN(5, 29)
+#define WMT_PIN_UART3_CTS       WMT_PIN(5, 30)
+#define WMT_PIN_UART3_RXD       WMT_PIN(5, 31)
+#define WMT_PIN_SD2CD           WMT_PIN(6, 0)
+#define WMT_PIN_SD2DATA3        WMT_PIN(6, 1)
+#define WMT_PIN_SD2DATA0        WMT_PIN(6, 2)
+#define WMT_PIN_SD2WP           WMT_PIN(6, 3)
+#define WMT_PIN_SD2DATA1        WMT_PIN(6, 4)
+#define WMT_PIN_SD2DATA2        WMT_PIN(6, 5)
+#define WMT_PIN_SD2CMD          WMT_PIN(6, 6)
+#define WMT_PIN_SD2CLK          WMT_PIN(6, 7)
+#define WMT_PIN_SD2PWR          WMT_PIN(6, 9)
+#define WMT_PIN_SD1CLK          WMT_PIN(7, 0)
+#define WMT_PIN_SD1CMD          WMT_PIN(7, 1)
+#define WMT_PIN_SD1PWR          WMT_PIN(7, 10)
+#define WMT_PIN_SD1WP           WMT_PIN(7, 11)
+#define WMT_PIN_SD1CD           WMT_PIN(7, 12)
+#define WMT_PIN_SPI0SS3         WMT_PIN(7, 24)
+#define WMT_PIN_SPI0SS2         WMT_PIN(7, 25)
+#define WMT_PIN_PWMOUT1         WMT_PIN(7, 26)
+#define WMT_PIN_PWMOUT0         WMT_PIN(7, 27)
+
+static const struct pinctrl_pin_desc wm8750_pins[] = {
+        PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
+        PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"),
+        PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
+        PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
+        PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
+        PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
+        PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
+        PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
+        PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"),
+        PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"),
+        PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"),
+        PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"),
+        PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"),
+        PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"),
+        PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"),
+        PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"),
+        PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"),
+        PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"),
+        PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"),
+        PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"),
+        PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"),
+        PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"),
+        PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"),
+        PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"),
+        PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"),
+        PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"),
+        PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
+        PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
+        PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
+        PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
+        PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
+        PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
+        PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
+        PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
+        PINCTRL_PIN(WMT_PIN_SPI0_MOSI, "spi0_mosi"),
+        PINCTRL_PIN(WMT_PIN_SPI0_MISO, "spi0_miso"),
+        PINCTRL_PIN(WMT_PIN_SPI0_SS, "spi0_ss"),
+        PINCTRL_PIN(WMT_PIN_SPI0_CLK, "spi0_clk"),
+        PINCTRL_PIN(WMT_PIN_SPI0_SSB, "spi0_ssb"),
+        PINCTRL_PIN(WMT_PIN_SD0CLK, "sd0_clk"),
+        PINCTRL_PIN(WMT_PIN_SD0CMD, "sd0_cmd"),
+        PINCTRL_PIN(WMT_PIN_SD0WP, "sd0_wp"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA0, "sd0_data0"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA1, "sd0_data1"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA2, "sd0_data2"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA3, "sd0_data3"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA0, "sd1_data0"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA1, "sd1_data1"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA2, "sd1_data2"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA3, "sd1_data3"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA4, "sd1_data4"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA5, "sd1_data5"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA6, "sd1_data6"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA7, "sd1_data7"),
+        PINCTRL_PIN(WMT_PIN_I2C0_SCL, "i2c0_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C0_SDA, "i2c0_sda"),
+        PINCTRL_PIN(WMT_PIN_I2C1_SCL, "i2c1_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C1_SDA, "i2c1_sda"),
+        PINCTRL_PIN(WMT_PIN_I2C2_SCL, "i2c2_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C2_SDA, "i2c2_sda"),
+        PINCTRL_PIN(WMT_PIN_UART0_RTS, "uart0_rts"),
+        PINCTRL_PIN(WMT_PIN_UART0_TXD, "uart0_txd"),
+        PINCTRL_PIN(WMT_PIN_UART0_CTS, "uart0_cts"),
+        PINCTRL_PIN(WMT_PIN_UART0_RXD, "uart0_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART1_RTS, "uart1_rts"),
+        PINCTRL_PIN(WMT_PIN_UART1_TXD, "uart1_txd"),
+        PINCTRL_PIN(WMT_PIN_UART1_CTS, "uart1_cts"),
+        PINCTRL_PIN(WMT_PIN_UART1_RXD, "uart1_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART2_RTS, "uart2_rts"),
+        PINCTRL_PIN(WMT_PIN_UART2_TXD, "uart2_txd"),
+        PINCTRL_PIN(WMT_PIN_UART2_CTS, "uart2_cts"),
+        PINCTRL_PIN(WMT_PIN_UART2_RXD, "uart2_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART3_RTS, "uart3_rts"),
+        PINCTRL_PIN(WMT_PIN_UART3_TXD, "uart3_txd"),
+        PINCTRL_PIN(WMT_PIN_UART3_CTS, "uart3_cts"),
+        PINCTRL_PIN(WMT_PIN_UART3_RXD, "uart3_rxd"),
+        PINCTRL_PIN(WMT_PIN_SD2CD, "sd2_cd"),
+        PINCTRL_PIN(WMT_PIN_SD2DATA3, "sd2_data3"),
+        PINCTRL_PIN(WMT_PIN_SD2DATA0, "sd2_data0"),
+        PINCTRL_PIN(WMT_PIN_SD2WP, "sd2_wp"),
+        PINCTRL_PIN(WMT_PIN_SD2DATA1, "sd2_data1"),
+        PINCTRL_PIN(WMT_PIN_SD2DATA2, "sd2_data2"),
+        PINCTRL_PIN(WMT_PIN_SD2CMD, "sd2_cmd"),
+        PINCTRL_PIN(WMT_PIN_SD2CLK, "sd2_clk"),
+        PINCTRL_PIN(WMT_PIN_SD2PWR, "sd2_pwr"),
+        PINCTRL_PIN(WMT_PIN_SD1CLK, "sd1_clk"),
+        PINCTRL_PIN(WMT_PIN_SD1CMD, "sd1_cmd"),
+        PINCTRL_PIN(WMT_PIN_SD1PWR, "sd1_pwr"),
+        PINCTRL_PIN(WMT_PIN_SD1WP, "sd1_wp"),
+        PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"),
+        PINCTRL_PIN(WMT_PIN_SPI0SS3, "spi0_ss3"),
+        PINCTRL_PIN(WMT_PIN_SPI0SS2, "spi0_ss2"),
+        PINCTRL_PIN(WMT_PIN_PWMOUT1, "pwmout1"),
+        PINCTRL_PIN(WMT_PIN_PWMOUT0, "pwmout0"),
+};
+
+/* Order of these names must match the above list */
+static const char * const wm8750_groups[] = {
+        "extgpio0",
+        "extgpio1",
+        "extgpio2",
+        "extgpio3",
+        "extgpio4",
+        "extgpio5",
+        "extgpio6",
+        "extgpio7",
+        "wakeup0",
+        "wakeup1",
+        "sd0_cd",
+        "vdout0",
+        "vdout1",
+        "vdout2",
+        "vdout3",
+        "vdout4",
+        "vdout5",
+        "vdout6",
+        "vdout7",
+        "vdout8",
+        "vdout9",
+        "vdout10",
+        "vdout11",
+        "vdout12",
+        "vdout13",
+        "vdout14",
+        "vdout15",
+        "vdout16",
+        "vdout17",
+        "vdout18",
+        "vdout19",
+        "vdout20",
+        "vdout21",
+        "vdout22",
+        "vdout23",
+        "vdin0",
+        "vdin1",
+        "vdin2",
+        "vdin3",
+        "vdin4",
+        "vdin5",
+        "vdin6",
+        "vdin7",
+        "spi0_mosi",
+        "spi0_miso",
+        "spi0_ss",
+        "spi0_clk",
+        "spi0_ssb",
+        "sd0_clk",
+        "sd0_cmd",
+        "sd0_wp",
+        "sd0_data0",
+        "sd0_data1",
+        "sd0_data2",
+        "sd0_data3",
+        "sd1_data0",
+        "sd1_data1",
+        "sd1_data2",
+        "sd1_data3",
+        "sd1_data4",
+        "sd1_data5",
+        "sd1_data6",
+        "sd1_data7",
+        "i2c0_scl",
+        "i2c0_sda",
+        "i2c1_scl",
+        "i2c1_sda",
+        "i2c2_scl",
+        "i2c2_sda",
+        "uart0_rts",
+        "uart0_txd",
+        "uart0_cts",
+        "uart0_rxd",
+        "uart1_rts",
+        "uart1_txd",
+        "uart1_cts",
+        "uart1_rxd",
+        "uart2_rts",
+        "uart2_txd",
+        "uart2_cts",
+        "uart2_rxd",
+        "uart3_rts",
+        "uart3_txd",
+        "uart3_cts",
+        "uart3_rxd",
+        "sd2_cd",
+        "sd2_data3",
+        "sd2_data0",
+        "sd2_wp",
+        "sd2_data1",
+        "sd2_data2",
+        "sd2_cmd",
+        "sd2_clk",
+        "sd2_pwr",
+        "sd1_clk",
+        "sd1_cmd",
+        "sd1_pwr",
+        "sd1_wp",
+        "sd1_cd",
+        "spi0_ss3",
+        "spi0_ss2",
+        "pwmout1",
+        "pwmout0",
+};
+
+static int wm8750_pinctrl_probe(struct platform_device *pdev)
+{
+        struct wmt_pinctrl_data *data;
+
+        data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+        if (!data) {
+                dev_err(&pdev->dev, "failed to allocate data\n");
+                return -ENOMEM;
+        }
+
+        data->banks = wm8750_banks;
+        data->nbanks = ARRAY_SIZE(wm8750_banks);
+        data->pins = wm8750_pins;
+        data->npins = ARRAY_SIZE(wm8750_pins);
+        data->groups = wm8750_groups;
+        data->ngroups = ARRAY_SIZE(wm8750_groups);
+
+        return wmt_pinctrl_probe(pdev, data);
+}
+
+static int wm8750_pinctrl_remove(struct platform_device *pdev)
+{
+        return wmt_pinctrl_remove(pdev);
+}
+
+static struct of_device_id wmt_pinctrl_of_match[] = {
+        { .compatible = "wm,wm8750-pinctrl" },
+        { /* sentinel */ },
+};
+
+static struct platform_driver wmt_pinctrl_driver = {
+        .probe  = wm8750_pinctrl_probe,
+        .remove = wm8750_pinctrl_remove,
+        .driver = {
+                .name   = "pinctrl-wm8750",
+                .owner  = THIS_MODULE,
+                .of_match_table = wmt_pinctrl_of_match,
+        },
+};
+
+module_platform_driver(wmt_pinctrl_driver);
+
+MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
+MODULE_DESCRIPTION("Wondermedia WM8750 Pincontrol driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8850.c b/drivers/pinctrl/vt8500/pinctrl-wm8850.c
new file mode 100644
index 000000000000..ecadce9c91d5
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8850.c
@@ -0,0 +1,388 @@
+/*
+ * Pinctrl data for Wondermedia WM8850 SoC
+ *
+ * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "pinctrl-wmt.h"
+
+/*
+ * Describe the register offsets within the GPIO memory space
+ * The dedicated external GPIO's should always be listed in bank 0
+ * so they are exported in the 0..31 range which is what users
+ * expect.
+ *
+ * Do not reorder these banks as it will change the pin numbering
+ */
+static const struct wmt_pinctrl_bank_registers wm8850_banks[] = {
+        WMT_PINCTRL_BANK(0x40, 0x80, 0xC0, 0x00, 0x480, 0x4C0),         /* 0 */
+        WMT_PINCTRL_BANK(0x44, 0x84, 0xC4, 0x04, 0x484, 0x4C4),         /* 1 */
+        WMT_PINCTRL_BANK(0x48, 0x88, 0xC8, 0x08, 0x488, 0x4C8),         /* 2 */
+        WMT_PINCTRL_BANK(0x4C, 0x8C, 0xCC, 0x0C, 0x48C, 0x4CC),         /* 3 */
+        WMT_PINCTRL_BANK(0x50, 0x90, 0xD0, 0x10, 0x490, 0x4D0),         /* 4 */
+        WMT_PINCTRL_BANK(0x54, 0x94, 0xD4, 0x14, 0x494, 0x4D4),         /* 5 */
+        WMT_PINCTRL_BANK(0x58, 0x98, 0xD8, 0x18, 0x498, 0x4D8),         /* 6 */
+        WMT_PINCTRL_BANK(0x5C, 0x9C, 0xDC, 0x1C, 0x49C, 0x4DC),         /* 7 */
+        WMT_PINCTRL_BANK(0x60, 0xA0, 0xE0, 0x20, 0x4A0, 0x4E0),         /* 8 */
+        WMT_PINCTRL_BANK(0x70, 0xB0, 0xF0, 0x30, 0x4B0, 0x4F0),         /* 9 */
+        WMT_PINCTRL_BANK(0x7C, 0xBC, 0xDC, 0x3C, 0x4BC, 0x4FC),         /* 10 */
+};
+
+/* Please keep sorted by bank/bit */
+#define WMT_PIN_EXTGPIO0        WMT_PIN(0, 0)
+#define WMT_PIN_EXTGPIO1        WMT_PIN(0, 1)
+#define WMT_PIN_EXTGPIO2        WMT_PIN(0, 2)
+#define WMT_PIN_EXTGPIO3        WMT_PIN(0, 3)
+#define WMT_PIN_EXTGPIO4        WMT_PIN(0, 4)
+#define WMT_PIN_EXTGPIO5        WMT_PIN(0, 5)
+#define WMT_PIN_EXTGPIO6        WMT_PIN(0, 6)
+#define WMT_PIN_EXTGPIO7        WMT_PIN(0, 7)
+#define WMT_PIN_WAKEUP0         WMT_PIN(0, 16)
+#define WMT_PIN_WAKEUP1         WMT_PIN(0, 17)
+#define WMT_PIN_WAKEUP2         WMT_PIN(0, 18)
+#define WMT_PIN_WAKEUP3         WMT_PIN(0, 19)
+#define WMT_PIN_SUSGPIO0        WMT_PIN(0, 21)
+#define WMT_PIN_SUSGPIO1        WMT_PIN(0, 22)
+#define WMT_PIN_SD0CD           WMT_PIN(0, 28)
+#define WMT_PIN_VDOUT0          WMT_PIN(1, 0)
+#define WMT_PIN_VDOUT1          WMT_PIN(1, 1)
+#define WMT_PIN_VDOUT2          WMT_PIN(1, 2)
+#define WMT_PIN_VDOUT3          WMT_PIN(1, 3)
+#define WMT_PIN_VDOUT4          WMT_PIN(1, 4)
+#define WMT_PIN_VDOUT5          WMT_PIN(1, 5)
+#define WMT_PIN_VDOUT6          WMT_PIN(1, 6)
+#define WMT_PIN_VDOUT7          WMT_PIN(1, 7)
+#define WMT_PIN_VDOUT8          WMT_PIN(1, 8)
+#define WMT_PIN_VDOUT9          WMT_PIN(1, 9)
+#define WMT_PIN_VDOUT10         WMT_PIN(1, 10)
+#define WMT_PIN_VDOUT11         WMT_PIN(1, 11)
+#define WMT_PIN_VDOUT12         WMT_PIN(1, 12)
+#define WMT_PIN_VDOUT13         WMT_PIN(1, 13)
+#define WMT_PIN_VDOUT14         WMT_PIN(1, 14)
+#define WMT_PIN_VDOUT15         WMT_PIN(1, 15)
+#define WMT_PIN_VDOUT16         WMT_PIN(1, 16)
+#define WMT_PIN_VDOUT17         WMT_PIN(1, 17)
+#define WMT_PIN_VDOUT18         WMT_PIN(1, 18)
+#define WMT_PIN_VDOUT19         WMT_PIN(1, 19)
+#define WMT_PIN_VDOUT20         WMT_PIN(1, 20)
+#define WMT_PIN_VDOUT21         WMT_PIN(1, 21)
+#define WMT_PIN_VDOUT22         WMT_PIN(1, 22)
+#define WMT_PIN_VDOUT23         WMT_PIN(1, 23)
+#define WMT_PIN_VDIN0           WMT_PIN(2, 0)
+#define WMT_PIN_VDIN1           WMT_PIN(2, 1)
+#define WMT_PIN_VDIN2           WMT_PIN(2, 2)
+#define WMT_PIN_VDIN3           WMT_PIN(2, 3)
+#define WMT_PIN_VDIN4           WMT_PIN(2, 4)
+#define WMT_PIN_VDIN5           WMT_PIN(2, 5)
+#define WMT_PIN_VDIN6           WMT_PIN(2, 6)
+#define WMT_PIN_VDIN7           WMT_PIN(2, 7)
+#define WMT_PIN_SPI0_MOSI       WMT_PIN(2, 24)
+#define WMT_PIN_SPI0_MISO       WMT_PIN(2, 25)
+#define WMT_PIN_SPI0_SS         WMT_PIN(2, 26)
+#define WMT_PIN_SPI0_CLK        WMT_PIN(2, 27)
+#define WMT_PIN_SPI0_SSB        WMT_PIN(2, 28)
+#define WMT_PIN_SD0CLK          WMT_PIN(3, 17)
+#define WMT_PIN_SD0CMD          WMT_PIN(3, 18)
+#define WMT_PIN_SD0WP           WMT_PIN(3, 19)
+#define WMT_PIN_SD0DATA0        WMT_PIN(3, 20)
+#define WMT_PIN_SD0DATA1        WMT_PIN(3, 21)
+#define WMT_PIN_SD0DATA2        WMT_PIN(3, 22)
+#define WMT_PIN_SD0DATA3        WMT_PIN(3, 23)
+#define WMT_PIN_SD1DATA0        WMT_PIN(3, 24)
+#define WMT_PIN_SD1DATA1        WMT_PIN(3, 25)
+#define WMT_PIN_SD1DATA2        WMT_PIN(3, 26)
+#define WMT_PIN_SD1DATA3        WMT_PIN(3, 27)
+#define WMT_PIN_SD1DATA4        WMT_PIN(3, 28)
+#define WMT_PIN_SD1DATA5        WMT_PIN(3, 29)
+#define WMT_PIN_SD1DATA6        WMT_PIN(3, 30)
+#define WMT_PIN_SD1DATA7        WMT_PIN(3, 31)
+#define WMT_PIN_I2C0_SCL        WMT_PIN(5, 8)
+#define WMT_PIN_I2C0_SDA        WMT_PIN(5, 9)
+#define WMT_PIN_I2C1_SCL        WMT_PIN(5, 10)
+#define WMT_PIN_I2C1_SDA        WMT_PIN(5, 11)
+#define WMT_PIN_I2C2_SCL        WMT_PIN(5, 12)
+#define WMT_PIN_I2C2_SDA        WMT_PIN(5, 13)
+#define WMT_PIN_UART0_RTS       WMT_PIN(5, 16)
+#define WMT_PIN_UART0_TXD       WMT_PIN(5, 17)
+#define WMT_PIN_UART0_CTS       WMT_PIN(5, 18)
+#define WMT_PIN_UART0_RXD       WMT_PIN(5, 19)
+#define WMT_PIN_UART1_RTS       WMT_PIN(5, 20)
+#define WMT_PIN_UART1_TXD       WMT_PIN(5, 21)
+#define WMT_PIN_UART1_CTS       WMT_PIN(5, 22)
+#define WMT_PIN_UART1_RXD       WMT_PIN(5, 23)
+#define WMT_PIN_UART2_RTS       WMT_PIN(5, 24)
+#define WMT_PIN_UART2_TXD       WMT_PIN(5, 25)
+#define WMT_PIN_UART2_CTS       WMT_PIN(5, 26)
+#define WMT_PIN_UART2_RXD       WMT_PIN(5, 27)
+#define WMT_PIN_SD2WP           WMT_PIN(6, 3)
+#define WMT_PIN_SD2CMD          WMT_PIN(6, 6)
+#define WMT_PIN_SD2CLK          WMT_PIN(6, 7)
+#define WMT_PIN_SD2PWR          WMT_PIN(6, 9)
+#define WMT_PIN_SD1CLK          WMT_PIN(7, 0)
+#define WMT_PIN_SD1CMD          WMT_PIN(7, 1)
+#define WMT_PIN_SD1PWR          WMT_PIN(7, 10)
+#define WMT_PIN_SD1WP           WMT_PIN(7, 11)
+#define WMT_PIN_SD1CD           WMT_PIN(7, 12)
+#define WMT_PIN_PWMOUT1         WMT_PIN(7, 26)
+#define WMT_PIN_PWMOUT0         WMT_PIN(7, 27)
+
+static const struct pinctrl_pin_desc wm8850_pins[] = {
+        PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
+        PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP2, "wakeup2"),
+        PINCTRL_PIN(WMT_PIN_WAKEUP3, "wakeup3"),
+        PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"),
+        PINCTRL_PIN(WMT_PIN_SUSGPIO1, "susgpio1"),
+        PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"),
+        PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
+        PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
+        PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
+        PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
+        PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
+        PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
+        PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"),
+        PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"),
+        PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"),
+        PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"),
+        PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"),
+        PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"),
+        PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"),
+        PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"),
+        PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"),
+        PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"),
+        PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"),
+        PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"),
+        PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"),
+        PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"),
+        PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"),
+        PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"),
+        PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"),
+        PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"),
+        PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
+        PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
+        PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
+        PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
+        PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
+        PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
+        PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
+        PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
+        PINCTRL_PIN(WMT_PIN_SPI0_MOSI, "spi0_mosi"),
+        PINCTRL_PIN(WMT_PIN_SPI0_MISO, "spi0_miso"),
+        PINCTRL_PIN(WMT_PIN_SPI0_SS, "spi0_ss"),
+        PINCTRL_PIN(WMT_PIN_SPI0_CLK, "spi0_clk"),
+        PINCTRL_PIN(WMT_PIN_SPI0_SSB, "spi0_ssb"),
+        PINCTRL_PIN(WMT_PIN_SD0CLK, "sd0_clk"),
+        PINCTRL_PIN(WMT_PIN_SD0CMD, "sd0_cmd"),
+        PINCTRL_PIN(WMT_PIN_SD0WP, "sd0_wp"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA0, "sd0_data0"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA1, "sd0_data1"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA2, "sd0_data2"),
+        PINCTRL_PIN(WMT_PIN_SD0DATA3, "sd0_data3"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA0, "sd1_data0"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA1, "sd1_data1"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA2, "sd1_data2"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA3, "sd1_data3"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA4, "sd1_data4"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA5, "sd1_data5"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA6, "sd1_data6"),
+        PINCTRL_PIN(WMT_PIN_SD1DATA7, "sd1_data7"),
+        PINCTRL_PIN(WMT_PIN_I2C0_SCL, "i2c0_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C0_SDA, "i2c0_sda"),
+        PINCTRL_PIN(WMT_PIN_I2C1_SCL, "i2c1_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C1_SDA, "i2c1_sda"),
+        PINCTRL_PIN(WMT_PIN_I2C2_SCL, "i2c2_scl"),
+        PINCTRL_PIN(WMT_PIN_I2C2_SDA, "i2c2_sda"),
+        PINCTRL_PIN(WMT_PIN_UART0_RTS, "uart0_rts"),
+        PINCTRL_PIN(WMT_PIN_UART0_TXD, "uart0_txd"),
+        PINCTRL_PIN(WMT_PIN_UART0_CTS, "uart0_cts"),
+        PINCTRL_PIN(WMT_PIN_UART0_RXD, "uart0_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART1_RTS, "uart1_rts"),
+        PINCTRL_PIN(WMT_PIN_UART1_TXD, "uart1_txd"),
+        PINCTRL_PIN(WMT_PIN_UART1_CTS, "uart1_cts"),
+        PINCTRL_PIN(WMT_PIN_UART1_RXD, "uart1_rxd"),
+        PINCTRL_PIN(WMT_PIN_UART2_RTS, "uart2_rts"),
+        PINCTRL_PIN(WMT_PIN_UART2_TXD, "uart2_txd"),
+        PINCTRL_PIN(WMT_PIN_UART2_CTS, "uart2_cts"),
+        PINCTRL_PIN(WMT_PIN_UART2_RXD, "uart2_rxd"),
+        PINCTRL_PIN(WMT_PIN_SD2WP, "sd2_wp"),
+        PINCTRL_PIN(WMT_PIN_SD2CMD, "sd2_cmd"),
+        PINCTRL_PIN(WMT_PIN_SD2CLK, "sd2_clk"),
+        PINCTRL_PIN(WMT_PIN_SD2PWR, "sd2_pwr"),
+        PINCTRL_PIN(WMT_PIN_SD1CLK, "sd1_clk"),
+        PINCTRL_PIN(WMT_PIN_SD1CMD, "sd1_cmd"),
+        PINCTRL_PIN(WMT_PIN_SD1PWR, "sd1_pwr"),
+        PINCTRL_PIN(WMT_PIN_SD1WP, "sd1_wp"),
+        PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"),
+        PINCTRL_PIN(WMT_PIN_PWMOUT1, "pwmout1"),
+        PINCTRL_PIN(WMT_PIN_PWMOUT0, "pwmout0"),
+};
+
+/* Order of these names must match the above list */
+static const char * const wm8850_groups[] = {
+        "extgpio0",
+        "extgpio1",
+        "extgpio2",
+        "extgpio3",
+        "extgpio4",
+        "extgpio5",
+        "extgpio6",
+        "extgpio7",
+        "wakeup0",
+        "wakeup1",
+        "wakeup2",
+        "wakeup3",
+        "susgpio0",
+        "susgpio1",
+        "sd0_cd",
+        "vdout0",
+        "vdout1",
+        "vdout2",
+        "vdout3",
+        "vdout4",
+        "vdout5",
+        "vdout6",
+        "vdout7",
+        "vdout8",
+        "vdout9",
+        "vdout10",
+        "vdout11",
+        "vdout12",
+        "vdout13",
+        "vdout14",
+        "vdout15",
+        "vdout16",
+        "vdout17",
+        "vdout18",
+        "vdout19",
+        "vdout20",
+        "vdout21",
+        "vdout22",
+        "vdout23",
+        "vdin0",
+        "vdin1",
+        "vdin2",
+        "vdin3",
+        "vdin4",
+        "vdin5",
+        "vdin6",
+        "vdin7",
+        "spi0_mosi",
+        "spi0_miso",
+        "spi0_ss",
+        "spi0_clk",
+        "spi0_ssb",
+        "sd0_clk",
+        "sd0_cmd",
+        "sd0_wp",
+        "sd0_data0",
+        "sd0_data1",
+        "sd0_data2",
+        "sd0_data3",
+        "sd1_data0",
+        "sd1_data1",
+        "sd1_data2",
+        "sd1_data3",
+        "sd1_data4",
+        "sd1_data5",
+        "sd1_data6",
+        "sd1_data7",
+        "i2c0_scl",
+        "i2c0_sda",
+        "i2c1_scl",
+        "i2c1_sda",
+        "i2c2_scl",
+        "i2c2_sda",
+        "uart0_rts",
+        "uart0_txd",
+        "uart0_cts",
+        "uart0_rxd",
+        "uart1_rts",
+        "uart1_txd",
+        "uart1_cts",
+        "uart1_rxd",
+        "uart2_rts",
+        "uart2_txd",
+        "uart2_cts",
+        "uart2_rxd",
+        "sd2_wp",
+        "sd2_cmd",
+        "sd2_clk",
+        "sd2_pwr",
+        "sd1_clk",
+        "sd1_cmd",
+        "sd1_pwr",
+        "sd1_wp",
+        "sd1_cd",
+        "pwmout1",
+        "pwmout0",
+};
+
+static int wm8850_pinctrl_probe(struct platform_device *pdev)
+{
+        struct wmt_pinctrl_data *data;
+
+        data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+        if (!data) {
+                dev_err(&pdev->dev, "failed to allocate data\n");
+                return -ENOMEM;
+        }
+
+        data->banks = wm8850_banks;
+        data->nbanks = ARRAY_SIZE(wm8850_banks);
+        data->pins = wm8850_pins;
+        data->npins = ARRAY_SIZE(wm8850_pins);
+        data->groups = wm8850_groups;
+        data->ngroups = ARRAY_SIZE(wm8850_groups);
+
+        return wmt_pinctrl_probe(pdev, data);
+}
+
+static int wm8850_pinctrl_remove(struct platform_device *pdev)
+{
+        return wmt_pinctrl_remove(pdev);
+}
+
+static struct of_device_id wmt_pinctrl_of_match[] = {
+        { .compatible = "wm,wm8850-pinctrl" },
+        { /* sentinel */ },
+};
+
+static struct platform_driver wmt_pinctrl_driver = {
+        .probe  = wm8850_pinctrl_probe,
+        .remove = wm8850_pinctrl_remove,
+        .driver = {
+                .name   = "pinctrl-wm8850",
+                .owner  = THIS_MODULE,
+                .of_match_table = wmt_pinctrl_of_match,
+        },
+};
+
+module_platform_driver(wmt_pinctrl_driver);
+
+MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
+MODULE_DESCRIPTION("Wondermedia WM8850 Pincontrol driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_pinctrl_of_match);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
new file mode 100644
index 000000000000..ab63104e8dc9
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -0,0 +1,632 @@
+/*
+ * Pinctrl driver for the Wondermedia SoC's
+ *
+ * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "pinctrl-wmt.h"
+
+static inline void wmt_setbits(struct wmt_pinctrl_data *data, u32 reg,
+                                 u32 mask)
+{
+        u32 val;
+
+        val = readl_relaxed(data->base + reg);
+        val |= mask;
+        writel_relaxed(val, data->base + reg);
+}
+
+static inline void wmt_clearbits(struct wmt_pinctrl_data *data, u32 reg,
+                                   u32 mask)
+{
+        u32 val;
+
+        val = readl_relaxed(data->base + reg);
+        val &= ~mask;
+        writel_relaxed(val, data->base + reg);
+}
+
+enum wmt_func_sel {
+        WMT_FSEL_GPIO_IN = 0,
+        WMT_FSEL_GPIO_OUT = 1,
+        WMT_FSEL_ALT = 2,
+        WMT_FSEL_COUNT = 3,
+};
+
+static const char * const wmt_functions[WMT_FSEL_COUNT] = {
+        [WMT_FSEL_GPIO_IN] = "gpio_in",
+        [WMT_FSEL_GPIO_OUT] = "gpio_out",
+        [WMT_FSEL_ALT] = "alt",
+};
+
+static int wmt_pmx_get_functions_count(struct pinctrl_dev *pctldev)
+{
+        return WMT_FSEL_COUNT;
+}
+
+static const char *wmt_pmx_get_function_name(struct pinctrl_dev *pctldev,
+                                             unsigned selector)
+{
+        return wmt_functions[selector];
+}
+
+static int wmt_pmx_get_function_groups(struct pinctrl_dev *pctldev,
+                                       unsigned selector,
+                                       const char * const **groups,
+                                       unsigned * const num_groups)
+{
+        struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
+
+        /* every pin does every function */
+        *groups = data->groups;
+        *num_groups = data->ngroups;
+
+        return 0;
+}
+
+static int wmt_set_pinmux(struct wmt_pinctrl_data *data, unsigned func,
+                          unsigned pin)
+{
+        u32 bank = WMT_BANK_FROM_PIN(pin);
+        u32 bit = WMT_BIT_FROM_PIN(pin);
+        u32 reg_en = data->banks[bank].reg_en;
+        u32 reg_dir = data->banks[bank].reg_dir;
+
+        if (reg_dir == NO_REG) {
+                dev_err(data->dev, "pin:%d no direction register defined\n",
+                        pin);
+                return -EINVAL;
+        }
+
+        /*
+         * If reg_en == NO_REG, we assume it is a dedicated GPIO and cannot be
+         * disabled (as on VT8500) and that no alternate function is available.
+         */
+        switch (func) {
+        case WMT_FSEL_GPIO_IN:
+                if (reg_en != NO_REG)
+                        wmt_setbits(data, reg_en, BIT(bit));
+                wmt_clearbits(data, reg_dir, BIT(bit));
+                break;
+        case WMT_FSEL_GPIO_OUT:
+                if (reg_en != NO_REG)
+                        wmt_setbits(data, reg_en, BIT(bit));
+                wmt_setbits(data, reg_dir, BIT(bit));
+                break;
+        case WMT_FSEL_ALT:
+                if (reg_en == NO_REG) {
+                        dev_err(data->dev, "pin:%d no alt function available\n",
+                                pin);
+                        return -EINVAL;
+                }
+                wmt_clearbits(data, reg_en, BIT(bit));
+        }
+
+        return 0;
+}
+
+static int wmt_pmx_enable(struct pinctrl_dev *pctldev,
+                          unsigned func_selector,
+                          unsigned group_selector)
+{
+        struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
+        u32 pinnum = data->pins[group_selector].number;
+
+        return wmt_set_pinmux(data, func_selector, pinnum);
+}
+
+static void wmt_pmx_disable(struct pinctrl_dev *pctldev,
+                            unsigned func_selector,
+                            unsigned group_selector)
+{
+        struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
+        u32 pinnum = data->pins[group_selector].number;
+
+        /* disable by setting GPIO_IN */
+        wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, pinnum);
+}
+
+static void wmt_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
+                                      struct pinctrl_gpio_range *range,
+                                      unsigned offset)
+{
+        struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
+
+        /* disable by setting GPIO_IN */
+        wmt_set_pinmux(data, WMT_FSEL_GPIO_IN, offset);
+}
+
+static int wmt_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+                                      struct pinctrl_gpio_range *range,
+                                      unsigned offset,
+                                      bool input)
+{
+        struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
+
+        wmt_set_pinmux(data, (input ? WMT_FSEL_GPIO_IN : WMT_FSEL_GPIO_OUT),
+                       offset);
+
+        return 0;
+}
+
+static struct pinmux_ops wmt_pinmux_ops = {
+        .get_functions_count = wmt_pmx_get_functions_count,
+        .get_function_name = wmt_pmx_get_function_name,
+        .get_function_groups = wmt_pmx_get_function_groups,
+        .enable = wmt_pmx_enable,
+        .disable = wmt_pmx_disable,
+        .gpio_disable_free = wmt_pmx_gpio_disable_free,
+        .gpio_set_direction = wmt_pmx_gpio_set_direction,
+};
+
+static int wmt_get_groups_count(struct pinctrl_dev *pctldev)
+{
+        struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
+
+        return data->ngroups;
+}
+
+static const char *wmt_get_group_name(struct pinctrl_dev *pctldev,
+                                      unsigned selector)
+{
+        struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
+
+        return data->groups[selector];
+}
+
+static int wmt_get_group_pins(struct pinctrl_dev *pctldev,
+                              unsigned selector,
+                              const unsigned **pins,
+                              unsigned *num_pins)
+{
+        struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
+
+        *pins = &data->pins[selector].number;
+        *num_pins = 1;
+
+        return 0;
+}
+
+static int wmt_pctl_find_group_by_pin(struct wmt_pinctrl_data *data, u32 pin)
+{
+        int i;
+
+        for (i = 0; i < data->npins; i++) {
+                if (data->pins[i].number == pin)
+                        return i;
+        }
+
+        return -EINVAL;
+}
+
+static int wmt_pctl_dt_node_to_map_func(struct wmt_pinctrl_data *data,
+                                        struct device_node *np,
+                                        u32 pin, u32 fnum,
+                                        struct pinctrl_map **maps)
+{
+        int group;
+        struct pinctrl_map *map = *maps;
+
+        if (fnum >= ARRAY_SIZE(wmt_functions)) {
+                dev_err(data->dev, "invalid wm,function %d\n", fnum);
+                return -EINVAL;
+        }
+
+        group = wmt_pctl_find_group_by_pin(data, pin);
+        if (group < 0) {
+                dev_err(data->dev, "unable to match pin %d to group\n", pin);
+                return group;
+        }
+
+        map->type = PIN_MAP_TYPE_MUX_GROUP;
+        map->data.mux.group = data->groups[group];
+        map->data.mux.function = wmt_functions[fnum];
+        (*maps)++;
+
+        return 0;
+}
+
+static int wmt_pctl_dt_node_to_map_pull(struct wmt_pinctrl_data *data,
+                                        struct device_node *np,
+                                        u32 pin, u32 pull,
+                                        struct pinctrl_map **maps)
+{
+        int group;
+        unsigned long *configs;
+        struct pinctrl_map *map = *maps;
+
+        if (pull > 2) {
+                dev_err(data->dev, "invalid wm,pull %d\n", pull);
+                return -EINVAL;
+        }
+
+        group = wmt_pctl_find_group_by_pin(data, pin);
+        if (group < 0) {
+                dev_err(data->dev, "unable to match pin %d to group\n", pin);
+                return group;
+        }
+
+        configs = kzalloc(sizeof(*configs), GFP_KERNEL);
+        if (!configs)
+                return -ENOMEM;
+
+        configs[0] = pull;
+
+        map->type = PIN_MAP_TYPE_CONFIGS_PIN;
+        map->data.configs.group_or_pin = data->groups[group];
+        map->data.configs.configs = configs;
+        map->data.configs.num_configs = 1;
+        (*maps)++;
+
+        return 0;
+}
+
+static void wmt_pctl_dt_free_map(struct pinctrl_dev *pctldev,
+                                 struct pinctrl_map *maps,
+                                 unsigned num_maps)
+{
+        int i;
+
+        for (i = 0; i < num_maps; i++)
+                if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
+                        kfree(maps[i].data.configs.configs);
+
+        kfree(maps);
+}
+
+static int wmt_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                   struct device_node *np,
+                                   struct pinctrl_map **map,
+                                   unsigned *num_maps)
+{
+        struct pinctrl_map *maps, *cur_map;
+        struct property *pins, *funcs, *pulls;
+        u32 pin, func, pull;
+        int num_pins, num_funcs, num_pulls, maps_per_pin;
+        int i, err;
+        struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
+
+        pins = of_find_property(np, "wm,pins", NULL);
+        if (!pins) {
+                dev_err(data->dev, "missing wmt,pins property\n");
+                return -EINVAL;
+        }
+
+        funcs = of_find_property(np, "wm,function", NULL);
+        pulls = of_find_property(np, "wm,pull", NULL);
+
+        if (!funcs && !pulls) {
+                dev_err(data->dev, "neither wm,function nor wm,pull specified\n");
+                return -EINVAL;
+        }
+
+        /*
+         * The following lines calculate how many values are defined for each
+         * of the properties.
+         */
+        num_pins = pins->length / sizeof(u32);
+        num_funcs = funcs ? (funcs->length / sizeof(u32)) : 0;
+        num_pulls = pulls ? (pulls->length / sizeof(u32)) : 0;
+
+        if (num_funcs > 1 && num_funcs != num_pins) {
+                dev_err(data->dev, "wm,function must have 1 or %d entries\n",
+                        num_pins);
+                return -EINVAL;
+        }
+
+        if (num_pulls > 1 && num_pulls != num_pins) {
+                dev_err(data->dev, "wm,pull must have 1 or %d entries\n",
+                        num_pins);
+                return -EINVAL;
+        }
+
+        maps_per_pin = 0;
+        if (num_funcs)
+                maps_per_pin++;
+        if (num_pulls)
+                maps_per_pin++;
+
+        cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
+                                 GFP_KERNEL);
+        if (!maps)
+                return -ENOMEM;
+
+        for (i = 0; i < num_pins; i++) {
+                err = of_property_read_u32_index(np, "wm,pins", i, &pin);
+                if (err)
+                        goto fail;
+
+                if (pin >= (data->nbanks * 32)) {
+                        dev_err(data->dev, "invalid wm,pins value\n");
+                        err = -EINVAL;
+                        goto fail;
+                }
+
+                if (num_funcs) {
+                        err = of_property_read_u32_index(np, "wm,function",
+                                                (num_funcs > 1 ? i : 0), &func);
+                        if (err)
+                                goto fail;
+
+                        err = wmt_pctl_dt_node_to_map_func(data, np, pin, func,
+                                                           &cur_map);
+                        if (err)
+                                goto fail;
+                }
+
+                if (num_pulls) {
+                        err = of_property_read_u32_index(np, "wm,pull",
+                                                (num_pulls > 1 ? i : 0), &pull);
+                        if (err)
+                                goto fail;
+
+                        err = wmt_pctl_dt_node_to_map_pull(data, np, pin, pull,
+                                                           &cur_map);
+                        if (err)
+                                goto fail;
+                }
+        }
+        *map = maps;
+        *num_maps = num_pins * maps_per_pin;
+        return 0;
+
+/*
+ * The fail path removes any maps that have been allocated. The fail path is
+ * only called from code after maps has been kzalloc'd. It is also safe to
+ * pass 'num_pins * maps_per_pin' as the map count even though we probably
+ * failed before all the mappings were read as all maps are allocated at once,
+ * and configs are only allocated for .type = PIN_MAP_TYPE_CONFIGS_PIN - there
+ * is no failpath where a config can be allocated without .type being set.
+ */
+fail:
+        wmt_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
+        return err;
+}
+
+static struct pinctrl_ops wmt_pctl_ops = {
+        .get_groups_count = wmt_get_groups_count,
+        .get_group_name = wmt_get_group_name,
+        .get_group_pins = wmt_get_group_pins,
+        .dt_node_to_map = wmt_pctl_dt_node_to_map,
+        .dt_free_map = wmt_pctl_dt_free_map,
+};
+
+static int wmt_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
+                           unsigned long *config)
+{
+        return -ENOTSUPP;
+}
+
+static int wmt_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
+                           unsigned long config)
+{
+        struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
+        enum pin_config_param param = pinconf_to_config_param(config);
+        u16 arg = pinconf_to_config_argument(config);
+        u32 bank = WMT_BANK_FROM_PIN(pin);
+        u32 bit = WMT_BIT_FROM_PIN(pin);
+        u32 reg_pull_en = data->banks[bank].reg_pull_en;
+        u32 reg_pull_cfg = data->banks[bank].reg_pull_cfg;
+
+        if ((reg_pull_en == NO_REG) || (reg_pull_cfg == NO_REG)) {
+                dev_err(data->dev, "bias functions not supported on pin %d\n",
+                        pin);
+                return -EINVAL;
+        }
+
+        if ((param == PIN_CONFIG_BIAS_PULL_DOWN) ||
+            (param == PIN_CONFIG_BIAS_PULL_UP)) {
+                if (arg == 0)
+                        param = PIN_CONFIG_BIAS_DISABLE;
+        }
+
+        switch (param) {
+        case PIN_CONFIG_BIAS_DISABLE:
+                wmt_clearbits(data, reg_pull_en, BIT(bit));
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                wmt_clearbits(data, reg_pull_cfg, BIT(bit));
+                wmt_setbits(data, reg_pull_en, BIT(bit));
+                break;
+        case PIN_CONFIG_BIAS_PULL_UP:
+                wmt_setbits(data, reg_pull_cfg, BIT(bit));
+                wmt_setbits(data, reg_pull_en, BIT(bit));
+                break;
+        default:
+                dev_err(data->dev, "unknown pinconf param\n");
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static struct pinconf_ops wmt_pinconf_ops = {
+        .pin_config_get = wmt_pinconf_get,
+        .pin_config_set = wmt_pinconf_set,
+};
+
+static struct pinctrl_desc wmt_desc = {
+        .owner = THIS_MODULE,
+        .name = "pinctrl-wmt",
+        .pctlops = &wmt_pctl_ops,
+        .pmxops = &wmt_pinmux_ops,
+        .confops = &wmt_pinconf_ops,
+};
+
+static int wmt_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void wmt_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        pinctrl_free_gpio(chip->base + offset);
+}
+
+static int wmt_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
+{
+        struct wmt_pinctrl_data *data = dev_get_drvdata(chip->dev);
+        u32 bank = WMT_BANK_FROM_PIN(offset);
+        u32 bit = WMT_BIT_FROM_PIN(offset);
+        u32 reg_dir = data->banks[bank].reg_dir;
+        u32 val;
+
+        val = readl_relaxed(data->base + reg_dir);
+        if (val & BIT(bit))
+                return GPIOF_DIR_OUT;
+        else
+                return GPIOF_DIR_IN;
+}
+
+static int wmt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        return pinctrl_gpio_direction_input(chip->base + offset);
+}
+
+static int wmt_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+                                     int value)
+{
+        return pinctrl_gpio_direction_output(chip->base + offset);
+}
+
+static int wmt_gpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+        struct wmt_pinctrl_data *data = dev_get_drvdata(chip->dev);
+        u32 bank = WMT_BANK_FROM_PIN(offset);
+        u32 bit = WMT_BIT_FROM_PIN(offset);
+        u32 reg_data_in = data->banks[bank].reg_data_in;
+
+        if (reg_data_in == NO_REG) {
+                dev_err(data->dev, "no data in register defined\n");
+                return -EINVAL;
+        }
+
+        return !!(readl_relaxed(data->base + reg_data_in) & BIT(bit));
+}
+
+static void wmt_gpio_set_value(struct gpio_chip *chip, unsigned offset,
+                               int val)
+{
+        struct wmt_pinctrl_data *data = dev_get_drvdata(chip->dev);
+        u32 bank = WMT_BANK_FROM_PIN(offset);
+        u32 bit = WMT_BIT_FROM_PIN(offset);
+        u32 reg_data_out = data->banks[bank].reg_data_out;
+
+        if (reg_data_out == NO_REG) {
+                dev_err(data->dev, "no data out register defined\n");
+                return;
+        }
+
+        if (val)
+                wmt_setbits(data, reg_data_out, BIT(bit));
+        else
+                wmt_clearbits(data, reg_data_out, BIT(bit));
+}
+
+static struct gpio_chip wmt_gpio_chip = {
+        .label = "gpio-wmt",
+        .owner = THIS_MODULE,
+        .request = wmt_gpio_request,
+        .free = wmt_gpio_free,
+        .get_direction = wmt_gpio_get_direction,
+        .direction_input = wmt_gpio_direction_input,
+        .direction_output = wmt_gpio_direction_output,
+        .get = wmt_gpio_get_value,
+        .set = wmt_gpio_set_value,
+        .can_sleep = 0,
+};
+
+int wmt_pinctrl_probe(struct platform_device *pdev,
+                      struct wmt_pinctrl_data *data)
+{
+        int err;
+        struct resource *res;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        data->base = devm_request_and_ioremap(&pdev->dev, res);
+        if (!data->base) {
+                dev_err(&pdev->dev, "failed to map memory resource\n");
+                return -EBUSY;
+        }
+
+        wmt_desc.pins = data->pins;
+        wmt_desc.npins = data->npins;
+
+        data->gpio_chip = wmt_gpio_chip;
+        data->gpio_chip.dev = &pdev->dev;
+        data->gpio_chip.of_node = pdev->dev.of_node;
+        data->gpio_chip.ngpio = data->nbanks * 32;
+
+        platform_set_drvdata(pdev, data);
+
+        data->dev = &pdev->dev;
+
+        data->pctl_dev = pinctrl_register(&wmt_desc, &pdev->dev, data);
+        if (!data->pctl_dev) {
+                dev_err(&pdev->dev, "Failed to register pinctrl\n");
+                return -EINVAL;
+        }
+
+        err = gpiochip_add(&data->gpio_chip);
+        if (err) {
+                dev_err(&pdev->dev, "could not add GPIO chip\n");
+                goto fail_gpio;
+        }
+
+        err = gpiochip_add_pin_range(&data->gpio_chip, dev_name(data->dev),
+                                     0, 0, data->nbanks * 32);
+        if (err)
+                goto fail_range;
+
+        dev_info(&pdev->dev, "Pin controller initialized\n");
+
+        return 0;
+
+fail_range:
+        err = gpiochip_remove(&data->gpio_chip);
+        if (err)
+                dev_err(&pdev->dev, "failed to remove gpio chip\n");
+fail_gpio:
+        pinctrl_unregister(data->pctl_dev);
+        return err;
+}
+
+int wmt_pinctrl_remove(struct platform_device *pdev)
+{
+        struct wmt_pinctrl_data *data = platform_get_drvdata(pdev);
+        int err;
+
+        err = gpiochip_remove(&data->gpio_chip);
+        if (err)
+                dev_err(&pdev->dev, "failed to remove gpio chip\n");
+
+        pinctrl_unregister(data->pctl_dev);
+
+        return 0;
+}
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.h b/drivers/pinctrl/vt8500/pinctrl-wmt.h
new file mode 100644
index 000000000000..41f5f2deb5d6
--- /dev/null
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.h
@@ -0,0 +1,79 @@
+/*
+ * Pinctrl driver for the Wondermedia SoC's
+ *
+ * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/gpio.h>
+
+/* VT8500 has no enable register in the extgpio bank. */
+#define NO_REG  0xFFFF
+
+#define WMT_PINCTRL_BANK(__en, __dir, __dout, __din, __pen, __pcfg)     \
+{                                                                       \
+        .reg_en         = __en,                                         \
+        .reg_dir        = __dir,                                        \
+        .reg_data_out   = __dout,                                       \
+        .reg_data_in    = __din,                                        \
+        .reg_pull_en    = __pen,                                        \
+        .reg_pull_cfg   = __pcfg,                                       \
+}
+
+/* Encode/decode the bank/bit pairs into a pin value */
+#define WMT_PIN(__bank, __offset)       ((__bank << 5) | __offset)
+#define WMT_BANK_FROM_PIN(__pin)        (__pin >> 5)
+#define WMT_BIT_FROM_PIN(__pin)         (__pin & 0x1f)
+
+#define WMT_GROUP(__name, __data)               \
+{                                               \
+        .name = __name,                         \
+        .pins = __data,                         \
+        .npins = ARRAY_SIZE(__data),            \
+}
+
+struct wmt_pinctrl_bank_registers {
+        u32     reg_en;
+        u32     reg_dir;
+        u32     reg_data_out;
+        u32     reg_data_in;
+
+        u32     reg_pull_en;
+        u32     reg_pull_cfg;
+};
+
+struct wmt_pinctrl_group {
+        const char *name;
+        const unsigned int *pins;
+        const unsigned npins;
+};
+
+struct wmt_pinctrl_data {
+        struct device *dev;
+        struct pinctrl_dev *pctl_dev;
+
+        /* must be initialized before calling wmt_pinctrl_probe */
+        void __iomem *base;
+        const struct wmt_pinctrl_bank_registers *banks;
+        const struct pinctrl_pin_desc *pins;
+        const char * const *groups;
+
+        u32 nbanks;
+        u32 npins;
+        u32 ngroups;
+
+        struct gpio_chip gpio_chip;
+        struct pinctrl_gpio_range gpio_range;
+};
+
+int wmt_pinctrl_probe(struct platform_device *pdev,
+                      struct wmt_pinctrl_data *data);
+int wmt_pinctrl_remove(struct platform_device *pdev);
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
new file mode 100644
index 000000000000..c9d04f797862
--- /dev/null
+++ b/drivers/reset/Kconfig
@@ -0,0 +1,13 @@
+config ARCH_HAS_RESET_CONTROLLER
+        bool
+
+menuconfig RESET_CONTROLLER
+        bool "Reset Controller Support"
+        default y if ARCH_HAS_RESET_CONTROLLER
+        help
+          Generic Reset Controller support.
+
+          This framework is designed to abstract reset handling of devices
+          via GPIOs or SoC-internal reset controller modules.
+
+          If unsure, say no.
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
new file mode 100644
index 000000000000..1e2d83f2b995
--- /dev/null
+++ b/drivers/reset/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_RESET_CONTROLLER) += core.o
diff --git a/drivers/reset/core.c b/drivers/reset/core.c
new file mode 100644
index 000000000000..d1b6089a0ef8
--- /dev/null
+++ b/drivers/reset/core.c
@@ -0,0 +1,297 @@
+/*
+ * Reset Controller framework
+ *
+ * Copyright 2013 Philipp Zabel, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/reset.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+
+static DEFINE_MUTEX(reset_controller_list_mutex);
+static LIST_HEAD(reset_controller_list);
+
+/**
+ * struct reset_control - a reset control
+ * @rcdev: a pointer to the reset controller device
+ *         this reset control belongs to
+ * @id: ID of the reset controller in the reset
+ *      controller device
+ */
+struct reset_control {
+        struct reset_controller_dev *rcdev;
+        struct device *dev;
+        unsigned int id;
+};
+
+/**
+ * of_reset_simple_xlate - translate reset_spec to the reset line number
+ * @rcdev: a pointer to the reset controller device
+ * @reset_spec: reset line specifier as found in the device tree
+ * @flags: a flags pointer to fill in (optional)
+ *
+ * This simple translation function should be used for reset controllers
+ * with 1:1 mapping, where reset lines can be indexed by number without gaps.
+ */
+int of_reset_simple_xlate(struct reset_controller_dev *rcdev,
+                          const struct of_phandle_args *reset_spec)
+{
+        if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+                return -EINVAL;
+
+        if (reset_spec->args[0] >= rcdev->nr_resets)
+                return -EINVAL;
+
+        return reset_spec->args[0];
+}
+EXPORT_SYMBOL_GPL(of_reset_simple_xlate);
+
+/**
+ * reset_controller_register - register a reset controller device
+ * @rcdev: a pointer to the initialized reset controller device
+ */
+int reset_controller_register(struct reset_controller_dev *rcdev)
+{
+        if (!rcdev->of_xlate) {
+                rcdev->of_reset_n_cells = 1;
+                rcdev->of_xlate = of_reset_simple_xlate;
+        }
+
+        mutex_lock(&reset_controller_list_mutex);
+        list_add(&rcdev->list, &reset_controller_list);
+        mutex_unlock(&reset_controller_list_mutex);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(reset_controller_register);
+
+/**
+ * reset_controller_unregister - unregister a reset controller device
+ * @rcdev: a pointer to the reset controller device
+ */
+void reset_controller_unregister(struct reset_controller_dev *rcdev)
+{
+        mutex_lock(&reset_controller_list_mutex);
+        list_del(&rcdev->list);
+        mutex_unlock(&reset_controller_list_mutex);
+}
+EXPORT_SYMBOL_GPL(reset_controller_unregister);
+
+/**
+ * reset_control_reset - reset the controlled device
+ * @rstc: reset controller
+ */
+int reset_control_reset(struct reset_control *rstc)
+{
+        if (rstc->rcdev->ops->reset)
+                return rstc->rcdev->ops->reset(rstc->rcdev, rstc->id);
+
+        return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(reset_control_reset);
+
+/**
+ * reset_control_assert - asserts the reset line
+ * @rstc: reset controller
+ */
+int reset_control_assert(struct reset_control *rstc)
+{
+        if (rstc->rcdev->ops->assert)
+                return rstc->rcdev->ops->assert(rstc->rcdev, rstc->id);
+
+        return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(reset_control_assert);
+
+/**
+ * reset_control_deassert - deasserts the reset line
+ * @rstc: reset controller
+ */
+int reset_control_deassert(struct reset_control *rstc)
+{
+        if (rstc->rcdev->ops->deassert)
+                return rstc->rcdev->ops->deassert(rstc->rcdev, rstc->id);
+
+        return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(reset_control_deassert);
+
+/**
+ * reset_control_get - Lookup and obtain a reference to a reset controller.
+ * @dev: device to be reset by the controller
+ * @id: reset line name
+ *
+ * Returns a struct reset_control or IS_ERR() condition containing errno.
+ *
+ * Use of id names is optional.
+ */
+struct reset_control *reset_control_get(struct device *dev, const char *id)
+{
+        struct reset_control *rstc = ERR_PTR(-EPROBE_DEFER);
+        struct reset_controller_dev *r, *rcdev;
+        struct of_phandle_args args;
+        int index = 0;
+        int rstc_id;
+        int ret;
+
+        if (!dev)
+                return ERR_PTR(-EINVAL);
+
+        if (id)
+                index = of_property_match_string(dev->of_node,
+                                                 "reset-names", id);
+        ret = of_parse_phandle_with_args(dev->of_node, "resets", "#reset-cells",
+                                         index, &args);
+        if (ret)
+                return ERR_PTR(ret);
+
+        mutex_lock(&reset_controller_list_mutex);
+        rcdev = NULL;
+        list_for_each_entry(r, &reset_controller_list, list) {
+                if (args.np == r->of_node) {
+                        rcdev = r;
+                        break;
+                }
+        }
+        of_node_put(args.np);
+
+        if (!rcdev) {
+                mutex_unlock(&reset_controller_list_mutex);
+                return ERR_PTR(-ENODEV);
+        }
+
+        rstc_id = rcdev->of_xlate(rcdev, &args);
+        if (rstc_id < 0) {
+                mutex_unlock(&reset_controller_list_mutex);
+                return ERR_PTR(rstc_id);
+        }
+
+        try_module_get(rcdev->owner);
+        mutex_unlock(&reset_controller_list_mutex);
+
+        rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
+        if (!rstc) {
+                module_put(rcdev->owner);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        rstc->dev = dev;
+        rstc->rcdev = rcdev;
+        rstc->id = rstc_id;
+
+        return rstc;
+}
+EXPORT_SYMBOL_GPL(reset_control_get);
+
+/**
+ * reset_control_put - free the reset controller
+ * @rstc: reset controller
+ */
+
+void reset_control_put(struct reset_control *rstc)
+{
+        if (IS_ERR(rstc))
+                return;
+
+        module_put(rstc->rcdev->owner);
+        kfree(rstc);
+}
+EXPORT_SYMBOL_GPL(reset_control_put);
+
+static void devm_reset_control_release(struct device *dev, void *res)
+{
+        reset_control_put(*(struct reset_control **)res);
+}
+
+/**
+ * devm_reset_control_get - resource managed reset_control_get()
+ * @dev: device to be reset by the controller
+ * @id: reset line name
+ *
+ * Managed reset_control_get(). For reset controllers returned from this
+ * function, reset_control_put() is called automatically on driver detach.
+ * See reset_control_get() for more information.
+ */
+struct reset_control *devm_reset_control_get(struct device *dev, const char *id)
+{
+        struct reset_control **ptr, *rstc;
+
+        ptr = devres_alloc(devm_reset_control_release, sizeof(*ptr),
+                           GFP_KERNEL);
+        if (!ptr)
+                return ERR_PTR(-ENOMEM);
+
+        rstc = reset_control_get(dev, id);
+        if (!IS_ERR(rstc)) {
+                *ptr = rstc;
+                devres_add(dev, ptr);
+        } else {
+                devres_free(ptr);
+        }
+
+        return rstc;
+}
+EXPORT_SYMBOL_GPL(devm_reset_control_get);
+
+static int devm_reset_control_match(struct device *dev, void *res, void *data)
+{
+        struct reset_control **rstc = res;
+        if (WARN_ON(!rstc || !*rstc))
+                return 0;
+        return *rstc == data;
+}
+
+/**
+ * devm_reset_control_put - resource managed reset_control_put()
+ * @rstc: reset controller to free
+ *
+ * Deallocate a reset control allocated withd devm_reset_control_get().
+ * This function will not need to be called normally, as devres will take
+ * care of freeing the resource.
+ */
+void devm_reset_control_put(struct reset_control *rstc)
+{
+        int ret;
+
+        ret = devres_release(rstc->dev, devm_reset_control_release,
+                             devm_reset_control_match, rstc);
+        if (ret)
+                WARN_ON(ret);
+}
+EXPORT_SYMBOL_GPL(devm_reset_control_put);
+
+/**
+ * device_reset - find reset controller associated with the device
+ *                and perform reset
+ * @dev: device to be reset by the controller
+ *
+ * Convenience wrapper for reset_control_get() and reset_control_reset().
+ * This is useful for the common case of devices with single, dedicated reset
+ * lines.
+ */
+int device_reset(struct device *dev)
+{
+        struct reset_control *rstc;
+        int ret;
+
+        rstc = reset_control_get(dev, NULL);
+        if (IS_ERR(rstc))
+                return PTR_ERR(rstc);
+
+        ret = reset_control_reset(rstc);
+
+        reset_control_put(rstc);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(device_reset);
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 98348ec0b3ce..540909de6247 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -34,6 +34,77 @@
 #define ATMEL_LCDC_DMA_BURST_LEN        8       /* words */
 #define ATMEL_LCDC_FIFO_SIZE            512     /* words */
 
+struct atmel_lcdfb_config {
+        bool have_alt_pixclock;
+        bool have_hozval;
+        bool have_intensity_bit;
+};
+
+static struct atmel_lcdfb_config at91sam9261_config = {
+        .have_hozval            = true,
+        .have_intensity_bit     = true,
+};
+
+static struct atmel_lcdfb_config at91sam9263_config = {
+        .have_intensity_bit     = true,
+};
+
+static struct atmel_lcdfb_config at91sam9g10_config = {
+        .have_hozval            = true,
+};
+
+static struct atmel_lcdfb_config at91sam9g45_config = {
+        .have_alt_pixclock      = true,
+};
+
+static struct atmel_lcdfb_config at91sam9g45es_config = {
+};
+
+static struct atmel_lcdfb_config at91sam9rl_config = {
+        .have_intensity_bit     = true,
+};
+
+static struct atmel_lcdfb_config at32ap_config = {
+        .have_hozval            = true,
+};
+
+static const struct platform_device_id atmel_lcdfb_devtypes[] = {
+        {
+                .name = "at91sam9261-lcdfb",
+                .driver_data = (unsigned long)&at91sam9261_config,
+        }, {
+                .name = "at91sam9263-lcdfb",
+                .driver_data = (unsigned long)&at91sam9263_config,
+        }, {
+                .name = "at91sam9g10-lcdfb",
+                .driver_data = (unsigned long)&at91sam9g10_config,
+        }, {
+                .name = "at91sam9g45-lcdfb",
+                .driver_data = (unsigned long)&at91sam9g45_config,
+        }, {
+                .name = "at91sam9g45es-lcdfb",
+                .driver_data = (unsigned long)&at91sam9g45es_config,
+        }, {
+                .name = "at91sam9rl-lcdfb",
+                .driver_data = (unsigned long)&at91sam9rl_config,
+        }, {
+                .name = "at32ap-lcdfb",
+                .driver_data = (unsigned long)&at32ap_config,
+        }, {
+                /* terminator */
+        }
+};
+
+static struct atmel_lcdfb_config *
+atmel_lcdfb_get_config(struct platform_device *pdev)
+{
+        unsigned long data;
+
+        data = platform_get_device_id(pdev)->driver_data;
+
+        return (struct atmel_lcdfb_config *)data;
+}
+
 #if defined(CONFIG_ARCH_AT91)
 #define ATMEL_LCDFB_FBINFO_DEFAULT      (FBINFO_DEFAULT \
                                          | FBINFO_PARTIAL_PAN_OK \
@@ -193,14 +264,16 @@ static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
         .accel          = FB_ACCEL_NONE,
 };
 
-static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
+static unsigned long compute_hozval(struct atmel_lcdfb_info *sinfo,
+                                                        unsigned long xres)
 {
+        unsigned long lcdcon2;
         unsigned long value;
 
-        if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
-                || cpu_is_at32ap7000()))
+        if (!sinfo->config->have_hozval)
                 return xres;
 
+        lcdcon2 = lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2);
         value = xres;
         if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
                 /* STN display */
@@ -423,7 +496,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
                 break;
         case 16:
                 /* Older SOCs use IBGR:555 rather than BGR:565. */
-                if (sinfo->have_intensity_bit)
+                if (sinfo->config->have_intensity_bit)
                         var->green.length = 5;
                 else
                         var->green.length = 6;
@@ -531,7 +604,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
         /* Now, the LCDC core... */
 
         /* Set pixel clock */
-        if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
+        if (sinfo->config->have_alt_pixclock)
                 pix_factor = 1;
 
         clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
@@ -591,8 +664,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
         lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
 
         /* Horizontal value (aka line size) */
-        hozval_linesz = compute_hozval(info->var.xres,
-                                        lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
+        hozval_linesz = compute_hozval(sinfo, info->var.xres);
 
         /* Display size */
         value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
@@ -684,7 +756,7 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
 
         case FB_VISUAL_PSEUDOCOLOR:
                 if (regno < 256) {
-                        if (sinfo->have_intensity_bit) {
+                        if (sinfo->config->have_intensity_bit) {
                                 /* old style I+BGR:555 */
                                 val  = ((red   >> 11) & 0x001f);
                                 val |= ((green >>  6) & 0x03e0);
@@ -821,15 +893,13 @@ static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
 
 static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
 {
-        if (sinfo->bus_clk)
-                clk_enable(sinfo->bus_clk);
+        clk_enable(sinfo->bus_clk);
         clk_enable(sinfo->lcdc_clk);
 }
 
 static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
 {
-        if (sinfo->bus_clk)
-                clk_disable(sinfo->bus_clk);
+        clk_disable(sinfo->bus_clk);
         clk_disable(sinfo->lcdc_clk);
 }
 
@@ -874,10 +944,9 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
         }
         sinfo->info = info;
         sinfo->pdev = pdev;
-        if (cpu_is_at91sam9261() || cpu_is_at91sam9263() ||
-                                                        cpu_is_at91sam9rl()) {
-                sinfo->have_intensity_bit = true;
-        }
+        sinfo->config = atmel_lcdfb_get_config(pdev);
+        if (!sinfo->config)
+                goto free_info;
 
         strcpy(info->fix.id, sinfo->pdev->name);
         info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
@@ -888,13 +957,10 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
         info->fix = atmel_lcdfb_fix;
 
         /* Enable LCDC Clocks */
-        if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()
-         || cpu_is_at32ap7000()) {
-                sinfo->bus_clk = clk_get(dev, "hck1");
-                if (IS_ERR(sinfo->bus_clk)) {
-                        ret = PTR_ERR(sinfo->bus_clk);
-                        goto free_info;
-                }
+        sinfo->bus_clk = clk_get(dev, "hclk");
+        if (IS_ERR(sinfo->bus_clk)) {
+                ret = PTR_ERR(sinfo->bus_clk);
+                goto free_info;
         }
         sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
         if (IS_ERR(sinfo->lcdc_clk)) {
@@ -1055,8 +1121,7 @@ stop_clk:
         atmel_lcdfb_stop_clock(sinfo);
         clk_put(sinfo->lcdc_clk);
 put_bus_clk:
-        if (sinfo->bus_clk)
-                clk_put(sinfo->bus_clk);
+        clk_put(sinfo->bus_clk);
 free_info:
         framebuffer_release(info);
 out:
@@ -1081,8 +1146,7 @@ static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
         unregister_framebuffer(info);
         atmel_lcdfb_stop_clock(sinfo);
         clk_put(sinfo->lcdc_clk);
-        if (sinfo->bus_clk)
-                clk_put(sinfo->bus_clk);
+        clk_put(sinfo->bus_clk);
         fb_dealloc_cmap(&info->cmap);
         free_irq(sinfo->irq_base, info);
         iounmap(sinfo->mmio);
@@ -1151,7 +1215,7 @@ static struct platform_driver atmel_lcdfb_driver = {
         .remove         = __exit_p(atmel_lcdfb_remove),
         .suspend        = atmel_lcdfb_suspend,
         .resume         = atmel_lcdfb_resume,
-
+        .id_table       = atmel_lcdfb_devtypes,
         .driver         = {
                 .name   = "atmel_lcdfb",
                 .owner  = THIS_MODULE,
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 404d6f940872..642789baec74 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -123,5 +123,6 @@ static inline void tegra_cpu_clock_resume(void)
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 void tegra_clocks_init(void);
+void tegra_clocks_apply_init_table(void);
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/of.h b/include/linux/of.h
index 2d25ff8fe39a..fb2002f3c7dc 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -235,6 +235,9 @@ extern struct device_node *of_find_node_with_property(
 extern struct property *of_find_property(const struct device_node *np,
                                          const char *name,
                                          int *lenp);
+extern int of_property_read_u32_index(const struct device_node *np,
+                                       const char *propname,
+                                       u32 index, u32 *out_value);
 extern int of_property_read_u8_array(const struct device_node *np,
                         const char *propname, u8 *out_values, size_t sz);
 extern int of_property_read_u16_array(const struct device_node *np,
@@ -394,6 +397,12 @@ static inline struct device_node *of_find_compatible_node(
         return NULL;
 }
 
+static inline int of_property_read_u32_index(const struct device_node *np,
+                        const char *propname, u32 index, u32 *out_value)
+{
+        return -ENOSYS;
+}
+
 static inline int of_property_read_u8_array(const struct device_node *np,
                         const char *propname, u8 *out_values, size_t sz)
 {
diff --git a/include/linux/platform_data/irq-renesas-intc-irqpin.h b/include/linux/platform_data/irq-renesas-intc-irqpin.h
new file mode 100644
index 000000000000..e4cb911066a6
--- /dev/null
+++ b/include/linux/platform_data/irq-renesas-intc-irqpin.h
@@ -0,0 +1,29 @@
+/*
+ * Renesas INTC External IRQ Pin Driver
+ *
+ *  Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __IRQ_RENESAS_INTC_IRQPIN_H__
+#define __IRQ_RENESAS_INTC_IRQPIN_H__
+
+struct renesas_intc_irqpin_config {
+        unsigned int sense_bitfield_width;
+        unsigned int irq_base;
+        bool control_parent;
+};
+
+#endif /* __IRQ_RENESAS_INTC_IRQPIN_H__ */
diff --git a/include/linux/platform_data/irq-renesas-irqc.h b/include/linux/platform_data/irq-renesas-irqc.h
new file mode 100644
index 000000000000..3ae17b3e00ed
--- /dev/null
+++ b/include/linux/platform_data/irq-renesas-irqc.h
@@ -0,0 +1,27 @@
+/*
+ * Renesas IRQC Driver
+ *
+ *  Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __IRQ_RENESAS_IRQC_H__
+#define __IRQ_RENESAS_IRQC_H__
+
+struct renesas_irqc_config {
+        unsigned int irq_base;
+};
+
+#endif /* __IRQ_RENESAS_IRQC_H__ */
diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h
new file mode 100644
index 000000000000..2f61311ae3e0
--- /dev/null
+++ b/include/linux/reset-controller.h
@@ -0,0 +1,51 @@
+#ifndef _LINUX_RESET_CONTROLLER_H_
+#define _LINUX_RESET_CONTROLLER_H_
+
+#include <linux/list.h>
+
+struct reset_controller_dev;
+
+/**
+ * struct reset_control_ops
+ *
+ * @reset: for self-deasserting resets, does all necessary
+ *         things to reset the device
+ * @assert: manually assert the reset line, if supported
+ * @deassert: manually deassert the reset line, if supported
+ */
+struct reset_control_ops {
+        int (*reset)(struct reset_controller_dev *rcdev, unsigned long id);
+        int (*assert)(struct reset_controller_dev *rcdev, unsigned long id);
+        int (*deassert)(struct reset_controller_dev *rcdev, unsigned long id);
+};
+
+struct module;
+struct device_node;
+
+/**
+ * struct reset_controller_dev - reset controller entity that might
+ *                               provide multiple reset controls
+ * @ops: a pointer to device specific struct reset_control_ops
+ * @owner: kernel module of the reset controller driver
+ * @list: internal list of reset controller devices
+ * @of_node: corresponding device tree node as phandle target
+ * @of_reset_n_cells: number of cells in reset line specifiers
+ * @of_xlate: translation function to translate from specifier as found in the
+ *            device tree to id as given to the reset control ops
+ * @nr_resets: number of reset controls in this reset controller device
+ */
+struct reset_controller_dev {
+        struct reset_control_ops *ops;
+        struct module *owner;
+        struct list_head list;
+        struct device_node *of_node;
+        int of_reset_n_cells;
+        int (*of_xlate)(struct reset_controller_dev *rcdev,
+                        const struct of_phandle_args *reset_spec);
+        unsigned int nr_resets;
+};
+
+int reset_controller_register(struct reset_controller_dev *rcdev);
+void reset_controller_unregister(struct reset_controller_dev *rcdev);
+
+#endif
diff --git a/include/linux/reset.h b/include/linux/reset.h
new file mode 100644
index 000000000000..6082247feab1
--- /dev/null
+++ b/include/linux/reset.h
@@ -0,0 +1,17 @@
+#ifndef _LINUX_RESET_H_
+#define _LINUX_RESET_H_
+
+struct device;
+struct reset_control;
+
+int reset_control_reset(struct reset_control *rstc);
+int reset_control_assert(struct reset_control *rstc);
+int reset_control_deassert(struct reset_control *rstc);
+
+struct reset_control *reset_control_get(struct device *dev, const char *id);
+void reset_control_put(struct reset_control *rstc);
+struct reset_control *devm_reset_control_get(struct device *dev, const char *id);
+
+int device_reset(struct device *dev);
+
+#endif
diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
index 8deb22672ada..0f5a2fc69af9 100644
--- a/include/video/atmel_lcdc.h
+++ b/include/video/atmel_lcdc.h
@@ -31,6 +31,7 @@
 #define ATMEL_LCDC_WIRING_BGR   0
 #define ATMEL_LCDC_WIRING_RGB   1
 
+struct atmel_lcdfb_config;
 
  /* LCD Controller info data structure, stored in device platform_data */
 struct atmel_lcdfb_info {
@@ -61,7 +62,8 @@ struct atmel_lcdfb_info {
         void (*atmel_lcdfb_power_control)(int on);
         struct fb_monspecs      *default_monspecs;
         u32                     pseudo_palette[16];
-        bool                    have_intensity_bit;
+
+        struct atmel_lcdfb_config *config;
 };
 
 #define ATMEL_LCDC_DMABADDR1    0x00