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-rw-r--r--Documentation/blackfin/bfin-spi-notes.txt2
-rw-r--r--arch/blackfin/Kconfig10
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig8
-rw-r--r--arch/blackfin/include/asm/Kbuild43
-rw-r--r--arch/blackfin/include/asm/atomic.h13
-rw-r--r--arch/blackfin/include/asm/auxvec.h1
-rw-r--r--arch/blackfin/include/asm/bitsperlong.h1
-rw-r--r--arch/blackfin/include/asm/blackfin.h6
-rw-r--r--arch/blackfin/include/asm/bugs.h1
-rw-r--r--arch/blackfin/include/asm/cputime.h1
-rw-r--r--arch/blackfin/include/asm/current.h1
-rw-r--r--arch/blackfin/include/asm/device.h1
-rw-r--r--arch/blackfin/include/asm/div64.h1
-rw-r--r--arch/blackfin/include/asm/dpmc.h27
-rw-r--r--arch/blackfin/include/asm/emergency-restart.h1
-rw-r--r--arch/blackfin/include/asm/errno.h1
-rw-r--r--arch/blackfin/include/asm/fb.h1
-rw-r--r--arch/blackfin/include/asm/futex.h1
-rw-r--r--arch/blackfin/include/asm/gpio.h64
-rw-r--r--arch/blackfin/include/asm/gptimers.h19
-rw-r--r--arch/blackfin/include/asm/hw_irq.h1
-rw-r--r--arch/blackfin/include/asm/ioctl.h1
-rw-r--r--arch/blackfin/include/asm/ipcbuf.h1
-rw-r--r--arch/blackfin/include/asm/irq_regs.h1
-rw-r--r--arch/blackfin/include/asm/irqflags.h42
-rw-r--r--arch/blackfin/include/asm/kdebug.h1
-rw-r--r--arch/blackfin/include/asm/kmap_types.h1
-rw-r--r--arch/blackfin/include/asm/local.h1
-rw-r--r--arch/blackfin/include/asm/local64.h1
-rw-r--r--arch/blackfin/include/asm/mman.h1
-rw-r--r--arch/blackfin/include/asm/module.h8
-rw-r--r--arch/blackfin/include/asm/msgbuf.h1
-rw-r--r--arch/blackfin/include/asm/mutex.h77
-rw-r--r--arch/blackfin/include/asm/page.h8
-rw-r--r--arch/blackfin/include/asm/param.h1
-rw-r--r--arch/blackfin/include/asm/pda.h10
-rw-r--r--arch/blackfin/include/asm/percpu.h1
-rw-r--r--arch/blackfin/include/asm/pgalloc.h1
-rw-r--r--arch/blackfin/include/asm/resource.h1
-rw-r--r--arch/blackfin/include/asm/scatterlist.h6
-rw-r--r--arch/blackfin/include/asm/sections.h8
-rw-r--r--arch/blackfin/include/asm/sembuf.h1
-rw-r--r--arch/blackfin/include/asm/serial.h1
-rw-r--r--arch/blackfin/include/asm/setup.h1
-rw-r--r--arch/blackfin/include/asm/shmbuf.h1
-rw-r--r--arch/blackfin/include/asm/shmparam.h1
-rw-r--r--arch/blackfin/include/asm/sigcontext.h8
-rw-r--r--arch/blackfin/include/asm/socket.h1
-rw-r--r--arch/blackfin/include/asm/sockios.h1
-rw-r--r--arch/blackfin/include/asm/spinlock.h8
-rw-r--r--arch/blackfin/include/asm/statfs.h1
-rw-r--r--arch/blackfin/include/asm/termbits.h1
-rw-r--r--arch/blackfin/include/asm/termios.h1
-rw-r--r--arch/blackfin/include/asm/topology.h1
-rw-r--r--arch/blackfin/include/asm/types.h1
-rw-r--r--arch/blackfin/include/asm/ucontext.h1
-rw-r--r--arch/blackfin/include/asm/unaligned.h1
-rw-r--r--arch/blackfin/include/asm/user.h1
-rw-r--r--arch/blackfin/include/asm/xor.h1
-rw-r--r--arch/blackfin/kernel/Makefile1
-rw-r--r--arch/blackfin/kernel/asm-offsets.c10
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c26
-rw-r--r--arch/blackfin/kernel/debug-mmrs.c109
-rw-r--r--arch/blackfin/kernel/gptimers.c93
-rw-r--r--arch/blackfin/kernel/process.c1
-rw-r--r--arch/blackfin/kernel/pwm.c100
-rw-r--r--arch/blackfin/kernel/reboot.c4
-rw-r--r--arch/blackfin/kernel/setup.c16
-rw-r--r--arch/blackfin/kernel/time.c4
-rw-r--r--arch/blackfin/kernel/vmlinux.lds.S1
-rw-r--r--arch/blackfin/mach-bf518/Kconfig78
-rw-r--r--arch/blackfin/mach-bf518/boards/ezbrd.c59
-rw-r--r--arch/blackfin/mach-bf518/boards/tcm-bf518.c47
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h24
-rw-r--r--arch/blackfin/mach-bf518/include/mach/portmux.h54
-rw-r--r--arch/blackfin/mach-bf527/boards/ad7160eval.c19
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c55
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c62
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c98
-rw-r--r--arch/blackfin/mach-bf527/boards/tll6527m.c70
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h34
-rw-r--r--arch/blackfin/mach-bf533/boards/H8606.c28
-rw-r--r--arch/blackfin/mach-bf533/boards/blackstamp.c10
-rw-r--r--arch/blackfin/mach-bf533/boards/cm_bf533.c29
-rw-r--r--arch/blackfin/mach-bf533/boards/ezkit.c36
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c1
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c78
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h19
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537e.c51
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537u.c63
-rw-r--r--arch/blackfin/mach-bf537/boards/dnp5370.c2
-rw-r--r--arch/blackfin/mach-bf537/boards/minotaur.c2
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c38
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c176
-rw-r--r--arch/blackfin/mach-bf537/boards/tcm_bf537.c51
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h34
-rw-r--r--arch/blackfin/mach-bf538/boards/ezkit.c25
-rw-r--r--arch/blackfin/mach-bf538/ext-gpio.c37
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h38
-rw-r--r--arch/blackfin/mach-bf538/include/mach/gpio.h3
-rw-r--r--arch/blackfin/mach-bf548/boards/cm_bf548.c15
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c32
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h220
-rw-r--r--arch/blackfin/mach-bf548/include/mach/gpio.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf561/boards/acvilon.c9
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c58
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c41
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h132
-rw-r--r--arch/blackfin/mach-bf561/include/mach/gpio.h6
-rw-r--r--arch/blackfin/mach-bf561/secondary.S152
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S1016
-rw-r--r--arch/blackfin/mach-common/head.S36
-rw-r--r--arch/blackfin/mach-common/ints-priority.c41
-rw-r--r--arch/blackfin/mach-common/smp.c17
115 files changed, 1735 insertions, 2138 deletions
diff --git a/Documentation/blackfin/bfin-spi-notes.txt b/Documentation/blackfin/bfin-spi-notes.txt
index 556fa877f2e8..eae6eaf2a09d 100644
--- a/Documentation/blackfin/bfin-spi-notes.txt
+++ b/Documentation/blackfin/bfin-spi-notes.txt
@@ -9,6 +9,8 @@ the entire SPI transfer. - And not just bits_per_word duration.
9In most cases you can utilize SPI MODE_3 instead of MODE_0 to work-around this 9In most cases you can utilize SPI MODE_3 instead of MODE_0 to work-around this
10behavior. If your SPI slave device in question requires SPI MODE_0 or MODE_2 10behavior. If your SPI slave device in question requires SPI MODE_0 or MODE_2
11timing, you can utilize the GPIO controlled SPI Slave Select option instead. 11timing, you can utilize the GPIO controlled SPI Slave Select option instead.
12In this case, you should use GPIO based CS for all of your slaves and not just
13the ones using mode 0 or 2 in order to guarantee correct CS toggling behavior.
12 14
13You can even use the same pin whose peripheral role is a SSEL, 15You can even use the same pin whose peripheral role is a SSEL,
14but use it as a GPIO instead. 16but use it as a GPIO instead.
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index d619b17c4413..c7476295de80 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -953,6 +953,16 @@ config BFIN_GPTIMERS
953 To compile this driver as a module, choose M here: the module 953 To compile this driver as a module, choose M here: the module
954 will be called gptimers. 954 will be called gptimers.
955 955
956config HAVE_PWM
957 tristate "Enable PWM API support"
958 depends on BFIN_GPTIMERS
959 help
960 Enable support for the Pulse Width Modulation framework (as
961 found in linux/pwm.h).
962
963 To compile this driver as a module, choose M here: the module
964 will be called pwm.
965
956choice 966choice
957 prompt "Uncached DMA region" 967 prompt "Uncached DMA region"
958 default DMA_UNCACHED_1M 968 default DMA_UNCACHED_1M
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 1c0a82a10591..d7ff2aee3fbc 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -58,13 +58,13 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
58CONFIG_MTD=y 58CONFIG_MTD=y
59CONFIG_MTD_PARTITIONS=y 59CONFIG_MTD_PARTITIONS=y
60CONFIG_MTD_CMDLINE_PARTS=y 60CONFIG_MTD_CMDLINE_PARTS=y
61CONFIG_MTD_CHAR=m 61CONFIG_MTD_CHAR=y
62CONFIG_MTD_BLOCK=y 62CONFIG_MTD_BLOCK=y
63CONFIG_MTD_CFI=m 63CONFIG_MTD_CFI=y
64CONFIG_MTD_CFI_AMDSTD=m 64CONFIG_MTD_CFI_AMDSTD=y
65CONFIG_MTD_RAM=y 65CONFIG_MTD_RAM=y
66CONFIG_MTD_ROM=m 66CONFIG_MTD_ROM=m
67CONFIG_MTD_PHYSMAP=m 67CONFIG_MTD_PHYSMAP=y
68CONFIG_BLK_DEV_RAM=y 68CONFIG_BLK_DEV_RAM=y
69CONFIG_NETDEVICES=y 69CONFIG_NETDEVICES=y
70CONFIG_NET_ETHERNET=y 70CONFIG_NET_ETHERNET=y
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index 9e7c5379d3ff..7a075eaf6041 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -1,5 +1,48 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3generic-y += auxvec.h
4generic-y += bitsperlong.h
5generic-y += bugs.h
6generic-y += cputime.h
7generic-y += current.h
8generic-y += device.h
9generic-y += div64.h
10generic-y += emergency-restart.h
11generic-y += errno.h
12generic-y += fb.h
13generic-y += futex.h
14generic-y += hw_irq.h
15generic-y += ioctl.h
16generic-y += ipcbuf.h
17generic-y += irq_regs.h
18generic-y += kdebug.h
19generic-y += kmap_types.h
20generic-y += local64.h
21generic-y += local.h
22generic-y += mman.h
23generic-y += msgbuf.h
24generic-y += param.h
25generic-y += percpu.h
26generic-y += pgalloc.h
27generic-y += resource.h
28generic-y += scatterlist.h
29generic-y += sembuf.h
30generic-y += serial.h
31generic-y += setup.h
32generic-y += shmbuf.h
33generic-y += shmparam.h
34generic-y += socket.h
35generic-y += sockios.h
36generic-y += statfs.h
37generic-y += termbits.h
38generic-y += termios.h
39generic-y += topology.h
40generic-y += types.h
41generic-y += ucontext.h
42generic-y += unaligned.h
43generic-y += user.h
44generic-y += xor.h
45
3header-y += bfin_sport.h 46header-y += bfin_sport.h
4header-y += cachectl.h 47header-y += cachectl.h
5header-y += fixed_code.h 48header-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
index e48508957160..4c707dbe1ff9 100644
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef __ARCH_BLACKFIN_ATOMIC__ 7#ifndef __ARCH_BLACKFIN_ATOMIC__
8#define __ARCH_BLACKFIN_ATOMIC__ 8#define __ARCH_BLACKFIN_ATOMIC__
@@ -76,11 +76,6 @@ static inline void atomic_set_mask(int mask, atomic_t *v)
76 __raw_atomic_set_asm(&v->counter, mask); 76 __raw_atomic_set_asm(&v->counter, mask);
77} 77}
78 78
79static inline int atomic_test_mask(int mask, atomic_t *v)
80{
81 return __raw_atomic_test_asm(&v->counter, mask);
82}
83
84/* Atomic operations are already serializing */ 79/* Atomic operations are already serializing */
85#define smp_mb__before_atomic_dec() barrier() 80#define smp_mb__before_atomic_dec() barrier()
86#define smp_mb__after_atomic_dec() barrier() 81#define smp_mb__after_atomic_dec() barrier()
diff --git a/arch/blackfin/include/asm/auxvec.h b/arch/blackfin/include/asm/auxvec.h
deleted file mode 100644
index 41fa68b71287..000000000000
--- a/arch/blackfin/include/asm/auxvec.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/auxvec.h>
diff --git a/arch/blackfin/include/asm/bitsperlong.h b/arch/blackfin/include/asm/bitsperlong.h
deleted file mode 100644
index 6dc0bb0c13b2..000000000000
--- a/arch/blackfin/include/asm/bitsperlong.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/bitsperlong.h>
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
index eb7c1441d8f9..0928700b6bc4 100644
--- a/arch/blackfin/include/asm/blackfin.h
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * Common header file for Blackfin family of processors. 2 * Common header file for Blackfin family of processors.
3 * 3 *
4 * Copyright 2004-2009 Analog Devices Inc. 4 * Copyright 2004-2009 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9#ifndef _BLACKFIN_H_ 9#ifndef _BLACKFIN_H_
diff --git a/arch/blackfin/include/asm/bugs.h b/arch/blackfin/include/asm/bugs.h
deleted file mode 100644
index 61791e1ad9f5..000000000000
--- a/arch/blackfin/include/asm/bugs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/bugs.h>
diff --git a/arch/blackfin/include/asm/cputime.h b/arch/blackfin/include/asm/cputime.h
deleted file mode 100644
index 6d68ad7e0ea3..000000000000
--- a/arch/blackfin/include/asm/cputime.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/cputime.h>
diff --git a/arch/blackfin/include/asm/current.h b/arch/blackfin/include/asm/current.h
deleted file mode 100644
index 4c51401b5537..000000000000
--- a/arch/blackfin/include/asm/current.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/current.h>
diff --git a/arch/blackfin/include/asm/device.h b/arch/blackfin/include/asm/device.h
deleted file mode 100644
index f0a4c256403b..000000000000
--- a/arch/blackfin/include/asm/device.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/device.h>
diff --git a/arch/blackfin/include/asm/div64.h b/arch/blackfin/include/asm/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/arch/blackfin/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/div64.h>
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index edf2a2ad5183..c4ec959dad78 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -117,7 +117,6 @@
117#ifndef __ASSEMBLY__ 117#ifndef __ASSEMBLY__
118 118
119void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 119void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
120void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
121void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 120void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
122void do_hibernate(int wakeup); 121void do_hibernate(int wakeup);
123void set_dram_srfs(void); 122void set_dram_srfs(void);
@@ -134,32 +133,6 @@ struct bfin_dpmc_platform_data {
134 unsigned short vr_settling_time; /* in us */ 133 unsigned short vr_settling_time; /* in us */
135}; 134};
136 135
137#else
138
139#define PM_PUSH(x) \
140 R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
141 [--SP] = R0;\
142
143#define PM_POP(x) \
144 R0 = [SP++];\
145 [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
146
147#define PM_SYS_PUSH(x) \
148 R0 = [P0 + (x - PLL_CTL)];\
149 [--SP] = R0;\
150
151#define PM_SYS_POP(x) \
152 R0 = [SP++];\
153 [P0 + (x - PLL_CTL)] = R0;\
154
155#define PM_SYS_PUSH16(x) \
156 R0 = w[P0 + (x - PLL_CTL)];\
157 [--SP] = R0;\
158
159#define PM_SYS_POP16(x) \
160 R0 = [SP++];\
161 w[P0 + (x - PLL_CTL)] = R0;\
162
163#endif 136#endif
164 137
165#endif /*_BLACKFIN_DPMC_H_*/ 138#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/emergency-restart.h b/arch/blackfin/include/asm/emergency-restart.h
deleted file mode 100644
index 3711bd9d50bd..000000000000
--- a/arch/blackfin/include/asm/emergency-restart.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/emergency-restart.h>
diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h
deleted file mode 100644
index 4c82b503d92f..000000000000
--- a/arch/blackfin/include/asm/errno.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/errno.h>
diff --git a/arch/blackfin/include/asm/fb.h b/arch/blackfin/include/asm/fb.h
deleted file mode 100644
index 3a4988e8df45..000000000000
--- a/arch/blackfin/include/asm/fb.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/fb.h>
diff --git a/arch/blackfin/include/asm/futex.h b/arch/blackfin/include/asm/futex.h
deleted file mode 100644
index 0b745828f42b..000000000000
--- a/arch/blackfin/include/asm/futex.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/futex.h>
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 1ef8417f5d27..5a25856381ff 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -16,58 +16,13 @@
16 16
17#include <mach/gpio.h> 17#include <mach/gpio.h>
18 18
19#define GPIO_0 0
20#define GPIO_1 1
21#define GPIO_2 2
22#define GPIO_3 3
23#define GPIO_4 4
24#define GPIO_5 5
25#define GPIO_6 6
26#define GPIO_7 7
27#define GPIO_8 8
28#define GPIO_9 9
29#define GPIO_10 10
30#define GPIO_11 11
31#define GPIO_12 12
32#define GPIO_13 13
33#define GPIO_14 14
34#define GPIO_15 15
35#define GPIO_16 16
36#define GPIO_17 17
37#define GPIO_18 18
38#define GPIO_19 19
39#define GPIO_20 20
40#define GPIO_21 21
41#define GPIO_22 22
42#define GPIO_23 23
43#define GPIO_24 24
44#define GPIO_25 25
45#define GPIO_26 26
46#define GPIO_27 27
47#define GPIO_28 28
48#define GPIO_29 29
49#define GPIO_30 30
50#define GPIO_31 31
51#define GPIO_32 32
52#define GPIO_33 33
53#define GPIO_34 34
54#define GPIO_35 35
55#define GPIO_36 36
56#define GPIO_37 37
57#define GPIO_38 38
58#define GPIO_39 39
59#define GPIO_40 40
60#define GPIO_41 41
61#define GPIO_42 42
62#define GPIO_43 43
63#define GPIO_44 44
64#define GPIO_45 45
65#define GPIO_46 46
66#define GPIO_47 47
67
68#define PERIPHERAL_USAGE 1 19#define PERIPHERAL_USAGE 1
69#define GPIO_USAGE 0 20#define GPIO_USAGE 0
70 21
22#ifndef BFIN_GPIO_PINT
23# define BFIN_GPIO_PINT 0
24#endif
25
71#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
72 27
73#include <linux/compiler.h> 28#include <linux/compiler.h>
@@ -89,7 +44,7 @@
89* MODIFICATION HISTORY : 44* MODIFICATION HISTORY :
90**************************************************************/ 45**************************************************************/
91 46
92#ifndef CONFIG_BF54x 47#if !BFIN_GPIO_PINT
93void set_gpio_dir(unsigned, unsigned short); 48void set_gpio_dir(unsigned, unsigned short);
94void set_gpio_inen(unsigned, unsigned short); 49void set_gpio_inen(unsigned, unsigned short);
95void set_gpio_polar(unsigned, unsigned short); 50void set_gpio_polar(unsigned, unsigned short);
@@ -164,6 +119,10 @@ struct gpio_port_t {
164#ifdef BFIN_SPECIAL_GPIO_BANKS 119#ifdef BFIN_SPECIAL_GPIO_BANKS
165void bfin_special_gpio_free(unsigned gpio); 120void bfin_special_gpio_free(unsigned gpio);
166int bfin_special_gpio_request(unsigned gpio, const char *label); 121int bfin_special_gpio_request(unsigned gpio, const char *label);
122# ifdef CONFIG_PM
123void bfin_special_gpio_pm_hibernate_restore(void);
124void bfin_special_gpio_pm_hibernate_suspend(void);
125# endif
167#endif 126#endif
168 127
169#ifdef CONFIG_PM 128#ifdef CONFIG_PM
@@ -182,7 +141,7 @@ static inline void bfin_pm_standby_restore(void)
182void bfin_gpio_pm_hibernate_restore(void); 141void bfin_gpio_pm_hibernate_restore(void);
183void bfin_gpio_pm_hibernate_suspend(void); 142void bfin_gpio_pm_hibernate_suspend(void);
184 143
185#ifndef CONFIG_BF54x 144# if !BFIN_GPIO_PINT
186int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl); 145int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
187 146
188struct gpio_port_s { 147struct gpio_port_s {
@@ -199,8 +158,9 @@ struct gpio_port_s {
199 unsigned short reserved; 158 unsigned short reserved;
200 unsigned short mux; 159 unsigned short mux;
201}; 160};
202#endif /*CONFIG_BF54x*/ 161# endif
203#endif /*CONFIG_PM*/ 162#endif /*CONFIG_PM*/
163
204/*********************************************************** 164/***********************************************************
205* 165*
206* FUNCTIONS: Blackfin GPIO Driver 166* FUNCTIONS: Blackfin GPIO Driver
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index 38657dac1235..38bddcb190c8 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -193,6 +193,16 @@ uint16_t get_enabled_gptimers(void);
193uint32_t get_gptimer_status(unsigned int group); 193uint32_t get_gptimer_status(unsigned int group);
194void set_gptimer_status(unsigned int group, uint32_t value); 194void set_gptimer_status(unsigned int group, uint32_t value);
195 195
196static inline void enable_gptimer(unsigned int timer_id)
197{
198 enable_gptimers(1 << timer_id);
199}
200
201static inline void disable_gptimer(unsigned int timer_id)
202{
203 disable_gptimers(1 << timer_id);
204}
205
196/* 206/*
197 * All Blackfin system MMRs are padded to 32bits even if the register 207 * All Blackfin system MMRs are padded to 32bits even if the register
198 * itself is only 16bits. So use a helper macro to streamline this. 208 * itself is only 16bits. So use a helper macro to streamline this.
@@ -209,6 +219,15 @@ struct bfin_gptimer_regs {
209 u32 width; 219 u32 width;
210}; 220};
211 221
222/*
223 * bfin group timer registers layout
224 */
225struct bfin_gptimer_group_regs {
226 __BFP(enable);
227 __BFP(disable);
228 u32 status;
229};
230
212#undef __BFP 231#undef __BFP
213 232
214#endif 233#endif
diff --git a/arch/blackfin/include/asm/hw_irq.h b/arch/blackfin/include/asm/hw_irq.h
deleted file mode 100644
index 1f5ef7da0045..000000000000
--- a/arch/blackfin/include/asm/hw_irq.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/hw_irq.h>
diff --git a/arch/blackfin/include/asm/ioctl.h b/arch/blackfin/include/asm/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/arch/blackfin/include/asm/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ioctl.h>
diff --git a/arch/blackfin/include/asm/ipcbuf.h b/arch/blackfin/include/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51cb6d0..000000000000
--- a/arch/blackfin/include/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ipcbuf.h>
diff --git a/arch/blackfin/include/asm/irq_regs.h b/arch/blackfin/include/asm/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/arch/blackfin/include/asm/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/irq_regs.h>
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index b4bbb75a9e15..43eb4749de3d 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -18,12 +18,12 @@
18extern unsigned long bfin_irq_flags; 18extern unsigned long bfin_irq_flags;
19#endif 19#endif
20 20
21static inline void bfin_sti(unsigned long flags) 21static inline notrace void bfin_sti(unsigned long flags)
22{ 22{
23 asm volatile("sti %0;" : : "d" (flags)); 23 asm volatile("sti %0;" : : "d" (flags));
24} 24}
25 25
26static inline unsigned long bfin_cli(void) 26static inline notrace unsigned long bfin_cli(void)
27{ 27{
28 unsigned long flags; 28 unsigned long flags;
29 asm volatile("cli %0;" : "=d" (flags)); 29 asm volatile("cli %0;" : "=d" (flags));
@@ -40,22 +40,22 @@ static inline unsigned long bfin_cli(void)
40/* 40/*
41 * Hard, untraced CPU interrupt flag manipulation and access. 41 * Hard, untraced CPU interrupt flag manipulation and access.
42 */ 42 */
43static inline void __hard_local_irq_disable(void) 43static inline notrace void __hard_local_irq_disable(void)
44{ 44{
45 bfin_cli(); 45 bfin_cli();
46} 46}
47 47
48static inline void __hard_local_irq_enable(void) 48static inline notrace void __hard_local_irq_enable(void)
49{ 49{
50 bfin_sti(bfin_irq_flags); 50 bfin_sti(bfin_irq_flags);
51} 51}
52 52
53static inline unsigned long hard_local_save_flags(void) 53static inline notrace unsigned long hard_local_save_flags(void)
54{ 54{
55 return bfin_read_IMASK(); 55 return bfin_read_IMASK();
56} 56}
57 57
58static inline unsigned long __hard_local_irq_save(void) 58static inline notrace unsigned long __hard_local_irq_save(void)
59{ 59{
60 unsigned long flags; 60 unsigned long flags;
61 flags = bfin_cli(); 61 flags = bfin_cli();
@@ -65,18 +65,18 @@ static inline unsigned long __hard_local_irq_save(void)
65 return flags; 65 return flags;
66} 66}
67 67
68static inline int hard_irqs_disabled_flags(unsigned long flags) 68static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
69{ 69{
70 return (flags & ~0x3f) == 0; 70 return (flags & ~0x3f) == 0;
71} 71}
72 72
73static inline int hard_irqs_disabled(void) 73static inline notrace int hard_irqs_disabled(void)
74{ 74{
75 unsigned long flags = hard_local_save_flags(); 75 unsigned long flags = hard_local_save_flags();
76 return hard_irqs_disabled_flags(flags); 76 return hard_irqs_disabled_flags(flags);
77} 77}
78 78
79static inline void __hard_local_irq_restore(unsigned long flags) 79static inline notrace void __hard_local_irq_restore(unsigned long flags)
80{ 80{
81 if (!hard_irqs_disabled_flags(flags)) 81 if (!hard_irqs_disabled_flags(flags))
82 __hard_local_irq_enable(); 82 __hard_local_irq_enable();
@@ -113,31 +113,31 @@ void ipipe_check_context(struct ipipe_domain *ipd);
113/* 113/*
114 * Interrupt pipe interface to linux/irqflags.h. 114 * Interrupt pipe interface to linux/irqflags.h.
115 */ 115 */
116static inline void arch_local_irq_disable(void) 116static inline notrace void arch_local_irq_disable(void)
117{ 117{
118 __check_irqop_context(); 118 __check_irqop_context();
119 __ipipe_stall_root(); 119 __ipipe_stall_root();
120 barrier(); 120 barrier();
121} 121}
122 122
123static inline void arch_local_irq_enable(void) 123static inline notrace void arch_local_irq_enable(void)
124{ 124{
125 barrier(); 125 barrier();
126 __check_irqop_context(); 126 __check_irqop_context();
127 __ipipe_unstall_root(); 127 __ipipe_unstall_root();
128} 128}
129 129
130static inline unsigned long arch_local_save_flags(void) 130static inline notrace unsigned long arch_local_save_flags(void)
131{ 131{
132 return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; 132 return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
133} 133}
134 134
135static inline int arch_irqs_disabled_flags(unsigned long flags) 135static inline notrace int arch_irqs_disabled_flags(unsigned long flags)
136{ 136{
137 return flags == bfin_no_irqs; 137 return flags == bfin_no_irqs;
138} 138}
139 139
140static inline unsigned long arch_local_irq_save(void) 140static inline notrace unsigned long arch_local_irq_save(void)
141{ 141{
142 unsigned long flags; 142 unsigned long flags;
143 143
@@ -148,13 +148,13 @@ static inline unsigned long arch_local_irq_save(void)
148 return flags; 148 return flags;
149} 149}
150 150
151static inline void arch_local_irq_restore(unsigned long flags) 151static inline notrace void arch_local_irq_restore(unsigned long flags)
152{ 152{
153 __check_irqop_context(); 153 __check_irqop_context();
154 __ipipe_restore_root(flags == bfin_no_irqs); 154 __ipipe_restore_root(flags == bfin_no_irqs);
155} 155}
156 156
157static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real) 157static inline notrace unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
158{ 158{
159 /* 159 /*
160 * Merge virtual and real interrupt mask bits into a single 160 * Merge virtual and real interrupt mask bits into a single
@@ -163,7 +163,7 @@ static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
163 return (real & ~(1 << 31)) | ((virt != 0) << 31); 163 return (real & ~(1 << 31)) | ((virt != 0) << 31);
164} 164}
165 165
166static inline int arch_demangle_irq_bits(unsigned long *x) 166static inline notrace int arch_demangle_irq_bits(unsigned long *x)
167{ 167{
168 int virt = (*x & (1 << 31)) != 0; 168 int virt = (*x & (1 << 31)) != 0;
169 *x &= ~(1L << 31); 169 *x &= ~(1L << 31);
@@ -174,7 +174,7 @@ static inline int arch_demangle_irq_bits(unsigned long *x)
174 * Interface to various arch routines that may be traced. 174 * Interface to various arch routines that may be traced.
175 */ 175 */
176#ifdef CONFIG_IPIPE_TRACE_IRQSOFF 176#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
177static inline void hard_local_irq_disable(void) 177static inline notrace void hard_local_irq_disable(void)
178{ 178{
179 if (!hard_irqs_disabled()) { 179 if (!hard_irqs_disabled()) {
180 __hard_local_irq_disable(); 180 __hard_local_irq_disable();
@@ -182,7 +182,7 @@ static inline void hard_local_irq_disable(void)
182 } 182 }
183} 183}
184 184
185static inline void hard_local_irq_enable(void) 185static inline notrace void hard_local_irq_enable(void)
186{ 186{
187 if (hard_irqs_disabled()) { 187 if (hard_irqs_disabled()) {
188 ipipe_trace_end(0x80000000); 188 ipipe_trace_end(0x80000000);
@@ -190,7 +190,7 @@ static inline void hard_local_irq_enable(void)
190 } 190 }
191} 191}
192 192
193static inline unsigned long hard_local_irq_save(void) 193static inline notrace unsigned long hard_local_irq_save(void)
194{ 194{
195 unsigned long flags = hard_local_save_flags(); 195 unsigned long flags = hard_local_save_flags();
196 if (!hard_irqs_disabled_flags(flags)) { 196 if (!hard_irqs_disabled_flags(flags)) {
@@ -200,7 +200,7 @@ static inline unsigned long hard_local_irq_save(void)
200 return flags; 200 return flags;
201} 201}
202 202
203static inline void hard_local_irq_restore(unsigned long flags) 203static inline notrace void hard_local_irq_restore(unsigned long flags)
204{ 204{
205 if (!hard_irqs_disabled_flags(flags)) { 205 if (!hard_irqs_disabled_flags(flags)) {
206 ipipe_trace_end(0x80000001); 206 ipipe_trace_end(0x80000001);
diff --git a/arch/blackfin/include/asm/kdebug.h b/arch/blackfin/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/blackfin/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/kdebug.h>
diff --git a/arch/blackfin/include/asm/kmap_types.h b/arch/blackfin/include/asm/kmap_types.h
deleted file mode 100644
index 3575c64af42a..000000000000
--- a/arch/blackfin/include/asm/kmap_types.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/kmap_types.h>
diff --git a/arch/blackfin/include/asm/local.h b/arch/blackfin/include/asm/local.h
deleted file mode 100644
index c11c530f74d0..000000000000
--- a/arch/blackfin/include/asm/local.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/local.h>
diff --git a/arch/blackfin/include/asm/local64.h b/arch/blackfin/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/blackfin/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/local64.h>
diff --git a/arch/blackfin/include/asm/mman.h b/arch/blackfin/include/asm/mman.h
deleted file mode 100644
index 8eebf89f5ab1..000000000000
--- a/arch/blackfin/include/asm/mman.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/mman.h>
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
index 4282b169ead9..ed5689b82c9f 100644
--- a/arch/blackfin/include/asm/module.h
+++ b/arch/blackfin/include/asm/module.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright 2004-2008 Analog Devices Inc. 2 * Copyright 2004-2008 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _ASM_BFIN_MODULE_H 7#ifndef _ASM_BFIN_MODULE_H
8#define _ASM_BFIN_MODULE_H 8#define _ASM_BFIN_MODULE_H
diff --git a/arch/blackfin/include/asm/msgbuf.h b/arch/blackfin/include/asm/msgbuf.h
deleted file mode 100644
index 809134c644a6..000000000000
--- a/arch/blackfin/include/asm/msgbuf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/msgbuf.h>
diff --git a/arch/blackfin/include/asm/mutex.h b/arch/blackfin/include/asm/mutex.h
index f726e3a80ad0..ff6101aa2c71 100644
--- a/arch/blackfin/include/asm/mutex.h
+++ b/arch/blackfin/include/asm/mutex.h
@@ -1,76 +1 @@
1/* #include <asm-generic/mutex-dec.h>
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 *
8 * Copyright 2006-2009 Analog Devices Inc.
9 *
10 * Licensed under the GPL-2 or later.
11 */
12
13#ifndef _ASM_MUTEX_H
14#define _ASM_MUTEX_H
15
16#ifndef CONFIG_SMP
17#include <asm-generic/mutex.h>
18#else
19
20static inline void
21__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
22{
23 if (unlikely(atomic_dec_return(count) < 0))
24 fail_fn(count);
25 else
26 smp_mb();
27}
28
29static inline int
30__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
31{
32 if (unlikely(atomic_dec_return(count) < 0))
33 return fail_fn(count);
34 else {
35 smp_mb();
36 return 0;
37 }
38}
39
40static inline void
41__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
42{
43 smp_mb();
44 if (unlikely(atomic_inc_return(count) <= 0))
45 fail_fn(count);
46}
47
48#define __mutex_slowpath_needs_to_unlock() 1
49
50static inline int
51__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
52{
53 /*
54 * We have two variants here. The cmpxchg based one is the best one
55 * because it never induce a false contention state. It is included
56 * here because architectures using the inc/dec algorithms over the
57 * xchg ones are much more likely to support cmpxchg natively.
58 *
59 * If not we fall back to the spinlock based variant - that is
60 * just as efficient (and simpler) as a 'destructive' probing of
61 * the mutex state would be.
62 */
63#ifdef __HAVE_ARCH_CMPXCHG
64 if (likely(atomic_cmpxchg(count, 1, 0) == 1)) {
65 smp_mb();
66 return 1;
67 }
68 return 0;
69#else
70 return fail_fn(count);
71#endif
72}
73
74#endif
75
76#endif
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
index d0ce975bcd48..7202404966f6 100644
--- a/arch/blackfin/include/asm/page.h
+++ b/arch/blackfin/include/asm/page.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _BLACKFIN_PAGE_H 7#ifndef _BLACKFIN_PAGE_H
8#define _BLACKFIN_PAGE_H 8#define _BLACKFIN_PAGE_H
diff --git a/arch/blackfin/include/asm/param.h b/arch/blackfin/include/asm/param.h
deleted file mode 100644
index 965d45427975..000000000000
--- a/arch/blackfin/include/asm/param.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/param.h>
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h
index d49bb261d9b7..28c2498c9c98 100644
--- a/arch/blackfin/include/asm/pda.h
+++ b/arch/blackfin/include/asm/pda.h
@@ -54,6 +54,16 @@ struct blackfin_pda { /* Per-processor Data Area */
54#endif 54#endif
55}; 55};
56 56
57struct blackfin_initial_pda {
58 void *retx;
59#ifdef CONFIG_DEBUG_DOUBLEFAULT
60 void *dcplb_doublefault_addr;
61 void *icplb_doublefault_addr;
62 void *retx_doublefault;
63 unsigned seqstat_doublefault;
64#endif
65};
66
57extern struct blackfin_pda cpu_pda[]; 67extern struct blackfin_pda cpu_pda[];
58 68
59#endif /* __ASSEMBLY__ */ 69#endif /* __ASSEMBLY__ */
diff --git a/arch/blackfin/include/asm/percpu.h b/arch/blackfin/include/asm/percpu.h
deleted file mode 100644
index 06a959d67234..000000000000
--- a/arch/blackfin/include/asm/percpu.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/percpu.h>
diff --git a/arch/blackfin/include/asm/pgalloc.h b/arch/blackfin/include/asm/pgalloc.h
deleted file mode 100644
index f261cb7dda06..000000000000
--- a/arch/blackfin/include/asm/pgalloc.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/pgalloc.h>
diff --git a/arch/blackfin/include/asm/resource.h b/arch/blackfin/include/asm/resource.h
deleted file mode 100644
index 04bc4db8921b..000000000000
--- a/arch/blackfin/include/asm/resource.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/resource.h>
diff --git a/arch/blackfin/include/asm/scatterlist.h b/arch/blackfin/include/asm/scatterlist.h
deleted file mode 100644
index d177a1588958..000000000000
--- a/arch/blackfin/include/asm/scatterlist.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _BLACKFIN_SCATTERLIST_H
2#define _BLACKFIN_SCATTERLIST_H
3
4#include <asm-generic/scatterlist.h>
5
6#endif /* !(_BLACKFIN_SCATTERLIST_H) */
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
index 14a3e66d9167..fbd408475725 100644
--- a/arch/blackfin/include/asm/sections.h
+++ b/arch/blackfin/include/asm/sections.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _BLACKFIN_SECTIONS_H 7#ifndef _BLACKFIN_SECTIONS_H
8#define _BLACKFIN_SECTIONS_H 8#define _BLACKFIN_SECTIONS_H
diff --git a/arch/blackfin/include/asm/sembuf.h b/arch/blackfin/include/asm/sembuf.h
deleted file mode 100644
index 7673b83cfef7..000000000000
--- a/arch/blackfin/include/asm/sembuf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/sembuf.h>
diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
deleted file mode 100644
index a0cb0caff152..000000000000
--- a/arch/blackfin/include/asm/serial.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/serial.h>
diff --git a/arch/blackfin/include/asm/setup.h b/arch/blackfin/include/asm/setup.h
deleted file mode 100644
index 552df83f1a49..000000000000
--- a/arch/blackfin/include/asm/setup.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/setup.h>
diff --git a/arch/blackfin/include/asm/shmbuf.h b/arch/blackfin/include/asm/shmbuf.h
deleted file mode 100644
index 83c05fc2de38..000000000000
--- a/arch/blackfin/include/asm/shmbuf.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/shmbuf.h>
diff --git a/arch/blackfin/include/asm/shmparam.h b/arch/blackfin/include/asm/shmparam.h
deleted file mode 100644
index 93f30deb95d0..000000000000
--- a/arch/blackfin/include/asm/shmparam.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/shmparam.h>
diff --git a/arch/blackfin/include/asm/sigcontext.h b/arch/blackfin/include/asm/sigcontext.h
index ce4081a4d815..906bdc1f5fda 100644
--- a/arch/blackfin/include/asm/sigcontext.h
+++ b/arch/blackfin/include/asm/sigcontext.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright 2004-2008 Analog Devices Inc. 2 * Copyright 2004-2008 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef _ASM_BLACKFIN_SIGCONTEXT_H 7#ifndef _ASM_BLACKFIN_SIGCONTEXT_H
8#define _ASM_BLACKFIN_SIGCONTEXT_H 8#define _ASM_BLACKFIN_SIGCONTEXT_H
diff --git a/arch/blackfin/include/asm/socket.h b/arch/blackfin/include/asm/socket.h
deleted file mode 100644
index 6b71384b9d8b..000000000000
--- a/arch/blackfin/include/asm/socket.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/socket.h>
diff --git a/arch/blackfin/include/asm/sockios.h b/arch/blackfin/include/asm/sockios.h
deleted file mode 100644
index def6d4746ee7..000000000000
--- a/arch/blackfin/include/asm/sockios.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/sockios.h>
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index 1f286e71c21f..2336093fca23 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
6 6
7#ifndef __BFIN_SPINLOCK_H 7#ifndef __BFIN_SPINLOCK_H
8#define __BFIN_SPINLOCK_H 8#define __BFIN_SPINLOCK_H
diff --git a/arch/blackfin/include/asm/statfs.h b/arch/blackfin/include/asm/statfs.h
deleted file mode 100644
index 0b91fe198c20..000000000000
--- a/arch/blackfin/include/asm/statfs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/statfs.h>
diff --git a/arch/blackfin/include/asm/termbits.h b/arch/blackfin/include/asm/termbits.h
deleted file mode 100644
index 3935b106de79..000000000000
--- a/arch/blackfin/include/asm/termbits.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/termbits.h>
diff --git a/arch/blackfin/include/asm/termios.h b/arch/blackfin/include/asm/termios.h
deleted file mode 100644
index 280d78a9d966..000000000000
--- a/arch/blackfin/include/asm/termios.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/termios.h>
diff --git a/arch/blackfin/include/asm/topology.h b/arch/blackfin/include/asm/topology.h
deleted file mode 100644
index 5428f333a02c..000000000000
--- a/arch/blackfin/include/asm/topology.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/topology.h>
diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h
deleted file mode 100644
index b9e79bc580dd..000000000000
--- a/arch/blackfin/include/asm/types.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/types.h>
diff --git a/arch/blackfin/include/asm/ucontext.h b/arch/blackfin/include/asm/ucontext.h
deleted file mode 100644
index 9bc07b9f30fb..000000000000
--- a/arch/blackfin/include/asm/ucontext.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ucontext.h>
diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h
deleted file mode 100644
index 6cecbbb2111f..000000000000
--- a/arch/blackfin/include/asm/unaligned.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/unaligned.h>
diff --git a/arch/blackfin/include/asm/user.h b/arch/blackfin/include/asm/user.h
deleted file mode 100644
index 4792a60831e4..000000000000
--- a/arch/blackfin/include/asm/user.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/user.h>
diff --git a/arch/blackfin/include/asm/xor.h b/arch/blackfin/include/asm/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/arch/blackfin/include/asm/xor.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/xor.h>
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index d550b24d9e9b..b7bdc42fe1a3 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
21obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o 21obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
22CFLAGS_REMOVE_ftrace.o = -pg 22CFLAGS_REMOVE_ftrace.o = -pg
23 23
24obj-$(CONFIG_HAVE_PWM) += pwm.o
24obj-$(CONFIG_IPIPE) += ipipe.o 25obj-$(CONFIG_IPIPE) += ipipe.o
25obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o 26obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
26obj-$(CONFIG_CPLB_INFO) += cplbinfo.o 27obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
index bd32c09b9349..17e35465a416 100644
--- a/arch/blackfin/kernel/asm-offsets.c
+++ b/arch/blackfin/kernel/asm-offsets.c
@@ -138,6 +138,16 @@ int main(void)
138 DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault)); 138 DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault));
139 DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault)); 139 DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault));
140#endif 140#endif
141
142 /* PDA initial management */
143 DEFINE(PDA_INIT_RETX, offsetof(struct blackfin_initial_pda, retx));
144#ifdef CONFIG_DEBUG_DOUBLEFAULT
145 DEFINE(PDA_INIT_DF_DCPLB, offsetof(struct blackfin_initial_pda, dcplb_doublefault_addr));
146 DEFINE(PDA_INIT_DF_ICPLB, offsetof(struct blackfin_initial_pda, icplb_doublefault_addr));
147 DEFINE(PDA_INIT_DF_SEQSTAT, offsetof(struct blackfin_initial_pda, seqstat_doublefault));
148 DEFINE(PDA_INIT_DF_RETX, offsetof(struct blackfin_initial_pda, retx_doublefault));
149#endif
150
141#ifdef CONFIG_SMP 151#ifdef CONFIG_SMP
142 /* Inter-core lock (in L2 SRAM) */ 152 /* Inter-core lock (in L2 SRAM) */
143 DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot)); 153 DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot));
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index bcf8cf6fe412..02796b88443d 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -118,6 +118,9 @@ static struct str_ident {
118 118
119#if defined(CONFIG_PM) 119#if defined(CONFIG_PM)
120static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM]; 120static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
121# ifdef BF538_FAMILY
122static unsigned short port_fer_saved[3];
123# endif
121#endif 124#endif
122 125
123static void gpio_error(unsigned gpio) 126static void gpio_error(unsigned gpio)
@@ -604,6 +607,11 @@ void bfin_gpio_pm_hibernate_suspend(void)
604{ 607{
605 int i, bank; 608 int i, bank;
606 609
610#ifdef BF538_FAMILY
611 for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
612 port_fer_saved[i] = *port_fer[i];
613#endif
614
607 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { 615 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
608 bank = gpio_bank(i); 616 bank = gpio_bank(i);
609 617
@@ -625,6 +633,10 @@ void bfin_gpio_pm_hibernate_suspend(void)
625 gpio_bank_saved[bank].maska = gpio_array[bank]->maska; 633 gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
626 } 634 }
627 635
636#ifdef BFIN_SPECIAL_GPIO_BANKS
637 bfin_special_gpio_pm_hibernate_suspend();
638#endif
639
628 AWA_DUMMY_READ(maska); 640 AWA_DUMMY_READ(maska);
629} 641}
630 642
@@ -632,6 +644,11 @@ void bfin_gpio_pm_hibernate_restore(void)
632{ 644{
633 int i, bank; 645 int i, bank;
634 646
647#ifdef BF538_FAMILY
648 for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
649 *port_fer[i] = port_fer_saved[i];
650#endif
651
635 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) { 652 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
636 bank = gpio_bank(i); 653 bank = gpio_bank(i);
637 654
@@ -653,6 +670,11 @@ void bfin_gpio_pm_hibernate_restore(void)
653 gpio_array[bank]->both = gpio_bank_saved[bank].both; 670 gpio_array[bank]->both = gpio_bank_saved[bank].both;
654 gpio_array[bank]->maska = gpio_bank_saved[bank].maska; 671 gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
655 } 672 }
673
674#ifdef BFIN_SPECIAL_GPIO_BANKS
675 bfin_special_gpio_pm_hibernate_restore();
676#endif
677
656 AWA_DUMMY_READ(maska); 678 AWA_DUMMY_READ(maska);
657} 679}
658 680
@@ -691,9 +713,9 @@ void bfin_gpio_pm_hibernate_restore(void)
691 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux; 713 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
692 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer; 714 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
693 gpio_array[bank]->inen = gpio_bank_saved[bank].inen; 715 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
694 gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
695 gpio_array[bank]->data_set = gpio_bank_saved[bank].data 716 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
696 | gpio_bank_saved[bank].dir; 717 & gpio_bank_saved[bank].dir;
718 gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
697 } 719 }
698} 720}
699#endif 721#endif
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
index fce4807ceef9..92f664826281 100644
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -27,7 +27,7 @@
27#define PORT_MUX BFIN_PORT_MUX 27#define PORT_MUX BFIN_PORT_MUX
28#endif 28#endif
29 29
30#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr) 30#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
31#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR) 31#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
32#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR) 32#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
33#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR) 33#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
@@ -223,7 +223,8 @@ bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdm
223 __DMA(CURR_DESC_PTR, curr_desc_ptr); 223 __DMA(CURR_DESC_PTR, curr_desc_ptr);
224 __DMA(CURR_ADDR, curr_addr); 224 __DMA(CURR_ADDR, curr_addr);
225 __DMA(IRQ_STATUS, irq_status); 225 __DMA(IRQ_STATUS, irq_status);
226 __DMA(PERIPHERAL_MAP, peripheral_map); 226 if (strcmp(pfx, "IMDMA") != 0)
227 __DMA(PERIPHERAL_MAP, peripheral_map);
227 __DMA(CURR_X_COUNT, curr_x_count); 228 __DMA(CURR_X_COUNT, curr_x_count);
228 __DMA(CURR_Y_COUNT, curr_y_count); 229 __DMA(CURR_Y_COUNT, curr_y_count);
229} 230}
@@ -277,6 +278,32 @@ bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
277} 278}
278#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num) 279#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
279 280
281#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
282#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
283static void __init __maybe_unused
284bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
285{
286 char buf[32], *_buf;
287
288 if (num == -1) {
289 _buf = buf + sprintf(buf, "TIMER_");
290 __GPTIMER_GROUP(ENABLE, enable);
291 __GPTIMER_GROUP(DISABLE, disable);
292 __GPTIMER_GROUP(STATUS, status);
293 } else {
294 /* These MMRs are a bit odd as the group # is a suffix */
295 _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
296 d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
297
298 _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
299 d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
300
301 _buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
302 d(buf, 32, base + GPTIMER_GROUP_OFF(status));
303 }
304}
305#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
306
280/* 307/*
281 * Handshake MDMA 308 * Handshake MDMA
282 */ 309 */
@@ -296,6 +323,29 @@ bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
296#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num) 323#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
297 324
298/* 325/*
326 * Peripheral Interrupts (PINT/GPIO)
327 */
328#ifdef PINT0_MASK_SET
329#define __PINT(uname, lname) __REGS(pint, #uname, lname)
330static void __init __maybe_unused
331bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num)
332{
333 char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num);
334 __PINT(MASK_SET, mask_set);
335 __PINT(MASK_CLEAR, mask_clear);
336 __PINT(REQUEST, request);
337 __PINT(ASSIGN, assign);
338 __PINT(EDGE_SET, edge_set);
339 __PINT(EDGE_CLEAR, edge_clear);
340 __PINT(INVERT_SET, invert_set);
341 __PINT(INVERT_CLEAR, invert_clear);
342 __PINT(PINSTATE, pinstate);
343 __PINT(LATCH, latch);
344}
345#define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num)
346#endif
347
348/*
299 * Port/GPIO 349 * Port/GPIO
300 */ 350 */
301#define bfin_gpio_regs gpio_port_t 351#define bfin_gpio_regs gpio_port_t
@@ -747,7 +797,7 @@ static int __init bfin_debug_mmrs_init(void)
747#endif 797#endif
748 798
749 parent = debugfs_create_dir("dmac", top); 799 parent = debugfs_create_dir("dmac", top);
750#ifdef DMA_TC_CNT 800#ifdef DMAC_TC_CNT
751 D16(DMAC_TC_CNT); 801 D16(DMAC_TC_CNT);
752 D16(DMAC_TC_PER); 802 D16(DMAC_TC_PER);
753#endif 803#endif
@@ -1005,29 +1055,19 @@ static int __init bfin_debug_mmrs_init(void)
1005#endif 1055#endif
1006 1056
1007 parent = debugfs_create_dir("gptimer", top); 1057 parent = debugfs_create_dir("gptimer", top);
1008#ifdef TIMER_DISABLE 1058#ifdef TIMER_ENABLE
1009 D16(TIMER_DISABLE); 1059 GPTIMER_GROUP(TIMER_ENABLE, -1);
1010 D16(TIMER_ENABLE);
1011 D32(TIMER_STATUS);
1012#endif 1060#endif
1013#ifdef TIMER_DISABLE0 1061#ifdef TIMER_ENABLE0
1014 D16(TIMER_DISABLE0); 1062 GPTIMER_GROUP(TIMER_ENABLE0, 0);
1015 D16(TIMER_ENABLE0);
1016 D32(TIMER_STATUS0);
1017#endif 1063#endif
1018#ifdef TIMER_DISABLE1 1064#ifdef TIMER_ENABLE1
1019 D16(TIMER_DISABLE1); 1065 GPTIMER_GROUP(TIMER_ENABLE1, 1);
1020 D16(TIMER_ENABLE1);
1021 D32(TIMER_STATUS1);
1022#endif 1066#endif
1023 /* XXX: Should convert BF561 MMR names */ 1067 /* XXX: Should convert BF561 MMR names */
1024#ifdef TMRS4_DISABLE 1068#ifdef TMRS4_DISABLE
1025 D16(TMRS4_DISABLE); 1069 GPTIMER_GROUP(TMRS4_ENABLE, 0);
1026 D16(TMRS4_ENABLE); 1070 GPTIMER_GROUP(TMRS8_ENABLE, 1);
1027 D32(TMRS4_STATUS);
1028 D16(TMRS8_DISABLE);
1029 D16(TMRS8_ENABLE);
1030 D32(TMRS8_STATUS);
1031#endif 1071#endif
1032 GPTIMER(0); 1072 GPTIMER(0);
1033 GPTIMER(1); 1073 GPTIMER(1);
@@ -1253,6 +1293,14 @@ static int __init bfin_debug_mmrs_init(void)
1253 D32(OTP_DATA3); 1293 D32(OTP_DATA3);
1254#endif 1294#endif
1255 1295
1296#ifdef PINT0_MASK_SET
1297 parent = debugfs_create_dir("pint", top);
1298 PINT(0);
1299 PINT(1);
1300 PINT(2);
1301 PINT(3);
1302#endif
1303
1256#ifdef PIXC_CTL 1304#ifdef PIXC_CTL
1257 parent = debugfs_create_dir("pixc", top); 1305 parent = debugfs_create_dir("pixc", top);
1258 D16(PIXC_CTL); 1306 D16(PIXC_CTL);
@@ -1816,7 +1864,6 @@ static int __init bfin_debug_mmrs_init(void)
1816 { 1864 {
1817 int num; 1865 int num;
1818 unsigned long base; 1866 unsigned long base;
1819 char *_buf, buf[32];
1820 1867
1821 base = PORTA_FER; 1868 base = PORTA_FER;
1822 for (num = 0; num < 10; ++num) { 1869 for (num = 0; num < 10; ++num) {
@@ -1824,24 +1871,6 @@ static int __init bfin_debug_mmrs_init(void)
1824 base += sizeof(struct bfin_gpio_regs); 1871 base += sizeof(struct bfin_gpio_regs);
1825 } 1872 }
1826 1873
1827#define __PINT(uname, lname) __REGS(pint, #uname, lname)
1828 parent = debugfs_create_dir("pint", top);
1829 base = PINT0_MASK_SET;
1830 for (num = 0; num < 4; ++num) {
1831 _buf = REGS_STR_PFX(buf, PINT, num);
1832 __PINT(MASK_SET, mask_set);
1833 __PINT(MASK_CLEAR, mask_clear);
1834 __PINT(IRQ, irq);
1835 __PINT(ASSIGN, assign);
1836 __PINT(EDGE_SET, edge_set);
1837 __PINT(EDGE_CLEAR, edge_clear);
1838 __PINT(INVERT_SET, invert_set);
1839 __PINT(INVERT_CLEAR, invert_clear);
1840 __PINT(PINSTATE, pinstate);
1841 __PINT(LATCH, latch);
1842 base += sizeof(struct bfin_pint_regs);
1843 }
1844
1845 } 1874 }
1846#endif /* BF54x */ 1875#endif /* BF54x */
1847 1876
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
index 8b81dc04488a..06459f4bf43a 100644
--- a/arch/blackfin/kernel/gptimers.c
+++ b/arch/blackfin/kernel/gptimers.c
@@ -25,49 +25,33 @@
25 25
26#define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1) 26#define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
27 27
28typedef struct { 28static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
29 uint16_t config;
30 uint16_t __pad;
31 uint32_t counter;
32 uint32_t period;
33 uint32_t width;
34} GPTIMER_timer_regs;
35
36typedef struct {
37 uint16_t enable;
38 uint16_t __pad0;
39 uint16_t disable;
40 uint16_t __pad1;
41 uint32_t status;
42} GPTIMER_group_regs;
43
44static volatile GPTIMER_timer_regs *const timer_regs[MAX_BLACKFIN_GPTIMERS] =
45{ 29{
46 (GPTIMER_timer_regs *)TIMER0_CONFIG, 30 (void *)TIMER0_CONFIG,
47 (GPTIMER_timer_regs *)TIMER1_CONFIG, 31 (void *)TIMER1_CONFIG,
48 (GPTIMER_timer_regs *)TIMER2_CONFIG, 32 (void *)TIMER2_CONFIG,
49#if (MAX_BLACKFIN_GPTIMERS > 3) 33#if (MAX_BLACKFIN_GPTIMERS > 3)
50 (GPTIMER_timer_regs *)TIMER3_CONFIG, 34 (void *)TIMER3_CONFIG,
51 (GPTIMER_timer_regs *)TIMER4_CONFIG, 35 (void *)TIMER4_CONFIG,
52 (GPTIMER_timer_regs *)TIMER5_CONFIG, 36 (void *)TIMER5_CONFIG,
53 (GPTIMER_timer_regs *)TIMER6_CONFIG, 37 (void *)TIMER6_CONFIG,
54 (GPTIMER_timer_regs *)TIMER7_CONFIG, 38 (void *)TIMER7_CONFIG,
55# if (MAX_BLACKFIN_GPTIMERS > 8) 39# if (MAX_BLACKFIN_GPTIMERS > 8)
56 (GPTIMER_timer_regs *)TIMER8_CONFIG, 40 (void *)TIMER8_CONFIG,
57 (GPTIMER_timer_regs *)TIMER9_CONFIG, 41 (void *)TIMER9_CONFIG,
58 (GPTIMER_timer_regs *)TIMER10_CONFIG, 42 (void *)TIMER10_CONFIG,
59# if (MAX_BLACKFIN_GPTIMERS > 11) 43# if (MAX_BLACKFIN_GPTIMERS > 11)
60 (GPTIMER_timer_regs *)TIMER11_CONFIG, 44 (void *)TIMER11_CONFIG,
61# endif 45# endif
62# endif 46# endif
63#endif 47#endif
64}; 48};
65 49
66static volatile GPTIMER_group_regs *const group_regs[BFIN_TIMER_NUM_GROUP] = 50static struct bfin_gptimer_group_regs * const group_regs[BFIN_TIMER_NUM_GROUP] =
67{ 51{
68 (GPTIMER_group_regs *)TIMER0_GROUP_REG, 52 (void *)TIMER0_GROUP_REG,
69#if (MAX_BLACKFIN_GPTIMERS > 8) 53#if (MAX_BLACKFIN_GPTIMERS > 8)
70 (GPTIMER_group_regs *)TIMER8_GROUP_REG, 54 (void *)TIMER8_GROUP_REG,
71#endif 55#endif
72}; 56};
73 57
@@ -140,7 +124,7 @@ static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
140void set_gptimer_pwidth(unsigned int timer_id, uint32_t value) 124void set_gptimer_pwidth(unsigned int timer_id, uint32_t value)
141{ 125{
142 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 126 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
143 timer_regs[timer_id]->width = value; 127 bfin_write(&timer_regs[timer_id]->width, value);
144 SSYNC(); 128 SSYNC();
145} 129}
146EXPORT_SYMBOL(set_gptimer_pwidth); 130EXPORT_SYMBOL(set_gptimer_pwidth);
@@ -148,14 +132,14 @@ EXPORT_SYMBOL(set_gptimer_pwidth);
148uint32_t get_gptimer_pwidth(unsigned int timer_id) 132uint32_t get_gptimer_pwidth(unsigned int timer_id)
149{ 133{
150 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 134 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
151 return timer_regs[timer_id]->width; 135 return bfin_read(&timer_regs[timer_id]->width);
152} 136}
153EXPORT_SYMBOL(get_gptimer_pwidth); 137EXPORT_SYMBOL(get_gptimer_pwidth);
154 138
155void set_gptimer_period(unsigned int timer_id, uint32_t period) 139void set_gptimer_period(unsigned int timer_id, uint32_t period)
156{ 140{
157 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 141 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
158 timer_regs[timer_id]->period = period; 142 bfin_write(&timer_regs[timer_id]->period, period);
159 SSYNC(); 143 SSYNC();
160} 144}
161EXPORT_SYMBOL(set_gptimer_period); 145EXPORT_SYMBOL(set_gptimer_period);
@@ -163,71 +147,76 @@ EXPORT_SYMBOL(set_gptimer_period);
163uint32_t get_gptimer_period(unsigned int timer_id) 147uint32_t get_gptimer_period(unsigned int timer_id)
164{ 148{
165 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 149 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
166 return timer_regs[timer_id]->period; 150 return bfin_read(&timer_regs[timer_id]->period);
167} 151}
168EXPORT_SYMBOL(get_gptimer_period); 152EXPORT_SYMBOL(get_gptimer_period);
169 153
170uint32_t get_gptimer_count(unsigned int timer_id) 154uint32_t get_gptimer_count(unsigned int timer_id)
171{ 155{
172 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 156 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
173 return timer_regs[timer_id]->counter; 157 return bfin_read(&timer_regs[timer_id]->counter);
174} 158}
175EXPORT_SYMBOL(get_gptimer_count); 159EXPORT_SYMBOL(get_gptimer_count);
176 160
177uint32_t get_gptimer_status(unsigned int group) 161uint32_t get_gptimer_status(unsigned int group)
178{ 162{
179 tassert(group < BFIN_TIMER_NUM_GROUP); 163 tassert(group < BFIN_TIMER_NUM_GROUP);
180 return group_regs[group]->status; 164 return bfin_read(&group_regs[group]->status);
181} 165}
182EXPORT_SYMBOL(get_gptimer_status); 166EXPORT_SYMBOL(get_gptimer_status);
183 167
184void set_gptimer_status(unsigned int group, uint32_t value) 168void set_gptimer_status(unsigned int group, uint32_t value)
185{ 169{
186 tassert(group < BFIN_TIMER_NUM_GROUP); 170 tassert(group < BFIN_TIMER_NUM_GROUP);
187 group_regs[group]->status = value; 171 bfin_write(&group_regs[group]->status, value);
188 SSYNC(); 172 SSYNC();
189} 173}
190EXPORT_SYMBOL(set_gptimer_status); 174EXPORT_SYMBOL(set_gptimer_status);
191 175
176static uint32_t read_gptimer_status(unsigned int timer_id)
177{
178 return bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status);
179}
180
192int get_gptimer_intr(unsigned int timer_id) 181int get_gptimer_intr(unsigned int timer_id)
193{ 182{
194 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 183 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
195 return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]); 184 return !!(read_gptimer_status(timer_id) & timil_mask[timer_id]);
196} 185}
197EXPORT_SYMBOL(get_gptimer_intr); 186EXPORT_SYMBOL(get_gptimer_intr);
198 187
199void clear_gptimer_intr(unsigned int timer_id) 188void clear_gptimer_intr(unsigned int timer_id)
200{ 189{
201 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 190 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
202 group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id]; 191 bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, timil_mask[timer_id]);
203} 192}
204EXPORT_SYMBOL(clear_gptimer_intr); 193EXPORT_SYMBOL(clear_gptimer_intr);
205 194
206int get_gptimer_over(unsigned int timer_id) 195int get_gptimer_over(unsigned int timer_id)
207{ 196{
208 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 197 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
209 return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]); 198 return !!(read_gptimer_status(timer_id) & tovf_mask[timer_id]);
210} 199}
211EXPORT_SYMBOL(get_gptimer_over); 200EXPORT_SYMBOL(get_gptimer_over);
212 201
213void clear_gptimer_over(unsigned int timer_id) 202void clear_gptimer_over(unsigned int timer_id)
214{ 203{
215 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 204 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
216 group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id]; 205 bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, tovf_mask[timer_id]);
217} 206}
218EXPORT_SYMBOL(clear_gptimer_over); 207EXPORT_SYMBOL(clear_gptimer_over);
219 208
220int get_gptimer_run(unsigned int timer_id) 209int get_gptimer_run(unsigned int timer_id)
221{ 210{
222 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 211 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
223 return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]); 212 return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
224} 213}
225EXPORT_SYMBOL(get_gptimer_run); 214EXPORT_SYMBOL(get_gptimer_run);
226 215
227void set_gptimer_config(unsigned int timer_id, uint16_t config) 216void set_gptimer_config(unsigned int timer_id, uint16_t config)
228{ 217{
229 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 218 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
230 timer_regs[timer_id]->config = config; 219 bfin_write(&timer_regs[timer_id]->config, config);
231 SSYNC(); 220 SSYNC();
232} 221}
233EXPORT_SYMBOL(set_gptimer_config); 222EXPORT_SYMBOL(set_gptimer_config);
@@ -235,7 +224,7 @@ EXPORT_SYMBOL(set_gptimer_config);
235uint16_t get_gptimer_config(unsigned int timer_id) 224uint16_t get_gptimer_config(unsigned int timer_id)
236{ 225{
237 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 226 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
238 return timer_regs[timer_id]->config; 227 return bfin_read(&timer_regs[timer_id]->config);
239} 228}
240EXPORT_SYMBOL(get_gptimer_config); 229EXPORT_SYMBOL(get_gptimer_config);
241 230
@@ -244,7 +233,7 @@ void enable_gptimers(uint16_t mask)
244 int i; 233 int i;
245 tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0); 234 tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
246 for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) { 235 for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
247 group_regs[i]->enable = mask & 0xFF; 236 bfin_write(&group_regs[i]->enable, mask & 0xFF);
248 mask >>= 8; 237 mask >>= 8;
249 } 238 }
250 SSYNC(); 239 SSYNC();
@@ -257,7 +246,7 @@ static void _disable_gptimers(uint16_t mask)
257 uint16_t m = mask; 246 uint16_t m = mask;
258 tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0); 247 tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
259 for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) { 248 for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
260 group_regs[i]->disable = m & 0xFF; 249 bfin_write(&group_regs[i]->disable, m & 0xFF);
261 m >>= 8; 250 m >>= 8;
262 } 251 }
263} 252}
@@ -268,7 +257,7 @@ void disable_gptimers(uint16_t mask)
268 _disable_gptimers(mask); 257 _disable_gptimers(mask);
269 for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i) 258 for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
270 if (mask & (1 << i)) 259 if (mask & (1 << i))
271 group_regs[BFIN_TIMER_OCTET(i)]->status = trun_mask[i]; 260 bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
272 SSYNC(); 261 SSYNC();
273} 262}
274EXPORT_SYMBOL(disable_gptimers); 263EXPORT_SYMBOL(disable_gptimers);
@@ -283,7 +272,7 @@ EXPORT_SYMBOL(disable_gptimers_sync);
283void set_gptimer_pulse_hi(unsigned int timer_id) 272void set_gptimer_pulse_hi(unsigned int timer_id)
284{ 273{
285 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 274 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
286 timer_regs[timer_id]->config |= TIMER_PULSE_HI; 275 bfin_write_or(&timer_regs[timer_id]->config, TIMER_PULSE_HI);
287 SSYNC(); 276 SSYNC();
288} 277}
289EXPORT_SYMBOL(set_gptimer_pulse_hi); 278EXPORT_SYMBOL(set_gptimer_pulse_hi);
@@ -291,7 +280,7 @@ EXPORT_SYMBOL(set_gptimer_pulse_hi);
291void clear_gptimer_pulse_hi(unsigned int timer_id) 280void clear_gptimer_pulse_hi(unsigned int timer_id)
292{ 281{
293 tassert(timer_id < MAX_BLACKFIN_GPTIMERS); 282 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
294 timer_regs[timer_id]->config &= ~TIMER_PULSE_HI; 283 bfin_write_and(&timer_regs[timer_id]->config, ~TIMER_PULSE_HI);
295 SSYNC(); 284 SSYNC();
296} 285}
297EXPORT_SYMBOL(clear_gptimer_pulse_hi); 286EXPORT_SYMBOL(clear_gptimer_pulse_hi);
@@ -301,7 +290,7 @@ uint16_t get_enabled_gptimers(void)
301 int i; 290 int i;
302 uint16_t result = 0; 291 uint16_t result = 0;
303 for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) 292 for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i)
304 result |= (group_regs[i]->enable << (i << 3)); 293 result |= (bfin_read(&group_regs[i]->enable) << (i << 3));
305 return result; 294 return result;
306} 295}
307EXPORT_SYMBOL(get_enabled_gptimers); 296EXPORT_SYMBOL(get_enabled_gptimers);
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 6a660fa921b5..6a80a9e9fc4a 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -140,7 +140,6 @@ EXPORT_SYMBOL(kernel_thread);
140 */ 140 */
141void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp) 141void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
142{ 142{
143 set_fs(USER_DS);
144 regs->pc = new_ip; 143 regs->pc = new_ip;
145 if (current->mm) 144 if (current->mm)
146 regs->p5 = current->mm->start_data; 145 regs->p5 = current->mm->start_data;
diff --git a/arch/blackfin/kernel/pwm.c b/arch/blackfin/kernel/pwm.c
new file mode 100644
index 000000000000..33f5942733bd
--- /dev/null
+++ b/arch/blackfin/kernel/pwm.c
@@ -0,0 +1,100 @@
1/*
2 * Blackfin Pulse Width Modulation (PWM) core
3 *
4 * Copyright (c) 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/pwm.h>
11#include <linux/slab.h>
12
13#include <asm/gptimers.h>
14#include <asm/portmux.h>
15
16struct pwm_device {
17 unsigned id;
18 unsigned short pin;
19};
20
21static const unsigned short pwm_to_gptimer_per[] = {
22 P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR4, P_TMR5,
23 P_TMR6, P_TMR7, P_TMR8, P_TMR9, P_TMR10, P_TMR11,
24};
25
26struct pwm_device *pwm_request(int pwm_id, const char *label)
27{
28 struct pwm_device *pwm;
29 int ret;
30
31 /* XXX: pwm_id really should be unsigned */
32 if (pwm_id < 0)
33 return NULL;
34
35 pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
36 if (!pwm)
37 return pwm;
38
39 pwm->id = pwm_id;
40 if (pwm->id >= ARRAY_SIZE(pwm_to_gptimer_per))
41 goto err;
42
43 pwm->pin = pwm_to_gptimer_per[pwm->id];
44 ret = peripheral_request(pwm->pin, label);
45 if (ret)
46 goto err;
47
48 return pwm;
49 err:
50 kfree(pwm);
51 return NULL;
52}
53EXPORT_SYMBOL(pwm_request);
54
55void pwm_free(struct pwm_device *pwm)
56{
57 peripheral_free(pwm->pin);
58 kfree(pwm);
59}
60EXPORT_SYMBOL(pwm_free);
61
62int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
63{
64 unsigned long period, duty;
65 unsigned long long val;
66
67 if (duty_ns < 0 || duty_ns > period_ns)
68 return -EINVAL;
69
70 val = (unsigned long long)get_sclk() * period_ns;
71 do_div(val, NSEC_PER_SEC);
72 period = val;
73
74 val = (unsigned long long)period * duty_ns;
75 do_div(val, period_ns);
76 duty = period - val;
77
78 if (duty >= period)
79 duty = period - 1;
80
81 set_gptimer_config(pwm->id, TIMER_MODE_PWM | TIMER_PERIOD_CNT);
82 set_gptimer_pwidth(pwm->id, duty);
83 set_gptimer_period(pwm->id, period);
84
85 return 0;
86}
87EXPORT_SYMBOL(pwm_config);
88
89int pwm_enable(struct pwm_device *pwm)
90{
91 enable_gptimer(pwm->id);
92 return 0;
93}
94EXPORT_SYMBOL(pwm_enable);
95
96void pwm_disable(struct pwm_device *pwm)
97{
98 disable_gptimer(pwm->id);
99}
100EXPORT_SYMBOL(pwm_disable);
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 488bdc51aaa5..c4c0081b1996 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -54,7 +54,9 @@ static void bfin_reset(void)
54 54
55 /* The BF526 ROM will crash during reset */ 55 /* The BF526 ROM will crash during reset */
56#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) 56#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
57 bfin_read_SWRST(); 57 /* Seems to be fixed with newer parts though ... */
58 if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
59 bfin_read_SWRST();
58#endif 60#endif
59 61
60 /* Wait for the SWRST write to complete. Cannot rely on SSYNC 62 /* Wait for the SWRST write to complete. Cannot rely on SSYNC
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 536bd9d7e0cf..dfa2525a442d 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -54,8 +54,7 @@ EXPORT_SYMBOL(mtd_size);
54#endif 54#endif
55 55
56char __initdata command_line[COMMAND_LINE_SIZE]; 56char __initdata command_line[COMMAND_LINE_SIZE];
57void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat, 57struct blackfin_initial_pda __initdata initial_pda;
58 *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr;
59 58
60/* boot memmap, for parsing "memmap=" */ 59/* boot memmap, for parsing "memmap=" */
61#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */ 60#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
@@ -957,13 +956,16 @@ void __init setup_arch(char **cmdline_p)
957 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n"); 956 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
958#ifdef CONFIG_DEBUG_DOUBLEFAULT 957#ifdef CONFIG_DEBUG_DOUBLEFAULT
959 /* We assume the crashing kernel, and the current symbol table match */ 958 /* We assume the crashing kernel, and the current symbol table match */
960 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n", 959 printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
961 (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx); 960 initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE,
962 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr); 961 initial_pda.retx_doublefault);
963 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr); 962 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
963 initial_pda.dcplb_doublefault_addr);
964 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
965 initial_pda.icplb_doublefault_addr);
964#endif 966#endif
965 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", 967 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
966 init_retx); 968 initial_pda.retx);
967 } else if (_bfin_swrst & RESET_WDOG) 969 } else if (_bfin_swrst & RESET_WDOG)
968 printk(KERN_INFO "Recovering from Watchdog event\n"); 970 printk(KERN_INFO "Recovering from Watchdog event\n");
969 else if (_bfin_swrst & RESET_SOFTWARE) 971 else if (_bfin_swrst & RESET_SOFTWARE)
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index 8d73724c0092..ceb2bf63dfe2 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -51,7 +51,7 @@ void __init setup_core_timer(void)
51 u32 tcount; 51 u32 tcount;
52 52
53 /* power up the timer, but don't enable it just yet */ 53 /* power up the timer, but don't enable it just yet */
54 bfin_write_TCNTL(1); 54 bfin_write_TCNTL(TMPWR);
55 CSYNC(); 55 CSYNC();
56 56
57 /* the TSCALE prescaler counter */ 57 /* the TSCALE prescaler counter */
@@ -64,7 +64,7 @@ void __init setup_core_timer(void)
64 /* now enable the timer */ 64 /* now enable the timer */
65 CSYNC(); 65 CSYNC();
66 66
67 bfin_write_TCNTL(7); 67 bfin_write_TCNTL(TAUTORLD | TMREN | TMPWR);
68} 68}
69#endif 69#endif
70 70
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 3ac5b66d14aa..ba35864b2b74 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -155,6 +155,7 @@ SECTIONS
155 SECURITY_INITCALL 155 SECURITY_INITCALL
156 INIT_RAM_FS 156 INIT_RAM_FS
157 157
158 . = ALIGN(PAGE_SIZE);
158 ___per_cpu_load = .; 159 ___per_cpu_load = .;
159 PERCPU_INPUT(32) 160 PERCPU_INPUT(32)
160 161
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
index 1d9f631a7f94..bde92a19970e 100644
--- a/arch/blackfin/mach-bf518/Kconfig
+++ b/arch/blackfin/mach-bf518/Kconfig
@@ -11,55 +11,75 @@ menu "BF518 Specific Configuration"
11comment "Alternative Multiplexing Scheme" 11comment "Alternative Multiplexing Scheme"
12 12
13choice 13choice
14 prompt "SPORT0" 14 prompt "PWM Channel Pins"
15 default BF518_SPORT0_PORTG 15 default BF518_PWM_ALL_PORTF
16 help 16 help
17 Select PORT used for SPORT0. See Hardware Reference Manual 17 Select pins used for the PWM channels:
18 PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL
18 19
19config BF518_SPORT0_PORTF 20 See the Hardware Reference Manual for more details.
20 bool "PORT F" 21
22config BF518_PWM_ALL_PORTF
23 bool "PF1 - PF6"
21 help 24 help
22 PORT F 25 PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL}
23 26
24config BF518_SPORT0_PORTG 27config BF518_PWM_PORTF_PORTG
25 bool "PORT G" 28 bool "PF11 - PF14 / PG1 - PG2"
26 help 29 help
27 PORT G 30 PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL}
31 PG{1,2} <-> PWM_{CH,CL}
32
28endchoice 33endchoice
29 34
30choice 35choice
31 prompt "SPORT0 TSCLK Location" 36 prompt "PWM Sync Pin"
32 depends on BF518_SPORT0_PORTG 37 default BF518_PWM_SYNC_PF7
33 default BF518_SPORT0_TSCLK_PG10
34 help 38 help
35 Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual 39 Select the pin used for PWM_SYNC.
36 40
37config BF518_SPORT0_TSCLK_PG10 41 See the Hardware Reference Manual for more details.
38 bool "PORT PG10" 42
39 help 43config BF518_PWM_SYNC_PF7
40 PORT PG10 44 bool "PF7"
45config BF518_PWM_SYNC_PF15
46 bool "PF15"
47endchoice
41 48
42config BF518_SPORT0_TSCLK_PG14 49choice
43 bool "PORT PG14" 50 prompt "PWM Trip B Pin"
51 default BF518_PWM_TRIPB_PG10
44 help 52 help
45 PORT PG14 53 Select the pin used for PWM_TRIPB.
54
55 See the Hardware Reference Manual for more details.
56
57config BF518_PWM_TRIPB_PG10
58 bool "PG10"
59config BF518_PWM_TRIPB_PG14
60 bool "PG14"
46endchoice 61endchoice
47 62
48choice 63choice
49 prompt "UART1" 64 prompt "PPI / Timer Pins"
50 default BF518_UART1_PORTF 65 default BF518_PPI_TMR_PG5
51 help 66 help
52 Select PORT used for UART1. See Hardware Reference Manual 67 Select pins used for PPI/Timer:
68 PPICLK PPIFS1 PPIFS2
69 TMRCLK TMR0 TMR1
53 70
54config BF518_UART1_PORTF 71 See the Hardware Reference Manual for more details.
55 bool "PORT F" 72
73config BF518_PPI_TMR_PG5
74 bool "PG5 - PG7"
56 help 75 help
57 PORT F 76 PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
58 77
59config BF518_UART1_PORTG 78config BF518_PPI_TMR_PG12
60 bool "PORT G" 79 bool "PG12 - PG14"
61 help 80 help
62 PORT G 81 PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
82
63endchoice 83endchoice
64 84
65comment "Hysteresis/Schmitt Trigger Control" 85comment "Hysteresis/Schmitt Trigger Control"
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index c0ccadcfa44e..d78fc2cc7d16 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -187,43 +187,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
187/* SPI flash chip (m25p64) */ 187/* SPI flash chip (m25p64) */
188static struct bfin5xx_spi_chip spi_flash_chip_info = { 188static struct bfin5xx_spi_chip spi_flash_chip_info = {
189 .enable_dma = 0, /* use dma transfer with this chip*/ 189 .enable_dma = 0, /* use dma transfer with this chip*/
190 .bits_per_word = 8,
191}; 190};
192#endif 191#endif
193 192
194#if defined(CONFIG_BFIN_SPI_ADC) \
195 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
196/* SPI ADC chip */
197static struct bfin5xx_spi_chip spi_adc_chip_info = {
198 .enable_dma = 1, /* use dma transfer with this chip*/
199 .bits_per_word = 16,
200};
201#endif
202
203#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
204#if defined(CONFIG_NET_DSA_KSZ8893M) \
205 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
206/* SPI SWITCH CHIP */
207static struct bfin5xx_spi_chip spi_switch_info = {
208 .enable_dma = 0,
209 .bits_per_word = 8,
210};
211#endif
212#endif
213
214#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 193#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
215static struct bfin5xx_spi_chip mmc_spi_chip_info = { 194static struct bfin5xx_spi_chip mmc_spi_chip_info = {
216 .enable_dma = 0, 195 .enable_dma = 0,
217 .bits_per_word = 8,
218}; 196};
219#endif 197#endif
220 198
221#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 199#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
222static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
223 .enable_dma = 0,
224 .bits_per_word = 16,
225};
226
227static const struct ad7877_platform_data bfin_ad7877_ts_info = { 200static const struct ad7877_platform_data bfin_ad7877_ts_info = {
228 .model = 7877, 201 .model = 7877,
229 .vref_delay_usecs = 50, /* internal, no capacitor */ 202 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -239,21 +212,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
239}; 212};
240#endif 213#endif
241 214
242#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
243 && defined(CONFIG_SND_SOC_WM8731_SPI)
244static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
245 .enable_dma = 0,
246 .bits_per_word = 16,
247};
248#endif
249
250#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
251static struct bfin5xx_spi_chip spidev_chip_info = {
252 .enable_dma = 0,
253 .bits_per_word = 8,
254};
255#endif
256
257static struct spi_board_info bfin_spi_board_info[] __initdata = { 215static struct spi_board_info bfin_spi_board_info[] __initdata = {
258#if defined(CONFIG_MTD_M25P80) \ 216#if defined(CONFIG_MTD_M25P80) \
259 || defined(CONFIG_MTD_M25P80_MODULE) 217 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -269,18 +227,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
269 }, 227 },
270#endif 228#endif
271 229
272#if defined(CONFIG_BFIN_SPI_ADC) \
273 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
274 {
275 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
276 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
277 .bus_num = 0, /* Framework bus number */
278 .chip_select = 1, /* Framework chip select. */
279 .platform_data = NULL, /* No spi_driver specific config */
280 .controller_data = &spi_adc_chip_info,
281 },
282#endif
283
284#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 230#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
285#if defined(CONFIG_NET_DSA_KSZ8893M) \ 231#if defined(CONFIG_NET_DSA_KSZ8893M) \
286 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 232 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
@@ -290,7 +236,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
290 .bus_num = 0, 236 .bus_num = 0,
291 .chip_select = 1, 237 .chip_select = 1,
292 .platform_data = NULL, 238 .platform_data = NULL,
293 .controller_data = &spi_switch_info,
294 .mode = SPI_MODE_3, 239 .mode = SPI_MODE_3,
295 }, 240 },
296#endif 241#endif
@@ -314,7 +259,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
314 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 259 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
315 .bus_num = 0, 260 .bus_num = 0,
316 .chip_select = 2, 261 .chip_select = 2,
317 .controller_data = &spi_ad7877_chip_info,
318 }, 262 },
319#endif 263#endif
320#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ 264#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
@@ -324,7 +268,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
324 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 268 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
325 .bus_num = 0, 269 .bus_num = 0,
326 .chip_select = 5, 270 .chip_select = 5,
327 .controller_data = &spi_wm8731_chip_info,
328 .mode = SPI_MODE_0, 271 .mode = SPI_MODE_0,
329 }, 272 },
330#endif 273#endif
@@ -334,7 +277,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
334 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 277 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
335 .bus_num = 0, 278 .bus_num = 0,
336 .chip_select = 1, 279 .chip_select = 1,
337 .controller_data = &spidev_chip_info,
338 }, 280 },
339#endif 281#endif
340#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) 282#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -343,7 +285,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
343 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 285 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
344 .bus_num = 0, 286 .bus_num = 0,
345 .chip_select = 1, 287 .chip_select = 1,
346 .controller_data = &lq035q1_spi_chip_info,
347 .mode = SPI_CPHA | SPI_CPOL, 288 .mode = SPI_CPHA | SPI_CPOL,
348 }, 289 },
349#endif 290#endif
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index 50fc5c89e379..55c127908815 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -138,32 +138,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
138/* SPI flash chip (m25p64) */ 138/* SPI flash chip (m25p64) */
139static struct bfin5xx_spi_chip spi_flash_chip_info = { 139static struct bfin5xx_spi_chip spi_flash_chip_info = {
140 .enable_dma = 0, /* use dma transfer with this chip*/ 140 .enable_dma = 0, /* use dma transfer with this chip*/
141 .bits_per_word = 8,
142};
143#endif
144
145#if defined(CONFIG_BFIN_SPI_ADC) \
146 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
147/* SPI ADC chip */
148static struct bfin5xx_spi_chip spi_adc_chip_info = {
149 .enable_dma = 1, /* use dma transfer with this chip*/
150 .bits_per_word = 16,
151}; 141};
152#endif 142#endif
153 143
154#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 144#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
155static struct bfin5xx_spi_chip mmc_spi_chip_info = { 145static struct bfin5xx_spi_chip mmc_spi_chip_info = {
156 .enable_dma = 0, 146 .enable_dma = 0,
157 .bits_per_word = 8,
158}; 147};
159#endif 148#endif
160 149
161#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 150#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
162static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
163 .enable_dma = 0,
164 .bits_per_word = 16,
165};
166
167static const struct ad7877_platform_data bfin_ad7877_ts_info = { 151static const struct ad7877_platform_data bfin_ad7877_ts_info = {
168 .model = 7877, 152 .model = 7877,
169 .vref_delay_usecs = 50, /* internal, no capacitor */ 153 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -179,21 +163,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
179}; 163};
180#endif 164#endif
181 165
182#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
183 && defined(CONFIG_SND_SOC_WM8731_SPI)
184static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
185 .enable_dma = 0,
186 .bits_per_word = 16,
187};
188#endif
189
190#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
191static struct bfin5xx_spi_chip spidev_chip_info = {
192 .enable_dma = 0,
193 .bits_per_word = 8,
194};
195#endif
196
197static struct spi_board_info bfin_spi_board_info[] __initdata = { 166static struct spi_board_info bfin_spi_board_info[] __initdata = {
198#if defined(CONFIG_MTD_M25P80) \ 167#if defined(CONFIG_MTD_M25P80) \
199 || defined(CONFIG_MTD_M25P80_MODULE) 168 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -209,18 +178,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
209 }, 178 },
210#endif 179#endif
211 180
212#if defined(CONFIG_BFIN_SPI_ADC) \
213 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
214 {
215 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
216 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
217 .bus_num = 0, /* Framework bus number */
218 .chip_select = 1, /* Framework chip select. */
219 .platform_data = NULL, /* No spi_driver specific config */
220 .controller_data = &spi_adc_chip_info,
221 },
222#endif
223
224#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 181#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
225 { 182 {
226 .modalias = "mmc_spi", 183 .modalias = "mmc_spi",
@@ -239,7 +196,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
239 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 196 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
240 .bus_num = 0, 197 .bus_num = 0,
241 .chip_select = 2, 198 .chip_select = 2,
242 .controller_data = &spi_ad7877_chip_info,
243 }, 199 },
244#endif 200#endif
245#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ 201#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
@@ -249,7 +205,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
249 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 205 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
250 .bus_num = 0, 206 .bus_num = 0,
251 .chip_select = 5, 207 .chip_select = 5,
252 .controller_data = &spi_wm8731_chip_info,
253 .mode = SPI_MODE_0, 208 .mode = SPI_MODE_0,
254 }, 209 },
255#endif 210#endif
@@ -259,7 +214,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
259 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 214 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
260 .bus_num = 0, 215 .bus_num = 0,
261 .chip_select = 1, 216 .chip_select = 1,
262 .controller_data = &spidev_chip_info,
263 }, 217 },
264#endif 218#endif
265#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) 219#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -268,7 +222,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
268 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 222 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
269 .bus_num = 0, 223 .bus_num = 0,
270 .chip_select = 1, 224 .chip_select = 1,
271 .controller_data = &lq035q1_spi_chip_info,
272 .mode = SPI_CPHA | SPI_CPOL, 225 .mode = SPI_CPHA | SPI_CPOL,
273 }, 226 },
274#endif 227#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index d2f076fbbc9e..56383f7cbc07 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -11,10 +11,9 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List 14 * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
18#if __SILICON_REVISION__ < 0 17#if __SILICON_REVISION__ < 0
19# error will not work on BF518 silicon version 18# error will not work on BF518 silicon version
20#endif 19#endif
@@ -77,19 +76,29 @@
77/* False Hardware Error when RETI Points to Invalid Memory */ 76/* False Hardware Error when RETI Points to Invalid Memory */
78#define ANOMALY_05000461 (1) 77#define ANOMALY_05000461 (1)
79/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 78/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
80#define ANOMALY_05000462 (1) 79#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
81/* PLL Latches Incorrect Settings During Reset */
82#define ANOMALY_05000469 (1)
83/* Incorrect Default MSEL Value in PLL_CTL */ 80/* Incorrect Default MSEL Value in PLL_CTL */
84#define ANOMALY_05000472 (1) 81#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
85/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ 82/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
86#define ANOMALY_05000473 (1) 83#define ANOMALY_05000473 (1)
87/* TESTSET Instruction Cannot Be Interrupted */ 84/* TESTSET Instruction Cannot Be Interrupted */
88#define ANOMALY_05000477 (1) 85#define ANOMALY_05000477 (1)
89/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 86/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
90#define ANOMALY_05000481 (1) 87#define ANOMALY_05000481 (1)
91/* IFLUSH sucks at life */ 88/* PLL Latches Incorrect Settings During Reset */
89#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
90/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
91#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
92/* SPI Master Boot Can Fail Under Certain Conditions */
93#define ANOMALY_05000490 (1)
94/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
92#define ANOMALY_05000491 (1) 95#define ANOMALY_05000491 (1)
96/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
97#define ANOMALY_05000494 (1)
98/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
99#define ANOMALY_05000498 (1)
100/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
101#define ANOMALY_05000501 (1)
93 102
94/* Anomalies that don't exist on this proc */ 103/* Anomalies that don't exist on this proc */
95#define ANOMALY_05000099 (0) 104#define ANOMALY_05000099 (0)
@@ -157,6 +166,5 @@
157#define ANOMALY_05000474 (0) 166#define ANOMALY_05000474 (0)
158#define ANOMALY_05000475 (0) 167#define ANOMALY_05000475 (0)
159#define ANOMALY_05000480 (0) 168#define ANOMALY_05000480 (0)
160#define ANOMALY_05000485 (0)
161 169
162#endif 170#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
index cd84a569b04e..b3b806f468da 100644
--- a/arch/blackfin/mach-bf518/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf518/include/mach/portmux.h
@@ -81,9 +81,15 @@
81#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) 81#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
82#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) 82#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
83 83
84#ifndef CONFIG_BF518_PPI_TMR_PG12
85#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
86#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
87#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
88#else
84#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) 89#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
85#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) 90#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
86#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) 91#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
92#endif
87#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) 93#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
88 94
89/* SPI Port Mux */ 95/* SPI Port Mux */
@@ -139,9 +145,15 @@
139#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1)) 145#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
140 146
141/* Timer */ 147/* Timer */
148#ifndef CONFIG_BF518_PPI_TMR_PG12
142#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) 149#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
143#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) 150#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
144#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) 151#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
152#else
153#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
154#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
155#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
156#endif
145#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) 157#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
146#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) 158#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
147#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2)) 159#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
@@ -158,23 +170,33 @@
158#define P_TWI0_SDA (P_DONTCARE) 170#define P_TWI0_SDA (P_DONTCARE)
159 171
160/* PWM */ 172/* PWM */
161#define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) 173#ifndef CONFIG_BF518_PWM_PORTF_PORTG
162#define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) 174#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
163#define P_PWM0_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) 175#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
164#define P_PWM0_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) 176#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
165#define P_PWM0_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) 177#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
166#define P_PWM0_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) 178#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
167#define P_PWM0_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) 179#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
168 180#else
169#define P_PWM1_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2)) 181#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
170#define P_PWM1_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) 182#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
171#define P_PWM1_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) 183#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
172#define P_PWM1_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) 184#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
173#define P_PWM1_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) 185#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
174#define P_PWM1_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) 186#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
175#define P_PWM1_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) 187#endif
176 188
189#ifndef CONFIG_BF518_PWM_SYNC_PF15
190#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
191#else
192#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
193#endif
194
195#ifndef CONFIG_BF518_PWM_TRIPB_PG14
196#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
197#else
177#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) 198#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
199#endif
178 200
179/* RSI */ 201/* RSI */
180#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) 202#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index ccab4c689dc3..c04df43f6391 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -265,29 +265,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
265/* SPI flash chip (m25p64) */ 265/* SPI flash chip (m25p64) */
266static struct bfin5xx_spi_chip spi_flash_chip_info = { 266static struct bfin5xx_spi_chip spi_flash_chip_info = {
267 .enable_dma = 0, /* use dma transfer with this chip*/ 267 .enable_dma = 0, /* use dma transfer with this chip*/
268 .bits_per_word = 8,
269};
270#endif
271
272#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
273 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
274static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
275 .enable_dma = 0,
276 .bits_per_word = 16,
277}; 268};
278#endif 269#endif
279 270
280#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 271#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
281static struct bfin5xx_spi_chip mmc_spi_chip_info = { 272static struct bfin5xx_spi_chip mmc_spi_chip_info = {
282 .enable_dma = 0, 273 .enable_dma = 0,
283 .bits_per_word = 8,
284};
285#endif
286
287#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
288static struct bfin5xx_spi_chip spidev_chip_info = {
289 .enable_dma = 0,
290 .bits_per_word = 8,
291}; 274};
292#endif 275#endif
293 276
@@ -328,7 +311,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
328 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 311 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
329 .bus_num = 0, 312 .bus_num = 0,
330 .chip_select = 4, 313 .chip_select = 4,
331 .controller_data = &ad1836_spi_chip_info,
332 }, 314 },
333#endif 315#endif
334#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 316#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -347,7 +329,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
347 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 329 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
348 .bus_num = 0, 330 .bus_num = 0,
349 .chip_select = 1, 331 .chip_select = 1,
350 .controller_data = &spidev_chip_info,
351 }, 332 },
352#endif 333#endif
353}; 334};
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index c9d6dc88f0e6..6400341cc230 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -354,40 +354,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
354/* SPI flash chip (m25p64) */ 354/* SPI flash chip (m25p64) */
355static struct bfin5xx_spi_chip spi_flash_chip_info = { 355static struct bfin5xx_spi_chip spi_flash_chip_info = {
356 .enable_dma = 0, /* use dma transfer with this chip*/ 356 .enable_dma = 0, /* use dma transfer with this chip*/
357 .bits_per_word = 8,
358};
359#endif
360
361#if defined(CONFIG_BFIN_SPI_ADC) \
362 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
363/* SPI ADC chip */
364static struct bfin5xx_spi_chip spi_adc_chip_info = {
365 .enable_dma = 1, /* use dma transfer with this chip*/
366 .bits_per_word = 16,
367};
368#endif
369
370#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
371 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
372static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
373 .enable_dma = 0,
374 .bits_per_word = 16,
375}; 357};
376#endif 358#endif
377 359
378#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 360#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
379static struct bfin5xx_spi_chip mmc_spi_chip_info = { 361static struct bfin5xx_spi_chip mmc_spi_chip_info = {
380 .enable_dma = 0, 362 .enable_dma = 0,
381 .bits_per_word = 8,
382}; 363};
383#endif 364#endif
384 365
385#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 366#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
386static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
387 .enable_dma = 0,
388 .bits_per_word = 16,
389};
390
391static const struct ad7877_platform_data bfin_ad7877_ts_info = { 367static const struct ad7877_platform_data bfin_ad7877_ts_info = {
392 .model = 7877, 368 .model = 7877,
393 .vref_delay_usecs = 50, /* internal, no capacitor */ 369 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -403,21 +379,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
403}; 379};
404#endif 380#endif
405 381
406#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
407 && defined(CONFIG_SND_SOC_WM8731_SPI)
408static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
409 .enable_dma = 0,
410 .bits_per_word = 16,
411};
412#endif
413
414#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
415static struct bfin5xx_spi_chip spidev_chip_info = {
416 .enable_dma = 0,
417 .bits_per_word = 8,
418};
419#endif
420
421static struct spi_board_info bfin_spi_board_info[] __initdata = { 382static struct spi_board_info bfin_spi_board_info[] __initdata = {
422#if defined(CONFIG_MTD_M25P80) \ 383#if defined(CONFIG_MTD_M25P80) \
423 || defined(CONFIG_MTD_M25P80_MODULE) 384 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -433,18 +394,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
433 }, 394 },
434#endif 395#endif
435 396
436#if defined(CONFIG_BFIN_SPI_ADC) \
437 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
438 {
439 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
440 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
441 .bus_num = 0, /* Framework bus number */
442 .chip_select = 1, /* Framework chip select. */
443 .platform_data = NULL, /* No spi_driver specific config */
444 .controller_data = &spi_adc_chip_info,
445 },
446#endif
447
448#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ 397#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
449 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 398 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
450 { 399 {
@@ -452,7 +401,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
452 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 401 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
453 .bus_num = 0, 402 .bus_num = 0,
454 .chip_select = 4, 403 .chip_select = 4,
455 .controller_data = &ad1836_spi_chip_info,
456 }, 404 },
457#endif 405#endif
458#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 406#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -473,7 +421,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
473 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 421 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
474 .bus_num = 0, 422 .bus_num = 0,
475 .chip_select = 2, 423 .chip_select = 2,
476 .controller_data = &spi_ad7877_chip_info,
477 }, 424 },
478#endif 425#endif
479#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ 426#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
@@ -483,7 +430,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
483 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 430 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
484 .bus_num = 0, 431 .bus_num = 0,
485 .chip_select = 5, 432 .chip_select = 5,
486 .controller_data = &spi_wm8731_chip_info,
487 .mode = SPI_MODE_0, 433 .mode = SPI_MODE_0,
488 }, 434 },
489#endif 435#endif
@@ -493,7 +439,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
493 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 439 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
494 .bus_num = 0, 440 .bus_num = 0,
495 .chip_select = 1, 441 .chip_select = 1,
496 .controller_data = &spidev_chip_info,
497 }, 442 },
498#endif 443#endif
499}; 444};
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index b7101aa6e3aa..6dbb1b403763 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -253,32 +253,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
253/* SPI flash chip (sst25wf040) */ 253/* SPI flash chip (sst25wf040) */
254static struct bfin5xx_spi_chip spi_flash_chip_info = { 254static struct bfin5xx_spi_chip spi_flash_chip_info = {
255 .enable_dma = 0, /* use dma transfer with this chip*/ 255 .enable_dma = 0, /* use dma transfer with this chip*/
256 .bits_per_word = 8,
257};
258#endif
259
260#if defined(CONFIG_BFIN_SPI_ADC) \
261 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
262/* SPI ADC chip */
263static struct bfin5xx_spi_chip spi_adc_chip_info = {
264 .enable_dma = 1, /* use dma transfer with this chip*/
265 .bits_per_word = 16,
266}; 256};
267#endif 257#endif
268 258
269#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 259#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
270static struct bfin5xx_spi_chip mmc_spi_chip_info = { 260static struct bfin5xx_spi_chip mmc_spi_chip_info = {
271 .enable_dma = 0, 261 .enable_dma = 0,
272 .bits_per_word = 8,
273}; 262};
274#endif 263#endif
275 264
276#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 265#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
277static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
278 .enable_dma = 0,
279 .bits_per_word = 16,
280};
281
282static const struct ad7877_platform_data bfin_ad7877_ts_info = { 266static const struct ad7877_platform_data bfin_ad7877_ts_info = {
283 .model = 7877, 267 .model = 7877,
284 .vref_delay_usecs = 50, /* internal, no capacitor */ 268 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -311,35 +295,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
311}; 295};
312#endif 296#endif
313 297
314#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
315static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
316 .enable_dma = 0,
317 .bits_per_word = 16,
318};
319#endif
320
321#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
322 && defined(CONFIG_SND_SOC_WM8731_SPI)
323static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
324 .enable_dma = 0,
325 .bits_per_word = 16,
326};
327#endif
328
329#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
330static struct bfin5xx_spi_chip spidev_chip_info = {
331 .enable_dma = 0,
332 .bits_per_word = 8,
333};
334#endif
335
336#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
337static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
338 .enable_dma = 0,
339 .bits_per_word = 8,
340};
341#endif
342
343static struct spi_board_info bfin_spi_board_info[] __initdata = { 298static struct spi_board_info bfin_spi_board_info[] __initdata = {
344#if defined(CONFIG_MTD_M25P80) \ 299#if defined(CONFIG_MTD_M25P80) \
345 || defined(CONFIG_MTD_M25P80_MODULE) 300 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -355,18 +310,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
355 }, 310 },
356#endif 311#endif
357 312
358#if defined(CONFIG_BFIN_SPI_ADC) \
359 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
360 {
361 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
362 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
363 .bus_num = 0, /* Framework bus number */
364 .chip_select = 1, /* Framework chip select. */
365 .platform_data = NULL, /* No spi_driver specific config */
366 .controller_data = &spi_adc_chip_info,
367 },
368#endif
369
370#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 313#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
371 { 314 {
372 .modalias = "mmc_spi", 315 .modalias = "mmc_spi",
@@ -385,7 +328,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
385 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 328 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
386 .bus_num = 0, 329 .bus_num = 0,
387 .chip_select = 2, 330 .chip_select = 2,
388 .controller_data = &spi_ad7877_chip_info,
389 }, 331 },
390#endif 332#endif
391#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) 333#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -396,7 +338,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
396 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 338 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
397 .bus_num = 0, 339 .bus_num = 0,
398 .chip_select = 5, 340 .chip_select = 5,
399 .controller_data = &spi_ad7879_chip_info,
400 .mode = SPI_CPHA | SPI_CPOL, 341 .mode = SPI_CPHA | SPI_CPOL,
401 }, 342 },
402#endif 343#endif
@@ -407,7 +348,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
407 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 348 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
408 .bus_num = 0, 349 .bus_num = 0,
409 .chip_select = 5, 350 .chip_select = 5,
410 .controller_data = &spi_wm8731_chip_info,
411 .mode = SPI_MODE_0, 351 .mode = SPI_MODE_0,
412 }, 352 },
413#endif 353#endif
@@ -417,7 +357,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
417 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 357 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
418 .bus_num = 0, 358 .bus_num = 0,
419 .chip_select = 1, 359 .chip_select = 1,
420 .controller_data = &spidev_chip_info,
421 }, 360 },
422#endif 361#endif
423#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) 362#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -426,7 +365,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
426 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 365 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
427 .bus_num = 0, 366 .bus_num = 0,
428 .chip_select = 1, 367 .chip_select = 1,
429 .controller_data = &lq035q1_spi_chip_info,
430 .mode = SPI_CPHA | SPI_CPOL, 368 .mode = SPI_CPHA | SPI_CPOL,
431 }, 369 },
432#endif 370#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index e67ac7720668..4e9dc9cf8241 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -409,6 +409,9 @@ static struct resource net2272_bfin_resources[] = {
409 .end = 0x20300000 + 0x100, 409 .end = 0x20300000 + 0x100,
410 .flags = IORESOURCE_MEM, 410 .flags = IORESOURCE_MEM,
411 }, { 411 }, {
412 .start = 1,
413 .flags = IORESOURCE_BUS,
414 }, {
412 .start = IRQ_PF7, 415 .start = IRQ_PF7,
413 .end = IRQ_PF7, 416 .end = IRQ_PF7,
414 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 417 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -448,40 +451,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
448/* SPI flash chip (m25p64) */ 451/* SPI flash chip (m25p64) */
449static struct bfin5xx_spi_chip spi_flash_chip_info = { 452static struct bfin5xx_spi_chip spi_flash_chip_info = {
450 .enable_dma = 0, /* use dma transfer with this chip*/ 453 .enable_dma = 0, /* use dma transfer with this chip*/
451 .bits_per_word = 8,
452};
453#endif
454
455#if defined(CONFIG_BFIN_SPI_ADC) \
456 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
457/* SPI ADC chip */
458static struct bfin5xx_spi_chip spi_adc_chip_info = {
459 .enable_dma = 1, /* use dma transfer with this chip*/
460 .bits_per_word = 16,
461};
462#endif
463
464#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
465 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
466static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
467 .enable_dma = 0,
468 .bits_per_word = 16,
469}; 454};
470#endif 455#endif
471 456
472#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 457#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
473static struct bfin5xx_spi_chip mmc_spi_chip_info = { 458static struct bfin5xx_spi_chip mmc_spi_chip_info = {
474 .enable_dma = 0, 459 .enable_dma = 0,
475 .bits_per_word = 8,
476}; 460};
477#endif 461#endif
478 462
479#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 463#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
480static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
481 .enable_dma = 0,
482 .bits_per_word = 16,
483};
484
485static const struct ad7877_platform_data bfin_ad7877_ts_info = { 464static const struct ad7877_platform_data bfin_ad7877_ts_info = {
486 .model = 7877, 465 .model = 7877,
487 .vref_delay_usecs = 50, /* internal, no capacitor */ 466 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -513,20 +492,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
513}; 492};
514#endif 493#endif
515 494
516#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
517static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
518 .enable_dma = 0,
519 .bits_per_word = 16,
520};
521#endif
522
523#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
524static struct bfin5xx_spi_chip spidev_chip_info = {
525 .enable_dma = 0,
526 .bits_per_word = 8,
527};
528#endif
529
530#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ 495#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
531 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) 496 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
532 497
@@ -574,9 +539,25 @@ static struct resource bfin_snd_resources[][4] = {
574 BFIN_SND_RES(0), 539 BFIN_SND_RES(0),
575 BFIN_SND_RES(1), 540 BFIN_SND_RES(1),
576}; 541};
542#endif
577 543
578static struct platform_device bfin_pcm = { 544#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
579 .name = "bfin-pcm-audio", 545static struct platform_device bfin_i2s_pcm = {
546 .name = "bfin-i2s-pcm-audio",
547 .id = -1,
548};
549#endif
550
551#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
552static struct platform_device bfin_tdm_pcm = {
553 .name = "bfin-tdm-pcm-audio",
554 .id = -1,
555};
556#endif
557
558#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
559static struct platform_device bfin_ac97_pcm = {
560 .name = "bfin-ac97-pcm-audio",
580 .id = -1, 561 .id = -1,
581}; 562};
582#endif 563#endif
@@ -605,13 +586,6 @@ static struct platform_device bfin_tdm = {
605}; 586};
606#endif 587#endif
607 588
608#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
609static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
610 .enable_dma = 0,
611 .bits_per_word = 8,
612};
613#endif
614
615static struct spi_board_info bfin_spi_board_info[] __initdata = { 589static struct spi_board_info bfin_spi_board_info[] __initdata = {
616#if defined(CONFIG_MTD_M25P80) \ 590#if defined(CONFIG_MTD_M25P80) \
617 || defined(CONFIG_MTD_M25P80_MODULE) 591 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -627,18 +601,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
627 }, 601 },
628#endif 602#endif
629 603
630#if defined(CONFIG_BFIN_SPI_ADC) \
631 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
632 {
633 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
634 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
635 .bus_num = 0, /* Framework bus number */
636 .chip_select = 1, /* Framework chip select. */
637 .platform_data = NULL, /* No spi_driver specific config */
638 .controller_data = &spi_adc_chip_info,
639 },
640#endif
641
642#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ 604#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
643 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 605 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
644 { 606 {
@@ -647,7 +609,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
647 .bus_num = 0, 609 .bus_num = 0,
648 .chip_select = 4, 610 .chip_select = 4,
649 .platform_data = "ad1836", 611 .platform_data = "ad1836",
650 .controller_data = &ad1836_spi_chip_info,
651 .mode = SPI_MODE_3, 612 .mode = SPI_MODE_3,
652 }, 613 },
653#endif 614#endif
@@ -670,7 +631,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
670 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 631 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
671 .bus_num = 0, 632 .bus_num = 0,
672 .chip_select = 2, 633 .chip_select = 2,
673 .controller_data = &spi_ad7877_chip_info,
674 }, 634 },
675#endif 635#endif
676#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) 636#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -681,7 +641,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
681 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 641 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
682 .bus_num = 0, 642 .bus_num = 0,
683 .chip_select = 3, 643 .chip_select = 3,
684 .controller_data = &spi_ad7879_chip_info,
685 .mode = SPI_CPHA | SPI_CPOL, 644 .mode = SPI_CPHA | SPI_CPOL,
686 }, 645 },
687#endif 646#endif
@@ -691,7 +650,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
691 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 650 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
692 .bus_num = 0, 651 .bus_num = 0,
693 .chip_select = 1, 652 .chip_select = 1,
694 .controller_data = &spidev_chip_info,
695 }, 653 },
696#endif 654#endif
697#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) 655#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -700,7 +658,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
700 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 658 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
701 .bus_num = 0, 659 .bus_num = 0,
702 .chip_select = 7, 660 .chip_select = 7,
703 .controller_data = &lq035q1_spi_chip_info,
704 .mode = SPI_CPHA | SPI_CPOL, 661 .mode = SPI_CPHA | SPI_CPOL,
705 }, 662 },
706#endif 663#endif
@@ -1276,9 +1233,16 @@ static struct platform_device *stamp_devices[] __initdata = {
1276 &ezkit_flash_device, 1233 &ezkit_flash_device,
1277#endif 1234#endif
1278 1235
1279#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ 1236#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
1280 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) 1237 &bfin_i2s_pcm,
1281 &bfin_pcm, 1238#endif
1239
1240#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
1241 &bfin_tdm_pcm,
1242#endif
1243
1244#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
1245 &bfin_ac97_pcm,
1282#endif 1246#endif
1283 1247
1284#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 1248#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index 18d303dd5627..ec4bc7429c9f 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -314,29 +314,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
314/* SPI flash chip (m25p64) */ 314/* SPI flash chip (m25p64) */
315static struct bfin5xx_spi_chip spi_flash_chip_info = { 315static struct bfin5xx_spi_chip spi_flash_chip_info = {
316 .enable_dma = 0, /* use dma transfer with this chip*/ 316 .enable_dma = 0, /* use dma transfer with this chip*/
317 .bits_per_word = 8,
318};
319#endif
320
321#if defined(CONFIG_BFIN_SPI_ADC) \
322 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
323/* SPI ADC chip */
324static struct bfin5xx_spi_chip spi_adc_chip_info = {
325 .enable_dma = 0, /* use dma transfer with this chip*/
326/*
327 * tll6527m V1.0 does not support native spi slave selects
328 * hence DMA mode will not be useful since the ADC needs
329 * CS to toggle for each sample and cs_change_per_word
330 * seems to be removed from spi_bfin5xx.c
331 */
332 .bits_per_word = 16,
333}; 317};
334#endif 318#endif
335 319
336#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 320#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
337static struct bfin5xx_spi_chip mmc_spi_chip_info = { 321static struct bfin5xx_spi_chip mmc_spi_chip_info = {
338 .enable_dma = 0, 322 .enable_dma = 0,
339 .bits_per_word = 8,
340}; 323};
341#endif 324#endif
342 325
@@ -359,21 +342,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
359}; 342};
360#endif 343#endif
361 344
362#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) \
363 || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
364static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
365 .enable_dma = 0,
366 .bits_per_word = 16,
367};
368#endif
369
370#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
371static struct bfin5xx_spi_chip spidev_chip_info = {
372 .enable_dma = 0,
373 .bits_per_word = 8,
374};
375#endif
376
377#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) 345#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
378static struct platform_device bfin_i2s = { 346static struct platform_device bfin_i2s = {
379 .name = "bfin-i2s", 347 .name = "bfin-i2s",
@@ -382,24 +350,7 @@ static struct platform_device bfin_i2s = {
382}; 350};
383#endif 351#endif
384 352
385#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
386static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
387 .enable_dma = 0,
388 .bits_per_word = 8,
389};
390#endif
391
392#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE) 353#if defined(CONFIG_GPIO_MCP23S08) || defined(CONFIG_GPIO_MCP23S08_MODULE)
393static struct bfin5xx_spi_chip spi_mcp23s08_sys_chip_info = {
394 .enable_dma = 0,
395 .bits_per_word = 8,
396};
397
398static struct bfin5xx_spi_chip spi_mcp23s08_usr_chip_info = {
399 .enable_dma = 0,
400 .bits_per_word = 8,
401};
402
403#include <linux/spi/mcp23s08.h> 354#include <linux/spi/mcp23s08.h>
404static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = { 355static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
405 .chip[0].is_present = true, 356 .chip[0].is_present = true,
@@ -429,22 +380,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
429 }, 380 },
430#endif 381#endif
431 382
432#if defined(CONFIG_BFIN_SPI_ADC)
433 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
434 {
435 .modalias = "bfin_spi_adc",
436 /* Name of spi_driver for this device */
437 .max_speed_hz = 10000000,
438 /* max spi clock (SCK) speed in HZ */
439 .bus_num = 0, /* Framework bus number */
440 .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
441 /* Framework chip select. */
442 .platform_data = NULL, /* No spi_driver specific config */
443 .controller_data = &spi_adc_chip_info,
444 .mode = SPI_MODE_0,
445 },
446#endif
447
448#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 383#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
449 { 384 {
450 .modalias = "mmc_spi", 385 .modalias = "mmc_spi",
@@ -470,7 +405,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
470 /* max spi clock (SCK) speed in HZ */ 405 /* max spi clock (SCK) speed in HZ */
471 .bus_num = 0, 406 .bus_num = 0,
472 .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS, 407 .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
473 .controller_data = &spi_ad7879_chip_info,
474 .mode = SPI_CPHA | SPI_CPOL, 408 .mode = SPI_CPHA | SPI_CPOL,
475 }, 409 },
476#endif 410#endif
@@ -482,7 +416,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
482 .bus_num = 0, 416 .bus_num = 0,
483 .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS, 417 .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
484 .mode = SPI_CPHA | SPI_CPOL, 418 .mode = SPI_CPHA | SPI_CPOL,
485 .controller_data = &spidev_chip_info,
486 }, 419 },
487#endif 420#endif
488#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) 421#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -491,7 +424,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
491 .max_speed_hz = 20000000, 424 .max_speed_hz = 20000000,
492 .bus_num = 0, 425 .bus_num = 0,
493 .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS, 426 .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
494 .controller_data = &lq035q1_spi_chip_info,
495 .mode = SPI_CPHA | SPI_CPOL, 427 .mode = SPI_CPHA | SPI_CPOL,
496 }, 428 },
497#endif 429#endif
@@ -502,7 +434,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
502 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 434 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
503 .bus_num = 0, 435 .bus_num = 0,
504 .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS, 436 .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
505 .controller_data = &spi_mcp23s08_sys_chip_info,
506 .mode = SPI_CPHA | SPI_CPOL, 437 .mode = SPI_CPHA | SPI_CPOL,
507 }, 438 },
508 { 439 {
@@ -511,7 +442,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
511 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 442 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
512 .bus_num = 0, 443 .bus_num = 0,
513 .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS, 444 .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
514 .controller_data = &spi_mcp23s08_usr_chip_info,
515 .mode = SPI_CPHA | SPI_CPOL, 445 .mode = SPI_CPHA | SPI_CPOL,
516 }, 446 },
517#endif 447#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index e66a7e89cd3c..688470611e15 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -11,8 +11,8 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List 14 * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
15 * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List 15 * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
16 */ 16 */
17 17
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
@@ -57,7 +57,7 @@
57/* Incorrect Access of OTP_STATUS During otp_write() Function */ 57/* Incorrect Access of OTP_STATUS During otp_write() Function */
58#define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) 58#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
59/* Host DMA Boot Modes Are Not Functional */ 59/* Host DMA Boot Modes Are Not Functional */
60#define ANOMALY_05000330 (__SILICON_REVISION__ < 2) 60#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
61/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ 61/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
62#define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) 62#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
63/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 63/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
@@ -135,7 +135,7 @@
135/* Incorrect Default Internal Voltage Regulator Setting */ 135/* Incorrect Default Internal Voltage Regulator Setting */
136#define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) 136#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
137/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ 137/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
138#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) 138#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
139/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ 139/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
140#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) 140#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
141/* DEB2_URGENT Bit Not Functional */ 141/* DEB2_URGENT Bit Not Functional */
@@ -181,11 +181,11 @@
181/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 181/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
182#define ANOMALY_05000443 (1) 182#define ANOMALY_05000443 (1)
183/* The WURESET Bit in the SYSCR Register is not Functional */ 183/* The WURESET Bit in the SYSCR Register is not Functional */
184#define ANOMALY_05000445 (1) 184#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
185/* USB DMA Mode 1 Short Packet Data Corruption */ 185/* USB DMA Short Packet Data Corruption */
186#define ANOMALY_05000450 (1) 186#define ANOMALY_05000450 (1)
187/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ 187/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
188#define ANOMALY_05000451 (1) 188#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
189/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ 189/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
190#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) 190#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
191/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ 191/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
@@ -198,19 +198,19 @@
198#define ANOMALY_05000461 (1) 198#define ANOMALY_05000461 (1)
199/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 199/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
200#define ANOMALY_05000462 (1) 200#define ANOMALY_05000462 (1)
201/* USB Rx DMA hang */ 201/* USB Rx DMA Hang */
202#define ANOMALY_05000465 (1) 202#define ANOMALY_05000465 (1)
203/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ 203/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
204#define ANOMALY_05000466 (1) 204#define ANOMALY_05000466 (1)
205/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ 205/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
206#define ANOMALY_05000467 (1) 206#define ANOMALY_05000467 (1)
207/* PLL Latches Incorrect Settings During Reset */ 207/* PLL Latches Incorrect Settings During Reset */
208#define ANOMALY_05000469 (1) 208#define ANOMALY_05000469 (1)
209/* Incorrect Default MSEL Value in PLL_CTL */ 209/* Incorrect Default MSEL Value in PLL_CTL */
210#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) 210#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
211/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 211/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
212#define ANOMALY_05000473 (1) 212#define ANOMALY_05000473 (1)
213/* Possible Lockup Condition whem Modifying PLL from External Memory */ 213/* Possible Lockup Condition when Modifying PLL from External Memory */
214#define ANOMALY_05000475 (1) 214#define ANOMALY_05000475 (1)
215/* TESTSET Instruction Cannot Be Interrupted */ 215/* TESTSET Instruction Cannot Be Interrupted */
216#define ANOMALY_05000477 (1) 216#define ANOMALY_05000477 (1)
@@ -219,11 +219,19 @@
219/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ 219/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
220#define ANOMALY_05000483 (1) 220#define ANOMALY_05000483 (1)
221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ 221/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) 222#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
223/* The CODEC Zero-Cross Detect Feature is not Functional */ 223/* The CODEC Zero-Cross Detect Feature is not Functional */
224#define ANOMALY_05000487 (1) 224#define ANOMALY_05000487 (1)
225/* IFLUSH sucks at life */ 225/* SPI Master Boot Can Fail Under Certain Conditions */
226#define ANOMALY_05000490 (1)
227/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
226#define ANOMALY_05000491 (1) 228#define ANOMALY_05000491 (1)
229/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
230#define ANOMALY_05000494 (1)
231/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
232#define ANOMALY_05000498 (1)
233/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
234#define ANOMALY_05000501 (1)
227 235
228/* Anomalies that don't exist on this proc */ 236/* Anomalies that don't exist on this proc */
229#define ANOMALY_05000099 (0) 237#define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index d4bfcea56828..eb325ed6607e 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -159,22 +159,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
159/* SPI flash chip (m25p64) */ 159/* SPI flash chip (m25p64) */
160static struct bfin5xx_spi_chip spi_flash_chip_info = { 160static struct bfin5xx_spi_chip spi_flash_chip_info = {
161 .enable_dma = 0, /* use dma transfer with this chip*/ 161 .enable_dma = 0, /* use dma transfer with this chip*/
162 .bits_per_word = 8,
163};
164#endif
165
166#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
167/* SPI ADC chip */
168static struct bfin5xx_spi_chip spi_adc_chip_info = {
169 .enable_dma = 1, /* use dma transfer with this chip*/
170 .bits_per_word = 16,
171};
172#endif
173
174#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
175static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
176 .enable_dma = 0,
177 .bits_per_word = 16,
178}; 162};
179#endif 163#endif
180 164
@@ -195,24 +179,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
195 }, 179 },
196#endif 180#endif
197 181
198#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
199 {
200 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
201 .max_speed_hz = 4, /* actual baudrate is SCLK/(2xspeed_hz) */
202 .bus_num = 1, /* Framework bus number */
203 .chip_select = 1, /* Framework chip select. */
204 .platform_data = NULL, /* No spi_driver specific config */
205 .controller_data = &spi_adc_chip_info,
206 },
207#endif
208
209#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 182#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
210 { 183 {
211 .modalias = "ad183x", 184 .modalias = "ad183x",
212 .max_speed_hz = 16, 185 .max_speed_hz = 16,
213 .bus_num = 1, 186 .bus_num = 1,
214 .chip_select = 4, 187 .chip_select = 4,
215 .controller_data = &ad1836_spi_chip_info,
216 }, 188 },
217#endif 189#endif
218 190
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 87b5af3693c1..b0ec825fb4ec 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -102,21 +102,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
102/* SPI flash chip (m25p64) */ 102/* SPI flash chip (m25p64) */
103static struct bfin5xx_spi_chip spi_flash_chip_info = { 103static struct bfin5xx_spi_chip spi_flash_chip_info = {
104 .enable_dma = 0, /* use dma transfer with this chip*/ 104 .enable_dma = 0, /* use dma transfer with this chip*/
105 .bits_per_word = 8,
106}; 105};
107#endif 106#endif
108 107
109#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 108#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
110static struct bfin5xx_spi_chip mmc_spi_chip_info = { 109static struct bfin5xx_spi_chip mmc_spi_chip_info = {
111 .enable_dma = 0, 110 .enable_dma = 0,
112 .bits_per_word = 8,
113};
114#endif
115
116#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
117static struct bfin5xx_spi_chip spidev_chip_info = {
118 .enable_dma = 0,
119 .bits_per_word = 8,
120}; 111};
121#endif 112#endif
122 113
@@ -151,7 +142,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
151 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 142 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
152 .bus_num = 0, 143 .bus_num = 0,
153 .chip_select = 7, 144 .chip_select = 7,
154 .controller_data = &spidev_chip_info,
155 }, 145 },
156#endif 146#endif
157}; 147};
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index 4d5604eaa7c2..14f54a31e74c 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -59,29 +59,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
59/* SPI flash chip (m25p64) */ 59/* SPI flash chip (m25p64) */
60static struct bfin5xx_spi_chip spi_flash_chip_info = { 60static struct bfin5xx_spi_chip spi_flash_chip_info = {
61 .enable_dma = 0, /* use dma transfer with this chip*/ 61 .enable_dma = 0, /* use dma transfer with this chip*/
62 .bits_per_word = 8,
63};
64#endif
65
66/* SPI ADC chip */
67#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
68static struct bfin5xx_spi_chip spi_adc_chip_info = {
69 .enable_dma = 1, /* use dma transfer with this chip*/
70 .bits_per_word = 16,
71};
72#endif
73
74#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
75static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
76 .enable_dma = 0,
77 .bits_per_word = 16,
78}; 62};
79#endif 63#endif
80 64
81#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 65#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
82static struct bfin5xx_spi_chip mmc_spi_chip_info = { 66static struct bfin5xx_spi_chip mmc_spi_chip_info = {
83 .enable_dma = 0, 67 .enable_dma = 0,
84 .bits_per_word = 8,
85}; 68};
86#endif 69#endif
87 70
@@ -99,24 +82,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
99 }, 82 },
100#endif 83#endif
101 84
102#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
103 {
104 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
105 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
106 .bus_num = 0, /* Framework bus number */
107 .chip_select = 2, /* Framework chip select. */
108 .platform_data = NULL, /* No spi_driver specific config */
109 .controller_data = &spi_adc_chip_info,
110 },
111#endif
112
113#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 85#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
114 { 86 {
115 .modalias = "ad183x", 87 .modalias = "ad183x",
116 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 88 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
117 .bus_num = 0, 89 .bus_num = 0,
118 .chip_select = 4, 90 .chip_select = 4,
119 .controller_data = &ad1836_spi_chip_info,
120 }, 91 },
121#endif 92#endif
122 93
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index b67b91d82242..ecd2801f050d 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -210,29 +210,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
210/* SPI flash chip (m25p64) */ 210/* SPI flash chip (m25p64) */
211static struct bfin5xx_spi_chip spi_flash_chip_info = { 211static struct bfin5xx_spi_chip spi_flash_chip_info = {
212 .enable_dma = 0, /* use dma transfer with this chip*/ 212 .enable_dma = 0, /* use dma transfer with this chip*/
213 .bits_per_word = 8,
214};
215#endif
216
217#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
218/* SPI ADC chip */
219static struct bfin5xx_spi_chip spi_adc_chip_info = {
220 .enable_dma = 1, /* use dma transfer with this chip*/
221 .bits_per_word = 16,
222};
223#endif
224
225#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
226static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
227 .enable_dma = 0,
228 .bits_per_word = 16,
229};
230#endif
231
232#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
233static struct bfin5xx_spi_chip spidev_chip_info = {
234 .enable_dma = 0,
235 .bits_per_word = 8,
236}; 213};
237#endif 214#endif
238 215
@@ -250,24 +227,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
250 }, 227 },
251#endif 228#endif
252 229
253#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
254 {
255 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
256 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
257 .bus_num = 0, /* Framework bus number */
258 .chip_select = 1, /* Framework chip select. */
259 .platform_data = NULL, /* No spi_driver specific config */
260 .controller_data = &spi_adc_chip_info,
261 },
262#endif
263
264#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 230#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
265 { 231 {
266 .modalias = "ad183x", 232 .modalias = "ad183x",
267 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 233 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
268 .bus_num = 0, 234 .bus_num = 0,
269 .chip_select = 4, 235 .chip_select = 4,
270 .controller_data = &ad1836_spi_chip_info,
271 }, 236 },
272#endif 237#endif
273#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 238#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -276,7 +241,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
276 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 241 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
277 .bus_num = 0, 242 .bus_num = 0,
278 .chip_select = 1, 243 .chip_select = 1,
279 .controller_data = &spidev_chip_info,
280 }, 244 },
281#endif 245#endif
282}; 246};
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index a377d8afea03..fbee77fa9211 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -110,7 +110,6 @@ static struct platform_device dm9000_device2 = {
110#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 110#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
111static struct bfin5xx_spi_chip mmc_spi_chip_info = { 111static struct bfin5xx_spi_chip mmc_spi_chip_info = {
112 .enable_dma = 0, /* if 1 - block!!! */ 112 .enable_dma = 0, /* if 1 - block!!! */
113 .bits_per_word = 8,
114}; 113};
115#endif 114#endif
116 115
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 43224ef00b8c..964a8e5f79b4 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -80,6 +80,9 @@ static struct resource net2272_bfin_resources[] = {
80 .end = 0x20300000 + 0x100, 80 .end = 0x20300000 + 0x100,
81 .flags = IORESOURCE_MEM, 81 .flags = IORESOURCE_MEM,
82 }, { 82 }, {
83 .start = 1,
84 .flags = IORESOURCE_BUS,
85 }, {
83 .start = IRQ_PF10, 86 .start = IRQ_PF10,
84 .end = IRQ_PF10, 87 .end = IRQ_PF10,
85 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 88 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -172,29 +175,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
172/* SPI flash chip (m25p64) */ 175/* SPI flash chip (m25p64) */
173static struct bfin5xx_spi_chip spi_flash_chip_info = { 176static struct bfin5xx_spi_chip spi_flash_chip_info = {
174 .enable_dma = 0, /* use dma transfer with this chip*/ 177 .enable_dma = 0, /* use dma transfer with this chip*/
175 .bits_per_word = 8,
176};
177#endif
178
179#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
180/* SPI ADC chip */
181static struct bfin5xx_spi_chip spi_adc_chip_info = {
182 .enable_dma = 1, /* use dma transfer with this chip*/
183 .bits_per_word = 16,
184};
185#endif
186
187#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
188static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
189 .enable_dma = 0,
190 .bits_per_word = 16,
191};
192#endif
193
194#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
195static struct bfin5xx_spi_chip spidev_chip_info = {
196 .enable_dma = 0,
197 .bits_per_word = 8,
198}; 178};
199#endif 179#endif
200 180
@@ -221,7 +201,6 @@ static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
221 201
222static struct bfin5xx_spi_chip mmc_spi_chip_info = { 202static struct bfin5xx_spi_chip mmc_spi_chip_info = {
223 .enable_dma = 0, 203 .enable_dma = 0,
224 .bits_per_word = 8,
225 .pio_interrupt = 0, 204 .pio_interrupt = 0,
226}; 205};
227#endif 206#endif
@@ -240,17 +219,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
240 }, 219 },
241#endif 220#endif
242 221
243#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
244 {
245 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
246 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
247 .bus_num = 0, /* Framework bus number */
248 .chip_select = 1, /* Framework chip select. */
249 .platform_data = NULL, /* No spi_driver specific config */
250 .controller_data = &spi_adc_chip_info,
251 },
252#endif
253
254#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 222#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
255 { 223 {
256 .modalias = "ad183x", 224 .modalias = "ad183x",
@@ -258,7 +226,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
258 .bus_num = 0, 226 .bus_num = 0,
259 .chip_select = 4, 227 .chip_select = 4,
260 .platform_data = "ad1836", /* only includes chip name for the moment */ 228 .platform_data = "ad1836", /* only includes chip name for the moment */
261 .controller_data = &ad1836_spi_chip_info,
262 .mode = SPI_MODE_3, 229 .mode = SPI_MODE_3,
263 }, 230 },
264#endif 231#endif
@@ -269,7 +236,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
269 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 236 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
270 .bus_num = 0, 237 .bus_num = 0,
271 .chip_select = 1, 238 .chip_select = 1,
272 .controller_data = &spidev_chip_info,
273 }, 239 },
274#endif 240#endif
275#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 241#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -659,6 +625,41 @@ static struct platform_device *stamp_devices[] __initdata = {
659#endif 625#endif
660}; 626};
661 627
628static int __init net2272_init(void)
629{
630#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
631 int ret;
632
633 /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */
634 ret = gpio_request(GPIO_PF0, "net2272");
635 if (ret)
636 return ret;
637
638 ret = gpio_request(GPIO_PF1, "net2272");
639 if (ret) {
640 gpio_free(GPIO_PF0);
641 return ret;
642 }
643
644 ret = gpio_request(GPIO_PF11, "net2272");
645 if (ret) {
646 gpio_free(GPIO_PF0);
647 gpio_free(GPIO_PF1);
648 return ret;
649 }
650
651 gpio_direction_output(GPIO_PF0, 0);
652 gpio_direction_output(GPIO_PF1, 1);
653
654 /* Reset the USB chip */
655 gpio_direction_output(GPIO_PF11, 0);
656 mdelay(2);
657 gpio_set_value(GPIO_PF11, 1);
658#endif
659
660 return 0;
661}
662
662static int __init stamp_init(void) 663static int __init stamp_init(void)
663{ 664{
664 int ret; 665 int ret;
@@ -685,6 +686,9 @@ static int __init stamp_init(void)
685 } 686 }
686#endif 687#endif
687 688
689 if (net2272_init())
690 pr_warning("unable to configure net2272; it probably won't work\n");
691
688 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 692 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
689 return 0; 693 return 0;
690} 694}
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 72aa59440f82..03f2b40912a3 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List 14 * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -152,7 +152,7 @@
152#define ANOMALY_05000277 (__SILICON_REVISION__ < 6) 152#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
153/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 153/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
154#define ANOMALY_05000278 (__SILICON_REVISION__ < 6) 154#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
155/* False Hardware Error Exception when ISR Context Is Not Restored */ 155/* False Hardware Error when ISR Context Is Not Restored */
156#define ANOMALY_05000281 (__SILICON_REVISION__ < 6) 156#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
157/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 157/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
158#define ANOMALY_05000282 (__SILICON_REVISION__ < 6) 158#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
@@ -210,18 +210,25 @@
210#define ANOMALY_05000462 (1) 210#define ANOMALY_05000462 (1)
211/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ 211/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
212#define ANOMALY_05000471 (1) 212#define ANOMALY_05000471 (1)
213/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 213/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
214#define ANOMALY_05000473 (1) 214#define ANOMALY_05000473 (1)
215/* Possible Lockup Condition whem Modifying PLL from External Memory */ 215/* Possible Lockup Condition when Modifying PLL from External Memory */
216#define ANOMALY_05000475 (1) 216#define ANOMALY_05000475 (1)
217/* TESTSET Instruction Cannot Be Interrupted */ 217/* TESTSET Instruction Cannot Be Interrupted */
218#define ANOMALY_05000477 (1) 218#define ANOMALY_05000477 (1)
219/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 219/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
220#define ANOMALY_05000481 (1) 220#define ANOMALY_05000481 (1)
221/* IFLUSH sucks at life */ 221/* PLL May Latch Incorrect Values Coming Out of Reset */
222#define ANOMALY_05000489 (1)
223/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
222#define ANOMALY_05000491 (1) 224#define ANOMALY_05000491 (1)
225/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
226#define ANOMALY_05000494 (1)
227/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
228#define ANOMALY_05000501 (1)
223 229
224/* These anomalies have been "phased" out of analog.com anomaly sheets and are 230/*
231 * These anomalies have been "phased" out of analog.com anomaly sheets and are
225 * here to show running on older silicon just isn't feasible. 232 * here to show running on older silicon just isn't feasible.
226 */ 233 */
227 234
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index d582b810e7a7..44fd8409db10 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -61,29 +61,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
61/* SPI flash chip (m25p64) */ 61/* SPI flash chip (m25p64) */
62static struct bfin5xx_spi_chip spi_flash_chip_info = { 62static struct bfin5xx_spi_chip spi_flash_chip_info = {
63 .enable_dma = 0, /* use dma transfer with this chip*/ 63 .enable_dma = 0, /* use dma transfer with this chip*/
64 .bits_per_word = 8,
65};
66#endif
67
68#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
69/* SPI ADC chip */
70static struct bfin5xx_spi_chip spi_adc_chip_info = {
71 .enable_dma = 1, /* use dma transfer with this chip*/
72 .bits_per_word = 16,
73};
74#endif
75
76#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
77static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
78 .enable_dma = 0,
79 .bits_per_word = 16,
80}; 64};
81#endif 65#endif
82 66
83#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 67#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
84static struct bfin5xx_spi_chip mmc_spi_chip_info = { 68static struct bfin5xx_spi_chip mmc_spi_chip_info = {
85 .enable_dma = 0, 69 .enable_dma = 0,
86 .bits_per_word = 8,
87}; 70};
88#endif 71#endif
89 72
@@ -101,24 +84,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
101 }, 84 },
102#endif 85#endif
103 86
104#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
105 {
106 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
107 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
108 .bus_num = 0, /* Framework bus number */
109 .chip_select = 1, /* Framework chip select. */
110 .platform_data = NULL, /* No spi_driver specific config */
111 .controller_data = &spi_adc_chip_info,
112 },
113#endif
114
115#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 87#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
116 { 88 {
117 .modalias = "ad183x", 89 .modalias = "ad183x",
118 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 90 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
119 .bus_num = 0, 91 .bus_num = 0,
120 .chip_select = 4, 92 .chip_select = 4,
121 .controller_data = &ad1836_spi_chip_info,
122 }, 93 },
123#endif 94#endif
124 95
@@ -766,6 +737,24 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
766#endif 737#endif
767}; 738};
768 739
740static int __init net2272_init(void)
741{
742#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
743 int ret;
744
745 ret = gpio_request(GPIO_PG14, "net2272");
746 if (ret)
747 return ret;
748
749 /* Reset USB Chip, PG14 */
750 gpio_direction_output(GPIO_PG14, 0);
751 mdelay(2);
752 gpio_set_value(GPIO_PG14, 1);
753#endif
754
755 return 0;
756}
757
769static int __init cm_bf537e_init(void) 758static int __init cm_bf537e_init(void)
770{ 759{
771 printk(KERN_INFO "%s(): registering device resources\n", __func__); 760 printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -777,6 +766,10 @@ static int __init cm_bf537e_init(void)
777#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 766#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
778 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); 767 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
779#endif 768#endif
769
770 if (net2272_init())
771 pr_warning("unable to configure net2272; it probably won't work\n");
772
780 return 0; 773 return 0;
781} 774}
782 775
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index cbb8098604c5..1b4ac5c64aae 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -62,29 +62,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
62/* SPI flash chip (m25p64) */ 62/* SPI flash chip (m25p64) */
63static struct bfin5xx_spi_chip spi_flash_chip_info = { 63static struct bfin5xx_spi_chip spi_flash_chip_info = {
64 .enable_dma = 0, /* use dma transfer with this chip*/ 64 .enable_dma = 0, /* use dma transfer with this chip*/
65 .bits_per_word = 8,
66};
67#endif
68
69#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
70/* SPI ADC chip */
71static struct bfin5xx_spi_chip spi_adc_chip_info = {
72 .enable_dma = 1, /* use dma transfer with this chip*/
73 .bits_per_word = 16,
74};
75#endif
76
77#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
78static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
79 .enable_dma = 0,
80 .bits_per_word = 16,
81}; 65};
82#endif 66#endif
83 67
84#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 68#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
85static struct bfin5xx_spi_chip mmc_spi_chip_info = { 69static struct bfin5xx_spi_chip mmc_spi_chip_info = {
86 .enable_dma = 0, 70 .enable_dma = 0,
87 .bits_per_word = 8,
88}; 71};
89#endif 72#endif
90 73
@@ -102,24 +85,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
102 }, 85 },
103#endif 86#endif
104 87
105#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
106 {
107 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
108 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
109 .bus_num = 0, /* Framework bus number */
110 .chip_select = 1, /* Framework chip select. */
111 .platform_data = NULL, /* No spi_driver specific config */
112 .controller_data = &spi_adc_chip_info,
113 },
114#endif
115
116#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 88#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
117 { 89 {
118 .modalias = "ad183x", 90 .modalias = "ad183x",
119 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 91 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
120 .bus_num = 0, 92 .bus_num = 0,
121 .chip_select = 4, 93 .chip_select = 4,
122 .controller_data = &ad1836_spi_chip_info,
123 }, 94 },
124#endif 95#endif
125 96
@@ -731,6 +702,36 @@ static struct platform_device *cm_bf537u_devices[] __initdata = {
731#endif 702#endif
732}; 703};
733 704
705static int __init net2272_init(void)
706{
707#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
708 int ret;
709
710 ret = gpio_request(GPIO_PH15, driver_name);
711 if (ret)
712 return ret;
713
714 ret = gpio_request(GPIO_PH13, "net2272");
715 if (ret) {
716 gpio_free(GPIO_PH15);
717 return ret;
718 }
719
720 /* Set PH15 Low make /AMS2 work properly */
721 gpio_direction_output(GPIO_PH15, 0);
722
723 /* enable CLKBUF output */
724 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
725
726 /* Reset the USB chip */
727 gpio_direction_output(GPIO_PH13, 0);
728 mdelay(2);
729 gpio_set_value(GPIO_PH13, 1);
730#endif
731
732 return 0;
733}
734
734static int __init cm_bf537u_init(void) 735static int __init cm_bf537u_init(void)
735{ 736{
736 printk(KERN_INFO "%s(): registering device resources\n", __func__); 737 printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -742,6 +743,10 @@ static int __init cm_bf537u_init(void)
742#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 743#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
743 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); 744 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
744#endif 745#endif
746
747 if (net2272_init())
748 pr_warning("unable to configure net2272; it probably won't work\n");
749
745 return 0; 750 return 0;
746} 751}
747 752
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
index 6b4ff4605bff..8bc951de979d 100644
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -130,7 +130,6 @@ static struct platform_device asmb_flash_device = {
130 130
131static struct bfin5xx_spi_chip mmc_spi_chip_info = { 131static struct bfin5xx_spi_chip mmc_spi_chip_info = {
132 .enable_dma = 0, /* use no dma transfer with this chip*/ 132 .enable_dma = 0, /* use no dma transfer with this chip*/
133 .bits_per_word = 8,
134}; 133};
135 134
136#endif 135#endif
@@ -161,7 +160,6 @@ static struct flash_platform_data bfin_spi_dataflash_data = {
161 160
162static struct bfin5xx_spi_chip spi_dataflash_chip_info = { 161static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
163 .enable_dma = 0, /* use no dma transfer with this chip*/ 162 .enable_dma = 0, /* use no dma transfer with this chip*/
164 .bits_per_word = 8,
165}; 163};
166#endif 164#endif
167 165
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index bfb3671a78da..c62f9dccd9f7 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -159,14 +159,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
159/* SPI flash chip (m25p64) */ 159/* SPI flash chip (m25p64) */
160static struct bfin5xx_spi_chip spi_flash_chip_info = { 160static struct bfin5xx_spi_chip spi_flash_chip_info = {
161 .enable_dma = 0, /* use dma transfer with this chip*/ 161 .enable_dma = 0, /* use dma transfer with this chip*/
162 .bits_per_word = 8,
163}; 162};
164#endif 163#endif
165 164
166#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 165#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
167static struct bfin5xx_spi_chip mmc_spi_chip_info = { 166static struct bfin5xx_spi_chip mmc_spi_chip_info = {
168 .enable_dma = 0, 167 .enable_dma = 0,
169 .bits_per_word = 8,
170}; 168};
171#endif 169#endif
172 170
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 9389f03e3b0a..3b8151d99b9a 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -184,40 +184,16 @@ static struct flash_platform_data bfin_spi_flash_data = {
184/* SPI flash chip (m25p64) */ 184/* SPI flash chip (m25p64) */
185static struct bfin5xx_spi_chip spi_flash_chip_info = { 185static struct bfin5xx_spi_chip spi_flash_chip_info = {
186 .enable_dma = 0, /* use dma transfer with this chip*/ 186 .enable_dma = 0, /* use dma transfer with this chip*/
187 .bits_per_word = 8,
188};
189#endif
190
191#if defined(CONFIG_BFIN_SPI_ADC) \
192 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
193/* SPI ADC chip */
194static struct bfin5xx_spi_chip spi_adc_chip_info = {
195 .enable_dma = 1, /* use dma transfer with this chip*/
196 .bits_per_word = 16,
197};
198#endif
199
200#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
201 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
202static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
203 .enable_dma = 0,
204 .bits_per_word = 16,
205}; 187};
206#endif 188#endif
207 189
208#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 190#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
209static struct bfin5xx_spi_chip mmc_spi_chip_info = { 191static struct bfin5xx_spi_chip mmc_spi_chip_info = {
210 .enable_dma = 0, 192 .enable_dma = 0,
211 .bits_per_word = 8,
212}; 193};
213#endif 194#endif
214 195
215#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 196#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
216static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
217 .enable_dma = 0,
218 .bits_per_word = 16,
219};
220
221static const struct ad7877_platform_data bfin_ad7877_ts_info = { 197static const struct ad7877_platform_data bfin_ad7877_ts_info = {
222 .model = 7877, 198 .model = 7877,
223 .vref_delay_usecs = 50, /* internal, no capacitor */ 199 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -248,18 +224,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
248 }, 224 },
249#endif 225#endif
250 226
251#if defined(CONFIG_BFIN_SPI_ADC) \
252 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
253 {
254 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
255 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
256 .bus_num = 0, /* Framework bus number */
257 .chip_select = 1, /* Framework chip select. */
258 .platform_data = NULL, /* No spi_driver specific config */
259 .controller_data = &spi_adc_chip_info,
260 },
261#endif
262
263#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ 227#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
264 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 228 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
265 { 229 {
@@ -267,7 +231,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
267 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 231 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
268 .bus_num = 0, 232 .bus_num = 0,
269 .chip_select = 4, 233 .chip_select = 4,
270 .controller_data = &ad1836_spi_chip_info,
271 }, 234 },
272#endif 235#endif
273#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 236#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -288,7 +251,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
288 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 251 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
289 .bus_num = 0, 252 .bus_num = 0,
290 .chip_select = 5, 253 .chip_select = 5,
291 .controller_data = &spi_ad7877_chip_info,
292}, 254},
293#endif 255#endif
294 256
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 76db1d483173..b52e6728f64f 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -367,6 +367,9 @@ static struct resource net2272_bfin_resources[] = {
367 .end = 0x20300000 + 0x100, 367 .end = 0x20300000 + 0x100,
368 .flags = IORESOURCE_MEM, 368 .flags = IORESOURCE_MEM,
369 }, { 369 }, {
370 .start = 1,
371 .flags = IORESOURCE_BUS,
372 }, {
370 .start = IRQ_PF7, 373 .start = IRQ_PF7,
371 .end = IRQ_PF7, 374 .end = IRQ_PF7,
372 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 375 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -533,49 +536,11 @@ static struct flash_platform_data bfin_spi_flash_data = {
533/* SPI flash chip (m25p64) */ 536/* SPI flash chip (m25p64) */
534static struct bfin5xx_spi_chip spi_flash_chip_info = { 537static struct bfin5xx_spi_chip spi_flash_chip_info = {
535 .enable_dma = 0, /* use dma transfer with this chip*/ 538 .enable_dma = 0, /* use dma transfer with this chip*/
536 .bits_per_word = 8,
537};
538#endif
539
540#if defined(CONFIG_BFIN_SPI_ADC) \
541 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
542/* SPI ADC chip */
543static struct bfin5xx_spi_chip spi_adc_chip_info = {
544 .enable_dma = 1, /* use dma transfer with this chip*/
545 .bits_per_word = 16,
546};
547#endif
548
549#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
550 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
551static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
552 .enable_dma = 0,
553 .bits_per_word = 16,
554};
555#endif
556
557#if defined(CONFIG_SND_BF5XX_SOC_AD193X) \
558 || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE)
559static struct bfin5xx_spi_chip ad1938_spi_chip_info = {
560 .enable_dma = 0,
561 .bits_per_word = 8,
562};
563#endif
564
565#if defined(CONFIG_SND_BF5XX_SOC_ADAV80X) \
566 || defined(CONFIG_SND_BF5XX_SOC_ADAV80X_MODULE)
567static struct bfin5xx_spi_chip adav801_spi_chip_info = {
568 .enable_dma = 0,
569 .bits_per_word = 8,
570}; 539};
571#endif 540#endif
572 541
573#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) 542#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE)
574#include <linux/input/ad714x.h> 543#include <linux/input/ad714x.h>
575static struct bfin5xx_spi_chip ad7147_spi_chip_info = {
576 .enable_dma = 0,
577 .bits_per_word = 16,
578};
579 544
580static struct ad714x_slider_plat ad7147_spi_slider_plat[] = { 545static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
581 { 546 {
@@ -685,7 +650,6 @@ static struct ad714x_platform_data ad7142_i2c_platform_data = {
685#if defined(CONFIG_AD2S90) || defined(CONFIG_AD2S90_MODULE) 650#if defined(CONFIG_AD2S90) || defined(CONFIG_AD2S90_MODULE)
686static struct bfin5xx_spi_chip ad2s90_spi_chip_info = { 651static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
687 .enable_dma = 0, 652 .enable_dma = 0,
688 .bits_per_word = 16,
689}; 653};
690#endif 654#endif
691 655
@@ -697,7 +661,6 @@ static unsigned short ad2s120x_platform_data[] = {
697 661
698static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = { 662static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
699 .enable_dma = 0, 663 .enable_dma = 0,
700 .bits_per_word = 16,
701}; 664};
702#endif 665#endif
703 666
@@ -714,14 +677,12 @@ static unsigned short ad2s1210_platform_data[] = {
714 677
715static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = { 678static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
716 .enable_dma = 0, 679 .enable_dma = 0,
717 .bits_per_word = 8,
718}; 680};
719#endif 681#endif
720 682
721#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE) 683#if defined(CONFIG_AD7314) || defined(CONFIG_AD7314_MODULE)
722static struct bfin5xx_spi_chip ad7314_spi_chip_info = { 684static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
723 .enable_dma = 0, 685 .enable_dma = 0,
724 .bits_per_word = 16,
725}; 686};
726#endif 687#endif
727 688
@@ -735,7 +696,6 @@ static unsigned short ad7816_platform_data[] = {
735 696
736static struct bfin5xx_spi_chip ad7816_spi_chip_info = { 697static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
737 .enable_dma = 0, 698 .enable_dma = 0,
738 .bits_per_word = 8,
739}; 699};
740#endif 700#endif
741 701
@@ -749,7 +709,6 @@ static unsigned long adt7310_platform_data[3] = {
749 709
750static struct bfin5xx_spi_chip adt7310_spi_chip_info = { 710static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
751 .enable_dma = 0, 711 .enable_dma = 0,
752 .bits_per_word = 8,
753}; 712};
754#endif 713#endif
755 714
@@ -758,11 +717,6 @@ static unsigned short ad7298_platform_data[] = {
758 GPIO_PF7, /* busy_pin */ 717 GPIO_PF7, /* busy_pin */
759 0, 718 0,
760}; 719};
761
762static struct bfin5xx_spi_chip ad7298_spi_chip_info = {
763 .enable_dma = 0,
764 .bits_per_word = 16,
765};
766#endif 720#endif
767 721
768#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE) 722#if defined(CONFIG_ADT7316_SPI) || defined(CONFIG_ADT7316_SPI_MODULE)
@@ -773,7 +727,6 @@ static unsigned long adt7316_spi_data[2] = {
773 727
774static struct bfin5xx_spi_chip adt7316_spi_chip_info = { 728static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
775 .enable_dma = 0, 729 .enable_dma = 0,
776 .bits_per_word = 8,
777}; 730};
778#endif 731#endif
779 732
@@ -800,18 +753,12 @@ static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
800 753
801static struct bfin5xx_spi_chip mmc_spi_chip_info = { 754static struct bfin5xx_spi_chip mmc_spi_chip_info = {
802 .enable_dma = 0, 755 .enable_dma = 0,
803 .bits_per_word = 8,
804 .pio_interrupt = 0, 756 .pio_interrupt = 0,
805}; 757};
806#endif 758#endif
807 759
808#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 760#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
809#include <linux/spi/ad7877.h> 761#include <linux/spi/ad7877.h>
810static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
811 .enable_dma = 0,
812 .bits_per_word = 16,
813};
814
815static const struct ad7877_platform_data bfin_ad7877_ts_info = { 762static const struct ad7877_platform_data bfin_ad7877_ts_info = {
816 .model = 7877, 763 .model = 7877,
817 .vref_delay_usecs = 50, /* internal, no capacitor */ 764 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -883,39 +830,13 @@ static const struct adxl34x_platform_data adxl34x_info = {
883}; 830};
884#endif 831#endif
885 832
886#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
887static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
888 .enable_dma = 0,
889 .bits_per_word = 16,
890};
891#endif
892
893#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
894static struct bfin5xx_spi_chip spidev_chip_info = {
895 .enable_dma = 0,
896 .bits_per_word = 8,
897};
898#endif
899
900#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
901static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
902 .enable_dma = 0,
903 .bits_per_word = 8,
904};
905#endif
906
907#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) 833#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
908static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { 834static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
909 .enable_dma = 1, 835 .enable_dma = 1,
910 .bits_per_word = 8,
911}; 836};
912#endif 837#endif
913 838
914#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE) 839#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE)
915static struct bfin5xx_spi_chip adf7021_spi_chip_info = {
916 .bits_per_word = 16,
917};
918
919#include <linux/spi/adf702x.h> 840#include <linux/spi/adf702x.h>
920#define TXREG 0x0160A470 841#define TXREG 0x0160A470
921static const u32 adf7021_regs[] = { 842static const u32 adf7021_regs[] = {
@@ -959,10 +880,6 @@ static inline void adf702x_mac_init(void) {}
959 880
960#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 881#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
961#include <linux/spi/ads7846.h> 882#include <linux/spi/ads7846.h>
962static struct bfin5xx_spi_chip ad7873_spi_chip_info = {
963 .bits_per_word = 8,
964};
965
966static int ads7873_get_pendown_state(void) 883static int ads7873_get_pendown_state(void)
967{ 884{
968 return gpio_get_value(GPIO_PF6); 885 return gpio_get_value(GPIO_PF6);
@@ -1009,21 +926,12 @@ static struct flash_platform_data bfin_spi_dataflash_data = {
1009/* DataFlash chip */ 926/* DataFlash chip */
1010static struct bfin5xx_spi_chip data_flash_chip_info = { 927static struct bfin5xx_spi_chip data_flash_chip_info = {
1011 .enable_dma = 0, /* use dma transfer with this chip*/ 928 .enable_dma = 0, /* use dma transfer with this chip*/
1012 .bits_per_word = 8,
1013};
1014#endif
1015
1016#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1017static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
1018 .enable_dma = 0, /* use dma transfer with this chip*/
1019 .bits_per_word = 8,
1020}; 929};
1021#endif 930#endif
1022 931
1023#if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE) 932#if defined(CONFIG_AD7476) || defined(CONFIG_AD7476_MODULE)
1024static struct bfin5xx_spi_chip spi_ad7476_chip_info = { 933static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
1025 .enable_dma = 0, /* use dma transfer with this chip*/ 934 .enable_dma = 0, /* use dma transfer with this chip*/
1026 .bits_per_word = 8,
1027}; 935};
1028#endif 936#endif
1029 937
@@ -1053,17 +961,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1053 .mode = SPI_MODE_3, 961 .mode = SPI_MODE_3,
1054 }, 962 },
1055#endif 963#endif
1056#if defined(CONFIG_BFIN_SPI_ADC) \
1057 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
1058 {
1059 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
1060 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
1061 .bus_num = 0, /* Framework bus number */
1062 .chip_select = 1, /* Framework chip select. */
1063 .platform_data = NULL, /* No spi_driver specific config */
1064 .controller_data = &spi_adc_chip_info,
1065 },
1066#endif
1067 964
1068#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \ 965#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
1069 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 966 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
@@ -1073,7 +970,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1073 .bus_num = 0, 970 .bus_num = 0,
1074 .chip_select = 4, 971 .chip_select = 4,
1075 .platform_data = "ad1836", /* only includes chip name for the moment */ 972 .platform_data = "ad1836", /* only includes chip name for the moment */
1076 .controller_data = &ad1836_spi_chip_info,
1077 .mode = SPI_MODE_3, 973 .mode = SPI_MODE_3,
1078 }, 974 },
1079#endif 975#endif
@@ -1084,7 +980,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1084 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 980 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1085 .bus_num = 0, 981 .bus_num = 0,
1086 .chip_select = 5, 982 .chip_select = 5,
1087 .controller_data = &ad1938_spi_chip_info,
1088 .mode = SPI_MODE_3, 983 .mode = SPI_MODE_3,
1089 }, 984 },
1090#endif 985#endif
@@ -1095,7 +990,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1095 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 990 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1096 .bus_num = 0, 991 .bus_num = 0,
1097 .chip_select = 1, 992 .chip_select = 1,
1098 .controller_data = &adav801_spi_chip_info,
1099 .mode = SPI_MODE_3, 993 .mode = SPI_MODE_3,
1100 }, 994 },
1101#endif 995#endif
@@ -1109,7 +1003,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1109 .chip_select = 5, 1003 .chip_select = 5,
1110 .mode = SPI_MODE_3, 1004 .mode = SPI_MODE_3,
1111 .platform_data = &ad7147_spi_platform_data, 1005 .platform_data = &ad7147_spi_platform_data,
1112 .controller_data = &ad7147_spi_chip_info,
1113 }, 1006 },
1114#endif 1007#endif
1115 1008
@@ -1188,7 +1081,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1188 .bus_num = 0, 1081 .bus_num = 0,
1189 .chip_select = 4, /* CS, change it for your board */ 1082 .chip_select = 4, /* CS, change it for your board */
1190 .platform_data = ad7298_platform_data, 1083 .platform_data = ad7298_platform_data,
1191 .controller_data = &ad7298_spi_chip_info,
1192 .mode = SPI_MODE_3, 1084 .mode = SPI_MODE_3,
1193 }, 1085 },
1194#endif 1086#endif
@@ -1225,7 +1117,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1225 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 1117 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1226 .bus_num = 0, 1118 .bus_num = 0,
1227 .chip_select = 1, 1119 .chip_select = 1,
1228 .controller_data = &spi_ad7877_chip_info,
1229 }, 1120 },
1230#endif 1121#endif
1231#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE) 1122#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
@@ -1236,7 +1127,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1236 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 1127 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1237 .bus_num = 0, 1128 .bus_num = 0,
1238 .chip_select = 1, 1129 .chip_select = 1,
1239 .controller_data = &spi_ad7879_chip_info,
1240 .mode = SPI_CPHA | SPI_CPOL, 1130 .mode = SPI_CPHA | SPI_CPOL,
1241 }, 1131 },
1242#endif 1132#endif
@@ -1246,7 +1136,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1246 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1136 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1247 .bus_num = 0, 1137 .bus_num = 0,
1248 .chip_select = 1, 1138 .chip_select = 1,
1249 .controller_data = &spidev_chip_info,
1250 }, 1139 },
1251#endif 1140#endif
1252#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) 1141#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
@@ -1255,7 +1144,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1255 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 1144 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
1256 .bus_num = 0, 1145 .bus_num = 0,
1257 .chip_select = 2, 1146 .chip_select = 2,
1258 .controller_data = &lq035q1_spi_chip_info,
1259 .mode = SPI_CPHA | SPI_CPOL, 1147 .mode = SPI_CPHA | SPI_CPOL,
1260 }, 1148 },
1261#endif 1149#endif
@@ -1278,7 +1166,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1278 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 1166 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1279 .bus_num = 0, 1167 .bus_num = 0,
1280 .chip_select = 2, 1168 .chip_select = 2,
1281 .controller_data = &spi_adxl34x_chip_info,
1282 .mode = SPI_MODE_3, 1169 .mode = SPI_MODE_3,
1283 }, 1170 },
1284#endif 1171#endif
@@ -1288,7 +1175,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1288 .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */ 1175 .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
1289 .bus_num = 0, 1176 .bus_num = 0,
1290 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ 1177 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
1291 .controller_data = &adf7021_spi_chip_info,
1292 .platform_data = &adf7021_platform_data, 1178 .platform_data = &adf7021_platform_data,
1293 .mode = SPI_MODE_0, 1179 .mode = SPI_MODE_0,
1294 }, 1180 },
@@ -1300,7 +1186,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1300 .bus_num = 0, 1186 .bus_num = 0,
1301 .irq = IRQ_PF6, 1187 .irq = IRQ_PF6,
1302 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */ 1188 .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
1303 .controller_data = &ad7873_spi_chip_info,
1304 .platform_data = &ad7873_pdata, 1189 .platform_data = &ad7873_pdata,
1305 .mode = SPI_MODE_0, 1190 .mode = SPI_MODE_0,
1306 }, 1191 },
@@ -2632,9 +2517,25 @@ static struct resource bfin_snd_resources[][4] = {
2632 BFIN_SND_RES(0), 2517 BFIN_SND_RES(0),
2633 BFIN_SND_RES(1), 2518 BFIN_SND_RES(1),
2634}; 2519};
2520#endif
2521
2522#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
2523static struct platform_device bfin_i2s_pcm = {
2524 .name = "bfin-i2s-pcm-audio",
2525 .id = -1,
2526};
2527#endif
2635 2528
2636static struct platform_device bfin_pcm = { 2529#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
2637 .name = "bfin-pcm-audio", 2530static struct platform_device bfin_tdm_pcm = {
2531 .name = "bfin-tdm-pcm-audio",
2532 .id = -1,
2533};
2534#endif
2535
2536#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
2537static struct platform_device bfin_ac97_pcm = {
2538 .name = "bfin-ac97-pcm-audio",
2638 .id = -1, 2539 .id = -1,
2639}; 2540};
2640#endif 2541#endif
@@ -2869,10 +2770,16 @@ static struct platform_device *stamp_devices[] __initdata = {
2869 &stamp_flash_device, 2770 &stamp_flash_device,
2870#endif 2771#endif
2871 2772
2872#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \ 2773#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
2873 defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \ 2774 &bfin_i2s_pcm,
2874 defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE) 2775#endif
2875 &bfin_pcm, 2776
2777#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
2778 &bfin_tdm_pcm,
2779#endif
2780
2781#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
2782 &bfin_ac97_pcm,
2876#endif 2783#endif
2877 2784
2878#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE) 2785#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
@@ -2916,6 +2823,24 @@ static struct platform_device *stamp_devices[] __initdata = {
2916#endif 2823#endif
2917}; 2824};
2918 2825
2826static int __init net2272_init(void)
2827{
2828#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
2829 int ret;
2830
2831 ret = gpio_request(GPIO_PF6, "net2272");
2832 if (ret)
2833 return ret;
2834
2835 /* Reset the USB chip */
2836 gpio_direction_output(GPIO_PF6, 0);
2837 mdelay(2);
2838 gpio_set_value(GPIO_PF6, 1);
2839#endif
2840
2841 return 0;
2842}
2843
2919static int __init stamp_init(void) 2844static int __init stamp_init(void)
2920{ 2845{
2921 printk(KERN_INFO "%s(): registering device resources\n", __func__); 2846 printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -2926,6 +2851,9 @@ static int __init stamp_init(void)
2926 ARRAY_SIZE(bfin_i2c_board_info)); 2851 ARRAY_SIZE(bfin_i2c_board_info));
2927 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 2852 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
2928 2853
2854 if (net2272_init())
2855 pr_warning("unable to configure net2272; it probably won't work\n");
2856
2929 return 0; 2857 return 0;
2930} 2858}
2931 2859
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 164a7e02c022..9b7287abdfa1 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -62,29 +62,12 @@ static struct flash_platform_data bfin_spi_flash_data = {
62/* SPI flash chip (m25p64) */ 62/* SPI flash chip (m25p64) */
63static struct bfin5xx_spi_chip spi_flash_chip_info = { 63static struct bfin5xx_spi_chip spi_flash_chip_info = {
64 .enable_dma = 0, /* use dma transfer with this chip*/ 64 .enable_dma = 0, /* use dma transfer with this chip*/
65 .bits_per_word = 8,
66};
67#endif
68
69#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
70/* SPI ADC chip */
71static struct bfin5xx_spi_chip spi_adc_chip_info = {
72 .enable_dma = 1, /* use dma transfer with this chip*/
73 .bits_per_word = 16,
74};
75#endif
76
77#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
78static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
79 .enable_dma = 0,
80 .bits_per_word = 16,
81}; 65};
82#endif 66#endif
83 67
84#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 68#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
85static struct bfin5xx_spi_chip mmc_spi_chip_info = { 69static struct bfin5xx_spi_chip mmc_spi_chip_info = {
86 .enable_dma = 0, 70 .enable_dma = 0,
87 .bits_per_word = 8,
88}; 71};
89#endif 72#endif
90 73
@@ -102,24 +85,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
102 }, 85 },
103#endif 86#endif
104 87
105#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
106 {
107 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
108 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
109 .bus_num = 0, /* Framework bus number */
110 .chip_select = 1, /* Framework chip select. */
111 .platform_data = NULL, /* No spi_driver specific config */
112 .controller_data = &spi_adc_chip_info,
113 },
114#endif
115
116#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 88#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
117 { 89 {
118 .modalias = "ad183x", 90 .modalias = "ad183x",
119 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 91 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
120 .bus_num = 0, 92 .bus_num = 0,
121 .chip_select = 4, 93 .chip_select = 4,
122 .controller_data = &ad1836_spi_chip_info,
123 }, 94 },
124#endif 95#endif
125 96
@@ -733,6 +704,24 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
733#endif 704#endif
734}; 705};
735 706
707static int __init net2272_init(void)
708{
709#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
710 int ret;
711
712 ret = gpio_request(GPIO_PG14, "net2272");
713 if (ret)
714 return ret;
715
716 /* Reset USB Chip, PG14 */
717 gpio_direction_output(GPIO_PG14, 0);
718 mdelay(2);
719 gpio_set_value(GPIO_PG14, 1);
720#endif
721
722 return 0;
723}
724
736static int __init tcm_bf537_init(void) 725static int __init tcm_bf537_init(void)
737{ 726{
738 printk(KERN_INFO "%s(): registering device resources\n", __func__); 727 printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -744,6 +733,10 @@ static int __init tcm_bf537_init(void)
744#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 733#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
745 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); 734 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
746#endif 735#endif
736
737 if (net2272_init())
738 pr_warning("unable to configure net2272; it probably won't work\n");
739
747 return 0; 740 return 0;
748} 741}
749 742
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 7f8e5a9f5db6..543cd3fb305e 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List 14 * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -44,18 +44,12 @@
44#define ANOMALY_05000119 (1) 44#define ANOMALY_05000119 (1)
45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 45/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
46#define ANOMALY_05000122 (1) 46#define ANOMALY_05000122 (1)
47/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
48#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
49/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ 47/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
50#define ANOMALY_05000180 (1) 48#define ANOMALY_05000180 (1)
51/* Instruction Cache Is Not Functional */
52#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
53/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ 49/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
54#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) 50#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
55/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 51/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
56#define ANOMALY_05000245 (1) 52#define ANOMALY_05000245 (1)
57/* Buffered CLKIN Output Is Disabled by Default */
58#define ANOMALY_05000247 (1)
59/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ 53/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
60#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) 54#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
61/* EMAC TX DMA Error After an Early Frame Abort */ 55/* EMAC TX DMA Error After an Early Frame Abort */
@@ -98,7 +92,7 @@
98#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) 92#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
99/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ 93/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
100#define ANOMALY_05000280 (1) 94#define ANOMALY_05000280 (1)
101/* False Hardware Error Exception when ISR Context Is Not Restored */ 95/* False Hardware Error when ISR Context Is Not Restored */
102#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) 96#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
103/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 97/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
104#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) 98#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
@@ -162,9 +156,9 @@
162#define ANOMALY_05000461 (1) 156#define ANOMALY_05000461 (1)
163/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 157/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
164#define ANOMALY_05000462 (1) 158#define ANOMALY_05000462 (1)
165/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 159/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
166#define ANOMALY_05000473 (1) 160#define ANOMALY_05000473 (1)
167/* Possible Lockup Condition whem Modifying PLL from External Memory */ 161/* Possible Lockup Condition when Modifying PLL from External Memory */
168#define ANOMALY_05000475 (1) 162#define ANOMALY_05000475 (1)
169/* TESTSET Instruction Cannot Be Interrupted */ 163/* TESTSET Instruction Cannot Be Interrupted */
170#define ANOMALY_05000477 (1) 164#define ANOMALY_05000477 (1)
@@ -172,8 +166,26 @@
172#define ANOMALY_05000480 (__SILICON_REVISION__ < 3) 166#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
173/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 167/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
174#define ANOMALY_05000481 (1) 168#define ANOMALY_05000481 (1)
175/* IFLUSH sucks at life */ 169/* PLL May Latch Incorrect Values Coming Out of Reset */
170#define ANOMALY_05000489 (1)
171/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
176#define ANOMALY_05000491 (1) 172#define ANOMALY_05000491 (1)
173/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
174#define ANOMALY_05000494 (1)
175/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
176#define ANOMALY_05000501 (1)
177
178/*
179 * These anomalies have been "phased" out of analog.com anomaly sheets and are
180 * here to show running on older silicon just isn't feasible.
181 */
182
183/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
184#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
185/* Instruction Cache Is Not Functional */
186#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
187/* Buffered CLKIN Output Is Disabled by Default */
188#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
177 189
178/* Anomalies that don't exist on this proc */ 190/* Anomalies that don't exist on this proc */
179#define ANOMALY_05000099 (0) 191#define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index e61424ef35eb..629f3c333415 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -502,7 +502,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
502 502
503static struct bfin5xx_spi_chip spi_flash_chip_info = { 503static struct bfin5xx_spi_chip spi_flash_chip_info = {
504 .enable_dma = 0, /* use dma transfer with this chip*/ 504 .enable_dma = 0, /* use dma transfer with this chip*/
505 .bits_per_word = 8,
506}; 505};
507#endif 506#endif
508 507
@@ -523,13 +522,6 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
523}; 522};
524#endif 523#endif
525 524
526#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
527static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
528 .enable_dma = 0,
529 .bits_per_word = 16,
530};
531#endif
532
533#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) 525#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
534#include <asm/bfin-lq035q1.h> 526#include <asm/bfin-lq035q1.h>
535 527
@@ -559,20 +551,6 @@ static struct platform_device bfin_lq035q1_device = {
559}; 551};
560#endif 552#endif
561 553
562#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
563static struct bfin5xx_spi_chip spidev_chip_info = {
564 .enable_dma = 0,
565 .bits_per_word = 8,
566};
567#endif
568
569#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
570static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
571 .enable_dma = 0,
572 .bits_per_word = 8,
573};
574#endif
575
576static struct spi_board_info bf538_spi_board_info[] __initdata = { 554static struct spi_board_info bf538_spi_board_info[] __initdata = {
577#if defined(CONFIG_MTD_M25P80) \ 555#if defined(CONFIG_MTD_M25P80) \
578 || defined(CONFIG_MTD_M25P80_MODULE) 556 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -595,7 +573,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
595 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 573 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
596 .bus_num = 0, 574 .bus_num = 0,
597 .chip_select = 1, 575 .chip_select = 1,
598 .controller_data = &spi_ad7879_chip_info,
599 .mode = SPI_CPHA | SPI_CPOL, 576 .mode = SPI_CPHA | SPI_CPOL,
600 }, 577 },
601#endif 578#endif
@@ -605,7 +582,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
605 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 582 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
606 .bus_num = 0, 583 .bus_num = 0,
607 .chip_select = 2, 584 .chip_select = 2,
608 .controller_data = &lq035q1_spi_chip_info,
609 .mode = SPI_CPHA | SPI_CPOL, 585 .mode = SPI_CPHA | SPI_CPOL,
610 }, 586 },
611#endif 587#endif
@@ -615,7 +591,6 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
615 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 591 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
616 .bus_num = 0, 592 .bus_num = 0,
617 .chip_select = 1, 593 .chip_select = 1,
618 .controller_data = &spidev_chip_info,
619 }, 594 },
620#endif 595#endif
621}; 596};
diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c
index 180b1252679f..471a9b184d5b 100644
--- a/arch/blackfin/mach-bf538/ext-gpio.c
+++ b/arch/blackfin/mach-bf538/ext-gpio.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs 2 * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
3 * 3 *
4 * Copyright 2009 Analog Devices Inc. 4 * Copyright 2009-2011 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
@@ -121,3 +121,38 @@ static int __init bf538_extgpio_setup(void)
121 gpiochip_add(&bf538_porte_chip); 121 gpiochip_add(&bf538_porte_chip);
122} 122}
123arch_initcall(bf538_extgpio_setup); 123arch_initcall(bf538_extgpio_setup);
124
125#ifdef CONFIG_PM
126static struct {
127 u16 data, dir, inen;
128} gpio_bank_saved[3];
129
130static void __iomem * const port_bases[3] = {
131 (void *)PORTCIO,
132 (void *)PORTDIO,
133 (void *)PORTEIO,
134};
135
136void bfin_special_gpio_pm_hibernate_suspend(void)
137{
138 int i;
139
140 for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
141 gpio_bank_saved[i].data = read_PORTIO(port_bases[i]);
142 gpio_bank_saved[i].inen = read_PORTIO_INEN(port_bases[i]);
143 gpio_bank_saved[i].dir = read_PORTIO_DIR(port_bases[i]);
144 }
145}
146
147void bfin_special_gpio_pm_hibernate_restore(void)
148{
149 int i;
150
151 for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
152 write_PORTIO_INEN(port_bases[i], gpio_bank_saved[i].inen);
153 write_PORTIO_SET(port_bases[i],
154 gpio_bank_saved[i].data & gpio_bank_saved[i].dir);
155 write_PORTIO_DIR(port_bases[i], gpio_bank_saved[i].dir);
156 }
157}
158#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index 55e7d0712a94..b6ca99788710 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -11,8 +11,8 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List 14 * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
15 * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List 15 * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
16 */ 16 */
17 17
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
@@ -56,25 +56,21 @@
56#define ANOMALY_05000229 (1) 56#define ANOMALY_05000229 (1)
57/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ 57/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
58#define ANOMALY_05000233 (1) 58#define ANOMALY_05000233 (1)
59/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
60#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
61/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 59/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
62#define ANOMALY_05000245 (1) 60#define ANOMALY_05000245 (1)
63/* Maximum External Clock Speed for Timers */ 61/* Maximum External Clock Speed for Timers */
64#define ANOMALY_05000253 (1) 62#define ANOMALY_05000253 (1)
65/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
66#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
67/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ 63/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
68#define ANOMALY_05000270 (__SILICON_REVISION__ < 4) 64#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
69/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 65/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
70#define ANOMALY_05000272 (1) 66#define ANOMALY_05000272 (ANOMALY_BF538)
71/* Writes to Synchronous SDRAM Memory May Be Lost */ 67/* Writes to Synchronous SDRAM Memory May Be Lost */
72#define ANOMALY_05000273 (__SILICON_REVISION__ < 4) 68#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
73/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ 69/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
74#define ANOMALY_05000277 (__SILICON_REVISION__ < 4) 70#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
75/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 71/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
76#define ANOMALY_05000278 (__SILICON_REVISION__ < 4) 72#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
77/* False Hardware Error Exception when ISR Context Is Not Restored */ 73/* False Hardware Error when ISR Context Is Not Restored */
78#define ANOMALY_05000281 (__SILICON_REVISION__ < 4) 74#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
79/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 75/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
80#define ANOMALY_05000282 (__SILICON_REVISION__ < 4) 76#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
@@ -102,8 +98,10 @@
102#define ANOMALY_05000313 (__SILICON_REVISION__ < 4) 98#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
103/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ 99/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
104#define ANOMALY_05000315 (__SILICON_REVISION__ < 4) 100#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
101/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
102#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */
105/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ 103/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
106#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) 104#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */
107/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ 105/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
108#define ANOMALY_05000355 (__SILICON_REVISION__ < 5) 106#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
109/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 107/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
@@ -134,16 +132,32 @@
134#define ANOMALY_05000461 (1) 132#define ANOMALY_05000461 (1)
135/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 133/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
136#define ANOMALY_05000462 (1) 134#define ANOMALY_05000462 (1)
137/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 135/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
138#define ANOMALY_05000473 (1) 136#define ANOMALY_05000473 (1)
139/* Possible Lockup Condition whem Modifying PLL from External Memory */ 137/* Possible Lockup Condition when Modifying PLL from External Memory */
140#define ANOMALY_05000475 (1) 138#define ANOMALY_05000475 (1)
141/* TESTSET Instruction Cannot Be Interrupted */ 139/* TESTSET Instruction Cannot Be Interrupted */
142#define ANOMALY_05000477 (1) 140#define ANOMALY_05000477 (1)
143/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 141/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
144#define ANOMALY_05000481 (1) 142#define ANOMALY_05000481 (1)
145/* IFLUSH sucks at life */ 143/* PLL May Latch Incorrect Values Coming Out of Reset */
144#define ANOMALY_05000489 (1)
145/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
146#define ANOMALY_05000491 (1) 146#define ANOMALY_05000491 (1)
147/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
148#define ANOMALY_05000494 (1)
149/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
150#define ANOMALY_05000501 (1)
151
152/*
153 * These anomalies have been "phased" out of analog.com anomaly sheets and are
154 * here to show running on older silicon just isn't feasible.
155 */
156
157/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
158#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
159/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
160#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
147 161
148/* Anomalies that don't exist on this proc */ 162/* Anomalies that don't exist on this proc */
149#define ANOMALY_05000099 (0) 163#define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index 8a5beeece996..3561c7d8935b 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -8,7 +8,10 @@
8#define _MACH_GPIO_H_ 8#define _MACH_GPIO_H_
9 9
10#define MAX_BLACKFIN_GPIOS 16 10#define MAX_BLACKFIN_GPIOS 16
11#ifdef CONFIG_GPIOLIB
12/* We only use the special logic with GPIOLIB devices */
11#define BFIN_SPECIAL_GPIO_BANKS 3 13#define BFIN_SPECIAL_GPIO_BANKS 3
14#endif
12 15
13#define GPIO_PF0 0 /* PF */ 16#define GPIO_PF0 0 /* PF */
14#define GPIO_PF1 1 17#define GPIO_PF1 1
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index d11502ac5623..212b9e0a08c8 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -861,16 +861,10 @@ static struct flash_platform_data bfin_spi_flash_data = {
861 861
862static struct bfin5xx_spi_chip spi_flash_chip_info = { 862static struct bfin5xx_spi_chip spi_flash_chip_info = {
863 .enable_dma = 0, /* use dma transfer with this chip*/ 863 .enable_dma = 0, /* use dma transfer with this chip*/
864 .bits_per_word = 8,
865}; 864};
866#endif 865#endif
867 866
868#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 867#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
869static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
870 .enable_dma = 0,
871 .bits_per_word = 16,
872};
873
874static const struct ad7877_platform_data bfin_ad7877_ts_info = { 868static const struct ad7877_platform_data bfin_ad7877_ts_info = {
875 .model = 7877, 869 .model = 7877,
876 .vref_delay_usecs = 50, /* internal, no capacitor */ 870 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -886,13 +880,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
886}; 880};
887#endif 881#endif
888 882
889#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
890static struct bfin5xx_spi_chip spidev_chip_info = {
891 .enable_dma = 0,
892 .bits_per_word = 8,
893};
894#endif
895
896static struct spi_board_info bf54x_spi_board_info[] __initdata = { 883static struct spi_board_info bf54x_spi_board_info[] __initdata = {
897#if defined(CONFIG_MTD_M25P80) \ 884#if defined(CONFIG_MTD_M25P80) \
898 || defined(CONFIG_MTD_M25P80_MODULE) 885 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -915,7 +902,6 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
915 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 902 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
916 .bus_num = 0, 903 .bus_num = 0,
917 .chip_select = 2, 904 .chip_select = 2,
918 .controller_data = &spi_ad7877_chip_info,
919}, 905},
920#endif 906#endif
921#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 907#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -924,7 +910,6 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
924 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 910 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
925 .bus_num = 0, 911 .bus_num = 0,
926 .chip_select = 1, 912 .chip_select = 1,
927 .controller_data = &spidev_chip_info,
928 }, 913 },
929#endif 914#endif
930}; 915};
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 311bf9970fe7..cd9cbb68de69 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -1018,24 +1018,10 @@ static struct flash_platform_data bfin_spi_flash_data = {
1018 1018
1019static struct bfin5xx_spi_chip spi_flash_chip_info = { 1019static struct bfin5xx_spi_chip spi_flash_chip_info = {
1020 .enable_dma = 0, /* use dma transfer with this chip*/ 1020 .enable_dma = 0, /* use dma transfer with this chip*/
1021 .bits_per_word = 8,
1022};
1023#endif
1024
1025#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
1026 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
1027static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
1028 .enable_dma = 0,
1029 .bits_per_word = 16,
1030}; 1021};
1031#endif 1022#endif
1032 1023
1033#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 1024#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
1034static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
1035 .enable_dma = 0,
1036 .bits_per_word = 16,
1037};
1038
1039static const struct ad7877_platform_data bfin_ad7877_ts_info = { 1025static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1040 .model = 7877, 1026 .model = 7877,
1041 .vref_delay_usecs = 50, /* internal, no capacitor */ 1027 .vref_delay_usecs = 50, /* internal, no capacitor */
@@ -1051,20 +1037,6 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1051}; 1037};
1052#endif 1038#endif
1053 1039
1054#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1055static struct bfin5xx_spi_chip spidev_chip_info = {
1056 .enable_dma = 0,
1057 .bits_per_word = 8,
1058};
1059#endif
1060
1061#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1062static struct bfin5xx_spi_chip spi_adxl34x_chip_info = {
1063 .enable_dma = 0, /* use dma transfer with this chip*/
1064 .bits_per_word = 8,
1065};
1066#endif
1067
1068static struct spi_board_info bfin_spi_board_info[] __initdata = { 1040static struct spi_board_info bfin_spi_board_info[] __initdata = {
1069#if defined(CONFIG_MTD_M25P80) \ 1041#if defined(CONFIG_MTD_M25P80) \
1070 || defined(CONFIG_MTD_M25P80_MODULE) 1042 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -1086,7 +1058,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1086 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1058 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1087 .bus_num = 1, 1059 .bus_num = 1,
1088 .chip_select = 4, 1060 .chip_select = 4,
1089 .controller_data = &ad1836_spi_chip_info,
1090 }, 1061 },
1091#endif 1062#endif
1092#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 1063#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
@@ -1097,7 +1068,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1097 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 1068 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1098 .bus_num = 0, 1069 .bus_num = 0,
1099 .chip_select = 2, 1070 .chip_select = 2,
1100 .controller_data = &spi_ad7877_chip_info,
1101 }, 1071 },
1102#endif 1072#endif
1103#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) 1073#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1106,7 +1076,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1106 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1076 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1107 .bus_num = 0, 1077 .bus_num = 0,
1108 .chip_select = 1, 1078 .chip_select = 1,
1109 .controller_data = &spidev_chip_info,
1110 }, 1079 },
1111#endif 1080#endif
1112#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) 1081#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
@@ -1117,7 +1086,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
1117 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 1086 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1118 .bus_num = 1, 1087 .bus_num = 1,
1119 .chip_select = 2, 1088 .chip_select = 2,
1120 .controller_data = &spi_adxl34x_chip_info,
1121 .mode = SPI_MODE_3, 1089 .mode = SPI_MODE_3,
1122 }, 1090 },
1123#endif 1091#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 9e70785bdde3..ac96ee83b00e 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List 14 * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -29,117 +29,37 @@
29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30#define ANOMALY_05000122 (1) 30#define ANOMALY_05000122 (1)
31/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ 31/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
32#define ANOMALY_05000220 (1) 32#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
33/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 33/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
34#define ANOMALY_05000245 (1) 34#define ANOMALY_05000245 (1)
35/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 35/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
36#define ANOMALY_05000265 (1) 36#define ANOMALY_05000265 (1)
37/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 37/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
38#define ANOMALY_05000272 (1) 38#define ANOMALY_05000272 (1)
39/* False Hardware Error Exception when ISR Context Is Not Restored */
40#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
41/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
42#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
43/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 39/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
44#define ANOMALY_05000310 (1) 40#define ANOMALY_05000310 (1)
45/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
46#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
47/* TWI Slave Boot Mode Is Not Functional */
48#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
49/* FIFO Boot Mode Not Functional */ 41/* FIFO Boot Mode Not Functional */
50#define ANOMALY_05000325 (__SILICON_REVISION__ < 2) 42#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
51/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
52#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
53/* Incorrect Access of OTP_STATUS During otp_write() Function */
54#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
55/* Synchronous Burst Flash Boot Mode Is Not Functional */
56#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
57/* Host DMA Boot Modes Are Not Functional */
58#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
59/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
60#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
61/* Inadequate Rotary Debounce Logic Duration */
62#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
63/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
64#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
65/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
66#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
67/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
68#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
69/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
70#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
71/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
72#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
73/* USB Calibration Value Is Not Initialized */
74#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
75/* USB Calibration Value to use */
76#define ANOMALY_05000346_value 0x5411
77/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
78#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
79/* Data Lost when Core Reads SDH Data FIFO */
80#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
81/* PLL Status Register Is Inaccurate */
82#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
83/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ 43/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
84/* 44/*
85 * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing 45 * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
86 * shows that the fix itself does not cover all cases. 46 * shows that the fix itself does not cover all cases.
87 */ 47 */
88#define ANOMALY_05000353 (1) 48#define ANOMALY_05000353 (1)
89/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
90#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
91/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
92#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
93/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ 49/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
94#define ANOMALY_05000357 (1) 50#define ANOMALY_05000357 (1)
95/* External Memory Read Access Hangs Core With PLL Bypass */ 51/* External Memory Read Access Hangs Core With PLL Bypass */
96#define ANOMALY_05000360 (1) 52#define ANOMALY_05000360 (1)
97/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ 53/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
98#define ANOMALY_05000365 (1) 54#define ANOMALY_05000365 (1)
99/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
100#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
101/* Addressing Conflict between Boot ROM and Asynchronous Memory */ 55/* Addressing Conflict between Boot ROM and Asynchronous Memory */
102#define ANOMALY_05000369 (1) 56#define ANOMALY_05000369 (1)
103/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
104#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
105/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 57/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
106#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) 58#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
107/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
108#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
109/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ 59/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
110#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) 60#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
111/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ 61/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
112#define ANOMALY_05000379 (1) 62#define ANOMALY_05000379 (1)
113/* 8-Bit NAND Flash Boot Mode Not Functional */
114#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
115/* Some ATAPI Modes Are Not Functional */
116#define ANOMALY_05000383 (1)
117/* Boot from OTP Memory Not Functional */
118#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
119/* bfrom_SysControl() Firmware Routine Not Functional */
120#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
121/* Programmable Preboot Settings Not Functional */
122#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
123/* CRC32 Checksum Support Not Functional */
124#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
125/* Reset Vector Must Not Be in SDRAM Memory Space */
126#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
127/* Changed Meaning of BCODE Field in SYSCR Register */
128#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
129/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
130#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
131/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
132#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
133/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
134#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
135/* Log Buffer Not Functional */
136#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
137/* Hook Routine Not Functional */
138#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
139/* Header Indirect Bit Not Functional */
140#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
141/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
142#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
143/* Lockbox SESR Disallows Certain User Interrupts */ 63/* Lockbox SESR Disallows Certain User Interrupts */
144#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) 64#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
145/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ 65/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
@@ -161,7 +81,7 @@
161/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 81/* Speculative Fetches Can Cause Undesired External FIFO Operations */
162#define ANOMALY_05000416 (1) 82#define ANOMALY_05000416 (1)
163/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ 83/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
164#define ANOMALY_05000425 (1) 84#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
165/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ 85/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
166#define ANOMALY_05000426 (1) 86#define ANOMALY_05000426 (1)
167/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ 87/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
@@ -174,8 +94,6 @@
174#define ANOMALY_05000431 (__SILICON_REVISION__ < 3) 94#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
175/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ 95/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
176#define ANOMALY_05000434 (1) 96#define ANOMALY_05000434 (1)
177/* OTP Write Accesses Not Supported */
178#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
179/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 97/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
180#define ANOMALY_05000443 (1) 98#define ANOMALY_05000443 (1)
181/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ 99/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
@@ -186,34 +104,32 @@
186#define ANOMALY_05000448 (__SILICON_REVISION__ == 1) 104#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
187/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ 105/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
188#define ANOMALY_05000449 (__SILICON_REVISION__ == 1) 106#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
189/* USB DMA Mode 1 Short Packet Data Corruption */ 107/* USB DMA Short Packet Data Corruption */
190#define ANOMALY_05000450 (1) 108#define ANOMALY_05000450 (1)
191/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
192#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
193/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ 109/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
194#define ANOMALY_05000456 (1) 110#define ANOMALY_05000456 (1)
195/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ 111/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
196#define ANOMALY_05000457 (1) 112#define ANOMALY_05000457 (1)
197/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ 113/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
198#define ANOMALY_05000460 (1) 114#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
199/* False Hardware Error when RETI Points to Invalid Memory */ 115/* False Hardware Error when RETI Points to Invalid Memory */
200#define ANOMALY_05000461 (1) 116#define ANOMALY_05000461 (1)
201/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ 117/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
202#define ANOMALY_05000462 (1) 118#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
203/* USB DMA RX Data Corruption */ 119/* USB DMA RX Data Corruption */
204#define ANOMALY_05000463 (1) 120#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
205/* USB TX DMA Hang */ 121/* USB TX DMA Hang */
206#define ANOMALY_05000464 (1) 122#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
207/* USB Rx DMA hang */ 123/* USB Rx DMA Hang */
208#define ANOMALY_05000465 (1) 124#define ANOMALY_05000465 (1)
209/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ 125/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
210#define ANOMALY_05000466 (1) 126#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
211/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ 127/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
212#define ANOMALY_05000467 (1) 128#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
213/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 129/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
214#define ANOMALY_05000473 (1) 130#define ANOMALY_05000473 (1)
215/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ 131/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
216#define ANOMALY_05000474 (1) 132#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
217/* TESTSET Instruction Cannot Be Interrupted */ 133/* TESTSET Instruction Cannot Be Interrupted */
218#define ANOMALY_05000477 (1) 134#define ANOMALY_05000477 (1)
219/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 135/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
@@ -223,9 +139,111 @@
223/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */ 139/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
224#define ANOMALY_05000484 (__SILICON_REVISION__ < 3) 140#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
225/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ 141/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
226#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2) 142#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
227/* IFLUSH sucks at life */ 143/* PLL May Latch Incorrect Values Coming Out of Reset */
144#define ANOMALY_05000489 (1)
145/* SPI Master Boot Can Fail Under Certain Conditions */
146#define ANOMALY_05000490 (1)
147/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
228#define ANOMALY_05000491 (1) 148#define ANOMALY_05000491 (1)
149/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
150#define ANOMALY_05000494 (1)
151/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
152#define ANOMALY_05000498 (1)
153/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
154#define ANOMALY_05000500 (1)
155/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
156#define ANOMALY_05000501 (1)
157/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
158#define ANOMALY_05000502 (1)
159
160/*
161 * These anomalies have been "phased" out of analog.com anomaly sheets and are
162 * here to show running on older silicon just isn't feasible.
163 */
164
165/* False Hardware Error when ISR Context Is Not Restored */
166#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
167/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
168#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
169/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
170#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
171/* TWI Slave Boot Mode Is Not Functional */
172#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
173/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
174#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
175/* Incorrect Access of OTP_STATUS During otp_write() Function */
176#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
177/* Synchronous Burst Flash Boot Mode Is Not Functional */
178#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
179/* Host DMA Boot Modes Are Not Functional */
180#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
181/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
182#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
183/* Inadequate Rotary Debounce Logic Duration */
184#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
185/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
186#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
187/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
188#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
189/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
190#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
191/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
192#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
193/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
194#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
195/* USB Calibration Value Is Not Initialized */
196#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
197/* USB Calibration Value to use */
198#define ANOMALY_05000346_value 0x5411
199/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
200#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
201/* Data Lost when Core Reads SDH Data FIFO */
202#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
203/* PLL Status Register Is Inaccurate */
204#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
205/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
206#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
207/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
208#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
209/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
210#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
211/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
212#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
213/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
214#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
215/* 8-Bit NAND Flash Boot Mode Not Functional */
216#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
217/* Boot from OTP Memory Not Functional */
218#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
219/* bfrom_SysControl() Firmware Routine Not Functional */
220#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
221/* Programmable Preboot Settings Not Functional */
222#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
223/* CRC32 Checksum Support Not Functional */
224#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
225/* Reset Vector Must Not Be in SDRAM Memory Space */
226#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
227/* Changed Meaning of BCODE Field in SYSCR Register */
228#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
229/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
230#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
231/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
232#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
233/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
234#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
235/* Log Buffer Not Functional */
236#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
237/* Hook Routine Not Functional */
238#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
239/* Header Indirect Bit Not Functional */
240#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
241/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
242#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
243/* OTP Write Accesses Not Supported */
244#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
245/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
246#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
229 247
230/* Anomalies that don't exist on this proc */ 248/* Anomalies that don't exist on this proc */
231#define ANOMALY_05000099 (0) 249#define ANOMALY_05000099 (0)
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 7db433514e3f..35c8ced46158 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -170,6 +170,8 @@
170 170
171#define MAX_BLACKFIN_GPIOS 160 171#define MAX_BLACKFIN_GPIOS 160
172 172
173#define BFIN_GPIO_PINT 1
174
173#ifndef __ASSEMBLY__ 175#ifndef __ASSEMBLY__
174 176
175struct gpio_port_t { 177struct gpio_port_t {
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 533b8095b540..10dc142c518d 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -438,7 +438,7 @@
438struct bfin_pint_regs { 438struct bfin_pint_regs {
439 u32 mask_set; 439 u32 mask_set;
440 u32 mask_clear; 440 u32 mask_clear;
441 u32 irq; 441 u32 request;
442 u32 assign; 442 u32 assign;
443 u32 edge_set; 443 u32 edge_set;
444 u32 edge_clear; 444 u32 edge_clear;
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 9231a942892b..972e1347c6bc 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -364,14 +364,6 @@ static struct flash_platform_data bfin_spi_dataflash_data = {
364/* DataFlash chip */ 364/* DataFlash chip */
365static struct bfin5xx_spi_chip data_flash_chip_info = { 365static struct bfin5xx_spi_chip data_flash_chip_info = {
366 .enable_dma = 0, /* use dma transfer with this chip */ 366 .enable_dma = 0, /* use dma transfer with this chip */
367 .bits_per_word = 8,
368};
369#endif
370
371#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
372static struct bfin5xx_spi_chip spidev_chip_info = {
373 .enable_dma = 0,
374 .bits_per_word = 8,
375}; 367};
376#endif 368#endif
377 369
@@ -420,7 +412,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
420 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 412 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
421 .bus_num = 0, 413 .bus_num = 0,
422 .chip_select = 3, 414 .chip_select = 3,
423 .controller_data = &spidev_chip_info,
424 }, 415 },
425#endif 416#endif
426#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) 417#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 87595cd38afe..e4f397d1d65b 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -60,29 +60,6 @@ static struct flash_platform_data bfin_spi_flash_data = {
60/* SPI flash chip (m25p64) */ 60/* SPI flash chip (m25p64) */
61static struct bfin5xx_spi_chip spi_flash_chip_info = { 61static struct bfin5xx_spi_chip spi_flash_chip_info = {
62 .enable_dma = 0, /* use dma transfer with this chip*/ 62 .enable_dma = 0, /* use dma transfer with this chip*/
63 .bits_per_word = 8,
64};
65#endif
66
67#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
68/* SPI ADC chip */
69static struct bfin5xx_spi_chip spi_adc_chip_info = {
70 .enable_dma = 1, /* use dma transfer with this chip*/
71 .bits_per_word = 16,
72};
73#endif
74
75#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
76static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
77 .enable_dma = 0,
78 .bits_per_word = 16,
79};
80#endif
81
82#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
83static struct bfin5xx_spi_chip mmc_spi_chip_info = {
84 .enable_dma = 0,
85 .bits_per_word = 8,
86}; 63};
87#endif 64#endif
88 65
@@ -100,24 +77,12 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
100 }, 77 },
101#endif 78#endif
102 79
103#if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE)
104 {
105 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
106 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
107 .bus_num = 0, /* Framework bus number */
108 .chip_select = 1, /* Framework chip select. */
109 .platform_data = NULL, /* No spi_driver specific config */
110 .controller_data = &spi_adc_chip_info,
111 },
112#endif
113
114#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE) 80#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
115 { 81 {
116 .modalias = "ad183x", 82 .modalias = "ad183x",
117 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 83 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
118 .bus_num = 0, 84 .bus_num = 0,
119 .chip_select = 4, 85 .chip_select = 4,
120 .controller_data = &ad1836_spi_chip_info,
121 }, 86 },
122#endif 87#endif
123#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 88#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -126,7 +91,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
126 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 91 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
127 .bus_num = 0, 92 .bus_num = 0,
128 .chip_select = 1, 93 .chip_select = 1,
129 .controller_data = &mmc_spi_chip_info,
130 .mode = SPI_MODE_3, 94 .mode = SPI_MODE_3,
131 }, 95 },
132#endif 96#endif
@@ -532,6 +496,24 @@ static struct platform_device *cm_bf561_devices[] __initdata = {
532#endif 496#endif
533}; 497};
534 498
499static int __init net2272_init(void)
500{
501#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
502 int ret;
503
504 ret = gpio_request(GPIO_PF46, "net2272");
505 if (ret)
506 return ret;
507
508 /* Reset USB Chip, PF46 */
509 gpio_direction_output(GPIO_PF46, 0);
510 mdelay(2);
511 gpio_set_value(GPIO_PF46, 1);
512#endif
513
514 return 0;
515}
516
535static int __init cm_bf561_init(void) 517static int __init cm_bf561_init(void)
536{ 518{
537 printk(KERN_INFO "%s(): registering device resources\n", __func__); 519 printk(KERN_INFO "%s(): registering device resources\n", __func__);
@@ -543,6 +525,10 @@ static int __init cm_bf561_init(void)
543#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 525#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
544 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN); 526 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
545#endif 527#endif
528
529 if (net2272_init())
530 pr_warning("unable to configure net2272; it probably won't work\n");
531
546 return 0; 532 return 0;
547} 533}
548 534
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 5067984a62e7..9490dc800ca5 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -108,6 +108,9 @@ static struct resource net2272_bfin_resources[] = {
108 .end = 0x2C000000 + 0x7F, 108 .end = 0x2C000000 + 0x7F,
109 .flags = IORESOURCE_MEM, 109 .flags = IORESOURCE_MEM,
110 }, { 110 }, {
111 .start = 1,
112 .flags = IORESOURCE_BUS,
113 }, {
111 .start = IRQ_PF10, 114 .start = IRQ_PF10,
112 .end = IRQ_PF10, 115 .end = IRQ_PF10,
113 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 116 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
@@ -283,21 +286,6 @@ static struct platform_device ezkit_flash_device = {
283}; 286};
284#endif 287#endif
285 288
286#if defined(CONFIG_SND_BF5XX_SOC_AD183X) \
287 || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
288static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
289 .enable_dma = 0,
290 .bits_per_word = 16,
291};
292#endif
293
294#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
295static struct bfin5xx_spi_chip spidev_chip_info = {
296 .enable_dma = 0,
297 .bits_per_word = 8,
298};
299#endif
300
301#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 289#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
302/* SPI (0) */ 290/* SPI (0) */
303static struct resource bfin_spi0_resource[] = { 291static struct resource bfin_spi0_resource[] = {
@@ -345,7 +333,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
345 .bus_num = 0, 333 .bus_num = 0,
346 .chip_select = 4, 334 .chip_select = 4,
347 .platform_data = "ad1836", /* only includes chip name for the moment */ 335 .platform_data = "ad1836", /* only includes chip name for the moment */
348 .controller_data = &ad1836_spi_chip_info,
349 .mode = SPI_MODE_3, 336 .mode = SPI_MODE_3,
350 }, 337 },
351#endif 338#endif
@@ -355,7 +342,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
355 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 342 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
356 .bus_num = 0, 343 .bus_num = 0,
357 .chip_select = 1, 344 .chip_select = 1,
358 .controller_data = &spidev_chip_info,
359 }, 345 },
360#endif 346#endif
361}; 347};
@@ -516,6 +502,24 @@ static struct platform_device *ezkit_devices[] __initdata = {
516#endif 502#endif
517}; 503};
518 504
505static int __init net2272_init(void)
506{
507#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
508 int ret;
509
510 ret = gpio_request(GPIO_PF11, "net2272");
511 if (ret)
512 return ret;
513
514 /* Reset the USB chip */
515 gpio_direction_output(GPIO_PF11, 0);
516 mdelay(2);
517 gpio_set_value(GPIO_PF11, 1);
518#endif
519
520 return 0;
521}
522
519static int __init ezkit_init(void) 523static int __init ezkit_init(void)
520{ 524{
521 int ret; 525 int ret;
@@ -542,6 +546,9 @@ static int __init ezkit_init(void)
542 udelay(400); 546 udelay(400);
543#endif 547#endif
544 548
549 if (net2272_init())
550 pr_warning("unable to configure net2272; it probably won't work\n");
551
545 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 552 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
546 return 0; 553 return 0;
547} 554}
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 22b5ab773027..836baeed303a 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/* This file should be up to date with: 13/* This file should be up to date with:
14 * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List 14 * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
15 */ 15 */
16 16
17#ifndef _MACH_ANOMALY_H_ 17#ifndef _MACH_ANOMALY_H_
@@ -26,62 +26,16 @@
26#define ANOMALY_05000074 (1) 26#define ANOMALY_05000074 (1)
27/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ 27/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
28#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) 28#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
29/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
30#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
31/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ 29/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
32#define ANOMALY_05000120 (1) 30#define ANOMALY_05000120 (1)
33/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 31/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
34#define ANOMALY_05000122 (1) 32#define ANOMALY_05000122 (1)
35/* Erroneous Exception when Enabling Cache */
36#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
37/* SIGNBITS Instruction Not Functional under Certain Conditions */ 33/* SIGNBITS Instruction Not Functional under Certain Conditions */
38#define ANOMALY_05000127 (1) 34#define ANOMALY_05000127 (1)
39/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
40#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
41/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
42#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
43/* Stall in multi-unit DMA operations */
44#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
45/* Allowing the SPORT RX FIFO to fill will cause an overflow */
46#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
47/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
48#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
49/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
50#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
51/* DMA and TESTSET conflict when both are accessing external memory */
52#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
53/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
54#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
55/* MDMA may lose the first few words of a descriptor chain */
56#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
57/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
58#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
59/* IMDMA S1/D1 Channel May Stall */ 35/* IMDMA S1/D1 Channel May Stall */
60#define ANOMALY_05000149 (1) 36#define ANOMALY_05000149 (1)
61/* DMA engine may lose data due to incorrect handshaking */
62#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
63/* DMA stalls when all three controllers read data from the same source */
64#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
65/* Execution stall when executing in L2 and doing external accesses */
66#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
67/* Frame Delay in SPORT Multichannel Mode */
68#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
69/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
70#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
71/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ 37/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
72#define ANOMALY_05000156 (__SILICON_REVISION__ < 4) 38#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
73/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
74#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
75/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
76#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
77/* A read from external memory may return a wrong value with data cache enabled */
78#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
79/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
80#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
81/* DMEM_CONTROL<12> is not set on Reset */
82#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
83/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
84#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
85/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ 39/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
86#define ANOMALY_05000166 (1) 40#define ANOMALY_05000166 (1)
87/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ 41/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
@@ -92,10 +46,6 @@
92#define ANOMALY_05000169 (__SILICON_REVISION__ < 5) 46#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
93/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ 47/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
94#define ANOMALY_05000171 (__SILICON_REVISION__ < 5) 48#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
95/* DSPID register values incorrect */
96#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
97/* DMA vs Core accesses to external memory */
98#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
99/* Cache Fill Buffer Data lost */ 49/* Cache Fill Buffer Data lost */
100#define ANOMALY_05000174 (__SILICON_REVISION__ < 5) 50#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
101/* Overlapping Sequencer and Memory Stalls */ 51/* Overlapping Sequencer and Memory Stalls */
@@ -124,8 +74,6 @@
124#define ANOMALY_05000189 (__SILICON_REVISION__ < 5) 74#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
125/* PPI Not Functional at Core Voltage < 1Volt */ 75/* PPI Not Functional at Core Voltage < 1Volt */
126#define ANOMALY_05000190 (1) 76#define ANOMALY_05000190 (1)
127/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
128#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
129/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ 77/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
130#define ANOMALY_05000193 (__SILICON_REVISION__ < 5) 78#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
131/* Restarting SPORT in Specific Modes May Cause Data Corruption */ 79/* Restarting SPORT in Specific Modes May Cause Data Corruption */
@@ -217,10 +165,10 @@
217/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ 165/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
218#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
219/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ 167/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
220#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) 168#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
221/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 169/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
222#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) 170#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
223/* False Hardware Error Exception when ISR Context Is Not Restored */ 171/* False Hardware Error when ISR Context Is Not Restored */
224/* Temporarily walk around for bug 5423 till this issue is confirmed by 172/* Temporarily walk around for bug 5423 till this issue is confirmed by
225 * official anomaly document. It looks 05000281 still exists on bf561 173 * official anomaly document. It looks 05000281 still exists on bf561
226 * v0.5. 174 * v0.5.
@@ -274,8 +222,6 @@
274#define ANOMALY_05000366 (1) 222#define ANOMALY_05000366 (1)
275/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 223/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
276#define ANOMALY_05000371 (1) 224#define ANOMALY_05000371 (1)
277/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
278#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
279/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 225/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
280#define ANOMALY_05000403 (1) 226#define ANOMALY_05000403 (1)
281/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ 227/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
@@ -298,16 +244,82 @@
298#define ANOMALY_05000462 (1) 244#define ANOMALY_05000462 (1)
299/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ 245/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
300#define ANOMALY_05000471 (1) 246#define ANOMALY_05000471 (1)
301/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ 247/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
302#define ANOMALY_05000473 (1) 248#define ANOMALY_05000473 (1)
303/* Possible Lockup Condition whem Modifying PLL from External Memory */ 249/* Possible Lockup Condition when Modifying PLL from External Memory */
304#define ANOMALY_05000475 (1) 250#define ANOMALY_05000475 (1)
305/* TESTSET Instruction Cannot Be Interrupted */ 251/* TESTSET Instruction Cannot Be Interrupted */
306#define ANOMALY_05000477 (1) 252#define ANOMALY_05000477 (1)
307/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ 253/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
308#define ANOMALY_05000481 (1) 254#define ANOMALY_05000481 (1)
309/* IFLUSH sucks at life */ 255/* PLL May Latch Incorrect Values Coming Out of Reset */
256#define ANOMALY_05000489 (1)
257/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
310#define ANOMALY_05000491 (1) 258#define ANOMALY_05000491 (1)
259/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
260#define ANOMALY_05000494 (1)
261/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
262#define ANOMALY_05000501 (1)
263
264/*
265 * These anomalies have been "phased" out of analog.com anomaly sheets and are
266 * here to show running on older silicon just isn't feasible.
267 */
268
269/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
270#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
271/* Erroneous Exception when Enabling Cache */
272#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
273/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
274#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
275/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
276#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
277/* Stall in multi-unit DMA operations */
278#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
279/* Allowing the SPORT RX FIFO to fill will cause an overflow */
280#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
281/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
282#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
283/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
284#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
285/* DMA and TESTSET conflict when both are accessing external memory */
286#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
287/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
288#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
289/* MDMA may lose the first few words of a descriptor chain */
290#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
291/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
292#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
293/* DMA engine may lose data due to incorrect handshaking */
294#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
295/* DMA stalls when all three controllers read data from the same source */
296#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
297/* Execution stall when executing in L2 and doing external accesses */
298#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
299/* Frame Delay in SPORT Multichannel Mode */
300#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
301/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
302#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
303/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
304#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
305/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
306#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
307/* A read from external memory may return a wrong value with data cache enabled */
308#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
309/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
310#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
311/* DMEM_CONTROL<12> is not set on Reset */
312#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
313/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
314#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
315/* DSPID register values incorrect */
316#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
317/* DMA vs Core accesses to external memory */
318#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
319/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
320#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
321/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
322#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
311 323
312/* Anomalies that don't exist on this proc */ 324/* Anomalies that don't exist on this proc */
313#define ANOMALY_05000119 (0) 325#define ANOMALY_05000119 (0)
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
index 57d5eab59faf..f9f8b2adf4ba 100644
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -58,9 +58,9 @@
58#define GPIO_PF46 46 58#define GPIO_PF46 46
59#define GPIO_PF47 47 59#define GPIO_PF47 47
60 60
61#define PORT_FIO0 GPIO_0 61#define PORT_FIO0 GPIO_PF0
62#define PORT_FIO1 GPIO_16 62#define PORT_FIO1 GPIO_PF16
63#define PORT_FIO2 GPIO_32 63#define PORT_FIO2 GPIO_PF32
64 64
65#include <mach-common/ports-f.h> 65#include <mach-common/ports-f.h>
66 66
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index 4c462838f4e1..01e5408620ac 100644
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -23,108 +23,78 @@
23#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) 23#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
24 24
25ENTRY(_coreb_trampoline_start) 25ENTRY(_coreb_trampoline_start)
26 /* Set the SYSCFG register */ 26 /* Enable Cycle Counter and Nesting Of Interrupts */
27 R0 = 0x36; 27#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
28 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/ 28 R0 = SYSCFG_SNEN;
29 R0 = 0; 29#else
30 30 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
31 /*Clear Out All the data and pointer Registers*/ 31#endif
32 R1 = R0; 32 SYSCFG = R0;
33 R2 = R0;
34 R3 = R0;
35 R4 = R0;
36 R5 = R0;
37 R6 = R0;
38 R7 = R0;
39
40 P0 = R0;
41 P1 = R0;
42 P2 = R0;
43 P3 = R0;
44 P4 = R0;
45 P5 = R0;
46
47 LC0 = r0;
48 LC1 = r0;
49 L0 = r0;
50 L1 = r0;
51 L2 = r0;
52 L3 = r0;
53
54 /* Clear Out All the DAG Registers*/
55 B0 = r0;
56 B1 = r0;
57 B2 = r0;
58 B3 = r0;
59
60 I0 = r0;
61 I1 = r0;
62 I2 = r0;
63 I3 = r0;
64
65 M0 = r0;
66 M1 = r0;
67 M2 = r0;
68 M3 = r0;
69 33
70 trace_buffer_init(p0,r0); 34 /* Optimization register tricks: keep a base value in the
35 * reserved P registers so we use the load/store with an
36 * offset syntax. R0 = [P5 + <constant>];
37 * P5 - core MMR base
38 * R6 - 0
39 */
40 r6 = 0;
41 p5.l = 0;
42 p5.h = hi(COREMMR_BASE);
71 43
72 /* Turn off the icache */ 44 /* Zero out registers required by Blackfin ABI */
73 p0.l = LO(IMEM_CONTROL);
74 p0.h = HI(IMEM_CONTROL);
75 R1 = [p0];
76 R0 = ~ENICPLB;
77 R0 = R0 & R1;
78 45
79 /* Disabling of CPLBs should be proceeded by a CSYNC */ 46 /* Disable circular buffers */
47 L0 = r6;
48 L1 = r6;
49 L2 = r6;
50 L3 = r6;
51
52 /* Disable hardware loops in case we were started by 'go' */
53 LC0 = r6;
54 LC1 = r6;
55
56 /*
57 * Clear ITEST_COMMAND and DTEST_COMMAND registers,
58 * Leaving these as non-zero can confuse the emulator
59 */
60 [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
61 [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
80 CSYNC; 62 CSYNC;
81 [p0] = R0; 63
64 trace_buffer_init(p0,r0);
65
66 /* Turn off the icache */
67 r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
68 BITCLR (r1, ENICPLB_P);
69 [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
82 SSYNC; 70 SSYNC;
83 71
84 /* Turn off the dcache */ 72 /* Turn off the dcache */
85 p0.l = LO(DMEM_CONTROL); 73 r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
86 p0.h = HI(DMEM_CONTROL); 74 BITCLR (r1, ENDCPLB_P);
87 R1 = [p0]; 75 [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
88 R0 = ~ENDCPLB;
89 R0 = R0 & R1;
90
91 /* Disabling of CPLBs should be proceeded by a CSYNC */
92 CSYNC;
93 [p0] = R0;
94 SSYNC; 76 SSYNC;
95 77
96 /* in case of double faults, save a few things */ 78 /* in case of double faults, save a few things */
97 p0.l = _init_retx_coreb; 79 p1.l = _initial_pda_coreb;
98 p0.h = _init_retx_coreb; 80 p1.h = _initial_pda_coreb;
99 R0 = RETX; 81 r4 = RETX;
100 [P0] = R0;
101
102#ifdef CONFIG_DEBUG_DOUBLEFAULT 82#ifdef CONFIG_DEBUG_DOUBLEFAULT
103 /* Only save these if we are storing them, 83 /* Only save these if we are storing them,
104 * This happens here, since L1 gets clobbered 84 * This happens here, since L1 gets clobbered
105 * below 85 * below
106 */ 86 */
107 GET_PDA(p0, r0); 87 GET_PDA(p0, r0);
108 r7 = [p0 + PDA_DF_RETX]; 88 r0 = [p0 + PDA_DF_RETX];
109 p1.l = _init_saved_retx_coreb; 89 r1 = [p0 + PDA_DF_DCPLB];
110 p1.h = _init_saved_retx_coreb; 90 r2 = [p0 + PDA_DF_ICPLB];
111 [p1] = r7; 91 r3 = [p0 + PDA_DF_SEQSTAT];
112 92 [p1 + PDA_INIT_DF_RETX] = r0;
113 r7 = [p0 + PDA_DF_DCPLB]; 93 [p1 + PDA_INIT_DF_DCPLB] = r1;
114 p1.l = _init_saved_dcplb_fault_addr_coreb; 94 [p1 + PDA_INIT_DF_ICPLB] = r2;
115 p1.h = _init_saved_dcplb_fault_addr_coreb; 95 [p1 + PDA_INIT_DF_SEQSTAT] = r3;
116 [p1] = r7;
117
118 r7 = [p0 + PDA_DF_ICPLB];
119 p1.l = _init_saved_icplb_fault_addr_coreb;
120 p1.h = _init_saved_icplb_fault_addr_coreb;
121 [p1] = r7;
122
123 r7 = [p0 + PDA_DF_SEQSTAT];
124 p1.l = _init_saved_seqstat_coreb;
125 p1.h = _init_saved_seqstat_coreb;
126 [p1] = r7;
127#endif 96#endif
97 [p1 + PDA_INIT_RETX] = r4;
128 98
129 /* Initialize stack pointer */ 99 /* Initialize stack pointer */
130 sp.l = lo(INITIAL_STACK); 100 sp.l = lo(INITIAL_STACK);
@@ -138,19 +108,13 @@ ENTRY(_coreb_trampoline_start)
138 108
139 /* EVT15 = _real_start */ 109 /* EVT15 = _real_start */
140 110
141 p0.l = lo(EVT15);
142 p0.h = hi(EVT15);
143 p1.l = _coreb_start; 111 p1.l = _coreb_start;
144 p1.h = _coreb_start; 112 p1.h = _coreb_start;
145 [p0] = p1; 113 [p5 + (EVT15 - COREMMR_BASE)] = p1;
146 csync; 114 csync;
147 115
148 p0.l = lo(IMASK); 116 r0 = EVT_IVG15 (z);
149 p0.h = hi(IMASK); 117 sti r0;
150 p1.l = IMASK_IVG15;
151 p1.h = 0x0;
152 [p0] = p1;
153 csync;
154 118
155 raise 15; 119 raise 15;
156 p0.l = .LWAIT_HERE; 120 p0.l = .LWAIT_HERE;
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 9cfdd49a3127..1c534d298de4 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -12,8 +12,8 @@
12.section .l1.text 12.section .l1.text
13 13
14ENTRY(_sleep_mode) 14ENTRY(_sleep_mode)
15 [--SP] = ( R7:0, P5:0 ); 15 [--SP] = (R7:4, P5:3);
16 [--SP] = RETS; 16 [--SP] = RETS;
17 17
18 call _set_sic_iwr; 18 call _set_sic_iwr;
19 19
@@ -46,15 +46,25 @@ ENTRY(_sleep_mode)
46 call _test_pll_locked; 46 call _test_pll_locked;
47 47
48 RETS = [SP++]; 48 RETS = [SP++];
49 ( R7:0, P5:0 ) = [SP++]; 49 (R7:4, P5:3) = [SP++];
50 RTS; 50 RTS;
51ENDPROC(_sleep_mode) 51ENDPROC(_sleep_mode)
52 52
53/*
54 * This func never returns as it puts the part into hibernate, and
55 * is only called from do_hibernate, so we don't bother saving or
56 * restoring any of the normal C runtime state. When we wake up,
57 * the entry point will be in do_hibernate and not here.
58 *
59 * We accept just one argument -- the value to write to VR_CTL.
60 */
53ENTRY(_hibernate_mode) 61ENTRY(_hibernate_mode)
54 [--SP] = ( R7:0, P5:0 ); 62 /* Save/setup the regs we need early for minor pipeline optimization */
55 [--SP] = RETS; 63 R4 = R0;
64 P3.H = hi(VR_CTL);
65 P3.L = lo(VR_CTL);
56 66
57 R3 = R0; 67 /* Disable all wakeup sources */
58 R0 = IWR_DISABLE_ALL; 68 R0 = IWR_DISABLE_ALL;
59 R1 = IWR_DISABLE_ALL; 69 R1 = IWR_DISABLE_ALL;
60 R2 = IWR_DISABLE_ALL; 70 R2 = IWR_DISABLE_ALL;
@@ -62,10 +72,8 @@ ENTRY(_hibernate_mode)
62 call _set_dram_srfs; 72 call _set_dram_srfs;
63 SSYNC; 73 SSYNC;
64 74
65 P0.H = hi(VR_CTL); 75 /* Finally, we climb into our cave to hibernate */
66 P0.L = lo(VR_CTL); 76 W[P3] = R4.L;
67
68 W[P0] = R3.L;
69 CLI R2; 77 CLI R2;
70 IDLE; 78 IDLE;
71.Lforever: 79.Lforever:
@@ -73,8 +81,8 @@ ENTRY(_hibernate_mode)
73ENDPROC(_hibernate_mode) 81ENDPROC(_hibernate_mode)
74 82
75ENTRY(_sleep_deeper) 83ENTRY(_sleep_deeper)
76 [--SP] = ( R7:0, P5:0 ); 84 [--SP] = (R7:4, P5:3);
77 [--SP] = RETS; 85 [--SP] = RETS;
78 86
79 CLI R4; 87 CLI R4;
80 88
@@ -167,7 +175,7 @@ ENTRY(_sleep_deeper)
167 STI R4; 175 STI R4;
168 176
169 RETS = [SP++]; 177 RETS = [SP++];
170 ( R7:0, P5:0 ) = [SP++]; 178 (R7:4, P5:3) = [SP++];
171 RTS; 179 RTS;
172ENDPROC(_sleep_deeper) 180ENDPROC(_sleep_deeper)
173 181
@@ -188,21 +196,20 @@ ENTRY(_set_dram_srfs)
188#else /* SDRAM */ 196#else /* SDRAM */
189 P0.L = lo(EBIU_SDGCTL); 197 P0.L = lo(EBIU_SDGCTL);
190 P0.H = hi(EBIU_SDGCTL); 198 P0.H = hi(EBIU_SDGCTL);
199 P1.L = lo(EBIU_SDSTAT);
200 P1.H = hi(EBIU_SDSTAT);
201
191 R2 = [P0]; 202 R2 = [P0];
192 BITSET(R2, 24); /* SRFS enter self-refresh mode */ 203 BITSET(R2, 24); /* SRFS enter self-refresh mode */
193 [P0] = R2; 204 [P0] = R2;
194 SSYNC; 205 SSYNC;
195 206
196 P0.L = lo(EBIU_SDSTAT);
197 P0.H = hi(EBIU_SDSTAT);
1981: 2071:
199 R2 = w[P0]; 208 R2 = w[P1];
200 SSYNC; 209 SSYNC;
201 cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */ 210 cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
202 if !cc jump 1b; 211 if !cc jump 1b;
203 212
204 P0.L = lo(EBIU_SDGCTL);
205 P0.H = hi(EBIU_SDGCTL);
206 R2 = [P0]; 213 R2 = [P0];
207 BITCLR(R2, 0); /* SCTLE disable CLKOUT */ 214 BITCLR(R2, 0); /* SCTLE disable CLKOUT */
208 [P0] = R2; 215 [P0] = R2;
@@ -212,6 +219,7 @@ ENDPROC(_set_dram_srfs)
212 219
213ENTRY(_unset_dram_srfs) 220ENTRY(_unset_dram_srfs)
214 /* set the dram out of self refresh mode */ 221 /* set the dram out of self refresh mode */
222
215#if defined(EBIU_RSTCTL) /* DDR */ 223#if defined(EBIU_RSTCTL) /* DDR */
216 P0.H = hi(EBIU_RSTCTL); 224 P0.H = hi(EBIU_RSTCTL);
217 P0.L = lo(EBIU_RSTCTL); 225 P0.L = lo(EBIU_RSTCTL);
@@ -219,42 +227,39 @@ ENTRY(_unset_dram_srfs)
219 BITCLR(R2, 3); /* clear SRREQ bit */ 227 BITCLR(R2, 3); /* clear SRREQ bit */
220 [P0] = R2; 228 [P0] = R2;
221#elif defined(EBIU_SDGCTL) /* SDRAM */ 229#elif defined(EBIU_SDGCTL) /* SDRAM */
222 230 /* release CLKOUT from self-refresh */
223 P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */ 231 P0.L = lo(EBIU_SDGCTL);
224 P0.H = hi(EBIU_SDGCTL); 232 P0.H = hi(EBIU_SDGCTL);
233
225 R2 = [P0]; 234 R2 = [P0];
226 BITSET(R2, 0); /* SCTLE enable CLKOUT */ 235 BITSET(R2, 0); /* SCTLE enable CLKOUT */
227 [P0] = R2 236 [P0] = R2
228 SSYNC; 237 SSYNC;
229 238
230 P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */ 239 /* release SDRAM from self-refresh */
231 P0.H = hi(EBIU_SDGCTL);
232 R2 = [P0]; 240 R2 = [P0];
233 BITCLR(R2, 24); /* clear SRFS bit */ 241 BITCLR(R2, 24); /* clear SRFS bit */
234 [P0] = R2 242 [P0] = R2
235#endif 243#endif
244
236 SSYNC; 245 SSYNC;
237 RTS; 246 RTS;
238ENDPROC(_unset_dram_srfs) 247ENDPROC(_unset_dram_srfs)
239 248
240ENTRY(_set_sic_iwr) 249ENTRY(_set_sic_iwr)
241#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \ 250#ifdef SIC_IWR0
242 defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x) 251 P0.H = hi(SYSMMR_BASE);
243 P0.H = hi(SIC_IWR0); 252 P0.L = lo(SYSMMR_BASE);
244 P0.L = lo(SIC_IWR0); 253 [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
245 P1.H = hi(SIC_IWR1); 254 [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
246 P1.L = lo(SIC_IWR1); 255# ifdef SIC_IWR2
247 [P1] = R1; 256 [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
248#if defined(CONFIG_BF54x) 257# endif
249 P1.H = hi(SIC_IWR2);
250 P1.L = lo(SIC_IWR2);
251 [P1] = R2;
252#endif
253#else 258#else
254 P0.H = hi(SIC_IWR); 259 P0.H = hi(SIC_IWR);
255 P0.L = lo(SIC_IWR); 260 P0.L = lo(SIC_IWR);
256#endif
257 [P0] = R0; 261 [P0] = R0;
262#endif
258 263
259 SSYNC; 264 SSYNC;
260 RTS; 265 RTS;
@@ -272,206 +277,55 @@ ENDPROC(_test_pll_locked)
272 277
273.section .text 278.section .text
274 279
275ENTRY(_do_hibernate) 280#define PM_REG0 R7
276 [--SP] = ( R7:0, P5:0 ); 281#define PM_REG1 R6
277 [--SP] = RETS; 282#define PM_REG2 R5
278 /* Save System MMRs */ 283#define PM_REG3 R4
279 R2 = R0; 284#define PM_REG4 R3
280 P0.H = hi(PLL_CTL); 285#define PM_REG5 R2
281 P0.L = lo(PLL_CTL); 286#define PM_REG6 R1
282 287#define PM_REG7 R0
283#ifdef SIC_IMASK0 288#define PM_REG8 P5
284 PM_SYS_PUSH(SIC_IMASK0) 289#define PM_REG9 P4
285#endif 290#define PM_REG10 P3
286#ifdef SIC_IMASK1 291#define PM_REG11 P2
287 PM_SYS_PUSH(SIC_IMASK1) 292#define PM_REG12 P1
288#endif 293#define PM_REG13 P0
289#ifdef SIC_IMASK2 294
290 PM_SYS_PUSH(SIC_IMASK2) 295#define PM_REGSET0 R7:7
291#endif 296#define PM_REGSET1 R7:6
292#ifdef SIC_IMASK 297#define PM_REGSET2 R7:5
293 PM_SYS_PUSH(SIC_IMASK) 298#define PM_REGSET3 R7:4
294#endif 299#define PM_REGSET4 R7:3
295#ifdef SIC_IAR0 300#define PM_REGSET5 R7:2
296 PM_SYS_PUSH(SIC_IAR0) 301#define PM_REGSET6 R7:1
297 PM_SYS_PUSH(SIC_IAR1) 302#define PM_REGSET7 R7:0
298 PM_SYS_PUSH(SIC_IAR2) 303#define PM_REGSET8 R7:0, P5:5
299#endif 304#define PM_REGSET9 R7:0, P5:4
300#ifdef SIC_IAR3 305#define PM_REGSET10 R7:0, P5:3
301 PM_SYS_PUSH(SIC_IAR3) 306#define PM_REGSET11 R7:0, P5:2
302#endif 307#define PM_REGSET12 R7:0, P5:1
303#ifdef SIC_IAR4 308#define PM_REGSET13 R7:0, P5:0
304 PM_SYS_PUSH(SIC_IAR4) 309
305 PM_SYS_PUSH(SIC_IAR5) 310#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
306 PM_SYS_PUSH(SIC_IAR6) 311#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
307#endif 312#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
308#ifdef SIC_IAR7 313#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
309 PM_SYS_PUSH(SIC_IAR7) 314#define PM_PUSH(n, x) PM_REG##n = [FP++];
310#endif 315#define PM_POP(n, x) [FP--] = PM_REG##n;
311#ifdef SIC_IAR8 316#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
312 PM_SYS_PUSH(SIC_IAR8) 317#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
313 PM_SYS_PUSH(SIC_IAR9) 318#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
314 PM_SYS_PUSH(SIC_IAR10) 319#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
315 PM_SYS_PUSH(SIC_IAR11) 320#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
316#endif 321#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
317 322
318#ifdef SIC_IWR 323ENTRY(_do_hibernate)
319 PM_SYS_PUSH(SIC_IWR) 324 /*
320#endif 325 * Save the core regs early so we can blow them away when
321#ifdef SIC_IWR0 326 * saving/restoring MMR states
322 PM_SYS_PUSH(SIC_IWR0) 327 */
323#endif 328 [--sp] = (R7:0, P5:0);
324#ifdef SIC_IWR1
325 PM_SYS_PUSH(SIC_IWR1)
326#endif
327#ifdef SIC_IWR2
328 PM_SYS_PUSH(SIC_IWR2)
329#endif
330
331#ifdef PINT0_ASSIGN
332 PM_SYS_PUSH(PINT0_MASK_SET)
333 PM_SYS_PUSH(PINT1_MASK_SET)
334 PM_SYS_PUSH(PINT2_MASK_SET)
335 PM_SYS_PUSH(PINT3_MASK_SET)
336 PM_SYS_PUSH(PINT0_ASSIGN)
337 PM_SYS_PUSH(PINT1_ASSIGN)
338 PM_SYS_PUSH(PINT2_ASSIGN)
339 PM_SYS_PUSH(PINT3_ASSIGN)
340 PM_SYS_PUSH(PINT0_INVERT_SET)
341 PM_SYS_PUSH(PINT1_INVERT_SET)
342 PM_SYS_PUSH(PINT2_INVERT_SET)
343 PM_SYS_PUSH(PINT3_INVERT_SET)
344 PM_SYS_PUSH(PINT0_EDGE_SET)
345 PM_SYS_PUSH(PINT1_EDGE_SET)
346 PM_SYS_PUSH(PINT2_EDGE_SET)
347 PM_SYS_PUSH(PINT3_EDGE_SET)
348#endif
349
350 PM_SYS_PUSH(EBIU_AMBCTL0)
351 PM_SYS_PUSH(EBIU_AMBCTL1)
352 PM_SYS_PUSH16(EBIU_AMGCTL)
353
354#ifdef EBIU_FCTL
355 PM_SYS_PUSH(EBIU_MBSCTL)
356 PM_SYS_PUSH(EBIU_MODE)
357 PM_SYS_PUSH(EBIU_FCTL)
358#endif
359
360#ifdef PORTCIO_FER
361 PM_SYS_PUSH16(PORTCIO_DIR)
362 PM_SYS_PUSH16(PORTCIO_INEN)
363 PM_SYS_PUSH16(PORTCIO)
364 PM_SYS_PUSH16(PORTCIO_FER)
365 PM_SYS_PUSH16(PORTDIO_DIR)
366 PM_SYS_PUSH16(PORTDIO_INEN)
367 PM_SYS_PUSH16(PORTDIO)
368 PM_SYS_PUSH16(PORTDIO_FER)
369 PM_SYS_PUSH16(PORTEIO_DIR)
370 PM_SYS_PUSH16(PORTEIO_INEN)
371 PM_SYS_PUSH16(PORTEIO)
372 PM_SYS_PUSH16(PORTEIO_FER)
373#endif
374
375 PM_SYS_PUSH16(SYSCR)
376
377 /* Save Core MMRs */
378 P0.H = hi(SRAM_BASE_ADDRESS);
379 P0.L = lo(SRAM_BASE_ADDRESS);
380
381 PM_PUSH(DMEM_CONTROL)
382 PM_PUSH(DCPLB_ADDR0)
383 PM_PUSH(DCPLB_ADDR1)
384 PM_PUSH(DCPLB_ADDR2)
385 PM_PUSH(DCPLB_ADDR3)
386 PM_PUSH(DCPLB_ADDR4)
387 PM_PUSH(DCPLB_ADDR5)
388 PM_PUSH(DCPLB_ADDR6)
389 PM_PUSH(DCPLB_ADDR7)
390 PM_PUSH(DCPLB_ADDR8)
391 PM_PUSH(DCPLB_ADDR9)
392 PM_PUSH(DCPLB_ADDR10)
393 PM_PUSH(DCPLB_ADDR11)
394 PM_PUSH(DCPLB_ADDR12)
395 PM_PUSH(DCPLB_ADDR13)
396 PM_PUSH(DCPLB_ADDR14)
397 PM_PUSH(DCPLB_ADDR15)
398 PM_PUSH(DCPLB_DATA0)
399 PM_PUSH(DCPLB_DATA1)
400 PM_PUSH(DCPLB_DATA2)
401 PM_PUSH(DCPLB_DATA3)
402 PM_PUSH(DCPLB_DATA4)
403 PM_PUSH(DCPLB_DATA5)
404 PM_PUSH(DCPLB_DATA6)
405 PM_PUSH(DCPLB_DATA7)
406 PM_PUSH(DCPLB_DATA8)
407 PM_PUSH(DCPLB_DATA9)
408 PM_PUSH(DCPLB_DATA10)
409 PM_PUSH(DCPLB_DATA11)
410 PM_PUSH(DCPLB_DATA12)
411 PM_PUSH(DCPLB_DATA13)
412 PM_PUSH(DCPLB_DATA14)
413 PM_PUSH(DCPLB_DATA15)
414 PM_PUSH(IMEM_CONTROL)
415 PM_PUSH(ICPLB_ADDR0)
416 PM_PUSH(ICPLB_ADDR1)
417 PM_PUSH(ICPLB_ADDR2)
418 PM_PUSH(ICPLB_ADDR3)
419 PM_PUSH(ICPLB_ADDR4)
420 PM_PUSH(ICPLB_ADDR5)
421 PM_PUSH(ICPLB_ADDR6)
422 PM_PUSH(ICPLB_ADDR7)
423 PM_PUSH(ICPLB_ADDR8)
424 PM_PUSH(ICPLB_ADDR9)
425 PM_PUSH(ICPLB_ADDR10)
426 PM_PUSH(ICPLB_ADDR11)
427 PM_PUSH(ICPLB_ADDR12)
428 PM_PUSH(ICPLB_ADDR13)
429 PM_PUSH(ICPLB_ADDR14)
430 PM_PUSH(ICPLB_ADDR15)
431 PM_PUSH(ICPLB_DATA0)
432 PM_PUSH(ICPLB_DATA1)
433 PM_PUSH(ICPLB_DATA2)
434 PM_PUSH(ICPLB_DATA3)
435 PM_PUSH(ICPLB_DATA4)
436 PM_PUSH(ICPLB_DATA5)
437 PM_PUSH(ICPLB_DATA6)
438 PM_PUSH(ICPLB_DATA7)
439 PM_PUSH(ICPLB_DATA8)
440 PM_PUSH(ICPLB_DATA9)
441 PM_PUSH(ICPLB_DATA10)
442 PM_PUSH(ICPLB_DATA11)
443 PM_PUSH(ICPLB_DATA12)
444 PM_PUSH(ICPLB_DATA13)
445 PM_PUSH(ICPLB_DATA14)
446 PM_PUSH(ICPLB_DATA15)
447 PM_PUSH(EVT0)
448 PM_PUSH(EVT1)
449 PM_PUSH(EVT2)
450 PM_PUSH(EVT3)
451 PM_PUSH(EVT4)
452 PM_PUSH(EVT5)
453 PM_PUSH(EVT6)
454 PM_PUSH(EVT7)
455 PM_PUSH(EVT8)
456 PM_PUSH(EVT9)
457 PM_PUSH(EVT10)
458 PM_PUSH(EVT11)
459 PM_PUSH(EVT12)
460 PM_PUSH(EVT13)
461 PM_PUSH(EVT14)
462 PM_PUSH(EVT15)
463 PM_PUSH(IMASK)
464 PM_PUSH(ILAT)
465 PM_PUSH(IPRIO)
466 PM_PUSH(TCNTL)
467 PM_PUSH(TPERIOD)
468 PM_PUSH(TSCALE)
469 PM_PUSH(TCOUNT)
470 PM_PUSH(TBUFCTL)
471
472 /* Save Core Registers */
473 [--sp] = SYSCFG;
474 [--sp] = ( R7:0, P5:0 );
475 [--sp] = fp; 329 [--sp] = fp;
476 [--sp] = usp; 330 [--sp] = usp;
477 331
@@ -506,47 +360,497 @@ ENTRY(_do_hibernate)
506 [--sp] = LB0; 360 [--sp] = LB0;
507 [--sp] = LB1; 361 [--sp] = LB1;
508 362
363 /* We can't push RETI directly as that'll change IPEND[4] */
364 r7 = RETI;
365 [--sp] = RETS;
509 [--sp] = ASTAT; 366 [--sp] = ASTAT;
510 [--sp] = CYCLES; 367 [--sp] = CYCLES;
511 [--sp] = CYCLES2; 368 [--sp] = CYCLES2;
512 369 [--sp] = SYSCFG;
513 [--sp] = RETS;
514 r0 = RETI;
515 [--sp] = r0;
516 [--sp] = RETX; 370 [--sp] = RETX;
517 [--sp] = RETN;
518 [--sp] = RETE;
519 [--sp] = SEQSTAT; 371 [--sp] = SEQSTAT;
372 [--sp] = r7;
373
374 /* Save first func arg in M3 */
375 M3 = R0;
376
377 /* Save system MMRs */
378 FP.H = hi(SYSMMR_BASE);
379 FP.L = lo(SYSMMR_BASE);
380
381#ifdef SIC_IMASK0
382 PM_SYS_PUSH(0, SIC_IMASK0)
383 PM_SYS_PUSH(1, SIC_IMASK1)
384# ifdef SIC_IMASK2
385 PM_SYS_PUSH(2, SIC_IMASK2)
386# endif
387#else
388 PM_SYS_PUSH(0, SIC_IMASK)
389#endif
390#ifdef SIC_IAR0
391 PM_SYS_PUSH(3, SIC_IAR0)
392 PM_SYS_PUSH(4, SIC_IAR1)
393 PM_SYS_PUSH(5, SIC_IAR2)
394#endif
395#ifdef SIC_IAR3
396 PM_SYS_PUSH(6, SIC_IAR3)
397#endif
398#ifdef SIC_IAR4
399 PM_SYS_PUSH(7, SIC_IAR4)
400 PM_SYS_PUSH(8, SIC_IAR5)
401 PM_SYS_PUSH(9, SIC_IAR6)
402#endif
403#ifdef SIC_IAR7
404 PM_SYS_PUSH(10, SIC_IAR7)
405#endif
406#ifdef SIC_IAR8
407 PM_SYS_PUSH(11, SIC_IAR8)
408 PM_SYS_PUSH(12, SIC_IAR9)
409 PM_SYS_PUSH(13, SIC_IAR10)
410#endif
411 PM_PUSH_SYNC(13)
412#ifdef SIC_IAR11
413 PM_SYS_PUSH(0, SIC_IAR11)
414#endif
415
416#ifdef SIC_IWR
417 PM_SYS_PUSH(1, SIC_IWR)
418#endif
419#ifdef SIC_IWR0
420 PM_SYS_PUSH(1, SIC_IWR0)
421#endif
422#ifdef SIC_IWR1
423 PM_SYS_PUSH(2, SIC_IWR1)
424#endif
425#ifdef SIC_IWR2
426 PM_SYS_PUSH(3, SIC_IWR2)
427#endif
428
429#ifdef PINT0_ASSIGN
430 PM_SYS_PUSH(4, PINT0_MASK_SET)
431 PM_SYS_PUSH(5, PINT1_MASK_SET)
432 PM_SYS_PUSH(6, PINT2_MASK_SET)
433 PM_SYS_PUSH(7, PINT3_MASK_SET)
434 PM_SYS_PUSH(8, PINT0_ASSIGN)
435 PM_SYS_PUSH(9, PINT1_ASSIGN)
436 PM_SYS_PUSH(10, PINT2_ASSIGN)
437 PM_SYS_PUSH(11, PINT3_ASSIGN)
438 PM_SYS_PUSH(12, PINT0_INVERT_SET)
439 PM_SYS_PUSH(13, PINT1_INVERT_SET)
440 PM_PUSH_SYNC(13)
441 PM_SYS_PUSH(0, PINT2_INVERT_SET)
442 PM_SYS_PUSH(1, PINT3_INVERT_SET)
443 PM_SYS_PUSH(2, PINT0_EDGE_SET)
444 PM_SYS_PUSH(3, PINT1_EDGE_SET)
445 PM_SYS_PUSH(4, PINT2_EDGE_SET)
446 PM_SYS_PUSH(5, PINT3_EDGE_SET)
447#endif
448
449 PM_SYS_PUSH16(6, SYSCR)
450
451 PM_SYS_PUSH16(7, EBIU_AMGCTL)
452 PM_SYS_PUSH(8, EBIU_AMBCTL0)
453 PM_SYS_PUSH(9, EBIU_AMBCTL1)
454#ifdef EBIU_FCTL
455 PM_SYS_PUSH(10, EBIU_MBSCTL)
456 PM_SYS_PUSH(11, EBIU_MODE)
457 PM_SYS_PUSH(12, EBIU_FCTL)
458 PM_PUSH_SYNC(12)
459#else
460 PM_PUSH_SYNC(9)
461#endif
462
463 /* Save Core MMRs */
464 I0.H = hi(COREMMR_BASE);
465 I0.L = lo(COREMMR_BASE);
466 I1 = I0;
467 I2 = I0;
468 I3 = I0;
469 B0 = I0;
470 B1 = I0;
471 B2 = I0;
472 B3 = I0;
473 I1.L = lo(DCPLB_ADDR0);
474 I2.L = lo(DCPLB_DATA0);
475 I3.L = lo(ICPLB_ADDR0);
476 B0.L = lo(ICPLB_DATA0);
477 B1.L = lo(EVT2);
478 B2.L = lo(IMASK);
479 B3.L = lo(TCNTL);
480
481 /* DCPLB Addr */
482 FP = I1;
483 PM_PUSH(0, DCPLB_ADDR0)
484 PM_PUSH(1, DCPLB_ADDR1)
485 PM_PUSH(2, DCPLB_ADDR2)
486 PM_PUSH(3, DCPLB_ADDR3)
487 PM_PUSH(4, DCPLB_ADDR4)
488 PM_PUSH(5, DCPLB_ADDR5)
489 PM_PUSH(6, DCPLB_ADDR6)
490 PM_PUSH(7, DCPLB_ADDR7)
491 PM_PUSH(8, DCPLB_ADDR8)
492 PM_PUSH(9, DCPLB_ADDR9)
493 PM_PUSH(10, DCPLB_ADDR10)
494 PM_PUSH(11, DCPLB_ADDR11)
495 PM_PUSH(12, DCPLB_ADDR12)
496 PM_PUSH(13, DCPLB_ADDR13)
497 PM_PUSH_SYNC(13)
498 PM_PUSH(0, DCPLB_ADDR14)
499 PM_PUSH(1, DCPLB_ADDR15)
500
501 /* DCPLB Data */
502 FP = I2;
503 PM_PUSH(2, DCPLB_DATA0)
504 PM_PUSH(3, DCPLB_DATA1)
505 PM_PUSH(4, DCPLB_DATA2)
506 PM_PUSH(5, DCPLB_DATA3)
507 PM_PUSH(6, DCPLB_DATA4)
508 PM_PUSH(7, DCPLB_DATA5)
509 PM_PUSH(8, DCPLB_DATA6)
510 PM_PUSH(9, DCPLB_DATA7)
511 PM_PUSH(10, DCPLB_DATA8)
512 PM_PUSH(11, DCPLB_DATA9)
513 PM_PUSH(12, DCPLB_DATA10)
514 PM_PUSH(13, DCPLB_DATA11)
515 PM_PUSH_SYNC(13)
516 PM_PUSH(0, DCPLB_DATA12)
517 PM_PUSH(1, DCPLB_DATA13)
518 PM_PUSH(2, DCPLB_DATA14)
519 PM_PUSH(3, DCPLB_DATA15)
520
521 /* ICPLB Addr */
522 FP = I3;
523 PM_PUSH(4, ICPLB_ADDR0)
524 PM_PUSH(5, ICPLB_ADDR1)
525 PM_PUSH(6, ICPLB_ADDR2)
526 PM_PUSH(7, ICPLB_ADDR3)
527 PM_PUSH(8, ICPLB_ADDR4)
528 PM_PUSH(9, ICPLB_ADDR5)
529 PM_PUSH(10, ICPLB_ADDR6)
530 PM_PUSH(11, ICPLB_ADDR7)
531 PM_PUSH(12, ICPLB_ADDR8)
532 PM_PUSH(13, ICPLB_ADDR9)
533 PM_PUSH_SYNC(13)
534 PM_PUSH(0, ICPLB_ADDR10)
535 PM_PUSH(1, ICPLB_ADDR11)
536 PM_PUSH(2, ICPLB_ADDR12)
537 PM_PUSH(3, ICPLB_ADDR13)
538 PM_PUSH(4, ICPLB_ADDR14)
539 PM_PUSH(5, ICPLB_ADDR15)
540
541 /* ICPLB Data */
542 FP = B0;
543 PM_PUSH(6, ICPLB_DATA0)
544 PM_PUSH(7, ICPLB_DATA1)
545 PM_PUSH(8, ICPLB_DATA2)
546 PM_PUSH(9, ICPLB_DATA3)
547 PM_PUSH(10, ICPLB_DATA4)
548 PM_PUSH(11, ICPLB_DATA5)
549 PM_PUSH(12, ICPLB_DATA6)
550 PM_PUSH(13, ICPLB_DATA7)
551 PM_PUSH_SYNC(13)
552 PM_PUSH(0, ICPLB_DATA8)
553 PM_PUSH(1, ICPLB_DATA9)
554 PM_PUSH(2, ICPLB_DATA10)
555 PM_PUSH(3, ICPLB_DATA11)
556 PM_PUSH(4, ICPLB_DATA12)
557 PM_PUSH(5, ICPLB_DATA13)
558 PM_PUSH(6, ICPLB_DATA14)
559 PM_PUSH(7, ICPLB_DATA15)
560
561 /* Event Vectors */
562 FP = B1;
563 PM_PUSH(8, EVT2)
564 PM_PUSH(9, EVT3)
565 FP += 4; /* EVT4 */
566 PM_PUSH(10, EVT5)
567 PM_PUSH(11, EVT6)
568 PM_PUSH(12, EVT7)
569 PM_PUSH(13, EVT8)
570 PM_PUSH_SYNC(13)
571 PM_PUSH(0, EVT9)
572 PM_PUSH(1, EVT10)
573 PM_PUSH(2, EVT11)
574 PM_PUSH(3, EVT12)
575 PM_PUSH(4, EVT13)
576 PM_PUSH(5, EVT14)
577 PM_PUSH(6, EVT15)
578
579 /* CEC */
580 FP = B2;
581 PM_PUSH(7, IMASK)
582 FP += 4; /* IPEND */
583 PM_PUSH(8, ILAT)
584 PM_PUSH(9, IPRIO)
585
586 /* Core Timer */
587 FP = B3;
588 PM_PUSH(10, TCNTL)
589 PM_PUSH(11, TPERIOD)
590 PM_PUSH(12, TSCALE)
591 PM_PUSH(13, TCOUNT)
592 PM_PUSH_SYNC(13)
593
594 /* Misc non-contiguous registers */
595 FP = I0;
596 PM_CORE_PUSH(0, DMEM_CONTROL);
597 PM_CORE_PUSH(1, IMEM_CONTROL);
598 PM_CORE_PUSH(2, TBUFCTL);
599 PM_PUSH_SYNC(2)
600
601 /* Setup args to hibernate mode early for pipeline optimization */
602 R0 = M3;
603 P1.H = _hibernate_mode;
604 P1.L = _hibernate_mode;
520 605
521 /* Save Magic, return address and Stack Pointer */ 606 /* Save Magic, return address and Stack Pointer */
522 P0.H = 0; 607 P0 = 0;
523 P0.L = 0; 608 R1.H = 0xDEAD; /* Hibernate Magic */
524 R0.H = 0xDEAD; /* Hibernate Magic */ 609 R1.L = 0xBEEF;
525 R0.L = 0xBEEF; 610 R2.H = .Lpm_resume_here;
526 [P0++] = R0; /* Store Hibernate Magic */ 611 R2.L = .Lpm_resume_here;
527 R0.H = .Lpm_resume_here; 612 [P0++] = R1; /* Store Hibernate Magic */
528 R0.L = .Lpm_resume_here; 613 [P0++] = R2; /* Save Return Address */
529 [P0++] = R0; /* Save Return Address */
530 [P0++] = SP; /* Save Stack Pointer */ 614 [P0++] = SP; /* Save Stack Pointer */
531 P0.H = _hibernate_mode; 615
532 P0.L = _hibernate_mode; 616 /* Must use an indirect call as we need to jump to L1 */
533 R0 = R2; 617 call (P1); /* Goodbye */
534 call (P0); /* Goodbye */
535 618
536.Lpm_resume_here: 619.Lpm_resume_here:
537 620
621 /* Restore Core MMRs */
622 I0.H = hi(COREMMR_BASE);
623 I0.L = lo(COREMMR_BASE);
624 I1 = I0;
625 I2 = I0;
626 I3 = I0;
627 B0 = I0;
628 B1 = I0;
629 B2 = I0;
630 B3 = I0;
631 I1.L = lo(DCPLB_ADDR15);
632 I2.L = lo(DCPLB_DATA15);
633 I3.L = lo(ICPLB_ADDR15);
634 B0.L = lo(ICPLB_DATA15);
635 B1.L = lo(EVT15);
636 B2.L = lo(IPRIO);
637 B3.L = lo(TCOUNT);
638
639 /* Misc non-contiguous registers */
640 FP = I0;
641 PM_POP_SYNC(2)
642 PM_CORE_POP(2, TBUFCTL)
643 PM_CORE_POP(1, IMEM_CONTROL)
644 PM_CORE_POP(0, DMEM_CONTROL)
645
646 /* Core Timer */
647 PM_POP_SYNC(13)
648 FP = B3;
649 PM_POP(13, TCOUNT)
650 PM_POP(12, TSCALE)
651 PM_POP(11, TPERIOD)
652 PM_POP(10, TCNTL)
653
654 /* CEC */
655 FP = B2;
656 PM_POP(9, IPRIO)
657 PM_POP(8, ILAT)
658 FP += -4; /* IPEND */
659 PM_POP(7, IMASK)
660
661 /* Event Vectors */
662 FP = B1;
663 PM_POP(6, EVT15)
664 PM_POP(5, EVT14)
665 PM_POP(4, EVT13)
666 PM_POP(3, EVT12)
667 PM_POP(2, EVT11)
668 PM_POP(1, EVT10)
669 PM_POP(0, EVT9)
670 PM_POP_SYNC(13)
671 PM_POP(13, EVT8)
672 PM_POP(12, EVT7)
673 PM_POP(11, EVT6)
674 PM_POP(10, EVT5)
675 FP += -4; /* EVT4 */
676 PM_POP(9, EVT3)
677 PM_POP(8, EVT2)
678
679 /* ICPLB Data */
680 FP = B0;
681 PM_POP(7, ICPLB_DATA15)
682 PM_POP(6, ICPLB_DATA14)
683 PM_POP(5, ICPLB_DATA13)
684 PM_POP(4, ICPLB_DATA12)
685 PM_POP(3, ICPLB_DATA11)
686 PM_POP(2, ICPLB_DATA10)
687 PM_POP(1, ICPLB_DATA9)
688 PM_POP(0, ICPLB_DATA8)
689 PM_POP_SYNC(13)
690 PM_POP(13, ICPLB_DATA7)
691 PM_POP(12, ICPLB_DATA6)
692 PM_POP(11, ICPLB_DATA5)
693 PM_POP(10, ICPLB_DATA4)
694 PM_POP(9, ICPLB_DATA3)
695 PM_POP(8, ICPLB_DATA2)
696 PM_POP(7, ICPLB_DATA1)
697 PM_POP(6, ICPLB_DATA0)
698
699 /* ICPLB Addr */
700 FP = I3;
701 PM_POP(5, ICPLB_ADDR15)
702 PM_POP(4, ICPLB_ADDR14)
703 PM_POP(3, ICPLB_ADDR13)
704 PM_POP(2, ICPLB_ADDR12)
705 PM_POP(1, ICPLB_ADDR11)
706 PM_POP(0, ICPLB_ADDR10)
707 PM_POP_SYNC(13)
708 PM_POP(13, ICPLB_ADDR9)
709 PM_POP(12, ICPLB_ADDR8)
710 PM_POP(11, ICPLB_ADDR7)
711 PM_POP(10, ICPLB_ADDR6)
712 PM_POP(9, ICPLB_ADDR5)
713 PM_POP(8, ICPLB_ADDR4)
714 PM_POP(7, ICPLB_ADDR3)
715 PM_POP(6, ICPLB_ADDR2)
716 PM_POP(5, ICPLB_ADDR1)
717 PM_POP(4, ICPLB_ADDR0)
718
719 /* DCPLB Data */
720 FP = I2;
721 PM_POP(3, DCPLB_DATA15)
722 PM_POP(2, DCPLB_DATA14)
723 PM_POP(1, DCPLB_DATA13)
724 PM_POP(0, DCPLB_DATA12)
725 PM_POP_SYNC(13)
726 PM_POP(13, DCPLB_DATA11)
727 PM_POP(12, DCPLB_DATA10)
728 PM_POP(11, DCPLB_DATA9)
729 PM_POP(10, DCPLB_DATA8)
730 PM_POP(9, DCPLB_DATA7)
731 PM_POP(8, DCPLB_DATA6)
732 PM_POP(7, DCPLB_DATA5)
733 PM_POP(6, DCPLB_DATA4)
734 PM_POP(5, DCPLB_DATA3)
735 PM_POP(4, DCPLB_DATA2)
736 PM_POP(3, DCPLB_DATA1)
737 PM_POP(2, DCPLB_DATA0)
738
739 /* DCPLB Addr */
740 FP = I1;
741 PM_POP(1, DCPLB_ADDR15)
742 PM_POP(0, DCPLB_ADDR14)
743 PM_POP_SYNC(13)
744 PM_POP(13, DCPLB_ADDR13)
745 PM_POP(12, DCPLB_ADDR12)
746 PM_POP(11, DCPLB_ADDR11)
747 PM_POP(10, DCPLB_ADDR10)
748 PM_POP(9, DCPLB_ADDR9)
749 PM_POP(8, DCPLB_ADDR8)
750 PM_POP(7, DCPLB_ADDR7)
751 PM_POP(6, DCPLB_ADDR6)
752 PM_POP(5, DCPLB_ADDR5)
753 PM_POP(4, DCPLB_ADDR4)
754 PM_POP(3, DCPLB_ADDR3)
755 PM_POP(2, DCPLB_ADDR2)
756 PM_POP(1, DCPLB_ADDR1)
757 PM_POP(0, DCPLB_ADDR0)
758
759 /* Restore System MMRs */
760 FP.H = hi(SYSMMR_BASE);
761 FP.L = lo(SYSMMR_BASE);
762
763#ifdef EBIU_FCTL
764 PM_POP_SYNC(12)
765 PM_SYS_POP(12, EBIU_FCTL)
766 PM_SYS_POP(11, EBIU_MODE)
767 PM_SYS_POP(10, EBIU_MBSCTL)
768#else
769 PM_POP_SYNC(9)
770#endif
771 PM_SYS_POP(9, EBIU_AMBCTL1)
772 PM_SYS_POP(8, EBIU_AMBCTL0)
773 PM_SYS_POP16(7, EBIU_AMGCTL)
774
775 PM_SYS_POP16(6, SYSCR)
776
777#ifdef PINT0_ASSIGN
778 PM_SYS_POP(5, PINT3_EDGE_SET)
779 PM_SYS_POP(4, PINT2_EDGE_SET)
780 PM_SYS_POP(3, PINT1_EDGE_SET)
781 PM_SYS_POP(2, PINT0_EDGE_SET)
782 PM_SYS_POP(1, PINT3_INVERT_SET)
783 PM_SYS_POP(0, PINT2_INVERT_SET)
784 PM_POP_SYNC(13)
785 PM_SYS_POP(13, PINT1_INVERT_SET)
786 PM_SYS_POP(12, PINT0_INVERT_SET)
787 PM_SYS_POP(11, PINT3_ASSIGN)
788 PM_SYS_POP(10, PINT2_ASSIGN)
789 PM_SYS_POP(9, PINT1_ASSIGN)
790 PM_SYS_POP(8, PINT0_ASSIGN)
791 PM_SYS_POP(7, PINT3_MASK_SET)
792 PM_SYS_POP(6, PINT2_MASK_SET)
793 PM_SYS_POP(5, PINT1_MASK_SET)
794 PM_SYS_POP(4, PINT0_MASK_SET)
795#endif
796
797#ifdef SIC_IWR2
798 PM_SYS_POP(3, SIC_IWR2)
799#endif
800#ifdef SIC_IWR1
801 PM_SYS_POP(2, SIC_IWR1)
802#endif
803#ifdef SIC_IWR0
804 PM_SYS_POP(1, SIC_IWR0)
805#endif
806#ifdef SIC_IWR
807 PM_SYS_POP(1, SIC_IWR)
808#endif
809
810#ifdef SIC_IAR11
811 PM_SYS_POP(0, SIC_IAR11)
812#endif
813 PM_POP_SYNC(13)
814#ifdef SIC_IAR8
815 PM_SYS_POP(13, SIC_IAR10)
816 PM_SYS_POP(12, SIC_IAR9)
817 PM_SYS_POP(11, SIC_IAR8)
818#endif
819#ifdef SIC_IAR7
820 PM_SYS_POP(10, SIC_IAR7)
821#endif
822#ifdef SIC_IAR6
823 PM_SYS_POP(9, SIC_IAR6)
824 PM_SYS_POP(8, SIC_IAR5)
825 PM_SYS_POP(7, SIC_IAR4)
826#endif
827#ifdef SIC_IAR3
828 PM_SYS_POP(6, SIC_IAR3)
829#endif
830#ifdef SIC_IAR0
831 PM_SYS_POP(5, SIC_IAR2)
832 PM_SYS_POP(4, SIC_IAR1)
833 PM_SYS_POP(3, SIC_IAR0)
834#endif
835#ifdef SIC_IMASK0
836# ifdef SIC_IMASK2
837 PM_SYS_POP(2, SIC_IMASK2)
838# endif
839 PM_SYS_POP(1, SIC_IMASK1)
840 PM_SYS_POP(0, SIC_IMASK0)
841#else
842 PM_SYS_POP(0, SIC_IMASK)
843#endif
844
538 /* Restore Core Registers */ 845 /* Restore Core Registers */
846 RETI = [sp++];
539 SEQSTAT = [sp++]; 847 SEQSTAT = [sp++];
540 RETE = [sp++];
541 RETN = [sp++];
542 RETX = [sp++]; 848 RETX = [sp++];
543 r0 = [sp++]; 849 SYSCFG = [sp++];
544 RETI = r0;
545 RETS = [sp++];
546
547 CYCLES2 = [sp++]; 850 CYCLES2 = [sp++];
548 CYCLES = [sp++]; 851 CYCLES = [sp++];
549 ASTAT = [sp++]; 852 ASTAT = [sp++];
853 RETS = [sp++];
550 854
551 LB1 = [sp++]; 855 LB1 = [sp++];
552 LB0 = [sp++]; 856 LB0 = [sp++];
@@ -581,204 +885,10 @@ ENTRY(_do_hibernate)
581 885
582 usp = [sp++]; 886 usp = [sp++];
583 fp = [sp++]; 887 fp = [sp++];
584 888 (R7:0, P5:0) = [sp++];
585 ( R7 : 0, P5 : 0) = [ SP ++ ];
586 SYSCFG = [sp++];
587
588 /* Restore Core MMRs */
589
590 PM_POP(TBUFCTL)
591 PM_POP(TCOUNT)
592 PM_POP(TSCALE)
593 PM_POP(TPERIOD)
594 PM_POP(TCNTL)
595 PM_POP(IPRIO)
596 PM_POP(ILAT)
597 PM_POP(IMASK)
598 PM_POP(EVT15)
599 PM_POP(EVT14)
600 PM_POP(EVT13)
601 PM_POP(EVT12)
602 PM_POP(EVT11)
603 PM_POP(EVT10)
604 PM_POP(EVT9)
605 PM_POP(EVT8)
606 PM_POP(EVT7)
607 PM_POP(EVT6)
608 PM_POP(EVT5)
609 PM_POP(EVT4)
610 PM_POP(EVT3)
611 PM_POP(EVT2)
612 PM_POP(EVT1)
613 PM_POP(EVT0)
614 PM_POP(ICPLB_DATA15)
615 PM_POP(ICPLB_DATA14)
616 PM_POP(ICPLB_DATA13)
617 PM_POP(ICPLB_DATA12)
618 PM_POP(ICPLB_DATA11)
619 PM_POP(ICPLB_DATA10)
620 PM_POP(ICPLB_DATA9)
621 PM_POP(ICPLB_DATA8)
622 PM_POP(ICPLB_DATA7)
623 PM_POP(ICPLB_DATA6)
624 PM_POP(ICPLB_DATA5)
625 PM_POP(ICPLB_DATA4)
626 PM_POP(ICPLB_DATA3)
627 PM_POP(ICPLB_DATA2)
628 PM_POP(ICPLB_DATA1)
629 PM_POP(ICPLB_DATA0)
630 PM_POP(ICPLB_ADDR15)
631 PM_POP(ICPLB_ADDR14)
632 PM_POP(ICPLB_ADDR13)
633 PM_POP(ICPLB_ADDR12)
634 PM_POP(ICPLB_ADDR11)
635 PM_POP(ICPLB_ADDR10)
636 PM_POP(ICPLB_ADDR9)
637 PM_POP(ICPLB_ADDR8)
638 PM_POP(ICPLB_ADDR7)
639 PM_POP(ICPLB_ADDR6)
640 PM_POP(ICPLB_ADDR5)
641 PM_POP(ICPLB_ADDR4)
642 PM_POP(ICPLB_ADDR3)
643 PM_POP(ICPLB_ADDR2)
644 PM_POP(ICPLB_ADDR1)
645 PM_POP(ICPLB_ADDR0)
646 PM_POP(IMEM_CONTROL)
647 PM_POP(DCPLB_DATA15)
648 PM_POP(DCPLB_DATA14)
649 PM_POP(DCPLB_DATA13)
650 PM_POP(DCPLB_DATA12)
651 PM_POP(DCPLB_DATA11)
652 PM_POP(DCPLB_DATA10)
653 PM_POP(DCPLB_DATA9)
654 PM_POP(DCPLB_DATA8)
655 PM_POP(DCPLB_DATA7)
656 PM_POP(DCPLB_DATA6)
657 PM_POP(DCPLB_DATA5)
658 PM_POP(DCPLB_DATA4)
659 PM_POP(DCPLB_DATA3)
660 PM_POP(DCPLB_DATA2)
661 PM_POP(DCPLB_DATA1)
662 PM_POP(DCPLB_DATA0)
663 PM_POP(DCPLB_ADDR15)
664 PM_POP(DCPLB_ADDR14)
665 PM_POP(DCPLB_ADDR13)
666 PM_POP(DCPLB_ADDR12)
667 PM_POP(DCPLB_ADDR11)
668 PM_POP(DCPLB_ADDR10)
669 PM_POP(DCPLB_ADDR9)
670 PM_POP(DCPLB_ADDR8)
671 PM_POP(DCPLB_ADDR7)
672 PM_POP(DCPLB_ADDR6)
673 PM_POP(DCPLB_ADDR5)
674 PM_POP(DCPLB_ADDR4)
675 PM_POP(DCPLB_ADDR3)
676 PM_POP(DCPLB_ADDR2)
677 PM_POP(DCPLB_ADDR1)
678 PM_POP(DCPLB_ADDR0)
679 PM_POP(DMEM_CONTROL)
680
681 /* Restore System MMRs */
682
683 P0.H = hi(PLL_CTL);
684 P0.L = lo(PLL_CTL);
685 PM_SYS_POP16(SYSCR)
686
687#ifdef PORTCIO_FER
688 PM_SYS_POP16(PORTEIO_FER)
689 PM_SYS_POP16(PORTEIO)
690 PM_SYS_POP16(PORTEIO_INEN)
691 PM_SYS_POP16(PORTEIO_DIR)
692 PM_SYS_POP16(PORTDIO_FER)
693 PM_SYS_POP16(PORTDIO)
694 PM_SYS_POP16(PORTDIO_INEN)
695 PM_SYS_POP16(PORTDIO_DIR)
696 PM_SYS_POP16(PORTCIO_FER)
697 PM_SYS_POP16(PORTCIO)
698 PM_SYS_POP16(PORTCIO_INEN)
699 PM_SYS_POP16(PORTCIO_DIR)
700#endif
701
702#ifdef EBIU_FCTL
703 PM_SYS_POP(EBIU_FCTL)
704 PM_SYS_POP(EBIU_MODE)
705 PM_SYS_POP(EBIU_MBSCTL)
706#endif
707 PM_SYS_POP16(EBIU_AMGCTL)
708 PM_SYS_POP(EBIU_AMBCTL1)
709 PM_SYS_POP(EBIU_AMBCTL0)
710
711#ifdef PINT0_ASSIGN
712 PM_SYS_POP(PINT3_EDGE_SET)
713 PM_SYS_POP(PINT2_EDGE_SET)
714 PM_SYS_POP(PINT1_EDGE_SET)
715 PM_SYS_POP(PINT0_EDGE_SET)
716 PM_SYS_POP(PINT3_INVERT_SET)
717 PM_SYS_POP(PINT2_INVERT_SET)
718 PM_SYS_POP(PINT1_INVERT_SET)
719 PM_SYS_POP(PINT0_INVERT_SET)
720 PM_SYS_POP(PINT3_ASSIGN)
721 PM_SYS_POP(PINT2_ASSIGN)
722 PM_SYS_POP(PINT1_ASSIGN)
723 PM_SYS_POP(PINT0_ASSIGN)
724 PM_SYS_POP(PINT3_MASK_SET)
725 PM_SYS_POP(PINT2_MASK_SET)
726 PM_SYS_POP(PINT1_MASK_SET)
727 PM_SYS_POP(PINT0_MASK_SET)
728#endif
729
730#ifdef SIC_IWR2
731 PM_SYS_POP(SIC_IWR2)
732#endif
733#ifdef SIC_IWR1
734 PM_SYS_POP(SIC_IWR1)
735#endif
736#ifdef SIC_IWR0
737 PM_SYS_POP(SIC_IWR0)
738#endif
739#ifdef SIC_IWR
740 PM_SYS_POP(SIC_IWR)
741#endif
742
743#ifdef SIC_IAR8
744 PM_SYS_POP(SIC_IAR11)
745 PM_SYS_POP(SIC_IAR10)
746 PM_SYS_POP(SIC_IAR9)
747 PM_SYS_POP(SIC_IAR8)
748#endif
749#ifdef SIC_IAR7
750 PM_SYS_POP(SIC_IAR7)
751#endif
752#ifdef SIC_IAR6
753 PM_SYS_POP(SIC_IAR6)
754 PM_SYS_POP(SIC_IAR5)
755 PM_SYS_POP(SIC_IAR4)
756#endif
757#ifdef SIC_IAR3
758 PM_SYS_POP(SIC_IAR3)
759#endif
760#ifdef SIC_IAR0
761 PM_SYS_POP(SIC_IAR2)
762 PM_SYS_POP(SIC_IAR1)
763 PM_SYS_POP(SIC_IAR0)
764#endif
765#ifdef SIC_IMASK
766 PM_SYS_POP(SIC_IMASK)
767#endif
768#ifdef SIC_IMASK2
769 PM_SYS_POP(SIC_IMASK2)
770#endif
771#ifdef SIC_IMASK1
772 PM_SYS_POP(SIC_IMASK1)
773#endif
774#ifdef SIC_IMASK0
775 PM_SYS_POP(SIC_IMASK0)
776#endif
777 889
778 [--sp] = RETI; /* Clear Global Interrupt Disable */ 890 [--sp] = RETI; /* Clear Global Interrupt Disable */
779 SP += 4; 891 SP += 4;
780 892
781 RETS = [SP++];
782 ( R7:0, P5:0 ) = [SP++];
783 RTS; 893 RTS;
784ENDPROC(_do_hibernate) 894ENDPROC(_do_hibernate)
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
index 76de5724c1e3..8b4d98854403 100644
--- a/arch/blackfin/mach-common/head.S
+++ b/arch/blackfin/mach-common/head.S
@@ -85,37 +85,25 @@ ENTRY(__start)
85 SSYNC; 85 SSYNC;
86 86
87 /* in case of double faults, save a few things */ 87 /* in case of double faults, save a few things */
88 p0.l = _init_retx; 88 p1.l = _initial_pda;
89 p0.h = _init_retx; 89 p1.h = _initial_pda;
90 R0 = RETX; 90 r4 = RETX;
91 [P0] = R0;
92
93#ifdef CONFIG_DEBUG_DOUBLEFAULT 91#ifdef CONFIG_DEBUG_DOUBLEFAULT
94 /* Only save these if we are storing them, 92 /* Only save these if we are storing them,
95 * This happens here, since L1 gets clobbered 93 * This happens here, since L1 gets clobbered
96 * below 94 * below
97 */ 95 */
98 GET_PDA(p0, r0); 96 GET_PDA(p0, r0);
99 r5 = [p0 + PDA_DF_RETX]; 97 r0 = [p0 + PDA_DF_RETX];
100 p1.l = _init_saved_retx; 98 r1 = [p0 + PDA_DF_DCPLB];
101 p1.h = _init_saved_retx; 99 r2 = [p0 + PDA_DF_ICPLB];
102 [p1] = r5; 100 r3 = [p0 + PDA_DF_SEQSTAT];
103 101 [p1 + PDA_INIT_DF_RETX] = r0;
104 r5 = [p0 + PDA_DF_DCPLB]; 102 [p1 + PDA_INIT_DF_DCPLB] = r1;
105 p1.l = _init_saved_dcplb_fault_addr; 103 [p1 + PDA_INIT_DF_ICPLB] = r2;
106 p1.h = _init_saved_dcplb_fault_addr; 104 [p1 + PDA_INIT_DF_SEQSTAT] = r3;
107 [p1] = r5;
108
109 r5 = [p0 + PDA_DF_ICPLB];
110 p1.l = _init_saved_icplb_fault_addr;
111 p1.h = _init_saved_icplb_fault_addr;
112 [p1] = r5;
113
114 r5 = [p0 + PDA_DF_SEQSTAT];
115 p1.l = _init_saved_seqstat;
116 p1.h = _init_saved_seqstat;
117 [p1] = r5;
118#endif 105#endif
106 [p1 + PDA_INIT_RETX] = r4;
119 107
120 /* Initialize stack pointer */ 108 /* Initialize stack pointer */
121 sp.l = _init_thread_union + THREAD_SIZE; 109 sp.l = _init_thread_union + THREAD_SIZE;
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 1177369f9922..332dace6af34 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -444,7 +444,7 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
444static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); 444static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
445extern void bfin_gpio_irq_prepare(unsigned gpio); 445extern void bfin_gpio_irq_prepare(unsigned gpio);
446 446
447#if !defined(CONFIG_BF54x) 447#if !BFIN_GPIO_PINT
448 448
449static void bfin_gpio_ack_irq(struct irq_data *d) 449static void bfin_gpio_ack_irq(struct irq_data *d)
450{ 450{
@@ -633,7 +633,7 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
633 bfin_demux_gpio_block(irq); 633 bfin_demux_gpio_block(irq);
634} 634}
635 635
636#else /* CONFIG_BF54x */ 636#else
637 637
638#define NR_PINT_SYS_IRQS 4 638#define NR_PINT_SYS_IRQS 4
639#define NR_PINT_BITS 32 639#define NR_PINT_BITS 32
@@ -647,24 +647,11 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
647static unsigned char irq2pint_lut[NR_PINTS]; 647static unsigned char irq2pint_lut[NR_PINTS];
648static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; 648static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
649 649
650struct pin_int_t { 650static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
651 unsigned int mask_set; 651 (struct bfin_pint_regs *)PINT0_MASK_SET,
652 unsigned int mask_clear; 652 (struct bfin_pint_regs *)PINT1_MASK_SET,
653 unsigned int request; 653 (struct bfin_pint_regs *)PINT2_MASK_SET,
654 unsigned int assign; 654 (struct bfin_pint_regs *)PINT3_MASK_SET,
655 unsigned int edge_set;
656 unsigned int edge_clear;
657 unsigned int invert_set;
658 unsigned int invert_clear;
659 unsigned int pinstate;
660 unsigned int latch;
661};
662
663static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
664 (struct pin_int_t *)PINT0_MASK_SET,
665 (struct pin_int_t *)PINT1_MASK_SET,
666 (struct pin_int_t *)PINT2_MASK_SET,
667 (struct pin_int_t *)PINT3_MASK_SET,
668}; 655};
669 656
670inline unsigned int get_irq_base(u32 bank, u8 bmap) 657inline unsigned int get_irq_base(u32 bank, u8 bmap)
@@ -981,7 +968,7 @@ int __init init_arch_irq(void)
981 968
982 local_irq_disable(); 969 local_irq_disable();
983 970
984#ifdef CONFIG_BF54x 971#if BFIN_GPIO_PINT
985# ifdef CONFIG_PINTx_REASSIGN 972# ifdef CONFIG_PINTx_REASSIGN
986 pint[0]->assign = CONFIG_PINT0_ASSIGN; 973 pint[0]->assign = CONFIG_PINT0_ASSIGN;
987 pint[1]->assign = CONFIG_PINT1_ASSIGN; 974 pint[1]->assign = CONFIG_PINT1_ASSIGN;
@@ -999,16 +986,16 @@ int __init init_arch_irq(void)
999 irq_set_chip(irq, &bfin_internal_irqchip); 986 irq_set_chip(irq, &bfin_internal_irqchip);
1000 987
1001 switch (irq) { 988 switch (irq) {
1002#if defined(BF537_FAMILY) 989#if BFIN_GPIO_PINT
1003 case IRQ_PH_INTA_MAC_RX:
1004 case IRQ_PF_INTA_PG_INTA:
1005#elif defined(BF533_FAMILY)
1006 case IRQ_PROG_INTA:
1007#elif defined(CONFIG_BF54x)
1008 case IRQ_PINT0: 990 case IRQ_PINT0:
1009 case IRQ_PINT1: 991 case IRQ_PINT1:
1010 case IRQ_PINT2: 992 case IRQ_PINT2:
1011 case IRQ_PINT3: 993 case IRQ_PINT3:
994#elif defined(BF537_FAMILY)
995 case IRQ_PH_INTA_MAC_RX:
996 case IRQ_PF_INTA_PG_INTA:
997#elif defined(BF533_FAMILY)
998 case IRQ_PROG_INTA:
1012#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) 999#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1013 case IRQ_PORTF_INTA: 1000 case IRQ_PORTF_INTA:
1014 case IRQ_PORTG_INTA: 1001 case IRQ_PORTG_INTA:
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 35e7e1eb0188..1c143a4de5f5 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -45,9 +45,7 @@ struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
45unsigned long blackfin_iflush_l1_entry[NR_CPUS]; 45unsigned long blackfin_iflush_l1_entry[NR_CPUS];
46#endif 46#endif
47 47
48void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, 48struct blackfin_initial_pda __cpuinitdata initial_pda_coreb;
49 *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
50 *init_saved_dcplb_fault_addr_coreb;
51 49
52#define BFIN_IPI_RESCHEDULE 0 50#define BFIN_IPI_RESCHEDULE 0
53#define BFIN_IPI_CALL_FUNC 1 51#define BFIN_IPI_CALL_FUNC 1
@@ -369,13 +367,16 @@ void __cpuinit secondary_start_kernel(void)
369 if (_bfin_swrst & SWRST_DBL_FAULT_B) { 367 if (_bfin_swrst & SWRST_DBL_FAULT_B) {
370 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n"); 368 printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
371#ifdef CONFIG_DEBUG_DOUBLEFAULT 369#ifdef CONFIG_DEBUG_DOUBLEFAULT
372 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n", 370 printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
373 (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb); 371 initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
374 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb); 372 initial_pda_coreb.retx_doublefault);
375 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb); 373 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
374 initial_pda_coreb.dcplb_doublefault_addr);
375 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
376 initial_pda_coreb.icplb_doublefault_addr);
376#endif 377#endif
377 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", 378 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
378 init_retx_coreb); 379 initial_pda_coreb.retx);
379 } 380 }
380 381
381 /* 382 /*
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-07 17:39:54 -0500