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-rw-r--r--arch/m68k/include/asm/m54xxsim.h21
-rw-r--r--arch/m68k/platform/coldfire/m54xx.c10
-rw-r--r--arch/m68k/platform/coldfire/pci.c4
3 files changed, 20 insertions, 15 deletions
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index d6a50799ff27..d3bd83887429 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -70,15 +70,25 @@
70#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ 70#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
71 71
72/* 72/*
73 * Some PSC related definitions 73 * Pin Assignment register definitions
74 */ 74 */
75#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) 75#define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
76#define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
77#define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
78#define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
79#define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
80#define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
81#define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
82#define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
83#define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
84#define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
85#define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
86#define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
87
76#define MCF_PAR_SDA (0x0008) 88#define MCF_PAR_SDA (0x0008)
77#define MCF_PAR_SCL (0x0004) 89#define MCF_PAR_SCL (0x0004)
78#define MCF_PAR_PSC_TXD (0x04) 90#define MCF_PAR_PSC_TXD (0x04)
79#define MCF_PAR_PSC_RXD (0x08) 91#define MCF_PAR_PSC_RXD (0x08)
80#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
81#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
82#define MCF_PAR_PSC_CTS_GPIO (0x00) 92#define MCF_PAR_PSC_CTS_GPIO (0x00)
83#define MCF_PAR_PSC_CTS_BCLK (0x80) 93#define MCF_PAR_PSC_CTS_BCLK (0x80)
84#define MCF_PAR_PSC_CTS_CTS (0xC0) 94#define MCF_PAR_PSC_CTS_CTS (0xC0)
@@ -87,7 +97,4 @@
87#define MCF_PAR_PSC_RTS_RTS (0x30) 97#define MCF_PAR_PSC_RTS_RTS (0x30)
88#define MCF_PAR_PSC_CANRX (0x40) 98#define MCF_PAR_PSC_CANRX (0x40)
89 99
90#define MCF_PAR_PCIBG (CONFIG_MBAR + 0xa48) /* PCI bus grant */
91#define MCF_PAR_PCIBR (CONFIG_MBAR + 0xa4a) /* PCI */
92
93#endif /* m54xxsim_h */ 100#endif /* m54xxsim_h */
diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c
index 2081c6cbb3de..1f7c7fd83e2f 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -30,14 +30,12 @@
30static void __init m54xx_uarts_init(void) 30static void __init m54xx_uarts_init(void)
31{ 31{
32 /* enable io pins */ 32 /* enable io pins */
33 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, 33 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
34 MCF_MBAR + MCF_PAR_PSC(0));
35 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS, 34 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
36 MCF_MBAR + MCF_PAR_PSC(1)); 35 MCFGPIO_PAR_PSC1);
37 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS | 36 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
38 MCF_PAR_PSC_CTS_CTS, MCF_MBAR + MCF_PAR_PSC(2)); 37 MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
39 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, 38 __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
40 MCF_MBAR + MCF_PAR_PSC(3));
41} 39}
42 40
43/***************************************************************************/ 41/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c
index 553210d3d4c1..8572246db84d 100644
--- a/arch/m68k/platform/coldfire/pci.c
+++ b/arch/m68k/platform/coldfire/pci.c
@@ -272,8 +272,8 @@ static int __init mcf_pci_init(void)
272 PACR_EXTMINTE(0x1f), PACR); 272 PACR_EXTMINTE(0x1f), PACR);
273 273
274 /* Set required multi-function pins for PCI bus use */ 274 /* Set required multi-function pins for PCI bus use */
275 __raw_writew(0x3ff, MCF_PAR_PCIBG); 275 __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
276 __raw_writew(0x3ff, MCF_PAR_PCIBR); 276 __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
277 277
278 /* Set up config space for local host bus controller */ 278 /* Set up config space for local host bus controller */
279 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 279 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |