aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--drivers/acpi/processor_idle.c47
-rw-r--r--drivers/idle/intel_idle.c75
2 files changed, 40 insertions, 82 deletions
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index ed9a1cc690be..8b433cb08a33 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -28,19 +28,12 @@
28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 28 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
29 */ 29 */
30 30
31#include <linux/kernel.h>
32#include <linux/module.h> 31#include <linux/module.h>
33#include <linux/init.h>
34#include <linux/cpufreq.h>
35#include <linux/slab.h>
36#include <linux/acpi.h> 32#include <linux/acpi.h>
37#include <linux/dmi.h> 33#include <linux/dmi.h>
38#include <linux/moduleparam.h> 34#include <linux/sched.h> /* need_resched() */
39#include <linux/sched.h> /* need_resched() */
40#include <linux/pm_qos.h>
41#include <linux/clockchips.h> 35#include <linux/clockchips.h>
42#include <linux/cpuidle.h> 36#include <linux/cpuidle.h>
43#include <linux/irqflags.h>
44 37
45/* 38/*
46 * Include the apic definitions for x86 to have the APIC timer related defines 39 * Include the apic definitions for x86 to have the APIC timer related defines
@@ -52,22 +45,14 @@
52#include <asm/apic.h> 45#include <asm/apic.h>
53#endif 46#endif
54 47
55#include <asm/io.h>
56#include <asm/uaccess.h>
57
58#include <acpi/acpi_bus.h> 48#include <acpi/acpi_bus.h>
59#include <acpi/processor.h> 49#include <acpi/processor.h>
60#include <asm/processor.h>
61 50
62#define PREFIX "ACPI: " 51#define PREFIX "ACPI: "
63 52
64#define ACPI_PROCESSOR_CLASS "processor" 53#define ACPI_PROCESSOR_CLASS "processor"
65#define _COMPONENT ACPI_PROCESSOR_COMPONENT 54#define _COMPONENT ACPI_PROCESSOR_COMPONENT
66ACPI_MODULE_NAME("processor_idle"); 55ACPI_MODULE_NAME("processor_idle");
67#define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY)
68#define C2_OVERHEAD 1 /* 1us */
69#define C3_OVERHEAD 1 /* 1us */
70#define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000))
71 56
72static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; 57static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
73module_param(max_cstate, uint, 0000); 58module_param(max_cstate, uint, 0000);
@@ -81,6 +66,8 @@ module_param(latency_factor, uint, 0644);
81 66
82static DEFINE_PER_CPU(struct cpuidle_device *, acpi_cpuidle_device); 67static DEFINE_PER_CPU(struct cpuidle_device *, acpi_cpuidle_device);
83 68
69static struct acpi_processor_cx *acpi_cstate[CPUIDLE_STATE_MAX];
70
84static int disabled_by_idle_boot_param(void) 71static int disabled_by_idle_boot_param(void)
85{ 72{
86 return boot_option_idle_override == IDLE_POLL || 73 return boot_option_idle_override == IDLE_POLL ||
@@ -736,8 +723,7 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
736 struct cpuidle_driver *drv, int index) 723 struct cpuidle_driver *drv, int index)
737{ 724{
738 struct acpi_processor *pr; 725 struct acpi_processor *pr;
739 struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; 726 struct acpi_processor_cx *cx = acpi_cstate[index];
740 struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage);
741 727
742 pr = __this_cpu_read(processors); 728 pr = __this_cpu_read(processors);
743 729
@@ -760,8 +746,7 @@ static int acpi_idle_enter_c1(struct cpuidle_device *dev,
760 */ 746 */
761static int acpi_idle_play_dead(struct cpuidle_device *dev, int index) 747static int acpi_idle_play_dead(struct cpuidle_device *dev, int index)
762{ 748{
763 struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; 749 struct acpi_processor_cx *cx = acpi_cstate[index];
764 struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage);
765 750
766 ACPI_FLUSH_CPU_CACHE(); 751 ACPI_FLUSH_CPU_CACHE();
767 752
@@ -791,8 +776,7 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
791 struct cpuidle_driver *drv, int index) 776 struct cpuidle_driver *drv, int index)
792{ 777{
793 struct acpi_processor *pr; 778 struct acpi_processor *pr;
794 struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; 779 struct acpi_processor_cx *cx = acpi_cstate[index];
795 struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage);
796 780
797 pr = __this_cpu_read(processors); 781 pr = __this_cpu_read(processors);
798 782
@@ -850,8 +834,7 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
850 struct cpuidle_driver *drv, int index) 834 struct cpuidle_driver *drv, int index)
851{ 835{
852 struct acpi_processor *pr; 836 struct acpi_processor *pr;
853 struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; 837 struct acpi_processor_cx *cx = acpi_cstate[index];
854 struct acpi_processor_cx *cx = cpuidle_get_statedata(state_usage);
855 838
856 pr = __this_cpu_read(processors); 839 pr = __this_cpu_read(processors);
857 840
@@ -943,13 +926,13 @@ struct cpuidle_driver acpi_idle_driver = {
943 * device i.e. per-cpu data 926 * device i.e. per-cpu data
944 * 927 *
945 * @pr: the ACPI processor 928 * @pr: the ACPI processor
929 * @dev : the cpuidle device
946 */ 930 */
947static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr) 931static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr,
932 struct cpuidle_device *dev)
948{ 933{
949 int i, count = CPUIDLE_DRIVER_STATE_START; 934 int i, count = CPUIDLE_DRIVER_STATE_START;
950 struct acpi_processor_cx *cx; 935 struct acpi_processor_cx *cx;
951 struct cpuidle_state_usage *state_usage;
952 struct cpuidle_device *dev = per_cpu(acpi_cpuidle_device, pr->id);
953 936
954 if (!pr->flags.power_setup_done) 937 if (!pr->flags.power_setup_done)
955 return -EINVAL; 938 return -EINVAL;
@@ -968,7 +951,6 @@ static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr)
968 951
969 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { 952 for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
970 cx = &pr->power.states[i]; 953 cx = &pr->power.states[i];
971 state_usage = &dev->states_usage[count];
972 954
973 if (!cx->valid) 955 if (!cx->valid)
974 continue; 956 continue;
@@ -979,8 +961,7 @@ static int acpi_processor_setup_cpuidle_cx(struct acpi_processor *pr)
979 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) 961 !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
980 continue; 962 continue;
981#endif 963#endif
982 964 acpi_cstate[count] = cx;
983 cpuidle_set_statedata(state_usage, cx);
984 965
985 count++; 966 count++;
986 if (count == CPUIDLE_STATE_MAX) 967 if (count == CPUIDLE_STATE_MAX)
@@ -1104,7 +1085,7 @@ int acpi_processor_hotplug(struct acpi_processor *pr)
1104 cpuidle_disable_device(dev); 1085 cpuidle_disable_device(dev);
1105 acpi_processor_get_power_info(pr); 1086 acpi_processor_get_power_info(pr);
1106 if (pr->flags.power) { 1087 if (pr->flags.power) {
1107 acpi_processor_setup_cpuidle_cx(pr); 1088 acpi_processor_setup_cpuidle_cx(pr, dev);
1108 ret = cpuidle_enable_device(dev); 1089 ret = cpuidle_enable_device(dev);
1109 } 1090 }
1110 cpuidle_resume_and_unlock(); 1091 cpuidle_resume_and_unlock();
@@ -1162,8 +1143,8 @@ int acpi_processor_cst_has_changed(struct acpi_processor *pr)
1162 continue; 1143 continue;
1163 acpi_processor_get_power_info(_pr); 1144 acpi_processor_get_power_info(_pr);
1164 if (_pr->flags.power) { 1145 if (_pr->flags.power) {
1165 acpi_processor_setup_cpuidle_cx(_pr);
1166 dev = per_cpu(acpi_cpuidle_device, cpu); 1146 dev = per_cpu(acpi_cpuidle_device, cpu);
1147 acpi_processor_setup_cpuidle_cx(_pr, dev);
1167 cpuidle_enable_device(dev); 1148 cpuidle_enable_device(dev);
1168 } 1149 }
1169 } 1150 }
@@ -1232,7 +1213,7 @@ int __cpuinit acpi_processor_power_init(struct acpi_processor *pr)
1232 return -ENOMEM; 1213 return -ENOMEM;
1233 per_cpu(acpi_cpuidle_device, pr->id) = dev; 1214 per_cpu(acpi_cpuidle_device, pr->id) = dev;
1234 1215
1235 acpi_processor_setup_cpuidle_cx(pr); 1216 acpi_processor_setup_cpuidle_cx(pr, dev);
1236 1217
1237 /* Register per-cpu cpuidle_device. Cpuidle driver 1218 /* Register per-cpu cpuidle_device. Cpuidle driver
1238 * must already be registered before registering device 1219 * must already be registered before registering device
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 2df9414a72f7..b2cf489ba3e1 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -109,6 +109,16 @@ static struct cpuidle_state *cpuidle_state_table;
109#define CPUIDLE_FLAG_TLB_FLUSHED 0x10000 109#define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
110 110
111/* 111/*
112 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
113 * the C-state (top nibble) and sub-state (bottom nibble)
114 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
115 *
116 * We store the hint at the top of our "flags" for each state.
117 */
118#define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
119#define MWAIT2flg(eax) ((eax & 0xFF) << 24)
120
121/*
112 * States are indexed by the cstate number, 122 * States are indexed by the cstate number,
113 * which is also the index into the MWAIT hint array. 123 * which is also the index into the MWAIT hint array.
114 * Thus C0 is a dummy. 124 * Thus C0 is a dummy.
@@ -118,21 +128,21 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
118 { /* MWAIT C1 */ 128 { /* MWAIT C1 */
119 .name = "C1-NHM", 129 .name = "C1-NHM",
120 .desc = "MWAIT 0x00", 130 .desc = "MWAIT 0x00",
121 .flags = CPUIDLE_FLAG_TIME_VALID, 131 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
122 .exit_latency = 3, 132 .exit_latency = 3,
123 .target_residency = 6, 133 .target_residency = 6,
124 .enter = &intel_idle }, 134 .enter = &intel_idle },
125 { /* MWAIT C2 */ 135 { /* MWAIT C2 */
126 .name = "C3-NHM", 136 .name = "C3-NHM",
127 .desc = "MWAIT 0x10", 137 .desc = "MWAIT 0x10",
128 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 138 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
129 .exit_latency = 20, 139 .exit_latency = 20,
130 .target_residency = 80, 140 .target_residency = 80,
131 .enter = &intel_idle }, 141 .enter = &intel_idle },
132 { /* MWAIT C3 */ 142 { /* MWAIT C3 */
133 .name = "C6-NHM", 143 .name = "C6-NHM",
134 .desc = "MWAIT 0x20", 144 .desc = "MWAIT 0x20",
135 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 145 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
136 .exit_latency = 200, 146 .exit_latency = 200,
137 .target_residency = 800, 147 .target_residency = 800,
138 .enter = &intel_idle }, 148 .enter = &intel_idle },
@@ -143,28 +153,28 @@ static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
143 { /* MWAIT C1 */ 153 { /* MWAIT C1 */
144 .name = "C1-SNB", 154 .name = "C1-SNB",
145 .desc = "MWAIT 0x00", 155 .desc = "MWAIT 0x00",
146 .flags = CPUIDLE_FLAG_TIME_VALID, 156 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
147 .exit_latency = 1, 157 .exit_latency = 1,
148 .target_residency = 1, 158 .target_residency = 1,
149 .enter = &intel_idle }, 159 .enter = &intel_idle },
150 { /* MWAIT C2 */ 160 { /* MWAIT C2 */
151 .name = "C3-SNB", 161 .name = "C3-SNB",
152 .desc = "MWAIT 0x10", 162 .desc = "MWAIT 0x10",
153 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 163 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
154 .exit_latency = 80, 164 .exit_latency = 80,
155 .target_residency = 211, 165 .target_residency = 211,
156 .enter = &intel_idle }, 166 .enter = &intel_idle },
157 { /* MWAIT C3 */ 167 { /* MWAIT C3 */
158 .name = "C6-SNB", 168 .name = "C6-SNB",
159 .desc = "MWAIT 0x20", 169 .desc = "MWAIT 0x20",
160 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 170 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
161 .exit_latency = 104, 171 .exit_latency = 104,
162 .target_residency = 345, 172 .target_residency = 345,
163 .enter = &intel_idle }, 173 .enter = &intel_idle },
164 { /* MWAIT C4 */ 174 { /* MWAIT C4 */
165 .name = "C7-SNB", 175 .name = "C7-SNB",
166 .desc = "MWAIT 0x30", 176 .desc = "MWAIT 0x30",
167 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 177 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
168 .exit_latency = 109, 178 .exit_latency = 109,
169 .target_residency = 345, 179 .target_residency = 345,
170 .enter = &intel_idle }, 180 .enter = &intel_idle },
@@ -175,28 +185,28 @@ static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = {
175 { /* MWAIT C1 */ 185 { /* MWAIT C1 */
176 .name = "C1-IVB", 186 .name = "C1-IVB",
177 .desc = "MWAIT 0x00", 187 .desc = "MWAIT 0x00",
178 .flags = CPUIDLE_FLAG_TIME_VALID, 188 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
179 .exit_latency = 1, 189 .exit_latency = 1,
180 .target_residency = 1, 190 .target_residency = 1,
181 .enter = &intel_idle }, 191 .enter = &intel_idle },
182 { /* MWAIT C2 */ 192 { /* MWAIT C2 */
183 .name = "C3-IVB", 193 .name = "C3-IVB",
184 .desc = "MWAIT 0x10", 194 .desc = "MWAIT 0x10",
185 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 195 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
186 .exit_latency = 59, 196 .exit_latency = 59,
187 .target_residency = 156, 197 .target_residency = 156,
188 .enter = &intel_idle }, 198 .enter = &intel_idle },
189 { /* MWAIT C3 */ 199 { /* MWAIT C3 */
190 .name = "C6-IVB", 200 .name = "C6-IVB",
191 .desc = "MWAIT 0x20", 201 .desc = "MWAIT 0x20",
192 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 202 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
193 .exit_latency = 80, 203 .exit_latency = 80,
194 .target_residency = 300, 204 .target_residency = 300,
195 .enter = &intel_idle }, 205 .enter = &intel_idle },
196 { /* MWAIT C4 */ 206 { /* MWAIT C4 */
197 .name = "C7-IVB", 207 .name = "C7-IVB",
198 .desc = "MWAIT 0x30", 208 .desc = "MWAIT 0x30",
199 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 209 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
200 .exit_latency = 87, 210 .exit_latency = 87,
201 .target_residency = 300, 211 .target_residency = 300,
202 .enter = &intel_idle }, 212 .enter = &intel_idle },
@@ -207,14 +217,14 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
207 { /* MWAIT C1 */ 217 { /* MWAIT C1 */
208 .name = "C1-ATM", 218 .name = "C1-ATM",
209 .desc = "MWAIT 0x00", 219 .desc = "MWAIT 0x00",
210 .flags = CPUIDLE_FLAG_TIME_VALID, 220 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
211 .exit_latency = 1, 221 .exit_latency = 1,
212 .target_residency = 4, 222 .target_residency = 4,
213 .enter = &intel_idle }, 223 .enter = &intel_idle },
214 { /* MWAIT C2 */ 224 { /* MWAIT C2 */
215 .name = "C2-ATM", 225 .name = "C2-ATM",
216 .desc = "MWAIT 0x10", 226 .desc = "MWAIT 0x10",
217 .flags = CPUIDLE_FLAG_TIME_VALID, 227 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
218 .exit_latency = 20, 228 .exit_latency = 20,
219 .target_residency = 80, 229 .target_residency = 80,
220 .enter = &intel_idle }, 230 .enter = &intel_idle },
@@ -222,7 +232,7 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
222 { /* MWAIT C4 */ 232 { /* MWAIT C4 */
223 .name = "C4-ATM", 233 .name = "C4-ATM",
224 .desc = "MWAIT 0x30", 234 .desc = "MWAIT 0x30",
225 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 235 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
226 .exit_latency = 100, 236 .exit_latency = 100,
227 .target_residency = 400, 237 .target_residency = 400,
228 .enter = &intel_idle }, 238 .enter = &intel_idle },
@@ -230,41 +240,12 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
230 { /* MWAIT C6 */ 240 { /* MWAIT C6 */
231 .name = "C6-ATM", 241 .name = "C6-ATM",
232 .desc = "MWAIT 0x52", 242 .desc = "MWAIT 0x52",
233 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 243 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
234 .exit_latency = 140, 244 .exit_latency = 140,
235 .target_residency = 560, 245 .target_residency = 560,
236 .enter = &intel_idle }, 246 .enter = &intel_idle },
237}; 247};
238 248
239static long get_driver_data(int cstate)
240{
241 int driver_data;
242 switch (cstate) {
243
244 case 1: /* MWAIT C1 */
245 driver_data = 0x00;
246 break;
247 case 2: /* MWAIT C2 */
248 driver_data = 0x10;
249 break;
250 case 3: /* MWAIT C3 */
251 driver_data = 0x20;
252 break;
253 case 4: /* MWAIT C4 */
254 driver_data = 0x30;
255 break;
256 case 5: /* MWAIT C5 */
257 driver_data = 0x40;
258 break;
259 case 6: /* MWAIT C6 */
260 driver_data = 0x52;
261 break;
262 default:
263 driver_data = 0x00;
264 }
265 return driver_data;
266}
267
268/** 249/**
269 * intel_idle 250 * intel_idle
270 * @dev: cpuidle_device 251 * @dev: cpuidle_device
@@ -278,8 +259,7 @@ static int intel_idle(struct cpuidle_device *dev,
278{ 259{
279 unsigned long ecx = 1; /* break on interrupt flag */ 260 unsigned long ecx = 1; /* break on interrupt flag */
280 struct cpuidle_state *state = &drv->states[index]; 261 struct cpuidle_state *state = &drv->states[index];
281 struct cpuidle_state_usage *state_usage = &dev->states_usage[index]; 262 unsigned long eax = flg2MWAIT(state->flags);
282 unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);
283 unsigned int cstate; 263 unsigned int cstate;
284 int cpu = smp_processor_id(); 264 int cpu = smp_processor_id();
285 265
@@ -558,9 +538,6 @@ static int intel_idle_cpu_init(int cpu)
558 if (cpuidle_state_table[cstate].enter == NULL) 538 if (cpuidle_state_table[cstate].enter == NULL)
559 continue; 539 continue;
560 540
561 dev->states_usage[dev->state_count].driver_data =
562 (void *)get_driver_data(cstate);
563
564 dev->state_count += 1; 541 dev->state_count += 1;
565 } 542 }
566 543