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-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h74
-rw-r--r--drivers/usb/host/ohci-pxa27x.c73
2 files changed, 72 insertions, 75 deletions
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
index b34e8a735391..15295d960000 100644
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h
@@ -758,80 +758,6 @@
758 758
759#endif 759#endif
760 760
761#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
762/*
763 * UHC: USB Host Controller (OHCI-like) register definitions
764 */
765#define UHC_BASE_PHYS (0x4C000000)
766#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
767#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
768#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
769#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
770#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
771#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
772#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
773#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
774#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
775#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
776#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
777#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
778#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
779#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
780#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
781#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
782#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
783#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
784
785#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
786#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
787#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
788#define UHCRHDA_POTPGT(x) \
789 (((x) & 0xff) << 24) /* Power On To Power Good Time */
790
791#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
792#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
793#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
794#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
795#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
796
797#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
798#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
799#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
800#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
801#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
802#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
803#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
804#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
805#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
806#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
807
808#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
809#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
810#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
811#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
812#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
813#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
814#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
815#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
816#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
817#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
818#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
819#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
820
821#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
822#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
823#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
824#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
825#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
826#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
827 Interrupt Enable*/
828#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
829#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
830
831#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
832
833#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
834
835/* PWRMODE register M field values */ 761/* PWRMODE register M field values */
836 762
837#define PWRMODE_IDLE 0x1 763#define PWRMODE_IDLE 0x1
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index 2a7d5e0965d7..551581734c21 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -25,10 +25,81 @@
25#include <linux/clk.h> 25#include <linux/clk.h>
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/pxa-regs.h>
29#include <mach/pxa2xx-regs.h> /* FIXME: for PSSR */ 28#include <mach/pxa2xx-regs.h> /* FIXME: for PSSR */
30#include <mach/ohci.h> 29#include <mach/ohci.h>
31 30
31/*
32 * UHC: USB Host Controller (OHCI-like) register definitions
33 */
34#define UHC_BASE_PHYS (0x4C000000)
35#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
36#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
37#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
38#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
39#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
40#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
41#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
42#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
43#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
44#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
45#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
46#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
47#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
48#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
49#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
50#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
51#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
52#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
53
54#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
55#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
56#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
57#define UHCRHDA_POTPGT(x) \
58 (((x) & 0xff) << 24) /* Power On To Power Good Time */
59
60#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
61#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
62#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
63#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
64#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
65
66#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
67#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
68#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
69#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
70#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
71#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
72#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
73#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
74#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
75#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
76
77#define UHCHR __REG(0x4C000064) /* UHC Reset Register */
78#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
79#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
80#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
81#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
82#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
83#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
84#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
85#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
86#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
87#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
88#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
89
90#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
91#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
92#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
93#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
94#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
95#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
96 Interrupt Enable*/
97#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
98#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
99
100#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
101
102
32#define PXA_UHC_MAX_PORTNUM 3 103#define PXA_UHC_MAX_PORTNUM 3
33 104
34#define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 ) 105#define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 )
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 12:45:35 -0500