diff options
45 files changed, 757 insertions, 562 deletions
diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt index c4728839d0c1..6edc3b616e98 100644 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt | |||
@@ -36,6 +36,7 @@ Optional properties: | |||
36 | - reg : should specify the address and size used for NFC command registers, | 36 | - reg : should specify the address and size used for NFC command registers, |
37 | NFC registers and NFC Sram. NFC Sram address and size can be absent | 37 | NFC registers and NFC Sram. NFC Sram address and size can be absent |
38 | if don't want to use it. | 38 | if don't want to use it. |
39 | - clocks: phandle to the peripheral clock | ||
39 | - Optional properties: | 40 | - Optional properties: |
40 | - atmel,write-by-sram: boolean to enable NFC write by sram. | 41 | - atmel,write-by-sram: boolean to enable NFC write by sram. |
41 | 42 | ||
@@ -98,6 +99,7 @@ nand0: nand@40000000 { | |||
98 | compatible = "atmel,sama5d3-nfc"; | 99 | compatible = "atmel,sama5d3-nfc"; |
99 | #address-cells = <1>; | 100 | #address-cells = <1>; |
100 | #size-cells = <1>; | 101 | #size-cells = <1>; |
102 | clocks = <&hsmc_clk> | ||
101 | reg = < | 103 | reg = < |
102 | 0x70000000 0x10000000 /* NFC Command Registers */ | 104 | 0x70000000 0x10000000 /* NFC Command Registers */ |
103 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | 105 | 0xffffc000 0x00000070 /* NFC HSMC regs */ |
diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt index 61c5ec850f2f..6b9f680cb579 100644 --- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt +++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt | |||
@@ -4,8 +4,8 @@ Flash chips (Memory Technology Devices) are often used for solid state | |||
4 | file systems on embedded devices. | 4 | file systems on embedded devices. |
5 | 5 | ||
6 | - compatible : should contain the specific model of mtd chip(s) | 6 | - compatible : should contain the specific model of mtd chip(s) |
7 | used, if known, followed by either "cfi-flash", "jedec-flash" | 7 | used, if known, followed by either "cfi-flash", "jedec-flash", |
8 | or "mtd-ram". | 8 | "mtd-ram" or "mtd-rom". |
9 | - reg : Address range(s) of the mtd chip(s) | 9 | - reg : Address range(s) of the mtd chip(s) |
10 | It's possible to (optionally) define multiple "reg" tuples so that | 10 | It's possible to (optionally) define multiple "reg" tuples so that |
11 | non-identical chips can be described in one node. | 11 | non-identical chips can be described in one node. |
diff --git a/MAINTAINERS b/MAINTAINERS index 90baf1bef4ca..6c59c6697a54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
@@ -5992,6 +5992,7 @@ L: linux-mtd@lists.infradead.org | |||
5992 | W: http://www.linux-mtd.infradead.org/ | 5992 | W: http://www.linux-mtd.infradead.org/ |
5993 | Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ | 5993 | Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ |
5994 | T: git git://git.infradead.org/linux-mtd.git | 5994 | T: git git://git.infradead.org/linux-mtd.git |
5995 | T: git git://git.infradead.org/l2-mtd.git | ||
5995 | S: Maintained | 5996 | S: Maintained |
5996 | F: drivers/mtd/ | 5997 | F: drivers/mtd/ |
5997 | F: include/linux/mtd/ | 5998 | F: include/linux/mtd/ |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index a4d52c42a438..5fa3755261ce 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
@@ -1440,6 +1440,8 @@ static int gpmc_probe_nand_child(struct platform_device *pdev, | |||
1440 | break; | 1440 | break; |
1441 | } | 1441 | } |
1442 | 1442 | ||
1443 | gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child); | ||
1444 | |||
1443 | val = of_get_nand_bus_width(child); | 1445 | val = of_get_nand_bus_width(child); |
1444 | if (val == 16) | 1446 | if (val == 16) |
1445 | gpmc_nand_data->devsize = NAND_BUSWIDTH_16; | 1447 | gpmc_nand_data->devsize = NAND_BUSWIDTH_16; |
diff --git a/drivers/mtd/bcm47xxpart.c b/drivers/mtd/bcm47xxpart.c index adfa74c1bc45..8057f52a45b7 100644 --- a/drivers/mtd/bcm47xxpart.c +++ b/drivers/mtd/bcm47xxpart.c | |||
@@ -199,6 +199,17 @@ static int bcm47xxpart_parse(struct mtd_info *master, | |||
199 | continue; | 199 | continue; |
200 | } | 200 | } |
201 | 201 | ||
202 | /* | ||
203 | * New (ARM?) devices may have NVRAM in some middle block. Last | ||
204 | * block will be checked later, so skip it. | ||
205 | */ | ||
206 | if (offset != master->size - blocksize && | ||
207 | buf[0x000 / 4] == NVRAM_HEADER) { | ||
208 | bcm47xxpart_add_part(&parts[curr_part++], "nvram", | ||
209 | offset, 0); | ||
210 | continue; | ||
211 | } | ||
212 | |||
202 | /* Read middle of the block */ | 213 | /* Read middle of the block */ |
203 | if (mtd_read(master, offset + 0x8000, 0x4, | 214 | if (mtd_read(master, offset + 0x8000, 0x4, |
204 | &bytes_read, (uint8_t *)buf) < 0) { | 215 | &bytes_read, (uint8_t *)buf) < 0) { |
diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c index 46c4643b7a07..c50d8cf0f60d 100644 --- a/drivers/mtd/chips/cfi_cmdset_0002.c +++ b/drivers/mtd/chips/cfi_cmdset_0002.c | |||
@@ -2033,6 +2033,8 @@ static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip, | |||
2033 | 2033 | ||
2034 | udelay(1); | 2034 | udelay(1); |
2035 | } | 2035 | } |
2036 | |||
2037 | retries--; | ||
2036 | } | 2038 | } |
2037 | 2039 | ||
2038 | /* the chip never became ready */ | 2040 | /* the chip never became ready */ |
diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile index c68868f60588..f0b0e611d1d6 100644 --- a/drivers/mtd/devices/Makefile +++ b/drivers/mtd/devices/Makefile | |||
@@ -12,7 +12,6 @@ obj-$(CONFIG_MTD_LART) += lart.o | |||
12 | obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o | 12 | obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o |
13 | obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o | 13 | obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o |
14 | obj-$(CONFIG_MTD_M25P80) += m25p80.o | 14 | obj-$(CONFIG_MTD_M25P80) += m25p80.o |
15 | obj-$(CONFIG_MTD_NAND_OMAP_BCH) += elm.o | ||
16 | obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o | 15 | obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o |
17 | obj-$(CONFIG_MTD_SST25L) += sst25l.o | 16 | obj-$(CONFIG_MTD_SST25L) += sst25l.o |
18 | obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o | 17 | obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o |
diff --git a/drivers/mtd/devices/docg3.c b/drivers/mtd/devices/docg3.c index 91a169c44b39..21cc4b66feaa 100644 --- a/drivers/mtd/devices/docg3.c +++ b/drivers/mtd/devices/docg3.c | |||
@@ -1697,16 +1697,16 @@ static int dbg_asicmode_show(struct seq_file *s, void *p) | |||
1697 | 1697 | ||
1698 | switch (mode) { | 1698 | switch (mode) { |
1699 | case DOC_ASICMODE_RESET: | 1699 | case DOC_ASICMODE_RESET: |
1700 | pos += seq_printf(s, "reset"); | 1700 | pos += seq_puts(s, "reset"); |
1701 | break; | 1701 | break; |
1702 | case DOC_ASICMODE_NORMAL: | 1702 | case DOC_ASICMODE_NORMAL: |
1703 | pos += seq_printf(s, "normal"); | 1703 | pos += seq_puts(s, "normal"); |
1704 | break; | 1704 | break; |
1705 | case DOC_ASICMODE_POWERDOWN: | 1705 | case DOC_ASICMODE_POWERDOWN: |
1706 | pos += seq_printf(s, "powerdown"); | 1706 | pos += seq_puts(s, "powerdown"); |
1707 | break; | 1707 | break; |
1708 | } | 1708 | } |
1709 | pos += seq_printf(s, ")\n"); | 1709 | pos += seq_puts(s, ")\n"); |
1710 | return pos; | 1710 | return pos; |
1711 | } | 1711 | } |
1712 | DEBUGFS_RO_ATTR(asic_mode, dbg_asicmode_show); | 1712 | DEBUGFS_RO_ATTR(asic_mode, dbg_asicmode_show); |
@@ -1745,22 +1745,22 @@ static int dbg_protection_show(struct seq_file *s, void *p) | |||
1745 | pos += seq_printf(s, "Protection = 0x%02x (", | 1745 | pos += seq_printf(s, "Protection = 0x%02x (", |
1746 | protect); | 1746 | protect); |
1747 | if (protect & DOC_PROTECT_FOUNDRY_OTP_LOCK) | 1747 | if (protect & DOC_PROTECT_FOUNDRY_OTP_LOCK) |
1748 | pos += seq_printf(s, "FOUNDRY_OTP_LOCK,"); | 1748 | pos += seq_puts(s, "FOUNDRY_OTP_LOCK,"); |
1749 | if (protect & DOC_PROTECT_CUSTOMER_OTP_LOCK) | 1749 | if (protect & DOC_PROTECT_CUSTOMER_OTP_LOCK) |
1750 | pos += seq_printf(s, "CUSTOMER_OTP_LOCK,"); | 1750 | pos += seq_puts(s, "CUSTOMER_OTP_LOCK,"); |
1751 | if (protect & DOC_PROTECT_LOCK_INPUT) | 1751 | if (protect & DOC_PROTECT_LOCK_INPUT) |
1752 | pos += seq_printf(s, "LOCK_INPUT,"); | 1752 | pos += seq_puts(s, "LOCK_INPUT,"); |
1753 | if (protect & DOC_PROTECT_STICKY_LOCK) | 1753 | if (protect & DOC_PROTECT_STICKY_LOCK) |
1754 | pos += seq_printf(s, "STICKY_LOCK,"); | 1754 | pos += seq_puts(s, "STICKY_LOCK,"); |
1755 | if (protect & DOC_PROTECT_PROTECTION_ENABLED) | 1755 | if (protect & DOC_PROTECT_PROTECTION_ENABLED) |
1756 | pos += seq_printf(s, "PROTECTION ON,"); | 1756 | pos += seq_puts(s, "PROTECTION ON,"); |
1757 | if (protect & DOC_PROTECT_IPL_DOWNLOAD_LOCK) | 1757 | if (protect & DOC_PROTECT_IPL_DOWNLOAD_LOCK) |
1758 | pos += seq_printf(s, "IPL_DOWNLOAD_LOCK,"); | 1758 | pos += seq_puts(s, "IPL_DOWNLOAD_LOCK,"); |
1759 | if (protect & DOC_PROTECT_PROTECTION_ERROR) | 1759 | if (protect & DOC_PROTECT_PROTECTION_ERROR) |
1760 | pos += seq_printf(s, "PROTECT_ERR,"); | 1760 | pos += seq_puts(s, "PROTECT_ERR,"); |
1761 | else | 1761 | else |
1762 | pos += seq_printf(s, "NO_PROTECT_ERR"); | 1762 | pos += seq_puts(s, "NO_PROTECT_ERR"); |
1763 | pos += seq_printf(s, ")\n"); | 1763 | pos += seq_puts(s, ")\n"); |
1764 | 1764 | ||
1765 | pos += seq_printf(s, "DPS0 = 0x%02x : " | 1765 | pos += seq_printf(s, "DPS0 = 0x%02x : " |
1766 | "Protected area [0x%x - 0x%x] : OTP=%d, READ=%d, " | 1766 | "Protected area [0x%x - 0x%x] : OTP=%d, READ=%d, " |
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index ed7e0a1bed3c..dcda6287228d 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c | |||
@@ -193,11 +193,14 @@ static int m25p_probe(struct spi_device *spi) | |||
193 | { | 193 | { |
194 | struct mtd_part_parser_data ppdata; | 194 | struct mtd_part_parser_data ppdata; |
195 | struct flash_platform_data *data; | 195 | struct flash_platform_data *data; |
196 | const struct spi_device_id *id = NULL; | ||
196 | struct m25p *flash; | 197 | struct m25p *flash; |
197 | struct spi_nor *nor; | 198 | struct spi_nor *nor; |
198 | enum read_mode mode = SPI_NOR_NORMAL; | 199 | enum read_mode mode = SPI_NOR_NORMAL; |
199 | int ret; | 200 | int ret; |
200 | 201 | ||
202 | data = dev_get_platdata(&spi->dev); | ||
203 | |||
201 | flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL); | 204 | flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL); |
202 | if (!flash) | 205 | if (!flash) |
203 | return -ENOMEM; | 206 | return -ENOMEM; |
@@ -223,11 +226,26 @@ static int m25p_probe(struct spi_device *spi) | |||
223 | mode = SPI_NOR_QUAD; | 226 | mode = SPI_NOR_QUAD; |
224 | else if (spi->mode & SPI_RX_DUAL) | 227 | else if (spi->mode & SPI_RX_DUAL) |
225 | mode = SPI_NOR_DUAL; | 228 | mode = SPI_NOR_DUAL; |
226 | ret = spi_nor_scan(nor, spi_get_device_id(spi), mode); | 229 | |
230 | if (data && data->name) | ||
231 | flash->mtd.name = data->name; | ||
232 | |||
233 | /* For some (historical?) reason many platforms provide two different | ||
234 | * names in flash_platform_data: "name" and "type". Quite often name is | ||
235 | * set to "m25p80" and then "type" provides a real chip name. | ||
236 | * If that's the case, respect "type" and ignore a "name". | ||
237 | */ | ||
238 | if (data && data->type) | ||
239 | id = spi_nor_match_id(data->type); | ||
240 | |||
241 | /* If we didn't get name from platform, simply use "modalias". */ | ||
242 | if (!id) | ||
243 | id = spi_get_device_id(spi); | ||
244 | |||
245 | ret = spi_nor_scan(nor, id, mode); | ||
227 | if (ret) | 246 | if (ret) |
228 | return ret; | 247 | return ret; |
229 | 248 | ||
230 | data = dev_get_platdata(&spi->dev); | ||
231 | ppdata.of_node = spi->dev.of_node; | 249 | ppdata.of_node = spi->dev.of_node; |
232 | 250 | ||
233 | return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, | 251 | return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, |
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 21b2874a303b..ba801d2c6dcc 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig | |||
@@ -249,7 +249,7 @@ config MTD_CFI_FLAGADM | |||
249 | 249 | ||
250 | config MTD_SOLUTIONENGINE | 250 | config MTD_SOLUTIONENGINE |
251 | tristate "CFI Flash device mapped on Hitachi SolutionEngine" | 251 | tristate "CFI Flash device mapped on Hitachi SolutionEngine" |
252 | depends on SUPERH && SOLUTION_ENGINE && MTD_CFI && MTD_REDBOOT_PARTS | 252 | depends on SOLUTION_ENGINE && MTD_CFI && MTD_REDBOOT_PARTS |
253 | help | 253 | help |
254 | This enables access to the flash chips on the Hitachi SolutionEngine and | 254 | This enables access to the flash chips on the Hitachi SolutionEngine and |
255 | similar boards. Say 'Y' if you are building a kernel for such a board. | 255 | similar boards. Say 'Y' if you are building a kernel for such a board. |
diff --git a/drivers/mtd/maps/gpio-addr-flash.c b/drivers/mtd/maps/gpio-addr-flash.c index a4c477b9fdd6..2fb346091af2 100644 --- a/drivers/mtd/maps/gpio-addr-flash.c +++ b/drivers/mtd/maps/gpio-addr-flash.c | |||
@@ -99,22 +99,28 @@ static map_word gf_read(struct map_info *map, unsigned long ofs) | |||
99 | * @from: flash offset to copy from | 99 | * @from: flash offset to copy from |
100 | * @len: how much to copy | 100 | * @len: how much to copy |
101 | * | 101 | * |
102 | * We rely on the MTD layer to chunk up copies such that a single request here | 102 | * The "from" region may straddle more than one window, so toggle the GPIOs for |
103 | * will not cross a window size. This allows us to only wiggle the GPIOs once | 103 | * each window region before reading its data. |
104 | * before falling back to a normal memcpy. Reading the higher layer code shows | ||
105 | * that this is indeed the case, but add a BUG_ON() to future proof. | ||
106 | */ | 104 | */ |
107 | static void gf_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) | 105 | static void gf_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) |
108 | { | 106 | { |
109 | struct async_state *state = gf_map_info_to_state(map); | 107 | struct async_state *state = gf_map_info_to_state(map); |
110 | 108 | ||
111 | gf_set_gpios(state, from); | 109 | int this_len; |
112 | 110 | ||
113 | /* BUG if operation crosses the win_size */ | 111 | while (len) { |
114 | BUG_ON(!((from + len) % state->win_size <= (from + len))); | 112 | if ((from % state->win_size) + len > state->win_size) |
113 | this_len = state->win_size - (from % state->win_size); | ||
114 | else | ||
115 | this_len = len; | ||
115 | 116 | ||
116 | /* operation does not cross the win_size, so one shot it */ | 117 | gf_set_gpios(state, from); |
117 | memcpy_fromio(to, map->virt + (from % state->win_size), len); | 118 | memcpy_fromio(to, map->virt + (from % state->win_size), |
119 | this_len); | ||
120 | len -= this_len; | ||
121 | from += this_len; | ||
122 | to += this_len; | ||
123 | } | ||
118 | } | 124 | } |
119 | 125 | ||
120 | /** | 126 | /** |
@@ -147,13 +153,21 @@ static void gf_copy_to(struct map_info *map, unsigned long to, | |||
147 | { | 153 | { |
148 | struct async_state *state = gf_map_info_to_state(map); | 154 | struct async_state *state = gf_map_info_to_state(map); |
149 | 155 | ||
150 | gf_set_gpios(state, to); | 156 | int this_len; |
157 | |||
158 | while (len) { | ||
159 | if ((to % state->win_size) + len > state->win_size) | ||
160 | this_len = state->win_size - (to % state->win_size); | ||
161 | else | ||
162 | this_len = len; | ||
151 | 163 | ||
152 | /* BUG if operation crosses the win_size */ | 164 | gf_set_gpios(state, to); |
153 | BUG_ON(!((to + len) % state->win_size <= (to + len))); | 165 | memcpy_toio(map->virt + (to % state->win_size), from, len); |
154 | 166 | ||
155 | /* operation does not cross the win_size, so one shot it */ | 167 | len -= this_len; |
156 | memcpy_toio(map->virt + (to % state->win_size), from, len); | 168 | to += this_len; |
169 | from += this_len; | ||
170 | } | ||
157 | } | 171 | } |
158 | 172 | ||
159 | static const char * const part_probe_types[] = { | 173 | static const char * const part_probe_types[] = { |
diff --git a/drivers/mtd/maps/pcmciamtd.c b/drivers/mtd/maps/pcmciamtd.c index a3cfad392ed6..af747af5eee9 100644 --- a/drivers/mtd/maps/pcmciamtd.c +++ b/drivers/mtd/maps/pcmciamtd.c | |||
@@ -89,7 +89,7 @@ static caddr_t remap_window(struct map_info *map, unsigned long to) | |||
89 | 89 | ||
90 | if (!pcmcia_dev_present(dev->p_dev)) { | 90 | if (!pcmcia_dev_present(dev->p_dev)) { |
91 | pr_debug("device removed\n"); | 91 | pr_debug("device removed\n"); |
92 | return 0; | 92 | return NULL; |
93 | } | 93 | } |
94 | 94 | ||
95 | offset = to & ~(dev->win_size-1); | 95 | offset = to & ~(dev->win_size-1); |
diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c index 217c25d7381b..c1d21cb501ca 100644 --- a/drivers/mtd/maps/physmap_of.c +++ b/drivers/mtd/maps/physmap_of.c | |||
@@ -103,7 +103,7 @@ static struct mtd_info *obsolete_probe(struct platform_device *dev, | |||
103 | if (strcmp(of_probe, "ROM") != 0) | 103 | if (strcmp(of_probe, "ROM") != 0) |
104 | dev_warn(&dev->dev, "obsolete_probe: don't know probe " | 104 | dev_warn(&dev->dev, "obsolete_probe: don't know probe " |
105 | "type '%s', mapping as rom\n", of_probe); | 105 | "type '%s', mapping as rom\n", of_probe); |
106 | return do_map_probe("mtd_rom", map); | 106 | return do_map_probe("map_rom", map); |
107 | } | 107 | } |
108 | } | 108 | } |
109 | 109 | ||
@@ -340,6 +340,10 @@ static struct of_device_id of_flash_match[] = { | |||
340 | .data = (void *)"map_ram", | 340 | .data = (void *)"map_ram", |
341 | }, | 341 | }, |
342 | { | 342 | { |
343 | .compatible = "mtd-rom", | ||
344 | .data = (void *)"map_rom", | ||
345 | }, | ||
346 | { | ||
343 | .type = "rom", | 347 | .type = "rom", |
344 | .compatible = "direct-mapped" | 348 | .compatible = "direct-mapped" |
345 | }, | 349 | }, |
diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c index a0f54e80670c..53563955931b 100644 --- a/drivers/mtd/mtdchar.c +++ b/drivers/mtd/mtdchar.c | |||
@@ -549,6 +549,9 @@ static int mtdchar_blkpg_ioctl(struct mtd_info *mtd, | |||
549 | if (mtd_is_partition(mtd)) | 549 | if (mtd_is_partition(mtd)) |
550 | return -EINVAL; | 550 | return -EINVAL; |
551 | 551 | ||
552 | /* Sanitize user input */ | ||
553 | p.devname[BLKPG_DEVNAMELTH - 1] = '\0'; | ||
554 | |||
552 | return mtd_add_partition(mtd, p.devname, p.start, p.length); | 555 | return mtd_add_partition(mtd, p.devname, p.start, p.length); |
553 | 556 | ||
554 | case BLKPG_DEL_PARTITION: | 557 | case BLKPG_DEL_PARTITION: |
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index e4831b4159db..4c611871d7e6 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c | |||
@@ -105,12 +105,11 @@ static LIST_HEAD(mtd_notifiers); | |||
105 | */ | 105 | */ |
106 | static void mtd_release(struct device *dev) | 106 | static void mtd_release(struct device *dev) |
107 | { | 107 | { |
108 | struct mtd_info __maybe_unused *mtd = dev_get_drvdata(dev); | 108 | struct mtd_info *mtd = dev_get_drvdata(dev); |
109 | dev_t index = MTD_DEVT(mtd->index); | 109 | dev_t index = MTD_DEVT(mtd->index); |
110 | 110 | ||
111 | /* remove /dev/mtdXro node if needed */ | 111 | /* remove /dev/mtdXro node */ |
112 | if (index) | 112 | device_destroy(&mtd_class, index + 1); |
113 | device_destroy(&mtd_class, index + 1); | ||
114 | } | 113 | } |
115 | 114 | ||
116 | static int mtd_cls_suspend(struct device *dev, pm_message_t state) | 115 | static int mtd_cls_suspend(struct device *dev, pm_message_t state) |
@@ -442,10 +441,8 @@ int add_mtd_device(struct mtd_info *mtd) | |||
442 | if (device_register(&mtd->dev) != 0) | 441 | if (device_register(&mtd->dev) != 0) |
443 | goto fail_added; | 442 | goto fail_added; |
444 | 443 | ||
445 | if (MTD_DEVT(i)) | 444 | device_create(&mtd_class, mtd->dev.parent, MTD_DEVT(i) + 1, NULL, |
446 | device_create(&mtd_class, mtd->dev.parent, | 445 | "mtd%dro", i); |
447 | MTD_DEVT(i) + 1, | ||
448 | NULL, "mtd%dro", i); | ||
449 | 446 | ||
450 | pr_debug("mtd: Giving out device %d to %s\n", i, mtd->name); | 447 | pr_debug("mtd: Giving out device %d to %s\n", i, mtd->name); |
451 | /* No need to get a refcount on the module containing | 448 | /* No need to get a refcount on the module containing |
@@ -778,7 +775,7 @@ EXPORT_SYMBOL_GPL(__put_mtd_device); | |||
778 | */ | 775 | */ |
779 | int mtd_erase(struct mtd_info *mtd, struct erase_info *instr) | 776 | int mtd_erase(struct mtd_info *mtd, struct erase_info *instr) |
780 | { | 777 | { |
781 | if (instr->addr > mtd->size || instr->len > mtd->size - instr->addr) | 778 | if (instr->addr >= mtd->size || instr->len > mtd->size - instr->addr) |
782 | return -EINVAL; | 779 | return -EINVAL; |
783 | if (!(mtd->flags & MTD_WRITEABLE)) | 780 | if (!(mtd->flags & MTD_WRITEABLE)) |
784 | return -EROFS; | 781 | return -EROFS; |
@@ -804,7 +801,7 @@ int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, | |||
804 | *phys = 0; | 801 | *phys = 0; |
805 | if (!mtd->_point) | 802 | if (!mtd->_point) |
806 | return -EOPNOTSUPP; | 803 | return -EOPNOTSUPP; |
807 | if (from < 0 || from > mtd->size || len > mtd->size - from) | 804 | if (from < 0 || from >= mtd->size || len > mtd->size - from) |
808 | return -EINVAL; | 805 | return -EINVAL; |
809 | if (!len) | 806 | if (!len) |
810 | return 0; | 807 | return 0; |
@@ -817,7 +814,7 @@ int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len) | |||
817 | { | 814 | { |
818 | if (!mtd->_point) | 815 | if (!mtd->_point) |
819 | return -EOPNOTSUPP; | 816 | return -EOPNOTSUPP; |
820 | if (from < 0 || from > mtd->size || len > mtd->size - from) | 817 | if (from < 0 || from >= mtd->size || len > mtd->size - from) |
821 | return -EINVAL; | 818 | return -EINVAL; |
822 | if (!len) | 819 | if (!len) |
823 | return 0; | 820 | return 0; |
@@ -835,7 +832,7 @@ unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len, | |||
835 | { | 832 | { |
836 | if (!mtd->_get_unmapped_area) | 833 | if (!mtd->_get_unmapped_area) |
837 | return -EOPNOTSUPP; | 834 | return -EOPNOTSUPP; |
838 | if (offset > mtd->size || len > mtd->size - offset) | 835 | if (offset >= mtd->size || len > mtd->size - offset) |
839 | return -EINVAL; | 836 | return -EINVAL; |
840 | return mtd->_get_unmapped_area(mtd, len, offset, flags); | 837 | return mtd->_get_unmapped_area(mtd, len, offset, flags); |
841 | } | 838 | } |
@@ -846,7 +843,7 @@ int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, | |||
846 | { | 843 | { |
847 | int ret_code; | 844 | int ret_code; |
848 | *retlen = 0; | 845 | *retlen = 0; |
849 | if (from < 0 || from > mtd->size || len > mtd->size - from) | 846 | if (from < 0 || from >= mtd->size || len > mtd->size - from) |
850 | return -EINVAL; | 847 | return -EINVAL; |
851 | if (!len) | 848 | if (!len) |
852 | return 0; | 849 | return 0; |
@@ -869,7 +866,7 @@ int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, | |||
869 | const u_char *buf) | 866 | const u_char *buf) |
870 | { | 867 | { |
871 | *retlen = 0; | 868 | *retlen = 0; |
872 | if (to < 0 || to > mtd->size || len > mtd->size - to) | 869 | if (to < 0 || to >= mtd->size || len > mtd->size - to) |
873 | return -EINVAL; | 870 | return -EINVAL; |
874 | if (!mtd->_write || !(mtd->flags & MTD_WRITEABLE)) | 871 | if (!mtd->_write || !(mtd->flags & MTD_WRITEABLE)) |
875 | return -EROFS; | 872 | return -EROFS; |
@@ -892,7 +889,7 @@ int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, | |||
892 | *retlen = 0; | 889 | *retlen = 0; |
893 | if (!mtd->_panic_write) | 890 | if (!mtd->_panic_write) |
894 | return -EOPNOTSUPP; | 891 | return -EOPNOTSUPP; |
895 | if (to < 0 || to > mtd->size || len > mtd->size - to) | 892 | if (to < 0 || to >= mtd->size || len > mtd->size - to) |
896 | return -EINVAL; | 893 | return -EINVAL; |
897 | if (!(mtd->flags & MTD_WRITEABLE)) | 894 | if (!(mtd->flags & MTD_WRITEABLE)) |
898 | return -EROFS; | 895 | return -EROFS; |
@@ -1011,7 +1008,7 @@ int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |||
1011 | { | 1008 | { |
1012 | if (!mtd->_lock) | 1009 | if (!mtd->_lock) |
1013 | return -EOPNOTSUPP; | 1010 | return -EOPNOTSUPP; |
1014 | if (ofs < 0 || ofs > mtd->size || len > mtd->size - ofs) | 1011 | if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs) |
1015 | return -EINVAL; | 1012 | return -EINVAL; |
1016 | if (!len) | 1013 | if (!len) |
1017 | return 0; | 1014 | return 0; |
@@ -1023,7 +1020,7 @@ int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |||
1023 | { | 1020 | { |
1024 | if (!mtd->_unlock) | 1021 | if (!mtd->_unlock) |
1025 | return -EOPNOTSUPP; | 1022 | return -EOPNOTSUPP; |
1026 | if (ofs < 0 || ofs > mtd->size || len > mtd->size - ofs) | 1023 | if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs) |
1027 | return -EINVAL; | 1024 | return -EINVAL; |
1028 | if (!len) | 1025 | if (!len) |
1029 | return 0; | 1026 | return 0; |
@@ -1035,7 +1032,7 @@ int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |||
1035 | { | 1032 | { |
1036 | if (!mtd->_is_locked) | 1033 | if (!mtd->_is_locked) |
1037 | return -EOPNOTSUPP; | 1034 | return -EOPNOTSUPP; |
1038 | if (ofs < 0 || ofs > mtd->size || len > mtd->size - ofs) | 1035 | if (ofs < 0 || ofs >= mtd->size || len > mtd->size - ofs) |
1039 | return -EINVAL; | 1036 | return -EINVAL; |
1040 | if (!len) | 1037 | if (!len) |
1041 | return 0; | 1038 | return 0; |
@@ -1045,7 +1042,7 @@ EXPORT_SYMBOL_GPL(mtd_is_locked); | |||
1045 | 1042 | ||
1046 | int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs) | 1043 | int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs) |
1047 | { | 1044 | { |
1048 | if (ofs < 0 || ofs > mtd->size) | 1045 | if (ofs < 0 || ofs >= mtd->size) |
1049 | return -EINVAL; | 1046 | return -EINVAL; |
1050 | if (!mtd->_block_isreserved) | 1047 | if (!mtd->_block_isreserved) |
1051 | return 0; | 1048 | return 0; |
@@ -1055,7 +1052,7 @@ EXPORT_SYMBOL_GPL(mtd_block_isreserved); | |||
1055 | 1052 | ||
1056 | int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs) | 1053 | int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs) |
1057 | { | 1054 | { |
1058 | if (ofs < 0 || ofs > mtd->size) | 1055 | if (ofs < 0 || ofs >= mtd->size) |
1059 | return -EINVAL; | 1056 | return -EINVAL; |
1060 | if (!mtd->_block_isbad) | 1057 | if (!mtd->_block_isbad) |
1061 | return 0; | 1058 | return 0; |
@@ -1067,7 +1064,7 @@ int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs) | |||
1067 | { | 1064 | { |
1068 | if (!mtd->_block_markbad) | 1065 | if (!mtd->_block_markbad) |
1069 | return -EOPNOTSUPP; | 1066 | return -EOPNOTSUPP; |
1070 | if (ofs < 0 || ofs > mtd->size) | 1067 | if (ofs < 0 || ofs >= mtd->size) |
1071 | return -EINVAL; | 1068 | return -EINVAL; |
1072 | if (!(mtd->flags & MTD_WRITEABLE)) | 1069 | if (!(mtd->flags & MTD_WRITEABLE)) |
1073 | return -EROFS; | 1070 | return -EROFS; |
diff --git a/drivers/mtd/mtdswap.c b/drivers/mtd/mtdswap.c index 8b33b26eb12b..fc8b3d16cce7 100644 --- a/drivers/mtd/mtdswap.c +++ b/drivers/mtd/mtdswap.c | |||
@@ -145,7 +145,7 @@ struct mtdswap_dev { | |||
145 | struct mtdswap_oobdata { | 145 | struct mtdswap_oobdata { |
146 | __le16 magic; | 146 | __le16 magic; |
147 | __le32 count; | 147 | __le32 count; |
148 | } __attribute__((packed)); | 148 | } __packed; |
149 | 149 | ||
150 | #define MTDSWAP_MAGIC_CLEAN 0x2095 | 150 | #define MTDSWAP_MAGIC_CLEAN 0x2095 |
151 | #define MTDSWAP_MAGIC_DIRTY (MTDSWAP_MAGIC_CLEAN + 1) | 151 | #define MTDSWAP_MAGIC_DIRTY (MTDSWAP_MAGIC_CLEAN + 1) |
@@ -1287,7 +1287,7 @@ static int mtdswap_show(struct seq_file *s, void *data) | |||
1287 | 1287 | ||
1288 | seq_printf(s, "total erasures: %lu\n", sum); | 1288 | seq_printf(s, "total erasures: %lu\n", sum); |
1289 | 1289 | ||
1290 | seq_printf(s, "\n"); | 1290 | seq_puts(s, "\n"); |
1291 | 1291 | ||
1292 | seq_printf(s, "mtdswap_readsect count: %llu\n", d->sect_read_count); | 1292 | seq_printf(s, "mtdswap_readsect count: %llu\n", d->sect_read_count); |
1293 | seq_printf(s, "mtdswap_writesect count: %llu\n", d->sect_write_count); | 1293 | seq_printf(s, "mtdswap_writesect count: %llu\n", d->sect_write_count); |
@@ -1296,7 +1296,7 @@ static int mtdswap_show(struct seq_file *s, void *data) | |||
1296 | seq_printf(s, "mtd write count: %llu\n", d->mtd_write_count); | 1296 | seq_printf(s, "mtd write count: %llu\n", d->mtd_write_count); |
1297 | seq_printf(s, "discarded pages count: %llu\n", d->discard_page_count); | 1297 | seq_printf(s, "discarded pages count: %llu\n", d->discard_page_count); |
1298 | 1298 | ||
1299 | seq_printf(s, "\n"); | 1299 | seq_puts(s, "\n"); |
1300 | seq_printf(s, "total pages: %u\n", pages); | 1300 | seq_printf(s, "total pages: %u\n", pages); |
1301 | seq_printf(s, "pages mapped: %u\n", mapped); | 1301 | seq_printf(s, "pages mapped: %u\n", mapped); |
1302 | 1302 | ||
@@ -1474,7 +1474,7 @@ static void mtdswap_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd) | |||
1474 | } | 1474 | } |
1475 | 1475 | ||
1476 | eblocks = mtd_div_by_eb(use_size, mtd); | 1476 | eblocks = mtd_div_by_eb(use_size, mtd); |
1477 | use_size = eblocks * mtd->erasesize; | 1477 | use_size = (uint64_t)eblocks * mtd->erasesize; |
1478 | bad_blocks = mtdswap_badblocks(mtd, use_size); | 1478 | bad_blocks = mtdswap_badblocks(mtd, use_size); |
1479 | eavailable = eblocks - bad_blocks; | 1479 | eavailable = eblocks - bad_blocks; |
1480 | 1480 | ||
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index f1cf503517fd..dd10646982ae 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig | |||
@@ -96,7 +96,7 @@ config MTD_NAND_OMAP2 | |||
96 | 96 | ||
97 | config MTD_NAND_OMAP_BCH | 97 | config MTD_NAND_OMAP_BCH |
98 | depends on MTD_NAND_OMAP2 | 98 | depends on MTD_NAND_OMAP2 |
99 | tristate "Support hardware based BCH error correction" | 99 | bool "Support hardware based BCH error correction" |
100 | default n | 100 | default n |
101 | select BCH | 101 | select BCH |
102 | help | 102 | help |
@@ -104,7 +104,10 @@ config MTD_NAND_OMAP_BCH | |||
104 | locate and correct errors when using BCH ECC scheme. This offloads | 104 | locate and correct errors when using BCH ECC scheme. This offloads |
105 | the cpu from doing ECC error searching and correction. However some | 105 | the cpu from doing ECC error searching and correction. However some |
106 | legacy OMAP families like OMAP2xxx, OMAP3xxx do not have ELM engine | 106 | legacy OMAP families like OMAP2xxx, OMAP3xxx do not have ELM engine |
107 | so they should not enable this config symbol. | 107 | so this is optional for them. |
108 | |||
109 | config MTD_NAND_OMAP_BCH_BUILD | ||
110 | def_tristate MTD_NAND_OMAP2 && MTD_NAND_OMAP_BCH | ||
108 | 111 | ||
109 | config MTD_NAND_IDS | 112 | config MTD_NAND_IDS |
110 | tristate | 113 | tristate |
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index a035e7cc6d46..9c847e469ca7 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile | |||
@@ -27,6 +27,7 @@ obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o | |||
27 | obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o | 27 | obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o |
28 | obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o | 28 | obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o |
29 | obj-$(CONFIG_MTD_NAND_OMAP2) += omap2.o | 29 | obj-$(CONFIG_MTD_NAND_OMAP2) += omap2.o |
30 | obj-$(CONFIG_MTD_NAND_OMAP_BCH_BUILD) += omap_elm.o | ||
30 | obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o | 31 | obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o |
31 | obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o | 32 | obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o |
32 | obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o | 33 | obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o |
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index e321c564ff05..19d1e9d17bf9 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c | |||
@@ -27,6 +27,7 @@ | |||
27 | * | 27 | * |
28 | */ | 28 | */ |
29 | 29 | ||
30 | #include <linux/clk.h> | ||
30 | #include <linux/dma-mapping.h> | 31 | #include <linux/dma-mapping.h> |
31 | #include <linux/slab.h> | 32 | #include <linux/slab.h> |
32 | #include <linux/module.h> | 33 | #include <linux/module.h> |
@@ -96,6 +97,8 @@ struct atmel_nfc { | |||
96 | bool use_nfc_sram; | 97 | bool use_nfc_sram; |
97 | bool write_by_sram; | 98 | bool write_by_sram; |
98 | 99 | ||
100 | struct clk *clk; | ||
101 | |||
99 | bool is_initialized; | 102 | bool is_initialized; |
100 | struct completion comp_ready; | 103 | struct completion comp_ready; |
101 | struct completion comp_cmd_done; | 104 | struct completion comp_cmd_done; |
@@ -128,8 +131,6 @@ struct atmel_nand_host { | |||
128 | u32 pmecc_lookup_table_offset_512; | 131 | u32 pmecc_lookup_table_offset_512; |
129 | u32 pmecc_lookup_table_offset_1024; | 132 | u32 pmecc_lookup_table_offset_1024; |
130 | 133 | ||
131 | int pmecc_bytes_per_sector; | ||
132 | int pmecc_sector_number; | ||
133 | int pmecc_degree; /* Degree of remainders */ | 134 | int pmecc_degree; /* Degree of remainders */ |
134 | int pmecc_cw_len; /* Length of codeword */ | 135 | int pmecc_cw_len; /* Length of codeword */ |
135 | 136 | ||
@@ -841,7 +842,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, | |||
841 | pos, bit_pos, err_byte, *(buf + byte_pos)); | 842 | pos, bit_pos, err_byte, *(buf + byte_pos)); |
842 | } else { | 843 | } else { |
843 | /* Bit flip in OOB area */ | 844 | /* Bit flip in OOB area */ |
844 | tmp = sector_num * host->pmecc_bytes_per_sector | 845 | tmp = sector_num * nand_chip->ecc.bytes |
845 | + (byte_pos - sector_size); | 846 | + (byte_pos - sector_size); |
846 | err_byte = ecc[tmp]; | 847 | err_byte = ecc[tmp]; |
847 | ecc[tmp] ^= (1 << bit_pos); | 848 | ecc[tmp] ^= (1 << bit_pos); |
@@ -874,7 +875,7 @@ static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf, | |||
874 | return 0; | 875 | return 0; |
875 | 876 | ||
876 | normal_check: | 877 | normal_check: |
877 | for (i = 0; i < host->pmecc_sector_number; i++) { | 878 | for (i = 0; i < nand_chip->ecc.steps; i++) { |
878 | err_nbr = 0; | 879 | err_nbr = 0; |
879 | if (pmecc_stat & 0x1) { | 880 | if (pmecc_stat & 0x1) { |
880 | buf_pos = buf + i * host->pmecc_sector_size; | 881 | buf_pos = buf + i * host->pmecc_sector_size; |
@@ -890,7 +891,7 @@ normal_check: | |||
890 | return -EIO; | 891 | return -EIO; |
891 | } else { | 892 | } else { |
892 | pmecc_correct_data(mtd, buf_pos, ecc, i, | 893 | pmecc_correct_data(mtd, buf_pos, ecc, i, |
893 | host->pmecc_bytes_per_sector, err_nbr); | 894 | nand_chip->ecc.bytes, err_nbr); |
894 | mtd->ecc_stats.corrected += err_nbr; | 895 | mtd->ecc_stats.corrected += err_nbr; |
895 | total_err += err_nbr; | 896 | total_err += err_nbr; |
896 | } | 897 | } |
@@ -984,11 +985,11 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, | |||
984 | cpu_relax(); | 985 | cpu_relax(); |
985 | } | 986 | } |
986 | 987 | ||
987 | for (i = 0; i < host->pmecc_sector_number; i++) { | 988 | for (i = 0; i < chip->ecc.steps; i++) { |
988 | for (j = 0; j < host->pmecc_bytes_per_sector; j++) { | 989 | for (j = 0; j < chip->ecc.bytes; j++) { |
989 | int pos; | 990 | int pos; |
990 | 991 | ||
991 | pos = i * host->pmecc_bytes_per_sector + j; | 992 | pos = i * chip->ecc.bytes + j; |
992 | chip->oob_poi[eccpos[pos]] = | 993 | chip->oob_poi[eccpos[pos]] = |
993 | pmecc_readb_ecc_relaxed(host->ecc, i, j); | 994 | pmecc_readb_ecc_relaxed(host->ecc, i, j); |
994 | } | 995 | } |
@@ -1031,7 +1032,7 @@ static void atmel_pmecc_core_init(struct mtd_info *mtd) | |||
1031 | else if (host->pmecc_sector_size == 1024) | 1032 | else if (host->pmecc_sector_size == 1024) |
1032 | val |= PMECC_CFG_SECTOR1024; | 1033 | val |= PMECC_CFG_SECTOR1024; |
1033 | 1034 | ||
1034 | switch (host->pmecc_sector_number) { | 1035 | switch (nand_chip->ecc.steps) { |
1035 | case 1: | 1036 | case 1: |
1036 | val |= PMECC_CFG_PAGE_1SECTOR; | 1037 | val |= PMECC_CFG_PAGE_1SECTOR; |
1037 | break; | 1038 | break; |
@@ -1148,7 +1149,6 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev, | |||
1148 | 1149 | ||
1149 | host->ecc = devm_ioremap_resource(&pdev->dev, regs); | 1150 | host->ecc = devm_ioremap_resource(&pdev->dev, regs); |
1150 | if (IS_ERR(host->ecc)) { | 1151 | if (IS_ERR(host->ecc)) { |
1151 | dev_err(host->dev, "ioremap failed\n"); | ||
1152 | err_no = PTR_ERR(host->ecc); | 1152 | err_no = PTR_ERR(host->ecc); |
1153 | goto err; | 1153 | goto err; |
1154 | } | 1154 | } |
@@ -1156,8 +1156,6 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev, | |||
1156 | regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2); | 1156 | regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
1157 | host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr); | 1157 | host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr); |
1158 | if (IS_ERR(host->pmerrloc_base)) { | 1158 | if (IS_ERR(host->pmerrloc_base)) { |
1159 | dev_err(host->dev, | ||
1160 | "Can not get I/O resource for PMECC ERRLOC controller!\n"); | ||
1161 | err_no = PTR_ERR(host->pmerrloc_base); | 1159 | err_no = PTR_ERR(host->pmerrloc_base); |
1162 | goto err; | 1160 | goto err; |
1163 | } | 1161 | } |
@@ -1165,7 +1163,6 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev, | |||
1165 | regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3); | 1163 | regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3); |
1166 | host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom); | 1164 | host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom); |
1167 | if (IS_ERR(host->pmecc_rom_base)) { | 1165 | if (IS_ERR(host->pmecc_rom_base)) { |
1168 | dev_err(host->dev, "Can not get I/O resource for ROM!\n"); | ||
1169 | err_no = PTR_ERR(host->pmecc_rom_base); | 1166 | err_no = PTR_ERR(host->pmecc_rom_base); |
1170 | goto err; | 1167 | goto err; |
1171 | } | 1168 | } |
@@ -1174,22 +1171,29 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev, | |||
1174 | 1171 | ||
1175 | /* set ECC page size and oob layout */ | 1172 | /* set ECC page size and oob layout */ |
1176 | switch (mtd->writesize) { | 1173 | switch (mtd->writesize) { |
1174 | case 512: | ||
1175 | case 1024: | ||
1177 | case 2048: | 1176 | case 2048: |
1177 | case 4096: | ||
1178 | case 8192: | ||
1179 | if (sector_size > mtd->writesize) { | ||
1180 | dev_err(host->dev, "pmecc sector size is bigger than the page size!\n"); | ||
1181 | err_no = -EINVAL; | ||
1182 | goto err; | ||
1183 | } | ||
1184 | |||
1178 | host->pmecc_degree = (sector_size == 512) ? | 1185 | host->pmecc_degree = (sector_size == 512) ? |
1179 | PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14; | 1186 | PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14; |
1180 | host->pmecc_cw_len = (1 << host->pmecc_degree) - 1; | 1187 | host->pmecc_cw_len = (1 << host->pmecc_degree) - 1; |
1181 | host->pmecc_sector_number = mtd->writesize / sector_size; | ||
1182 | host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes( | ||
1183 | cap, sector_size); | ||
1184 | host->pmecc_alpha_to = pmecc_get_alpha_to(host); | 1188 | host->pmecc_alpha_to = pmecc_get_alpha_to(host); |
1185 | host->pmecc_index_of = host->pmecc_rom_base + | 1189 | host->pmecc_index_of = host->pmecc_rom_base + |
1186 | host->pmecc_lookup_table_offset; | 1190 | host->pmecc_lookup_table_offset; |
1187 | 1191 | ||
1188 | nand_chip->ecc.steps = host->pmecc_sector_number; | ||
1189 | nand_chip->ecc.strength = cap; | 1192 | nand_chip->ecc.strength = cap; |
1190 | nand_chip->ecc.bytes = host->pmecc_bytes_per_sector; | 1193 | nand_chip->ecc.bytes = pmecc_get_ecc_bytes(cap, sector_size); |
1191 | nand_chip->ecc.total = host->pmecc_bytes_per_sector * | 1194 | nand_chip->ecc.steps = mtd->writesize / sector_size; |
1192 | host->pmecc_sector_number; | 1195 | nand_chip->ecc.total = nand_chip->ecc.bytes * |
1196 | nand_chip->ecc.steps; | ||
1193 | if (nand_chip->ecc.total > mtd->oobsize - 2) { | 1197 | if (nand_chip->ecc.total > mtd->oobsize - 2) { |
1194 | dev_err(host->dev, "No room for ECC bytes\n"); | 1198 | dev_err(host->dev, "No room for ECC bytes\n"); |
1195 | err_no = -EINVAL; | 1199 | err_no = -EINVAL; |
@@ -1201,13 +1205,9 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev, | |||
1201 | 1205 | ||
1202 | nand_chip->ecc.layout = &atmel_pmecc_oobinfo; | 1206 | nand_chip->ecc.layout = &atmel_pmecc_oobinfo; |
1203 | break; | 1207 | break; |
1204 | case 512: | 1208 | default: |
1205 | case 1024: | ||
1206 | case 4096: | ||
1207 | /* TODO */ | ||
1208 | dev_warn(host->dev, | 1209 | dev_warn(host->dev, |
1209 | "Unsupported page size for PMECC, use Software ECC\n"); | 1210 | "Unsupported page size for PMECC, use Software ECC\n"); |
1210 | default: | ||
1211 | /* page size not handled by HW ECC */ | 1211 | /* page size not handled by HW ECC */ |
1212 | /* switching back to soft ECC */ | 1212 | /* switching back to soft ECC */ |
1213 | nand_chip->ecc.mode = NAND_ECC_SOFT; | 1213 | nand_chip->ecc.mode = NAND_ECC_SOFT; |
@@ -1530,10 +1530,8 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev, | |||
1530 | } | 1530 | } |
1531 | 1531 | ||
1532 | host->ecc = devm_ioremap_resource(&pdev->dev, regs); | 1532 | host->ecc = devm_ioremap_resource(&pdev->dev, regs); |
1533 | if (IS_ERR(host->ecc)) { | 1533 | if (IS_ERR(host->ecc)) |
1534 | dev_err(host->dev, "ioremap failed\n"); | ||
1535 | return PTR_ERR(host->ecc); | 1534 | return PTR_ERR(host->ecc); |
1536 | } | ||
1537 | 1535 | ||
1538 | /* ECC is calculated for the whole page (1 step) */ | 1536 | /* ECC is calculated for the whole page (1 step) */ |
1539 | nand_chip->ecc.size = mtd->writesize; | 1537 | nand_chip->ecc.size = mtd->writesize; |
@@ -1907,15 +1905,7 @@ static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1907 | if (offset || (data_len < mtd->writesize)) | 1905 | if (offset || (data_len < mtd->writesize)) |
1908 | return -EINVAL; | 1906 | return -EINVAL; |
1909 | 1907 | ||
1910 | cfg = nfc_readl(host->nfc->hsmc_regs, CFG); | ||
1911 | len = mtd->writesize; | 1908 | len = mtd->writesize; |
1912 | |||
1913 | if (unlikely(raw)) { | ||
1914 | len += mtd->oobsize; | ||
1915 | nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE); | ||
1916 | } else | ||
1917 | nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE); | ||
1918 | |||
1919 | /* Copy page data to sram that will write to nand via NFC */ | 1909 | /* Copy page data to sram that will write to nand via NFC */ |
1920 | if (use_dma) { | 1910 | if (use_dma) { |
1921 | if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0) | 1911 | if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0) |
@@ -1925,6 +1915,15 @@ static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1925 | memcpy32_toio(sram, buf, len); | 1915 | memcpy32_toio(sram, buf, len); |
1926 | } | 1916 | } |
1927 | 1917 | ||
1918 | cfg = nfc_readl(host->nfc->hsmc_regs, CFG); | ||
1919 | if (unlikely(raw) && oob_required) { | ||
1920 | memcpy32_toio(sram + len, chip->oob_poi, mtd->oobsize); | ||
1921 | len += mtd->oobsize; | ||
1922 | nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE); | ||
1923 | } else { | ||
1924 | nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE); | ||
1925 | } | ||
1926 | |||
1928 | if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) | 1927 | if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) |
1929 | /* | 1928 | /* |
1930 | * When use NFC sram, need set up PMECC before send | 1929 | * When use NFC sram, need set up PMECC before send |
@@ -2040,7 +2039,6 @@ static int atmel_nand_probe(struct platform_device *pdev) | |||
2040 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 2039 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2041 | host->io_base = devm_ioremap_resource(&pdev->dev, mem); | 2040 | host->io_base = devm_ioremap_resource(&pdev->dev, mem); |
2042 | if (IS_ERR(host->io_base)) { | 2041 | if (IS_ERR(host->io_base)) { |
2043 | dev_err(&pdev->dev, "atmel_nand: ioremap resource failed\n"); | ||
2044 | res = PTR_ERR(host->io_base); | 2042 | res = PTR_ERR(host->io_base); |
2045 | goto err_nand_ioremap; | 2043 | goto err_nand_ioremap; |
2046 | } | 2044 | } |
@@ -2099,7 +2097,7 @@ static int atmel_nand_probe(struct platform_device *pdev) | |||
2099 | } | 2097 | } |
2100 | 2098 | ||
2101 | nand_chip->ecc.mode = host->board.ecc_mode; | 2099 | nand_chip->ecc.mode = host->board.ecc_mode; |
2102 | nand_chip->chip_delay = 20; /* 20us command delay time */ | 2100 | nand_chip->chip_delay = 40; /* 40us command delay time */ |
2103 | 2101 | ||
2104 | if (host->board.bus_width_16) /* 16-bit bus width */ | 2102 | if (host->board.bus_width_16) /* 16-bit bus width */ |
2105 | nand_chip->options |= NAND_BUSWIDTH_16; | 2103 | nand_chip->options |= NAND_BUSWIDTH_16; |
@@ -2248,6 +2246,7 @@ static int atmel_nand_nfc_probe(struct platform_device *pdev) | |||
2248 | { | 2246 | { |
2249 | struct atmel_nfc *nfc = &nand_nfc; | 2247 | struct atmel_nfc *nfc = &nand_nfc; |
2250 | struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram; | 2248 | struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram; |
2249 | int ret; | ||
2251 | 2250 | ||
2252 | nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 2251 | nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2253 | nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs); | 2252 | nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs); |
@@ -2279,8 +2278,28 @@ static int atmel_nand_nfc_probe(struct platform_device *pdev) | |||
2279 | nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff); | 2278 | nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff); |
2280 | nfc_readl(nfc->hsmc_regs, SR); /* clear the NFC_SR */ | 2279 | nfc_readl(nfc->hsmc_regs, SR); /* clear the NFC_SR */ |
2281 | 2280 | ||
2281 | nfc->clk = devm_clk_get(&pdev->dev, NULL); | ||
2282 | if (!IS_ERR(nfc->clk)) { | ||
2283 | ret = clk_prepare_enable(nfc->clk); | ||
2284 | if (ret) | ||
2285 | return ret; | ||
2286 | } else { | ||
2287 | dev_warn(&pdev->dev, "NFC clock missing, update your Device Tree"); | ||
2288 | } | ||
2289 | |||
2282 | nfc->is_initialized = true; | 2290 | nfc->is_initialized = true; |
2283 | dev_info(&pdev->dev, "NFC is probed.\n"); | 2291 | dev_info(&pdev->dev, "NFC is probed.\n"); |
2292 | |||
2293 | return 0; | ||
2294 | } | ||
2295 | |||
2296 | static int atmel_nand_nfc_remove(struct platform_device *pdev) | ||
2297 | { | ||
2298 | struct atmel_nfc *nfc = &nand_nfc; | ||
2299 | |||
2300 | if (!IS_ERR(nfc->clk)) | ||
2301 | clk_disable_unprepare(nfc->clk); | ||
2302 | |||
2284 | return 0; | 2303 | return 0; |
2285 | } | 2304 | } |
2286 | 2305 | ||
@@ -2297,6 +2316,7 @@ static struct platform_driver atmel_nand_nfc_driver = { | |||
2297 | .of_match_table = of_match_ptr(atmel_nand_nfc_match), | 2316 | .of_match_table = of_match_ptr(atmel_nand_nfc_match), |
2298 | }, | 2317 | }, |
2299 | .probe = atmel_nand_nfc_probe, | 2318 | .probe = atmel_nand_nfc_probe, |
2319 | .remove = atmel_nand_nfc_remove, | ||
2300 | }; | 2320 | }; |
2301 | 2321 | ||
2302 | static struct platform_driver atmel_nand_driver = { | 2322 | static struct platform_driver atmel_nand_driver = { |
diff --git a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c index b2ab373c9eef..592befc7ffa1 100644 --- a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c +++ b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/module.h> | 14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/slab.h> | 16 | #include <linux/slab.h> |
17 | #include <linux/delay.h> | ||
17 | #include <linux/bcma/bcma.h> | 18 | #include <linux/bcma/bcma.h> |
18 | 19 | ||
19 | /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has | 20 | /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has |
@@ -23,6 +24,8 @@ | |||
23 | #define NFLASH_SECTOR_SIZE 512 | 24 | #define NFLASH_SECTOR_SIZE 512 |
24 | 25 | ||
25 | #define NCTL_CMD0 0x00010000 | 26 | #define NCTL_CMD0 0x00010000 |
27 | #define NCTL_COL 0x00020000 /* Update column with value from BCMA_CC_NFLASH_COL_ADDR */ | ||
28 | #define NCTL_ROW 0x00040000 /* Update row (page) with value from BCMA_CC_NFLASH_ROW_ADDR */ | ||
26 | #define NCTL_CMD1W 0x00080000 | 29 | #define NCTL_CMD1W 0x00080000 |
27 | #define NCTL_READ 0x00100000 | 30 | #define NCTL_READ 0x00100000 |
28 | #define NCTL_WRITE 0x00200000 | 31 | #define NCTL_WRITE 0x00200000 |
@@ -109,7 +112,7 @@ static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf, | |||
109 | b47n->curr_page_addr); | 112 | b47n->curr_page_addr); |
110 | 113 | ||
111 | /* Prepare to read */ | 114 | /* Prepare to read */ |
112 | ctlcode = NCTL_CSA | NCTL_CMD1W | 0x00040000 | 0x00020000 | | 115 | ctlcode = NCTL_CSA | NCTL_CMD1W | NCTL_ROW | NCTL_COL | |
113 | NCTL_CMD0; | 116 | NCTL_CMD0; |
114 | ctlcode |= NAND_CMD_READSTART << 8; | 117 | ctlcode |= NAND_CMD_READSTART << 8; |
115 | if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) | 118 | if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) |
@@ -167,6 +170,26 @@ static void bcm47xxnflash_ops_bcm4706_write(struct mtd_info *mtd, | |||
167 | * NAND chip ops | 170 | * NAND chip ops |
168 | **************************************************/ | 171 | **************************************************/ |
169 | 172 | ||
173 | static void bcm47xxnflash_ops_bcm4706_cmd_ctrl(struct mtd_info *mtd, int cmd, | ||
174 | unsigned int ctrl) | ||
175 | { | ||
176 | struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv; | ||
177 | struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv; | ||
178 | u32 code = 0; | ||
179 | |||
180 | if (cmd == NAND_CMD_NONE) | ||
181 | return; | ||
182 | |||
183 | if (cmd & NAND_CTRL_CLE) | ||
184 | code = cmd | NCTL_CMD0; | ||
185 | |||
186 | /* nCS is not needed for reset command */ | ||
187 | if (cmd != NAND_CMD_RESET) | ||
188 | code |= NCTL_CSA; | ||
189 | |||
190 | bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, code); | ||
191 | } | ||
192 | |||
170 | /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */ | 193 | /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */ |
171 | static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd, | 194 | static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd, |
172 | int chip) | 195 | int chip) |
@@ -174,6 +197,14 @@ static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd, | |||
174 | return; | 197 | return; |
175 | } | 198 | } |
176 | 199 | ||
200 | static int bcm47xxnflash_ops_bcm4706_dev_ready(struct mtd_info *mtd) | ||
201 | { | ||
202 | struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv; | ||
203 | struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv; | ||
204 | |||
205 | return !!(bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_CTL) & NCTL_READY); | ||
206 | } | ||
207 | |||
177 | /* | 208 | /* |
178 | * Default nand_command and nand_command_lp don't match BCM4706 hardware layout. | 209 | * Default nand_command and nand_command_lp don't match BCM4706 hardware layout. |
179 | * For example, reading chip id is performed in a non-standard way. | 210 | * For example, reading chip id is performed in a non-standard way. |
@@ -198,7 +229,10 @@ static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd, | |||
198 | 229 | ||
199 | switch (command) { | 230 | switch (command) { |
200 | case NAND_CMD_RESET: | 231 | case NAND_CMD_RESET: |
201 | pr_warn("Chip reset not implemented yet\n"); | 232 | nand_chip->cmd_ctrl(mtd, command, NAND_CTRL_CLE); |
233 | |||
234 | ndelay(100); | ||
235 | nand_wait_ready(mtd); | ||
202 | break; | 236 | break; |
203 | case NAND_CMD_READID: | 237 | case NAND_CMD_READID: |
204 | ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0; | 238 | ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0; |
@@ -242,7 +276,7 @@ static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd, | |||
242 | case NAND_CMD_ERASE1: | 276 | case NAND_CMD_ERASE1: |
243 | bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR, | 277 | bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR, |
244 | b47n->curr_page_addr); | 278 | b47n->curr_page_addr); |
245 | ctlcode = 0x00040000 | NCTL_CMD1W | NCTL_CMD0 | | 279 | ctlcode = NCTL_ROW | NCTL_CMD1W | NCTL_CMD0 | |
246 | NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8); | 280 | NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8); |
247 | if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) | 281 | if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) |
248 | pr_err("ERASE1 failed\n"); | 282 | pr_err("ERASE1 failed\n"); |
@@ -257,13 +291,13 @@ static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd, | |||
257 | b47n->curr_page_addr); | 291 | b47n->curr_page_addr); |
258 | 292 | ||
259 | /* Prepare to write */ | 293 | /* Prepare to write */ |
260 | ctlcode = 0x40000000 | 0x00040000 | 0x00020000 | 0x00010000; | 294 | ctlcode = 0x40000000 | NCTL_ROW | NCTL_COL | NCTL_CMD0; |
261 | ctlcode |= NAND_CMD_SEQIN; | 295 | ctlcode |= NAND_CMD_SEQIN; |
262 | if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) | 296 | if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) |
263 | pr_err("SEQIN failed\n"); | 297 | pr_err("SEQIN failed\n"); |
264 | break; | 298 | break; |
265 | case NAND_CMD_PAGEPROG: | 299 | case NAND_CMD_PAGEPROG: |
266 | if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, 0x00010000 | | 300 | if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_CMD0 | |
267 | NAND_CMD_PAGEPROG)) | 301 | NAND_CMD_PAGEPROG)) |
268 | pr_err("PAGEPROG failed\n"); | 302 | pr_err("PAGEPROG failed\n"); |
269 | if (bcm47xxnflash_ops_bcm4706_poll(cc)) | 303 | if (bcm47xxnflash_ops_bcm4706_poll(cc)) |
@@ -341,6 +375,7 @@ static void bcm47xxnflash_ops_bcm4706_write_buf(struct mtd_info *mtd, | |||
341 | 375 | ||
342 | int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n) | 376 | int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n) |
343 | { | 377 | { |
378 | struct nand_chip *nand_chip = (struct nand_chip *)&b47n->nand_chip; | ||
344 | int err; | 379 | int err; |
345 | u32 freq; | 380 | u32 freq; |
346 | u16 clock; | 381 | u16 clock; |
@@ -351,10 +386,14 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n) | |||
351 | u32 val; | 386 | u32 val; |
352 | 387 | ||
353 | b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip; | 388 | b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip; |
389 | nand_chip->cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl; | ||
390 | nand_chip->dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready; | ||
354 | b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc; | 391 | b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc; |
355 | b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte; | 392 | b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte; |
356 | b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf; | 393 | b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf; |
357 | b47n->nand_chip.write_buf = bcm47xxnflash_ops_bcm4706_write_buf; | 394 | b47n->nand_chip.write_buf = bcm47xxnflash_ops_bcm4706_write_buf; |
395 | |||
396 | nand_chip->chip_delay = 50; | ||
358 | b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH; | 397 | b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH; |
359 | b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */ | 398 | b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */ |
360 | 399 | ||
@@ -364,11 +403,13 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n) | |||
364 | 403 | ||
365 | /* Configure wait counters */ | 404 | /* Configure wait counters */ |
366 | if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) { | 405 | if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) { |
367 | freq = 100000000; | 406 | /* 400 MHz */ |
407 | freq = 400000000 / 4; | ||
368 | } else { | 408 | } else { |
369 | freq = bcma_chipco_pll_read(b47n->cc, 4); | 409 | freq = bcma_chipco_pll_read(b47n->cc, 4); |
370 | freq = (freq * 0xFFF) >> 3; | 410 | freq = (freq & 0xFFF) >> 3; |
371 | freq = (freq * 25000000) >> 3; | 411 | /* Fixed reference clock 25 MHz and m = 2 */ |
412 | freq = (freq * 25000000 / 2) / 4; | ||
372 | } | 413 | } |
373 | clock = freq / 1000000; | 414 | clock = freq / 1000000; |
374 | w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock); | 415 | w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock); |
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 0b071a3136a2..b3b7ca1bafb8 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c | |||
@@ -29,20 +29,23 @@ | |||
29 | 29 | ||
30 | MODULE_LICENSE("GPL"); | 30 | MODULE_LICENSE("GPL"); |
31 | 31 | ||
32 | /* We define a module parameter that allows the user to override | 32 | /* |
33 | * We define a module parameter that allows the user to override | ||
33 | * the hardware and decide what timing mode should be used. | 34 | * the hardware and decide what timing mode should be used. |
34 | */ | 35 | */ |
35 | #define NAND_DEFAULT_TIMINGS -1 | 36 | #define NAND_DEFAULT_TIMINGS -1 |
36 | 37 | ||
37 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; | 38 | static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; |
38 | module_param(onfi_timing_mode, int, S_IRUGO); | 39 | module_param(onfi_timing_mode, int, S_IRUGO); |
39 | MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting." | 40 | MODULE_PARM_DESC(onfi_timing_mode, |
40 | " -1 indicates use default timings"); | 41 | "Overrides default ONFI setting. -1 indicates use default timings"); |
41 | 42 | ||
42 | #define DENALI_NAND_NAME "denali-nand" | 43 | #define DENALI_NAND_NAME "denali-nand" |
43 | 44 | ||
44 | /* We define a macro here that combines all interrupts this driver uses into | 45 | /* |
45 | * a single constant value, for convenience. */ | 46 | * We define a macro here that combines all interrupts this driver uses into |
47 | * a single constant value, for convenience. | ||
48 | */ | ||
46 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ | 49 | #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \ |
47 | INTR_STATUS__ECC_TRANSACTION_DONE | \ | 50 | INTR_STATUS__ECC_TRANSACTION_DONE | \ |
48 | INTR_STATUS__ECC_ERR | \ | 51 | INTR_STATUS__ECC_ERR | \ |
@@ -54,26 +57,34 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting." | |||
54 | INTR_STATUS__RST_COMP | \ | 57 | INTR_STATUS__RST_COMP | \ |
55 | INTR_STATUS__ERASE_COMP) | 58 | INTR_STATUS__ERASE_COMP) |
56 | 59 | ||
57 | /* indicates whether or not the internal value for the flash bank is | 60 | /* |
58 | * valid or not */ | 61 | * indicates whether or not the internal value for the flash bank is |
62 | * valid or not | ||
63 | */ | ||
59 | #define CHIP_SELECT_INVALID -1 | 64 | #define CHIP_SELECT_INVALID -1 |
60 | 65 | ||
61 | #define SUPPORT_8BITECC 1 | 66 | #define SUPPORT_8BITECC 1 |
62 | 67 | ||
63 | /* This macro divides two integers and rounds fractional values up | 68 | /* |
64 | * to the nearest integer value. */ | 69 | * This macro divides two integers and rounds fractional values up |
70 | * to the nearest integer value. | ||
71 | */ | ||
65 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) | 72 | #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y))) |
66 | 73 | ||
67 | /* this macro allows us to convert from an MTD structure to our own | 74 | /* |
75 | * this macro allows us to convert from an MTD structure to our own | ||
68 | * device context (denali) structure. | 76 | * device context (denali) structure. |
69 | */ | 77 | */ |
70 | #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd) | 78 | #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd) |
71 | 79 | ||
72 | /* These constants are defined by the driver to enable common driver | 80 | /* |
73 | * configuration options. */ | 81 | * These constants are defined by the driver to enable common driver |
82 | * configuration options. | ||
83 | */ | ||
74 | #define SPARE_ACCESS 0x41 | 84 | #define SPARE_ACCESS 0x41 |
75 | #define MAIN_ACCESS 0x42 | 85 | #define MAIN_ACCESS 0x42 |
76 | #define MAIN_SPARE_ACCESS 0x43 | 86 | #define MAIN_SPARE_ACCESS 0x43 |
87 | #define PIPELINE_ACCESS 0x2000 | ||
77 | 88 | ||
78 | #define DENALI_READ 0 | 89 | #define DENALI_READ 0 |
79 | #define DENALI_WRITE 0x100 | 90 | #define DENALI_WRITE 0x100 |
@@ -83,8 +94,10 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting." | |||
83 | #define ADDR_CYCLE 1 | 94 | #define ADDR_CYCLE 1 |
84 | #define STATUS_CYCLE 2 | 95 | #define STATUS_CYCLE 2 |
85 | 96 | ||
86 | /* this is a helper macro that allows us to | 97 | /* |
87 | * format the bank into the proper bits for the controller */ | 98 | * this is a helper macro that allows us to |
99 | * format the bank into the proper bits for the controller | ||
100 | */ | ||
88 | #define BANK(x) ((x) << 24) | 101 | #define BANK(x) ((x) << 24) |
89 | 102 | ||
90 | /* forward declarations */ | 103 | /* forward declarations */ |
@@ -95,12 +108,12 @@ static void denali_irq_enable(struct denali_nand_info *denali, | |||
95 | uint32_t int_mask); | 108 | uint32_t int_mask); |
96 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); | 109 | static uint32_t read_interrupt_status(struct denali_nand_info *denali); |
97 | 110 | ||
98 | /* Certain operations for the denali NAND controller use | 111 | /* |
99 | * an indexed mode to read/write data. The operation is | 112 | * Certain operations for the denali NAND controller use an indexed mode to |
100 | * performed by writing the address value of the command | 113 | * read/write data. The operation is performed by writing the address value |
101 | * to the device memory followed by the data. This function | 114 | * of the command to the device memory followed by the data. This function |
102 | * abstracts this common operation. | 115 | * abstracts this common operation. |
103 | */ | 116 | */ |
104 | static void index_addr(struct denali_nand_info *denali, | 117 | static void index_addr(struct denali_nand_info *denali, |
105 | uint32_t address, uint32_t data) | 118 | uint32_t address, uint32_t data) |
106 | { | 119 | { |
@@ -116,8 +129,10 @@ static void index_addr_read_data(struct denali_nand_info *denali, | |||
116 | *pdata = ioread32(denali->flash_mem + 0x10); | 129 | *pdata = ioread32(denali->flash_mem + 0x10); |
117 | } | 130 | } |
118 | 131 | ||
119 | /* We need to buffer some data for some of the NAND core routines. | 132 | /* |
120 | * The operations manage buffering that data. */ | 133 | * We need to buffer some data for some of the NAND core routines. |
134 | * The operations manage buffering that data. | ||
135 | */ | ||
121 | static void reset_buf(struct denali_nand_info *denali) | 136 | static void reset_buf(struct denali_nand_info *denali) |
122 | { | 137 | { |
123 | denali->buf.head = denali->buf.tail = 0; | 138 | denali->buf.head = denali->buf.tail = 0; |
@@ -131,7 +146,7 @@ static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte) | |||
131 | /* reads the status of the device */ | 146 | /* reads the status of the device */ |
132 | static void read_status(struct denali_nand_info *denali) | 147 | static void read_status(struct denali_nand_info *denali) |
133 | { | 148 | { |
134 | uint32_t cmd = 0x0; | 149 | uint32_t cmd; |
135 | 150 | ||
136 | /* initialize the data buffer to store status */ | 151 | /* initialize the data buffer to store status */ |
137 | reset_buf(denali); | 152 | reset_buf(denali); |
@@ -146,9 +161,8 @@ static void read_status(struct denali_nand_info *denali) | |||
146 | /* resets a specific device connected to the core */ | 161 | /* resets a specific device connected to the core */ |
147 | static void reset_bank(struct denali_nand_info *denali) | 162 | static void reset_bank(struct denali_nand_info *denali) |
148 | { | 163 | { |
149 | uint32_t irq_status = 0; | 164 | uint32_t irq_status; |
150 | uint32_t irq_mask = INTR_STATUS__RST_COMP | | 165 | uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT; |
151 | INTR_STATUS__TIME_OUT; | ||
152 | 166 | ||
153 | clear_interrupts(denali); | 167 | clear_interrupts(denali); |
154 | 168 | ||
@@ -163,19 +177,18 @@ static void reset_bank(struct denali_nand_info *denali) | |||
163 | /* Reset the flash controller */ | 177 | /* Reset the flash controller */ |
164 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) | 178 | static uint16_t denali_nand_reset(struct denali_nand_info *denali) |
165 | { | 179 | { |
166 | uint32_t i; | 180 | int i; |
167 | 181 | ||
168 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", | 182 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
169 | __FILE__, __LINE__, __func__); | 183 | __FILE__, __LINE__, __func__); |
170 | 184 | ||
171 | for (i = 0 ; i < denali->max_banks; i++) | 185 | for (i = 0; i < denali->max_banks; i++) |
172 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, | 186 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
173 | denali->flash_reg + INTR_STATUS(i)); | 187 | denali->flash_reg + INTR_STATUS(i)); |
174 | 188 | ||
175 | for (i = 0 ; i < denali->max_banks; i++) { | 189 | for (i = 0; i < denali->max_banks; i++) { |
176 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); | 190 | iowrite32(1 << i, denali->flash_reg + DEVICE_RESET); |
177 | while (!(ioread32(denali->flash_reg + | 191 | while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) & |
178 | INTR_STATUS(i)) & | ||
179 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) | 192 | (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT))) |
180 | cpu_relax(); | 193 | cpu_relax(); |
181 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & | 194 | if (ioread32(denali->flash_reg + INTR_STATUS(i)) & |
@@ -186,12 +199,13 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali) | |||
186 | 199 | ||
187 | for (i = 0; i < denali->max_banks; i++) | 200 | for (i = 0; i < denali->max_banks; i++) |
188 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, | 201 | iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT, |
189 | denali->flash_reg + INTR_STATUS(i)); | 202 | denali->flash_reg + INTR_STATUS(i)); |
190 | 203 | ||
191 | return PASS; | 204 | return PASS; |
192 | } | 205 | } |
193 | 206 | ||
194 | /* this routine calculates the ONFI timing values for a given mode and | 207 | /* |
208 | * this routine calculates the ONFI timing values for a given mode and | ||
195 | * programs the clocking register accordingly. The mode is determined by | 209 | * programs the clocking register accordingly. The mode is determined by |
196 | * the get_onfi_nand_para routine. | 210 | * the get_onfi_nand_para routine. |
197 | */ | 211 | */ |
@@ -219,7 +233,7 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali, | |||
219 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; | 233 | uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt; |
220 | 234 | ||
221 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", | 235 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
222 | __FILE__, __LINE__, __func__); | 236 | __FILE__, __LINE__, __func__); |
223 | 237 | ||
224 | en_lo = CEIL_DIV(Trp[mode], CLK_X); | 238 | en_lo = CEIL_DIV(Trp[mode], CLK_X); |
225 | en_hi = CEIL_DIV(Treh[mode], CLK_X); | 239 | en_hi = CEIL_DIV(Treh[mode], CLK_X); |
@@ -239,9 +253,8 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali, | |||
239 | 253 | ||
240 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; | 254 | data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode]; |
241 | 255 | ||
242 | data_invalid = | 256 | data_invalid = data_invalid_rhoh < data_invalid_rloh ? |
243 | data_invalid_rhoh < | 257 | data_invalid_rhoh : data_invalid_rloh; |
244 | data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh; | ||
245 | 258 | ||
246 | dv_window = data_invalid - Trea[mode]; | 259 | dv_window = data_invalid - Trea[mode]; |
247 | 260 | ||
@@ -251,12 +264,12 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali, | |||
251 | 264 | ||
252 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); | 265 | acc_clks = CEIL_DIV(Trea[mode], CLK_X); |
253 | 266 | ||
254 | while (((acc_clks * CLK_X) - Trea[mode]) < 3) | 267 | while (acc_clks * CLK_X - Trea[mode] < 3) |
255 | acc_clks++; | 268 | acc_clks++; |
256 | 269 | ||
257 | if ((data_invalid - acc_clks * CLK_X) < 2) | 270 | if (data_invalid - acc_clks * CLK_X < 2) |
258 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", | 271 | dev_warn(denali->dev, "%s, Line %d: Warning!\n", |
259 | __FILE__, __LINE__); | 272 | __FILE__, __LINE__); |
260 | 273 | ||
261 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); | 274 | addr_2_data = CEIL_DIV(Tadl[mode], CLK_X); |
262 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); | 275 | re_2_we = CEIL_DIV(Trhw[mode], CLK_X); |
@@ -269,7 +282,7 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali, | |||
269 | cs_cnt = 1; | 282 | cs_cnt = 1; |
270 | 283 | ||
271 | if (Tcea[mode]) { | 284 | if (Tcea[mode]) { |
272 | while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode]) | 285 | while (cs_cnt * CLK_X + Trea[mode] < Tcea[mode]) |
273 | cs_cnt++; | 286 | cs_cnt++; |
274 | } | 287 | } |
275 | 288 | ||
@@ -279,8 +292,8 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali, | |||
279 | #endif | 292 | #endif |
280 | 293 | ||
281 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ | 294 | /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */ |
282 | if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) && | 295 | if (ioread32(denali->flash_reg + MANUFACTURER_ID) == 0 && |
283 | (ioread32(denali->flash_reg + DEVICE_ID) == 0x88)) | 296 | ioread32(denali->flash_reg + DEVICE_ID) == 0x88) |
284 | acc_clks = 6; | 297 | acc_clks = 6; |
285 | 298 | ||
286 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); | 299 | iowrite32(acc_clks, denali->flash_reg + ACC_CLKS); |
@@ -297,9 +310,11 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali, | |||
297 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | 310 | static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) |
298 | { | 311 | { |
299 | int i; | 312 | int i; |
300 | /* we needn't to do a reset here because driver has already | 313 | |
314 | /* | ||
315 | * we needn't to do a reset here because driver has already | ||
301 | * reset all the banks before | 316 | * reset all the banks before |
302 | * */ | 317 | */ |
303 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & | 318 | if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) & |
304 | ONFI_TIMING_MODE__VALUE)) | 319 | ONFI_TIMING_MODE__VALUE)) |
305 | return FAIL; | 320 | return FAIL; |
@@ -312,8 +327,10 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali) | |||
312 | 327 | ||
313 | nand_onfi_timing_set(denali, i); | 328 | nand_onfi_timing_set(denali, i); |
314 | 329 | ||
315 | /* By now, all the ONFI devices we know support the page cache */ | 330 | /* |
316 | /* rw feature. So here we enable the pipeline_rw_ahead feature */ | 331 | * By now, all the ONFI devices we know support the page cache |
332 | * rw feature. So here we enable the pipeline_rw_ahead feature | ||
333 | */ | ||
317 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ | 334 | /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */ |
318 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ | 335 | /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */ |
319 | 336 | ||
@@ -339,8 +356,10 @@ static void get_toshiba_nand_para(struct denali_nand_info *denali) | |||
339 | { | 356 | { |
340 | uint32_t tmp; | 357 | uint32_t tmp; |
341 | 358 | ||
342 | /* Workaround to fix a controller bug which reports a wrong */ | 359 | /* |
343 | /* spare area size for some kind of Toshiba NAND device */ | 360 | * Workaround to fix a controller bug which reports a wrong |
361 | * spare area size for some kind of Toshiba NAND device | ||
362 | */ | ||
344 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && | 363 | if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) && |
345 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { | 364 | (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) { |
346 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); | 365 | iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); |
@@ -384,13 +403,14 @@ static void get_hynix_nand_para(struct denali_nand_info *denali, | |||
384 | break; | 403 | break; |
385 | default: | 404 | default: |
386 | dev_warn(denali->dev, | 405 | dev_warn(denali->dev, |
387 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x)." | 406 | "Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n" |
388 | "Will use default parameter values instead.\n", | 407 | "Will use default parameter values instead.\n", |
389 | device_id); | 408 | device_id); |
390 | } | 409 | } |
391 | } | 410 | } |
392 | 411 | ||
393 | /* determines how many NAND chips are connected to the controller. Note for | 412 | /* |
413 | * determines how many NAND chips are connected to the controller. Note for | ||
394 | * Intel CE4100 devices we don't support more than one device. | 414 | * Intel CE4100 devices we don't support more than one device. |
395 | */ | 415 | */ |
396 | static void find_valid_banks(struct denali_nand_info *denali) | 416 | static void find_valid_banks(struct denali_nand_info *denali) |
@@ -400,10 +420,9 @@ static void find_valid_banks(struct denali_nand_info *denali) | |||
400 | 420 | ||
401 | denali->total_used_banks = 1; | 421 | denali->total_used_banks = 1; |
402 | for (i = 0; i < denali->max_banks; i++) { | 422 | for (i = 0; i < denali->max_banks; i++) { |
403 | index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90); | 423 | index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); |
404 | index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0); | 424 | index_addr(denali, MODE_11 | (i << 24) | 1, 0); |
405 | index_addr_read_data(denali, | 425 | index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); |
406 | (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); | ||
407 | 426 | ||
408 | dev_dbg(denali->dev, | 427 | dev_dbg(denali->dev, |
409 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); | 428 | "Return 1st ID for bank[%d]: %x\n", i, id[i]); |
@@ -420,14 +439,14 @@ static void find_valid_banks(struct denali_nand_info *denali) | |||
420 | } | 439 | } |
421 | 440 | ||
422 | if (denali->platform == INTEL_CE4100) { | 441 | if (denali->platform == INTEL_CE4100) { |
423 | /* Platform limitations of the CE4100 device limit | 442 | /* |
443 | * Platform limitations of the CE4100 device limit | ||
424 | * users to a single chip solution for NAND. | 444 | * users to a single chip solution for NAND. |
425 | * Multichip support is not enabled. | 445 | * Multichip support is not enabled. |
426 | */ | 446 | */ |
427 | if (denali->total_used_banks != 1) { | 447 | if (denali->total_used_banks != 1) { |
428 | dev_err(denali->dev, | 448 | dev_err(denali->dev, |
429 | "Sorry, Intel CE4100 only supports " | 449 | "Sorry, Intel CE4100 only supports a single NAND device.\n"); |
430 | "a single NAND device.\n"); | ||
431 | BUG(); | 450 | BUG(); |
432 | } | 451 | } |
433 | } | 452 | } |
@@ -448,12 +467,13 @@ static void detect_max_banks(struct denali_nand_info *denali) | |||
448 | 467 | ||
449 | static void detect_partition_feature(struct denali_nand_info *denali) | 468 | static void detect_partition_feature(struct denali_nand_info *denali) |
450 | { | 469 | { |
451 | /* For MRST platform, denali->fwblks represent the | 470 | /* |
471 | * For MRST platform, denali->fwblks represent the | ||
452 | * number of blocks firmware is taken, | 472 | * number of blocks firmware is taken, |
453 | * FW is in protect partition and MTD driver has no | 473 | * FW is in protect partition and MTD driver has no |
454 | * permission to access it. So let driver know how many | 474 | * permission to access it. So let driver know how many |
455 | * blocks it can't touch. | 475 | * blocks it can't touch. |
456 | * */ | 476 | */ |
457 | if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { | 477 | if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) { |
458 | if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) & | 478 | if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) & |
459 | PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { | 479 | PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) { |
@@ -464,30 +484,32 @@ static void detect_partition_feature(struct denali_nand_info *denali) | |||
464 | + | 484 | + |
465 | (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) & | 485 | (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) & |
466 | MIN_BLK_ADDR__VALUE); | 486 | MIN_BLK_ADDR__VALUE); |
467 | } else | 487 | } else { |
468 | denali->fwblks = SPECTRA_START_BLOCK; | 488 | denali->fwblks = SPECTRA_START_BLOCK; |
469 | } else | 489 | } |
490 | } else { | ||
470 | denali->fwblks = SPECTRA_START_BLOCK; | 491 | denali->fwblks = SPECTRA_START_BLOCK; |
492 | } | ||
471 | } | 493 | } |
472 | 494 | ||
473 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) | 495 | static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) |
474 | { | 496 | { |
475 | uint16_t status = PASS; | 497 | uint16_t status = PASS; |
476 | uint32_t id_bytes[8], addr; | 498 | uint32_t id_bytes[8], addr; |
477 | uint8_t i, maf_id, device_id; | 499 | uint8_t maf_id, device_id; |
500 | int i; | ||
478 | 501 | ||
479 | dev_dbg(denali->dev, | 502 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
480 | "%s, Line %d, Function: %s\n", | ||
481 | __FILE__, __LINE__, __func__); | 503 | __FILE__, __LINE__, __func__); |
482 | 504 | ||
483 | /* Use read id method to get device ID and other | 505 | /* |
484 | * params. For some NAND chips, controller can't | 506 | * Use read id method to get device ID and other params. |
485 | * report the correct device ID by reading from | 507 | * For some NAND chips, controller can't report the correct |
486 | * DEVICE_ID register | 508 | * device ID by reading from DEVICE_ID register |
487 | * */ | 509 | */ |
488 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | 510 | addr = MODE_11 | BANK(denali->flash_bank); |
489 | index_addr(denali, (uint32_t)addr | 0, 0x90); | 511 | index_addr(denali, addr | 0, 0x90); |
490 | index_addr(denali, (uint32_t)addr | 1, 0); | 512 | index_addr(denali, addr | 1, 0); |
491 | for (i = 0; i < 8; i++) | 513 | for (i = 0; i < 8; i++) |
492 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); | 514 | index_addr_read_data(denali, addr | 2, &id_bytes[i]); |
493 | maf_id = id_bytes[0]; | 515 | maf_id = id_bytes[0]; |
@@ -506,7 +528,7 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) | |||
506 | } | 528 | } |
507 | 529 | ||
508 | dev_info(denali->dev, | 530 | dev_info(denali->dev, |
509 | "Dump timing register values:" | 531 | "Dump timing register values:\n" |
510 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" | 532 | "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" |
511 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" | 533 | "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" |
512 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", | 534 | "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", |
@@ -523,7 +545,8 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) | |||
523 | 545 | ||
524 | detect_partition_feature(denali); | 546 | detect_partition_feature(denali); |
525 | 547 | ||
526 | /* If the user specified to override the default timings | 548 | /* |
549 | * If the user specified to override the default timings | ||
527 | * with a specific ONFI mode, we apply those changes here. | 550 | * with a specific ONFI mode, we apply those changes here. |
528 | */ | 551 | */ |
529 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) | 552 | if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) |
@@ -536,7 +559,7 @@ static void denali_set_intr_modes(struct denali_nand_info *denali, | |||
536 | uint16_t INT_ENABLE) | 559 | uint16_t INT_ENABLE) |
537 | { | 560 | { |
538 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", | 561 | dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", |
539 | __FILE__, __LINE__, __func__); | 562 | __FILE__, __LINE__, __func__); |
540 | 563 | ||
541 | if (INT_ENABLE) | 564 | if (INT_ENABLE) |
542 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); | 565 | iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE); |
@@ -544,17 +567,18 @@ static void denali_set_intr_modes(struct denali_nand_info *denali, | |||
544 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); | 567 | iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE); |
545 | } | 568 | } |
546 | 569 | ||
547 | /* validation function to verify that the controlling software is making | 570 | /* |
571 | * validation function to verify that the controlling software is making | ||
548 | * a valid request | 572 | * a valid request |
549 | */ | 573 | */ |
550 | static inline bool is_flash_bank_valid(int flash_bank) | 574 | static inline bool is_flash_bank_valid(int flash_bank) |
551 | { | 575 | { |
552 | return (flash_bank >= 0 && flash_bank < 4); | 576 | return flash_bank >= 0 && flash_bank < 4; |
553 | } | 577 | } |
554 | 578 | ||
555 | static void denali_irq_init(struct denali_nand_info *denali) | 579 | static void denali_irq_init(struct denali_nand_info *denali) |
556 | { | 580 | { |
557 | uint32_t int_mask = 0; | 581 | uint32_t int_mask; |
558 | int i; | 582 | int i; |
559 | 583 | ||
560 | /* Disable global interrupts */ | 584 | /* Disable global interrupts */ |
@@ -584,7 +608,8 @@ static void denali_irq_enable(struct denali_nand_info *denali, | |||
584 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); | 608 | iowrite32(int_mask, denali->flash_reg + INTR_EN(i)); |
585 | } | 609 | } |
586 | 610 | ||
587 | /* This function only returns when an interrupt that this driver cares about | 611 | /* |
612 | * This function only returns when an interrupt that this driver cares about | ||
588 | * occurs. This is to reduce the overhead of servicing interrupts | 613 | * occurs. This is to reduce the overhead of servicing interrupts |
589 | */ | 614 | */ |
590 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | 615 | static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) |
@@ -596,7 +621,7 @@ static inline uint32_t denali_irq_detected(struct denali_nand_info *denali) | |||
596 | static inline void clear_interrupt(struct denali_nand_info *denali, | 621 | static inline void clear_interrupt(struct denali_nand_info *denali, |
597 | uint32_t irq_mask) | 622 | uint32_t irq_mask) |
598 | { | 623 | { |
599 | uint32_t intr_status_reg = 0; | 624 | uint32_t intr_status_reg; |
600 | 625 | ||
601 | intr_status_reg = INTR_STATUS(denali->flash_bank); | 626 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
602 | 627 | ||
@@ -605,7 +630,8 @@ static inline void clear_interrupt(struct denali_nand_info *denali, | |||
605 | 630 | ||
606 | static void clear_interrupts(struct denali_nand_info *denali) | 631 | static void clear_interrupts(struct denali_nand_info *denali) |
607 | { | 632 | { |
608 | uint32_t status = 0x0; | 633 | uint32_t status; |
634 | |||
609 | spin_lock_irq(&denali->irq_lock); | 635 | spin_lock_irq(&denali->irq_lock); |
610 | 636 | ||
611 | status = read_interrupt_status(denali); | 637 | status = read_interrupt_status(denali); |
@@ -617,38 +643,40 @@ static void clear_interrupts(struct denali_nand_info *denali) | |||
617 | 643 | ||
618 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) | 644 | static uint32_t read_interrupt_status(struct denali_nand_info *denali) |
619 | { | 645 | { |
620 | uint32_t intr_status_reg = 0; | 646 | uint32_t intr_status_reg; |
621 | 647 | ||
622 | intr_status_reg = INTR_STATUS(denali->flash_bank); | 648 | intr_status_reg = INTR_STATUS(denali->flash_bank); |
623 | 649 | ||
624 | return ioread32(denali->flash_reg + intr_status_reg); | 650 | return ioread32(denali->flash_reg + intr_status_reg); |
625 | } | 651 | } |
626 | 652 | ||
627 | /* This is the interrupt service routine. It handles all interrupts | 653 | /* |
628 | * sent to this device. Note that on CE4100, this is a shared | 654 | * This is the interrupt service routine. It handles all interrupts |
629 | * interrupt. | 655 | * sent to this device. Note that on CE4100, this is a shared interrupt. |
630 | */ | 656 | */ |
631 | static irqreturn_t denali_isr(int irq, void *dev_id) | 657 | static irqreturn_t denali_isr(int irq, void *dev_id) |
632 | { | 658 | { |
633 | struct denali_nand_info *denali = dev_id; | 659 | struct denali_nand_info *denali = dev_id; |
634 | uint32_t irq_status = 0x0; | 660 | uint32_t irq_status; |
635 | irqreturn_t result = IRQ_NONE; | 661 | irqreturn_t result = IRQ_NONE; |
636 | 662 | ||
637 | spin_lock(&denali->irq_lock); | 663 | spin_lock(&denali->irq_lock); |
638 | 664 | ||
639 | /* check to see if a valid NAND chip has | 665 | /* check to see if a valid NAND chip has been selected. */ |
640 | * been selected. | ||
641 | */ | ||
642 | if (is_flash_bank_valid(denali->flash_bank)) { | 666 | if (is_flash_bank_valid(denali->flash_bank)) { |
643 | /* check to see if controller generated | 667 | /* |
644 | * the interrupt, since this is a shared interrupt */ | 668 | * check to see if controller generated the interrupt, |
669 | * since this is a shared interrupt | ||
670 | */ | ||
645 | irq_status = denali_irq_detected(denali); | 671 | irq_status = denali_irq_detected(denali); |
646 | if (irq_status != 0) { | 672 | if (irq_status != 0) { |
647 | /* handle interrupt */ | 673 | /* handle interrupt */ |
648 | /* first acknowledge it */ | 674 | /* first acknowledge it */ |
649 | clear_interrupt(denali, irq_status); | 675 | clear_interrupt(denali, irq_status); |
650 | /* store the status in the device context for someone | 676 | /* |
651 | to read */ | 677 | * store the status in the device context for someone |
678 | * to read | ||
679 | */ | ||
652 | denali->irq_status |= irq_status; | 680 | denali->irq_status |= irq_status; |
653 | /* notify anyone who cares that it happened */ | 681 | /* notify anyone who cares that it happened */ |
654 | complete(&denali->complete); | 682 | complete(&denali->complete); |
@@ -663,9 +691,8 @@ static irqreturn_t denali_isr(int irq, void *dev_id) | |||
663 | 691 | ||
664 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | 692 | static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) |
665 | { | 693 | { |
666 | unsigned long comp_res = 0; | 694 | unsigned long comp_res; |
667 | uint32_t intr_status = 0; | 695 | uint32_t intr_status; |
668 | bool retry = false; | ||
669 | unsigned long timeout = msecs_to_jiffies(1000); | 696 | unsigned long timeout = msecs_to_jiffies(1000); |
670 | 697 | ||
671 | do { | 698 | do { |
@@ -679,12 +706,13 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |||
679 | spin_unlock_irq(&denali->irq_lock); | 706 | spin_unlock_irq(&denali->irq_lock); |
680 | /* our interrupt was detected */ | 707 | /* our interrupt was detected */ |
681 | break; | 708 | break; |
682 | } else { | ||
683 | /* these are not the interrupts you are looking for - | ||
684 | * need to wait again */ | ||
685 | spin_unlock_irq(&denali->irq_lock); | ||
686 | retry = true; | ||
687 | } | 709 | } |
710 | |||
711 | /* | ||
712 | * these are not the interrupts you are looking for - | ||
713 | * need to wait again | ||
714 | */ | ||
715 | spin_unlock_irq(&denali->irq_lock); | ||
688 | } while (comp_res != 0); | 716 | } while (comp_res != 0); |
689 | 717 | ||
690 | if (comp_res == 0) { | 718 | if (comp_res == 0) { |
@@ -697,12 +725,14 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask) | |||
697 | return intr_status; | 725 | return intr_status; |
698 | } | 726 | } |
699 | 727 | ||
700 | /* This helper function setups the registers for ECC and whether or not | 728 | /* |
701 | * the spare area will be transferred. */ | 729 | * This helper function setups the registers for ECC and whether or not |
730 | * the spare area will be transferred. | ||
731 | */ | ||
702 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, | 732 | static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, |
703 | bool transfer_spare) | 733 | bool transfer_spare) |
704 | { | 734 | { |
705 | int ecc_en_flag = 0, transfer_spare_flag = 0; | 735 | int ecc_en_flag, transfer_spare_flag; |
706 | 736 | ||
707 | /* set ECC, transfer spare bits if needed */ | 737 | /* set ECC, transfer spare bits if needed */ |
708 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; | 738 | ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0; |
@@ -710,22 +740,20 @@ static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en, | |||
710 | 740 | ||
711 | /* Enable spare area/ECC per user's request. */ | 741 | /* Enable spare area/ECC per user's request. */ |
712 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); | 742 | iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); |
713 | iowrite32(transfer_spare_flag, | 743 | iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); |
714 | denali->flash_reg + TRANSFER_SPARE_REG); | ||
715 | } | 744 | } |
716 | 745 | ||
717 | /* sends a pipeline command operation to the controller. See the Denali NAND | 746 | /* |
747 | * sends a pipeline command operation to the controller. See the Denali NAND | ||
718 | * controller's user guide for more information (section 4.2.3.6). | 748 | * controller's user guide for more information (section 4.2.3.6). |
719 | */ | 749 | */ |
720 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | 750 | static int denali_send_pipeline_cmd(struct denali_nand_info *denali, |
721 | bool ecc_en, | 751 | bool ecc_en, bool transfer_spare, |
722 | bool transfer_spare, | 752 | int access_type, int op) |
723 | int access_type, | ||
724 | int op) | ||
725 | { | 753 | { |
726 | int status = PASS; | 754 | int status = PASS; |
727 | uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, | 755 | uint32_t page_count = 1; |
728 | irq_mask = 0; | 756 | uint32_t addr, cmd, irq_status, irq_mask; |
729 | 757 | ||
730 | if (op == DENALI_READ) | 758 | if (op == DENALI_READ) |
731 | irq_mask = INTR_STATUS__LOAD_COMP; | 759 | irq_mask = INTR_STATUS__LOAD_COMP; |
@@ -736,7 +764,6 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |||
736 | 764 | ||
737 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | 765 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); |
738 | 766 | ||
739 | /* clear interrupts */ | ||
740 | clear_interrupts(denali); | 767 | clear_interrupts(denali); |
741 | 768 | ||
742 | addr = BANK(denali->flash_bank) | denali->page; | 769 | addr = BANK(denali->flash_bank) | denali->page; |
@@ -747,37 +774,38 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |||
747 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { | 774 | } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { |
748 | /* read spare area */ | 775 | /* read spare area */ |
749 | cmd = MODE_10 | addr; | 776 | cmd = MODE_10 | addr; |
750 | index_addr(denali, (uint32_t)cmd, access_type); | 777 | index_addr(denali, cmd, access_type); |
751 | 778 | ||
752 | cmd = MODE_01 | addr; | 779 | cmd = MODE_01 | addr; |
753 | iowrite32(cmd, denali->flash_mem); | 780 | iowrite32(cmd, denali->flash_mem); |
754 | } else if (op == DENALI_READ) { | 781 | } else if (op == DENALI_READ) { |
755 | /* setup page read request for access type */ | 782 | /* setup page read request for access type */ |
756 | cmd = MODE_10 | addr; | 783 | cmd = MODE_10 | addr; |
757 | index_addr(denali, (uint32_t)cmd, access_type); | 784 | index_addr(denali, cmd, access_type); |
758 | 785 | ||
759 | /* page 33 of the NAND controller spec indicates we should not | 786 | /* |
760 | use the pipeline commands in Spare area only mode. So we | 787 | * page 33 of the NAND controller spec indicates we should not |
761 | don't. | 788 | * use the pipeline commands in Spare area only mode. |
789 | * So we don't. | ||
762 | */ | 790 | */ |
763 | if (access_type == SPARE_ACCESS) { | 791 | if (access_type == SPARE_ACCESS) { |
764 | cmd = MODE_01 | addr; | 792 | cmd = MODE_01 | addr; |
765 | iowrite32(cmd, denali->flash_mem); | 793 | iowrite32(cmd, denali->flash_mem); |
766 | } else { | 794 | } else { |
767 | index_addr(denali, (uint32_t)cmd, | 795 | index_addr(denali, cmd, |
768 | 0x2000 | op | page_count); | 796 | PIPELINE_ACCESS | op | page_count); |
769 | 797 | ||
770 | /* wait for command to be accepted | 798 | /* |
799 | * wait for command to be accepted | ||
771 | * can always use status0 bit as the | 800 | * can always use status0 bit as the |
772 | * mask is identical for each | 801 | * mask is identical for each bank. |
773 | * bank. */ | 802 | */ |
774 | irq_status = wait_for_irq(denali, irq_mask); | 803 | irq_status = wait_for_irq(denali, irq_mask); |
775 | 804 | ||
776 | if (irq_status == 0) { | 805 | if (irq_status == 0) { |
777 | dev_err(denali->dev, | 806 | dev_err(denali->dev, |
778 | "cmd, page, addr on timeout " | 807 | "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n", |
779 | "(0x%x, 0x%x, 0x%x)\n", | 808 | cmd, denali->page, addr); |
780 | cmd, denali->page, addr); | ||
781 | status = FAIL; | 809 | status = FAIL; |
782 | } else { | 810 | } else { |
783 | cmd = MODE_01 | addr; | 811 | cmd = MODE_01 | addr; |
@@ -790,51 +818,51 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |||
790 | 818 | ||
791 | /* helper function that simply writes a buffer to the flash */ | 819 | /* helper function that simply writes a buffer to the flash */ |
792 | static int write_data_to_flash_mem(struct denali_nand_info *denali, | 820 | static int write_data_to_flash_mem(struct denali_nand_info *denali, |
793 | const uint8_t *buf, | 821 | const uint8_t *buf, int len) |
794 | int len) | ||
795 | { | 822 | { |
796 | uint32_t i = 0, *buf32; | 823 | uint32_t *buf32; |
824 | int i; | ||
797 | 825 | ||
798 | /* verify that the len is a multiple of 4. see comment in | 826 | /* |
799 | * read_data_from_flash_mem() */ | 827 | * verify that the len is a multiple of 4. |
828 | * see comment in read_data_from_flash_mem() | ||
829 | */ | ||
800 | BUG_ON((len % 4) != 0); | 830 | BUG_ON((len % 4) != 0); |
801 | 831 | ||
802 | /* write the data to the flash memory */ | 832 | /* write the data to the flash memory */ |
803 | buf32 = (uint32_t *)buf; | 833 | buf32 = (uint32_t *)buf; |
804 | for (i = 0; i < len / 4; i++) | 834 | for (i = 0; i < len / 4; i++) |
805 | iowrite32(*buf32++, denali->flash_mem + 0x10); | 835 | iowrite32(*buf32++, denali->flash_mem + 0x10); |
806 | return i*4; /* intent is to return the number of bytes read */ | 836 | return i * 4; /* intent is to return the number of bytes read */ |
807 | } | 837 | } |
808 | 838 | ||
809 | /* helper function that simply reads a buffer from the flash */ | 839 | /* helper function that simply reads a buffer from the flash */ |
810 | static int read_data_from_flash_mem(struct denali_nand_info *denali, | 840 | static int read_data_from_flash_mem(struct denali_nand_info *denali, |
811 | uint8_t *buf, | 841 | uint8_t *buf, int len) |
812 | int len) | ||
813 | { | 842 | { |
814 | uint32_t i = 0, *buf32; | 843 | uint32_t *buf32; |
815 | 844 | int i; | |
816 | /* we assume that len will be a multiple of 4, if not | ||
817 | * it would be nice to know about it ASAP rather than | ||
818 | * have random failures... | ||
819 | * This assumption is based on the fact that this | ||
820 | * function is designed to be used to read flash pages, | ||
821 | * which are typically multiples of 4... | ||
822 | */ | ||
823 | 845 | ||
846 | /* | ||
847 | * we assume that len will be a multiple of 4, if not it would be nice | ||
848 | * to know about it ASAP rather than have random failures... | ||
849 | * This assumption is based on the fact that this function is designed | ||
850 | * to be used to read flash pages, which are typically multiples of 4. | ||
851 | */ | ||
824 | BUG_ON((len % 4) != 0); | 852 | BUG_ON((len % 4) != 0); |
825 | 853 | ||
826 | /* transfer the data from the flash */ | 854 | /* transfer the data from the flash */ |
827 | buf32 = (uint32_t *)buf; | 855 | buf32 = (uint32_t *)buf; |
828 | for (i = 0; i < len / 4; i++) | 856 | for (i = 0; i < len / 4; i++) |
829 | *buf32++ = ioread32(denali->flash_mem + 0x10); | 857 | *buf32++ = ioread32(denali->flash_mem + 0x10); |
830 | return i*4; /* intent is to return the number of bytes read */ | 858 | return i * 4; /* intent is to return the number of bytes read */ |
831 | } | 859 | } |
832 | 860 | ||
833 | /* writes OOB data to the device */ | 861 | /* writes OOB data to the device */ |
834 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | 862 | static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) |
835 | { | 863 | { |
836 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 864 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
837 | uint32_t irq_status = 0; | 865 | uint32_t irq_status; |
838 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | | 866 | uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | |
839 | INTR_STATUS__PROGRAM_FAIL; | 867 | INTR_STATUS__PROGRAM_FAIL; |
840 | int status = 0; | 868 | int status = 0; |
@@ -863,8 +891,8 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
863 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | 891 | static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) |
864 | { | 892 | { |
865 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 893 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
866 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP, | 894 | uint32_t irq_mask = INTR_STATUS__LOAD_COMP; |
867 | irq_status = 0, addr = 0x0, cmd = 0x0; | 895 | uint32_t irq_status, addr, cmd; |
868 | 896 | ||
869 | denali->page = page; | 897 | denali->page = page; |
870 | 898 | ||
@@ -872,16 +900,19 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
872 | DENALI_READ) == PASS) { | 900 | DENALI_READ) == PASS) { |
873 | read_data_from_flash_mem(denali, buf, mtd->oobsize); | 901 | read_data_from_flash_mem(denali, buf, mtd->oobsize); |
874 | 902 | ||
875 | /* wait for command to be accepted | 903 | /* |
876 | * can always use status0 bit as the mask is identical for each | 904 | * wait for command to be accepted |
877 | * bank. */ | 905 | * can always use status0 bit as the |
906 | * mask is identical for each bank. | ||
907 | */ | ||
878 | irq_status = wait_for_irq(denali, irq_mask); | 908 | irq_status = wait_for_irq(denali, irq_mask); |
879 | 909 | ||
880 | if (irq_status == 0) | 910 | if (irq_status == 0) |
881 | dev_err(denali->dev, "page on OOB timeout %d\n", | 911 | dev_err(denali->dev, "page on OOB timeout %d\n", |
882 | denali->page); | 912 | denali->page); |
883 | 913 | ||
884 | /* We set the device back to MAIN_ACCESS here as I observed | 914 | /* |
915 | * We set the device back to MAIN_ACCESS here as I observed | ||
885 | * instability with the controller if you do a block erase | 916 | * instability with the controller if you do a block erase |
886 | * and the last transaction was a SPARE_ACCESS. Block erase | 917 | * and the last transaction was a SPARE_ACCESS. Block erase |
887 | * is reliable (according to the MTD test infrastructure) | 918 | * is reliable (according to the MTD test infrastructure) |
@@ -889,16 +920,18 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) | |||
889 | */ | 920 | */ |
890 | addr = BANK(denali->flash_bank) | denali->page; | 921 | addr = BANK(denali->flash_bank) | denali->page; |
891 | cmd = MODE_10 | addr; | 922 | cmd = MODE_10 | addr; |
892 | index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); | 923 | index_addr(denali, cmd, MAIN_ACCESS); |
893 | } | 924 | } |
894 | } | 925 | } |
895 | 926 | ||
896 | /* this function examines buffers to see if they contain data that | 927 | /* |
928 | * this function examines buffers to see if they contain data that | ||
897 | * indicate that the buffer is part of an erased region of flash. | 929 | * indicate that the buffer is part of an erased region of flash. |
898 | */ | 930 | */ |
899 | static bool is_erased(uint8_t *buf, int len) | 931 | static bool is_erased(uint8_t *buf, int len) |
900 | { | 932 | { |
901 | int i = 0; | 933 | int i; |
934 | |||
902 | for (i = 0; i < len; i++) | 935 | for (i = 0; i < len; i++) |
903 | if (buf[i] != 0xFF) | 936 | if (buf[i] != 0xFF) |
904 | return false; | 937 | return false; |
@@ -921,9 +954,8 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, | |||
921 | 954 | ||
922 | if (irq_status & INTR_STATUS__ECC_ERR) { | 955 | if (irq_status & INTR_STATUS__ECC_ERR) { |
923 | /* read the ECC errors. we'll ignore them for now */ | 956 | /* read the ECC errors. we'll ignore them for now */ |
924 | uint32_t err_address = 0, err_correction_info = 0; | 957 | uint32_t err_address, err_correction_info, err_byte, |
925 | uint32_t err_byte = 0, err_sector = 0, err_device = 0; | 958 | err_sector, err_device, err_correction_value; |
926 | uint32_t err_correction_value = 0; | ||
927 | denali_set_intr_modes(denali, false); | 959 | denali_set_intr_modes(denali, false); |
928 | 960 | ||
929 | do { | 961 | do { |
@@ -939,15 +971,17 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, | |||
939 | err_device = ECC_ERR_DEVICE(err_correction_info); | 971 | err_device = ECC_ERR_DEVICE(err_correction_info); |
940 | 972 | ||
941 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { | 973 | if (ECC_ERROR_CORRECTABLE(err_correction_info)) { |
942 | /* If err_byte is larger than ECC_SECTOR_SIZE, | 974 | /* |
975 | * If err_byte is larger than ECC_SECTOR_SIZE, | ||
943 | * means error happened in OOB, so we ignore | 976 | * means error happened in OOB, so we ignore |
944 | * it. It's no need for us to correct it | 977 | * it. It's no need for us to correct it |
945 | * err_device is represented the NAND error | 978 | * err_device is represented the NAND error |
946 | * bits are happened in if there are more | 979 | * bits are happened in if there are more |
947 | * than one NAND connected. | 980 | * than one NAND connected. |
948 | * */ | 981 | */ |
949 | if (err_byte < ECC_SECTOR_SIZE) { | 982 | if (err_byte < ECC_SECTOR_SIZE) { |
950 | int offset; | 983 | int offset; |
984 | |||
951 | offset = (err_sector * | 985 | offset = (err_sector * |
952 | ECC_SECTOR_SIZE + | 986 | ECC_SECTOR_SIZE + |
953 | err_byte) * | 987 | err_byte) * |
@@ -959,17 +993,19 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, | |||
959 | bitflips++; | 993 | bitflips++; |
960 | } | 994 | } |
961 | } else { | 995 | } else { |
962 | /* if the error is not correctable, need to | 996 | /* |
997 | * if the error is not correctable, need to | ||
963 | * look at the page to see if it is an erased | 998 | * look at the page to see if it is an erased |
964 | * page. if so, then it's not a real ECC error | 999 | * page. if so, then it's not a real ECC error |
965 | * */ | 1000 | */ |
966 | check_erased_page = true; | 1001 | check_erased_page = true; |
967 | } | 1002 | } |
968 | } while (!ECC_LAST_ERR(err_correction_info)); | 1003 | } while (!ECC_LAST_ERR(err_correction_info)); |
969 | /* Once handle all ecc errors, controller will triger | 1004 | /* |
1005 | * Once handle all ecc errors, controller will triger | ||
970 | * a ECC_TRANSACTION_DONE interrupt, so here just wait | 1006 | * a ECC_TRANSACTION_DONE interrupt, so here just wait |
971 | * for a while for this interrupt | 1007 | * for a while for this interrupt |
972 | * */ | 1008 | */ |
973 | while (!(read_interrupt_status(denali) & | 1009 | while (!(read_interrupt_status(denali) & |
974 | INTR_STATUS__ECC_TRANSACTION_DONE)) | 1010 | INTR_STATUS__ECC_TRANSACTION_DONE)) |
975 | cpu_relax(); | 1011 | cpu_relax(); |
@@ -983,21 +1019,16 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf, | |||
983 | /* programs the controller to either enable/disable DMA transfers */ | 1019 | /* programs the controller to either enable/disable DMA transfers */ |
984 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) | 1020 | static void denali_enable_dma(struct denali_nand_info *denali, bool en) |
985 | { | 1021 | { |
986 | uint32_t reg_val = 0x0; | 1022 | iowrite32(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE); |
987 | |||
988 | if (en) | ||
989 | reg_val = DMA_ENABLE__FLAG; | ||
990 | |||
991 | iowrite32(reg_val, denali->flash_reg + DMA_ENABLE); | ||
992 | ioread32(denali->flash_reg + DMA_ENABLE); | 1023 | ioread32(denali->flash_reg + DMA_ENABLE); |
993 | } | 1024 | } |
994 | 1025 | ||
995 | /* setups the HW to perform the data DMA */ | 1026 | /* setups the HW to perform the data DMA */ |
996 | static void denali_setup_dma(struct denali_nand_info *denali, int op) | 1027 | static void denali_setup_dma(struct denali_nand_info *denali, int op) |
997 | { | 1028 | { |
998 | uint32_t mode = 0x0; | 1029 | uint32_t mode; |
999 | const int page_count = 1; | 1030 | const int page_count = 1; |
1000 | dma_addr_t addr = denali->buf.dma_buf; | 1031 | uint32_t addr = denali->buf.dma_buf; |
1001 | 1032 | ||
1002 | mode = MODE_10 | BANK(denali->flash_bank); | 1033 | mode = MODE_10 | BANK(denali->flash_bank); |
1003 | 1034 | ||
@@ -1007,31 +1038,31 @@ static void denali_setup_dma(struct denali_nand_info *denali, int op) | |||
1007 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); | 1038 | index_addr(denali, mode | denali->page, 0x2000 | op | page_count); |
1008 | 1039 | ||
1009 | /* 2. set memory high address bits 23:8 */ | 1040 | /* 2. set memory high address bits 23:8 */ |
1010 | index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200); | 1041 | index_addr(denali, mode | ((addr >> 16) << 8), 0x2200); |
1011 | 1042 | ||
1012 | /* 3. set memory low address bits 23:8 */ | 1043 | /* 3. set memory low address bits 23:8 */ |
1013 | index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300); | 1044 | index_addr(denali, mode | ((addr & 0xff) << 8), 0x2300); |
1014 | 1045 | ||
1015 | /* 4. interrupt when complete, burst len = 64 bytes*/ | 1046 | /* 4. interrupt when complete, burst len = 64 bytes */ |
1016 | index_addr(denali, mode | 0x14000, 0x2400); | 1047 | index_addr(denali, mode | 0x14000, 0x2400); |
1017 | } | 1048 | } |
1018 | 1049 | ||
1019 | /* writes a page. user specifies type, and this function handles the | 1050 | /* |
1020 | * configuration details. */ | 1051 | * writes a page. user specifies type, and this function handles the |
1052 | * configuration details. | ||
1053 | */ | ||
1021 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, | 1054 | static int write_page(struct mtd_info *mtd, struct nand_chip *chip, |
1022 | const uint8_t *buf, bool raw_xfer) | 1055 | const uint8_t *buf, bool raw_xfer) |
1023 | { | 1056 | { |
1024 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1057 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1025 | |||
1026 | dma_addr_t addr = denali->buf.dma_buf; | 1058 | dma_addr_t addr = denali->buf.dma_buf; |
1027 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | 1059 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
1028 | 1060 | uint32_t irq_status; | |
1029 | uint32_t irq_status = 0; | ||
1030 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | | 1061 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP | |
1031 | INTR_STATUS__PROGRAM_FAIL; | 1062 | INTR_STATUS__PROGRAM_FAIL; |
1032 | 1063 | ||
1033 | /* if it is a raw xfer, we want to disable ecc, and send | 1064 | /* |
1034 | * the spare area. | 1065 | * if it is a raw xfer, we want to disable ecc and send the spare area. |
1035 | * !raw_xfer - enable ecc | 1066 | * !raw_xfer - enable ecc |
1036 | * raw_xfer - transfer spare | 1067 | * raw_xfer - transfer spare |
1037 | */ | 1068 | */ |
@@ -1058,12 +1089,9 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1058 | irq_status = wait_for_irq(denali, irq_mask); | 1089 | irq_status = wait_for_irq(denali, irq_mask); |
1059 | 1090 | ||
1060 | if (irq_status == 0) { | 1091 | if (irq_status == 0) { |
1061 | dev_err(denali->dev, | 1092 | dev_err(denali->dev, "timeout on write_page (type = %d)\n", |
1062 | "timeout on write_page (type = %d)\n", | 1093 | raw_xfer); |
1063 | raw_xfer); | 1094 | denali->status = NAND_STATUS_FAIL; |
1064 | denali->status = | ||
1065 | (irq_status & INTR_STATUS__PROGRAM_FAIL) ? | ||
1066 | NAND_STATUS_FAIL : PASS; | ||
1067 | } | 1095 | } |
1068 | 1096 | ||
1069 | denali_enable_dma(denali, false); | 1097 | denali_enable_dma(denali, false); |
@@ -1074,27 +1102,33 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1074 | 1102 | ||
1075 | /* NAND core entry points */ | 1103 | /* NAND core entry points */ |
1076 | 1104 | ||
1077 | /* this is the callback that the NAND core calls to write a page. Since | 1105 | /* |
1106 | * this is the callback that the NAND core calls to write a page. Since | ||
1078 | * writing a page with ECC or without is similar, all the work is done | 1107 | * writing a page with ECC or without is similar, all the work is done |
1079 | * by write_page above. | 1108 | * by write_page above. |
1080 | * */ | 1109 | */ |
1081 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, | 1110 | static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, |
1082 | const uint8_t *buf, int oob_required) | 1111 | const uint8_t *buf, int oob_required) |
1083 | { | 1112 | { |
1084 | /* for regular page writes, we let HW handle all the ECC | 1113 | /* |
1085 | * data written to the device. */ | 1114 | * for regular page writes, we let HW handle all the ECC |
1115 | * data written to the device. | ||
1116 | */ | ||
1086 | return write_page(mtd, chip, buf, false); | 1117 | return write_page(mtd, chip, buf, false); |
1087 | } | 1118 | } |
1088 | 1119 | ||
1089 | /* This is the callback that the NAND core calls to write a page without ECC. | 1120 | /* |
1121 | * This is the callback that the NAND core calls to write a page without ECC. | ||
1090 | * raw access is similar to ECC page writes, so all the work is done in the | 1122 | * raw access is similar to ECC page writes, so all the work is done in the |
1091 | * write_page() function above. | 1123 | * write_page() function above. |
1092 | */ | 1124 | */ |
1093 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | 1125 | static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1094 | const uint8_t *buf, int oob_required) | 1126 | const uint8_t *buf, int oob_required) |
1095 | { | 1127 | { |
1096 | /* for raw page writes, we want to disable ECC and simply write | 1128 | /* |
1097 | whatever data is in the buffer. */ | 1129 | * for raw page writes, we want to disable ECC and simply write |
1130 | * whatever data is in the buffer. | ||
1131 | */ | ||
1098 | return write_page(mtd, chip, buf, true); | 1132 | return write_page(mtd, chip, buf, true); |
1099 | } | 1133 | } |
1100 | 1134 | ||
@@ -1121,15 +1155,15 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |||
1121 | dma_addr_t addr = denali->buf.dma_buf; | 1155 | dma_addr_t addr = denali->buf.dma_buf; |
1122 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | 1156 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
1123 | 1157 | ||
1124 | uint32_t irq_status = 0; | 1158 | uint32_t irq_status; |
1125 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | | 1159 | uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE | |
1126 | INTR_STATUS__ECC_ERR; | 1160 | INTR_STATUS__ECC_ERR; |
1127 | bool check_erased_page = false; | 1161 | bool check_erased_page = false; |
1128 | 1162 | ||
1129 | if (page != denali->page) { | 1163 | if (page != denali->page) { |
1130 | dev_err(denali->dev, "IN %s: page %d is not" | 1164 | dev_err(denali->dev, |
1131 | " equal to denali->page %d, investigate!!", | 1165 | "IN %s: page %d is not equal to denali->page %d", |
1132 | __func__, page, denali->page); | 1166 | __func__, page, denali->page); |
1133 | BUG(); | 1167 | BUG(); |
1134 | } | 1168 | } |
1135 | 1169 | ||
@@ -1169,17 +1203,14 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |||
1169 | uint8_t *buf, int oob_required, int page) | 1203 | uint8_t *buf, int oob_required, int page) |
1170 | { | 1204 | { |
1171 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1205 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1172 | |||
1173 | dma_addr_t addr = denali->buf.dma_buf; | 1206 | dma_addr_t addr = denali->buf.dma_buf; |
1174 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; | 1207 | size_t size = denali->mtd.writesize + denali->mtd.oobsize; |
1175 | |||
1176 | uint32_t irq_status = 0; | ||
1177 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; | 1208 | uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP; |
1178 | 1209 | ||
1179 | if (page != denali->page) { | 1210 | if (page != denali->page) { |
1180 | dev_err(denali->dev, "IN %s: page %d is not" | 1211 | dev_err(denali->dev, |
1181 | " equal to denali->page %d, investigate!!", | 1212 | "IN %s: page %d is not equal to denali->page %d", |
1182 | __func__, page, denali->page); | 1213 | __func__, page, denali->page); |
1183 | BUG(); | 1214 | BUG(); |
1184 | } | 1215 | } |
1185 | 1216 | ||
@@ -1192,7 +1223,7 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |||
1192 | denali_setup_dma(denali, DENALI_READ); | 1223 | denali_setup_dma(denali, DENALI_READ); |
1193 | 1224 | ||
1194 | /* wait for operation to complete */ | 1225 | /* wait for operation to complete */ |
1195 | irq_status = wait_for_irq(denali, irq_mask); | 1226 | wait_for_irq(denali, irq_mask); |
1196 | 1227 | ||
1197 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); | 1228 | dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE); |
1198 | 1229 | ||
@@ -1228,6 +1259,7 @@ static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) | |||
1228 | { | 1259 | { |
1229 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1260 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1230 | int status = denali->status; | 1261 | int status = denali->status; |
1262 | |||
1231 | denali->status = 0; | 1263 | denali->status = 0; |
1232 | 1264 | ||
1233 | return status; | 1265 | return status; |
@@ -1237,20 +1269,19 @@ static int denali_erase(struct mtd_info *mtd, int page) | |||
1237 | { | 1269 | { |
1238 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1270 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1239 | 1271 | ||
1240 | uint32_t cmd = 0x0, irq_status = 0; | 1272 | uint32_t cmd, irq_status; |
1241 | 1273 | ||
1242 | /* clear interrupts */ | ||
1243 | clear_interrupts(denali); | 1274 | clear_interrupts(denali); |
1244 | 1275 | ||
1245 | /* setup page read request for access type */ | 1276 | /* setup page read request for access type */ |
1246 | cmd = MODE_10 | BANK(denali->flash_bank) | page; | 1277 | cmd = MODE_10 | BANK(denali->flash_bank) | page; |
1247 | index_addr(denali, (uint32_t)cmd, 0x1); | 1278 | index_addr(denali, cmd, 0x1); |
1248 | 1279 | ||
1249 | /* wait for erase to complete or failure to occur */ | 1280 | /* wait for erase to complete or failure to occur */ |
1250 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | | 1281 | irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | |
1251 | INTR_STATUS__ERASE_FAIL); | 1282 | INTR_STATUS__ERASE_FAIL); |
1252 | 1283 | ||
1253 | return (irq_status & INTR_STATUS__ERASE_FAIL) ? NAND_STATUS_FAIL : PASS; | 1284 | return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; |
1254 | } | 1285 | } |
1255 | 1286 | ||
1256 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, | 1287 | static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, |
@@ -1269,17 +1300,16 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, | |||
1269 | case NAND_CMD_READID: | 1300 | case NAND_CMD_READID: |
1270 | case NAND_CMD_PARAM: | 1301 | case NAND_CMD_PARAM: |
1271 | reset_buf(denali); | 1302 | reset_buf(denali); |
1272 | /*sometimes ManufactureId read from register is not right | 1303 | /* |
1304 | * sometimes ManufactureId read from register is not right | ||
1273 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips | 1305 | * e.g. some of Micron MT29F32G08QAA MLC NAND chips |
1274 | * So here we send READID cmd to NAND insteand | 1306 | * So here we send READID cmd to NAND insteand |
1275 | * */ | 1307 | */ |
1276 | addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); | 1308 | addr = MODE_11 | BANK(denali->flash_bank); |
1277 | index_addr(denali, (uint32_t)addr | 0, 0x90); | 1309 | index_addr(denali, addr | 0, 0x90); |
1278 | index_addr(denali, (uint32_t)addr | 1, 0); | 1310 | index_addr(denali, addr | 1, 0); |
1279 | for (i = 0; i < 8; i++) { | 1311 | for (i = 0; i < 8; i++) { |
1280 | index_addr_read_data(denali, | 1312 | index_addr_read_data(denali, addr | 2, &id); |
1281 | (uint32_t)addr | 2, | ||
1282 | &id); | ||
1283 | write_byte_to_buf(denali, id); | 1313 | write_byte_to_buf(denali, id); |
1284 | } | 1314 | } |
1285 | break; | 1315 | break; |
@@ -1304,8 +1334,8 @@ static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data, | |||
1304 | uint8_t *ecc_code) | 1334 | uint8_t *ecc_code) |
1305 | { | 1335 | { |
1306 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1336 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1307 | dev_err(denali->dev, | 1337 | |
1308 | "denali_ecc_calculate called unexpectedly\n"); | 1338 | dev_err(denali->dev, "denali_ecc_calculate called unexpectedly\n"); |
1309 | BUG(); | 1339 | BUG(); |
1310 | return -EIO; | 1340 | return -EIO; |
1311 | } | 1341 | } |
@@ -1314,8 +1344,8 @@ static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, | |||
1314 | uint8_t *read_ecc, uint8_t *calc_ecc) | 1344 | uint8_t *read_ecc, uint8_t *calc_ecc) |
1315 | { | 1345 | { |
1316 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1346 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1317 | dev_err(denali->dev, | 1347 | |
1318 | "denali_ecc_correct called unexpectedly\n"); | 1348 | dev_err(denali->dev, "denali_ecc_correct called unexpectedly\n"); |
1319 | BUG(); | 1349 | BUG(); |
1320 | return -EIO; | 1350 | return -EIO; |
1321 | } | 1351 | } |
@@ -1323,8 +1353,8 @@ static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data, | |||
1323 | static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) | 1353 | static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) |
1324 | { | 1354 | { |
1325 | struct denali_nand_info *denali = mtd_to_denali(mtd); | 1355 | struct denali_nand_info *denali = mtd_to_denali(mtd); |
1326 | dev_err(denali->dev, | 1356 | |
1327 | "denali_ecc_hwctl called unexpectedly\n"); | 1357 | dev_err(denali->dev, "denali_ecc_hwctl called unexpectedly\n"); |
1328 | BUG(); | 1358 | BUG(); |
1329 | } | 1359 | } |
1330 | /* end NAND core entry points */ | 1360 | /* end NAND core entry points */ |
@@ -1332,11 +1362,12 @@ static void denali_ecc_hwctl(struct mtd_info *mtd, int mode) | |||
1332 | /* Initialization code to bring the device up to a known good state */ | 1362 | /* Initialization code to bring the device up to a known good state */ |
1333 | static void denali_hw_init(struct denali_nand_info *denali) | 1363 | static void denali_hw_init(struct denali_nand_info *denali) |
1334 | { | 1364 | { |
1335 | /* tell driver how many bit controller will skip before | 1365 | /* |
1366 | * tell driver how many bit controller will skip before | ||
1336 | * writing ECC code in OOB, this register may be already | 1367 | * writing ECC code in OOB, this register may be already |
1337 | * set by firmware. So we read this value out. | 1368 | * set by firmware. So we read this value out. |
1338 | * if this value is 0, just let it be. | 1369 | * if this value is 0, just let it be. |
1339 | * */ | 1370 | */ |
1340 | denali->bbtskipbytes = ioread32(denali->flash_reg + | 1371 | denali->bbtskipbytes = ioread32(denali->flash_reg + |
1341 | SPARE_AREA_SKIP_BYTES); | 1372 | SPARE_AREA_SKIP_BYTES); |
1342 | detect_max_banks(denali); | 1373 | detect_max_banks(denali); |
@@ -1354,10 +1385,11 @@ static void denali_hw_init(struct denali_nand_info *denali) | |||
1354 | denali_irq_init(denali); | 1385 | denali_irq_init(denali); |
1355 | } | 1386 | } |
1356 | 1387 | ||
1357 | /* Althogh controller spec said SLC ECC is forceb to be 4bit, | 1388 | /* |
1389 | * Althogh controller spec said SLC ECC is forceb to be 4bit, | ||
1358 | * but denali controller in MRST only support 15bit and 8bit ECC | 1390 | * but denali controller in MRST only support 15bit and 8bit ECC |
1359 | * correction | 1391 | * correction |
1360 | * */ | 1392 | */ |
1361 | #define ECC_8BITS 14 | 1393 | #define ECC_8BITS 14 |
1362 | static struct nand_ecclayout nand_8bit_oob = { | 1394 | static struct nand_ecclayout nand_8bit_oob = { |
1363 | .eccbytes = 14, | 1395 | .eccbytes = 14, |
@@ -1397,13 +1429,16 @@ static void denali_drv_init(struct denali_nand_info *denali) | |||
1397 | denali->idx = 0; | 1429 | denali->idx = 0; |
1398 | 1430 | ||
1399 | /* setup interrupt handler */ | 1431 | /* setup interrupt handler */ |
1400 | /* the completion object will be used to notify | 1432 | /* |
1401 | * the callee that the interrupt is done */ | 1433 | * the completion object will be used to notify |
1434 | * the callee that the interrupt is done | ||
1435 | */ | ||
1402 | init_completion(&denali->complete); | 1436 | init_completion(&denali->complete); |
1403 | 1437 | ||
1404 | /* the spinlock will be used to synchronize the ISR | 1438 | /* |
1405 | * with any element that might be access shared | 1439 | * the spinlock will be used to synchronize the ISR with any |
1406 | * data (interrupt status) */ | 1440 | * element that might be access shared data (interrupt status) |
1441 | */ | ||
1407 | spin_lock_init(&denali->irq_lock); | 1442 | spin_lock_init(&denali->irq_lock); |
1408 | 1443 | ||
1409 | /* indicate that MTD has not selected a valid bank yet */ | 1444 | /* indicate that MTD has not selected a valid bank yet */ |
@@ -1418,7 +1453,8 @@ int denali_init(struct denali_nand_info *denali) | |||
1418 | int ret; | 1453 | int ret; |
1419 | 1454 | ||
1420 | if (denali->platform == INTEL_CE4100) { | 1455 | if (denali->platform == INTEL_CE4100) { |
1421 | /* Due to a silicon limitation, we can only support | 1456 | /* |
1457 | * Due to a silicon limitation, we can only support | ||
1422 | * ONFI timing mode 1 and below. | 1458 | * ONFI timing mode 1 and below. |
1423 | */ | 1459 | */ |
1424 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { | 1460 | if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { |
@@ -1437,8 +1473,10 @@ int denali_init(struct denali_nand_info *denali) | |||
1437 | denali_hw_init(denali); | 1473 | denali_hw_init(denali); |
1438 | denali_drv_init(denali); | 1474 | denali_drv_init(denali); |
1439 | 1475 | ||
1440 | /* denali_isr register is done after all the hardware | 1476 | /* |
1441 | * initilization is finished*/ | 1477 | * denali_isr register is done after all the hardware |
1478 | * initilization is finished | ||
1479 | */ | ||
1442 | if (request_irq(denali->irq, denali_isr, IRQF_SHARED, | 1480 | if (request_irq(denali->irq, denali_isr, IRQF_SHARED, |
1443 | DENALI_NAND_NAME, denali)) { | 1481 | DENALI_NAND_NAME, denali)) { |
1444 | pr_err("Spectra: Unable to allocate IRQ\n"); | 1482 | pr_err("Spectra: Unable to allocate IRQ\n"); |
@@ -1457,9 +1495,11 @@ int denali_init(struct denali_nand_info *denali) | |||
1457 | denali->nand.read_byte = denali_read_byte; | 1495 | denali->nand.read_byte = denali_read_byte; |
1458 | denali->nand.waitfunc = denali_waitfunc; | 1496 | denali->nand.waitfunc = denali_waitfunc; |
1459 | 1497 | ||
1460 | /* scan for NAND devices attached to the controller | 1498 | /* |
1499 | * scan for NAND devices attached to the controller | ||
1461 | * this is the first stage in a two step process to register | 1500 | * this is the first stage in a two step process to register |
1462 | * with the nand subsystem */ | 1501 | * with the nand subsystem |
1502 | */ | ||
1463 | if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) { | 1503 | if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) { |
1464 | ret = -ENXIO; | 1504 | ret = -ENXIO; |
1465 | goto failed_req_irq; | 1505 | goto failed_req_irq; |
@@ -1491,10 +1531,10 @@ int denali_init(struct denali_nand_info *denali) | |||
1491 | goto failed_req_irq; | 1531 | goto failed_req_irq; |
1492 | } | 1532 | } |
1493 | 1533 | ||
1494 | /* support for multi nand | 1534 | /* |
1495 | * MTD known nothing about multi nand, | 1535 | * support for multi nand |
1496 | * so we should tell it the real pagesize | 1536 | * MTD known nothing about multi nand, so we should tell it |
1497 | * and anything necessery | 1537 | * the real pagesize and anything necessery |
1498 | */ | 1538 | */ |
1499 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); | 1539 | denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); |
1500 | denali->nand.chipsize <<= (denali->devnum - 1); | 1540 | denali->nand.chipsize <<= (denali->devnum - 1); |
@@ -1510,9 +1550,11 @@ int denali_init(struct denali_nand_info *denali) | |||
1510 | denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; | 1550 | denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; |
1511 | denali->bbtskipbytes *= denali->devnum; | 1551 | denali->bbtskipbytes *= denali->devnum; |
1512 | 1552 | ||
1513 | /* second stage of the NAND scan | 1553 | /* |
1554 | * second stage of the NAND scan | ||
1514 | * this stage requires information regarding ECC and | 1555 | * this stage requires information regarding ECC and |
1515 | * bad block management. */ | 1556 | * bad block management. |
1557 | */ | ||
1516 | 1558 | ||
1517 | /* Bad block management */ | 1559 | /* Bad block management */ |
1518 | denali->nand.bbt_td = &bbt_main_descr; | 1560 | denali->nand.bbt_td = &bbt_main_descr; |
@@ -1523,7 +1565,8 @@ int denali_init(struct denali_nand_info *denali) | |||
1523 | denali->nand.options |= NAND_SKIP_BBTSCAN; | 1565 | denali->nand.options |= NAND_SKIP_BBTSCAN; |
1524 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; | 1566 | denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
1525 | 1567 | ||
1526 | /* Denali Controller only support 15bit and 8bit ECC in MRST, | 1568 | /* |
1569 | * Denali Controller only support 15bit and 8bit ECC in MRST, | ||
1527 | * so just let controller do 15bit ECC for MLC and 8bit ECC for | 1570 | * so just let controller do 15bit ECC for MLC and 8bit ECC for |
1528 | * SLC if possible. | 1571 | * SLC if possible. |
1529 | * */ | 1572 | * */ |
@@ -1539,8 +1582,7 @@ int denali_init(struct denali_nand_info *denali) | |||
1539 | } else if (denali->mtd.oobsize < (denali->bbtskipbytes + | 1582 | } else if (denali->mtd.oobsize < (denali->bbtskipbytes + |
1540 | ECC_8BITS * (denali->mtd.writesize / | 1583 | ECC_8BITS * (denali->mtd.writesize / |
1541 | ECC_SECTOR_SIZE))) { | 1584 | ECC_SECTOR_SIZE))) { |
1542 | pr_err("Your NAND chip OOB is not large enough to \ | 1585 | pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); |
1543 | contain 8bit ECC correction codes"); | ||
1544 | goto failed_req_irq; | 1586 | goto failed_req_irq; |
1545 | } else { | 1587 | } else { |
1546 | denali->nand.ecc.strength = 8; | 1588 | denali->nand.ecc.strength = 8; |
@@ -1559,18 +1601,19 @@ int denali_init(struct denali_nand_info *denali) | |||
1559 | denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - | 1601 | denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - |
1560 | denali->bbtskipbytes; | 1602 | denali->bbtskipbytes; |
1561 | 1603 | ||
1562 | /* Let driver know the total blocks number and | 1604 | /* |
1563 | * how many blocks contained by each nand chip. | 1605 | * Let driver know the total blocks number and how many blocks |
1564 | * blksperchip will help driver to know how many | 1606 | * contained by each nand chip. blksperchip will help driver to |
1565 | * blocks is taken by FW. | 1607 | * know how many blocks is taken by FW. |
1566 | * */ | 1608 | */ |
1567 | denali->totalblks = denali->mtd.size >> | 1609 | denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift; |
1568 | denali->nand.phys_erase_shift; | ||
1569 | denali->blksperchip = denali->totalblks / denali->nand.numchips; | 1610 | denali->blksperchip = denali->totalblks / denali->nand.numchips; |
1570 | 1611 | ||
1571 | /* These functions are required by the NAND core framework, otherwise, | 1612 | /* |
1613 | * These functions are required by the NAND core framework, otherwise, | ||
1572 | * the NAND core will assert. However, we don't need them, so we'll stub | 1614 | * the NAND core will assert. However, we don't need them, so we'll stub |
1573 | * them out. */ | 1615 | * them out. |
1616 | */ | ||
1574 | denali->nand.ecc.calculate = denali_ecc_calculate; | 1617 | denali->nand.ecc.calculate = denali_ecc_calculate; |
1575 | denali->nand.ecc.correct = denali_ecc_correct; | 1618 | denali->nand.ecc.correct = denali_ecc_correct; |
1576 | denali->nand.ecc.hwctl = denali_ecc_hwctl; | 1619 | denali->nand.ecc.hwctl = denali_ecc_hwctl; |
@@ -1610,7 +1653,7 @@ void denali_remove(struct denali_nand_info *denali) | |||
1610 | { | 1653 | { |
1611 | denali_irq_cleanup(denali->irq, denali); | 1654 | denali_irq_cleanup(denali->irq, denali); |
1612 | dma_unmap_single(denali->dev, denali->buf.dma_buf, | 1655 | dma_unmap_single(denali->dev, denali->buf.dma_buf, |
1613 | denali->mtd.writesize + denali->mtd.oobsize, | 1656 | denali->mtd.writesize + denali->mtd.oobsize, |
1614 | DMA_BIDIRECTIONAL); | 1657 | DMA_BIDIRECTIONAL); |
1615 | } | 1658 | } |
1616 | EXPORT_SYMBOL(denali_remove); | 1659 | EXPORT_SYMBOL(denali_remove); |
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 966817462421..145bf88930e8 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h | |||
@@ -17,6 +17,9 @@ | |||
17 | * | 17 | * |
18 | */ | 18 | */ |
19 | 19 | ||
20 | #ifndef __DENALI_H__ | ||
21 | #define __DENALI_H__ | ||
22 | |||
20 | #include <linux/mtd/nand.h> | 23 | #include <linux/mtd/nand.h> |
21 | 24 | ||
22 | #define DEVICE_RESET 0x0 | 25 | #define DEVICE_RESET 0x0 |
@@ -400,28 +403,6 @@ | |||
400 | #define ONFI_BLOOM_TIME 1 | 403 | #define ONFI_BLOOM_TIME 1 |
401 | #define MODE5_WORKAROUND 0 | 404 | #define MODE5_WORKAROUND 0 |
402 | 405 | ||
403 | /* lld_nand.h */ | ||
404 | /* | ||
405 | * NAND Flash Controller Device Driver | ||
406 | * Copyright (c) 2009, Intel Corporation and its suppliers. | ||
407 | * | ||
408 | * This program is free software; you can redistribute it and/or modify it | ||
409 | * under the terms and conditions of the GNU General Public License, | ||
410 | * version 2, as published by the Free Software Foundation. | ||
411 | * | ||
412 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
413 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
414 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
415 | * more details. | ||
416 | * | ||
417 | * You should have received a copy of the GNU General Public License along with | ||
418 | * this program; if not, write to the Free Software Foundation, Inc., | ||
419 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
420 | * | ||
421 | */ | ||
422 | |||
423 | #ifndef _LLD_NAND_ | ||
424 | #define _LLD_NAND_ | ||
425 | 406 | ||
426 | #define MODE_00 0x00000000 | 407 | #define MODE_00 0x00000000 |
427 | #define MODE_01 0x04000000 | 408 | #define MODE_01 0x04000000 |
@@ -499,4 +480,4 @@ struct denali_nand_info { | |||
499 | extern int denali_init(struct denali_nand_info *denali); | 480 | extern int denali_init(struct denali_nand_info *denali); |
500 | extern void denali_remove(struct denali_nand_info *denali); | 481 | extern void denali_remove(struct denali_nand_info *denali); |
501 | 482 | ||
502 | #endif /*_LLD_NAND_*/ | 483 | #endif /* __DENALI_H__ */ |
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index d8cdf06343fb..5b5c62712814 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c | |||
@@ -982,6 +982,15 @@ int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |||
982 | 982 | ||
983 | chip->select_chip(mtd, chipnr); | 983 | chip->select_chip(mtd, chipnr); |
984 | 984 | ||
985 | /* | ||
986 | * Reset the chip. | ||
987 | * If we want to check the WP through READ STATUS and check the bit 7 | ||
988 | * we must reset the chip | ||
989 | * some operation can also clear the bit 7 of status register | ||
990 | * eg. erase/program a locked block | ||
991 | */ | ||
992 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | ||
993 | |||
985 | /* Check, if it is write protected */ | 994 | /* Check, if it is write protected */ |
986 | if (nand_check_wp(mtd)) { | 995 | if (nand_check_wp(mtd)) { |
987 | pr_debug("%s: device is write protected!\n", | 996 | pr_debug("%s: device is write protected!\n", |
@@ -1032,6 +1041,15 @@ int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |||
1032 | 1041 | ||
1033 | chip->select_chip(mtd, chipnr); | 1042 | chip->select_chip(mtd, chipnr); |
1034 | 1043 | ||
1044 | /* | ||
1045 | * Reset the chip. | ||
1046 | * If we want to check the WP through READ STATUS and check the bit 7 | ||
1047 | * we must reset the chip | ||
1048 | * some operation can also clear the bit 7 of status register | ||
1049 | * eg. erase/program a locked block | ||
1050 | */ | ||
1051 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | ||
1052 | |||
1035 | /* Check, if it is write protected */ | 1053 | /* Check, if it is write protected */ |
1036 | if (nand_check_wp(mtd)) { | 1054 | if (nand_check_wp(mtd)) { |
1037 | pr_debug("%s: device is write protected!\n", | 1055 | pr_debug("%s: device is write protected!\n", |
@@ -2391,8 +2409,8 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, | |||
2391 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | 2409 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
2392 | 2410 | ||
2393 | /* Invalidate the page cache, when we write to the cached page */ | 2411 | /* Invalidate the page cache, when we write to the cached page */ |
2394 | if (to <= (chip->pagebuf << chip->page_shift) && | 2412 | if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && |
2395 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) | 2413 | ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) |
2396 | chip->pagebuf = -1; | 2414 | chip->pagebuf = -1; |
2397 | 2415 | ||
2398 | /* Don't allow multipage oob writes with offset */ | 2416 | /* Don't allow multipage oob writes with offset */ |
@@ -3576,6 +3594,8 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, | |||
3576 | chip->options |= type->options; | 3594 | chip->options |= type->options; |
3577 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); | 3595 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3578 | chip->ecc_step_ds = NAND_ECC_STEP(type); | 3596 | chip->ecc_step_ds = NAND_ECC_STEP(type); |
3597 | chip->onfi_timing_mode_default = | ||
3598 | type->onfi_timing_mode_default; | ||
3579 | 3599 | ||
3580 | *busw = type->options & NAND_BUSWIDTH_16; | 3600 | *busw = type->options & NAND_BUSWIDTH_16; |
3581 | 3601 | ||
@@ -3918,8 +3938,7 @@ int nand_scan_tail(struct mtd_info *mtd) | |||
3918 | case NAND_ECC_HW_OOB_FIRST: | 3938 | case NAND_ECC_HW_OOB_FIRST: |
3919 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | 3939 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ |
3920 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { | 3940 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
3921 | pr_warn("No ECC functions supplied; " | 3941 | pr_warn("No ECC functions supplied; hardware ECC not possible\n"); |
3922 | "hardware ECC not possible\n"); | ||
3923 | BUG(); | 3942 | BUG(); |
3924 | } | 3943 | } |
3925 | if (!ecc->read_page) | 3944 | if (!ecc->read_page) |
@@ -3950,8 +3969,7 @@ int nand_scan_tail(struct mtd_info *mtd) | |||
3950 | ecc->read_page == nand_read_page_hwecc || | 3969 | ecc->read_page == nand_read_page_hwecc || |
3951 | !ecc->write_page || | 3970 | !ecc->write_page || |
3952 | ecc->write_page == nand_write_page_hwecc)) { | 3971 | ecc->write_page == nand_write_page_hwecc)) { |
3953 | pr_warn("No ECC functions supplied; " | 3972 | pr_warn("No ECC functions supplied; hardware ECC not possible\n"); |
3954 | "hardware ECC not possible\n"); | ||
3955 | BUG(); | 3973 | BUG(); |
3956 | } | 3974 | } |
3957 | /* Use standard syndrome read/write page function? */ | 3975 | /* Use standard syndrome read/write page function? */ |
@@ -3975,9 +3993,8 @@ int nand_scan_tail(struct mtd_info *mtd) | |||
3975 | } | 3993 | } |
3976 | break; | 3994 | break; |
3977 | } | 3995 | } |
3978 | pr_warn("%d byte HW ECC not possible on " | 3996 | pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", |
3979 | "%d byte page size, fallback to SW ECC\n", | 3997 | ecc->size, mtd->writesize); |
3980 | ecc->size, mtd->writesize); | ||
3981 | ecc->mode = NAND_ECC_SOFT; | 3998 | ecc->mode = NAND_ECC_SOFT; |
3982 | 3999 | ||
3983 | case NAND_ECC_SOFT: | 4000 | case NAND_ECC_SOFT: |
@@ -4030,8 +4047,7 @@ int nand_scan_tail(struct mtd_info *mtd) | |||
4030 | break; | 4047 | break; |
4031 | 4048 | ||
4032 | case NAND_ECC_NONE: | 4049 | case NAND_ECC_NONE: |
4033 | pr_warn("NAND_ECC_NONE selected by board driver. " | 4050 | pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); |
4034 | "This is not recommended!\n"); | ||
4035 | ecc->read_page = nand_read_page_raw; | 4051 | ecc->read_page = nand_read_page_raw; |
4036 | ecc->write_page = nand_write_page_raw; | 4052 | ecc->write_page = nand_write_page_raw; |
4037 | ecc->read_oob = nand_read_oob_std; | 4053 | ecc->read_oob = nand_read_oob_std; |
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 443fa82cde6a..9bb8453d224e 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c | |||
@@ -201,12 +201,12 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, | |||
201 | res = mtd_read(mtd, from, len, &retlen, buf); | 201 | res = mtd_read(mtd, from, len, &retlen, buf); |
202 | if (res < 0) { | 202 | if (res < 0) { |
203 | if (mtd_is_eccerr(res)) { | 203 | if (mtd_is_eccerr(res)) { |
204 | pr_info("nand_bbt: ECC error in BBT at " | 204 | pr_info("nand_bbt: ECC error in BBT at 0x%012llx\n", |
205 | "0x%012llx\n", from & ~mtd->writesize); | 205 | from & ~mtd->writesize); |
206 | return res; | 206 | return res; |
207 | } else if (mtd_is_bitflip(res)) { | 207 | } else if (mtd_is_bitflip(res)) { |
208 | pr_info("nand_bbt: corrected error in BBT at " | 208 | pr_info("nand_bbt: corrected error in BBT at 0x%012llx\n", |
209 | "0x%012llx\n", from & ~mtd->writesize); | 209 | from & ~mtd->writesize); |
210 | ret = res; | 210 | ret = res; |
211 | } else { | 211 | } else { |
212 | pr_info("nand_bbt: error reading BBT\n"); | 212 | pr_info("nand_bbt: error reading BBT\n"); |
@@ -580,8 +580,8 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr | |||
580 | if (td->pages[i] == -1) | 580 | if (td->pages[i] == -1) |
581 | pr_warn("Bad block table not found for chip %d\n", i); | 581 | pr_warn("Bad block table not found for chip %d\n", i); |
582 | else | 582 | else |
583 | pr_info("Bad block table found at page %d, version " | 583 | pr_info("Bad block table found at page %d, version 0x%02X\n", |
584 | "0x%02X\n", td->pages[i], td->version[i]); | 584 | td->pages[i], td->version[i]); |
585 | } | 585 | } |
586 | return 0; | 586 | return 0; |
587 | } | 587 | } |
@@ -725,12 +725,10 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, | |||
725 | res = mtd_read(mtd, to, len, &retlen, buf); | 725 | res = mtd_read(mtd, to, len, &retlen, buf); |
726 | if (res < 0) { | 726 | if (res < 0) { |
727 | if (retlen != len) { | 727 | if (retlen != len) { |
728 | pr_info("nand_bbt: error reading block " | 728 | pr_info("nand_bbt: error reading block for writing the bad block table\n"); |
729 | "for writing the bad block table\n"); | ||
730 | return res; | 729 | return res; |
731 | } | 730 | } |
732 | pr_warn("nand_bbt: ECC error while reading " | 731 | pr_warn("nand_bbt: ECC error while reading block for writing bad block table\n"); |
733 | "block for writing bad block table\n"); | ||
734 | } | 732 | } |
735 | /* Read oob data */ | 733 | /* Read oob data */ |
736 | ops.ooblen = (len >> this->page_shift) * mtd->oobsize; | 734 | ops.ooblen = (len >> this->page_shift) * mtd->oobsize; |
@@ -1338,9 +1336,8 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) | |||
1338 | block = (int)(offs >> this->bbt_erase_shift); | 1336 | block = (int)(offs >> this->bbt_erase_shift); |
1339 | res = bbt_get_entry(this, block); | 1337 | res = bbt_get_entry(this, block); |
1340 | 1338 | ||
1341 | pr_debug("nand_isbad_bbt(): bbt info for offs 0x%08x: " | 1339 | pr_debug("nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n", |
1342 | "(block %d) 0x%02x\n", | 1340 | (unsigned int)offs, block, res); |
1343 | (unsigned int)offs, block, res); | ||
1344 | 1341 | ||
1345 | switch (res) { | 1342 | switch (res) { |
1346 | case BBT_BLOCK_GOOD: | 1343 | case BBT_BLOCK_GOOD: |
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 3d7c89fc1031..fbde89105245 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c | |||
@@ -46,6 +46,10 @@ struct nand_flash_dev nand_flash_ids[] = { | |||
46 | {"SDTNRGAMA 64G 3.3V 8-bit", | 46 | {"SDTNRGAMA 64G 3.3V 8-bit", |
47 | { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, | 47 | { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, |
48 | SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, | 48 | SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, |
49 | {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", | ||
50 | { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, | ||
51 | SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K), | ||
52 | 4 }, | ||
49 | 53 | ||
50 | LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), | 54 | LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), |
51 | LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), | 55 | LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), |
diff --git a/drivers/mtd/nand/nand_timings.c b/drivers/mtd/nand/nand_timings.c index 8b36253420fa..e81470a8ac67 100644 --- a/drivers/mtd/nand/nand_timings.c +++ b/drivers/mtd/nand/nand_timings.c | |||
@@ -42,7 +42,7 @@ static const struct nand_sdr_timings onfi_sdr_timings[] = { | |||
42 | .tRHZ_max = 200000, | 42 | .tRHZ_max = 200000, |
43 | .tRLOH_min = 0, | 43 | .tRLOH_min = 0, |
44 | .tRP_min = 50000, | 44 | .tRP_min = 50000, |
45 | .tRST_max = 250000000000, | 45 | .tRST_max = 250000000000ULL, |
46 | .tWB_max = 200000, | 46 | .tWB_max = 200000, |
47 | .tRR_min = 40000, | 47 | .tRR_min = 40000, |
48 | .tWC_min = 100000, | 48 | .tWC_min = 100000, |
diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c index 4f0d83648e5a..7dc1dd28d896 100644 --- a/drivers/mtd/nand/nandsim.c +++ b/drivers/mtd/nand/nandsim.c | |||
@@ -827,7 +827,7 @@ static int parse_badblocks(struct nandsim *ns, struct mtd_info *mtd) | |||
827 | NS_ERR("invalid badblocks.\n"); | 827 | NS_ERR("invalid badblocks.\n"); |
828 | return -EINVAL; | 828 | return -EINVAL; |
829 | } | 829 | } |
830 | offset = erase_block_no * ns->geom.secsz; | 830 | offset = (loff_t)erase_block_no * ns->geom.secsz; |
831 | if (mtd_block_markbad(mtd, offset)) { | 831 | if (mtd_block_markbad(mtd, offset)) { |
832 | NS_ERR("invalid badblocks.\n"); | 832 | NS_ERR("invalid badblocks.\n"); |
833 | return -EINVAL; | 833 | return -EINVAL; |
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 69eaba690a99..253a644da76a 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c | |||
@@ -203,7 +203,8 @@ static int ndfc_probe(struct platform_device *ofdev) | |||
203 | struct ndfc_controller *ndfc; | 203 | struct ndfc_controller *ndfc; |
204 | const __be32 *reg; | 204 | const __be32 *reg; |
205 | u32 ccr; | 205 | u32 ccr; |
206 | int err, len, cs; | 206 | u32 cs; |
207 | int err, len; | ||
207 | 208 | ||
208 | /* Read the reg property to get the chip select */ | 209 | /* Read the reg property to get the chip select */ |
209 | reg = of_get_property(ofdev->dev.of_node, "reg", &len); | 210 | reg = of_get_property(ofdev->dev.of_node, "reg", &len); |
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 5967b385141b..3b357e920a0c 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c | |||
@@ -136,7 +136,6 @@ | |||
136 | 136 | ||
137 | #define BADBLOCK_MARKER_LENGTH 2 | 137 | #define BADBLOCK_MARKER_LENGTH 2 |
138 | 138 | ||
139 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | ||
140 | static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55, | 139 | static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55, |
141 | 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78, | 140 | 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78, |
142 | 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93, | 141 | 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93, |
@@ -144,7 +143,6 @@ static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55, | |||
144 | static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc, | 143 | static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc, |
145 | 0xac, 0x6b, 0xff, 0x99, 0x7b}; | 144 | 0xac, 0x6b, 0xff, 0x99, 0x7b}; |
146 | static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10}; | 145 | static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10}; |
147 | #endif | ||
148 | 146 | ||
149 | /* oob info generated runtime depending on ecc algorithm and layout selected */ | 147 | /* oob info generated runtime depending on ecc algorithm and layout selected */ |
150 | static struct nand_ecclayout omap_oobinfo; | 148 | static struct nand_ecclayout omap_oobinfo; |
@@ -1292,7 +1290,6 @@ static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, | |||
1292 | return 0; | 1290 | return 0; |
1293 | } | 1291 | } |
1294 | 1292 | ||
1295 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | ||
1296 | /** | 1293 | /** |
1297 | * erased_sector_bitflips - count bit flips | 1294 | * erased_sector_bitflips - count bit flips |
1298 | * @data: data sector buffer | 1295 | * @data: data sector buffer |
@@ -1378,7 +1375,7 @@ static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data, | |||
1378 | erased_ecc_vec = bch16_vector; | 1375 | erased_ecc_vec = bch16_vector; |
1379 | break; | 1376 | break; |
1380 | default: | 1377 | default: |
1381 | pr_err("invalid driver configuration\n"); | 1378 | dev_err(&info->pdev->dev, "invalid driver configuration\n"); |
1382 | return -EINVAL; | 1379 | return -EINVAL; |
1383 | } | 1380 | } |
1384 | 1381 | ||
@@ -1449,7 +1446,8 @@ static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data, | |||
1449 | err = 0; | 1446 | err = 0; |
1450 | for (i = 0; i < eccsteps; i++) { | 1447 | for (i = 0; i < eccsteps; i++) { |
1451 | if (err_vec[i].error_uncorrectable) { | 1448 | if (err_vec[i].error_uncorrectable) { |
1452 | pr_err("nand: uncorrectable bit-flips found\n"); | 1449 | dev_err(&info->pdev->dev, |
1450 | "uncorrectable bit-flips found\n"); | ||
1453 | err = -EBADMSG; | 1451 | err = -EBADMSG; |
1454 | } else if (err_vec[i].error_reported) { | 1452 | } else if (err_vec[i].error_reported) { |
1455 | for (j = 0; j < err_vec[i].error_count; j++) { | 1453 | for (j = 0; j < err_vec[i].error_count; j++) { |
@@ -1486,8 +1484,9 @@ static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data, | |||
1486 | 1 << bit_pos; | 1484 | 1 << bit_pos; |
1487 | } | 1485 | } |
1488 | } else { | 1486 | } else { |
1489 | pr_err("invalid bit-flip @ %d:%d\n", | 1487 | dev_err(&info->pdev->dev, |
1490 | byte_pos, bit_pos); | 1488 | "invalid bit-flip @ %d:%d\n", |
1489 | byte_pos, bit_pos); | ||
1491 | err = -EBADMSG; | 1490 | err = -EBADMSG; |
1492 | } | 1491 | } |
1493 | } | 1492 | } |
@@ -1593,33 +1592,71 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |||
1593 | /** | 1592 | /** |
1594 | * is_elm_present - checks for presence of ELM module by scanning DT nodes | 1593 | * is_elm_present - checks for presence of ELM module by scanning DT nodes |
1595 | * @omap_nand_info: NAND device structure containing platform data | 1594 | * @omap_nand_info: NAND device structure containing platform data |
1596 | * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16 | ||
1597 | */ | 1595 | */ |
1598 | static int is_elm_present(struct omap_nand_info *info, | 1596 | static bool is_elm_present(struct omap_nand_info *info, |
1599 | struct device_node *elm_node, enum bch_ecc bch_type) | 1597 | struct device_node *elm_node) |
1600 | { | 1598 | { |
1601 | struct platform_device *pdev; | 1599 | struct platform_device *pdev; |
1602 | struct nand_ecc_ctrl *ecc = &info->nand.ecc; | 1600 | |
1603 | int err; | ||
1604 | /* check whether elm-id is passed via DT */ | 1601 | /* check whether elm-id is passed via DT */ |
1605 | if (!elm_node) { | 1602 | if (!elm_node) { |
1606 | pr_err("nand: error: ELM DT node not found\n"); | 1603 | dev_err(&info->pdev->dev, "ELM devicetree node not found\n"); |
1607 | return -ENODEV; | 1604 | return false; |
1608 | } | 1605 | } |
1609 | pdev = of_find_device_by_node(elm_node); | 1606 | pdev = of_find_device_by_node(elm_node); |
1610 | /* check whether ELM device is registered */ | 1607 | /* check whether ELM device is registered */ |
1611 | if (!pdev) { | 1608 | if (!pdev) { |
1612 | pr_err("nand: error: ELM device not found\n"); | 1609 | dev_err(&info->pdev->dev, "ELM device not found\n"); |
1613 | return -ENODEV; | 1610 | return false; |
1614 | } | 1611 | } |
1615 | /* ELM module available, now configure it */ | 1612 | /* ELM module available, now configure it */ |
1616 | info->elm_dev = &pdev->dev; | 1613 | info->elm_dev = &pdev->dev; |
1617 | err = elm_config(info->elm_dev, bch_type, | 1614 | return true; |
1618 | (info->mtd.writesize / ecc->size), ecc->size, ecc->bytes); | 1615 | } |
1619 | 1616 | ||
1620 | return err; | 1617 | static bool omap2_nand_ecc_check(struct omap_nand_info *info, |
1618 | struct omap_nand_platform_data *pdata) | ||
1619 | { | ||
1620 | bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm; | ||
1621 | |||
1622 | switch (info->ecc_opt) { | ||
1623 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | ||
1624 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | ||
1625 | ecc_needs_omap_bch = false; | ||
1626 | ecc_needs_bch = true; | ||
1627 | ecc_needs_elm = false; | ||
1628 | break; | ||
1629 | case OMAP_ECC_BCH4_CODE_HW: | ||
1630 | case OMAP_ECC_BCH8_CODE_HW: | ||
1631 | case OMAP_ECC_BCH16_CODE_HW: | ||
1632 | ecc_needs_omap_bch = true; | ||
1633 | ecc_needs_bch = false; | ||
1634 | ecc_needs_elm = true; | ||
1635 | break; | ||
1636 | default: | ||
1637 | ecc_needs_omap_bch = false; | ||
1638 | ecc_needs_bch = false; | ||
1639 | ecc_needs_elm = false; | ||
1640 | break; | ||
1641 | } | ||
1642 | |||
1643 | if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) { | ||
1644 | dev_err(&info->pdev->dev, | ||
1645 | "CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | ||
1646 | return false; | ||
1647 | } | ||
1648 | if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) { | ||
1649 | dev_err(&info->pdev->dev, | ||
1650 | "CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | ||
1651 | return false; | ||
1652 | } | ||
1653 | if (ecc_needs_elm && !is_elm_present(info, pdata->elm_of_node)) { | ||
1654 | dev_err(&info->pdev->dev, "ELM not available\n"); | ||
1655 | return false; | ||
1656 | } | ||
1657 | |||
1658 | return true; | ||
1621 | } | 1659 | } |
1622 | #endif /* CONFIG_MTD_NAND_ECC_BCH */ | ||
1623 | 1660 | ||
1624 | static int omap_nand_probe(struct platform_device *pdev) | 1661 | static int omap_nand_probe(struct platform_device *pdev) |
1625 | { | 1662 | { |
@@ -1663,7 +1700,6 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
1663 | mtd->owner = THIS_MODULE; | 1700 | mtd->owner = THIS_MODULE; |
1664 | nand_chip = &info->nand; | 1701 | nand_chip = &info->nand; |
1665 | nand_chip->ecc.priv = NULL; | 1702 | nand_chip->ecc.priv = NULL; |
1666 | nand_chip->options |= NAND_SKIP_BBTSCAN; | ||
1667 | 1703 | ||
1668 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1704 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1669 | nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res); | 1705 | nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res); |
@@ -1692,17 +1728,22 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
1692 | nand_chip->chip_delay = 50; | 1728 | nand_chip->chip_delay = 50; |
1693 | } | 1729 | } |
1694 | 1730 | ||
1731 | if (pdata->flash_bbt) | ||
1732 | nand_chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; | ||
1733 | else | ||
1734 | nand_chip->options |= NAND_SKIP_BBTSCAN; | ||
1735 | |||
1695 | /* scan NAND device connected to chip controller */ | 1736 | /* scan NAND device connected to chip controller */ |
1696 | nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16; | 1737 | nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16; |
1697 | if (nand_scan_ident(mtd, 1, NULL)) { | 1738 | if (nand_scan_ident(mtd, 1, NULL)) { |
1698 | pr_err("nand device scan failed, may be bus-width mismatch\n"); | 1739 | dev_err(&info->pdev->dev, "scan failed, may be bus-width mismatch\n"); |
1699 | err = -ENXIO; | 1740 | err = -ENXIO; |
1700 | goto return_error; | 1741 | goto return_error; |
1701 | } | 1742 | } |
1702 | 1743 | ||
1703 | /* check for small page devices */ | 1744 | /* check for small page devices */ |
1704 | if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) { | 1745 | if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) { |
1705 | pr_err("small page devices are not supported\n"); | 1746 | dev_err(&info->pdev->dev, "small page devices are not supported\n"); |
1706 | err = -EINVAL; | 1747 | err = -EINVAL; |
1707 | goto return_error; | 1748 | goto return_error; |
1708 | } | 1749 | } |
@@ -1793,6 +1834,11 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
1793 | goto return_error; | 1834 | goto return_error; |
1794 | } | 1835 | } |
1795 | 1836 | ||
1837 | if (!omap2_nand_ecc_check(info, pdata)) { | ||
1838 | err = -EINVAL; | ||
1839 | goto return_error; | ||
1840 | } | ||
1841 | |||
1796 | /* populate MTD interface based on ECC scheme */ | 1842 | /* populate MTD interface based on ECC scheme */ |
1797 | ecclayout = &omap_oobinfo; | 1843 | ecclayout = &omap_oobinfo; |
1798 | switch (info->ecc_opt) { | 1844 | switch (info->ecc_opt) { |
@@ -1825,7 +1871,6 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
1825 | break; | 1871 | break; |
1826 | 1872 | ||
1827 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | 1873 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: |
1828 | #ifdef CONFIG_MTD_NAND_ECC_BCH | ||
1829 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); | 1874 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); |
1830 | nand_chip->ecc.mode = NAND_ECC_HW; | 1875 | nand_chip->ecc.mode = NAND_ECC_HW; |
1831 | nand_chip->ecc.size = 512; | 1876 | nand_chip->ecc.size = 512; |
@@ -1853,18 +1898,13 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
1853 | nand_chip->ecc.bytes, | 1898 | nand_chip->ecc.bytes, |
1854 | &ecclayout); | 1899 | &ecclayout); |
1855 | if (!nand_chip->ecc.priv) { | 1900 | if (!nand_chip->ecc.priv) { |
1856 | pr_err("nand: error: unable to use s/w BCH library\n"); | 1901 | dev_err(&info->pdev->dev, "unable to use BCH library\n"); |
1857 | err = -EINVAL; | 1902 | err = -EINVAL; |
1903 | goto return_error; | ||
1858 | } | 1904 | } |
1859 | break; | 1905 | break; |
1860 | #else | ||
1861 | pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | ||
1862 | err = -EINVAL; | ||
1863 | goto return_error; | ||
1864 | #endif | ||
1865 | 1906 | ||
1866 | case OMAP_ECC_BCH4_CODE_HW: | 1907 | case OMAP_ECC_BCH4_CODE_HW: |
1867 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | ||
1868 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); | 1908 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); |
1869 | nand_chip->ecc.mode = NAND_ECC_HW; | 1909 | nand_chip->ecc.mode = NAND_ECC_HW; |
1870 | nand_chip->ecc.size = 512; | 1910 | nand_chip->ecc.size = 512; |
@@ -1886,21 +1926,15 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
1886 | /* reserved marker already included in ecclayout->eccbytes */ | 1926 | /* reserved marker already included in ecclayout->eccbytes */ |
1887 | ecclayout->oobfree->offset = | 1927 | ecclayout->oobfree->offset = |
1888 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | 1928 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; |
1889 | /* This ECC scheme requires ELM H/W block */ | 1929 | |
1890 | if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) { | 1930 | err = elm_config(info->elm_dev, BCH4_ECC, |
1891 | pr_err("nand: error: could not initialize ELM\n"); | 1931 | info->mtd.writesize / nand_chip->ecc.size, |
1892 | err = -ENODEV; | 1932 | nand_chip->ecc.size, nand_chip->ecc.bytes); |
1933 | if (err < 0) | ||
1893 | goto return_error; | 1934 | goto return_error; |
1894 | } | ||
1895 | break; | 1935 | break; |
1896 | #else | ||
1897 | pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | ||
1898 | err = -EINVAL; | ||
1899 | goto return_error; | ||
1900 | #endif | ||
1901 | 1936 | ||
1902 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | 1937 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: |
1903 | #ifdef CONFIG_MTD_NAND_ECC_BCH | ||
1904 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); | 1938 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); |
1905 | nand_chip->ecc.mode = NAND_ECC_HW; | 1939 | nand_chip->ecc.mode = NAND_ECC_HW; |
1906 | nand_chip->ecc.size = 512; | 1940 | nand_chip->ecc.size = 512; |
@@ -1928,19 +1962,13 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
1928 | nand_chip->ecc.bytes, | 1962 | nand_chip->ecc.bytes, |
1929 | &ecclayout); | 1963 | &ecclayout); |
1930 | if (!nand_chip->ecc.priv) { | 1964 | if (!nand_chip->ecc.priv) { |
1931 | pr_err("nand: error: unable to use s/w BCH library\n"); | 1965 | dev_err(&info->pdev->dev, "unable to use BCH library\n"); |
1932 | err = -EINVAL; | 1966 | err = -EINVAL; |
1933 | goto return_error; | 1967 | goto return_error; |
1934 | } | 1968 | } |
1935 | break; | 1969 | break; |
1936 | #else | ||
1937 | pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | ||
1938 | err = -EINVAL; | ||
1939 | goto return_error; | ||
1940 | #endif | ||
1941 | 1970 | ||
1942 | case OMAP_ECC_BCH8_CODE_HW: | 1971 | case OMAP_ECC_BCH8_CODE_HW: |
1943 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | ||
1944 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); | 1972 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); |
1945 | nand_chip->ecc.mode = NAND_ECC_HW; | 1973 | nand_chip->ecc.mode = NAND_ECC_HW; |
1946 | nand_chip->ecc.size = 512; | 1974 | nand_chip->ecc.size = 512; |
@@ -1952,12 +1980,13 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
1952 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; | 1980 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
1953 | nand_chip->ecc.read_page = omap_read_page_bch; | 1981 | nand_chip->ecc.read_page = omap_read_page_bch; |
1954 | nand_chip->ecc.write_page = omap_write_page_bch; | 1982 | nand_chip->ecc.write_page = omap_write_page_bch; |
1955 | /* This ECC scheme requires ELM H/W block */ | 1983 | |
1956 | err = is_elm_present(info, pdata->elm_of_node, BCH8_ECC); | 1984 | err = elm_config(info->elm_dev, BCH8_ECC, |
1957 | if (err < 0) { | 1985 | info->mtd.writesize / nand_chip->ecc.size, |
1958 | pr_err("nand: error: could not initialize ELM\n"); | 1986 | nand_chip->ecc.size, nand_chip->ecc.bytes); |
1987 | if (err < 0) | ||
1959 | goto return_error; | 1988 | goto return_error; |
1960 | } | 1989 | |
1961 | /* define ECC layout */ | 1990 | /* define ECC layout */ |
1962 | ecclayout->eccbytes = nand_chip->ecc.bytes * | 1991 | ecclayout->eccbytes = nand_chip->ecc.bytes * |
1963 | (mtd->writesize / | 1992 | (mtd->writesize / |
@@ -1969,14 +1998,8 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
1969 | ecclayout->oobfree->offset = | 1998 | ecclayout->oobfree->offset = |
1970 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | 1999 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; |
1971 | break; | 2000 | break; |
1972 | #else | ||
1973 | pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | ||
1974 | err = -EINVAL; | ||
1975 | goto return_error; | ||
1976 | #endif | ||
1977 | 2001 | ||
1978 | case OMAP_ECC_BCH16_CODE_HW: | 2002 | case OMAP_ECC_BCH16_CODE_HW: |
1979 | #ifdef CONFIG_MTD_NAND_OMAP_BCH | ||
1980 | pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n"); | 2003 | pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n"); |
1981 | nand_chip->ecc.mode = NAND_ECC_HW; | 2004 | nand_chip->ecc.mode = NAND_ECC_HW; |
1982 | nand_chip->ecc.size = 512; | 2005 | nand_chip->ecc.size = 512; |
@@ -1987,12 +2010,13 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
1987 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; | 2010 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
1988 | nand_chip->ecc.read_page = omap_read_page_bch; | 2011 | nand_chip->ecc.read_page = omap_read_page_bch; |
1989 | nand_chip->ecc.write_page = omap_write_page_bch; | 2012 | nand_chip->ecc.write_page = omap_write_page_bch; |
1990 | /* This ECC scheme requires ELM H/W block */ | 2013 | |
1991 | err = is_elm_present(info, pdata->elm_of_node, BCH16_ECC); | 2014 | err = elm_config(info->elm_dev, BCH16_ECC, |
1992 | if (err < 0) { | 2015 | info->mtd.writesize / nand_chip->ecc.size, |
1993 | pr_err("ELM is required for this ECC scheme\n"); | 2016 | nand_chip->ecc.size, nand_chip->ecc.bytes); |
2017 | if (err < 0) | ||
1994 | goto return_error; | 2018 | goto return_error; |
1995 | } | 2019 | |
1996 | /* define ECC layout */ | 2020 | /* define ECC layout */ |
1997 | ecclayout->eccbytes = nand_chip->ecc.bytes * | 2021 | ecclayout->eccbytes = nand_chip->ecc.bytes * |
1998 | (mtd->writesize / | 2022 | (mtd->writesize / |
@@ -2004,13 +2028,8 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
2004 | ecclayout->oobfree->offset = | 2028 | ecclayout->oobfree->offset = |
2005 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; | 2029 | ecclayout->eccpos[ecclayout->eccbytes - 1] + 1; |
2006 | break; | 2030 | break; |
2007 | #else | ||
2008 | pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | ||
2009 | err = -EINVAL; | ||
2010 | goto return_error; | ||
2011 | #endif | ||
2012 | default: | 2031 | default: |
2013 | pr_err("nand: error: invalid or unsupported ECC scheme\n"); | 2032 | dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n"); |
2014 | err = -EINVAL; | 2033 | err = -EINVAL; |
2015 | goto return_error; | 2034 | goto return_error; |
2016 | } | 2035 | } |
@@ -2022,8 +2041,9 @@ static int omap_nand_probe(struct platform_device *pdev) | |||
2022 | ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; | 2041 | ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; |
2023 | /* check if NAND device's OOB is enough to store ECC signatures */ | 2042 | /* check if NAND device's OOB is enough to store ECC signatures */ |
2024 | if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) { | 2043 | if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) { |
2025 | pr_err("not enough OOB bytes required = %d, available=%d\n", | 2044 | dev_err(&info->pdev->dev, |
2026 | ecclayout->eccbytes, mtd->oobsize); | 2045 | "not enough OOB bytes required = %d, available=%d\n", |
2046 | ecclayout->eccbytes, mtd->oobsize); | ||
2027 | err = -EINVAL; | 2047 | err = -EINVAL; |
2028 | goto return_error; | 2048 | goto return_error; |
2029 | } | 2049 | } |
diff --git a/drivers/mtd/devices/elm.c b/drivers/mtd/nand/omap_elm.c index b4f61c7fc161..b4f61c7fc161 100644 --- a/drivers/mtd/devices/elm.c +++ b/drivers/mtd/nand/omap_elm.c | |||
diff --git a/drivers/mtd/nand/sm_common.h b/drivers/mtd/nand/sm_common.h index 00f4a83359b2..d3e028e58b0f 100644 --- a/drivers/mtd/nand/sm_common.h +++ b/drivers/mtd/nand/sm_common.h | |||
@@ -18,7 +18,7 @@ struct sm_oob { | |||
18 | uint8_t ecc2[3]; | 18 | uint8_t ecc2[3]; |
19 | uint8_t lba_copy2[2]; | 19 | uint8_t lba_copy2[2]; |
20 | uint8_t ecc1[3]; | 20 | uint8_t ecc1[3]; |
21 | } __attribute__((packed)); | 21 | } __packed; |
22 | 22 | ||
23 | 23 | ||
24 | /* one sector is always 512 bytes, but it can consist of two nand pages */ | 24 | /* one sector is always 512 bytes, but it can consist of two nand pages */ |
diff --git a/drivers/mtd/sm_ftl.c b/drivers/mtd/sm_ftl.c index cf49c22673b9..c23184a47fc4 100644 --- a/drivers/mtd/sm_ftl.c +++ b/drivers/mtd/sm_ftl.c | |||
@@ -1058,7 +1058,7 @@ static int sm_write(struct mtd_blktrans_dev *dev, | |||
1058 | { | 1058 | { |
1059 | struct sm_ftl *ftl = dev->priv; | 1059 | struct sm_ftl *ftl = dev->priv; |
1060 | struct ftl_zone *zone; | 1060 | struct ftl_zone *zone; |
1061 | int error, zone_num, block, boffset; | 1061 | int error = 0, zone_num, block, boffset; |
1062 | 1062 | ||
1063 | BUG_ON(ftl->readonly); | 1063 | BUG_ON(ftl->readonly); |
1064 | sm_break_offset(ftl, sec_no << 9, &zone_num, &block, &boffset); | 1064 | sm_break_offset(ftl, sec_no << 9, &zone_num, &block, &boffset); |
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index f8acfa4310ef..64a4f0edabc7 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig | |||
@@ -7,6 +7,20 @@ menuconfig MTD_SPI_NOR | |||
7 | 7 | ||
8 | if MTD_SPI_NOR | 8 | if MTD_SPI_NOR |
9 | 9 | ||
10 | config MTD_SPI_NOR_USE_4K_SECTORS | ||
11 | bool "Use small 4096 B erase sectors" | ||
12 | default y | ||
13 | help | ||
14 | Many flash memories support erasing small (4096 B) sectors. Depending | ||
15 | on the usage this feature may provide performance gain in comparison | ||
16 | to erasing whole blocks (32/64 KiB). | ||
17 | Changing a small part of the flash's contents is usually faster with | ||
18 | small sectors. On the other hand erasing should be faster when using | ||
19 | 64 KiB block instead of 16 × 4 KiB sectors. | ||
20 | |||
21 | Please note that some tools/drivers/filesystems may not work with | ||
22 | 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum). | ||
23 | |||
10 | config SPI_FSL_QUADSPI | 24 | config SPI_FSL_QUADSPI |
11 | tristate "Freescale Quad SPI controller" | 25 | tristate "Freescale Quad SPI controller" |
12 | depends on ARCH_MXC | 26 | depends on ARCH_MXC |
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index b5ad6bebf5e7..ae16aa2f6885 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c | |||
@@ -611,6 +611,7 @@ const struct spi_device_id spi_nor_ids[] = { | |||
611 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, | 611 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, |
612 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, | 612 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, |
613 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, | 613 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, |
614 | { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, | ||
614 | 615 | ||
615 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ | 616 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
616 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, | 617 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
@@ -623,7 +624,6 @@ const struct spi_device_id spi_nor_ids[] = { | |||
623 | { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) }, | 624 | { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) }, |
624 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, | 625 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
625 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | 626 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
626 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, | ||
627 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, | 627 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
628 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, | 628 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, |
629 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, | 629 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, |
@@ -671,11 +671,6 @@ static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor) | |||
671 | return ERR_PTR(-ENODEV); | 671 | return ERR_PTR(-ENODEV); |
672 | } | 672 | } |
673 | 673 | ||
674 | static const struct spi_device_id *jedec_probe(struct spi_nor *nor) | ||
675 | { | ||
676 | return nor->read_id(nor); | ||
677 | } | ||
678 | |||
679 | static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, | 674 | static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, |
680 | size_t *retlen, u_char *buf) | 675 | size_t *retlen, u_char *buf) |
681 | { | 676 | { |
@@ -920,7 +915,6 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, | |||
920 | enum read_mode mode) | 915 | enum read_mode mode) |
921 | { | 916 | { |
922 | struct flash_info *info; | 917 | struct flash_info *info; |
923 | struct flash_platform_data *data; | ||
924 | struct device *dev = nor->dev; | 918 | struct device *dev = nor->dev; |
925 | struct mtd_info *mtd = nor->mtd; | 919 | struct mtd_info *mtd = nor->mtd; |
926 | struct device_node *np = dev->of_node; | 920 | struct device_node *np = dev->of_node; |
@@ -931,34 +925,12 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, | |||
931 | if (ret) | 925 | if (ret) |
932 | return ret; | 926 | return ret; |
933 | 927 | ||
934 | /* Platform data helps sort out which chip type we have, as | ||
935 | * well as how this board partitions it. If we don't have | ||
936 | * a chip ID, try the JEDEC id commands; they'll work for most | ||
937 | * newer chips, even if we don't recognize the particular chip. | ||
938 | */ | ||
939 | data = dev_get_platdata(dev); | ||
940 | if (data && data->type) { | ||
941 | const struct spi_device_id *plat_id; | ||
942 | |||
943 | for (i = 0; i < ARRAY_SIZE(spi_nor_ids) - 1; i++) { | ||
944 | plat_id = &spi_nor_ids[i]; | ||
945 | if (strcmp(data->type, plat_id->name)) | ||
946 | continue; | ||
947 | break; | ||
948 | } | ||
949 | |||
950 | if (i < ARRAY_SIZE(spi_nor_ids) - 1) | ||
951 | id = plat_id; | ||
952 | else | ||
953 | dev_warn(dev, "unrecognized id %s\n", data->type); | ||
954 | } | ||
955 | |||
956 | info = (void *)id->driver_data; | 928 | info = (void *)id->driver_data; |
957 | 929 | ||
958 | if (info->jedec_id) { | 930 | if (info->jedec_id) { |
959 | const struct spi_device_id *jid; | 931 | const struct spi_device_id *jid; |
960 | 932 | ||
961 | jid = jedec_probe(nor); | 933 | jid = nor->read_id(nor); |
962 | if (IS_ERR(jid)) { | 934 | if (IS_ERR(jid)) { |
963 | return PTR_ERR(jid); | 935 | return PTR_ERR(jid); |
964 | } else if (jid != id) { | 936 | } else if (jid != id) { |
@@ -990,11 +962,8 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, | |||
990 | write_sr(nor, 0); | 962 | write_sr(nor, 0); |
991 | } | 963 | } |
992 | 964 | ||
993 | if (data && data->name) | 965 | if (!mtd->name) |
994 | mtd->name = data->name; | ||
995 | else | ||
996 | mtd->name = dev_name(dev); | 966 | mtd->name = dev_name(dev); |
997 | |||
998 | mtd->type = MTD_NORFLASH; | 967 | mtd->type = MTD_NORFLASH; |
999 | mtd->writesize = 1; | 968 | mtd->writesize = 1; |
1000 | mtd->flags = MTD_CAP_NORFLASH; | 969 | mtd->flags = MTD_CAP_NORFLASH; |
@@ -1018,6 +987,7 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, | |||
1018 | nor->wait_till_ready == spi_nor_wait_till_ready) | 987 | nor->wait_till_ready == spi_nor_wait_till_ready) |
1019 | nor->wait_till_ready = spi_nor_wait_till_fsr_ready; | 988 | nor->wait_till_ready = spi_nor_wait_till_fsr_ready; |
1020 | 989 | ||
990 | #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS | ||
1021 | /* prefer "small sector" erase if possible */ | 991 | /* prefer "small sector" erase if possible */ |
1022 | if (info->flags & SECT_4K) { | 992 | if (info->flags & SECT_4K) { |
1023 | nor->erase_opcode = SPINOR_OP_BE_4K; | 993 | nor->erase_opcode = SPINOR_OP_BE_4K; |
@@ -1025,7 +995,9 @@ int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id, | |||
1025 | } else if (info->flags & SECT_4K_PMC) { | 995 | } else if (info->flags & SECT_4K_PMC) { |
1026 | nor->erase_opcode = SPINOR_OP_BE_4K_PMC; | 996 | nor->erase_opcode = SPINOR_OP_BE_4K_PMC; |
1027 | mtd->erasesize = 4096; | 997 | mtd->erasesize = 4096; |
1028 | } else { | 998 | } else |
999 | #endif | ||
1000 | { | ||
1029 | nor->erase_opcode = SPINOR_OP_SE; | 1001 | nor->erase_opcode = SPINOR_OP_SE; |
1030 | mtd->erasesize = info->sector_size; | 1002 | mtd->erasesize = info->sector_size; |
1031 | } | 1003 | } |
diff --git a/drivers/mtd/tests/mtd_test.c b/drivers/mtd/tests/mtd_test.c index 111ee46a7428..34736bbcc07b 100644 --- a/drivers/mtd/tests/mtd_test.c +++ b/drivers/mtd/tests/mtd_test.c | |||
@@ -10,7 +10,7 @@ int mtdtest_erase_eraseblock(struct mtd_info *mtd, unsigned int ebnum) | |||
10 | { | 10 | { |
11 | int err; | 11 | int err; |
12 | struct erase_info ei; | 12 | struct erase_info ei; |
13 | loff_t addr = ebnum * mtd->erasesize; | 13 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
14 | 14 | ||
15 | memset(&ei, 0, sizeof(struct erase_info)); | 15 | memset(&ei, 0, sizeof(struct erase_info)); |
16 | ei.mtd = mtd; | 16 | ei.mtd = mtd; |
@@ -33,7 +33,7 @@ int mtdtest_erase_eraseblock(struct mtd_info *mtd, unsigned int ebnum) | |||
33 | static int is_block_bad(struct mtd_info *mtd, unsigned int ebnum) | 33 | static int is_block_bad(struct mtd_info *mtd, unsigned int ebnum) |
34 | { | 34 | { |
35 | int ret; | 35 | int ret; |
36 | loff_t addr = ebnum * mtd->erasesize; | 36 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
37 | 37 | ||
38 | ret = mtd_block_isbad(mtd, addr); | 38 | ret = mtd_block_isbad(mtd, addr); |
39 | if (ret) | 39 | if (ret) |
diff --git a/drivers/mtd/tests/nandbiterrs.c b/drivers/mtd/tests/nandbiterrs.c index 6f976159611f..273f7e553954 100644 --- a/drivers/mtd/tests/nandbiterrs.c +++ b/drivers/mtd/tests/nandbiterrs.c | |||
@@ -364,7 +364,7 @@ static int __init mtd_nandbiterrs_init(void) | |||
364 | 364 | ||
365 | pr_info("Device uses %d subpages of %d bytes\n", subcount, subsize); | 365 | pr_info("Device uses %d subpages of %d bytes\n", subcount, subsize); |
366 | 366 | ||
367 | offset = page_offset * mtd->writesize; | 367 | offset = (loff_t)page_offset * mtd->writesize; |
368 | eraseblock = mtd_div_by_eb(offset, mtd); | 368 | eraseblock = mtd_div_by_eb(offset, mtd); |
369 | 369 | ||
370 | pr_info("Using page=%u, offset=%llu, eraseblock=%u\n", | 370 | pr_info("Using page=%u, offset=%llu, eraseblock=%u\n", |
diff --git a/drivers/mtd/tests/oobtest.c b/drivers/mtd/tests/oobtest.c index f19ab1acde1f..dc4f9602b97e 100644 --- a/drivers/mtd/tests/oobtest.c +++ b/drivers/mtd/tests/oobtest.c | |||
@@ -120,7 +120,7 @@ static int verify_eraseblock(int ebnum) | |||
120 | int i; | 120 | int i; |
121 | struct mtd_oob_ops ops; | 121 | struct mtd_oob_ops ops; |
122 | int err = 0; | 122 | int err = 0; |
123 | loff_t addr = ebnum * mtd->erasesize; | 123 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
124 | 124 | ||
125 | prandom_bytes_state(&rnd_state, writebuf, use_len_max * pgcnt); | 125 | prandom_bytes_state(&rnd_state, writebuf, use_len_max * pgcnt); |
126 | for (i = 0; i < pgcnt; ++i, addr += mtd->writesize) { | 126 | for (i = 0; i < pgcnt; ++i, addr += mtd->writesize) { |
@@ -214,7 +214,7 @@ static int verify_eraseblock_in_one_go(int ebnum) | |||
214 | { | 214 | { |
215 | struct mtd_oob_ops ops; | 215 | struct mtd_oob_ops ops; |
216 | int err = 0; | 216 | int err = 0; |
217 | loff_t addr = ebnum * mtd->erasesize; | 217 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
218 | size_t len = mtd->ecclayout->oobavail * pgcnt; | 218 | size_t len = mtd->ecclayout->oobavail * pgcnt; |
219 | 219 | ||
220 | prandom_bytes_state(&rnd_state, writebuf, len); | 220 | prandom_bytes_state(&rnd_state, writebuf, len); |
@@ -568,7 +568,7 @@ static int __init mtd_oobtest_init(void) | |||
568 | size_t sz = mtd->ecclayout->oobavail; | 568 | size_t sz = mtd->ecclayout->oobavail; |
569 | if (bbt[i] || bbt[i + 1]) | 569 | if (bbt[i] || bbt[i + 1]) |
570 | continue; | 570 | continue; |
571 | addr = (i + 1) * mtd->erasesize - mtd->writesize; | 571 | addr = (loff_t)(i + 1) * mtd->erasesize - mtd->writesize; |
572 | prandom_bytes_state(&rnd_state, writebuf, sz * cnt); | 572 | prandom_bytes_state(&rnd_state, writebuf, sz * cnt); |
573 | for (pg = 0; pg < cnt; ++pg) { | 573 | for (pg = 0; pg < cnt; ++pg) { |
574 | ops.mode = MTD_OPS_AUTO_OOB; | 574 | ops.mode = MTD_OPS_AUTO_OOB; |
@@ -598,7 +598,7 @@ static int __init mtd_oobtest_init(void) | |||
598 | continue; | 598 | continue; |
599 | prandom_bytes_state(&rnd_state, writebuf, | 599 | prandom_bytes_state(&rnd_state, writebuf, |
600 | mtd->ecclayout->oobavail * 2); | 600 | mtd->ecclayout->oobavail * 2); |
601 | addr = (i + 1) * mtd->erasesize - mtd->writesize; | 601 | addr = (loff_t)(i + 1) * mtd->erasesize - mtd->writesize; |
602 | ops.mode = MTD_OPS_AUTO_OOB; | 602 | ops.mode = MTD_OPS_AUTO_OOB; |
603 | ops.len = 0; | 603 | ops.len = 0; |
604 | ops.retlen = 0; | 604 | ops.retlen = 0; |
diff --git a/drivers/mtd/tests/pagetest.c b/drivers/mtd/tests/pagetest.c index ed2d3f656fd2..88296e888e9d 100644 --- a/drivers/mtd/tests/pagetest.c +++ b/drivers/mtd/tests/pagetest.c | |||
@@ -52,7 +52,7 @@ static struct rnd_state rnd_state; | |||
52 | 52 | ||
53 | static int write_eraseblock(int ebnum) | 53 | static int write_eraseblock(int ebnum) |
54 | { | 54 | { |
55 | loff_t addr = ebnum * mtd->erasesize; | 55 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
56 | 56 | ||
57 | prandom_bytes_state(&rnd_state, writebuf, mtd->erasesize); | 57 | prandom_bytes_state(&rnd_state, writebuf, mtd->erasesize); |
58 | cond_resched(); | 58 | cond_resched(); |
@@ -64,7 +64,7 @@ static int verify_eraseblock(int ebnum) | |||
64 | uint32_t j; | 64 | uint32_t j; |
65 | int err = 0, i; | 65 | int err = 0, i; |
66 | loff_t addr0, addrn; | 66 | loff_t addr0, addrn; |
67 | loff_t addr = ebnum * mtd->erasesize; | 67 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
68 | 68 | ||
69 | addr0 = 0; | 69 | addr0 = 0; |
70 | for (i = 0; i < ebcnt && bbt[i]; ++i) | 70 | for (i = 0; i < ebcnt && bbt[i]; ++i) |
diff --git a/drivers/mtd/tests/readtest.c b/drivers/mtd/tests/readtest.c index 626e66d0f7e7..a54cf1511114 100644 --- a/drivers/mtd/tests/readtest.c +++ b/drivers/mtd/tests/readtest.c | |||
@@ -47,7 +47,7 @@ static int pgcnt; | |||
47 | static int read_eraseblock_by_page(int ebnum) | 47 | static int read_eraseblock_by_page(int ebnum) |
48 | { | 48 | { |
49 | int i, ret, err = 0; | 49 | int i, ret, err = 0; |
50 | loff_t addr = ebnum * mtd->erasesize; | 50 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
51 | void *buf = iobuf; | 51 | void *buf = iobuf; |
52 | void *oobbuf = iobuf1; | 52 | void *oobbuf = iobuf1; |
53 | 53 | ||
diff --git a/drivers/mtd/tests/speedtest.c b/drivers/mtd/tests/speedtest.c index 87ff6a29f84e..5ee9f7021020 100644 --- a/drivers/mtd/tests/speedtest.c +++ b/drivers/mtd/tests/speedtest.c | |||
@@ -55,7 +55,7 @@ static int multiblock_erase(int ebnum, int blocks) | |||
55 | { | 55 | { |
56 | int err; | 56 | int err; |
57 | struct erase_info ei; | 57 | struct erase_info ei; |
58 | loff_t addr = ebnum * mtd->erasesize; | 58 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
59 | 59 | ||
60 | memset(&ei, 0, sizeof(struct erase_info)); | 60 | memset(&ei, 0, sizeof(struct erase_info)); |
61 | ei.mtd = mtd; | 61 | ei.mtd = mtd; |
@@ -80,7 +80,7 @@ static int multiblock_erase(int ebnum, int blocks) | |||
80 | 80 | ||
81 | static int write_eraseblock(int ebnum) | 81 | static int write_eraseblock(int ebnum) |
82 | { | 82 | { |
83 | loff_t addr = ebnum * mtd->erasesize; | 83 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
84 | 84 | ||
85 | return mtdtest_write(mtd, addr, mtd->erasesize, iobuf); | 85 | return mtdtest_write(mtd, addr, mtd->erasesize, iobuf); |
86 | } | 86 | } |
@@ -88,7 +88,7 @@ static int write_eraseblock(int ebnum) | |||
88 | static int write_eraseblock_by_page(int ebnum) | 88 | static int write_eraseblock_by_page(int ebnum) |
89 | { | 89 | { |
90 | int i, err = 0; | 90 | int i, err = 0; |
91 | loff_t addr = ebnum * mtd->erasesize; | 91 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
92 | void *buf = iobuf; | 92 | void *buf = iobuf; |
93 | 93 | ||
94 | for (i = 0; i < pgcnt; i++) { | 94 | for (i = 0; i < pgcnt; i++) { |
@@ -106,7 +106,7 @@ static int write_eraseblock_by_2pages(int ebnum) | |||
106 | { | 106 | { |
107 | size_t sz = pgsize * 2; | 107 | size_t sz = pgsize * 2; |
108 | int i, n = pgcnt / 2, err = 0; | 108 | int i, n = pgcnt / 2, err = 0; |
109 | loff_t addr = ebnum * mtd->erasesize; | 109 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
110 | void *buf = iobuf; | 110 | void *buf = iobuf; |
111 | 111 | ||
112 | for (i = 0; i < n; i++) { | 112 | for (i = 0; i < n; i++) { |
@@ -124,7 +124,7 @@ static int write_eraseblock_by_2pages(int ebnum) | |||
124 | 124 | ||
125 | static int read_eraseblock(int ebnum) | 125 | static int read_eraseblock(int ebnum) |
126 | { | 126 | { |
127 | loff_t addr = ebnum * mtd->erasesize; | 127 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
128 | 128 | ||
129 | return mtdtest_read(mtd, addr, mtd->erasesize, iobuf); | 129 | return mtdtest_read(mtd, addr, mtd->erasesize, iobuf); |
130 | } | 130 | } |
@@ -132,7 +132,7 @@ static int read_eraseblock(int ebnum) | |||
132 | static int read_eraseblock_by_page(int ebnum) | 132 | static int read_eraseblock_by_page(int ebnum) |
133 | { | 133 | { |
134 | int i, err = 0; | 134 | int i, err = 0; |
135 | loff_t addr = ebnum * mtd->erasesize; | 135 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
136 | void *buf = iobuf; | 136 | void *buf = iobuf; |
137 | 137 | ||
138 | for (i = 0; i < pgcnt; i++) { | 138 | for (i = 0; i < pgcnt; i++) { |
@@ -150,7 +150,7 @@ static int read_eraseblock_by_2pages(int ebnum) | |||
150 | { | 150 | { |
151 | size_t sz = pgsize * 2; | 151 | size_t sz = pgsize * 2; |
152 | int i, n = pgcnt / 2, err = 0; | 152 | int i, n = pgcnt / 2, err = 0; |
153 | loff_t addr = ebnum * mtd->erasesize; | 153 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
154 | void *buf = iobuf; | 154 | void *buf = iobuf; |
155 | 155 | ||
156 | for (i = 0; i < n; i++) { | 156 | for (i = 0; i < n; i++) { |
diff --git a/drivers/mtd/tests/subpagetest.c b/drivers/mtd/tests/subpagetest.c index a876371ad410..7b59ef522d5e 100644 --- a/drivers/mtd/tests/subpagetest.c +++ b/drivers/mtd/tests/subpagetest.c | |||
@@ -57,7 +57,7 @@ static int write_eraseblock(int ebnum) | |||
57 | { | 57 | { |
58 | size_t written; | 58 | size_t written; |
59 | int err = 0; | 59 | int err = 0; |
60 | loff_t addr = ebnum * mtd->erasesize; | 60 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
61 | 61 | ||
62 | prandom_bytes_state(&rnd_state, writebuf, subpgsize); | 62 | prandom_bytes_state(&rnd_state, writebuf, subpgsize); |
63 | err = mtd_write(mtd, addr, subpgsize, &written, writebuf); | 63 | err = mtd_write(mtd, addr, subpgsize, &written, writebuf); |
@@ -92,7 +92,7 @@ static int write_eraseblock2(int ebnum) | |||
92 | { | 92 | { |
93 | size_t written; | 93 | size_t written; |
94 | int err = 0, k; | 94 | int err = 0, k; |
95 | loff_t addr = ebnum * mtd->erasesize; | 95 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
96 | 96 | ||
97 | for (k = 1; k < 33; ++k) { | 97 | for (k = 1; k < 33; ++k) { |
98 | if (addr + (subpgsize * k) > (ebnum + 1) * mtd->erasesize) | 98 | if (addr + (subpgsize * k) > (ebnum + 1) * mtd->erasesize) |
@@ -131,7 +131,7 @@ static int verify_eraseblock(int ebnum) | |||
131 | { | 131 | { |
132 | size_t read; | 132 | size_t read; |
133 | int err = 0; | 133 | int err = 0; |
134 | loff_t addr = ebnum * mtd->erasesize; | 134 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
135 | 135 | ||
136 | prandom_bytes_state(&rnd_state, writebuf, subpgsize); | 136 | prandom_bytes_state(&rnd_state, writebuf, subpgsize); |
137 | clear_data(readbuf, subpgsize); | 137 | clear_data(readbuf, subpgsize); |
@@ -192,7 +192,7 @@ static int verify_eraseblock2(int ebnum) | |||
192 | { | 192 | { |
193 | size_t read; | 193 | size_t read; |
194 | int err = 0, k; | 194 | int err = 0, k; |
195 | loff_t addr = ebnum * mtd->erasesize; | 195 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
196 | 196 | ||
197 | for (k = 1; k < 33; ++k) { | 197 | for (k = 1; k < 33; ++k) { |
198 | if (addr + (subpgsize * k) > (ebnum + 1) * mtd->erasesize) | 198 | if (addr + (subpgsize * k) > (ebnum + 1) * mtd->erasesize) |
@@ -227,7 +227,7 @@ static int verify_eraseblock_ff(int ebnum) | |||
227 | uint32_t j; | 227 | uint32_t j; |
228 | size_t read; | 228 | size_t read; |
229 | int err = 0; | 229 | int err = 0; |
230 | loff_t addr = ebnum * mtd->erasesize; | 230 | loff_t addr = (loff_t)ebnum * mtd->erasesize; |
231 | 231 | ||
232 | memset(writebuf, 0xff, subpgsize); | 232 | memset(writebuf, 0xff, subpgsize); |
233 | for (j = 0; j < mtd->erasesize / subpgsize; ++j) { | 233 | for (j = 0; j < mtd->erasesize / subpgsize; ++j) { |
diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index 37ef6b194089..299d7d31fe53 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h | |||
@@ -153,7 +153,7 @@ struct cfi_ident { | |||
153 | uint16_t MaxBufWriteSize; | 153 | uint16_t MaxBufWriteSize; |
154 | uint8_t NumEraseRegions; | 154 | uint8_t NumEraseRegions; |
155 | uint32_t EraseRegionInfo[0]; /* Not host ordered */ | 155 | uint32_t EraseRegionInfo[0]; /* Not host ordered */ |
156 | } __attribute__((packed)); | 156 | } __packed; |
157 | 157 | ||
158 | /* Extended Query Structure for both PRI and ALT */ | 158 | /* Extended Query Structure for both PRI and ALT */ |
159 | 159 | ||
@@ -161,7 +161,7 @@ struct cfi_extquery { | |||
161 | uint8_t pri[3]; | 161 | uint8_t pri[3]; |
162 | uint8_t MajorVersion; | 162 | uint8_t MajorVersion; |
163 | uint8_t MinorVersion; | 163 | uint8_t MinorVersion; |
164 | } __attribute__((packed)); | 164 | } __packed; |
165 | 165 | ||
166 | /* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */ | 166 | /* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */ |
167 | 167 | ||
@@ -180,7 +180,7 @@ struct cfi_pri_intelext { | |||
180 | uint8_t FactProtRegSize; | 180 | uint8_t FactProtRegSize; |
181 | uint8_t UserProtRegSize; | 181 | uint8_t UserProtRegSize; |
182 | uint8_t extra[0]; | 182 | uint8_t extra[0]; |
183 | } __attribute__((packed)); | 183 | } __packed; |
184 | 184 | ||
185 | struct cfi_intelext_otpinfo { | 185 | struct cfi_intelext_otpinfo { |
186 | uint32_t ProtRegAddr; | 186 | uint32_t ProtRegAddr; |
@@ -188,7 +188,7 @@ struct cfi_intelext_otpinfo { | |||
188 | uint8_t FactProtRegSize; | 188 | uint8_t FactProtRegSize; |
189 | uint16_t UserGroups; | 189 | uint16_t UserGroups; |
190 | uint8_t UserProtRegSize; | 190 | uint8_t UserProtRegSize; |
191 | } __attribute__((packed)); | 191 | } __packed; |
192 | 192 | ||
193 | struct cfi_intelext_blockinfo { | 193 | struct cfi_intelext_blockinfo { |
194 | uint16_t NumIdentBlocks; | 194 | uint16_t NumIdentBlocks; |
@@ -196,7 +196,7 @@ struct cfi_intelext_blockinfo { | |||
196 | uint16_t MinBlockEraseCycles; | 196 | uint16_t MinBlockEraseCycles; |
197 | uint8_t BitsPerCell; | 197 | uint8_t BitsPerCell; |
198 | uint8_t BlockCap; | 198 | uint8_t BlockCap; |
199 | } __attribute__((packed)); | 199 | } __packed; |
200 | 200 | ||
201 | struct cfi_intelext_regioninfo { | 201 | struct cfi_intelext_regioninfo { |
202 | uint16_t NumIdentPartitions; | 202 | uint16_t NumIdentPartitions; |
@@ -205,7 +205,7 @@ struct cfi_intelext_regioninfo { | |||
205 | uint8_t NumOpAllowedSimEraMode; | 205 | uint8_t NumOpAllowedSimEraMode; |
206 | uint8_t NumBlockTypes; | 206 | uint8_t NumBlockTypes; |
207 | struct cfi_intelext_blockinfo BlockTypes[1]; | 207 | struct cfi_intelext_blockinfo BlockTypes[1]; |
208 | } __attribute__((packed)); | 208 | } __packed; |
209 | 209 | ||
210 | struct cfi_intelext_programming_regioninfo { | 210 | struct cfi_intelext_programming_regioninfo { |
211 | uint8_t ProgRegShift; | 211 | uint8_t ProgRegShift; |
@@ -214,7 +214,7 @@ struct cfi_intelext_programming_regioninfo { | |||
214 | uint8_t Reserved2; | 214 | uint8_t Reserved2; |
215 | uint8_t ControlInvalid; | 215 | uint8_t ControlInvalid; |
216 | uint8_t Reserved3; | 216 | uint8_t Reserved3; |
217 | } __attribute__((packed)); | 217 | } __packed; |
218 | 218 | ||
219 | /* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */ | 219 | /* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */ |
220 | 220 | ||
@@ -233,7 +233,7 @@ struct cfi_pri_amdstd { | |||
233 | uint8_t VppMin; | 233 | uint8_t VppMin; |
234 | uint8_t VppMax; | 234 | uint8_t VppMax; |
235 | uint8_t TopBottom; | 235 | uint8_t TopBottom; |
236 | } __attribute__((packed)); | 236 | } __packed; |
237 | 237 | ||
238 | /* Vendor-Specific PRI for Atmel chips (command set 0x0002) */ | 238 | /* Vendor-Specific PRI for Atmel chips (command set 0x0002) */ |
239 | 239 | ||
@@ -245,18 +245,18 @@ struct cfi_pri_atmel { | |||
245 | uint8_t BottomBoot; | 245 | uint8_t BottomBoot; |
246 | uint8_t BurstMode; | 246 | uint8_t BurstMode; |
247 | uint8_t PageMode; | 247 | uint8_t PageMode; |
248 | } __attribute__((packed)); | 248 | } __packed; |
249 | 249 | ||
250 | struct cfi_pri_query { | 250 | struct cfi_pri_query { |
251 | uint8_t NumFields; | 251 | uint8_t NumFields; |
252 | uint32_t ProtField[1]; /* Not host ordered */ | 252 | uint32_t ProtField[1]; /* Not host ordered */ |
253 | } __attribute__((packed)); | 253 | } __packed; |
254 | 254 | ||
255 | struct cfi_bri_query { | 255 | struct cfi_bri_query { |
256 | uint8_t PageModeReadCap; | 256 | uint8_t PageModeReadCap; |
257 | uint8_t NumFields; | 257 | uint8_t NumFields; |
258 | uint32_t ConfField[1]; /* Not host ordered */ | 258 | uint32_t ConfField[1]; /* Not host ordered */ |
259 | } __attribute__((packed)); | 259 | } __packed; |
260 | 260 | ||
261 | #define P_ID_NONE 0x0000 | 261 | #define P_ID_NONE 0x0000 |
262 | #define P_ID_INTEL_EXT 0x0001 | 262 | #define P_ID_INTEL_EXT 0x0001 |
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index c300db3ae285..e4d451e4600b 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h | |||
@@ -587,6 +587,11 @@ struct nand_buffers { | |||
587 | * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, | 587 | * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds, |
588 | * also from the datasheet. It is the recommended ECC step | 588 | * also from the datasheet. It is the recommended ECC step |
589 | * size, if known; if unknown, set to zero. | 589 | * size, if known; if unknown, set to zero. |
590 | * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is | ||
591 | * either deduced from the datasheet if the NAND | ||
592 | * chip is not ONFI compliant or set to 0 if it is | ||
593 | * (an ONFI chip is always configured in mode 0 | ||
594 | * after a NAND reset) | ||
590 | * @numchips: [INTERN] number of physical chips | 595 | * @numchips: [INTERN] number of physical chips |
591 | * @chipsize: [INTERN] the size of one chip for multichip arrays | 596 | * @chipsize: [INTERN] the size of one chip for multichip arrays |
592 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 | 597 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 |
@@ -671,6 +676,7 @@ struct nand_chip { | |||
671 | uint8_t bits_per_cell; | 676 | uint8_t bits_per_cell; |
672 | uint16_t ecc_strength_ds; | 677 | uint16_t ecc_strength_ds; |
673 | uint16_t ecc_step_ds; | 678 | uint16_t ecc_step_ds; |
679 | int onfi_timing_mode_default; | ||
674 | int badblockpos; | 680 | int badblockpos; |
675 | int badblockbits; | 681 | int badblockbits; |
676 | 682 | ||
@@ -766,12 +772,17 @@ struct nand_chip { | |||
766 | * @options: stores various chip bit options | 772 | * @options: stores various chip bit options |
767 | * @id_len: The valid length of the @id. | 773 | * @id_len: The valid length of the @id. |
768 | * @oobsize: OOB size | 774 | * @oobsize: OOB size |
775 | * @ecc: ECC correctability and step information from the datasheet. | ||
769 | * @ecc.strength_ds: The ECC correctability from the datasheet, same as the | 776 | * @ecc.strength_ds: The ECC correctability from the datasheet, same as the |
770 | * @ecc_strength_ds in nand_chip{}. | 777 | * @ecc_strength_ds in nand_chip{}. |
771 | * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the | 778 | * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the |
772 | * @ecc_step_ds in nand_chip{}, also from the datasheet. | 779 | * @ecc_step_ds in nand_chip{}, also from the datasheet. |
773 | * For example, the "4bit ECC for each 512Byte" can be set with | 780 | * For example, the "4bit ECC for each 512Byte" can be set with |
774 | * NAND_ECC_INFO(4, 512). | 781 | * NAND_ECC_INFO(4, 512). |
782 | * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND | ||
783 | * reset. Should be deduced from timings described | ||
784 | * in the datasheet. | ||
785 | * | ||
775 | */ | 786 | */ |
776 | struct nand_flash_dev { | 787 | struct nand_flash_dev { |
777 | char *name; | 788 | char *name; |
@@ -792,6 +803,7 @@ struct nand_flash_dev { | |||
792 | uint16_t strength_ds; | 803 | uint16_t strength_ds; |
793 | uint16_t step_ds; | 804 | uint16_t step_ds; |
794 | } ecc; | 805 | } ecc; |
806 | int onfi_timing_mode_default; | ||
795 | }; | 807 | }; |
796 | 808 | ||
797 | /** | 809 | /** |
diff --git a/include/linux/platform_data/elm.h b/include/linux/platform_data/elm.h index 780d1e97f620..b8686c00f15f 100644 --- a/include/linux/platform_data/elm.h +++ b/include/linux/platform_data/elm.h | |||
@@ -42,8 +42,24 @@ struct elm_errorvec { | |||
42 | int error_loc[16]; | 42 | int error_loc[16]; |
43 | }; | 43 | }; |
44 | 44 | ||
45 | #if IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH) | ||
45 | void elm_decode_bch_error_page(struct device *dev, u8 *ecc_calc, | 46 | void elm_decode_bch_error_page(struct device *dev, u8 *ecc_calc, |
46 | struct elm_errorvec *err_vec); | 47 | struct elm_errorvec *err_vec); |
47 | int elm_config(struct device *dev, enum bch_ecc bch_type, | 48 | int elm_config(struct device *dev, enum bch_ecc bch_type, |
48 | int ecc_steps, int ecc_step_size, int ecc_syndrome_size); | 49 | int ecc_steps, int ecc_step_size, int ecc_syndrome_size); |
50 | #else | ||
51 | static inline void | ||
52 | elm_decode_bch_error_page(struct device *dev, u8 *ecc_calc, | ||
53 | struct elm_errorvec *err_vec) | ||
54 | { | ||
55 | } | ||
56 | |||
57 | static inline int elm_config(struct device *dev, enum bch_ecc bch_type, | ||
58 | int ecc_steps, int ecc_step_size, | ||
59 | int ecc_syndrome_size) | ||
60 | { | ||
61 | return -ENOSYS; | ||
62 | } | ||
63 | #endif /* CONFIG_MTD_NAND_ECC_BCH */ | ||
64 | |||
49 | #endif /* __ELM_H */ | 65 | #endif /* __ELM_H */ |
diff --git a/include/linux/platform_data/mtd-nand-omap2.h b/include/linux/platform_data/mtd-nand-omap2.h index 16ec262dfcc8..090bbab0130a 100644 --- a/include/linux/platform_data/mtd-nand-omap2.h +++ b/include/linux/platform_data/mtd-nand-omap2.h | |||
@@ -71,6 +71,7 @@ struct omap_nand_platform_data { | |||
71 | struct mtd_partition *parts; | 71 | struct mtd_partition *parts; |
72 | int nr_parts; | 72 | int nr_parts; |
73 | bool dev_ready; | 73 | bool dev_ready; |
74 | bool flash_bbt; | ||
74 | enum nand_io xfer_type; | 75 | enum nand_io xfer_type; |
75 | int devsize; | 76 | int devsize; |
76 | enum omap_ecc ecc_opt; | 77 | enum omap_ecc ecc_opt; |