diff options
-rw-r--r-- | drivers/net/tg3.c | 27 | ||||
-rw-r--r-- | drivers/net/tg3.h | 2 |
2 files changed, 28 insertions, 1 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 9915734ac3e9..58787ea8b7a4 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -339,6 +339,7 @@ static const struct { | |||
339 | { "dma_write_prioq_full" }, | 339 | { "dma_write_prioq_full" }, |
340 | { "rxbds_empty" }, | 340 | { "rxbds_empty" }, |
341 | { "rx_discards" }, | 341 | { "rx_discards" }, |
342 | { "mbuf_lwm_thresh_hit" }, | ||
342 | { "rx_errors" }, | 343 | { "rx_errors" }, |
343 | { "rx_threshold_hit" }, | 344 | { "rx_threshold_hit" }, |
344 | 345 | ||
@@ -8207,6 +8208,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
8207 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; | 8208 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
8208 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | 8209 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) |
8209 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | 8210 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; |
8211 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | ||
8212 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | ||
8213 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | ||
8214 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | ||
8210 | tw32(BUFMGR_MODE, val); | 8215 | tw32(BUFMGR_MODE, val); |
8211 | for (i = 0; i < 2000; i++) { | 8216 | for (i = 0; i < 2000; i++) { |
8212 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | 8217 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) |
@@ -8870,7 +8875,19 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp) | |||
8870 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | 8875 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); |
8871 | 8876 | ||
8872 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | 8877 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); |
8873 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | 8878 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) { |
8879 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | ||
8880 | } else { | ||
8881 | u32 val = tr32(HOSTCC_FLOW_ATTN); | ||
8882 | val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; | ||
8883 | if (val) { | ||
8884 | tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM); | ||
8885 | sp->rx_discards.low += val; | ||
8886 | if (sp->rx_discards.low < val) | ||
8887 | sp->rx_discards.high += 1; | ||
8888 | } | ||
8889 | sp->mbuf_lwm_thresh_hit = sp->rx_discards; | ||
8890 | } | ||
8874 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); | 8891 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); |
8875 | } | 8892 | } |
8876 | 8893 | ||
@@ -13973,6 +13990,14 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
13973 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | 13990 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) |
13974 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | 13991 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; |
13975 | 13992 | ||
13993 | /* Set these bits to enable statistics workaround. */ | ||
13994 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | ||
13995 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | ||
13996 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | ||
13997 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | ||
13998 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | ||
13999 | } | ||
14000 | |||
13976 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | 14001 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
13977 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | 14002 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
13978 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; | 14003 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 224c3e0ec695..db50bfe046e4 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -147,6 +147,7 @@ | |||
147 | #define CHIPREV_ID_5717_A0 0x05717000 | 147 | #define CHIPREV_ID_5717_A0 0x05717000 |
148 | #define CHIPREV_ID_57765_A0 0x57785000 | 148 | #define CHIPREV_ID_57765_A0 0x57785000 |
149 | #define CHIPREV_ID_5719_A0 0x05719000 | 149 | #define CHIPREV_ID_5719_A0 0x05719000 |
150 | #define CHIPREV_ID_5720_A0 0x05720000 | ||
150 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) | 151 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) |
151 | #define ASIC_REV_5700 0x07 | 152 | #define ASIC_REV_5700 0x07 |
152 | #define ASIC_REV_5701 0x00 | 153 | #define ASIC_REV_5701 0x00 |
@@ -2602,6 +2603,7 @@ struct tg3_hw_stats { | |||
2602 | tg3_stat64_t dma_write_prioq_full; | 2603 | tg3_stat64_t dma_write_prioq_full; |
2603 | tg3_stat64_t rxbds_empty; | 2604 | tg3_stat64_t rxbds_empty; |
2604 | tg3_stat64_t rx_discards; | 2605 | tg3_stat64_t rx_discards; |
2606 | tg3_stat64_t mbuf_lwm_thresh_hit; | ||
2605 | tg3_stat64_t rx_errors; | 2607 | tg3_stat64_t rx_errors; |
2606 | tg3_stat64_t rx_threshold_hit; | 2608 | tg3_stat64_t rx_threshold_hit; |
2607 | 2609 | ||