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-rw-r--r--drivers/mmc/host/sh_mmcif.c125
-rw-r--r--include/linux/mmc/sh_mmcif.h32
2 files changed, 82 insertions, 75 deletions
diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index eb97830c0344..5d3f824bb5a3 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -30,25 +30,6 @@
30#define DRIVER_NAME "sh_mmcif" 30#define DRIVER_NAME "sh_mmcif"
31#define DRIVER_VERSION "2010-04-28" 31#define DRIVER_VERSION "2010-04-28"
32 32
33#define MMCIF_CE_CMD_SET 0x00000000
34#define MMCIF_CE_ARG 0x00000008
35#define MMCIF_CE_ARG_CMD12 0x0000000C
36#define MMCIF_CE_CMD_CTRL 0x00000010
37#define MMCIF_CE_BLOCK_SET 0x00000014
38#define MMCIF_CE_CLK_CTRL 0x00000018
39#define MMCIF_CE_BUF_ACC 0x0000001C
40#define MMCIF_CE_RESP3 0x00000020
41#define MMCIF_CE_RESP2 0x00000024
42#define MMCIF_CE_RESP1 0x00000028
43#define MMCIF_CE_RESP0 0x0000002C
44#define MMCIF_CE_RESP_CMD12 0x00000030
45#define MMCIF_CE_DATA 0x00000034
46#define MMCIF_CE_INT 0x00000040
47#define MMCIF_CE_INT_MASK 0x00000044
48#define MMCIF_CE_HOST_STS1 0x00000048
49#define MMCIF_CE_HOST_STS2 0x0000004C
50#define MMCIF_CE_VERSION 0x0000007C
51
52/* CE_CMD_SET */ 33/* CE_CMD_SET */
53#define CMD_MASK 0x3f000000 34#define CMD_MASK 0x3f000000
54#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 35#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
@@ -207,27 +188,17 @@ struct sh_mmcif_host {
207 wait_queue_head_t intr_wait; 188 wait_queue_head_t intr_wait;
208}; 189};
209 190
210static inline u32 sh_mmcif_readl(struct sh_mmcif_host *host, unsigned int reg)
211{
212 return readl(host->addr + reg);
213}
214
215static inline void sh_mmcif_writel(struct sh_mmcif_host *host,
216 unsigned int reg, u32 val)
217{
218 writel(val, host->addr + reg);
219}
220 191
221static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 192static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
222 unsigned int reg, u32 val) 193 unsigned int reg, u32 val)
223{ 194{
224 writel(val | sh_mmcif_readl(host, reg), host->addr + reg); 195 writel(val | readl(host->addr + reg), host->addr + reg);
225} 196}
226 197
227static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 198static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
228 unsigned int reg, u32 val) 199 unsigned int reg, u32 val)
229{ 200{
230 writel(~val & sh_mmcif_readl(host, reg), host->addr + reg); 201 writel(~val & readl(host->addr + reg), host->addr + reg);
231} 202}
232 203
233 204
@@ -253,10 +224,10 @@ static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
253{ 224{
254 u32 tmp; 225 u32 tmp;
255 226
256 tmp = 0x010f0000 & sh_mmcif_readl(host, MMCIF_CE_CLK_CTRL); 227 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
257 228
258 sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_ON); 229 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
259 sh_mmcif_writel(host, MMCIF_CE_VERSION, SOFT_RST_OFF); 230 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
260 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 231 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
261 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 232 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
262 /* byte swap on */ 233 /* byte swap on */
@@ -271,12 +242,10 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
271 host->sd_error = 0; 242 host->sd_error = 0;
272 host->wait_int = 0; 243 host->wait_int = 0;
273 244
274 state1 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS1); 245 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
275 state2 = sh_mmcif_readl(host, MMCIF_CE_HOST_STS2); 246 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
276 pr_debug("%s: ERR HOST_STS1 = %08x\n", \ 247 pr_debug("%s: ERR HOST_STS1 = %08x\n", DRIVER_NAME, state1);
277 DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS1)); 248 pr_debug("%s: ERR HOST_STS2 = %08x\n", DRIVER_NAME, state2);
278 pr_debug("%s: ERR HOST_STS2 = %08x\n", \
279 DRIVER_NAME, sh_mmcif_readl(host, MMCIF_CE_HOST_STS2));
280 249
281 if (state1 & STS1_CMDSEQ) { 250 if (state1 & STS1_CMDSEQ) {
282 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 251 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
@@ -288,7 +257,7 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
288 "command sequence timeout err\n"); 257 "command sequence timeout err\n");
289 return -EIO; 258 return -EIO;
290 } 259 }
291 if (!(sh_mmcif_readl(host, MMCIF_CE_HOST_STS1) 260 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
292 & STS1_CMDSEQ)) 261 & STS1_CMDSEQ))
293 break; 262 break;
294 mdelay(1); 263 mdelay(1);
@@ -330,9 +299,9 @@ static int sh_mmcif_single_read(struct sh_mmcif_host *host,
330 299
331 host->wait_int = 0; 300 host->wait_int = 0;
332 blocksize = (BLOCK_SIZE_MASK & 301 blocksize = (BLOCK_SIZE_MASK &
333 sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3; 302 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
334 for (i = 0; i < blocksize / 4; i++) 303 for (i = 0; i < blocksize / 4; i++)
335 *p++ = sh_mmcif_readl(host, MMCIF_CE_DATA); 304 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
336 305
337 /* buffer read end */ 306 /* buffer read end */
338 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 307 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
@@ -353,7 +322,8 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
353 long time; 322 long time;
354 u32 blocksize, i, j, sec, *p; 323 u32 blocksize, i, j, sec, *p;
355 324
356 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET); 325 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
326 MMCIF_CE_BLOCK_SET);
357 for (j = 0; j < data->sg_len; j++) { 327 for (j = 0; j < data->sg_len; j++) {
358 p = sg_virt(data->sg); 328 p = sg_virt(data->sg);
359 host->wait_int = 0; 329 host->wait_int = 0;
@@ -370,7 +340,8 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
370 340
371 host->wait_int = 0; 341 host->wait_int = 0;
372 for (i = 0; i < blocksize / 4; i++) 342 for (i = 0; i < blocksize / 4; i++)
373 *p++ = sh_mmcif_readl(host, MMCIF_CE_DATA); 343 *p++ = sh_mmcif_readl(host->addr,
344 MMCIF_CE_DATA);
374 } 345 }
375 if (j < data->sg_len - 1) 346 if (j < data->sg_len - 1)
376 data->sg++; 347 data->sg++;
@@ -397,9 +368,9 @@ static int sh_mmcif_single_write(struct sh_mmcif_host *host,
397 368
398 host->wait_int = 0; 369 host->wait_int = 0;
399 blocksize = (BLOCK_SIZE_MASK & 370 blocksize = (BLOCK_SIZE_MASK &
400 sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET)) + 3; 371 sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
401 for (i = 0; i < blocksize / 4; i++) 372 for (i = 0; i < blocksize / 4; i++)
402 sh_mmcif_writel(host, MMCIF_CE_DATA, *p++); 373 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
403 374
404 /* buffer write end */ 375 /* buffer write end */
405 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 376 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
@@ -421,7 +392,8 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
421 long time; 392 long time;
422 u32 i, sec, j, blocksize, *p; 393 u32 i, sec, j, blocksize, *p;
423 394
424 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host, MMCIF_CE_BLOCK_SET); 395 blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
396 MMCIF_CE_BLOCK_SET);
425 397
426 for (j = 0; j < data->sg_len; j++) { 398 for (j = 0; j < data->sg_len; j++) {
427 p = sg_virt(data->sg); 399 p = sg_virt(data->sg);
@@ -439,7 +411,8 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
439 411
440 host->wait_int = 0; 412 host->wait_int = 0;
441 for (i = 0; i < blocksize / 4; i++) 413 for (i = 0; i < blocksize / 4; i++)
442 sh_mmcif_writel(host, MMCIF_CE_DATA, *p++); 414 sh_mmcif_writel(host->addr,
415 MMCIF_CE_DATA, *p++);
443 } 416 }
444 if (j < data->sg_len - 1) 417 if (j < data->sg_len - 1)
445 data->sg++; 418 data->sg++;
@@ -451,18 +424,18 @@ static void sh_mmcif_get_response(struct sh_mmcif_host *host,
451 struct mmc_command *cmd) 424 struct mmc_command *cmd)
452{ 425{
453 if (cmd->flags & MMC_RSP_136) { 426 if (cmd->flags & MMC_RSP_136) {
454 cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP3); 427 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
455 cmd->resp[1] = sh_mmcif_readl(host, MMCIF_CE_RESP2); 428 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
456 cmd->resp[2] = sh_mmcif_readl(host, MMCIF_CE_RESP1); 429 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
457 cmd->resp[3] = sh_mmcif_readl(host, MMCIF_CE_RESP0); 430 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
458 } else 431 } else
459 cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP0); 432 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
460} 433}
461 434
462static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 435static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
463 struct mmc_command *cmd) 436 struct mmc_command *cmd)
464{ 437{
465 cmd->resp[0] = sh_mmcif_readl(host, MMCIF_CE_RESP_CMD12); 438 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
466} 439}
467 440
468static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 441static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
@@ -596,18 +569,19 @@ static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
596 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; 569 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
597 570
598 if (host->data) { 571 if (host->data) {
599 sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, 0); 572 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
600 sh_mmcif_writel(host, MMCIF_CE_BLOCK_SET, mrq->data->blksz); 573 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
574 mrq->data->blksz);
601 } 575 }
602 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc); 576 opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
603 577
604 sh_mmcif_writel(host, MMCIF_CE_INT, 0xD80430C0); 578 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
605 sh_mmcif_writel(host, MMCIF_CE_INT_MASK, mask); 579 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
606 /* set arg */ 580 /* set arg */
607 sh_mmcif_writel(host, MMCIF_CE_ARG, cmd->arg); 581 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
608 host->wait_int = 0; 582 host->wait_int = 0;
609 /* set cmd */ 583 /* set cmd */
610 sh_mmcif_writel(host, MMCIF_CE_CMD_SET, opc); 584 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
611 585
612 time = wait_event_interruptible_timeout(host->intr_wait, 586 time = wait_event_interruptible_timeout(host->intr_wait,
613 host->wait_int == 1 || host->sd_error == 1, host->timeout); 587 host->wait_int == 1 || host->sd_error == 1, host->timeout);
@@ -752,43 +726,44 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
752 u32 state = 0; 726 u32 state = 0;
753 int err = 0; 727 int err = 0;
754 728
755 state = sh_mmcif_readl(host, MMCIF_CE_INT); 729 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
756 730
757 if (state & INT_RBSYE) { 731 if (state & INT_RBSYE) {
758 sh_mmcif_writel(host, MMCIF_CE_INT, ~(INT_RBSYE | INT_CRSPE)); 732 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
733 ~(INT_RBSYE | INT_CRSPE));
759 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 734 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
760 } else if (state & INT_CRSPE) { 735 } else if (state & INT_CRSPE) {
761 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_CRSPE); 736 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
762 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 737 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
763 } else if (state & INT_BUFREN) { 738 } else if (state & INT_BUFREN) {
764 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFREN); 739 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
765 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 740 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
766 } else if (state & INT_BUFWEN) { 741 } else if (state & INT_BUFWEN) {
767 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFWEN); 742 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
768 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 743 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
769 } else if (state & INT_CMD12DRE) { 744 } else if (state & INT_CMD12DRE) {
770 sh_mmcif_writel(host, MMCIF_CE_INT, 745 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
771 ~(INT_CMD12DRE | INT_CMD12RBE | 746 ~(INT_CMD12DRE | INT_CMD12RBE |
772 INT_CMD12CRE | INT_BUFRE)); 747 INT_CMD12CRE | INT_BUFRE));
773 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 748 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
774 } else if (state & INT_BUFRE) { 749 } else if (state & INT_BUFRE) {
775 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_BUFRE); 750 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
776 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 751 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
777 } else if (state & INT_DTRANE) { 752 } else if (state & INT_DTRANE) {
778 sh_mmcif_writel(host, MMCIF_CE_INT, ~INT_DTRANE); 753 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
779 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 754 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
780 } else if (state & INT_CMD12RBE) { 755 } else if (state & INT_CMD12RBE) {
781 sh_mmcif_writel(host, MMCIF_CE_INT, 756 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
782 ~(INT_CMD12RBE | INT_CMD12CRE)); 757 ~(INT_CMD12RBE | INT_CMD12CRE));
783 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 758 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
784 } else if (state & INT_ERR_STS) { 759 } else if (state & INT_ERR_STS) {
785 /* err interrupts */ 760 /* err interrupts */
786 sh_mmcif_writel(host, MMCIF_CE_INT, ~state); 761 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
787 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 762 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
788 err = 1; 763 err = 1;
789 } else { 764 } else {
790 pr_debug("%s: Not support int\n", DRIVER_NAME); 765 pr_debug("%s: Not support int\n", DRIVER_NAME);
791 sh_mmcif_writel(host, MMCIF_CE_INT, ~state); 766 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
792 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 767 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
793 err = 1; 768 err = 1;
794 } 769 }
@@ -894,12 +869,12 @@ static int __devinit sh_mmcif_probe(struct platform_device *pdev)
894 goto clean_up2; 869 goto clean_up2;
895 } 870 }
896 871
897 sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL); 872 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
898 sh_mmcif_detect(host->mmc); 873 sh_mmcif_detect(host->mmc);
899 874
900 pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION); 875 pr_info("%s: driver version %s\n", DRIVER_NAME, DRIVER_VERSION);
901 pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME, 876 pr_debug("%s: chip ver H'%04x\n", DRIVER_NAME,
902 sh_mmcif_readl(host, MMCIF_CE_VERSION) & 0x0000ffff); 877 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
903 return ret; 878 return ret;
904 879
905clean_up2: 880clean_up2:
@@ -917,7 +892,7 @@ static int __devexit sh_mmcif_remove(struct platform_device *pdev)
917 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 892 struct sh_mmcif_host *host = platform_get_drvdata(pdev);
918 int irq[2]; 893 int irq[2];
919 894
920 sh_mmcif_writel(host, MMCIF_CE_INT_MASK, MASK_ALL); 895 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
921 896
922 irq[0] = platform_get_irq(pdev, 0); 897 irq[0] = platform_get_irq(pdev, 0);
923 irq[1] = platform_get_irq(pdev, 1); 898 irq[1] = platform_get_irq(pdev, 1);
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
index aafe832f18aa..e079c6beeb98 100644
--- a/include/linux/mmc/sh_mmcif.h
+++ b/include/linux/mmc/sh_mmcif.h
@@ -14,6 +14,9 @@
14#ifndef __SH_MMCIF_H__ 14#ifndef __SH_MMCIF_H__
15#define __SH_MMCIF_H__ 15#define __SH_MMCIF_H__
16 16
17#include <linux/platform_device.h>
18#include <linux/io.h>
19
17/* 20/*
18 * MMCIF : CE_CLK_CTRL [19:16] 21 * MMCIF : CE_CLK_CTRL [19:16]
19 * 1000 : Peripheral clock / 512 22 * 1000 : Peripheral clock / 512
@@ -36,4 +39,33 @@ struct sh_mmcif_plat_data {
36 u32 ocr; 39 u32 ocr;
37}; 40};
38 41
42#define MMCIF_CE_CMD_SET 0x00000000
43#define MMCIF_CE_ARG 0x00000008
44#define MMCIF_CE_ARG_CMD12 0x0000000C
45#define MMCIF_CE_CMD_CTRL 0x00000010
46#define MMCIF_CE_BLOCK_SET 0x00000014
47#define MMCIF_CE_CLK_CTRL 0x00000018
48#define MMCIF_CE_BUF_ACC 0x0000001C
49#define MMCIF_CE_RESP3 0x00000020
50#define MMCIF_CE_RESP2 0x00000024
51#define MMCIF_CE_RESP1 0x00000028
52#define MMCIF_CE_RESP0 0x0000002C
53#define MMCIF_CE_RESP_CMD12 0x00000030
54#define MMCIF_CE_DATA 0x00000034
55#define MMCIF_CE_INT 0x00000040
56#define MMCIF_CE_INT_MASK 0x00000044
57#define MMCIF_CE_HOST_STS1 0x00000048
58#define MMCIF_CE_HOST_STS2 0x0000004C
59#define MMCIF_CE_VERSION 0x0000007C
60
61extern inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
62{
63 return readl(addr + reg);
64}
65
66extern inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
67{
68 writel(val, addr + reg);
69}
70
39#endif /* __SH_MMCIF_H__ */ 71#endif /* __SH_MMCIF_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 14:52:11 -0500