diff options
-rw-r--r-- | drivers/spi/spi-bfin5xx.c | 208 |
1 files changed, 84 insertions, 124 deletions
diff --git a/drivers/spi/spi-bfin5xx.c b/drivers/spi/spi-bfin5xx.c index cc880c95e7de..733183186012 100644 --- a/drivers/spi/spi-bfin5xx.c +++ b/drivers/spi/spi-bfin5xx.c | |||
@@ -58,7 +58,7 @@ struct bfin_spi_master_data { | |||
58 | struct spi_master *master; | 58 | struct spi_master *master; |
59 | 59 | ||
60 | /* Regs base of SPI controller */ | 60 | /* Regs base of SPI controller */ |
61 | void __iomem *regs_base; | 61 | struct bfin_spi_regs __iomem *regs; |
62 | 62 | ||
63 | /* Pin request list */ | 63 | /* Pin request list */ |
64 | u16 *pin_req; | 64 | u16 *pin_req; |
@@ -122,34 +122,14 @@ struct bfin_spi_slave_data { | |||
122 | const struct bfin_spi_transfer_ops *ops; | 122 | const struct bfin_spi_transfer_ops *ops; |
123 | }; | 123 | }; |
124 | 124 | ||
125 | #define DEFINE_SPI_REG(reg, off) \ | ||
126 | static inline u16 read_##reg(struct bfin_spi_master_data *drv_data) \ | ||
127 | { return bfin_read16(drv_data->regs_base + off); } \ | ||
128 | static inline void write_##reg(struct bfin_spi_master_data *drv_data, u16 v) \ | ||
129 | { bfin_write16(drv_data->regs_base + off, v); } | ||
130 | |||
131 | DEFINE_SPI_REG(CTRL, 0x00) | ||
132 | DEFINE_SPI_REG(FLAG, 0x04) | ||
133 | DEFINE_SPI_REG(STAT, 0x08) | ||
134 | DEFINE_SPI_REG(TDBR, 0x0C) | ||
135 | DEFINE_SPI_REG(RDBR, 0x10) | ||
136 | DEFINE_SPI_REG(BAUD, 0x14) | ||
137 | DEFINE_SPI_REG(SHAW, 0x18) | ||
138 | |||
139 | static void bfin_spi_enable(struct bfin_spi_master_data *drv_data) | 125 | static void bfin_spi_enable(struct bfin_spi_master_data *drv_data) |
140 | { | 126 | { |
141 | u16 cr; | 127 | bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE); |
142 | |||
143 | cr = read_CTRL(drv_data); | ||
144 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | ||
145 | } | 128 | } |
146 | 129 | ||
147 | static void bfin_spi_disable(struct bfin_spi_master_data *drv_data) | 130 | static void bfin_spi_disable(struct bfin_spi_master_data *drv_data) |
148 | { | 131 | { |
149 | u16 cr; | 132 | bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE); |
150 | |||
151 | cr = read_CTRL(drv_data); | ||
152 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | ||
153 | } | 133 | } |
154 | 134 | ||
155 | /* Caculate the SPI_BAUD register value based on input HZ */ | 135 | /* Caculate the SPI_BAUD register value based on input HZ */ |
@@ -172,10 +152,10 @@ static int bfin_spi_flush(struct bfin_spi_master_data *drv_data) | |||
172 | unsigned long limit = loops_per_jiffy << 1; | 152 | unsigned long limit = loops_per_jiffy << 1; |
173 | 153 | ||
174 | /* wait for stop and clear stat */ | 154 | /* wait for stop and clear stat */ |
175 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit) | 155 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit) |
176 | cpu_relax(); | 156 | cpu_relax(); |
177 | 157 | ||
178 | write_STAT(drv_data, BIT_STAT_CLR); | 158 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
179 | 159 | ||
180 | return limit; | 160 | return limit; |
181 | } | 161 | } |
@@ -183,29 +163,19 @@ static int bfin_spi_flush(struct bfin_spi_master_data *drv_data) | |||
183 | /* Chip select operation functions for cs_change flag */ | 163 | /* Chip select operation functions for cs_change flag */ |
184 | static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip) | 164 | static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip) |
185 | { | 165 | { |
186 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { | 166 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) |
187 | u16 flag = read_FLAG(drv_data); | 167 | bfin_write_and(&drv_data->regs->flg, ~chip->flag); |
188 | 168 | else | |
189 | flag &= ~chip->flag; | ||
190 | |||
191 | write_FLAG(drv_data, flag); | ||
192 | } else { | ||
193 | gpio_set_value(chip->cs_gpio, 0); | 169 | gpio_set_value(chip->cs_gpio, 0); |
194 | } | ||
195 | } | 170 | } |
196 | 171 | ||
197 | static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data, | 172 | static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data, |
198 | struct bfin_spi_slave_data *chip) | 173 | struct bfin_spi_slave_data *chip) |
199 | { | 174 | { |
200 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { | 175 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) |
201 | u16 flag = read_FLAG(drv_data); | 176 | bfin_write_or(&drv_data->regs->flg, chip->flag); |
202 | 177 | else | |
203 | flag |= chip->flag; | ||
204 | |||
205 | write_FLAG(drv_data, flag); | ||
206 | } else { | ||
207 | gpio_set_value(chip->cs_gpio, 1); | 178 | gpio_set_value(chip->cs_gpio, 1); |
208 | } | ||
209 | 179 | ||
210 | /* Move delay here for consistency */ | 180 | /* Move delay here for consistency */ |
211 | if (chip->cs_chg_udelay) | 181 | if (chip->cs_chg_udelay) |
@@ -216,25 +186,15 @@ static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data, | |||
216 | static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data, | 186 | static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data, |
217 | struct bfin_spi_slave_data *chip) | 187 | struct bfin_spi_slave_data *chip) |
218 | { | 188 | { |
219 | if (chip->chip_select_num < MAX_CTRL_CS) { | 189 | if (chip->chip_select_num < MAX_CTRL_CS) |
220 | u16 flag = read_FLAG(drv_data); | 190 | bfin_write_or(&drv_data->regs->flg, chip->flag >> 8); |
221 | |||
222 | flag |= (chip->flag >> 8); | ||
223 | |||
224 | write_FLAG(drv_data, flag); | ||
225 | } | ||
226 | } | 191 | } |
227 | 192 | ||
228 | static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data, | 193 | static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data, |
229 | struct bfin_spi_slave_data *chip) | 194 | struct bfin_spi_slave_data *chip) |
230 | { | 195 | { |
231 | if (chip->chip_select_num < MAX_CTRL_CS) { | 196 | if (chip->chip_select_num < MAX_CTRL_CS) |
232 | u16 flag = read_FLAG(drv_data); | 197 | bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8)); |
233 | |||
234 | flag &= ~(chip->flag >> 8); | ||
235 | |||
236 | write_FLAG(drv_data, flag); | ||
237 | } | ||
238 | } | 198 | } |
239 | 199 | ||
240 | /* stop controller and re-config current chip*/ | 200 | /* stop controller and re-config current chip*/ |
@@ -243,15 +203,15 @@ static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data) | |||
243 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; | 203 | struct bfin_spi_slave_data *chip = drv_data->cur_chip; |
244 | 204 | ||
245 | /* Clear status and disable clock */ | 205 | /* Clear status and disable clock */ |
246 | write_STAT(drv_data, BIT_STAT_CLR); | 206 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
247 | bfin_spi_disable(drv_data); | 207 | bfin_spi_disable(drv_data); |
248 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); | 208 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
249 | 209 | ||
250 | SSYNC(); | 210 | SSYNC(); |
251 | 211 | ||
252 | /* Load the registers */ | 212 | /* Load the registers */ |
253 | write_CTRL(drv_data, chip->ctl_reg); | 213 | bfin_write(&drv_data->regs->ctl, chip->ctl_reg); |
254 | write_BAUD(drv_data, chip->baud); | 214 | bfin_write(&drv_data->regs->baud, chip->baud); |
255 | 215 | ||
256 | bfin_spi_enable(drv_data); | 216 | bfin_spi_enable(drv_data); |
257 | bfin_spi_cs_active(drv_data, chip); | 217 | bfin_spi_cs_active(drv_data, chip); |
@@ -260,7 +220,7 @@ static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data) | |||
260 | /* used to kick off transfer in rx mode and read unwanted RX data */ | 220 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
261 | static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data) | 221 | static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data) |
262 | { | 222 | { |
263 | (void) read_RDBR(drv_data); | 223 | (void) bfin_read(&drv_data->regs->rdbr); |
264 | } | 224 | } |
265 | 225 | ||
266 | static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data) | 226 | static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data) |
@@ -269,10 +229,10 @@ static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data) | |||
269 | bfin_spi_dummy_read(drv_data); | 229 | bfin_spi_dummy_read(drv_data); |
270 | 230 | ||
271 | while (drv_data->tx < drv_data->tx_end) { | 231 | while (drv_data->tx < drv_data->tx_end) { |
272 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); | 232 | bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++))); |
273 | /* wait until transfer finished. | 233 | /* wait until transfer finished. |
274 | checking SPIF or TXS may not guarantee transfer completion */ | 234 | checking SPIF or TXS may not guarantee transfer completion */ |
275 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | 235 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
276 | cpu_relax(); | 236 | cpu_relax(); |
277 | /* discard RX data and clear RXS */ | 237 | /* discard RX data and clear RXS */ |
278 | bfin_spi_dummy_read(drv_data); | 238 | bfin_spi_dummy_read(drv_data); |
@@ -287,10 +247,10 @@ static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data) | |||
287 | bfin_spi_dummy_read(drv_data); | 247 | bfin_spi_dummy_read(drv_data); |
288 | 248 | ||
289 | while (drv_data->rx < drv_data->rx_end) { | 249 | while (drv_data->rx < drv_data->rx_end) { |
290 | write_TDBR(drv_data, tx_val); | 250 | bfin_write(&drv_data->regs->tdbr, tx_val); |
291 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | 251 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
292 | cpu_relax(); | 252 | cpu_relax(); |
293 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); | 253 | *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr); |
294 | } | 254 | } |
295 | } | 255 | } |
296 | 256 | ||
@@ -300,10 +260,10 @@ static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data) | |||
300 | bfin_spi_dummy_read(drv_data); | 260 | bfin_spi_dummy_read(drv_data); |
301 | 261 | ||
302 | while (drv_data->rx < drv_data->rx_end) { | 262 | while (drv_data->rx < drv_data->rx_end) { |
303 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); | 263 | bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++))); |
304 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | 264 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
305 | cpu_relax(); | 265 | cpu_relax(); |
306 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); | 266 | *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr); |
307 | } | 267 | } |
308 | } | 268 | } |
309 | 269 | ||
@@ -319,11 +279,11 @@ static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data) | |||
319 | bfin_spi_dummy_read(drv_data); | 279 | bfin_spi_dummy_read(drv_data); |
320 | 280 | ||
321 | while (drv_data->tx < drv_data->tx_end) { | 281 | while (drv_data->tx < drv_data->tx_end) { |
322 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | 282 | bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx))); |
323 | drv_data->tx += 2; | 283 | drv_data->tx += 2; |
324 | /* wait until transfer finished. | 284 | /* wait until transfer finished. |
325 | checking SPIF or TXS may not guarantee transfer completion */ | 285 | checking SPIF or TXS may not guarantee transfer completion */ |
326 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | 286 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
327 | cpu_relax(); | 287 | cpu_relax(); |
328 | /* discard RX data and clear RXS */ | 288 | /* discard RX data and clear RXS */ |
329 | bfin_spi_dummy_read(drv_data); | 289 | bfin_spi_dummy_read(drv_data); |
@@ -338,10 +298,10 @@ static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data) | |||
338 | bfin_spi_dummy_read(drv_data); | 298 | bfin_spi_dummy_read(drv_data); |
339 | 299 | ||
340 | while (drv_data->rx < drv_data->rx_end) { | 300 | while (drv_data->rx < drv_data->rx_end) { |
341 | write_TDBR(drv_data, tx_val); | 301 | bfin_write(&drv_data->regs->tdbr, tx_val); |
342 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | 302 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
343 | cpu_relax(); | 303 | cpu_relax(); |
344 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | 304 | *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr); |
345 | drv_data->rx += 2; | 305 | drv_data->rx += 2; |
346 | } | 306 | } |
347 | } | 307 | } |
@@ -352,11 +312,11 @@ static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data) | |||
352 | bfin_spi_dummy_read(drv_data); | 312 | bfin_spi_dummy_read(drv_data); |
353 | 313 | ||
354 | while (drv_data->rx < drv_data->rx_end) { | 314 | while (drv_data->rx < drv_data->rx_end) { |
355 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | 315 | bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx))); |
356 | drv_data->tx += 2; | 316 | drv_data->tx += 2; |
357 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | 317 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
358 | cpu_relax(); | 318 | cpu_relax(); |
359 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | 319 | *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr); |
360 | drv_data->rx += 2; | 320 | drv_data->rx += 2; |
361 | } | 321 | } |
362 | } | 322 | } |
@@ -428,7 +388,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |||
428 | int loop = 0; | 388 | int loop = 0; |
429 | 389 | ||
430 | /* wait until transfer finished. */ | 390 | /* wait until transfer finished. */ |
431 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | 391 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS)) |
432 | cpu_relax(); | 392 | cpu_relax(); |
433 | 393 | ||
434 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || | 394 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || |
@@ -439,11 +399,11 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |||
439 | if (n_bytes % 2) { | 399 | if (n_bytes % 2) { |
440 | u16 *buf = (u16 *)drv_data->rx; | 400 | u16 *buf = (u16 *)drv_data->rx; |
441 | for (loop = 0; loop < n_bytes / 2; loop++) | 401 | for (loop = 0; loop < n_bytes / 2; loop++) |
442 | *buf++ = read_RDBR(drv_data); | 402 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
443 | } else { | 403 | } else { |
444 | u8 *buf = (u8 *)drv_data->rx; | 404 | u8 *buf = (u8 *)drv_data->rx; |
445 | for (loop = 0; loop < n_bytes; loop++) | 405 | for (loop = 0; loop < n_bytes; loop++) |
446 | *buf++ = read_RDBR(drv_data); | 406 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
447 | } | 407 | } |
448 | drv_data->rx += n_bytes; | 408 | drv_data->rx += n_bytes; |
449 | } | 409 | } |
@@ -468,15 +428,15 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |||
468 | u16 *buf = (u16 *)drv_data->rx; | 428 | u16 *buf = (u16 *)drv_data->rx; |
469 | u16 *buf2 = (u16 *)drv_data->tx; | 429 | u16 *buf2 = (u16 *)drv_data->tx; |
470 | for (loop = 0; loop < n_bytes / 2; loop++) { | 430 | for (loop = 0; loop < n_bytes / 2; loop++) { |
471 | *buf++ = read_RDBR(drv_data); | 431 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
472 | write_TDBR(drv_data, *buf2++); | 432 | bfin_write(&drv_data->regs->tdbr, *buf2++); |
473 | } | 433 | } |
474 | } else { | 434 | } else { |
475 | u8 *buf = (u8 *)drv_data->rx; | 435 | u8 *buf = (u8 *)drv_data->rx; |
476 | u8 *buf2 = (u8 *)drv_data->tx; | 436 | u8 *buf2 = (u8 *)drv_data->tx; |
477 | for (loop = 0; loop < n_bytes; loop++) { | 437 | for (loop = 0; loop < n_bytes; loop++) { |
478 | *buf++ = read_RDBR(drv_data); | 438 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
479 | write_TDBR(drv_data, *buf2++); | 439 | bfin_write(&drv_data->regs->tdbr, *buf2++); |
480 | } | 440 | } |
481 | } | 441 | } |
482 | } else if (drv_data->rx) { | 442 | } else if (drv_data->rx) { |
@@ -485,14 +445,14 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |||
485 | if (n_bytes % 2) { | 445 | if (n_bytes % 2) { |
486 | u16 *buf = (u16 *)drv_data->rx; | 446 | u16 *buf = (u16 *)drv_data->rx; |
487 | for (loop = 0; loop < n_bytes / 2; loop++) { | 447 | for (loop = 0; loop < n_bytes / 2; loop++) { |
488 | *buf++ = read_RDBR(drv_data); | 448 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
489 | write_TDBR(drv_data, chip->idle_tx_val); | 449 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); |
490 | } | 450 | } |
491 | } else { | 451 | } else { |
492 | u8 *buf = (u8 *)drv_data->rx; | 452 | u8 *buf = (u8 *)drv_data->rx; |
493 | for (loop = 0; loop < n_bytes; loop++) { | 453 | for (loop = 0; loop < n_bytes; loop++) { |
494 | *buf++ = read_RDBR(drv_data); | 454 | *buf++ = bfin_read(&drv_data->regs->rdbr); |
495 | write_TDBR(drv_data, chip->idle_tx_val); | 455 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); |
496 | } | 456 | } |
497 | } | 457 | } |
498 | } else if (drv_data->tx) { | 458 | } else if (drv_data->tx) { |
@@ -501,14 +461,14 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |||
501 | if (n_bytes % 2) { | 461 | if (n_bytes % 2) { |
502 | u16 *buf = (u16 *)drv_data->tx; | 462 | u16 *buf = (u16 *)drv_data->tx; |
503 | for (loop = 0; loop < n_bytes / 2; loop++) { | 463 | for (loop = 0; loop < n_bytes / 2; loop++) { |
504 | read_RDBR(drv_data); | 464 | bfin_read(&drv_data->regs->rdbr); |
505 | write_TDBR(drv_data, *buf++); | 465 | bfin_write(&drv_data->regs->tdbr, *buf++); |
506 | } | 466 | } |
507 | } else { | 467 | } else { |
508 | u8 *buf = (u8 *)drv_data->tx; | 468 | u8 *buf = (u8 *)drv_data->tx; |
509 | for (loop = 0; loop < n_bytes; loop++) { | 469 | for (loop = 0; loop < n_bytes; loop++) { |
510 | read_RDBR(drv_data); | 470 | bfin_read(&drv_data->regs->rdbr); |
511 | write_TDBR(drv_data, *buf++); | 471 | bfin_write(&drv_data->regs->tdbr, *buf++); |
512 | } | 472 | } |
513 | } | 473 | } |
514 | } | 474 | } |
@@ -528,19 +488,19 @@ static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) | |||
528 | struct spi_message *msg = drv_data->cur_msg; | 488 | struct spi_message *msg = drv_data->cur_msg; |
529 | unsigned long timeout; | 489 | unsigned long timeout; |
530 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); | 490 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
531 | u16 spistat = read_STAT(drv_data); | 491 | u16 spistat = bfin_read(&drv_data->regs->stat); |
532 | 492 | ||
533 | dev_dbg(&drv_data->pdev->dev, | 493 | dev_dbg(&drv_data->pdev->dev, |
534 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | 494 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", |
535 | dmastat, spistat); | 495 | dmastat, spistat); |
536 | 496 | ||
537 | if (drv_data->rx != NULL) { | 497 | if (drv_data->rx != NULL) { |
538 | u16 cr = read_CTRL(drv_data); | 498 | u16 cr = bfin_read(&drv_data->regs->ctl); |
539 | /* discard old RX data and clear RXS */ | 499 | /* discard old RX data and clear RXS */ |
540 | bfin_spi_dummy_read(drv_data); | 500 | bfin_spi_dummy_read(drv_data); |
541 | write_CTRL(drv_data, cr & ~BIT_CTL_ENABLE); /* Disable SPI */ | 501 | bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */ |
542 | write_CTRL(drv_data, cr & ~BIT_CTL_TIMOD); /* Restore State */ | 502 | bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */ |
543 | write_STAT(drv_data, BIT_STAT_CLR); /* Clear Status */ | 503 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */ |
544 | } | 504 | } |
545 | 505 | ||
546 | clear_dma_irqstat(drv_data->dma_channel); | 506 | clear_dma_irqstat(drv_data->dma_channel); |
@@ -552,17 +512,17 @@ static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) | |||
552 | * register until it goes low for 2 successive reads | 512 | * register until it goes low for 2 successive reads |
553 | */ | 513 | */ |
554 | if (drv_data->tx != NULL) { | 514 | if (drv_data->tx != NULL) { |
555 | while ((read_STAT(drv_data) & BIT_STAT_TXS) || | 515 | while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) || |
556 | (read_STAT(drv_data) & BIT_STAT_TXS)) | 516 | (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS)) |
557 | cpu_relax(); | 517 | cpu_relax(); |
558 | } | 518 | } |
559 | 519 | ||
560 | dev_dbg(&drv_data->pdev->dev, | 520 | dev_dbg(&drv_data->pdev->dev, |
561 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | 521 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", |
562 | dmastat, read_STAT(drv_data)); | 522 | dmastat, bfin_read(&drv_data->regs->stat)); |
563 | 523 | ||
564 | timeout = jiffies + HZ; | 524 | timeout = jiffies + HZ; |
565 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) | 525 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF)) |
566 | if (!time_before(jiffies, timeout)) { | 526 | if (!time_before(jiffies, timeout)) { |
567 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | 527 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); |
568 | break; | 528 | break; |
@@ -699,9 +659,9 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
699 | bfin_spi_giveback(drv_data); | 659 | bfin_spi_giveback(drv_data); |
700 | return; | 660 | return; |
701 | } | 661 | } |
702 | cr = read_CTRL(drv_data) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE); | 662 | cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE); |
703 | cr |= cr_width; | 663 | cr |= cr_width; |
704 | write_CTRL(drv_data, cr); | 664 | bfin_write(&drv_data->regs->ctl, cr); |
705 | 665 | ||
706 | dev_dbg(&drv_data->pdev->dev, | 666 | dev_dbg(&drv_data->pdev->dev, |
707 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", | 667 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", |
@@ -712,11 +672,11 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
712 | 672 | ||
713 | /* Speed setup (surely valid because already checked) */ | 673 | /* Speed setup (surely valid because already checked) */ |
714 | if (transfer->speed_hz) | 674 | if (transfer->speed_hz) |
715 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | 675 | bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz)); |
716 | else | 676 | else |
717 | write_BAUD(drv_data, chip->baud); | 677 | bfin_write(&drv_data->regs->baud, chip->baud); |
718 | 678 | ||
719 | write_STAT(drv_data, BIT_STAT_CLR); | 679 | bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); |
720 | bfin_spi_cs_active(drv_data, chip); | 680 | bfin_spi_cs_active(drv_data, chip); |
721 | 681 | ||
722 | dev_dbg(&drv_data->pdev->dev, | 682 | dev_dbg(&drv_data->pdev->dev, |
@@ -749,7 +709,7 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
749 | } | 709 | } |
750 | 710 | ||
751 | /* poll for SPI completion before start */ | 711 | /* poll for SPI completion before start */ |
752 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) | 712 | while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF)) |
753 | cpu_relax(); | 713 | cpu_relax(); |
754 | 714 | ||
755 | /* dirty hack for autobuffer DMA mode */ | 715 | /* dirty hack for autobuffer DMA mode */ |
@@ -766,7 +726,7 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
766 | enable_dma(drv_data->dma_channel); | 726 | enable_dma(drv_data->dma_channel); |
767 | 727 | ||
768 | /* start SPI transfer */ | 728 | /* start SPI transfer */ |
769 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); | 729 | bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX); |
770 | 730 | ||
771 | /* just return here, there can only be one transfer | 731 | /* just return here, there can only be one transfer |
772 | * in this mode | 732 | * in this mode |
@@ -821,7 +781,7 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
821 | set_dma_config(drv_data->dma_channel, dma_config); | 781 | set_dma_config(drv_data->dma_channel, dma_config); |
822 | local_irq_save(flags); | 782 | local_irq_save(flags); |
823 | SSYNC(); | 783 | SSYNC(); |
824 | write_CTRL(drv_data, cr); | 784 | bfin_write(&drv_data->regs->ctl, cr); |
825 | enable_dma(drv_data->dma_channel); | 785 | enable_dma(drv_data->dma_channel); |
826 | dma_enable_irq(drv_data->dma_channel); | 786 | dma_enable_irq(drv_data->dma_channel); |
827 | local_irq_restore(flags); | 787 | local_irq_restore(flags); |
@@ -835,7 +795,7 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
835 | * problems with setting up the output value in TDBR prior to the | 795 | * problems with setting up the output value in TDBR prior to the |
836 | * start of the transfer. | 796 | * start of the transfer. |
837 | */ | 797 | */ |
838 | write_CTRL(drv_data, cr | BIT_CTL_TXMOD); | 798 | bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD); |
839 | 799 | ||
840 | if (chip->pio_interrupt) { | 800 | if (chip->pio_interrupt) { |
841 | /* SPI irq should have been disabled by now */ | 801 | /* SPI irq should have been disabled by now */ |
@@ -845,19 +805,19 @@ static void bfin_spi_pump_transfers(unsigned long data) | |||
845 | 805 | ||
846 | /* start transfer */ | 806 | /* start transfer */ |
847 | if (drv_data->tx == NULL) | 807 | if (drv_data->tx == NULL) |
848 | write_TDBR(drv_data, chip->idle_tx_val); | 808 | bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val); |
849 | else { | 809 | else { |
850 | int loop; | 810 | int loop; |
851 | if (bits_per_word % 16 == 0) { | 811 | if (bits_per_word % 16 == 0) { |
852 | u16 *buf = (u16 *)drv_data->tx; | 812 | u16 *buf = (u16 *)drv_data->tx; |
853 | for (loop = 0; loop < bits_per_word / 16; | 813 | for (loop = 0; loop < bits_per_word / 16; |
854 | loop++) { | 814 | loop++) { |
855 | write_TDBR(drv_data, *buf++); | 815 | bfin_write(&drv_data->regs->tdbr, *buf++); |
856 | } | 816 | } |
857 | } else if (bits_per_word % 8 == 0) { | 817 | } else if (bits_per_word % 8 == 0) { |
858 | u8 *buf = (u8 *)drv_data->tx; | 818 | u8 *buf = (u8 *)drv_data->tx; |
859 | for (loop = 0; loop < bits_per_word / 8; loop++) | 819 | for (loop = 0; loop < bits_per_word / 8; loop++) |
860 | write_TDBR(drv_data, *buf++); | 820 | bfin_write(&drv_data->regs->tdbr, *buf++); |
861 | } | 821 | } |
862 | 822 | ||
863 | drv_data->tx += drv_data->n_bytes; | 823 | drv_data->tx += drv_data->n_bytes; |
@@ -1353,8 +1313,8 @@ static int __init bfin_spi_probe(struct platform_device *pdev) | |||
1353 | goto out_error_get_res; | 1313 | goto out_error_get_res; |
1354 | } | 1314 | } |
1355 | 1315 | ||
1356 | drv_data->regs_base = ioremap(res->start, resource_size(res)); | 1316 | drv_data->regs = ioremap(res->start, resource_size(res)); |
1357 | if (drv_data->regs_base == NULL) { | 1317 | if (drv_data->regs == NULL) { |
1358 | dev_err(dev, "Cannot map IO\n"); | 1318 | dev_err(dev, "Cannot map IO\n"); |
1359 | status = -ENXIO; | 1319 | status = -ENXIO; |
1360 | goto out_error_ioremap; | 1320 | goto out_error_ioremap; |
@@ -1397,8 +1357,8 @@ static int __init bfin_spi_probe(struct platform_device *pdev) | |||
1397 | /* Reset SPI registers. If these registers were used by the boot loader, | 1357 | /* Reset SPI registers. If these registers were used by the boot loader, |
1398 | * the sky may fall on your head if you enable the dma controller. | 1358 | * the sky may fall on your head if you enable the dma controller. |
1399 | */ | 1359 | */ |
1400 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | 1360 | bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER); |
1401 | write_FLAG(drv_data, 0xFF00); | 1361 | bfin_write(&drv_data->regs->flg, 0xFF00); |
1402 | 1362 | ||
1403 | /* Register with the SPI framework */ | 1363 | /* Register with the SPI framework */ |
1404 | platform_set_drvdata(pdev, drv_data); | 1364 | platform_set_drvdata(pdev, drv_data); |
@@ -1408,15 +1368,15 @@ static int __init bfin_spi_probe(struct platform_device *pdev) | |||
1408 | goto out_error_queue_alloc; | 1368 | goto out_error_queue_alloc; |
1409 | } | 1369 | } |
1410 | 1370 | ||
1411 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", | 1371 | dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n", |
1412 | DRV_DESC, DRV_VERSION, drv_data->regs_base, | 1372 | DRV_DESC, DRV_VERSION, drv_data->regs, |
1413 | drv_data->dma_channel); | 1373 | drv_data->dma_channel); |
1414 | return status; | 1374 | return status; |
1415 | 1375 | ||
1416 | out_error_queue_alloc: | 1376 | out_error_queue_alloc: |
1417 | bfin_spi_destroy_queue(drv_data); | 1377 | bfin_spi_destroy_queue(drv_data); |
1418 | out_error_free_io: | 1378 | out_error_free_io: |
1419 | iounmap((void *) drv_data->regs_base); | 1379 | iounmap(drv_data->regs); |
1420 | out_error_ioremap: | 1380 | out_error_ioremap: |
1421 | out_error_get_res: | 1381 | out_error_get_res: |
1422 | spi_master_put(master); | 1382 | spi_master_put(master); |
@@ -1473,14 +1433,14 @@ static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) | |||
1473 | if (status != 0) | 1433 | if (status != 0) |
1474 | return status; | 1434 | return status; |
1475 | 1435 | ||
1476 | drv_data->ctrl_reg = read_CTRL(drv_data); | 1436 | drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl); |
1477 | drv_data->flag_reg = read_FLAG(drv_data); | 1437 | drv_data->flag_reg = bfin_read(&drv_data->regs->flg); |
1478 | 1438 | ||
1479 | /* | 1439 | /* |
1480 | * reset SPI_CTL and SPI_FLG registers | 1440 | * reset SPI_CTL and SPI_FLG registers |
1481 | */ | 1441 | */ |
1482 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | 1442 | bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER); |
1483 | write_FLAG(drv_data, 0xFF00); | 1443 | bfin_write(&drv_data->regs->flg, 0xFF00); |
1484 | 1444 | ||
1485 | return 0; | 1445 | return 0; |
1486 | } | 1446 | } |
@@ -1490,8 +1450,8 @@ static int bfin_spi_resume(struct platform_device *pdev) | |||
1490 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); | 1450 | struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev); |
1491 | int status = 0; | 1451 | int status = 0; |
1492 | 1452 | ||
1493 | write_CTRL(drv_data, drv_data->ctrl_reg); | 1453 | bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg); |
1494 | write_FLAG(drv_data, drv_data->flag_reg); | 1454 | bfin_write(&drv_data->regs->flg, drv_data->flag_reg); |
1495 | 1455 | ||
1496 | /* Start the queue running */ | 1456 | /* Start the queue running */ |
1497 | status = bfin_spi_start_queue(drv_data); | 1457 | status = bfin_spi_start_queue(drv_data); |