aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--MAINTAINERS2
-rw-r--r--drivers/gpu/drm/exynos/exynos_dp_core.c4
-rw-r--r--drivers/gpu/drm/gma500/cdv_intel_dp.c4
-rw-r--r--drivers/gpu/drm/gma500/intel_bios.c16
-rw-r--r--drivers/gpu/drm/i915/dvo_ns2501.c560
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c124
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c7
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c38
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h63
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c51
-rw-r--r--drivers/gpu/drm/i915/i915_gem_context.c65
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c82
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.h3
-rw-r--r--drivers/gpu/drm/i915/i915_gem_render_state.c40
-rw-r--r--drivers/gpu/drm/i915/i915_gem_render_state.h47
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c9
-rw-r--r--drivers/gpu/drm/i915/i915_gpu_error.c106
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c185
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h35
-rw-r--r--drivers/gpu/drm/i915/i915_sysfs.c2
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c16
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c217
-rw-r--r--drivers/gpu/drm/i915/intel_display.c479
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c1188
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h24
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c11
-rw-r--r--drivers/gpu/drm/i915/intel_fbdev.c39
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c145
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c78
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.h2
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c29
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c508
-rw-r--r--drivers/gpu/drm/i915/intel_renderstate.h8
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c161
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h2
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c19
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c6
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c4
-rw-r--r--drivers/gpu/drm/tegra/dpaux.c4
-rw-r--r--include/drm/drm_dp_helper.h16
40 files changed, 2911 insertions, 1488 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 809ecd680d88..dd31933400e8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3091,7 +3091,7 @@ F: include/drm/drm_panel.h
3091F: Documentation/devicetree/bindings/panel/ 3091F: Documentation/devicetree/bindings/panel/
3092 3092
3093INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets) 3093INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
3094M: Daniel Vetter <daniel.vetter@ffwll.ch> 3094M: Daniel Vetter <daniel.vetter@intel.com>
3095M: Jani Nikula <jani.nikula@linux.intel.com> 3095M: Jani Nikula <jani.nikula@linux.intel.com>
3096L: intel-gfx@lists.freedesktop.org 3096L: intel-gfx@lists.freedesktop.org
3097L: dri-devel@lists.freedesktop.org 3097L: dri-devel@lists.freedesktop.org
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 4f3c7eb2d37d..02602a8254c4 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -329,8 +329,8 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
329 return retval; 329 return retval;
330 330
331 for (lane = 0; lane < lane_count; lane++) 331 for (lane = 0; lane < lane_count; lane++)
332 buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 | 332 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
333 DP_TRAIN_VOLTAGE_SWING_400; 333 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
334 334
335 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, 335 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
336 lane_count, buf); 336 lane_count, buf);
diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c
index a4cc0e60a1be..9f158eab517a 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
@@ -1089,7 +1089,7 @@ static char *link_train_names[] = {
1089}; 1089};
1090#endif 1090#endif
1091 1091
1092#define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 1092#define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
1093/* 1093/*
1094static uint8_t 1094static uint8_t
1095cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing) 1095cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
@@ -1276,7 +1276,7 @@ cdv_intel_dp_set_vswing_premph(struct gma_encoder *encoder, uint8_t signal_level
1276 cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]); 1276 cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
1277 1277
1278 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */ 1278 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
1279 if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200) 1279 if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
1280 cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040); 1280 cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
1281 else 1281 else
1282 cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040); 1282 cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
diff --git a/drivers/gpu/drm/gma500/intel_bios.c b/drivers/gpu/drm/gma500/intel_bios.c
index d3497348c4d5..63bde4e86c6a 100644
--- a/drivers/gpu/drm/gma500/intel_bios.c
+++ b/drivers/gpu/drm/gma500/intel_bios.c
@@ -116,30 +116,30 @@ parse_edp(struct drm_psb_private *dev_priv, struct bdb_header *bdb)
116 116
117 switch (edp_link_params->preemphasis) { 117 switch (edp_link_params->preemphasis) {
118 case 0: 118 case 0:
119 dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_0; 119 dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
120 break; 120 break;
121 case 1: 121 case 1:
122 dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5; 122 dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
123 break; 123 break;
124 case 2: 124 case 2:
125 dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_6; 125 dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
126 break; 126 break;
127 case 3: 127 case 3:
128 dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5; 128 dev_priv->edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
129 break; 129 break;
130 } 130 }
131 switch (edp_link_params->vswing) { 131 switch (edp_link_params->vswing) {
132 case 0: 132 case 0:
133 dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_400; 133 dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
134 break; 134 break;
135 case 1: 135 case 1:
136 dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_600; 136 dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
137 break; 137 break;
138 case 2: 138 case 2:
139 dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_800; 139 dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
140 break; 140 break;
141 case 3: 141 case 3:
142 dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_1200; 142 dev_priv->edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
143 break; 143 break;
144 } 144 }
145 DRM_DEBUG_KMS("VBT reports EDP: VSwing %d, Preemph %d\n", 145 DRM_DEBUG_KMS("VBT reports EDP: VSwing %d, Preemph %d\n",
diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo_ns2501.c
index 74f2af7c2d3e..441630434d34 100644
--- a/drivers/gpu/drm/i915/dvo_ns2501.c
+++ b/drivers/gpu/drm/i915/dvo_ns2501.c
@@ -60,16 +60,297 @@
60 60
61#define NS2501_REGC 0x0c 61#define NS2501_REGC 0x0c
62 62
63enum {
64 MODE_640x480,
65 MODE_800x600,
66 MODE_1024x768,
67};
68
69struct ns2501_reg {
70 uint8_t offset;
71 uint8_t value;
72};
73
74/*
75 * Magic values based on what the BIOS on
76 * Fujitsu-Siemens Lifebook S6010 programs (1024x768 panel).
77 */
78static const struct ns2501_reg regs_1024x768[][86] = {
79 [MODE_640x480] = {
80 [0] = { .offset = 0x0a, .value = 0x81, },
81 [1] = { .offset = 0x18, .value = 0x07, },
82 [2] = { .offset = 0x19, .value = 0x00, },
83 [3] = { .offset = 0x1a, .value = 0x00, },
84 [4] = { .offset = 0x1b, .value = 0x11, },
85 [5] = { .offset = 0x1c, .value = 0x54, },
86 [6] = { .offset = 0x1d, .value = 0x03, },
87 [7] = { .offset = 0x1e, .value = 0x02, },
88 [8] = { .offset = 0xf3, .value = 0x90, },
89 [9] = { .offset = 0xf9, .value = 0x00, },
90 [10] = { .offset = 0xc1, .value = 0x90, },
91 [11] = { .offset = 0xc2, .value = 0x00, },
92 [12] = { .offset = 0xc3, .value = 0x0f, },
93 [13] = { .offset = 0xc4, .value = 0x03, },
94 [14] = { .offset = 0xc5, .value = 0x16, },
95 [15] = { .offset = 0xc6, .value = 0x00, },
96 [16] = { .offset = 0xc7, .value = 0x02, },
97 [17] = { .offset = 0xc8, .value = 0x02, },
98 [18] = { .offset = 0xf4, .value = 0x00, },
99 [19] = { .offset = 0x80, .value = 0xff, },
100 [20] = { .offset = 0x81, .value = 0x07, },
101 [21] = { .offset = 0x82, .value = 0x3d, },
102 [22] = { .offset = 0x83, .value = 0x05, },
103 [23] = { .offset = 0x94, .value = 0x00, },
104 [24] = { .offset = 0x95, .value = 0x00, },
105 [25] = { .offset = 0x96, .value = 0x05, },
106 [26] = { .offset = 0x97, .value = 0x00, },
107 [27] = { .offset = 0x9a, .value = 0x88, },
108 [28] = { .offset = 0x9b, .value = 0x00, },
109 [29] = { .offset = 0x98, .value = 0x00, },
110 [30] = { .offset = 0x99, .value = 0x00, },
111 [31] = { .offset = 0xf7, .value = 0x88, },
112 [32] = { .offset = 0xf8, .value = 0x0a, },
113 [33] = { .offset = 0x9c, .value = 0x24, },
114 [34] = { .offset = 0x9d, .value = 0x00, },
115 [35] = { .offset = 0x9e, .value = 0x25, },
116 [36] = { .offset = 0x9f, .value = 0x03, },
117 [37] = { .offset = 0xa0, .value = 0x28, },
118 [38] = { .offset = 0xa1, .value = 0x01, },
119 [39] = { .offset = 0xa2, .value = 0x28, },
120 [40] = { .offset = 0xa3, .value = 0x05, },
121 [41] = { .offset = 0xb6, .value = 0x09, },
122 [42] = { .offset = 0xb8, .value = 0x00, },
123 [43] = { .offset = 0xb9, .value = 0xa0, },
124 [44] = { .offset = 0xba, .value = 0x00, },
125 [45] = { .offset = 0xbb, .value = 0x20, },
126 [46] = { .offset = 0x10, .value = 0x00, },
127 [47] = { .offset = 0x11, .value = 0xa0, },
128 [48] = { .offset = 0x12, .value = 0x02, },
129 [49] = { .offset = 0x20, .value = 0x00, },
130 [50] = { .offset = 0x22, .value = 0x00, },
131 [51] = { .offset = 0x23, .value = 0x00, },
132 [52] = { .offset = 0x24, .value = 0x00, },
133 [53] = { .offset = 0x25, .value = 0x00, },
134 [54] = { .offset = 0x8c, .value = 0x10, },
135 [55] = { .offset = 0x8d, .value = 0x02, },
136 [56] = { .offset = 0x8e, .value = 0x10, },
137 [57] = { .offset = 0x8f, .value = 0x00, },
138 [58] = { .offset = 0x90, .value = 0xff, },
139 [59] = { .offset = 0x91, .value = 0x07, },
140 [60] = { .offset = 0x92, .value = 0xa0, },
141 [61] = { .offset = 0x93, .value = 0x02, },
142 [62] = { .offset = 0xa5, .value = 0x00, },
143 [63] = { .offset = 0xa6, .value = 0x00, },
144 [64] = { .offset = 0xa7, .value = 0x00, },
145 [65] = { .offset = 0xa8, .value = 0x00, },
146 [66] = { .offset = 0xa9, .value = 0x04, },
147 [67] = { .offset = 0xaa, .value = 0x70, },
148 [68] = { .offset = 0xab, .value = 0x4f, },
149 [69] = { .offset = 0xac, .value = 0x00, },
150 [70] = { .offset = 0xa4, .value = 0x84, },
151 [71] = { .offset = 0x7e, .value = 0x18, },
152 [72] = { .offset = 0x84, .value = 0x00, },
153 [73] = { .offset = 0x85, .value = 0x00, },
154 [74] = { .offset = 0x86, .value = 0x00, },
155 [75] = { .offset = 0x87, .value = 0x00, },
156 [76] = { .offset = 0x88, .value = 0x00, },
157 [77] = { .offset = 0x89, .value = 0x00, },
158 [78] = { .offset = 0x8a, .value = 0x00, },
159 [79] = { .offset = 0x8b, .value = 0x00, },
160 [80] = { .offset = 0x26, .value = 0x00, },
161 [81] = { .offset = 0x27, .value = 0x00, },
162 [82] = { .offset = 0xad, .value = 0x00, },
163 [83] = { .offset = 0x08, .value = 0x30, }, /* 0x31 */
164 [84] = { .offset = 0x41, .value = 0x00, },
165 [85] = { .offset = 0xc0, .value = 0x05, },
166 },
167 [MODE_800x600] = {
168 [0] = { .offset = 0x0a, .value = 0x81, },
169 [1] = { .offset = 0x18, .value = 0x07, },
170 [2] = { .offset = 0x19, .value = 0x00, },
171 [3] = { .offset = 0x1a, .value = 0x00, },
172 [4] = { .offset = 0x1b, .value = 0x19, },
173 [5] = { .offset = 0x1c, .value = 0x64, },
174 [6] = { .offset = 0x1d, .value = 0x02, },
175 [7] = { .offset = 0x1e, .value = 0x02, },
176 [8] = { .offset = 0xf3, .value = 0x90, },
177 [9] = { .offset = 0xf9, .value = 0x00, },
178 [10] = { .offset = 0xc1, .value = 0xd7, },
179 [11] = { .offset = 0xc2, .value = 0x00, },
180 [12] = { .offset = 0xc3, .value = 0xf8, },
181 [13] = { .offset = 0xc4, .value = 0x03, },
182 [14] = { .offset = 0xc5, .value = 0x1a, },
183 [15] = { .offset = 0xc6, .value = 0x00, },
184 [16] = { .offset = 0xc7, .value = 0x73, },
185 [17] = { .offset = 0xc8, .value = 0x02, },
186 [18] = { .offset = 0xf4, .value = 0x00, },
187 [19] = { .offset = 0x80, .value = 0x27, },
188 [20] = { .offset = 0x81, .value = 0x03, },
189 [21] = { .offset = 0x82, .value = 0x41, },
190 [22] = { .offset = 0x83, .value = 0x05, },
191 [23] = { .offset = 0x94, .value = 0x00, },
192 [24] = { .offset = 0x95, .value = 0x00, },
193 [25] = { .offset = 0x96, .value = 0x05, },
194 [26] = { .offset = 0x97, .value = 0x00, },
195 [27] = { .offset = 0x9a, .value = 0x88, },
196 [28] = { .offset = 0x9b, .value = 0x00, },
197 [29] = { .offset = 0x98, .value = 0x00, },
198 [30] = { .offset = 0x99, .value = 0x00, },
199 [31] = { .offset = 0xf7, .value = 0x88, },
200 [32] = { .offset = 0xf8, .value = 0x06, },
201 [33] = { .offset = 0x9c, .value = 0x23, },
202 [34] = { .offset = 0x9d, .value = 0x00, },
203 [35] = { .offset = 0x9e, .value = 0x25, },
204 [36] = { .offset = 0x9f, .value = 0x03, },
205 [37] = { .offset = 0xa0, .value = 0x28, },
206 [38] = { .offset = 0xa1, .value = 0x01, },
207 [39] = { .offset = 0xa2, .value = 0x28, },
208 [40] = { .offset = 0xa3, .value = 0x05, },
209 [41] = { .offset = 0xb6, .value = 0x09, },
210 [42] = { .offset = 0xb8, .value = 0x30, },
211 [43] = { .offset = 0xb9, .value = 0xc8, },
212 [44] = { .offset = 0xba, .value = 0x00, },
213 [45] = { .offset = 0xbb, .value = 0x20, },
214 [46] = { .offset = 0x10, .value = 0x20, },
215 [47] = { .offset = 0x11, .value = 0xc8, },
216 [48] = { .offset = 0x12, .value = 0x02, },
217 [49] = { .offset = 0x20, .value = 0x00, },
218 [50] = { .offset = 0x22, .value = 0x00, },
219 [51] = { .offset = 0x23, .value = 0x00, },
220 [52] = { .offset = 0x24, .value = 0x00, },
221 [53] = { .offset = 0x25, .value = 0x00, },
222 [54] = { .offset = 0x8c, .value = 0x10, },
223 [55] = { .offset = 0x8d, .value = 0x02, },
224 [56] = { .offset = 0x8e, .value = 0x04, },
225 [57] = { .offset = 0x8f, .value = 0x00, },
226 [58] = { .offset = 0x90, .value = 0xff, },
227 [59] = { .offset = 0x91, .value = 0x07, },
228 [60] = { .offset = 0x92, .value = 0xa0, },
229 [61] = { .offset = 0x93, .value = 0x02, },
230 [62] = { .offset = 0xa5, .value = 0x00, },
231 [63] = { .offset = 0xa6, .value = 0x00, },
232 [64] = { .offset = 0xa7, .value = 0x00, },
233 [65] = { .offset = 0xa8, .value = 0x00, },
234 [66] = { .offset = 0xa9, .value = 0x83, },
235 [67] = { .offset = 0xaa, .value = 0x40, },
236 [68] = { .offset = 0xab, .value = 0x32, },
237 [69] = { .offset = 0xac, .value = 0x00, },
238 [70] = { .offset = 0xa4, .value = 0x80, },
239 [71] = { .offset = 0x7e, .value = 0x18, },
240 [72] = { .offset = 0x84, .value = 0x00, },
241 [73] = { .offset = 0x85, .value = 0x00, },
242 [74] = { .offset = 0x86, .value = 0x00, },
243 [75] = { .offset = 0x87, .value = 0x00, },
244 [76] = { .offset = 0x88, .value = 0x00, },
245 [77] = { .offset = 0x89, .value = 0x00, },
246 [78] = { .offset = 0x8a, .value = 0x00, },
247 [79] = { .offset = 0x8b, .value = 0x00, },
248 [80] = { .offset = 0x26, .value = 0x00, },
249 [81] = { .offset = 0x27, .value = 0x00, },
250 [82] = { .offset = 0xad, .value = 0x00, },
251 [83] = { .offset = 0x08, .value = 0x30, }, /* 0x31 */
252 [84] = { .offset = 0x41, .value = 0x00, },
253 [85] = { .offset = 0xc0, .value = 0x07, },
254 },
255 [MODE_1024x768] = {
256 [0] = { .offset = 0x0a, .value = 0x81, },
257 [1] = { .offset = 0x18, .value = 0x07, },
258 [2] = { .offset = 0x19, .value = 0x00, },
259 [3] = { .offset = 0x1a, .value = 0x00, },
260 [4] = { .offset = 0x1b, .value = 0x11, },
261 [5] = { .offset = 0x1c, .value = 0x54, },
262 [6] = { .offset = 0x1d, .value = 0x03, },
263 [7] = { .offset = 0x1e, .value = 0x02, },
264 [8] = { .offset = 0xf3, .value = 0x90, },
265 [9] = { .offset = 0xf9, .value = 0x00, },
266 [10] = { .offset = 0xc1, .value = 0x90, },
267 [11] = { .offset = 0xc2, .value = 0x00, },
268 [12] = { .offset = 0xc3, .value = 0x0f, },
269 [13] = { .offset = 0xc4, .value = 0x03, },
270 [14] = { .offset = 0xc5, .value = 0x16, },
271 [15] = { .offset = 0xc6, .value = 0x00, },
272 [16] = { .offset = 0xc7, .value = 0x02, },
273 [17] = { .offset = 0xc8, .value = 0x02, },
274 [18] = { .offset = 0xf4, .value = 0x00, },
275 [19] = { .offset = 0x80, .value = 0xff, },
276 [20] = { .offset = 0x81, .value = 0x07, },
277 [21] = { .offset = 0x82, .value = 0x3d, },
278 [22] = { .offset = 0x83, .value = 0x05, },
279 [23] = { .offset = 0x94, .value = 0x00, },
280 [24] = { .offset = 0x95, .value = 0x00, },
281 [25] = { .offset = 0x96, .value = 0x05, },
282 [26] = { .offset = 0x97, .value = 0x00, },
283 [27] = { .offset = 0x9a, .value = 0x88, },
284 [28] = { .offset = 0x9b, .value = 0x00, },
285 [29] = { .offset = 0x98, .value = 0x00, },
286 [30] = { .offset = 0x99, .value = 0x00, },
287 [31] = { .offset = 0xf7, .value = 0x88, },
288 [32] = { .offset = 0xf8, .value = 0x0a, },
289 [33] = { .offset = 0x9c, .value = 0x24, },
290 [34] = { .offset = 0x9d, .value = 0x00, },
291 [35] = { .offset = 0x9e, .value = 0x25, },
292 [36] = { .offset = 0x9f, .value = 0x03, },
293 [37] = { .offset = 0xa0, .value = 0x28, },
294 [38] = { .offset = 0xa1, .value = 0x01, },
295 [39] = { .offset = 0xa2, .value = 0x28, },
296 [40] = { .offset = 0xa3, .value = 0x05, },
297 [41] = { .offset = 0xb6, .value = 0x09, },
298 [42] = { .offset = 0xb8, .value = 0x00, },
299 [43] = { .offset = 0xb9, .value = 0xa0, },
300 [44] = { .offset = 0xba, .value = 0x00, },
301 [45] = { .offset = 0xbb, .value = 0x20, },
302 [46] = { .offset = 0x10, .value = 0x00, },
303 [47] = { .offset = 0x11, .value = 0xa0, },
304 [48] = { .offset = 0x12, .value = 0x02, },
305 [49] = { .offset = 0x20, .value = 0x00, },
306 [50] = { .offset = 0x22, .value = 0x00, },
307 [51] = { .offset = 0x23, .value = 0x00, },
308 [52] = { .offset = 0x24, .value = 0x00, },
309 [53] = { .offset = 0x25, .value = 0x00, },
310 [54] = { .offset = 0x8c, .value = 0x10, },
311 [55] = { .offset = 0x8d, .value = 0x02, },
312 [56] = { .offset = 0x8e, .value = 0x10, },
313 [57] = { .offset = 0x8f, .value = 0x00, },
314 [58] = { .offset = 0x90, .value = 0xff, },
315 [59] = { .offset = 0x91, .value = 0x07, },
316 [60] = { .offset = 0x92, .value = 0xa0, },
317 [61] = { .offset = 0x93, .value = 0x02, },
318 [62] = { .offset = 0xa5, .value = 0x00, },
319 [63] = { .offset = 0xa6, .value = 0x00, },
320 [64] = { .offset = 0xa7, .value = 0x00, },
321 [65] = { .offset = 0xa8, .value = 0x00, },
322 [66] = { .offset = 0xa9, .value = 0x04, },
323 [67] = { .offset = 0xaa, .value = 0x70, },
324 [68] = { .offset = 0xab, .value = 0x4f, },
325 [69] = { .offset = 0xac, .value = 0x00, },
326 [70] = { .offset = 0xa4, .value = 0x84, },
327 [71] = { .offset = 0x7e, .value = 0x18, },
328 [72] = { .offset = 0x84, .value = 0x00, },
329 [73] = { .offset = 0x85, .value = 0x00, },
330 [74] = { .offset = 0x86, .value = 0x00, },
331 [75] = { .offset = 0x87, .value = 0x00, },
332 [76] = { .offset = 0x88, .value = 0x00, },
333 [77] = { .offset = 0x89, .value = 0x00, },
334 [78] = { .offset = 0x8a, .value = 0x00, },
335 [79] = { .offset = 0x8b, .value = 0x00, },
336 [80] = { .offset = 0x26, .value = 0x00, },
337 [81] = { .offset = 0x27, .value = 0x00, },
338 [82] = { .offset = 0xad, .value = 0x00, },
339 [83] = { .offset = 0x08, .value = 0x34, }, /* 0x35 */
340 [84] = { .offset = 0x41, .value = 0x00, },
341 [85] = { .offset = 0xc0, .value = 0x01, },
342 },
343};
344
345static const struct ns2501_reg regs_init[] = {
346 [0] = { .offset = 0x35, .value = 0xff, },
347 [1] = { .offset = 0x34, .value = 0x00, },
348 [2] = { .offset = 0x08, .value = 0x30, },
349};
350
63struct ns2501_priv { 351struct ns2501_priv {
64 //I2CDevRec d;
65 bool quiet; 352 bool quiet;
66 int reg_8_shadow; 353 const struct ns2501_reg *regs;
67 int reg_8_set;
68 // Shadow registers for i915
69 int dvoc;
70 int pll_a;
71 int srcdim;
72 int fw_blc;
73}; 354};
74 355
75#define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr)) 356#define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr))
@@ -205,11 +486,9 @@ static bool ns2501_init(struct intel_dvo_device *dvo,
205 goto out; 486 goto out;
206 } 487 }
207 ns->quiet = false; 488 ns->quiet = false;
208 ns->reg_8_set = 0;
209 ns->reg_8_shadow =
210 NS2501_8_PD | NS2501_8_BPAS | NS2501_8_VEN | NS2501_8_HEN;
211 489
212 DRM_DEBUG_KMS("init ns2501 dvo controller successfully!\n"); 490 DRM_DEBUG_KMS("init ns2501 dvo controller successfully!\n");
491
213 return true; 492 return true;
214 493
215out: 494out:
@@ -242,9 +521,9 @@ static enum drm_mode_status ns2501_mode_valid(struct intel_dvo_device *dvo,
242 * of the panel in here so we could always accept it 521 * of the panel in here so we could always accept it
243 * by disabling the scaler. 522 * by disabling the scaler.
244 */ 523 */
245 if ((mode->hdisplay == 800 && mode->vdisplay == 600) || 524 if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) ||
246 (mode->hdisplay == 640 && mode->vdisplay == 480) || 525 (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) ||
247 (mode->hdisplay == 1024 && mode->vdisplay == 768)) { 526 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) {
248 return MODE_OK; 527 return MODE_OK;
249 } else { 528 } else {
250 return MODE_ONE_SIZE; /* Is this a reasonable error? */ 529 return MODE_ONE_SIZE; /* Is this a reasonable error? */
@@ -255,180 +534,30 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo,
255 struct drm_display_mode *mode, 534 struct drm_display_mode *mode,
256 struct drm_display_mode *adjusted_mode) 535 struct drm_display_mode *adjusted_mode)
257{ 536{
258 bool ok;
259 int retries = 10;
260 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); 537 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
538 int mode_idx, i;
261 539
262 DRM_DEBUG_KMS 540 DRM_DEBUG_KMS
263 ("set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d).\n", 541 ("set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d).\n",
264 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal); 542 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal);
265 543
266 /* 544 if (mode->hdisplay == 640 && mode->vdisplay == 480)
267 * Where do I find the native resolution for which scaling is not required??? 545 mode_idx = MODE_640x480;
268 * 546 else if (mode->hdisplay == 800 && mode->vdisplay == 600)
269 * First trigger the DVO on as otherwise the chip does not appear on the i2c 547 mode_idx = MODE_800x600;
270 * bus. 548 else if (mode->hdisplay == 1024 && mode->vdisplay == 768)
271 */ 549 mode_idx = MODE_1024x768;
272 do { 550 else
273 ok = true; 551 return;
274
275 if (mode->hdisplay == 800 && mode->vdisplay == 600) {
276 /* mode 277 */
277 ns->reg_8_shadow &= ~NS2501_8_BPAS;
278 DRM_DEBUG_KMS("switching to 800x600\n");
279
280 /*
281 * No, I do not know where this data comes from.
282 * It is just what the video bios left in the DVO, so
283 * I'm just copying it here over.
284 * This also means that I cannot support any other modes
285 * except the ones supported by the bios.
286 */
287 ok &= ns2501_writeb(dvo, 0x11, 0xc8); // 0xc7 also works.
288 ok &= ns2501_writeb(dvo, 0x1b, 0x19);
289 ok &= ns2501_writeb(dvo, 0x1c, 0x62); // VBIOS left 0x64 here, but 0x62 works nicer
290 ok &= ns2501_writeb(dvo, 0x1d, 0x02);
291
292 ok &= ns2501_writeb(dvo, 0x34, 0x03);
293 ok &= ns2501_writeb(dvo, 0x35, 0xff);
294 552
295 ok &= ns2501_writeb(dvo, 0x80, 0x27); 553 /* Hopefully doing it every time won't hurt... */
296 ok &= ns2501_writeb(dvo, 0x81, 0x03); 554 for (i = 0; i < ARRAY_SIZE(regs_init); i++)
297 ok &= ns2501_writeb(dvo, 0x82, 0x41); 555 ns2501_writeb(dvo, regs_init[i].offset, regs_init[i].value);
298 ok &= ns2501_writeb(dvo, 0x83, 0x05);
299 556
300 ok &= ns2501_writeb(dvo, 0x8d, 0x02); 557 ns->regs = regs_1024x768[mode_idx];
301 ok &= ns2501_writeb(dvo, 0x8e, 0x04);
302 ok &= ns2501_writeb(dvo, 0x8f, 0x00);
303 558
304 ok &= ns2501_writeb(dvo, 0x90, 0xfe); /* vertical. VBIOS left 0xff here, but 0xfe works better */ 559 for (i = 0; i < 84; i++)
305 ok &= ns2501_writeb(dvo, 0x91, 0x07); 560 ns2501_writeb(dvo, ns->regs[i].offset, ns->regs[i].value);
306 ok &= ns2501_writeb(dvo, 0x94, 0x00);
307 ok &= ns2501_writeb(dvo, 0x95, 0x00);
308
309 ok &= ns2501_writeb(dvo, 0x96, 0x00);
310
311 ok &= ns2501_writeb(dvo, 0x99, 0x00);
312 ok &= ns2501_writeb(dvo, 0x9a, 0x88);
313
314 ok &= ns2501_writeb(dvo, 0x9c, 0x23); /* Looks like first and last line of the image. */
315 ok &= ns2501_writeb(dvo, 0x9d, 0x00);
316 ok &= ns2501_writeb(dvo, 0x9e, 0x25);
317 ok &= ns2501_writeb(dvo, 0x9f, 0x03);
318
319 ok &= ns2501_writeb(dvo, 0xa4, 0x80);
320
321 ok &= ns2501_writeb(dvo, 0xb6, 0x00);
322
323 ok &= ns2501_writeb(dvo, 0xb9, 0xc8); /* horizontal? */
324 ok &= ns2501_writeb(dvo, 0xba, 0x00); /* horizontal? */
325
326 ok &= ns2501_writeb(dvo, 0xc0, 0x05); /* horizontal? */
327 ok &= ns2501_writeb(dvo, 0xc1, 0xd7);
328
329 ok &= ns2501_writeb(dvo, 0xc2, 0x00);
330 ok &= ns2501_writeb(dvo, 0xc3, 0xf8);
331
332 ok &= ns2501_writeb(dvo, 0xc4, 0x03);
333 ok &= ns2501_writeb(dvo, 0xc5, 0x1a);
334
335 ok &= ns2501_writeb(dvo, 0xc6, 0x00);
336 ok &= ns2501_writeb(dvo, 0xc7, 0x73);
337 ok &= ns2501_writeb(dvo, 0xc8, 0x02);
338
339 } else if (mode->hdisplay == 640 && mode->vdisplay == 480) {
340 /* mode 274 */
341 DRM_DEBUG_KMS("switching to 640x480\n");
342 /*
343 * No, I do not know where this data comes from.
344 * It is just what the video bios left in the DVO, so
345 * I'm just copying it here over.
346 * This also means that I cannot support any other modes
347 * except the ones supported by the bios.
348 */
349 ns->reg_8_shadow &= ~NS2501_8_BPAS;
350
351 ok &= ns2501_writeb(dvo, 0x11, 0xa0);
352 ok &= ns2501_writeb(dvo, 0x1b, 0x11);
353 ok &= ns2501_writeb(dvo, 0x1c, 0x54);
354 ok &= ns2501_writeb(dvo, 0x1d, 0x03);
355
356 ok &= ns2501_writeb(dvo, 0x34, 0x03);
357 ok &= ns2501_writeb(dvo, 0x35, 0xff);
358
359 ok &= ns2501_writeb(dvo, 0x80, 0xff);
360 ok &= ns2501_writeb(dvo, 0x81, 0x07);
361 ok &= ns2501_writeb(dvo, 0x82, 0x3d);
362 ok &= ns2501_writeb(dvo, 0x83, 0x05);
363
364 ok &= ns2501_writeb(dvo, 0x8d, 0x02);
365 ok &= ns2501_writeb(dvo, 0x8e, 0x10);
366 ok &= ns2501_writeb(dvo, 0x8f, 0x00);
367
368 ok &= ns2501_writeb(dvo, 0x90, 0xff); /* vertical */
369 ok &= ns2501_writeb(dvo, 0x91, 0x07);
370 ok &= ns2501_writeb(dvo, 0x94, 0x00);
371 ok &= ns2501_writeb(dvo, 0x95, 0x00);
372
373 ok &= ns2501_writeb(dvo, 0x96, 0x05);
374
375 ok &= ns2501_writeb(dvo, 0x99, 0x00);
376 ok &= ns2501_writeb(dvo, 0x9a, 0x88);
377
378 ok &= ns2501_writeb(dvo, 0x9c, 0x24);
379 ok &= ns2501_writeb(dvo, 0x9d, 0x00);
380 ok &= ns2501_writeb(dvo, 0x9e, 0x25);
381 ok &= ns2501_writeb(dvo, 0x9f, 0x03);
382
383 ok &= ns2501_writeb(dvo, 0xa4, 0x84);
384
385 ok &= ns2501_writeb(dvo, 0xb6, 0x09);
386
387 ok &= ns2501_writeb(dvo, 0xb9, 0xa0); /* horizontal? */
388 ok &= ns2501_writeb(dvo, 0xba, 0x00); /* horizontal? */
389
390 ok &= ns2501_writeb(dvo, 0xc0, 0x05); /* horizontal? */
391 ok &= ns2501_writeb(dvo, 0xc1, 0x90);
392
393 ok &= ns2501_writeb(dvo, 0xc2, 0x00);
394 ok &= ns2501_writeb(dvo, 0xc3, 0x0f);
395
396 ok &= ns2501_writeb(dvo, 0xc4, 0x03);
397 ok &= ns2501_writeb(dvo, 0xc5, 0x16);
398
399 ok &= ns2501_writeb(dvo, 0xc6, 0x00);
400 ok &= ns2501_writeb(dvo, 0xc7, 0x02);
401 ok &= ns2501_writeb(dvo, 0xc8, 0x02);
402
403 } else if (mode->hdisplay == 1024 && mode->vdisplay == 768) {
404 /* mode 280 */
405 DRM_DEBUG_KMS("switching to 1024x768\n");
406 /*
407 * This might or might not work, actually. I'm silently
408 * assuming here that the native panel resolution is
409 * 1024x768. If not, then this leaves the scaler disabled
410 * generating a picture that is likely not the expected.
411 *
412 * Problem is that I do not know where to take the panel
413 * dimensions from.
414 *
415 * Enable the bypass, scaling not required.
416 *
417 * The scaler registers are irrelevant here....
418 *
419 */
420 ns->reg_8_shadow |= NS2501_8_BPAS;
421 ok &= ns2501_writeb(dvo, 0x37, 0x44);
422 } else {
423 /*
424 * Data not known. Bummer!
425 * Hopefully, the code should not go here
426 * as mode_OK delivered no other modes.
427 */
428 ns->reg_8_shadow |= NS2501_8_BPAS;
429 }
430 ok &= ns2501_writeb(dvo, NS2501_REG8, ns->reg_8_shadow);
431 } while (!ok && retries--);
432} 561}
433 562
434/* set the NS2501 power state */ 563/* set the NS2501 power state */
@@ -439,60 +568,46 @@ static bool ns2501_get_hw_state(struct intel_dvo_device *dvo)
439 if (!ns2501_readb(dvo, NS2501_REG8, &ch)) 568 if (!ns2501_readb(dvo, NS2501_REG8, &ch))
440 return false; 569 return false;
441 570
442 if (ch & NS2501_8_PD) 571 return ch & NS2501_8_PD;
443 return true;
444 else
445 return false;
446} 572}
447 573
448/* set the NS2501 power state */ 574/* set the NS2501 power state */
449static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable) 575static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
450{ 576{
451 bool ok;
452 int retries = 10;
453 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); 577 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
454 unsigned char ch;
455 578
456 DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable); 579 DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable);
457 580
458 ch = ns->reg_8_shadow; 581 if (enable) {
582 if (WARN_ON(ns->regs[83].offset != 0x08 ||
583 ns->regs[84].offset != 0x41 ||
584 ns->regs[85].offset != 0xc0))
585 return;
459 586
460 if (enable) 587 ns2501_writeb(dvo, 0xc0, ns->regs[85].value | 0x08);
461 ch |= NS2501_8_PD;
462 else
463 ch &= ~NS2501_8_PD;
464
465 if (ns->reg_8_set == 0 || ns->reg_8_shadow != ch) {
466 ns->reg_8_set = 1;
467 ns->reg_8_shadow = ch;
468
469 do {
470 ok = true;
471 ok &= ns2501_writeb(dvo, NS2501_REG8, ch);
472 ok &=
473 ns2501_writeb(dvo, 0x34,
474 enable ? 0x03 : 0x00);
475 ok &=
476 ns2501_writeb(dvo, 0x35,
477 enable ? 0xff : 0x00);
478 } while (!ok && retries--);
479 }
480}
481 588
482static void ns2501_dump_regs(struct intel_dvo_device *dvo) 589 ns2501_writeb(dvo, 0x41, ns->regs[84].value);
483{ 590
484 uint8_t val; 591 ns2501_writeb(dvo, 0x34, 0x01);
485 592 msleep(15);
486 ns2501_readb(dvo, NS2501_FREQ_LO, &val); 593
487 DRM_DEBUG_KMS("NS2501_FREQ_LO: 0x%02x\n", val); 594 ns2501_writeb(dvo, 0x08, 0x35);
488 ns2501_readb(dvo, NS2501_FREQ_HI, &val); 595 if (!(ns->regs[83].value & NS2501_8_BPAS))
489 DRM_DEBUG_KMS("NS2501_FREQ_HI: 0x%02x\n", val); 596 ns2501_writeb(dvo, 0x08, 0x31);
490 ns2501_readb(dvo, NS2501_REG8, &val); 597 msleep(200);
491 DRM_DEBUG_KMS("NS2501_REG8: 0x%02x\n", val); 598
492 ns2501_readb(dvo, NS2501_REG9, &val); 599 ns2501_writeb(dvo, 0x34, 0x03);
493 DRM_DEBUG_KMS("NS2501_REG9: 0x%02x\n", val); 600
494 ns2501_readb(dvo, NS2501_REGC, &val); 601 ns2501_writeb(dvo, 0xc0, ns->regs[85].value);
495 DRM_DEBUG_KMS("NS2501_REGC: 0x%02x\n", val); 602 } else {
603 ns2501_writeb(dvo, 0x34, 0x01);
604 msleep(200);
605
606 ns2501_writeb(dvo, 0x08, 0x34);
607 msleep(15);
608
609 ns2501_writeb(dvo, 0x34, 0x00);
610 }
496} 611}
497 612
498static void ns2501_destroy(struct intel_dvo_device *dvo) 613static void ns2501_destroy(struct intel_dvo_device *dvo)
@@ -512,6 +627,5 @@ struct intel_dvo_dev_ops ns2501_ops = {
512 .mode_set = ns2501_mode_set, 627 .mode_set = ns2501_mode_set,
513 .dpms = ns2501_dpms, 628 .dpms = ns2501_dpms,
514 .get_hw_state = ns2501_get_hw_state, 629 .get_hw_state = ns2501_get_hw_state,
515 .dump_regs = ns2501_dump_regs,
516 .destroy = ns2501_destroy, 630 .destroy = ns2501_destroy,
517}; 631};
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6c82bdaa0822..2cbc85f3b237 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -136,7 +136,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
136 obj->last_read_seqno, 136 obj->last_read_seqno,
137 obj->last_write_seqno, 137 obj->last_write_seqno,
138 obj->last_fenced_seqno, 138 obj->last_fenced_seqno,
139 i915_cache_level_str(obj->cache_level), 139 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
140 obj->dirty ? " dirty" : "", 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); 141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name) 142 if (obj->base.name)
@@ -515,6 +515,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
515{ 515{
516 struct drm_info_node *node = m->private; 516 struct drm_info_node *node = m->private;
517 struct drm_device *dev = node->minor->dev; 517 struct drm_device *dev = node->minor->dev;
518 struct drm_i915_private *dev_priv = dev->dev_private;
518 unsigned long flags; 519 unsigned long flags;
519 struct intel_crtc *crtc; 520 struct intel_crtc *crtc;
520 int ret; 521 int ret;
@@ -534,6 +535,8 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
534 seq_printf(m, "No flip due on pipe %c (plane %c)\n", 535 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
535 pipe, plane); 536 pipe, plane);
536 } else { 537 } else {
538 u32 addr;
539
537 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { 540 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
538 seq_printf(m, "Flip queued on pipe %c (plane %c)\n", 541 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
539 pipe, plane); 542 pipe, plane);
@@ -541,23 +544,35 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
541 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", 544 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
542 pipe, plane); 545 pipe, plane);
543 } 546 }
547 if (work->flip_queued_ring) {
548 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
549 work->flip_queued_ring->name,
550 work->flip_queued_seqno,
551 dev_priv->next_seqno,
552 work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
553 i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
554 work->flip_queued_seqno));
555 } else
556 seq_printf(m, "Flip not associated with any ring\n");
557 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
558 work->flip_queued_vblank,
559 work->flip_ready_vblank,
560 drm_vblank_count(dev, crtc->pipe));
544 if (work->enable_stall_check) 561 if (work->enable_stall_check)
545 seq_puts(m, "Stall check enabled, "); 562 seq_puts(m, "Stall check enabled, ");
546 else 563 else
547 seq_puts(m, "Stall check waiting for page flip ioctl, "); 564 seq_puts(m, "Stall check waiting for page flip ioctl, ");
548 seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); 565 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
549 566
550 if (work->old_fb_obj) { 567 if (INTEL_INFO(dev)->gen >= 4)
551 struct drm_i915_gem_object *obj = work->old_fb_obj; 568 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
552 if (obj) 569 else
553 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", 570 addr = I915_READ(DSPADDR(crtc->plane));
554 i915_gem_obj_ggtt_offset(obj)); 571 seq_printf(m, "Current scanout address 0x%08x\n", addr);
555 } 572
556 if (work->pending_flip_obj) { 573 if (work->pending_flip_obj) {
557 struct drm_i915_gem_object *obj = work->pending_flip_obj; 574 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
558 if (obj) 575 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
559 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
560 i915_gem_obj_ggtt_offset(obj));
561 } 576 }
562 } 577 }
563 spin_unlock_irqrestore(&dev->event_lock, flags); 578 spin_unlock_irqrestore(&dev->event_lock, flags);
@@ -650,7 +665,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
650 intel_runtime_pm_get(dev_priv); 665 intel_runtime_pm_get(dev_priv);
651 666
652 if (IS_CHERRYVIEW(dev)) { 667 if (IS_CHERRYVIEW(dev)) {
653 int i;
654 seq_printf(m, "Master Interrupt Control:\t%08x\n", 668 seq_printf(m, "Master Interrupt Control:\t%08x\n",
655 I915_READ(GEN8_MASTER_IRQ)); 669 I915_READ(GEN8_MASTER_IRQ));
656 670
@@ -662,7 +676,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
662 I915_READ(VLV_IIR_RW)); 676 I915_READ(VLV_IIR_RW));
663 seq_printf(m, "Display IMR:\t%08x\n", 677 seq_printf(m, "Display IMR:\t%08x\n",
664 I915_READ(VLV_IMR)); 678 I915_READ(VLV_IMR));
665 for_each_pipe(pipe) 679 for_each_pipe(dev_priv, pipe)
666 seq_printf(m, "Pipe %c stat:\t%08x\n", 680 seq_printf(m, "Pipe %c stat:\t%08x\n",
667 pipe_name(pipe), 681 pipe_name(pipe),
668 I915_READ(PIPESTAT(pipe))); 682 I915_READ(PIPESTAT(pipe)));
@@ -702,7 +716,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
702 i, I915_READ(GEN8_GT_IER(i))); 716 i, I915_READ(GEN8_GT_IER(i)));
703 } 717 }
704 718
705 for_each_pipe(pipe) { 719 for_each_pipe(dev_priv, pipe) {
706 if (!intel_display_power_enabled(dev_priv, 720 if (!intel_display_power_enabled(dev_priv,
707 POWER_DOMAIN_PIPE(pipe))) { 721 POWER_DOMAIN_PIPE(pipe))) {
708 seq_printf(m, "Pipe %c power disabled\n", 722 seq_printf(m, "Pipe %c power disabled\n",
@@ -749,7 +763,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
749 I915_READ(VLV_IIR_RW)); 763 I915_READ(VLV_IIR_RW));
750 seq_printf(m, "Display IMR:\t%08x\n", 764 seq_printf(m, "Display IMR:\t%08x\n",
751 I915_READ(VLV_IMR)); 765 I915_READ(VLV_IMR));
752 for_each_pipe(pipe) 766 for_each_pipe(dev_priv, pipe)
753 seq_printf(m, "Pipe %c stat:\t%08x\n", 767 seq_printf(m, "Pipe %c stat:\t%08x\n",
754 pipe_name(pipe), 768 pipe_name(pipe),
755 I915_READ(PIPESTAT(pipe))); 769 I915_READ(PIPESTAT(pipe)));
@@ -785,7 +799,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
785 I915_READ(IIR)); 799 I915_READ(IIR));
786 seq_printf(m, "Interrupt mask: %08x\n", 800 seq_printf(m, "Interrupt mask: %08x\n",
787 I915_READ(IMR)); 801 I915_READ(IMR));
788 for_each_pipe(pipe) 802 for_each_pipe(dev_priv, pipe)
789 seq_printf(m, "Pipe %c stat: %08x\n", 803 seq_printf(m, "Pipe %c stat: %08x\n",
790 pipe_name(pipe), 804 pipe_name(pipe),
791 I915_READ(PIPESTAT(pipe))); 805 I915_READ(PIPESTAT(pipe)));
@@ -933,7 +947,7 @@ static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
933 ssize_t ret_count = 0; 947 ssize_t ret_count = 0;
934 int ret; 948 int ret;
935 949
936 ret = i915_error_state_buf_init(&error_str, count, *pos); 950 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
937 if (ret) 951 if (ret)
938 return ret; 952 return ret;
939 953
@@ -1030,6 +1044,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
1030 u32 rpstat, cagf, reqf; 1044 u32 rpstat, cagf, reqf;
1031 u32 rpupei, rpcurup, rpprevup; 1045 u32 rpupei, rpcurup, rpprevup;
1032 u32 rpdownei, rpcurdown, rpprevdown; 1046 u32 rpdownei, rpcurdown, rpprevdown;
1047 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1033 int max_freq; 1048 int max_freq;
1034 1049
1035 /* RPSTAT1 is in the GT power well */ 1050 /* RPSTAT1 is in the GT power well */
@@ -1067,12 +1082,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
1067 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 1082 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1068 mutex_unlock(&dev->struct_mutex); 1083 mutex_unlock(&dev->struct_mutex);
1069 1084
1085 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1086 pm_ier = I915_READ(GEN6_PMIER);
1087 pm_imr = I915_READ(GEN6_PMIMR);
1088 pm_isr = I915_READ(GEN6_PMISR);
1089 pm_iir = I915_READ(GEN6_PMIIR);
1090 pm_mask = I915_READ(GEN6_PMINTRMSK);
1091 } else {
1092 pm_ier = I915_READ(GEN8_GT_IER(2));
1093 pm_imr = I915_READ(GEN8_GT_IMR(2));
1094 pm_isr = I915_READ(GEN8_GT_ISR(2));
1095 pm_iir = I915_READ(GEN8_GT_IIR(2));
1096 pm_mask = I915_READ(GEN6_PMINTRMSK);
1097 }
1070 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", 1098 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1071 I915_READ(GEN6_PMIER), 1099 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1072 I915_READ(GEN6_PMIMR),
1073 I915_READ(GEN6_PMISR),
1074 I915_READ(GEN6_PMIIR),
1075 I915_READ(GEN6_PMINTRMSK));
1076 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 1100 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1077 seq_printf(m, "Render p-state ratio: %d\n", 1101 seq_printf(m, "Render p-state ratio: %d\n",
1078 (gt_perf_status & 0xff00) >> 8); 1102 (gt_perf_status & 0xff00) >> 8);
@@ -1371,7 +1395,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused)
1371 1395
1372 if (IS_VALLEYVIEW(dev)) 1396 if (IS_VALLEYVIEW(dev))
1373 return vlv_drpc_info(m); 1397 return vlv_drpc_info(m);
1374 else if (IS_GEN6(dev) || IS_GEN7(dev)) 1398 else if (INTEL_INFO(dev)->gen >= 6)
1375 return gen6_drpc_info(m); 1399 return gen6_drpc_info(m);
1376 else 1400 else
1377 return ironlake_drpc_info(m); 1401 return ironlake_drpc_info(m);
@@ -2618,6 +2642,40 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2618 return 0; 2642 return 0;
2619} 2643}
2620 2644
2645static int i915_wa_registers(struct seq_file *m, void *unused)
2646{
2647 int i;
2648 int ret;
2649 struct drm_info_node *node = (struct drm_info_node *) m->private;
2650 struct drm_device *dev = node->minor->dev;
2651 struct drm_i915_private *dev_priv = dev->dev_private;
2652
2653 ret = mutex_lock_interruptible(&dev->struct_mutex);
2654 if (ret)
2655 return ret;
2656
2657 intel_runtime_pm_get(dev_priv);
2658
2659 seq_printf(m, "Workarounds applied: %d\n", dev_priv->num_wa_regs);
2660 for (i = 0; i < dev_priv->num_wa_regs; ++i) {
2661 u32 addr, mask;
2662
2663 addr = dev_priv->intel_wa_regs[i].addr;
2664 mask = dev_priv->intel_wa_regs[i].mask;
2665 dev_priv->intel_wa_regs[i].value = I915_READ(addr) | mask;
2666 if (dev_priv->intel_wa_regs[i].addr)
2667 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
2668 dev_priv->intel_wa_regs[i].addr,
2669 dev_priv->intel_wa_regs[i].value,
2670 dev_priv->intel_wa_regs[i].mask);
2671 }
2672
2673 intel_runtime_pm_put(dev_priv);
2674 mutex_unlock(&dev->struct_mutex);
2675
2676 return 0;
2677}
2678
2621struct pipe_crc_info { 2679struct pipe_crc_info {
2622 const char *name; 2680 const char *name;
2623 struct drm_device *dev; 2681 struct drm_device *dev;
@@ -3769,8 +3827,6 @@ i915_drop_caches_set(void *data, u64 val)
3769 struct drm_device *dev = data; 3827 struct drm_device *dev = data;
3770 struct drm_i915_private *dev_priv = dev->dev_private; 3828 struct drm_i915_private *dev_priv = dev->dev_private;
3771 struct drm_i915_gem_object *obj, *next; 3829 struct drm_i915_gem_object *obj, *next;
3772 struct i915_address_space *vm;
3773 struct i915_vma *vma, *x;
3774 int ret; 3830 int ret;
3775 3831
3776 DRM_DEBUG("Dropping caches: 0x%08llx\n", val); 3832 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
@@ -3791,16 +3847,23 @@ i915_drop_caches_set(void *data, u64 val)
3791 i915_gem_retire_requests(dev); 3847 i915_gem_retire_requests(dev);
3792 3848
3793 if (val & DROP_BOUND) { 3849 if (val & DROP_BOUND) {
3794 list_for_each_entry(vm, &dev_priv->vm_list, global_link) { 3850 list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list,
3795 list_for_each_entry_safe(vma, x, &vm->inactive_list, 3851 global_list) {
3796 mm_list) { 3852 struct i915_vma *vma, *v;
3853
3854 ret = 0;
3855 drm_gem_object_reference(&obj->base);
3856 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) {
3797 if (vma->pin_count) 3857 if (vma->pin_count)
3798 continue; 3858 continue;
3799 3859
3800 ret = i915_vma_unbind(vma); 3860 ret = i915_vma_unbind(vma);
3801 if (ret) 3861 if (ret)
3802 goto unlock; 3862 break;
3803 } 3863 }
3864 drm_gem_object_unreference(&obj->base);
3865 if (ret)
3866 goto unlock;
3804 } 3867 }
3805 } 3868 }
3806 3869
@@ -4149,6 +4212,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
4149 {"i915_semaphore_status", i915_semaphore_status, 0}, 4212 {"i915_semaphore_status", i915_semaphore_status, 0},
4150 {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, 4213 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4151 {"i915_dp_mst_info", i915_dp_mst_info, 0}, 4214 {"i915_dp_mst_info", i915_dp_mst_info, 0},
4215 {"i915_wa_registers", i915_wa_registers, 0},
4152}; 4216};
4153#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 4217#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4154 4218
@@ -4178,7 +4242,7 @@ void intel_display_crc_init(struct drm_device *dev)
4178 struct drm_i915_private *dev_priv = dev->dev_private; 4242 struct drm_i915_private *dev_priv = dev->dev_private;
4179 enum pipe pipe; 4243 enum pipe pipe;
4180 4244
4181 for_each_pipe(pipe) { 4245 for_each_pipe(dev_priv, pipe) {
4182 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 4246 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4183 4247
4184 pipe_crc->opened = false; 4248 pipe_crc->opened = false;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 272d3d16147c..1403b01e8216 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -28,6 +28,7 @@
28 28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 30
31#include <linux/async.h>
31#include <drm/drmP.h> 32#include <drm/drmP.h>
32#include <drm/drm_crtc_helper.h> 33#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h> 34#include <drm/drm_fb_helper.h>
@@ -1381,7 +1382,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
1381 * scanning against hotplug events. Hence do this first and ignore the 1382 * scanning against hotplug events. Hence do this first and ignore the
1382 * tiny window where we will loose hotplug notifactions. 1383 * tiny window where we will loose hotplug notifactions.
1383 */ 1384 */
1384 intel_fbdev_initial_config(dev); 1385 async_schedule(intel_fbdev_initial_config, dev_priv);
1385 1386
1386 drm_kms_helper_poll_init(dev); 1387 drm_kms_helper_poll_init(dev);
1387 1388
@@ -1534,10 +1535,10 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
1534 info = (struct intel_device_info *)&dev_priv->info; 1535 info = (struct intel_device_info *)&dev_priv->info;
1535 1536
1536 if (IS_VALLEYVIEW(dev)) 1537 if (IS_VALLEYVIEW(dev))
1537 for_each_pipe(pipe) 1538 for_each_pipe(dev_priv, pipe)
1538 info->num_sprites[pipe] = 2; 1539 info->num_sprites[pipe] = 2;
1539 else 1540 else
1540 for_each_pipe(pipe) 1541 for_each_pipe(dev_priv, pipe)
1541 info->num_sprites[pipe] = 1; 1542 info->num_sprites[pipe] = 1;
1542 1543
1543 if (i915.disable_display) { 1544 if (i915.disable_display) {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cdd95956811d..3870c7359a16 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -844,7 +844,13 @@ int i915_reset(struct drm_device *dev)
844 !dev_priv->ums.mm_suspended) { 844 !dev_priv->ums.mm_suspended) {
845 dev_priv->ums.mm_suspended = 0; 845 dev_priv->ums.mm_suspended = 0;
846 846
847 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
848 dev_priv->gpu_error.reload_in_reset = true;
849
847 ret = i915_gem_init_hw(dev); 850 ret = i915_gem_init_hw(dev);
851
852 dev_priv->gpu_error.reload_in_reset = false;
853
848 mutex_unlock(&dev->struct_mutex); 854 mutex_unlock(&dev->struct_mutex);
849 if (ret) { 855 if (ret) {
850 DRM_ERROR("Failed hw init on reset %d\n", ret); 856 DRM_ERROR("Failed hw init on reset %d\n", ret);
@@ -1456,13 +1462,29 @@ static int intel_runtime_suspend(struct device *device)
1456 dev_priv->pm.suspended = true; 1462 dev_priv->pm.suspended = true;
1457 1463
1458 /* 1464 /*
1459 * current versions of firmware which depend on this opregion 1465 * FIXME: We really should find a document that references the arguments
1460 * notification have repurposed the D1 definition to mean 1466 * used below!
1461 * "runtime suspended" vs. what you would normally expect (D3)
1462 * to distinguish it from notifications that might be sent
1463 * via the suspend path.
1464 */ 1467 */
1465 intel_opregion_notify_adapter(dev, PCI_D1); 1468 if (IS_HASWELL(dev)) {
1469 /*
1470 * current versions of firmware which depend on this opregion
1471 * notification have repurposed the D1 definition to mean
1472 * "runtime suspended" vs. what you would normally expect (D3)
1473 * to distinguish it from notifications that might be sent via
1474 * the suspend path.
1475 */
1476 intel_opregion_notify_adapter(dev, PCI_D1);
1477 } else {
1478 /*
1479 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1480 * being detected, and the call we do at intel_runtime_resume()
1481 * won't be able to restore them. Since PCI_D3hot matches the
1482 * actual specification and appears to be working, use it. Let's
1483 * assume the other non-Haswell platforms will stay the same as
1484 * Broadwell.
1485 */
1486 intel_opregion_notify_adapter(dev, PCI_D3hot);
1487 }
1466 1488
1467 DRM_DEBUG_KMS("Device suspended\n"); 1489 DRM_DEBUG_KMS("Device suspended\n");
1468 return 0; 1490 return 0;
@@ -1685,6 +1707,8 @@ static void __exit i915_exit(void)
1685module_init(i915_init); 1707module_init(i915_init);
1686module_exit(i915_exit); 1708module_exit(i915_exit);
1687 1709
1688MODULE_AUTHOR(DRIVER_AUTHOR); 1710MODULE_AUTHOR("Tungsten Graphics, Inc.");
1711MODULE_AUTHOR("Intel Corporation");
1712
1689MODULE_DESCRIPTION(DRIVER_DESC); 1713MODULE_DESCRIPTION(DRIVER_DESC);
1690MODULE_LICENSE("GPL and additional rights"); 1714MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 357913c4f2c6..88a8b72b553e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -37,6 +37,7 @@
37#include "intel_ringbuffer.h" 37#include "intel_ringbuffer.h"
38#include "intel_lrc.h" 38#include "intel_lrc.h"
39#include "i915_gem_gtt.h" 39#include "i915_gem_gtt.h"
40#include "i915_gem_render_state.h"
40#include <linux/io-mapping.h> 41#include <linux/io-mapping.h>
41#include <linux/i2c.h> 42#include <linux/i2c.h>
42#include <linux/i2c-algo-bit.h> 43#include <linux/i2c-algo-bit.h>
@@ -51,11 +52,9 @@
51/* General customization: 52/* General customization:
52 */ 53 */
53 54
54#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
55
56#define DRIVER_NAME "i915" 55#define DRIVER_NAME "i915"
57#define DRIVER_DESC "Intel Graphics" 56#define DRIVER_DESC "Intel Graphics"
58#define DRIVER_DATE "20140822" 57#define DRIVER_DATE "20140905"
59 58
60enum pipe { 59enum pipe {
61 INVALID_PIPE = -1, 60 INVALID_PIPE = -1,
@@ -164,7 +163,10 @@ enum hpd_pin {
164 I915_GEM_DOMAIN_INSTRUCTION | \ 163 I915_GEM_DOMAIN_INSTRUCTION | \
165 I915_GEM_DOMAIN_VERTEX) 164 I915_GEM_DOMAIN_VERTEX)
166 165
167#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) 166#define for_each_pipe(__dev_priv, __p) \
167 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
168#define for_each_plane(pipe, p) \
169 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
168#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) 170#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
169 171
170#define for_each_crtc(dev, crtc) \ 172#define for_each_crtc(dev, crtc) \
@@ -639,6 +641,7 @@ struct intel_context {
639 } legacy_hw_ctx; 641 } legacy_hw_ctx;
640 642
641 /* Execlists */ 643 /* Execlists */
644 bool rcs_initialized;
642 struct { 645 struct {
643 struct drm_i915_gem_object *state; 646 struct drm_i915_gem_object *state;
644 struct intel_ringbuffer *ringbuf; 647 struct intel_ringbuffer *ringbuf;
@@ -712,6 +715,7 @@ enum intel_sbi_destination {
712#define QUIRK_LVDS_SSC_DISABLE (1<<1) 715#define QUIRK_LVDS_SSC_DISABLE (1<<1)
713#define QUIRK_INVERT_BRIGHTNESS (1<<2) 716#define QUIRK_INVERT_BRIGHTNESS (1<<2)
714#define QUIRK_BACKLIGHT_PRESENT (1<<3) 717#define QUIRK_BACKLIGHT_PRESENT (1<<3)
718#define QUIRK_PIPEB_FORCE (1<<4)
715 719
716struct intel_fbdev; 720struct intel_fbdev;
717struct intel_fbc_work; 721struct intel_fbc_work;
@@ -941,6 +945,23 @@ struct intel_rps_ei {
941 u32 media_c0; 945 u32 media_c0;
942}; 946};
943 947
948struct intel_rps_bdw_cal {
949 u32 it_threshold_pct; /* interrupt, in percentage */
950 u32 eval_interval; /* evaluation interval, in us */
951 u32 last_ts;
952 u32 last_c0;
953 bool is_up;
954};
955
956struct intel_rps_bdw_turbo {
957 struct intel_rps_bdw_cal up;
958 struct intel_rps_bdw_cal down;
959 struct timer_list flip_timer;
960 u32 timeout;
961 atomic_t flip_received;
962 struct work_struct work_max_freq;
963};
964
944struct intel_gen6_power_mgmt { 965struct intel_gen6_power_mgmt {
945 /* work and pm_iir are protected by dev_priv->irq_lock */ 966 /* work and pm_iir are protected by dev_priv->irq_lock */
946 struct work_struct work; 967 struct work_struct work;
@@ -974,6 +995,9 @@ struct intel_gen6_power_mgmt {
974 bool enabled; 995 bool enabled;
975 struct delayed_work delayed_resume_work; 996 struct delayed_work delayed_resume_work;
976 997
998 bool is_bdw_sw_turbo; /* Switch of BDW software turbo */
999 struct intel_rps_bdw_turbo sw_turbo; /* Calculate RP interrupt timing */
1000
977 /* manual wa residency calculations */ 1001 /* manual wa residency calculations */
978 struct intel_rps_ei up_ei, down_ei; 1002 struct intel_rps_ei up_ei, down_ei;
979 1003
@@ -1171,6 +1195,7 @@ struct i915_gem_mm {
1171}; 1195};
1172 1196
1173struct drm_i915_error_state_buf { 1197struct drm_i915_error_state_buf {
1198 struct drm_i915_private *i915;
1174 unsigned bytes; 1199 unsigned bytes;
1175 unsigned size; 1200 unsigned size;
1176 int err; 1201 int err;
@@ -1243,6 +1268,9 @@ struct i915_gpu_error {
1243 1268
1244 /* For missed irq/seqno simulation. */ 1269 /* For missed irq/seqno simulation. */
1245 unsigned int test_irq_rings; 1270 unsigned int test_irq_rings;
1271
1272 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1273 bool reload_in_reset;
1246}; 1274};
1247 1275
1248enum modeset_restore { 1276enum modeset_restore {
@@ -1505,6 +1533,9 @@ struct drm_i915_private {
1505 /* LVDS info */ 1533 /* LVDS info */
1506 bool no_aux_handshake; 1534 bool no_aux_handshake;
1507 1535
1536 /* protects panel power sequencer state */
1537 struct mutex pps_mutex;
1538
1508 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1539 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1509 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1540 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1510 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1541 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
@@ -1556,6 +1587,20 @@ struct drm_i915_private {
1556 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1587 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1557 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1588 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1558 1589
1590 /*
1591 * workarounds are currently applied at different places and
1592 * changes are being done to consolidate them so exact count is
1593 * not clear at this point, use a max value for now.
1594 */
1595#define I915_MAX_WA_REGS 16
1596 struct {
1597 u32 addr;
1598 u32 value;
1599 /* bitmask representing WA bits */
1600 u32 mask;
1601 } intel_wa_regs[I915_MAX_WA_REGS];
1602 u32 num_wa_regs;
1603
1559 /* Reclocking support */ 1604 /* Reclocking support */
1560 bool render_reclock_avail; 1605 bool render_reclock_avail;
1561 bool lvds_downclock_avail; 1606 bool lvds_downclock_avail;
@@ -1639,6 +1684,8 @@ struct drm_i915_private {
1639 */ 1684 */
1640 struct workqueue_struct *dp_wq; 1685 struct workqueue_struct *dp_wq;
1641 1686
1687 uint32_t bios_vgacntr;
1688
1642 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1689 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1643 * here! */ 1690 * here! */
1644 struct i915_dri1_state dri1; 1691 struct i915_dri1_state dri1;
@@ -2596,8 +2643,6 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2596int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2643int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2597 struct drm_file *file); 2644 struct drm_file *file);
2598 2645
2599/* i915_gem_render_state.c */
2600int i915_gem_render_state_init(struct intel_engine_cs *ring);
2601/* i915_gem_evict.c */ 2646/* i915_gem_evict.c */
2602int __must_check i915_gem_evict_something(struct drm_device *dev, 2647int __must_check i915_gem_evict_something(struct drm_device *dev,
2603 struct i915_address_space *vm, 2648 struct i915_address_space *vm,
@@ -2665,6 +2710,7 @@ void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2665int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 2710int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2666 const struct i915_error_state_file_priv *error); 2711 const struct i915_error_state_file_priv *error);
2667int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 2712int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2713 struct drm_i915_private *i915,
2668 size_t count, loff_t pos); 2714 size_t count, loff_t pos);
2669static inline void i915_error_state_buf_release( 2715static inline void i915_error_state_buf_release(
2670 struct drm_i915_error_state_buf *eb) 2716 struct drm_i915_error_state_buf *eb)
@@ -2679,7 +2725,7 @@ void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2679void i915_destroy_error_state(struct drm_device *dev); 2725void i915_destroy_error_state(struct drm_device *dev);
2680 2726
2681void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 2727void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2682const char *i915_cache_level_str(int type); 2728const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2683 2729
2684/* i915_cmd_parser.c */ 2730/* i915_cmd_parser.c */
2685int i915_cmd_parser_get_version(void); 2731int i915_cmd_parser_get_version(void);
@@ -2771,10 +2817,13 @@ extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2771extern void i915_redisable_vga(struct drm_device *dev); 2817extern void i915_redisable_vga(struct drm_device *dev);
2772extern void i915_redisable_vga_power_on(struct drm_device *dev); 2818extern void i915_redisable_vga_power_on(struct drm_device *dev);
2773extern bool intel_fbc_enabled(struct drm_device *dev); 2819extern bool intel_fbc_enabled(struct drm_device *dev);
2820extern void gen8_fbc_sw_flush(struct drm_device *dev, u32 value);
2774extern void intel_disable_fbc(struct drm_device *dev); 2821extern void intel_disable_fbc(struct drm_device *dev);
2775extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 2822extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2776extern void intel_init_pch_refclk(struct drm_device *dev); 2823extern void intel_init_pch_refclk(struct drm_device *dev);
2777extern void gen6_set_rps(struct drm_device *dev, u8 val); 2824extern void gen6_set_rps(struct drm_device *dev, u8 val);
2825extern void bdw_software_turbo(struct drm_device *dev);
2826extern void gen8_flip_interrupt(struct drm_device *dev);
2778extern void valleyview_set_rps(struct drm_device *dev, u8 val); 2827extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2779extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 2828extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2780 bool enable); 2829 bool enable);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1133bb3b2766..4ca3a6dcf10b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1085,7 +1085,13 @@ i915_gem_check_wedge(struct i915_gpu_error *error,
1085 if (i915_terminally_wedged(error)) 1085 if (i915_terminally_wedged(error))
1086 return -EIO; 1086 return -EIO;
1087 1087
1088 return -EAGAIN; 1088 /*
1089 * Check if GPU Reset is in progress - we need intel_ring_begin
1090 * to work properly to reinit the hw state while the gpu is
1091 * still marked as reset-in-progress. Handle this with a flag.
1092 */
1093 if (!error->reload_in_reset)
1094 return -EAGAIN;
1089 } 1095 }
1090 1096
1091 return 0; 1097 return 0;
@@ -2982,9 +2988,11 @@ int i915_gpu_idle(struct drm_device *dev)
2982 2988
2983 /* Flush everything onto the inactive list. */ 2989 /* Flush everything onto the inactive list. */
2984 for_each_ring(ring, dev_priv, i) { 2990 for_each_ring(ring, dev_priv, i) {
2985 ret = i915_switch_context(ring, ring->default_context); 2991 if (!i915.enable_execlists) {
2986 if (ret) 2992 ret = i915_switch_context(ring, ring->default_context);
2987 return ret; 2993 if (ret)
2994 return ret;
2995 }
2988 2996
2989 ret = intel_ring_idle(ring); 2997 ret = intel_ring_idle(ring);
2990 if (ret) 2998 if (ret)
@@ -4658,11 +4666,46 @@ intel_enable_blt(struct drm_device *dev)
4658 return true; 4666 return true;
4659} 4667}
4660 4668
4669static void init_unused_ring(struct drm_device *dev, u32 base)
4670{
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672
4673 I915_WRITE(RING_CTL(base), 0);
4674 I915_WRITE(RING_HEAD(base), 0);
4675 I915_WRITE(RING_TAIL(base), 0);
4676 I915_WRITE(RING_START(base), 0);
4677}
4678
4679static void init_unused_rings(struct drm_device *dev)
4680{
4681 if (IS_I830(dev)) {
4682 init_unused_ring(dev, PRB1_BASE);
4683 init_unused_ring(dev, SRB0_BASE);
4684 init_unused_ring(dev, SRB1_BASE);
4685 init_unused_ring(dev, SRB2_BASE);
4686 init_unused_ring(dev, SRB3_BASE);
4687 } else if (IS_GEN2(dev)) {
4688 init_unused_ring(dev, SRB0_BASE);
4689 init_unused_ring(dev, SRB1_BASE);
4690 } else if (IS_GEN3(dev)) {
4691 init_unused_ring(dev, PRB1_BASE);
4692 init_unused_ring(dev, PRB2_BASE);
4693 }
4694}
4695
4661int i915_gem_init_rings(struct drm_device *dev) 4696int i915_gem_init_rings(struct drm_device *dev)
4662{ 4697{
4663 struct drm_i915_private *dev_priv = dev->dev_private; 4698 struct drm_i915_private *dev_priv = dev->dev_private;
4664 int ret; 4699 int ret;
4665 4700
4701 /*
4702 * At least 830 can leave some of the unused rings
4703 * "active" (ie. head != tail) after resume which
4704 * will prevent c3 entry. Makes sure all unused rings
4705 * are totally idle.
4706 */
4707 init_unused_rings(dev);
4708
4666 ret = intel_init_render_ring_buffer(dev); 4709 ret = intel_init_render_ring_buffer(dev);
4667 if (ret) 4710 if (ret)
4668 return ret; 4711 return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 9683e62ec61a..a5221d8f1580 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -289,34 +289,23 @@ void i915_gem_context_reset(struct drm_device *dev)
289 struct drm_i915_private *dev_priv = dev->dev_private; 289 struct drm_i915_private *dev_priv = dev->dev_private;
290 int i; 290 int i;
291 291
292 /* Prevent the hardware from restoring the last context (which hung) on 292 /* In execlists mode we will unreference the context when the execlist
293 * the next switch */ 293 * queue is cleared and the requests destroyed.
294 */
295 if (i915.enable_execlists)
296 return;
297
294 for (i = 0; i < I915_NUM_RINGS; i++) { 298 for (i = 0; i < I915_NUM_RINGS; i++) {
295 struct intel_engine_cs *ring = &dev_priv->ring[i]; 299 struct intel_engine_cs *ring = &dev_priv->ring[i];
296 struct intel_context *dctx = ring->default_context;
297 struct intel_context *lctx = ring->last_context; 300 struct intel_context *lctx = ring->last_context;
298 301
299 /* Do a fake switch to the default context */ 302 if (lctx) {
300 if (lctx == dctx) 303 if (lctx->legacy_hw_ctx.rcs_state && i == RCS)
301 continue; 304 i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state);
302 305
303 if (!lctx) 306 i915_gem_context_unreference(lctx);
304 continue; 307 ring->last_context = NULL;
305
306 if (dctx->legacy_hw_ctx.rcs_state && i == RCS) {
307 WARN_ON(i915_gem_obj_ggtt_pin(dctx->legacy_hw_ctx.rcs_state,
308 get_context_alignment(dev), 0));
309 /* Fake a finish/inactive */
310 dctx->legacy_hw_ctx.rcs_state->base.write_domain = 0;
311 dctx->legacy_hw_ctx.rcs_state->active = 0;
312 } 308 }
313
314 if (lctx->legacy_hw_ctx.rcs_state && i == RCS)
315 i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state);
316
317 i915_gem_context_unreference(lctx);
318 i915_gem_context_reference(dctx);
319 ring->last_context = dctx;
320 } 309 }
321} 310}
322 311
@@ -412,12 +401,11 @@ int i915_gem_context_enable(struct drm_i915_private *dev_priv)
412 struct intel_engine_cs *ring; 401 struct intel_engine_cs *ring;
413 int ret, i; 402 int ret, i;
414 403
415 /* FIXME: We should make this work, even in reset */
416 if (i915_reset_in_progress(&dev_priv->gpu_error))
417 return 0;
418
419 BUG_ON(!dev_priv->ring[RCS].default_context); 404 BUG_ON(!dev_priv->ring[RCS].default_context);
420 405
406 if (i915.enable_execlists)
407 return 0;
408
421 for_each_ring(ring, dev_priv, i) { 409 for_each_ring(ring, dev_priv, i) {
422 ret = i915_switch_context(ring, ring->default_context); 410 ret = i915_switch_context(ring, ring->default_context);
423 if (ret) 411 if (ret)
@@ -479,6 +467,7 @@ mi_set_context(struct intel_engine_cs *ring,
479 struct intel_context *new_context, 467 struct intel_context *new_context,
480 u32 hw_flags) 468 u32 hw_flags)
481{ 469{
470 u32 flags = hw_flags | MI_MM_SPACE_GTT;
482 int ret; 471 int ret;
483 472
484 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB 473 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
@@ -492,6 +481,10 @@ mi_set_context(struct intel_engine_cs *ring,
492 return ret; 481 return ret;
493 } 482 }
494 483
484 /* These flags are for resource streamer on HSW+ */
485 if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8)
486 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
487
495 ret = intel_ring_begin(ring, 6); 488 ret = intel_ring_begin(ring, 6);
496 if (ret) 489 if (ret)
497 return ret; 490 return ret;
@@ -505,10 +498,7 @@ mi_set_context(struct intel_engine_cs *ring,
505 intel_ring_emit(ring, MI_NOOP); 498 intel_ring_emit(ring, MI_NOOP);
506 intel_ring_emit(ring, MI_SET_CONTEXT); 499 intel_ring_emit(ring, MI_SET_CONTEXT);
507 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) | 500 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) |
508 MI_MM_SPACE_GTT | 501 flags);
509 MI_SAVE_EXT_STATE_EN |
510 MI_RESTORE_EXT_STATE_EN |
511 hw_flags);
512 /* 502 /*
513 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP 503 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
514 * WaMiSetContext_Hang:snb,ivb,vlv 504 * WaMiSetContext_Hang:snb,ivb,vlv
@@ -558,7 +548,7 @@ static int do_switch(struct intel_engine_cs *ring,
558 from = ring->last_context; 548 from = ring->last_context;
559 549
560 if (to->ppgtt) { 550 if (to->ppgtt) {
561 ret = to->ppgtt->switch_mm(to->ppgtt, ring, false); 551 ret = to->ppgtt->switch_mm(to->ppgtt, ring);
562 if (ret) 552 if (ret)
563 goto unpin_out; 553 goto unpin_out;
564 } 554 }
@@ -638,6 +628,12 @@ done:
638 ring->last_context = to; 628 ring->last_context = to;
639 629
640 if (uninitialized) { 630 if (uninitialized) {
631 if (ring->init_context) {
632 ret = ring->init_context(ring);
633 if (ret)
634 DRM_ERROR("ring init context: %d\n", ret);
635 }
636
641 ret = i915_gem_render_state_init(ring); 637 ret = i915_gem_render_state_init(ring);
642 if (ret) 638 if (ret)
643 DRM_ERROR("init render state: %d\n", ret); 639 DRM_ERROR("init render state: %d\n", ret);
@@ -658,14 +654,19 @@ unpin_out:
658 * 654 *
659 * The context life cycle is simple. The context refcount is incremented and 655 * The context life cycle is simple. The context refcount is incremented and
660 * decremented by 1 and create and destroy. If the context is in use by the GPU, 656 * decremented by 1 and create and destroy. If the context is in use by the GPU,
661 * it will have a refoucnt > 1. This allows us to destroy the context abstract 657 * it will have a refcount > 1. This allows us to destroy the context abstract
662 * object while letting the normal object tracking destroy the backing BO. 658 * object while letting the normal object tracking destroy the backing BO.
659 *
660 * This function should not be used in execlists mode. Instead the context is
661 * switched by writing to the ELSP and requests keep a reference to their
662 * context.
663 */ 663 */
664int i915_switch_context(struct intel_engine_cs *ring, 664int i915_switch_context(struct intel_engine_cs *ring,
665 struct intel_context *to) 665 struct intel_context *to)
666{ 666{
667 struct drm_i915_private *dev_priv = ring->dev->dev_private; 667 struct drm_i915_private *dev_priv = ring->dev->dev_private;
668 668
669 WARN_ON(i915.enable_execlists);
669 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); 670 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
670 671
671 if (to->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */ 672 if (to->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4db237065610..6f410cfb0510 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -204,19 +204,12 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
204 204
205/* Broadwell Page Directory Pointer Descriptors */ 205/* Broadwell Page Directory Pointer Descriptors */
206static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, 206static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
207 uint64_t val, bool synchronous) 207 uint64_t val)
208{ 208{
209 struct drm_i915_private *dev_priv = ring->dev->dev_private;
210 int ret; 209 int ret;
211 210
212 BUG_ON(entry >= 4); 211 BUG_ON(entry >= 4);
213 212
214 if (synchronous) {
215 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
216 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
217 return 0;
218 }
219
220 ret = intel_ring_begin(ring, 6); 213 ret = intel_ring_begin(ring, 6);
221 if (ret) 214 if (ret)
222 return ret; 215 return ret;
@@ -233,8 +226,7 @@ static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
233} 226}
234 227
235static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, 228static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
236 struct intel_engine_cs *ring, 229 struct intel_engine_cs *ring)
237 bool synchronous)
238{ 230{
239 int i, ret; 231 int i, ret;
240 232
@@ -243,7 +235,7 @@ static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
243 235
244 for (i = used_pd - 1; i >= 0; i--) { 236 for (i = used_pd - 1; i >= 0; i--) {
245 dma_addr_t addr = ppgtt->pd_dma_addr[i]; 237 dma_addr_t addr = ppgtt->pd_dma_addr[i];
246 ret = gen8_write_pdp(ring, i, addr, synchronous); 238 ret = gen8_write_pdp(ring, i, addr);
247 if (ret) 239 if (ret)
248 return ret; 240 return ret;
249 } 241 }
@@ -708,29 +700,10 @@ static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
708} 700}
709 701
710static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, 702static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
711 struct intel_engine_cs *ring, 703 struct intel_engine_cs *ring)
712 bool synchronous)
713{ 704{
714 struct drm_device *dev = ppgtt->base.dev;
715 struct drm_i915_private *dev_priv = dev->dev_private;
716 int ret; 705 int ret;
717 706
718 /* If we're in reset, we can assume the GPU is sufficiently idle to
719 * manually frob these bits. Ideally we could use the ring functions,
720 * except our error handling makes it quite difficult (can't use
721 * intel_ring_begin, ring->flush, or intel_ring_advance)
722 *
723 * FIXME: We should try not to special case reset
724 */
725 if (synchronous ||
726 i915_reset_in_progress(&dev_priv->gpu_error)) {
727 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
728 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
729 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
730 POSTING_READ(RING_PP_DIR_BASE(ring));
731 return 0;
732 }
733
734 /* NB: TLBs must be flushed and invalidated before a switch */ 707 /* NB: TLBs must be flushed and invalidated before a switch */
735 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); 708 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
736 if (ret) 709 if (ret)
@@ -752,29 +725,10 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
752} 725}
753 726
754static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, 727static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
755 struct intel_engine_cs *ring, 728 struct intel_engine_cs *ring)
756 bool synchronous)
757{ 729{
758 struct drm_device *dev = ppgtt->base.dev;
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 int ret; 730 int ret;
761 731
762 /* If we're in reset, we can assume the GPU is sufficiently idle to
763 * manually frob these bits. Ideally we could use the ring functions,
764 * except our error handling makes it quite difficult (can't use
765 * intel_ring_begin, ring->flush, or intel_ring_advance)
766 *
767 * FIXME: We should try not to special case reset
768 */
769 if (synchronous ||
770 i915_reset_in_progress(&dev_priv->gpu_error)) {
771 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
772 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
773 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
774 POSTING_READ(RING_PP_DIR_BASE(ring));
775 return 0;
776 }
777
778 /* NB: TLBs must be flushed and invalidated before a switch */ 732 /* NB: TLBs must be flushed and invalidated before a switch */
779 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); 733 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
780 if (ret) 734 if (ret)
@@ -803,14 +757,11 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
803} 757}
804 758
805static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, 759static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
806 struct intel_engine_cs *ring, 760 struct intel_engine_cs *ring)
807 bool synchronous)
808{ 761{
809 struct drm_device *dev = ppgtt->base.dev; 762 struct drm_device *dev = ppgtt->base.dev;
810 struct drm_i915_private *dev_priv = dev->dev_private; 763 struct drm_i915_private *dev_priv = dev->dev_private;
811 764
812 if (!synchronous)
813 return 0;
814 765
815 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); 766 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
816 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); 767 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
@@ -826,12 +777,6 @@ static void gen8_ppgtt_enable(struct drm_device *dev)
826 struct intel_engine_cs *ring; 777 struct intel_engine_cs *ring;
827 int j; 778 int j;
828 779
829 /* In the case of execlists, PPGTT is enabled by the context descriptor
830 * and the PDPs are contained within the context itself. We don't
831 * need to do anything here. */
832 if (i915.enable_execlists)
833 return;
834
835 for_each_ring(ring, dev_priv, j) { 780 for_each_ring(ring, dev_priv, j) {
836 I915_WRITE(RING_MODE_GEN7(ring), 781 I915_WRITE(RING_MODE_GEN7(ring),
837 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); 782 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
@@ -1175,6 +1120,12 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
1175 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 1120 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1176 int i, ret = 0; 1121 int i, ret = 0;
1177 1122
1123 /* In the case of execlists, PPGTT is enabled by the context descriptor
1124 * and the PDPs are contained within the context itself. We don't
1125 * need to do anything here. */
1126 if (i915.enable_execlists)
1127 return 0;
1128
1178 if (!USES_PPGTT(dev)) 1129 if (!USES_PPGTT(dev))
1179 return 0; 1130 return 0;
1180 1131
@@ -1189,7 +1140,7 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
1189 1140
1190 if (ppgtt) { 1141 if (ppgtt) {
1191 for_each_ring(ring, dev_priv, i) { 1142 for_each_ring(ring, dev_priv, i) {
1192 ret = ppgtt->switch_mm(ppgtt, ring, true); 1143 ret = ppgtt->switch_mm(ppgtt, ring);
1193 if (ret != 0) 1144 if (ret != 0)
1194 return ret; 1145 return ret;
1195 } 1146 }
@@ -2190,8 +2141,10 @@ static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2190 /* Keep GGTT vmas first to make debug easier */ 2141 /* Keep GGTT vmas first to make debug easier */
2191 if (i915_is_ggtt(vm)) 2142 if (i915_is_ggtt(vm))
2192 list_add(&vma->vma_link, &obj->vma_list); 2143 list_add(&vma->vma_link, &obj->vma_list);
2193 else 2144 else {
2194 list_add_tail(&vma->vma_link, &obj->vma_list); 2145 list_add_tail(&vma->vma_link, &obj->vma_list);
2146 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2147 }
2195 2148
2196 return vma; 2149 return vma;
2197} 2150}
@@ -2206,8 +2159,5 @@ i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2206 if (!vma) 2159 if (!vma)
2207 vma = __i915_gem_vma_create(obj, vm); 2160 vma = __i915_gem_vma_create(obj, vm);
2208 2161
2209 if (!i915_is_ggtt(vm))
2210 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2211
2212 return vma; 2162 return vma;
2213} 2163}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 6280648d4805..d5c14af51e99 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -264,8 +264,7 @@ struct i915_hw_ppgtt {
264 264
265 int (*enable)(struct i915_hw_ppgtt *ppgtt); 265 int (*enable)(struct i915_hw_ppgtt *ppgtt);
266 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 266 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
267 struct intel_engine_cs *ring, 267 struct intel_engine_cs *ring);
268 bool synchronous);
269 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 268 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
270}; 269};
271 270
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index e60be3f552a6..a9a62d75aa57 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -28,13 +28,6 @@
28#include "i915_drv.h" 28#include "i915_drv.h"
29#include "intel_renderstate.h" 29#include "intel_renderstate.h"
30 30
31struct render_state {
32 const struct intel_renderstate_rodata *rodata;
33 struct drm_i915_gem_object *obj;
34 u64 ggtt_offset;
35 int gen;
36};
37
38static const struct intel_renderstate_rodata * 31static const struct intel_renderstate_rodata *
39render_state_get_rodata(struct drm_device *dev, const int gen) 32render_state_get_rodata(struct drm_device *dev, const int gen)
40{ 33{
@@ -127,30 +120,47 @@ static int render_state_setup(struct render_state *so)
127 return 0; 120 return 0;
128} 121}
129 122
130static void render_state_fini(struct render_state *so) 123void i915_gem_render_state_fini(struct render_state *so)
131{ 124{
132 i915_gem_object_ggtt_unpin(so->obj); 125 i915_gem_object_ggtt_unpin(so->obj);
133 drm_gem_object_unreference(&so->obj->base); 126 drm_gem_object_unreference(&so->obj->base);
134} 127}
135 128
136int i915_gem_render_state_init(struct intel_engine_cs *ring) 129int i915_gem_render_state_prepare(struct intel_engine_cs *ring,
130 struct render_state *so)
137{ 131{
138 struct render_state so;
139 int ret; 132 int ret;
140 133
141 if (WARN_ON(ring->id != RCS)) 134 if (WARN_ON(ring->id != RCS))
142 return -ENOENT; 135 return -ENOENT;
143 136
144 ret = render_state_init(&so, ring->dev); 137 ret = render_state_init(so, ring->dev);
145 if (ret) 138 if (ret)
146 return ret; 139 return ret;
147 140
148 if (so.rodata == NULL) 141 if (so->rodata == NULL)
149 return 0; 142 return 0;
150 143
151 ret = render_state_setup(&so); 144 ret = render_state_setup(so);
145 if (ret) {
146 i915_gem_render_state_fini(so);
147 return ret;
148 }
149
150 return 0;
151}
152
153int i915_gem_render_state_init(struct intel_engine_cs *ring)
154{
155 struct render_state so;
156 int ret;
157
158 ret = i915_gem_render_state_prepare(ring, &so);
152 if (ret) 159 if (ret)
153 goto out; 160 return ret;
161
162 if (so.rodata == NULL)
163 return 0;
154 164
155 ret = ring->dispatch_execbuffer(ring, 165 ret = ring->dispatch_execbuffer(ring,
156 so.ggtt_offset, 166 so.ggtt_offset,
@@ -164,6 +174,6 @@ int i915_gem_render_state_init(struct intel_engine_cs *ring)
164 ret = __i915_add_request(ring, NULL, so.obj, NULL); 174 ret = __i915_add_request(ring, NULL, so.obj, NULL);
165 /* __i915_add_request moves object to inactive if it fails */ 175 /* __i915_add_request moves object to inactive if it fails */
166out: 176out:
167 render_state_fini(&so); 177 i915_gem_render_state_fini(&so);
168 return ret; 178 return ret;
169} 179}
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.h b/drivers/gpu/drm/i915/i915_gem_render_state.h
new file mode 100644
index 000000000000..c44961ed3fad
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.h
@@ -0,0 +1,47 @@
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef _I915_GEM_RENDER_STATE_H_
25#define _I915_GEM_RENDER_STATE_H_
26
27#include <linux/types.h>
28
29struct intel_renderstate_rodata {
30 const u32 *reloc;
31 const u32 *batch;
32 const u32 batch_items;
33};
34
35struct render_state {
36 const struct intel_renderstate_rodata *rodata;
37 struct drm_i915_gem_object *obj;
38 u64 ggtt_offset;
39 int gen;
40};
41
42int i915_gem_render_state_init(struct intel_engine_cs *ring);
43void i915_gem_render_state_fini(struct render_state *so);
44int i915_gem_render_state_prepare(struct intel_engine_cs *ring,
45 struct render_state *so);
46
47#endif /* _I915_GEM_RENDER_STATE_H_ */
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 7e623bf097a1..2cefb597df6d 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -91,7 +91,14 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
91 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 91 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
92 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 92 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
93 93
94 if (IS_VALLEYVIEW(dev)) { 94 if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
95 /*
96 * On BDW+, swizzling is not used. We leave the CPU memory
97 * controller in charge of optimizing memory accesses without
98 * the extra address manipulation GPU side.
99 *
100 * VLV and CHV don't have GPU swizzling.
101 */
95 swizzle_x = I915_BIT_6_SWIZZLE_NONE; 102 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
96 swizzle_y = I915_BIT_6_SWIZZLE_NONE; 103 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
97 } else if (INTEL_INFO(dev)->gen >= 6) { 104 } else if (INTEL_INFO(dev)->gen >= 6) {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 35e70d5d6282..2c87a797213f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -208,7 +208,7 @@ static void print_error_buffers(struct drm_i915_error_state_buf *m,
208 err_puts(m, err->userptr ? " userptr" : ""); 208 err_puts(m, err->userptr ? " userptr" : "");
209 err_puts(m, err->ring != -1 ? " " : ""); 209 err_puts(m, err->ring != -1 ? " " : "");
210 err_puts(m, ring_str(err->ring)); 210 err_puts(m, ring_str(err->ring));
211 err_puts(m, i915_cache_level_str(err->cache_level)); 211 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
212 212
213 if (err->name) 213 if (err->name)
214 err_printf(m, " (name: %d)", err->name); 214 err_printf(m, " (name: %d)", err->name);
@@ -494,9 +494,11 @@ out:
494} 494}
495 495
496int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 496int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
497 struct drm_i915_private *i915,
497 size_t count, loff_t pos) 498 size_t count, loff_t pos)
498{ 499{
499 memset(ebuf, 0, sizeof(*ebuf)); 500 memset(ebuf, 0, sizeof(*ebuf));
501 ebuf->i915 = i915;
500 502
501 /* We need to have enough room to store any i915_error_state printf 503 /* We need to have enough room to store any i915_error_state printf
502 * so that we can move it to start position. 504 * so that we can move it to start position.
@@ -558,24 +560,54 @@ static void i915_error_state_free(struct kref *error_ref)
558} 560}
559 561
560static struct drm_i915_error_object * 562static struct drm_i915_error_object *
561i915_error_object_create_sized(struct drm_i915_private *dev_priv, 563i915_error_object_create(struct drm_i915_private *dev_priv,
562 struct drm_i915_gem_object *src, 564 struct drm_i915_gem_object *src,
563 struct i915_address_space *vm, 565 struct i915_address_space *vm)
564 const int num_pages)
565{ 566{
566 struct drm_i915_error_object *dst; 567 struct drm_i915_error_object *dst;
567 int i; 568 int num_pages;
569 bool use_ggtt;
570 int i = 0;
568 u32 reloc_offset; 571 u32 reloc_offset;
569 572
570 if (src == NULL || src->pages == NULL) 573 if (src == NULL || src->pages == NULL)
571 return NULL; 574 return NULL;
572 575
576 num_pages = src->base.size >> PAGE_SHIFT;
577
573 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 578 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
574 if (dst == NULL) 579 if (dst == NULL)
575 return NULL; 580 return NULL;
576 581
577 reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm); 582 if (i915_gem_obj_bound(src, vm))
578 for (i = 0; i < num_pages; i++) { 583 dst->gtt_offset = i915_gem_obj_offset(src, vm);
584 else
585 dst->gtt_offset = -1;
586
587 reloc_offset = dst->gtt_offset;
588 use_ggtt = (src->cache_level == I915_CACHE_NONE &&
589 i915_is_ggtt(vm) &&
590 src->has_global_gtt_mapping &&
591 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
592
593 /* Cannot access stolen address directly, try to use the aperture */
594 if (src->stolen) {
595 use_ggtt = true;
596
597 if (!src->has_global_gtt_mapping)
598 goto unwind;
599
600 reloc_offset = i915_gem_obj_ggtt_offset(src);
601 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
602 goto unwind;
603 }
604
605 /* Cannot access snooped pages through the aperture */
606 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
607 goto unwind;
608
609 dst->page_count = num_pages;
610 while (num_pages--) {
579 unsigned long flags; 611 unsigned long flags;
580 void *d; 612 void *d;
581 613
@@ -584,10 +616,7 @@ i915_error_object_create_sized(struct drm_i915_private *dev_priv,
584 goto unwind; 616 goto unwind;
585 617
586 local_irq_save(flags); 618 local_irq_save(flags);
587 if (src->cache_level == I915_CACHE_NONE && 619 if (use_ggtt) {
588 reloc_offset < dev_priv->gtt.mappable_end &&
589 src->has_global_gtt_mapping &&
590 i915_is_ggtt(vm)) {
591 void __iomem *s; 620 void __iomem *s;
592 621
593 /* Simply ignore tiling or any overlapping fence. 622 /* Simply ignore tiling or any overlapping fence.
@@ -599,14 +628,6 @@ i915_error_object_create_sized(struct drm_i915_private *dev_priv,
599 reloc_offset); 628 reloc_offset);
600 memcpy_fromio(d, s, PAGE_SIZE); 629 memcpy_fromio(d, s, PAGE_SIZE);
601 io_mapping_unmap_atomic(s); 630 io_mapping_unmap_atomic(s);
602 } else if (src->stolen) {
603 unsigned long offset;
604
605 offset = dev_priv->mm.stolen_base;
606 offset += src->stolen->start;
607 offset += i << PAGE_SHIFT;
608
609 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
610 } else { 631 } else {
611 struct page *page; 632 struct page *page;
612 void *s; 633 void *s;
@@ -623,11 +644,9 @@ i915_error_object_create_sized(struct drm_i915_private *dev_priv,
623 } 644 }
624 local_irq_restore(flags); 645 local_irq_restore(flags);
625 646
626 dst->pages[i] = d; 647 dst->pages[i++] = d;
627
628 reloc_offset += PAGE_SIZE; 648 reloc_offset += PAGE_SIZE;
629 } 649 }
630 dst->page_count = num_pages;
631 650
632 return dst; 651 return dst;
633 652
@@ -637,13 +656,8 @@ unwind:
637 kfree(dst); 656 kfree(dst);
638 return NULL; 657 return NULL;
639} 658}
640#define i915_error_object_create(dev_priv, src, vm) \
641 i915_error_object_create_sized((dev_priv), (src), (vm), \
642 (src)->base.size>>PAGE_SHIFT)
643
644#define i915_error_ggtt_object_create(dev_priv, src) \ 659#define i915_error_ggtt_object_create(dev_priv, src) \
645 i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \ 660 i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
646 (src)->base.size>>PAGE_SHIFT)
647 661
648static void capture_bo(struct drm_i915_error_buffer *err, 662static void capture_bo(struct drm_i915_error_buffer *err,
649 struct i915_vma *vma) 663 struct i915_vma *vma)
@@ -900,9 +914,6 @@ static void i915_record_ring_state(struct drm_device *dev,
900 ering->hws = I915_READ(mmio); 914 ering->hws = I915_READ(mmio);
901 } 915 }
902 916
903 ering->cpu_ring_head = ring->buffer->head;
904 ering->cpu_ring_tail = ring->buffer->tail;
905
906 ering->hangcheck_score = ring->hangcheck.score; 917 ering->hangcheck_score = ring->hangcheck.score;
907 ering->hangcheck_action = ring->hangcheck.action; 918 ering->hangcheck_action = ring->hangcheck.action;
908 919
@@ -965,6 +976,7 @@ static void i915_gem_record_rings(struct drm_device *dev,
965 976
966 for (i = 0; i < I915_NUM_RINGS; i++) { 977 for (i = 0; i < I915_NUM_RINGS; i++) {
967 struct intel_engine_cs *ring = &dev_priv->ring[i]; 978 struct intel_engine_cs *ring = &dev_priv->ring[i];
979 struct intel_ringbuffer *rbuf;
968 980
969 error->ring[i].pid = -1; 981 error->ring[i].pid = -1;
970 982
@@ -992,8 +1004,7 @@ static void i915_gem_record_rings(struct drm_device *dev,
992 request->batch_obj, 1004 request->batch_obj,
993 vm); 1005 vm);
994 1006
995 if (HAS_BROKEN_CS_TLB(dev_priv->dev) && 1007 if (HAS_BROKEN_CS_TLB(dev_priv->dev))
996 ring->scratch.obj)
997 error->ring[i].wa_batchbuffer = 1008 error->ring[i].wa_batchbuffer =
998 i915_error_ggtt_object_create(dev_priv, 1009 i915_error_ggtt_object_create(dev_priv,
999 ring->scratch.obj); 1010 ring->scratch.obj);
@@ -1012,12 +1023,27 @@ static void i915_gem_record_rings(struct drm_device *dev,
1012 } 1023 }
1013 } 1024 }
1014 1025
1026 if (i915.enable_execlists) {
1027 /* TODO: This is only a small fix to keep basic error
1028 * capture working, but we need to add more information
1029 * for it to be useful (e.g. dump the context being
1030 * executed).
1031 */
1032 if (request)
1033 rbuf = request->ctx->engine[ring->id].ringbuf;
1034 else
1035 rbuf = ring->default_context->engine[ring->id].ringbuf;
1036 } else
1037 rbuf = ring->buffer;
1038
1039 error->ring[i].cpu_ring_head = rbuf->head;
1040 error->ring[i].cpu_ring_tail = rbuf->tail;
1041
1015 error->ring[i].ringbuffer = 1042 error->ring[i].ringbuffer =
1016 i915_error_ggtt_object_create(dev_priv, ring->buffer->obj); 1043 i915_error_ggtt_object_create(dev_priv, rbuf->obj);
1017 1044
1018 if (ring->status_page.obj) 1045 error->ring[i].hws_page =
1019 error->ring[i].hws_page = 1046 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
1020 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
1021 1047
1022 i915_gem_record_active_context(ring, error, &error->ring[i]); 1048 i915_gem_record_active_context(ring, error, &error->ring[i]);
1023 1049
@@ -1331,11 +1357,11 @@ void i915_destroy_error_state(struct drm_device *dev)
1331 kref_put(&error->ref, i915_error_state_free); 1357 kref_put(&error->ref, i915_error_state_free);
1332} 1358}
1333 1359
1334const char *i915_cache_level_str(int type) 1360const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1335{ 1361{
1336 switch (type) { 1362 switch (type) {
1337 case I915_CACHE_NONE: return " uncached"; 1363 case I915_CACHE_NONE: return " uncached";
1338 case I915_CACHE_LLC: return " snooped or LLC"; 1364 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1339 case I915_CACHE_L3_LLC: return " L3+LLC"; 1365 case I915_CACHE_L3_LLC: return " L3+LLC";
1340 case I915_CACHE_WT: return " WT"; 1366 case I915_CACHE_WT: return " WT";
1341 default: return ""; 1367 default: return "";
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7391697c25e7..c96ddc953531 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -238,7 +238,7 @@ static bool ivb_can_enable_err_int(struct drm_device *dev)
238 238
239 assert_spin_locked(&dev_priv->irq_lock); 239 assert_spin_locked(&dev_priv->irq_lock);
240 240
241 for_each_pipe(pipe) { 241 for_each_pipe(dev_priv, pipe) {
242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 242 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
243 243
244 if (crtc->cpu_fifo_underrun_disabled) 244 if (crtc->cpu_fifo_underrun_disabled)
@@ -296,7 +296,7 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
296 296
297 assert_spin_locked(&dev_priv->irq_lock); 297 assert_spin_locked(&dev_priv->irq_lock);
298 298
299 for_each_pipe(pipe) { 299 for_each_pipe(dev_priv, pipe) {
300 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 300 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
301 301
302 if (crtc->pch_fifo_underrun_disabled) 302 if (crtc->pch_fifo_underrun_disabled)
@@ -497,7 +497,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
497 old = !intel_crtc->cpu_fifo_underrun_disabled; 497 old = !intel_crtc->cpu_fifo_underrun_disabled;
498 intel_crtc->cpu_fifo_underrun_disabled = !enable; 498 intel_crtc->cpu_fifo_underrun_disabled = !enable;
499 499
500 if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) 500 if (HAS_GMCH_DISPLAY(dev))
501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); 501 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
502 else if (IS_GEN5(dev) || IS_GEN6(dev)) 502 else if (IS_GEN5(dev) || IS_GEN6(dev))
503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable); 503 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
@@ -1979,6 +1979,27 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1979 res1, res2); 1979 res1, res2);
1980} 1980}
1981 1981
1982void gen8_flip_interrupt(struct drm_device *dev)
1983{
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1985
1986 if (!dev_priv->rps.is_bdw_sw_turbo)
1987 return;
1988
1989 if(atomic_read(&dev_priv->rps.sw_turbo.flip_received)) {
1990 mod_timer(&dev_priv->rps.sw_turbo.flip_timer,
1991 usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies);
1992 }
1993 else {
1994 dev_priv->rps.sw_turbo.flip_timer.expires =
1995 usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies;
1996 add_timer(&dev_priv->rps.sw_turbo.flip_timer);
1997 atomic_set(&dev_priv->rps.sw_turbo.flip_received, true);
1998 }
1999
2000 bdw_software_turbo(dev);
2001}
2002
1982/* The RPS events need forcewake, so we add them to a work queue and mask their 2003/* The RPS events need forcewake, so we add them to a work queue and mask their
1983 * IMR bits until the work is done. Other interrupts can be processed without 2004 * IMR bits until the work is done. Other interrupts can be processed without
1984 * the work queue. */ 2005 * the work queue. */
@@ -2020,7 +2041,7 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
2020 int pipe; 2041 int pipe;
2021 2042
2022 spin_lock(&dev_priv->irq_lock); 2043 spin_lock(&dev_priv->irq_lock);
2023 for_each_pipe(pipe) { 2044 for_each_pipe(dev_priv, pipe) {
2024 int reg; 2045 int reg;
2025 u32 mask, iir_bit = 0; 2046 u32 mask, iir_bit = 0;
2026 2047
@@ -2065,9 +2086,10 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
2065 } 2086 }
2066 spin_unlock(&dev_priv->irq_lock); 2087 spin_unlock(&dev_priv->irq_lock);
2067 2088
2068 for_each_pipe(pipe) { 2089 for_each_pipe(dev_priv, pipe) {
2069 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 2090 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2070 intel_pipe_handle_vblank(dev, pipe); 2091 intel_pipe_handle_vblank(dev, pipe))
2092 intel_check_page_flip(dev, pipe);
2071 2093
2072 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { 2094 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
2073 intel_prepare_page_flip(dev, pipe); 2095 intel_prepare_page_flip(dev, pipe);
@@ -2234,7 +2256,7 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
2234 DRM_ERROR("PCH poison interrupt\n"); 2256 DRM_ERROR("PCH poison interrupt\n");
2235 2257
2236 if (pch_iir & SDE_FDI_MASK) 2258 if (pch_iir & SDE_FDI_MASK)
2237 for_each_pipe(pipe) 2259 for_each_pipe(dev_priv, pipe)
2238 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 2260 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2239 pipe_name(pipe), 2261 pipe_name(pipe),
2240 I915_READ(FDI_RX_IIR(pipe))); 2262 I915_READ(FDI_RX_IIR(pipe)));
@@ -2265,7 +2287,7 @@ static void ivb_err_int_handler(struct drm_device *dev)
2265 if (err_int & ERR_INT_POISON) 2287 if (err_int & ERR_INT_POISON)
2266 DRM_ERROR("Poison interrupt\n"); 2288 DRM_ERROR("Poison interrupt\n");
2267 2289
2268 for_each_pipe(pipe) { 2290 for_each_pipe(dev_priv, pipe) {
2269 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { 2291 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
2270 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 2292 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2271 false)) 2293 false))
@@ -2342,7 +2364,7 @@ static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2342 DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); 2364 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2343 2365
2344 if (pch_iir & SDE_FDI_MASK_CPT) 2366 if (pch_iir & SDE_FDI_MASK_CPT)
2345 for_each_pipe(pipe) 2367 for_each_pipe(dev_priv, pipe)
2346 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 2368 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2347 pipe_name(pipe), 2369 pipe_name(pipe),
2348 I915_READ(FDI_RX_IIR(pipe))); 2370 I915_READ(FDI_RX_IIR(pipe)));
@@ -2365,9 +2387,10 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2365 if (de_iir & DE_POISON) 2387 if (de_iir & DE_POISON)
2366 DRM_ERROR("Poison interrupt\n"); 2388 DRM_ERROR("Poison interrupt\n");
2367 2389
2368 for_each_pipe(pipe) { 2390 for_each_pipe(dev_priv, pipe) {
2369 if (de_iir & DE_PIPE_VBLANK(pipe)) 2391 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2370 intel_pipe_handle_vblank(dev, pipe); 2392 intel_pipe_handle_vblank(dev, pipe))
2393 intel_check_page_flip(dev, pipe);
2371 2394
2372 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 2395 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2373 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 2396 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
@@ -2415,9 +2438,10 @@ static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2415 if (de_iir & DE_GSE_IVB) 2438 if (de_iir & DE_GSE_IVB)
2416 intel_opregion_asle_intr(dev); 2439 intel_opregion_asle_intr(dev);
2417 2440
2418 for_each_pipe(pipe) { 2441 for_each_pipe(dev_priv, pipe) {
2419 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe))) 2442 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2420 intel_pipe_handle_vblank(dev, pipe); 2443 intel_pipe_handle_vblank(dev, pipe))
2444 intel_check_page_flip(dev, pipe);
2421 2445
2422 /* plane/pipes map 1:1 on ilk+ */ 2446 /* plane/pipes map 1:1 on ilk+ */
2423 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { 2447 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
@@ -2562,7 +2586,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2562 DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); 2586 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2563 } 2587 }
2564 2588
2565 for_each_pipe(pipe) { 2589 for_each_pipe(dev_priv, pipe) {
2566 uint32_t pipe_iir; 2590 uint32_t pipe_iir;
2567 2591
2568 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 2592 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
@@ -2572,8 +2596,9 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2572 if (pipe_iir) { 2596 if (pipe_iir) {
2573 ret = IRQ_HANDLED; 2597 ret = IRQ_HANDLED;
2574 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); 2598 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2575 if (pipe_iir & GEN8_PIPE_VBLANK) 2599 if (pipe_iir & GEN8_PIPE_VBLANK &&
2576 intel_pipe_handle_vblank(dev, pipe); 2600 intel_pipe_handle_vblank(dev, pipe))
2601 intel_check_page_flip(dev, pipe);
2577 2602
2578 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) { 2603 if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
2579 intel_prepare_page_flip(dev, pipe); 2604 intel_prepare_page_flip(dev, pipe);
@@ -2781,7 +2806,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
2781 2806
2782 if (eir & I915_ERROR_MEMORY_REFRESH) { 2807 if (eir & I915_ERROR_MEMORY_REFRESH) {
2783 pr_err("memory refresh error:\n"); 2808 pr_err("memory refresh error:\n");
2784 for_each_pipe(pipe) 2809 for_each_pipe(dev_priv, pipe)
2785 pr_err("pipe %c stat: 0x%08x\n", 2810 pr_err("pipe %c stat: 0x%08x\n",
2786 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 2811 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2787 /* pipestat has already been acked */ 2812 /* pipestat has already been acked */
@@ -2878,52 +2903,6 @@ void i915_handle_error(struct drm_device *dev, bool wedged,
2878 schedule_work(&dev_priv->gpu_error.work); 2903 schedule_work(&dev_priv->gpu_error.work);
2879} 2904}
2880 2905
2881static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2882{
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2886 struct drm_i915_gem_object *obj;
2887 struct intel_unpin_work *work;
2888 unsigned long flags;
2889 bool stall_detected;
2890
2891 /* Ignore early vblank irqs */
2892 if (intel_crtc == NULL)
2893 return;
2894
2895 spin_lock_irqsave(&dev->event_lock, flags);
2896 work = intel_crtc->unpin_work;
2897
2898 if (work == NULL ||
2899 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2900 !work->enable_stall_check) {
2901 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2902 spin_unlock_irqrestore(&dev->event_lock, flags);
2903 return;
2904 }
2905
2906 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2907 obj = work->pending_flip_obj;
2908 if (INTEL_INFO(dev)->gen >= 4) {
2909 int dspsurf = DSPSURF(intel_crtc->plane);
2910 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2911 i915_gem_obj_ggtt_offset(obj);
2912 } else {
2913 int dspaddr = DSPADDR(intel_crtc->plane);
2914 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2915 crtc->y * crtc->primary->fb->pitches[0] +
2916 crtc->x * crtc->primary->fb->bits_per_pixel/8);
2917 }
2918
2919 spin_unlock_irqrestore(&dev->event_lock, flags);
2920
2921 if (stall_detected) {
2922 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2923 intel_prepare_page_flip(dev, intel_crtc->plane);
2924 }
2925}
2926
2927/* Called from drm generic code, passed 'crtc' which 2906/* Called from drm generic code, passed 'crtc' which
2928 * we use as a pipe index 2907 * we use as a pipe index
2929 */ 2908 */
@@ -3459,7 +3438,7 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
3459 3438
3460 I915_WRITE(PORT_HOTPLUG_EN, 0); 3439 I915_WRITE(PORT_HOTPLUG_EN, 0);
3461 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3440 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3462 for_each_pipe(pipe) 3441 for_each_pipe(dev_priv, pipe)
3463 I915_WRITE(PIPESTAT(pipe), 0xffff); 3442 I915_WRITE(PIPESTAT(pipe), 0xffff);
3464 I915_WRITE(VLV_IIR, 0xffffffff); 3443 I915_WRITE(VLV_IIR, 0xffffffff);
3465 I915_WRITE(VLV_IMR, 0xffffffff); 3444 I915_WRITE(VLV_IMR, 0xffffffff);
@@ -3485,7 +3464,7 @@ static void gen8_irq_reset(struct drm_device *dev)
3485 3464
3486 gen8_gt_irq_reset(dev_priv); 3465 gen8_gt_irq_reset(dev_priv);
3487 3466
3488 for_each_pipe(pipe) 3467 for_each_pipe(dev_priv, pipe)
3489 if (intel_display_power_enabled(dev_priv, 3468 if (intel_display_power_enabled(dev_priv,
3490 POWER_DOMAIN_PIPE(pipe))) 3469 POWER_DOMAIN_PIPE(pipe)))
3491 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); 3470 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
@@ -3528,7 +3507,7 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
3528 I915_WRITE(PORT_HOTPLUG_EN, 0); 3507 I915_WRITE(PORT_HOTPLUG_EN, 0);
3529 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3508 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3530 3509
3531 for_each_pipe(pipe) 3510 for_each_pipe(dev_priv, pipe)
3532 I915_WRITE(PIPESTAT(pipe), 0xffff); 3511 I915_WRITE(PIPESTAT(pipe), 0xffff);
3533 3512
3534 I915_WRITE(VLV_IMR, 0xffffffff); 3513 I915_WRITE(VLV_IMR, 0xffffffff);
@@ -3799,8 +3778,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
3799 3778
3800static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) 3779static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3801{ 3780{
3802 int i;
3803
3804 /* These are interrupts we'll toggle with the ring mask register */ 3781 /* These are interrupts we'll toggle with the ring mask register */
3805 uint32_t gt_interrupts[] = { 3782 uint32_t gt_interrupts[] = {
3806 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | 3783 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
@@ -3817,15 +3794,15 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3817 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT 3794 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3818 }; 3795 };
3819 3796
3820 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3821 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3822
3823 dev_priv->pm_irq_mask = 0xffffffff; 3797 dev_priv->pm_irq_mask = 0xffffffff;
3798 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3799 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3800 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events);
3801 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3824} 3802}
3825 3803
3826static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 3804static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3827{ 3805{
3828 struct drm_device *dev = dev_priv->dev;
3829 uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE | 3806 uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
3830 GEN8_PIPE_CDCLK_CRC_DONE | 3807 GEN8_PIPE_CDCLK_CRC_DONE |
3831 GEN8_DE_PIPE_IRQ_FAULT_ERRORS; 3808 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
@@ -3836,7 +3813,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3836 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; 3813 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3837 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; 3814 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3838 3815
3839 for_each_pipe(pipe) 3816 for_each_pipe(dev_priv, pipe)
3840 if (intel_display_power_enabled(dev_priv, 3817 if (intel_display_power_enabled(dev_priv,
3841 POWER_DOMAIN_PIPE(pipe))) 3818 POWER_DOMAIN_PIPE(pipe)))
3842 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, 3819 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
@@ -3881,12 +3858,12 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
3881 */ 3858 */
3882 dev_priv->irq_mask = ~enable_mask; 3859 dev_priv->irq_mask = ~enable_mask;
3883 3860
3884 for_each_pipe(pipe) 3861 for_each_pipe(dev_priv, pipe)
3885 I915_WRITE(PIPESTAT(pipe), 0xffff); 3862 I915_WRITE(PIPESTAT(pipe), 0xffff);
3886 3863
3887 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3864 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3888 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); 3865 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3889 for_each_pipe(pipe) 3866 for_each_pipe(dev_priv, pipe)
3890 i915_enable_pipestat(dev_priv, pipe, pipestat_enable); 3867 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3891 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3868 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3892 3869
@@ -3923,7 +3900,7 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
3923 3900
3924 I915_WRITE(VLV_MASTER_IER, 0); 3901 I915_WRITE(VLV_MASTER_IER, 0);
3925 3902
3926 for_each_pipe(pipe) 3903 for_each_pipe(dev_priv, pipe)
3927 I915_WRITE(PIPESTAT(pipe), 0xffff); 3904 I915_WRITE(PIPESTAT(pipe), 0xffff);
3928 3905
3929 I915_WRITE(HWSTAM, 0xffffffff); 3906 I915_WRITE(HWSTAM, 0xffffffff);
@@ -3985,7 +3962,7 @@ do { \
3985 I915_WRITE(PORT_HOTPLUG_EN, 0); 3962 I915_WRITE(PORT_HOTPLUG_EN, 0);
3986 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3963 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3987 3964
3988 for_each_pipe(pipe) 3965 for_each_pipe(dev_priv, pipe)
3989 I915_WRITE(PIPESTAT(pipe), 0xffff); 3966 I915_WRITE(PIPESTAT(pipe), 0xffff);
3990 3967
3991 I915_WRITE(VLV_IMR, 0xffffffff); 3968 I915_WRITE(VLV_IMR, 0xffffffff);
@@ -4009,7 +3986,7 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
4009 struct drm_i915_private *dev_priv = dev->dev_private; 3986 struct drm_i915_private *dev_priv = dev->dev_private;
4010 int pipe; 3987 int pipe;
4011 3988
4012 for_each_pipe(pipe) 3989 for_each_pipe(dev_priv, pipe)
4013 I915_WRITE(PIPESTAT(pipe), 0); 3990 I915_WRITE(PIPESTAT(pipe), 0);
4014 I915_WRITE16(IMR, 0xffff); 3991 I915_WRITE16(IMR, 0xffff);
4015 I915_WRITE16(IER, 0x0); 3992 I915_WRITE16(IER, 0x0);
@@ -4063,7 +4040,7 @@ static bool i8xx_handle_vblank(struct drm_device *dev,
4063 return false; 4040 return false;
4064 4041
4065 if ((iir & flip_pending) == 0) 4042 if ((iir & flip_pending) == 0)
4066 return false; 4043 goto check_page_flip;
4067 4044
4068 intel_prepare_page_flip(dev, plane); 4045 intel_prepare_page_flip(dev, plane);
4069 4046
@@ -4074,11 +4051,14 @@ static bool i8xx_handle_vblank(struct drm_device *dev,
4074 * an interrupt per se, we watch for the change at vblank. 4051 * an interrupt per se, we watch for the change at vblank.
4075 */ 4052 */
4076 if (I915_READ16(ISR) & flip_pending) 4053 if (I915_READ16(ISR) & flip_pending)
4077 return false; 4054 goto check_page_flip;
4078 4055
4079 intel_finish_page_flip(dev, pipe); 4056 intel_finish_page_flip(dev, pipe);
4080
4081 return true; 4057 return true;
4058
4059check_page_flip:
4060 intel_check_page_flip(dev, pipe);
4061 return false;
4082} 4062}
4083 4063
4084static irqreturn_t i8xx_irq_handler(int irq, void *arg) 4064static irqreturn_t i8xx_irq_handler(int irq, void *arg)
@@ -4109,7 +4089,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4109 "Command parser error, iir 0x%08x", 4089 "Command parser error, iir 0x%08x",
4110 iir); 4090 iir);
4111 4091
4112 for_each_pipe(pipe) { 4092 for_each_pipe(dev_priv, pipe) {
4113 int reg = PIPESTAT(pipe); 4093 int reg = PIPESTAT(pipe);
4114 pipe_stats[pipe] = I915_READ(reg); 4094 pipe_stats[pipe] = I915_READ(reg);
4115 4095
@@ -4129,7 +4109,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4129 if (iir & I915_USER_INTERRUPT) 4109 if (iir & I915_USER_INTERRUPT)
4130 notify_ring(dev, &dev_priv->ring[RCS]); 4110 notify_ring(dev, &dev_priv->ring[RCS]);
4131 4111
4132 for_each_pipe(pipe) { 4112 for_each_pipe(dev_priv, pipe) {
4133 int plane = pipe; 4113 int plane = pipe;
4134 if (HAS_FBC(dev)) 4114 if (HAS_FBC(dev))
4135 plane = !plane; 4115 plane = !plane;
@@ -4157,7 +4137,7 @@ static void i8xx_irq_uninstall(struct drm_device * dev)
4157 struct drm_i915_private *dev_priv = dev->dev_private; 4137 struct drm_i915_private *dev_priv = dev->dev_private;
4158 int pipe; 4138 int pipe;
4159 4139
4160 for_each_pipe(pipe) { 4140 for_each_pipe(dev_priv, pipe) {
4161 /* Clear enable bits; then clear status bits */ 4141 /* Clear enable bits; then clear status bits */
4162 I915_WRITE(PIPESTAT(pipe), 0); 4142 I915_WRITE(PIPESTAT(pipe), 0);
4163 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 4143 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
@@ -4178,7 +4158,7 @@ static void i915_irq_preinstall(struct drm_device * dev)
4178 } 4158 }
4179 4159
4180 I915_WRITE16(HWSTAM, 0xeffe); 4160 I915_WRITE16(HWSTAM, 0xeffe);
4181 for_each_pipe(pipe) 4161 for_each_pipe(dev_priv, pipe)
4182 I915_WRITE(PIPESTAT(pipe), 0); 4162 I915_WRITE(PIPESTAT(pipe), 0);
4183 I915_WRITE(IMR, 0xffffffff); 4163 I915_WRITE(IMR, 0xffffffff);
4184 I915_WRITE(IER, 0x0); 4164 I915_WRITE(IER, 0x0);
@@ -4248,7 +4228,7 @@ static bool i915_handle_vblank(struct drm_device *dev,
4248 return false; 4228 return false;
4249 4229
4250 if ((iir & flip_pending) == 0) 4230 if ((iir & flip_pending) == 0)
4251 return false; 4231 goto check_page_flip;
4252 4232
4253 intel_prepare_page_flip(dev, plane); 4233 intel_prepare_page_flip(dev, plane);
4254 4234
@@ -4259,11 +4239,14 @@ static bool i915_handle_vblank(struct drm_device *dev,
4259 * an interrupt per se, we watch for the change at vblank. 4239 * an interrupt per se, we watch for the change at vblank.
4260 */ 4240 */
4261 if (I915_READ(ISR) & flip_pending) 4241 if (I915_READ(ISR) & flip_pending)
4262 return false; 4242 goto check_page_flip;
4263 4243
4264 intel_finish_page_flip(dev, pipe); 4244 intel_finish_page_flip(dev, pipe);
4265
4266 return true; 4245 return true;
4246
4247check_page_flip:
4248 intel_check_page_flip(dev, pipe);
4249 return false;
4267} 4250}
4268 4251
4269static irqreturn_t i915_irq_handler(int irq, void *arg) 4252static irqreturn_t i915_irq_handler(int irq, void *arg)
@@ -4293,7 +4276,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4293 "Command parser error, iir 0x%08x", 4276 "Command parser error, iir 0x%08x",
4294 iir); 4277 iir);
4295 4278
4296 for_each_pipe(pipe) { 4279 for_each_pipe(dev_priv, pipe) {
4297 int reg = PIPESTAT(pipe); 4280 int reg = PIPESTAT(pipe);
4298 pipe_stats[pipe] = I915_READ(reg); 4281 pipe_stats[pipe] = I915_READ(reg);
4299 4282
@@ -4319,7 +4302,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4319 if (iir & I915_USER_INTERRUPT) 4302 if (iir & I915_USER_INTERRUPT)
4320 notify_ring(dev, &dev_priv->ring[RCS]); 4303 notify_ring(dev, &dev_priv->ring[RCS]);
4321 4304
4322 for_each_pipe(pipe) { 4305 for_each_pipe(dev_priv, pipe) {
4323 int plane = pipe; 4306 int plane = pipe;
4324 if (HAS_FBC(dev)) 4307 if (HAS_FBC(dev))
4325 plane = !plane; 4308 plane = !plane;
@@ -4377,7 +4360,7 @@ static void i915_irq_uninstall(struct drm_device * dev)
4377 } 4360 }
4378 4361
4379 I915_WRITE16(HWSTAM, 0xffff); 4362 I915_WRITE16(HWSTAM, 0xffff);
4380 for_each_pipe(pipe) { 4363 for_each_pipe(dev_priv, pipe) {
4381 /* Clear enable bits; then clear status bits */ 4364 /* Clear enable bits; then clear status bits */
4382 I915_WRITE(PIPESTAT(pipe), 0); 4365 I915_WRITE(PIPESTAT(pipe), 0);
4383 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 4366 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
@@ -4397,7 +4380,7 @@ static void i965_irq_preinstall(struct drm_device * dev)
4397 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 4380 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4398 4381
4399 I915_WRITE(HWSTAM, 0xeffe); 4382 I915_WRITE(HWSTAM, 0xeffe);
4400 for_each_pipe(pipe) 4383 for_each_pipe(dev_priv, pipe)
4401 I915_WRITE(PIPESTAT(pipe), 0); 4384 I915_WRITE(PIPESTAT(pipe), 0);
4402 I915_WRITE(IMR, 0xffffffff); 4385 I915_WRITE(IMR, 0xffffffff);
4403 I915_WRITE(IER, 0x0); 4386 I915_WRITE(IER, 0x0);
@@ -4522,7 +4505,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4522 "Command parser error, iir 0x%08x", 4505 "Command parser error, iir 0x%08x",
4523 iir); 4506 iir);
4524 4507
4525 for_each_pipe(pipe) { 4508 for_each_pipe(dev_priv, pipe) {
4526 int reg = PIPESTAT(pipe); 4509 int reg = PIPESTAT(pipe);
4527 pipe_stats[pipe] = I915_READ(reg); 4510 pipe_stats[pipe] = I915_READ(reg);
4528 4511
@@ -4553,7 +4536,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4553 if (iir & I915_BSD_USER_INTERRUPT) 4536 if (iir & I915_BSD_USER_INTERRUPT)
4554 notify_ring(dev, &dev_priv->ring[VCS]); 4537 notify_ring(dev, &dev_priv->ring[VCS]);
4555 4538
4556 for_each_pipe(pipe) { 4539 for_each_pipe(dev_priv, pipe) {
4557 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && 4540 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4558 i915_handle_vblank(dev, pipe, pipe, iir)) 4541 i915_handle_vblank(dev, pipe, pipe, iir))
4559 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); 4542 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
@@ -4610,12 +4593,12 @@ static void i965_irq_uninstall(struct drm_device * dev)
4610 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 4593 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4611 4594
4612 I915_WRITE(HWSTAM, 0xffffffff); 4595 I915_WRITE(HWSTAM, 0xffffffff);
4613 for_each_pipe(pipe) 4596 for_each_pipe(dev_priv, pipe)
4614 I915_WRITE(PIPESTAT(pipe), 0); 4597 I915_WRITE(PIPESTAT(pipe), 0);
4615 I915_WRITE(IMR, 0xffffffff); 4598 I915_WRITE(IMR, 0xffffffff);
4616 I915_WRITE(IER, 0x0); 4599 I915_WRITE(IER, 0x0);
4617 4600
4618 for_each_pipe(pipe) 4601 for_each_pipe(dev_priv, pipe)
4619 I915_WRITE(PIPESTAT(pipe), 4602 I915_WRITE(PIPESTAT(pipe),
4620 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 4603 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4621 I915_WRITE(IIR, I915_READ(IIR)); 4604 I915_WRITE(IIR, I915_READ(IIR));
@@ -4673,8 +4656,8 @@ void intel_irq_init(struct drm_device *dev)
4673 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); 4656 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4674 4657
4675 /* Let's track the enabled rps events */ 4658 /* Let's track the enabled rps events */
4676 if (IS_VALLEYVIEW(dev)) 4659 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
4677 /* WaGsvRC0ResidenncyMethod:VLV */ 4660 /* WaGsvRC0ResidencyMethod:vlv */
4678 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; 4661 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4679 else 4662 else
4680 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; 4663 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1e4fb846d9a5..b65bdfc23ccb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1030,6 +1030,13 @@ enum punit_power_well {
1030#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 1030#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1031#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 1031#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
1032#define PGTBL_ER 0x02024 1032#define PGTBL_ER 0x02024
1033#define PRB0_BASE (0x2030-0x30)
1034#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1035#define PRB2_BASE (0x2050-0x30) /* gen3 */
1036#define SRB0_BASE (0x2100-0x30) /* gen2 */
1037#define SRB1_BASE (0x2110-0x30) /* gen2 */
1038#define SRB2_BASE (0x2120-0x30) /* 830 */
1039#define SRB3_BASE (0x2130-0x30) /* 830 */
1033#define RENDER_RING_BASE 0x02000 1040#define RENDER_RING_BASE 0x02000
1034#define BSD_RING_BASE 0x04000 1041#define BSD_RING_BASE 0x04000
1035#define GEN6_BSD_RING_BASE 0x12000 1042#define GEN6_BSD_RING_BASE 0x12000
@@ -1276,6 +1283,10 @@ enum punit_power_well {
1276#define INSTPM_TLB_INVALIDATE (1<<9) 1283#define INSTPM_TLB_INVALIDATE (1<<9)
1277#define INSTPM_SYNC_FLUSH (1<<5) 1284#define INSTPM_SYNC_FLUSH (1<<5)
1278#define ACTHD 0x020c8 1285#define ACTHD 0x020c8
1286#define MEM_MODE 0x020cc
1287#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1288#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1289#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
1279#define FW_BLC 0x020d8 1290#define FW_BLC 0x020d8
1280#define FW_BLC2 0x020dc 1291#define FW_BLC2 0x020dc
1281#define FW_BLC_SELF 0x020e0 /* 915+ only */ 1292#define FW_BLC_SELF 0x020e0 /* 915+ only */
@@ -4218,6 +4229,7 @@ enum punit_power_well {
4218#define DISPPLANE_NO_LINE_DOUBLE 0 4229#define DISPPLANE_NO_LINE_DOUBLE 0
4219#define DISPPLANE_STEREO_POLARITY_FIRST 0 4230#define DISPPLANE_STEREO_POLARITY_FIRST 0
4220#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 4231#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
4232#define DISPPLANE_ROTATE_180 (1<<15)
4221#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 4233#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
4222#define DISPPLANE_TILED (1<<10) 4234#define DISPPLANE_TILED (1<<10)
4223#define _DSPAADDR 0x70184 4235#define _DSPAADDR 0x70184
@@ -5356,8 +5368,7 @@ enum punit_power_well {
5356#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) 5368#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
5357#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) 5369#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
5358#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) 5370#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
5359#define PANEL_PORT_SELECT_DPB_VLV (1 << 30) 5371#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
5360#define PANEL_PORT_SELECT_DPC_VLV (2 << 30)
5361#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) 5372#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
5362#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) 5373#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
5363 5374
@@ -5566,6 +5577,10 @@ enum punit_power_well {
5566#define GEN8_UCGCTL6 0x9430 5577#define GEN8_UCGCTL6 0x9430
5567#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) 5578#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
5568 5579
5580#define TIMESTAMP_CTR 0x44070
5581#define FREQ_1_28_US(us) (((us) * 100) >> 7)
5582#define MCHBAR_PCU_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5960)
5583
5569#define GEN6_GFXPAUSE 0xA000 5584#define GEN6_GFXPAUSE 0xA000
5570#define GEN6_RPNSWREQ 0xA008 5585#define GEN6_RPNSWREQ 0xA008
5571#define GEN6_TURBO_DISABLE (1<<31) 5586#define GEN6_TURBO_DISABLE (1<<31)
@@ -5654,12 +5669,6 @@ enum punit_power_well {
5654 GEN6_PM_RP_DOWN_THRESHOLD | \ 5669 GEN6_PM_RP_DOWN_THRESHOLD | \
5655 GEN6_PM_RP_DOWN_TIMEOUT) 5670 GEN6_PM_RP_DOWN_TIMEOUT)
5656 5671
5657#define CHV_CZ_CLOCK_FREQ_MODE_200 200
5658#define CHV_CZ_CLOCK_FREQ_MODE_267 267
5659#define CHV_CZ_CLOCK_FREQ_MODE_320 320
5660#define CHV_CZ_CLOCK_FREQ_MODE_333 333
5661#define CHV_CZ_CLOCK_FREQ_MODE_400 400
5662
5663#define GEN7_GT_SCRATCH_BASE 0x4F100 5672#define GEN7_GT_SCRATCH_BASE 0x4F100
5664#define GEN7_GT_SCRATCH_REG_NUM 8 5673#define GEN7_GT_SCRATCH_REG_NUM 8
5665 5674
@@ -5975,15 +5984,7 @@ enum punit_power_well {
5975#define DDI_BUF_CTL_B 0x64100 5984#define DDI_BUF_CTL_B 0x64100
5976#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) 5985#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
5977#define DDI_BUF_CTL_ENABLE (1<<31) 5986#define DDI_BUF_CTL_ENABLE (1<<31)
5978#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */ 5987#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
5979#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
5980#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
5981#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
5982#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
5983#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
5984#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
5985#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
5986#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
5987#define DDI_BUF_EMP_MASK (0xf<<24) 5988#define DDI_BUF_EMP_MASK (0xf<<24)
5988#define DDI_BUF_PORT_REVERSAL (1<<16) 5989#define DDI_BUF_PORT_REVERSAL (1<<16)
5989#define DDI_BUF_IS_IDLE (1<<7) 5990#define DDI_BUF_IS_IDLE (1<<7)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index ae7fd8fc27f0..503847f18fdd 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -540,7 +540,7 @@ static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
540 540
541 memset(&error_priv, 0, sizeof(error_priv)); 541 memset(&error_priv, 0, sizeof(error_priv));
542 542
543 ret = i915_error_state_buf_init(&error_str, count, off); 543 ret = i915_error_state_buf_init(&error_str, to_i915(dev), count, off);
544 if (ret) 544 if (ret)
545 return ret; 545 return ret;
546 546
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 32d22339c130..b3e579b4428e 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -627,16 +627,16 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
627 627
628 switch (edp_link_params->preemphasis) { 628 switch (edp_link_params->preemphasis) {
629 case EDP_PREEMPHASIS_NONE: 629 case EDP_PREEMPHASIS_NONE:
630 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0; 630 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
631 break; 631 break;
632 case EDP_PREEMPHASIS_3_5dB: 632 case EDP_PREEMPHASIS_3_5dB:
633 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5; 633 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
634 break; 634 break;
635 case EDP_PREEMPHASIS_6dB: 635 case EDP_PREEMPHASIS_6dB:
636 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6; 636 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
637 break; 637 break;
638 case EDP_PREEMPHASIS_9_5dB: 638 case EDP_PREEMPHASIS_9_5dB:
639 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5; 639 dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
640 break; 640 break;
641 default: 641 default:
642 DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n", 642 DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
@@ -646,16 +646,16 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
646 646
647 switch (edp_link_params->vswing) { 647 switch (edp_link_params->vswing) {
648 case EDP_VSWING_0_4V: 648 case EDP_VSWING_0_4V:
649 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400; 649 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
650 break; 650 break;
651 case EDP_VSWING_0_6V: 651 case EDP_VSWING_0_6V:
652 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600; 652 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
653 break; 653 break;
654 case EDP_VSWING_0_8V: 654 case EDP_VSWING_0_8V:
655 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800; 655 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
656 break; 656 break;
657 case EDP_VSWING_1_2V: 657 case EDP_VSWING_1_2V:
658 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200; 658 dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
659 break; 659 break;
660 default: 660 default:
661 DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n", 661 DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 02d55843c78d..b63d4fa204a3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -28,98 +28,103 @@
28#include "i915_drv.h" 28#include "i915_drv.h"
29#include "intel_drv.h" 29#include "intel_drv.h"
30 30
31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
31/* HDMI/DVI modes ignore everything but the last 2 items. So we share 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to 37 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well 38 * automatically adapt to HDMI connections as well
34 */ 39 */
35static const u32 hsw_ddi_translations_dp[] = { 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, 41 { 0x00FFFFFF, 0x0006000E },
37 0x00D75FFF, 0x0005000A, 42 { 0x00D75FFF, 0x0005000A },
38 0x00C30FFF, 0x00040006, 43 { 0x00C30FFF, 0x00040006 },
39 0x80AAAFFF, 0x000B0000, 44 { 0x80AAAFFF, 0x000B0000 },
40 0x00FFFFFF, 0x0005000A, 45 { 0x00FFFFFF, 0x0005000A },
41 0x00D75FFF, 0x000C0004, 46 { 0x00D75FFF, 0x000C0004 },
42 0x80C30FFF, 0x000B0000, 47 { 0x80C30FFF, 0x000B0000 },
43 0x00FFFFFF, 0x00040006, 48 { 0x00FFFFFF, 0x00040006 },
44 0x80D75FFF, 0x000B0000, 49 { 0x80D75FFF, 0x000B0000 },
45}; 50};
46 51
47static const u32 hsw_ddi_translations_fdi[] = { 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
48 0x00FFFFFF, 0x0007000E, 53 { 0x00FFFFFF, 0x0007000E },
49 0x00D75FFF, 0x000F000A, 54 { 0x00D75FFF, 0x000F000A },
50 0x00C30FFF, 0x00060006, 55 { 0x00C30FFF, 0x00060006 },
51 0x00AAAFFF, 0x001E0000, 56 { 0x00AAAFFF, 0x001E0000 },
52 0x00FFFFFF, 0x000F000A, 57 { 0x00FFFFFF, 0x000F000A },
53 0x00D75FFF, 0x00160004, 58 { 0x00D75FFF, 0x00160004 },
54 0x00C30FFF, 0x001E0000, 59 { 0x00C30FFF, 0x001E0000 },
55 0x00FFFFFF, 0x00060006, 60 { 0x00FFFFFF, 0x00060006 },
56 0x00D75FFF, 0x001E0000, 61 { 0x00D75FFF, 0x001E0000 },
57}; 62};
58 63
59static const u32 hsw_ddi_translations_hdmi[] = { 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
60 /* Idx NT mV diff T mV diff db */ 65 /* Idx NT mV d T mV d db */
61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ 66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ 67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ 68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ 69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ 70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ 71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ 72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ 73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ 74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ 75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ 76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ 77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
73}; 78};
74 79
75static const u32 bdw_ddi_translations_edp[] = { 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
76 0x00FFFFFF, 0x00000012, 81 { 0x00FFFFFF, 0x00000012 },
77 0x00EBAFFF, 0x00020011, 82 { 0x00EBAFFF, 0x00020011 },
78 0x00C71FFF, 0x0006000F, 83 { 0x00C71FFF, 0x0006000F },
79 0x00AAAFFF, 0x000E000A, 84 { 0x00AAAFFF, 0x000E000A },
80 0x00FFFFFF, 0x00020011, 85 { 0x00FFFFFF, 0x00020011 },
81 0x00DB6FFF, 0x0005000F, 86 { 0x00DB6FFF, 0x0005000F },
82 0x00BEEFFF, 0x000A000C, 87 { 0x00BEEFFF, 0x000A000C },
83 0x00FFFFFF, 0x0005000F, 88 { 0x00FFFFFF, 0x0005000F },
84 0x00DB6FFF, 0x000A000C, 89 { 0x00DB6FFF, 0x000A000C },
85}; 90};
86 91
87static const u32 bdw_ddi_translations_dp[] = { 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
88 0x00FFFFFF, 0x0007000E, 93 { 0x00FFFFFF, 0x0007000E },
89 0x00D75FFF, 0x000E000A, 94 { 0x00D75FFF, 0x000E000A },
90 0x00BEFFFF, 0x00140006, 95 { 0x00BEFFFF, 0x00140006 },
91 0x80B2CFFF, 0x001B0002, 96 { 0x80B2CFFF, 0x001B0002 },
92 0x00FFFFFF, 0x000E000A, 97 { 0x00FFFFFF, 0x000E000A },
93 0x00D75FFF, 0x00180004, 98 { 0x00D75FFF, 0x00180004 },
94 0x80CB2FFF, 0x001B0002, 99 { 0x80CB2FFF, 0x001B0002 },
95 0x00F7DFFF, 0x00180004, 100 { 0x00F7DFFF, 0x00180004 },
96 0x80D75FFF, 0x001B0002, 101 { 0x80D75FFF, 0x001B0002 },
97}; 102};
98 103
99static const u32 bdw_ddi_translations_fdi[] = { 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
100 0x00FFFFFF, 0x0001000E, 105 { 0x00FFFFFF, 0x0001000E },
101 0x00D75FFF, 0x0004000A, 106 { 0x00D75FFF, 0x0004000A },
102 0x00C30FFF, 0x00070006, 107 { 0x00C30FFF, 0x00070006 },
103 0x00AAAFFF, 0x000C0000, 108 { 0x00AAAFFF, 0x000C0000 },
104 0x00FFFFFF, 0x0004000A, 109 { 0x00FFFFFF, 0x0004000A },
105 0x00D75FFF, 0x00090004, 110 { 0x00D75FFF, 0x00090004 },
106 0x00C30FFF, 0x000C0000, 111 { 0x00C30FFF, 0x000C0000 },
107 0x00FFFFFF, 0x00070006, 112 { 0x00FFFFFF, 0x00070006 },
108 0x00D75FFF, 0x000C0000, 113 { 0x00D75FFF, 0x000C0000 },
109}; 114};
110 115
111static const u32 bdw_ddi_translations_hdmi[] = { 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
112 /* Idx NT mV diff T mV diff db */ 117 /* Idx NT mV d T mV df db */
113 0x00FFFFFF, 0x0007000E, /* 0: 400 400 0 */ 118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
114 0x00D75FFF, 0x000E000A, /* 1: 400 600 3.5 */ 119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
115 0x00BEFFFF, 0x00140006, /* 2: 400 800 6 */ 120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
116 0x00FFFFFF, 0x0009000D, /* 3: 450 450 0 */ 121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
117 0x00FFFFFF, 0x000E000A, /* 4: 600 600 0 */ 122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
118 0x00D7FFFF, 0x00140006, /* 5: 600 800 2.5 */ 123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
119 0x80CB2FFF, 0x001B0002, /* 6: 600 1000 4.5 */ 124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
120 0x00FFFFFF, 0x00140006, /* 7: 800 800 0 */ 125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
121 0x80E79FFF, 0x001B0002, /* 8: 800 1000 2 */ 126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
122 0x80FFFFFF, 0x001B0002, /* 9: 1000 1000 0 */ 127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
123}; 128};
124 129
125enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 130enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
@@ -158,25 +163,25 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
158 u32 reg; 163 u32 reg;
159 int i, n_hdmi_entries, hdmi_800mV_0dB; 164 int i, n_hdmi_entries, hdmi_800mV_0dB;
160 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 165 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
161 const u32 *ddi_translations_fdi; 166 const struct ddi_buf_trans *ddi_translations_fdi;
162 const u32 *ddi_translations_dp; 167 const struct ddi_buf_trans *ddi_translations_dp;
163 const u32 *ddi_translations_edp; 168 const struct ddi_buf_trans *ddi_translations_edp;
164 const u32 *ddi_translations_hdmi; 169 const struct ddi_buf_trans *ddi_translations_hdmi;
165 const u32 *ddi_translations; 170 const struct ddi_buf_trans *ddi_translations;
166 171
167 if (IS_BROADWELL(dev)) { 172 if (IS_BROADWELL(dev)) {
168 ddi_translations_fdi = bdw_ddi_translations_fdi; 173 ddi_translations_fdi = bdw_ddi_translations_fdi;
169 ddi_translations_dp = bdw_ddi_translations_dp; 174 ddi_translations_dp = bdw_ddi_translations_dp;
170 ddi_translations_edp = bdw_ddi_translations_edp; 175 ddi_translations_edp = bdw_ddi_translations_edp;
171 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 176 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
172 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi) / 2; 177 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
173 hdmi_800mV_0dB = 7; 178 hdmi_800mV_0dB = 7;
174 } else if (IS_HASWELL(dev)) { 179 } else if (IS_HASWELL(dev)) {
175 ddi_translations_fdi = hsw_ddi_translations_fdi; 180 ddi_translations_fdi = hsw_ddi_translations_fdi;
176 ddi_translations_dp = hsw_ddi_translations_dp; 181 ddi_translations_dp = hsw_ddi_translations_dp;
177 ddi_translations_edp = hsw_ddi_translations_dp; 182 ddi_translations_edp = hsw_ddi_translations_dp;
178 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 183 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
179 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi) / 2; 184 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
180 hdmi_800mV_0dB = 6; 185 hdmi_800mV_0dB = 6;
181 } else { 186 } else {
182 WARN(1, "ddi translation table missing\n"); 187 WARN(1, "ddi translation table missing\n");
@@ -184,7 +189,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
184 ddi_translations_fdi = bdw_ddi_translations_fdi; 189 ddi_translations_fdi = bdw_ddi_translations_fdi;
185 ddi_translations_dp = bdw_ddi_translations_dp; 190 ddi_translations_dp = bdw_ddi_translations_dp;
186 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 191 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
187 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi) / 2; 192 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
188 hdmi_800mV_0dB = 7; 193 hdmi_800mV_0dB = 7;
189 } 194 }
190 195
@@ -211,7 +216,9 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
211 216
212 for (i = 0, reg = DDI_BUF_TRANS(port); 217 for (i = 0, reg = DDI_BUF_TRANS(port);
213 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { 218 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
214 I915_WRITE(reg, ddi_translations[i]); 219 I915_WRITE(reg, ddi_translations[i].trans1);
220 reg += 4;
221 I915_WRITE(reg, ddi_translations[i].trans2);
215 reg += 4; 222 reg += 4;
216 } 223 }
217 224
@@ -221,10 +228,10 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
221 hdmi_level = hdmi_800mV_0dB; 228 hdmi_level = hdmi_800mV_0dB;
222 229
223 /* Entry 9 is for HDMI: */ 230 /* Entry 9 is for HDMI: */
224 for (i = 0; i < 2; i++) { 231 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
225 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level * 2 + i]); 232 reg += 4;
226 reg += 4; 233 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
227 } 234 reg += 4;
228} 235}
229 236
230/* Program DDI buffers translations for DP. By default, program ports A-D in DP 237/* Program DDI buffers translations for DP. By default, program ports A-D in DP
@@ -241,18 +248,6 @@ void intel_prepare_ddi(struct drm_device *dev)
241 intel_prepare_ddi_buffers(dev, port); 248 intel_prepare_ddi_buffers(dev, port);
242} 249}
243 250
244static const long hsw_ddi_buf_ctl_values[] = {
245 DDI_BUF_EMP_400MV_0DB_HSW,
246 DDI_BUF_EMP_400MV_3_5DB_HSW,
247 DDI_BUF_EMP_400MV_6DB_HSW,
248 DDI_BUF_EMP_400MV_9_5DB_HSW,
249 DDI_BUF_EMP_600MV_0DB_HSW,
250 DDI_BUF_EMP_600MV_3_5DB_HSW,
251 DDI_BUF_EMP_600MV_6DB_HSW,
252 DDI_BUF_EMP_800MV_0DB_HSW,
253 DDI_BUF_EMP_800MV_3_5DB_HSW
254};
255
256static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 251static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
257 enum port port) 252 enum port port)
258{ 253{
@@ -312,7 +307,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
312 307
313 /* Start the training iterating through available voltages and emphasis, 308 /* Start the training iterating through available voltages and emphasis,
314 * testing each value twice. */ 309 * testing each value twice. */
315 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { 310 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
316 /* Configure DP_TP_CTL with auto-training */ 311 /* Configure DP_TP_CTL with auto-training */
317 I915_WRITE(DP_TP_CTL(PORT_E), 312 I915_WRITE(DP_TP_CTL(PORT_E),
318 DP_TP_CTL_FDI_AUTOTRAIN | 313 DP_TP_CTL_FDI_AUTOTRAIN |
@@ -327,7 +322,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
327 I915_WRITE(DDI_BUF_CTL(PORT_E), 322 I915_WRITE(DDI_BUF_CTL(PORT_E),
328 DDI_BUF_CTL_ENABLE | 323 DDI_BUF_CTL_ENABLE |
329 ((intel_crtc->config.fdi_lanes - 1) << 1) | 324 ((intel_crtc->config.fdi_lanes - 1) << 1) |
330 hsw_ddi_buf_ctl_values[i / 2]); 325 DDI_BUF_TRANS_SELECT(i / 2));
331 POSTING_READ(DDI_BUF_CTL(PORT_E)); 326 POSTING_READ(DDI_BUF_CTL(PORT_E));
332 327
333 udelay(600); 328 udelay(600);
@@ -402,7 +397,7 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
402 enc_to_dig_port(&encoder->base); 397 enc_to_dig_port(&encoder->base);
403 398
404 intel_dp->DP = intel_dig_port->saved_port_bits | 399 intel_dp->DP = intel_dig_port->saved_port_bits |
405 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; 400 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
406 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 401 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
407 402
408} 403}
@@ -429,7 +424,7 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
429} 424}
430 425
431#define LC_FREQ 2700 426#define LC_FREQ 2700
432#define LC_FREQ_2K (LC_FREQ * 2000) 427#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
433 428
434#define P_MIN 2 429#define P_MIN 2
435#define P_MAX 64 430#define P_MAX 64
@@ -441,7 +436,11 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
441#define VCO_MIN 2400 436#define VCO_MIN 2400
442#define VCO_MAX 4800 437#define VCO_MAX 4800
443 438
444#define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) 439#define abs_diff(a, b) ({ \
440 typeof(a) __a = (a); \
441 typeof(b) __b = (b); \
442 (void) (&__a == &__b); \
443 __a > __b ? (__a - __b) : (__b - __a); })
445 444
446struct wrpll_rnp { 445struct wrpll_rnp {
447 unsigned p, n2, r2; 446 unsigned p, n2, r2;
@@ -551,9 +550,9 @@ static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
551 */ 550 */
552 a = freq2k * budget * p * r2; 551 a = freq2k * budget * p * r2;
553 b = freq2k * budget * best->p * best->r2; 552 b = freq2k * budget * best->p * best->r2;
554 diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); 553 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
555 diff_best = ABS_DIFF((freq2k * best->p * best->r2), 554 diff_best = abs_diff(freq2k * best->p * best->r2,
556 (LC_FREQ_2K * best->n2)); 555 LC_FREQ_2K * best->n2);
557 c = 1000000 * diff; 556 c = 1000000 * diff;
558 d = 1000000 * diff_best; 557 d = 1000000 * diff_best;
559 558
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 32ede71fbe7f..1386086ec245 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -900,7 +900,8 @@ static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
900 frame = I915_READ(frame_reg); 900 frame = I915_READ(frame_reg);
901 901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) 902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait timed out\n"); 903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
904} 905}
905 906
906/** 907/**
@@ -941,7 +942,8 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
941 if (wait_for(I915_READ(pipestat_reg) & 942 if (wait_for(I915_READ(pipestat_reg) &
942 PIPE_VBLANK_INTERRUPT_STATUS, 943 PIPE_VBLANK_INTERRUPT_STATUS,
943 50)) 944 50))
944 DRM_DEBUG_KMS("vblank wait timed out\n"); 945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
945} 947}
946 948
947static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) 949static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
@@ -965,8 +967,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
965 967
966/* 968/*
967 * intel_wait_for_pipe_off - wait for pipe to turn off 969 * intel_wait_for_pipe_off - wait for pipe to turn off
968 * @dev: drm device 970 * @crtc: crtc whose pipe to wait for
969 * @pipe: pipe to wait for
970 * 971 *
971 * After disabling a pipe, we can't wait for vblank in the usual way, 972 * After disabling a pipe, we can't wait for vblank in the usual way,
972 * spinning on the vblank interrupt status bit, since we won't actually 973 * spinning on the vblank interrupt status bit, since we won't actually
@@ -980,11 +981,12 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
980 * ends up stopping at the start of the next frame). 981 * ends up stopping at the start of the next frame).
981 * 982 *
982 */ 983 */
983void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) 984static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
984{ 985{
986 struct drm_device *dev = crtc->base.dev;
985 struct drm_i915_private *dev_priv = dev->dev_private; 987 struct drm_i915_private *dev_priv = dev->dev_private;
986 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 988 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
987 pipe); 989 enum pipe pipe = crtc->pipe;
988 990
989 if (INTEL_INFO(dev)->gen >= 4) { 991 if (INTEL_INFO(dev)->gen >= 4) {
990 int reg = PIPECONF(cpu_transcoder); 992 int reg = PIPECONF(cpu_transcoder);
@@ -1193,27 +1195,40 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1193static void assert_panel_unlocked(struct drm_i915_private *dev_priv, 1195static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1194 enum pipe pipe) 1196 enum pipe pipe)
1195{ 1197{
1196 int pp_reg, lvds_reg; 1198 struct drm_device *dev = dev_priv->dev;
1199 int pp_reg;
1197 u32 val; 1200 u32 val;
1198 enum pipe panel_pipe = PIPE_A; 1201 enum pipe panel_pipe = PIPE_A;
1199 bool locked = true; 1202 bool locked = true;
1200 1203
1201 if (HAS_PCH_SPLIT(dev_priv->dev)) { 1204 if (WARN_ON(HAS_DDI(dev)))
1205 return;
1206
1207 if (HAS_PCH_SPLIT(dev)) {
1208 u32 port_sel;
1209
1202 pp_reg = PCH_PP_CONTROL; 1210 pp_reg = PCH_PP_CONTROL;
1203 lvds_reg = PCH_LVDS; 1211 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220 panel_pipe = pipe;
1204 } else { 1221 } else {
1205 pp_reg = PP_CONTROL; 1222 pp_reg = PP_CONTROL;
1206 lvds_reg = LVDS; 1223 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
1207 } 1225 }
1208 1226
1209 val = I915_READ(pp_reg); 1227 val = I915_READ(pp_reg);
1210 if (!(val & PANEL_POWER_ON) || 1228 if (!(val & PANEL_POWER_ON) ||
1211 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) 1229 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1212 locked = false; 1230 locked = false;
1213 1231
1214 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216
1217 WARN(panel_pipe == pipe && locked, 1232 WARN(panel_pipe == pipe && locked,
1218 "panel assertion failure, pipe %c regs locked\n", 1233 "panel assertion failure, pipe %c regs locked\n",
1219 pipe_name(pipe)); 1234 pipe_name(pipe));
@@ -1246,8 +1261,9 @@ void assert_pipe(struct drm_i915_private *dev_priv,
1246 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1261 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1247 pipe); 1262 pipe);
1248 1263
1249 /* if we need the pipe A quirk it must be always on */ 1264 /* if we need the pipe quirk it must be always on */
1250 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 1265 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1266 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1251 state = true; 1267 state = true;
1252 1268
1253 if (!intel_display_power_enabled(dev_priv, 1269 if (!intel_display_power_enabled(dev_priv,
@@ -1301,7 +1317,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1301 } 1317 }
1302 1318
1303 /* Need to check both planes against the pipe */ 1319 /* Need to check both planes against the pipe */
1304 for_each_pipe(i) { 1320 for_each_pipe(dev_priv, i) {
1305 reg = DSPCNTR(i); 1321 reg = DSPCNTR(i);
1306 val = I915_READ(reg); 1322 val = I915_READ(reg);
1307 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1323 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
@@ -1533,7 +1549,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc)
1533 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); 1549 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1534 1550
1535 /* PLL is protected by panel, make sure we can write it */ 1551 /* PLL is protected by panel, make sure we can write it */
1536 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) 1552 if (IS_MOBILE(dev_priv->dev))
1537 assert_panel_unlocked(dev_priv, crtc->pipe); 1553 assert_panel_unlocked(dev_priv, crtc->pipe);
1538 1554
1539 I915_WRITE(reg, dpll); 1555 I915_WRITE(reg, dpll);
@@ -1653,8 +1669,9 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
1653 */ 1669 */
1654static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1670static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1655{ 1671{
1656 /* Don't disable pipe A or pipe A PLLs if needed */ 1672 /* Don't disable pipe or pipe PLLs if needed */
1657 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1673 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1674 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1658 return; 1675 return;
1659 1676
1660 /* Make sure the pipe isn't still relying on us */ 1677 /* Make sure the pipe isn't still relying on us */
@@ -1847,7 +1864,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1847 uint32_t reg, val, pipeconf_val; 1864 uint32_t reg, val, pipeconf_val;
1848 1865
1849 /* PCH only available on ILK+ */ 1866 /* PCH only available on ILK+ */
1850 BUG_ON(INTEL_INFO(dev)->gen < 5); 1867 BUG_ON(!HAS_PCH_SPLIT(dev));
1851 1868
1852 /* Make sure PCH DPLL is enabled */ 1869 /* Make sure PCH DPLL is enabled */
1853 assert_shared_dpll_enabled(dev_priv, 1870 assert_shared_dpll_enabled(dev_priv,
@@ -1900,7 +1917,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1900 u32 val, pipeconf_val; 1917 u32 val, pipeconf_val;
1901 1918
1902 /* PCH only available on ILK+ */ 1919 /* PCH only available on ILK+ */
1903 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); 1920 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1904 1921
1905 /* FDI must be feeding us bits for PCH ports */ 1922 /* FDI must be feeding us bits for PCH ports */
1906 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); 1923 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
@@ -2022,8 +2039,8 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
2022 reg = PIPECONF(cpu_transcoder); 2039 reg = PIPECONF(cpu_transcoder);
2023 val = I915_READ(reg); 2040 val = I915_READ(reg);
2024 if (val & PIPECONF_ENABLE) { 2041 if (val & PIPECONF_ENABLE) {
2025 WARN_ON(!(pipe == PIPE_A && 2042 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2026 dev_priv->quirks & QUIRK_PIPEA_FORCE)); 2043 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2027 return; 2044 return;
2028 } 2045 }
2029 2046
@@ -2033,21 +2050,19 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
2033 2050
2034/** 2051/**
2035 * intel_disable_pipe - disable a pipe, asserting requirements 2052 * intel_disable_pipe - disable a pipe, asserting requirements
2036 * @dev_priv: i915 private structure 2053 * @crtc: crtc whose pipes is to be disabled
2037 * @pipe: pipe to disable
2038 *
2039 * Disable @pipe, making sure that various hardware specific requirements
2040 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2041 * 2054 *
2042 * @pipe should be %PIPE_A or %PIPE_B. 2055 * Disable the pipe of @crtc, making sure that various hardware
2056 * specific requirements are met, if applicable, e.g. plane
2057 * disabled, panel fitter off, etc.
2043 * 2058 *
2044 * Will wait until the pipe has shut down before returning. 2059 * Will wait until the pipe has shut down before returning.
2045 */ 2060 */
2046static void intel_disable_pipe(struct drm_i915_private *dev_priv, 2061static void intel_disable_pipe(struct intel_crtc *crtc)
2047 enum pipe pipe)
2048{ 2062{
2049 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 2063 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2050 pipe); 2064 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2065 enum pipe pipe = crtc->pipe;
2051 int reg; 2066 int reg;
2052 u32 val; 2067 u32 val;
2053 2068
@@ -2059,17 +2074,26 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2059 assert_cursor_disabled(dev_priv, pipe); 2074 assert_cursor_disabled(dev_priv, pipe);
2060 assert_sprites_disabled(dev_priv, pipe); 2075 assert_sprites_disabled(dev_priv, pipe);
2061 2076
2062 /* Don't disable pipe A or pipe A PLLs if needed */
2063 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2064 return;
2065
2066 reg = PIPECONF(cpu_transcoder); 2077 reg = PIPECONF(cpu_transcoder);
2067 val = I915_READ(reg); 2078 val = I915_READ(reg);
2068 if ((val & PIPECONF_ENABLE) == 0) 2079 if ((val & PIPECONF_ENABLE) == 0)
2069 return; 2080 return;
2070 2081
2071 I915_WRITE(reg, val & ~PIPECONF_ENABLE); 2082 /*
2072 intel_wait_for_pipe_off(dev_priv->dev, pipe); 2083 * Double wide has implications for planes
2084 * so best keep it disabled when not needed.
2085 */
2086 if (crtc->config.double_wide)
2087 val &= ~PIPECONF_DOUBLE_WIDE;
2088
2089 /* Don't disable pipe or pipe PLLs if needed */
2090 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2091 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2092 val &= ~PIPECONF_ENABLE;
2093
2094 I915_WRITE(reg, val);
2095 if ((val & PIPECONF_ENABLE) == 0)
2096 intel_wait_for_pipe_off(crtc);
2073} 2097}
2074 2098
2075/* 2099/*
@@ -2390,11 +2414,12 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2390 struct drm_device *dev = crtc->dev; 2414 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private; 2415 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2417 struct drm_i915_gem_object *obj;
2394 int plane = intel_crtc->plane; 2418 int plane = intel_crtc->plane;
2395 unsigned long linear_offset; 2419 unsigned long linear_offset;
2396 u32 dspcntr; 2420 u32 dspcntr;
2397 u32 reg = DSPCNTR(plane); 2421 u32 reg = DSPCNTR(plane);
2422 int pixel_size;
2398 2423
2399 if (!intel_crtc->primary_enabled) { 2424 if (!intel_crtc->primary_enabled) {
2400 I915_WRITE(reg, 0); 2425 I915_WRITE(reg, 0);
@@ -2406,6 +2431,12 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2406 return; 2431 return;
2407 } 2432 }
2408 2433
2434 obj = intel_fb_obj(fb);
2435 if (WARN_ON(obj == NULL))
2436 return;
2437
2438 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2439
2409 dspcntr = DISPPLANE_GAMMA_ENABLE; 2440 dspcntr = DISPPLANE_GAMMA_ENABLE;
2410 2441
2411 dspcntr |= DISPLAY_PLANE_ENABLE; 2442 dspcntr |= DISPLAY_PLANE_ENABLE;
@@ -2461,20 +2492,33 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2461 if (IS_G4X(dev)) 2492 if (IS_G4X(dev))
2462 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 2493 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2463 2494
2464 I915_WRITE(reg, dspcntr); 2495 linear_offset = y * fb->pitches[0] + x * pixel_size;
2465
2466 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2467 2496
2468 if (INTEL_INFO(dev)->gen >= 4) { 2497 if (INTEL_INFO(dev)->gen >= 4) {
2469 intel_crtc->dspaddr_offset = 2498 intel_crtc->dspaddr_offset =
2470 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, 2499 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2471 fb->bits_per_pixel / 8, 2500 pixel_size,
2472 fb->pitches[0]); 2501 fb->pitches[0]);
2473 linear_offset -= intel_crtc->dspaddr_offset; 2502 linear_offset -= intel_crtc->dspaddr_offset;
2474 } else { 2503 } else {
2475 intel_crtc->dspaddr_offset = linear_offset; 2504 intel_crtc->dspaddr_offset = linear_offset;
2476 } 2505 }
2477 2506
2507 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2508 dspcntr |= DISPPLANE_ROTATE_180;
2509
2510 x += (intel_crtc->config.pipe_src_w - 1);
2511 y += (intel_crtc->config.pipe_src_h - 1);
2512
2513 /* Finding the last pixel of the last line of the display
2514 data and adding to linear_offset*/
2515 linear_offset +=
2516 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2517 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2518 }
2519
2520 I915_WRITE(reg, dspcntr);
2521
2478 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 2522 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2479 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, 2523 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2480 fb->pitches[0]); 2524 fb->pitches[0]);
@@ -2496,11 +2540,12 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2496 struct drm_device *dev = crtc->dev; 2540 struct drm_device *dev = crtc->dev;
2497 struct drm_i915_private *dev_priv = dev->dev_private; 2541 struct drm_i915_private *dev_priv = dev->dev_private;
2498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2499 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 2543 struct drm_i915_gem_object *obj;
2500 int plane = intel_crtc->plane; 2544 int plane = intel_crtc->plane;
2501 unsigned long linear_offset; 2545 unsigned long linear_offset;
2502 u32 dspcntr; 2546 u32 dspcntr;
2503 u32 reg = DSPCNTR(plane); 2547 u32 reg = DSPCNTR(plane);
2548 int pixel_size;
2504 2549
2505 if (!intel_crtc->primary_enabled) { 2550 if (!intel_crtc->primary_enabled) {
2506 I915_WRITE(reg, 0); 2551 I915_WRITE(reg, 0);
@@ -2509,6 +2554,12 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2509 return; 2554 return;
2510 } 2555 }
2511 2556
2557 obj = intel_fb_obj(fb);
2558 if (WARN_ON(obj == NULL))
2559 return;
2560
2561 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2562
2512 dspcntr = DISPPLANE_GAMMA_ENABLE; 2563 dspcntr = DISPPLANE_GAMMA_ENABLE;
2513 2564
2514 dspcntr |= DISPLAY_PLANE_ENABLE; 2565 dspcntr |= DISPLAY_PLANE_ENABLE;
@@ -2549,14 +2600,28 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2549 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) 2600 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2550 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 2601 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2551 2602
2552 I915_WRITE(reg, dspcntr); 2603 linear_offset = y * fb->pitches[0] + x * pixel_size;
2553
2554 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2555 intel_crtc->dspaddr_offset = 2604 intel_crtc->dspaddr_offset =
2556 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, 2605 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2557 fb->bits_per_pixel / 8, 2606 pixel_size,
2558 fb->pitches[0]); 2607 fb->pitches[0]);
2559 linear_offset -= intel_crtc->dspaddr_offset; 2608 linear_offset -= intel_crtc->dspaddr_offset;
2609 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2610 dspcntr |= DISPPLANE_ROTATE_180;
2611
2612 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2613 x += (intel_crtc->config.pipe_src_w - 1);
2614 y += (intel_crtc->config.pipe_src_h - 1);
2615
2616 /* Finding the last pixel of the last line of the display
2617 data and adding to linear_offset*/
2618 linear_offset +=
2619 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2620 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2621 }
2622 }
2623
2624 I915_WRITE(reg, dspcntr);
2560 2625
2561 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", 2626 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2562 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, 2627 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
@@ -3340,23 +3405,54 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev)
3340 return false; 3405 return false;
3341} 3406}
3342 3407
3408static void page_flip_completed(struct intel_crtc *intel_crtc)
3409{
3410 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3411 struct intel_unpin_work *work = intel_crtc->unpin_work;
3412
3413 /* ensure that the unpin work is consistent wrt ->pending. */
3414 smp_rmb();
3415 intel_crtc->unpin_work = NULL;
3416
3417 if (work->event)
3418 drm_send_vblank_event(intel_crtc->base.dev,
3419 intel_crtc->pipe,
3420 work->event);
3421
3422 drm_crtc_vblank_put(&intel_crtc->base);
3423
3424 wake_up_all(&dev_priv->pending_flip_queue);
3425 queue_work(dev_priv->wq, &work->work);
3426
3427 trace_i915_flip_complete(intel_crtc->plane,
3428 work->pending_flip_obj);
3429}
3430
3343void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 3431void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3344{ 3432{
3345 struct drm_device *dev = crtc->dev; 3433 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private; 3434 struct drm_i915_private *dev_priv = dev->dev_private;
3347 3435
3348 if (crtc->primary->fb == NULL)
3349 return;
3350
3351 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); 3436 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3437 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3438 !intel_crtc_has_pending_flip(crtc),
3439 60*HZ) == 0)) {
3440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3441 unsigned long flags;
3352 3442
3353 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, 3443 spin_lock_irqsave(&dev->event_lock, flags);
3354 !intel_crtc_has_pending_flip(crtc), 3444 if (intel_crtc->unpin_work) {
3355 60*HZ) == 0); 3445 WARN_ONCE(1, "Removing stuck page flip\n");
3446 page_flip_completed(intel_crtc);
3447 }
3448 spin_unlock_irqrestore(&dev->event_lock, flags);
3449 }
3356 3450
3357 mutex_lock(&dev->struct_mutex); 3451 if (crtc->primary->fb) {
3358 intel_finish_fb(crtc->primary->fb); 3452 mutex_lock(&dev->struct_mutex);
3359 mutex_unlock(&dev->struct_mutex); 3453 intel_finish_fb(crtc->primary->fb);
3454 mutex_unlock(&dev->struct_mutex);
3455 }
3360} 3456}
3361 3457
3362/* Program iCLKIP clock to the desired frequency */ 3458/* Program iCLKIP clock to the desired frequency */
@@ -4178,7 +4274,8 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
4178 if (intel_crtc->config.has_pch_encoder) 4274 if (intel_crtc->config.has_pch_encoder)
4179 intel_set_pch_fifo_underrun_reporting(dev, pipe, false); 4275 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4180 4276
4181 intel_disable_pipe(dev_priv, pipe); 4277 intel_disable_pipe(intel_crtc);
4278
4182 ironlake_pfit_disable(intel_crtc); 4279 ironlake_pfit_disable(intel_crtc);
4183 4280
4184 for_each_encoder_on_crtc(dev, crtc, encoder) 4281 for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -4226,7 +4323,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
4226 struct drm_i915_private *dev_priv = dev->dev_private; 4323 struct drm_i915_private *dev_priv = dev->dev_private;
4227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4228 struct intel_encoder *encoder; 4325 struct intel_encoder *encoder;
4229 int pipe = intel_crtc->pipe;
4230 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 4326 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4231 4327
4232 if (!intel_crtc->active) 4328 if (!intel_crtc->active)
@@ -4241,7 +4337,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
4241 4337
4242 if (intel_crtc->config.has_pch_encoder) 4338 if (intel_crtc->config.has_pch_encoder)
4243 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); 4339 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4244 intel_disable_pipe(dev_priv, pipe); 4340 intel_disable_pipe(intel_crtc);
4245 4341
4246 if (intel_crtc->config.dp_encoder_is_mst) 4342 if (intel_crtc->config.dp_encoder_is_mst)
4247 intel_ddi_set_vc_payload_alloc(crtc, false); 4343 intel_ddi_set_vc_payload_alloc(crtc, false);
@@ -4831,7 +4927,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
4831 */ 4927 */
4832 intel_wait_for_vblank(dev, pipe); 4928 intel_wait_for_vblank(dev, pipe);
4833 4929
4834 intel_disable_pipe(dev_priv, pipe); 4930 intel_disable_pipe(intel_crtc);
4835 4931
4836 i9xx_pfit_disable(intel_crtc); 4932 i9xx_pfit_disable(intel_crtc);
4837 4933
@@ -6000,9 +6096,9 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6000 6096
6001 pipeconf = 0; 6097 pipeconf = 0;
6002 6098
6003 if (dev_priv->quirks & QUIRK_PIPEA_FORCE && 6099 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6004 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) 6100 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6005 pipeconf |= PIPECONF_ENABLE; 6101 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6006 6102
6007 if (intel_crtc->config.double_wide) 6103 if (intel_crtc->config.double_wide)
6008 pipeconf |= PIPECONF_DOUBLE_WIDE; 6104 pipeconf |= PIPECONF_DOUBLE_WIDE;
@@ -8274,7 +8370,6 @@ static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8274 if (!obj) { 8370 if (!obj) {
8275 DRM_DEBUG_KMS("cursor off\n"); 8371 DRM_DEBUG_KMS("cursor off\n");
8276 addr = 0; 8372 addr = 0;
8277 obj = NULL;
8278 mutex_lock(&dev->struct_mutex); 8373 mutex_lock(&dev->struct_mutex);
8279 goto finish; 8374 goto finish;
8280 } 8375 }
@@ -8994,12 +9089,13 @@ static void intel_mark_fb_busy(struct drm_device *dev,
8994 unsigned frontbuffer_bits, 9089 unsigned frontbuffer_bits,
8995 struct intel_engine_cs *ring) 9090 struct intel_engine_cs *ring)
8996{ 9091{
9092 struct drm_i915_private *dev_priv = dev->dev_private;
8997 enum pipe pipe; 9093 enum pipe pipe;
8998 9094
8999 if (!i915.powersave) 9095 if (!i915.powersave)
9000 return; 9096 return;
9001 9097
9002 for_each_pipe(pipe) { 9098 for_each_pipe(dev_priv, pipe) {
9003 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) 9099 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9004 continue; 9100 continue;
9005 9101
@@ -9069,6 +9165,14 @@ void intel_frontbuffer_flush(struct drm_device *dev,
9069 intel_mark_fb_busy(dev, frontbuffer_bits, NULL); 9165 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9070 9166
9071 intel_edp_psr_flush(dev, frontbuffer_bits); 9167 intel_edp_psr_flush(dev, frontbuffer_bits);
9168
9169 /*
9170 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9171 * needs to be reworked into a proper frontbuffer tracking scheme like
9172 * psr employs.
9173 */
9174 if (IS_BROADWELL(dev))
9175 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9072} 9176}
9073 9177
9074/** 9178/**
@@ -9201,7 +9305,6 @@ static void intel_unpin_work_fn(struct work_struct *__work)
9201static void do_intel_finish_page_flip(struct drm_device *dev, 9305static void do_intel_finish_page_flip(struct drm_device *dev,
9202 struct drm_crtc *crtc) 9306 struct drm_crtc *crtc)
9203{ 9307{
9204 struct drm_i915_private *dev_priv = dev->dev_private;
9205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9206 struct intel_unpin_work *work; 9309 struct intel_unpin_work *work;
9207 unsigned long flags; 9310 unsigned long flags;
@@ -9221,23 +9324,9 @@ static void do_intel_finish_page_flip(struct drm_device *dev,
9221 return; 9324 return;
9222 } 9325 }
9223 9326
9224 /* and that the unpin work is consistent wrt ->pending. */ 9327 page_flip_completed(intel_crtc);
9225 smp_rmb();
9226
9227 intel_crtc->unpin_work = NULL;
9228
9229 if (work->event)
9230 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9231
9232 drm_crtc_vblank_put(crtc);
9233 9328
9234 spin_unlock_irqrestore(&dev->event_lock, flags); 9329 spin_unlock_irqrestore(&dev->event_lock, flags);
9235
9236 wake_up_all(&dev_priv->pending_flip_queue);
9237
9238 queue_work(dev_priv->wq, &work->work);
9239
9240 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9241} 9330}
9242 9331
9243void intel_finish_page_flip(struct drm_device *dev, int pipe) 9332void intel_finish_page_flip(struct drm_device *dev, int pipe)
@@ -9717,6 +9806,65 @@ static int intel_default_queue_flip(struct drm_device *dev,
9717 return -ENODEV; 9806 return -ENODEV;
9718} 9807}
9719 9808
9809static bool __intel_pageflip_stall_check(struct drm_device *dev,
9810 struct drm_crtc *crtc)
9811{
9812 struct drm_i915_private *dev_priv = dev->dev_private;
9813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9814 struct intel_unpin_work *work = intel_crtc->unpin_work;
9815 u32 addr;
9816
9817 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9818 return true;
9819
9820 if (!work->enable_stall_check)
9821 return false;
9822
9823 if (work->flip_ready_vblank == 0) {
9824 if (work->flip_queued_ring &&
9825 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9826 work->flip_queued_seqno))
9827 return false;
9828
9829 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9830 }
9831
9832 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9833 return false;
9834
9835 /* Potential stall - if we see that the flip has happened,
9836 * assume a missed interrupt. */
9837 if (INTEL_INFO(dev)->gen >= 4)
9838 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9839 else
9840 addr = I915_READ(DSPADDR(intel_crtc->plane));
9841
9842 /* There is a potential issue here with a false positive after a flip
9843 * to the same address. We could address this by checking for a
9844 * non-incrementing frame counter.
9845 */
9846 return addr == work->gtt_offset;
9847}
9848
9849void intel_check_page_flip(struct drm_device *dev, int pipe)
9850{
9851 struct drm_i915_private *dev_priv = dev->dev_private;
9852 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9854 unsigned long flags;
9855
9856 if (crtc == NULL)
9857 return;
9858
9859 spin_lock_irqsave(&dev->event_lock, flags);
9860 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9861 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9862 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9863 page_flip_completed(intel_crtc);
9864 }
9865 spin_unlock_irqrestore(&dev->event_lock, flags);
9866}
9867
9720static int intel_crtc_page_flip(struct drm_crtc *crtc, 9868static int intel_crtc_page_flip(struct drm_crtc *crtc,
9721 struct drm_framebuffer *fb, 9869 struct drm_framebuffer *fb,
9722 struct drm_pending_vblank_event *event, 9870 struct drm_pending_vblank_event *event,
@@ -9733,6 +9881,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
9733 unsigned long flags; 9881 unsigned long flags;
9734 int ret; 9882 int ret;
9735 9883
9884 //trigger software GT busyness calculation
9885 gen8_flip_interrupt(dev);
9886
9736 /* 9887 /*
9737 * drm_mode_page_flip_ioctl() should already catch this, but double 9888 * drm_mode_page_flip_ioctl() should already catch this, but double
9738 * check to be safe. In the future we may enable pageflipping from 9889 * check to be safe. In the future we may enable pageflipping from
@@ -9773,12 +9924,20 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
9773 /* We borrow the event spin lock for protecting unpin_work */ 9924 /* We borrow the event spin lock for protecting unpin_work */
9774 spin_lock_irqsave(&dev->event_lock, flags); 9925 spin_lock_irqsave(&dev->event_lock, flags);
9775 if (intel_crtc->unpin_work) { 9926 if (intel_crtc->unpin_work) {
9776 spin_unlock_irqrestore(&dev->event_lock, flags); 9927 /* Before declaring the flip queue wedged, check if
9777 kfree(work); 9928 * the hardware completed the operation behind our backs.
9778 drm_crtc_vblank_put(crtc); 9929 */
9930 if (__intel_pageflip_stall_check(dev, crtc)) {
9931 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9932 page_flip_completed(intel_crtc);
9933 } else {
9934 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9935 spin_unlock_irqrestore(&dev->event_lock, flags);
9779 9936
9780 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 9937 drm_crtc_vblank_put(crtc);
9781 return -EBUSY; 9938 kfree(work);
9939 return -EBUSY;
9940 }
9782 } 9941 }
9783 intel_crtc->unpin_work = work; 9942 intel_crtc->unpin_work = work;
9784 spin_unlock_irqrestore(&dev->event_lock, flags); 9943 spin_unlock_irqrestore(&dev->event_lock, flags);
@@ -9798,8 +9957,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
9798 9957
9799 work->pending_flip_obj = obj; 9958 work->pending_flip_obj = obj;
9800 9959
9801 work->enable_stall_check = true;
9802
9803 atomic_inc(&intel_crtc->unpin_work_count); 9960 atomic_inc(&intel_crtc->unpin_work_count);
9804 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); 9961 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9805 9962
@@ -9828,14 +9985,26 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
9828 work->gtt_offset = 9985 work->gtt_offset =
9829 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; 9986 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9830 9987
9831 if (use_mmio_flip(ring, obj)) 9988 if (use_mmio_flip(ring, obj)) {
9832 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, 9989 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9833 page_flip_flags); 9990 page_flip_flags);
9834 else 9991 if (ret)
9992 goto cleanup_unpin;
9993
9994 work->flip_queued_seqno = obj->last_write_seqno;
9995 work->flip_queued_ring = obj->ring;
9996 } else {
9835 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, 9997 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9836 page_flip_flags); 9998 page_flip_flags);
9837 if (ret) 9999 if (ret)
9838 goto cleanup_unpin; 10000 goto cleanup_unpin;
10001
10002 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10003 work->flip_queued_ring = ring;
10004 }
10005
10006 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10007 work->enable_stall_check = true;
9839 10008
9840 i915_gem_track_fb(work->old_fb_obj, obj, 10009 i915_gem_track_fb(work->old_fb_obj, obj,
9841 INTEL_FRONTBUFFER_PRIMARY(pipe)); 10010 INTEL_FRONTBUFFER_PRIMARY(pipe));
@@ -10723,8 +10892,9 @@ check_crtc_state(struct drm_device *dev)
10723 active = dev_priv->display.get_pipe_config(crtc, 10892 active = dev_priv->display.get_pipe_config(crtc,
10724 &pipe_config); 10893 &pipe_config);
10725 10894
10726 /* hw state is inconsistent with the pipe A quirk */ 10895 /* hw state is inconsistent with the pipe quirk */
10727 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 10896 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10897 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10728 active = crtc->active; 10898 active = crtc->active;
10729 10899
10730 for_each_intel_encoder(dev, encoder) { 10900 for_each_intel_encoder(dev, encoder) {
@@ -11596,6 +11766,7 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11596 uint32_t src_w, uint32_t src_h) 11766 uint32_t src_w, uint32_t src_h)
11597{ 11767{
11598 struct drm_device *dev = crtc->dev; 11768 struct drm_device *dev = crtc->dev;
11769 struct drm_i915_private *dev_priv = dev->dev_private;
11599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 11770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11600 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 11771 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11601 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); 11772 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
@@ -11618,6 +11789,21 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11618 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, 11789 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11619 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, 11790 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11620 }; 11791 };
11792 const struct {
11793 int crtc_x, crtc_y;
11794 unsigned int crtc_w, crtc_h;
11795 uint32_t src_x, src_y, src_w, src_h;
11796 } orig = {
11797 .crtc_x = crtc_x,
11798 .crtc_y = crtc_y,
11799 .crtc_w = crtc_w,
11800 .crtc_h = crtc_h,
11801 .src_x = src_x,
11802 .src_y = src_y,
11803 .src_w = src_w,
11804 .src_h = src_h,
11805 };
11806 struct intel_plane *intel_plane = to_intel_plane(plane);
11621 bool visible; 11807 bool visible;
11622 int ret; 11808 int ret;
11623 11809
@@ -11692,15 +11878,42 @@ intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11692 11878
11693 mutex_unlock(&dev->struct_mutex); 11879 mutex_unlock(&dev->struct_mutex);
11694 11880
11695 return 0; 11881 } else {
11696 } 11882 if (intel_crtc && intel_crtc->active &&
11883 intel_crtc->primary_enabled) {
11884 /*
11885 * FBC does not work on some platforms for rotated
11886 * planes, so disable it when rotation is not 0 and
11887 * update it when rotation is set back to 0.
11888 *
11889 * FIXME: This is redundant with the fbc update done in
11890 * the primary plane enable function except that that
11891 * one is done too late. We eventually need to unify
11892 * this.
11893 */
11894 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11895 dev_priv->fbc.plane == intel_crtc->plane &&
11896 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11897 intel_disable_fbc(dev);
11898 }
11899 }
11900 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11901 if (ret)
11902 return ret;
11697 11903
11698 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); 11904 if (!intel_crtc->primary_enabled)
11699 if (ret) 11905 intel_enable_primary_hw_plane(plane, crtc);
11700 return ret; 11906 }
11701 11907
11702 if (!intel_crtc->primary_enabled) 11908 intel_plane->crtc_x = orig.crtc_x;
11703 intel_enable_primary_hw_plane(plane, crtc); 11909 intel_plane->crtc_y = orig.crtc_y;
11910 intel_plane->crtc_w = orig.crtc_w;
11911 intel_plane->crtc_h = orig.crtc_h;
11912 intel_plane->src_x = orig.src_x;
11913 intel_plane->src_y = orig.src_y;
11914 intel_plane->src_w = orig.src_w;
11915 intel_plane->src_h = orig.src_h;
11916 intel_plane->obj = obj;
11704 11917
11705 return 0; 11918 return 0;
11706} 11919}
@@ -11717,6 +11930,7 @@ static const struct drm_plane_funcs intel_primary_plane_funcs = {
11717 .update_plane = intel_primary_plane_setplane, 11930 .update_plane = intel_primary_plane_setplane,
11718 .disable_plane = intel_primary_plane_disable, 11931 .disable_plane = intel_primary_plane_disable,
11719 .destroy = intel_plane_destroy, 11932 .destroy = intel_plane_destroy,
11933 .set_property = intel_plane_set_property
11720}; 11934};
11721 11935
11722static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, 11936static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
@@ -11734,6 +11948,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11734 primary->max_downscale = 1; 11948 primary->max_downscale = 1;
11735 primary->pipe = pipe; 11949 primary->pipe = pipe;
11736 primary->plane = pipe; 11950 primary->plane = pipe;
11951 primary->rotation = BIT(DRM_ROTATE_0);
11737 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) 11952 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11738 primary->plane = !pipe; 11953 primary->plane = !pipe;
11739 11954
@@ -11749,6 +11964,19 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11749 &intel_primary_plane_funcs, 11964 &intel_primary_plane_funcs,
11750 intel_primary_formats, num_formats, 11965 intel_primary_formats, num_formats,
11751 DRM_PLANE_TYPE_PRIMARY); 11966 DRM_PLANE_TYPE_PRIMARY);
11967
11968 if (INTEL_INFO(dev)->gen >= 4) {
11969 if (!dev->mode_config.rotation_property)
11970 dev->mode_config.rotation_property =
11971 drm_mode_create_rotation_property(dev,
11972 BIT(DRM_ROTATE_0) |
11973 BIT(DRM_ROTATE_180));
11974 if (dev->mode_config.rotation_property)
11975 drm_object_attach_property(&primary->base.base,
11976 dev->mode_config.rotation_property,
11977 primary->rotation);
11978 }
11979
11752 return &primary->base; 11980 return &primary->base;
11753} 11981}
11754 11982
@@ -12423,7 +12651,7 @@ static void intel_init_display(struct drm_device *dev)
12423 dev_priv->display.write_eld = ironlake_write_eld; 12651 dev_priv->display.write_eld = ironlake_write_eld;
12424 dev_priv->display.modeset_global_resources = 12652 dev_priv->display.modeset_global_resources =
12425 ivb_modeset_global_resources; 12653 ivb_modeset_global_resources;
12426 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { 12654 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12427 dev_priv->display.fdi_link_train = hsw_fdi_link_train; 12655 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12428 dev_priv->display.write_eld = haswell_write_eld; 12656 dev_priv->display.write_eld = haswell_write_eld;
12429 dev_priv->display.modeset_global_resources = 12657 dev_priv->display.modeset_global_resources =
@@ -12461,6 +12689,8 @@ static void intel_init_display(struct drm_device *dev)
12461 } 12689 }
12462 12690
12463 intel_panel_init_backlight_funcs(dev); 12691 intel_panel_init_backlight_funcs(dev);
12692
12693 mutex_init(&dev_priv->pps_mutex);
12464} 12694}
12465 12695
12466/* 12696/*
@@ -12476,6 +12706,14 @@ static void quirk_pipea_force(struct drm_device *dev)
12476 DRM_INFO("applying pipe a force quirk\n"); 12706 DRM_INFO("applying pipe a force quirk\n");
12477} 12707}
12478 12708
12709static void quirk_pipeb_force(struct drm_device *dev)
12710{
12711 struct drm_i915_private *dev_priv = dev->dev_private;
12712
12713 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12714 DRM_INFO("applying pipe b force quirk\n");
12715}
12716
12479/* 12717/*
12480 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 12718 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12481 */ 12719 */
@@ -12550,6 +12788,12 @@ static struct intel_quirk intel_quirks[] = {
12550 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 12788 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12551 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, 12789 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12552 12790
12791 /* 830 needs to leave pipe A & dpll A up */
12792 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12793
12794 /* 830 needs to leave pipe B & dpll B up */
12795 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12796
12553 /* Lenovo U160 cannot use SSC on LVDS */ 12797 /* Lenovo U160 cannot use SSC on LVDS */
12554 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 12798 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12555 12799
@@ -12623,7 +12867,11 @@ static void i915_disable_vga(struct drm_device *dev)
12623 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 12867 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12624 udelay(300); 12868 udelay(300);
12625 12869
12626 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 12870 /*
12871 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12872 * from S3 without preserving (some of?) the other bits.
12873 */
12874 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12627 POSTING_READ(vga_reg); 12875 POSTING_READ(vga_reg);
12628} 12876}
12629 12877
@@ -12698,7 +12946,7 @@ void intel_modeset_init(struct drm_device *dev)
12698 INTEL_INFO(dev)->num_pipes, 12946 INTEL_INFO(dev)->num_pipes,
12699 INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); 12947 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12700 12948
12701 for_each_pipe(pipe) { 12949 for_each_pipe(dev_priv, pipe) {
12702 intel_crtc_init(dev, pipe); 12950 intel_crtc_init(dev, pipe);
12703 for_each_sprite(pipe, sprite) { 12951 for_each_sprite(pipe, sprite) {
12704 ret = intel_plane_init(dev, pipe, sprite); 12952 ret = intel_plane_init(dev, pipe, sprite);
@@ -12712,6 +12960,8 @@ void intel_modeset_init(struct drm_device *dev)
12712 12960
12713 intel_shared_dpll_init(dev); 12961 intel_shared_dpll_init(dev);
12714 12962
12963 /* save the BIOS value before clobbering it */
12964 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12715 /* Just disable it once at startup */ 12965 /* Just disable it once at startup */
12716 i915_disable_vga(dev); 12966 i915_disable_vga(dev);
12717 intel_setup_outputs(dev); 12967 intel_setup_outputs(dev);
@@ -12889,7 +13139,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
12889 } 13139 }
12890 } 13140 }
12891 13141
12892 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { 13142 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
12893 /* 13143 /*
12894 * We start out with underrun reporting disabled to avoid races. 13144 * We start out with underrun reporting disabled to avoid races.
12895 * For correct bookkeeping mark this on active crtcs. 13145 * For correct bookkeeping mark this on active crtcs.
@@ -13104,7 +13354,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
13104 intel_sanitize_encoder(encoder); 13354 intel_sanitize_encoder(encoder);
13105 } 13355 }
13106 13356
13107 for_each_pipe(pipe) { 13357 for_each_pipe(dev_priv, pipe) {
13108 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 13358 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13109 intel_sanitize_crtc(crtc); 13359 intel_sanitize_crtc(crtc);
13110 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); 13360 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
@@ -13132,7 +13382,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
13132 * We need to use raw interfaces for restoring state to avoid 13382 * We need to use raw interfaces for restoring state to avoid
13133 * checking (bogus) intermediate states. 13383 * checking (bogus) intermediate states.
13134 */ 13384 */
13135 for_each_pipe(pipe) { 13385 for_each_pipe(dev_priv, pipe) {
13136 struct drm_crtc *crtc = 13386 struct drm_crtc *crtc =
13137 dev_priv->pipe_to_crtc_mapping[pipe]; 13387 dev_priv->pipe_to_crtc_mapping[pipe];
13138 13388
@@ -13353,7 +13603,7 @@ intel_display_capture_error_state(struct drm_device *dev)
13353 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 13603 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13354 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); 13604 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13355 13605
13356 for_each_pipe(i) { 13606 for_each_pipe(dev_priv, i) {
13357 error->pipe[i].power_domain_on = 13607 error->pipe[i].power_domain_on =
13358 intel_display_power_enabled_unlocked(dev_priv, 13608 intel_display_power_enabled_unlocked(dev_priv,
13359 POWER_DOMAIN_PIPE(i)); 13609 POWER_DOMAIN_PIPE(i));
@@ -13417,6 +13667,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13417 struct drm_device *dev, 13667 struct drm_device *dev,
13418 struct intel_display_error_state *error) 13668 struct intel_display_error_state *error)
13419{ 13669{
13670 struct drm_i915_private *dev_priv = dev->dev_private;
13420 int i; 13671 int i;
13421 13672
13422 if (!error) 13673 if (!error)
@@ -13426,7 +13677,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13426 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 13677 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13427 err_printf(m, "PWR_WELL_CTL2: %08x\n", 13678 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13428 error->power_well_driver); 13679 error->power_well_driver);
13429 for_each_pipe(i) { 13680 for_each_pipe(dev_priv, i) {
13430 err_printf(m, "Pipe [%d]:\n", i); 13681 err_printf(m, "Pipe [%d]:\n", i);
13431 err_printf(m, " Power: %s\n", 13682 err_printf(m, " Power: %s\n",
13432 error->pipe[i].power_domain_on ? "on" : "off"); 13683 error->pipe[i].power_domain_on ? "on" : "off");
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a12a4d3363fd..2a26774ddb68 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -111,7 +111,7 @@ static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
111} 111}
112 112
113static void intel_dp_link_down(struct intel_dp *intel_dp); 113static void intel_dp_link_down(struct intel_dp *intel_dp);
114static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
116 116
117int 117int
@@ -290,32 +290,201 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp, 290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out); 291 struct edp_power_seq *out);
292 292
293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
293static enum pipe 325static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{ 327{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev; 329 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private; 330 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port; 331 struct intel_encoder *encoder;
301 enum pipe pipe; 332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
334
335 lockdep_assert_held(&dev_priv->pps_mutex);
336
337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
302 369
303 /* modeset should have pipe */ 370 /* init power sequencer on this pipe and port */
304 if (crtc) 371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
305 return to_intel_crtc(crtc)->pipe; 372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
398
399static enum pipe
400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
403{
404 enum pipe pipe;
306 405
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK; 408 PANEL_PORT_SELECT_MASK;
311 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 409
312 return pipe; 410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
313 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 411 continue;
314 return pipe; 412
413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
416 return pipe;
417 }
418
419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
315 } 451 }
316 452
317 /* shrug */ 453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
318 return PIPE_A; 454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
459}
460
461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
319} 488}
320 489
321static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
@@ -349,12 +518,15 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
349 struct drm_i915_private *dev_priv = dev->dev_private; 518 struct drm_i915_private *dev_priv = dev->dev_private;
350 u32 pp_div; 519 u32 pp_div;
351 u32 pp_ctrl_reg, pp_div_reg; 520 u32 pp_ctrl_reg, pp_div_reg;
352 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
353 521
354 if (!is_edp(intel_dp) || code != SYS_RESTART) 522 if (!is_edp(intel_dp) || code != SYS_RESTART)
355 return 0; 523 return 0;
356 524
525 pps_lock(intel_dp);
526
357 if (IS_VALLEYVIEW(dev)) { 527 if (IS_VALLEYVIEW(dev)) {
528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
358 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
359 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
360 pp_div = I915_READ(pp_div_reg); 532 pp_div = I915_READ(pp_div_reg);
@@ -366,6 +538,8 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
366 msleep(intel_dp->panel_power_cycle_delay); 538 msleep(intel_dp->panel_power_cycle_delay);
367 } 539 }
368 540
541 pps_unlock(intel_dp);
542
369 return 0; 543 return 0;
370} 544}
371 545
@@ -374,6 +548,8 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
374 struct drm_device *dev = intel_dp_to_dev(intel_dp); 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
375 struct drm_i915_private *dev_priv = dev->dev_private; 549 struct drm_i915_private *dev_priv = dev->dev_private;
376 550
551 lockdep_assert_held(&dev_priv->pps_mutex);
552
377 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
378} 554}
379 555
@@ -381,13 +557,10 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
381{ 557{
382 struct drm_device *dev = intel_dp_to_dev(intel_dp); 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
383 struct drm_i915_private *dev_priv = dev->dev_private; 559 struct drm_i915_private *dev_priv = dev->dev_private;
384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
385 struct intel_encoder *intel_encoder = &intel_dig_port->base;
386 enum intel_display_power_domain power_domain;
387 560
388 power_domain = intel_display_port_power_domain(intel_encoder); 561 lockdep_assert_held(&dev_priv->pps_mutex);
389 return intel_display_power_enabled(dev_priv, power_domain) && 562
390 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
391} 564}
392 565
393static void 566static void
@@ -535,7 +708,15 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
535 bool has_aux_irq = HAS_AUX_IRQ(dev); 708 bool has_aux_irq = HAS_AUX_IRQ(dev);
536 bool vdd; 709 bool vdd;
537 710
538 vdd = _edp_panel_vdd_on(intel_dp); 711 pps_lock(intel_dp);
712
713 /*
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
717 * ourselves.
718 */
719 vdd = edp_panel_vdd_on(intel_dp);
539 720
540 /* dp aux is extremely sensitive to irq latency, hence request the 721 /* dp aux is extremely sensitive to irq latency, hence request the
541 * lowest possible wakeup latency and so prevent the cpu from going into 722 * lowest possible wakeup latency and so prevent the cpu from going into
@@ -644,6 +825,8 @@ out:
644 if (vdd) 825 if (vdd)
645 edp_panel_vdd_off(intel_dp, false); 826 edp_panel_vdd_off(intel_dp, false);
646 827
828 pps_unlock(intel_dp);
829
647 return ret; 830 return ret;
648} 831}
649 832
@@ -1098,6 +1281,8 @@ static void wait_panel_status(struct intel_dp *intel_dp,
1098 struct drm_i915_private *dev_priv = dev->dev_private; 1281 struct drm_i915_private *dev_priv = dev->dev_private;
1099 u32 pp_stat_reg, pp_ctrl_reg; 1282 u32 pp_stat_reg, pp_ctrl_reg;
1100 1283
1284 lockdep_assert_held(&dev_priv->pps_mutex);
1285
1101 pp_stat_reg = _pp_stat_reg(intel_dp); 1286 pp_stat_reg = _pp_stat_reg(intel_dp);
1102 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1287 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1103 1288
@@ -1161,13 +1346,20 @@ static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1161 struct drm_i915_private *dev_priv = dev->dev_private; 1346 struct drm_i915_private *dev_priv = dev->dev_private;
1162 u32 control; 1347 u32 control;
1163 1348
1349 lockdep_assert_held(&dev_priv->pps_mutex);
1350
1164 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1351 control = I915_READ(_pp_ctrl_reg(intel_dp));
1165 control &= ~PANEL_UNLOCK_MASK; 1352 control &= ~PANEL_UNLOCK_MASK;
1166 control |= PANEL_UNLOCK_REGS; 1353 control |= PANEL_UNLOCK_REGS;
1167 return control; 1354 return control;
1168} 1355}
1169 1356
1170static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) 1357/*
1358 * Must be paired with edp_panel_vdd_off().
1359 * Must hold pps_mutex around the whole on/off sequence.
1360 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1361 */
1362static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1171{ 1363{
1172 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1364 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1173 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1365 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -1178,6 +1370,8 @@ static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1178 u32 pp_stat_reg, pp_ctrl_reg; 1370 u32 pp_stat_reg, pp_ctrl_reg;
1179 bool need_to_disable = !intel_dp->want_panel_vdd; 1371 bool need_to_disable = !intel_dp->want_panel_vdd;
1180 1372
1373 lockdep_assert_held(&dev_priv->pps_mutex);
1374
1181 if (!is_edp(intel_dp)) 1375 if (!is_edp(intel_dp))
1182 return false; 1376 return false;
1183 1377
@@ -1215,62 +1409,76 @@ static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1215 return need_to_disable; 1409 return need_to_disable;
1216} 1410}
1217 1411
1412/*
1413 * Must be paired with intel_edp_panel_vdd_off() or
1414 * intel_edp_panel_off().
1415 * Nested calls to these functions are not allowed since
1416 * we drop the lock. Caller must use some higher level
1417 * locking to prevent nested calls from other threads.
1418 */
1218void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1419void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1219{ 1420{
1220 if (is_edp(intel_dp)) { 1421 bool vdd;
1221 bool vdd = _edp_panel_vdd_on(intel_dp);
1222 1422
1223 WARN(!vdd, "eDP VDD already requested on\n"); 1423 if (!is_edp(intel_dp))
1224 } 1424 return;
1425
1426 pps_lock(intel_dp);
1427 vdd = edp_panel_vdd_on(intel_dp);
1428 pps_unlock(intel_dp);
1429
1430 WARN(!vdd, "eDP VDD already requested on\n");
1225} 1431}
1226 1432
1227static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1433static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1228{ 1434{
1229 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1435 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1230 struct drm_i915_private *dev_priv = dev->dev_private; 1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 struct intel_digital_port *intel_dig_port =
1438 dp_to_dig_port(intel_dp);
1439 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1440 enum intel_display_power_domain power_domain;
1231 u32 pp; 1441 u32 pp;
1232 u32 pp_stat_reg, pp_ctrl_reg; 1442 u32 pp_stat_reg, pp_ctrl_reg;
1233 1443
1234 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 1444 lockdep_assert_held(&dev_priv->pps_mutex);
1235 1445
1236 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { 1446 WARN_ON(intel_dp->want_panel_vdd);
1237 struct intel_digital_port *intel_dig_port =
1238 dp_to_dig_port(intel_dp);
1239 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1240 enum intel_display_power_domain power_domain;
1241 1447
1242 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1448 if (!edp_have_panel_vdd(intel_dp))
1449 return;
1243 1450
1244 pp = ironlake_get_pp_control(intel_dp); 1451 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1245 pp &= ~EDP_FORCE_VDD;
1246 1452
1247 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1453 pp = ironlake_get_pp_control(intel_dp);
1248 pp_stat_reg = _pp_stat_reg(intel_dp); 1454 pp &= ~EDP_FORCE_VDD;
1249 1455
1250 I915_WRITE(pp_ctrl_reg, pp); 1456 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1251 POSTING_READ(pp_ctrl_reg); 1457 pp_stat_reg = _pp_stat_reg(intel_dp);
1252 1458
1253 /* Make sure sequencer is idle before allowing subsequent activity */ 1459 I915_WRITE(pp_ctrl_reg, pp);
1254 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1460 POSTING_READ(pp_ctrl_reg);
1255 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1256 1461
1257 if ((pp & POWER_TARGET_ON) == 0) 1462 /* Make sure sequencer is idle before allowing subsequent activity */
1258 intel_dp->last_power_cycle = jiffies; 1463 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1464 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1259 1465
1260 power_domain = intel_display_port_power_domain(intel_encoder); 1466 if ((pp & POWER_TARGET_ON) == 0)
1261 intel_display_power_put(dev_priv, power_domain); 1467 intel_dp->last_power_cycle = jiffies;
1262 } 1468
1469 power_domain = intel_display_port_power_domain(intel_encoder);
1470 intel_display_power_put(dev_priv, power_domain);
1263} 1471}
1264 1472
1265static void edp_panel_vdd_work(struct work_struct *__work) 1473static void edp_panel_vdd_work(struct work_struct *__work)
1266{ 1474{
1267 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1475 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1268 struct intel_dp, panel_vdd_work); 1476 struct intel_dp, panel_vdd_work);
1269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1270 1477
1271 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1478 pps_lock(intel_dp);
1272 edp_panel_vdd_off_sync(intel_dp); 1479 if (!intel_dp->want_panel_vdd)
1273 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1480 edp_panel_vdd_off_sync(intel_dp);
1481 pps_unlock(intel_dp);
1274} 1482}
1275 1483
1276static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) 1484static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
@@ -1286,8 +1494,18 @@ static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1286 schedule_delayed_work(&intel_dp->panel_vdd_work, delay); 1494 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1287} 1495}
1288 1496
1497/*
1498 * Must be paired with edp_panel_vdd_on().
1499 * Must hold pps_mutex around the whole on/off sequence.
1500 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1501 */
1289static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1502static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1290{ 1503{
1504 struct drm_i915_private *dev_priv =
1505 intel_dp_to_dev(intel_dp)->dev_private;
1506
1507 lockdep_assert_held(&dev_priv->pps_mutex);
1508
1291 if (!is_edp(intel_dp)) 1509 if (!is_edp(intel_dp))
1292 return; 1510 return;
1293 1511
@@ -1301,6 +1519,22 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1301 edp_panel_vdd_schedule_off(intel_dp); 1519 edp_panel_vdd_schedule_off(intel_dp);
1302} 1520}
1303 1521
1522/*
1523 * Must be paired with intel_edp_panel_vdd_on().
1524 * Nested calls to these functions are not allowed since
1525 * we drop the lock. Caller must use some higher level
1526 * locking to prevent nested calls from other threads.
1527 */
1528static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1529{
1530 if (!is_edp(intel_dp))
1531 return;
1532
1533 pps_lock(intel_dp);
1534 edp_panel_vdd_off(intel_dp, sync);
1535 pps_unlock(intel_dp);
1536}
1537
1304void intel_edp_panel_on(struct intel_dp *intel_dp) 1538void intel_edp_panel_on(struct intel_dp *intel_dp)
1305{ 1539{
1306 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1540 struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -1313,9 +1547,11 @@ void intel_edp_panel_on(struct intel_dp *intel_dp)
1313 1547
1314 DRM_DEBUG_KMS("Turn eDP power on\n"); 1548 DRM_DEBUG_KMS("Turn eDP power on\n");
1315 1549
1550 pps_lock(intel_dp);
1551
1316 if (edp_have_panel_power(intel_dp)) { 1552 if (edp_have_panel_power(intel_dp)) {
1317 DRM_DEBUG_KMS("eDP power already on\n"); 1553 DRM_DEBUG_KMS("eDP power already on\n");
1318 return; 1554 goto out;
1319 } 1555 }
1320 1556
1321 wait_panel_power_cycle(intel_dp); 1557 wait_panel_power_cycle(intel_dp);
@@ -1344,6 +1580,9 @@ void intel_edp_panel_on(struct intel_dp *intel_dp)
1344 I915_WRITE(pp_ctrl_reg, pp); 1580 I915_WRITE(pp_ctrl_reg, pp);
1345 POSTING_READ(pp_ctrl_reg); 1581 POSTING_READ(pp_ctrl_reg);
1346 } 1582 }
1583
1584 out:
1585 pps_unlock(intel_dp);
1347} 1586}
1348 1587
1349void intel_edp_panel_off(struct intel_dp *intel_dp) 1588void intel_edp_panel_off(struct intel_dp *intel_dp)
@@ -1361,6 +1600,8 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
1361 1600
1362 DRM_DEBUG_KMS("Turn eDP power off\n"); 1601 DRM_DEBUG_KMS("Turn eDP power off\n");
1363 1602
1603 pps_lock(intel_dp);
1604
1364 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1605 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1365 1606
1366 pp = ironlake_get_pp_control(intel_dp); 1607 pp = ironlake_get_pp_control(intel_dp);
@@ -1382,9 +1623,12 @@ void intel_edp_panel_off(struct intel_dp *intel_dp)
1382 /* We got a reference when we enabled the VDD. */ 1623 /* We got a reference when we enabled the VDD. */
1383 power_domain = intel_display_port_power_domain(intel_encoder); 1624 power_domain = intel_display_port_power_domain(intel_encoder);
1384 intel_display_power_put(dev_priv, power_domain); 1625 intel_display_power_put(dev_priv, power_domain);
1626
1627 pps_unlock(intel_dp);
1385} 1628}
1386 1629
1387void intel_edp_backlight_on(struct intel_dp *intel_dp) 1630/* Enable backlight in the panel power control. */
1631static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1388{ 1632{
1389 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1633 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1390 struct drm_device *dev = intel_dig_port->base.base.dev; 1634 struct drm_device *dev = intel_dig_port->base.base.dev;
@@ -1392,13 +1636,6 @@ void intel_edp_backlight_on(struct intel_dp *intel_dp)
1392 u32 pp; 1636 u32 pp;
1393 u32 pp_ctrl_reg; 1637 u32 pp_ctrl_reg;
1394 1638
1395 if (!is_edp(intel_dp))
1396 return;
1397
1398 DRM_DEBUG_KMS("\n");
1399
1400 intel_panel_enable_backlight(intel_dp->attached_connector);
1401
1402 /* 1639 /*
1403 * If we enable the backlight right away following a panel power 1640 * If we enable the backlight right away following a panel power
1404 * on, we may see slight flicker as the panel syncs with the eDP 1641 * on, we may see slight flicker as the panel syncs with the eDP
@@ -1406,6 +1643,9 @@ void intel_edp_backlight_on(struct intel_dp *intel_dp)
1406 * allowing it to appear. 1643 * allowing it to appear.
1407 */ 1644 */
1408 wait_backlight_on(intel_dp); 1645 wait_backlight_on(intel_dp);
1646
1647 pps_lock(intel_dp);
1648
1409 pp = ironlake_get_pp_control(intel_dp); 1649 pp = ironlake_get_pp_control(intel_dp);
1410 pp |= EDP_BLC_ENABLE; 1650 pp |= EDP_BLC_ENABLE;
1411 1651
@@ -1413,9 +1653,24 @@ void intel_edp_backlight_on(struct intel_dp *intel_dp)
1413 1653
1414 I915_WRITE(pp_ctrl_reg, pp); 1654 I915_WRITE(pp_ctrl_reg, pp);
1415 POSTING_READ(pp_ctrl_reg); 1655 POSTING_READ(pp_ctrl_reg);
1656
1657 pps_unlock(intel_dp);
1416} 1658}
1417 1659
1418void intel_edp_backlight_off(struct intel_dp *intel_dp) 1660/* Enable backlight PWM and backlight PP control. */
1661void intel_edp_backlight_on(struct intel_dp *intel_dp)
1662{
1663 if (!is_edp(intel_dp))
1664 return;
1665
1666 DRM_DEBUG_KMS("\n");
1667
1668 intel_panel_enable_backlight(intel_dp->attached_connector);
1669 _intel_edp_backlight_on(intel_dp);
1670}
1671
1672/* Disable backlight in the panel power control. */
1673static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1419{ 1674{
1420 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1675 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1421 struct drm_i915_private *dev_priv = dev->dev_private; 1676 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1425,7 +1680,8 @@ void intel_edp_backlight_off(struct intel_dp *intel_dp)
1425 if (!is_edp(intel_dp)) 1680 if (!is_edp(intel_dp))
1426 return; 1681 return;
1427 1682
1428 DRM_DEBUG_KMS("\n"); 1683 pps_lock(intel_dp);
1684
1429 pp = ironlake_get_pp_control(intel_dp); 1685 pp = ironlake_get_pp_control(intel_dp);
1430 pp &= ~EDP_BLC_ENABLE; 1686 pp &= ~EDP_BLC_ENABLE;
1431 1687
@@ -1433,13 +1689,51 @@ void intel_edp_backlight_off(struct intel_dp *intel_dp)
1433 1689
1434 I915_WRITE(pp_ctrl_reg, pp); 1690 I915_WRITE(pp_ctrl_reg, pp);
1435 POSTING_READ(pp_ctrl_reg); 1691 POSTING_READ(pp_ctrl_reg);
1436 intel_dp->last_backlight_off = jiffies;
1437 1692
1693 pps_unlock(intel_dp);
1694
1695 intel_dp->last_backlight_off = jiffies;
1438 edp_wait_backlight_off(intel_dp); 1696 edp_wait_backlight_off(intel_dp);
1697}
1439 1698
1699/* Disable backlight PP control and backlight PWM. */
1700void intel_edp_backlight_off(struct intel_dp *intel_dp)
1701{
1702 if (!is_edp(intel_dp))
1703 return;
1704
1705 DRM_DEBUG_KMS("\n");
1706
1707 _intel_edp_backlight_off(intel_dp);
1440 intel_panel_disable_backlight(intel_dp->attached_connector); 1708 intel_panel_disable_backlight(intel_dp->attached_connector);
1441} 1709}
1442 1710
1711/*
1712 * Hook for controlling the panel power control backlight through the bl_power
1713 * sysfs attribute. Take care to handle multiple calls.
1714 */
1715static void intel_edp_backlight_power(struct intel_connector *connector,
1716 bool enable)
1717{
1718 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1719 bool is_enabled;
1720
1721 pps_lock(intel_dp);
1722 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1723 pps_unlock(intel_dp);
1724
1725 if (is_enabled == enable)
1726 return;
1727
1728 DRM_DEBUG_KMS("panel power control backlight %s\n",
1729 enable ? "enable" : "disable");
1730
1731 if (enable)
1732 _intel_edp_backlight_on(intel_dp);
1733 else
1734 _intel_edp_backlight_off(intel_dp);
1735}
1736
1443static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1737static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1444{ 1738{
1445 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1739 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -1503,8 +1797,6 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1503 if (mode != DRM_MODE_DPMS_ON) { 1797 if (mode != DRM_MODE_DPMS_ON) {
1504 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1798 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1505 DP_SET_POWER_D3); 1799 DP_SET_POWER_D3);
1506 if (ret != 1)
1507 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1508 } else { 1800 } else {
1509 /* 1801 /*
1510 * When turning on, we need to retry for 1ms to give the sink 1802 * When turning on, we need to retry for 1ms to give the sink
@@ -1518,6 +1810,10 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1518 msleep(1); 1810 msleep(1);
1519 } 1811 }
1520 } 1812 }
1813
1814 if (ret != 1)
1815 DRM_DEBUG_KMS("failed to %s sink power state\n",
1816 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
1521} 1817}
1522 1818
1523static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1819static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
@@ -1564,7 +1860,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1564 return true; 1860 return true;
1565 } 1861 }
1566 1862
1567 for_each_pipe(i) { 1863 for_each_pipe(dev_priv, i) {
1568 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1864 trans_dp = I915_READ(TRANS_DP_CTL(i));
1569 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1865 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1570 *pipe = i; 1866 *pipe = i;
@@ -2020,7 +2316,6 @@ void intel_edp_psr_init(struct drm_device *dev)
2020static void intel_disable_dp(struct intel_encoder *encoder) 2316static void intel_disable_dp(struct intel_encoder *encoder)
2021{ 2317{
2022 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2318 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2023 enum port port = dp_to_dig_port(intel_dp)->port;
2024 struct drm_device *dev = encoder->base.dev; 2319 struct drm_device *dev = encoder->base.dev;
2025 2320
2026 /* Make sure the panel is off before trying to change the mode. But also 2321 /* Make sure the panel is off before trying to change the mode. But also
@@ -2030,21 +2325,19 @@ static void intel_disable_dp(struct intel_encoder *encoder)
2030 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2325 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2031 intel_edp_panel_off(intel_dp); 2326 intel_edp_panel_off(intel_dp);
2032 2327
2033 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 2328 /* disable the port before the pipe on g4x */
2034 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 2329 if (INTEL_INFO(dev)->gen < 5)
2035 intel_dp_link_down(intel_dp); 2330 intel_dp_link_down(intel_dp);
2036} 2331}
2037 2332
2038static void g4x_post_disable_dp(struct intel_encoder *encoder) 2333static void ilk_post_disable_dp(struct intel_encoder *encoder)
2039{ 2334{
2040 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2335 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2041 enum port port = dp_to_dig_port(intel_dp)->port; 2336 enum port port = dp_to_dig_port(intel_dp)->port;
2042 2337
2043 if (port != PORT_A)
2044 return;
2045
2046 intel_dp_link_down(intel_dp); 2338 intel_dp_link_down(intel_dp);
2047 ironlake_edp_pll_off(intel_dp); 2339 if (port == PORT_A)
2340 ironlake_edp_pll_off(intel_dp);
2048} 2341}
2049 2342
2050static void vlv_post_disable_dp(struct intel_encoder *encoder) 2343static void vlv_post_disable_dp(struct intel_encoder *encoder)
@@ -2090,6 +2383,104 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
2090 mutex_unlock(&dev_priv->dpio_lock); 2383 mutex_unlock(&dev_priv->dpio_lock);
2091} 2384}
2092 2385
2386static void
2387_intel_dp_set_link_train(struct intel_dp *intel_dp,
2388 uint32_t *DP,
2389 uint8_t dp_train_pat)
2390{
2391 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2392 struct drm_device *dev = intel_dig_port->base.base.dev;
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 enum port port = intel_dig_port->port;
2395
2396 if (HAS_DDI(dev)) {
2397 uint32_t temp = I915_READ(DP_TP_CTL(port));
2398
2399 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2400 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2401 else
2402 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2403
2404 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2405 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2406 case DP_TRAINING_PATTERN_DISABLE:
2407 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2408
2409 break;
2410 case DP_TRAINING_PATTERN_1:
2411 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2412 break;
2413 case DP_TRAINING_PATTERN_2:
2414 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2415 break;
2416 case DP_TRAINING_PATTERN_3:
2417 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2418 break;
2419 }
2420 I915_WRITE(DP_TP_CTL(port), temp);
2421
2422 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2423 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2424
2425 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2426 case DP_TRAINING_PATTERN_DISABLE:
2427 *DP |= DP_LINK_TRAIN_OFF_CPT;
2428 break;
2429 case DP_TRAINING_PATTERN_1:
2430 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2431 break;
2432 case DP_TRAINING_PATTERN_2:
2433 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2434 break;
2435 case DP_TRAINING_PATTERN_3:
2436 DRM_ERROR("DP training pattern 3 not supported\n");
2437 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2438 break;
2439 }
2440
2441 } else {
2442 if (IS_CHERRYVIEW(dev))
2443 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2444 else
2445 *DP &= ~DP_LINK_TRAIN_MASK;
2446
2447 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2448 case DP_TRAINING_PATTERN_DISABLE:
2449 *DP |= DP_LINK_TRAIN_OFF;
2450 break;
2451 case DP_TRAINING_PATTERN_1:
2452 *DP |= DP_LINK_TRAIN_PAT_1;
2453 break;
2454 case DP_TRAINING_PATTERN_2:
2455 *DP |= DP_LINK_TRAIN_PAT_2;
2456 break;
2457 case DP_TRAINING_PATTERN_3:
2458 if (IS_CHERRYVIEW(dev)) {
2459 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2460 } else {
2461 DRM_ERROR("DP training pattern 3 not supported\n");
2462 *DP |= DP_LINK_TRAIN_PAT_2;
2463 }
2464 break;
2465 }
2466 }
2467}
2468
2469static void intel_dp_enable_port(struct intel_dp *intel_dp)
2470{
2471 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473
2474 intel_dp->DP |= DP_PORT_EN;
2475
2476 /* enable with pattern 1 (as per spec) */
2477 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2478 DP_TRAINING_PATTERN_1);
2479
2480 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2481 POSTING_READ(intel_dp->output_reg);
2482}
2483
2093static void intel_enable_dp(struct intel_encoder *encoder) 2484static void intel_enable_dp(struct intel_encoder *encoder)
2094{ 2485{
2095 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2486 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
@@ -2100,11 +2491,12 @@ static void intel_enable_dp(struct intel_encoder *encoder)
2100 if (WARN_ON(dp_reg & DP_PORT_EN)) 2491 if (WARN_ON(dp_reg & DP_PORT_EN))
2101 return; 2492 return;
2102 2493
2494 intel_dp_enable_port(intel_dp);
2103 intel_edp_panel_vdd_on(intel_dp); 2495 intel_edp_panel_vdd_on(intel_dp);
2496 intel_edp_panel_on(intel_dp);
2497 intel_edp_panel_vdd_off(intel_dp, true);
2104 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2498 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2105 intel_dp_start_link_train(intel_dp); 2499 intel_dp_start_link_train(intel_dp);
2106 intel_edp_panel_on(intel_dp);
2107 edp_panel_vdd_off(intel_dp, true);
2108 intel_dp_complete_link_train(intel_dp); 2500 intel_dp_complete_link_train(intel_dp);
2109 intel_dp_stop_link_train(intel_dp); 2501 intel_dp_stop_link_train(intel_dp);
2110} 2502}
@@ -2138,6 +2530,78 @@ static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2138 } 2530 }
2139} 2531}
2140 2532
2533static void vlv_steal_power_sequencer(struct drm_device *dev,
2534 enum pipe pipe)
2535{
2536 struct drm_i915_private *dev_priv = dev->dev_private;
2537 struct intel_encoder *encoder;
2538
2539 lockdep_assert_held(&dev_priv->pps_mutex);
2540
2541 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2542 base.head) {
2543 struct intel_dp *intel_dp;
2544 enum port port;
2545
2546 if (encoder->type != INTEL_OUTPUT_EDP)
2547 continue;
2548
2549 intel_dp = enc_to_intel_dp(&encoder->base);
2550 port = dp_to_dig_port(intel_dp)->port;
2551
2552 if (intel_dp->pps_pipe != pipe)
2553 continue;
2554
2555 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2556 pipe_name(pipe), port_name(port));
2557
2558 /* make sure vdd is off before we steal it */
2559 edp_panel_vdd_off_sync(intel_dp);
2560
2561 intel_dp->pps_pipe = INVALID_PIPE;
2562 }
2563}
2564
2565static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2566{
2567 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2568 struct intel_encoder *encoder = &intel_dig_port->base;
2569 struct drm_device *dev = encoder->base.dev;
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2572 struct edp_power_seq power_seq;
2573
2574 lockdep_assert_held(&dev_priv->pps_mutex);
2575
2576 if (intel_dp->pps_pipe == crtc->pipe)
2577 return;
2578
2579 /*
2580 * If another power sequencer was being used on this
2581 * port previously make sure to turn off vdd there while
2582 * we still have control of it.
2583 */
2584 if (intel_dp->pps_pipe != INVALID_PIPE)
2585 edp_panel_vdd_off_sync(intel_dp);
2586
2587 /*
2588 * We may be stealing the power
2589 * sequencer from another port.
2590 */
2591 vlv_steal_power_sequencer(dev, crtc->pipe);
2592
2593 /* now it's all ours */
2594 intel_dp->pps_pipe = crtc->pipe;
2595
2596 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2597 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2598
2599 /* init power sequencer on this pipe and port */
2600 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2601 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2602 &power_seq);
2603}
2604
2141static void vlv_pre_enable_dp(struct intel_encoder *encoder) 2605static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2142{ 2606{
2143 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2607 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
@@ -2147,7 +2611,6 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2147 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2611 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2148 enum dpio_channel port = vlv_dport_to_channel(dport); 2612 enum dpio_channel port = vlv_dport_to_channel(dport);
2149 int pipe = intel_crtc->pipe; 2613 int pipe = intel_crtc->pipe;
2150 struct edp_power_seq power_seq;
2151 u32 val; 2614 u32 val;
2152 2615
2153 mutex_lock(&dev_priv->dpio_lock); 2616 mutex_lock(&dev_priv->dpio_lock);
@@ -2166,10 +2629,9 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2166 mutex_unlock(&dev_priv->dpio_lock); 2629 mutex_unlock(&dev_priv->dpio_lock);
2167 2630
2168 if (is_edp(intel_dp)) { 2631 if (is_edp(intel_dp)) {
2169 /* init power sequencer on this pipe and port */ 2632 pps_lock(intel_dp);
2170 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2633 vlv_init_panel_power_sequencer(intel_dp);
2171 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2634 pps_unlock(intel_dp);
2172 &power_seq);
2173 } 2635 }
2174 2636
2175 intel_enable_dp(encoder); 2637 intel_enable_dp(encoder);
@@ -2213,7 +2675,6 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
2213 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2675 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2214 struct drm_device *dev = encoder->base.dev; 2676 struct drm_device *dev = encoder->base.dev;
2215 struct drm_i915_private *dev_priv = dev->dev_private; 2677 struct drm_i915_private *dev_priv = dev->dev_private;
2216 struct edp_power_seq power_seq;
2217 struct intel_crtc *intel_crtc = 2678 struct intel_crtc *intel_crtc =
2218 to_intel_crtc(encoder->base.crtc); 2679 to_intel_crtc(encoder->base.crtc);
2219 enum dpio_channel ch = vlv_dport_to_channel(dport); 2680 enum dpio_channel ch = vlv_dport_to_channel(dport);
@@ -2259,10 +2720,9 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
2259 mutex_unlock(&dev_priv->dpio_lock); 2720 mutex_unlock(&dev_priv->dpio_lock);
2260 2721
2261 if (is_edp(intel_dp)) { 2722 if (is_edp(intel_dp)) {
2262 /* init power sequencer on this pipe and port */ 2723 pps_lock(intel_dp);
2263 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2724 vlv_init_panel_power_sequencer(intel_dp);
2264 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2725 pps_unlock(intel_dp);
2265 &power_seq);
2266 } 2726 }
2267 2727
2268 intel_enable_dp(encoder); 2728 intel_enable_dp(encoder);
@@ -2381,13 +2841,13 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
2381 enum port port = dp_to_dig_port(intel_dp)->port; 2841 enum port port = dp_to_dig_port(intel_dp)->port;
2382 2842
2383 if (IS_VALLEYVIEW(dev)) 2843 if (IS_VALLEYVIEW(dev))
2384 return DP_TRAIN_VOLTAGE_SWING_1200; 2844 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2385 else if (IS_GEN7(dev) && port == PORT_A) 2845 else if (IS_GEN7(dev) && port == PORT_A)
2386 return DP_TRAIN_VOLTAGE_SWING_800; 2846 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2387 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2847 else if (HAS_PCH_CPT(dev) && port != PORT_A)
2388 return DP_TRAIN_VOLTAGE_SWING_1200; 2848 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2389 else 2849 else
2390 return DP_TRAIN_VOLTAGE_SWING_800; 2850 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2391} 2851}
2392 2852
2393static uint8_t 2853static uint8_t
@@ -2398,49 +2858,49 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2398 2858
2399 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2859 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2400 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2860 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2401 case DP_TRAIN_VOLTAGE_SWING_400: 2861 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2402 return DP_TRAIN_PRE_EMPHASIS_9_5; 2862 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2403 case DP_TRAIN_VOLTAGE_SWING_600: 2863 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2404 return DP_TRAIN_PRE_EMPHASIS_6; 2864 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2405 case DP_TRAIN_VOLTAGE_SWING_800: 2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2406 return DP_TRAIN_PRE_EMPHASIS_3_5; 2866 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2407 case DP_TRAIN_VOLTAGE_SWING_1200: 2867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2408 default: 2868 default:
2409 return DP_TRAIN_PRE_EMPHASIS_0; 2869 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2410 } 2870 }
2411 } else if (IS_VALLEYVIEW(dev)) { 2871 } else if (IS_VALLEYVIEW(dev)) {
2412 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2872 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2413 case DP_TRAIN_VOLTAGE_SWING_400: 2873 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2414 return DP_TRAIN_PRE_EMPHASIS_9_5; 2874 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2415 case DP_TRAIN_VOLTAGE_SWING_600: 2875 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2416 return DP_TRAIN_PRE_EMPHASIS_6; 2876 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2417 case DP_TRAIN_VOLTAGE_SWING_800: 2877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2418 return DP_TRAIN_PRE_EMPHASIS_3_5; 2878 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2419 case DP_TRAIN_VOLTAGE_SWING_1200: 2879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2420 default: 2880 default:
2421 return DP_TRAIN_PRE_EMPHASIS_0; 2881 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2422 } 2882 }
2423 } else if (IS_GEN7(dev) && port == PORT_A) { 2883 } else if (IS_GEN7(dev) && port == PORT_A) {
2424 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2884 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2425 case DP_TRAIN_VOLTAGE_SWING_400: 2885 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2426 return DP_TRAIN_PRE_EMPHASIS_6; 2886 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2427 case DP_TRAIN_VOLTAGE_SWING_600: 2887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2428 case DP_TRAIN_VOLTAGE_SWING_800: 2888 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2429 return DP_TRAIN_PRE_EMPHASIS_3_5; 2889 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2430 default: 2890 default:
2431 return DP_TRAIN_PRE_EMPHASIS_0; 2891 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2432 } 2892 }
2433 } else { 2893 } else {
2434 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2894 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2435 case DP_TRAIN_VOLTAGE_SWING_400: 2895 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2436 return DP_TRAIN_PRE_EMPHASIS_6; 2896 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2437 case DP_TRAIN_VOLTAGE_SWING_600: 2897 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2438 return DP_TRAIN_PRE_EMPHASIS_6; 2898 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2439 case DP_TRAIN_VOLTAGE_SWING_800: 2899 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2440 return DP_TRAIN_PRE_EMPHASIS_3_5; 2900 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2441 case DP_TRAIN_VOLTAGE_SWING_1200: 2901 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2442 default: 2902 default:
2443 return DP_TRAIN_PRE_EMPHASIS_0; 2903 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2444 } 2904 }
2445 } 2905 }
2446} 2906}
@@ -2459,22 +2919,22 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2459 int pipe = intel_crtc->pipe; 2919 int pipe = intel_crtc->pipe;
2460 2920
2461 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2921 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2462 case DP_TRAIN_PRE_EMPHASIS_0: 2922 case DP_TRAIN_PRE_EMPH_LEVEL_0:
2463 preemph_reg_value = 0x0004000; 2923 preemph_reg_value = 0x0004000;
2464 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2924 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2465 case DP_TRAIN_VOLTAGE_SWING_400: 2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2466 demph_reg_value = 0x2B405555; 2926 demph_reg_value = 0x2B405555;
2467 uniqtranscale_reg_value = 0x552AB83A; 2927 uniqtranscale_reg_value = 0x552AB83A;
2468 break; 2928 break;
2469 case DP_TRAIN_VOLTAGE_SWING_600: 2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2470 demph_reg_value = 0x2B404040; 2930 demph_reg_value = 0x2B404040;
2471 uniqtranscale_reg_value = 0x5548B83A; 2931 uniqtranscale_reg_value = 0x5548B83A;
2472 break; 2932 break;
2473 case DP_TRAIN_VOLTAGE_SWING_800: 2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2474 demph_reg_value = 0x2B245555; 2934 demph_reg_value = 0x2B245555;
2475 uniqtranscale_reg_value = 0x5560B83A; 2935 uniqtranscale_reg_value = 0x5560B83A;
2476 break; 2936 break;
2477 case DP_TRAIN_VOLTAGE_SWING_1200: 2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2478 demph_reg_value = 0x2B405555; 2938 demph_reg_value = 0x2B405555;
2479 uniqtranscale_reg_value = 0x5598DA3A; 2939 uniqtranscale_reg_value = 0x5598DA3A;
2480 break; 2940 break;
@@ -2482,18 +2942,18 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2482 return 0; 2942 return 0;
2483 } 2943 }
2484 break; 2944 break;
2485 case DP_TRAIN_PRE_EMPHASIS_3_5: 2945 case DP_TRAIN_PRE_EMPH_LEVEL_1:
2486 preemph_reg_value = 0x0002000; 2946 preemph_reg_value = 0x0002000;
2487 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2947 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2488 case DP_TRAIN_VOLTAGE_SWING_400: 2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2489 demph_reg_value = 0x2B404040; 2949 demph_reg_value = 0x2B404040;
2490 uniqtranscale_reg_value = 0x5552B83A; 2950 uniqtranscale_reg_value = 0x5552B83A;
2491 break; 2951 break;
2492 case DP_TRAIN_VOLTAGE_SWING_600: 2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2493 demph_reg_value = 0x2B404848; 2953 demph_reg_value = 0x2B404848;
2494 uniqtranscale_reg_value = 0x5580B83A; 2954 uniqtranscale_reg_value = 0x5580B83A;
2495 break; 2955 break;
2496 case DP_TRAIN_VOLTAGE_SWING_800: 2956 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2497 demph_reg_value = 0x2B404040; 2957 demph_reg_value = 0x2B404040;
2498 uniqtranscale_reg_value = 0x55ADDA3A; 2958 uniqtranscale_reg_value = 0x55ADDA3A;
2499 break; 2959 break;
@@ -2501,14 +2961,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2501 return 0; 2961 return 0;
2502 } 2962 }
2503 break; 2963 break;
2504 case DP_TRAIN_PRE_EMPHASIS_6: 2964 case DP_TRAIN_PRE_EMPH_LEVEL_2:
2505 preemph_reg_value = 0x0000000; 2965 preemph_reg_value = 0x0000000;
2506 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2966 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2507 case DP_TRAIN_VOLTAGE_SWING_400: 2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2508 demph_reg_value = 0x2B305555; 2968 demph_reg_value = 0x2B305555;
2509 uniqtranscale_reg_value = 0x5570B83A; 2969 uniqtranscale_reg_value = 0x5570B83A;
2510 break; 2970 break;
2511 case DP_TRAIN_VOLTAGE_SWING_600: 2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2512 demph_reg_value = 0x2B2B4040; 2972 demph_reg_value = 0x2B2B4040;
2513 uniqtranscale_reg_value = 0x55ADDA3A; 2973 uniqtranscale_reg_value = 0x55ADDA3A;
2514 break; 2974 break;
@@ -2516,10 +2976,10 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2516 return 0; 2976 return 0;
2517 } 2977 }
2518 break; 2978 break;
2519 case DP_TRAIN_PRE_EMPHASIS_9_5: 2979 case DP_TRAIN_PRE_EMPH_LEVEL_3:
2520 preemph_reg_value = 0x0006000; 2980 preemph_reg_value = 0x0006000;
2521 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2981 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2522 case DP_TRAIN_VOLTAGE_SWING_400: 2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2523 demph_reg_value = 0x1B405555; 2983 demph_reg_value = 0x1B405555;
2524 uniqtranscale_reg_value = 0x55ADDA3A; 2984 uniqtranscale_reg_value = 0x55ADDA3A;
2525 break; 2985 break;
@@ -2558,21 +3018,21 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2558 int i; 3018 int i;
2559 3019
2560 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3020 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2561 case DP_TRAIN_PRE_EMPHASIS_0: 3021 case DP_TRAIN_PRE_EMPH_LEVEL_0:
2562 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3022 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2563 case DP_TRAIN_VOLTAGE_SWING_400: 3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2564 deemph_reg_value = 128; 3024 deemph_reg_value = 128;
2565 margin_reg_value = 52; 3025 margin_reg_value = 52;
2566 break; 3026 break;
2567 case DP_TRAIN_VOLTAGE_SWING_600: 3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2568 deemph_reg_value = 128; 3028 deemph_reg_value = 128;
2569 margin_reg_value = 77; 3029 margin_reg_value = 77;
2570 break; 3030 break;
2571 case DP_TRAIN_VOLTAGE_SWING_800: 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2572 deemph_reg_value = 128; 3032 deemph_reg_value = 128;
2573 margin_reg_value = 102; 3033 margin_reg_value = 102;
2574 break; 3034 break;
2575 case DP_TRAIN_VOLTAGE_SWING_1200: 3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2576 deemph_reg_value = 128; 3036 deemph_reg_value = 128;
2577 margin_reg_value = 154; 3037 margin_reg_value = 154;
2578 /* FIXME extra to set for 1200 */ 3038 /* FIXME extra to set for 1200 */
@@ -2581,17 +3041,17 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2581 return 0; 3041 return 0;
2582 } 3042 }
2583 break; 3043 break;
2584 case DP_TRAIN_PRE_EMPHASIS_3_5: 3044 case DP_TRAIN_PRE_EMPH_LEVEL_1:
2585 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3045 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2586 case DP_TRAIN_VOLTAGE_SWING_400: 3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2587 deemph_reg_value = 85; 3047 deemph_reg_value = 85;
2588 margin_reg_value = 78; 3048 margin_reg_value = 78;
2589 break; 3049 break;
2590 case DP_TRAIN_VOLTAGE_SWING_600: 3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2591 deemph_reg_value = 85; 3051 deemph_reg_value = 85;
2592 margin_reg_value = 116; 3052 margin_reg_value = 116;
2593 break; 3053 break;
2594 case DP_TRAIN_VOLTAGE_SWING_800: 3054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2595 deemph_reg_value = 85; 3055 deemph_reg_value = 85;
2596 margin_reg_value = 154; 3056 margin_reg_value = 154;
2597 break; 3057 break;
@@ -2599,13 +3059,13 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2599 return 0; 3059 return 0;
2600 } 3060 }
2601 break; 3061 break;
2602 case DP_TRAIN_PRE_EMPHASIS_6: 3062 case DP_TRAIN_PRE_EMPH_LEVEL_2:
2603 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3063 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2604 case DP_TRAIN_VOLTAGE_SWING_400: 3064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2605 deemph_reg_value = 64; 3065 deemph_reg_value = 64;
2606 margin_reg_value = 104; 3066 margin_reg_value = 104;
2607 break; 3067 break;
2608 case DP_TRAIN_VOLTAGE_SWING_600: 3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2609 deemph_reg_value = 64; 3069 deemph_reg_value = 64;
2610 margin_reg_value = 154; 3070 margin_reg_value = 154;
2611 break; 3071 break;
@@ -2613,9 +3073,9 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2613 return 0; 3073 return 0;
2614 } 3074 }
2615 break; 3075 break;
2616 case DP_TRAIN_PRE_EMPHASIS_9_5: 3076 case DP_TRAIN_PRE_EMPH_LEVEL_3:
2617 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3077 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2618 case DP_TRAIN_VOLTAGE_SWING_400: 3078 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2619 deemph_reg_value = 43; 3079 deemph_reg_value = 43;
2620 margin_reg_value = 154; 3080 margin_reg_value = 154;
2621 break; 3081 break;
@@ -2662,9 +3122,9 @@ static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2662 } 3122 }
2663 3123
2664 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) 3124 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2665 == DP_TRAIN_PRE_EMPHASIS_0) && 3125 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
2666 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) 3126 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2667 == DP_TRAIN_VOLTAGE_SWING_1200)) { 3127 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
2668 3128
2669 /* 3129 /*
2670 * The document said it needs to set bit 27 for ch0 and bit 26 3130 * The document said it needs to set bit 27 for ch0 and bit 26
@@ -2743,32 +3203,32 @@ intel_gen4_signal_levels(uint8_t train_set)
2743 uint32_t signal_levels = 0; 3203 uint32_t signal_levels = 0;
2744 3204
2745 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3205 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2746 case DP_TRAIN_VOLTAGE_SWING_400: 3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2747 default: 3207 default:
2748 signal_levels |= DP_VOLTAGE_0_4; 3208 signal_levels |= DP_VOLTAGE_0_4;
2749 break; 3209 break;
2750 case DP_TRAIN_VOLTAGE_SWING_600: 3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2751 signal_levels |= DP_VOLTAGE_0_6; 3211 signal_levels |= DP_VOLTAGE_0_6;
2752 break; 3212 break;
2753 case DP_TRAIN_VOLTAGE_SWING_800: 3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2754 signal_levels |= DP_VOLTAGE_0_8; 3214 signal_levels |= DP_VOLTAGE_0_8;
2755 break; 3215 break;
2756 case DP_TRAIN_VOLTAGE_SWING_1200: 3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2757 signal_levels |= DP_VOLTAGE_1_2; 3217 signal_levels |= DP_VOLTAGE_1_2;
2758 break; 3218 break;
2759 } 3219 }
2760 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3220 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2761 case DP_TRAIN_PRE_EMPHASIS_0: 3221 case DP_TRAIN_PRE_EMPH_LEVEL_0:
2762 default: 3222 default:
2763 signal_levels |= DP_PRE_EMPHASIS_0; 3223 signal_levels |= DP_PRE_EMPHASIS_0;
2764 break; 3224 break;
2765 case DP_TRAIN_PRE_EMPHASIS_3_5: 3225 case DP_TRAIN_PRE_EMPH_LEVEL_1:
2766 signal_levels |= DP_PRE_EMPHASIS_3_5; 3226 signal_levels |= DP_PRE_EMPHASIS_3_5;
2767 break; 3227 break;
2768 case DP_TRAIN_PRE_EMPHASIS_6: 3228 case DP_TRAIN_PRE_EMPH_LEVEL_2:
2769 signal_levels |= DP_PRE_EMPHASIS_6; 3229 signal_levels |= DP_PRE_EMPHASIS_6;
2770 break; 3230 break;
2771 case DP_TRAIN_PRE_EMPHASIS_9_5: 3231 case DP_TRAIN_PRE_EMPH_LEVEL_3:
2772 signal_levels |= DP_PRE_EMPHASIS_9_5; 3232 signal_levels |= DP_PRE_EMPHASIS_9_5;
2773 break; 3233 break;
2774 } 3234 }
@@ -2782,19 +3242,19 @@ intel_gen6_edp_signal_levels(uint8_t train_set)
2782 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3242 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2783 DP_TRAIN_PRE_EMPHASIS_MASK); 3243 DP_TRAIN_PRE_EMPHASIS_MASK);
2784 switch (signal_levels) { 3244 switch (signal_levels) {
2785 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2786 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2787 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3247 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2788 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2789 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 3249 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2790 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2791 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2792 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 3252 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2793 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2794 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2795 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 3255 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2796 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2797 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 3257 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2798 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 3258 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2799 default: 3259 default:
2800 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3260 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
@@ -2810,21 +3270,21 @@ intel_gen7_edp_signal_levels(uint8_t train_set)
2810 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3270 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2811 DP_TRAIN_PRE_EMPHASIS_MASK); 3271 DP_TRAIN_PRE_EMPHASIS_MASK);
2812 switch (signal_levels) { 3272 switch (signal_levels) {
2813 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2814 return EDP_LINK_TRAIN_400MV_0DB_IVB; 3274 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2815 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 3275 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2816 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 3276 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2817 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 3277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2818 return EDP_LINK_TRAIN_400MV_6DB_IVB; 3278 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2819 3279
2820 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 3280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2821 return EDP_LINK_TRAIN_600MV_0DB_IVB; 3281 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2822 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2823 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 3283 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2824 3284
2825 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2826 return EDP_LINK_TRAIN_800MV_0DB_IVB; 3286 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2827 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2828 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 3288 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2829 3289
2830 default: 3290 default:
@@ -2841,30 +3301,30 @@ intel_hsw_signal_levels(uint8_t train_set)
2841 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3301 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2842 DP_TRAIN_PRE_EMPHASIS_MASK); 3302 DP_TRAIN_PRE_EMPHASIS_MASK);
2843 switch (signal_levels) { 3303 switch (signal_levels) {
2844 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2845 return DDI_BUF_EMP_400MV_0DB_HSW; 3305 return DDI_BUF_TRANS_SELECT(0);
2846 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2847 return DDI_BUF_EMP_400MV_3_5DB_HSW; 3307 return DDI_BUF_TRANS_SELECT(1);
2848 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2849 return DDI_BUF_EMP_400MV_6DB_HSW; 3309 return DDI_BUF_TRANS_SELECT(2);
2850 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2851 return DDI_BUF_EMP_400MV_9_5DB_HSW; 3311 return DDI_BUF_TRANS_SELECT(3);
2852 3312
2853 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2854 return DDI_BUF_EMP_600MV_0DB_HSW; 3314 return DDI_BUF_TRANS_SELECT(4);
2855 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2856 return DDI_BUF_EMP_600MV_3_5DB_HSW; 3316 return DDI_BUF_TRANS_SELECT(5);
2857 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2858 return DDI_BUF_EMP_600MV_6DB_HSW; 3318 return DDI_BUF_TRANS_SELECT(6);
2859 3319
2860 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2861 return DDI_BUF_EMP_800MV_0DB_HSW; 3321 return DDI_BUF_TRANS_SELECT(7);
2862 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2863 return DDI_BUF_EMP_800MV_3_5DB_HSW; 3323 return DDI_BUF_TRANS_SELECT(8);
2864 default: 3324 default:
2865 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3325 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2866 "0x%x\n", signal_levels); 3326 "0x%x\n", signal_levels);
2867 return DDI_BUF_EMP_400MV_0DB_HSW; 3327 return DDI_BUF_TRANS_SELECT(0);
2868 } 3328 }
2869} 3329}
2870 3330
@@ -2911,81 +3371,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
2911 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3371 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2912 struct drm_device *dev = intel_dig_port->base.base.dev; 3372 struct drm_device *dev = intel_dig_port->base.base.dev;
2913 struct drm_i915_private *dev_priv = dev->dev_private; 3373 struct drm_i915_private *dev_priv = dev->dev_private;
2914 enum port port = intel_dig_port->port;
2915 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 3374 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2916 int ret, len; 3375 int ret, len;
2917 3376
2918 if (HAS_DDI(dev)) { 3377 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2919 uint32_t temp = I915_READ(DP_TP_CTL(port));
2920
2921 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2922 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2923 else
2924 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2925
2926 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2927 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2928 case DP_TRAINING_PATTERN_DISABLE:
2929 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2930
2931 break;
2932 case DP_TRAINING_PATTERN_1:
2933 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2934 break;
2935 case DP_TRAINING_PATTERN_2:
2936 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2937 break;
2938 case DP_TRAINING_PATTERN_3:
2939 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2940 break;
2941 }
2942 I915_WRITE(DP_TP_CTL(port), temp);
2943
2944 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2945 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2946
2947 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2948 case DP_TRAINING_PATTERN_DISABLE:
2949 *DP |= DP_LINK_TRAIN_OFF_CPT;
2950 break;
2951 case DP_TRAINING_PATTERN_1:
2952 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2953 break;
2954 case DP_TRAINING_PATTERN_2:
2955 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2956 break;
2957 case DP_TRAINING_PATTERN_3:
2958 DRM_ERROR("DP training pattern 3 not supported\n");
2959 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2960 break;
2961 }
2962
2963 } else {
2964 if (IS_CHERRYVIEW(dev))
2965 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2966 else
2967 *DP &= ~DP_LINK_TRAIN_MASK;
2968
2969 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2970 case DP_TRAINING_PATTERN_DISABLE:
2971 *DP |= DP_LINK_TRAIN_OFF;
2972 break;
2973 case DP_TRAINING_PATTERN_1:
2974 *DP |= DP_LINK_TRAIN_PAT_1;
2975 break;
2976 case DP_TRAINING_PATTERN_2:
2977 *DP |= DP_LINK_TRAIN_PAT_2;
2978 break;
2979 case DP_TRAINING_PATTERN_3:
2980 if (IS_CHERRYVIEW(dev)) {
2981 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2982 } else {
2983 DRM_ERROR("DP training pattern 3 not supported\n");
2984 *DP |= DP_LINK_TRAIN_PAT_2;
2985 }
2986 break;
2987 }
2988 }
2989 3378
2990 I915_WRITE(intel_dp->output_reg, *DP); 3379 I915_WRITE(intel_dp->output_reg, *DP);
2991 POSTING_READ(intel_dp->output_reg); 3380 POSTING_READ(intel_dp->output_reg);
@@ -3318,15 +3707,11 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
3318 struct drm_device *dev = dig_port->base.base.dev; 3707 struct drm_device *dev = dig_port->base.base.dev;
3319 struct drm_i915_private *dev_priv = dev->dev_private; 3708 struct drm_i915_private *dev_priv = dev->dev_private;
3320 3709
3321 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3322
3323 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, 3710 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3324 sizeof(intel_dp->dpcd)) < 0) 3711 sizeof(intel_dp->dpcd)) < 0)
3325 return false; /* aux transfer failed */ 3712 return false; /* aux transfer failed */
3326 3713
3327 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 3714 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3328 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3329 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3330 3715
3331 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 3716 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3332 return false; /* DPCD not present */ 3717 return false; /* DPCD not present */
@@ -3384,7 +3769,7 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
3384 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 3769 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3385 buf[0], buf[1], buf[2]); 3770 buf[0], buf[1], buf[2]);
3386 3771
3387 edp_panel_vdd_off(intel_dp, false); 3772 intel_edp_panel_vdd_off(intel_dp, false);
3388} 3773}
3389 3774
3390static bool 3775static bool
@@ -3398,7 +3783,7 @@ intel_dp_probe_mst(struct intel_dp *intel_dp)
3398 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) 3783 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3399 return false; 3784 return false;
3400 3785
3401 _edp_panel_vdd_on(intel_dp); 3786 intel_edp_panel_vdd_on(intel_dp);
3402 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { 3787 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3403 if (buf[0] & DP_MST_CAP) { 3788 if (buf[0] & DP_MST_CAP) {
3404 DRM_DEBUG_KMS("Sink is MST capable\n"); 3789 DRM_DEBUG_KMS("Sink is MST capable\n");
@@ -3408,7 +3793,7 @@ intel_dp_probe_mst(struct intel_dp *intel_dp)
3408 intel_dp->is_mst = false; 3793 intel_dp->is_mst = false;
3409 } 3794 }
3410 } 3795 }
3411 edp_panel_vdd_off(intel_dp, false); 3796 intel_edp_panel_vdd_off(intel_dp, false);
3412 3797
3413 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3798 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3414 return intel_dp->is_mst; 3799 return intel_dp->is_mst;
@@ -3640,20 +4025,24 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3640} 4025}
3641 4026
3642static enum drm_connector_status 4027static enum drm_connector_status
4028edp_detect(struct intel_dp *intel_dp)
4029{
4030 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4031 enum drm_connector_status status;
4032
4033 status = intel_panel_detect(dev);
4034 if (status == connector_status_unknown)
4035 status = connector_status_connected;
4036
4037 return status;
4038}
4039
4040static enum drm_connector_status
3643ironlake_dp_detect(struct intel_dp *intel_dp) 4041ironlake_dp_detect(struct intel_dp *intel_dp)
3644{ 4042{
3645 struct drm_device *dev = intel_dp_to_dev(intel_dp); 4043 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3646 struct drm_i915_private *dev_priv = dev->dev_private; 4044 struct drm_i915_private *dev_priv = dev->dev_private;
3647 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4045 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3648 enum drm_connector_status status;
3649
3650 /* Can't disconnect eDP, but you can close the lid... */
3651 if (is_edp(intel_dp)) {
3652 status = intel_panel_detect(dev);
3653 if (status == connector_status_unknown)
3654 status = connector_status_connected;
3655 return status;
3656 }
3657 4046
3658 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 4047 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3659 return connector_status_disconnected; 4048 return connector_status_disconnected;
@@ -3729,9 +4118,9 @@ g4x_dp_detect(struct intel_dp *intel_dp)
3729} 4118}
3730 4119
3731static struct edid * 4120static struct edid *
3732intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 4121intel_dp_get_edid(struct intel_dp *intel_dp)
3733{ 4122{
3734 struct intel_connector *intel_connector = to_intel_connector(connector); 4123 struct intel_connector *intel_connector = intel_dp->attached_connector;
3735 4124
3736 /* use cached edid if we have one */ 4125 /* use cached edid if we have one */
3737 if (intel_connector->edid) { 4126 if (intel_connector->edid) {
@@ -3740,27 +4129,55 @@ intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3740 return NULL; 4129 return NULL;
3741 4130
3742 return drm_edid_duplicate(intel_connector->edid); 4131 return drm_edid_duplicate(intel_connector->edid);
3743 } 4132 } else
4133 return drm_get_edid(&intel_connector->base,
4134 &intel_dp->aux.ddc);
4135}
4136
4137static void
4138intel_dp_set_edid(struct intel_dp *intel_dp)
4139{
4140 struct intel_connector *intel_connector = intel_dp->attached_connector;
4141 struct edid *edid;
4142
4143 edid = intel_dp_get_edid(intel_dp);
4144 intel_connector->detect_edid = edid;
3744 4145
3745 return drm_get_edid(connector, adapter); 4146 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4147 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4148 else
4149 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3746} 4150}
3747 4151
3748static int 4152static void
3749intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 4153intel_dp_unset_edid(struct intel_dp *intel_dp)
3750{ 4154{
3751 struct intel_connector *intel_connector = to_intel_connector(connector); 4155 struct intel_connector *intel_connector = intel_dp->attached_connector;
3752 4156
3753 /* use cached edid if we have one */ 4157 kfree(intel_connector->detect_edid);
3754 if (intel_connector->edid) { 4158 intel_connector->detect_edid = NULL;
3755 /* invalid edid */
3756 if (IS_ERR(intel_connector->edid))
3757 return 0;
3758 4159
3759 return intel_connector_update_modes(connector, 4160 intel_dp->has_audio = false;
3760 intel_connector->edid); 4161}
3761 } 4162
4163static enum intel_display_power_domain
4164intel_dp_power_get(struct intel_dp *dp)
4165{
4166 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4167 enum intel_display_power_domain power_domain;
4168
4169 power_domain = intel_display_port_power_domain(encoder);
4170 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4171
4172 return power_domain;
4173}
3762 4174
3763 return intel_ddc_get_modes(connector, adapter); 4175static void
4176intel_dp_power_put(struct intel_dp *dp,
4177 enum intel_display_power_domain power_domain)
4178{
4179 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4180 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
3764} 4181}
3765 4182
3766static enum drm_connector_status 4183static enum drm_connector_status
@@ -3770,33 +4187,30 @@ intel_dp_detect(struct drm_connector *connector, bool force)
3770 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4187 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3771 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4188 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3772 struct drm_device *dev = connector->dev; 4189 struct drm_device *dev = connector->dev;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774 enum drm_connector_status status; 4190 enum drm_connector_status status;
3775 enum intel_display_power_domain power_domain; 4191 enum intel_display_power_domain power_domain;
3776 struct edid *edid = NULL;
3777 bool ret; 4192 bool ret;
3778 4193
3779 power_domain = intel_display_port_power_domain(intel_encoder);
3780 intel_display_power_get(dev_priv, power_domain);
3781
3782 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 4194 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3783 connector->base.id, connector->name); 4195 connector->base.id, connector->name);
4196 intel_dp_unset_edid(intel_dp);
3784 4197
3785 if (intel_dp->is_mst) { 4198 if (intel_dp->is_mst) {
3786 /* MST devices are disconnected from a monitor POV */ 4199 /* MST devices are disconnected from a monitor POV */
3787 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4200 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3788 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 4201 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3789 status = connector_status_disconnected; 4202 return connector_status_disconnected;
3790 goto out;
3791 } 4203 }
3792 4204
3793 intel_dp->has_audio = false; 4205 power_domain = intel_dp_power_get(intel_dp);
3794 4206
3795 if (HAS_PCH_SPLIT(dev)) 4207 /* Can't disconnect eDP, but you can close the lid... */
4208 if (is_edp(intel_dp))
4209 status = edp_detect(intel_dp);
4210 else if (HAS_PCH_SPLIT(dev))
3796 status = ironlake_dp_detect(intel_dp); 4211 status = ironlake_dp_detect(intel_dp);
3797 else 4212 else
3798 status = g4x_dp_detect(intel_dp); 4213 status = g4x_dp_detect(intel_dp);
3799
3800 if (status != connector_status_connected) 4214 if (status != connector_status_connected)
3801 goto out; 4215 goto out;
3802 4216
@@ -3812,82 +4226,78 @@ intel_dp_detect(struct drm_connector *connector, bool force)
3812 goto out; 4226 goto out;
3813 } 4227 }
3814 4228
3815 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 4229 intel_dp_set_edid(intel_dp);
3816 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3817 } else {
3818 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3819 if (edid) {
3820 intel_dp->has_audio = drm_detect_monitor_audio(edid);
3821 kfree(edid);
3822 }
3823 }
3824 4230
3825 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4231 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3826 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 4232 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3827 status = connector_status_connected; 4233 status = connector_status_connected;
3828 4234
3829out: 4235out:
3830 intel_display_power_put(dev_priv, power_domain); 4236 intel_dp_power_put(intel_dp, power_domain);
3831 return status; 4237 return status;
3832} 4238}
3833 4239
3834static int intel_dp_get_modes(struct drm_connector *connector) 4240static void
4241intel_dp_force(struct drm_connector *connector)
3835{ 4242{
3836 struct intel_dp *intel_dp = intel_attached_dp(connector); 4243 struct intel_dp *intel_dp = intel_attached_dp(connector);
3837 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4244 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3838 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3839 struct intel_connector *intel_connector = to_intel_connector(connector);
3840 struct drm_device *dev = connector->dev;
3841 struct drm_i915_private *dev_priv = dev->dev_private;
3842 enum intel_display_power_domain power_domain; 4245 enum intel_display_power_domain power_domain;
3843 int ret;
3844 4246
3845 /* We should parse the EDID data and find out if it has an audio sink 4247 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3846 */ 4248 connector->base.id, connector->name);
4249 intel_dp_unset_edid(intel_dp);
3847 4250
3848 power_domain = intel_display_port_power_domain(intel_encoder); 4251 if (connector->status != connector_status_connected)
3849 intel_display_power_get(dev_priv, power_domain); 4252 return;
3850 4253
3851 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); 4254 power_domain = intel_dp_power_get(intel_dp);
3852 intel_display_power_put(dev_priv, power_domain); 4255
3853 if (ret) 4256 intel_dp_set_edid(intel_dp);
3854 return ret; 4257
4258 intel_dp_power_put(intel_dp, power_domain);
4259
4260 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4261 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4262}
4263
4264static int intel_dp_get_modes(struct drm_connector *connector)
4265{
4266 struct intel_connector *intel_connector = to_intel_connector(connector);
4267 struct edid *edid;
4268
4269 edid = intel_connector->detect_edid;
4270 if (edid) {
4271 int ret = intel_connector_update_modes(connector, edid);
4272 if (ret)
4273 return ret;
4274 }
3855 4275
3856 /* if eDP has no EDID, fall back to fixed mode */ 4276 /* if eDP has no EDID, fall back to fixed mode */
3857 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 4277 if (is_edp(intel_attached_dp(connector)) &&
4278 intel_connector->panel.fixed_mode) {
3858 struct drm_display_mode *mode; 4279 struct drm_display_mode *mode;
3859 mode = drm_mode_duplicate(dev, 4280
4281 mode = drm_mode_duplicate(connector->dev,
3860 intel_connector->panel.fixed_mode); 4282 intel_connector->panel.fixed_mode);
3861 if (mode) { 4283 if (mode) {
3862 drm_mode_probed_add(connector, mode); 4284 drm_mode_probed_add(connector, mode);
3863 return 1; 4285 return 1;
3864 } 4286 }
3865 } 4287 }
4288
3866 return 0; 4289 return 0;
3867} 4290}
3868 4291
3869static bool 4292static bool
3870intel_dp_detect_audio(struct drm_connector *connector) 4293intel_dp_detect_audio(struct drm_connector *connector)
3871{ 4294{
3872 struct intel_dp *intel_dp = intel_attached_dp(connector);
3873 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3874 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3875 struct drm_device *dev = connector->dev;
3876 struct drm_i915_private *dev_priv = dev->dev_private;
3877 enum intel_display_power_domain power_domain;
3878 struct edid *edid;
3879 bool has_audio = false; 4295 bool has_audio = false;
4296 struct edid *edid;
3880 4297
3881 power_domain = intel_display_port_power_domain(intel_encoder); 4298 edid = to_intel_connector(connector)->detect_edid;
3882 intel_display_power_get(dev_priv, power_domain); 4299 if (edid)
3883
3884 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3885 if (edid) {
3886 has_audio = drm_detect_monitor_audio(edid); 4300 has_audio = drm_detect_monitor_audio(edid);
3887 kfree(edid);
3888 }
3889
3890 intel_display_power_put(dev_priv, power_domain);
3891 4301
3892 return has_audio; 4302 return has_audio;
3893} 4303}
@@ -3985,6 +4395,8 @@ intel_dp_connector_destroy(struct drm_connector *connector)
3985{ 4395{
3986 struct intel_connector *intel_connector = to_intel_connector(connector); 4396 struct intel_connector *intel_connector = to_intel_connector(connector);
3987 4397
4398 intel_dp_unset_edid(intel_attached_dp(connector));
4399
3988 if (!IS_ERR_OR_NULL(intel_connector->edid)) 4400 if (!IS_ERR_OR_NULL(intel_connector->edid))
3989 kfree(intel_connector->edid); 4401 kfree(intel_connector->edid);
3990 4402
@@ -4001,16 +4413,20 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4001{ 4413{
4002 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 4414 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4003 struct intel_dp *intel_dp = &intel_dig_port->dp; 4415 struct intel_dp *intel_dp = &intel_dig_port->dp;
4004 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4005 4416
4006 drm_dp_aux_unregister(&intel_dp->aux); 4417 drm_dp_aux_unregister(&intel_dp->aux);
4007 intel_dp_mst_encoder_cleanup(intel_dig_port); 4418 intel_dp_mst_encoder_cleanup(intel_dig_port);
4008 drm_encoder_cleanup(encoder); 4419 drm_encoder_cleanup(encoder);
4009 if (is_edp(intel_dp)) { 4420 if (is_edp(intel_dp)) {
4010 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4421 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4011 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4422 /*
4423 * vdd might still be enabled do to the delayed vdd off.
4424 * Make sure vdd is actually turned off here.
4425 */
4426 pps_lock(intel_dp);
4012 edp_panel_vdd_off_sync(intel_dp); 4427 edp_panel_vdd_off_sync(intel_dp);
4013 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4428 pps_unlock(intel_dp);
4429
4014 if (intel_dp->edp_notifier.notifier_call) { 4430 if (intel_dp->edp_notifier.notifier_call) {
4015 unregister_reboot_notifier(&intel_dp->edp_notifier); 4431 unregister_reboot_notifier(&intel_dp->edp_notifier);
4016 intel_dp->edp_notifier.notifier_call = NULL; 4432 intel_dp->edp_notifier.notifier_call = NULL;
@@ -4026,7 +4442,13 @@ static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4026 if (!is_edp(intel_dp)) 4442 if (!is_edp(intel_dp))
4027 return; 4443 return;
4028 4444
4445 /*
4446 * vdd might still be enabled do to the delayed vdd off.
4447 * Make sure vdd is actually turned off here.
4448 */
4449 pps_lock(intel_dp);
4029 edp_panel_vdd_off_sync(intel_dp); 4450 edp_panel_vdd_off_sync(intel_dp);
4451 pps_unlock(intel_dp);
4030} 4452}
4031 4453
4032static void intel_dp_encoder_reset(struct drm_encoder *encoder) 4454static void intel_dp_encoder_reset(struct drm_encoder *encoder)
@@ -4037,6 +4459,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4037static const struct drm_connector_funcs intel_dp_connector_funcs = { 4459static const struct drm_connector_funcs intel_dp_connector_funcs = {
4038 .dpms = intel_connector_dpms, 4460 .dpms = intel_connector_dpms,
4039 .detect = intel_dp_detect, 4461 .detect = intel_dp_detect,
4462 .force = intel_dp_force,
4040 .fill_modes = drm_helper_probe_single_connector_modes, 4463 .fill_modes = drm_helper_probe_single_connector_modes,
4041 .set_property = intel_dp_set_property, 4464 .set_property = intel_dp_set_property,
4042 .destroy = intel_dp_connector_destroy, 4465 .destroy = intel_dp_connector_destroy,
@@ -4213,6 +4636,8 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4213 u32 pp_on, pp_off, pp_div, pp; 4636 u32 pp_on, pp_off, pp_div, pp;
4214 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 4637 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4215 4638
4639 lockdep_assert_held(&dev_priv->pps_mutex);
4640
4216 if (HAS_PCH_SPLIT(dev)) { 4641 if (HAS_PCH_SPLIT(dev)) {
4217 pp_ctrl_reg = PCH_PP_CONTROL; 4642 pp_ctrl_reg = PCH_PP_CONTROL;
4218 pp_on_reg = PCH_PP_ON_DELAYS; 4643 pp_on_reg = PCH_PP_ON_DELAYS;
@@ -4312,6 +4737,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4312 u32 pp_on, pp_off, pp_div, port_sel = 0; 4737 u32 pp_on, pp_off, pp_div, port_sel = 0;
4313 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 4738 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4314 int pp_on_reg, pp_off_reg, pp_div_reg; 4739 int pp_on_reg, pp_off_reg, pp_div_reg;
4740 enum port port = dp_to_dig_port(intel_dp)->port;
4741
4742 lockdep_assert_held(&dev_priv->pps_mutex);
4315 4743
4316 if (HAS_PCH_SPLIT(dev)) { 4744 if (HAS_PCH_SPLIT(dev)) {
4317 pp_on_reg = PCH_PP_ON_DELAYS; 4745 pp_on_reg = PCH_PP_ON_DELAYS;
@@ -4346,12 +4774,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4346 /* Haswell doesn't have any port selection bits for the panel 4774 /* Haswell doesn't have any port selection bits for the panel
4347 * power sequencer any more. */ 4775 * power sequencer any more. */
4348 if (IS_VALLEYVIEW(dev)) { 4776 if (IS_VALLEYVIEW(dev)) {
4349 if (dp_to_dig_port(intel_dp)->port == PORT_B) 4777 port_sel = PANEL_PORT_SELECT_VLV(port);
4350 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4351 else
4352 port_sel = PANEL_PORT_SELECT_DPC_VLV;
4353 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 4778 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4354 if (dp_to_dig_port(intel_dp)->port == PORT_A) 4779 if (port == PORT_A)
4355 port_sel = PANEL_PORT_SELECT_DPA; 4780 port_sel = PANEL_PORT_SELECT_DPA;
4356 else 4781 else
4357 port_sel = PANEL_PORT_SELECT_DPD; 4782 port_sel = PANEL_PORT_SELECT_DPD;
@@ -4509,8 +4934,11 @@ void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4509 return; 4934 return;
4510 4935
4511 intel_dp = enc_to_intel_dp(&intel_encoder->base); 4936 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4937
4938 pps_lock(intel_dp);
4939
4512 if (!edp_have_panel_vdd(intel_dp)) 4940 if (!edp_have_panel_vdd(intel_dp))
4513 return; 4941 goto out;
4514 /* 4942 /*
4515 * The VDD bit needs a power domain reference, so if the bit is 4943 * The VDD bit needs a power domain reference, so if the bit is
4516 * already enabled when we boot or resume, grab this reference and 4944 * already enabled when we boot or resume, grab this reference and
@@ -4522,6 +4950,8 @@ void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4522 intel_display_power_get(dev_priv, power_domain); 4950 intel_display_power_get(dev_priv, power_domain);
4523 4951
4524 edp_panel_vdd_schedule_off(intel_dp); 4952 edp_panel_vdd_schedule_off(intel_dp);
4953 out:
4954 pps_unlock(intel_dp);
4525} 4955}
4526 4956
4527static bool intel_edp_init_connector(struct intel_dp *intel_dp, 4957static bool intel_edp_init_connector(struct intel_dp *intel_dp,
@@ -4549,7 +4979,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4549 /* Cache DPCD and EDID for edp. */ 4979 /* Cache DPCD and EDID for edp. */
4550 intel_edp_panel_vdd_on(intel_dp); 4980 intel_edp_panel_vdd_on(intel_dp);
4551 has_dpcd = intel_dp_get_dpcd(intel_dp); 4981 has_dpcd = intel_dp_get_dpcd(intel_dp);
4552 edp_panel_vdd_off(intel_dp, false); 4982 intel_edp_panel_vdd_off(intel_dp, false);
4553 4983
4554 if (has_dpcd) { 4984 if (has_dpcd) {
4555 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 4985 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
@@ -4563,7 +4993,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4563 } 4993 }
4564 4994
4565 /* We now know it's not a ghost, init power sequence regs. */ 4995 /* We now know it's not a ghost, init power sequence regs. */
4996 pps_lock(intel_dp);
4566 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); 4997 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4998 pps_unlock(intel_dp);
4567 4999
4568 mutex_lock(&dev->mode_config.mutex); 5000 mutex_lock(&dev->mode_config.mutex);
4569 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 5001 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
@@ -4607,6 +5039,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4607 } 5039 }
4608 5040
4609 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 5041 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5042 intel_connector->panel.backlight_power = intel_edp_backlight_power;
4610 intel_panel_setup_backlight(connector); 5043 intel_panel_setup_backlight(connector);
4611 5044
4612 return true; 5045 return true;
@@ -4625,6 +5058,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4625 struct edp_power_seq power_seq = { 0 }; 5058 struct edp_power_seq power_seq = { 0 };
4626 int type; 5059 int type;
4627 5060
5061 intel_dp->pps_pipe = INVALID_PIPE;
5062
4628 /* intel_dp vfuncs */ 5063 /* intel_dp vfuncs */
4629 if (IS_VALLEYVIEW(dev)) 5064 if (IS_VALLEYVIEW(dev))
4630 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 5065 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
@@ -4695,8 +5130,15 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4695 } 5130 }
4696 5131
4697 if (is_edp(intel_dp)) { 5132 if (is_edp(intel_dp)) {
4698 intel_dp_init_panel_power_timestamps(intel_dp); 5133 pps_lock(intel_dp);
4699 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 5134 if (IS_VALLEYVIEW(dev)) {
5135 vlv_initial_power_sequencer_setup(intel_dp);
5136 } else {
5137 intel_dp_init_panel_power_timestamps(intel_dp);
5138 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5139 &power_seq);
5140 }
5141 pps_unlock(intel_dp);
4700 } 5142 }
4701 5143
4702 intel_dp_aux_init(intel_dp, intel_connector); 5144 intel_dp_aux_init(intel_dp, intel_connector);
@@ -4704,7 +5146,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4704 /* init MST on ports that can support it */ 5146 /* init MST on ports that can support it */
4705 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 5147 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4706 if (port == PORT_B || port == PORT_C || port == PORT_D) { 5148 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4707 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id); 5149 intel_dp_mst_encoder_init(intel_dig_port,
5150 intel_connector->base.base.id);
4708 } 5151 }
4709 } 5152 }
4710 5153
@@ -4712,9 +5155,13 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4712 drm_dp_aux_unregister(&intel_dp->aux); 5155 drm_dp_aux_unregister(&intel_dp->aux);
4713 if (is_edp(intel_dp)) { 5156 if (is_edp(intel_dp)) {
4714 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 5157 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4715 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 5158 /*
5159 * vdd might still be enabled do to the delayed vdd off.
5160 * Make sure vdd is actually turned off here.
5161 */
5162 pps_lock(intel_dp);
4716 edp_panel_vdd_off_sync(intel_dp); 5163 edp_panel_vdd_off_sync(intel_dp);
4717 drm_modeset_unlock(&dev->mode_config.connection_mutex); 5164 pps_unlock(intel_dp);
4718 } 5165 }
4719 drm_connector_unregister(connector); 5166 drm_connector_unregister(connector);
4720 drm_connector_cleanup(connector); 5167 drm_connector_cleanup(connector);
@@ -4778,7 +5225,8 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4778 } else { 5225 } else {
4779 intel_encoder->pre_enable = g4x_pre_enable_dp; 5226 intel_encoder->pre_enable = g4x_pre_enable_dp;
4780 intel_encoder->enable = g4x_enable_dp; 5227 intel_encoder->enable = g4x_enable_dp;
4781 intel_encoder->post_disable = g4x_post_disable_dp; 5228 if (INTEL_INFO(dev)->gen >= 5)
5229 intel_encoder->post_disable = ilk_post_disable_dp;
4782 } 5230 }
4783 5231
4784 intel_dig_port->port = port; 5232 intel_dig_port->port = port;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d683a2090249..07ce04683c30 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -25,6 +25,7 @@
25#ifndef __INTEL_DRV_H__ 25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__ 26#define __INTEL_DRV_H__
27 27
28#include <linux/async.h>
28#include <linux/i2c.h> 29#include <linux/i2c.h>
29#include <linux/hdmi.h> 30#include <linux/hdmi.h>
30#include <drm/i915_drm.h> 31#include <drm/i915_drm.h>
@@ -179,6 +180,8 @@ struct intel_panel {
179 bool active_low_pwm; 180 bool active_low_pwm;
180 struct backlight_device *device; 181 struct backlight_device *device;
181 } backlight; 182 } backlight;
183
184 void (*backlight_power)(struct intel_connector *, bool enable);
182}; 185};
183 186
184struct intel_connector { 187struct intel_connector {
@@ -211,6 +214,7 @@ struct intel_connector {
211 214
212 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 215 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
213 struct edid *edid; 216 struct edid *edid;
217 struct edid *detect_edid;
214 218
215 /* since POLL and HPD connectors may use the same HPD line keep the native 219 /* since POLL and HPD connectors may use the same HPD line keep the native
216 state of connector->polled in case hotplug storm detection changes it */ 220 state of connector->polled in case hotplug storm detection changes it */
@@ -566,6 +570,12 @@ struct intel_dp {
566 570
567 struct notifier_block edp_notifier; 571 struct notifier_block edp_notifier;
568 572
573 /*
574 * Pipe whose power sequencer is currently locked into
575 * this port. Only relevant on VLV/CHV.
576 */
577 enum pipe pps_pipe;
578
569 bool use_tps3; 579 bool use_tps3;
570 bool can_mst; /* this port supports mst */ 580 bool can_mst; /* this port supports mst */
571 bool is_mst; 581 bool is_mst;
@@ -664,6 +674,10 @@ struct intel_unpin_work {
664#define INTEL_FLIP_COMPLETE 2 674#define INTEL_FLIP_COMPLETE 2
665 u32 flip_count; 675 u32 flip_count;
666 u32 gtt_offset; 676 u32 gtt_offset;
677 struct intel_engine_cs *flip_queued_ring;
678 u32 flip_queued_seqno;
679 int flip_queued_vblank;
680 int flip_ready_vblank;
667 bool enable_stall_check; 681 bool enable_stall_check;
668}; 682};
669 683
@@ -828,7 +842,6 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
828enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 842enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
829 enum pipe pipe); 843 enum pipe pipe);
830void intel_wait_for_vblank(struct drm_device *dev, int pipe); 844void intel_wait_for_vblank(struct drm_device *dev, int pipe);
831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
832int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 845int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
833void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 846void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
834 struct intel_digital_port *dport); 847 struct intel_digital_port *dport);
@@ -849,6 +862,7 @@ __intel_framebuffer_create(struct drm_device *dev,
849void intel_prepare_page_flip(struct drm_device *dev, int plane); 862void intel_prepare_page_flip(struct drm_device *dev, int plane);
850void intel_finish_page_flip(struct drm_device *dev, int pipe); 863void intel_finish_page_flip(struct drm_device *dev, int pipe);
851void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 864void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
865void intel_check_page_flip(struct drm_device *dev, int pipe);
852 866
853/* shared dpll functions */ 867/* shared dpll functions */
854struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); 868struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
@@ -937,6 +951,7 @@ void intel_dp_mst_suspend(struct drm_device *dev);
937void intel_dp_mst_resume(struct drm_device *dev); 951void intel_dp_mst_resume(struct drm_device *dev);
938int intel_dp_max_link_bw(struct intel_dp *intel_dp); 952int intel_dp_max_link_bw(struct intel_dp *intel_dp);
939void intel_dp_hot_plug(struct intel_encoder *intel_encoder); 953void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
954void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
940/* intel_dp_mst.c */ 955/* intel_dp_mst.c */
941int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); 956int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
942void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); 957void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
@@ -951,7 +966,7 @@ void intel_dvo_init(struct drm_device *dev);
951/* legacy fbdev emulation in intel_fbdev.c */ 966/* legacy fbdev emulation in intel_fbdev.c */
952#ifdef CONFIG_DRM_I915_FBDEV 967#ifdef CONFIG_DRM_I915_FBDEV
953extern int intel_fbdev_init(struct drm_device *dev); 968extern int intel_fbdev_init(struct drm_device *dev);
954extern void intel_fbdev_initial_config(struct drm_device *dev); 969extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
955extern void intel_fbdev_fini(struct drm_device *dev); 970extern void intel_fbdev_fini(struct drm_device *dev);
956extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); 971extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
957extern void intel_fbdev_output_poll_changed(struct drm_device *dev); 972extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
@@ -962,7 +977,7 @@ static inline int intel_fbdev_init(struct drm_device *dev)
962 return 0; 977 return 0;
963} 978}
964 979
965static inline void intel_fbdev_initial_config(struct drm_device *dev) 980static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
966{ 981{
967} 982}
968 983
@@ -1093,6 +1108,9 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1093int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); 1108int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1094void intel_flush_primary_plane(struct drm_i915_private *dev_priv, 1109void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1095 enum plane plane); 1110 enum plane plane);
1111int intel_plane_set_property(struct drm_plane *plane,
1112 struct drm_property *prop,
1113 uint64_t val);
1096int intel_plane_restore(struct drm_plane *plane); 1114int intel_plane_restore(struct drm_plane *plane);
1097void intel_plane_disable(struct drm_plane *plane); 1115void intel_plane_disable(struct drm_plane *plane);
1098int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 1116int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 56b47d2ffaf7..e40e3df33517 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -85,7 +85,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
85 { 85 {
86 .type = INTEL_DVO_CHIP_TMDS, 86 .type = INTEL_DVO_CHIP_TMDS,
87 .name = "ns2501", 87 .name = "ns2501",
88 .dvo_reg = DVOC, 88 .dvo_reg = DVOB,
89 .slave_addr = NS2501_ADDR, 89 .slave_addr = NS2501_ADDR,
90 .dev_ops = &ns2501_ops, 90 .dev_ops = &ns2501_ops,
91 } 91 }
@@ -185,12 +185,13 @@ static void intel_enable_dvo(struct intel_encoder *encoder)
185 u32 dvo_reg = intel_dvo->dev.dvo_reg; 185 u32 dvo_reg = intel_dvo->dev.dvo_reg;
186 u32 temp = I915_READ(dvo_reg); 186 u32 temp = I915_READ(dvo_reg);
187 187
188 I915_WRITE(dvo_reg, temp | DVO_ENABLE);
189 I915_READ(dvo_reg);
190 intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, 188 intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
191 &crtc->config.requested_mode, 189 &crtc->config.requested_mode,
192 &crtc->config.adjusted_mode); 190 &crtc->config.adjusted_mode);
193 191
192 I915_WRITE(dvo_reg, temp | DVO_ENABLE);
193 I915_READ(dvo_reg);
194
194 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); 195 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
195} 196}
196 197
@@ -226,10 +227,6 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode)
226 227
227 intel_crtc_update_dpms(crtc); 228 intel_crtc_update_dpms(crtc);
228 229
229 intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
230 &config->requested_mode,
231 &config->adjusted_mode);
232
233 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); 230 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
234 } else { 231 } else {
235 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); 232 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index cf052a39558d..9b584f3fbb99 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -24,6 +24,7 @@
24 * David Airlie 24 * David Airlie
25 */ 25 */
26 26
27#include <linux/async.h>
27#include <linux/module.h> 28#include <linux/module.h>
28#include <linux/kernel.h> 29#include <linux/kernel.h>
29#include <linux/console.h> 30#include <linux/console.h>
@@ -332,24 +333,6 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
332 int num_connectors_enabled = 0; 333 int num_connectors_enabled = 0;
333 int num_connectors_detected = 0; 334 int num_connectors_detected = 0;
334 335
335 /*
336 * If the user specified any force options, just bail here
337 * and use that config.
338 */
339 for (i = 0; i < fb_helper->connector_count; i++) {
340 struct drm_fb_helper_connector *fb_conn;
341 struct drm_connector *connector;
342
343 fb_conn = fb_helper->connector_info[i];
344 connector = fb_conn->connector;
345
346 if (!enabled[i])
347 continue;
348
349 if (connector->force != DRM_FORCE_UNSPECIFIED)
350 return false;
351 }
352
353 save_enabled = kcalloc(dev->mode_config.num_connector, sizeof(bool), 336 save_enabled = kcalloc(dev->mode_config.num_connector, sizeof(bool),
354 GFP_KERNEL); 337 GFP_KERNEL);
355 if (!save_enabled) 338 if (!save_enabled)
@@ -375,8 +358,18 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
375 continue; 358 continue;
376 } 359 }
377 360
361 if (connector->force == DRM_FORCE_OFF) {
362 DRM_DEBUG_KMS("connector %s is disabled by user, skipping\n",
363 connector->name);
364 enabled[i] = false;
365 continue;
366 }
367
378 encoder = connector->encoder; 368 encoder = connector->encoder;
379 if (!encoder || WARN_ON(!encoder->crtc)) { 369 if (!encoder || WARN_ON(!encoder->crtc)) {
370 if (connector->force > DRM_FORCE_OFF)
371 goto bail;
372
380 DRM_DEBUG_KMS("connector %s has no encoder or crtc, skipping\n", 373 DRM_DEBUG_KMS("connector %s has no encoder or crtc, skipping\n",
381 connector->name); 374 connector->name);
382 enabled[i] = false; 375 enabled[i] = false;
@@ -395,8 +388,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
395 for (j = 0; j < fb_helper->connector_count; j++) { 388 for (j = 0; j < fb_helper->connector_count; j++) {
396 if (crtcs[j] == new_crtc) { 389 if (crtcs[j] == new_crtc) {
397 DRM_DEBUG_KMS("fallback: cloned configuration\n"); 390 DRM_DEBUG_KMS("fallback: cloned configuration\n");
398 fallback = true; 391 goto bail;
399 goto out;
400 } 392 }
401 } 393 }
402 394
@@ -467,8 +459,8 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
467 fallback = true; 459 fallback = true;
468 } 460 }
469 461
470out:
471 if (fallback) { 462 if (fallback) {
463bail:
472 DRM_DEBUG_KMS("Not using firmware configuration\n"); 464 DRM_DEBUG_KMS("Not using firmware configuration\n");
473 memcpy(enabled, save_enabled, dev->mode_config.num_connector); 465 memcpy(enabled, save_enabled, dev->mode_config.num_connector);
474 kfree(save_enabled); 466 kfree(save_enabled);
@@ -679,9 +671,9 @@ int intel_fbdev_init(struct drm_device *dev)
679 return 0; 671 return 0;
680} 672}
681 673
682void intel_fbdev_initial_config(struct drm_device *dev) 674void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
683{ 675{
684 struct drm_i915_private *dev_priv = dev->dev_private; 676 struct drm_i915_private *dev_priv = data;
685 struct intel_fbdev *ifbdev = dev_priv->fbdev; 677 struct intel_fbdev *ifbdev = dev_priv->fbdev;
686 678
687 /* Due to peculiar init order wrt to hpd handling this is separate. */ 679 /* Due to peculiar init order wrt to hpd handling this is separate. */
@@ -696,6 +688,7 @@ void intel_fbdev_fini(struct drm_device *dev)
696 688
697 flush_work(&dev_priv->fbdev_suspend_work); 689 flush_work(&dev_priv->fbdev_suspend_work);
698 690
691 async_synchronize_full();
699 intel_fbdev_destroy(dev, dev_priv->fbdev); 692 intel_fbdev_destroy(dev, dev_priv->fbdev);
700 kfree(dev_priv->fbdev); 693 kfree(dev_priv->fbdev);
701 dev_priv->fbdev = NULL; 694 dev_priv->fbdev = NULL;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 96957683032e..c5861736b4b0 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -971,104 +971,117 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
971 return true; 971 return true;
972} 972}
973 973
974static enum drm_connector_status 974static void
975intel_hdmi_detect(struct drm_connector *connector, bool force) 975intel_hdmi_unset_edid(struct drm_connector *connector)
976{ 976{
977 struct drm_device *dev = connector->dev;
978 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 977 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
979 struct intel_digital_port *intel_dig_port =
980 hdmi_to_dig_port(intel_hdmi);
981 struct intel_encoder *intel_encoder = &intel_dig_port->base;
982 struct drm_i915_private *dev_priv = dev->dev_private;
983 struct edid *edid;
984 enum intel_display_power_domain power_domain;
985 enum drm_connector_status status = connector_status_disconnected;
986 978
987 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 979 intel_hdmi->has_hdmi_sink = false;
988 connector->base.id, connector->name); 980 intel_hdmi->has_audio = false;
981 intel_hdmi->rgb_quant_range_selectable = false;
982
983 kfree(to_intel_connector(connector)->detect_edid);
984 to_intel_connector(connector)->detect_edid = NULL;
985}
986
987static bool
988intel_hdmi_set_edid(struct drm_connector *connector)
989{
990 struct drm_i915_private *dev_priv = to_i915(connector->dev);
991 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
992 struct intel_encoder *intel_encoder =
993 &hdmi_to_dig_port(intel_hdmi)->base;
994 enum intel_display_power_domain power_domain;
995 struct edid *edid;
996 bool connected = false;
989 997
990 power_domain = intel_display_port_power_domain(intel_encoder); 998 power_domain = intel_display_port_power_domain(intel_encoder);
991 intel_display_power_get(dev_priv, power_domain); 999 intel_display_power_get(dev_priv, power_domain);
992 1000
993 intel_hdmi->has_hdmi_sink = false;
994 intel_hdmi->has_audio = false;
995 intel_hdmi->rgb_quant_range_selectable = false;
996 edid = drm_get_edid(connector, 1001 edid = drm_get_edid(connector,
997 intel_gmbus_get_adapter(dev_priv, 1002 intel_gmbus_get_adapter(dev_priv,
998 intel_hdmi->ddc_bus)); 1003 intel_hdmi->ddc_bus));
999 1004
1000 if (edid) { 1005 intel_display_power_put(dev_priv, power_domain);
1001 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1006
1002 status = connector_status_connected; 1007 to_intel_connector(connector)->detect_edid = edid;
1003 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 1008 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1004 intel_hdmi->has_hdmi_sink = 1009 intel_hdmi->rgb_quant_range_selectable =
1005 drm_detect_hdmi_monitor(edid); 1010 drm_rgb_quant_range_selectable(edid);
1006 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1007 intel_hdmi->rgb_quant_range_selectable =
1008 drm_rgb_quant_range_selectable(edid);
1009 }
1010 kfree(edid);
1011 }
1012 1011
1013 if (status == connector_status_connected) { 1012 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1014 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 1013 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1015 intel_hdmi->has_audio = 1014 intel_hdmi->has_audio =
1016 (intel_hdmi->force_audio == HDMI_AUDIO_ON); 1015 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1017 intel_encoder->type = INTEL_OUTPUT_HDMI; 1016
1017 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1018 intel_hdmi->has_hdmi_sink =
1019 drm_detect_hdmi_monitor(edid);
1020
1021 connected = true;
1018 } 1022 }
1019 1023
1020 intel_display_power_put(dev_priv, power_domain); 1024 return connected;
1025}
1026
1027static enum drm_connector_status
1028intel_hdmi_detect(struct drm_connector *connector, bool force)
1029{
1030 enum drm_connector_status status;
1031
1032 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1033 connector->base.id, connector->name);
1034
1035 intel_hdmi_unset_edid(connector);
1036
1037 if (intel_hdmi_set_edid(connector)) {
1038 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1039
1040 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1041 status = connector_status_connected;
1042 } else
1043 status = connector_status_disconnected;
1021 1044
1022 return status; 1045 return status;
1023} 1046}
1024 1047
1025static int intel_hdmi_get_modes(struct drm_connector *connector) 1048static void
1049intel_hdmi_force(struct drm_connector *connector)
1026{ 1050{
1027 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 1051 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1028 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1029 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1030 enum intel_display_power_domain power_domain;
1031 int ret;
1032 1052
1033 /* We should parse the EDID data and find out if it's an HDMI sink so 1053 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1034 * we can send audio to it. 1054 connector->base.id, connector->name);
1035 */
1036 1055
1037 power_domain = intel_display_port_power_domain(intel_encoder); 1056 intel_hdmi_unset_edid(connector);
1038 intel_display_power_get(dev_priv, power_domain);
1039 1057
1040 ret = intel_ddc_get_modes(connector, 1058 if (connector->status != connector_status_connected)
1041 intel_gmbus_get_adapter(dev_priv, 1059 return;
1042 intel_hdmi->ddc_bus));
1043 1060
1044 intel_display_power_put(dev_priv, power_domain); 1061 intel_hdmi_set_edid(connector);
1062 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1063}
1045 1064
1046 return ret; 1065static int intel_hdmi_get_modes(struct drm_connector *connector)
1066{
1067 struct edid *edid;
1068
1069 edid = to_intel_connector(connector)->detect_edid;
1070 if (edid == NULL)
1071 return 0;
1072
1073 return intel_connector_update_modes(connector, edid);
1047} 1074}
1048 1075
1049static bool 1076static bool
1050intel_hdmi_detect_audio(struct drm_connector *connector) 1077intel_hdmi_detect_audio(struct drm_connector *connector)
1051{ 1078{
1052 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
1053 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1054 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1055 enum intel_display_power_domain power_domain;
1056 struct edid *edid;
1057 bool has_audio = false; 1079 bool has_audio = false;
1080 struct edid *edid;
1058 1081
1059 power_domain = intel_display_port_power_domain(intel_encoder); 1082 edid = to_intel_connector(connector)->detect_edid;
1060 intel_display_power_get(dev_priv, power_domain); 1083 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1061 1084 has_audio = drm_detect_monitor_audio(edid);
1062 edid = drm_get_edid(connector,
1063 intel_gmbus_get_adapter(dev_priv,
1064 intel_hdmi->ddc_bus));
1065 if (edid) {
1066 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1067 has_audio = drm_detect_monitor_audio(edid);
1068 kfree(edid);
1069 }
1070
1071 intel_display_power_put(dev_priv, power_domain);
1072 1085
1073 return has_audio; 1086 return has_audio;
1074} 1087}
@@ -1488,6 +1501,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1488 1501
1489static void intel_hdmi_destroy(struct drm_connector *connector) 1502static void intel_hdmi_destroy(struct drm_connector *connector)
1490{ 1503{
1504 intel_hdmi_unset_edid(connector);
1491 drm_connector_cleanup(connector); 1505 drm_connector_cleanup(connector);
1492 kfree(connector); 1506 kfree(connector);
1493} 1507}
@@ -1495,6 +1509,7 @@ static void intel_hdmi_destroy(struct drm_connector *connector)
1495static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 1509static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1496 .dpms = intel_connector_dpms, 1510 .dpms = intel_connector_dpms,
1497 .detect = intel_hdmi_detect, 1511 .detect = intel_hdmi_detect,
1512 .force = intel_hdmi_force,
1498 .fill_modes = drm_helper_probe_single_connector_modes, 1513 .fill_modes = drm_helper_probe_single_connector_modes,
1499 .set_property = intel_hdmi_set_property, 1514 .set_property = intel_hdmi_set_property,
1500 .destroy = intel_hdmi_destroy, 1515 .destroy = intel_hdmi_destroy,
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c096b9b7f22a..bd1b28d99920 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1217,8 +1217,6 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
1217static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) 1217static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring)
1218{ 1218{
1219 int ret; 1219 int ret;
1220 struct intel_context *dctx = ring->default_context;
1221 struct drm_i915_gem_object *dctx_obj;
1222 1220
1223 /* Intentionally left blank. */ 1221 /* Intentionally left blank. */
1224 ring->buffer = NULL; 1222 ring->buffer = NULL;
@@ -1232,18 +1230,6 @@ static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin
1232 spin_lock_init(&ring->execlist_lock); 1230 spin_lock_init(&ring->execlist_lock);
1233 ring->next_context_status_buffer = 0; 1231 ring->next_context_status_buffer = 0;
1234 1232
1235 ret = intel_lr_context_deferred_create(dctx, ring);
1236 if (ret)
1237 return ret;
1238
1239 /* The status page is offset 0 from the context object in LRCs. */
1240 dctx_obj = dctx->engine[ring->id].state;
1241 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj);
1242 ring->status_page.page_addr = kmap(sg_page(dctx_obj->pages->sgl));
1243 if (ring->status_page.page_addr == NULL)
1244 return -ENOMEM;
1245 ring->status_page.obj = dctx_obj;
1246
1247 ret = i915_cmd_parser_init_ring(ring); 1233 ret = i915_cmd_parser_init_ring(ring);
1248 if (ret) 1234 if (ret)
1249 return ret; 1235 return ret;
@@ -1254,7 +1240,9 @@ static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin
1254 return ret; 1240 return ret;
1255 } 1241 }
1256 1242
1257 return 0; 1243 ret = intel_lr_context_deferred_create(ring->default_context, ring);
1244
1245 return ret;
1258} 1246}
1259 1247
1260static int logical_render_ring_init(struct drm_device *dev) 1248static int logical_render_ring_init(struct drm_device *dev)
@@ -1448,16 +1436,53 @@ cleanup_render_ring:
1448 return ret; 1436 return ret;
1449} 1437}
1450 1438
1439int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1440 struct intel_context *ctx)
1441{
1442 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
1443 struct render_state so;
1444 struct drm_i915_file_private *file_priv = ctx->file_priv;
1445 struct drm_file *file = file_priv ? file_priv->file : NULL;
1446 int ret;
1447
1448 ret = i915_gem_render_state_prepare(ring, &so);
1449 if (ret)
1450 return ret;
1451
1452 if (so.rodata == NULL)
1453 return 0;
1454
1455 ret = ring->emit_bb_start(ringbuf,
1456 so.ggtt_offset,
1457 I915_DISPATCH_SECURE);
1458 if (ret)
1459 goto out;
1460
1461 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
1462
1463 ret = __i915_add_request(ring, file, so.obj, NULL);
1464 /* intel_logical_ring_add_request moves object to inactive if it
1465 * fails */
1466out:
1467 i915_gem_render_state_fini(&so);
1468 return ret;
1469}
1470
1451static int 1471static int
1452populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, 1472populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
1453 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) 1473 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
1454{ 1474{
1475 struct drm_device *dev = ring->dev;
1476 struct drm_i915_private *dev_priv = dev->dev_private;
1455 struct drm_i915_gem_object *ring_obj = ringbuf->obj; 1477 struct drm_i915_gem_object *ring_obj = ringbuf->obj;
1456 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; 1478 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1457 struct page *page; 1479 struct page *page;
1458 uint32_t *reg_state; 1480 uint32_t *reg_state;
1459 int ret; 1481 int ret;
1460 1482
1483 if (!ppgtt)
1484 ppgtt = dev_priv->mm.aliasing_ppgtt;
1485
1461 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); 1486 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1462 if (ret) { 1487 if (ret) {
1463 DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); 1488 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
@@ -1687,6 +1712,29 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
1687 ctx->engine[ring->id].ringbuf = ringbuf; 1712 ctx->engine[ring->id].ringbuf = ringbuf;
1688 ctx->engine[ring->id].state = ctx_obj; 1713 ctx->engine[ring->id].state = ctx_obj;
1689 1714
1715 if (ctx == ring->default_context) {
1716 /* The status page is offset 0 from the default context object
1717 * in LRC mode. */
1718 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(ctx_obj);
1719 ring->status_page.page_addr =
1720 kmap(sg_page(ctx_obj->pages->sgl));
1721 if (ring->status_page.page_addr == NULL)
1722 return -ENOMEM;
1723 ring->status_page.obj = ctx_obj;
1724 }
1725
1726 if (ring->id == RCS && !ctx->rcs_initialized) {
1727 ret = intel_lr_context_render_state_init(ring, ctx);
1728 if (ret) {
1729 DRM_ERROR("Init render state failed: %d\n", ret);
1730 ctx->engine[ring->id].ringbuf = NULL;
1731 ctx->engine[ring->id].state = NULL;
1732 intel_destroy_ringbuffer_obj(ringbuf);
1733 goto error;
1734 }
1735 ctx->rcs_initialized = true;
1736 }
1737
1690 return 0; 1738 return 0;
1691 1739
1692error: 1740error:
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 991d4499fb03..33c3b4bf28c5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -62,6 +62,8 @@ static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
62int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords); 62int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords);
63 63
64/* Logical Ring Contexts */ 64/* Logical Ring Contexts */
65int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
66 struct intel_context *ctx);
65void intel_lr_context_free(struct intel_context *ctx); 67void intel_lr_context_free(struct intel_context *ctx);
66int intel_lr_context_deferred_create(struct intel_context *ctx, 68int intel_lr_context_deferred_create(struct intel_context *ctx,
67 struct intel_engine_cs *ring); 69 struct intel_engine_cs *ring);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 8e374449c6b5..18784470a760 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -751,6 +751,8 @@ void intel_panel_disable_backlight(struct intel_connector *connector)
751 751
752 spin_lock_irqsave(&dev_priv->backlight_lock, flags); 752 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
753 753
754 if (panel->backlight.device)
755 panel->backlight.device->props.power = FB_BLANK_POWERDOWN;
754 panel->backlight.enabled = false; 756 panel->backlight.enabled = false;
755 dev_priv->display.disable_backlight(connector); 757 dev_priv->display.disable_backlight(connector);
756 758
@@ -957,6 +959,8 @@ void intel_panel_enable_backlight(struct intel_connector *connector)
957 959
958 dev_priv->display.enable_backlight(connector); 960 dev_priv->display.enable_backlight(connector);
959 panel->backlight.enabled = true; 961 panel->backlight.enabled = true;
962 if (panel->backlight.device)
963 panel->backlight.device->props.power = FB_BLANK_UNBLANK;
960 964
961 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); 965 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
962} 966}
@@ -965,6 +969,7 @@ void intel_panel_enable_backlight(struct intel_connector *connector)
965static int intel_backlight_device_update_status(struct backlight_device *bd) 969static int intel_backlight_device_update_status(struct backlight_device *bd)
966{ 970{
967 struct intel_connector *connector = bl_get_data(bd); 971 struct intel_connector *connector = bl_get_data(bd);
972 struct intel_panel *panel = &connector->panel;
968 struct drm_device *dev = connector->base.dev; 973 struct drm_device *dev = connector->base.dev;
969 974
970 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 975 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
@@ -972,6 +977,23 @@ static int intel_backlight_device_update_status(struct backlight_device *bd)
972 bd->props.brightness, bd->props.max_brightness); 977 bd->props.brightness, bd->props.max_brightness);
973 intel_panel_set_backlight(connector, bd->props.brightness, 978 intel_panel_set_backlight(connector, bd->props.brightness,
974 bd->props.max_brightness); 979 bd->props.max_brightness);
980
981 /*
982 * Allow flipping bl_power as a sub-state of enabled. Sadly the
983 * backlight class device does not make it easy to to differentiate
984 * between callbacks for brightness and bl_power, so our backlight_power
985 * callback needs to take this into account.
986 */
987 if (panel->backlight.enabled) {
988 if (panel->backlight_power) {
989 bool enable = bd->props.power == FB_BLANK_UNBLANK &&
990 bd->props.brightness != 0;
991 panel->backlight_power(connector, enable);
992 }
993 } else {
994 bd->props.power = FB_BLANK_POWERDOWN;
995 }
996
975 drm_modeset_unlock(&dev->mode_config.connection_mutex); 997 drm_modeset_unlock(&dev->mode_config.connection_mutex);
976 return 0; 998 return 0;
977} 999}
@@ -1023,6 +1045,11 @@ static int intel_backlight_device_register(struct intel_connector *connector)
1023 panel->backlight.level, 1045 panel->backlight.level,
1024 props.max_brightness); 1046 props.max_brightness);
1025 1047
1048 if (panel->backlight.enabled)
1049 props.power = FB_BLANK_UNBLANK;
1050 else
1051 props.power = FB_BLANK_POWERDOWN;
1052
1026 /* 1053 /*
1027 * Note: using the same name independent of the connector prevents 1054 * Note: using the same name independent of the connector prevents
1028 * registration of multiple backlight devices in the driver. 1055 * registration of multiple backlight devices in the driver.
@@ -1203,7 +1230,7 @@ static int vlv_setup_backlight(struct intel_connector *connector)
1203 enum pipe pipe; 1230 enum pipe pipe;
1204 u32 ctl, ctl2, val; 1231 u32 ctl, ctl2, val;
1205 1232
1206 for_each_pipe(pipe) { 1233 for_each_pipe(dev_priv, pipe) {
1207 u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe)); 1234 u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe));
1208 1235
1209 /* Skip if the modulation freq is already set */ 1236 /* Skip if the modulation freq is already set */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c8f744c418f0..45f71e6dc544 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -345,6 +345,16 @@ bool intel_fbc_enabled(struct drm_device *dev)
345 return dev_priv->display.fbc_enabled(dev); 345 return dev_priv->display.fbc_enabled(dev);
346} 346}
347 347
348void gen8_fbc_sw_flush(struct drm_device *dev, u32 value)
349{
350 struct drm_i915_private *dev_priv = dev->dev_private;
351
352 if (!IS_GEN8(dev))
353 return;
354
355 I915_WRITE(MSG_FBC_REND_STATE, value);
356}
357
348static void intel_fbc_work_fn(struct work_struct *__work) 358static void intel_fbc_work_fn(struct work_struct *__work)
349{ 359{
350 struct intel_fbc_work *work = 360 struct intel_fbc_work *work =
@@ -581,6 +591,12 @@ void intel_update_fbc(struct drm_device *dev)
581 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); 591 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
582 goto out_disable; 592 goto out_disable;
583 } 593 }
594 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
595 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
596 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
597 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
598 goto out_disable;
599 }
584 600
585 /* If the kernel debugger is active, always disable compression */ 601 /* If the kernel debugger is active, always disable compression */
586 if (in_dbg_master()) 602 if (in_dbg_master())
@@ -856,7 +872,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
856 * A value of 5us seems to be a good balance; safe for very low end 872 * A value of 5us seems to be a good balance; safe for very low end
857 * platforms but not overly aggressive on lower latency configs. 873 * platforms but not overly aggressive on lower latency configs.
858 */ 874 */
859static const int latency_ns = 5000; 875static const int pessimal_latency_ns = 5000;
860 876
861static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 877static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
862{ 878{
@@ -985,13 +1001,20 @@ static const struct intel_watermark_params i915_wm_info = {
985 .guard_size = 2, 1001 .guard_size = 2,
986 .cacheline_size = I915_FIFO_LINE_SIZE, 1002 .cacheline_size = I915_FIFO_LINE_SIZE,
987}; 1003};
988static const struct intel_watermark_params i830_wm_info = { 1004static const struct intel_watermark_params i830_a_wm_info = {
989 .fifo_size = I855GM_FIFO_SIZE, 1005 .fifo_size = I855GM_FIFO_SIZE,
990 .max_wm = I915_MAX_WM, 1006 .max_wm = I915_MAX_WM,
991 .default_wm = 1, 1007 .default_wm = 1,
992 .guard_size = 2, 1008 .guard_size = 2,
993 .cacheline_size = I830_FIFO_LINE_SIZE, 1009 .cacheline_size = I830_FIFO_LINE_SIZE,
994}; 1010};
1011static const struct intel_watermark_params i830_bc_wm_info = {
1012 .fifo_size = I855GM_FIFO_SIZE,
1013 .max_wm = I915_MAX_WM/2,
1014 .default_wm = 1,
1015 .guard_size = 2,
1016 .cacheline_size = I830_FIFO_LINE_SIZE,
1017};
995static const struct intel_watermark_params i845_wm_info = { 1018static const struct intel_watermark_params i845_wm_info = {
996 .fifo_size = I830_FIFO_SIZE, 1019 .fifo_size = I830_FIFO_SIZE,
997 .max_wm = I915_MAX_WM, 1020 .max_wm = I915_MAX_WM,
@@ -1364,14 +1387,14 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
1364 vlv_update_drain_latency(crtc); 1387 vlv_update_drain_latency(crtc);
1365 1388
1366 if (g4x_compute_wm0(dev, PIPE_A, 1389 if (g4x_compute_wm0(dev, PIPE_A,
1367 &valleyview_wm_info, latency_ns, 1390 &valleyview_wm_info, pessimal_latency_ns,
1368 &valleyview_cursor_wm_info, latency_ns, 1391 &valleyview_cursor_wm_info, pessimal_latency_ns,
1369 &planea_wm, &cursora_wm)) 1392 &planea_wm, &cursora_wm))
1370 enabled |= 1 << PIPE_A; 1393 enabled |= 1 << PIPE_A;
1371 1394
1372 if (g4x_compute_wm0(dev, PIPE_B, 1395 if (g4x_compute_wm0(dev, PIPE_B,
1373 &valleyview_wm_info, latency_ns, 1396 &valleyview_wm_info, pessimal_latency_ns,
1374 &valleyview_cursor_wm_info, latency_ns, 1397 &valleyview_cursor_wm_info, pessimal_latency_ns,
1375 &planeb_wm, &cursorb_wm)) 1398 &planeb_wm, &cursorb_wm))
1376 enabled |= 1 << PIPE_B; 1399 enabled |= 1 << PIPE_B;
1377 1400
@@ -1430,20 +1453,20 @@ static void cherryview_update_wm(struct drm_crtc *crtc)
1430 vlv_update_drain_latency(crtc); 1453 vlv_update_drain_latency(crtc);
1431 1454
1432 if (g4x_compute_wm0(dev, PIPE_A, 1455 if (g4x_compute_wm0(dev, PIPE_A,
1433 &valleyview_wm_info, latency_ns, 1456 &valleyview_wm_info, pessimal_latency_ns,
1434 &valleyview_cursor_wm_info, latency_ns, 1457 &valleyview_cursor_wm_info, pessimal_latency_ns,
1435 &planea_wm, &cursora_wm)) 1458 &planea_wm, &cursora_wm))
1436 enabled |= 1 << PIPE_A; 1459 enabled |= 1 << PIPE_A;
1437 1460
1438 if (g4x_compute_wm0(dev, PIPE_B, 1461 if (g4x_compute_wm0(dev, PIPE_B,
1439 &valleyview_wm_info, latency_ns, 1462 &valleyview_wm_info, pessimal_latency_ns,
1440 &valleyview_cursor_wm_info, latency_ns, 1463 &valleyview_cursor_wm_info, pessimal_latency_ns,
1441 &planeb_wm, &cursorb_wm)) 1464 &planeb_wm, &cursorb_wm))
1442 enabled |= 1 << PIPE_B; 1465 enabled |= 1 << PIPE_B;
1443 1466
1444 if (g4x_compute_wm0(dev, PIPE_C, 1467 if (g4x_compute_wm0(dev, PIPE_C,
1445 &valleyview_wm_info, latency_ns, 1468 &valleyview_wm_info, pessimal_latency_ns,
1446 &valleyview_cursor_wm_info, latency_ns, 1469 &valleyview_cursor_wm_info, pessimal_latency_ns,
1447 &planec_wm, &cursorc_wm)) 1470 &planec_wm, &cursorc_wm))
1448 enabled |= 1 << PIPE_C; 1471 enabled |= 1 << PIPE_C;
1449 1472
@@ -1536,14 +1559,14 @@ static void g4x_update_wm(struct drm_crtc *crtc)
1536 bool cxsr_enabled; 1559 bool cxsr_enabled;
1537 1560
1538 if (g4x_compute_wm0(dev, PIPE_A, 1561 if (g4x_compute_wm0(dev, PIPE_A,
1539 &g4x_wm_info, latency_ns, 1562 &g4x_wm_info, pessimal_latency_ns,
1540 &g4x_cursor_wm_info, latency_ns, 1563 &g4x_cursor_wm_info, pessimal_latency_ns,
1541 &planea_wm, &cursora_wm)) 1564 &planea_wm, &cursora_wm))
1542 enabled |= 1 << PIPE_A; 1565 enabled |= 1 << PIPE_A;
1543 1566
1544 if (g4x_compute_wm0(dev, PIPE_B, 1567 if (g4x_compute_wm0(dev, PIPE_B,
1545 &g4x_wm_info, latency_ns, 1568 &g4x_wm_info, pessimal_latency_ns,
1546 &g4x_cursor_wm_info, latency_ns, 1569 &g4x_cursor_wm_info, pessimal_latency_ns,
1547 &planeb_wm, &cursorb_wm)) 1570 &planeb_wm, &cursorb_wm))
1548 enabled |= 1 << PIPE_B; 1571 enabled |= 1 << PIPE_B;
1549 1572
@@ -1673,7 +1696,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1673 else if (!IS_GEN2(dev)) 1696 else if (!IS_GEN2(dev))
1674 wm_info = &i915_wm_info; 1697 wm_info = &i915_wm_info;
1675 else 1698 else
1676 wm_info = &i830_wm_info; 1699 wm_info = &i830_a_wm_info;
1677 1700
1678 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1701 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1679 crtc = intel_get_crtc_for_plane(dev, 0); 1702 crtc = intel_get_crtc_for_plane(dev, 0);
@@ -1686,10 +1709,16 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1686 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1709 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1687 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1710 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1688 wm_info, fifo_size, cpp, 1711 wm_info, fifo_size, cpp,
1689 latency_ns); 1712 pessimal_latency_ns);
1690 enabled = crtc; 1713 enabled = crtc;
1691 } else 1714 } else {
1692 planea_wm = fifo_size - wm_info->guard_size; 1715 planea_wm = fifo_size - wm_info->guard_size;
1716 if (planea_wm > (long)wm_info->max_wm)
1717 planea_wm = wm_info->max_wm;
1718 }
1719
1720 if (IS_GEN2(dev))
1721 wm_info = &i830_bc_wm_info;
1693 1722
1694 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1723 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1695 crtc = intel_get_crtc_for_plane(dev, 1); 1724 crtc = intel_get_crtc_for_plane(dev, 1);
@@ -1702,13 +1731,16 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1702 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1731 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1703 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1732 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1704 wm_info, fifo_size, cpp, 1733 wm_info, fifo_size, cpp,
1705 latency_ns); 1734 pessimal_latency_ns);
1706 if (enabled == NULL) 1735 if (enabled == NULL)
1707 enabled = crtc; 1736 enabled = crtc;
1708 else 1737 else
1709 enabled = NULL; 1738 enabled = NULL;
1710 } else 1739 } else {
1711 planeb_wm = fifo_size - wm_info->guard_size; 1740 planeb_wm = fifo_size - wm_info->guard_size;
1741 if (planeb_wm > (long)wm_info->max_wm)
1742 planeb_wm = wm_info->max_wm;
1743 }
1712 1744
1713 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1745 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1714 1746
@@ -1795,7 +1827,7 @@ static void i845_update_wm(struct drm_crtc *unused_crtc)
1795 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1827 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1796 &i845_wm_info, 1828 &i845_wm_info,
1797 dev_priv->display.get_fifo_size(dev, 0), 1829 dev_priv->display.get_fifo_size(dev, 0),
1798 4, latency_ns); 1830 4, pessimal_latency_ns);
1799 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1831 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1800 fwater_lo |= (3<<8) | planea_wm; 1832 fwater_lo |= (3<<8) | planea_wm;
1801 1833
@@ -2242,7 +2274,6 @@ int ilk_wm_max_level(const struct drm_device *dev)
2242 else 2274 else
2243 return 2; 2275 return 2;
2244} 2276}
2245
2246static void intel_print_wm_latency(struct drm_device *dev, 2277static void intel_print_wm_latency(struct drm_device *dev,
2247 const char *name, 2278 const char *name,
2248 const uint16_t wm[5]) 2279 const uint16_t wm[5])
@@ -2648,7 +2679,7 @@ static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2648#define WM_DIRTY_FBC (1 << 24) 2679#define WM_DIRTY_FBC (1 << 24)
2649#define WM_DIRTY_DDB (1 << 25) 2680#define WM_DIRTY_DDB (1 << 25)
2650 2681
2651static unsigned int ilk_compute_wm_dirty(struct drm_device *dev, 2682static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2652 const struct ilk_wm_values *old, 2683 const struct ilk_wm_values *old,
2653 const struct ilk_wm_values *new) 2684 const struct ilk_wm_values *new)
2654{ 2685{
@@ -2656,7 +2687,7 @@ static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2656 enum pipe pipe; 2687 enum pipe pipe;
2657 int wm_lp; 2688 int wm_lp;
2658 2689
2659 for_each_pipe(pipe) { 2690 for_each_pipe(dev_priv, pipe) {
2660 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { 2691 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2661 dirty |= WM_DIRTY_LINETIME(pipe); 2692 dirty |= WM_DIRTY_LINETIME(pipe);
2662 /* Must disable LP1+ watermarks too */ 2693 /* Must disable LP1+ watermarks too */
@@ -2742,7 +2773,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2742 unsigned int dirty; 2773 unsigned int dirty;
2743 uint32_t val; 2774 uint32_t val;
2744 2775
2745 dirty = ilk_compute_wm_dirty(dev, previous, results); 2776 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2746 if (!dirty) 2777 if (!dirty)
2747 return; 2778 return;
2748 2779
@@ -3211,6 +3242,9 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3211{ 3242{
3212 int new_power; 3243 int new_power;
3213 3244
3245 if (dev_priv->rps.is_bdw_sw_turbo)
3246 return;
3247
3214 new_power = dev_priv->rps.power; 3248 new_power = dev_priv->rps.power;
3215 switch (dev_priv->rps.power) { 3249 switch (dev_priv->rps.power) {
3216 case LOW_POWER: 3250 case LOW_POWER:
@@ -3418,8 +3452,11 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
3418 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 3452 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3419 else if (IS_VALLEYVIEW(dev)) 3453 else if (IS_VALLEYVIEW(dev))
3420 vlv_set_rps_idle(dev_priv); 3454 vlv_set_rps_idle(dev_priv);
3421 else 3455 else if (!dev_priv->rps.is_bdw_sw_turbo
3456 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3422 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 3457 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3458 }
3459
3423 dev_priv->rps.last_adj = 0; 3460 dev_priv->rps.last_adj = 0;
3424 } 3461 }
3425 mutex_unlock(&dev_priv->rps.hw_lock); 3462 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -3433,8 +3470,11 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv)
3433 if (dev_priv->rps.enabled) { 3470 if (dev_priv->rps.enabled) {
3434 if (IS_VALLEYVIEW(dev)) 3471 if (IS_VALLEYVIEW(dev))
3435 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); 3472 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3436 else 3473 else if (!dev_priv->rps.is_bdw_sw_turbo
3474 || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){
3437 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); 3475 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3476 }
3477
3438 dev_priv->rps.last_adj = 0; 3478 dev_priv->rps.last_adj = 0;
3439 } 3479 }
3440 mutex_unlock(&dev_priv->rps.hw_lock); 3480 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -3453,6 +3493,10 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
3453 dev_priv->rps.cur_freq, 3493 dev_priv->rps.cur_freq,
3454 vlv_gpu_freq(dev_priv, val), val); 3494 vlv_gpu_freq(dev_priv, val), val);
3455 3495
3496 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3497 "Odd GPU freq value\n"))
3498 val &= ~1;
3499
3456 if (val != dev_priv->rps.cur_freq) 3500 if (val != dev_priv->rps.cur_freq)
3457 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); 3501 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3458 3502
@@ -3465,21 +3509,26 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
3465static void gen8_disable_rps_interrupts(struct drm_device *dev) 3509static void gen8_disable_rps_interrupts(struct drm_device *dev)
3466{ 3510{
3467 struct drm_i915_private *dev_priv = dev->dev_private; 3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 if (IS_BROADWELL(dev) && dev_priv->rps.is_bdw_sw_turbo){
3513 if (atomic_read(&dev_priv->rps.sw_turbo.flip_received))
3514 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3515 dev_priv-> rps.is_bdw_sw_turbo = false;
3516 } else {
3517 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3518 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3519 ~dev_priv->pm_rps_events);
3520 /* Complete PM interrupt masking here doesn't race with the rps work
3521 * item again unmasking PM interrupts because that is using a different
3522 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3523 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3524 * gen8_enable_rps will clean up. */
3468 3525
3469 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP); 3526 spin_lock_irq(&dev_priv->irq_lock);
3470 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) & 3527 dev_priv->rps.pm_iir = 0;
3471 ~dev_priv->pm_rps_events); 3528 spin_unlock_irq(&dev_priv->irq_lock);
3472 /* Complete PM interrupt masking here doesn't race with the rps work
3473 * item again unmasking PM interrupts because that is using a different
3474 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3475 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3476 * gen8_enable_rps will clean up. */
3477
3478 spin_lock_irq(&dev_priv->irq_lock);
3479 dev_priv->rps.pm_iir = 0;
3480 spin_unlock_irq(&dev_priv->irq_lock);
3481 3529
3482 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); 3530 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3531 }
3483} 3532}
3484 3533
3485static void gen6_disable_rps_interrupts(struct drm_device *dev) 3534static void gen6_disable_rps_interrupts(struct drm_device *dev)
@@ -3527,8 +3576,14 @@ static void valleyview_disable_rps(struct drm_device *dev)
3527{ 3576{
3528 struct drm_i915_private *dev_priv = dev->dev_private; 3577 struct drm_i915_private *dev_priv = dev->dev_private;
3529 3578
3579 /* we're doing forcewake before Disabling RC6,
3580 * This what the BIOS expects when going into suspend */
3581 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3582
3530 I915_WRITE(GEN6_RC_CONTROL, 0); 3583 I915_WRITE(GEN6_RC_CONTROL, 0);
3531 3584
3585 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3586
3532 gen6_disable_rps_interrupts(dev); 3587 gen6_disable_rps_interrupts(dev);
3533} 3588}
3534 3589
@@ -3631,13 +3686,111 @@ static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_c
3631 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 3686 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3632} 3687}
3633 3688
3689static void bdw_sw_calculate_freq(struct drm_device *dev,
3690 struct intel_rps_bdw_cal *c, u32 *cur_time, u32 *c0)
3691{
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693 u64 busy = 0;
3694 u32 busyness_pct = 0;
3695 u32 elapsed_time = 0;
3696 u16 new_freq = 0;
3697
3698 if (!c || !cur_time || !c0)
3699 return;
3700
3701 if (0 == c->last_c0)
3702 goto out;
3703
3704 /* Check Evaluation interval */
3705 elapsed_time = *cur_time - c->last_ts;
3706 if (elapsed_time < c->eval_interval)
3707 return;
3708
3709 mutex_lock(&dev_priv->rps.hw_lock);
3710
3711 /*
3712 * c0 unit in 32*1.28 usec, elapsed_time unit in 1 usec.
3713 * Whole busyness_pct calculation should be
3714 * busy = ((u64)(*c0 - c->last_c0) << 5 << 7) / 100;
3715 * busyness_pct = (u32)(busy * 100 / elapsed_time);
3716 * The final formula is to simplify CPU calculation
3717 */
3718 busy = (u64)(*c0 - c->last_c0) << 12;
3719 do_div(busy, elapsed_time);
3720 busyness_pct = (u32)busy;
3721
3722 if (c->is_up && busyness_pct >= c->it_threshold_pct)
3723 new_freq = (u16)dev_priv->rps.cur_freq + 3;
3724 if (!c->is_up && busyness_pct <= c->it_threshold_pct)
3725 new_freq = (u16)dev_priv->rps.cur_freq - 1;
3726
3727 /* Adjust to new frequency busyness and compare with threshold */
3728 if (0 != new_freq) {
3729 if (new_freq > dev_priv->rps.max_freq_softlimit)
3730 new_freq = dev_priv->rps.max_freq_softlimit;
3731 else if (new_freq < dev_priv->rps.min_freq_softlimit)
3732 new_freq = dev_priv->rps.min_freq_softlimit;
3733
3734 gen6_set_rps(dev, new_freq);
3735 }
3736
3737 mutex_unlock(&dev_priv->rps.hw_lock);
3738
3739out:
3740 c->last_c0 = *c0;
3741 c->last_ts = *cur_time;
3742}
3743
3744static void gen8_set_frequency_RP0(struct work_struct *work)
3745{
3746 struct intel_rps_bdw_turbo *p_bdw_turbo =
3747 container_of(work, struct intel_rps_bdw_turbo, work_max_freq);
3748 struct intel_gen6_power_mgmt *p_power_mgmt =
3749 container_of(p_bdw_turbo, struct intel_gen6_power_mgmt, sw_turbo);
3750 struct drm_i915_private *dev_priv =
3751 container_of(p_power_mgmt, struct drm_i915_private, rps);
3752
3753 mutex_lock(&dev_priv->rps.hw_lock);
3754 gen6_set_rps(dev_priv->dev, dev_priv->rps.rp0_freq);
3755 mutex_unlock(&dev_priv->rps.hw_lock);
3756}
3757
3758static void flip_active_timeout_handler(unsigned long var)
3759{
3760 struct drm_i915_private *dev_priv = (struct drm_i915_private *) var;
3761
3762 del_timer(&dev_priv->rps.sw_turbo.flip_timer);
3763 atomic_set(&dev_priv->rps.sw_turbo.flip_received, false);
3764
3765 queue_work(dev_priv->wq, &dev_priv->rps.sw_turbo.work_max_freq);
3766}
3767
3768void bdw_software_turbo(struct drm_device *dev)
3769{
3770 struct drm_i915_private *dev_priv = dev->dev_private;
3771
3772 u32 current_time = I915_READ(TIMESTAMP_CTR); /* unit in usec */
3773 u32 current_c0 = I915_READ(MCHBAR_PCU_C0); /* unit in 32*1.28 usec */
3774
3775 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.up,
3776 &current_time, &current_c0);
3777 bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.down,
3778 &current_time, &current_c0);
3779}
3780
3634static void gen8_enable_rps(struct drm_device *dev) 3781static void gen8_enable_rps(struct drm_device *dev)
3635{ 3782{
3636 struct drm_i915_private *dev_priv = dev->dev_private; 3783 struct drm_i915_private *dev_priv = dev->dev_private;
3637 struct intel_engine_cs *ring; 3784 struct intel_engine_cs *ring;
3638 uint32_t rc6_mask = 0, rp_state_cap; 3785 uint32_t rc6_mask = 0, rp_state_cap;
3786 uint32_t threshold_up_pct, threshold_down_pct;
3787 uint32_t ei_up, ei_down; /* up and down evaluation interval */
3788 u32 rp_ctl_flag;
3639 int unused; 3789 int unused;
3640 3790
3791 /* Use software Turbo for BDW */
3792 dev_priv->rps.is_bdw_sw_turbo = IS_BROADWELL(dev);
3793
3641 /* 1a: Software RC state - RC0 */ 3794 /* 1a: Software RC state - RC0 */
3642 I915_WRITE(GEN6_RC_STATE, 0); 3795 I915_WRITE(GEN6_RC_STATE, 0);
3643 3796
@@ -3681,35 +3834,74 @@ static void gen8_enable_rps(struct drm_device *dev)
3681 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 3834 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3682 I915_WRITE(GEN6_RC_VIDEO_FREQ, 3835 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3683 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 3836 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3684 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ 3837 ei_up = 84480; /* 84.48ms */
3685 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ 3838 ei_down = 448000;
3839 threshold_up_pct = 90; /* x percent busy */
3840 threshold_down_pct = 70;
3841
3842 if (dev_priv->rps.is_bdw_sw_turbo) {
3843 dev_priv->rps.sw_turbo.up.it_threshold_pct = threshold_up_pct;
3844 dev_priv->rps.sw_turbo.up.eval_interval = ei_up;
3845 dev_priv->rps.sw_turbo.up.is_up = true;
3846 dev_priv->rps.sw_turbo.up.last_ts = 0;
3847 dev_priv->rps.sw_turbo.up.last_c0 = 0;
3848
3849 dev_priv->rps.sw_turbo.down.it_threshold_pct = threshold_down_pct;
3850 dev_priv->rps.sw_turbo.down.eval_interval = ei_down;
3851 dev_priv->rps.sw_turbo.down.is_up = false;
3852 dev_priv->rps.sw_turbo.down.last_ts = 0;
3853 dev_priv->rps.sw_turbo.down.last_c0 = 0;
3854
3855 /* Start the timer to track if flip comes*/
3856 dev_priv->rps.sw_turbo.timeout = 200*1000; /* in us */
3857
3858 init_timer(&dev_priv->rps.sw_turbo.flip_timer);
3859 dev_priv->rps.sw_turbo.flip_timer.function = flip_active_timeout_handler;
3860 dev_priv->rps.sw_turbo.flip_timer.data = (unsigned long) dev_priv;
3861 dev_priv->rps.sw_turbo.flip_timer.expires =
3862 usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies;
3863 add_timer(&dev_priv->rps.sw_turbo.flip_timer);
3864 INIT_WORK(&dev_priv->rps.sw_turbo.work_max_freq, gen8_set_frequency_RP0);
3865
3866 atomic_set(&dev_priv->rps.sw_turbo.flip_received, true);
3867 } else {
3868 /* NB: Docs say 1s, and 1000000 - which aren't equivalent
3869 * 1 second timeout*/
3870 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, FREQ_1_28_US(1000000));
3686 3871
3687 /* Docs recommend 900MHz, and 300 MHz respectively */ 3872 /* Docs recommend 900MHz, and 300 MHz respectively */
3688 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 3873 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3689 dev_priv->rps.max_freq_softlimit << 24 | 3874 dev_priv->rps.max_freq_softlimit << 24 |
3690 dev_priv->rps.min_freq_softlimit << 16); 3875 dev_priv->rps.min_freq_softlimit << 16);
3691 3876
3692 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ 3877 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3693 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ 3878 FREQ_1_28_US(ei_up * threshold_up_pct / 100));
3694 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ 3879 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3695 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ 3880 FREQ_1_28_US(ei_down * threshold_down_pct / 100));
3881 I915_WRITE(GEN6_RP_UP_EI,
3882 FREQ_1_28_US(ei_up));
3883 I915_WRITE(GEN6_RP_DOWN_EI,
3884 FREQ_1_28_US(ei_down));
3696 3885
3697 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 3886 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3887 }
3698 3888
3699 /* 5: Enable RPS */ 3889 /* 5: Enable RPS */
3700 I915_WRITE(GEN6_RP_CONTROL, 3890 rp_ctl_flag = GEN6_RP_MEDIA_TURBO |
3701 GEN6_RP_MEDIA_TURBO | 3891 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3702 GEN6_RP_MEDIA_HW_NORMAL_MODE | 3892 GEN6_RP_MEDIA_IS_GFX |
3703 GEN6_RP_MEDIA_IS_GFX | 3893 GEN6_RP_UP_BUSY_AVG |
3704 GEN6_RP_ENABLE | 3894 GEN6_RP_DOWN_IDLE_AVG;
3705 GEN6_RP_UP_BUSY_AVG | 3895 if (!dev_priv->rps.is_bdw_sw_turbo)
3706 GEN6_RP_DOWN_IDLE_AVG); 3896 rp_ctl_flag |= GEN6_RP_ENABLE;
3707 3897
3708 /* 6: Ring frequency + overclocking (our driver does this later */ 3898 I915_WRITE(GEN6_RP_CONTROL, rp_ctl_flag);
3709 3899
3900 /* 6: Ring frequency + overclocking
3901 * (our driver does this later */
3710 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); 3902 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3711 3903 if (!dev_priv->rps.is_bdw_sw_turbo)
3712 gen8_enable_rps_interrupts(dev); 3904 gen8_enable_rps_interrupts(dev);
3713 3905
3714 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 3906 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3715} 3907}
@@ -4084,11 +4276,27 @@ static void valleyview_cleanup_pctx(struct drm_device *dev)
4084static void valleyview_init_gt_powersave(struct drm_device *dev) 4276static void valleyview_init_gt_powersave(struct drm_device *dev)
4085{ 4277{
4086 struct drm_i915_private *dev_priv = dev->dev_private; 4278 struct drm_i915_private *dev_priv = dev->dev_private;
4279 u32 val;
4087 4280
4088 valleyview_setup_pctx(dev); 4281 valleyview_setup_pctx(dev);
4089 4282
4090 mutex_lock(&dev_priv->rps.hw_lock); 4283 mutex_lock(&dev_priv->rps.hw_lock);
4091 4284
4285 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4286 switch ((val >> 6) & 3) {
4287 case 0:
4288 case 1:
4289 dev_priv->mem_freq = 800;
4290 break;
4291 case 2:
4292 dev_priv->mem_freq = 1066;
4293 break;
4294 case 3:
4295 dev_priv->mem_freq = 1333;
4296 break;
4297 }
4298 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4299
4092 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); 4300 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4093 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 4301 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4094 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 4302 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
@@ -4123,11 +4331,38 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
4123static void cherryview_init_gt_powersave(struct drm_device *dev) 4331static void cherryview_init_gt_powersave(struct drm_device *dev)
4124{ 4332{
4125 struct drm_i915_private *dev_priv = dev->dev_private; 4333 struct drm_i915_private *dev_priv = dev->dev_private;
4334 u32 val;
4126 4335
4127 cherryview_setup_pctx(dev); 4336 cherryview_setup_pctx(dev);
4128 4337
4129 mutex_lock(&dev_priv->rps.hw_lock); 4338 mutex_lock(&dev_priv->rps.hw_lock);
4130 4339
4340 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
4341 switch ((val >> 2) & 0x7) {
4342 case 0:
4343 case 1:
4344 dev_priv->rps.cz_freq = 200;
4345 dev_priv->mem_freq = 1600;
4346 break;
4347 case 2:
4348 dev_priv->rps.cz_freq = 267;
4349 dev_priv->mem_freq = 1600;
4350 break;
4351 case 3:
4352 dev_priv->rps.cz_freq = 333;
4353 dev_priv->mem_freq = 2000;
4354 break;
4355 case 4:
4356 dev_priv->rps.cz_freq = 320;
4357 dev_priv->mem_freq = 1600;
4358 break;
4359 case 5:
4360 dev_priv->rps.cz_freq = 400;
4361 dev_priv->mem_freq = 1600;
4362 break;
4363 }
4364 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4365
4131 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); 4366 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4132 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 4367 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4133 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 4368 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
@@ -4149,6 +4384,12 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
4149 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), 4384 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4150 dev_priv->rps.min_freq); 4385 dev_priv->rps.min_freq);
4151 4386
4387 WARN_ONCE((dev_priv->rps.max_freq |
4388 dev_priv->rps.efficient_freq |
4389 dev_priv->rps.rp1_freq |
4390 dev_priv->rps.min_freq) & 1,
4391 "Odd GPU freq values\n");
4392
4152 /* Preserve min/max settings in case of re-init */ 4393 /* Preserve min/max settings in case of re-init */
4153 if (dev_priv->rps.max_freq_softlimit == 0) 4394 if (dev_priv->rps.max_freq_softlimit == 0)
4154 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 4395 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
@@ -5134,6 +5375,8 @@ static void intel_gen6_powersave_work(struct work_struct *work)
5134 rps.delayed_resume_work.work); 5375 rps.delayed_resume_work.work);
5135 struct drm_device *dev = dev_priv->dev; 5376 struct drm_device *dev = dev_priv->dev;
5136 5377
5378 dev_priv->rps.is_bdw_sw_turbo = false;
5379
5137 mutex_lock(&dev_priv->rps.hw_lock); 5380 mutex_lock(&dev_priv->rps.hw_lock);
5138 5381
5139 if (IS_CHERRYVIEW(dev)) { 5382 if (IS_CHERRYVIEW(dev)) {
@@ -5207,7 +5450,7 @@ static void g4x_disable_trickle_feed(struct drm_device *dev)
5207 struct drm_i915_private *dev_priv = dev->dev_private; 5450 struct drm_i915_private *dev_priv = dev->dev_private;
5208 int pipe; 5451 int pipe;
5209 5452
5210 for_each_pipe(pipe) { 5453 for_each_pipe(dev_priv, pipe) {
5211 I915_WRITE(DSPCNTR(pipe), 5454 I915_WRITE(DSPCNTR(pipe),
5212 I915_READ(DSPCNTR(pipe)) | 5455 I915_READ(DSPCNTR(pipe)) |
5213 DISPPLANE_TRICKLE_FEED_DISABLE); 5456 DISPPLANE_TRICKLE_FEED_DISABLE);
@@ -5322,7 +5565,7 @@ static void cpt_init_clock_gating(struct drm_device *dev)
5322 /* The below fixes the weird display corruption, a few pixels shifted 5565 /* The below fixes the weird display corruption, a few pixels shifted
5323 * downward, on (only) LVDS of some HP laptops with IVY. 5566 * downward, on (only) LVDS of some HP laptops with IVY.
5324 */ 5567 */
5325 for_each_pipe(pipe) { 5568 for_each_pipe(dev_priv, pipe) {
5326 val = I915_READ(TRANS_CHICKEN2(pipe)); 5569 val = I915_READ(TRANS_CHICKEN2(pipe));
5327 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 5570 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5328 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 5571 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
@@ -5334,7 +5577,7 @@ static void cpt_init_clock_gating(struct drm_device *dev)
5334 I915_WRITE(TRANS_CHICKEN2(pipe), val); 5577 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5335 } 5578 }
5336 /* WADP0ClockGatingDisable */ 5579 /* WADP0ClockGatingDisable */
5337 for_each_pipe(pipe) { 5580 for_each_pipe(dev_priv, pipe) {
5338 I915_WRITE(TRANS_CHICKEN1(pipe), 5581 I915_WRITE(TRANS_CHICKEN1(pipe),
5339 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 5582 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5340 } 5583 }
@@ -5502,7 +5745,7 @@ static void lpt_suspend_hw(struct drm_device *dev)
5502 } 5745 }
5503} 5746}
5504 5747
5505static void gen8_init_clock_gating(struct drm_device *dev) 5748static void broadwell_init_clock_gating(struct drm_device *dev)
5506{ 5749{
5507 struct drm_i915_private *dev_priv = dev->dev_private; 5750 struct drm_i915_private *dev_priv = dev->dev_private;
5508 enum pipe pipe; 5751 enum pipe pipe;
@@ -5514,37 +5757,12 @@ static void gen8_init_clock_gating(struct drm_device *dev)
5514 /* FIXME(BDW): Check all the w/a, some might only apply to 5757 /* FIXME(BDW): Check all the w/a, some might only apply to
5515 * pre-production hw. */ 5758 * pre-production hw. */
5516 5759
5517 /* WaDisablePartialInstShootdown:bdw */
5518 I915_WRITE(GEN8_ROW_CHICKEN,
5519 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5520
5521 /* WaDisableThreadStallDopClockGating:bdw */
5522 /* FIXME: Unclear whether we really need this on production bdw. */
5523 I915_WRITE(GEN8_ROW_CHICKEN,
5524 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5525 5760
5526 /*
5527 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5528 * pre-production hardware
5529 */
5530 I915_WRITE(HALF_SLICE_CHICKEN3,
5531 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5532 I915_WRITE(HALF_SLICE_CHICKEN3,
5533 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5534 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); 5761 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5535 5762
5536 I915_WRITE(_3D_CHICKEN3, 5763 I915_WRITE(_3D_CHICKEN3,
5537 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2))); 5764 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
5538 5765
5539 I915_WRITE(COMMON_SLICE_CHICKEN2,
5540 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5541
5542 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5543 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5544
5545 /* WaDisableDopClockGating:bdw May not be needed for production */
5546 I915_WRITE(GEN7_ROW_CHICKEN2,
5547 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5548 5766
5549 /* WaSwitchSolVfFArbitrationPriority:bdw */ 5767 /* WaSwitchSolVfFArbitrationPriority:bdw */
5550 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 5768 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
@@ -5554,37 +5772,18 @@ static void gen8_init_clock_gating(struct drm_device *dev)
5554 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); 5772 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5555 5773
5556 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 5774 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5557 for_each_pipe(pipe) { 5775 for_each_pipe(dev_priv, pipe) {
5558 I915_WRITE(CHICKEN_PIPESL_1(pipe), 5776 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5559 I915_READ(CHICKEN_PIPESL_1(pipe)) | 5777 I915_READ(CHICKEN_PIPESL_1(pipe)) |
5560 BDW_DPRS_MASK_VBLANK_SRD); 5778 BDW_DPRS_MASK_VBLANK_SRD);
5561 } 5779 }
5562 5780
5563 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5564 * workaround for for a possible hang in the unlikely event a TLB
5565 * invalidation occurs during a PSD flush.
5566 */
5567 I915_WRITE(HDC_CHICKEN0,
5568 I915_READ(HDC_CHICKEN0) |
5569 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5570
5571 /* WaVSRefCountFullforceMissDisable:bdw */ 5781 /* WaVSRefCountFullforceMissDisable:bdw */
5572 /* WaDSRefCountFullforceMissDisable:bdw */ 5782 /* WaDSRefCountFullforceMissDisable:bdw */
5573 I915_WRITE(GEN7_FF_THREAD_MODE, 5783 I915_WRITE(GEN7_FF_THREAD_MODE,
5574 I915_READ(GEN7_FF_THREAD_MODE) & 5784 I915_READ(GEN7_FF_THREAD_MODE) &
5575 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 5785 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5576 5786
5577 /*
5578 * BSpec recommends 8x4 when MSAA is used,
5579 * however in practice 16x4 seems fastest.
5580 *
5581 * Note that PS/WM thread counts depend on the WIZ hashing
5582 * disable bit, which we don't touch here, but it's good
5583 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5584 */
5585 I915_WRITE(GEN7_GT_MODE,
5586 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5587
5588 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 5787 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5589 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 5788 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5590 5789
@@ -5592,9 +5791,7 @@ static void gen8_init_clock_gating(struct drm_device *dev)
5592 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 5791 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5593 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 5792 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5594 5793
5595 /* Wa4x4STCOptimizationDisable:bdw */ 5794 lpt_init_clock_gating(dev);
5596 I915_WRITE(CACHE_MODE_1,
5597 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5598} 5795}
5599 5796
5600static void haswell_init_clock_gating(struct drm_device *dev) 5797static void haswell_init_clock_gating(struct drm_device *dev)
@@ -5750,24 +5947,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
5750static void valleyview_init_clock_gating(struct drm_device *dev) 5947static void valleyview_init_clock_gating(struct drm_device *dev)
5751{ 5948{
5752 struct drm_i915_private *dev_priv = dev->dev_private; 5949 struct drm_i915_private *dev_priv = dev->dev_private;
5753 u32 val;
5754
5755 mutex_lock(&dev_priv->rps.hw_lock);
5756 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5757 mutex_unlock(&dev_priv->rps.hw_lock);
5758 switch ((val >> 6) & 3) {
5759 case 0:
5760 case 1:
5761 dev_priv->mem_freq = 800;
5762 break;
5763 case 2:
5764 dev_priv->mem_freq = 1066;
5765 break;
5766 case 3:
5767 dev_priv->mem_freq = 1333;
5768 break;
5769 }
5770 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5771 5950
5772 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); 5951 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5773 5952
@@ -5843,48 +6022,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
5843static void cherryview_init_clock_gating(struct drm_device *dev) 6022static void cherryview_init_clock_gating(struct drm_device *dev)
5844{ 6023{
5845 struct drm_i915_private *dev_priv = dev->dev_private; 6024 struct drm_i915_private *dev_priv = dev->dev_private;
5846 u32 val;
5847
5848 mutex_lock(&dev_priv->rps.hw_lock);
5849 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5850 mutex_unlock(&dev_priv->rps.hw_lock);
5851 switch ((val >> 2) & 0x7) {
5852 case 0:
5853 case 1:
5854 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
5855 dev_priv->mem_freq = 1600;
5856 break;
5857 case 2:
5858 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
5859 dev_priv->mem_freq = 1600;
5860 break;
5861 case 3:
5862 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
5863 dev_priv->mem_freq = 2000;
5864 break;
5865 case 4:
5866 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
5867 dev_priv->mem_freq = 1600;
5868 break;
5869 case 5:
5870 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
5871 dev_priv->mem_freq = 1600;
5872 break;
5873 }
5874 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5875 6025
5876 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); 6026 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5877 6027
5878 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 6028 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5879 6029
5880 /* WaDisablePartialInstShootdown:chv */
5881 I915_WRITE(GEN8_ROW_CHICKEN,
5882 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5883
5884 /* WaDisableThreadStallDopClockGating:chv */
5885 I915_WRITE(GEN8_ROW_CHICKEN,
5886 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5887
5888 /* WaVSRefCountFullforceMissDisable:chv */ 6030 /* WaVSRefCountFullforceMissDisable:chv */
5889 /* WaDSRefCountFullforceMissDisable:chv */ 6031 /* WaDSRefCountFullforceMissDisable:chv */
5890 I915_WRITE(GEN7_FF_THREAD_MODE, 6032 I915_WRITE(GEN7_FF_THREAD_MODE,
@@ -5903,10 +6045,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
5903 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6045 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5904 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6046 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5905 6047
5906 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5907 I915_WRITE(HALF_SLICE_CHICKEN3,
5908 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5909
5910 /* WaDisableGunitClockGating:chv (pre-production hw) */ 6048 /* WaDisableGunitClockGating:chv (pre-production hw) */
5911 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) | 6049 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5912 GINT_DIS); 6050 GINT_DIS);
@@ -5916,8 +6054,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
5916 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE)); 6054 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5917 6055
5918 /* WaDisableDopClockGating:chv (pre-production hw) */ 6056 /* WaDisableDopClockGating:chv (pre-production hw) */
5919 I915_WRITE(GEN7_ROW_CHICKEN2,
5920 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5921 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | 6057 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5922 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); 6058 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5923} 6059}
@@ -6002,6 +6138,9 @@ static void gen3_init_clock_gating(struct drm_device *dev)
6002 6138
6003 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 6139 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6004 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 6140 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6141
6142 I915_WRITE(MI_ARB_STATE,
6143 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6005} 6144}
6006 6145
6007static void i85x_init_clock_gating(struct drm_device *dev) 6146static void i85x_init_clock_gating(struct drm_device *dev)
@@ -6013,6 +6152,9 @@ static void i85x_init_clock_gating(struct drm_device *dev)
6013 /* interrupts should cause a wake up from C3 */ 6152 /* interrupts should cause a wake up from C3 */
6014 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | 6153 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6015 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); 6154 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6155
6156 I915_WRITE(MEM_MODE,
6157 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6016} 6158}
6017 6159
6018static void i830_init_clock_gating(struct drm_device *dev) 6160static void i830_init_clock_gating(struct drm_device *dev)
@@ -6020,6 +6162,10 @@ static void i830_init_clock_gating(struct drm_device *dev)
6020 struct drm_i915_private *dev_priv = dev->dev_private; 6162 struct drm_i915_private *dev_priv = dev->dev_private;
6021 6163
6022 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 6164 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6165
6166 I915_WRITE(MEM_MODE,
6167 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6168 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6023} 6169}
6024 6170
6025void intel_init_clock_gating(struct drm_device *dev) 6171void intel_init_clock_gating(struct drm_device *dev)
@@ -6322,6 +6468,8 @@ static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6322 spin_unlock_irq(&dev_priv->irq_lock); 6468 spin_unlock_irq(&dev_priv->irq_lock);
6323 6469
6324 vlv_set_power_well(dev_priv, power_well, false); 6470 vlv_set_power_well(dev_priv, power_well, false);
6471
6472 vlv_power_sequencer_reset(dev_priv);
6325} 6473}
6326 6474
6327static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 6475static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
@@ -6357,12 +6505,11 @@ static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6357static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 6505static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6358 struct i915_power_well *power_well) 6506 struct i915_power_well *power_well)
6359{ 6507{
6360 struct drm_device *dev = dev_priv->dev;
6361 enum pipe pipe; 6508 enum pipe pipe;
6362 6509
6363 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 6510 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6364 6511
6365 for_each_pipe(pipe) 6512 for_each_pipe(dev_priv, pipe)
6366 assert_pll_disabled(dev_priv, pipe); 6513 assert_pll_disabled(dev_priv, pipe);
6367 6514
6368 /* Assert common reset */ 6515 /* Assert common reset */
@@ -7249,7 +7396,7 @@ void intel_init_pm(struct drm_device *dev)
7249 else if (IS_HASWELL(dev)) 7396 else if (IS_HASWELL(dev))
7250 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 7397 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7251 else if (INTEL_INFO(dev)->gen == 8) 7398 else if (INTEL_INFO(dev)->gen == 8)
7252 dev_priv->display.init_clock_gating = gen8_init_clock_gating; 7399 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7253 } else if (IS_CHERRYVIEW(dev)) { 7400 } else if (IS_CHERRYVIEW(dev)) {
7254 dev_priv->display.update_wm = cherryview_update_wm; 7401 dev_priv->display.update_wm = cherryview_update_wm;
7255 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; 7402 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
@@ -7443,6 +7590,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7443 return -1; 7590 return -1;
7444 } 7591 }
7445 7592
7593 /* CHV needs even values */
7446 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2); 7594 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7447 7595
7448 return opcode; 7596 return opcode;
diff --git a/drivers/gpu/drm/i915/intel_renderstate.h b/drivers/gpu/drm/i915/intel_renderstate.h
index fd4f66231d30..6c792d3a9c9c 100644
--- a/drivers/gpu/drm/i915/intel_renderstate.h
+++ b/drivers/gpu/drm/i915/intel_renderstate.h
@@ -24,13 +24,7 @@
24#ifndef _INTEL_RENDERSTATE_H 24#ifndef _INTEL_RENDERSTATE_H
25#define _INTEL_RENDERSTATE_H 25#define _INTEL_RENDERSTATE_H
26 26
27#include <linux/types.h> 27#include "i915_drv.h"
28
29struct intel_renderstate_rodata {
30 const u32 *reloc;
31 const u32 *batch;
32 const u32 batch_items;
33};
34 28
35extern const struct intel_renderstate_rodata gen6_null_state; 29extern const struct intel_renderstate_rodata gen6_null_state;
36extern const struct intel_renderstate_rodata gen7_null_state; 30extern const struct intel_renderstate_rodata gen7_null_state;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3c7283d8f160..109de2eeb9a8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -444,7 +444,14 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
444 return ret; 444 return ret;
445 } 445 }
446 446
447 return gen8_emit_pipe_control(ring, flags, scratch_addr); 447 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
448 if (ret)
449 return ret;
450
451 if (!invalidate_domains && flush_domains)
452 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
453
454 return 0;
448} 455}
449 456
450static void ring_write_tail(struct intel_engine_cs *ring, 457static void ring_write_tail(struct intel_engine_cs *ring,
@@ -556,6 +563,14 @@ static int init_ring_common(struct intel_engine_cs *ring)
556 * also enforces ordering), otherwise the hw might lose the new ring 563 * also enforces ordering), otherwise the hw might lose the new ring
557 * register values. */ 564 * register values. */
558 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); 565 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
566
567 /* WaClearRingBufHeadRegAtInit:ctg,elk */
568 if (I915_READ_HEAD(ring))
569 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
570 ring->name, I915_READ_HEAD(ring));
571 I915_WRITE_HEAD(ring, 0);
572 (void)I915_READ_HEAD(ring);
573
559 I915_WRITE_CTL(ring, 574 I915_WRITE_CTL(ring,
560 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) 575 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
561 | RING_VALID); 576 | RING_VALID);
@@ -650,6 +665,146 @@ err:
650 return ret; 665 return ret;
651} 666}
652 667
668static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
669 u32 addr, u32 value)
670{
671 struct drm_device *dev = ring->dev;
672 struct drm_i915_private *dev_priv = dev->dev_private;
673
674 if (WARN_ON(dev_priv->num_wa_regs >= I915_MAX_WA_REGS))
675 return;
676
677 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
678 intel_ring_emit(ring, addr);
679 intel_ring_emit(ring, value);
680
681 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr;
682 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF;
683 /* value is updated with the status of remaining bits of this
684 * register when it is read from debugfs file
685 */
686 dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value;
687 dev_priv->num_wa_regs++;
688
689 return;
690}
691
692static int bdw_init_workarounds(struct intel_engine_cs *ring)
693{
694 int ret;
695 struct drm_device *dev = ring->dev;
696 struct drm_i915_private *dev_priv = dev->dev_private;
697
698 /*
699 * workarounds applied in this fn are part of register state context,
700 * they need to be re-initialized followed by gpu reset, suspend/resume,
701 * module reload.
702 */
703 dev_priv->num_wa_regs = 0;
704 memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
705
706 /*
707 * update the number of dwords required based on the
708 * actual number of workarounds applied
709 */
710 ret = intel_ring_begin(ring, 24);
711 if (ret)
712 return ret;
713
714 /* WaDisablePartialInstShootdown:bdw */
715 /* WaDisableThreadStallDopClockGating:bdw */
716 /* FIXME: Unclear whether we really need this on production bdw. */
717 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
718 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
719 | STALL_DOP_GATING_DISABLE));
720
721 /* WaDisableDopClockGating:bdw May not be needed for production */
722 intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
723 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
724
725 /*
726 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
727 * pre-production hardware
728 */
729 intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
730 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
731 | GEN8_SAMPLER_POWER_BYPASS_DIS));
732
733 intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1,
734 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
735
736 intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2,
737 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
738
739 /* Use Force Non-Coherent whenever executing a 3D context. This is a
740 * workaround for for a possible hang in the unlikely event a TLB
741 * invalidation occurs during a PSD flush.
742 */
743 intel_ring_emit_wa(ring, HDC_CHICKEN0,
744 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
745
746 /* Wa4x4STCOptimizationDisable:bdw */
747 intel_ring_emit_wa(ring, CACHE_MODE_1,
748 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
749
750 /*
751 * BSpec recommends 8x4 when MSAA is used,
752 * however in practice 16x4 seems fastest.
753 *
754 * Note that PS/WM thread counts depend on the WIZ hashing
755 * disable bit, which we don't touch here, but it's good
756 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
757 */
758 intel_ring_emit_wa(ring, GEN7_GT_MODE,
759 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
760
761 intel_ring_advance(ring);
762
763 DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
764 dev_priv->num_wa_regs);
765
766 return 0;
767}
768
769static int chv_init_workarounds(struct intel_engine_cs *ring)
770{
771 int ret;
772 struct drm_device *dev = ring->dev;
773 struct drm_i915_private *dev_priv = dev->dev_private;
774
775 /*
776 * workarounds applied in this fn are part of register state context,
777 * they need to be re-initialized followed by gpu reset, suspend/resume,
778 * module reload.
779 */
780 dev_priv->num_wa_regs = 0;
781 memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
782
783 ret = intel_ring_begin(ring, 12);
784 if (ret)
785 return ret;
786
787 /* WaDisablePartialInstShootdown:chv */
788 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
789 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
790
791 /* WaDisableThreadStallDopClockGating:chv */
792 intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
793 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
794
795 /* WaDisableDopClockGating:chv (pre-production hw) */
796 intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
797 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
798
799 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
800 intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
801 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
802
803 intel_ring_advance(ring);
804
805 return 0;
806}
807
653static int init_render_ring(struct intel_engine_cs *ring) 808static int init_render_ring(struct intel_engine_cs *ring)
654{ 809{
655 struct drm_device *dev = ring->dev; 810 struct drm_device *dev = ring->dev;
@@ -2148,6 +2303,10 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
2148 dev_priv->semaphore_obj = obj; 2303 dev_priv->semaphore_obj = obj;
2149 } 2304 }
2150 } 2305 }
2306 if (IS_CHERRYVIEW(dev))
2307 ring->init_context = chv_init_workarounds;
2308 else
2309 ring->init_context = bdw_init_workarounds;
2151 ring->add_request = gen6_add_request; 2310 ring->add_request = gen6_add_request;
2152 ring->flush = gen8_render_ring_flush; 2311 ring->flush = gen8_render_ring_flush;
2153 ring->irq_get = gen8_ring_get_irq; 2312 ring->irq_get = gen8_ring_get_irq;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 9cbf7b0ebc99..96479c89f4bd 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -148,6 +148,8 @@ struct intel_engine_cs {
148 148
149 int (*init)(struct intel_engine_cs *ring); 149 int (*init)(struct intel_engine_cs *ring);
150 150
151 int (*init_context)(struct intel_engine_cs *ring);
152
151 void (*write_tail)(struct intel_engine_cs *ring, 153 void (*write_tail)(struct intel_engine_cs *ring,
152 u32 value); 154 u32 value);
153 int __must_check (*flush)(struct intel_engine_cs *ring, 155 int __must_check (*flush)(struct intel_engine_cs *ring,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0bdb00b7c59c..07a74ef589bd 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1218,9 +1218,9 @@ out_unlock:
1218 return ret; 1218 return ret;
1219} 1219}
1220 1220
1221static int intel_plane_set_property(struct drm_plane *plane, 1221int intel_plane_set_property(struct drm_plane *plane,
1222 struct drm_property *prop, 1222 struct drm_property *prop,
1223 uint64_t val) 1223 uint64_t val)
1224{ 1224{
1225 struct drm_device *dev = plane->dev; 1225 struct drm_device *dev = plane->dev;
1226 struct intel_plane *intel_plane = to_intel_plane(plane); 1226 struct intel_plane *intel_plane = to_intel_plane(plane);
@@ -1232,6 +1232,9 @@ static int intel_plane_set_property(struct drm_plane *plane,
1232 if (hweight32(val & 0xf) != 1) 1232 if (hweight32(val & 0xf) != 1)
1233 return -EINVAL; 1233 return -EINVAL;
1234 1234
1235 if (intel_plane->rotation == val)
1236 return 0;
1237
1235 old_val = intel_plane->rotation; 1238 old_val = intel_plane->rotation;
1236 intel_plane->rotation = val; 1239 intel_plane->rotation = val;
1237 ret = intel_plane_restore(plane); 1240 ret = intel_plane_restore(plane);
@@ -1249,7 +1252,7 @@ int intel_plane_restore(struct drm_plane *plane)
1249 if (!plane->crtc || !plane->fb) 1252 if (!plane->crtc || !plane->fb)
1250 return 0; 1253 return 0;
1251 1254
1252 return intel_update_plane(plane, plane->crtc, plane->fb, 1255 return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
1253 intel_plane->crtc_x, intel_plane->crtc_y, 1256 intel_plane->crtc_x, intel_plane->crtc_y,
1254 intel_plane->crtc_w, intel_plane->crtc_h, 1257 intel_plane->crtc_w, intel_plane->crtc_h,
1255 intel_plane->src_x, intel_plane->src_y, 1258 intel_plane->src_x, intel_plane->src_y,
@@ -1375,10 +1378,10 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1375 intel_plane->plane = plane; 1378 intel_plane->plane = plane;
1376 intel_plane->rotation = BIT(DRM_ROTATE_0); 1379 intel_plane->rotation = BIT(DRM_ROTATE_0);
1377 possible_crtcs = (1 << pipe); 1380 possible_crtcs = (1 << pipe);
1378 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, 1381 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1379 &intel_plane_funcs, 1382 &intel_plane_funcs,
1380 plane_formats, num_plane_formats, 1383 plane_formats, num_plane_formats,
1381 false); 1384 DRM_PLANE_TYPE_OVERLAY);
1382 if (ret) { 1385 if (ret) {
1383 kfree(intel_plane); 1386 kfree(intel_plane);
1384 goto out; 1387 goto out;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e81bc3bdc533..918b76163965 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -101,7 +101,7 @@ static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
101{ 101{
102 u32 forcewake_ack; 102 u32 forcewake_ack;
103 103
104 if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) 104 if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev))
105 forcewake_ack = FORCEWAKE_ACK_HSW; 105 forcewake_ack = FORCEWAKE_ACK_HSW;
106 else 106 else
107 forcewake_ack = FORCEWAKE_MT_ACK; 107 forcewake_ack = FORCEWAKE_MT_ACK;
@@ -334,7 +334,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
334 else if (IS_GEN6(dev) || IS_GEN7(dev)) 334 else if (IS_GEN6(dev) || IS_GEN7(dev))
335 __gen6_gt_force_wake_reset(dev_priv); 335 __gen6_gt_force_wake_reset(dev_priv);
336 336
337 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev)) 337 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
338 __gen7_gt_force_wake_mt_reset(dev_priv); 338 __gen7_gt_force_wake_mt_reset(dev_priv);
339 339
340 if (restore) { /* If reset with a user forcewake, try to restore */ 340 if (restore) { /* If reset with a user forcewake, try to restore */
@@ -838,7 +838,7 @@ void intel_uncore_init(struct drm_device *dev)
838 if (IS_VALLEYVIEW(dev)) { 838 if (IS_VALLEYVIEW(dev)) {
839 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; 839 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
840 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; 840 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
841 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { 841 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
842 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; 842 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
843 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; 843 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
844 } else if (IS_IVYBRIDGE(dev)) { 844 } else if (IS_IVYBRIDGE(dev)) {
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index ac14b67621d3..95d5d4ab3335 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -232,8 +232,8 @@ void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
232 232
233/***** general DP utility functions *****/ 233/***** general DP utility functions *****/
234 234
235#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 235#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
236#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 236#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
237 237
238static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], 238static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
239 int lane_count, 239 int lane_count,
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 708f783ead47..d6b55e3e3716 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -533,9 +533,9 @@ int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
533 533
534 for (i = 0; i < link->num_lanes; i++) 534 for (i = 0; i < link->num_lanes; i++)
535 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED | 535 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
536 DP_TRAIN_PRE_EMPHASIS_0 | 536 DP_TRAIN_PRE_EMPH_LEVEL_0 |
537 DP_TRAIN_MAX_SWING_REACHED | 537 DP_TRAIN_MAX_SWING_REACHED |
538 DP_TRAIN_VOLTAGE_SWING_400; 538 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
539 539
540 err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values, 540 err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
541 link->num_lanes); 541 link->num_lanes);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index a21568bf1514..9305c718d789 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -190,16 +190,16 @@
190# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 190# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
191# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 191# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
192# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 192# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
193# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) 193# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
194# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) 194# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
195# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) 195# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
196# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) 196# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
197 197
198# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 198# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
199# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) 199# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
200# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) 200# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
201# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) 201# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
202# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) 202# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
203 203
204# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 204# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
205# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 205# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-13 17:41:40 -0400