1 files changed, 13 insertions, 0 deletions

diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index 35bd5cc7f285..3cb69d5fb817 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -565,6 +565,19 @@ static void sil_freeze(struct ata_port *ap)
         tmp |= SIL_MASK_IDE0_INT << ap->port_no;
         writel(tmp, mmio_base + SIL_SYSCFG);
         readl(mmio_base + SIL_SYSCFG);  /* flush */
+
+        /* Ensure DMA_ENABLE is off.
+         *
+         * This is because the controller will not give us access to the
+         * taskfile registers while a DMA is in progress
+         */
+        iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE,
+                 ap->ioaddr.bmdma_addr);
+
+        /* According to ata_bmdma_stop, an HDMA transition requires
+         * on PIO cycle. But we can't read a taskfile register.
+         */
+        ioread8(ap->ioaddr.bmdma_addr);
 }
 
 static void sil_thaw(struct ata_port *ap)