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-rw-r--r--arch/arm/plat-mxc/include/mach/mx21-usbhost.h38
-rw-r--r--drivers/usb/Makefile1
-rw-r--r--drivers/usb/host/Kconfig11
-rw-r--r--drivers/usb/host/Makefile2
-rw-r--r--drivers/usb/host/imx21-dbg.c527
-rw-r--r--drivers/usb/host/imx21-hcd.c1789
-rw-r--r--drivers/usb/host/imx21-hcd.h436
7 files changed, 2804 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mx21-usbhost.h b/arch/arm/plat-mxc/include/mach/mx21-usbhost.h
new file mode 100644
index 000000000000..22d0b596262c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx21-usbhost.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2009 Martin Fuzzey <mfuzzey@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __ASM_ARCH_MX21_USBH
16#define __ASM_ARCH_MX21_USBH
17
18enum mx21_usbh_xcvr {
19 /* Values below as used by hardware (HWMODE register) */
20 MX21_USBXCVR_TXDIF_RXDIF = 0,
21 MX21_USBXCVR_TXDIF_RXSE = 1,
22 MX21_USBXCVR_TXSE_RXDIF = 2,
23 MX21_USBXCVR_TXSE_RXSE = 3,
24};
25
26struct mx21_usbh_platform_data {
27 enum mx21_usbh_xcvr host_xcvr; /* tranceiver mode host 1,2 ports */
28 enum mx21_usbh_xcvr otg_xcvr; /* tranceiver mode otg (as host) port */
29 u16 enable_host1:1,
30 enable_host2:1,
31 enable_otg_host:1, /* enable "OTG" port (as host) */
32 host1_xcverless:1, /* traceiverless host1 port */
33 host1_txenoe:1, /* output enable host1 transmit enable */
34 otg_ext_xcvr:1, /* external tranceiver for OTG port */
35 unused:10;
36};
37
38#endif /* __ASM_ARCH_MX21_USBH */
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index be3c9b80bc9f..80b4008c89ba 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_USB_U132_HCD) += host/
21obj-$(CONFIG_USB_R8A66597_HCD) += host/ 21obj-$(CONFIG_USB_R8A66597_HCD) += host/
22obj-$(CONFIG_USB_HWA_HCD) += host/ 22obj-$(CONFIG_USB_HWA_HCD) += host/
23obj-$(CONFIG_USB_ISP1760_HCD) += host/ 23obj-$(CONFIG_USB_ISP1760_HCD) += host/
24obj-$(CONFIG_USB_IMX21_HCD) += host/
24 25
25obj-$(CONFIG_USB_C67X00_HCD) += c67x00/ 26obj-$(CONFIG_USB_C67X00_HCD) += c67x00/
26 27
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 2678a1624fcc..8d3df0397de3 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -399,3 +399,14 @@ config USB_HWA_HCD
399 399
400 To compile this driver a module, choose M here: the module 400 To compile this driver a module, choose M here: the module
401 will be called "hwa-hc". 401 will be called "hwa-hc".
402
403config USB_IMX21_HCD
404 tristate "iMX21 HCD support"
405 depends on USB && ARM && MACH_MX21
406 help
407 This driver enables support for the on-chip USB host in the
408 iMX21 processor.
409
410 To compile this driver as a module, choose M here: the
411 module will be called "imx21-hcd".
412
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index f58b2494c44a..4e0c67f1f51b 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -32,3 +32,5 @@ obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
32obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o 32obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
33obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o 33obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o
34obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o 34obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o
35obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
36
diff --git a/drivers/usb/host/imx21-dbg.c b/drivers/usb/host/imx21-dbg.c
new file mode 100644
index 000000000000..512f647448ca
--- /dev/null
+++ b/drivers/usb/host/imx21-dbg.c
@@ -0,0 +1,527 @@
1/*
2 * Copyright (c) 2009 by Martin Fuzzey
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* this file is part of imx21-hcd.c */
20
21#ifndef DEBUG
22
23static inline void create_debug_files(struct imx21 *imx21) { }
24static inline void remove_debug_files(struct imx21 *imx21) { }
25static inline void debug_urb_submitted(struct imx21 *imx21, struct urb *urb) {}
26static inline void debug_urb_completed(struct imx21 *imx21, struct urb *urb,
27 int status) {}
28static inline void debug_urb_unlinked(struct imx21 *imx21, struct urb *urb) {}
29static inline void debug_urb_queued_for_etd(struct imx21 *imx21,
30 struct urb *urb) {}
31static inline void debug_urb_queued_for_dmem(struct imx21 *imx21,
32 struct urb *urb) {}
33static inline void debug_etd_allocated(struct imx21 *imx21) {}
34static inline void debug_etd_freed(struct imx21 *imx21) {}
35static inline void debug_dmem_allocated(struct imx21 *imx21, int size) {}
36static inline void debug_dmem_freed(struct imx21 *imx21, int size) {}
37static inline void debug_isoc_submitted(struct imx21 *imx21,
38 int frame, struct td *td) {}
39static inline void debug_isoc_completed(struct imx21 *imx21,
40 int frame, struct td *td, int cc, int len) {}
41
42#else
43
44#include <linux/debugfs.h>
45#include <linux/seq_file.h>
46
47static const char *dir_labels[] = {
48 "TD 0",
49 "OUT",
50 "IN",
51 "TD 1"
52};
53
54static const char *speed_labels[] = {
55 "Full",
56 "Low"
57};
58
59static const char *format_labels[] = {
60 "Control",
61 "ISO",
62 "Bulk",
63 "Interrupt"
64};
65
66static inline struct debug_stats *stats_for_urb(struct imx21 *imx21,
67 struct urb *urb)
68{
69 return usb_pipeisoc(urb->pipe) ?
70 &imx21->isoc_stats : &imx21->nonisoc_stats;
71}
72
73static void debug_urb_submitted(struct imx21 *imx21, struct urb *urb)
74{
75 stats_for_urb(imx21, urb)->submitted++;
76}
77
78static void debug_urb_completed(struct imx21 *imx21, struct urb *urb, int st)
79{
80 if (st)
81 stats_for_urb(imx21, urb)->completed_failed++;
82 else
83 stats_for_urb(imx21, urb)->completed_ok++;
84}
85
86static void debug_urb_unlinked(struct imx21 *imx21, struct urb *urb)
87{
88 stats_for_urb(imx21, urb)->unlinked++;
89}
90
91static void debug_urb_queued_for_etd(struct imx21 *imx21, struct urb *urb)
92{
93 stats_for_urb(imx21, urb)->queue_etd++;
94}
95
96static void debug_urb_queued_for_dmem(struct imx21 *imx21, struct urb *urb)
97{
98 stats_for_urb(imx21, urb)->queue_dmem++;
99}
100
101static inline void debug_etd_allocated(struct imx21 *imx21)
102{
103 imx21->etd_usage.maximum = max(
104 ++(imx21->etd_usage.value),
105 imx21->etd_usage.maximum);
106}
107
108static inline void debug_etd_freed(struct imx21 *imx21)
109{
110 imx21->etd_usage.value--;
111}
112
113static inline void debug_dmem_allocated(struct imx21 *imx21, int size)
114{
115 imx21->dmem_usage.value += size;
116 imx21->dmem_usage.maximum = max(
117 imx21->dmem_usage.value,
118 imx21->dmem_usage.maximum);
119}
120
121static inline void debug_dmem_freed(struct imx21 *imx21, int size)
122{
123 imx21->dmem_usage.value -= size;
124}
125
126
127static void debug_isoc_submitted(struct imx21 *imx21,
128 int frame, struct td *td)
129{
130 struct debug_isoc_trace *trace = &imx21->isoc_trace[
131 imx21->isoc_trace_index++];
132
133 imx21->isoc_trace_index %= ARRAY_SIZE(imx21->isoc_trace);
134 trace->schedule_frame = td->frame;
135 trace->submit_frame = frame;
136 trace->request_len = td->len;
137 trace->td = td;
138}
139
140static inline void debug_isoc_completed(struct imx21 *imx21,
141 int frame, struct td *td, int cc, int len)
142{
143 struct debug_isoc_trace *trace, *trace_failed;
144 int i;
145 int found = 0;
146
147 trace = imx21->isoc_trace;
148 for (i = 0; i < ARRAY_SIZE(imx21->isoc_trace); i++, trace++) {
149 if (trace->td == td) {
150 trace->done_frame = frame;
151 trace->done_len = len;
152 trace->cc = cc;
153 trace->td = NULL;
154 found = 1;
155 break;
156 }
157 }
158
159 if (found && cc) {
160 trace_failed = &imx21->isoc_trace_failed[
161 imx21->isoc_trace_index_failed++];
162
163 imx21->isoc_trace_index_failed %= ARRAY_SIZE(
164 imx21->isoc_trace_failed);
165 *trace_failed = *trace;
166 }
167}
168
169
170static char *format_ep(struct usb_host_endpoint *ep, char *buf, int bufsize)
171{
172 if (ep)
173 snprintf(buf, bufsize, "ep_%02x (type:%02X kaddr:%p)",
174 ep->desc.bEndpointAddress,
175 usb_endpoint_type(&ep->desc),
176 ep);
177 else
178 snprintf(buf, bufsize, "none");
179 return buf;
180}
181
182static char *format_etd_dword0(u32 value, char *buf, int bufsize)
183{
184 snprintf(buf, bufsize,
185 "addr=%d ep=%d dir=%s speed=%s format=%s halted=%d",
186 value & 0x7F,
187 (value >> DW0_ENDPNT) & 0x0F,
188 dir_labels[(value >> DW0_DIRECT) & 0x03],
189 speed_labels[(value >> DW0_SPEED) & 0x01],
190 format_labels[(value >> DW0_FORMAT) & 0x03],
191 (value >> DW0_HALTED) & 0x01);
192 return buf;
193}
194
195static int debug_status_show(struct seq_file *s, void *v)
196{
197 struct imx21 *imx21 = s->private;
198 int etds_allocated = 0;
199 int etds_sw_busy = 0;
200 int etds_hw_busy = 0;
201 int dmem_blocks = 0;
202 int queued_for_etd = 0;
203 int queued_for_dmem = 0;
204 unsigned int dmem_bytes = 0;
205 int i;
206 struct etd_priv *etd;
207 u32 etd_enable_mask;
208 unsigned long flags;
209 struct imx21_dmem_area *dmem;
210 struct ep_priv *ep_priv;
211
212 spin_lock_irqsave(&imx21->lock, flags);
213
214 etd_enable_mask = readl(imx21->regs + USBH_ETDENSET);
215 for (i = 0, etd = imx21->etd; i < USB_NUM_ETD; i++, etd++) {
216 if (etd->alloc)
217 etds_allocated++;
218 if (etd->urb)
219 etds_sw_busy++;
220 if (etd_enable_mask & (1<<i))
221 etds_hw_busy++;
222 }
223
224 list_for_each_entry(dmem, &imx21->dmem_list, list) {
225 dmem_bytes += dmem->size;
226 dmem_blocks++;
227 }
228
229 list_for_each_entry(ep_priv, &imx21->queue_for_etd, queue)
230 queued_for_etd++;
231
232 list_for_each_entry(etd, &imx21->queue_for_dmem, queue)
233 queued_for_dmem++;
234
235 spin_unlock_irqrestore(&imx21->lock, flags);
236
237 seq_printf(s,
238 "Frame: %d\n"
239 "ETDs allocated: %d/%d (max=%d)\n"
240 "ETDs in use sw: %d\n"
241 "ETDs in use hw: %d\n"
242 "DMEM alocated: %d/%d (max=%d)\n"
243 "DMEM blocks: %d\n"
244 "Queued waiting for ETD: %d\n"
245 "Queued waiting for DMEM: %d\n",
246 readl(imx21->regs + USBH_FRMNUB) & 0xFFFF,
247 etds_allocated, USB_NUM_ETD, imx21->etd_usage.maximum,
248 etds_sw_busy,
249 etds_hw_busy,
250 dmem_bytes, DMEM_SIZE, imx21->dmem_usage.maximum,
251 dmem_blocks,
252 queued_for_etd,
253 queued_for_dmem);
254
255 return 0;
256}
257
258static int debug_dmem_show(struct seq_file *s, void *v)
259{
260 struct imx21 *imx21 = s->private;
261 struct imx21_dmem_area *dmem;
262 unsigned long flags;
263 char ep_text[40];
264
265 spin_lock_irqsave(&imx21->lock, flags);
266
267 list_for_each_entry(dmem, &imx21->dmem_list, list)
268 seq_printf(s,
269 "%04X: size=0x%X "
270 "ep=%s\n",
271 dmem->offset, dmem->size,
272 format_ep(dmem->ep, ep_text, sizeof(ep_text)));
273
274 spin_unlock_irqrestore(&imx21->lock, flags);
275
276 return 0;
277}
278
279static int debug_etd_show(struct seq_file *s, void *v)
280{
281 struct imx21 *imx21 = s->private;
282 struct etd_priv *etd;
283 char buf[60];
284 u32 dword;
285 int i, j;
286 unsigned long flags;
287
288 spin_lock_irqsave(&imx21->lock, flags);
289
290 for (i = 0, etd = imx21->etd; i < USB_NUM_ETD; i++, etd++) {
291 int state = -1;
292 struct urb_priv *urb_priv;
293 if (etd->urb) {
294 urb_priv = etd->urb->hcpriv;
295 if (urb_priv)
296 state = urb_priv->state;
297 }
298
299 seq_printf(s,
300 "etd_num: %d\n"
301 "ep: %s\n"
302 "alloc: %d\n"
303 "len: %d\n"
304 "busy sw: %d\n"
305 "busy hw: %d\n"
306 "urb state: %d\n"
307 "current urb: %p\n",
308
309 i,
310 format_ep(etd->ep, buf, sizeof(buf)),
311 etd->alloc,
312 etd->len,
313 etd->urb != NULL,
314 (readl(imx21->regs + USBH_ETDENSET) & (1 << i)) > 0,
315 state,
316 etd->urb);
317
318 for (j = 0; j < 4; j++) {
319 dword = etd_readl(imx21, i, j);
320 switch (j) {
321 case 0:
322 format_etd_dword0(dword, buf, sizeof(buf));
323 break;
324 case 2:
325 snprintf(buf, sizeof(buf),
326 "cc=0X%02X", dword >> DW2_COMPCODE);
327 break;
328 default:
329 *buf = 0;
330 break;
331 }
332 seq_printf(s,
333 "dword %d: submitted=%08X cur=%08X [%s]\n",
334 j,
335 etd->submitted_dwords[j],
336 dword,
337 buf);
338 }
339 seq_printf(s, "\n");
340 }
341
342 spin_unlock_irqrestore(&imx21->lock, flags);
343
344 return 0;
345}
346
347static void debug_statistics_show_one(struct seq_file *s,
348 const char *name, struct debug_stats *stats)
349{
350 seq_printf(s, "%s:\n"
351 "submitted URBs: %lu\n"
352 "completed OK: %lu\n"
353 "completed failed: %lu\n"
354 "unlinked: %lu\n"
355 "queued for ETD: %lu\n"
356 "queued for DMEM: %lu\n\n",
357 name,
358 stats->submitted,
359 stats->completed_ok,
360 stats->completed_failed,
361 stats->unlinked,
362 stats->queue_etd,
363 stats->queue_dmem);
364}
365
366static int debug_statistics_show(struct seq_file *s, void *v)
367{
368 struct imx21 *imx21 = s->private;
369 unsigned long flags;
370
371 spin_lock_irqsave(&imx21->lock, flags);
372
373 debug_statistics_show_one(s, "nonisoc", &imx21->nonisoc_stats);
374 debug_statistics_show_one(s, "isoc", &imx21->isoc_stats);
375 seq_printf(s, "unblock kludge triggers: %lu\n", imx21->debug_unblocks);
376 spin_unlock_irqrestore(&imx21->lock, flags);
377
378 return 0;
379}
380
381static void debug_isoc_show_one(struct seq_file *s,
382 const char *name, int index, struct debug_isoc_trace *trace)
383{
384 seq_printf(s, "%s %d:\n"
385 "cc=0X%02X\n"
386 "scheduled frame %d (%d)\n"
387 "submittted frame %d (%d)\n"
388 "completed frame %d (%d)\n"
389 "requested length=%d\n"
390 "completed length=%d\n\n",
391 name, index,
392 trace->cc,
393 trace->schedule_frame, trace->schedule_frame & 0xFFFF,
394 trace->submit_frame, trace->submit_frame & 0xFFFF,
395 trace->done_frame, trace->done_frame & 0xFFFF,
396 trace->request_len,
397 trace->done_len);
398}
399
400static int debug_isoc_show(struct seq_file *s, void *v)
401{
402 struct imx21 *imx21 = s->private;
403 struct debug_isoc_trace *trace;
404 unsigned long flags;
405 int i;
406
407 spin_lock_irqsave(&imx21->lock, flags);
408
409 trace = imx21->isoc_trace_failed;
410 for (i = 0; i < ARRAY_SIZE(imx21->isoc_trace_failed); i++, trace++)
411 debug_isoc_show_one(s, "isoc failed", i, trace);
412
413 trace = imx21->isoc_trace;
414 for (i = 0; i < ARRAY_SIZE(imx21->isoc_trace); i++, trace++)
415 debug_isoc_show_one(s, "isoc", i, trace);
416
417 spin_unlock_irqrestore(&imx21->lock, flags);
418
419 return 0;
420}
421
422static int debug_status_open(struct inode *inode, struct file *file)
423{
424 return single_open(file, debug_status_show, inode->i_private);
425}
426
427static int debug_dmem_open(struct inode *inode, struct file *file)
428{
429 return single_open(file, debug_dmem_show, inode->i_private);
430}
431
432static int debug_etd_open(struct inode *inode, struct file *file)
433{
434 return single_open(file, debug_etd_show, inode->i_private);
435}
436
437static int debug_statistics_open(struct inode *inode, struct file *file)
438{
439 return single_open(file, debug_statistics_show, inode->i_private);
440}
441
442static int debug_isoc_open(struct inode *inode, struct file *file)
443{
444 return single_open(file, debug_isoc_show, inode->i_private);
445}
446
447static const struct file_operations debug_status_fops = {
448 .open = debug_status_open,
449 .read = seq_read,
450 .llseek = seq_lseek,
451 .release = single_release,
452};
453
454static const struct file_operations debug_dmem_fops = {
455 .open = debug_dmem_open,
456 .read = seq_read,
457 .llseek = seq_lseek,
458 .release = single_release,
459};
460
461static const struct file_operations debug_etd_fops = {
462 .open = debug_etd_open,
463 .read = seq_read,
464 .llseek = seq_lseek,
465 .release = single_release,
466};
467
468static const struct file_operations debug_statistics_fops = {
469 .open = debug_statistics_open,
470 .read = seq_read,
471 .llseek = seq_lseek,
472 .release = single_release,
473};
474
475static const struct file_operations debug_isoc_fops = {
476 .open = debug_isoc_open,
477 .read = seq_read,
478 .llseek = seq_lseek,
479 .release = single_release,
480};
481
482static void create_debug_files(struct imx21 *imx21)
483{
484 imx21->debug_root = debugfs_create_dir(dev_name(imx21->dev), NULL);
485 if (!imx21->debug_root)
486 goto failed_create_rootdir;
487
488 if (!debugfs_create_file("status", S_IRUGO,
489 imx21->debug_root, imx21, &debug_status_fops))
490 goto failed_create;
491
492 if (!debugfs_create_file("dmem", S_IRUGO,
493 imx21->debug_root, imx21, &debug_dmem_fops))
494 goto failed_create;
495
496 if (!debugfs_create_file("etd", S_IRUGO,
497 imx21->debug_root, imx21, &debug_etd_fops))
498 goto failed_create;
499
500 if (!debugfs_create_file("statistics", S_IRUGO,
501 imx21->debug_root, imx21, &debug_statistics_fops))
502 goto failed_create;
503
504 if (!debugfs_create_file("isoc", S_IRUGO,
505 imx21->debug_root, imx21, &debug_isoc_fops))
506 goto failed_create;
507
508 return;
509
510failed_create:
511 debugfs_remove_recursive(imx21->debug_root);
512
513failed_create_rootdir:
514 imx21->debug_root = NULL;
515}
516
517
518static void remove_debug_files(struct imx21 *imx21)
519{
520 if (imx21->debug_root) {
521 debugfs_remove_recursive(imx21->debug_root);
522 imx21->debug_root = NULL;
523 }
524}
525
526#endif
527
diff --git a/drivers/usb/host/imx21-hcd.c b/drivers/usb/host/imx21-hcd.c
new file mode 100644
index 000000000000..213e270e1c29
--- /dev/null
+++ b/drivers/usb/host/imx21-hcd.c
@@ -0,0 +1,1789 @@
1/*
2 * USB Host Controller Driver for IMX21
3 *
4 * Copyright (C) 2006 Loping Dog Embedded Systems
5 * Copyright (C) 2009 Martin Fuzzey
6 * Originally written by Jay Monkman <jtm@lopingdog.com>
7 * Ported to 2.6.30, debugged and enhanced by Martin Fuzzey
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation,
21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24
25 /*
26 * The i.MX21 USB hardware contains
27 * * 32 transfer descriptors (called ETDs)
28 * * 4Kb of Data memory
29 *
30 * The data memory is shared between the host and fuction controlers
31 * (but this driver only supports the host controler)
32 *
33 * So setting up a transfer involves:
34 * * Allocating a ETD
35 * * Fill in ETD with appropriate information
36 * * Allocating data memory (and putting the offset in the ETD)
37 * * Activate the ETD
38 * * Get interrupt when done.
39 *
40 * An ETD is assigned to each active endpoint.
41 *
42 * Low resource (ETD and Data memory) situations are handled differently for
43 * isochronous and non insosynchronous transactions :
44 *
45 * Non ISOC transfers are queued if either ETDs or Data memory are unavailable
46 *
47 * ISOC transfers use 2 ETDs per endpoint to achieve double buffering.
48 * They allocate both ETDs and Data memory during URB submission
49 * (and fail if unavailable).
50 */
51
52#include <linux/clk.h>
53#include <linux/io.h>
54#include <linux/kernel.h>
55#include <linux/list.h>
56#include <linux/platform_device.h>
57#include <linux/usb.h>
58
59#include "../core/hcd.h"
60#include "imx21-hcd.h"
61
62#ifdef DEBUG
63#define DEBUG_LOG_FRAME(imx21, etd, event) \
64 (etd)->event##_frame = readl((imx21)->regs + USBH_FRMNUB)
65#else
66#define DEBUG_LOG_FRAME(imx21, etd, event) do { } while (0)
67#endif
68
69static const char hcd_name[] = "imx21-hcd";
70
71static inline struct imx21 *hcd_to_imx21(struct usb_hcd *hcd)
72{
73 return (struct imx21 *)hcd->hcd_priv;
74}
75
76
77/* =========================================== */
78/* Hardware access helpers */
79/* =========================================== */
80
81static inline void set_register_bits(struct imx21 *imx21, u32 offset, u32 mask)
82{
83 void __iomem *reg = imx21->regs + offset;
84 writel(readl(reg) | mask, reg);
85}
86
87static inline void clear_register_bits(struct imx21 *imx21,
88 u32 offset, u32 mask)
89{
90 void __iomem *reg = imx21->regs + offset;
91 writel(readl(reg) & ~mask, reg);
92}
93
94static inline void clear_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
95{
96 void __iomem *reg = imx21->regs + offset;
97
98 if (readl(reg) & mask)
99 writel(mask, reg);
100}
101
102static inline void set_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
103{
104 void __iomem *reg = imx21->regs + offset;
105
106 if (!(readl(reg) & mask))
107 writel(mask, reg);
108}
109
110static void etd_writel(struct imx21 *imx21, int etd_num, int dword, u32 value)
111{
112 writel(value, imx21->regs + USB_ETD_DWORD(etd_num, dword));
113}
114
115static u32 etd_readl(struct imx21 *imx21, int etd_num, int dword)
116{
117 return readl(imx21->regs + USB_ETD_DWORD(etd_num, dword));
118}
119
120static inline int wrap_frame(int counter)
121{
122 return counter & 0xFFFF;
123}
124
125static inline int frame_after(int frame, int after)
126{
127 /* handle wrapping like jiffies time_afer */
128 return (s16)((s16)after - (s16)frame) < 0;
129}
130
131static int imx21_hc_get_frame(struct usb_hcd *hcd)
132{
133 struct imx21 *imx21 = hcd_to_imx21(hcd);
134
135 return wrap_frame(readl(imx21->regs + USBH_FRMNUB));
136}
137
138
139#include "imx21-dbg.c"
140
141/* =========================================== */
142/* ETD management */
143/* =========================================== */
144
145static int alloc_etd(struct imx21 *imx21)
146{
147 int i;
148 struct etd_priv *etd = imx21->etd;
149
150 for (i = 0; i < USB_NUM_ETD; i++, etd++) {
151 if (etd->alloc == 0) {
152 memset(etd, 0, sizeof(imx21->etd[0]));
153 etd->alloc = 1;
154 debug_etd_allocated(imx21);
155 return i;
156 }
157 }
158 return -1;
159}
160
161static void disactivate_etd(struct imx21 *imx21, int num)
162{
163 int etd_mask = (1 << num);
164 struct etd_priv *etd = &imx21->etd[num];
165
166 writel(etd_mask, imx21->regs + USBH_ETDENCLR);
167 clear_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
168 writel(etd_mask, imx21->regs + USB_ETDDMACHANLCLR);
169 clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
170
171 etd->active_count = 0;
172
173 DEBUG_LOG_FRAME(imx21, etd, disactivated);
174}
175
176static void reset_etd(struct imx21 *imx21, int num)
177{
178 struct etd_priv *etd = imx21->etd + num;
179 int i;
180
181 disactivate_etd(imx21, num);
182
183 for (i = 0; i < 4; i++)
184 etd_writel(imx21, num, i, 0);
185 etd->urb = NULL;
186 etd->ep = NULL;
187 etd->td = NULL;;
188}
189
190static void free_etd(struct imx21 *imx21, int num)
191{
192 if (num < 0)
193 return;
194
195 if (num >= USB_NUM_ETD) {
196 dev_err(imx21->dev, "BAD etd=%d!\n", num);
197 return;
198 }
199 if (imx21->etd[num].alloc == 0) {
200 dev_err(imx21->dev, "ETD %d already free!\n", num);
201 return;
202 }
203
204 debug_etd_freed(imx21);
205 reset_etd(imx21, num);
206 memset(&imx21->etd[num], 0, sizeof(imx21->etd[0]));
207}
208
209
210static void setup_etd_dword0(struct imx21 *imx21,
211 int etd_num, struct urb *urb, u8 dir, u16 maxpacket)
212{
213 etd_writel(imx21, etd_num, 0,
214 ((u32) usb_pipedevice(urb->pipe)) << DW0_ADDRESS |
215 ((u32) usb_pipeendpoint(urb->pipe) << DW0_ENDPNT) |
216 ((u32) dir << DW0_DIRECT) |
217 ((u32) ((urb->dev->speed == USB_SPEED_LOW) ?
218 1 : 0) << DW0_SPEED) |
219 ((u32) fmt_urb_to_etd[usb_pipetype(urb->pipe)] << DW0_FORMAT) |
220 ((u32) maxpacket << DW0_MAXPKTSIZ));
221}
222
223static void activate_etd(struct imx21 *imx21,
224 int etd_num, dma_addr_t dma, u8 dir)
225{
226 u32 etd_mask = 1 << etd_num;
227 struct etd_priv *etd = &imx21->etd[etd_num];
228
229 clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
230 set_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
231 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
232 clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
233
234 if (dma) {
235 set_register_bits(imx21, USB_ETDDMACHANLCLR, etd_mask);
236 clear_toggle_bit(imx21, USBH_XBUFSTAT, etd_mask);
237 clear_toggle_bit(imx21, USBH_YBUFSTAT, etd_mask);
238 writel(dma, imx21->regs + USB_ETDSMSA(etd_num));
239 set_register_bits(imx21, USB_ETDDMAEN, etd_mask);
240 } else {
241 if (dir != TD_DIR_IN) {
242 /* need to set for ZLP */
243 set_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
244 set_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
245 }
246 }
247
248 DEBUG_LOG_FRAME(imx21, etd, activated);
249
250#ifdef DEBUG
251 if (!etd->active_count) {
252 int i;
253 etd->activated_frame = readl(imx21->regs + USBH_FRMNUB);
254 etd->disactivated_frame = -1;
255 etd->last_int_frame = -1;
256 etd->last_req_frame = -1;
257
258 for (i = 0; i < 4; i++)
259 etd->submitted_dwords[i] = etd_readl(imx21, etd_num, i);
260 }
261#endif
262
263 etd->active_count = 1;
264 writel(etd_mask, imx21->regs + USBH_ETDENSET);
265}
266
267/* =========================================== */
268/* Data memory management */
269/* =========================================== */
270
271static int alloc_dmem(struct imx21 *imx21, unsigned int size,
272 struct usb_host_endpoint *ep)
273{
274 unsigned int offset = 0;
275 struct imx21_dmem_area *area;
276 struct imx21_dmem_area *tmp;
277
278 size += (~size + 1) & 0x3; /* Round to 4 byte multiple */
279
280 if (size > DMEM_SIZE) {
281 dev_err(imx21->dev, "size=%d > DMEM_SIZE(%d)\n",
282 size, DMEM_SIZE);
283 return -EINVAL;
284 }
285
286 list_for_each_entry(tmp, &imx21->dmem_list, list) {
287 if ((size + offset) < offset)
288 goto fail;
289 if ((size + offset) <= tmp->offset)
290 break;
291 offset = tmp->size + tmp->offset;
292 if ((offset + size) > DMEM_SIZE)
293 goto fail;
294 }
295
296 area = kmalloc(sizeof(struct imx21_dmem_area), GFP_ATOMIC);
297 if (area == NULL)
298 return -ENOMEM;
299
300 area->ep = ep;
301 area->offset = offset;
302 area->size = size;
303 list_add_tail(&area->list, &tmp->list);
304 debug_dmem_allocated(imx21, size);
305 return offset;
306
307fail:
308 return -ENOMEM;
309}
310
311/* Memory now available for a queued ETD - activate it */
312static void activate_queued_etd(struct imx21 *imx21,
313 struct etd_priv *etd, u32 dmem_offset)
314{
315 struct urb_priv *urb_priv = etd->urb->hcpriv;
316 int etd_num = etd - &imx21->etd[0];
317 u32 maxpacket = etd_readl(imx21, etd_num, 1) >> DW1_YBUFSRTAD;
318 u8 dir = (etd_readl(imx21, etd_num, 2) >> DW2_DIRPID) & 0x03;
319
320 dev_dbg(imx21->dev, "activating queued ETD %d now DMEM available\n",
321 etd_num);
322 etd_writel(imx21, etd_num, 1,
323 ((dmem_offset + maxpacket) << DW1_YBUFSRTAD) | dmem_offset);
324
325 urb_priv->active = 1;
326 activate_etd(imx21, etd_num, etd->dma_handle, dir);
327}
328
329static void free_dmem(struct imx21 *imx21, int offset)
330{
331 struct imx21_dmem_area *area;
332 struct etd_priv *etd, *tmp;
333 int found = 0;
334
335 list_for_each_entry(area, &imx21->dmem_list, list) {
336 if (area->offset == offset) {
337 debug_dmem_freed(imx21, area->size);
338 list_del(&area->list);
339 kfree(area);
340 found = 1;
341 break;
342 }
343 }
344
345 if (!found) {
346 dev_err(imx21->dev,
347 "Trying to free unallocated DMEM %d\n", offset);
348 return;
349 }
350
351 /* Try again to allocate memory for anything we've queued */
352 list_for_each_entry_safe(etd, tmp, &imx21->queue_for_dmem, queue) {
353 offset = alloc_dmem(imx21, etd->dmem_size, etd->ep);
354 if (offset >= 0) {
355 list_del(&etd->queue);
356 activate_queued_etd(imx21, etd, (u32)offset);
357 }
358 }
359}
360
361static void free_epdmem(struct imx21 *imx21, struct usb_host_endpoint *ep)
362{
363 struct imx21_dmem_area *area, *tmp;
364
365 list_for_each_entry_safe(area, tmp, &imx21->dmem_list, list) {
366 if (area->ep == ep) {
367 dev_err(imx21->dev,
368 "Active DMEM %d for disabled ep=%p\n",
369 area->offset, ep);
370 list_del(&area->list);
371 kfree(area);
372 }
373 }
374}
375
376
377/* =========================================== */
378/* End handling */
379/* =========================================== */
380static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb);
381
382/* Endpoint now idle - release it's ETD(s) or asssign to queued request */
383static void ep_idle(struct imx21 *imx21, struct ep_priv *ep_priv)
384{
385 int etd_num;
386 int i;
387
388 for (i = 0; i < NUM_ISO_ETDS; i++) {
389 etd_num = ep_priv->etd[i];
390 if (etd_num < 0)
391 continue;
392
393 ep_priv->etd[i] = -1;
394 if (list_empty(&imx21->queue_for_etd)) {
395 free_etd(imx21, etd_num);
396 continue;
397 }
398
399 dev_dbg(imx21->dev,
400 "assigning idle etd %d for queued request\n", etd_num);
401 ep_priv = list_first_entry(&imx21->queue_for_etd,
402 struct ep_priv, queue);
403 list_del(&ep_priv->queue);
404 reset_etd(imx21, etd_num);
405 ep_priv->waiting_etd = 0;
406 ep_priv->etd[i] = etd_num;
407
408 if (list_empty(&ep_priv->ep->urb_list)) {
409 dev_err(imx21->dev, "No urb for queued ep!\n");
410 continue;
411 }
412 schedule_nonisoc_etd(imx21, list_first_entry(
413 &ep_priv->ep->urb_list, struct urb, urb_list));
414 }
415}
416
417static void urb_done(struct usb_hcd *hcd, struct urb *urb, int status)
418__releases(imx21->lock)
419__acquires(imx21->lock)
420{
421 struct imx21 *imx21 = hcd_to_imx21(hcd);
422 struct ep_priv *ep_priv = urb->ep->hcpriv;
423 struct urb_priv *urb_priv = urb->hcpriv;
424
425 debug_urb_completed(imx21, urb, status);
426 dev_vdbg(imx21->dev, "urb %p done %d\n", urb, status);
427
428 kfree(urb_priv->isoc_td);
429 kfree(urb->hcpriv);
430 urb->hcpriv = NULL;
431 usb_hcd_unlink_urb_from_ep(hcd, urb);
432 spin_unlock(&imx21->lock);
433 usb_hcd_giveback_urb(hcd, urb, status);
434 spin_lock(&imx21->lock);
435 if (list_empty(&ep_priv->ep->urb_list))
436 ep_idle(imx21, ep_priv);
437}
438
439/* =========================================== */
440/* ISOC Handling ... */
441/* =========================================== */
442
443static void schedule_isoc_etds(struct usb_hcd *hcd,
444 struct usb_host_endpoint *ep)
445{
446 struct imx21 *imx21 = hcd_to_imx21(hcd);
447 struct ep_priv *ep_priv = ep->hcpriv;
448 struct etd_priv *etd;
449 struct urb_priv *urb_priv;
450 struct td *td;
451 int etd_num;
452 int i;
453 int cur_frame;
454 u8 dir;
455
456 for (i = 0; i < NUM_ISO_ETDS; i++) {
457too_late:
458 if (list_empty(&ep_priv->td_list))
459 break;
460
461 etd_num = ep_priv->etd[i];
462 if (etd_num < 0)
463 break;
464
465 etd = &imx21->etd[etd_num];
466 if (etd->urb)
467 continue;
468
469 td = list_entry(ep_priv->td_list.next, struct td, list);
470 list_del(&td->list);
471 urb_priv = td->urb->hcpriv;
472
473 cur_frame = imx21_hc_get_frame(hcd);
474 if (frame_after(cur_frame, td->frame)) {
475 dev_dbg(imx21->dev, "isoc too late frame %d > %d\n",
476 cur_frame, td->frame);
477 urb_priv->isoc_status = -EXDEV;
478 td->urb->iso_frame_desc[
479 td->isoc_index].actual_length = 0;
480 td->urb->iso_frame_desc[td->isoc_index].status = -EXDEV;
481 if (--urb_priv->isoc_remaining == 0)
482 urb_done(hcd, td->urb, urb_priv->isoc_status);
483 goto too_late;
484 }
485
486 urb_priv->active = 1;
487 etd->td = td;
488 etd->ep = td->ep;
489 etd->urb = td->urb;
490 etd->len = td->len;
491
492 debug_isoc_submitted(imx21, cur_frame, td);
493
494 dir = usb_pipeout(td->urb->pipe) ? TD_DIR_OUT : TD_DIR_IN;
495 setup_etd_dword0(imx21, etd_num, td->urb, dir, etd->dmem_size);
496 etd_writel(imx21, etd_num, 1, etd->dmem_offset);
497 etd_writel(imx21, etd_num, 2,
498 (TD_NOTACCESSED << DW2_COMPCODE) |
499 ((td->frame & 0xFFFF) << DW2_STARTFRM));
500 etd_writel(imx21, etd_num, 3,
501 (TD_NOTACCESSED << DW3_COMPCODE0) |
502 (td->len << DW3_PKTLEN0));
503
504 activate_etd(imx21, etd_num, td->data, dir);
505 }
506}
507
508static void isoc_etd_done(struct usb_hcd *hcd, struct urb *urb, int etd_num)
509{
510 struct imx21 *imx21 = hcd_to_imx21(hcd);
511 int etd_mask = 1 << etd_num;
512 struct urb_priv *urb_priv = urb->hcpriv;
513 struct etd_priv *etd = imx21->etd + etd_num;
514 struct td *td = etd->td;
515 struct usb_host_endpoint *ep = etd->ep;
516 int isoc_index = td->isoc_index;
517 unsigned int pipe = urb->pipe;
518 int dir_in = usb_pipein(pipe);
519 int cc;
520 int bytes_xfrd;
521
522 disactivate_etd(imx21, etd_num);
523
524 cc = (etd_readl(imx21, etd_num, 3) >> DW3_COMPCODE0) & 0xf;
525 bytes_xfrd = etd_readl(imx21, etd_num, 3) & 0x3ff;
526
527 /* Input doesn't always fill the buffer, don't generate an error
528 * when this happens.
529 */
530 if (dir_in && (cc == TD_DATAUNDERRUN))
531 cc = TD_CC_NOERROR;
532
533 if (cc == TD_NOTACCESSED)
534 bytes_xfrd = 0;
535
536 debug_isoc_completed(imx21,
537 imx21_hc_get_frame(hcd), td, cc, bytes_xfrd);
538 if (cc) {
539 urb_priv->isoc_status = -EXDEV;
540 dev_dbg(imx21->dev,
541 "bad iso cc=0x%X frame=%d sched frame=%d "
542 "cnt=%d len=%d urb=%p etd=%d index=%d\n",
543 cc, imx21_hc_get_frame(hcd), td->frame,
544 bytes_xfrd, td->len, urb, etd_num, isoc_index);
545 }
546
547 if (dir_in)
548 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
549
550 urb->actual_length += bytes_xfrd;
551 urb->iso_frame_desc[isoc_index].actual_length = bytes_xfrd;
552 urb->iso_frame_desc[isoc_index].status = cc_to_error[cc];
553
554 etd->td = NULL;
555 etd->urb = NULL;
556 etd->ep = NULL;
557
558 if (--urb_priv->isoc_remaining == 0)
559 urb_done(hcd, urb, urb_priv->isoc_status);
560
561 schedule_isoc_etds(hcd, ep);
562}
563
564static struct ep_priv *alloc_isoc_ep(
565 struct imx21 *imx21, struct usb_host_endpoint *ep)
566{
567 struct ep_priv *ep_priv;
568 int i;
569
570 ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC);
571 if (ep_priv == NULL)
572 return NULL;
573
574 /* Allocate the ETDs */
575 for (i = 0; i < NUM_ISO_ETDS; i++) {
576 ep_priv->etd[i] = alloc_etd(imx21);
577 if (ep_priv->etd[i] < 0) {
578 int j;
579 dev_err(imx21->dev, "isoc: Couldn't allocate etd\n");
580 for (j = 0; j < i; j++)
581 free_etd(imx21, ep_priv->etd[j]);
582 goto alloc_etd_failed;
583 }
584 imx21->etd[ep_priv->etd[i]].ep = ep;
585 }
586
587 INIT_LIST_HEAD(&ep_priv->td_list);
588 ep_priv->ep = ep;
589 ep->hcpriv = ep_priv;
590 return ep_priv;
591
592alloc_etd_failed:
593 kfree(ep_priv);
594 return NULL;
595}
596
597static int imx21_hc_urb_enqueue_isoc(struct usb_hcd *hcd,
598 struct usb_host_endpoint *ep,
599 struct urb *urb, gfp_t mem_flags)
600{
601 struct imx21 *imx21 = hcd_to_imx21(hcd);
602 struct urb_priv *urb_priv;
603 unsigned long flags;
604 struct ep_priv *ep_priv;
605 struct td *td = NULL;
606 int i;
607 int ret;
608 int cur_frame;
609 u16 maxpacket;
610
611 urb_priv = kzalloc(sizeof(struct urb_priv), mem_flags);
612 if (urb_priv == NULL)
613 return -ENOMEM;
614
615 urb_priv->isoc_td = kzalloc(
616 sizeof(struct td) * urb->number_of_packets, mem_flags);
617 if (urb_priv->isoc_td == NULL) {
618 ret = -ENOMEM;
619 goto alloc_td_failed;
620 }
621
622 spin_lock_irqsave(&imx21->lock, flags);
623
624 if (ep->hcpriv == NULL) {
625 ep_priv = alloc_isoc_ep(imx21, ep);
626 if (ep_priv == NULL) {
627 ret = -ENOMEM;
628 goto alloc_ep_failed;
629 }
630 } else {
631 ep_priv = ep->hcpriv;
632 }
633
634 ret = usb_hcd_link_urb_to_ep(hcd, urb);
635 if (ret)
636 goto link_failed;
637
638 urb->status = -EINPROGRESS;
639 urb->actual_length = 0;
640 urb->error_count = 0;
641 urb->hcpriv = urb_priv;
642 urb_priv->ep = ep;
643
644 /* allocate data memory for largest packets if not already done */
645 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
646 for (i = 0; i < NUM_ISO_ETDS; i++) {
647 struct etd_priv *etd = &imx21->etd[ep_priv->etd[i]];
648
649 if (etd->dmem_size > 0 && etd->dmem_size < maxpacket) {
650 /* not sure if this can really occur.... */
651 dev_err(imx21->dev, "increasing isoc buffer %d->%d\n",
652 etd->dmem_size, maxpacket);
653 ret = -EMSGSIZE;
654 goto alloc_dmem_failed;
655 }
656
657 if (etd->dmem_size == 0) {
658 etd->dmem_offset = alloc_dmem(imx21, maxpacket, ep);
659 if (etd->dmem_offset < 0) {
660 dev_dbg(imx21->dev, "failed alloc isoc dmem\n");
661 ret = -EAGAIN;
662 goto alloc_dmem_failed;
663 }
664 etd->dmem_size = maxpacket;
665 }
666 }
667
668 /* calculate frame */
669 cur_frame = imx21_hc_get_frame(hcd);
670 if (urb->transfer_flags & URB_ISO_ASAP) {
671 if (list_empty(&ep_priv->td_list))
672 urb->start_frame = cur_frame + 5;
673 else
674 urb->start_frame = list_entry(
675 ep_priv->td_list.prev,
676 struct td, list)->frame + urb->interval;
677 }
678 urb->start_frame = wrap_frame(urb->start_frame);
679 if (frame_after(cur_frame, urb->start_frame)) {
680 dev_dbg(imx21->dev,
681 "enqueue: adjusting iso start %d (cur=%d) asap=%d\n",
682 urb->start_frame, cur_frame,
683 (urb->transfer_flags & URB_ISO_ASAP) != 0);
684 urb->start_frame = wrap_frame(cur_frame + 1);
685 }
686
687 /* set up transfers */
688 td = urb_priv->isoc_td;
689 for (i = 0; i < urb->number_of_packets; i++, td++) {
690 td->ep = ep;
691 td->urb = urb;
692 td->len = urb->iso_frame_desc[i].length;
693 td->isoc_index = i;
694 td->frame = wrap_frame(urb->start_frame + urb->interval * i);
695 td->data = urb->transfer_dma + urb->iso_frame_desc[i].offset;
696 list_add_tail(&td->list, &ep_priv->td_list);
697 }
698
699 urb_priv->isoc_remaining = urb->number_of_packets;
700 dev_vdbg(imx21->dev, "setup %d packets for iso frame %d->%d\n",
701 urb->number_of_packets, urb->start_frame, td->frame);
702
703 debug_urb_submitted(imx21, urb);
704 schedule_isoc_etds(hcd, ep);
705
706 spin_unlock_irqrestore(&imx21->lock, flags);
707 return 0;
708
709alloc_dmem_failed:
710 usb_hcd_unlink_urb_from_ep(hcd, urb);
711
712link_failed:
713alloc_ep_failed:
714 spin_unlock_irqrestore(&imx21->lock, flags);
715 kfree(urb_priv->isoc_td);
716
717alloc_td_failed:
718 kfree(urb_priv);
719 return ret;
720}
721
722static void dequeue_isoc_urb(struct imx21 *imx21,
723 struct urb *urb, struct ep_priv *ep_priv)
724{
725 struct urb_priv *urb_priv = urb->hcpriv;
726 struct td *td, *tmp;
727 int i;
728
729 if (urb_priv->active) {
730 for (i = 0; i < NUM_ISO_ETDS; i++) {
731 int etd_num = ep_priv->etd[i];
732 if (etd_num != -1 && imx21->etd[etd_num].urb == urb) {
733 struct etd_priv *etd = imx21->etd + etd_num;
734
735 reset_etd(imx21, etd_num);
736 if (etd->dmem_size)
737 free_dmem(imx21, etd->dmem_offset);
738 etd->dmem_size = 0;
739 }
740 }
741 }
742
743 list_for_each_entry_safe(td, tmp, &ep_priv->td_list, list) {
744 if (td->urb == urb) {
745 dev_vdbg(imx21->dev, "removing td %p\n", td);
746 list_del(&td->list);
747 }
748 }
749}
750
751/* =========================================== */
752/* NON ISOC Handling ... */
753/* =========================================== */
754
755static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb)
756{
757 unsigned int pipe = urb->pipe;
758 struct urb_priv *urb_priv = urb->hcpriv;
759 struct ep_priv *ep_priv = urb_priv->ep->hcpriv;
760 int state = urb_priv->state;
761 int etd_num = ep_priv->etd[0];
762 struct etd_priv *etd;
763 int dmem_offset;
764 u32 count;
765 u16 etd_buf_size;
766 u16 maxpacket;
767 u8 dir;
768 u8 bufround;
769 u8 datatoggle;
770 u8 interval = 0;
771 u8 relpolpos = 0;
772
773 if (etd_num < 0) {
774 dev_err(imx21->dev, "No valid ETD\n");
775 return;
776 }
777 if (readl(imx21->regs + USBH_ETDENSET) & (1 << etd_num))
778 dev_err(imx21->dev, "submitting to active ETD %d\n", etd_num);
779
780 etd = &imx21->etd[etd_num];
781 maxpacket = usb_maxpacket(urb->dev, pipe, usb_pipeout(pipe));
782 if (!maxpacket)
783 maxpacket = 8;
784
785 if (usb_pipecontrol(pipe) && (state != US_CTRL_DATA)) {
786 if (state == US_CTRL_SETUP) {
787 dir = TD_DIR_SETUP;
788 etd->dma_handle = urb->setup_dma;
789 bufround = 0;
790 count = 8;
791 datatoggle = TD_TOGGLE_DATA0;
792 } else { /* US_CTRL_ACK */
793 dir = usb_pipeout(pipe) ? TD_DIR_IN : TD_DIR_OUT;
794 etd->dma_handle = urb->transfer_dma;
795 bufround = 0;
796 count = 0;
797 datatoggle = TD_TOGGLE_DATA1;
798 }
799 } else {
800 dir = usb_pipeout(pipe) ? TD_DIR_OUT : TD_DIR_IN;
801 bufround = (dir == TD_DIR_IN) ? 1 : 0;
802 etd->dma_handle = urb->transfer_dma;
803 if (usb_pipebulk(pipe) && (state == US_BULK0))
804 count = 0;
805 else
806 count = urb->transfer_buffer_length;
807
808 if (usb_pipecontrol(pipe)) {
809 datatoggle = TD_TOGGLE_DATA1;
810 } else {
811 if (usb_gettoggle(
812 urb->dev,
813 usb_pipeendpoint(urb->pipe),
814 usb_pipeout(urb->pipe)))
815 datatoggle = TD_TOGGLE_DATA1;
816 else
817 datatoggle = TD_TOGGLE_DATA0;
818 }
819 }
820
821 etd->urb = urb;
822 etd->ep = urb_priv->ep;
823 etd->len = count;
824
825 if (usb_pipeint(pipe)) {
826 interval = urb->interval;
827 relpolpos = (readl(imx21->regs + USBH_FRMNUB) + 1) & 0xff;
828 }
829
830 /* Write ETD to device memory */
831 setup_etd_dword0(imx21, etd_num, urb, dir, maxpacket);
832
833 etd_writel(imx21, etd_num, 2,
834 (u32) interval << DW2_POLINTERV |
835 ((u32) relpolpos << DW2_RELPOLPOS) |
836 ((u32) dir << DW2_DIRPID) |
837 ((u32) bufround << DW2_BUFROUND) |
838 ((u32) datatoggle << DW2_DATATOG) |
839 ((u32) TD_NOTACCESSED << DW2_COMPCODE));
840
841 /* DMA will always transfer buffer size even if TOBYCNT in DWORD3
842 is smaller. Make sure we don't overrun the buffer!
843 */
844 if (count && count < maxpacket)
845 etd_buf_size = count;
846 else
847 etd_buf_size = maxpacket;
848
849 etd_writel(imx21, etd_num, 3,
850 ((u32) (etd_buf_size - 1) << DW3_BUFSIZE) | (u32) count);
851
852 if (!count)
853 etd->dma_handle = 0;
854
855 /* allocate x and y buffer space at once */
856 etd->dmem_size = (count > maxpacket) ? maxpacket * 2 : maxpacket;
857 dmem_offset = alloc_dmem(imx21, etd->dmem_size, urb_priv->ep);
858 if (dmem_offset < 0) {
859 /* Setup everything we can in HW and update when we get DMEM */
860 etd_writel(imx21, etd_num, 1, (u32)maxpacket << 16);
861
862 dev_dbg(imx21->dev, "Queuing etd %d for DMEM\n", etd_num);
863 debug_urb_queued_for_dmem(imx21, urb);
864 list_add_tail(&etd->queue, &imx21->queue_for_dmem);
865 return;
866 }
867
868 etd_writel(imx21, etd_num, 1,
869 (((u32) dmem_offset + (u32) maxpacket) << DW1_YBUFSRTAD) |
870 (u32) dmem_offset);
871
872 urb_priv->active = 1;
873
874 /* enable the ETD to kick off transfer */
875 dev_vdbg(imx21->dev, "Activating etd %d for %d bytes %s\n",
876 etd_num, count, dir != TD_DIR_IN ? "out" : "in");
877 activate_etd(imx21, etd_num, etd->dma_handle, dir);
878
879}
880
881static void nonisoc_etd_done(struct usb_hcd *hcd, struct urb *urb, int etd_num)
882{
883 struct imx21 *imx21 = hcd_to_imx21(hcd);
884 struct etd_priv *etd = &imx21->etd[etd_num];
885 u32 etd_mask = 1 << etd_num;
886 struct urb_priv *urb_priv = urb->hcpriv;
887 int dir;
888 u16 xbufaddr;
889 int cc;
890 u32 bytes_xfrd;
891 int etd_done;
892
893 disactivate_etd(imx21, etd_num);
894
895 dir = (etd_readl(imx21, etd_num, 0) >> DW0_DIRECT) & 0x3;
896 xbufaddr = etd_readl(imx21, etd_num, 1) & 0xffff;
897 cc = (etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE) & 0xf;
898 bytes_xfrd = etd->len - (etd_readl(imx21, etd_num, 3) & 0x1fffff);
899
900 /* save toggle carry */
901 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
902 usb_pipeout(urb->pipe),
903 (etd_readl(imx21, etd_num, 0) >> DW0_TOGCRY) & 0x1);
904
905 if (dir == TD_DIR_IN) {
906 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
907 clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
908 }
909 free_dmem(imx21, xbufaddr);
910
911 urb->error_count = 0;
912 if (!(urb->transfer_flags & URB_SHORT_NOT_OK)
913 && (cc == TD_DATAUNDERRUN))
914 cc = TD_CC_NOERROR;
915
916 if (cc != 0)
917 dev_vdbg(imx21->dev, "cc is 0x%x\n", cc);
918
919 etd_done = (cc_to_error[cc] != 0); /* stop if error */
920
921 switch (usb_pipetype(urb->pipe)) {
922 case PIPE_CONTROL:
923 switch (urb_priv->state) {
924 case US_CTRL_SETUP:
925 if (urb->transfer_buffer_length > 0)
926 urb_priv->state = US_CTRL_DATA;
927 else
928 urb_priv->state = US_CTRL_ACK;
929 break;
930 case US_CTRL_DATA:
931 urb->actual_length += bytes_xfrd;
932 urb_priv->state = US_CTRL_ACK;
933 break;
934 case US_CTRL_ACK:
935 etd_done = 1;
936 break;
937 default:
938 dev_err(imx21->dev,
939 "Invalid pipe state %d\n", urb_priv->state);
940 etd_done = 1;
941 break;
942 }
943 break;
944
945 case PIPE_BULK:
946 urb->actual_length += bytes_xfrd;
947 if ((urb_priv->state == US_BULK)
948 && (urb->transfer_flags & URB_ZERO_PACKET)
949 && urb->transfer_buffer_length > 0
950 && ((urb->transfer_buffer_length %
951 usb_maxpacket(urb->dev, urb->pipe,
952 usb_pipeout(urb->pipe))) == 0)) {
953 /* need a 0-packet */
954 urb_priv->state = US_BULK0;
955 } else {
956 etd_done = 1;
957 }
958 break;
959
960 case PIPE_INTERRUPT:
961 urb->actual_length += bytes_xfrd;
962 etd_done = 1;
963 break;
964 }
965
966 if (!etd_done) {
967 dev_vdbg(imx21->dev, "next state=%d\n", urb_priv->state);
968 schedule_nonisoc_etd(imx21, urb);
969 } else {
970 struct usb_host_endpoint *ep = urb->ep;
971
972 urb_done(hcd, urb, cc_to_error[cc]);
973 etd->urb = NULL;
974
975 if (!list_empty(&ep->urb_list)) {
976 urb = list_first_entry(&ep->urb_list,
977 struct urb, urb_list);
978 dev_vdbg(imx21->dev, "next URB %p\n", urb);
979 schedule_nonisoc_etd(imx21, urb);
980 }
981 }
982}
983
984static struct ep_priv *alloc_ep(void)
985{
986 int i;
987 struct ep_priv *ep_priv;
988
989 ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC);
990 if (!ep_priv)
991 return NULL;
992
993 for (i = 0; i < NUM_ISO_ETDS; ++i)
994 ep_priv->etd[i] = -1;
995
996 return ep_priv;
997}
998
999static int imx21_hc_urb_enqueue(struct usb_hcd *hcd,
1000 struct urb *urb, gfp_t mem_flags)
1001{
1002 struct imx21 *imx21 = hcd_to_imx21(hcd);
1003 struct usb_host_endpoint *ep = urb->ep;
1004 struct urb_priv *urb_priv;
1005 struct ep_priv *ep_priv;
1006 struct etd_priv *etd;
1007 int ret;
1008 unsigned long flags;
1009 int new_ep = 0;
1010
1011 dev_vdbg(imx21->dev,
1012 "enqueue urb=%p ep=%p len=%d "
1013 "buffer=%p dma=%08X setupBuf=%p setupDma=%08X\n",
1014 urb, ep,
1015 urb->transfer_buffer_length,
1016 urb->transfer_buffer, urb->transfer_dma,
1017 urb->setup_packet, urb->setup_dma);
1018
1019 if (usb_pipeisoc(urb->pipe))
1020 return imx21_hc_urb_enqueue_isoc(hcd, ep, urb, mem_flags);
1021
1022 urb_priv = kzalloc(sizeof(struct urb_priv), mem_flags);
1023 if (!urb_priv)
1024 return -ENOMEM;
1025
1026 spin_lock_irqsave(&imx21->lock, flags);
1027
1028 ep_priv = ep->hcpriv;
1029 if (ep_priv == NULL) {
1030 ep_priv = alloc_ep();
1031 if (!ep_priv) {
1032 ret = -ENOMEM;
1033 goto failed_alloc_ep;
1034 }
1035 ep->hcpriv = ep_priv;
1036 ep_priv->ep = ep;
1037 new_ep = 1;
1038 }
1039
1040 ret = usb_hcd_link_urb_to_ep(hcd, urb);
1041 if (ret)
1042 goto failed_link;
1043
1044 urb->status = -EINPROGRESS;
1045 urb->actual_length = 0;
1046 urb->error_count = 0;
1047 urb->hcpriv = urb_priv;
1048 urb_priv->ep = ep;
1049
1050 switch (usb_pipetype(urb->pipe)) {
1051 case PIPE_CONTROL:
1052 urb_priv->state = US_CTRL_SETUP;
1053 break;
1054 case PIPE_BULK:
1055 urb_priv->state = US_BULK;
1056 break;
1057 }
1058
1059 debug_urb_submitted(imx21, urb);
1060 if (ep_priv->etd[0] < 0) {
1061 if (ep_priv->waiting_etd) {
1062 dev_dbg(imx21->dev,
1063 "no ETD available already queued %p\n",
1064 ep_priv);
1065 debug_urb_queued_for_etd(imx21, urb);
1066 goto out;
1067 }
1068 ep_priv->etd[0] = alloc_etd(imx21);
1069 if (ep_priv->etd[0] < 0) {
1070 dev_dbg(imx21->dev,
1071 "no ETD available queueing %p\n", ep_priv);
1072 debug_urb_queued_for_etd(imx21, urb);
1073 list_add_tail(&ep_priv->queue, &imx21->queue_for_etd);
1074 ep_priv->waiting_etd = 1;
1075 goto out;
1076 }
1077 }
1078
1079 /* Schedule if no URB already active for this endpoint */
1080 etd = &imx21->etd[ep_priv->etd[0]];
1081 if (etd->urb == NULL) {
1082 DEBUG_LOG_FRAME(imx21, etd, last_req);
1083 schedule_nonisoc_etd(imx21, urb);
1084 }
1085
1086out:
1087 spin_unlock_irqrestore(&imx21->lock, flags);
1088 return 0;
1089
1090failed_link:
1091failed_alloc_ep:
1092 spin_unlock_irqrestore(&imx21->lock, flags);
1093 kfree(urb_priv);
1094 return ret;
1095}
1096
1097static int imx21_hc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1098 int status)
1099{
1100 struct imx21 *imx21 = hcd_to_imx21(hcd);
1101 unsigned long flags;
1102 struct usb_host_endpoint *ep;
1103 struct ep_priv *ep_priv;
1104 struct urb_priv *urb_priv = urb->hcpriv;
1105 int ret = -EINVAL;
1106
1107 dev_vdbg(imx21->dev, "dequeue urb=%p iso=%d status=%d\n",
1108 urb, usb_pipeisoc(urb->pipe), status);
1109
1110 spin_lock_irqsave(&imx21->lock, flags);
1111
1112 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1113 if (ret)
1114 goto fail;
1115 ep = urb_priv->ep;
1116 ep_priv = ep->hcpriv;
1117
1118 debug_urb_unlinked(imx21, urb);
1119
1120 if (usb_pipeisoc(urb->pipe)) {
1121 dequeue_isoc_urb(imx21, urb, ep_priv);
1122 schedule_isoc_etds(hcd, ep);
1123 } else if (urb_priv->active) {
1124 int etd_num = ep_priv->etd[0];
1125 if (etd_num != -1) {
1126 disactivate_etd(imx21, etd_num);
1127 free_dmem(imx21, etd_readl(imx21, etd_num, 1) & 0xffff);
1128 imx21->etd[etd_num].urb = NULL;
1129 }
1130 }
1131
1132 urb_done(hcd, urb, status);
1133
1134 spin_unlock_irqrestore(&imx21->lock, flags);
1135 return 0;
1136
1137fail:
1138 spin_unlock_irqrestore(&imx21->lock, flags);
1139 return ret;
1140}
1141
1142/* =========================================== */
1143/* Interrupt dispatch */
1144/* =========================================== */
1145
1146static void process_etds(struct usb_hcd *hcd, struct imx21 *imx21, int sof)
1147{
1148 int etd_num;
1149 int enable_sof_int = 0;
1150 unsigned long flags;
1151
1152 spin_lock_irqsave(&imx21->lock, flags);
1153
1154 for (etd_num = 0; etd_num < USB_NUM_ETD; etd_num++) {
1155 u32 etd_mask = 1 << etd_num;
1156 u32 enabled = readl(imx21->regs + USBH_ETDENSET) & etd_mask;
1157 u32 done = readl(imx21->regs + USBH_ETDDONESTAT) & etd_mask;
1158 struct etd_priv *etd = &imx21->etd[etd_num];
1159
1160
1161 if (done) {
1162 DEBUG_LOG_FRAME(imx21, etd, last_int);
1163 } else {
1164/*
1165 * Kludge warning!
1166 *
1167 * When multiple transfers are using the bus we sometimes get into a state
1168 * where the transfer has completed (the CC field of the ETD is != 0x0F),
1169 * the ETD has self disabled but the ETDDONESTAT flag is not set
1170 * (and hence no interrupt occurs).
1171 * This causes the transfer in question to hang.
1172 * The kludge below checks for this condition at each SOF and processes any
1173 * blocked ETDs (after an arbitary 10 frame wait)
1174 *
1175 * With a single active transfer the usbtest test suite will run for days
1176 * without the kludge.
1177 * With other bus activity (eg mass storage) even just test1 will hang without
1178 * the kludge.
1179 */
1180 u32 dword0;
1181 int cc;
1182
1183 if (etd->active_count && !enabled) /* suspicious... */
1184 enable_sof_int = 1;
1185
1186 if (!sof || enabled || !etd->active_count)
1187 continue;
1188
1189 cc = etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE;
1190 if (cc == TD_NOTACCESSED)
1191 continue;
1192
1193 if (++etd->active_count < 10)
1194 continue;
1195
1196 dword0 = etd_readl(imx21, etd_num, 0);
1197 dev_dbg(imx21->dev,
1198 "unblock ETD %d dev=0x%X ep=0x%X cc=0x%02X!\n",
1199 etd_num, dword0 & 0x7F,
1200 (dword0 >> DW0_ENDPNT) & 0x0F,
1201 cc);
1202
1203#ifdef DEBUG
1204 dev_dbg(imx21->dev,
1205 "frame: act=%d disact=%d"
1206 " int=%d req=%d cur=%d\n",
1207 etd->activated_frame,
1208 etd->disactivated_frame,
1209 etd->last_int_frame,
1210 etd->last_req_frame,
1211 readl(imx21->regs + USBH_FRMNUB));
1212 imx21->debug_unblocks++;
1213#endif
1214 etd->active_count = 0;
1215/* End of kludge */
1216 }
1217
1218 if (etd->ep == NULL || etd->urb == NULL) {
1219 dev_dbg(imx21->dev,
1220 "Interrupt for unexpected etd %d"
1221 " ep=%p urb=%p\n",
1222 etd_num, etd->ep, etd->urb);
1223 disactivate_etd(imx21, etd_num);
1224 continue;
1225 }
1226
1227 if (usb_pipeisoc(etd->urb->pipe))
1228 isoc_etd_done(hcd, etd->urb, etd_num);
1229 else
1230 nonisoc_etd_done(hcd, etd->urb, etd_num);
1231 }
1232
1233 /* only enable SOF interrupt if it may be needed for the kludge */
1234 if (enable_sof_int)
1235 set_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
1236 else
1237 clear_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
1238
1239
1240 spin_unlock_irqrestore(&imx21->lock, flags);
1241}
1242
1243static irqreturn_t imx21_irq(struct usb_hcd *hcd)
1244{
1245 struct imx21 *imx21 = hcd_to_imx21(hcd);
1246 u32 ints = readl(imx21->regs + USBH_SYSISR);
1247
1248 if (ints & USBH_SYSIEN_HERRINT)
1249 dev_dbg(imx21->dev, "Scheduling error\n");
1250
1251 if (ints & USBH_SYSIEN_SORINT)
1252 dev_dbg(imx21->dev, "Scheduling overrun\n");
1253
1254 if (ints & (USBH_SYSISR_DONEINT | USBH_SYSISR_SOFINT))
1255 process_etds(hcd, imx21, ints & USBH_SYSISR_SOFINT);
1256
1257 writel(ints, imx21->regs + USBH_SYSISR);
1258 return IRQ_HANDLED;
1259}
1260
1261static void imx21_hc_endpoint_disable(struct usb_hcd *hcd,
1262 struct usb_host_endpoint *ep)
1263{
1264 struct imx21 *imx21 = hcd_to_imx21(hcd);
1265 unsigned long flags;
1266 struct ep_priv *ep_priv;
1267 int i;
1268
1269 if (ep == NULL)
1270 return;
1271
1272 spin_lock_irqsave(&imx21->lock, flags);
1273 ep_priv = ep->hcpriv;
1274 dev_vdbg(imx21->dev, "disable ep=%p, ep->hcpriv=%p\n", ep, ep_priv);
1275
1276 if (!list_empty(&ep->urb_list))
1277 dev_dbg(imx21->dev, "ep's URB list is not empty\n");
1278
1279 if (ep_priv != NULL) {
1280 for (i = 0; i < NUM_ISO_ETDS; i++) {
1281 if (ep_priv->etd[i] > -1)
1282 dev_dbg(imx21->dev, "free etd %d for disable\n",
1283 ep_priv->etd[i]);
1284
1285 free_etd(imx21, ep_priv->etd[i]);
1286 }
1287 kfree(ep_priv);
1288 ep->hcpriv = NULL;
1289 }
1290
1291 for (i = 0; i < USB_NUM_ETD; i++) {
1292 if (imx21->etd[i].alloc && imx21->etd[i].ep == ep) {
1293 dev_err(imx21->dev,
1294 "Active etd %d for disabled ep=%p!\n", i, ep);
1295 free_etd(imx21, i);
1296 }
1297 }
1298 free_epdmem(imx21, ep);
1299 spin_unlock_irqrestore(&imx21->lock, flags);
1300}
1301
1302/* =========================================== */
1303/* Hub handling */
1304/* =========================================== */
1305
1306static int get_hub_descriptor(struct usb_hcd *hcd,
1307 struct usb_hub_descriptor *desc)
1308{
1309 struct imx21 *imx21 = hcd_to_imx21(hcd);
1310 desc->bDescriptorType = 0x29; /* HUB descriptor */
1311 desc->bHubContrCurrent = 0;
1312
1313 desc->bNbrPorts = readl(imx21->regs + USBH_ROOTHUBA)
1314 & USBH_ROOTHUBA_NDNSTMPRT_MASK;
1315 desc->bDescLength = 9;
1316 desc->bPwrOn2PwrGood = 0;
1317 desc->wHubCharacteristics = (__force __u16) cpu_to_le16(
1318 0x0002 | /* No power switching */
1319 0x0010 | /* No over current protection */
1320 0);
1321
1322 desc->bitmap[0] = 1 << 1;
1323 desc->bitmap[1] = ~0;
1324 return 0;
1325}
1326
1327static int imx21_hc_hub_status_data(struct usb_hcd *hcd, char *buf)
1328{
1329 struct imx21 *imx21 = hcd_to_imx21(hcd);
1330 int ports;
1331 int changed = 0;
1332 int i;
1333 unsigned long flags;
1334
1335 spin_lock_irqsave(&imx21->lock, flags);
1336 ports = readl(imx21->regs + USBH_ROOTHUBA)
1337 & USBH_ROOTHUBA_NDNSTMPRT_MASK;
1338 if (ports > 7) {
1339 ports = 7;
1340 dev_err(imx21->dev, "ports %d > 7\n", ports);
1341 }
1342 for (i = 0; i < ports; i++) {
1343 if (readl(imx21->regs + USBH_PORTSTAT(i)) &
1344 (USBH_PORTSTAT_CONNECTSC |
1345 USBH_PORTSTAT_PRTENBLSC |
1346 USBH_PORTSTAT_PRTSTATSC |
1347 USBH_PORTSTAT_OVRCURIC |
1348 USBH_PORTSTAT_PRTRSTSC)) {
1349
1350 changed = 1;
1351 buf[0] |= 1 << (i + 1);
1352 }
1353 }
1354 spin_unlock_irqrestore(&imx21->lock, flags);
1355
1356 if (changed)
1357 dev_info(imx21->dev, "Hub status changed\n");
1358 return changed;
1359}
1360
1361static int imx21_hc_hub_control(struct usb_hcd *hcd,
1362 u16 typeReq,
1363 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1364{
1365 struct imx21 *imx21 = hcd_to_imx21(hcd);
1366 int rc = 0;
1367 u32 status_write = 0;
1368
1369 switch (typeReq) {
1370 case ClearHubFeature:
1371 dev_dbg(imx21->dev, "ClearHubFeature\n");
1372 switch (wValue) {
1373 case C_HUB_OVER_CURRENT:
1374 dev_dbg(imx21->dev, " OVER_CURRENT\n");
1375 break;
1376 case C_HUB_LOCAL_POWER:
1377 dev_dbg(imx21->dev, " LOCAL_POWER\n");
1378 break;
1379 default:
1380 dev_dbg(imx21->dev, " unknown\n");
1381 rc = -EINVAL;
1382 break;
1383 }
1384 break;
1385
1386 case ClearPortFeature:
1387 dev_dbg(imx21->dev, "ClearPortFeature\n");
1388 switch (wValue) {
1389 case USB_PORT_FEAT_ENABLE:
1390 dev_dbg(imx21->dev, " ENABLE\n");
1391 status_write = USBH_PORTSTAT_CURCONST;
1392 break;
1393 case USB_PORT_FEAT_SUSPEND:
1394 dev_dbg(imx21->dev, " SUSPEND\n");
1395 status_write = USBH_PORTSTAT_PRTOVRCURI;
1396 break;
1397 case USB_PORT_FEAT_POWER:
1398 dev_dbg(imx21->dev, " POWER\n");
1399 status_write = USBH_PORTSTAT_LSDEVCON;
1400 break;
1401 case USB_PORT_FEAT_C_ENABLE:
1402 dev_dbg(imx21->dev, " C_ENABLE\n");
1403 status_write = USBH_PORTSTAT_PRTENBLSC;
1404 break;
1405 case USB_PORT_FEAT_C_SUSPEND:
1406 dev_dbg(imx21->dev, " C_SUSPEND\n");
1407 status_write = USBH_PORTSTAT_PRTSTATSC;
1408 break;
1409 case USB_PORT_FEAT_C_CONNECTION:
1410 dev_dbg(imx21->dev, " C_CONNECTION\n");
1411 status_write = USBH_PORTSTAT_CONNECTSC;
1412 break;
1413 case USB_PORT_FEAT_C_OVER_CURRENT:
1414 dev_dbg(imx21->dev, " C_OVER_CURRENT\n");
1415 status_write = USBH_PORTSTAT_OVRCURIC;
1416 break;
1417 case USB_PORT_FEAT_C_RESET:
1418 dev_dbg(imx21->dev, " C_RESET\n");
1419 status_write = USBH_PORTSTAT_PRTRSTSC;
1420 break;
1421 default:
1422 dev_dbg(imx21->dev, " unknown\n");
1423 rc = -EINVAL;
1424 break;
1425 }
1426
1427 break;
1428
1429 case GetHubDescriptor:
1430 dev_dbg(imx21->dev, "GetHubDescriptor\n");
1431 rc = get_hub_descriptor(hcd, (void *)buf);
1432 break;
1433
1434 case GetHubStatus:
1435 dev_dbg(imx21->dev, " GetHubStatus\n");
1436 *(__le32 *) buf = 0;
1437 break;
1438
1439 case GetPortStatus:
1440 dev_dbg(imx21->dev, "GetPortStatus: port: %d, 0x%x\n",
1441 wIndex, USBH_PORTSTAT(wIndex - 1));
1442 *(__le32 *) buf = readl(imx21->regs +
1443 USBH_PORTSTAT(wIndex - 1));
1444 break;
1445
1446 case SetHubFeature:
1447 dev_dbg(imx21->dev, "SetHubFeature\n");
1448 switch (wValue) {
1449 case C_HUB_OVER_CURRENT:
1450 dev_dbg(imx21->dev, " OVER_CURRENT\n");
1451 break;
1452
1453 case C_HUB_LOCAL_POWER:
1454 dev_dbg(imx21->dev, " LOCAL_POWER\n");
1455 break;
1456 default:
1457 dev_dbg(imx21->dev, " unknown\n");
1458 rc = -EINVAL;
1459 break;
1460 }
1461
1462 break;
1463
1464 case SetPortFeature:
1465 dev_dbg(imx21->dev, "SetPortFeature\n");
1466 switch (wValue) {
1467 case USB_PORT_FEAT_SUSPEND:
1468 dev_dbg(imx21->dev, " SUSPEND\n");
1469 status_write = USBH_PORTSTAT_PRTSUSPST;
1470 break;
1471 case USB_PORT_FEAT_POWER:
1472 dev_dbg(imx21->dev, " POWER\n");
1473 status_write = USBH_PORTSTAT_PRTPWRST;
1474 break;
1475 case USB_PORT_FEAT_RESET:
1476 dev_dbg(imx21->dev, " RESET\n");
1477 status_write = USBH_PORTSTAT_PRTRSTST;
1478 break;
1479 default:
1480 dev_dbg(imx21->dev, " unknown\n");
1481 rc = -EINVAL;
1482 break;
1483 }
1484 break;
1485
1486 default:
1487 dev_dbg(imx21->dev, " unknown\n");
1488 rc = -EINVAL;
1489 break;
1490 }
1491
1492 if (status_write)
1493 writel(status_write, imx21->regs + USBH_PORTSTAT(wIndex - 1));
1494 return rc;
1495}
1496
1497/* =========================================== */
1498/* Host controller management */
1499/* =========================================== */
1500
1501static int imx21_hc_reset(struct usb_hcd *hcd)
1502{
1503 struct imx21 *imx21 = hcd_to_imx21(hcd);
1504 unsigned long timeout;
1505 unsigned long flags;
1506
1507 spin_lock_irqsave(&imx21->lock, flags);
1508
1509 /* Reset the Host controler modules */
1510 writel(USBOTG_RST_RSTCTRL | USBOTG_RST_RSTRH |
1511 USBOTG_RST_RSTHSIE | USBOTG_RST_RSTHC,
1512 imx21->regs + USBOTG_RST_CTRL);
1513
1514 /* Wait for reset to finish */
1515 timeout = jiffies + HZ;
1516 while (readl(imx21->regs + USBOTG_RST_CTRL) != 0) {
1517 if (time_after(jiffies, timeout)) {
1518 spin_unlock_irqrestore(&imx21->lock, flags);
1519 dev_err(imx21->dev, "timeout waiting for reset\n");
1520 return -ETIMEDOUT;
1521 }
1522 spin_unlock_irq(&imx21->lock);
1523 schedule_timeout(1);
1524 spin_lock_irq(&imx21->lock);
1525 }
1526 spin_unlock_irqrestore(&imx21->lock, flags);
1527 return 0;
1528}
1529
1530static int __devinit imx21_hc_start(struct usb_hcd *hcd)
1531{
1532 struct imx21 *imx21 = hcd_to_imx21(hcd);
1533 unsigned long flags;
1534 int i, j;
1535 u32 hw_mode = USBOTG_HWMODE_CRECFG_HOST;
1536 u32 usb_control = 0;
1537
1538 hw_mode |= ((imx21->pdata->host_xcvr << USBOTG_HWMODE_HOSTXCVR_SHIFT) &
1539 USBOTG_HWMODE_HOSTXCVR_MASK);
1540 hw_mode |= ((imx21->pdata->otg_xcvr << USBOTG_HWMODE_OTGXCVR_SHIFT) &
1541 USBOTG_HWMODE_OTGXCVR_MASK);
1542
1543 if (imx21->pdata->host1_txenoe)
1544 usb_control |= USBCTRL_HOST1_TXEN_OE;
1545
1546 if (!imx21->pdata->host1_xcverless)
1547 usb_control |= USBCTRL_HOST1_BYP_TLL;
1548
1549 if (imx21->pdata->otg_ext_xcvr)
1550 usb_control |= USBCTRL_OTC_RCV_RXDP;
1551
1552
1553 spin_lock_irqsave(&imx21->lock, flags);
1554
1555 writel((USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN),
1556 imx21->regs + USBOTG_CLK_CTRL);
1557 writel(hw_mode, imx21->regs + USBOTG_HWMODE);
1558 writel(usb_control, imx21->regs + USBCTRL);
1559 writel(USB_MISCCONTROL_SKPRTRY | USB_MISCCONTROL_ARBMODE,
1560 imx21->regs + USB_MISCCONTROL);
1561
1562 /* Clear the ETDs */
1563 for (i = 0; i < USB_NUM_ETD; i++)
1564 for (j = 0; j < 4; j++)
1565 etd_writel(imx21, i, j, 0);
1566
1567 /* Take the HC out of reset */
1568 writel(USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL | USBH_HOST_CTRL_CTLBLKSR_1,
1569 imx21->regs + USBH_HOST_CTRL);
1570
1571 /* Enable ports */
1572 if (imx21->pdata->enable_otg_host)
1573 writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
1574 imx21->regs + USBH_PORTSTAT(0));
1575
1576 if (imx21->pdata->enable_host1)
1577 writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
1578 imx21->regs + USBH_PORTSTAT(1));
1579
1580 if (imx21->pdata->enable_host2)
1581 writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
1582 imx21->regs + USBH_PORTSTAT(2));
1583
1584
1585 hcd->state = HC_STATE_RUNNING;
1586
1587 /* Enable host controller interrupts */
1588 set_register_bits(imx21, USBH_SYSIEN,
1589 USBH_SYSIEN_HERRINT |
1590 USBH_SYSIEN_DONEINT | USBH_SYSIEN_SORINT);
1591 set_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
1592
1593 spin_unlock_irqrestore(&imx21->lock, flags);
1594
1595 return 0;
1596}
1597
1598static void imx21_hc_stop(struct usb_hcd *hcd)
1599{
1600 struct imx21 *imx21 = hcd_to_imx21(hcd);
1601 unsigned long flags;
1602
1603 spin_lock_irqsave(&imx21->lock, flags);
1604
1605 writel(0, imx21->regs + USBH_SYSIEN);
1606 clear_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
1607 clear_register_bits(imx21, USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN,
1608 USBOTG_CLK_CTRL);
1609 spin_unlock_irqrestore(&imx21->lock, flags);
1610}
1611
1612/* =========================================== */
1613/* Driver glue */
1614/* =========================================== */
1615
1616static struct hc_driver imx21_hc_driver = {
1617 .description = hcd_name,
1618 .product_desc = "IMX21 USB Host Controller",
1619 .hcd_priv_size = sizeof(struct imx21),
1620
1621 .flags = HCD_USB11,
1622 .irq = imx21_irq,
1623
1624 .reset = imx21_hc_reset,
1625 .start = imx21_hc_start,
1626 .stop = imx21_hc_stop,
1627
1628 /* I/O requests */
1629 .urb_enqueue = imx21_hc_urb_enqueue,
1630 .urb_dequeue = imx21_hc_urb_dequeue,
1631 .endpoint_disable = imx21_hc_endpoint_disable,
1632
1633 /* scheduling support */
1634 .get_frame_number = imx21_hc_get_frame,
1635
1636 /* Root hub support */
1637 .hub_status_data = imx21_hc_hub_status_data,
1638 .hub_control = imx21_hc_hub_control,
1639
1640};
1641
1642static struct mx21_usbh_platform_data default_pdata = {
1643 .host_xcvr = MX21_USBXCVR_TXDIF_RXDIF,
1644 .otg_xcvr = MX21_USBXCVR_TXDIF_RXDIF,
1645 .enable_host1 = 1,
1646 .enable_host2 = 1,
1647 .enable_otg_host = 1,
1648
1649};
1650
1651static int imx21_remove(struct platform_device *pdev)
1652{
1653 struct usb_hcd *hcd = platform_get_drvdata(pdev);
1654 struct imx21 *imx21 = hcd_to_imx21(hcd);
1655 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1656
1657 remove_debug_files(imx21);
1658 usb_remove_hcd(hcd);
1659
1660 if (res != NULL) {
1661 clk_disable(imx21->clk);
1662 clk_put(imx21->clk);
1663 iounmap(imx21->regs);
1664 release_mem_region(res->start, resource_size(res));
1665 }
1666
1667 kfree(hcd);
1668 return 0;
1669}
1670
1671
1672static int imx21_probe(struct platform_device *pdev)
1673{
1674 struct usb_hcd *hcd;
1675 struct imx21 *imx21;
1676 struct resource *res;
1677 int ret;
1678 int irq;
1679
1680 printk(KERN_INFO "%s\n", imx21_hc_driver.product_desc);
1681
1682 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1683 if (!res)
1684 return -ENODEV;
1685 irq = platform_get_irq(pdev, 0);
1686 if (irq < 0)
1687 return -ENXIO;
1688
1689 hcd = usb_create_hcd(&imx21_hc_driver,
1690 &pdev->dev, dev_name(&pdev->dev));
1691 if (hcd == NULL) {
1692 dev_err(&pdev->dev, "Cannot create hcd (%s)\n",
1693 dev_name(&pdev->dev));
1694 return -ENOMEM;
1695 }
1696
1697 imx21 = hcd_to_imx21(hcd);
1698 imx21->dev = &pdev->dev;
1699 imx21->pdata = pdev->dev.platform_data;
1700 if (!imx21->pdata)
1701 imx21->pdata = &default_pdata;
1702
1703 spin_lock_init(&imx21->lock);
1704 INIT_LIST_HEAD(&imx21->dmem_list);
1705 INIT_LIST_HEAD(&imx21->queue_for_etd);
1706 INIT_LIST_HEAD(&imx21->queue_for_dmem);
1707 create_debug_files(imx21);
1708
1709 res = request_mem_region(res->start, resource_size(res), hcd_name);
1710 if (!res) {
1711 ret = -EBUSY;
1712 goto failed_request_mem;
1713 }
1714
1715 imx21->regs = ioremap(res->start, resource_size(res));
1716 if (imx21->regs == NULL) {
1717 dev_err(imx21->dev, "Cannot map registers\n");
1718 ret = -ENOMEM;
1719 goto failed_ioremap;
1720 }
1721
1722 /* Enable clocks source */
1723 imx21->clk = clk_get(imx21->dev, NULL);
1724 if (IS_ERR(imx21->clk)) {
1725 dev_err(imx21->dev, "no clock found\n");
1726 ret = PTR_ERR(imx21->clk);
1727 goto failed_clock_get;
1728 }
1729
1730 ret = clk_set_rate(imx21->clk, clk_round_rate(imx21->clk, 48000000));
1731 if (ret)
1732 goto failed_clock_set;
1733 ret = clk_enable(imx21->clk);
1734 if (ret)
1735 goto failed_clock_enable;
1736
1737 dev_info(imx21->dev, "Hardware HC revision: 0x%02X\n",
1738 (readl(imx21->regs + USBOTG_HWMODE) >> 16) & 0xFF);
1739
1740 ret = usb_add_hcd(hcd, irq, IRQF_DISABLED);
1741 if (ret != 0) {
1742 dev_err(imx21->dev, "usb_add_hcd() returned %d\n", ret);
1743 goto failed_add_hcd;
1744 }
1745
1746 return 0;
1747
1748failed_add_hcd:
1749 clk_disable(imx21->clk);
1750failed_clock_enable:
1751failed_clock_set:
1752 clk_put(imx21->clk);
1753failed_clock_get:
1754 iounmap(imx21->regs);
1755failed_ioremap:
1756 release_mem_region(res->start, res->end - res->start);
1757failed_request_mem:
1758 remove_debug_files(imx21);
1759 usb_put_hcd(hcd);
1760 return ret;
1761}
1762
1763static struct platform_driver imx21_hcd_driver = {
1764 .driver = {
1765 .name = (char *)hcd_name,
1766 },
1767 .probe = imx21_probe,
1768 .remove = imx21_remove,
1769 .suspend = NULL,
1770 .resume = NULL,
1771};
1772
1773static int __init imx21_hcd_init(void)
1774{
1775 return platform_driver_register(&imx21_hcd_driver);
1776}
1777
1778static void __exit imx21_hcd_cleanup(void)
1779{
1780 platform_driver_unregister(&imx21_hcd_driver);
1781}
1782
1783module_init(imx21_hcd_init);
1784module_exit(imx21_hcd_cleanup);
1785
1786MODULE_DESCRIPTION("i.MX21 USB Host controller");
1787MODULE_AUTHOR("Martin Fuzzey");
1788MODULE_LICENSE("GPL");
1789MODULE_ALIAS("platform:imx21-hcd");
diff --git a/drivers/usb/host/imx21-hcd.h b/drivers/usb/host/imx21-hcd.h
new file mode 100644
index 000000000000..1b0d913780a5
--- /dev/null
+++ b/drivers/usb/host/imx21-hcd.h
@@ -0,0 +1,436 @@
1/*
2 * Macros and prototypes for i.MX21
3 *
4 * Copyright (C) 2006 Loping Dog Embedded Systems
5 * Copyright (C) 2009 Martin Fuzzey
6 * Originally written by Jay Monkman <jtm@lopingdog.com>
7 * Ported to 2.6.30, debugged and enhanced by Martin Fuzzey
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation,
21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#ifndef __LINUX_IMX21_HCD_H__
25#define __LINUX_IMX21_HCD_H__
26
27#include <mach/mx21-usbhost.h>
28
29#define NUM_ISO_ETDS 2
30#define USB_NUM_ETD 32
31#define DMEM_SIZE 4096
32
33/* Register definitions */
34#define USBOTG_HWMODE 0x00
35#define USBOTG_HWMODE_ANASDBEN (1 << 14)
36#define USBOTG_HWMODE_OTGXCVR_SHIFT 6
37#define USBOTG_HWMODE_OTGXCVR_MASK (3 << 6)
38#define USBOTG_HWMODE_OTGXCVR_TD_RD (0 << 6)
39#define USBOTG_HWMODE_OTGXCVR_TS_RD (2 << 6)
40#define USBOTG_HWMODE_OTGXCVR_TD_RS (1 << 6)
41#define USBOTG_HWMODE_OTGXCVR_TS_RS (3 << 6)
42#define USBOTG_HWMODE_HOSTXCVR_SHIFT 4
43#define USBOTG_HWMODE_HOSTXCVR_MASK (3 << 4)
44#define USBOTG_HWMODE_HOSTXCVR_TD_RD (0 << 4)
45#define USBOTG_HWMODE_HOSTXCVR_TS_RD (2 << 4)
46#define USBOTG_HWMODE_HOSTXCVR_TD_RS (1 << 4)
47#define USBOTG_HWMODE_HOSTXCVR_TS_RS (3 << 4)
48#define USBOTG_HWMODE_CRECFG_MASK (3 << 0)
49#define USBOTG_HWMODE_CRECFG_HOST (1 << 0)
50#define USBOTG_HWMODE_CRECFG_FUNC (2 << 0)
51#define USBOTG_HWMODE_CRECFG_HNP (3 << 0)
52
53#define USBOTG_CINT_STAT 0x04
54#define USBOTG_CINT_STEN 0x08
55#define USBOTG_ASHNPINT (1 << 5)
56#define USBOTG_ASFCINT (1 << 4)
57#define USBOTG_ASHCINT (1 << 3)
58#define USBOTG_SHNPINT (1 << 2)
59#define USBOTG_FCINT (1 << 1)
60#define USBOTG_HCINT (1 << 0)
61
62#define USBOTG_CLK_CTRL 0x0c
63#define USBOTG_CLK_CTRL_FUNC (1 << 2)
64#define USBOTG_CLK_CTRL_HST (1 << 1)
65#define USBOTG_CLK_CTRL_MAIN (1 << 0)
66
67#define USBOTG_RST_CTRL 0x10
68#define USBOTG_RST_RSTI2C (1 << 15)
69#define USBOTG_RST_RSTCTRL (1 << 5)
70#define USBOTG_RST_RSTFC (1 << 4)
71#define USBOTG_RST_RSTFSKE (1 << 3)
72#define USBOTG_RST_RSTRH (1 << 2)
73#define USBOTG_RST_RSTHSIE (1 << 1)
74#define USBOTG_RST_RSTHC (1 << 0)
75
76#define USBOTG_FRM_INTVL 0x14
77#define USBOTG_FRM_REMAIN 0x18
78#define USBOTG_HNP_CSR 0x1c
79#define USBOTG_HNP_ISR 0x2c
80#define USBOTG_HNP_IEN 0x30
81
82#define USBOTG_I2C_TXCVR_REG(x) (0x100 + (x))
83#define USBOTG_I2C_XCVR_DEVAD 0x118
84#define USBOTG_I2C_SEQ_OP_REG 0x119
85#define USBOTG_I2C_SEQ_RD_STARTAD 0x11a
86#define USBOTG_I2C_OP_CTRL_REG 0x11b
87#define USBOTG_I2C_SCLK_TO_SCK_HPER 0x11e
88#define USBOTG_I2C_MASTER_INT_REG 0x11f
89
90#define USBH_HOST_CTRL 0x80
91#define USBH_HOST_CTRL_HCRESET (1 << 31)
92#define USBH_HOST_CTRL_SCHDOVR(x) ((x) << 16)
93#define USBH_HOST_CTRL_RMTWUEN (1 << 4)
94#define USBH_HOST_CTRL_HCUSBSTE_RESET (0 << 2)
95#define USBH_HOST_CTRL_HCUSBSTE_RESUME (1 << 2)
96#define USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL (2 << 2)
97#define USBH_HOST_CTRL_HCUSBSTE_SUSPEND (3 << 2)
98#define USBH_HOST_CTRL_CTLBLKSR_1 (0 << 0)
99#define USBH_HOST_CTRL_CTLBLKSR_2 (1 << 0)
100#define USBH_HOST_CTRL_CTLBLKSR_3 (2 << 0)
101#define USBH_HOST_CTRL_CTLBLKSR_4 (3 << 0)
102
103#define USBH_SYSISR 0x88
104#define USBH_SYSISR_PSCINT (1 << 6)
105#define USBH_SYSISR_FMOFINT (1 << 5)
106#define USBH_SYSISR_HERRINT (1 << 4)
107#define USBH_SYSISR_RESDETINT (1 << 3)
108#define USBH_SYSISR_SOFINT (1 << 2)
109#define USBH_SYSISR_DONEINT (1 << 1)
110#define USBH_SYSISR_SORINT (1 << 0)
111
112#define USBH_SYSIEN 0x8c
113#define USBH_SYSIEN_PSCINT (1 << 6)
114#define USBH_SYSIEN_FMOFINT (1 << 5)
115#define USBH_SYSIEN_HERRINT (1 << 4)
116#define USBH_SYSIEN_RESDETINT (1 << 3)
117#define USBH_SYSIEN_SOFINT (1 << 2)
118#define USBH_SYSIEN_DONEINT (1 << 1)
119#define USBH_SYSIEN_SORINT (1 << 0)
120
121#define USBH_XBUFSTAT 0x98
122#define USBH_YBUFSTAT 0x9c
123#define USBH_XYINTEN 0xa0
124#define USBH_XFILLSTAT 0xa8
125#define USBH_YFILLSTAT 0xac
126#define USBH_ETDENSET 0xc0
127#define USBH_ETDENCLR 0xc4
128#define USBH_IMMEDINT 0xcc
129#define USBH_ETDDONESTAT 0xd0
130#define USBH_ETDDONEEN 0xd4
131#define USBH_FRMNUB 0xe0
132#define USBH_LSTHRESH 0xe4
133
134#define USBH_ROOTHUBA 0xe8
135#define USBH_ROOTHUBA_PWRTOGOOD_MASK (0xff)
136#define USBH_ROOTHUBA_PWRTOGOOD_SHIFT (24)
137#define USBH_ROOTHUBA_NOOVRCURP (1 << 12)
138#define USBH_ROOTHUBA_OVRCURPM (1 << 11)
139#define USBH_ROOTHUBA_DEVTYPE (1 << 10)
140#define USBH_ROOTHUBA_PWRSWTMD (1 << 9)
141#define USBH_ROOTHUBA_NOPWRSWT (1 << 8)
142#define USBH_ROOTHUBA_NDNSTMPRT_MASK (0xff)
143
144#define USBH_ROOTHUBB 0xec
145#define USBH_ROOTHUBB_PRTPWRCM(x) (1 << ((x) + 16))
146#define USBH_ROOTHUBB_DEVREMOVE(x) (1 << (x))
147
148#define USBH_ROOTSTAT 0xf0
149#define USBH_ROOTSTAT_CLRRMTWUE (1 << 31)
150#define USBH_ROOTSTAT_OVRCURCHG (1 << 17)
151#define USBH_ROOTSTAT_DEVCONWUE (1 << 15)
152#define USBH_ROOTSTAT_OVRCURI (1 << 1)
153#define USBH_ROOTSTAT_LOCPWRS (1 << 0)
154
155#define USBH_PORTSTAT(x) (0xf4 + ((x) * 4))
156#define USBH_PORTSTAT_PRTRSTSC (1 << 20)
157#define USBH_PORTSTAT_OVRCURIC (1 << 19)
158#define USBH_PORTSTAT_PRTSTATSC (1 << 18)
159#define USBH_PORTSTAT_PRTENBLSC (1 << 17)
160#define USBH_PORTSTAT_CONNECTSC (1 << 16)
161#define USBH_PORTSTAT_LSDEVCON (1 << 9)
162#define USBH_PORTSTAT_PRTPWRST (1 << 8)
163#define USBH_PORTSTAT_PRTRSTST (1 << 4)
164#define USBH_PORTSTAT_PRTOVRCURI (1 << 3)
165#define USBH_PORTSTAT_PRTSUSPST (1 << 2)
166#define USBH_PORTSTAT_PRTENABST (1 << 1)
167#define USBH_PORTSTAT_CURCONST (1 << 0)
168
169#define USB_DMAREV 0x800
170#define USB_DMAINTSTAT 0x804
171#define USB_DMAINTSTAT_EPERR (1 << 1)
172#define USB_DMAINTSTAT_ETDERR (1 << 0)
173
174#define USB_DMAINTEN 0x808
175#define USB_DMAINTEN_EPERRINTEN (1 << 1)
176#define USB_DMAINTEN_ETDERRINTEN (1 << 0)
177
178#define USB_ETDDMAERSTAT 0x80c
179#define USB_EPDMAERSTAT 0x810
180#define USB_ETDDMAEN 0x820
181#define USB_EPDMAEN 0x824
182#define USB_ETDDMAXTEN 0x828
183#define USB_EPDMAXTEN 0x82c
184#define USB_ETDDMAENXYT 0x830
185#define USB_EPDMAENXYT 0x834
186#define USB_ETDDMABST4EN 0x838
187#define USB_EPDMABST4EN 0x83c
188
189#define USB_MISCCONTROL 0x840
190#define USB_MISCCONTROL_ISOPREVFRM (1 << 3)
191#define USB_MISCCONTROL_SKPRTRY (1 << 2)
192#define USB_MISCCONTROL_ARBMODE (1 << 1)
193#define USB_MISCCONTROL_FILTCC (1 << 0)
194
195#define USB_ETDDMACHANLCLR 0x848
196#define USB_EPDMACHANLCLR 0x84c
197#define USB_ETDSMSA(x) (0x900 + ((x) * 4))
198#define USB_EPSMSA(x) (0x980 + ((x) * 4))
199#define USB_ETDDMABUFPTR(x) (0xa00 + ((x) * 4))
200#define USB_EPDMABUFPTR(x) (0xa80 + ((x) * 4))
201
202#define USB_ETD_DWORD(x, w) (0x200 + ((x) * 16) + ((w) * 4))
203#define DW0_ADDRESS 0
204#define DW0_ENDPNT 7
205#define DW0_DIRECT 11
206#define DW0_SPEED 13
207#define DW0_FORMAT 14
208#define DW0_MAXPKTSIZ 16
209#define DW0_HALTED 27
210#define DW0_TOGCRY 28
211#define DW0_SNDNAK 30
212
213#define DW1_XBUFSRTAD 0
214#define DW1_YBUFSRTAD 16
215
216#define DW2_RTRYDELAY 0
217#define DW2_POLINTERV 0
218#define DW2_STARTFRM 0
219#define DW2_RELPOLPOS 8
220#define DW2_DIRPID 16
221#define DW2_BUFROUND 18
222#define DW2_DELAYINT 19
223#define DW2_DATATOG 22
224#define DW2_ERRORCNT 24
225#define DW2_COMPCODE 28
226
227#define DW3_TOTBYECNT 0
228#define DW3_PKTLEN0 0
229#define DW3_COMPCODE0 12
230#define DW3_PKTLEN1 16
231#define DW3_BUFSIZE 21
232#define DW3_COMPCODE1 28
233
234#define USBCTRL 0x600
235#define USBCTRL_I2C_WU_INT_STAT (1 << 27)
236#define USBCTRL_OTG_WU_INT_STAT (1 << 26)
237#define USBCTRL_HOST_WU_INT_STAT (1 << 25)
238#define USBCTRL_FNT_WU_INT_STAT (1 << 24)
239#define USBCTRL_I2C_WU_INT_EN (1 << 19)
240#define USBCTRL_OTG_WU_INT_EN (1 << 18)
241#define USBCTRL_HOST_WU_INT_EN (1 << 17)
242#define USBCTRL_FNT_WU_INT_EN (1 << 16)
243#define USBCTRL_OTC_RCV_RXDP (1 << 13)
244#define USBCTRL_HOST1_BYP_TLL (1 << 12)
245#define USBCTRL_OTG_BYP_VAL(x) ((x) << 10)
246#define USBCTRL_HOST1_BYP_VAL(x) ((x) << 8)
247#define USBCTRL_OTG_PWR_MASK (1 << 6)
248#define USBCTRL_HOST1_PWR_MASK (1 << 5)
249#define USBCTRL_HOST2_PWR_MASK (1 << 4)
250#define USBCTRL_USB_BYP (1 << 2)
251#define USBCTRL_HOST1_TXEN_OE (1 << 1)
252
253
254/* Values in TD blocks */
255#define TD_DIR_SETUP 0
256#define TD_DIR_OUT 1
257#define TD_DIR_IN 2
258#define TD_FORMAT_CONTROL 0
259#define TD_FORMAT_ISO 1
260#define TD_FORMAT_BULK 2
261#define TD_FORMAT_INT 3
262#define TD_TOGGLE_CARRY 0
263#define TD_TOGGLE_DATA0 2
264#define TD_TOGGLE_DATA1 3
265
266/* control transfer states */
267#define US_CTRL_SETUP 2
268#define US_CTRL_DATA 1
269#define US_CTRL_ACK 0
270
271/* bulk transfer main state and 0-length packet */
272#define US_BULK 1
273#define US_BULK0 0
274
275/*ETD format description*/
276#define IMX_FMT_CTRL 0x0
277#define IMX_FMT_ISO 0x1
278#define IMX_FMT_BULK 0x2
279#define IMX_FMT_INT 0x3
280
281static char fmt_urb_to_etd[4] = {
282/*PIPE_ISOCHRONOUS*/ IMX_FMT_ISO,
283/*PIPE_INTERRUPT*/ IMX_FMT_INT,
284/*PIPE_CONTROL*/ IMX_FMT_CTRL,
285/*PIPE_BULK*/ IMX_FMT_BULK
286};
287
288/* condition (error) CC codes and mapping (OHCI like) */
289
290#define TD_CC_NOERROR 0x00
291#define TD_CC_CRC 0x01
292#define TD_CC_BITSTUFFING 0x02
293#define TD_CC_DATATOGGLEM 0x03
294#define TD_CC_STALL 0x04
295#define TD_DEVNOTRESP 0x05
296#define TD_PIDCHECKFAIL 0x06
297/*#define TD_UNEXPECTEDPID 0x07 - reserved, not active on MX2*/
298#define TD_DATAOVERRUN 0x08
299#define TD_DATAUNDERRUN 0x09
300#define TD_BUFFEROVERRUN 0x0C
301#define TD_BUFFERUNDERRUN 0x0D
302#define TD_SCHEDULEOVERRUN 0x0E
303#define TD_NOTACCESSED 0x0F
304
305static const int cc_to_error[16] = {
306 /* No Error */ 0,
307 /* CRC Error */ -EILSEQ,
308 /* Bit Stuff */ -EPROTO,
309 /* Data Togg */ -EILSEQ,
310 /* Stall */ -EPIPE,
311 /* DevNotResp */ -ETIMEDOUT,
312 /* PIDCheck */ -EPROTO,
313 /* UnExpPID */ -EPROTO,
314 /* DataOver */ -EOVERFLOW,
315 /* DataUnder */ -EREMOTEIO,
316 /* (for hw) */ -EIO,
317 /* (for hw) */ -EIO,
318 /* BufferOver */ -ECOMM,
319 /* BuffUnder */ -ENOSR,
320 /* (for HCD) */ -ENOSPC,
321 /* (for HCD) */ -EALREADY
322};
323
324/* HCD data associated with a usb core URB */
325struct urb_priv {
326 struct urb *urb;
327 struct usb_host_endpoint *ep;
328 int active;
329 int state;
330 struct td *isoc_td;
331 int isoc_remaining;
332 int isoc_status;
333};
334
335/* HCD data associated with a usb core endpoint */
336struct ep_priv {
337 struct usb_host_endpoint *ep;
338 struct list_head td_list;
339 struct list_head queue;
340 int etd[NUM_ISO_ETDS];
341 int waiting_etd;
342};
343
344/* isoc packet */
345struct td {
346 struct list_head list;
347 struct urb *urb;
348 struct usb_host_endpoint *ep;
349 dma_addr_t data;
350 unsigned long buf_addr;
351 int len;
352 int frame;
353 int isoc_index;
354};
355
356/* HCD data associated with a hardware ETD */
357struct etd_priv {
358 struct usb_host_endpoint *ep;
359 struct urb *urb;
360 struct td *td;
361 struct list_head queue;
362 dma_addr_t dma_handle;
363 int alloc;
364 int len;
365 int dmem_size;
366 int dmem_offset;
367 int active_count;
368#ifdef DEBUG
369 int activated_frame;
370 int disactivated_frame;
371 int last_int_frame;
372 int last_req_frame;
373 u32 submitted_dwords[4];
374#endif
375};
376
377/* Hardware data memory info */
378struct imx21_dmem_area {
379 struct usb_host_endpoint *ep;
380 unsigned int offset;
381 unsigned int size;
382 struct list_head list;
383};
384
385#ifdef DEBUG
386struct debug_usage_stats {
387 unsigned int value;
388 unsigned int maximum;
389};
390
391struct debug_stats {
392 unsigned long submitted;
393 unsigned long completed_ok;
394 unsigned long completed_failed;
395 unsigned long unlinked;
396 unsigned long queue_etd;
397 unsigned long queue_dmem;
398};
399
400struct debug_isoc_trace {
401 int schedule_frame;
402 int submit_frame;
403 int request_len;
404 int done_frame;
405 int done_len;
406 int cc;
407 struct td *td;
408};
409#endif
410
411/* HCD data structure */
412struct imx21 {
413 spinlock_t lock;
414 struct device *dev;
415 struct mx21_usbh_platform_data *pdata;
416 struct list_head dmem_list;
417 struct list_head queue_for_etd; /* eps queued due to etd shortage */
418 struct list_head queue_for_dmem; /* etds queued due to dmem shortage */
419 struct etd_priv etd[USB_NUM_ETD];
420 struct clk *clk;
421 void __iomem *regs;
422#ifdef DEBUG
423 struct dentry *debug_root;
424 struct debug_stats nonisoc_stats;
425 struct debug_stats isoc_stats;
426 struct debug_usage_stats etd_usage;
427 struct debug_usage_stats dmem_usage;
428 struct debug_isoc_trace isoc_trace[20];
429 struct debug_isoc_trace isoc_trace_failed[20];
430 unsigned long debug_unblocks;
431 int isoc_trace_index;
432 int isoc_trace_index_failed;
433#endif
434};
435
436#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 16:05:15 -0500