diff options
-rw-r--r-- | drivers/usb/host/xhci-hub.c | 35 | ||||
-rw-r--r-- | drivers/usb/host/xhci-mem.c | 6 | ||||
-rw-r--r-- | drivers/usb/host/xhci-ring.c | 8 | ||||
-rw-r--r-- | drivers/usb/host/xhci.c | 51 | ||||
-rw-r--r-- | drivers/usb/host/xhci.h | 8 |
5 files changed, 47 insertions, 61 deletions
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c index 70ed7c94e917..9992fbfec85f 100644 --- a/drivers/usb/host/xhci-hub.c +++ b/drivers/usb/host/xhci-hub.c | |||
@@ -342,7 +342,7 @@ static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |||
342 | } | 342 | } |
343 | 343 | ||
344 | /* Write 1 to disable the port */ | 344 | /* Write 1 to disable the port */ |
345 | xhci_writel(xhci, port_status | PORT_PE, addr); | 345 | writel(port_status | PORT_PE, addr); |
346 | port_status = readl(addr); | 346 | port_status = readl(addr); |
347 | xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", | 347 | xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", |
348 | wIndex, port_status); | 348 | wIndex, port_status); |
@@ -388,7 +388,7 @@ static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, | |||
388 | return; | 388 | return; |
389 | } | 389 | } |
390 | /* Change bits are all write 1 to clear */ | 390 | /* Change bits are all write 1 to clear */ |
391 | xhci_writel(xhci, port_status | status, addr); | 391 | writel(port_status | status, addr); |
392 | port_status = readl(addr); | 392 | port_status = readl(addr); |
393 | xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", | 393 | xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", |
394 | port_change_bit, wIndex, port_status); | 394 | port_change_bit, wIndex, port_status); |
@@ -419,7 +419,7 @@ void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, | |||
419 | temp = xhci_port_state_to_neutral(temp); | 419 | temp = xhci_port_state_to_neutral(temp); |
420 | temp &= ~PORT_PLS_MASK; | 420 | temp &= ~PORT_PLS_MASK; |
421 | temp |= PORT_LINK_STROBE | link_state; | 421 | temp |= PORT_LINK_STROBE | link_state; |
422 | xhci_writel(xhci, temp, port_array[port_id]); | 422 | writel(temp, port_array[port_id]); |
423 | } | 423 | } |
424 | 424 | ||
425 | static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, | 425 | static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, |
@@ -445,7 +445,7 @@ static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, | |||
445 | else | 445 | else |
446 | temp &= ~PORT_WKOC_E; | 446 | temp &= ~PORT_WKOC_E; |
447 | 447 | ||
448 | xhci_writel(xhci, temp, port_array[port_id]); | 448 | writel(temp, port_array[port_id]); |
449 | } | 449 | } |
450 | 450 | ||
451 | /* Test and clear port RWC bit */ | 451 | /* Test and clear port RWC bit */ |
@@ -458,7 +458,7 @@ void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, | |||
458 | if (temp & port_bit) { | 458 | if (temp & port_bit) { |
459 | temp = xhci_port_state_to_neutral(temp); | 459 | temp = xhci_port_state_to_neutral(temp); |
460 | temp |= port_bit; | 460 | temp |= port_bit; |
461 | xhci_writel(xhci, temp, port_array[port_id]); | 461 | writel(temp, port_array[port_id]); |
462 | } | 462 | } |
463 | } | 463 | } |
464 | 464 | ||
@@ -838,8 +838,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
838 | temp |= PORT_CSC | PORT_PEC | PORT_WRC | | 838 | temp |= PORT_CSC | PORT_PEC | PORT_WRC | |
839 | PORT_OCC | PORT_RC | PORT_PLC | | 839 | PORT_OCC | PORT_RC | PORT_PLC | |
840 | PORT_CEC; | 840 | PORT_CEC; |
841 | xhci_writel(xhci, temp | PORT_PE, | 841 | writel(temp | PORT_PE, port_array[wIndex]); |
842 | port_array[wIndex]); | ||
843 | temp = readl(port_array[wIndex]); | 842 | temp = readl(port_array[wIndex]); |
844 | break; | 843 | break; |
845 | } | 844 | } |
@@ -894,8 +893,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
894 | * However, khubd will ignore the roothub events until | 893 | * However, khubd will ignore the roothub events until |
895 | * the roothub is registered. | 894 | * the roothub is registered. |
896 | */ | 895 | */ |
897 | xhci_writel(xhci, temp | PORT_POWER, | 896 | writel(temp | PORT_POWER, port_array[wIndex]); |
898 | port_array[wIndex]); | ||
899 | 897 | ||
900 | temp = readl(port_array[wIndex]); | 898 | temp = readl(port_array[wIndex]); |
901 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); | 899 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp); |
@@ -910,7 +908,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
910 | break; | 908 | break; |
911 | case USB_PORT_FEAT_RESET: | 909 | case USB_PORT_FEAT_RESET: |
912 | temp = (temp | PORT_RESET); | 910 | temp = (temp | PORT_RESET); |
913 | xhci_writel(xhci, temp, port_array[wIndex]); | 911 | writel(temp, port_array[wIndex]); |
914 | 912 | ||
915 | temp = readl(port_array[wIndex]); | 913 | temp = readl(port_array[wIndex]); |
916 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); | 914 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); |
@@ -925,7 +923,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
925 | break; | 923 | break; |
926 | case USB_PORT_FEAT_BH_PORT_RESET: | 924 | case USB_PORT_FEAT_BH_PORT_RESET: |
927 | temp |= PORT_WR; | 925 | temp |= PORT_WR; |
928 | xhci_writel(xhci, temp, port_array[wIndex]); | 926 | writel(temp, port_array[wIndex]); |
929 | 927 | ||
930 | temp = readl(port_array[wIndex]); | 928 | temp = readl(port_array[wIndex]); |
931 | break; | 929 | break; |
@@ -935,7 +933,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
935 | temp = readl(port_array[wIndex] + PORTPMSC); | 933 | temp = readl(port_array[wIndex] + PORTPMSC); |
936 | temp &= ~PORT_U1_TIMEOUT_MASK; | 934 | temp &= ~PORT_U1_TIMEOUT_MASK; |
937 | temp |= PORT_U1_TIMEOUT(timeout); | 935 | temp |= PORT_U1_TIMEOUT(timeout); |
938 | xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC); | 936 | writel(temp, port_array[wIndex] + PORTPMSC); |
939 | break; | 937 | break; |
940 | case USB_PORT_FEAT_U2_TIMEOUT: | 938 | case USB_PORT_FEAT_U2_TIMEOUT: |
941 | if (hcd->speed != HCD_USB3) | 939 | if (hcd->speed != HCD_USB3) |
@@ -943,7 +941,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
943 | temp = readl(port_array[wIndex] + PORTPMSC); | 941 | temp = readl(port_array[wIndex] + PORTPMSC); |
944 | temp &= ~PORT_U2_TIMEOUT_MASK; | 942 | temp &= ~PORT_U2_TIMEOUT_MASK; |
945 | temp |= PORT_U2_TIMEOUT(timeout); | 943 | temp |= PORT_U2_TIMEOUT(timeout); |
946 | xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC); | 944 | writel(temp, port_array[wIndex] + PORTPMSC); |
947 | break; | 945 | break; |
948 | default: | 946 | default: |
949 | goto error; | 947 | goto error; |
@@ -1007,8 +1005,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, | |||
1007 | port_array[wIndex], temp); | 1005 | port_array[wIndex], temp); |
1008 | break; | 1006 | break; |
1009 | case USB_PORT_FEAT_POWER: | 1007 | case USB_PORT_FEAT_POWER: |
1010 | xhci_writel(xhci, temp & ~PORT_POWER, | 1008 | writel(temp & ~PORT_POWER, port_array[wIndex]); |
1011 | port_array[wIndex]); | ||
1012 | 1009 | ||
1013 | spin_unlock_irqrestore(&xhci->lock, flags); | 1010 | spin_unlock_irqrestore(&xhci->lock, flags); |
1014 | temp = usb_acpi_power_manageable(hcd->self.root_hub, | 1011 | temp = usb_acpi_power_manageable(hcd->self.root_hub, |
@@ -1156,7 +1153,7 @@ int xhci_bus_suspend(struct usb_hcd *hcd) | |||
1156 | 1153 | ||
1157 | t1 = xhci_port_state_to_neutral(t1); | 1154 | t1 = xhci_port_state_to_neutral(t1); |
1158 | if (t1 != t2) | 1155 | if (t1 != t2) |
1159 | xhci_writel(xhci, t2, port_array[port_index]); | 1156 | writel(t2, port_array[port_index]); |
1160 | } | 1157 | } |
1161 | hcd->state = HC_STATE_SUSPENDED; | 1158 | hcd->state = HC_STATE_SUSPENDED; |
1162 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); | 1159 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); |
@@ -1188,7 +1185,7 @@ int xhci_bus_resume(struct usb_hcd *hcd) | |||
1188 | /* delay the irqs */ | 1185 | /* delay the irqs */ |
1189 | temp = readl(&xhci->op_regs->command); | 1186 | temp = readl(&xhci->op_regs->command); |
1190 | temp &= ~CMD_EIE; | 1187 | temp &= ~CMD_EIE; |
1191 | xhci_writel(xhci, temp, &xhci->op_regs->command); | 1188 | writel(temp, &xhci->op_regs->command); |
1192 | 1189 | ||
1193 | port_index = max_ports; | 1190 | port_index = max_ports; |
1194 | while (port_index--) { | 1191 | while (port_index--) { |
@@ -1234,7 +1231,7 @@ int xhci_bus_resume(struct usb_hcd *hcd) | |||
1234 | if (slot_id) | 1231 | if (slot_id) |
1235 | xhci_ring_device(xhci, slot_id); | 1232 | xhci_ring_device(xhci, slot_id); |
1236 | } else | 1233 | } else |
1237 | xhci_writel(xhci, temp, port_array[port_index]); | 1234 | writel(temp, port_array[port_index]); |
1238 | } | 1235 | } |
1239 | 1236 | ||
1240 | (void) readl(&xhci->op_regs->command); | 1237 | (void) readl(&xhci->op_regs->command); |
@@ -1243,7 +1240,7 @@ int xhci_bus_resume(struct usb_hcd *hcd) | |||
1243 | /* re-enable irqs */ | 1240 | /* re-enable irqs */ |
1244 | temp = readl(&xhci->op_regs->command); | 1241 | temp = readl(&xhci->op_regs->command); |
1245 | temp |= CMD_EIE; | 1242 | temp |= CMD_EIE; |
1246 | xhci_writel(xhci, temp, &xhci->op_regs->command); | 1243 | writel(temp, &xhci->op_regs->command); |
1247 | temp = readl(&xhci->op_regs->command); | 1244 | temp = readl(&xhci->op_regs->command); |
1248 | 1245 | ||
1249 | spin_unlock_irqrestore(&xhci->lock, flags); | 1246 | spin_unlock_irqrestore(&xhci->lock, flags); |
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 3682a3b7e057..bce4391a0e7d 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c | |||
@@ -2254,7 +2254,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) | |||
2254 | val |= (val2 & ~HCS_SLOTS_MASK); | 2254 | val |= (val2 & ~HCS_SLOTS_MASK); |
2255 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 2255 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2256 | "// Setting Max device slots reg = 0x%x.", val); | 2256 | "// Setting Max device slots reg = 0x%x.", val); |
2257 | xhci_writel(xhci, val, &xhci->op_regs->config_reg); | 2257 | writel(val, &xhci->op_regs->config_reg); |
2258 | 2258 | ||
2259 | /* | 2259 | /* |
2260 | * Section 5.4.8 - doorbell array must be | 2260 | * Section 5.4.8 - doorbell array must be |
@@ -2388,7 +2388,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) | |||
2388 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 2388 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2389 | "// Write ERST size = %i to ir_set 0 (some bits preserved)", | 2389 | "// Write ERST size = %i to ir_set 0 (some bits preserved)", |
2390 | val); | 2390 | val); |
2391 | xhci_writel(xhci, val, &xhci->ir_set->erst_size); | 2391 | writel(val, &xhci->ir_set->erst_size); |
2392 | 2392 | ||
2393 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 2393 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
2394 | "// Set ERST entries to point to event ring."); | 2394 | "// Set ERST entries to point to event ring."); |
@@ -2434,7 +2434,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) | |||
2434 | temp = readl(&xhci->op_regs->dev_notification); | 2434 | temp = readl(&xhci->op_regs->dev_notification); |
2435 | temp &= ~DEV_NOTE_MASK; | 2435 | temp &= ~DEV_NOTE_MASK; |
2436 | temp |= DEV_NOTE_FWAKE; | 2436 | temp |= DEV_NOTE_FWAKE; |
2437 | xhci_writel(xhci, temp, &xhci->op_regs->dev_notification); | 2437 | writel(temp, &xhci->op_regs->dev_notification); |
2438 | 2438 | ||
2439 | return 0; | 2439 | return 0; |
2440 | 2440 | ||
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 9f2349b2aea5..bc46cce46db8 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c | |||
@@ -295,7 +295,7 @@ void xhci_ring_cmd_db(struct xhci_hcd *xhci) | |||
295 | return; | 295 | return; |
296 | 296 | ||
297 | xhci_dbg(xhci, "// Ding dong!\n"); | 297 | xhci_dbg(xhci, "// Ding dong!\n"); |
298 | xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]); | 298 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
299 | /* Flush PCI posted writes */ | 299 | /* Flush PCI posted writes */ |
300 | readl(&xhci->dba->doorbell[0]); | 300 | readl(&xhci->dba->doorbell[0]); |
301 | } | 301 | } |
@@ -427,7 +427,7 @@ void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, | |||
427 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || | 427 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
428 | (ep_state & EP_HALTED)) | 428 | (ep_state & EP_HALTED)) |
429 | return; | 429 | return; |
430 | xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr); | 430 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
431 | /* The CPU has better things to do at this point than wait for a | 431 | /* The CPU has better things to do at this point than wait for a |
432 | * write-posting flush. It'll get there soon enough. | 432 | * write-posting flush. It'll get there soon enough. |
433 | */ | 433 | */ |
@@ -2853,7 +2853,7 @@ hw_died: | |||
2853 | * Write 1 to clear the interrupt status. | 2853 | * Write 1 to clear the interrupt status. |
2854 | */ | 2854 | */ |
2855 | status |= STS_EINT; | 2855 | status |= STS_EINT; |
2856 | xhci_writel(xhci, status, &xhci->op_regs->status); | 2856 | writel(status, &xhci->op_regs->status); |
2857 | /* FIXME when MSI-X is supported and there are multiple vectors */ | 2857 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2858 | /* Clear the MSI-X event interrupt status */ | 2858 | /* Clear the MSI-X event interrupt status */ |
2859 | 2859 | ||
@@ -2862,7 +2862,7 @@ hw_died: | |||
2862 | /* Acknowledge the PCI interrupt */ | 2862 | /* Acknowledge the PCI interrupt */ |
2863 | irq_pending = readl(&xhci->ir_set->irq_pending); | 2863 | irq_pending = readl(&xhci->ir_set->irq_pending); |
2864 | irq_pending |= IMAN_IP; | 2864 | irq_pending |= IMAN_IP; |
2865 | xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending); | 2865 | writel(irq_pending, &xhci->ir_set->irq_pending); |
2866 | } | 2866 | } |
2867 | 2867 | ||
2868 | if (xhci->xhc_state & XHCI_STATE_DYING) { | 2868 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 5e6a8651c2a8..7630b9ff56d4 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c | |||
@@ -88,7 +88,7 @@ void xhci_quiesce(struct xhci_hcd *xhci) | |||
88 | 88 | ||
89 | cmd = readl(&xhci->op_regs->command); | 89 | cmd = readl(&xhci->op_regs->command); |
90 | cmd &= mask; | 90 | cmd &= mask; |
91 | xhci_writel(xhci, cmd, &xhci->op_regs->command); | 91 | writel(cmd, &xhci->op_regs->command); |
92 | } | 92 | } |
93 | 93 | ||
94 | /* | 94 | /* |
@@ -128,7 +128,7 @@ static int xhci_start(struct xhci_hcd *xhci) | |||
128 | temp |= (CMD_RUN); | 128 | temp |= (CMD_RUN); |
129 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", | 129 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", |
130 | temp); | 130 | temp); |
131 | xhci_writel(xhci, temp, &xhci->op_regs->command); | 131 | writel(temp, &xhci->op_regs->command); |
132 | 132 | ||
133 | /* | 133 | /* |
134 | * Wait for the HCHalted Status bit to be 0 to indicate the host is | 134 | * Wait for the HCHalted Status bit to be 0 to indicate the host is |
@@ -167,7 +167,7 @@ int xhci_reset(struct xhci_hcd *xhci) | |||
167 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); | 167 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); |
168 | command = readl(&xhci->op_regs->command); | 168 | command = readl(&xhci->op_regs->command); |
169 | command |= CMD_RESET; | 169 | command |= CMD_RESET; |
170 | xhci_writel(xhci, command, &xhci->op_regs->command); | 170 | writel(command, &xhci->op_regs->command); |
171 | 171 | ||
172 | ret = xhci_handshake(xhci, &xhci->op_regs->command, | 172 | ret = xhci_handshake(xhci, &xhci->op_regs->command, |
173 | CMD_RESET, 0, 10 * 1000 * 1000); | 173 | CMD_RESET, 0, 10 * 1000 * 1000); |
@@ -614,21 +614,20 @@ int xhci_run(struct usb_hcd *hcd) | |||
614 | temp = readl(&xhci->ir_set->irq_control); | 614 | temp = readl(&xhci->ir_set->irq_control); |
615 | temp &= ~ER_IRQ_INTERVAL_MASK; | 615 | temp &= ~ER_IRQ_INTERVAL_MASK; |
616 | temp |= (u32) 160; | 616 | temp |= (u32) 160; |
617 | xhci_writel(xhci, temp, &xhci->ir_set->irq_control); | 617 | writel(temp, &xhci->ir_set->irq_control); |
618 | 618 | ||
619 | /* Set the HCD state before we enable the irqs */ | 619 | /* Set the HCD state before we enable the irqs */ |
620 | temp = readl(&xhci->op_regs->command); | 620 | temp = readl(&xhci->op_regs->command); |
621 | temp |= (CMD_EIE); | 621 | temp |= (CMD_EIE); |
622 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 622 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
623 | "// Enable interrupts, cmd = 0x%x.", temp); | 623 | "// Enable interrupts, cmd = 0x%x.", temp); |
624 | xhci_writel(xhci, temp, &xhci->op_regs->command); | 624 | writel(temp, &xhci->op_regs->command); |
625 | 625 | ||
626 | temp = readl(&xhci->ir_set->irq_pending); | 626 | temp = readl(&xhci->ir_set->irq_pending); |
627 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 627 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
628 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", | 628 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", |
629 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); | 629 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); |
630 | xhci_writel(xhci, ER_IRQ_ENABLE(temp), | 630 | writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); |
631 | &xhci->ir_set->irq_pending); | ||
632 | xhci_print_ir_set(xhci, 0); | 631 | xhci_print_ir_set(xhci, 0); |
633 | 632 | ||
634 | if (xhci->quirks & XHCI_NEC_HOST) | 633 | if (xhci->quirks & XHCI_NEC_HOST) |
@@ -699,10 +698,9 @@ void xhci_stop(struct usb_hcd *hcd) | |||
699 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, | 698 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
700 | "// Disabling event ring interrupts"); | 699 | "// Disabling event ring interrupts"); |
701 | temp = readl(&xhci->op_regs->status); | 700 | temp = readl(&xhci->op_regs->status); |
702 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); | 701 | writel(temp & ~STS_EINT, &xhci->op_regs->status); |
703 | temp = readl(&xhci->ir_set->irq_pending); | 702 | temp = readl(&xhci->ir_set->irq_pending); |
704 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), | 703 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
705 | &xhci->ir_set->irq_pending); | ||
706 | xhci_print_ir_set(xhci, 0); | 704 | xhci_print_ir_set(xhci, 0); |
707 | 705 | ||
708 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); | 706 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); |
@@ -762,15 +760,15 @@ static void xhci_save_registers(struct xhci_hcd *xhci) | |||
762 | 760 | ||
763 | static void xhci_restore_registers(struct xhci_hcd *xhci) | 761 | static void xhci_restore_registers(struct xhci_hcd *xhci) |
764 | { | 762 | { |
765 | xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command); | 763 | writel(xhci->s3.command, &xhci->op_regs->command); |
766 | xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification); | 764 | writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification); |
767 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); | 765 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); |
768 | xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg); | 766 | writel(xhci->s3.config_reg, &xhci->op_regs->config_reg); |
769 | xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size); | 767 | writel(xhci->s3.erst_size, &xhci->ir_set->erst_size); |
770 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); | 768 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); |
771 | xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); | 769 | xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); |
772 | xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending); | 770 | writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending); |
773 | xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control); | 771 | writel(xhci->s3.irq_control, &xhci->ir_set->irq_control); |
774 | } | 772 | } |
775 | 773 | ||
776 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) | 774 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) |
@@ -868,7 +866,7 @@ int xhci_suspend(struct xhci_hcd *xhci) | |||
868 | /* step 2: clear Run/Stop bit */ | 866 | /* step 2: clear Run/Stop bit */ |
869 | command = readl(&xhci->op_regs->command); | 867 | command = readl(&xhci->op_regs->command); |
870 | command &= ~CMD_RUN; | 868 | command &= ~CMD_RUN; |
871 | xhci_writel(xhci, command, &xhci->op_regs->command); | 869 | writel(command, &xhci->op_regs->command); |
872 | 870 | ||
873 | /* Some chips from Fresco Logic need an extraordinary delay */ | 871 | /* Some chips from Fresco Logic need an extraordinary delay */ |
874 | delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; | 872 | delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; |
@@ -887,7 +885,7 @@ int xhci_suspend(struct xhci_hcd *xhci) | |||
887 | /* step 4: set CSS flag */ | 885 | /* step 4: set CSS flag */ |
888 | command = readl(&xhci->op_regs->command); | 886 | command = readl(&xhci->op_regs->command); |
889 | command |= CMD_CSS; | 887 | command |= CMD_CSS; |
890 | xhci_writel(xhci, command, &xhci->op_regs->command); | 888 | writel(command, &xhci->op_regs->command); |
891 | if (xhci_handshake(xhci, &xhci->op_regs->status, | 889 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
892 | STS_SAVE, 0, 10 * 1000)) { | 890 | STS_SAVE, 0, 10 * 1000)) { |
893 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); | 891 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); |
@@ -953,7 +951,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |||
953 | /* step 3: set CRS flag */ | 951 | /* step 3: set CRS flag */ |
954 | command = readl(&xhci->op_regs->command); | 952 | command = readl(&xhci->op_regs->command); |
955 | command |= CMD_CRS; | 953 | command |= CMD_CRS; |
956 | xhci_writel(xhci, command, &xhci->op_regs->command); | 954 | writel(command, &xhci->op_regs->command); |
957 | if (xhci_handshake(xhci, &xhci->op_regs->status, | 955 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
958 | STS_RESTORE, 0, 10 * 1000)) { | 956 | STS_RESTORE, 0, 10 * 1000)) { |
959 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); | 957 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); |
@@ -985,10 +983,9 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |||
985 | 983 | ||
986 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); | 984 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
987 | temp = readl(&xhci->op_regs->status); | 985 | temp = readl(&xhci->op_regs->status); |
988 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); | 986 | writel(temp & ~STS_EINT, &xhci->op_regs->status); |
989 | temp = readl(&xhci->ir_set->irq_pending); | 987 | temp = readl(&xhci->ir_set->irq_pending); |
990 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), | 988 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
991 | &xhci->ir_set->irq_pending); | ||
992 | xhci_print_ir_set(xhci, 0); | 989 | xhci_print_ir_set(xhci, 0); |
993 | 990 | ||
994 | xhci_dbg(xhci, "cleaning up memory\n"); | 991 | xhci_dbg(xhci, "cleaning up memory\n"); |
@@ -1025,7 +1022,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |||
1025 | /* step 4: set Run/Stop bit */ | 1022 | /* step 4: set Run/Stop bit */ |
1026 | command = readl(&xhci->op_regs->command); | 1023 | command = readl(&xhci->op_regs->command); |
1027 | command |= CMD_RUN; | 1024 | command |= CMD_RUN; |
1028 | xhci_writel(xhci, command, &xhci->op_regs->command); | 1025 | writel(command, &xhci->op_regs->command); |
1029 | xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, | 1026 | xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, |
1030 | 0, 250 * 1000); | 1027 | 0, 250 * 1000); |
1031 | 1028 | ||
@@ -4082,7 +4079,7 @@ int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, | |||
4082 | spin_lock_irqsave(&xhci->lock, flags); | 4079 | spin_lock_irqsave(&xhci->lock, flags); |
4083 | 4080 | ||
4084 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); | 4081 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); |
4085 | xhci_writel(xhci, hlpm_val, hlpm_addr); | 4082 | writel(hlpm_val, hlpm_addr); |
4086 | /* flush write */ | 4083 | /* flush write */ |
4087 | readl(hlpm_addr); | 4084 | readl(hlpm_addr); |
4088 | } else { | 4085 | } else { |
@@ -4091,15 +4088,15 @@ int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, | |||
4091 | 4088 | ||
4092 | pm_val &= ~PORT_HIRD_MASK; | 4089 | pm_val &= ~PORT_HIRD_MASK; |
4093 | pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id); | 4090 | pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id); |
4094 | xhci_writel(xhci, pm_val, pm_addr); | 4091 | writel(pm_val, pm_addr); |
4095 | pm_val = readl(pm_addr); | 4092 | pm_val = readl(pm_addr); |
4096 | pm_val |= PORT_HLE; | 4093 | pm_val |= PORT_HLE; |
4097 | xhci_writel(xhci, pm_val, pm_addr); | 4094 | writel(pm_val, pm_addr); |
4098 | /* flush write */ | 4095 | /* flush write */ |
4099 | readl(pm_addr); | 4096 | readl(pm_addr); |
4100 | } else { | 4097 | } else { |
4101 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK); | 4098 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK); |
4102 | xhci_writel(xhci, pm_val, pm_addr); | 4099 | writel(pm_val, pm_addr); |
4103 | /* flush write */ | 4100 | /* flush write */ |
4104 | readl(pm_addr); | 4101 | readl(pm_addr); |
4105 | if (udev->usb2_hw_lpm_besl_capable) { | 4102 | if (udev->usb2_hw_lpm_besl_capable) { |
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index c727f1edb37f..402d8743d245 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h | |||
@@ -1595,14 +1595,6 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) | |||
1595 | #define xhci_warn_ratelimited(xhci, fmt, args...) \ | 1595 | #define xhci_warn_ratelimited(xhci, fmt, args...) \ |
1596 | dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | 1596 | dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
1597 | 1597 | ||
1598 | /* TODO: copied from ehci.h - can be refactored? */ | ||
1599 | /* xHCI spec says all registers are little endian */ | ||
1600 | static inline void xhci_writel(struct xhci_hcd *xhci, | ||
1601 | const unsigned int val, __le32 __iomem *regs) | ||
1602 | { | ||
1603 | writel(val, regs); | ||
1604 | } | ||
1605 | |||
1606 | /* | 1598 | /* |
1607 | * Registers should always be accessed with double word or quad word accesses. | 1599 | * Registers should always be accessed with double word or quad word accesses. |
1608 | * | 1600 | * |