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-rw-r--r--arch/blackfin/mach-bf609/boards/ezkit.c16
-rw-r--r--arch/blackfin/mach-bf609/include/mach/defBF60x_base.h10
2 files changed, 26 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index d4dcbab70bb7..d56a55ad83a7 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -104,6 +104,7 @@ static struct platform_device bfin_rotary_device = {
104 104
105#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE) 105#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
106#include <linux/stmmac.h> 106#include <linux/stmmac.h>
107#include <linux/phy.h>
107 108
108static unsigned short pins[] = P_RMII0; 109static unsigned short pins[] = P_RMII0;
109 110
@@ -111,11 +112,26 @@ static struct stmmac_mdio_bus_data phy_private_data = {
111 .phy_mask = 1, 112 .phy_mask = 1,
112}; 113};
113 114
115static struct stmmac_dma_cfg eth_dma_cfg = {
116 .pbl = 2,
117};
118
119int stmmac_ptp_clk_init(struct platform_device *pdev)
120{
121 bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
122 return 0;
123}
124
114static struct plat_stmmacenet_data eth_private_data = { 125static struct plat_stmmacenet_data eth_private_data = {
126 .has_gmac = 1,
115 .bus_id = 0, 127 .bus_id = 0,
116 .enh_desc = 1, 128 .enh_desc = 1,
117 .phy_addr = 1, 129 .phy_addr = 1,
118 .mdio_bus_data = &phy_private_data, 130 .mdio_bus_data = &phy_private_data,
131 .dma_cfg = &eth_dma_cfg,
132 .force_thresh_dma_mode = 1,
133 .interface = PHY_INTERFACE_MODE_RMII,
134 .init = stmmac_ptp_clk_init,
119}; 135};
120 136
121static struct platform_device bfin_eth_device = { 137static struct platform_device bfin_eth_device = {
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
index f1a6afae1a71..35caa7bc192c 100644
--- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
+++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
@@ -839,6 +839,16 @@
839#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */ 839#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
840#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */ 840#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
841 841
842/* ==================================================
843 Pads Controller Registers
844 ================================================== */
845
846/* =========================
847 PADS0
848 ========================= */
849#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */
850#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */
851#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */
842 852
843/* ========================= 853/* =========================
844 PINT Registers 854 PINT Registers