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-rw-r--r--arch/microblaze/kernel/head.S5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 77320b8fc16a..a5ba9925ae89 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -63,9 +63,7 @@ ENTRY(_start)
63real_start: 63real_start:
64#endif 64#endif
65 65
66 mfs r1, rmsr 66 mts rmsr, r0
67 andi r1, r1, ~2
68 mts rmsr, r1
69/* 67/*
70 * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc' 68 * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
71 * if the msrclr instruction is not enabled. We use this to detect 69 * if the msrclr instruction is not enabled. We use this to detect
@@ -73,6 +71,7 @@ real_start:
73 * r8 == 0 - msr instructions are implemented 71 * r8 == 0 - msr instructions are implemented
74 * r8 != 0 - msr instructions are not implemented 72 * r8 != 0 - msr instructions are not implemented
75 */ 73 */
74 mfs r1, rmsr
76 msrclr r8, 0 /* clear nothing - just read msr for test */ 75 msrclr r8, 0 /* clear nothing - just read msr for test */
77 cmpu r8, r8, r1 /* r1 must contain msr reg content */ 76 cmpu r8, r8, r1 /* r1 must contain msr reg content */
78 77