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-rw-r--r--drivers/video/pm2fb.c42
-rw-r--r--include/video/permedia2.h1
2 files changed, 19 insertions, 24 deletions
diff --git a/drivers/video/pm2fb.c b/drivers/video/pm2fb.c
index 25431257e286..a5ccddc141a0 100644
--- a/drivers/video/pm2fb.c
+++ b/drivers/video/pm2fb.c
@@ -343,7 +343,7 @@ static void reset_card(struct pm2fb_par* p)
343 343
344static void reset_config(struct pm2fb_par* p) 344static void reset_config(struct pm2fb_par* p)
345{ 345{
346 WAIT_FIFO(p, 52); 346 WAIT_FIFO(p, 53);
347 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) & 347 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
348 ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED)); 348 ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED));
349 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L)); 349 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
@@ -380,6 +380,7 @@ static void reset_config(struct pm2fb_par* p)
380 pm2_WR(p, PM2R_STATISTICS_MODE, 0); 380 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
381 pm2_WR(p, PM2R_SCISSOR_MODE, 0); 381 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
382 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION); 382 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
383 pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);
383 switch (p->type) { 384 switch (p->type) {
384 case PM2_TYPE_PERMEDIA2: 385 case PM2_TYPE_PERMEDIA2:
385 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */ 386 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
@@ -393,11 +394,6 @@ static void reset_config(struct pm2fb_par* p)
393 break; 394 break;
394 case PM2_TYPE_PERMEDIA2V: 395 case PM2_TYPE_PERMEDIA2V:
395 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */ 396 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
396 pm2v_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
397 pm2v_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
398 pm2v_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
399 pm2v_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
400 pm2v_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
401 break; 397 break;
402 } 398 }
403} 399}
@@ -532,7 +528,7 @@ static void set_video(struct pm2fb_par* p, u32 video) {
532 vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK); 528 vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK);
533 vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH; 529 vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH;
534 530
535 WAIT_FIFO(p, 5); 531 WAIT_FIFO(p, 3);
536 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync); 532 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
537 533
538 switch (p->type) { 534 switch (p->type) {
@@ -551,7 +547,6 @@ static void set_video(struct pm2fb_par* p, u32 video) {
551 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW) 547 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
552 tmp |= 4; /* invert vsync */ 548 tmp |= 4; /* invert vsync */
553 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp); 549 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
554 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
555 break; 550 break;
556 } 551 }
557} 552}
@@ -686,6 +681,7 @@ static int pm2fb_set_par(struct fb_info *info)
686 u32 txtmap = 0; 681 u32 txtmap = 0;
687 u32 pixsize = 0; 682 u32 pixsize = 0;
688 u32 clrformat = 0; 683 u32 clrformat = 0;
684 u32 misc = 1; /* 8-bit DAC */
689 u32 xres = (info->var.xres + 31) & ~31; 685 u32 xres = (info->var.xres + 31) & ~31;
690 int data64; 686 int data64;
691 687
@@ -767,7 +763,7 @@ static int pm2fb_set_par(struct fb_info *info)
767 switch (depth) { 763 switch (depth) {
768 case 8: 764 case 8:
769 pm2_WR(par, PM2R_FB_READ_PIXEL, 0); 765 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
770 clrformat = 0x0e; 766 clrformat = 0x2e;
771 break; 767 break;
772 case 16: 768 case 16:
773 pm2_WR(par, PM2R_FB_READ_PIXEL, 1); 769 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
@@ -775,6 +771,7 @@ static int pm2fb_set_par(struct fb_info *info)
775 txtmap = PM2F_TEXTEL_SIZE_16; 771 txtmap = PM2F_TEXTEL_SIZE_16;
776 pixsize = 1; 772 pixsize = 1;
777 clrformat = 0x70; 773 clrformat = 0x70;
774 misc |= 8;
778 break; 775 break;
779 case 32: 776 case 32:
780 pm2_WR(par, PM2R_FB_READ_PIXEL, 2); 777 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
@@ -782,6 +779,7 @@ static int pm2fb_set_par(struct fb_info *info)
782 txtmap = PM2F_TEXTEL_SIZE_32; 779 txtmap = PM2F_TEXTEL_SIZE_32;
783 pixsize = 2; 780 pixsize = 2;
784 clrformat = 0x20; 781 clrformat = 0x20;
782 misc |= 8;
785 break; 783 break;
786 case 24: 784 case 24:
787 pm2_WR(par, PM2R_FB_READ_PIXEL, 4); 785 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
@@ -789,6 +787,7 @@ static int pm2fb_set_par(struct fb_info *info)
789 txtmap = PM2F_TEXTEL_SIZE_24; 787 txtmap = PM2F_TEXTEL_SIZE_24;
790 pixsize = 4; 788 pixsize = 4;
791 clrformat = 0x20; 789 clrformat = 0x20;
790 misc |= 8;
792 break; 791 break;
793 } 792 }
794 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE); 793 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
@@ -813,7 +812,7 @@ static int pm2fb_set_par(struct fb_info *info)
813 pm2_WR(par, PM2R_SCREEN_BASE, base); 812 pm2_WR(par, PM2R_SCREEN_BASE, base);
814 wmb(); 813 wmb();
815 set_video(par, video); 814 set_video(par, video);
816 WAIT_FIFO(par, 6); 815 WAIT_FIFO(par, 10);
817 switch (par->type) { 816 switch (par->type) {
818 case PM2_TYPE_PERMEDIA2: 817 case PM2_TYPE_PERMEDIA2:
819 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode); 818 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
@@ -821,10 +820,11 @@ static int pm2fb_set_par(struct fb_info *info)
821 (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF); 820 (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
822 break; 821 break;
823 case PM2_TYPE_PERMEDIA2V: 822 case PM2_TYPE_PERMEDIA2V:
823 pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0);
824 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize); 824 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
825 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat); 825 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
826 pm2v_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL, 826 pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc);
827 (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF); 827 pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0);
828 break; 828 break;
829 } 829 }
830 set_pixclock(par, pixclock); 830 set_pixclock(par, pixclock);
@@ -855,7 +855,7 @@ static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
855 struct pm2fb_par *par = info->par; 855 struct pm2fb_par *par = info->par;
856 856
857 if (regno >= info->cmap.len) /* no. of hw registers */ 857 if (regno >= info->cmap.len) /* no. of hw registers */
858 return 1; 858 return -EINVAL;
859 /* 859 /*
860 * Program hardware... do anything you want with transp 860 * Program hardware... do anything you want with transp
861 */ 861 */
@@ -914,7 +914,7 @@ static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
914 u32 v; 914 u32 v;
915 915
916 if (regno >= 16) 916 if (regno >= 16)
917 return 1; 917 return -EINVAL;
918 918
919 v = (red << info->var.red.offset) | 919 v = (red << info->var.red.offset) |
920 (green << info->var.green.offset) | 920 (green << info->var.green.offset) |
@@ -1341,7 +1341,7 @@ static int __devinit pm2fb_probe(struct pci_dev *pdev,
1341 DPRINTK("We have not been initialized by VGA BIOS " 1341 DPRINTK("We have not been initialized by VGA BIOS "
1342 "and are running on an Elsa Winner 2000 Office\n"); 1342 "and are running on an Elsa Winner 2000 Office\n");
1343 DPRINTK("Initializing card timings manually...\n"); 1343 DPRINTK("Initializing card timings manually...\n");
1344 default_par->memclock = 70000; 1344 default_par->memclock = 100000;
1345 } 1345 }
1346 if (pdev->subsystem_vendor == 0x3d3d && 1346 if (pdev->subsystem_vendor == 0x3d3d &&
1347 pdev->subsystem_device == 0x0100) { 1347 pdev->subsystem_device == 0x0100) {
@@ -1491,17 +1491,11 @@ static void __devexit pm2fb_remove(struct pci_dev *pdev)
1491 1491
1492static struct pci_device_id pm2fb_id_table[] = { 1492static struct pci_device_id pm2fb_id_table[] = {
1493 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020, 1493 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1494 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, 1494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1495 0xff0000, 0 },
1496 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2, 1495 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1497 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16, 1496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1498 0xff0000, 0 },
1499 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1500 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1501 0xff0000, 0 },
1502 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V, 1497 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1503 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA << 8, 1498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1504 0xff00, 0 },
1505 { 0, } 1499 { 0, }
1506}; 1500};
1507 1501
diff --git a/include/video/permedia2.h b/include/video/permedia2.h
index 144c81cbcfc6..cf1d95bce412 100644
--- a/include/video/permedia2.h
+++ b/include/video/permedia2.h
@@ -153,6 +153,7 @@
153#define PM2VI_RD_CURSOR_Y_HIGH 0x00A 153#define PM2VI_RD_CURSOR_Y_HIGH 0x00A
154#define PM2VI_RD_CURSOR_X_HOT 0x00B 154#define PM2VI_RD_CURSOR_X_HOT 0x00B
155#define PM2VI_RD_CURSOR_Y_HOT 0x00C 155#define PM2VI_RD_CURSOR_Y_HOT 0x00C
156#define PM2VI_RD_OVERLAY_KEY 0x00D
156#define PM2VI_RD_CLK0_PRESCALE 0x201 157#define PM2VI_RD_CLK0_PRESCALE 0x201
157#define PM2VI_RD_CLK0_FEEDBACK 0x202 158#define PM2VI_RD_CLK0_FEEDBACK 0x202
158#define PM2VI_RD_CLK0_POSTSCALE 0x203 159#define PM2VI_RD_CLK0_POSTSCALE 0x203