86 files changed, 10502 insertions, 4998 deletions

diff --git a/Documentation/devicetree/bindings/arm/bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm2835.txt
new file mode 100644
index 000000000000..ac683480c486
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm2835.txt
@@ -0,0 +1,8 @@
+Broadcom BCM2835 device tree bindings
+-------------------------------------------
+
+Boards with the BCM2835 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "brcm,bcm2835";
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
new file mode 100644
index 000000000000..548892c08c59
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
@@ -0,0 +1,110 @@
+BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
+
+The BCM2835 contains a custom top-level interrupt controller, which supports
+72 interrupt sources using a 2-level register scheme. The interrupt
+controller, or the HW block containing it, is referred to occasionally
+as "armctrl" in the SoC documentation, hence naming of this binding.
+
+Required properties:
+
+- compatible : should be "brcm,bcm2835-armctrl-ic.txt"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 2.
+
+  The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
+  pending" register, or 1/2 respectively for interrupts in the "IRQ pending
+  1/2" register.
+
+  The 2nd cell contains the interrupt number within the bank. Valid values
+  are 0..7 for bank 0, and 0..31 for bank 1.
+
+The interrupt sources are as follows:
+
+Bank 0:
+0: ARM_TIMER
+1: ARM_MAILBOX
+2: ARM_DOORBELL_0
+3: ARM_DOORBELL_1
+4: VPU0_HALTED
+5: VPU1_HALTED
+6: ILLEGAL_TYPE0
+7: ILLEGAL_TYPE1
+
+Bank 1:
+0: TIMER0
+1: TIMER1
+2: TIMER2
+3: TIMER3
+4: CODEC0
+5: CODEC1
+6: CODEC2
+7: VC_JPEG
+8: ISP
+9: VC_USB
+10: VC_3D
+11: TRANSPOSER
+12: MULTICORESYNC0
+13: MULTICORESYNC1
+14: MULTICORESYNC2
+15: MULTICORESYNC3
+16: DMA0
+17: DMA1
+18: VC_DMA2
+19: VC_DMA3
+20: DMA4
+21: DMA5
+22: DMA6
+23: DMA7
+24: DMA8
+25: DMA9
+26: DMA10
+27: DMA11
+28: DMA12
+29: AUX
+30: ARM
+31: VPUDMA
+
+Bank 2:
+0: HOSTPORT
+1: VIDEOSCALER
+2: CCP2TX
+3: SDC
+4: DSI0
+5: AVE
+6: CAM0
+7: CAM1
+8: HDMI0
+9: HDMI1
+10: PIXELVALVE1
+11: I2CSPISLV
+12: DSI1
+13: PWA0
+14: PWA1
+15: CPR
+16: SMI
+17: GPIO0
+18: GPIO1
+19: GPIO2
+20: GPIO3
+21: VC_I2C
+22: VC_SPI
+23: VC_I2SPCM
+24: VC_SDIO
+25: VC_UART
+26: SLIMBUS
+27: VEC
+28: CPG
+29: RNG
+30: VC_ARASANSDIO
+31: AVSPMON
+
+Example:
+
+intc: interrupt-controller {
+        compatible = "brcm,bcm2835-armctrl-ic";
+        reg = <0x7e00b200 0x200>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt b/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
new file mode 100644
index 000000000000..2de21c2acf55
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/brcm,bcm2835-system-timer.txt
@@ -0,0 +1,22 @@
+BCM2835 System Timer
+
+The System Timer peripheral provides four 32-bit timer channels and a
+single 64-bit free running counter. Each channel has an output compare
+register, which is compared against the 32 least significant bits of the
+free running counter values, and generates an interrupt.
+
+Required properties:
+
+- compatible : should be "brcm,bcm2835-system-timer.txt"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 4 interrupt sinks; one per timer channel.
+- clock-frequency : The frequency of the clock that drives the counter, in Hz.
+
+Example:
+
+timer {
+        compatible = "brcm,bcm2835-system-timer";
+        reg = <0x7e003000 0x1000>;
+        interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
+        clock-frequency = <1000000>;
+};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index db4d3af3643c..4f293e5571f0 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -10,6 +10,7 @@ apm	Applied Micro Circuits Corporation (APM)
 arm     ARM Ltd.
 atmel   Atmel Corporation
 bosch   Bosch Sensortec GmbH
+brcm    Broadcom Corporation
 cavium  Cavium, Inc.
 chrp    Common Hardware Reference Platform
 cortina Cortina Systems, Inc.
diff --git a/MAINTAINERS b/MAINTAINERS
index 8443eda055dd..140dba10dd43 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1624,6 +1624,16 @@ L:	netdev@vger.kernel.org
 S:      Supported
 F:      drivers/net/ethernet/broadcom/bnx2x/
 
+BROADCOM BCM2835 ARM ARCHICTURE
+M:      Stephen Warren <swarren@wwwdotorg.org>
+L:      linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
+T:      git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi.git
+S:      Maintained
+F:      arch/arm/mach-bcm2835/
+F:      arch/arm/boot/dts/bcm2835*
+F:      arch/arm/configs/bcm2835_defconfig
+F:      drivers/*/*bcm2835*
+
 BROADCOM TG3 GIGABIT ETHERNET DRIVER
 M:      Matt Carlson <mcarlson@broadcom.com>
 M:      Michael Chan <mchan@broadcom.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 884768cb5332..a97adeccf558 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -347,6 +347,23 @@ config ARCH_AT91
           This enables support for systems based on Atmel
           AT91RM9200 and AT91SAM9* processors.
 
+config ARCH_BCM2835
+        bool "Broadcom BCM2835 family"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_AMBA
+        select ARM_ERRATA_411920
+        select ARM_TIMER_SP804
+        select CLKDEV_LOOKUP
+        select COMMON_CLK
+        select CPU_V6
+        select GENERIC_CLOCKEVENTS
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          This enables support for the Broadcom BCM2835 SoC. This SoC is
+          use in the Raspberry Pi, and Roku 2 devices.
+
 config ARCH_BCMRING
         bool "Broadcom BCMRING"
         depends on MMU
@@ -674,6 +691,7 @@ config ARCH_TEGRA
         select MIGHT_HAVE_CACHE_L2X0
         select ARCH_HAS_CPUFREQ
         select USE_OF
+        select COMMON_CLK
         help
           This enables support for NVIDIA Tegra based systems (Tegra APX,
           Tegra 6xx and Tegra 2 series).
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 74381a31ee42..f47618252e5d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -136,6 +136,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)             := at91
+machine-$(CONFIG_ARCH_BCM2835)          := bcm2835
 machine-$(CONFIG_ARCH_BCMRING)          := bcmring
 machine-$(CONFIG_ARCH_CLPS711X)         := clps711x
 machine-$(CONFIG_ARCH_CNS3XXX)          := cns3xxx
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
new file mode 100644
index 000000000000..7dd860f83f96
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/memreserve/ 0x0c000000 0x04000000;
+/include/ "bcm2835.dtsi"
+
+/ {
+        compatible = "raspberrypi,model-b", "brcm,bcm2835";
+        model = "Raspberry Pi Model B";
+
+        memory {
+                reg = <0 0x10000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
new file mode 100644
index 000000000000..0b619398532c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -0,0 +1,39 @@
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "brcm,bcm2835";
+        model = "BCM2835";
+        interrupt-parent = <&intc>;
+
+        chosen {
+                bootargs = "earlyprintk console=ttyAMA0";
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x7e000000 0x20000000 0x02000000>;
+
+                timer {
+                        compatible = "brcm,bcm2835-system-timer";
+                        reg = <0x7e003000 0x1000>;
+                        interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
+                        clock-frequency = <1000000>;
+                };
+
+                intc: interrupt-controller {
+                        compatible = "brcm,bcm2835-armctrl-ic";
+                        reg = <0x7e00b200 0x200>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                uart@20201000 {
+                        compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
+                        reg = <0x7e201000 0x1000>;
+                        interrupts = <2 25>;
+                        clock-frequency = <3000000>;
+                };
+        };
+};
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
new file mode 100644
index 000000000000..7aea70253c63
--- /dev/null
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -0,0 +1,95 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_FHANDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_NAMESPACES=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_JUMP_LABEL=y
+# CONFIG_BLOCK is not set
+CONFIG_ARCH_BCM2835=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_COMPACTION=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_CLEANCACHE=y
+CONFIG_SECCOMP=y
+CONFIG_CC_STACKPROTECTOR=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_UNIX98_PTYS is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_TTY_PRINTK=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_PROC_FS is not set
+# CONFIG_SYSFS is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_BOOT_PRINTK_DELAY=y
+CONFIG_SCHED_TRACER=y
+CONFIG_STACK_TRACER=y
+CONFIG_FUNCTION_PROFILER=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_KGDB=y
+CONFIG_KGDB_KDB=y
+CONFIG_TEST_KSTRTOX=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
index 26146ffea1a5..8c49df66cac3 100644
--- a/arch/arm/configs/kzm9d_defconfig
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -8,6 +8,7 @@ CONFIG_LOG_BUF_SHIFT=16
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 2388c8610627..5d0c66708960 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -14,6 +14,7 @@ CONFIG_NAMESPACES=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
diff --git a/arch/arm/mach-bcm2835/Makefile b/arch/arm/mach-bcm2835/Makefile
new file mode 100644
index 000000000000..4c3892fe02c3
--- /dev/null
+++ b/arch/arm/mach-bcm2835/Makefile
@@ -0,0 +1 @@
+obj-y += bcm2835.o
diff --git a/arch/arm/mach-bcm2835/Makefile.boot b/arch/arm/mach-bcm2835/Makefile.boot
new file mode 100644
index 000000000000..0831fd1764e7
--- /dev/null
+++ b/arch/arm/mach-bcm2835/Makefile.boot
@@ -0,0 +1,5 @@
+   zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
+
+dtb-y += bcm2835-rpi-b.dtb
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
new file mode 100644
index 000000000000..f6fea4933571
--- /dev/null
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/irqchip/bcm2835.h>
+#include <linux/of_platform.h>
+#include <linux/bcm2835_timer.h>
+#include <linux/clk/bcm2835.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/bcm2835_soc.h>
+
+static struct map_desc io_map __initdata = {
+        .virtual = BCM2835_PERIPH_VIRT,
+        .pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
+        .length = BCM2835_PERIPH_SIZE,
+        .type = MT_DEVICE
+};
+
+void __init bcm2835_map_io(void)
+{
+        iotable_init(&io_map, 1);
+}
+
+void __init bcm2835_init(void)
+{
+        int ret;
+
+        bcm2835_init_clocks();
+
+        ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
+                                   NULL);
+        if (ret) {
+                pr_err("of_platform_populate failed: %d\n", ret);
+                BUG();
+        }
+}
+
+static const char * const bcm2835_compat[] = {
+        "brcm,bcm2835",
+        NULL
+};
+
+DT_MACHINE_START(BCM2835, "BCM2835")
+        .map_io = bcm2835_map_io,
+        .init_irq = bcm2835_init_irq,
+        .handle_irq = bcm2835_handle_irq,
+        .init_machine = bcm2835_init,
+        .timer = &bcm2835_timer,
+        .dt_compat = bcm2835_compat
+MACHINE_END
diff --git a/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
new file mode 100644
index 000000000000..d4dfcf7a9cda
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2012 Stephen Warren
+ *
+ * Derived from code:
+ * Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_BCM2835_BCM2835_SOC_H__
+#define __MACH_BCM2835_BCM2835_SOC_H__
+
+#include <asm/sizes.h>
+
+#define BCM2835_PERIPH_PHYS     0x20000000
+#define BCM2835_PERIPH_VIRT     0xf0000000
+#define BCM2835_PERIPH_SIZE     SZ_16M
+#define BCM2835_DEBUG_PHYS      0x20201000
+#define BCM2835_DEBUG_VIRT      0xf0201000
+
+#endif
diff --git a/arch/arm/mach-bcm2835/include/mach/debug-macro.S b/arch/arm/mach-bcm2835/include/mach/debug-macro.S
new file mode 100644
index 000000000000..8a161e44ae28
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/debug-macro.S
@@ -0,0 +1,21 @@
+/*
+ * Debugging macro include header
+ *
+ * Copyright (C) 2010 Broadcom
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/bcm2835_soc.h>
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =BCM2835_DEBUG_PHYS
+        ldr     \rv, =BCM2835_DEBUG_VIRT
+        .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-bcm2835/include/mach/timex.h b/arch/arm/mach-bcm2835/include/mach/timex.h
new file mode 100644
index 000000000000..6d021e136ae3
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/timex.h
@@ -0,0 +1,26 @@
+/*
+ *  BCM2835 system clock frequency
+ *
+ *  Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#define CLOCK_TICK_RATE         (1000000)
+
+#endif
diff --git a/arch/arm/mach-bcm2835/include/mach/uncompress.h b/arch/arm/mach-bcm2835/include/mach/uncompress.h
new file mode 100644
index 000000000000..cc46dcc72377
--- /dev/null
+++ b/arch/arm/mach-bcm2835/include/mach/uncompress.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ * Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/amba/serial.h>
+#include <mach/bcm2835_soc.h>
+
+#define UART0_BASE BCM2835_DEBUG_PHYS
+
+#define BCM2835_UART_DR IOMEM(UART0_BASE + UART01x_DR)
+#define BCM2835_UART_FR IOMEM(UART0_BASE + UART01x_FR)
+#define BCM2835_UART_CR IOMEM(UART0_BASE + UART011_CR)
+
+static inline void putc(int c)
+{
+        while (__raw_readl(BCM2835_UART_FR) & UART01x_FR_TXFF)
+                barrier();
+
+        __raw_writel(c, BCM2835_UART_DR);
+}
+
+static inline void flush(void)
+{
+        int fr;
+
+        do {
+                fr = __raw_readl(BCM2835_UART_FR);
+                barrier();
+        } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b5b4c8c9db11..6c3299ebbfc5 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -418,8 +418,8 @@ config MACH_EXYNOS5_DT
         select USE_OF
         select ARM_AMBA
         help
-          Machine support for Samsung Exynos4 machine with device tree enabled.
-          Select this if a fdt blob is available for the EXYNOS4 SoC based board.
+          Machine support for Samsung EXYNOS5 machine with device tree enabled.
+          Select this if a fdt blob is available for the EXYNOS5 SoC based board.
 
 if ARCH_EXYNOS4
 
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index 2f51293c1875..6a45c9a9abe9 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -501,6 +501,10 @@ static struct clk exynos4_init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_cam_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
+                .name           = "tsi",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
                 .name           = "hsmmc",
                 .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos4_clk_aclk_133.clk,
@@ -530,6 +534,14 @@ static struct clk exynos4_init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 9),
         }, {
+                .name           = "onenand",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "nfcon",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
                 .name           = "dac",
                 .devname        = "s5p-sdo",
                 .enable         = exynos4_clk_ip_tv_ctrl,
@@ -615,6 +627,25 @@ static struct clk exynos4_init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 21),
         }, {
+                .name           = "pcm",
+                .devname        = "samsung-pcm.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 22),
+        }, {
+                .name           = "pcm",
+                .devname        = "samsung-pcm.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 23),
+        }, {
+                .name           = "slimbus",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 25),
+        }, {
+                .name           = "spdif",
+                .devname        = "samsung-spdif",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 26),
+        }, {
                 .name           = "ac97",
                 .devname        = "samsung-ac97",
                 .enable         = exynos4_clk_ip_peril_ctrl,
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 3b00e299b624..618d0aaaa599 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -882,6 +882,13 @@ static struct clk exynos5_clk_mdma1 = {
         .ctrlbit        = (1 << 4),
 };
 
+static struct clk exynos5_clk_fimd1 = {
+        .name           = "fimd",
+        .devname        = "exynos5-fb.1",
+        .enable         = exynos5_clk_ip_disp1_ctrl,
+        .ctrlbit        = (1 << 0),
+};
+
 struct clk *exynos5_clkset_group_list[] = {
         [0] = &clk_ext_xtal_mux,
         [1] = NULL,
@@ -1111,6 +1118,18 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
 };
 
+struct clksrc_clk exynos5_clk_sclk_fimd1 = {
+        .clk    = {
+                .name           = "sclk_fimd",
+                .devname        = "exynos5-fb.1",
+                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+};
+
 static struct clksrc_clk exynos5_clksrcs[] = {
         {
                 .clk    = {
@@ -1122,16 +1141,6 @@ static struct clksrc_clk exynos5_clksrcs[] = {
                 .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 8, .size = 8 },
         }, {
                 .clk    = {
-                        .name           = "sclk_fimd",
-                        .devname        = "s3cfb.1",
-                        .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "aclk_266_gscl",
                 },
                 .sources = &clk_src_gscl_266,
@@ -1231,12 +1240,14 @@ static struct clksrc_clk *exynos5_sysclks[] = {
         &exynos5_clk_mdout_spi0,
         &exynos5_clk_mdout_spi1,
         &exynos5_clk_mdout_spi2,
+        &exynos5_clk_sclk_fimd1,
 };
 
 static struct clk *exynos5_clk_cdev[] = {
         &exynos5_clk_pdma0,
         &exynos5_clk_pdma1,
         &exynos5_clk_mdma1,
+        &exynos5_clk_fimd1,
 };
 
 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
@@ -1265,6 +1276,7 @@ static struct clk_lookup exynos5_clk_lookup[] = {
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+        CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
 };
 
 static unsigned long exynos5_epll_get_rate(struct clk *clk)
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 65fb8bcd86cb..177259b523cd 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -62,8 +62,8 @@ enum mx35_clks {
         kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
         rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
         ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
-        wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate,
-        clk_max
+        wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
+        gpu2d_gate, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -142,6 +142,9 @@ int __init mx35_clocks_init()
 
         clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
 
+        clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
+        clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
+
         clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0,  0);
         clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0,  2);
         clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0,  4);
@@ -192,7 +195,7 @@ int __init mx35_clocks_init()
         clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
         clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
 
-        clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3,  0);
+        clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3,  0);
         clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3,  2);
         clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3,  4);
 
@@ -228,6 +231,7 @@ int __init mx35_clocks_init()
         clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
         clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
         clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
+        clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
         clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
         clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
         clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
@@ -253,6 +257,7 @@ int __init mx35_clocks_init()
         clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
         clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
         clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
+        clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
 
         clk_prepare_enable(clk[spba_gate]);
         clk_prepare_enable(clk[gpio1_gate]);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index f89c4403a922..e5165a84f93f 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -49,6 +49,7 @@ static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
 static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
 static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
 static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
+static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
 
 enum imx5_clks {
         dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -82,6 +83,7 @@ enum imx5_clks {
         ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
         ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
         epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
+        can_sel, can1_serial_gate, can1_ipg_gate,
         clk_max
 };
 
@@ -421,8 +423,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
         clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
         clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
-        clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6);
-        clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
+        clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
+                                mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
+        clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
+        clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
+        clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
+        clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
         clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
@@ -455,6 +461,10 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
         clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
+        clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
+        clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
+        clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
+        clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
 
         /* set SDHC root clock to 200MHZ*/
         clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
index 1816e22a3479..a544e962a818 100644
--- a/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio-lpc32xx.h
@@ -30,7 +30,7 @@
 #define LPC32XX_GPIO_P1_MAX 24
 #define LPC32XX_GPIO_P2_MAX 13
 #define LPC32XX_GPIO_P3_MAX 6
-#define LPC32XX_GPI_P3_MAX 28
+#define LPC32XX_GPI_P3_MAX 29
 #define LPC32XX_GPO_P3_MAX 24
 
 #define LPC32XX_GPIO_P0_GRP 0
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 5b1cc35e6fba..3c6332753358 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -283,21 +283,25 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
         case IRQ_TYPE_EDGE_RISING:
                 /* Rising edge sensitive */
                 __lpc32xx_set_irq_type(d->hwirq, 1, 1);
+                __irq_set_handler_locked(d->hwirq, handle_edge_irq);
                 break;
 
         case IRQ_TYPE_EDGE_FALLING:
                 /* Falling edge sensitive */
                 __lpc32xx_set_irq_type(d->hwirq, 0, 1);
+                __irq_set_handler_locked(d->hwirq, handle_edge_irq);
                 break;
 
         case IRQ_TYPE_LEVEL_LOW:
                 /* Low level sensitive */
                 __lpc32xx_set_irq_type(d->hwirq, 0, 0);
+                __irq_set_handler_locked(d->hwirq, handle_level_irq);
                 break;
 
         case IRQ_TYPE_LEVEL_HIGH:
                 /* High level sensitive */
                 __lpc32xx_set_irq_type(d->hwirq, 1, 0);
+                __irq_set_handler_locked(d->hwirq, handle_level_irq);
                 break;
 
         /* Other modes are not supported */
@@ -305,9 +309,6 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
                 return -EINVAL;
         }
 
-        /* Ok to use the level handler for all types */
-        irq_set_handler(d->hwirq, handle_level_irq);
-
         return 0;
 }
 
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index b07dcc90829d..e8ff4c3f0566 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -24,12 +24,9 @@
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
 #include <linux/device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
-#include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
 #include <linux/amba/mmci.h>
 #include <linux/of.h>
@@ -37,6 +34,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/clk.h>
+#include <linux/mtd/lpc32xx_slc.h>
+#include <linux/mtd/lpc32xx_mlc.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -156,21 +155,6 @@ static struct clcd_board lpc32xx_clcd_data = {
         .remove         = lpc32xx_clcd_remove,
 };
 
-/*
- * AMBA SSP (SPI)
- */
-static struct pl022_ssp_controller lpc32xx_ssp0_data = {
-        .bus_id                 = 0,
-        .num_chipselect         = 1,
-        .enable_dma             = 0,
-};
-
-static struct pl022_ssp_controller lpc32xx_ssp1_data = {
-        .bus_id                 = 1,
-        .num_chipselect         = 1,
-        .enable_dma             = 0,
-};
-
 static struct pl08x_channel_data pl08x_slave_channels[] = {
         {
                 .bus_id = "nand-slc",
@@ -223,13 +207,25 @@ static struct mmci_platform_data lpc32xx_mmci_data = {
          * gather, and the MMCI driver doesn't do it this way */
 };
 
+static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
+        .dma_filter = pl08x_filter_id,
+};
+
+static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
+        .dma_filter = pl08x_filter_id,
+};
+
 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
-        OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
+        OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL),
+        OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL),
         OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
         OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
         OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
                        &lpc32xx_mmci_data),
+        OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
+                       &lpc32xx_slc_data),
+        OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
+                       &lpc32xx_mlc_data),
         { }
 };
 
@@ -253,12 +249,6 @@ static void __init lpc3250_machine_init(void)
 
         of_platform_populate(NULL, of_default_bus_match_table,
                              lpc32xx_auxdata_lookup, NULL);
-
-        /* Register GPIOs used on this board */
-        if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
-                pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
-        else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
-                pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
 }
 
 static char const *lpc32xx_dt_compat[] __initdata = {
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 7706fdfd0252..845202358ddc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -174,6 +174,7 @@ obj-$(CONFIG_SOC_OMAP2430)		+= omap_hwmod_2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_ipblock_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_2xxx_3xxx_interconnect_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += omap_hwmod_33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 
 # EMU peripherals
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index a3b60c7b9aa8..83b658bf385a 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk)
                 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP3XXX_EN_DPLL_FRBYPASS)
                         clk_reparent(clk, dd->clk_bypass);
-        } else if (cpu_is_omap44xx()) {
+        } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                     v == OMAP4XXX_EN_DPLL_MNBYPASS)
@@ -257,7 +257,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
                 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP3XXX_EN_DPLL_FRBYPASS)
                         return dd->clk_bypass->rate;
-        } else if (cpu_is_omap44xx()) {
+        } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                     v == OMAP4XXX_EN_DPLL_MNBYPASS)
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 8e06de665b14..2026311a4ff6 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1027,7 +1027,9 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
         CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick, CK_AM33XX),
         CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
+        CLK("481cc000.d_can",   NULL,           &dcan0_fck,     CK_AM33XX),
         CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
+        CLK("481d0000.d_can",   NULL,           &dcan1_fck,     CK_AM33XX),
         CLK(NULL,       "debugss_ick",          &debugss_ick,   CK_AM33XX),
         CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk,        CK_AM33XX),
         CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index ef666455c13a..27d79deb4ba2 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -311,7 +311,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
          * Set jitter correction. No jitter correction for OMAP4 and 3630
          * since freqsel field is no longer present
          */
-        if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+        if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
                 v = __raw_readl(dd->control_reg);
                 v &= ~dd->freqsel_mask;
                 v |= freqsel << __ffs(dd->freqsel_mask);
@@ -471,7 +471,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
                         return -EINVAL;
 
                 /* No freqsel on OMAP4 and OMAP3630 */
-                if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
+                if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
                         freqsel = _omap3_dpll_compute_freqsel(clk,
                                                 dd->last_rounded_n);
                         if (!freqsel)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 0d79c23e9f88..4234d28dc171 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -524,6 +524,8 @@ void __init am33xx_init_early(void)
         am33xx_voltagedomains_init();
         am33xx_powerdomains_init();
         am33xx_clockdomains_init();
+        am33xx_hwmod_init();
+        omap_hwmod_init_postsetup();
         am33xx_clk_init();
 }
 #endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 3615e0d9ee3c..7d843cd3b33d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -149,8 +149,10 @@
 #include "powerdomain.h"
 #include "cm2xxx_3xxx.h"
 #include "cminst44xx.h"
+#include "cm33xx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
+#include "prm33xx.h"
 #include "prminst44xx.h"
 #include "mux.h"
 #include "pm.h"
@@ -868,6 +870,26 @@ static void _omap4_enable_module(struct omap_hwmod *oh)
 }
 
 /**
+ * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX
+ * @oh: struct omap_hwmod *
+ *
+ * Enables the PRCM module mode related to the hwmod @oh.
+ * No return value.
+ */
+static void _am33xx_enable_module(struct omap_hwmod *oh)
+{
+        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+                return;
+
+        pr_debug("omap_hwmod: %s: %s: %d\n",
+                 oh->name, __func__, oh->prcm.omap4.modulemode);
+
+        am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst,
+                                oh->clkdm->clkdm_offs,
+                                oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
  * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
  * @oh: struct omap_hwmod *
  *
@@ -894,6 +916,31 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 }
 
 /**
+ * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to enter slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully enters
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_idle() function.
+ */
+static int _am33xx_wait_target_disable(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return 0;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst,
+                                             oh->clkdm->clkdm_offs,
+                                             oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
  * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
  * @oh: struct omap_hwmod *oh
  *
@@ -1614,6 +1661,36 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
 }
 
 /**
+ * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX
+ * @oh: struct omap_hwmod *
+ *
+ * Disable the PRCM module mode related to the hwmod @oh.
+ * Return EINVAL if the modulemode is not supported and 0 in case of success.
+ */
+static int _am33xx_disable_module(struct omap_hwmod *oh)
+{
+        int v;
+
+        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+                return -EINVAL;
+
+        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
+
+        am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs,
+                                 oh->prcm.omap4.clkctrl_offs);
+
+        if (_are_any_hardreset_lines_asserted(oh))
+                return 0;
+
+        v = _am33xx_wait_target_disable(oh);
+        if (v)
+                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+                        oh->name);
+
+        return 0;
+}
+
+/**
  * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
  * @oh: struct omap_hwmod *
  *
@@ -2549,6 +2626,33 @@ static int _omap4_wait_target_ready(struct omap_hwmod *oh)
 }
 
 /**
+ * _am33xx_wait_target_ready - wait for a module to leave slave idle
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_ready() function.
+ */
+static int _am33xx_wait_target_ready(struct omap_hwmod *oh)
+{
+        if (!oh || !oh->clkdm)
+                return -EINVAL;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        if (!_find_mpu_rt_port(oh))
+                return 0;
+
+        /* XXX check module SIDLEMODE, hardreset status */
+
+        return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst,
+                                              oh->clkdm->clkdm_offs,
+                                              oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
  * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
  * @oh: struct omap_hwmod * to assert hardreset
  * @ohri: hardreset line data
@@ -2679,6 +2783,72 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
                                 oh->prcm.omap4.rstctrl_offs);
 }
 
+/**
+ * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to assert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call am33xx_prminst_assert_hardreset() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from am33xx_prminst_assert_hardreset().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
+                                   struct omap_hwmod_rst_info *ohri)
+
+{
+        return am33xx_prm_assert_hardreset(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+
+/**
+ * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to deassert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call am33xx_prminst_deassert_hardreset() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from am33xx_prminst_deassert_hardreset().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
+                                     struct omap_hwmod_rst_info *ohri)
+{
+        if (ohri->st_shift)
+                pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
+                       oh->name, ohri->name);
+
+        return am33xx_prm_deassert_hardreset(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs,
+                                oh->prcm.omap4.rstst_offs);
+}
+
+/**
+ * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to test hardreset
+ * @ohri: hardreset line data
+ *
+ * Call am33xx_prminst_is_hardreset_asserted() with parameters
+ * extracted from the hwmod @oh and the hardreset line data @ohri.
+ * Only intended for use as an soc_ops function pointer.  Passes along
+ * the return value from am33xx_prminst_is_hardreset_asserted().  XXX
+ * This function is scheduled for removal when the PRM code is moved
+ * into drivers/.
+ */
+static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
+                                        struct omap_hwmod_rst_info *ohri)
+{
+        return am33xx_prm_is_hardreset_asserted(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+
 /* Public functions */
 
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
@@ -3678,6 +3848,14 @@ void __init omap_hwmod_init(void)
                 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
                 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
                 soc_ops.init_clkdm = _init_clkdm;
+        } else if (soc_is_am33xx()) {
+                soc_ops.enable_module = _am33xx_enable_module;
+                soc_ops.disable_module = _am33xx_disable_module;
+                soc_ops.wait_target_ready = _am33xx_wait_target_ready;
+                soc_ops.assert_hardreset = _am33xx_assert_hardreset;
+                soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
+                soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted;
+                soc_ops.init_clkdm = _init_clkdm;
         } else {
                 WARN(1, "omap_hwmod: unknown SoC type\n");
         }
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
new file mode 100644
index 000000000000..59d5c1cd316d
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -0,0 +1,3381 @@
+/*
+ * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
+ *
+ * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <plat/dma.h>
+#include <plat/mmc.h>
+#include <plat/i2c.h>
+
+#include "omap_hwmod_common_data.h"
+
+#include "control.h"
+#include "cm33xx.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'emif_fw' class
+ * instance(s): emif_fw
+ */
+static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
+        .name           = "emif_fw",
+};
+
+/* emif_fw */
+static struct omap_hwmod am33xx_emif_fw_hwmod = {
+        .name           = "emif_fw",
+        .class          = &am33xx_emif_fw_hwmod_class,
+        .clkdm_name     = "l4fw_clkdm",
+        .main_clk       = "l4fw_gclk",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'emif' class
+ * instance(s): emif
+ */
+static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
+        .rev_offs       = 0x0000,
+};
+
+static struct omap_hwmod_class am33xx_emif_hwmod_class = {
+        .name           = "emif",
+        .sysc           = &am33xx_emif_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
+        { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+/* emif */
+static struct omap_hwmod am33xx_emif_hwmod = {
+        .name           = "emif",
+        .class          = &am33xx_emif_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_emif_irqs,
+        .main_clk       = "dpll_ddr_m2_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_main, l3_s, l3_instr
+ */
+static struct omap_hwmod_class am33xx_l3_hwmod_class = {
+        .name           = "l3",
+};
+
+/* l3_main (l3_fast) */
+static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
+        { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
+        { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_l3_main_hwmod = {
+        .name           = "l3_main",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_l3_main_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* l3_s */
+static struct omap_hwmod am33xx_l3_s_hwmod = {
+        .name           = "l3_s",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+};
+
+/* l3_instr */
+static struct omap_hwmod am33xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &am33xx_l3_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
+ */
+static struct omap_hwmod_class am33xx_l4_hwmod_class = {
+        .name           = "l4",
+};
+
+/* l4_ls */
+static struct omap_hwmod am33xx_l4_ls_hwmod = {
+        .name           = "l4_ls",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* l4_hs */
+static struct omap_hwmod am33xx_l4_hs_hwmod = {
+        .name           = "l4_hs",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4hs_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l4hs_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+
+/* l4_wkup */
+static struct omap_hwmod am33xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* l4_fw */
+static struct omap_hwmod am33xx_l4_fw_hwmod = {
+        .name           = "l4_fw",
+        .class          = &am33xx_l4_hwmod_class,
+        .clkdm_name     = "l4fw_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mpu' class
+ */
+static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
+        .name   = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
+        { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
+        { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
+        { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
+        { .name = "bench", .irq = 3 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &am33xx_mpu_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_mpu_irqs,
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'wakeup m3' class
+ * Wakeup controller sub-system under wakeup domain
+ */
+static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
+        .name           = "wkup_m3",
+};
+
+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+        { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+};
+
+static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
+        { .name = "txev", .irq = 78 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+/* wkup_m3  */
+static struct omap_hwmod am33xx_wkup_m3_hwmod = {
+        .name           = "wkup_m3",
+        .class          = &am33xx_wkup_m3_hwmod_class,
+        .clkdm_name     = "l4_wkup_aon_clkdm",
+        .flags          = HWMOD_INIT_NO_RESET,  /* Keep hardreset asserted */
+        .mpu_irqs       = am33xx_wkup_m3_irqs,
+        .main_clk       = "dpll_core_m4_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+                        .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_wkup_m3_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
+};
+
+/*
+ * 'pru-icss' class
+ * Programmable Real-Time Unit and Industrial Communication Subsystem
+ */
+static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
+        .name   = "pruss",
+};
+
+static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
+        { .name = "pruss", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
+        { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
+        { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
+        { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
+        { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
+        { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
+        { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
+        { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
+        { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+/* pru-icss */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod am33xx_pruss_hwmod = {
+        .name           = "pruss",
+        .class          = &am33xx_pruss_hwmod_class,
+        .clkdm_name     = "pruss_ocp_clkdm",
+        .mpu_irqs       = am33xx_pruss_irqs,
+        .main_clk       = "pruss_ocp_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
+                        .rstctrl_offs   = AM33XX_RM_PER_RSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_pruss_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
+};
+
+/* gfx */
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
+        .name   = "gfx",
+};
+
+static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
+        { .name = "gfx", .rst_shift = 0 },
+};
+
+static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
+        { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_gfx_hwmod = {
+        .name           = "gfx",
+        .class          = &am33xx_gfx_hwmod_class,
+        .clkdm_name     = "gfx_l3_clkdm",
+        .mpu_irqs       = am33xx_gfx_irqs,
+        .main_clk       = "gfx_fck_div_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
+                        .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .rst_lines      = am33xx_gfx_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
+};
+
+/*
+ * 'prcm' class
+ * power and reset manager (whole prcm infrastructure)
+ */
+static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
+        .name   = "prcm",
+};
+
+/* prcm */
+static struct omap_hwmod am33xx_prcm_hwmod = {
+        .name           = "prcm",
+        .class          = &am33xx_prcm_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/*
+ * 'adc/tsc' class
+ * TouchScreen Controller (Anolog-To-Digital Converter)
+ */
+static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
+        .name           = "adc_tsc",
+        .sysc           = &am33xx_adc_tsc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
+        { .irq = 16 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_adc_tsc_hwmod = {
+        .name           = "adc_tsc",
+        .class          = &am33xx_adc_tsc_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_adc_tsc_irqs,
+        .main_clk       = "adc_tsc_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * Modules omap_hwmod structures
+ *
+ * The following IPs are excluded for the moment because:
+ * - They do not need an explicit SW control using omap_hwmod API.
+ * - They still need to be validated with the driver
+ *   properly adapted to omap_hwmod / omap_device
+ *
+ *    - cEFUSE (doesn't fall under any ocp_if)
+ *    - clkdiv32k
+ *    - debugss
+ *    - ocmc ram
+ *    - ocp watch point
+ *    - aes0
+ *    - sha0
+ */
+#if 0
+/*
+ * 'cefuse' class
+ */
+static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
+        .name           = "cefuse",
+};
+
+static struct omap_hwmod am33xx_cefuse_hwmod = {
+        .name           = "cefuse",
+        .class          = &am33xx_cefuse_hwmod_class,
+        .clkdm_name     = "l4_cefuse_clkdm",
+        .main_clk       = "cefuse_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'clkdiv32k' class
+ */
+static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
+        .name           = "clkdiv32k",
+};
+
+static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
+        .name           = "clkdiv32k",
+        .class          = &am33xx_clkdiv32k_hwmod_class,
+        .clkdm_name     = "clk_24mhz_clkdm",
+        .main_clk       = "clkdiv32k_ick",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'debugss' class
+ * debug sub system
+ */
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+        .name           = "debugss",
+};
+
+static struct omap_hwmod am33xx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &am33xx_debugss_hwmod_class,
+        .clkdm_name     = "l3_aon_clkdm",
+        .main_clk       = "debugss_ick",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ocmcram */
+static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
+        .name = "ocmcram",
+};
+
+static struct omap_hwmod am33xx_ocmcram_hwmod = {
+        .name           = "ocmcram",
+        .class          = &am33xx_ocmcram_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ocpwp */
+static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
+        .name           = "ocpwp",
+};
+
+static struct omap_hwmod am33xx_ocpwp_hwmod = {
+        .name           = "ocpwp",
+        .class          = &am33xx_ocpwp_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'aes' class
+ */
+static struct omap_hwmod_class am33xx_aes_hwmod_class = {
+        .name           = "aes",
+};
+
+static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
+        { .irq = 102 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_aes0_hwmod = {
+        .name           = "aes0",
+        .class          = &am33xx_aes_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_aes0_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* sha0 */
+static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
+        .name           = "sha0",
+};
+
+static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
+        { .irq = 108 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_sha0_hwmod = {
+        .name           = "sha0",
+        .class          = &am33xx_sha0_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_sha0_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+#endif
+
+/* 'smartreflex' class */
+static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
+        .name           = "smartreflex",
+};
+
+/* smartreflex0 */
+static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
+        { .irq = 120 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_smartreflex0_hwmod = {
+        .name           = "smartreflex0",
+        .class          = &am33xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_smartreflex0_irqs,
+        .main_clk       = "smartreflex0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* smartreflex1 */
+static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
+        { .irq = 121 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_smartreflex1_hwmod = {
+        .name           = "smartreflex1",
+        .class          = &am33xx_smartreflex_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_smartreflex1_irqs,
+        .main_clk       = "smartreflex1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'control' module class
+ */
+static struct omap_hwmod_class am33xx_control_hwmod_class = {
+        .name           = "control",
+};
+
+static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
+        { .irq = 8 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_control_hwmod = {
+        .name           = "control",
+        .class          = &am33xx_control_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_control_irqs,
+        .main_clk       = "dpll_core_m4_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'cpgmac' class
+ * cpsw/cpgmac sub system
+ */
+static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x8,
+        .syss_offs      = 0x4,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+                           MSTANDBY_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
+        .name           = "cpgmac0",
+        .sysc           = &am33xx_cpgmac_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
+        { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
+        { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
+        { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
+        { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_cpgmac0_hwmod = {
+        .name           = "cpgmac0",
+        .class          = &am33xx_cpgmac0_hwmod_class,
+        .clkdm_name     = "cpsw_125mhz_clkdm",
+        .mpu_irqs       = am33xx_cpgmac0_irqs,
+        .main_clk       = "cpsw_125mhz_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * dcan class
+ */
+static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
+        .name = "d_can",
+};
+
+/* dcan0 */
+static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
+        { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
+        { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_dcan0_hwmod = {
+        .name           = "d_can0",
+        .class          = &am33xx_dcan_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_dcan0_irqs,
+        .main_clk       = "dcan0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* dcan1 */
+static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
+        { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
+        { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+static struct omap_hwmod am33xx_dcan1_hwmod = {
+        .name           = "d_can1",
+        .class          = &am33xx_dcan_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_dcan1_irqs,
+        .main_clk       = "dcan1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* elm */
+static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                        SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_elm_hwmod_class = {
+        .name           = "elm",
+        .sysc           = &am33xx_elm_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
+        { .irq = 4 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_elm_hwmod = {
+        .name           = "elm",
+        .class          = &am33xx_elm_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_elm_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'epwmss' class: ecap0,1,2,  ehrpwm0,1,2
+ */
+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x4,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                        MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
+        .name           = "epwmss",
+        .sysc           = &am33xx_epwmss_sysc,
+};
+
+/* ehrpwm0 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
+        { .name = "int", .irq = 86 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+        .name           = "ehrpwm0",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm0_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ehrpwm1 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
+        { .name = "int", .irq = 87 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+        .name           = "ehrpwm1",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm1_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ehrpwm2 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
+        { .name = "int", .irq = 39 + OMAP_INTC_START, },
+        { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+        .name           = "ehrpwm2",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ehrpwm2_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ecap0 */
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+        { .irq = 31 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ecap0_hwmod = {
+        .name           = "ecap0",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ecap0_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ecap1 */
+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
+        { .irq = 47 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ecap1_hwmod = {
+        .name           = "ecap1",
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_ecap1_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* ecap2 */
+static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
+        { .irq = 61 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_ecap2_hwmod = {
+        .name           = "ecap2",
+        .mpu_irqs       = am33xx_ecap2_irqs,
+        .class          = &am33xx_epwmss_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'gpio' class: for gpio 0,1,2,3
+ */
+static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                          SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                          SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
+        .name           = "gpio",
+        .sysc           = &am33xx_gpio_sysc,
+        .rev            = 2,
+};
+
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width     = 32,
+        .dbck_flag      = true,
+};
+
+/* gpio0 */
+static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio0_dbclk" },
+};
+
+static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
+        { .irq = 96 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_gpio0_hwmod = {
+        .name           = "gpio1",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio0_irqs,
+        .main_clk       = "dpll_core_m4_div2_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio0_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
+        { .irq = 98 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio1_hwmod = {
+        .name           = "gpio2",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio1_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
+        { .irq = 32 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio2_hwmod = {
+        .name           = "gpio3",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio2_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
+        { .irq = 62 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod am33xx_gpio3_hwmod = {
+        .name           = "gpio4",
+        .class          = &am33xx_gpio_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = am33xx_gpio3_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpmc */
+static struct omap_hwmod_class_sysconfig gpmc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
+        .name           = "gpmc",
+        .sysc           = &gpmc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
+        { .irq = 100 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &am33xx_gpmc_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = am33xx_gpmc_irqs,
+        .main_clk       = "l3s_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'i2c' class */
+static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0090,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+        .name           = "i2c",
+        .sysc           = &am33xx_i2c_sysc,
+        .rev            = OMAP_I2C_IP_VERSION_2,
+        .reset          = &omap_i2c_reset,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+        { .irq = 70 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 0, },
+        { .name = "rx", .dma_req = 0, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = i2c1_mpu_irqs,
+        .sdma_reqs      = i2c1_edma_reqs,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+        { .irq = 71 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
+        { .name = "tx", .dma_req = 0, },
+        { .name = "rx", .dma_req = 0, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = i2c2_mpu_irqs,
+        .sdma_reqs      = i2c2_edma_reqs,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4 = {
+                        .clkctrl_offs   = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
+        { .name = "tx", .dma_req = 0, },
+        { .name = "rx", .dma_req = 0, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+        { .irq = 30 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .class          = &i2c_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = i2c3_mpu_irqs,
+        .sdma_reqs      = i2c3_edma_reqs,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+
+/* lcdc */
+static struct omap_hwmod_class_sysconfig lcdc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x54,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
+        .name           = "lcdc",
+        .sysc           = &lcdc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
+        { .irq = 36 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_lcdc_hwmod = {
+        .name           = "lcdc",
+        .class          = &am33xx_lcdc_hwmod_class,
+        .clkdm_name     = "lcdc_clkdm",
+        .mpu_irqs       = am33xx_lcdc_irqs,
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+        .main_clk       = "lcd_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+        .name   = "mailbox",
+        .sysc   = &am33xx_mailbox_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
+        { .irq = 77 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &am33xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_mailbox_irqs,
+        .main_clk       = "l4ls_gclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mcasp' class
+ */
+static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x4,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
+        .name           = "mcasp",
+        .sysc           = &am33xx_mcasp_sysc,
+};
+
+/* mcasp0 */
+static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
+        { .name = "ax", .irq = 80 + OMAP_INTC_START, },
+        { .name = "ar", .irq = 81 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
+        { .name = "tx", .dma_req = 8, },
+        { .name = "rx", .dma_req = 9, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp0_hwmod = {
+        .name           = "mcasp0",
+        .class          = &am33xx_mcasp_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_mcasp0_irqs,
+        .sdma_reqs      = am33xx_mcasp0_edma_reqs,
+        .main_clk       = "mcasp0_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* mcasp1 */
+static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
+        { .name = "ax", .irq = 82 + OMAP_INTC_START, },
+        { .name = "ar", .irq = 83 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 10, },
+        { .name = "rx", .dma_req = 11, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_mcasp1_hwmod = {
+        .name           = "mcasp1",
+        .class          = &am33xx_mcasp_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_mcasp1_irqs,
+        .sdma_reqs      = am33xx_mcasp1_edma_reqs,
+        .main_clk       = "mcasp1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'mmc' class */
+static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
+        .rev_offs       = 0x1fc,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
+        .name           = "mmc",
+        .sysc           = &am33xx_mmc_sysc,
+};
+
+/* mmc0 */
+static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
+        { .irq = 64 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
+        { .name = "tx", .dma_req = 24, },
+        { .name = "rx", .dma_req = 25, },
+        { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc0_hwmod = {
+        .name           = "mmc1",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_mmc0_irqs,
+        .sdma_reqs      = am33xx_mmc0_edma_reqs,
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc0_dev_attr,
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
+        { .irq = 28 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 2, },
+        { .name = "rx", .dma_req = 3, },
+        { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod am33xx_mmc1_hwmod = {
+        .name           = "mmc2",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_mmc1_irqs,
+        .sdma_reqs      = am33xx_mmc1_edma_reqs,
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
+        { .irq = 29 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
+        { .name = "tx", .dma_req = 64, },
+        { .name = "rx", .dma_req = 65, },
+        { .dma_req = -1 }
+};
+
+static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
+        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+static struct omap_hwmod am33xx_mmc2_hwmod = {
+        .name           = "mmc3",
+        .class          = &am33xx_mmc_hwmod_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_mmc2_irqs,
+        .sdma_reqs      = am33xx_mmc2_edma_reqs,
+        .main_clk       = "mmc_clk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &am33xx_mmc2_dev_attr,
+};
+
+/*
+ * 'rtc' class
+ * rtc subsystem
+ */
+static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
+        .rev_offs       = 0x0074,
+        .sysc_offs      = 0x0078,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
+                          SIDLE_SMART | SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
+        .name           = "rtc",
+        .sysc           = &am33xx_rtc_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
+        { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
+        { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_rtc_hwmod = {
+        .name           = "rtc",
+        .class          = &am33xx_rtc_hwmod_class,
+        .clkdm_name     = "l4_rtc_clkdm",
+        .mpu_irqs       = am33xx_rtc_irqs,
+        .main_clk       = "clk_32768_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'spi' class */
+static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0110,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                          SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_spi_hwmod_class = {
+        .name           = "mcspi",
+        .sysc           = &am33xx_mcspi_sysc,
+        .rev            = OMAP4_MCSPI_REV,
+};
+
+/* spi0 */
+static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
+        { .irq = 65 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
+        { .name = "rx0", .dma_req = 17 },
+        { .name = "tx0", .dma_req = 16 },
+        { .name = "rx1", .dma_req = 19 },
+        { .name = "tx1", .dma_req = 18 },
+        { .dma_req = -1 }
+};
+
+static struct omap2_mcspi_dev_attr mcspi_attrib = {
+        .num_chipselect = 2,
+};
+static struct omap_hwmod am33xx_spi0_hwmod = {
+        .name           = "spi0",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_spi0_irqs,
+        .sdma_reqs      = am33xx_mcspi0_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+
+/* spi1 */
+static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
+        { .irq = 125 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
+        { .name = "rx0", .dma_req = 43 },
+        { .name = "tx0", .dma_req = 42 },
+        { .name = "rx1", .dma_req = 45 },
+        { .name = "tx1", .dma_req = 44 },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod am33xx_spi1_hwmod = {
+        .name           = "spi1",
+        .class          = &am33xx_spi_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_spi1_irqs,
+        .sdma_reqs      = am33xx_mcspi1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi_attrib,
+};
+
+/*
+ * 'spinlock' class
+ * spinlock provides hardware assistance for synchronizing the
+ * processes running on multiple processors
+ */
+static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
+        .name           = "spinlock",
+};
+
+static struct omap_hwmod am33xx_spinlock_hwmod = {
+        .name           = "spinlock",
+        .class          = &am33xx_spinlock_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .main_clk       = "l4ls_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'timer 2-7' class */
+static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_timer_hwmod_class = {
+        .name           = "timer",
+        .sysc           = &am33xx_timer_sysc,
+};
+
+/* timer1 1ms */
+static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                        SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
+        .name           = "timer",
+        .sysc           = &am33xx_timer1ms_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
+        { .irq = 67 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer1_hwmod = {
+        .name           = "timer1",
+        .class          = &am33xx_timer1ms_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_timer1_irqs,
+        .main_clk       = "timer1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
+        { .irq = 68 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer2_hwmod = {
+        .name           = "timer2",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer2_irqs,
+        .main_clk       = "timer2_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
+        { .irq = 69 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer3_hwmod = {
+        .name           = "timer3",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer3_irqs,
+        .main_clk       = "timer3_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
+        { .irq = 92 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer4_hwmod = {
+        .name           = "timer4",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer4_irqs,
+        .main_clk       = "timer4_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
+        { .irq = 93 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer5_hwmod = {
+        .name           = "timer5",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer5_irqs,
+        .main_clk       = "timer5_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
+        { .irq = 94 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer6_hwmod = {
+        .name           = "timer6",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer6_irqs,
+        .main_clk       = "timer6_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
+        { .irq = 95 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_timer7_hwmod = {
+        .name           = "timer7",
+        .class          = &am33xx_timer_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_timer7_irqs,
+        .main_clk       = "timer7_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* tpcc */
+static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
+        .name           = "tpcc",
+};
+
+static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
+        { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
+        { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
+        { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tpcc_hwmod = {
+        .name           = "tpcc",
+        .class          = &am33xx_tpcc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tpcc_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                          SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+/* 'tptc' class */
+static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
+        .name           = "tptc",
+        .sysc           = &am33xx_tptc_sysc,
+};
+
+/* tptc0 */
+static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
+        { .irq = 112 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc0_hwmod = {
+        .name           = "tptc0",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tptc0_irqs,
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* tptc1 */
+static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
+        { .irq = 113 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc1_hwmod = {
+        .name           = "tptc1",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tptc1_irqs,
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* tptc2 */
+static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
+        { .irq = 114 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_tptc2_hwmod = {
+        .name           = "tptc2",
+        .class          = &am33xx_tptc_hwmod_class,
+        .clkdm_name     = "l3_clkdm",
+        .mpu_irqs       = am33xx_tptc2_irqs,
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "l3_gclk",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'uart' class */
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name           = "uart",
+        .sysc           = &uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
+        { .name = "tx", .dma_req = 26, },
+        { .name = "rx", .dma_req = 27, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
+        { .irq = 72 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &uart_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .mpu_irqs       = am33xx_uart1_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
+        { .irq = 73 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart2_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart3 */
+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+        { .name = "tx", .dma_req = 30, },
+        { .name = "rx", .dma_req = 31, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
+        { .irq = 74 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart3_irqs,
+        .sdma_reqs      = uart3_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
+        { .irq = 44 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart4_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
+        { .irq = 45 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart5_hwmod = {
+        .name           = "uart5",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart5_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
+        { .irq = 46 + OMAP_INTC_START, },
+        { .irq = -1 },
+};
+
+static struct omap_hwmod am33xx_uart6_hwmod = {
+        .name           = "uart6",
+        .class          = &uart_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .mpu_irqs       = am33xx_uart6_irqs,
+        .sdma_reqs      = uart1_edma_reqs,
+        .main_clk       = "dpll_per_m2_div4_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* 'wd_timer' class */
+static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+};
+
+/*
+ * XXX: device.c file uses hardcoded name for watchdog timer
+ * driver "wd_timer2, so we are also using same name as of now...
+ */
+static struct omap_hwmod am33xx_wd_timer1_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &am33xx_wd_timer_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .main_clk       = "wdt1_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'usb_otg' class
+ * high-speed on-the-go universal serial bus (usb_otg) controller
+ */
+static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_usbotg_class = {
+        .name           = "usbotg",
+        .sysc           = &am33xx_usbhsotg_sysc,
+};
+
+static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
+        { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
+        { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
+        { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
+        { .irq = -1 + OMAP_INTC_START, },
+};
+
+static struct omap_hwmod am33xx_usbss_hwmod = {
+        .name           = "usb_otg_hs",
+        .class          = &am33xx_usbotg_class,
+        .clkdm_name     = "l3s_clkdm",
+        .mpu_irqs       = am33xx_usbss_mpu_irqs,
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+        .main_clk       = "usbotg_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l4 fw -> emif fw */
+static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
+        .master         = &am33xx_l4_fw_hwmod,
+        .slave          = &am33xx_emif_fw_hwmod,
+        .clk            = "l4fw_gclk",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
+        {
+                .pa_start       = 0x4c000000,
+                .pa_end         = 0x4c000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3 main -> emif */
+static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_emif_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_emif_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
+        .master         = &am33xx_mpu_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "dpll_mpu_m2_ck",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> l4 hs */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l4_hs_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 s */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l3_s_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 per/ls */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_ls_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_wkup_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l4 fw */
+static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l4_fw_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> l3 instr */
+static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_l3_instr_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> prcm */
+static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
+        .master         = &am33xx_mpu_hwmod,
+        .slave          = &am33xx_prcm_hwmod,
+        .clk            = "dpll_mpu_m2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 s -> l3 main*/
+static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3s_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* pru-icss -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
+        .master         = &am33xx_pruss_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "l3_gclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* wkup m3 -> l4 wkup */
+static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
+        .master         = &am33xx_wkup_m3_hwmod,
+        .slave          = &am33xx_l4_wkup_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gfx -> l3 main */
+static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
+        .master         = &am33xx_gfx_hwmod,
+        .slave          = &am33xx_l3_main_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> wkup m3 */
+static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
+        {
+                .name           = "umem",
+                .pa_start       = 0x44d00000,
+                .pa_end         = 0x44d00000 + SZ_16K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "dmem",
+                .pa_start       = 0x44d80000,
+                .pa_end         = 0x44d80000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_wkup_m3_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_wkup_m3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 hs -> pru-icss */
+static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
+        {
+                .pa_start       = 0x4a300000,
+                .pa_end         = 0x4a300000 + SZ_512K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
+        .master         = &am33xx_l4_hs_hwmod,
+        .slave          = &am33xx_pruss_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_pruss_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> gfx */
+static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
+        {
+                .pa_start       = 0x56000000,
+                .pa_end         = 0x56000000 + SZ_16M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_gfx_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_gfx_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 wkup -> smartreflex0 */
+static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
+        {
+                .pa_start       = 0x44e37000,
+                .pa_end         = 0x44e37000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_smartreflex0_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_smartreflex0_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> smartreflex1 */
+static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
+        {
+                .pa_start       = 0x44e39000,
+                .pa_end         = 0x44e39000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_smartreflex1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_smartreflex1_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> control */
+static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
+        {
+                .pa_start       = 0x44e10000,
+                .pa_end         = 0x44e10000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_control_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_control_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> rtc */
+static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
+        {
+                .pa_start       = 0x44e3e000,
+                .pa_end         = 0x44e3e000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_rtc_hwmod,
+        .clk            = "clkdiv32k_ick",
+        .addr           = am33xx_rtc_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per/ls -> DCAN0 */
+static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
+        {
+                .pa_start       = 0x481CC000,
+                .pa_end         = 0x481CC000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_dcan0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_dcan0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> DCAN1 */
+static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
+        {
+                .pa_start       = 0x481D0000,
+                .pa_end         = 0x481D0000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_dcan1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_dcan1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> GPIO2 */
+static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x4804C000,
+                .pa_end         = 0x4804C000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_gpio1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio3 */
+static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x481AC000,
+                .pa_end         = 0x481AC000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_gpio2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 per/ls -> gpio4 */
+static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x481AE000,
+                .pa_end         = 0x481AE000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_gpio3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_gpio3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> I2C1 */
+static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
+        {
+                .pa_start       = 0x44E0B000,
+                .pa_end         = 0x44E0B000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_i2c1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_i2c1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* L4 WKUP -> GPIO1 */
+static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
+        {
+                .pa_start       = 0x44E07000,
+                .pa_end         = 0x44E07000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_gpio0_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_gpio0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 WKUP -> ADC_TSC */
+static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
+        {
+                .pa_start       = 0x44E0D000,
+                .pa_end         = 0x44E0D000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_adc_tsc_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_adc_tsc_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+        /* cpsw ss */
+        {
+                .pa_start       = 0x4a100000,
+                .pa_end         = 0x4a100000 + SZ_2K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        /* cpsw wr */
+        {
+                .pa_start       = 0x4a101200,
+                .pa_end         = 0x4a101200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
+        .master         = &am33xx_l4_hs_hwmod,
+        .slave          = &am33xx_cpgmac0_hwmod,
+        .clk            = "cpsw_125mhz_gclk",
+        .addr           = am33xx_cpgmac0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_elm_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_elm_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
+        {
+                .pa_start       = 0x48300000,
+                .pa_end         = 0x48300000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48300200,
+                .pa_end         = 0x48300200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ehrpwm0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
+        {
+                .pa_start       = 0x48302000,
+                .pa_end         = 0x48302000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48302200,
+                .pa_end         = 0x48302200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ehrpwm1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48304200,
+                .pa_end         = 0x48304200 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ehrpwm2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ehrpwm2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
+        {
+                .pa_start       = 0x48300000,
+                .pa_end         = 0x48300000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48300100,
+                .pa_end         = 0x48300100 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ecap0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ecap0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
+        {
+                .pa_start       = 0x48302000,
+                .pa_end         = 0x48302000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48302100,
+                .pa_end         = 0x48302100 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ecap1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ecap1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/*
+ * Splitting the resources to handle access of PWMSS config space
+ * and module specific part independently
+ */
+static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_16 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .pa_start       = 0x48304100,
+                .pa_end         = 0x48304100 + SZ_256 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_ecap2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_ecap2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3s cfg -> gpmc */
+static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
+        {
+                .pa_start       = 0x50000000,
+                .pa_end         = 0x50000000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_gpmc_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_gpmc_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* i2c2 */
+static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
+        {
+                .pa_start       = 0x4802A000,
+                .pa_end         = 0x4802A000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_i2c2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_i2c2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
+        {
+                .pa_start       = 0x4819C000,
+                .pa_end         = 0x4819C000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_i2c3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_i2c3_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
+        {
+                .pa_start       = 0x4830E000,
+                .pa_end         = 0x4830E000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_lcdc_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_lcdc_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x480C8000,
+                .pa_end         = 0x480C8000 + (SZ_4K - 1),
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4 ls -> mailbox */
+static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mailbox_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mailbox_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> spinlock */
+static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
+        {
+                .pa_start       = 0x480Ca000,
+                .pa_end         = 0x480Ca000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spinlock_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_spinlock_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcasp0 */
+static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
+        {
+                .pa_start       = 0x48038000,
+                .pa_end         = 0x48038000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mcasp0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcasp0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp0 data */
+static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
+        {
+                .pa_start       = 0x46000000,
+                .pa_end         = 0x46000000 + SZ_4M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_mcasp0_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_mcasp0_data_addr_space,
+        .user           = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mcasp1 */
+static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
+        {
+                .pa_start       = 0x4803C000,
+                .pa_end         = 0x4803C000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mcasp1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcasp1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 s -> mcasp1 data */
+static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
+        {
+                .pa_start       = 0x46400000,
+                .pa_end         = 0x46400000 + SZ_4M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_mcasp1_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_mcasp1_data_addr_space,
+        .user           = OCP_USER_SDMA,
+};
+
+/* l4 ls -> mmc0 */
+static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
+        {
+                .pa_start       = 0x48060100,
+                .pa_end         = 0x48060100 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mmc0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mmc0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mmc1 */
+static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
+        {
+                .pa_start       = 0x481d8100,
+                .pa_end         = 0x481d8100 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_mmc1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mmc1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 s -> mmc2 */
+static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
+        {
+                .pa_start       = 0x47810100,
+                .pa_end         = 0x47810100 + SZ_64K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_mmc2_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_mmc2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi0 */
+static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
+        {
+                .pa_start       = 0x48030000,
+                .pa_end         = 0x48030000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spi0_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcspi0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> mcspi1 */
+static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
+        {
+                .pa_start       = 0x481A0000,
+                .pa_end         = 0x481A0000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_spi1_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_mcspi1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> timer1 */
+static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
+        {
+                .pa_start       = 0x44E31000,
+                .pa_end         = 0x44E31000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_timer1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_timer1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer2 */
+static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
+        {
+                .pa_start       = 0x48040000,
+                .pa_end         = 0x48040000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer3 */
+static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
+        {
+                .pa_start       = 0x48042000,
+                .pa_end         = 0x48042000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer3_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer4 */
+static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
+        {
+                .pa_start       = 0x48044000,
+                .pa_end         = 0x48044000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer4_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer4_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer5 */
+static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
+        {
+                .pa_start       = 0x48046000,
+                .pa_end         = 0x48046000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer5_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer5_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer6 */
+static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
+        {
+                .pa_start       = 0x48048000,
+                .pa_end         = 0x48048000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer6_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer6_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 per -> timer7 */
+static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
+        {
+                .pa_start       = 0x4804A000,
+                .pa_end         = 0x4804A000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_timer7_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_timer7_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc */
+static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
+        {
+                .pa_start       = 0x49000000,
+                .pa_end         = 0x49000000 + SZ_32K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tpcc_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tpcc_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc0 */
+static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
+        {
+                .pa_start       = 0x49800000,
+                .pa_end         = 0x49800000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc0_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc0_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc1 */
+static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
+        {
+                .pa_start       = 0x49900000,
+                .pa_end         = 0x49900000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc1_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l3 main -> tpcc2 */
+static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
+        {
+                .pa_start       = 0x49a00000,
+                .pa_end         = 0x49a00000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_tptc2_hwmod,
+        .clk            = "l3_gclk",
+        .addr           = am33xx_tptc2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> uart1 */
+static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
+        {
+                .pa_start       = 0x44E09000,
+                .pa_end         = 0x44E09000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_uart1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_uart1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart2 */
+static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
+        {
+                .pa_start       = 0x48022000,
+                .pa_end         = 0x48022000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart2_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart3 */
+static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
+        {
+                .pa_start       = 0x48024000,
+                .pa_end         = 0x48024000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart3_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart3_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart4 */
+static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
+        {
+                .pa_start       = 0x481A6000,
+                .pa_end         = 0x481A6000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart4_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart4_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart5 */
+static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
+        {
+                .pa_start       = 0x481A8000,
+                .pa_end         = 0x481A8000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart5_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart5_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 ls -> uart6 */
+static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
+        {
+                .pa_start       = 0x481aa000,
+                .pa_end         = 0x481aa000 + SZ_8K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_uart6_hwmod,
+        .clk            = "l4ls_gclk",
+        .addr           = am33xx_uart6_addr_space,
+        .user           = OCP_USER_MPU,
+};
+
+/* l4 wkup -> wd_timer1 */
+static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
+        {
+                .pa_start       = 0x44e35000,
+                .pa_end         = 0x44e35000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
+        .master         = &am33xx_l4_wkup_hwmod,
+        .slave          = &am33xx_wd_timer1_hwmod,
+        .clk            = "dpll_core_m4_div2_ck",
+        .addr           = am33xx_wd_timer1_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+/* usbss */
+/* l3 s -> USBSS interface */
+static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
+        {
+                .name           = "usbss",
+                .pa_start       = 0x47400000,
+                .pa_end         = 0x47400000 + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "musb0",
+                .pa_start       = 0x47401000,
+                .pa_end         = 0x47401000 + SZ_2K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "musb1",
+                .pa_start       = 0x47401800,
+                .pa_end         = 0x47401800 + SZ_2K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
+        .master         = &am33xx_l3_s_hwmod,
+        .slave          = &am33xx_usbss_hwmod,
+        .clk            = "l3s_gclk",
+        .addr           = am33xx_usbss_addr_space,
+        .user           = OCP_USER_MPU,
+        .flags          = OCPIF_SWSUP_IDLE,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
+        &am33xx_l4_fw__emif_fw,
+        &am33xx_l3_main__emif,
+        &am33xx_mpu__l3_main,
+        &am33xx_mpu__prcm,
+        &am33xx_l3_s__l4_ls,
+        &am33xx_l3_s__l4_wkup,
+        &am33xx_l3_s__l4_fw,
+        &am33xx_l3_main__l4_hs,
+        &am33xx_l3_main__l3_s,
+        &am33xx_l3_main__l3_instr,
+        &am33xx_l3_main__gfx,
+        &am33xx_l3_s__l3_main,
+        &am33xx_pruss__l3_main,
+        &am33xx_wkup_m3__l4_wkup,
+        &am33xx_gfx__l3_main,
+        &am33xx_l4_wkup__wkup_m3,
+        &am33xx_l4_wkup__control,
+        &am33xx_l4_wkup__smartreflex0,
+        &am33xx_l4_wkup__smartreflex1,
+        &am33xx_l4_wkup__uart1,
+        &am33xx_l4_wkup__timer1,
+        &am33xx_l4_wkup__rtc,
+        &am33xx_l4_wkup__i2c1,
+        &am33xx_l4_wkup__gpio0,
+        &am33xx_l4_wkup__adc_tsc,
+        &am33xx_l4_wkup__wd_timer1,
+        &am33xx_l4_hs__pruss,
+        &am33xx_l4_per__dcan0,
+        &am33xx_l4_per__dcan1,
+        &am33xx_l4_per__gpio1,
+        &am33xx_l4_per__gpio2,
+        &am33xx_l4_per__gpio3,
+        &am33xx_l4_per__i2c2,
+        &am33xx_l4_per__i2c3,
+        &am33xx_l4_per__mailbox,
+        &am33xx_l4_ls__mcasp0,
+        &am33xx_l3_s__mcasp0_data,
+        &am33xx_l4_ls__mcasp1,
+        &am33xx_l3_s__mcasp1_data,
+        &am33xx_l4_ls__mmc0,
+        &am33xx_l4_ls__mmc1,
+        &am33xx_l3_s__mmc2,
+        &am33xx_l4_ls__timer2,
+        &am33xx_l4_ls__timer3,
+        &am33xx_l4_ls__timer4,
+        &am33xx_l4_ls__timer5,
+        &am33xx_l4_ls__timer6,
+        &am33xx_l4_ls__timer7,
+        &am33xx_l3_main__tpcc,
+        &am33xx_l4_ls__uart2,
+        &am33xx_l4_ls__uart3,
+        &am33xx_l4_ls__uart4,
+        &am33xx_l4_ls__uart5,
+        &am33xx_l4_ls__uart6,
+        &am33xx_l4_ls__spinlock,
+        &am33xx_l4_ls__elm,
+        &am33xx_l4_ls__ehrpwm0,
+        &am33xx_l4_ls__ehrpwm1,
+        &am33xx_l4_ls__ehrpwm2,
+        &am33xx_l4_ls__ecap0,
+        &am33xx_l4_ls__ecap1,
+        &am33xx_l4_ls__ecap2,
+        &am33xx_l3_s__gpmc,
+        &am33xx_l3_main__lcdc,
+        &am33xx_l4_ls__mcspi0,
+        &am33xx_l4_ls__mcspi1,
+        &am33xx_l3_main__tptc0,
+        &am33xx_l3_main__tptc1,
+        &am33xx_l3_main__tptc2,
+        &am33xx_l3_s__usbss,
+        &am33xx_l4_hs__cpgmac0,
+        NULL,
+};
+
+int __init am33xx_hwmod_init(void)
+{
+        omap_hwmod_init();
+        return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index cb2883d553b5..749220f91a70 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -87,6 +87,19 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
+static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
+
+        if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
+                return parent_rate;
+
+        camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
+
+        return parent_rate / (camdivn + 1) / 2;
+}
+
 /* Extra S3C2440 clocks */
 
 static struct clk s3c2440_clk_cam = {
@@ -99,6 +112,7 @@ static struct clk s3c2440_clk_cam_upll = {
         .name           = "camif-upll",
         .ops            = &(struct clk_ops) {
                 .set_rate       = s3c2440_camif_upll_setrate,
+                .get_rate       = s3c2440_camif_upll_getrate,
                 .round_rate     = s3c2440_camif_upll_round,
         },
 };
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 99ae066b87ed..1a413f07c8c4 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -763,6 +763,13 @@ static void __init kzm_init(void)
         platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));
 }
 
+static void kzm9g_restart(char mode, const char *cmd)
+{
+#define RESCNT2 IOMEM(0xe6188020)
+        /* Do soft power on reset */
+        writel((1 << 31), RESCNT2);
+}
+
 static const char *kzm9g_boards_compat_dt[] __initdata = {
         "renesas,kzm9g",
         NULL,
@@ -777,5 +784,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g")
         .init_machine   = kzm_init,
         .init_late      = shmobile_init_late,
         .timer          = &shmobile_timer,
+        .restart        = kzm9g_restart,
         .dt_compat      = kzm9g_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 339c62c824d5..3cafb6ab5e9a 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -86,11 +86,16 @@ static struct clk div4_clks[DIV4_NR] = {
                                       0x0300, CLK_ENABLE_ON_INIT),
 };
 
-enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+enum { MSTP323, MSTP322, MSTP321, MSTP320,
+        MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015, MSTP014,
         MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */
+        [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
+        [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
+        [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
         [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
         [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
         [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -149,6 +154,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
 };
 
 void __init r8a7779_clock_init(void)
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index dae9aa68bb09..61446f30e397 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -356,6 +356,26 @@ static struct platform_device gio4_device = {
         },
 };
 
+static struct resource pmu_resources[] = {
+        [0] = {
+                .start  = 152,
+                .end    = 152,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start  = 153,
+                .end    = 153,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device pmu_device = {
+        .name           = "arm-pmu",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pmu_resources),
+        .resource       = pmu_resources,
+};
+
 static struct platform_device *emev2_early_devices[] __initdata = {
         &uart0_device,
         &uart1_device,
@@ -370,6 +390,7 @@ static struct platform_device *emev2_late_devices[] __initdata = {
         &gio2_device,
         &gio3_device,
         &gio4_device,
+        &pmu_device,
 };
 
 void __init emev2_add_standard_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index a13c97b4ba1d..db99a4ade80c 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -734,6 +734,26 @@ static struct platform_device mpdma0_device = {
         },
 };
 
+static struct resource pmu_resources[] = {
+        [0] = {
+                .start  = gic_spi(55),
+                .end    = gic_spi(55),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [1] = {
+                .start  = gic_spi(56),
+                .end    = gic_spi(56),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device pmu_device = {
+        .name           = "arm-pmu",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pmu_resources),
+        .resource       = pmu_resources,
+};
+
 static struct platform_device *sh73a0_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -757,6 +777,7 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
         &i2c4_device,
         &dma0_device,
         &mpdma0_device,
+        &pmu_device,
 };
 
 #define SRCR2          IOMEM(0xe61580b0)
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 191d973122a5..77b19707be2a 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -12,9 +12,13 @@ obj-y					+= powergate.o
 obj-y                                   += apbio.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_CPU_IDLE)                  += sleep.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_clocks_data.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-t20.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += sleep-t30.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 37007d60bc37..5957ffbd4af6 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -70,6 +70,7 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 
 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
         /* name         parent          rate            enabled */
+        { "uarta",      "pll_p",        216000000,      true },
         { "uartd",      "pll_p",        216000000,      true },
         { "usbd",       "clk_m",        12000000,       false },
         { "usb2",       "clk_m",        12000000,       false },
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 58f981c0819c..fd82085eca5d 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,6 +1,7 @@
 /*
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@google.com>
@@ -19,8 +20,6 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/module.h>
@@ -32,325 +31,75 @@
 
 #include "board.h"
 #include "clock.h"
+#include "tegra_cpu_car.h"
+
+/* Global data of Tegra CPU CAR ops */
+struct tegra_cpu_car_ops *tegra_cpu_car_ops;
 
 /*
  * Locking:
  *
- * Each struct clk has a spinlock.
- *
- * To avoid AB-BA locking problems, locks must always be traversed from child
- * clock to parent clock.  For example, when enabling a clock, the clock's lock
- * is taken, and then clk_enable is called on the parent, which take's the
- * parent clock's lock.  There is one exceptions to this ordering: When dumping
- * the clock tree through debugfs.  In this case, clk_lock_all is called,
- * which attemps to iterate through the entire list of clocks and take every
- * clock lock.  If any call to spin_trylock fails, all locked clocks are
- * unlocked, and the process is retried.  When all the locks are held,
- * the only clock operation that can be called is clk_get_rate_all_locked.
- *
- * Within a single clock, no clock operation can call another clock operation
- * on itself, except for clk_get_rate_locked and clk_set_rate_locked.  Any
- * clock operation can call any other clock operation on any of it's possible
- * parents.
- *
  * An additional mutex, clock_list_lock, is used to protect the list of all
  * clocks.
  *
- * The clock operations must lock internally to protect against
- * read-modify-write on registers that are shared by multiple clocks
  */
 static DEFINE_MUTEX(clock_list_lock);
 static LIST_HEAD(clocks);
 
-struct clk *tegra_get_clock_by_name(const char *name)
-{
-        struct clk *c;
-        struct clk *ret = NULL;
-        mutex_lock(&clock_list_lock);
-        list_for_each_entry(c, &clocks, node) {
-                if (strcmp(c->name, name) == 0) {
-                        ret = c;
-                        break;
-                }
-        }
-        mutex_unlock(&clock_list_lock);
-        return ret;
-}
-
-/* Must be called with c->spinlock held */
-static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p)
-{
-        u64 rate;
-
-        rate = clk_get_rate(p);
-
-        if (c->mul != 0 && c->div != 0) {
-                rate *= c->mul;
-                rate += c->div - 1; /* round up */
-                do_div(rate, c->div);
-        }
-
-        return rate;
-}
-
-/* Must be called with c->spinlock held */
-unsigned long clk_get_rate_locked(struct clk *c)
-{
-        unsigned long rate;
-
-        if (c->parent)
-                rate = clk_predict_rate_from_parent(c, c->parent);
-        else
-                rate = c->rate;
-
-        return rate;
-}
-
-unsigned long clk_get_rate(struct clk *c)
+void tegra_clk_add(struct clk *clk)
 {
-        unsigned long flags;
-        unsigned long rate;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        rate = clk_get_rate_locked(c);
-
-        spin_unlock_irqrestore(&c->spinlock, flags);
-
-        return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_reparent(struct clk *c, struct clk *parent)
-{
-        c->parent = parent;
-        return 0;
-}
-
-void clk_init(struct clk *c)
-{
-        spin_lock_init(&c->spinlock);
-
-        if (c->ops && c->ops->init)
-                c->ops->init(c);
-
-        if (!c->ops || !c->ops->enable) {
-                c->refcnt++;
-                c->set = true;
-                if (c->parent)
-                        c->state = c->parent->state;
-                else
-                        c->state = ON;
-        }
+        struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
 
         mutex_lock(&clock_list_lock);
         list_add(&c->node, &clocks);
         mutex_unlock(&clock_list_lock);
 }
 
-int clk_enable(struct clk *c)
-{
-        int ret = 0;
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        if (c->refcnt == 0) {
-                if (c->parent) {
-                        ret = clk_enable(c->parent);
-                        if (ret)
-                                goto out;
-                }
-
-                if (c->ops && c->ops->enable) {
-                        ret = c->ops->enable(c);
-                        if (ret) {
-                                if (c->parent)
-                                        clk_disable(c->parent);
-                                goto out;
-                        }
-                        c->state = ON;
-                        c->set = true;
-                }
-        }
-        c->refcnt++;
-out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *c)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        if (c->refcnt == 0) {
-                WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
-                spin_unlock_irqrestore(&c->spinlock, flags);
-                return;
-        }
-        if (c->refcnt == 1) {
-                if (c->ops && c->ops->disable)
-                        c->ops->disable(c);
-
-                if (c->parent)
-                        clk_disable(c->parent);
-
-                c->state = OFF;
-        }
-        c->refcnt--;
-
-        spin_unlock_irqrestore(&c->spinlock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-int clk_set_parent(struct clk *c, struct clk *parent)
-{
-        int ret;
-        unsigned long flags;
-        unsigned long new_rate;
-        unsigned long old_rate;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        if (!c->ops || !c->ops->set_parent) {
-                ret = -ENOSYS;
-                goto out;
-        }
-
-        new_rate = clk_predict_rate_from_parent(c, parent);
-        old_rate = clk_get_rate_locked(c);
-
-        ret = c->ops->set_parent(c, parent);
-        if (ret)
-                goto out;
-
-out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *c)
-{
-        return c->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_rate_locked(struct clk *c, unsigned long rate)
-{
-        long new_rate;
-
-        if (!c->ops || !c->ops->set_rate)
-                return -ENOSYS;
-
-        if (rate > c->max_rate)
-                rate = c->max_rate;
-
-        if (c->ops && c->ops->round_rate) {
-                new_rate = c->ops->round_rate(c, rate);
-
-                if (new_rate < 0)
-                        return new_rate;
-
-                rate = new_rate;
-        }
-
-        return c->ops->set_rate(c, rate);
-}
-
-int clk_set_rate(struct clk *c, unsigned long rate)
-{
-        int ret;
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        ret = clk_set_rate_locked(c, rate);
-
-        spin_unlock_irqrestore(&c->spinlock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-
-/* Must be called with clocks lock and all indvidual clock locks held */
-unsigned long clk_get_rate_all_locked(struct clk *c)
+struct clk *tegra_get_clock_by_name(const char *name)
 {
-        u64 rate;
-        int mul = 1;
-        int div = 1;
-        struct clk *p = c;
-
-        while (p) {
-                c = p;
-                if (c->mul != 0 && c->div != 0) {
-                        mul *= c->mul;
-                        div *= c->div;
+        struct clk_tegra *c;
+        struct clk *ret = NULL;
+        mutex_lock(&clock_list_lock);
+        list_for_each_entry(c, &clocks, node) {
+                if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
+                        ret = c->hw.clk;
+                        break;
                 }
-                p = c->parent;
-        }
-
-        rate = c->rate;
-        rate *= mul;
-        do_div(rate, div);
-
-        return rate;
-}
-
-long clk_round_rate(struct clk *c, unsigned long rate)
-{
-        unsigned long flags;
-        long ret;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        if (!c->ops || !c->ops->round_rate) {
-                ret = -ENOSYS;
-                goto out;
         }
-
-        if (rate > c->max_rate)
-                rate = c->max_rate;
-
-        ret = c->ops->round_rate(c, rate);
-
-out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
+        mutex_unlock(&clock_list_lock);
         return ret;
 }
-EXPORT_SYMBOL(clk_round_rate);
 
 static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
 {
         struct clk *c;
         struct clk *p;
+        struct clk *parent;
 
         int ret = 0;
 
         c = tegra_get_clock_by_name(table->name);
 
         if (!c) {
-                pr_warning("Unable to initialize clock %s\n",
+                pr_warn("Unable to initialize clock %s\n",
                         table->name);
                 return -ENODEV;
         }
 
+        parent = clk_get_parent(c);
+
         if (table->parent) {
                 p = tegra_get_clock_by_name(table->parent);
                 if (!p) {
-                        pr_warning("Unable to find parent %s of clock %s\n",
+                        pr_warn("Unable to find parent %s of clock %s\n",
                                 table->parent, table->name);
                         return -ENODEV;
                 }
 
-                if (c->parent != p) {
+                if (parent != p) {
                         ret = clk_set_parent(c, p);
                         if (ret) {
-                                pr_warning("Unable to set parent %s of clock %s: %d\n",
+                                pr_warn("Unable to set parent %s of clock %s: %d\n",
                                         table->parent, table->name, ret);
                                 return -EINVAL;
                         }
@@ -360,16 +109,16 @@ static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
         if (table->rate && table->rate != clk_get_rate(c)) {
                 ret = clk_set_rate(c, table->rate);
                 if (ret) {
-                        pr_warning("Unable to set clock %s to rate %lu: %d\n",
+                        pr_warn("Unable to set clock %s to rate %lu: %d\n",
                                 table->name, table->rate, ret);
                         return -EINVAL;
                 }
         }
 
         if (table->enabled) {
-                ret = clk_enable(c);
+                ret = clk_prepare_enable(c);
                 if (ret) {
-                        pr_warning("Unable to enable clock %s: %d\n",
+                        pr_warn("Unable to enable clock %s: %d\n",
                                 table->name, ret);
                         return -EINVAL;
                 }
@@ -383,19 +132,20 @@ void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
         for (; table->name; table++)
                 tegra_clk_init_one_from_table(table);
 }
-EXPORT_SYMBOL(tegra_clk_init_from_table);
 
 void tegra_periph_reset_deassert(struct clk *c)
 {
-        BUG_ON(!c->ops->reset);
-        c->ops->reset(c, false);
+        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
+        BUG_ON(!clk->reset);
+        clk->reset(__clk_get_hw(c), false);
 }
 EXPORT_SYMBOL(tegra_periph_reset_deassert);
 
 void tegra_periph_reset_assert(struct clk *c)
 {
-        BUG_ON(!c->ops->reset);
-        c->ops->reset(c, true);
+        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
+        BUG_ON(!clk->reset);
+        clk->reset(__clk_get_hw(c), true);
 }
 EXPORT_SYMBOL(tegra_periph_reset_assert);
 
@@ -405,268 +155,14 @@ EXPORT_SYMBOL(tegra_periph_reset_assert);
 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 {
         int ret = 0;
-        unsigned long flags;
+        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
 
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        if (!c->ops || !c->ops->clk_cfg_ex) {
+        if (!clk->clk_cfg_ex) {
                 ret = -ENOSYS;
                 goto out;
         }
-        ret = c->ops->clk_cfg_ex(c, p, setting);
+        ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
 
 out:
-        spin_unlock_irqrestore(&c->spinlock, flags);
-
         return ret;
 }
-
-#ifdef CONFIG_DEBUG_FS
-
-static int __clk_lock_all_spinlocks(void)
-{
-        struct clk *c;
-
-        list_for_each_entry(c, &clocks, node)
-                if (!spin_trylock(&c->spinlock))
-                        goto unlock_spinlocks;
-
-        return 0;
-
-unlock_spinlocks:
-        list_for_each_entry_continue_reverse(c, &clocks, node)
-                spin_unlock(&c->spinlock);
-
-        return -EAGAIN;
-}
-
-static void __clk_unlock_all_spinlocks(void)
-{
-        struct clk *c;
-
-        list_for_each_entry_reverse(c, &clocks, node)
-                spin_unlock(&c->spinlock);
-}
-
-/*
- * This function retries until it can take all locks, and may take
- * an arbitrarily long time to complete.
- * Must be called with irqs enabled, returns with irqs disabled
- * Must be called with clock_list_lock held
- */
-static void clk_lock_all(void)
-{
-        int ret;
-retry:
-        local_irq_disable();
-
-        ret = __clk_lock_all_spinlocks();
-        if (ret)
-                goto failed_spinlocks;
-
-        /* All locks taken successfully, return */
-        return;
-
-failed_spinlocks:
-        local_irq_enable();
-        yield();
-        goto retry;
-}
-
-/*
- * Unlocks all clocks after a clk_lock_all
- * Must be called with irqs disabled, returns with irqs enabled
- * Must be called with clock_list_lock held
- */
-static void clk_unlock_all(void)
-{
-        __clk_unlock_all_spinlocks();
-
-        local_irq_enable();
-}
-
-static struct dentry *clk_debugfs_root;
-
-
-static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
-{
-        struct clk *child;
-        const char *state = "uninit";
-        char div[8] = {0};
-
-        if (c->state == ON)
-                state = "on";
-        else if (c->state == OFF)
-                state = "off";
-
-        if (c->mul != 0 && c->div != 0) {
-                if (c->mul > c->div) {
-                        int mul = c->mul / c->div;
-                        int mul2 = (c->mul * 10 / c->div) % 10;
-                        int mul3 = (c->mul * 10) % c->div;
-                        if (mul2 == 0 && mul3 == 0)
-                                snprintf(div, sizeof(div), "x%d", mul);
-                        else if (mul3 == 0)
-                                snprintf(div, sizeof(div), "x%d.%d", mul, mul2);
-                        else
-                                snprintf(div, sizeof(div), "x%d.%d..", mul, mul2);
-                } else {
-                        snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
-                                (c->div % c->mul) ? ".5" : "");
-                }
-        }
-
-        seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n",
-                level * 3 + 1, "",
-                c->rate > c->max_rate ? '!' : ' ',
-                !c->set ? '*' : ' ',
-                30 - level * 3, c->name,
-                state, c->refcnt, div, clk_get_rate_all_locked(c));
-
-        list_for_each_entry(child, &clocks, node) {
-                if (child->parent != c)
-                        continue;
-
-                clock_tree_show_one(s, child, level + 1);
-        }
-}
-
-static int clock_tree_show(struct seq_file *s, void *data)
-{
-        struct clk *c;
-        seq_printf(s, "   clock                          state  ref div      rate\n");
-        seq_printf(s, "--------------------------------------------------------------\n");
-
-        mutex_lock(&clock_list_lock);
-
-        clk_lock_all();
-
-        list_for_each_entry(c, &clocks, node)
-                if (c->parent == NULL)
-                        clock_tree_show_one(s, c, 0);
-
-        clk_unlock_all();
-
-        mutex_unlock(&clock_list_lock);
-        return 0;
-}
-
-static int clock_tree_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, clock_tree_show, inode->i_private);
-}
-
-static const struct file_operations clock_tree_fops = {
-        .open           = clock_tree_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int possible_parents_show(struct seq_file *s, void *data)
-{
-        struct clk *c = s->private;
-        int i;
-
-        for (i = 0; c->inputs[i].input; i++) {
-                char *first = (i == 0) ? "" : " ";
-                seq_printf(s, "%s%s", first, c->inputs[i].input->name);
-        }
-        seq_printf(s, "\n");
-        return 0;
-}
-
-static int possible_parents_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, possible_parents_show, inode->i_private);
-}
-
-static const struct file_operations possible_parents_fops = {
-        .open           = possible_parents_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int clk_debugfs_register_one(struct clk *c)
-{
-        struct dentry *d;
-
-        d = debugfs_create_dir(c->name, clk_debugfs_root);
-        if (!d)
-                return -ENOMEM;
-        c->dent = d;
-
-        d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
-        if (!d)
-                goto err_out;
-
-        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
-        if (!d)
-                goto err_out;
-
-        if (c->inputs) {
-                d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
-                        c, &possible_parents_fops);
-                if (!d)
-                        goto err_out;
-        }
-
-        return 0;
-
-err_out:
-        debugfs_remove_recursive(c->dent);
-        return -ENOMEM;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-        int err;
-        struct clk *pa = c->parent;
-
-        if (pa && !pa->dent) {
-                err = clk_debugfs_register(pa);
-                if (err)
-                        return err;
-        }
-
-        if (!c->dent) {
-                err = clk_debugfs_register_one(c);
-                if (err)
-                        return err;
-        }
-        return 0;
-}
-
-int __init tegra_clk_debugfs_init(void)
-{
-        struct clk *c;
-        struct dentry *d;
-        int err = -ENOMEM;
-
-        d = debugfs_create_dir("clock", NULL);
-        if (!d)
-                return -ENOMEM;
-        clk_debugfs_root = d;
-
-        d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
-                &clock_tree_fops);
-        if (!d)
-                goto err_out;
-
-        list_for_each_entry(c, &clocks, node) {
-                err = clk_debugfs_register(c);
-                if (err)
-                        goto err_out;
-        }
-        return 0;
-err_out:
-        debugfs_remove_recursive(clk_debugfs_root);
-        return err;
-}
-
-#endif
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index bc300657deba..2aa37f5c44c0 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/include/mach/clock.h
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@google.com>
@@ -20,9 +21,9 @@
 #ifndef __MACH_TEGRA_CLOCK_H
 #define __MACH_TEGRA_CLOCK_H
 
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/list.h>
-#include <linux/spinlock.h>
 
 #include <mach/clk.h>
 
@@ -52,7 +53,8 @@
 #define ENABLE_ON_INIT          (1 << 28)
 #define PERIPH_ON_APB           (1 << 29)
 
-struct clk;
+struct clk_tegra;
+#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
 
 struct clk_mux_sel {
         struct clk      *input;
@@ -68,47 +70,29 @@ struct clk_pll_freq_table {
         u8              cpcon;
 };
 
-struct clk_ops {
-        void            (*init)(struct clk *);
-        int             (*enable)(struct clk *);
-        void            (*disable)(struct clk *);
-        int             (*set_parent)(struct clk *, struct clk *);
-        int             (*set_rate)(struct clk *, unsigned long);
-        long            (*round_rate)(struct clk *, unsigned long);
-        void            (*reset)(struct clk *, bool);
-        int             (*clk_cfg_ex)(struct clk *,
-                                enum tegra_clk_ex_param, u32);
-};
-
 enum clk_state {
         UNINITIALIZED = 0,
         ON,
         OFF,
 };
 
-struct clk {
+struct clk_tegra {
         /* node for master clocks list */
-        struct list_head        node;           /* node for list of all clocks */
+        struct list_head        node;   /* node for list of all clocks */
         struct clk_lookup       lookup;
+        struct clk_hw           hw;
 
-#ifdef CONFIG_DEBUG_FS
-        struct dentry           *dent;
-#endif
         bool                    set;
-        struct clk_ops          *ops;
-        unsigned long           rate;
+        unsigned long           fixed_rate;
         unsigned long           max_rate;
         unsigned long           min_rate;
         u32                     flags;
         const char              *name;
 
-        u32                     refcnt;
         enum clk_state          state;
-        struct clk              *parent;
         u32                     div;
         u32                     mul;
 
-        const struct clk_mux_sel        *inputs;
         u32                             reg;
         u32                             reg_shift;
 
@@ -144,7 +128,8 @@ struct clk {
                 } shared_bus_user;
         } u;
 
-        spinlock_t spinlock;
+        void (*reset)(struct clk_hw *, bool);
+        int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
 };
 
 struct clk_duplicate {
@@ -159,13 +144,10 @@ struct tegra_clk_init_table {
         bool enabled;
 };
 
+void tegra_clk_add(struct clk *c);
 void tegra2_init_clocks(void);
 void tegra30_init_clocks(void);
-void clk_init(struct clk *clk);
 struct clk *tegra_get_clock_by_name(const char *name);
-int clk_reparent(struct clk *c, struct clk *parent);
 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
-unsigned long clk_get_rate_locked(struct clk *c);
-int clk_set_rate_locked(struct clk *c, unsigned long rate);
 
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 96fef6bcc651..0560538bf598 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -34,6 +34,7 @@
 #include "fuse.h"
 #include "pmc.h"
 #include "apbio.h"
+#include "sleep.h"
 
 /*
  * Storage for debug-macro.S's state.
@@ -135,6 +136,7 @@ void __init tegra20_init_early(void)
         tegra_init_cache(0x331, 0x441);
         tegra_pmc_init();
         tegra_powergate_init();
+        tegra20_hotplug_init();
 }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
@@ -147,11 +149,11 @@ void __init tegra30_init_early(void)
         tegra_init_cache(0x441, 0x551);
         tegra_pmc_init();
         tegra_powergate_init();
+        tegra30_hotplug_init();
 }
 #endif
 
 void __init tegra_init_late(void)
 {
-        tegra_clk_debugfs_init();
         tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index ceb52db1e2f1..627bf0f4262e 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -49,6 +49,8 @@ static struct cpufreq_frequency_table freq_table[] = {
 #define NUM_CPUS        2
 
 static struct clk *cpu_clk;
+static struct clk *pll_x_clk;
+static struct clk *pll_p_clk;
 static struct clk *emc_clk;
 
 static unsigned long target_cpu_speed[NUM_CPUS];
@@ -71,6 +73,42 @@ static unsigned int tegra_getspeed(unsigned int cpu)
         return rate;
 }
 
+static int tegra_cpu_clk_set_rate(unsigned long rate)
+{
+        int ret;
+
+        /*
+         * Take an extra reference to the main pll so it doesn't turn
+         * off when we move the cpu off of it
+         */
+        clk_prepare_enable(pll_x_clk);
+
+        ret = clk_set_parent(cpu_clk, pll_p_clk);
+        if (ret) {
+                pr_err("Failed to switch cpu to clock pll_p\n");
+                goto out;
+        }
+
+        if (rate == clk_get_rate(pll_p_clk))
+                goto out;
+
+        ret = clk_set_rate(pll_x_clk, rate);
+        if (ret) {
+                pr_err("Failed to change pll_x to %lu\n", rate);
+                goto out;
+        }
+
+        ret = clk_set_parent(cpu_clk, pll_x_clk);
+        if (ret) {
+                pr_err("Failed to switch cpu to clock pll_x\n");
+                goto out;
+        }
+
+out:
+        clk_disable_unprepare(pll_x_clk);
+        return ret;
+}
+
 static int tegra_update_cpu_speed(unsigned long rate)
 {
         int ret = 0;
@@ -101,7 +139,7 @@ static int tegra_update_cpu_speed(unsigned long rate)
                freqs.old, freqs.new);
 #endif
 
-        ret = clk_set_rate(cpu_clk, freqs.new * 1000);
+        ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
         if (ret) {
                 pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
                         freqs.new);
@@ -183,6 +221,14 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
         if (IS_ERR(cpu_clk))
                 return PTR_ERR(cpu_clk);
 
+        pll_x_clk = clk_get_sys(NULL, "pll_x");
+        if (IS_ERR(pll_x_clk))
+                return PTR_ERR(pll_x_clk);
+
+        pll_p_clk = clk_get_sys(NULL, "pll_p");
+        if (IS_ERR(pll_p_clk))
+                return PTR_ERR(pll_p_clk);
+
         emc_clk = clk_get_sys("cpu", "emc");
         if (IS_ERR(emc_clk)) {
                 clk_put(cpu_clk);
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fef9c2c51370..6addc78cb6b2 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,17 +7,13 @@
 
 #include "flowctrl.h"
 #include "reset.h"
+#include "sleep.h"
 
 #define APB_MISC_GP_HIDREV      0x804
 #define PMC_SCRATCH41   0x140
 
 #define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
 
-        .macro mov32, reg, val
-        movw    \reg, #:lower16:\val
-        movt    \reg, #:upper16:\val
-        .endm
-
         .section ".text.head", "ax"
         __CPUINIT
 
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d8dc9ddd6d18..d02a35476135 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,91 +1,23 @@
 /*
- *  linux/arch/arm/mach-realview/hotplug.c
  *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
+ *  Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #include <linux/kernel.h>
-#include <linux/errno.h>
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
-#include <asm/cp15.h>
+#include <asm/smp_plat.h>
 
-static inline void cpu_enter_lowpower(void)
-{
-        unsigned int v;
-
-        flush_cache_all();
-        asm volatile(
-        "       mcr     p15, 0, %1, c7, c5, 0\n"
-        "       mcr     p15, 0, %1, c7, c10, 4\n"
-        /*
-         * Turn off coherency
-         */
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, #0x20\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, %2\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-          : "=&r" (v)
-          : "r" (0), "Ir" (CR_C)
-          : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-        unsigned int v;
-
-        asm volatile(
-        "mrc    p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       orr     %0, %0, #0x20\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-          : "=&r" (v)
-          : "Ir" (CR_C)
-          : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
-        /*
-         * there is no power-control hardware on this platform, so all
-         * we can do is put the core into WFI; this is safe as the calling
-         * code will have already disabled interrupts
-         */
-        for (;;) {
-                /*
-                 * here's the WFI
-                 */
-                asm(".word      0xe320f003\n"
-                    :
-                    :
-                    : "memory", "cc");
+#include "sleep.h"
+#include "tegra_cpu_car.h"
 
-                /*if (pen_release == cpu) {*/
-                        /*
-                         * OK, proper wakeup, we're done
-                         */
-                        break;
-                /*}*/
-
-                /*
-                 * Getting here, means that we have come out of WFI without
-                 * having been woken up - this shouldn't happen
-                 *
-                 * Just note it happening - when we're woken, we can report
-                 * its occurrence.
-                 */
-                (*spurious)++;
-        }
-}
+static void (*tegra_hotplug_shutdown)(void);
 
 int platform_cpu_kill(unsigned int cpu)
 {
@@ -99,22 +31,20 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-        int spurious = 0;
+        cpu = cpu_logical_map(cpu);
 
-        /*
-         * we're ready for shutdown now, so do it
-         */
-        cpu_enter_lowpower();
-        platform_do_lowpower(cpu, &spurious);
+        /* Flush the L1 data cache. */
+        flush_cache_all();
 
-        /*
-         * bring this CPU back into the world of cache
-         * coherency, and then restore interrupts
-         */
-        cpu_leave_lowpower();
+        /* Shut down the current CPU. */
+        tegra_hotplug_shutdown();
 
-        if (spurious)
-                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+        /* Clock gate the CPU */
+        tegra_wait_cpu_in_reset(cpu);
+        tegra_disable_cpu_clock(cpu);
+
+        /* Should never return here. */
+        BUG();
 }
 
 int platform_cpu_disable(unsigned int cpu)
@@ -125,3 +55,19 @@ int platform_cpu_disable(unsigned int cpu)
          */
         return cpu == 0 ? -EPERM : 0;
 }
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+extern void tegra20_hotplug_shutdown(void);
+void __init tegra20_hotplug_init(void)
+{
+        tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+}
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+extern void tegra30_hotplug_shutdown(void);
+void __init tegra30_hotplug_init(void)
+{
+        tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+}
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index d97e403303a0..95f3a547c770 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -34,7 +34,10 @@ enum tegra_clk_ex_param {
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
+#ifndef CONFIG_COMMON_CLK
 unsigned long clk_get_rate_all_locked(struct clk *c);
+#endif
+
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
 
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1a208dbf682f..96ed1718eef0 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -31,6 +31,7 @@
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
+#include "tegra_cpu_car.h"
 
 extern void tegra_secondary_startup(void);
 
@@ -38,17 +39,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
 
 #define EVP_CPU_RESET_VECTOR \
         (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
-        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
-
-#define CPU_CLOCK(cpu)  (0x1<<(8+cpu))
-#define CPU_RESET(cpu)  (0x1111ul<<(cpu))
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
@@ -63,13 +53,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 
 static int tegra20_power_up_cpu(unsigned int cpu)
 {
-        u32 reg;
-
         /* Enable the CPU clock. */
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        barrier();
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        tegra_enable_cpu_clock(cpu);
 
         /* Clear flow controller CSR. */
         flowctrl_write_cpu_csr(cpu, 0);
@@ -79,7 +64,6 @@ static int tegra20_power_up_cpu(unsigned int cpu)
 
 static int tegra30_power_up_cpu(unsigned int cpu)
 {
-        u32 reg;
         int ret, pwrgateid;
         unsigned long timeout;
 
@@ -103,8 +87,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
         }
 
         /* CPU partition is powered. Enable the CPU clock. */
-        writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+        tegra_enable_cpu_clock(cpu);
         udelay(10);
 
         /* Remove I/O clamps. */
@@ -128,8 +111,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * via the flow controller). This will have no effect on first boot
          * of the CPU since it should already be in reset.
          */
-        writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
-        dmb();
+        tegra_put_cpu_in_reset(cpu);
 
         /*
          * Unhalt the CPU. If the flow controller was used to power-gate the
@@ -155,8 +137,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
                 goto done;
 
         /* Take the CPU out of reset. */
-        writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
-        wmb();
+        tegra_cpu_out_of_reset(cpu);
 done:
         return status;
 }
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S
new file mode 100644
index 000000000000..a36ae413e2b8
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t20.S
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2011, Google, Inc.
+ *
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra20_hotplug_shutdown(void)
+ *
+ * puts the current cpu in reset
+ * should never return
+ */
+ENTRY(tegra20_hotplug_shutdown)
+        /* Turn off SMP coherency */
+        exit_smp r4, r5
+
+        /* Put this CPU down */
+        cpu_id  r0
+        bl      tegra20_cpu_shutdown
+        mov     pc, lr                  @ should never get here
+ENDPROC(tegra20_hotplug_shutdown)
+
+/*
+ * tegra20_cpu_shutdown(int cpu)
+ *
+ * r0 is cpu to reset
+ *
+ * puts the specified CPU in wait-for-event mode on the flow controller
+ * and puts the CPU in reset
+ * can be called on the current cpu or another cpu
+ * if called on the current cpu, does not return
+ * MUST NOT BE CALLED FOR CPU 0.
+ *
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra20_cpu_shutdown)
+        cmp     r0, #0
+        moveq   pc, lr                  @ must not be called for CPU 0
+
+        cpu_to_halt_reg r1, r0
+        ldr     r3, =TEGRA_FLOW_CTRL_VIRT
+        mov     r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
+        str     r2, [r3, r1]            @ put flow controller in wait event mode
+        ldr     r2, [r3, r1]
+        isb
+        dsb
+        movw    r1, 0x1011
+        mov     r1, r1, lsl r0
+        ldr     r3, =TEGRA_CLK_RESET_VIRT
+        str     r1, [r3, #0x340]        @ put slave CPU in reset
+        isb
+        dsb
+        cpu_id  r3
+        cmp     r3, r0
+        beq     .
+        mov     pc, lr
+ENDPROC(tegra20_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
new file mode 100644
index 000000000000..777d9cee8b90
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#define TEGRA30_POWER_HOTPLUG_SHUTDOWN  (1 << 27) /* Hotplug shutdown */
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra30_hotplug_shutdown(void)
+ *
+ * Powergates the current CPU.
+ * Should never return.
+ */
+ENTRY(tegra30_hotplug_shutdown)
+        /* Turn off SMP coherency */
+        exit_smp r4, r5
+
+        /* Powergate this CPU */
+        mov     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        bl      tegra30_cpu_shutdown
+        mov     pc, lr                  @ should never get here
+ENDPROC(tegra30_hotplug_shutdown)
+
+/*
+ * tegra30_cpu_shutdown(unsigned long flags)
+ *
+ * Puts the current CPU in wait-for-event mode on the flow controller
+ * and powergates it -- flags (in R0) indicate the request type.
+ * Must never be called for CPU 0.
+ *
+ * corrupts r0-r4, r12
+ */
+ENTRY(tegra30_cpu_shutdown)
+        cpu_id  r3
+        cmp     r3, #0
+        moveq   pc, lr          @ Must never be called for CPU 0
+
+        ldr     r12, =TEGRA_FLOW_CTRL_VIRT
+        cpu_to_csr_reg r1, r3
+        add     r1, r1, r12     @ virtual CSR address for this CPU
+        cpu_to_halt_reg r2, r3
+        add     r2, r2, r12     @ virtual HALT_EVENTS address for this CPU
+
+        /*
+         * Clear this CPU's "event" and "interrupt" flags and power gate
+         * it when halting but not before it is in the "WFE" state.
+         */
+        movw    r12, \
+                FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
+                FLOW_CTRL_CSR_ENABLE
+        mov     r4, #(1 << 4)
+        orr     r12, r12, r4, lsl r3
+        str     r12, [r1]
+
+        /* Halt this CPU. */
+        mov     r3, #0x400
+delay_1:
+        subs    r3, r3, #1                      @ delay as a part of wfe war.
+        bge     delay_1;
+        cpsid   a                               @ disable imprecise aborts.
+        ldr     r3, [r1]                        @ read CSR
+        str     r3, [r1]                        @ clear CSR
+        tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        movne   r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
+        str     r3, [r2]
+        ldr     r0, [r2]
+        b       wfe_war
+
+__cpu_reset_again:
+        dsb
+        .align 5
+        wfe                                     @ CPU should be power gated here
+wfe_war:
+        b       __cpu_reset_again
+
+        /*
+         * 38 nop's, which fills reset of wfe cache line and
+         * 4 more cachelines with nop
+         */
+        .rept 38
+        nop
+        .endr
+        b       .                               @ should never get here
+
+ENDPROC(tegra30_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index d29b156a8011..ea81554c4833 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -29,36 +29,5 @@
 #include <mach/iomap.h>
 
 #include "flowctrl.h"
+#include "sleep.h"
 
-#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
-                                        + IO_PPSB_VIRT)
-
-/* returns the offset of the flow controller halt register for a cpu */
-.macro cpu_to_halt_reg rd, rcpu
-        cmp     \rcpu, #0
-        subne   \rd, \rcpu, #1
-        movne   \rd, \rd, lsl #3
-        addne   \rd, \rd, #0x14
-        moveq   \rd, #0
-.endm
-
-/* returns the offset of the flow controller csr register for a cpu */
-.macro cpu_to_csr_reg rd, rcpu
-        cmp     \rcpu, #0
-        subne   \rd, \rcpu, #1
-        movne   \rd, \rd, lsl #3
-        addne   \rd, \rd, #0x18
-        moveq   \rd, #8
-.endm
-
-/* returns the ID of the current processor */
-.macro cpu_id, rd
-        mrc     p15, 0, \rd, c0, c0, 5
-        and     \rd, \rd, #0xF
-.endm
-
-/* loads a 32-bit value into a register without a data access */
-.macro mov32, reg, val
-        movw    \reg, #:lower16:\val
-        movt    \reg, #:upper16:\val
-.endm
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
new file mode 100644
index 000000000000..e25a7cd703d9
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_SLEEP_H
+#define __MACH_TEGRA_SLEEP_H
+
+#include <mach/iomap.h>
+
+#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
+                                        + IO_CPU_VIRT)
+#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
+                                        + IO_PPSB_VIRT)
+#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
+                                        + IO_PPSB_VIRT)
+
+#ifdef __ASSEMBLY__
+/* returns the offset of the flow controller halt register for a cpu */
+.macro cpu_to_halt_reg rd, rcpu
+        cmp     \rcpu, #0
+        subne   \rd, \rcpu, #1
+        movne   \rd, \rd, lsl #3
+        addne   \rd, \rd, #0x14
+        moveq   \rd, #0
+.endm
+
+/* returns the offset of the flow controller csr register for a cpu */
+.macro cpu_to_csr_reg rd, rcpu
+        cmp     \rcpu, #0
+        subne   \rd, \rcpu, #1
+        movne   \rd, \rd, lsl #3
+        addne   \rd, \rd, #0x18
+        moveq   \rd, #8
+.endm
+
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+        mrc     p15, 0, \rd, c0, c0, 5
+        and     \rd, \rd, #0xF
+.endm
+
+/* loads a 32-bit value into a register without a data access */
+.macro mov32, reg, val
+        movw    \reg, #:lower16:\val
+        movt    \reg, #:upper16:\val
+.endm
+
+/* Macro to exit SMP coherency. */
+.macro exit_smp, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
+        bic     \tmp1, \tmp1, #(1<<6) | (1<<0)  @ clear ACTLR.SMP | ACTLR.FW
+        mcr     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
+        isb
+        cpu_id  \tmp1
+        mov     \tmp1, \tmp1, lsl #2
+        mov     \tmp2, #0xf
+        mov     \tmp2, \tmp2, lsl \tmp1
+        mov32   \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
+        str     \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
+        dsb
+.endm
+#else
+
+#ifdef CONFIG_HOTPLUG_CPU
+void tegra20_hotplug_init(void);
+void tegra30_hotplug_init(void);
+#else
+static inline void tegra20_hotplug_init(void) {}
+static inline void tegra30_hotplug_init(void) {}
+#endif
+
+#endif
+#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
new file mode 100644
index 000000000000..9273b0dffc66
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -0,0 +1,1625 @@
+/*
+ * arch/arm/mach-tegra/tegra20_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+
+#include <mach/iomap.h>
+#include <mach/suspend.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra2_emc.h"
+#include "tegra_cpu_car.h"
+
+#define RST_DEVICES                     0x004
+#define RST_DEVICES_SET                 0x300
+#define RST_DEVICES_CLR                 0x304
+#define RST_DEVICES_NUM                 3
+
+#define CLK_OUT_ENB                     0x010
+#define CLK_OUT_ENB_SET                 0x320
+#define CLK_OUT_ENB_CLR                 0x324
+#define CLK_OUT_ENB_NUM                 3
+
+#define CLK_MASK_ARM                    0x44
+#define MISC_CLK_ENB                    0x48
+
+#define OSC_CTRL                        0x50
+#define OSC_CTRL_OSC_FREQ_MASK          (3<<30)
+#define OSC_CTRL_OSC_FREQ_13MHZ         (0<<30)
+#define OSC_CTRL_OSC_FREQ_19_2MHZ       (1<<30)
+#define OSC_CTRL_OSC_FREQ_12MHZ         (2<<30)
+#define OSC_CTRL_OSC_FREQ_26MHZ         (3<<30)
+#define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
+
+#define OSC_FREQ_DET                    0x58
+#define OSC_FREQ_DET_TRIG               (1<<31)
+
+#define OSC_FREQ_DET_STATUS             0x5C
+#define OSC_FREQ_DET_BUSY               (1<<31)
+#define OSC_FREQ_DET_CNT_MASK           0xFFFF
+
+#define PERIPH_CLK_SOURCE_I2S1          0x100
+#define PERIPH_CLK_SOURCE_EMC           0x19c
+#define PERIPH_CLK_SOURCE_OSC           0x1fc
+#define PERIPH_CLK_SOURCE_NUM \
+        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
+
+#define PERIPH_CLK_SOURCE_MASK          (3<<30)
+#define PERIPH_CLK_SOURCE_SHIFT         30
+#define PERIPH_CLK_SOURCE_PWM_MASK      (7<<28)
+#define PERIPH_CLK_SOURCE_PWM_SHIFT     28
+#define PERIPH_CLK_SOURCE_ENABLE        (1<<28)
+#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
+#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
+#define PERIPH_CLK_SOURCE_DIV_SHIFT     0
+
+#define SDMMC_CLK_INT_FB_SEL            (1 << 23)
+#define SDMMC_CLK_INT_FB_DLY_SHIFT      16
+#define SDMMC_CLK_INT_FB_DLY_MASK       (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
+
+#define PLL_BASE                        0x0
+#define PLL_BASE_BYPASS                 (1<<31)
+#define PLL_BASE_ENABLE                 (1<<30)
+#define PLL_BASE_REF_ENABLE             (1<<29)
+#define PLL_BASE_OVERRIDE               (1<<28)
+#define PLL_BASE_DIVP_MASK              (0x7<<20)
+#define PLL_BASE_DIVP_SHIFT             20
+#define PLL_BASE_DIVN_MASK              (0x3FF<<8)
+#define PLL_BASE_DIVN_SHIFT             8
+#define PLL_BASE_DIVM_MASK              (0x1F)
+#define PLL_BASE_DIVM_SHIFT             0
+
+#define PLL_OUT_RATIO_MASK              (0xFF<<8)
+#define PLL_OUT_RATIO_SHIFT             8
+#define PLL_OUT_OVERRIDE                (1<<2)
+#define PLL_OUT_CLKEN                   (1<<1)
+#define PLL_OUT_RESET_DISABLE           (1<<0)
+
+#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
+
+#define PLL_MISC_DCCON_SHIFT            20
+#define PLL_MISC_CPCON_SHIFT            8
+#define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
+#define PLL_MISC_LFCON_SHIFT            4
+#define PLL_MISC_LFCON_MASK             (0xF<<PLL_MISC_LFCON_SHIFT)
+#define PLL_MISC_VCOCON_SHIFT           0
+#define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
+
+#define PLLU_BASE_POST_DIV              (1<<20)
+
+#define PLLD_MISC_CLKENABLE             (1<<30)
+#define PLLD_MISC_DIV_RST               (1<<23)
+#define PLLD_MISC_DCCON_SHIFT           12
+
+#define PLLE_MISC_READY                 (1 << 15)
+
+#define PERIPH_CLK_TO_ENB_REG(c)        ((c->u.periph.clk_num / 32) * 4)
+#define PERIPH_CLK_TO_ENB_SET_REG(c)    ((c->u.periph.clk_num / 32) * 8)
+#define PERIPH_CLK_TO_ENB_BIT(c)        (1 << (c->u.periph.clk_num % 32))
+
+#define SUPER_CLK_MUX                   0x00
+#define SUPER_STATE_SHIFT               28
+#define SUPER_STATE_MASK                (0xF << SUPER_STATE_SHIFT)
+#define SUPER_STATE_STANDBY             (0x0 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IDLE                (0x1 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_RUN                 (0x2 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IRQ                 (0x3 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_FIQ                 (0x4 << SUPER_STATE_SHIFT)
+#define SUPER_SOURCE_MASK               0xF
+#define SUPER_FIQ_SOURCE_SHIFT          12
+#define SUPER_IRQ_SOURCE_SHIFT          8
+#define SUPER_RUN_SOURCE_SHIFT          4
+#define SUPER_IDLE_SOURCE_SHIFT         0
+
+#define SUPER_CLK_DIVIDER               0x04
+
+#define BUS_CLK_DISABLE                 (1<<3)
+#define BUS_CLK_DIV_MASK                0x3
+
+#define PMC_CTRL                        0x0
+ #define PMC_CTRL_BLINK_ENB             (1 << 7)
+
+#define PMC_DPD_PADS_ORIDE              0x1c
+ #define PMC_DPD_PADS_ORIDE_BLINK_ENB   (1 << 20)
+
+#define PMC_BLINK_TIMER_DATA_ON_SHIFT   0
+#define PMC_BLINK_TIMER_DATA_ON_MASK    0x7fff
+#define PMC_BLINK_TIMER_ENB             (1 << 15)
+#define PMC_BLINK_TIMER_DATA_OFF_SHIFT  16
+#define PMC_BLINK_TIMER_DATA_OFF_MASK   0xffff
+
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
+
+#define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
+#define CPU_RESET(cpu)  (0x1111ul << (cpu))
+
+static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+
+/*
+ * Some clocks share a register with other clocks.  Any clock op that
+ * non-atomically modifies a register used by another clock must lock
+ * clock_register_lock first.
+ */
+static DEFINE_SPINLOCK(clock_register_lock);
+
+/*
+ * Some peripheral clocks share an enable bit, so refcount the enable bits
+ * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
+ */
+static int tegra_periph_clk_enable_refcount[3 * 32];
+
+#define clk_writel(value, reg) \
+        __raw_writel(value, reg_clk_base + (reg))
+#define clk_readl(reg) \
+        __raw_readl(reg_clk_base + (reg))
+#define pmc_writel(value, reg) \
+        __raw_writel(value, reg_pmc_base + (reg))
+#define pmc_readl(reg) \
+        __raw_readl(reg_pmc_base + (reg))
+
+static unsigned long clk_measure_input_freq(void)
+{
+        u32 clock_autodetect;
+        clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
+        do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
+        clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
+        if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
+                return 12000000;
+        } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
+                return 13000000;
+        } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
+                return 19200000;
+        } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
+                return 26000000;
+        } else {
+                pr_err("%s: Unexpected clock autodetect value %d",
+                                                __func__, clock_autodetect);
+                BUG();
+                return 0;
+        }
+}
+
+static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+        s64 divider_u71 = parent_rate * 2;
+        divider_u71 += rate - 1;
+        do_div(divider_u71, rate);
+
+        if (divider_u71 - 2 < 0)
+                return 0;
+
+        if (divider_u71 - 2 > 255)
+                return -EINVAL;
+
+        return divider_u71 - 2;
+}
+
+static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+        s64 divider_u16;
+
+        divider_u16 = parent_rate;
+        divider_u16 += rate - 1;
+        do_div(divider_u16, rate);
+
+        if (divider_u16 - 1 < 0)
+                return 0;
+
+        if (divider_u16 - 1 > 0xFFFF)
+                return -EINVAL;
+
+        return divider_u16 - 1;
+}
+
+static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra_clk_32k_ops = {
+        .recalc_rate = tegra_clk_fixed_recalc_rate,
+};
+
+/* clk_m functions */
+static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        if (!to_clk_tegra(hw)->fixed_rate)
+                to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
+        return to_clk_tegra(hw)->fixed_rate;
+}
+
+static void tegra20_clk_m_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 osc_ctrl = clk_readl(OSC_CTRL);
+        u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
+
+        switch (c->fixed_rate) {
+        case 12000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
+                break;
+        case 13000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
+                break;
+        case 19200000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
+                break;
+        case 26000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
+                break;
+        default:
+                BUG();
+        }
+        clk_writel(auto_clock_control, OSC_CTRL);
+}
+
+struct clk_ops tegra_clk_m_ops = {
+        .init = tegra20_clk_m_init,
+        .recalc_rate = tegra20_clk_m_recalc_rate,
+};
+
+/* super clock functions */
+/* "super clocks" on tegra have two-stage muxes and a clock skipping
+ * super divider.  We will ignore the clock skipping divider, since we
+ * can't lower the voltage when using the clock skip, but we can if we
+ * lower the PLL frequency.
+ */
+static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+
+        val = clk_readl(c->reg + SUPER_CLK_MUX);
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        c->state = ON;
+        return c->state;
+}
+
+static int tegra20_super_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
+        return 0;
+}
+
+static void tegra20_super_clk_disable(struct clk_hw *hw)
+{
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        /* oops - don't disable the CPU clock! */
+        BUG();
+}
+
+static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        int val = clk_readl(c->reg + SUPER_CLK_MUX);
+        int source;
+        int shift;
+
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        source = (val >> shift) & SUPER_SOURCE_MASK;
+        return source;
+}
+
+static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
+        int shift;
+
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        val &= ~(SUPER_SOURCE_MASK << shift);
+        val |= index << shift;
+
+        clk_writel(val, c->reg);
+
+        return 0;
+}
+
+/* FIX ME: Need to switch parents to change the source PLL rate */
+static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        return prate;
+}
+
+static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        return *prate;
+}
+
+static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        return 0;
+}
+
+struct clk_ops tegra_super_ops = {
+        .is_enabled = tegra20_super_clk_is_enabled,
+        .enable = tegra20_super_clk_enable,
+        .disable = tegra20_super_clk_disable,
+        .set_parent = tegra20_super_clk_set_parent,
+        .get_parent = tegra20_super_clk_get_parent,
+        .set_rate = tegra20_super_clk_set_rate,
+        .round_rate = tegra20_super_clk_round_rate,
+        .recalc_rate = tegra20_super_clk_recalc_rate,
+};
+
+static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
+}
+
+struct clk_ops tegra_twd_ops = {
+        .recalc_rate = tegra20_twd_clk_recalc_rate,
+};
+
+static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
+{
+        return 0;
+}
+
+struct clk_ops tegra_cop_ops = {
+        .get_parent = tegra20_cop_clk_get_parent,
+};
+
+/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
+ * reset the COP block (i.e. AVP) */
+void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
+{
+        unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
+
+        pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
+        clk_writel(1 << 1, reg);
+}
+
+/* bus clock functions */
+static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+
+        c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
+        return c->state;
+}
+
+static int tegra20_bus_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 val;
+
+        spin_lock_irqsave(&clock_register_lock, flags);
+
+        val = clk_readl(c->reg);
+        val &= ~(BUS_CLK_DISABLE << c->reg_shift);
+        clk_writel(val, c->reg);
+
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+
+        return 0;
+}
+
+static void tegra20_bus_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 val;
+
+        spin_lock_irqsave(&clock_register_lock, flags);
+
+        val = clk_readl(c->reg);
+        val |= BUS_CLK_DISABLE << c->reg_shift;
+        clk_writel(val, c->reg);
+
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+}
+
+static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        u64 rate = prate;
+
+        c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
+        c->mul = 1;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+
+static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        int ret = -EINVAL;
+        unsigned long flags;
+        u32 val;
+        int i;
+
+        spin_lock_irqsave(&clock_register_lock, flags);
+
+        val = clk_readl(c->reg);
+        for (i = 1; i <= 4; i++) {
+                if (rate == parent_rate / i) {
+                        val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
+                        val |= (i - 1) << c->reg_shift;
+                        clk_writel(val, c->reg);
+                        c->div = i;
+                        c->mul = 1;
+                        ret = 0;
+                        break;
+                }
+        }
+
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+
+        return ret;
+}
+
+static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        unsigned long parent_rate = *prate;
+        s64 divider;
+
+        if (rate >= parent_rate)
+                return rate;
+
+        divider = parent_rate;
+        divider += rate - 1;
+        do_div(divider, rate);
+
+        if (divider < 0)
+                return divider;
+
+        if (divider > 4)
+                divider = 4;
+        do_div(parent_rate, divider);
+
+        return parent_rate;
+}
+
+struct clk_ops tegra_bus_ops = {
+        .is_enabled = tegra20_bus_clk_is_enabled,
+        .enable = tegra20_bus_clk_enable,
+        .disable = tegra20_bus_clk_disable,
+        .set_rate = tegra20_bus_clk_set_rate,
+        .round_rate = tegra20_bus_clk_round_rate,
+        .recalc_rate = tegra20_bus_clk_recalc_rate,
+};
+
+/* Blink output functions */
+static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+
+        val = pmc_readl(PMC_CTRL);
+        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
+        return c->state;
+}
+
+static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = prate;
+        u32 val;
+
+        c->mul = 1;
+        val = pmc_readl(c->reg);
+
+        if (val & PMC_BLINK_TIMER_ENB) {
+                unsigned int on_off;
+
+                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+                        PMC_BLINK_TIMER_DATA_ON_MASK;
+                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off += val;
+                /* each tick in the blink timer is 4 32KHz clocks */
+                c->div = on_off * 4;
+        } else {
+                c->div = 1;
+        }
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+
+static int tegra20_blink_clk_enable(struct clk_hw *hw)
+{
+        u32 val;
+
+        val = pmc_readl(PMC_DPD_PADS_ORIDE);
+        pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+
+        val = pmc_readl(PMC_CTRL);
+        pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
+
+        return 0;
+}
+
+static void tegra20_blink_clk_disable(struct clk_hw *hw)
+{
+        u32 val;
+
+        val = pmc_readl(PMC_CTRL);
+        pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
+
+        val = pmc_readl(PMC_DPD_PADS_ORIDE);
+        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+}
+
+static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        if (rate >= parent_rate) {
+                c->div = 1;
+                pmc_writel(0, c->reg);
+        } else {
+                unsigned int on_off;
+                u32 val;
+
+                on_off = DIV_ROUND_UP(parent_rate / 8, rate);
+                c->div = on_off * 8;
+
+                val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
+                        PMC_BLINK_TIMER_DATA_ON_SHIFT;
+                on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val |= on_off;
+                val |= PMC_BLINK_TIMER_ENB;
+                pmc_writel(val, c->reg);
+        }
+
+        return 0;
+}
+
+static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        int div;
+        int mul;
+        long round_rate = *prate;
+
+        mul = 1;
+
+        if (rate >= *prate) {
+                div = 1;
+        } else {
+                div = DIV_ROUND_UP(*prate / 8, rate);
+                div *= 8;
+        }
+
+        round_rate *= mul;
+        round_rate += div - 1;
+        do_div(round_rate, div);
+
+        return round_rate;
+}
+
+struct clk_ops tegra_blink_clk_ops = {
+        .is_enabled = tegra20_blink_clk_is_enabled,
+        .enable = tegra20_blink_clk_enable,
+        .disable = tegra20_blink_clk_disable,
+        .set_rate = tegra20_blink_clk_set_rate,
+        .round_rate = tegra20_blink_clk_round_rate,
+        .recalc_rate = tegra20_blink_clk_recalc_rate,
+};
+
+/* PLL Functions */
+static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
+{
+        udelay(c->u.pll.lock_delay);
+        return 0;
+}
+
+static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg + PLL_BASE);
+
+        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+        return c->state;
+}
+
+static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
+                                unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg + PLL_BASE);
+        u64 rate = prate;
+
+        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+                const struct clk_pll_freq_table *sel;
+                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                        if (sel->input_rate == prate &&
+                                sel->output_rate == c->u.pll.fixed_rate) {
+                                c->mul = sel->n;
+                                c->div = sel->m * sel->p;
+                                break;
+                        }
+                }
+                pr_err("Clock %s has unknown fixed frequency\n",
+                        __clk_get_name(hw->clk));
+                BUG();
+        } else if (val & PLL_BASE_BYPASS) {
+                c->mul = 1;
+                c->div = 1;
+        } else {
+                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+                if (c->flags & PLLU)
+                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+                else
+                        c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
+        }
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+
+static int tegra20_pll_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        val = clk_readl(c->reg + PLL_BASE);
+        val &= ~PLL_BASE_BYPASS;
+        val |= PLL_BASE_ENABLE;
+        clk_writel(val, c->reg + PLL_BASE);
+
+        tegra20_pll_clk_wait_for_lock(c);
+
+        return 0;
+}
+
+static void tegra20_pll_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        val = clk_readl(c->reg);
+        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+        clk_writel(val, c->reg);
+}
+
+static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long input_rate = parent_rate;
+        const struct clk_pll_freq_table *sel;
+        u32 val;
+
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+        if (c->flags & PLL_FIXED) {
+                int ret = 0;
+                if (rate != c->u.pll.fixed_rate) {
+                        pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
+                                __func__, __clk_get_name(hw->clk),
+                                c->u.pll.fixed_rate, rate);
+                        ret = -EINVAL;
+                }
+                return ret;
+        }
+
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        c->mul = sel->n;
+                        c->div = sel->m * sel->p;
+
+                        val = clk_readl(c->reg + PLL_BASE);
+                        if (c->flags & PLL_FIXED)
+                                val |= PLL_BASE_OVERRIDE;
+                        val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
+                                 PLL_BASE_DIVM_MASK);
+                        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
+                                (sel->n << PLL_BASE_DIVN_SHIFT);
+                        BUG_ON(sel->p < 1 || sel->p > 2);
+                        if (c->flags & PLLU) {
+                                if (sel->p == 1)
+                                        val |= PLLU_BASE_POST_DIV;
+                        } else {
+                                if (sel->p == 2)
+                                        val |= 1 << PLL_BASE_DIVP_SHIFT;
+                        }
+                        clk_writel(val, c->reg + PLL_BASE);
+
+                        if (c->flags & PLL_HAS_CPCON) {
+                                val = clk_readl(c->reg + PLL_MISC(c));
+                                val &= ~PLL_MISC_CPCON_MASK;
+                                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
+                                clk_writel(val, c->reg + PLL_MISC(c));
+                        }
+
+                        if (c->state == ON)
+                                tegra20_pll_clk_enable(hw);
+                        return 0;
+                }
+        }
+        return -EINVAL;
+}
+
+static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        const struct clk_pll_freq_table *sel;
+        unsigned long input_rate = *prate;
+        u64 output_rate = *prate;
+        int mul;
+        int div;
+
+        if (c->flags & PLL_FIXED)
+                return c->u.pll.fixed_rate;
+
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        mul = sel->n;
+                        div = sel->m * sel->p;
+                        break;
+                }
+
+        if (sel->input_rate == 0)
+                return -EINVAL;
+
+        output_rate *= mul;
+        output_rate += div - 1; /* round up */
+        do_div(output_rate, div);
+
+        return output_rate;
+}
+
+struct clk_ops tegra_pll_ops = {
+        .is_enabled = tegra20_pll_clk_is_enabled,
+        .enable = tegra20_pll_clk_enable,
+        .disable = tegra20_pll_clk_disable,
+        .set_rate = tegra20_pll_clk_set_rate,
+        .recalc_rate = tegra20_pll_clk_recalc_rate,
+        .round_rate = tegra20_pll_clk_round_rate,
+};
+
+static void tegra20_pllx_clk_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        if (tegra_sku_id == 7)
+                c->max_rate = 750000000;
+}
+
+struct clk_ops tegra_pllx_ops = {
+        .init = tegra20_pllx_clk_init,
+        .is_enabled = tegra20_pll_clk_is_enabled,
+        .enable = tegra20_pll_clk_enable,
+        .disable = tegra20_pll_clk_disable,
+        .set_rate = tegra20_pll_clk_set_rate,
+        .recalc_rate = tegra20_pll_clk_recalc_rate,
+        .round_rate = tegra20_pll_clk_round_rate,
+};
+
+static int tegra20_plle_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        mdelay(1);
+
+        val = clk_readl(c->reg + PLL_BASE);
+        if (!(val & PLLE_MISC_READY))
+                return -EBUSY;
+
+        val = clk_readl(c->reg + PLL_BASE);
+        val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
+        clk_writel(val, c->reg + PLL_BASE);
+
+        return 0;
+}
+
+struct clk_ops tegra_plle_ops = {
+        .is_enabled = tegra20_pll_clk_is_enabled,
+        .enable = tegra20_plle_clk_enable,
+        .set_rate = tegra20_pll_clk_set_rate,
+        .recalc_rate = tegra20_pll_clk_recalc_rate,
+        .round_rate = tegra20_pll_clk_round_rate,
+};
+
+/* Clock divider ops */
+static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+
+        val >>= c->reg_shift;
+        c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
+        if (!(val & PLL_OUT_RESET_DISABLE))
+                c->state = OFF;
+        return c->state;
+}
+
+static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = prate;
+        u32 val = clk_readl(c->reg);
+        u32 divu71;
+
+        val >>= c->reg_shift;
+
+        if (c->flags & DIV_U71) {
+                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+                c->div = (divu71 + 2);
+                c->mul = 2;
+        } else if (c->flags & DIV_2) {
+                c->div = 2;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+
+        rate *= c->mul;
+        rate += c->div - 1; /* round up */
+        do_div(rate, c->div);
+
+        return rate;
+}
+
+static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 new_val;
+        u32 val;
+
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
+
+        if (c->flags & DIV_U71) {
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                new_val = val >> c->reg_shift;
+                new_val &= 0xFFFF;
+
+                new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+
+                val &= ~(0xFFFF << c->reg_shift);
+                val |= new_val << c->reg_shift;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+                return 0;
+        } else if (c->flags & DIV_2) {
+                BUG_ON(!(c->flags & PLLD));
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                val &= ~PLLD_MISC_DIV_RST;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 new_val;
+        u32 val;
+
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
+
+        if (c->flags & DIV_U71) {
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                new_val = val >> c->reg_shift;
+                new_val &= 0xFFFF;
+
+                new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
+
+                val &= ~(0xFFFF << c->reg_shift);
+                val |= new_val << c->reg_shift;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+        } else if (c->flags & DIV_2) {
+                BUG_ON(!(c->flags & PLLD));
+                spin_lock_irqsave(&clock_register_lock, flags);
+                val = clk_readl(c->reg);
+                val |= PLLD_MISC_DIV_RST;
+                clk_writel(val, c->reg);
+                spin_unlock_irqrestore(&clock_register_lock, flags);
+        }
+}
+
+static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        int divider_u71;
+        u32 new_val;
+        u32 val;
+
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+        if (c->flags & DIV_U71) {
+                divider_u71 = clk_div71_get_divider(parent_rate, rate);
+                if (divider_u71 >= 0) {
+                        spin_lock_irqsave(&clock_register_lock, flags);
+                        val = clk_readl(c->reg);
+                        new_val = val >> c->reg_shift;
+                        new_val &= 0xFFFF;
+                        if (c->flags & DIV_U71_FIXED)
+                                new_val |= PLL_OUT_OVERRIDE;
+                        new_val &= ~PLL_OUT_RATIO_MASK;
+                        new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
+
+                        val &= ~(0xFFFF << c->reg_shift);
+                        val |= new_val << c->reg_shift;
+                        clk_writel(val, c->reg);
+                        c->div = divider_u71 + 2;
+                        c->mul = 2;
+                        spin_unlock_irqrestore(&clock_register_lock, flags);
+                        return 0;
+                }
+        } else if (c->flags & DIV_2) {
+                if (parent_rate == rate * 2)
+                        return 0;
+        }
+        return -EINVAL;
+}
+
+static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = *prate;
+        int divider;
+
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+        } else if (c->flags & DIV_2) {
+                return DIV_ROUND_UP(parent_rate, 2);
+        }
+        return -EINVAL;
+}
+
+struct clk_ops tegra_pll_div_ops = {
+        .is_enabled = tegra20_pll_div_clk_is_enabled,
+        .enable = tegra20_pll_div_clk_enable,
+        .disable = tegra20_pll_div_clk_disable,
+        .set_rate = tegra20_pll_div_clk_set_rate,
+        .round_rate = tegra20_pll_div_clk_round_rate,
+        .recalc_rate = tegra20_pll_div_clk_recalc_rate,
+};
+
+/* Periph clk ops */
+
+static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        c->state = ON;
+
+        if (!c->u.periph.clk_num)
+                goto out;
+
+        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+                        PERIPH_CLK_TO_ENB_BIT(c)))
+                c->state = OFF;
+
+        if (!(c->flags & PERIPH_NO_RESET))
+                if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
+                                PERIPH_CLK_TO_ENB_BIT(c))
+                        c->state = OFF;
+
+out:
+        return c->state;
+}
+
+static int tegra20_periph_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+        u32 val;
+
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        if (!c->u.periph.clk_num)
+                return 0;
+
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
+                return 0;
+
+        spin_lock_irqsave(&clock_register_lock, flags);
+
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+        if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
+                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                        RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+        if (c->flags & PERIPH_EMC_ENB) {
+                /* The EMC peripheral clock has 2 extra enable bits */
+                /* FIXME: Do they need to be disabled? */
+                val = clk_readl(c->reg);
+                val |= 0x3 << 24;
+                clk_writel(val, c->reg);
+        }
+
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+
+        return 0;
+}
+
+static void tegra20_periph_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long flags;
+
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+        if (!c->u.periph.clk_num)
+                return;
+
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
+                return;
+
+        spin_lock_irqsave(&clock_register_lock, flags);
+
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+
+        spin_unlock_irqrestore(&clock_register_lock, flags);
+}
+
+void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
+
+        pr_debug("%s %s on clock %s\n", __func__,
+                assert ? "assert" : "deassert", __clk_get_name(hw->clk));
+
+        BUG_ON(!c->u.periph.clk_num);
+
+        if (!(c->flags & PERIPH_NO_RESET))
+                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                           base + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+
+static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        u32 mask;
+        u32 shift;
+
+        pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
+
+        if (c->flags & MUX_PWM) {
+                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+                mask = PERIPH_CLK_SOURCE_PWM_MASK;
+        } else {
+                shift = PERIPH_CLK_SOURCE_SHIFT;
+                mask = PERIPH_CLK_SOURCE_MASK;
+        }
+
+        val = clk_readl(c->reg);
+        val &= ~mask;
+        val |= (index) << shift;
+
+        clk_writel(val, c->reg);
+
+        return 0;
+}
+
+static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        u32 mask;
+        u32 shift;
+
+        if (c->flags & MUX_PWM) {
+                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+                mask = PERIPH_CLK_SOURCE_PWM_MASK;
+        } else {
+                shift = PERIPH_CLK_SOURCE_SHIFT;
+                mask = PERIPH_CLK_SOURCE_MASK;
+        }
+
+        if (c->flags & MUX)
+                return (val & mask) >> shift;
+        else
+                return 0;
+}
+
+static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long rate = prate;
+        u32 val = clk_readl(c->reg);
+
+        if (c->flags & DIV_U71) {
+                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+                c->div = divu71 + 2;
+                c->mul = 2;
+        } else if (c->flags & DIV_U16) {
+                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+                c->div = divu16 + 1;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+                return rate;
+        }
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
+}
+
+static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        int divider;
+
+        val = clk_readl(c->reg);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(parent_rate, rate);
+
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
+                        val |= divider;
+                        clk_writel(val, c->reg);
+                        c->div = divider + 2;
+                        c->mul = 2;
+                        return 0;
+                }
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(parent_rate, rate);
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
+                        val |= divider;
+                        clk_writel(val, c->reg);
+                        c->div = divider + 1;
+                        c->mul = 1;
+                        return 0;
+                }
+        } else if (parent_rate <= rate) {
+                c->div = 1;
+                c->mul = 1;
+                return 0;
+        }
+
+        return -EINVAL;
+}
+
+static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
+        unsigned long rate, unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+        int divider;
+
+        pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+        if (prate)
+                parent_rate = *prate;
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+
+                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate, divider + 1);
+        }
+        return -EINVAL;
+}
+
+struct clk_ops tegra_periph_clk_ops = {
+        .is_enabled = tegra20_periph_clk_is_enabled,
+        .enable = tegra20_periph_clk_enable,
+        .disable = tegra20_periph_clk_disable,
+        .set_parent = tegra20_periph_clk_set_parent,
+        .get_parent = tegra20_periph_clk_get_parent,
+        .set_rate = tegra20_periph_clk_set_rate,
+        .round_rate = tegra20_periph_clk_round_rate,
+        .recalc_rate = tegra20_periph_clk_recalc_rate,
+};
+
+/* External memory controller clock ops */
+static void tegra20_emc_clk_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        c->max_rate = __clk_get_rate(hw->clk);
+}
+
+static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        long emc_rate;
+        long clk_rate;
+
+        /*
+         * The slowest entry in the EMC clock table that is at least as
+         * fast as rate.
+         */
+        emc_rate = tegra_emc_round_rate(rate);
+        if (emc_rate < 0)
+                return c->max_rate;
+
+        /*
+         * The fastest rate the PLL will generate that is at most the
+         * requested rate.
+         */
+        clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
+
+        /*
+         * If this fails, and emc_rate > clk_rate, it's because the maximum
+         * rate in the EMC tables is larger than the maximum rate of the EMC
+         * clock. The EMC clock's max rate is the rate it was running when the
+         * kernel booted. Such a mismatch is probably due to using the wrong
+         * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
+         */
+        WARN_ONCE(emc_rate != clk_rate,
+                "emc_rate %ld != clk_rate %ld",
+                emc_rate, clk_rate);
+
+        return emc_rate;
+}
+
+static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        int ret;
+
+        /*
+         * The Tegra2 memory controller has an interlock with the clock
+         * block that allows memory shadowed registers to be updated,
+         * and then transfer them to the main registers at the same
+         * time as the clock update without glitches.
+         */
+        ret = tegra_emc_set_rate(rate);
+        if (ret < 0)
+                return ret;
+
+        ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
+        udelay(1);
+
+        return ret;
+}
+
+struct clk_ops tegra_emc_clk_ops = {
+        .init = tegra20_emc_clk_init,
+        .is_enabled = tegra20_periph_clk_is_enabled,
+        .enable = tegra20_periph_clk_enable,
+        .disable = tegra20_periph_clk_disable,
+        .set_parent = tegra20_periph_clk_set_parent,
+        .get_parent = tegra20_periph_clk_get_parent,
+        .set_rate = tegra20_emc_clk_set_rate,
+        .round_rate = tegra20_emc_clk_round_rate,
+        .recalc_rate = tegra20_periph_clk_recalc_rate,
+};
+
+/* Clock doubler ops */
+static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        c->state = ON;
+
+        if (!c->u.periph.clk_num)
+                goto out;
+
+        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+                        PERIPH_CLK_TO_ENB_BIT(c)))
+                c->state = OFF;
+
+out:
+        return c->state;
+};
+
+static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = prate;
+
+        c->mul = 2;
+        c->div = 1;
+
+        rate *= c->mul;
+        rate += c->div - 1; /* round up */
+        do_div(rate, c->div);
+
+        return rate;
+}
+
+static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        unsigned long output_rate = *prate;
+
+        do_div(output_rate, 2);
+        return output_rate;
+}
+
+static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
+{
+        if (rate != 2 * parent_rate)
+                return -EINVAL;
+        return 0;
+}
+
+struct clk_ops tegra_clk_double_ops = {
+        .is_enabled = tegra20_clk_double_is_enabled,
+        .enable = tegra20_periph_clk_enable,
+        .disable = tegra20_periph_clk_disable,
+        .set_rate = tegra20_clk_double_set_rate,
+        .recalc_rate = tegra20_clk_double_recalc_rate,
+        .round_rate = tegra20_clk_double_round_rate,
+};
+
+/* Audio sync clock ops */
+static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+
+        c->state = (val & (1<<4)) ? OFF : ON;
+        return c->state;
+}
+
+static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        clk_writel(0, c->reg);
+        return 0;
+}
+
+static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        clk_writel(1, c->reg);
+}
+
+static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        int source;
+
+        source = val & 0xf;
+        return source;
+}
+
+static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+
+        val = clk_readl(c->reg);
+        val &= ~0xf;
+        val |= index;
+
+        clk_writel(val, c->reg);
+
+        return 0;
+}
+
+struct clk_ops tegra_audio_sync_clk_ops = {
+        .is_enabled = tegra20_audio_sync_clk_is_enabled,
+        .enable = tegra20_audio_sync_clk_enable,
+        .disable = tegra20_audio_sync_clk_disable,
+        .set_parent = tegra20_audio_sync_clk_set_parent,
+        .get_parent = tegra20_audio_sync_clk_get_parent,
+};
+
+/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
+
+static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
+         * currently done in the pinmux code. */
+        c->state = ON;
+
+        BUG_ON(!c->u.periph.clk_num);
+
+        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+                        PERIPH_CLK_TO_ENB_BIT(c)))
+                c->state = OFF;
+        return c->state;
+}
+
+static int tegra20_cdev_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        BUG_ON(!c->u.periph.clk_num);
+
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+        return 0;
+}
+
+static void tegra20_cdev_clk_disable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        BUG_ON(!c->u.periph.clk_num);
+
+        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+
+static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
+                        unsigned long prate)
+{
+        return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra_cdev_clk_ops = {
+        .is_enabled = tegra20_cdev_clk_is_enabled,
+        .enable = tegra20_cdev_clk_enable,
+        .disable = tegra20_cdev_clk_disable,
+        .recalc_rate = tegra20_cdev_recalc_rate,
+};
+
+/* Tegra20 CPU clock and reset control functions */
+static void tegra20_wait_cpu_in_reset(u32 cpu)
+{
+        unsigned int reg;
+
+        do {
+                reg = readl(reg_clk_base +
+                            TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+                cpu_relax();
+        } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
+
+        return;
+}
+
+static void tegra20_put_cpu_in_reset(u32 cpu)
+{
+        writel(CPU_RESET(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+        dmb();
+}
+
+static void tegra20_cpu_out_of_reset(u32 cpu)
+{
+        writel(CPU_RESET(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+        wmb();
+}
+
+static void tegra20_enable_cpu_clock(u32 cpu)
+{
+        unsigned int reg;
+
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        writel(reg & ~CPU_CLOCK(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        barrier();
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static void tegra20_disable_cpu_clock(u32 cpu)
+{
+        unsigned int reg;
+
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        writel(reg | CPU_CLOCK(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
+        .wait_for_reset = tegra20_wait_cpu_in_reset,
+        .put_in_reset   = tegra20_put_cpu_in_reset,
+        .out_of_reset   = tegra20_cpu_out_of_reset,
+        .enable_clock   = tegra20_enable_cpu_clock,
+        .disable_clock  = tegra20_disable_cpu_clock,
+};
+
+void __init tegra20_cpu_car_ops_init(void)
+{
+        tegra_cpu_car_ops = &tegra20_cpu_car_ops;
+}
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
new file mode 100644
index 000000000000..8bfd31bcc490
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA20_CLOCK_H
+#define __MACH_TEGRA20_CLOCK_H
+
+extern struct clk_ops tegra_clk_32k_ops;
+extern struct clk_ops tegra_pll_ops;
+extern struct clk_ops tegra_clk_m_ops;
+extern struct clk_ops tegra_pll_div_ops;
+extern struct clk_ops tegra_pllx_ops;
+extern struct clk_ops tegra_plle_ops;
+extern struct clk_ops tegra_clk_double_ops;
+extern struct clk_ops tegra_cdev_clk_ops;
+extern struct clk_ops tegra_audio_sync_clk_ops;
+extern struct clk_ops tegra_super_ops;
+extern struct clk_ops tegra_cpu_ops;
+extern struct clk_ops tegra_twd_ops;
+extern struct clk_ops tegra_cop_ops;
+extern struct clk_ops tegra_bus_ops;
+extern struct clk_ops tegra_blink_clk_ops;
+extern struct clk_ops tegra_emc_clk_ops;
+extern struct clk_ops tegra_periph_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+
+void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
+void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
new file mode 100644
index 000000000000..e81dcd239c95
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -0,0 +1,1144 @@
+/*
+ * arch/arm/mach-tegra/tegra2_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk-private.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/iomap.h>
+#include <mach/suspend.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra2_emc.h"
+#include "tegra20_clocks.h"
+#include "tegra_cpu_car.h"
+
+/* Clock definitions */
+
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,            \
+                   _parent_names, _parents, _parent)            \
+        static struct clk tegra_##_name = {                     \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .name = #_name,                                 \
+                .rate = _rate,                                  \
+                .ops = _ops,                                    \
+                .flags = _flags,                                \
+                .parent_names = _parent_names,                  \
+                .parents = _parents,                            \
+                .num_parents = ARRAY_SIZE(_parent_names),       \
+                .parent = _parent,                              \
+        };
+
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+        .hw = {
+                .clk = &tegra_clk_32k,
+        },
+        .fixed_rate = 32768,
+};
+
+static struct clk tegra_clk_32k = {
+        .name = "clk_32k",
+        .rate = 32768,
+        .ops = &tegra_clk_32k_ops,
+        .hw = &tegra_clk_32k_hw.hw,
+        .flags = CLK_IS_ROOT,
+};
+
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+        .hw = {
+                .clk = &tegra_clk_m,
+        },
+        .flags = ENABLE_ON_INIT,
+        .reg = 0x1fc,
+        .reg_shift = 28,
+        .max_rate = 26000000,
+        .fixed_rate = 0,
+};
+
+static struct clk tegra_clk_m = {
+        .name = "clk_m",
+        .ops = &tegra_clk_m_ops,
+        .hw = &tegra_clk_m_hw.hw,
+        .flags = CLK_IS_ROOT,
+};
+
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,  \
+                   _input_max, _cf_min, _cf_max, _vco_min,      \
+                   _vco_max, _freq_table, _lock_delay, _ops,    \
+                   _fixed_rate, _parent)                        \
+        static const char *tegra_##_name##_parent_names[] = {   \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *tegra_##_name##_parents[] = {        \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .u.pll = {                                      \
+                        .input_min = _input_min,                \
+                        .input_max = _input_max,                \
+                        .cf_min = _cf_min,                      \
+                        .cf_max = _cf_max,                      \
+                        .vco_min = _vco_min,                    \
+                        .vco_max = _vco_max,                    \
+                        .freq_table = _freq_table,              \
+                        .lock_delay = _lock_delay,              \
+                        .fixed_rate = _fixed_rate,              \
+                },                                              \
+        };                                                      \
+        static struct clk tegra_##_name = {                     \
+                .name = #_name,                                 \
+                .ops = &_ops,                                   \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .parent = &tegra_##_parent,                     \
+                .parent_names = tegra_##_name##_parent_names,   \
+                .parents = tegra_##_name##_parents,             \
+                .num_parents = 1,                               \
+        };
+
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,         \
+                _max_rate, _ops, _parent, _clk_flags)           \
+        static const char *tegra_##_name##_parent_names[] = {   \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *tegra_##_name##_parents[] = {        \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .reg_shift = _reg_shift,                        \
+        };                                                      \
+        static struct clk tegra_##_name = {                     \
+                .name = #_name,                                 \
+                .ops = &tegra_pll_div_ops,                      \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .parent = &tegra_##_parent,                     \
+                .parent_names = tegra_##_name##_parent_names,   \
+                .parents = tegra_##_name##_parents,             \
+                .num_parents = 1,                               \
+                .flags = _clk_flags,                            \
+        };
+
+
+static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
+        {32768, 12000000, 366, 1, 1, 0},
+        {32768, 13000000, 397, 1, 1, 0},
+        {32768, 19200000, 586, 1, 1, 0},
+        {32768, 26000000, 793, 1, 1, 0},
+        {0, 0, 0, 0, 0, 0},
+};
+
+DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
+                0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
+                tegra_pll_ops, 0, clk_32k);
+
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+        { 12000000, 600000000, 600, 12, 1, 8 },
+        { 13000000, 600000000, 600, 13, 1, 8 },
+        { 19200000, 600000000, 500, 16, 1, 6 },
+        { 26000000, 600000000, 600, 26, 1, 8 },
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+                tegra_pll_ops, 0, clk_m);
+
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
+                tegra_pll_div_ops, pll_c, 0);
+
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+        { 12000000, 666000000, 666, 12, 1, 8},
+        { 13000000, 666000000, 666, 13, 1, 8},
+        { 19200000, 666000000, 555, 16, 1, 8},
+        { 26000000, 666000000, 666, 26, 1, 8},
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
+                tegra_pll_ops, 0, clk_m);
+
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+                tegra_pll_div_ops, pll_m, 0);
+
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+        { 12000000, 216000000, 432, 12, 2, 8},
+        { 13000000, 216000000, 432, 13, 2, 8},
+        { 19200000, 216000000, 90,   4, 2, 1},
+        { 26000000, 216000000, 432, 26, 2, 8},
+        { 12000000, 432000000, 432, 12, 1, 8},
+        { 13000000, 432000000, 432, 13, 1, 8},
+        { 19200000, 432000000, 90,   4, 1, 1},
+        { 26000000, 432000000, 432, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+                2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+                tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
+
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
+                432000000, tegra_pll_div_ops, pll_p, 0);
+
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+        { 28800000, 56448000, 49, 25, 1, 1},
+        { 28800000, 73728000, 64, 25, 1, 1},
+        { 28800000, 24000000,  5,  6, 1, 1},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
+                tegra_pll_ops, 0, pll_p_out1);
+
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
+                tegra_pll_div_ops, pll_a, 0);
+
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+        { 12000000, 216000000, 216, 12, 1, 4},
+        { 13000000, 216000000, 216, 13, 1, 4},
+        { 19200000, 216000000, 135, 12, 1, 3},
+        { 26000000, 216000000, 216, 26, 1, 4},
+
+        { 12000000, 594000000, 594, 12, 1, 8},
+        { 13000000, 594000000, 594, 13, 1, 8},
+        { 19200000, 594000000, 495, 16, 1, 8},
+        { 26000000, 594000000, 594, 26, 1, 8},
+
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+                1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+                1000, tegra_pll_ops, 0, clk_m);
+
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
+                tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
+
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+        { 12000000, 480000000, 960, 12, 2, 0},
+        { 13000000, 480000000, 960, 13, 2, 0},
+        { 19200000, 480000000, 200, 4,  2, 0},
+        { 26000000, 480000000, 960, 26, 2, 0},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
+                48000000, 960000000, tegra_pll_u_freq_table, 1000,
+                tegra_pll_ops, 0, clk_m);
+
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+        /* 1 GHz */
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+
+        /* 912 MHz */
+        { 12000000, 912000000,  912,  12, 1, 12},
+        { 13000000, 912000000,  912,  13, 1, 12},
+        { 19200000, 912000000,  760,  16, 1, 8},
+        { 26000000, 912000000,  912,  26, 1, 12},
+
+        /* 816 MHz */
+        { 12000000, 816000000,  816,  12, 1, 12},
+        { 13000000, 816000000,  816,  13, 1, 12},
+        { 19200000, 816000000,  680,  16, 1, 8},
+        { 26000000, 816000000,  816,  26, 1, 12},
+
+        /* 760 MHz */
+        { 12000000, 760000000,  760,  12, 1, 12},
+        { 13000000, 760000000,  760,  13, 1, 12},
+        { 19200000, 760000000,  950,  24, 1, 8},
+        { 26000000, 760000000,  760,  26, 1, 12},
+
+        /* 750 MHz */
+        { 12000000, 750000000,  750,  12, 1, 12},
+        { 13000000, 750000000,  750,  13, 1, 12},
+        { 19200000, 750000000,  625,  16, 1, 8},
+        { 26000000, 750000000,  750,  26, 1, 12},
+
+        /* 608 MHz */
+        { 12000000, 608000000,  608,  12, 1, 12},
+        { 13000000, 608000000,  608,  13, 1, 12},
+        { 19200000, 608000000,  380,  12, 1, 8},
+        { 26000000, 608000000,  608,  26, 1, 12},
+
+        /* 456 MHz */
+        { 12000000, 456000000,  456,  12, 1, 12},
+        { 13000000, 456000000,  456,  13, 1, 12},
+        { 19200000, 456000000,  380,  16, 1, 8},
+        { 26000000, 456000000,  456,  26, 1, 12},
+
+        /* 312 MHz */
+        { 12000000, 312000000,  312,  12, 1, 12},
+        { 13000000, 312000000,  312,  13, 1, 12},
+        { 19200000, 312000000,  260,  16, 1, 8},
+        { 26000000, 312000000,  312,  26, 1, 12},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
+                31000000, 1000000, 6000000, 20000000, 1200000000,
+                tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
+
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+        { 12000000, 100000000,  200,  24, 1, 0 },
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
+                0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
+
+static const char *tegra_common_parent_names[] = {
+        "clk_m",
+};
+
+static struct clk *tegra_common_parents[] = {
+        &tegra_clk_m,
+};
+
+static struct clk tegra_clk_d;
+static struct clk_tegra tegra_clk_d_hw = {
+        .hw = {
+                .clk = &tegra_clk_d,
+        },
+        .flags = PERIPH_NO_RESET,
+        .reg = 0x34,
+        .reg_shift = 12,
+        .max_rate = 52000000,
+        .u.periph = {
+                .clk_num = 90,
+        },
+};
+
+static struct clk tegra_clk_d = {
+        .name = "clk_d",
+        .hw = &tegra_clk_d_hw.hw,
+        .ops = &tegra_clk_double_ops,
+        .parent = &tegra_clk_m,
+        .parent_names = tegra_common_parent_names,
+        .parents = tegra_common_parents,
+        .num_parents = ARRAY_SIZE(tegra_common_parent_names),
+};
+
+static struct clk tegra_cdev1;
+static struct clk_tegra tegra_cdev1_hw = {
+        .hw = {
+                .clk = &tegra_cdev1,
+        },
+        .fixed_rate = 26000000,
+        .u.periph = {
+                .clk_num = 94,
+        },
+};
+static struct clk tegra_cdev1 = {
+        .name = "cdev1",
+        .hw = &tegra_cdev1_hw.hw,
+        .ops = &tegra_cdev_clk_ops,
+        .flags = CLK_IS_ROOT,
+};
+
+/* dap_mclk2, belongs to the cdev2 pingroup. */
+static struct clk tegra_cdev2;
+static struct clk_tegra tegra_cdev2_hw = {
+        .hw = {
+                .clk = &tegra_cdev2,
+        },
+        .fixed_rate = 26000000,
+        .u.periph = {
+                .clk_num  = 93,
+        },
+};
+static struct clk tegra_cdev2 = {
+        .name = "cdev2",
+        .hw = &tegra_cdev2_hw.hw,
+        .ops = &tegra_cdev_clk_ops,
+        .flags = CLK_IS_ROOT,
+};
+
+/* initialized before peripheral clocks */
+static struct clk_mux_sel mux_audio_sync_clk[8+1];
+static const struct audio_sources {
+        const char *name;
+        int value;
+} mux_audio_sync_clk_sources[] = {
+        { .name = "spdif_in", .value = 0 },
+        { .name = "i2s1", .value = 1 },
+        { .name = "i2s2", .value = 2 },
+        { .name = "pll_a_out0", .value = 4 },
+#if 0 /* FIXME: not implemented */
+        { .name = "ac97", .value = 3 },
+        { .name = "ext_audio_clk2", .value = 5 },
+        { .name = "ext_audio_clk1", .value = 6 },
+        { .name = "ext_vimclk", .value = 7 },
+#endif
+        { NULL, 0 }
+};
+
+static const char *audio_parent_names[] = {
+        "spdif_in",
+        "i2s1",
+        "i2s2",
+        "dummy",
+        "pll_a_out0",
+        "dummy",
+        "dummy",
+        "dummy",
+};
+
+static struct clk *audio_parents[] = {
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+        NULL,
+};
+
+static struct clk tegra_audio;
+static struct clk_tegra tegra_audio_hw = {
+        .hw = {
+                .clk = &tegra_audio,
+        },
+        .reg = 0x38,
+        .max_rate = 73728000,
+};
+DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
+                audio_parents, NULL);
+
+static const char *audio_2x_parent_names[] = {
+        "audio",
+};
+
+static struct clk *audio_2x_parents[] = {
+        &tegra_audio,
+};
+
+static struct clk tegra_audio_2x;
+static struct clk_tegra tegra_audio_2x_hw = {
+        .hw = {
+                .clk = &tegra_audio_2x,
+        },
+        .flags = PERIPH_NO_RESET,
+        .max_rate = 48000000,
+        .reg = 0x34,
+        .reg_shift = 8,
+        .u.periph = {
+                .clk_num = 89,
+        },
+};
+DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
+                audio_2x_parents, &tegra_audio);
+
+static struct clk_lookup tegra_audio_clk_lookups[] = {
+        { .con_id = "audio", .clk = &tegra_audio },
+        { .con_id = "audio_2x", .clk = &tegra_audio_2x }
+};
+
+/* This is called after peripheral clocks are initialized, as the
+ * audio_sync clock depends on some of the peripheral clocks.
+ */
+
+static void init_audio_sync_clock_mux(void)
+{
+        int i;
+        struct clk_mux_sel *sel = mux_audio_sync_clk;
+        const struct audio_sources *src = mux_audio_sync_clk_sources;
+        struct clk_lookup *lookup;
+
+        for (i = 0; src->name; i++, sel++, src++) {
+                sel->input = tegra_get_clock_by_name(src->name);
+                if (!sel->input)
+                        pr_err("%s: could not find clk %s\n", __func__,
+                                src->name);
+                audio_parents[src->value] = sel->input;
+                sel->value = src->value;
+        }
+
+        lookup = tegra_audio_clk_lookups;
+        for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
+                struct clk *c = lookup->clk;
+                struct clk_tegra *clk = to_clk_tegra(c->hw);
+                __clk_init(NULL, c);
+                INIT_LIST_HEAD(&clk->shared_bus_list);
+                clk->lookup.con_id = lookup->con_id;
+                clk->lookup.clk = c;
+                clkdev_add(&clk->lookup);
+                tegra_clk_add(c);
+        }
+}
+
+static const char *mux_cclk[] = {
+        "clk_m",
+        "pll_c",
+        "clk_32k",
+        "pll_m",
+        "pll_p",
+        "pll_p_out4",
+        "pll_p_out3",
+        "clk_d",
+        "pll_x",
+};
+
+
+static struct clk *mux_cclk_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c,
+        &tegra_clk_32k,
+        &tegra_pll_m,
+        &tegra_pll_p,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        &tegra_clk_d,
+        &tegra_pll_x,
+};
+
+static const char *mux_sclk[] = {
+        "clk_m",
+        "pll_c_out1",
+        "pll_p_out4",
+        "pllp_p_out3",
+        "pll_p_out2",
+        "clk_d",
+        "clk_32k",
+        "pll_m_out1",
+};
+
+static struct clk *mux_sclk_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c_out1,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out2,
+        &tegra_clk_d,
+        &tegra_clk_32k,
+        &tegra_pll_m_out1,
+};
+
+static struct clk tegra_cclk;
+static struct clk_tegra tegra_cclk_hw = {
+        .hw = {
+                .clk = &tegra_cclk,
+        },
+        .reg = 0x20,
+        .max_rate = 1000000000,
+};
+DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
+                mux_cclk_p, NULL);
+
+static const char *mux_twd[] = {
+        "cclk",
+};
+
+static struct clk *mux_twd_p[] = {
+        &tegra_cclk,
+};
+
+static struct clk tegra_clk_twd;
+static struct clk_tegra tegra_clk_twd_hw = {
+        .hw = {
+                .clk = &tegra_clk_twd,
+        },
+        .max_rate = 1000000000,
+        .mul = 1,
+        .div = 4,
+};
+
+static struct clk tegra_clk_twd = {
+        .name = "twd",
+        .ops = &tegra_twd_ops,
+        .hw = &tegra_clk_twd_hw.hw,
+        .parent = &tegra_cclk,
+        .parent_names = mux_twd,
+        .parents = mux_twd_p,
+        .num_parents = ARRAY_SIZE(mux_twd),
+};
+
+static struct clk tegra_sclk;
+static struct clk_tegra tegra_sclk_hw = {
+        .hw = {
+                .clk = &tegra_sclk,
+        },
+        .reg = 0x28,
+        .max_rate = 240000000,
+        .min_rate = 120000000,
+};
+DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
+                mux_sclk_p, NULL);
+
+static const char *tegra_cop_parent_names[] = {
+        "tegra_sclk",
+};
+
+static struct clk *tegra_cop_parents[] = {
+        &tegra_sclk,
+};
+
+static struct clk tegra_cop;
+static struct clk_tegra tegra_cop_hw = {
+        .hw = {
+                .clk = &tegra_cop,
+        },
+        .max_rate  = 240000000,
+        .reset = &tegra2_cop_clk_reset,
+};
+DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
+                tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
+
+static const char *tegra_hclk_parent_names[] = {
+        "tegra_sclk",
+};
+
+static struct clk *tegra_hclk_parents[] = {
+        &tegra_sclk,
+};
+
+static struct clk tegra_hclk;
+static struct clk_tegra tegra_hclk_hw = {
+        .hw = {
+                .clk = &tegra_hclk,
+        },
+        .flags = DIV_BUS,
+        .reg = 0x30,
+        .reg_shift = 4,
+        .max_rate = 240000000,
+};
+DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
+                tegra_hclk_parents, &tegra_sclk);
+
+static const char *tegra_pclk_parent_names[] = {
+        "tegra_hclk",
+};
+
+static struct clk *tegra_pclk_parents[] = {
+        &tegra_hclk,
+};
+
+static struct clk tegra_pclk;
+static struct clk_tegra tegra_pclk_hw = {
+        .hw = {
+                .clk = &tegra_pclk,
+        },
+        .flags = DIV_BUS,
+        .reg = 0x30,
+        .reg_shift = 0,
+        .max_rate = 120000000,
+};
+DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
+                tegra_pclk_parents, &tegra_hclk);
+
+static const char *tegra_blink_parent_names[] = {
+        "clk_32k",
+};
+
+static struct clk *tegra_blink_parents[] = {
+        &tegra_clk_32k,
+};
+
+static struct clk tegra_blink;
+static struct clk_tegra tegra_blink_hw = {
+        .hw = {
+                .clk = &tegra_blink,
+        },
+        .reg = 0x40,
+        .max_rate = 32768,
+};
+DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
+                tegra_blink_parents, &tegra_clk_32k);
+
+static const char *mux_pllm_pllc_pllp_plla[] = {
+        "pll_m",
+        "pll_c",
+        "pll_p",
+        "pll_a_out0",
+};
+
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+        &tegra_pll_m,
+        &tegra_pll_c,
+        &tegra_pll_p,
+        &tegra_pll_a_out0,
+};
+
+static const char *mux_pllm_pllc_pllp_clkm[] = {
+        "pll_m",
+        "pll_c",
+        "pll_p",
+        "clk_m",
+};
+
+static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
+        &tegra_pll_m,
+        &tegra_pll_c,
+        &tegra_pll_p,
+        &tegra_clk_m,
+};
+
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m",
+        "clk_m",
+};
+
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+        &tegra_clk_m,
+};
+
+static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
+        "pll_a_out0",
+        "audio_2x",
+        "pll_p",
+        "clk_m",
+};
+
+static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
+        &tegra_pll_a_out0,
+        &tegra_audio_2x,
+        &tegra_pll_p,
+        &tegra_clk_m,
+};
+
+static const char *mux_pllp_plld_pllc_clkm[] = {
+        "pllp",
+        "pll_d_out0",
+        "pll_c",
+        "clk_m",
+};
+
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_d_out0,
+        &tegra_pll_c,
+        &tegra_clk_m,
+};
+
+static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
+        "pll_p",
+        "pll_c",
+        "audio",
+        "clk_m",
+        "clk_32k",
+};
+
+static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_audio,
+        &tegra_clk_m,
+        &tegra_clk_32k,
+};
+
+static const char *mux_pllp_pllc_pllm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m"
+};
+
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+};
+
+static const char *mux_clk_m[] = {
+        "clk_m",
+};
+
+static struct clk *mux_clk_m_p[] = {
+        &tegra_clk_m,
+};
+
+static const char *mux_pllp_out3[] = {
+        "pll_p_out3",
+};
+
+static struct clk *mux_pllp_out3_p[] = {
+        &tegra_pll_p_out3,
+};
+
+static const char *mux_plld[] = {
+        "pll_d",
+};
+
+static struct clk *mux_plld_p[] = {
+        &tegra_pll_d,
+};
+
+static const char *mux_clk_32k[] = {
+        "clk_32k",
+};
+
+static struct clk *mux_clk_32k_p[] = {
+        &tegra_clk_32k,
+};
+
+static const char *mux_pclk[] = {
+        "pclk",
+};
+
+static struct clk *mux_pclk_p[] = {
+        &tegra_pclk,
+};
+
+static struct clk tegra_emc;
+static struct clk_tegra tegra_emc_hw = {
+        .hw = {
+                .clk = &tegra_emc,
+        },
+        .reg = 0x19c,
+        .max_rate = 800000000,
+        .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
+        .reset = &tegra2_periph_clk_reset,
+        .u.periph = {
+                .clk_num = 57,
+        },
+};
+DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
+                mux_pllm_pllc_pllp_clkm_p, NULL);
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,   \
+                _max, _inputs, _flags)                  \
+        static struct clk tegra_##_name;                \
+        static struct clk_tegra tegra_##_name##_hw = {  \
+                .hw = {                                 \
+                        .clk = &tegra_##_name,          \
+                },                                      \
+                .lookup = {                             \
+                        .dev_id = _dev,                 \
+                        .con_id = _con,                 \
+                },                                      \
+                .reg = _reg,                            \
+                .flags = _flags,                        \
+                .max_rate = _max,                       \
+                .u.periph = {                           \
+                        .clk_num = _clk_num,            \
+                },                                      \
+                .reset = tegra2_periph_clk_reset,       \
+        };                                              \
+        static struct clk tegra_##_name = {             \
+                .name = #_name,                         \
+                .ops = &tegra_periph_clk_ops,           \
+                .hw = &tegra_##_name##_hw.hw,           \
+                .parent_names = _inputs,                \
+                .parents = _inputs##_p,                 \
+                .num_parents = ARRAY_SIZE(_inputs),     \
+        };
+
+PERIPH_CLK(apbdma,      "tegra-apbdma",         NULL,   34,     0,      108000000, mux_pclk,                    0);
+PERIPH_CLK(rtc,         "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET);
+PERIPH_CLK(timer,       "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(i2s1,        "tegra20-i2s.0",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
+PERIPH_CLK(i2s2,        "tegra20-i2s.1",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
+PERIPH_CLK(spdif_out,   "spdif_out",            NULL,   10,     0x108,  100000000, mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71);
+PERIPH_CLK(spdif_in,    "spdif_in",             NULL,   10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71);
+PERIPH_CLK(pwm,         "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_audio_clkm_clk32,      MUX | DIV_U71 | MUX_PWM);
+PERIPH_CLK(spi,         "spi",                  NULL,   43,     0x114,  40000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(xio,         "xio",                  NULL,   45,     0x120,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(twc,         "twc",                  NULL,   16,     0x12c,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc1,        "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc2,        "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc3,        "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sbc4,        "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(ide,         "ide",                  NULL,   25,     0x144,  100000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(ndflash,     "tegra_nand",           NULL,   13,     0x160,  164000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vfir,        "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sdmmc1,      "sdhci-tegra.0",        NULL,   14,     0x150,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2,      "sdhci-tegra.1",        NULL,   9,      0x154,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3,      "sdhci-tegra.2",        NULL,   69,     0x1bc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4,      "sdhci-tegra.3",        NULL,   15,     0x164,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp,         "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsea,        "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsev,        "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(vde,         "tegra-avp",            "vde",  61,     0x1c8,  250000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(csite,       "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* max rate ??? */
+/* FIXME: what is la? */
+PERIPH_CLK(la,          "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  92000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(i2c1,        "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(i2c2,        "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(i2c3,        "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(dvc,         "tegra-i2c.3",          NULL,   47,     0x128,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16);
+PERIPH_CLK(i2c1_i2c,    "tegra-i2c.0",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
+PERIPH_CLK(i2c2_i2c,    "tegra-i2c.1",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
+PERIPH_CLK(i2c3_i2c,    "tegra-i2c.2",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
+PERIPH_CLK(dvc_i2c,     "tegra-i2c.3",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0);
+PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uartd,       "tegra-uart.3",         NULL,   65,     0x1c0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(uarte,       "tegra-uart.4",         NULL,   66,     0x1c4,  600000000, mux_pllp_pllc_pllm_clkm,     MUX);
+PERIPH_CLK(3d,          "3d",                   NULL,   24,     0x158,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
+PERIPH_CLK(2d,          "2d",                   NULL,   21,     0x15c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(vi,          "tegra_camera",         "vi",   20,     0x148,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(vi_sensor,   "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
+PERIPH_CLK(epp,         "epp",                  NULL,   19,     0x16c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(mpe,         "mpe",                  NULL,   60,     0x170,  250000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(host1x,      "host1x",               NULL,   28,     0x180,  166000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(cve,         "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo,         "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(hdmi,        "hdmi",                 NULL,   51,     0x18c,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvdac,       "tvdac",                NULL,   53,     0x194,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1,       "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX); /* scales with voltage and process_id */
+PERIPH_CLK(disp2,       "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX); /* scales with voltage and process_id */
+PERIPH_CLK(usbd,        "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb2,        "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb3,        "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(dsi,         "dsi",                  NULL,   48,     0,      500000000, mux_plld,                    0); /* scales with voltage */
+PERIPH_CLK(csi,         "tegra_camera",         "csi",  52,     0,      72000000,  mux_pllp_out3,               0);
+PERIPH_CLK(isp,         "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0); /* same frequency as VI */
+PERIPH_CLK(csus,        "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET);
+PERIPH_CLK(pex,         NULL,                   "pex",  70,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
+PERIPH_CLK(afi,         NULL,                   "afi",  72,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
+PERIPH_CLK(pcie_xclk,   NULL,             "pcie_xclk",  74,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET);
+
+static struct clk *tegra_list_clks[] = {
+        &tegra_apbdma,
+        &tegra_rtc,
+        &tegra_i2s1,
+        &tegra_i2s2,
+        &tegra_spdif_out,
+        &tegra_spdif_in,
+        &tegra_pwm,
+        &tegra_spi,
+        &tegra_xio,
+        &tegra_twc,
+        &tegra_sbc1,
+        &tegra_sbc2,
+        &tegra_sbc3,
+        &tegra_sbc4,
+        &tegra_ide,
+        &tegra_ndflash,
+        &tegra_vfir,
+        &tegra_sdmmc1,
+        &tegra_sdmmc2,
+        &tegra_sdmmc3,
+        &tegra_sdmmc4,
+        &tegra_vcp,
+        &tegra_bsea,
+        &tegra_bsev,
+        &tegra_vde,
+        &tegra_csite,
+        &tegra_la,
+        &tegra_owr,
+        &tegra_nor,
+        &tegra_mipi,
+        &tegra_i2c1,
+        &tegra_i2c2,
+        &tegra_i2c3,
+        &tegra_dvc,
+        &tegra_i2c1_i2c,
+        &tegra_i2c2_i2c,
+        &tegra_i2c3_i2c,
+        &tegra_dvc_i2c,
+        &tegra_uarta,
+        &tegra_uartb,
+        &tegra_uartc,
+        &tegra_uartd,
+        &tegra_uarte,
+        &tegra_3d,
+        &tegra_2d,
+        &tegra_vi,
+        &tegra_vi_sensor,
+        &tegra_epp,
+        &tegra_mpe,
+        &tegra_host1x,
+        &tegra_cve,
+        &tegra_tvo,
+        &tegra_hdmi,
+        &tegra_tvdac,
+        &tegra_disp1,
+        &tegra_disp2,
+        &tegra_usbd,
+        &tegra_usb2,
+        &tegra_usb3,
+        &tegra_dsi,
+        &tegra_csi,
+        &tegra_isp,
+        &tegra_csus,
+        &tegra_pex,
+        &tegra_afi,
+        &tegra_pcie_xclk,
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con)        \
+        {                                       \
+                .name   = _name,                \
+                .lookup = {                     \
+                        .dev_id = _dev,         \
+                        .con_id = _con,         \
+                },                              \
+        }
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+static struct clk_duplicate tegra_clk_duplicates[] = {
+        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
+        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
+        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
+        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
+        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
+        CLK_DUPLICATE("usbd",   "utmip-pad",    NULL),
+        CLK_DUPLICATE("usbd",   "tegra-ehci.0", NULL),
+        CLK_DUPLICATE("usbd",   "tegra-otg",    NULL),
+        CLK_DUPLICATE("hdmi",   "tegradc.0",    "hdmi"),
+        CLK_DUPLICATE("hdmi",   "tegradc.1",    "hdmi"),
+        CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
+        CLK_DUPLICATE("2d",     "tegra_grhost", "gr2d"),
+        CLK_DUPLICATE("3d",     "tegra_grhost", "gr3d"),
+        CLK_DUPLICATE("epp",    "tegra_grhost", "epp"),
+        CLK_DUPLICATE("mpe",    "tegra_grhost", "mpe"),
+        CLK_DUPLICATE("cop",    "tegra-avp",    "cop"),
+        CLK_DUPLICATE("vde",    "tegra-aes",    "vde"),
+        CLK_DUPLICATE("cclk",   NULL,           "cpu"),
+        CLK_DUPLICATE("twd",    "smp_twd",      NULL),
+};
+
+#define CLK(dev, con, ck)       \
+        {                       \
+                .dev_id = dev,  \
+                .con_id = con,  \
+                .clk    = ck,   \
+        }
+
+static struct clk *tegra_ptr_clks[] = {
+        &tegra_clk_32k,
+        &tegra_pll_s,
+        &tegra_clk_m,
+        &tegra_pll_m,
+        &tegra_pll_m_out1,
+        &tegra_pll_c,
+        &tegra_pll_c_out1,
+        &tegra_pll_p,
+        &tegra_pll_p_out1,
+        &tegra_pll_p_out2,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out4,
+        &tegra_pll_a,
+        &tegra_pll_a_out0,
+        &tegra_pll_d,
+        &tegra_pll_d_out0,
+        &tegra_pll_u,
+        &tegra_pll_x,
+        &tegra_pll_e,
+        &tegra_cclk,
+        &tegra_clk_twd,
+        &tegra_sclk,
+        &tegra_hclk,
+        &tegra_pclk,
+        &tegra_clk_d,
+        &tegra_cdev1,
+        &tegra_cdev2,
+        &tegra_blink,
+        &tegra_cop,
+        &tegra_emc,
+};
+
+static void tegra2_init_one_clock(struct clk *c)
+{
+        struct clk_tegra *clk = to_clk_tegra(c->hw);
+        int ret;
+
+        ret = __clk_init(NULL, c);
+        if (ret)
+                pr_err("clk init failed %s\n", __clk_get_name(c));
+
+        INIT_LIST_HEAD(&clk->shared_bus_list);
+        if (!clk->lookup.dev_id && !clk->lookup.con_id)
+                clk->lookup.con_id = c->name;
+        clk->lookup.clk = c;
+        clkdev_add(&clk->lookup);
+        tegra_clk_add(c);
+}
+
+void __init tegra2_init_clocks(void)
+{
+        int i;
+        struct clk *c;
+
+        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+                tegra2_init_one_clock(tegra_ptr_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+                tegra2_init_one_clock(tegra_list_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+                if (!c) {
+                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                                tegra_clk_duplicates[i].name);
+                        continue;
+                }
+
+                tegra_clk_duplicates[i].lookup.clk = c;
+                clkdev_add(&tegra_clk_duplicates[i].lookup);
+        }
+
+        init_audio_sync_clock_mux();
+        tegra20_cpu_car_ops_init();
+}
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
deleted file mode 100644
index a703844b2061..000000000000
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ /dev/null
@@ -1,2484 +0,0 @@
-/*
- * arch/arm/mach-tegra/tegra2_clocks.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-
-#include "clock.h"
-#include "fuse.h"
-#include "tegra2_emc.h"
-
-#define RST_DEVICES                     0x004
-#define RST_DEVICES_SET                 0x300
-#define RST_DEVICES_CLR                 0x304
-#define RST_DEVICES_NUM                 3
-
-#define CLK_OUT_ENB                     0x010
-#define CLK_OUT_ENB_SET                 0x320
-#define CLK_OUT_ENB_CLR                 0x324
-#define CLK_OUT_ENB_NUM                 3
-
-#define CLK_MASK_ARM                    0x44
-#define MISC_CLK_ENB                    0x48
-
-#define OSC_CTRL                        0x50
-#define OSC_CTRL_OSC_FREQ_MASK          (3<<30)
-#define OSC_CTRL_OSC_FREQ_13MHZ         (0<<30)
-#define OSC_CTRL_OSC_FREQ_19_2MHZ       (1<<30)
-#define OSC_CTRL_OSC_FREQ_12MHZ         (2<<30)
-#define OSC_CTRL_OSC_FREQ_26MHZ         (3<<30)
-#define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
-
-#define OSC_FREQ_DET                    0x58
-#define OSC_FREQ_DET_TRIG               (1<<31)
-
-#define OSC_FREQ_DET_STATUS             0x5C
-#define OSC_FREQ_DET_BUSY               (1<<31)
-#define OSC_FREQ_DET_CNT_MASK           0xFFFF
-
-#define PERIPH_CLK_SOURCE_I2S1          0x100
-#define PERIPH_CLK_SOURCE_EMC           0x19c
-#define PERIPH_CLK_SOURCE_OSC           0x1fc
-#define PERIPH_CLK_SOURCE_NUM \
-        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
-
-#define PERIPH_CLK_SOURCE_MASK          (3<<30)
-#define PERIPH_CLK_SOURCE_SHIFT         30
-#define PERIPH_CLK_SOURCE_PWM_MASK      (7<<28)
-#define PERIPH_CLK_SOURCE_PWM_SHIFT     28
-#define PERIPH_CLK_SOURCE_ENABLE        (1<<28)
-#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
-#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
-#define PERIPH_CLK_SOURCE_DIV_SHIFT     0
-
-#define SDMMC_CLK_INT_FB_SEL            (1 << 23)
-#define SDMMC_CLK_INT_FB_DLY_SHIFT      16
-#define SDMMC_CLK_INT_FB_DLY_MASK       (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
-
-#define PLL_BASE                        0x0
-#define PLL_BASE_BYPASS                 (1<<31)
-#define PLL_BASE_ENABLE                 (1<<30)
-#define PLL_BASE_REF_ENABLE             (1<<29)
-#define PLL_BASE_OVERRIDE               (1<<28)
-#define PLL_BASE_DIVP_MASK              (0x7<<20)
-#define PLL_BASE_DIVP_SHIFT             20
-#define PLL_BASE_DIVN_MASK              (0x3FF<<8)
-#define PLL_BASE_DIVN_SHIFT             8
-#define PLL_BASE_DIVM_MASK              (0x1F)
-#define PLL_BASE_DIVM_SHIFT             0
-
-#define PLL_OUT_RATIO_MASK              (0xFF<<8)
-#define PLL_OUT_RATIO_SHIFT             8
-#define PLL_OUT_OVERRIDE                (1<<2)
-#define PLL_OUT_CLKEN                   (1<<1)
-#define PLL_OUT_RESET_DISABLE           (1<<0)
-
-#define PLL_MISC(c)                     (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
-
-#define PLL_MISC_DCCON_SHIFT            20
-#define PLL_MISC_CPCON_SHIFT            8
-#define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
-#define PLL_MISC_LFCON_SHIFT            4
-#define PLL_MISC_LFCON_MASK             (0xF<<PLL_MISC_LFCON_SHIFT)
-#define PLL_MISC_VCOCON_SHIFT           0
-#define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
-
-#define PLLU_BASE_POST_DIV              (1<<20)
-
-#define PLLD_MISC_CLKENABLE             (1<<30)
-#define PLLD_MISC_DIV_RST               (1<<23)
-#define PLLD_MISC_DCCON_SHIFT           12
-
-#define PLLE_MISC_READY                 (1 << 15)
-
-#define PERIPH_CLK_TO_ENB_REG(c)        ((c->u.periph.clk_num / 32) * 4)
-#define PERIPH_CLK_TO_ENB_SET_REG(c)    ((c->u.periph.clk_num / 32) * 8)
-#define PERIPH_CLK_TO_ENB_BIT(c)        (1 << (c->u.periph.clk_num % 32))
-
-#define SUPER_CLK_MUX                   0x00
-#define SUPER_STATE_SHIFT               28
-#define SUPER_STATE_MASK                (0xF << SUPER_STATE_SHIFT)
-#define SUPER_STATE_STANDBY             (0x0 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IDLE                (0x1 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_RUN                 (0x2 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IRQ                 (0x3 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_FIQ                 (0x4 << SUPER_STATE_SHIFT)
-#define SUPER_SOURCE_MASK               0xF
-#define SUPER_FIQ_SOURCE_SHIFT          12
-#define SUPER_IRQ_SOURCE_SHIFT          8
-#define SUPER_RUN_SOURCE_SHIFT          4
-#define SUPER_IDLE_SOURCE_SHIFT         0
-
-#define SUPER_CLK_DIVIDER               0x04
-
-#define BUS_CLK_DISABLE                 (1<<3)
-#define BUS_CLK_DIV_MASK                0x3
-
-#define PMC_CTRL                        0x0
- #define PMC_CTRL_BLINK_ENB             (1 << 7)
-
-#define PMC_DPD_PADS_ORIDE              0x1c
- #define PMC_DPD_PADS_ORIDE_BLINK_ENB   (1 << 20)
-
-#define PMC_BLINK_TIMER_DATA_ON_SHIFT   0
-#define PMC_BLINK_TIMER_DATA_ON_MASK    0x7fff
-#define PMC_BLINK_TIMER_ENB             (1 << 15)
-#define PMC_BLINK_TIMER_DATA_OFF_SHIFT  16
-#define PMC_BLINK_TIMER_DATA_OFF_MASK   0xffff
-
-static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
-static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-
-/*
- * Some clocks share a register with other clocks.  Any clock op that
- * non-atomically modifies a register used by another clock must lock
- * clock_register_lock first.
- */
-static DEFINE_SPINLOCK(clock_register_lock);
-
-/*
- * Some peripheral clocks share an enable bit, so refcount the enable bits
- * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
- */
-static int tegra_periph_clk_enable_refcount[3 * 32];
-
-#define clk_writel(value, reg) \
-        __raw_writel(value, reg_clk_base + (reg))
-#define clk_readl(reg) \
-        __raw_readl(reg_clk_base + (reg))
-#define pmc_writel(value, reg) \
-        __raw_writel(value, reg_pmc_base + (reg))
-#define pmc_readl(reg) \
-        __raw_readl(reg_pmc_base + (reg))
-
-static unsigned long clk_measure_input_freq(void)
-{
-        u32 clock_autodetect;
-        clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
-        do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
-        clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
-        if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
-                return 12000000;
-        } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
-                return 13000000;
-        } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
-                return 19200000;
-        } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
-                return 26000000;
-        } else {
-                pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
-                BUG();
-                return 0;
-        }
-}
-
-static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
-{
-        s64 divider_u71 = parent_rate * 2;
-        divider_u71 += rate - 1;
-        do_div(divider_u71, rate);
-
-        if (divider_u71 - 2 < 0)
-                return 0;
-
-        if (divider_u71 - 2 > 255)
-                return -EINVAL;
-
-        return divider_u71 - 2;
-}
-
-static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
-{
-        s64 divider_u16;
-
-        divider_u16 = parent_rate;
-        divider_u16 += rate - 1;
-        do_div(divider_u16, rate);
-
-        if (divider_u16 - 1 < 0)
-                return 0;
-
-        if (divider_u16 - 1 > 255)
-                return -EINVAL;
-
-        return divider_u16 - 1;
-}
-
-/* clk_m functions */
-static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
-{
-        u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
-
-        c->rate = clk_measure_input_freq();
-        switch (c->rate) {
-        case 12000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
-                break;
-        case 13000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
-                break;
-        case 19200000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
-                break;
-        case 26000000:
-                auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
-                break;
-        default:
-                pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
-                BUG();
-        }
-        clk_writel(auto_clock_control, OSC_CTRL);
-        return c->rate;
-}
-
-static void tegra2_clk_m_init(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        tegra2_clk_m_autodetect_rate(c);
-}
-
-static int tegra2_clk_m_enable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        return 0;
-}
-
-static void tegra2_clk_m_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        BUG();
-}
-
-static struct clk_ops tegra_clk_m_ops = {
-        .init           = tegra2_clk_m_init,
-        .enable         = tegra2_clk_m_enable,
-        .disable        = tegra2_clk_m_disable,
-};
-
-/* super clock functions */
-/* "super clocks" on tegra have two-stage muxes and a clock skipping
- * super divider.  We will ignore the clock skipping divider, since we
- * can't lower the voltage when using the clock skip, but we can if we
- * lower the PLL frequency.
- */
-static void tegra2_super_clk_init(struct clk *c)
-{
-        u32 val;
-        int source;
-        int shift;
-        const struct clk_mux_sel *sel;
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        c->state = ON;
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        source = (val >> shift) & SUPER_SOURCE_MASK;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->value == source)
-                        break;
-        }
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
-}
-
-static int tegra2_super_clk_enable(struct clk *c)
-{
-        clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
-        return 0;
-}
-
-static void tegra2_super_clk_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        /* oops - don't disable the CPU clock! */
-        BUG();
-}
-
-static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
-{
-        u32 val;
-        const struct clk_mux_sel *sel;
-        int shift;
-
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val &= ~(SUPER_SOURCE_MASK << shift);
-                        val |= sel->value << shift;
-
-                        if (c->refcnt)
-                                clk_enable(p);
-
-                        clk_writel(val, c->reg);
-
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-
-/*
- * Super clocks have "clock skippers" instead of dividers.  Dividing using
- * a clock skipper does not allow the voltage to be scaled down, so instead
- * adjust the rate of the parent clock.  This requires that the parent of a
- * super clock have no other children, otherwise the rate will change
- * underneath the other children.
- */
-static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        return clk_set_rate(c->parent, rate);
-}
-
-static struct clk_ops tegra_super_ops = {
-        .init                   = tegra2_super_clk_init,
-        .enable                 = tegra2_super_clk_enable,
-        .disable                = tegra2_super_clk_disable,
-        .set_parent             = tegra2_super_clk_set_parent,
-        .set_rate               = tegra2_super_clk_set_rate,
-};
-
-/* virtual cpu clock functions */
-/* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
-   To change the frequency of these clocks, the parent pll may need to be
-   reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
-   and then the clock moved back to the pll.  To hide this sequence, a virtual
-   clock handles it.
- */
-static void tegra2_cpu_clk_init(struct clk *c)
-{
-}
-
-static int tegra2_cpu_clk_enable(struct clk *c)
-{
-        return 0;
-}
-
-static void tegra2_cpu_clk_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        /* oops - don't disable the CPU clock! */
-        BUG();
-}
-
-static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        int ret;
-        /*
-         * Take an extra reference to the main pll so it doesn't turn
-         * off when we move the cpu off of it
-         */
-        clk_enable(c->u.cpu.main);
-
-        ret = clk_set_parent(c->parent, c->u.cpu.backup);
-        if (ret) {
-                pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
-                goto out;
-        }
-
-        if (rate == clk_get_rate(c->u.cpu.backup))
-                goto out;
-
-        ret = clk_set_rate(c->u.cpu.main, rate);
-        if (ret) {
-                pr_err("Failed to change cpu pll to %lu\n", rate);
-                goto out;
-        }
-
-        ret = clk_set_parent(c->parent, c->u.cpu.main);
-        if (ret) {
-                pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
-                goto out;
-        }
-
-out:
-        clk_disable(c->u.cpu.main);
-        return ret;
-}
-
-static struct clk_ops tegra_cpu_ops = {
-        .init     = tegra2_cpu_clk_init,
-        .enable   = tegra2_cpu_clk_enable,
-        .disable  = tegra2_cpu_clk_disable,
-        .set_rate = tegra2_cpu_clk_set_rate,
-};
-
-/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
- * reset the COP block (i.e. AVP) */
-static void tegra2_cop_clk_reset(struct clk *c, bool assert)
-{
-        unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
-
-        pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
-        clk_writel(1 << 1, reg);
-}
-
-static struct clk_ops tegra_cop_ops = {
-        .reset    = tegra2_cop_clk_reset,
-};
-
-/* bus clock functions */
-static void tegra2_bus_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg);
-        c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
-        c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
-        c->mul = 1;
-}
-
-static int tegra2_bus_clk_enable(struct clk *c)
-{
-        u32 val;
-        unsigned long flags;
-
-        spin_lock_irqsave(&clock_register_lock, flags);
-
-        val = clk_readl(c->reg);
-        val &= ~(BUS_CLK_DISABLE << c->reg_shift);
-        clk_writel(val, c->reg);
-
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-
-        return 0;
-}
-
-static void tegra2_bus_clk_disable(struct clk *c)
-{
-        u32 val;
-        unsigned long flags;
-
-        spin_lock_irqsave(&clock_register_lock, flags);
-
-        val = clk_readl(c->reg);
-        val |= BUS_CLK_DISABLE << c->reg_shift;
-        clk_writel(val, c->reg);
-
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-}
-
-static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        unsigned long flags;
-        int ret = -EINVAL;
-        int i;
-
-        spin_lock_irqsave(&clock_register_lock, flags);
-
-        val = clk_readl(c->reg);
-        for (i = 1; i <= 4; i++) {
-                if (rate == parent_rate / i) {
-                        val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
-                        val |= (i - 1) << c->reg_shift;
-                        clk_writel(val, c->reg);
-                        c->div = i;
-                        c->mul = 1;
-                        ret = 0;
-                        break;
-                }
-        }
-
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-
-        return ret;
-}
-
-static struct clk_ops tegra_bus_ops = {
-        .init                   = tegra2_bus_clk_init,
-        .enable                 = tegra2_bus_clk_enable,
-        .disable                = tegra2_bus_clk_disable,
-        .set_rate               = tegra2_bus_clk_set_rate,
-};
-
-/* Blink output functions */
-
-static void tegra2_blink_clk_init(struct clk *c)
-{
-        u32 val;
-
-        val = pmc_readl(PMC_CTRL);
-        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
-        c->mul = 1;
-        val = pmc_readl(c->reg);
-
-        if (val & PMC_BLINK_TIMER_ENB) {
-                unsigned int on_off;
-
-                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
-                        PMC_BLINK_TIMER_DATA_ON_MASK;
-                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off += val;
-                /* each tick in the blink timer is 4 32KHz clocks */
-                c->div = on_off * 4;
-        } else {
-                c->div = 1;
-        }
-}
-
-static int tegra2_blink_clk_enable(struct clk *c)
-{
-        u32 val;
-
-        val = pmc_readl(PMC_DPD_PADS_ORIDE);
-        pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-
-        val = pmc_readl(PMC_CTRL);
-        pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
-
-        return 0;
-}
-
-static void tegra2_blink_clk_disable(struct clk *c)
-{
-        u32 val;
-
-        val = pmc_readl(PMC_CTRL);
-        pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
-
-        val = pmc_readl(PMC_DPD_PADS_ORIDE);
-        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-}
-
-static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        if (rate >= parent_rate) {
-                c->div = 1;
-                pmc_writel(0, c->reg);
-        } else {
-                unsigned int on_off;
-                u32 val;
-
-                on_off = DIV_ROUND_UP(parent_rate / 8, rate);
-                c->div = on_off * 8;
-
-                val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
-                        PMC_BLINK_TIMER_DATA_ON_SHIFT;
-                on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val |= on_off;
-                val |= PMC_BLINK_TIMER_ENB;
-                pmc_writel(val, c->reg);
-        }
-
-        return 0;
-}
-
-static struct clk_ops tegra_blink_clk_ops = {
-        .init                   = &tegra2_blink_clk_init,
-        .enable                 = &tegra2_blink_clk_enable,
-        .disable                = &tegra2_blink_clk_disable,
-        .set_rate               = &tegra2_blink_clk_set_rate,
-};
-
-/* PLL Functions */
-static int tegra2_pll_clk_wait_for_lock(struct clk *c)
-{
-        udelay(c->u.pll.lock_delay);
-
-        return 0;
-}
-
-static void tegra2_pll_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg + PLL_BASE);
-
-        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
-
-        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
-                pr_warning("Clock %s has unknown fixed frequency\n", c->name);
-                c->mul = 1;
-                c->div = 1;
-        } else if (val & PLL_BASE_BYPASS) {
-                c->mul = 1;
-                c->div = 1;
-        } else {
-                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
-                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-                if (c->flags & PLLU)
-                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
-                else
-                        c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
-        }
-}
-
-static int tegra2_pll_clk_enable(struct clk *c)
-{
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        val = clk_readl(c->reg + PLL_BASE);
-        val &= ~PLL_BASE_BYPASS;
-        val |= PLL_BASE_ENABLE;
-        clk_writel(val, c->reg + PLL_BASE);
-
-        tegra2_pll_clk_wait_for_lock(c);
-
-        return 0;
-}
-
-static void tegra2_pll_clk_disable(struct clk *c)
-{
-        u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        val = clk_readl(c->reg);
-        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
-        clk_writel(val, c->reg);
-}
-
-static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        unsigned long input_rate;
-        const struct clk_pll_freq_table *sel;
-
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
-        input_rate = clk_get_rate(c->parent);
-        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                if (sel->input_rate == input_rate && sel->output_rate == rate) {
-                        c->mul = sel->n;
-                        c->div = sel->m * sel->p;
-
-                        val = clk_readl(c->reg + PLL_BASE);
-                        if (c->flags & PLL_FIXED)
-                                val |= PLL_BASE_OVERRIDE;
-                        val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
-                                 PLL_BASE_DIVM_MASK);
-                        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
-                                (sel->n << PLL_BASE_DIVN_SHIFT);
-                        BUG_ON(sel->p < 1 || sel->p > 2);
-                        if (c->flags & PLLU) {
-                                if (sel->p == 1)
-                                        val |= PLLU_BASE_POST_DIV;
-                        } else {
-                                if (sel->p == 2)
-                                        val |= 1 << PLL_BASE_DIVP_SHIFT;
-                        }
-                        clk_writel(val, c->reg + PLL_BASE);
-
-                        if (c->flags & PLL_HAS_CPCON) {
-                                val = clk_readl(c->reg + PLL_MISC(c));
-                                val &= ~PLL_MISC_CPCON_MASK;
-                                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
-                                clk_writel(val, c->reg + PLL_MISC(c));
-                        }
-
-                        if (c->state == ON)
-                                tegra2_pll_clk_enable(c);
-
-                        return 0;
-                }
-        }
-        return -EINVAL;
-}
-
-static struct clk_ops tegra_pll_ops = {
-        .init                   = tegra2_pll_clk_init,
-        .enable                 = tegra2_pll_clk_enable,
-        .disable                = tegra2_pll_clk_disable,
-        .set_rate               = tegra2_pll_clk_set_rate,
-};
-
-static void tegra2_pllx_clk_init(struct clk *c)
-{
-        tegra2_pll_clk_init(c);
-
-        if (tegra_sku_id == 7)
-                c->max_rate = 750000000;
-}
-
-static struct clk_ops tegra_pllx_ops = {
-        .init     = tegra2_pllx_clk_init,
-        .enable   = tegra2_pll_clk_enable,
-        .disable  = tegra2_pll_clk_disable,
-        .set_rate = tegra2_pll_clk_set_rate,
-};
-
-static int tegra2_plle_clk_enable(struct clk *c)
-{
-        u32 val;
-
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        mdelay(1);
-
-        val = clk_readl(c->reg + PLL_BASE);
-        if (!(val & PLLE_MISC_READY))
-                return -EBUSY;
-
-        val = clk_readl(c->reg + PLL_BASE);
-        val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
-        clk_writel(val, c->reg + PLL_BASE);
-
-        return 0;
-}
-
-static struct clk_ops tegra_plle_ops = {
-        .init       = tegra2_pll_clk_init,
-        .enable     = tegra2_plle_clk_enable,
-        .set_rate   = tegra2_pll_clk_set_rate,
-};
-
-/* Clock divider ops */
-static void tegra2_pll_div_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg);
-        u32 divu71;
-        val >>= c->reg_shift;
-        c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
-        if (!(val & PLL_OUT_RESET_DISABLE))
-                c->state = OFF;
-
-        if (c->flags & DIV_U71) {
-                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
-                c->div = (divu71 + 2);
-                c->mul = 2;
-        } else if (c->flags & DIV_2) {
-                c->div = 2;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
-}
-
-static int tegra2_pll_div_clk_enable(struct clk *c)
-{
-        u32 val;
-        u32 new_val;
-        unsigned long flags;
-
-        pr_debug("%s: %s\n", __func__, c->name);
-        if (c->flags & DIV_U71) {
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                new_val = val >> c->reg_shift;
-                new_val &= 0xFFFF;
-
-                new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
-
-                val &= ~(0xFFFF << c->reg_shift);
-                val |= new_val << c->reg_shift;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-                return 0;
-        } else if (c->flags & DIV_2) {
-                BUG_ON(!(c->flags & PLLD));
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                val &= ~PLLD_MISC_DIV_RST;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-                return 0;
-        }
-        return -EINVAL;
-}
-
-static void tegra2_pll_div_clk_disable(struct clk *c)
-{
-        u32 val;
-        u32 new_val;
-        unsigned long flags;
-
-        pr_debug("%s: %s\n", __func__, c->name);
-        if (c->flags & DIV_U71) {
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                new_val = val >> c->reg_shift;
-                new_val &= 0xFFFF;
-
-                new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
-
-                val &= ~(0xFFFF << c->reg_shift);
-                val |= new_val << c->reg_shift;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-        } else if (c->flags & DIV_2) {
-                BUG_ON(!(c->flags & PLLD));
-                spin_lock_irqsave(&clock_register_lock, flags);
-                val = clk_readl(c->reg);
-                val |= PLLD_MISC_DIV_RST;
-                clk_writel(val, c->reg);
-                spin_unlock_irqrestore(&clock_register_lock, flags);
-        }
-}
-
-static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        u32 new_val;
-        int divider_u71;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        unsigned long flags;
-
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-        if (c->flags & DIV_U71) {
-                divider_u71 = clk_div71_get_divider(parent_rate, rate);
-                if (divider_u71 >= 0) {
-                        spin_lock_irqsave(&clock_register_lock, flags);
-                        val = clk_readl(c->reg);
-                        new_val = val >> c->reg_shift;
-                        new_val &= 0xFFFF;
-                        if (c->flags & DIV_U71_FIXED)
-                                new_val |= PLL_OUT_OVERRIDE;
-                        new_val &= ~PLL_OUT_RATIO_MASK;
-                        new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
-
-                        val &= ~(0xFFFF << c->reg_shift);
-                        val |= new_val << c->reg_shift;
-                        clk_writel(val, c->reg);
-                        c->div = divider_u71 + 2;
-                        c->mul = 2;
-                        spin_unlock_irqrestore(&clock_register_lock, flags);
-                        return 0;
-                }
-        } else if (c->flags & DIV_2) {
-                if (parent_rate == rate * 2)
-                        return 0;
-        }
-        return -EINVAL;
-}
-
-static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
-{
-        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_2) {
-                return DIV_ROUND_UP(parent_rate, 2);
-        }
-        return -EINVAL;
-}
-
-static struct clk_ops tegra_pll_div_ops = {
-        .init                   = tegra2_pll_div_clk_init,
-        .enable                 = tegra2_pll_div_clk_enable,
-        .disable                = tegra2_pll_div_clk_disable,
-        .set_rate               = tegra2_pll_div_clk_set_rate,
-        .round_rate             = tegra2_pll_div_clk_round_rate,
-};
-
-/* Periph clk ops */
-
-static void tegra2_periph_clk_init(struct clk *c)
-{
-        u32 val = clk_readl(c->reg);
-        const struct clk_mux_sel *mux = NULL;
-        const struct clk_mux_sel *sel;
-        u32 shift;
-        u32 mask;
-
-        if (c->flags & MUX_PWM) {
-                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
-                mask = PERIPH_CLK_SOURCE_PWM_MASK;
-        } else {
-                shift = PERIPH_CLK_SOURCE_SHIFT;
-                mask = PERIPH_CLK_SOURCE_MASK;
-        }
-
-        if (c->flags & MUX) {
-                for (sel = c->inputs; sel->input != NULL; sel++) {
-                        if ((val & mask) >> shift == sel->value)
-                                mux = sel;
-                }
-                BUG_ON(!mux);
-
-                c->parent = mux->input;
-        } else {
-                c->parent = c->inputs[0].input;
-        }
-
-        if (c->flags & DIV_U71) {
-                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
-                c->div = divu71 + 2;
-                c->mul = 2;
-        } else if (c->flags & DIV_U16) {
-                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
-                c->div = divu16 + 1;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
-
-        c->state = ON;
-
-        if (!c->u.periph.clk_num)
-                return;
-
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-
-        if (!(c->flags & PERIPH_NO_RESET))
-                if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
-                                PERIPH_CLK_TO_ENB_BIT(c))
-                        c->state = OFF;
-}
-
-static int tegra2_periph_clk_enable(struct clk *c)
-{
-        u32 val;
-        unsigned long flags;
-        int refcount;
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        if (!c->u.periph.clk_num)
-                return 0;
-
-        spin_lock_irqsave(&clock_register_lock, flags);
-
-        refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
-
-        if (refcount > 1)
-                goto out;
-
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
-        if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                        RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-        if (c->flags & PERIPH_EMC_ENB) {
-                /* The EMC peripheral clock has 2 extra enable bits */
-                /* FIXME: Do they need to be disabled? */
-                val = clk_readl(c->reg);
-                val |= 0x3 << 24;
-                clk_writel(val, c->reg);
-        }
-
-out:
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-
-        return 0;
-}
-
-static void tegra2_periph_clk_disable(struct clk *c)
-{
-        unsigned long flags;
-
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
-        if (!c->u.periph.clk_num)
-                return;
-
-        spin_lock_irqsave(&clock_register_lock, flags);
-
-        if (c->refcnt)
-                tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
-
-        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                        CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-
-        spin_unlock_irqrestore(&clock_register_lock, flags);
-}
-
-static void tegra2_periph_clk_reset(struct clk *c, bool assert)
-{
-        unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
-
-        pr_debug("%s %s on clock %s\n", __func__,
-                 assert ? "assert" : "deassert", c->name);
-
-        BUG_ON(!c->u.periph.clk_num);
-
-        if (!(c->flags & PERIPH_NO_RESET))
-                clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                           base + PERIPH_CLK_TO_ENB_SET_REG(c));
-}
-
-static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
-{
-        u32 val;
-        const struct clk_mux_sel *sel;
-        u32 mask, shift;
-
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-
-        if (c->flags & MUX_PWM) {
-                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
-                mask = PERIPH_CLK_SOURCE_PWM_MASK;
-        } else {
-                shift = PERIPH_CLK_SOURCE_SHIFT;
-                mask = PERIPH_CLK_SOURCE_MASK;
-        }
-
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~mask;
-                        val |= (sel->value) << shift;
-
-                        if (c->refcnt)
-                                clk_enable(p);
-
-                        clk_writel(val, c->reg);
-
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-
-        return -EINVAL;
-}
-
-static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        u32 val;
-        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider >= 0) {
-                        val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
-                        val |= divider;
-                        clk_writel(val, c->reg);
-                        c->div = divider + 2;
-                        c->mul = 2;
-                        return 0;
-                }
-        } else if (c->flags & DIV_U16) {
-                divider = clk_div16_get_divider(parent_rate, rate);
-                if (divider >= 0) {
-                        val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
-                        val |= divider;
-                        clk_writel(val, c->reg);
-                        c->div = divider + 1;
-                        c->mul = 1;
-                        return 0;
-                }
-        } else if (parent_rate <= rate) {
-                c->div = 1;
-                c->mul = 1;
-                return 0;
-        }
-        return -EINVAL;
-}
-
-static long tegra2_periph_clk_round_rate(struct clk *c,
-        unsigned long rate)
-{
-        int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
-        if (c->flags & DIV_U71) {
-                divider = clk_div71_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-
-                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_U16) {
-                divider = clk_div16_get_divider(parent_rate, rate);
-                if (divider < 0)
-                        return divider;
-                return DIV_ROUND_UP(parent_rate, divider + 1);
-        }
-        return -EINVAL;
-}
-
-static struct clk_ops tegra_periph_clk_ops = {
-        .init                   = &tegra2_periph_clk_init,
-        .enable                 = &tegra2_periph_clk_enable,
-        .disable                = &tegra2_periph_clk_disable,
-        .set_parent             = &tegra2_periph_clk_set_parent,
-        .set_rate               = &tegra2_periph_clk_set_rate,
-        .round_rate             = &tegra2_periph_clk_round_rate,
-        .reset                  = &tegra2_periph_clk_reset,
-};
-
-/* The SDMMC controllers have extra bits in the clock source register that
- * adjust the delay between the clock and data to compenstate for delays
- * on the PCB. */
-void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
-{
-        u32 reg;
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-
-        delay = clamp(delay, 0, 15);
-        reg = clk_readl(c->reg);
-        reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
-        reg |= SDMMC_CLK_INT_FB_SEL;
-        reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
-        clk_writel(reg, c->reg);
-
-        spin_unlock_irqrestore(&c->spinlock, flags);
-}
-
-/* External memory controller clock ops */
-static void tegra2_emc_clk_init(struct clk *c)
-{
-        tegra2_periph_clk_init(c);
-        c->max_rate = clk_get_rate_locked(c);
-}
-
-static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
-{
-        long emc_rate;
-        long clk_rate;
-
-        /*
-         * The slowest entry in the EMC clock table that is at least as
-         * fast as rate.
-         */
-        emc_rate = tegra_emc_round_rate(rate);
-        if (emc_rate < 0)
-                return c->max_rate;
-
-        /*
-         * The fastest rate the PLL will generate that is at most the
-         * requested rate.
-         */
-        clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
-
-        /*
-         * If this fails, and emc_rate > clk_rate, it's because the maximum
-         * rate in the EMC tables is larger than the maximum rate of the EMC
-         * clock. The EMC clock's max rate is the rate it was running when the
-         * kernel booted. Such a mismatch is probably due to using the wrong
-         * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
-         */
-        WARN_ONCE(emc_rate != clk_rate,
-                "emc_rate %ld != clk_rate %ld",
-                emc_rate, clk_rate);
-
-        return emc_rate;
-}
-
-static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
-{
-        int ret;
-        /*
-         * The Tegra2 memory controller has an interlock with the clock
-         * block that allows memory shadowed registers to be updated,
-         * and then transfer them to the main registers at the same
-         * time as the clock update without glitches.
-         */
-        ret = tegra_emc_set_rate(rate);
-        if (ret < 0)
-                return ret;
-
-        ret = tegra2_periph_clk_set_rate(c, rate);
-        udelay(1);
-
-        return ret;
-}
-
-static struct clk_ops tegra_emc_clk_ops = {
-        .init                   = &tegra2_emc_clk_init,
-        .enable                 = &tegra2_periph_clk_enable,
-        .disable                = &tegra2_periph_clk_disable,
-        .set_parent             = &tegra2_periph_clk_set_parent,
-        .set_rate               = &tegra2_emc_clk_set_rate,
-        .round_rate             = &tegra2_emc_clk_round_rate,
-        .reset                  = &tegra2_periph_clk_reset,
-};
-
-/* Clock doubler ops */
-static void tegra2_clk_double_init(struct clk *c)
-{
-        c->mul = 2;
-        c->div = 1;
-        c->state = ON;
-
-        if (!c->u.periph.clk_num)
-                return;
-
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-};
-
-static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
-{
-        if (rate != 2 * clk_get_rate(c->parent))
-                return -EINVAL;
-        c->mul = 2;
-        c->div = 1;
-        return 0;
-}
-
-static struct clk_ops tegra_clk_double_ops = {
-        .init                   = &tegra2_clk_double_init,
-        .enable                 = &tegra2_periph_clk_enable,
-        .disable                = &tegra2_periph_clk_disable,
-        .set_rate               = &tegra2_clk_double_set_rate,
-};
-
-/* Audio sync clock ops */
-static void tegra2_audio_sync_clk_init(struct clk *c)
-{
-        int source;
-        const struct clk_mux_sel *sel;
-        u32 val = clk_readl(c->reg);
-        c->state = (val & (1<<4)) ? OFF : ON;
-        source = val & 0xf;
-        for (sel = c->inputs; sel->input != NULL; sel++)
-                if (sel->value == source)
-                        break;
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
-}
-
-static int tegra2_audio_sync_clk_enable(struct clk *c)
-{
-        clk_writel(0, c->reg);
-        return 0;
-}
-
-static void tegra2_audio_sync_clk_disable(struct clk *c)
-{
-        clk_writel(1, c->reg);
-}
-
-static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
-{
-        u32 val;
-        const struct clk_mux_sel *sel;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~0xf;
-                        val |= sel->value;
-
-                        if (c->refcnt)
-                                clk_enable(p);
-
-                        clk_writel(val, c->reg);
-
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-
-        return -EINVAL;
-}
-
-static struct clk_ops tegra_audio_sync_clk_ops = {
-        .init       = tegra2_audio_sync_clk_init,
-        .enable     = tegra2_audio_sync_clk_enable,
-        .disable    = tegra2_audio_sync_clk_disable,
-        .set_parent = tegra2_audio_sync_clk_set_parent,
-};
-
-/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
-
-static void tegra2_cdev_clk_init(struct clk *c)
-{
-        /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
-         * currently done in the pinmux code. */
-        c->state = ON;
-
-        BUG_ON(!c->u.periph.clk_num);
-
-        if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
-                        PERIPH_CLK_TO_ENB_BIT(c)))
-                c->state = OFF;
-}
-
-static int tegra2_cdev_clk_enable(struct clk *c)
-{
-        BUG_ON(!c->u.periph.clk_num);
-
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
-        return 0;
-}
-
-static void tegra2_cdev_clk_disable(struct clk *c)
-{
-        BUG_ON(!c->u.periph.clk_num);
-
-        clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
-                CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-}
-
-static struct clk_ops tegra_cdev_clk_ops = {
-        .init                   = &tegra2_cdev_clk_init,
-        .enable                 = &tegra2_cdev_clk_enable,
-        .disable                = &tegra2_cdev_clk_disable,
-};
-
-/* shared bus ops */
-/*
- * Some clocks may have multiple downstream users that need to request a
- * higher clock rate.  Shared bus clocks provide a unique shared_bus_user
- * clock to each user.  The frequency of the bus is set to the highest
- * enabled shared_bus_user clock, with a minimum value set by the
- * shared bus.
- */
-static int tegra_clk_shared_bus_update(struct clk *bus)
-{
-        struct clk *c;
-        unsigned long rate = bus->min_rate;
-
-        list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
-                if (c->u.shared_bus_user.enabled)
-                        rate = max(c->u.shared_bus_user.rate, rate);
-
-        if (rate == clk_get_rate_locked(bus))
-                return 0;
-
-        return clk_set_rate_locked(bus, rate);
-};
-
-static void tegra_clk_shared_bus_init(struct clk *c)
-{
-        unsigned long flags;
-
-        c->max_rate = c->parent->max_rate;
-        c->u.shared_bus_user.rate = c->parent->max_rate;
-        c->state = OFF;
-        c->set = true;
-
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-
-        list_add_tail(&c->u.shared_bus_user.node,
-                &c->parent->shared_bus_list);
-
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-}
-
-static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
-{
-        unsigned long flags;
-        int ret;
-        long new_rate = rate;
-
-        new_rate = clk_round_rate(c->parent, new_rate);
-        if (new_rate < 0)
-                return new_rate;
-
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-
-        c->u.shared_bus_user.rate = new_rate;
-        ret = tegra_clk_shared_bus_update(c->parent);
-
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-
-        return ret;
-}
-
-static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
-{
-        return clk_round_rate(c->parent, rate);
-}
-
-static int tegra_clk_shared_bus_enable(struct clk *c)
-{
-        unsigned long flags;
-        int ret;
-
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-
-        c->u.shared_bus_user.enabled = true;
-        ret = tegra_clk_shared_bus_update(c->parent);
-
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-
-        return ret;
-}
-
-static void tegra_clk_shared_bus_disable(struct clk *c)
-{
-        unsigned long flags;
-        int ret;
-
-        spin_lock_irqsave(&c->parent->spinlock, flags);
-
-        c->u.shared_bus_user.enabled = false;
-        ret = tegra_clk_shared_bus_update(c->parent);
-        WARN_ON_ONCE(ret);
-
-        spin_unlock_irqrestore(&c->parent->spinlock, flags);
-}
-
-static struct clk_ops tegra_clk_shared_bus_ops = {
-        .init = tegra_clk_shared_bus_init,
-        .enable = tegra_clk_shared_bus_enable,
-        .disable = tegra_clk_shared_bus_disable,
-        .set_rate = tegra_clk_shared_bus_set_rate,
-        .round_rate = tegra_clk_shared_bus_round_rate,
-};
-
-
-/* Clock definitions */
-static struct clk tegra_clk_32k = {
-        .name = "clk_32k",
-        .rate = 32768,
-        .ops  = NULL,
-        .max_rate = 32768,
-};
-
-static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
-        {32768, 12000000, 366, 1, 1, 0},
-        {32768, 13000000, 397, 1, 1, 0},
-        {32768, 19200000, 586, 1, 1, 0},
-        {32768, 26000000, 793, 1, 1, 0},
-        {0, 0, 0, 0, 0, 0},
-};
-
-static struct clk tegra_pll_s = {
-        .name      = "pll_s",
-        .flags     = PLL_ALT_MISC_REG,
-        .ops       = &tegra_pll_ops,
-        .parent    = &tegra_clk_32k,
-        .max_rate  = 26000000,
-        .reg       = 0xf0,
-        .u.pll = {
-                .input_min = 32768,
-                .input_max = 32768,
-                .cf_min    = 0, /* FIXME */
-                .cf_max    = 0, /* FIXME */
-                .vco_min   = 12000000,
-                .vco_max   = 26000000,
-                .freq_table = tegra_pll_s_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk_mux_sel tegra_clk_m_sel[] = {
-        { .input = &tegra_clk_32k, .value = 0},
-        { .input = &tegra_pll_s,  .value = 1},
-        { NULL , 0},
-};
-
-static struct clk tegra_clk_m = {
-        .name      = "clk_m",
-        .flags     = ENABLE_ON_INIT,
-        .ops       = &tegra_clk_m_ops,
-        .inputs    = tegra_clk_m_sel,
-        .reg       = 0x1fc,
-        .reg_shift = 28,
-        .max_rate  = 26000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
-        { 12000000, 600000000, 600, 12, 1, 8 },
-        { 13000000, 600000000, 600, 13, 1, 8 },
-        { 19200000, 600000000, 500, 16, 1, 6 },
-        { 26000000, 600000000, 600, 26, 1, 8 },
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_c = {
-        .name      = "pll_c",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x80,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 600000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_c_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_c_out1 = {
-        .name      = "pll_c_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_c,
-        .reg       = 0x84,
-        .reg_shift = 0,
-        .max_rate  = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_m = {
-        .name      = "pll_m",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x90,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 800000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1200000000,
-                .freq_table = tegra_pll_m_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_m_out1 = {
-        .name      = "pll_m_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_m,
-        .reg       = 0x94,
-        .reg_shift = 0,
-        .max_rate  = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 19200000, 216000000, 90,   4, 2, 1},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 12000000, 432000000, 432, 12, 1, 8},
-        { 13000000, 432000000, 432, 13, 1, 8},
-        { 19200000, 432000000, 90,   4, 1, 1},
-        { 26000000, 432000000, 432, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_p = {
-        .name      = "pll_p",
-        .flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xa0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 432000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_p_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_p_out1 = {
-        .name      = "pll_p_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
-        .name      = "pll_p_out2",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out3 = {
-        .name      = "pll_p_out3",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out4 = {
-        .name      = "pll_p_out4",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_a = {
-        .name      = "pll_a",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xb0,
-        .parent    = &tegra_pll_p_out1,
-        .max_rate  = 73728000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_a_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_a_out0 = {
-        .name      = "pll_a_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_a,
-        .reg       = 0xb4,
-        .reg_shift = 0,
-        .max_rate  = 73728000,
-};
-
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 19200000, 216000000, 135, 12, 1, 3},
-        { 26000000, 216000000, 216, 26, 1, 4},
-
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
-
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_d = {
-        .name      = "pll_d",
-        .flags     = PLL_HAS_CPCON | PLLD,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xd0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 40000000,
-                .vco_max   = 1000000000,
-                .freq_table = tegra_pll_d_freq_table,
-                .lock_delay = 1000,
-        },
-};
-
-static struct clk tegra_pll_d_out0 = {
-        .name      = "pll_d_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLD,
-        .parent    = &tegra_pll_d,
-        .max_rate  = 500000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 0},
-        { 13000000, 480000000, 960, 13, 2, 0},
-        { 19200000, 480000000, 200, 4,  2, 0},
-        { 26000000, 480000000, 960, 26, 2, 0},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_u = {
-        .name      = "pll_u",
-        .flags     = PLLU,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xc0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 480000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 480000000,
-                .vco_max   = 960000000,
-                .freq_table = tegra_pll_u_freq_table,
-                .lock_delay = 1000,
-        },
-};
-
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
-        /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-
-        /* 912 MHz */
-        { 12000000, 912000000,  912,  12, 1, 12},
-        { 13000000, 912000000,  912,  13, 1, 12},
-        { 19200000, 912000000,  760,  16, 1, 8},
-        { 26000000, 912000000,  912,  26, 1, 12},
-
-        /* 816 MHz */
-        { 12000000, 816000000,  816,  12, 1, 12},
-        { 13000000, 816000000,  816,  13, 1, 12},
-        { 19200000, 816000000,  680,  16, 1, 8},
-        { 26000000, 816000000,  816,  26, 1, 12},
-
-        /* 760 MHz */
-        { 12000000, 760000000,  760,  12, 1, 12},
-        { 13000000, 760000000,  760,  13, 1, 12},
-        { 19200000, 760000000,  950,  24, 1, 8},
-        { 26000000, 760000000,  760,  26, 1, 12},
-
-        /* 750 MHz */
-        { 12000000, 750000000,  750,  12, 1, 12},
-        { 13000000, 750000000,  750,  13, 1, 12},
-        { 19200000, 750000000,  625,  16, 1, 8},
-        { 26000000, 750000000,  750,  26, 1, 12},
-
-        /* 608 MHz */
-        { 12000000, 608000000,  608,  12, 1, 12},
-        { 13000000, 608000000,  608,  13, 1, 12},
-        { 19200000, 608000000,  380,  12, 1, 8},
-        { 26000000, 608000000,  608,  26, 1, 12},
-
-        /* 456 MHz */
-        { 12000000, 456000000,  456,  12, 1, 12},
-        { 13000000, 456000000,  456,  13, 1, 12},
-        { 19200000, 456000000,  380,  16, 1, 8},
-        { 26000000, 456000000,  456,  26, 1, 12},
-
-        /* 312 MHz */
-        { 12000000, 312000000,  312,  12, 1, 12},
-        { 13000000, 312000000,  312,  13, 1, 12},
-        { 19200000, 312000000,  260,  16, 1, 8},
-        { 26000000, 312000000,  312,  26, 1, 12},
-
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_x = {
-        .name      = "pll_x",
-        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
-        .ops       = &tegra_pllx_ops,
-        .reg       = 0xe0,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1200000000,
-                .freq_table = tegra_pll_x_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
-        { 12000000, 100000000,  200,  24, 1, 0 },
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_e = {
-        .name      = "pll_e",
-        .flags     = PLL_ALT_MISC_REG,
-        .ops       = &tegra_plle_ops,
-        .parent    = &tegra_clk_m,
-        .reg       = 0xe8,
-        .max_rate  = 100000000,
-        .u.pll = {
-                .input_min = 12000000,
-                .input_max = 12000000,
-                .freq_table = tegra_pll_e_freq_table,
-        },
-};
-
-static struct clk tegra_clk_d = {
-        .name      = "clk_d",
-        .flags     = PERIPH_NO_RESET,
-        .ops       = &tegra_clk_double_ops,
-        .reg       = 0x34,
-        .reg_shift = 12,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 52000000,
-        .u.periph  = {
-                .clk_num = 90,
-        },
-};
-
-/* dap_mclk1, belongs to the cdev1 pingroup. */
-static struct clk tegra_clk_cdev1 = {
-        .name      = "cdev1",
-        .ops       = &tegra_cdev_clk_ops,
-        .rate      = 26000000,
-        .max_rate  = 26000000,
-        .u.periph  = {
-                .clk_num = 94,
-        },
-};
-
-/* dap_mclk2, belongs to the cdev2 pingroup. */
-static struct clk tegra_clk_cdev2 = {
-        .name      = "cdev2",
-        .ops       = &tegra_cdev_clk_ops,
-        .rate      = 26000000,
-        .max_rate  = 26000000,
-        .u.periph  = {
-                .clk_num   = 93,
-        },
-};
-
-/* initialized before peripheral clocks */
-static struct clk_mux_sel mux_audio_sync_clk[8+1];
-static const struct audio_sources {
-        const char *name;
-        int value;
-} mux_audio_sync_clk_sources[] = {
-        { .name = "spdif_in", .value = 0 },
-        { .name = "i2s1", .value = 1 },
-        { .name = "i2s2", .value = 2 },
-        { .name = "pll_a_out0", .value = 4 },
-#if 0 /* FIXME: not implemented */
-        { .name = "ac97", .value = 3 },
-        { .name = "ext_audio_clk2", .value = 5 },
-        { .name = "ext_audio_clk1", .value = 6 },
-        { .name = "ext_vimclk", .value = 7 },
-#endif
-        { NULL, 0 }
-};
-
-static struct clk tegra_clk_audio = {
-        .name      = "audio",
-        .inputs    = mux_audio_sync_clk,
-        .reg       = 0x38,
-        .max_rate  = 73728000,
-        .ops       = &tegra_audio_sync_clk_ops
-};
-
-static struct clk tegra_clk_audio_2x = {
-        .name      = "audio_2x",
-        .flags     = PERIPH_NO_RESET,
-        .max_rate  = 48000000,
-        .ops       = &tegra_clk_double_ops,
-        .reg       = 0x34,
-        .reg_shift = 8,
-        .parent    = &tegra_clk_audio,
-        .u.periph = {
-                .clk_num = 89,
-        },
-};
-
-static struct clk_lookup tegra_audio_clk_lookups[] = {
-        { .con_id = "audio", .clk = &tegra_clk_audio },
-        { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
-};
-
-/* This is called after peripheral clocks are initialized, as the
- * audio_sync clock depends on some of the peripheral clocks.
- */
-
-static void init_audio_sync_clock_mux(void)
-{
-        int i;
-        struct clk_mux_sel *sel = mux_audio_sync_clk;
-        const struct audio_sources *src = mux_audio_sync_clk_sources;
-        struct clk_lookup *lookup;
-
-        for (i = 0; src->name; i++, sel++, src++) {
-                sel->input = tegra_get_clock_by_name(src->name);
-                if (!sel->input)
-                        pr_err("%s: could not find clk %s\n", __func__,
-                                src->name);
-                sel->value = src->value;
-        }
-
-        lookup = tegra_audio_clk_lookups;
-        for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
-                clk_init(lookup->clk);
-                clkdev_add(lookup);
-        }
-}
-
-static struct clk_mux_sel mux_cclk[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c,        .value = 1},
-        { .input = &tegra_clk_32k,      .value = 2},
-        { .input = &tegra_pll_m,        .value = 3},
-        { .input = &tegra_pll_p,        .value = 4},
-        { .input = &tegra_pll_p_out4,   .value = 5},
-        { .input = &tegra_pll_p_out3,   .value = 6},
-        { .input = &tegra_clk_d,        .value = 7},
-        { .input = &tegra_pll_x,        .value = 8},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_sclk[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c_out1,   .value = 1},
-        { .input = &tegra_pll_p_out4,   .value = 2},
-        { .input = &tegra_pll_p_out3,   .value = 3},
-        { .input = &tegra_pll_p_out2,   .value = 4},
-        { .input = &tegra_clk_d,        .value = 5},
-        { .input = &tegra_clk_32k,      .value = 6},
-        { .input = &tegra_pll_m_out1,   .value = 7},
-        { NULL, 0},
-};
-
-static struct clk tegra_clk_cclk = {
-        .name   = "cclk",
-        .inputs = mux_cclk,
-        .reg    = 0x20,
-        .ops    = &tegra_super_ops,
-        .max_rate = 1000000000,
-};
-
-static struct clk tegra_clk_sclk = {
-        .name   = "sclk",
-        .inputs = mux_sclk,
-        .reg    = 0x28,
-        .ops    = &tegra_super_ops,
-        .max_rate = 240000000,
-        .min_rate = 120000000,
-};
-
-static struct clk tegra_clk_virtual_cpu = {
-        .name      = "cpu",
-        .parent    = &tegra_clk_cclk,
-        .ops       = &tegra_cpu_ops,
-        .max_rate  = 1000000000,
-        .u.cpu = {
-                .main      = &tegra_pll_x,
-                .backup    = &tegra_pll_p,
-        },
-};
-
-static struct clk tegra_clk_cop = {
-        .name      = "cop",
-        .parent    = &tegra_clk_sclk,
-        .ops       = &tegra_cop_ops,
-        .max_rate  = 240000000,
-};
-
-static struct clk tegra_clk_hclk = {
-        .name           = "hclk",
-        .flags          = DIV_BUS,
-        .parent         = &tegra_clk_sclk,
-        .reg            = 0x30,
-        .reg_shift      = 4,
-        .ops            = &tegra_bus_ops,
-        .max_rate       = 240000000,
-};
-
-static struct clk tegra_clk_pclk = {
-        .name           = "pclk",
-        .flags          = DIV_BUS,
-        .parent         = &tegra_clk_hclk,
-        .reg            = 0x30,
-        .reg_shift      = 0,
-        .ops            = &tegra_bus_ops,
-        .max_rate       = 120000000,
-};
-
-static struct clk tegra_clk_blink = {
-        .name           = "blink",
-        .parent         = &tegra_clk_32k,
-        .reg            = 0x40,
-        .ops            = &tegra_blink_clk_ops,
-        .max_rate       = 32768,
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
-        { .input = &tegra_pll_m, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_pll_a_out0, .value = 3},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
-        { .input = &tegra_pll_m, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
-        { .input = &tegra_pll_p, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_m, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
-        {.input = &tegra_pll_a_out0, .value = 0},
-        {.input = &tegra_clk_audio_2x, .value = 1},
-        {.input = &tegra_pll_p, .value = 2},
-        {.input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
-        {.input = &tegra_pll_p, .value = 0},
-        {.input = &tegra_pll_d_out0, .value = 1},
-        {.input = &tegra_pll_c, .value = 2},
-        {.input = &tegra_clk_m, .value = 3},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_clk_audio,     .value = 2},
-        {.input = &tegra_clk_m,     .value = 3},
-        {.input = &tegra_clk_32k,   .value = 4},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_pll_m,     .value = 2},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_clk_m[] = {
-        { .input = &tegra_clk_m, .value = 0},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_out3[] = {
-        { .input = &tegra_pll_p_out3, .value = 0},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_plld[] = {
-        { .input = &tegra_pll_d, .value = 0},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_clk_32k[] = {
-        { .input = &tegra_clk_32k, .value = 0},
-        { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pclk[] = {
-        { .input = &tegra_clk_pclk, .value = 0},
-        { NULL, 0},
-};
-
-static struct clk tegra_clk_emc = {
-        .name = "emc",
-        .ops = &tegra_emc_clk_ops,
-        .reg = 0x19c,
-        .max_rate = 800000000,
-        .inputs = mux_pllm_pllc_pllp_clkm,
-        .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
-        .u.periph = {
-                .clk_num = 57,
-        },
-};
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_periph_clk_ops,     \
-                .reg       = _reg,                      \
-                .inputs    = _inputs,                   \
-                .flags     = _flags,                    \
-                .max_rate  = _max,                      \
-                .u.periph = {                           \
-                        .clk_num   = _clk_num,          \
-                },                                      \
-        }
-
-#define SHARED_CLK(_name, _dev, _con, _parent)          \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_clk_shared_bus_ops, \
-                .parent = _parent,                      \
-        }
-
-static struct clk tegra_list_clks[] = {
-        PERIPH_CLK("apbdma",    "tegra-apbdma",         NULL,   34,     0,      108000000, mux_pclk,                    0),
-        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET),
-        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("i2s1",      "tegra20-i2s.0",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
-        PERIPH_CLK("i2s2",      "tegra20-i2s.1",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
-        PERIPH_CLK("spdif_out", "spdif_out",            NULL,   10,     0x108,  100000000, mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
-        PERIPH_CLK("spdif_in",  "spdif_in",             NULL,   10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71),
-        PERIPH_CLK("pwm",       "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_audio_clkm_clk32,      MUX | DIV_U71 | MUX_PWM),
-        PERIPH_CLK("spi",       "spi",                  NULL,   43,     0x114,  40000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("xio",       "xio",                  NULL,   45,     0x120,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("twc",       "twc",                  NULL,   16,     0x12c,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc1",      "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc2",      "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc3",      "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sbc4",      "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("ide",       "ide",                  NULL,   25,     0x144,  100000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("ndflash",   "tegra_nand",           NULL,   13,     0x160,  164000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",        NULL,   69,     0x1bc,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",        NULL,   15,     0x164,  52000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("vcp",       "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsea",      "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsev",      "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("vde",       "tegra-avp",            "vde",  61,     0x1c8,  250000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* max rate ??? */
-        /* FIXME: what is la? */
-        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("owr",       "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("nor",       "nor",                  NULL,   42,     0x1d0,  92000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("i2c1",      "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("i2c2",      "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("dvc",       "tegra-i2c.3",          NULL,   47,     0x128,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U16),
-        PERIPH_CLK("i2c1_i2c",  "tegra-i2c.0",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("i2c2_i2c",  "tegra-i2c.1",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("i2c3_i2c",  "tegra-i2c.2",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("dvc_i2c",   "tegra-i2c.3",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("uarta",     "tegra-uart.0",         NULL,   6,      0x178,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartb",     "tegra-uart.1",         NULL,   7,      0x17c,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartc",     "tegra-uart.2",         NULL,   55,     0x1a0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartd",     "tegra-uart.3",         NULL,   65,     0x1c0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uarte",     "tegra-uart.4",         NULL,   66,     0x1c4,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
-        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("vi",        "tegra_camera",         "vi",   20,     0x148,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
-        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("mpe",       "mpe",                  NULL,   60,     0x170,  250000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  166000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
-        PERIPH_CLK("cve",       "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX), /* scales with voltage and process_id */
-        PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX), /* scales with voltage and process_id */
-        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("dsi",       "dsi",                  NULL,   48,     0,      500000000, mux_plld,                    0), /* scales with voltage */
-        PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      72000000,  mux_pllp_out3,               0),
-        PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
-        PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
-        PERIPH_CLK("pex",       NULL,                   "pex",  70,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
-        PERIPH_CLK("afi",       NULL,                   "afi",  72,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
-        PERIPH_CLK("pcie_xclk", NULL,             "pcie_xclk",  74,     0,      26000000,  mux_clk_m,                   PERIPH_MANUAL_RESET),
-
-        SHARED_CLK("avp.sclk",  "tegra-avp",            "sclk", &tegra_clk_sclk),
-        SHARED_CLK("avp.emc",   "tegra-avp",            "emc",  &tegra_clk_emc),
-        SHARED_CLK("cpu.emc",   "cpu",                  "emc",  &tegra_clk_emc),
-        SHARED_CLK("disp1.emc", "tegradc.0",            "emc",  &tegra_clk_emc),
-        SHARED_CLK("disp2.emc", "tegradc.1",            "emc",  &tegra_clk_emc),
-        SHARED_CLK("hdmi.emc",  "hdmi",                 "emc",  &tegra_clk_emc),
-        SHARED_CLK("host.emc",  "tegra_grhost",         "emc",  &tegra_clk_emc),
-        SHARED_CLK("usbd.emc",  "fsl-tegra-udc",        "emc",  &tegra_clk_emc),
-        SHARED_CLK("usb1.emc",  "tegra-ehci.0",         "emc",  &tegra_clk_emc),
-        SHARED_CLK("usb2.emc",  "tegra-ehci.1",         "emc",  &tegra_clk_emc),
-        SHARED_CLK("usb3.emc",  "tegra-ehci.2",         "emc",  &tegra_clk_emc),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con)                \
-        {                                               \
-                .name   = _name,                        \
-                .lookup = {                             \
-                        .dev_id = _dev,                 \
-                        .con_id         = _con,         \
-                },                                      \
-        }
-
-/* Some clocks may be used by different drivers depending on the board
- * configuration.  List those here to register them twice in the clock lookup
- * table under two names.
- */
-static struct clk_duplicate tegra_clk_duplicates[] = {
-        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
-        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
-        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
-        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
-        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
-        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
-        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
-        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-        CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
-        CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
-        CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
-        CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
-        CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
-        CLK_DUPLICATE("cop", "tegra-avp", "cop"),
-        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-};
-
-#define CLK(dev, con, ck)       \
-        {                       \
-                .dev_id = dev,  \
-                .con_id = con,  \
-                .clk = ck,      \
-        }
-
-static struct clk *tegra_ptr_clks[] = {
-        &tegra_clk_32k,
-        &tegra_pll_s,
-        &tegra_clk_m,
-        &tegra_pll_m,
-        &tegra_pll_m_out1,
-        &tegra_pll_c,
-        &tegra_pll_c_out1,
-        &tegra_pll_p,
-        &tegra_pll_p_out1,
-        &tegra_pll_p_out2,
-        &tegra_pll_p_out3,
-        &tegra_pll_p_out4,
-        &tegra_pll_a,
-        &tegra_pll_a_out0,
-        &tegra_pll_d,
-        &tegra_pll_d_out0,
-        &tegra_pll_u,
-        &tegra_pll_x,
-        &tegra_pll_e,
-        &tegra_clk_cclk,
-        &tegra_clk_sclk,
-        &tegra_clk_hclk,
-        &tegra_clk_pclk,
-        &tegra_clk_d,
-        &tegra_clk_cdev1,
-        &tegra_clk_cdev2,
-        &tegra_clk_virtual_cpu,
-        &tegra_clk_blink,
-        &tegra_clk_cop,
-        &tegra_clk_emc,
-};
-
-static void tegra2_init_one_clock(struct clk *c)
-{
-        clk_init(c);
-        INIT_LIST_HEAD(&c->shared_bus_list);
-        if (!c->lookup.dev_id && !c->lookup.con_id)
-                c->lookup.con_id = c->name;
-        c->lookup.clk = c;
-        clkdev_add(&c->lookup);
-}
-
-void __init tegra2_init_clocks(void)
-{
-        int i;
-        struct clk *c;
-
-        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
-                tegra2_init_one_clock(tegra_ptr_clks[i]);
-
-        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-                tegra2_init_one_clock(&tegra_list_clks[i]);
-
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-                if (!c) {
-                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                                tegra_clk_duplicates[i].name);
-                        continue;
-                }
-
-                tegra_clk_duplicates[i].lookup.clk = c;
-                clkdev_add(&tegra_clk_duplicates[i].lookup);
-        }
-
-        init_audio_sync_clock_mux();
-}
-
-#ifdef CONFIG_PM
-static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
-                           PERIPH_CLK_SOURCE_NUM + 22];
-
-void tegra_clk_suspend(void)
-{
-        unsigned long off, i;
-        u32 *ctx = clk_rst_suspend;
-
-        *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
-        *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
-        *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
-        *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
-        *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
-        *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
-        *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
-
-        *ctx++ = clk_readl(tegra_pll_m_out1.reg);
-        *ctx++ = clk_readl(tegra_pll_a_out0.reg);
-        *ctx++ = clk_readl(tegra_pll_c_out1.reg);
-
-        *ctx++ = clk_readl(tegra_clk_cclk.reg);
-        *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
-
-        *ctx++ = clk_readl(tegra_clk_sclk.reg);
-        *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
-        *ctx++ = clk_readl(tegra_clk_pclk.reg);
-
-        *ctx++ = clk_readl(tegra_clk_audio.reg);
-
-        for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
-                        off += 4) {
-                if (off == PERIPH_CLK_SOURCE_EMC)
-                        continue;
-                *ctx++ = clk_readl(off);
-        }
-
-        off = RST_DEVICES;
-        for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
-                *ctx++ = clk_readl(off);
-
-        off = CLK_OUT_ENB;
-        for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
-                *ctx++ = clk_readl(off);
-
-        *ctx++ = clk_readl(MISC_CLK_ENB);
-        *ctx++ = clk_readl(CLK_MASK_ARM);
-
-        BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
-}
-
-void tegra_clk_resume(void)
-{
-        unsigned long off, i;
-        const u32 *ctx = clk_rst_suspend;
-        u32 val;
-
-        val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
-        val |= *ctx++;
-        clk_writel(val, OSC_CTRL);
-
-        clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
-        clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
-        clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
-        clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
-        clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
-        clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
-        udelay(1000);
-
-        clk_writel(*ctx++, tegra_pll_m_out1.reg);
-        clk_writel(*ctx++, tegra_pll_a_out0.reg);
-        clk_writel(*ctx++, tegra_pll_c_out1.reg);
-
-        clk_writel(*ctx++, tegra_clk_cclk.reg);
-        clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
-
-        clk_writel(*ctx++, tegra_clk_sclk.reg);
-        clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
-        clk_writel(*ctx++, tegra_clk_pclk.reg);
-
-        clk_writel(*ctx++, tegra_clk_audio.reg);
-
-        /* enable all clocks before configuring clock sources */
-        clk_writel(0xbffffff9ul, CLK_OUT_ENB);
-        clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
-        clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
-        wmb();
-
-        for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
-                        off += 4) {
-                if (off == PERIPH_CLK_SOURCE_EMC)
-                        continue;
-                clk_writel(*ctx++, off);
-        }
-        wmb();
-
-        off = RST_DEVICES;
-        for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
-                clk_writel(*ctx++, off);
-        wmb();
-
-        off = CLK_OUT_ENB;
-        for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
-                clk_writel(*ctx++, off);
-        wmb();
-
-        clk_writel(*ctx++, MISC_CLK_ENB);
-        clk_writel(*ctx++, CLK_MASK_ARM);
-}
-#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6674f100e16f..5cd502c27163 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra30_clocks.c
  *
- * Copyright (c) 2010-2011 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -35,6 +35,7 @@
 
 #include "clock.h"
 #include "fuse.h"
+#include "tegra_cpu_car.h"
 
 #define USE_PLL_LOCK_BITS 0
 
@@ -299,6 +300,16 @@
 /* FIXME: recommended safety delay after lock is detected */
 #define PLL_POST_LOCK_DELAY             100
 
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX          0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET      0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR      0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR    0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
+
+#define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
+#define CPU_RESET(cpu)  (0x1111ul << (cpu))
+
 /**
 * Structure defining the fields for USB UTMI clocks Parameters.
 */
@@ -365,30 +376,32 @@ static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
 
 #define clk_writel(value, reg) \
-        __raw_writel(value, (u32)reg_clk_base + (reg))
+        __raw_writel(value, reg_clk_base + (reg))
 #define clk_readl(reg) \
-        __raw_readl((u32)reg_clk_base + (reg))
+        __raw_readl(reg_clk_base + (reg))
 #define pmc_writel(value, reg) \
-        __raw_writel(value, (u32)reg_pmc_base + (reg))
+        __raw_writel(value, reg_pmc_base + (reg))
 #define pmc_readl(reg) \
-        __raw_readl((u32)reg_pmc_base + (reg))
+        __raw_readl(reg_pmc_base + (reg))
 #define chipid_readl() \
-        __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV)
+        __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
 
 #define clk_writel_delay(value, reg)                                    \
         do {                                                            \
-                __raw_writel((value), (u32)reg_clk_base + (reg));       \
+                __raw_writel((value), reg_clk_base + (reg));    \
                 udelay(2);                                              \
         } while (0)
 
-
-static inline int clk_set_div(struct clk *c, u32 n)
+static inline int clk_set_div(struct clk_tegra *c, u32 n)
 {
-        return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
+        struct clk *clk = c->hw.clk;
+
+        return clk_set_rate(clk,
+                        (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
 }
 
 static inline u32 periph_clk_to_reg(
-        struct clk *c, u32 reg_L, u32 reg_V, int offs)
+        struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
 {
         u32 reg = c->u.periph.clk_num / 32;
         BUG_ON(reg >= RST_DEVICES_NUM);
@@ -470,15 +483,32 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
         return divider_u16 - 1;
 }
 
+static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra30_clk_32k_ops = {
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
+};
+
 /* clk_m functions */
-static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
+static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        if (!to_clk_tegra(hw)->fixed_rate)
+                to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
+        return to_clk_tegra(hw)->fixed_rate;
+}
+
+static void tegra30_clk_m_init(struct clk_hw *hw)
 {
         u32 osc_ctrl = clk_readl(OSC_CTRL);
         u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
         u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
 
-        c->rate = clk_measure_input_freq();
-        switch (c->rate) {
+        switch (to_clk_tegra(hw)->fixed_rate) {
         case 12000000:
                 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
@@ -508,46 +538,44 @@ static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
                 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
                 break;
         default:
-                pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
+                pr_err("%s: Unexpected clock rate %ld", __func__,
+                                to_clk_tegra(hw)->fixed_rate);
                 BUG();
         }
         clk_writel(auto_clock_control, OSC_CTRL);
-        return c->rate;
 }
 
-static void tegra30_clk_m_init(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        tegra30_clk_m_autodetect_rate(c);
-}
+struct clk_ops tegra30_clk_m_ops = {
+        .init = tegra30_clk_m_init,
+        .recalc_rate = tegra30_clk_m_recalc_rate,
+};
 
-static int tegra30_clk_m_enable(struct clk *c)
+static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
 {
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        return 0;
-}
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
 
-static void tegra30_clk_m_disable(struct clk *c)
-{
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        WARN(1, "Attempting to disable main SoC clock\n");
-}
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
 
-static struct clk_ops tegra_clk_m_ops = {
-        .init           = tegra30_clk_m_init,
-        .enable         = tegra30_clk_m_enable,
-        .disable        = tegra30_clk_m_disable,
-};
+        return rate;
+}
 
-static struct clk_ops tegra_clk_m_div_ops = {
-        .enable         = tegra30_clk_m_enable,
+struct clk_ops tegra_clk_m_div_ops = {
+        .recalc_rate = tegra30_clk_m_div_recalc_rate,
 };
 
 /* PLL reference divider functions */
-static void tegra30_pll_ref_init(struct clk *c)
+static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
+                        unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long rate = parent_rate;
         u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
-        pr_debug("%s on clock %s\n", __func__, c->name);
 
         switch (pll_ref_div) {
         case OSC_CTRL_PLL_REF_DIV_1:
@@ -564,13 +592,18 @@ static void tegra30_pll_ref_init(struct clk *c)
                 BUG();
         }
         c->mul = 1;
-        c->state = ON;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
 }
 
-static struct clk_ops tegra_pll_ref_ops = {
-        .init           = tegra30_pll_ref_init,
-        .enable         = tegra30_clk_m_enable,
-        .disable        = tegra30_clk_m_disable,
+struct clk_ops tegra_pll_ref_ops = {
+        .recalc_rate = tegra30_pll_ref_recalc_rate,
 };
 
 /* super clock functions */
@@ -581,56 +614,50 @@ static struct clk_ops tegra_pll_ref_ops = {
  * only when its parent is a fixed rate PLL, since we can't change PLL rate
  * in this case.
  */
-static void tegra30_super_clk_init(struct clk *c)
+static void tegra30_super_clk_init(struct clk_hw *hw)
 {
-        u32 val;
-        int source;
-        int shift;
-        const struct clk_mux_sel *sel;
-        val = clk_readl(c->reg + SUPER_CLK_MUX);
-        c->state = ON;
-        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
-                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
-        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
-                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        source = (val >> shift) & SUPER_SOURCE_MASK;
-        if (c->flags & DIV_2)
-                source |= val & SUPER_LP_DIV2_BYPASS;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->value == source)
-                        break;
-        }
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk_tegra *p =
+                        to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
 
+        c->state = ON;
         if (c->flags & DIV_U71) {
                 /* Init safe 7.1 divider value (does not affect PLLX path) */
                 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
                            c->reg + SUPER_CLK_DIVIDER);
                 c->mul = 2;
                 c->div = 2;
-                if (!(c->parent->flags & PLLX))
+                if (!(p->flags & PLLX))
                         c->div += SUPER_CLOCK_DIV_U71_MIN;
         } else
                 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
 }
 
-static int tegra30_super_clk_enable(struct clk *c)
+static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
 {
-        return 0;
-}
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val;
+        int source;
+        int shift;
 
-static void tegra30_super_clk_disable(struct clk *c)
-{
-        /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
-           geared up g-mode super clock - mode switch may request to disable
-           either of them; accept request with no affect on h/w */
+        val = clk_readl(c->reg + SUPER_CLK_MUX);
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        source = (val >> shift) & SUPER_SOURCE_MASK;
+        if (c->flags & DIV_2)
+                source |= val & SUPER_LP_DIV2_BYPASS;
+
+        return source;
 }
 
-static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk_tegra *p =
+                        to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
         u32 val;
-        const struct clk_mux_sel *sel;
         int shift;
 
         val = clk_readl(c->reg + SUPER_CLK_MUX);
@@ -638,48 +665,36 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
                 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
         shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
                 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        /* For LP mode super-clock switch between PLLX direct
-                           and divided-by-2 outputs is allowed only when other
-                           than PLLX clock source is current parent */
-                        if ((c->flags & DIV_2) && (p->flags & PLLX) &&
-                            ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
-                                if (c->parent->flags & PLLX)
-                                        return -EINVAL;
-                                val ^= SUPER_LP_DIV2_BYPASS;
-                                clk_writel_delay(val, c->reg);
-                        }
-                        val &= ~(SUPER_SOURCE_MASK << shift);
-                        val |= (sel->value & SUPER_SOURCE_MASK) << shift;
-
-                        /* 7.1 divider for CPU super-clock does not affect
-                           PLLX path */
-                        if (c->flags & DIV_U71) {
-                                u32 div = 0;
-                                if (!(p->flags & PLLX)) {
-                                        div = clk_readl(c->reg +
-                                                        SUPER_CLK_DIVIDER);
-                                        div &= SUPER_CLOCK_DIV_U71_MASK;
-                                        div >>= SUPER_CLOCK_DIV_U71_SHIFT;
-                                }
-                                c->div = div + 2;
-                                c->mul = 2;
-                        }
-
-                        if (c->refcnt)
-                                clk_enable(p);
-
-                        clk_writel_delay(val, c->reg);
 
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
+        /* For LP mode super-clock switch between PLLX direct
+           and divided-by-2 outputs is allowed only when other
+           than PLLX clock source is current parent */
+        if ((c->flags & DIV_2) && (p->flags & PLLX) &&
+            ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
+                if (p->flags & PLLX)
+                        return -EINVAL;
+                val ^= SUPER_LP_DIV2_BYPASS;
+                clk_writel_delay(val, c->reg);
+        }
+        val &= ~(SUPER_SOURCE_MASK << shift);
+        val |= (index & SUPER_SOURCE_MASK) << shift;
 
-                        clk_reparent(c, p);
-                        return 0;
+        /* 7.1 divider for CPU super-clock does not affect
+           PLLX path */
+        if (c->flags & DIV_U71) {
+                u32 div = 0;
+                if (!(p->flags & PLLX)) {
+                        div = clk_readl(c->reg +
+                                        SUPER_CLK_DIVIDER);
+                        div &= SUPER_CLOCK_DIV_U71_MASK;
+                        div >>= SUPER_CLOCK_DIV_U71_SHIFT;
                 }
+                c->div = div + 2;
+                c->mul = 2;
         }
-        return -EINVAL;
+        clk_writel_delay(val, c->reg);
+
+        return 0;
 }
 
 /*
@@ -691,10 +706,15 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
  * rate of this PLL can't be changed, and it has many other children. In
  * this case use 7.1 fractional divider to adjust the super clock rate.
  */
-static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
-        if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) {
-                int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate,
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk *parent = __clk_get_parent(hw->clk);
+        struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
+
+        if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
+                int div = clk_div71_get_divider(parent_rate,
                                         rate, c->flags, ROUND_DIVIDER_DOWN);
                 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
 
@@ -704,55 +724,86 @@ static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
                 c->mul = 2;
                 return 0;
         }
-        return clk_set_rate(c->parent, rate);
+        return 0;
+}
+
+static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
 }
 
-static struct clk_ops tegra_super_ops = {
-        .init                   = tegra30_super_clk_init,
-        .enable                 = tegra30_super_clk_enable,
-        .disable                = tegra30_super_clk_disable,
-        .set_parent             = tegra30_super_clk_set_parent,
-        .set_rate               = tegra30_super_clk_set_rate,
+static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk *parent = __clk_get_parent(hw->clk);
+        struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
+        int mul = 2;
+        int div;
+
+        if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
+                div = clk_div71_get_divider(*prate,
+                                rate, c->flags, ROUND_DIVIDER_DOWN);
+                div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
+                rate = *prate * mul;
+                rate += div - 1; /* round up */
+                do_div(rate, c->div);
+
+                return rate;
+        }
+        return *prate;
+}
+
+struct clk_ops tegra30_super_ops = {
+        .init = tegra30_super_clk_init,
+        .set_parent = tegra30_super_clk_set_parent,
+        .get_parent = tegra30_super_clk_get_parent,
+        .recalc_rate = tegra30_super_clk_recalc_rate,
+        .round_rate = tegra30_super_clk_round_rate,
+        .set_rate = tegra30_super_clk_set_rate,
 };
 
-static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
 {
-        /* The input value 'rate' is the clock rate of the CPU complex. */
-        c->rate = (rate * c->mul) / c->div;
-        return 0;
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
 }
 
-static struct clk_ops tegra30_twd_ops = {
-        .set_rate       = tegra30_twd_clk_set_rate,
+struct clk_ops tegra30_twd_ops = {
+        .recalc_rate = tegra30_twd_clk_recalc_rate,
 };
 
 /* Blink output functions */
-
-static void tegra30_blink_clk_init(struct clk *c)
+static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
 
         val = pmc_readl(PMC_CTRL);
         c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
-        c->mul = 1;
-        val = pmc_readl(c->reg);
-
-        if (val & PMC_BLINK_TIMER_ENB) {
-                unsigned int on_off;
-
-                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
-                        PMC_BLINK_TIMER_DATA_ON_MASK;
-                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
-                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
-                on_off += val;
-                /* each tick in the blink timer is 4 32KHz clocks */
-                c->div = on_off * 4;
-        } else {
-                c->div = 1;
-        }
+        return c->state;
 }
 
-static int tegra30_blink_clk_enable(struct clk *c)
+static int tegra30_blink_clk_enable(struct clk_hw *hw)
 {
         u32 val;
 
@@ -765,7 +816,7 @@ static int tegra30_blink_clk_enable(struct clk *c)
         return 0;
 }
 
-static void tegra30_blink_clk_disable(struct clk *c)
+static void tegra30_blink_clk_disable(struct clk_hw *hw)
 {
         u32 val;
 
@@ -776,9 +827,11 @@ static void tegra30_blink_clk_disable(struct clk *c)
         pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
 }
 
-static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
-        unsigned long parent_rate = clk_get_rate(c->parent);
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         if (rate >= parent_rate) {
                 c->div = 1;
                 pmc_writel(0, c->reg);
@@ -801,41 +854,77 @@ static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
         return 0;
 }
 
-static struct clk_ops tegra_blink_clk_ops = {
-        .init                   = &tegra30_blink_clk_init,
-        .enable                 = &tegra30_blink_clk_enable,
-        .disable                = &tegra30_blink_clk_disable,
-        .set_rate               = &tegra30_blink_clk_set_rate,
-};
+static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        u32 val;
+        u32 mul;
+        u32 div;
+        u32 on_off;
 
-/* PLL Functions */
-static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg,
-                                         u32 lock_bit)
+        mul = 1;
+        val = pmc_readl(c->reg);
+
+        if (val & PMC_BLINK_TIMER_ENB) {
+                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+                        PMC_BLINK_TIMER_DATA_ON_MASK;
+                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off += val;
+                /* each tick in the blink timer is 4 32KHz clocks */
+                div = on_off * 4;
+        } else {
+                div = 1;
+        }
+
+        if (mul != 0 && div != 0) {
+                rate *= mul;
+                rate += div - 1; /* round up */
+                do_div(rate, div);
+        }
+        return rate;
+}
+
+static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
 {
-#if USE_PLL_LOCK_BITS
-        int i;
-        for (i = 0; i < c->u.pll.lock_delay; i++) {
-                if (clk_readl(lock_reg) & lock_bit) {
-                        udelay(PLL_POST_LOCK_DELAY);
-                        return 0;
-                }
-                udelay(2);              /* timeout = 2 * lock time */
+        int div;
+        int mul;
+        long round_rate = *prate;
+
+        mul = 1;
+
+        if (rate >= *prate) {
+                div = 1;
+        } else {
+                div = DIV_ROUND_UP(*prate / 8, rate);
+                div *= 8;
         }
-        pr_err("Timed out waiting for lock bit on pll %s", c->name);
-        return -1;
-#endif
-        udelay(c->u.pll.lock_delay);
 
-        return 0;
+        round_rate *= mul;
+        round_rate += div - 1;
+        do_div(round_rate, div);
+
+        return round_rate;
 }
 
+struct clk_ops tegra30_blink_clk_ops = {
+        .is_enabled = tegra30_blink_clk_is_enabled,
+        .enable = tegra30_blink_clk_enable,
+        .disable = tegra30_blink_clk_disable,
+        .recalc_rate = tegra30_blink_clk_recalc_rate,
+        .round_rate = tegra30_blink_clk_round_rate,
+        .set_rate = tegra30_blink_clk_set_rate,
+};
 
-static void tegra30_utmi_param_configure(struct clk *c)
+static void tegra30_utmi_param_configure(struct clk_hw *hw)
 {
+        unsigned long main_rate =
+                __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
         u32 reg;
         int i;
-        unsigned long main_rate =
-                clk_get_rate(c->parent->parent);
 
         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
                 if (main_rate == utmi_parameters[i].osc_frequency)
@@ -886,50 +975,52 @@ static void tegra30_utmi_param_configure(struct clk *c)
         clk_writel(reg, UTMIP_PLL_CFG1);
 }
 
-static void tegra30_pll_clk_init(struct clk *c)
+/* PLL Functions */
+static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
+                                         u32 lock_bit)
+{
+        int ret = 0;
+
+#if USE_PLL_LOCK_BITS
+        int i;
+        for (i = 0; i < c->u.pll.lock_delay; i++) {
+                if (clk_readl(lock_reg) & lock_bit) {
+                        udelay(PLL_POST_LOCK_DELAY);
+                        return 0;
+                }
+                udelay(2);      /* timeout = 2 * lock time */
+        }
+        pr_err("Timed out waiting for lock bit on pll %s",
+                                        __clk_get_name(hw->clk));
+        ret = -1;
+#else
+        udelay(c->u.pll.lock_delay);
+#endif
+        return ret;
+}
+
+static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = clk_readl(c->reg + PLL_BASE);
 
         c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+        return c->state;
+}
 
-        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
-                const struct clk_pll_freq_table *sel;
-                unsigned long input_rate = clk_get_rate(c->parent);
-                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
-                        if (sel->input_rate == input_rate &&
-                                sel->output_rate == c->u.pll.fixed_rate) {
-                                c->mul = sel->n;
-                                c->div = sel->m * sel->p;
-                                return;
-                        }
-                }
-                pr_err("Clock %s has unknown fixed frequency\n", c->name);
-                BUG();
-        } else if (val & PLL_BASE_BYPASS) {
-                c->mul = 1;
-                c->div = 1;
-        } else {
-                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
-                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
-                if (c->flags & PLLU)
-                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
-                else
-                        c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
-                                        PLL_BASE_DIVP_SHIFT));
-                if (c->flags & PLL_FIXED) {
-                        unsigned long rate = clk_get_rate_locked(c);
-                        BUG_ON(rate != c->u.pll.fixed_rate);
-                }
-        }
+static void tegra30_pll_clk_init(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
 
         if (c->flags & PLLU)
-                tegra30_utmi_param_configure(c);
+                tegra30_utmi_param_configure(hw);
 }
 
-static int tegra30_pll_clk_enable(struct clk *c)
+static int tegra30_pll_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
 #if USE_PLL_LOCK_BITS
         val = clk_readl(c->reg + PLL_MISC(c));
@@ -952,10 +1043,11 @@ static int tegra30_pll_clk_enable(struct clk *c)
         return 0;
 }
 
-static void tegra30_pll_clk_disable(struct clk *c)
+static void tegra30_pll_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
 
         val = clk_readl(c->reg);
         val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
@@ -968,36 +1060,36 @@ static void tegra30_pll_clk_disable(struct clk *c)
         }
 }
 
-static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val, p_div, old_base;
         unsigned long input_rate;
         const struct clk_pll_freq_table *sel;
         struct clk_pll_freq_table cfg;
 
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
         if (c->flags & PLL_FIXED) {
                 int ret = 0;
                 if (rate != c->u.pll.fixed_rate) {
                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
-                               __func__, c->name, c->u.pll.fixed_rate, rate);
+                               __func__, __clk_get_name(hw->clk),
+                                c->u.pll.fixed_rate, rate);
                         ret = -EINVAL;
                 }
                 return ret;
         }
 
         if (c->flags & PLLM) {
-                if (rate != clk_get_rate_locked(c)) {
+                if (rate != __clk_get_rate(hw->clk)) {
                         pr_err("%s: Can not change memory %s rate in flight\n",
-                               __func__, c->name);
+                                __func__, __clk_get_name(hw->clk));
                         return -EINVAL;
                 }
-                return 0;
         }
 
         p_div = 0;
-        input_rate = clk_get_rate(c->parent);
+        input_rate = parent_rate;
 
         /* Check if the target rate is tabulated */
         for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
@@ -1055,7 +1147,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
                     (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
                     (cfg.output_rate > c->u.pll.vco_max)) {
                         pr_err("%s: Failed to set %s out-of-table rate %lu\n",
-                               __func__, c->name, rate);
+                               __func__, __clk_get_name(hw->clk), rate);
                         return -EINVAL;
                 }
                 p_div <<= PLL_BASE_DIVP_SHIFT;
@@ -1073,7 +1165,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
                 return 0;
 
         if (c->state == ON) {
-                tegra30_pll_clk_disable(c);
+                tegra30_pll_clk_disable(hw);
                 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
         }
         clk_writel(val, c->reg + PLL_BASE);
@@ -1095,21 +1187,149 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
         }
 
         if (c->state == ON)
-                tegra30_pll_clk_enable(c);
+                tegra30_pll_clk_enable(hw);
+
+        c->u.pll.fixed_rate = rate;
 
         return 0;
 }
 
-static struct clk_ops tegra_pll_ops = {
-        .init                   = tegra30_pll_clk_init,
-        .enable                 = tegra30_pll_clk_enable,
-        .disable                = tegra30_pll_clk_disable,
-        .set_rate               = tegra30_pll_clk_set_rate,
+static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long input_rate = *prate;
+        unsigned long output_rate = *prate;
+        const struct clk_pll_freq_table *sel;
+        struct clk_pll_freq_table cfg;
+        int mul;
+        int div;
+        u32 p_div;
+        u32 val;
+
+        if (c->flags & PLL_FIXED)
+                return c->u.pll.fixed_rate;
+
+        if (c->flags & PLLM)
+                return __clk_get_rate(hw->clk);
+
+        p_div = 0;
+        /* Check if the target rate is tabulated */
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        if (c->flags & PLLU) {
+                                BUG_ON(sel->p < 1 || sel->p > 2);
+                                if (sel->p == 1)
+                                        p_div = PLLU_BASE_POST_DIV;
+                        } else {
+                                BUG_ON(sel->p < 1);
+                                for (val = sel->p; val > 1; val >>= 1)
+                                        p_div++;
+                                p_div <<= PLL_BASE_DIVP_SHIFT;
+                        }
+                        break;
+                }
+        }
+
+        if (sel->input_rate == 0) {
+                unsigned long cfreq;
+                BUG_ON(c->flags & PLLU);
+                sel = &cfg;
+
+                switch (input_rate) {
+                case 12000000:
+                case 26000000:
+                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
+                        break;
+                case 13000000:
+                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
+                        break;
+                case 16800000:
+                case 19200000:
+                        cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
+                        break;
+                default:
+                        pr_err("%s: Unexpected reference rate %lu\n",
+                               __func__, input_rate);
+                        BUG();
+                }
+
+                /* Raise VCO to guarantee 0.5% accuracy */
+                for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
+                      cfg.output_rate <<= 1)
+                        p_div++;
+
+                cfg.p = 0x1 << p_div;
+                cfg.m = input_rate / cfreq;
+                cfg.n = cfg.output_rate / cfreq;
+        }
+
+        mul = sel->n;
+        div = sel->m * sel->p;
+
+        output_rate *= mul;
+        output_rate += div - 1; /* round up */
+        do_div(output_rate, div);
+
+        return output_rate;
+}
+
+static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        u32 val = clk_readl(c->reg + PLL_BASE);
+
+        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+                const struct clk_pll_freq_table *sel;
+                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                        if (sel->input_rate == parent_rate &&
+                                sel->output_rate == c->u.pll.fixed_rate) {
+                                c->mul = sel->n;
+                                c->div = sel->m * sel->p;
+                                break;
+                        }
+                }
+                pr_err("Clock %s has unknown fixed frequency\n",
+                                                __clk_get_name(hw->clk));
+                BUG();
+        } else if (val & PLL_BASE_BYPASS) {
+                c->mul = 1;
+                c->div = 1;
+        } else {
+                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+                if (c->flags & PLLU)
+                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+                else
+                        c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
+                                        PLL_BASE_DIVP_SHIFT));
+        }
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
+}
+
+struct clk_ops tegra30_pll_ops = {
+        .is_enabled = tegra30_pll_clk_is_enabled,
+        .init = tegra30_pll_clk_init,
+        .enable = tegra30_pll_clk_enable,
+        .disable = tegra30_pll_clk_disable,
+        .recalc_rate = tegra30_pll_recalc_rate,
+        .round_rate = tegra30_pll_round_rate,
+        .set_rate = tegra30_pll_clk_set_rate,
 };
 
-static int
-tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val, mask, reg;
 
         switch (p) {
@@ -1141,41 +1361,27 @@ tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
         return 0;
 }
 
-static struct clk_ops tegra_plld_ops = {
-        .init                   = tegra30_pll_clk_init,
-        .enable                 = tegra30_pll_clk_enable,
-        .disable                = tegra30_pll_clk_disable,
-        .set_rate               = tegra30_pll_clk_set_rate,
-        .clk_cfg_ex             = tegra30_plld_clk_cfg_ex,
-};
-
-static void tegra30_plle_clk_init(struct clk *c)
+static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
 
-        val = clk_readl(PLLE_AUX);
-        c->parent = (val & PLLE_AUX_PLLP_SEL) ?
-                tegra_get_clock_by_name("pll_p") :
-                tegra_get_clock_by_name("pll_ref");
-
         val = clk_readl(c->reg + PLL_BASE);
         c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
-        c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
-        c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
-        c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+        return c->state;
 }
 
-static void tegra30_plle_clk_disable(struct clk *c)
+static void tegra30_plle_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
 
         val = clk_readl(c->reg + PLL_BASE);
         val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
         clk_writel(val, c->reg + PLL_BASE);
 }
 
-static void tegra30_plle_training(struct clk *c)
+static void tegra30_plle_training(struct clk_tegra *c)
 {
         u32 val;
 
@@ -1198,12 +1404,15 @@ static void tegra30_plle_training(struct clk *c)
         } while (!(val & PLLE_MISC_READY));
 }
 
-static int tegra30_plle_configure(struct clk *c, bool force_training)
+static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
 {
-        u32 val;
+        struct clk_tegra *c = to_clk_tegra(hw);
+        struct clk *parent = __clk_get_parent(hw->clk);
         const struct clk_pll_freq_table *sel;
+        u32 val;
+
         unsigned long rate = c->u.pll.fixed_rate;
-        unsigned long input_rate = clk_get_rate(c->parent);
+        unsigned long input_rate = __clk_get_rate(parent);
 
         for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
                 if (sel->input_rate == input_rate && sel->output_rate == rate)
@@ -1214,7 +1423,7 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
                 return -ENOSYS;
 
         /* disable PLLE, clear setup fiels */
-        tegra30_plle_clk_disable(c);
+        tegra30_plle_clk_disable(hw);
 
         val = clk_readl(c->reg + PLL_MISC(c));
         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
@@ -1252,52 +1461,64 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
         return 0;
 }
 
-static int tegra30_plle_clk_enable(struct clk *c)
+static int tegra30_plle_clk_enable(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+
+        return tegra30_plle_configure(hw, !c->set);
+}
+
+static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
+                        unsigned long parent_rate)
 {
-        pr_debug("%s on clock %s\n", __func__, c->name);
-        return tegra30_plle_configure(c, !c->set);
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long rate = parent_rate;
+        u32 val;
+
+        val = clk_readl(c->reg + PLL_BASE);
+        c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
+        c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
+        c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
 }
 
-static struct clk_ops tegra_plle_ops = {
-        .init                   = tegra30_plle_clk_init,
-        .enable                 = tegra30_plle_clk_enable,
-        .disable                = tegra30_plle_clk_disable,
+struct clk_ops tegra30_plle_ops = {
+        .is_enabled = tegra30_plle_clk_is_enabled,
+        .enable = tegra30_plle_clk_enable,
+        .disable = tegra30_plle_clk_disable,
+        .recalc_rate = tegra30_plle_clk_recalc_rate,
 };
 
 /* Clock divider ops */
-static void tegra30_pll_div_clk_init(struct clk *c)
+static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         if (c->flags & DIV_U71) {
-                u32 divu71;
                 u32 val = clk_readl(c->reg);
                 val >>= c->reg_shift;
                 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
                 if (!(val & PLL_OUT_RESET_DISABLE))
                         c->state = OFF;
-
-                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
-                c->div = (divu71 + 2);
-                c->mul = 2;
-        } else if (c->flags & DIV_2) {
-                c->state = ON;
-                if (c->flags & (PLLD | PLLX)) {
-                        c->div = 2;
-                        c->mul = 1;
-                } else
-                        BUG();
         } else {
                 c->state = ON;
-                c->div = 1;
-                c->mul = 1;
         }
+        return c->state;
 }
 
-static int tegra30_pll_div_clk_enable(struct clk *c)
+static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         u32 new_val;
 
-        pr_debug("%s: %s\n", __func__, c->name);
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
         if (c->flags & DIV_U71) {
                 val = clk_readl(c->reg);
                 new_val = val >> c->reg_shift;
@@ -1315,12 +1536,13 @@ static int tegra30_pll_div_clk_enable(struct clk *c)
         return -EINVAL;
 }
 
-static void tegra30_pll_div_clk_disable(struct clk *c)
+static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         u32 new_val;
 
-        pr_debug("%s: %s\n", __func__, c->name);
+        pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
         if (c->flags & DIV_U71) {
                 val = clk_readl(c->reg);
                 new_val = val >> c->reg_shift;
@@ -1334,14 +1556,14 @@ static void tegra30_pll_div_clk_disable(struct clk *c)
         }
 }
 
-static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         u32 new_val;
         int divider_u71;
-        unsigned long parent_rate = clk_get_rate(c->parent);
 
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
         if (c->flags & DIV_U71) {
                 divider_u71 = clk_div71_get_divider(
                         parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
@@ -1359,19 +1581,59 @@ static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
                         clk_writel_delay(val, c->reg);
                         c->div = divider_u71 + 2;
                         c->mul = 2;
+                        c->fixed_rate = rate;
                         return 0;
                 }
-        } else if (c->flags & DIV_2)
-                return clk_set_rate(c->parent, rate * 2);
+        } else if (c->flags & DIV_2) {
+                c->fixed_rate = rate;
+                return 0;
+        }
 
         return -EINVAL;
 }
 
-static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+
+        if (c->flags & DIV_U71) {
+                u32 divu71;
+                u32 val = clk_readl(c->reg);
+                val >>= c->reg_shift;
+
+                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+                c->div = (divu71 + 2);
+                c->mul = 2;
+        } else if (c->flags & DIV_2) {
+                if (c->flags & (PLLD | PLLX)) {
+                        c->div = 2;
+                        c->mul = 1;
+                } else
+                        BUG();
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
+}
+
+static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
+                                unsigned long rate, unsigned long *prate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
         int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (prate)
+                parent_rate = *prate;
 
         if (c->flags & DIV_U71) {
                 divider = clk_div71_get_divider(
@@ -1379,23 +1641,25 @@ static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
                 if (divider < 0)
                         return divider;
                 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
-        } else if (c->flags & DIV_2)
-                /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
+        } else if (c->flags & DIV_2) {
+                *prate = rate * 2;
                 return rate;
+        }
 
         return -EINVAL;
 }
 
-static struct clk_ops tegra_pll_div_ops = {
-        .init                   = tegra30_pll_div_clk_init,
-        .enable                 = tegra30_pll_div_clk_enable,
-        .disable                = tegra30_pll_div_clk_disable,
-        .set_rate               = tegra30_pll_div_clk_set_rate,
-        .round_rate             = tegra30_pll_div_clk_round_rate,
+struct clk_ops tegra30_pll_div_ops = {
+        .is_enabled = tegra30_pll_div_clk_is_enabled,
+        .enable = tegra30_pll_div_clk_enable,
+        .disable = tegra30_pll_div_clk_disable,
+        .set_rate = tegra30_pll_div_clk_set_rate,
+        .recalc_rate = tegra30_pll_div_clk_recalc_rate,
+        .round_rate = tegra30_pll_div_clk_round_rate,
 };
 
 /* Periph clk ops */
-static inline u32 periph_clk_source_mask(struct clk *c)
+static inline u32 periph_clk_source_mask(struct clk_tegra *c)
 {
         if (c->flags & MUX8)
                 return 7 << 29;
@@ -1409,7 +1673,7 @@ static inline u32 periph_clk_source_mask(struct clk *c)
                 return 3 << 30;
 }
 
-static inline u32 periph_clk_source_shift(struct clk *c)
+static inline u32 periph_clk_source_shift(struct clk_tegra *c)
 {
         if (c->flags & MUX8)
                 return 29;
@@ -1423,47 +1687,9 @@ static inline u32 periph_clk_source_shift(struct clk *c)
                 return 30;
 }
 
-static void tegra30_periph_clk_init(struct clk *c)
+static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
 {
-        u32 val = clk_readl(c->reg);
-        const struct clk_mux_sel *mux = 0;
-        const struct clk_mux_sel *sel;
-        if (c->flags & MUX) {
-                for (sel = c->inputs; sel->input != NULL; sel++) {
-                        if (((val & periph_clk_source_mask(c)) >>
-                            periph_clk_source_shift(c)) == sel->value)
-                                mux = sel;
-                }
-                BUG_ON(!mux);
-
-                c->parent = mux->input;
-        } else {
-                c->parent = c->inputs[0].input;
-        }
-
-        if (c->flags & DIV_U71) {
-                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
-                if ((c->flags & DIV_U71_UART) &&
-                    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
-                        divu71 = 0;
-                }
-                if (c->flags & DIV_U71_IDLE) {
-                        val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
-                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
-                        val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
-                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
-                        clk_writel(val, c->reg);
-                }
-                c->div = divu71 + 2;
-                c->mul = 2;
-        } else if (c->flags & DIV_U16) {
-                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
-                c->div = divu16 + 1;
-                c->mul = 1;
-        } else {
-                c->div = 1;
-                c->mul = 1;
-        }
+        struct clk_tegra *c = to_clk_tegra(hw);
 
         c->state = ON;
         if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
@@ -1471,11 +1697,12 @@ static void tegra30_periph_clk_init(struct clk *c)
         if (!(c->flags & PERIPH_NO_RESET))
                 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
                         c->state = OFF;
+        return c->state;
 }
 
-static int tegra30_periph_clk_enable(struct clk *c)
+static int tegra30_periph_clk_enable(struct clk_hw *hw)
 {
-        pr_debug("%s on clock %s\n", __func__, c->name);
+        struct clk_tegra *c = to_clk_tegra(hw);
 
         tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
         if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
@@ -1494,31 +1721,29 @@ static int tegra30_periph_clk_enable(struct clk *c)
         return 0;
 }
 
-static void tegra30_periph_clk_disable(struct clk *c)
+static void tegra30_periph_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         unsigned long val;
-        pr_debug("%s on clock %s\n", __func__, c->name);
 
-        if (c->refcnt)
-                tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
+                return;
 
-        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
-                /* If peripheral is in the APB bus then read the APB bus to
-                 * flush the write operation in apb bus. This will avoid the
-                 * peripheral access after disabling clock*/
-                if (c->flags & PERIPH_ON_APB)
-                        val = chipid_readl();
+        /* If peripheral is in the APB bus then read the APB bus to
+         * flush the write operation in apb bus. This will avoid the
+         * peripheral access after disabling clock*/
+        if (c->flags & PERIPH_ON_APB)
+                val = chipid_readl();
 
-                clk_writel_delay(
-                        PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
-        }
+        clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
 }
 
-static void tegra30_periph_clk_reset(struct clk *c, bool assert)
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         unsigned long val;
-        pr_debug("%s %s on clock %s\n", __func__,
-                 assert ? "assert" : "deassert", c->name);
 
         if (!(c->flags & PERIPH_NO_RESET)) {
                 if (assert) {
@@ -1537,42 +1762,40 @@ static void tegra30_periph_clk_reset(struct clk *c, bool assert)
         }
 }
 
-static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        const struct clk_mux_sel *sel;
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
 
         if (!(c->flags & MUX))
-                return (p == c->parent) ? 0 : (-EINVAL);
-
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~periph_clk_source_mask(c);
-                        val |= (sel->value << periph_clk_source_shift(c));
-
-                        if (c->refcnt)
-                                clk_enable(p);
+                return (index == 0) ? 0 : (-EINVAL);
 
-                        clk_writel_delay(val, c->reg);
+        val = clk_readl(c->reg);
+        val &= ~periph_clk_source_mask(c);
+        val |= (index << periph_clk_source_shift(c));
+        clk_writel_delay(val, c->reg);
+        return 0;
+}
 
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
+static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        int source  = (val & periph_clk_source_mask(c)) >>
+                                        periph_clk_source_shift(c);
 
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
+        if (!(c->flags & MUX))
+                return 0;
 
-        return -EINVAL;
+        return source;
 }
 
-static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
 
         if (c->flags & DIV_U71) {
                 divider = clk_div71_get_divider(
@@ -1611,12 +1834,15 @@ static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
         return -EINVAL;
 }
 
-static long tegra30_periph_clk_round_rate(struct clk *c,
-        unsigned long rate)
+static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+        unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
         int divider;
-        unsigned long parent_rate = clk_get_rate(c->parent);
-        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (prate)
+                parent_rate = *prate;
 
         if (c->flags & DIV_U71) {
                 divider = clk_div71_get_divider(
@@ -1634,21 +1860,85 @@ static long tegra30_periph_clk_round_rate(struct clk *c,
         return -EINVAL;
 }
 
-static struct clk_ops tegra_periph_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
+static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
+        u32 val = clk_readl(c->reg);
+
+        if (c->flags & DIV_U71) {
+                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+                if ((c->flags & DIV_U71_UART) &&
+                    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
+                        divu71 = 0;
+                }
+                if (c->flags & DIV_U71_IDLE) {
+                        val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
+                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+                        val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
+                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+                        clk_writel(val, c->reg);
+                }
+                c->div = divu71 + 2;
+                c->mul = 2;
+        } else if (c->flags & DIV_U16) {
+                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+                c->div = divu16 + 1;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+        return rate;
+}
+
+struct clk_ops tegra30_periph_clk_ops = {
+        .is_enabled = tegra30_periph_clk_is_enabled,
+        .enable = tegra30_periph_clk_enable,
+        .disable = tegra30_periph_clk_disable,
+        .set_parent = tegra30_periph_clk_set_parent,
+        .get_parent = tegra30_periph_clk_get_parent,
+        .set_rate = tegra30_periph_clk_set_rate,
+        .round_rate = tegra30_periph_clk_round_rate,
+        .recalc_rate = tegra30_periph_clk_recalc_rate,
+};
+
+static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk *d = clk_get_sys(NULL, "pll_d");
+        /* The DSIB parent selection bit is in PLLD base
+           register - can not do direct r-m-w, must be
+           protected by PLLD lock */
+        tegra_clk_cfg_ex(
+                d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
+
+        return 0;
+}
+
+struct clk_ops tegra30_dsib_clk_ops = {
+        .is_enabled = tegra30_periph_clk_is_enabled,
         .enable                 = &tegra30_periph_clk_enable,
         .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_parent             = &tegra30_dsib_clk_set_parent,
+        .get_parent             = &tegra30_periph_clk_get_parent,
         .set_rate               = &tegra30_periph_clk_set_rate,
         .round_rate             = &tegra30_periph_clk_round_rate,
-        .reset                  = &tegra30_periph_clk_reset,
+        .recalc_rate            = &tegra30_periph_clk_recalc_rate,
 };
 
-
 /* Periph extended clock configuration ops */
-static int
-tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         if (p == TEGRA_CLK_VI_INP_SEL) {
                 u32 val = clk_readl(c->reg);
                 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
@@ -1660,20 +1950,11 @@ tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
         return -EINVAL;
 }
 
-static struct clk_ops tegra_vi_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .clk_cfg_ex             = &tegra30_vi_clk_cfg_ex,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-
-static int
-tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
                 u32 val = clk_readl(c->reg);
                 if (setting)
@@ -1686,21 +1967,11 @@ tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
         return -EINVAL;
 }
 
-static struct clk_ops tegra_nand_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .clk_cfg_ex             = &tegra30_nand_clk_cfg_ex,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-
-
-static int
-tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         if (p == TEGRA_CLK_DTV_INVERT) {
                 u32 val = clk_readl(c->reg);
                 if (setting)
@@ -1713,91 +1984,27 @@ tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
         return -EINVAL;
 }
 
-static struct clk_ops tegra_dtv_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_periph_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .clk_cfg_ex             = &tegra30_dtv_clk_cfg_ex,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-
-static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
-{
-        const struct clk_mux_sel *sel;
-        struct clk *d = tegra_get_clock_by_name("pll_d");
-
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        if (c->refcnt)
-                                clk_enable(p);
-
-                        /* The DSIB parent selection bit is in PLLD base
-                           register - can not do direct r-m-w, must be
-                           protected by PLLD lock */
-                        tegra_clk_cfg_ex(
-                                d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
-
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
-
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-
-        return -EINVAL;
-}
-
-static struct clk_ops tegra_dsib_clk_ops = {
-        .init                   = &tegra30_periph_clk_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_parent             = &tegra30_dsib_clk_set_parent,
-        .set_rate               = &tegra30_periph_clk_set_rate,
-        .round_rate             = &tegra30_periph_clk_round_rate,
-        .reset                  = &tegra30_periph_clk_reset,
-};
-
-/* pciex clock support only reset function */
-static struct clk_ops tegra_pciex_clk_ops = {
-        .reset    = tegra30_periph_clk_reset,
-};
-
 /* Output clock ops */
 
 static DEFINE_SPINLOCK(clk_out_lock);
 
-static void tegra30_clk_out_init(struct clk *c)
+static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
 {
-        const struct clk_mux_sel *mux = 0;
-        const struct clk_mux_sel *sel;
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = pmc_readl(c->reg);
 
         c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
         c->mul = 1;
         c->div = 1;
-
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (((val & periph_clk_source_mask(c)) >>
-                     periph_clk_source_shift(c)) == sel->value)
-                        mux = sel;
-        }
-        BUG_ON(!mux);
-        c->parent = mux->input;
+        return c->state;
 }
 
-static int tegra30_clk_out_enable(struct clk *c)
+static int tegra30_clk_out_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         unsigned long flags;
 
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
         spin_lock_irqsave(&clk_out_lock, flags);
         val = pmc_readl(c->reg);
         val |= (0x1 << c->u.periph.clk_num);
@@ -1807,13 +2014,12 @@ static int tegra30_clk_out_enable(struct clk *c)
         return 0;
 }
 
-static void tegra30_clk_out_disable(struct clk *c)
+static void tegra30_clk_out_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         unsigned long flags;
 
-        pr_debug("%s on clock %s\n", __func__, c->name);
-
         spin_lock_irqsave(&clk_out_lock, flags);
         val = pmc_readl(c->reg);
         val &= ~(0x1 << c->u.periph.clk_num);
@@ -1821,59 +2027,59 @@ static void tegra30_clk_out_disable(struct clk *c)
         spin_unlock_irqrestore(&clk_out_lock, flags);
 }
 
-static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p)
+static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
         unsigned long flags;
-        const struct clk_mux_sel *sel;
 
-        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        if (c->refcnt)
-                                clk_enable(p);
+        spin_lock_irqsave(&clk_out_lock, flags);
+        val = pmc_readl(c->reg);
+        val &= ~periph_clk_source_mask(c);
+        val |= (index << periph_clk_source_shift(c));
+        pmc_writel(val, c->reg);
+        spin_unlock_irqrestore(&clk_out_lock, flags);
 
-                        spin_lock_irqsave(&clk_out_lock, flags);
-                        val = pmc_readl(c->reg);
-                        val &= ~periph_clk_source_mask(c);
-                        val |= (sel->value << periph_clk_source_shift(c));
-                        pmc_writel(val, c->reg);
-                        spin_unlock_irqrestore(&clk_out_lock, flags);
+        return 0;
+}
 
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
+static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = pmc_readl(c->reg);
+        int source;
 
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
-        return -EINVAL;
+        source = (val & periph_clk_source_mask(c)) >>
+                                periph_clk_source_shift(c);
+        return source;
 }
 
-static struct clk_ops tegra_clk_out_ops = {
-        .init                   = &tegra30_clk_out_init,
-        .enable                 = &tegra30_clk_out_enable,
-        .disable                = &tegra30_clk_out_disable,
-        .set_parent             = &tegra30_clk_out_set_parent,
+struct clk_ops tegra_clk_out_ops = {
+        .is_enabled = tegra30_clk_out_is_enabled,
+        .enable = tegra30_clk_out_enable,
+        .disable = tegra30_clk_out_disable,
+        .set_parent = tegra30_clk_out_set_parent,
+        .get_parent = tegra30_clk_out_get_parent,
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
-
 /* Clock doubler ops */
-static void tegra30_clk_double_init(struct clk *c)
+static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
 {
-        u32 val = clk_readl(c->reg);
-        c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
-        c->div = 1;
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         c->state = ON;
         if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
                 c->state = OFF;
+        return c->state;
 };
 
-static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        unsigned long parent_rate = clk_get_rate(c->parent);
+
         if (rate == parent_rate) {
                 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
                 clk_writel(val, c->reg);
@@ -1890,1215 +2096,200 @@ static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
         return -EINVAL;
 }
 
-static struct clk_ops tegra_clk_double_ops = {
-        .init                   = &tegra30_clk_double_init,
-        .enable                 = &tegra30_periph_clk_enable,
-        .disable                = &tegra30_periph_clk_disable,
-        .set_rate               = &tegra30_clk_double_set_rate,
-};
+static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u64 rate = parent_rate;
 
-/* Audio sync clock ops */
-static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate)
+        u32 val = clk_readl(c->reg);
+        c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
+        c->div = 1;
+
+        if (c->mul != 0 && c->div != 0) {
+                rate *= c->mul;
+                rate += c->div - 1; /* round up */
+                do_div(rate, c->div);
+        }
+
+        return rate;
+}
+
+static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
 {
-        c->rate = rate;
-        return 0;
+        unsigned long output_rate = *prate;
+
+        do_div(output_rate, 2);
+        return output_rate;
 }
 
-static struct clk_ops tegra_sync_source_ops = {
-        .set_rate               = &tegra30_sync_source_set_rate,
+struct clk_ops tegra30_clk_double_ops = {
+        .is_enabled = tegra30_clk_double_is_enabled,
+        .enable = tegra30_periph_clk_enable,
+        .disable = tegra30_periph_clk_disable,
+        .recalc_rate = tegra30_clk_double_recalc_rate,
+        .round_rate = tegra30_clk_double_round_rate,
+        .set_rate = tegra30_clk_double_set_rate,
+};
+
+/* Audio sync clock ops */
+struct clk_ops tegra_sync_source_ops = {
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
-static void tegra30_audio_sync_clk_init(struct clk *c)
+static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
 {
-        int source;
-        const struct clk_mux_sel *sel;
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = clk_readl(c->reg);
         c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
-        source = val & AUDIO_SYNC_SOURCE_MASK;
-        for (sel = c->inputs; sel->input != NULL; sel++)
-                if (sel->value == source)
-                        break;
-        BUG_ON(sel->input == NULL);
-        c->parent = sel->input;
+        return c->state;
 }
 
-static int tegra30_audio_sync_clk_enable(struct clk *c)
+static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = clk_readl(c->reg);
         clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
         return 0;
 }
 
-static void tegra30_audio_sync_clk_disable(struct clk *c)
+static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = clk_readl(c->reg);
         clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
 }
 
-static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val;
-        const struct clk_mux_sel *sel;
-        for (sel = c->inputs; sel->input != NULL; sel++) {
-                if (sel->input == p) {
-                        val = clk_readl(c->reg);
-                        val &= ~AUDIO_SYNC_SOURCE_MASK;
-                        val |= sel->value;
-
-                        if (c->refcnt)
-                                clk_enable(p);
 
-                        clk_writel(val, c->reg);
+        val = clk_readl(c->reg);
+        val &= ~AUDIO_SYNC_SOURCE_MASK;
+        val |= index;
 
-                        if (c->refcnt && c->parent)
-                                clk_disable(c->parent);
+        clk_writel(val, c->reg);
+        return 0;
+}
 
-                        clk_reparent(c, p);
-                        return 0;
-                }
-        }
+static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
+{
+        struct clk_tegra *c = to_clk_tegra(hw);
+        u32 val = clk_readl(c->reg);
+        int source;
 
-        return -EINVAL;
+        source = val & AUDIO_SYNC_SOURCE_MASK;
+        return source;
 }
 
-static struct clk_ops tegra_audio_sync_clk_ops = {
-        .init       = tegra30_audio_sync_clk_init,
-        .enable     = tegra30_audio_sync_clk_enable,
-        .disable    = tegra30_audio_sync_clk_disable,
+struct clk_ops tegra30_audio_sync_clk_ops = {
+        .is_enabled = tegra30_audio_sync_clk_is_enabled,
+        .enable = tegra30_audio_sync_clk_enable,
+        .disable = tegra30_audio_sync_clk_disable,
         .set_parent = tegra30_audio_sync_clk_set_parent,
+        .get_parent = tegra30_audio_sync_clk_get_parent,
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
 /* cml0 (pcie), and cml1 (sata) clock ops */
-static void tegra30_cml_clk_init(struct clk *c)
+static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
         u32 val = clk_readl(c->reg);
         c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
+        return c->state;
 }
 
-static int tegra30_cml_clk_enable(struct clk *c)
+static int tegra30_cml_clk_enable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         u32 val = clk_readl(c->reg);
         val |= (0x1 << c->u.periph.clk_num);
         clk_writel(val, c->reg);
+
         return 0;
 }
 
-static void tegra30_cml_clk_disable(struct clk *c)
+static void tegra30_cml_clk_disable(struct clk_hw *hw)
 {
+        struct clk_tegra *c = to_clk_tegra(hw);
+
         u32 val = clk_readl(c->reg);
         val &= ~(0x1 << c->u.periph.clk_num);
         clk_writel(val, c->reg);
 }
 
-static struct clk_ops tegra_cml_clk_ops = {
-        .init                   = &tegra30_cml_clk_init,
-        .enable                 = &tegra30_cml_clk_enable,
-        .disable                = &tegra30_cml_clk_disable,
-};
-
-/* Clock definitions */
-static struct clk tegra_clk_32k = {
-        .name = "clk_32k",
-        .rate = 32768,
-        .ops  = NULL,
-        .max_rate = 32768,
-};
-
-static struct clk tegra_clk_m = {
-        .name      = "clk_m",
-        .flags     = ENABLE_ON_INIT,
-        .ops       = &tegra_clk_m_ops,
-        .reg       = 0x1fc,
-        .reg_shift = 28,
-        .max_rate  = 48000000,
-};
-
-static struct clk tegra_clk_m_div2 = {
-        .name      = "clk_m_div2",
-        .ops       = &tegra_clk_m_div_ops,
-        .parent    = &tegra_clk_m,
-        .mul       = 1,
-        .div       = 2,
-        .state     = ON,
-        .max_rate  = 24000000,
-};
-
-static struct clk tegra_clk_m_div4 = {
-        .name      = "clk_m_div4",
-        .ops       = &tegra_clk_m_div_ops,
-        .parent    = &tegra_clk_m,
-        .mul       = 1,
-        .div       = 4,
-        .state     = ON,
-        .max_rate  = 12000000,
-};
-
-static struct clk tegra_pll_ref = {
-        .name      = "pll_ref",
-        .flags     = ENABLE_ON_INIT,
-        .ops       = &tegra_pll_ref_ops,
-        .parent    = &tegra_clk_m,
-        .max_rate  = 26000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
-        { 12000000, 1040000000, 520,  6, 1, 8},
-        { 13000000, 1040000000, 480,  6, 1, 8},
-        { 16800000, 1040000000, 495,  8, 1, 8},         /* actual: 1039.5 MHz */
-        { 19200000, 1040000000, 325,  6, 1, 6},
-        { 26000000, 1040000000, 520, 13, 1, 8},
-
-        { 12000000, 832000000, 416,  6, 1, 8},
-        { 13000000, 832000000, 832, 13, 1, 8},
-        { 16800000, 832000000, 396,  8, 1, 8},          /* actual: 831.6 MHz */
-        { 19200000, 832000000, 260,  6, 1, 8},
-        { 26000000, 832000000, 416, 13, 1, 8},
-
-        { 12000000, 624000000, 624, 12, 1, 8},
-        { 13000000, 624000000, 624, 13, 1, 8},
-        { 16800000, 600000000, 520, 14, 1, 8},
-        { 19200000, 624000000, 520, 16, 1, 8},
-        { 26000000, 624000000, 624, 26, 1, 8},
-
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-
-        { 12000000, 520000000, 520, 12, 1, 8},
-        { 13000000, 520000000, 520, 13, 1, 8},
-        { 16800000, 520000000, 495, 16, 1, 8},          /* actual: 519.75 MHz */
-        { 19200000, 520000000, 325, 12, 1, 6},
-        { 26000000, 520000000, 520, 26, 1, 8},
-
-        { 12000000, 416000000, 416, 12, 1, 8},
-        { 13000000, 416000000, 416, 13, 1, 8},
-        { 16800000, 416000000, 396, 16, 1, 8},          /* actual: 415.8 MHz */
-        { 19200000, 416000000, 260, 12, 1, 6},
-        { 26000000, 416000000, 416, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_c = {
-        .name      = "pll_c",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x80,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1400000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_c_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_c_out1 = {
-        .name      = "pll_c_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_c,
-        .reg       = 0x84,
-        .reg_shift = 0,
-        .max_rate  = 700000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
-        { 12000000, 666000000, 666, 12, 1, 8},
-        { 13000000, 666000000, 666, 13, 1, 8},
-        { 16800000, 666000000, 555, 14, 1, 8},
-        { 19200000, 666000000, 555, 16, 1, 8},
-        { 26000000, 666000000, 666, 26, 1, 8},
-        { 12000000, 600000000, 600, 12, 1, 8},
-        { 13000000, 600000000, 600, 13, 1, 8},
-        { 16800000, 600000000, 500, 14, 1, 8},
-        { 19200000, 600000000, 375, 12, 1, 6},
-        { 26000000, 600000000, 600, 26, 1, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_m = {
-        .name      = "pll_m",
-        .flags     = PLL_HAS_CPCON | PLLM,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0x90,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 800000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1200000000,
-                .freq_table = tegra_pll_m_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_m_out1 = {
-        .name      = "pll_m_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_m,
-        .reg       = 0x94,
-        .reg_shift = 0,
-        .max_rate  = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
-        { 12000000, 216000000, 432, 12, 2, 8},
-        { 13000000, 216000000, 432, 13, 2, 8},
-        { 16800000, 216000000, 360, 14, 2, 8},
-        { 19200000, 216000000, 360, 16, 2, 8},
-        { 26000000, 216000000, 432, 26, 2, 8},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_p = {
-        .name      = "pll_p",
-        .flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xa0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 432000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_p_freq_table,
-                .lock_delay = 300,
-                .fixed_rate = 408000000,
-        },
-};
-
-static struct clk tegra_pll_p_out1 = {
-        .name      = "pll_p_out1",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
-        .name      = "pll_p_out2",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa4,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out3 = {
-        .name      = "pll_p_out3",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 0,
-        .max_rate  = 432000000,
-};
-
-static struct clk tegra_pll_p_out4 = {
-        .name      = "pll_p_out4",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
-        .parent    = &tegra_pll_p,
-        .reg       = 0xa8,
-        .reg_shift = 16,
-        .max_rate  = 432000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
-        { 9600000, 564480000, 294, 5, 1, 4},
-        { 9600000, 552960000, 288, 5, 1, 4},
-        { 9600000, 24000000,  5,   2, 1, 1},
-
-        { 28800000, 56448000, 49, 25, 1, 1},
-        { 28800000, 73728000, 64, 25, 1, 1},
-        { 28800000, 24000000,  5,  6, 1, 1},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_a = {
-        .name      = "pll_a",
-        .flags     = PLL_HAS_CPCON,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xb0,
-        .parent    = &tegra_pll_p_out1,
-        .max_rate  = 700000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1400000000,
-                .freq_table = tegra_pll_a_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_a_out0 = {
-        .name      = "pll_a_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_U71,
-        .parent    = &tegra_pll_a,
-        .reg       = 0xb4,
-        .reg_shift = 0,
-        .max_rate  = 100000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
-        { 12000000, 216000000, 216, 12, 1, 4},
-        { 13000000, 216000000, 216, 13, 1, 4},
-        { 16800000, 216000000, 180, 14, 1, 4},
-        { 19200000, 216000000, 180, 16, 1, 4},
-        { 26000000, 216000000, 216, 26, 1, 4},
-
-        { 12000000, 594000000, 594, 12, 1, 8},
-        { 13000000, 594000000, 594, 13, 1, 8},
-        { 16800000, 594000000, 495, 14, 1, 8},
-        { 19200000, 594000000, 495, 16, 1, 8},
-        { 26000000, 594000000, 594, 26, 1, 8},
-
-        { 12000000, 1000000000, 1000, 12, 1, 12},
-        { 13000000, 1000000000, 1000, 13, 1, 12},
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 12},
-
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_d = {
-        .name      = "pll_d",
-        .flags     = PLL_HAS_CPCON | PLLD,
-        .ops       = &tegra_plld_ops,
-        .reg       = 0xd0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 40000000,
-                .vco_max   = 1000000000,
-                .freq_table = tegra_pll_d_freq_table,
-                .lock_delay = 1000,
-        },
-};
-
-static struct clk tegra_pll_d_out0 = {
-        .name      = "pll_d_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLD,
-        .parent    = &tegra_pll_d,
-        .max_rate  = 500000000,
-};
-
-static struct clk tegra_pll_d2 = {
-        .name      = "pll_d2",
-        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
-        .ops       = &tegra_plld_ops,
-        .reg       = 0x4b8,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1000000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 40000000,
-                .vco_max   = 1000000000,
-                .freq_table = tegra_pll_d_freq_table,
-                .lock_delay = 1000,
-        },
-};
-
-static struct clk tegra_pll_d2_out0 = {
-        .name      = "pll_d2_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLD,
-        .parent    = &tegra_pll_d2,
-        .max_rate  = 500000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
-        { 12000000, 480000000, 960, 12, 2, 12},
-        { 13000000, 480000000, 960, 13, 2, 12},
-        { 16800000, 480000000, 400, 7,  2, 5},
-        { 19200000, 480000000, 200, 4,  2, 3},
-        { 26000000, 480000000, 960, 26, 2, 12},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_u = {
-        .name      = "pll_u",
-        .flags     = PLL_HAS_CPCON | PLLU,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xc0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 480000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 40000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 480000000,
-                .vco_max   = 960000000,
-                .freq_table = tegra_pll_u_freq_table,
-                .lock_delay = 1000,
-        },
-};
-
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
-        /* 1.7 GHz */
-        { 12000000, 1700000000, 850,  6,  1, 8},
-        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
-        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
-        { 26000000, 1700000000, 850,  13, 1, 8},
-
-        /* 1.6 GHz */
-        { 12000000, 1600000000, 800,  6,  1, 8},
-        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
-        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
-        { 19200000, 1600000000, 500,  6,  1, 8},
-        { 26000000, 1600000000, 800,  13, 1, 8},
-
-        /* 1.5 GHz */
-        { 12000000, 1500000000, 750,  6,  1, 8},
-        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
-        { 16800000, 1500000000, 625,  7,  1, 8},
-        { 19200000, 1500000000, 625,  8,  1, 8},
-        { 26000000, 1500000000, 750,  13, 1, 8},
-
-        /* 1.4 GHz */
-        { 12000000, 1400000000, 700,  6,  1, 8},
-        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
-        { 16800000, 1400000000, 1000, 12, 1, 8},
-        { 19200000, 1400000000, 875,  12, 1, 8},
-        { 26000000, 1400000000, 700,  13, 1, 8},
-
-        /* 1.3 GHz */
-        { 12000000, 1300000000, 975,  9,  1, 8},
-        { 13000000, 1300000000, 1000, 10, 1, 8},
-        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
-        { 26000000, 1300000000, 650,  13, 1, 8},
-
-        /* 1.2 GHz */
-        { 12000000, 1200000000, 1000, 10, 1, 8},
-        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
-        { 16800000, 1200000000, 1000, 14, 1, 8},
-        { 19200000, 1200000000, 1000, 16, 1, 8},
-        { 26000000, 1200000000, 600,  13, 1, 8},
-
-        /* 1.1 GHz */
-        { 12000000, 1100000000, 825,  9,  1, 8},
-        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
-        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
-        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
-        { 26000000, 1100000000, 550,  13, 1, 8},
-
-        /* 1 GHz */
-        { 12000000, 1000000000, 1000, 12, 1, 8},
-        { 13000000, 1000000000, 1000, 13, 1, 8},
-        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
-        { 19200000, 1000000000, 625,  12, 1, 8},
-        { 26000000, 1000000000, 1000, 26, 1, 8},
-
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_x = {
-        .name      = "pll_x",
-        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
-        .ops       = &tegra_pll_ops,
-        .reg       = 0xe0,
-        .parent    = &tegra_pll_ref,
-        .max_rate  = 1700000000,
-        .u.pll = {
-                .input_min = 2000000,
-                .input_max = 31000000,
-                .cf_min    = 1000000,
-                .cf_max    = 6000000,
-                .vco_min   = 20000000,
-                .vco_max   = 1700000000,
-                .freq_table = tegra_pll_x_freq_table,
-                .lock_delay = 300,
-        },
-};
-
-static struct clk tegra_pll_x_out0 = {
-        .name      = "pll_x_out0",
-        .ops       = &tegra_pll_div_ops,
-        .flags     = DIV_2 | PLLX,
-        .parent    = &tegra_pll_x,
-        .max_rate  = 850000000,
-};
-
-
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
-        /* PLLE special case: use cpcon field to store cml divider value */
-        { 12000000,  100000000, 150, 1,  18, 11},
-        { 216000000, 100000000, 200, 18, 24, 13},
-        { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_e = {
-        .name      = "pll_e",
-        .flags     = PLL_ALT_MISC_REG,
-        .ops       = &tegra_plle_ops,
-        .reg       = 0xe8,
-        .max_rate  = 100000000,
-        .u.pll = {
-                .input_min = 12000000,
-                .input_max = 216000000,
-                .cf_min    = 12000000,
-                .cf_max    = 12000000,
-                .vco_min   = 1200000000,
-                .vco_max   = 2400000000U,
-                .freq_table = tegra_pll_e_freq_table,
-                .lock_delay = 300,
-                .fixed_rate = 100000000,
-        },
-};
-
-static struct clk tegra_cml0_clk = {
-        .name      = "cml0",
-        .parent    = &tegra_pll_e,
-        .ops       = &tegra_cml_clk_ops,
-        .reg       = PLLE_AUX,
-        .max_rate  = 100000000,
-        .u.periph  = {
-                .clk_num = 0,
-        },
-};
-
-static struct clk tegra_cml1_clk = {
-        .name      = "cml1",
-        .parent    = &tegra_pll_e,
-        .ops       = &tegra_cml_clk_ops,
-        .reg       = PLLE_AUX,
-        .max_rate  = 100000000,
-        .u.periph  = {
-                .clk_num   = 1,
-        },
-};
-
-static struct clk tegra_pciex_clk = {
-        .name      = "pciex",
-        .parent    = &tegra_pll_e,
-        .ops       = &tegra_pciex_clk_ops,
-        .max_rate  = 100000000,
-        .u.periph  = {
-                .clk_num   = 74,
-        },
-};
-
-/* Audio sync clocks */
-#define SYNC_SOURCE(_id)                                \
-        {                                               \
-                .name      = #_id "_sync",              \
-                .rate      = 24000000,                  \
-                .max_rate  = 24000000,                  \
-                .ops       = &tegra_sync_source_ops     \
-        }
-static struct clk tegra_sync_source_list[] = {
-        SYNC_SOURCE(spdif_in),
-        SYNC_SOURCE(i2s0),
-        SYNC_SOURCE(i2s1),
-        SYNC_SOURCE(i2s2),
-        SYNC_SOURCE(i2s3),
-        SYNC_SOURCE(i2s4),
-        SYNC_SOURCE(vimclk),
-};
-
-static struct clk_mux_sel mux_audio_sync_clk[] = {
-        { .input = &tegra_sync_source_list[0],  .value = 0},
-        { .input = &tegra_sync_source_list[1],  .value = 1},
-        { .input = &tegra_sync_source_list[2],  .value = 2},
-        { .input = &tegra_sync_source_list[3],  .value = 3},
-        { .input = &tegra_sync_source_list[4],  .value = 4},
-        { .input = &tegra_sync_source_list[5],  .value = 5},
-        { .input = &tegra_pll_a_out0,           .value = 6},
-        { .input = &tegra_sync_source_list[6],  .value = 7},
-        { 0, 0 }
+struct clk_ops tegra_cml_clk_ops = {
+        .is_enabled = tegra30_cml_clk_is_enabled,
+        .enable = tegra30_cml_clk_enable,
+        .disable = tegra30_cml_clk_disable,
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
-#define AUDIO_SYNC_CLK(_id, _index)                     \
-        {                                               \
-                .name      = #_id,                      \
-                .inputs    = mux_audio_sync_clk,        \
-                .reg       = 0x4A0 + (_index) * 4,      \
-                .max_rate  = 24000000,                  \
-                .ops       = &tegra_audio_sync_clk_ops  \
-        }
-static struct clk tegra_clk_audio_list[] = {
-        AUDIO_SYNC_CLK(audio0, 0),
-        AUDIO_SYNC_CLK(audio1, 1),
-        AUDIO_SYNC_CLK(audio2, 2),
-        AUDIO_SYNC_CLK(audio3, 3),
-        AUDIO_SYNC_CLK(audio4, 4),
-        AUDIO_SYNC_CLK(audio, 5),       /* SPDIF */
+struct clk_ops tegra_pciex_clk_ops = {
+        .recalc_rate = tegra30_clk_fixed_recalc_rate,
 };
 
-#define AUDIO_SYNC_2X_CLK(_id, _index)                          \
-        {                                                       \
-                .name      = #_id "_2x",                        \
-                .flags     = PERIPH_NO_RESET,                   \
-                .max_rate  = 48000000,                          \
-                .ops       = &tegra_clk_double_ops,             \
-                .reg       = 0x49C,                             \
-                .reg_shift = 24 + (_index),                     \
-                .parent    = &tegra_clk_audio_list[(_index)],   \
-                .u.periph = {                                   \
-                        .clk_num = 113 + (_index),              \
-                },                                              \
-        }
-static struct clk tegra_clk_audio_2x_list[] = {
-        AUDIO_SYNC_2X_CLK(audio0, 0),
-        AUDIO_SYNC_2X_CLK(audio1, 1),
-        AUDIO_SYNC_2X_CLK(audio2, 2),
-        AUDIO_SYNC_2X_CLK(audio3, 3),
-        AUDIO_SYNC_2X_CLK(audio4, 4),
-        AUDIO_SYNC_2X_CLK(audio, 5),    /* SPDIF */
-};
+/* Tegra30 CPU clock and reset control functions */
+static void tegra30_wait_cpu_in_reset(u32 cpu)
+{
+        unsigned int reg;
 
-#define MUX_I2S_SPDIF(_id, _index)                                      \
-static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = {       \
-        {.input = &tegra_pll_a_out0, .value = 0},                       \
-        {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1},      \
-        {.input = &tegra_pll_p, .value = 2},                            \
-        {.input = &tegra_clk_m, .value = 3},                            \
-        { 0, 0},                                                        \
-}
-MUX_I2S_SPDIF(audio0, 0);
-MUX_I2S_SPDIF(audio1, 1);
-MUX_I2S_SPDIF(audio2, 2);
-MUX_I2S_SPDIF(audio3, 3);
-MUX_I2S_SPDIF(audio4, 4);
-MUX_I2S_SPDIF(audio, 5);                /* SPDIF */
-
-/* External clock outputs (through PMC) */
-#define MUX_EXTERN_OUT(_id)                                             \
-static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = {        \
-        {.input = &tegra_clk_m,         .value = 0},                    \
-        {.input = &tegra_clk_m_div2,    .value = 1},                    \
-        {.input = &tegra_clk_m_div4,    .value = 2},                    \
-        {.input = NULL,                 .value = 3}, /* placeholder */  \
-        { 0, 0},                                                        \
-}
-MUX_EXTERN_OUT(1);
-MUX_EXTERN_OUT(2);
-MUX_EXTERN_OUT(3);
-
-static struct clk_mux_sel *mux_extern_out_list[] = {
-        mux_clkm_clkm2_clkm4_extern1,
-        mux_clkm_clkm2_clkm4_extern2,
-        mux_clkm_clkm2_clkm4_extern3,
-};
+        do {
+                reg = readl(reg_clk_base +
+                            TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+                cpu_relax();
+        } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
 
-#define CLK_OUT_CLK(_id)                                        \
-        {                                                       \
-                .name      = "clk_out_" #_id,                   \
-                .lookup    = {                                  \
-                        .dev_id    = "clk_out_" #_id,           \
-                        .con_id    = "extern" #_id,             \
-                },                                              \
-                .ops       = &tegra_clk_out_ops,                \
-                .reg       = 0x1a8,                             \
-                .inputs    = mux_clkm_clkm2_clkm4_extern##_id,  \
-                .flags     = MUX_CLK_OUT,                       \
-                .max_rate  = 216000000,                         \
-                .u.periph = {                                   \
-                        .clk_num   = (_id - 1) * 8 + 2,         \
-                },                                              \
-        }
-static struct clk tegra_clk_out_list[] = {
-        CLK_OUT_CLK(1),
-        CLK_OUT_CLK(2),
-        CLK_OUT_CLK(3),
-};
+        return;
+}
 
-/* called after peripheral external clocks are initialized */
-static void init_clk_out_mux(void)
+static void tegra30_put_cpu_in_reset(u32 cpu)
 {
-        int i;
-        struct clk *c;
-
-        /* output clock con_id is the name of peripheral
-           external clock connected to input 3 of the output mux */
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
-                c = tegra_get_clock_by_name(
-                        tegra_clk_out_list[i].lookup.con_id);
-                if (!c)
-                        pr_err("%s: could not find clk %s\n", __func__,
-                               tegra_clk_out_list[i].lookup.con_id);
-                mux_extern_out_list[i][3].input = c;
-        }
+        writel(CPU_RESET(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+        dmb();
 }
 
-/* Peripheral muxes */
-static struct clk_mux_sel mux_sclk[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c_out1,   .value = 1},
-        { .input = &tegra_pll_p_out4,   .value = 2},
-        { .input = &tegra_pll_p_out3,   .value = 3},
-        { .input = &tegra_pll_p_out2,   .value = 4},
-        /* { .input = &tegra_clk_d,     .value = 5}, - no use on tegra30 */
-        { .input = &tegra_clk_32k,      .value = 6},
-        { .input = &tegra_pll_m_out1,   .value = 7},
-        { 0, 0},
-};
-
-static struct clk tegra_clk_sclk = {
-        .name   = "sclk",
-        .inputs = mux_sclk,
-        .reg    = 0x28,
-        .ops    = &tegra_super_ops,
-        .max_rate = 334000000,
-        .min_rate = 40000000,
-};
-
-static struct clk tegra_clk_blink = {
-        .name           = "blink",
-        .parent         = &tegra_clk_32k,
-        .reg            = 0x40,
-        .ops            = &tegra_blink_clk_ops,
-        .max_rate       = 32768,
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
-        { .input = &tegra_pll_m, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_pll_a_out0, .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
-        { .input = &tegra_pll_p, .value = 0},
-        { .input = &tegra_pll_c, .value = 1},
-        { .input = &tegra_pll_m, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_clkm[] = {
-        { .input = &tegra_pll_p, .value = 0},
-        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
-        {.input = &tegra_pll_p, .value = 0},
-        {.input = &tegra_pll_d_out0, .value = 1},
-        {.input = &tegra_pll_c, .value = 2},
-        {.input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
-        {.input = &tegra_pll_p, .value = 0},
-        {.input = &tegra_pll_m, .value = 1},
-        {.input = &tegra_pll_d_out0, .value = 2},
-        {.input = &tegra_pll_a_out0, .value = 3},
-        {.input = &tegra_pll_c, .value = 4},
-        {.input = &tegra_pll_d2_out0, .value = 5},
-        {.input = &tegra_clk_m, .value = 6},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
-        { .input = &tegra_pll_a_out0, .value = 0},
-        /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
-        { .input = &tegra_pll_p, .value = 2},
-        { .input = &tegra_clk_m, .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_clk_32k,   .value = 2},
-        {.input = &tegra_clk_m,     .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_clk_m,     .value = 2},
-        {.input = &tegra_clk_32k,   .value = 3},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
-        {.input = &tegra_pll_p,     .value = 0},
-        {.input = &tegra_pll_c,     .value = 1},
-        {.input = &tegra_pll_m,     .value = 2},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_clk_m[] = {
-        { .input = &tegra_clk_m, .value = 0},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_out3[] = {
-        { .input = &tegra_pll_p_out3, .value = 0},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_plld_out0[] = {
-        { .input = &tegra_pll_d_out0, .value = 0},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
-        { .input = &tegra_pll_d_out0,  .value = 0},
-        { .input = &tegra_pll_d2_out0, .value = 1},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_clk_32k[] = {
-        { .input = &tegra_clk_32k, .value = 0},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
-        { .input = &tegra_pll_a_out0, .value = 0},
-        { .input = &tegra_clk_32k,    .value = 1},
-        { .input = &tegra_pll_p,      .value = 2},
-        { .input = &tegra_clk_m,      .value = 3},
-        { .input = &tegra_pll_e,      .value = 4},
-        { 0, 0},
-};
-
-static struct clk_mux_sel mux_cclk_g[] = {
-        { .input = &tegra_clk_m,        .value = 0},
-        { .input = &tegra_pll_c,        .value = 1},
-        { .input = &tegra_clk_32k,      .value = 2},
-        { .input = &tegra_pll_m,        .value = 3},
-        { .input = &tegra_pll_p,        .value = 4},
-        { .input = &tegra_pll_p_out4,   .value = 5},
-        { .input = &tegra_pll_p_out3,   .value = 6},
-        { .input = &tegra_pll_x,        .value = 8},
-        { 0, 0},
-};
-
-static struct clk tegra_clk_cclk_g = {
-        .name   = "cclk_g",
-        .flags  = DIV_U71 | DIV_U71_INT,
-        .inputs = mux_cclk_g,
-        .reg    = 0x368,
-        .ops    = &tegra_super_ops,
-        .max_rate = 1700000000,
-};
-
-static struct clk tegra30_clk_twd = {
-        .parent   = &tegra_clk_cclk_g,
-        .name     = "twd",
-        .ops      = &tegra30_twd_ops,
-        .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
-        .mul      = 1,
-        .div      = 2,
-};
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_periph_clk_ops,     \
-                .reg       = _reg,                      \
-                .inputs    = _inputs,                   \
-                .flags     = _flags,                    \
-                .max_rate  = _max,                      \
-                .u.periph = {                           \
-                        .clk_num   = _clk_num,          \
-                },                                      \
-        }
-
-#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
-                        _flags, _ops)                                   \
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = _ops,                      \
-                .reg       = _reg,                      \
-                .inputs    = _inputs,                   \
-                .flags     = _flags,                    \
-                .max_rate  = _max,                      \
-                .u.periph = {                           \
-                        .clk_num   = _clk_num,          \
-                },                                      \
-        }
-
-#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
-        {                                               \
-                .name      = _name,                     \
-                .lookup    = {                          \
-                        .dev_id    = _dev,              \
-                        .con_id    = _con,              \
-                },                                      \
-                .ops       = &tegra_clk_shared_bus_ops, \
-                .parent = _parent,                      \
-                .u.shared_bus_user = {                  \
-                        .client_id = _id,               \
-                        .client_div = _div,             \
-                        .mode = _mode,                  \
-                },                                      \
-        }
-struct clk tegra_list_clks[] = {
-        PERIPH_CLK("apbdma",    "tegra-apbdma",         NULL,   34,     0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
-        PERIPH_CLK("kbc",       "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
-        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("kfuse",     "kfuse-tegra",          NULL,   40,     0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("fuse",      "fuse-tegra",           "fuse", 39,     0,      26000000,  mux_clk_m,                   PERIPH_ON_APB),
-        PERIPH_CLK("fuse_burn", "fuse-tegra",           "fuse_burn",    39,     0,      26000000,  mux_clk_m,           PERIPH_ON_APB),
-        PERIPH_CLK("apbif",     "tegra30-ahub",         "apbif", 107,   0,      26000000,  mux_clk_m,                   0),
-        PERIPH_CLK("i2s0",      "tegra30-i2s.0",        NULL,   30,     0x1d8,  26000000,  mux_pllaout0_audio0_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s1",      "tegra30-i2s.1",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio1_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s2",      "tegra30-i2s.2",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s3",      "tegra30-i2s.3",        NULL,   101,    0x3bc,  26000000,  mux_pllaout0_audio3_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("i2s4",      "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("spdif_out", "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio_2x_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("spdif_in",  "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("pwm",       "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("d_audio",   "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("dam0",      "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("dam1",      "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("dam2",      "tegra30-dam.2",        NULL,   110,    0x3e0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("hda",       "tegra30-hda",          "hda",   125,   0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("hda2codec_2x",      "tegra30-hda",  "hda2codec",   111,     0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("hda2hdmi",  "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0),
-        PERIPH_CLK("sbc1",      "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc2",      "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc3",      "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc4",      "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc5",      "spi_tegra.4",          NULL,   104,    0x3c8,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sbc6",      "spi_tegra.5",          NULL,   105,    0x3cc,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0),
-        PERIPH_CLK_EX("ndflash", "tegra_nand",          NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71,  &tegra_nand_clk_ops),
-        PERIPH_CLK("ndspeed",   "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",        NULL,   69,     0x1bc,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",        NULL,   15,     0x164,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
-        PERIPH_CLK("vcp",       "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsea",      "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("bsev",      "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("vde",       "vde",                  NULL,   61,     0x1c8,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* max rate ??? */
-        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
-        PERIPH_CLK("owr",       "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("nor",       "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
-        PERIPH_CLK("i2c1",      "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c2",      "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c4",      "tegra-i2c.3",          NULL,   103,    0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("i2c5",      "tegra-i2c.4",          NULL,   47,     0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("uarta",     "tegra-uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartb",     "tegra-uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartc",     "tegra-uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartd",     "tegra-uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uarte",     "tegra-uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT,    &tegra_vi_clk_ops),
-        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-        PERIPH_CLK("3d2",       "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
-        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
-        PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
-        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("mpe",       "mpe",                  NULL,   60,     0x170,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  260000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
-        PERIPH_CLK("cve",       "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK_EX("dtv",    "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   0,              &tegra_dtv_clk_ops),
-        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  220000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
-        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
-        PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
-        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
-        PERIPH_CLK("dsia",      "tegradc.0",            "dsia", 48,     0,      500000000, mux_plld_out0,               0),
-        PERIPH_CLK_EX("dsib",   "tegradc.1",            "dsib", 82,     0xd0,   500000000, mux_plld_out0_plld2_out0,    MUX | PLLD,     &tegra_dsib_clk_ops),
-        PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0),
-        PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
-        PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
-
-        PERIPH_CLK("tsensor",   "tegra-tsensor",        NULL,   100,    0x3b8,  216000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71),
-        PERIPH_CLK("actmon",    "actmon",               NULL,   119,    0x3e8,  216000000, mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71),
-        PERIPH_CLK("extern1",   "extern1",              NULL,   120,    0x3ec,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("extern2",   "extern2",              NULL,   121,    0x3f0,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("extern3",   "extern3",              NULL,   122,    0x3f4,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
-        PERIPH_CLK("i2cslow",   "i2cslow",              NULL,   81,     0x3fc,  26000000,  mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("pcie",      "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("afi",       "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0),
-        PERIPH_CLK("se",        "se",                   NULL,   127,    0x42c,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con)                \
-        {                                               \
-                .name   = _name,                        \
-                .lookup = {                             \
-                        .dev_id = _dev,                 \
-                        .con_id         = _con,         \
-                },                                      \
-        }
-
-/* Some clocks may be used by different drivers depending on the board
- * configuration.  List those here to register them twice in the clock lookup
- * table under two names.
- */
-struct clk_duplicate tegra_clk_duplicates[] = {
-        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
-        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
-        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
-        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
-        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
-        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
-        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
-        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
-        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
-        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-        CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
-        CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
-        CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
-        CLK_DUPLICATE("bsev", "nvavp", "bsev"),
-        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-        CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
-        CLK_DUPLICATE("bsea", "nvavp", "bsea"),
-        CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
-        CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
-        CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
-        CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
-        CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
-        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
-        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
-        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
-        CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
-        CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
-        CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
-        CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
-        CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
-        CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
-        CLK_DUPLICATE("twd", "smp_twd", NULL),
-        CLK_DUPLICATE("vcp", "nvavp", "vcp"),
-        CLK_DUPLICATE("i2s0", NULL, "i2s0"),
-        CLK_DUPLICATE("i2s1", NULL, "i2s1"),
-        CLK_DUPLICATE("i2s2", NULL, "i2s2"),
-        CLK_DUPLICATE("i2s3", NULL, "i2s3"),
-        CLK_DUPLICATE("i2s4", NULL, "i2s4"),
-        CLK_DUPLICATE("dam0", NULL, "dam0"),
-        CLK_DUPLICATE("dam1", NULL, "dam1"),
-        CLK_DUPLICATE("dam2", NULL, "dam2"),
-        CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
-};
-
-struct clk *tegra_ptr_clks[] = {
-        &tegra_clk_32k,
-        &tegra_clk_m,
-        &tegra_clk_m_div2,
-        &tegra_clk_m_div4,
-        &tegra_pll_ref,
-        &tegra_pll_m,
-        &tegra_pll_m_out1,
-        &tegra_pll_c,
-        &tegra_pll_c_out1,
-        &tegra_pll_p,
-        &tegra_pll_p_out1,
-        &tegra_pll_p_out2,
-        &tegra_pll_p_out3,
-        &tegra_pll_p_out4,
-        &tegra_pll_a,
-        &tegra_pll_a_out0,
-        &tegra_pll_d,
-        &tegra_pll_d_out0,
-        &tegra_pll_d2,
-        &tegra_pll_d2_out0,
-        &tegra_pll_u,
-        &tegra_pll_x,
-        &tegra_pll_x_out0,
-        &tegra_pll_e,
-        &tegra_clk_cclk_g,
-        &tegra_cml0_clk,
-        &tegra_cml1_clk,
-        &tegra_pciex_clk,
-        &tegra_clk_sclk,
-        &tegra_clk_blink,
-        &tegra30_clk_twd,
-};
-
-
-static void tegra30_init_one_clock(struct clk *c)
+static void tegra30_cpu_out_of_reset(u32 cpu)
 {
-        clk_init(c);
-        INIT_LIST_HEAD(&c->shared_bus_list);
-        if (!c->lookup.dev_id && !c->lookup.con_id)
-                c->lookup.con_id = c->name;
-        c->lookup.clk = c;
-        clkdev_add(&c->lookup);
+        writel(CPU_RESET(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+        wmb();
 }
 
-void __init tegra30_init_clocks(void)
+static void tegra30_enable_cpu_clock(u32 cpu)
 {
-        int i;
-        struct clk *c;
+        unsigned int reg;
 
-        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
-                tegra30_init_one_clock(tegra_ptr_clks[i]);
-
-        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-                tegra30_init_one_clock(&tegra_list_clks[i]);
+        writel(CPU_CLOCK(cpu),
+               reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+        reg = readl(reg_clk_base +
+                    TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+}
 
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
-                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
-                if (!c) {
-                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
-                                tegra_clk_duplicates[i].name);
-                        continue;
-                }
+static void tegra30_disable_cpu_clock(u32 cpu)
+{
 
-                tegra_clk_duplicates[i].lookup.clk = c;
-                clkdev_add(&tegra_clk_duplicates[i].lookup);
-        }
+        unsigned int reg;
 
-        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
-                tegra30_init_one_clock(&tegra_sync_source_list[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
-                tegra30_init_one_clock(&tegra_clk_audio_list[i]);
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
-                tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
+        reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        writel(reg | CPU_CLOCK(cpu),
+               reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
 
-        init_clk_out_mux();
-        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
-                tegra30_init_one_clock(&tegra_clk_out_list[i]);
+static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
+        .wait_for_reset = tegra30_wait_cpu_in_reset,
+        .put_in_reset   = tegra30_put_cpu_in_reset,
+        .out_of_reset   = tegra30_cpu_out_of_reset,
+        .enable_clock   = tegra30_enable_cpu_clock,
+        .disable_clock  = tegra30_disable_cpu_clock,
+};
 
+void __init tegra30_cpu_car_ops_init(void)
+{
+        tegra_cpu_car_ops = &tegra30_cpu_car_ops;
 }
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
new file mode 100644
index 000000000000..f2f88fef6b8b
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA30_CLOCK_H
+#define __MACH_TEGRA30_CLOCK_H
+
+extern struct clk_ops tegra30_clk_32k_ops;
+extern struct clk_ops tegra30_clk_m_ops;
+extern struct clk_ops tegra_clk_m_div_ops;
+extern struct clk_ops tegra_pll_ref_ops;
+extern struct clk_ops tegra30_pll_ops;
+extern struct clk_ops tegra30_pll_div_ops;
+extern struct clk_ops tegra_plld_ops;
+extern struct clk_ops tegra30_plle_ops;
+extern struct clk_ops tegra_cml_clk_ops;
+extern struct clk_ops tegra_pciex_clk_ops;
+extern struct clk_ops tegra_sync_source_ops;
+extern struct clk_ops tegra30_audio_sync_clk_ops;
+extern struct clk_ops tegra30_clk_double_ops;
+extern struct clk_ops tegra_clk_out_ops;
+extern struct clk_ops tegra30_super_ops;
+extern struct clk_ops tegra30_blink_clk_ops;
+extern struct clk_ops tegra30_twd_ops;
+extern struct clk_ops tegra30_periph_clk_ops;
+extern struct clk_ops tegra30_dsib_clk_ops;
+extern struct clk_ops tegra_nand_clk_ops;
+extern struct clk_ops tegra_vi_clk_ops;
+extern struct clk_ops tegra_dtv_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
+                                enum tegra_clk_ex_param p, u32 setting);
+#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
new file mode 100644
index 000000000000..c10449603df0
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -0,0 +1,1372 @@
+/*
+ * arch/arm/mach-tegra/tegra30_clocks.c
+ *
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+
+#include <linux/clk-private.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra30_clocks.h"
+#include "tegra_cpu_car.h"
+
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,            \
+                   _parent_names, _parents, _parent)            \
+        static struct clk tegra_##_name = {                     \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .name = #_name,                                 \
+                .rate = _rate,                                  \
+                .ops = _ops,                                    \
+                .flags = _flags,                                \
+                .parent_names = _parent_names,                  \
+                .parents = _parents,                            \
+                .num_parents = ARRAY_SIZE(_parent_names),       \
+                .parent = _parent,                              \
+        };
+
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+        .hw = {
+                .clk = &tegra_clk_32k,
+        },
+        .fixed_rate = 32768,
+};
+static struct clk tegra_clk_32k = {
+        .name = "clk_32k",
+        .hw = &tegra_clk_32k_hw.hw,
+        .ops = &tegra30_clk_32k_ops,
+        .flags = CLK_IS_ROOT,
+};
+
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+        .hw = {
+                .clk = &tegra_clk_m,
+        },
+        .flags = ENABLE_ON_INIT,
+        .reg = 0x1fc,
+        .reg_shift = 28,
+        .max_rate = 48000000,
+};
+static struct clk tegra_clk_m = {
+        .name = "clk_m",
+        .hw = &tegra_clk_m_hw.hw,
+        .ops = &tegra30_clk_m_ops,
+        .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+};
+
+static const char *clk_m_div_parent_names[] = {
+        "clk_m",
+};
+
+static struct clk *clk_m_div_parents[] = {
+        &tegra_clk_m,
+};
+
+static struct clk tegra_clk_m_div2;
+static struct clk_tegra tegra_clk_m_div2_hw = {
+        .hw = {
+                .clk = &tegra_clk_m_div2,
+        },
+        .mul = 1,
+        .div = 2,
+        .max_rate = 24000000,
+};
+DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
+                clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+
+static struct clk tegra_clk_m_div4;
+static struct clk_tegra tegra_clk_m_div4_hw = {
+        .hw = {
+                .clk = &tegra_clk_m_div4,
+        },
+        .mul = 1,
+        .div = 4,
+        .max_rate = 12000000,
+};
+DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
+                clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+
+static struct clk tegra_pll_ref;
+static struct clk_tegra tegra_pll_ref_hw = {
+        .hw = {
+                .clk = &tegra_pll_ref,
+        },
+        .flags = ENABLE_ON_INIT,
+        .max_rate = 26000000,
+};
+DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
+                clk_m_div_parents, &tegra_clk_m);
+
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,  \
+                   _input_max, _cf_min, _cf_max, _vco_min,      \
+                   _vco_max, _freq_table, _lock_delay, _ops,    \
+                   _fixed_rate, _clk_cfg_ex, _parent)           \
+        static struct clk tegra_##_name;                        \
+        static const char *_name##_parent_names[] = {           \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *_name##_parents[] = {                \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .u.pll = {                                      \
+                        .input_min = _input_min,                \
+                        .input_max = _input_max,                \
+                        .cf_min = _cf_min,                      \
+                        .cf_max = _cf_max,                      \
+                        .vco_min = _vco_min,                    \
+                        .vco_max = _vco_max,                    \
+                        .freq_table = _freq_table,              \
+                        .lock_delay = _lock_delay,              \
+                        .fixed_rate = _fixed_rate,              \
+                },                                              \
+                .clk_cfg_ex = _clk_cfg_ex,                      \
+        };                                                      \
+        DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED,    \
+                         _name##_parent_names, _name##_parents, \
+                        &tegra_##_parent);
+
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,         \
+                _max_rate, _ops, _parent, _clk_flags)           \
+        static const char *_name##_parent_names[] = {           \
+                #_parent,                                       \
+        };                                                      \
+        static struct clk *_name##_parents[] = {                \
+                &tegra_##_parent,                               \
+        };                                                      \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .flags = _flags,                                \
+                .reg = _reg,                                    \
+                .max_rate = _max_rate,                          \
+                .reg_shift = _reg_shift,                        \
+        };                                                      \
+        DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops,        \
+                _clk_flags,  _name##_parent_names,              \
+                _name##_parents, &tegra_##_parent);
+
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+        { 12000000, 1040000000, 520,  6, 1, 8},
+        { 13000000, 1040000000, 480,  6, 1, 8},
+        { 16800000, 1040000000, 495,  8, 1, 8}, /* actual: 1039.5 MHz */
+        { 19200000, 1040000000, 325,  6, 1, 6},
+        { 26000000, 1040000000, 520, 13, 1, 8},
+
+        { 12000000, 832000000, 416,  6, 1, 8},
+        { 13000000, 832000000, 832, 13, 1, 8},
+        { 16800000, 832000000, 396,  8, 1, 8},  /* actual: 831.6 MHz */
+        { 19200000, 832000000, 260,  6, 1, 8},
+        { 26000000, 832000000, 416, 13, 1, 8},
+
+        { 12000000, 624000000, 624, 12, 1, 8},
+        { 13000000, 624000000, 624, 13, 1, 8},
+        { 16800000, 600000000, 520, 14, 1, 8},
+        { 19200000, 624000000, 520, 16, 1, 8},
+        { 26000000, 624000000, 624, 26, 1, 8},
+
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 16800000, 600000000, 500, 14, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+
+        { 12000000, 520000000, 520, 12, 1, 8},
+        { 13000000, 520000000, 520, 13, 1, 8},
+        { 16800000, 520000000, 495, 16, 1, 8},  /* actual: 519.75 MHz */
+        { 19200000, 520000000, 325, 12, 1, 6},
+        { 26000000, 520000000, 520, 26, 1, 8},
+
+        { 12000000, 416000000, 416, 12, 1, 8},
+        { 13000000, 416000000, 416, 13, 1, 8},
+        { 16800000, 416000000, 396, 16, 1, 8},  /* actual: 415.8 MHz */
+        { 19200000, 416000000, 260, 12, 1, 6},
+        { 26000000, 416000000, 416, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+                tegra30_pll_ops, 0, NULL, pll_ref);
+
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
+                tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+        { 12000000, 666000000, 666, 12, 1, 8},
+        { 13000000, 666000000, 666, 13, 1, 8},
+        { 16800000, 666000000, 555, 14, 1, 8},
+        { 19200000, 666000000, 555, 16, 1, 8},
+        { 26000000, 666000000, 666, 26, 1, 8},
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 16800000, 600000000, 500, 14, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
+                1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
+                300, tegra30_pll_ops, 0, NULL, pll_ref);
+
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+                tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+        { 12000000, 216000000, 432, 12, 2, 8},
+        { 13000000, 216000000, 432, 13, 2, 8},
+        { 16800000, 216000000, 360, 14, 2, 8},
+        { 19200000, 216000000, 360, 16, 2, 8},
+        { 26000000, 216000000, 432, 26, 2, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+                2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+                tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
+                pll_ref);
+
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+                0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+                16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+                0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+                16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+        { 9600000, 564480000, 294, 5, 1, 4},
+        { 9600000, 552960000, 288, 5, 1, 4},
+        { 9600000, 24000000,  5,   2, 1, 1},
+
+        { 28800000, 56448000, 49, 25, 1, 1},
+        { 28800000, 73728000, 64, 25, 1, 1},
+        { 28800000, 24000000,  5,  6, 1, 1},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
+                6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
+                300, tegra30_pll_ops, 0, NULL, pll_p_out1);
+
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
+                pll_a, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+        { 12000000, 216000000, 216, 12, 1, 4},
+        { 13000000, 216000000, 216, 13, 1, 4},
+        { 16800000, 216000000, 180, 14, 1, 4},
+        { 19200000, 216000000, 180, 16, 1, 4},
+        { 26000000, 216000000, 216, 26, 1, 4},
+
+        { 12000000, 594000000, 594, 12, 1, 8},
+        { 13000000, 594000000, 594, 13, 1, 8},
+        { 16800000, 594000000, 495, 14, 1, 8},
+        { 19200000, 594000000, 495, 16, 1, 8},
+        { 26000000, 594000000, 594, 26, 1, 8},
+
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+                1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+                1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
+
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+                pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+
+DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
+                2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
+                tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
+                pll_ref);
+
+DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+                pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+        { 12000000, 480000000, 960, 12, 2, 12},
+        { 13000000, 480000000, 960, 13, 2, 12},
+        { 16800000, 480000000, 400, 7,  2, 5},
+        { 19200000, 480000000, 200, 4,  2, 3},
+        { 26000000, 480000000, 960, 26, 2, 12},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
+                1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
+                1000, tegra30_pll_ops, 0, NULL, pll_ref);
+
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+        /* 1.7 GHz */
+        { 12000000, 1700000000, 850,  6,  1, 8},
+        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
+        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
+        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
+        { 26000000, 1700000000, 850,  13, 1, 8},
+
+        /* 1.6 GHz */
+        { 12000000, 1600000000, 800,  6,  1, 8},
+        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
+        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
+        { 19200000, 1600000000, 500,  6,  1, 8},
+        { 26000000, 1600000000, 800,  13, 1, 8},
+
+        /* 1.5 GHz */
+        { 12000000, 1500000000, 750,  6,  1, 8},
+        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
+        { 16800000, 1500000000, 625,  7,  1, 8},
+        { 19200000, 1500000000, 625,  8,  1, 8},
+        { 26000000, 1500000000, 750,  13, 1, 8},
+
+        /* 1.4 GHz */
+        { 12000000, 1400000000, 700,  6,  1, 8},
+        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
+        { 16800000, 1400000000, 1000, 12, 1, 8},
+        { 19200000, 1400000000, 875,  12, 1, 8},
+        { 26000000, 1400000000, 700,  13, 1, 8},
+
+        /* 1.3 GHz */
+        { 12000000, 1300000000, 975,  9,  1, 8},
+        { 13000000, 1300000000, 1000, 10, 1, 8},
+        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
+        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
+        { 26000000, 1300000000, 650,  13, 1, 8},
+
+        /* 1.2 GHz */
+        { 12000000, 1200000000, 1000, 10, 1, 8},
+        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
+        { 16800000, 1200000000, 1000, 14, 1, 8},
+        { 19200000, 1200000000, 1000, 16, 1, 8},
+        { 26000000, 1200000000, 600,  13, 1, 8},
+
+        /* 1.1 GHz */
+        { 12000000, 1100000000, 825,  9,  1, 8},
+        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
+        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
+        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
+        { 26000000, 1100000000, 550,  13, 1, 8},
+
+        /* 1 GHz */
+        { 12000000, 1000000000, 1000, 12, 1, 8},
+        { 13000000, 1000000000, 1000, 13, 1, 8},
+        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 8},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
+                2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
+                tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
+
+DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
+                pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+        /* PLLE special case: use cpcon field to store cml divider value */
+        { 12000000,  100000000, 150, 1,  18, 11},
+        { 216000000, 100000000, 200, 18, 24, 13},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
+                12000000, 12000000, 1200000000, 2400000000U,
+                tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
+                pll_ref);
+
+static const char *mux_plle[] = {
+        "pll_e",
+};
+
+static struct clk *mux_plle_p[] = {
+        &tegra_pll_e,
+};
+
+static struct clk tegra_cml0;
+static struct clk_tegra tegra_cml0_hw = {
+        .hw = {
+                .clk = &tegra_cml0,
+        },
+        .reg = 0x48c,
+        .fixed_rate = 100000000,
+        .u.periph = {
+                .clk_num = 0,
+        },
+};
+DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
+                mux_plle_p, &tegra_pll_e);
+
+static struct clk tegra_cml1;
+static struct clk_tegra tegra_cml1_hw = {
+        .hw = {
+                .clk = &tegra_cml1,
+        },
+        .reg = 0x48c,
+        .fixed_rate = 100000000,
+        .u.periph = {
+                .clk_num = 1,
+        },
+};
+DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
+                mux_plle_p, &tegra_pll_e);
+
+static struct clk tegra_pciex;
+static struct clk_tegra tegra_pciex_hw = {
+        .hw = {
+                .clk = &tegra_pciex,
+        },
+        .reg = 0x48c,
+        .fixed_rate = 100000000,
+        .reset = tegra30_periph_clk_reset,
+        .u.periph = {
+                .clk_num = 74,
+        },
+};
+DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
+                mux_plle_p, &tegra_pll_e);
+
+#define SYNC_SOURCE(_name)                                      \
+        static struct clk tegra_##_name##_sync;                 \
+        static struct clk_tegra tegra_##_name##_sync_hw = {     \
+                .hw = {                                         \
+                        .clk = &tegra_##_name##_sync,           \
+                },                                              \
+                .max_rate = 24000000,                           \
+                .fixed_rate = 24000000,                         \
+        };                                                      \
+        static struct clk tegra_##_name##_sync = {              \
+                .name = #_name "_sync",                         \
+                .hw = &tegra_##_name##_sync_hw.hw,              \
+                .ops = &tegra_sync_source_ops,                  \
+                .flags = CLK_IS_ROOT,                           \
+        };
+
+SYNC_SOURCE(spdif_in);
+SYNC_SOURCE(i2s0);
+SYNC_SOURCE(i2s1);
+SYNC_SOURCE(i2s2);
+SYNC_SOURCE(i2s3);
+SYNC_SOURCE(i2s4);
+SYNC_SOURCE(vimclk);
+
+static struct clk *tegra_sync_source_list[] = {
+        &tegra_spdif_in_sync,
+        &tegra_i2s0_sync,
+        &tegra_i2s1_sync,
+        &tegra_i2s2_sync,
+        &tegra_i2s3_sync,
+        &tegra_i2s4_sync,
+        &tegra_vimclk_sync,
+};
+
+static const char *mux_audio_sync_clk[] = {
+        "spdif_in_sync",
+        "i2s0_sync",
+        "i2s1_sync",
+        "i2s2_sync",
+        "i2s3_sync",
+        "i2s4_sync",
+        "vimclk_sync",
+};
+
+#define AUDIO_SYNC_CLK(_name, _index)                           \
+        static struct clk tegra_##_name;                        \
+        static struct clk_tegra tegra_##_name##_hw = {          \
+                .hw = {                                         \
+                        .clk = &tegra_##_name,                  \
+                },                                              \
+                .max_rate = 24000000,                           \
+                .reg = 0x4A0 + (_index) * 4,                    \
+        };                                                      \
+        static struct clk tegra_##_name = {                     \
+                .name = #_name,                                 \
+                .ops = &tegra30_audio_sync_clk_ops,             \
+                .hw = &tegra_##_name##_hw.hw,                   \
+                .parent_names = mux_audio_sync_clk,             \
+                .parents = tegra_sync_source_list,              \
+                .num_parents = ARRAY_SIZE(mux_audio_sync_clk),  \
+        };
+
+AUDIO_SYNC_CLK(audio0, 0);
+AUDIO_SYNC_CLK(audio1, 1);
+AUDIO_SYNC_CLK(audio2, 2);
+AUDIO_SYNC_CLK(audio3, 3);
+AUDIO_SYNC_CLK(audio4, 4);
+AUDIO_SYNC_CLK(audio5, 5);
+
+static struct clk *tegra_clk_audio_list[] = {
+        &tegra_audio0,
+        &tegra_audio1,
+        &tegra_audio2,
+        &tegra_audio3,
+        &tegra_audio4,
+        &tegra_audio5,  /* SPDIF */
+};
+
+#define AUDIO_SYNC_2X_CLK(_name, _index)                        \
+        static const char *_name##_parent_names[] = {           \
+                "tegra_" #_name,                                \
+        };                                                      \
+        static struct clk *_name##_parents[] = {                \
+                &tegra_##_name,                                 \
+        };                                                      \
+        static struct clk tegra_##_name##_2x;                   \
+        static struct clk_tegra tegra_##_name##_2x_hw = {       \
+                .hw = {                                         \
+                        .clk = &tegra_##_name##_2x,             \
+                },                                              \
+                .flags = PERIPH_NO_RESET,                       \
+                .max_rate = 48000000,                           \
+                .reg = 0x49C,                                   \
+                .reg_shift = 24 + (_index),                     \
+                .u.periph = {                                   \
+                        .clk_num = 113 + (_index),              \
+                },                                              \
+        };                                                      \
+        static struct clk tegra_##_name##_2x = {                \
+                .name = #_name "_2x",                           \
+                .ops = &tegra30_clk_double_ops,                 \
+                .hw = &tegra_##_name##_2x_hw.hw,                \
+                .parent_names = _name##_parent_names,           \
+                .parents = _name##_parents,                     \
+                .parent = &tegra_##_name,                       \
+                .num_parents = 1,                               \
+        };
+
+AUDIO_SYNC_2X_CLK(audio0, 0);
+AUDIO_SYNC_2X_CLK(audio1, 1);
+AUDIO_SYNC_2X_CLK(audio2, 2);
+AUDIO_SYNC_2X_CLK(audio3, 3);
+AUDIO_SYNC_2X_CLK(audio4, 4);
+AUDIO_SYNC_2X_CLK(audio5, 5);   /* SPDIF */
+
+static struct clk *tegra_clk_audio_2x_list[] = {
+        &tegra_audio0_2x,
+        &tegra_audio1_2x,
+        &tegra_audio2_2x,
+        &tegra_audio3_2x,
+        &tegra_audio4_2x,
+        &tegra_audio5_2x,       /* SPDIF */
+};
+
+#define MUX_I2S_SPDIF(_id)                                      \
+static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = {      \
+        "pll_a_out0",                                           \
+        #_id "_2x",                                             \
+        "pll_p",                                                \
+        "clk_m",                                                \
+};                                                              \
+static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = {    \
+        &tegra_pll_a_out0,                                      \
+        &tegra_##_id##_2x,                                      \
+        &tegra_pll_p,                                           \
+        &tegra_clk_m,                                           \
+};
+
+MUX_I2S_SPDIF(audio0);
+MUX_I2S_SPDIF(audio1);
+MUX_I2S_SPDIF(audio2);
+MUX_I2S_SPDIF(audio3);
+MUX_I2S_SPDIF(audio4);
+MUX_I2S_SPDIF(audio5);          /* SPDIF */
+
+static struct clk tegra_extern1;
+static struct clk tegra_extern2;
+static struct clk tegra_extern3;
+
+/* External clock outputs (through PMC) */
+#define MUX_EXTERN_OUT(_id)                                     \
+static const char *mux_clkm_clkm2_clkm4_extern##_id[] = {       \
+        "clk_m",                                                \
+        "clk_m_div2",                                           \
+        "clk_m_div4",                                           \
+        "extern" #_id,                                          \
+};                                                              \
+static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = {   \
+        &tegra_clk_m,                                           \
+        &tegra_clk_m_div2,                                      \
+        &tegra_clk_m_div4,                                      \
+        &tegra_extern##_id,                                     \
+};
+
+MUX_EXTERN_OUT(1);
+MUX_EXTERN_OUT(2);
+MUX_EXTERN_OUT(3);
+
+#define CLK_OUT_CLK(_name, _index)                                      \
+        static struct clk tegra_##_name;                                \
+        static struct clk_tegra tegra_##_name##_hw = {                  \
+                .hw = {                                                 \
+                        .clk = &tegra_##_name,                          \
+                },                                                      \
+                .lookup = {                                             \
+                        .dev_id = #_name,                               \
+                        .con_id = "extern" #_index,                     \
+                },                                                      \
+                .flags = MUX_CLK_OUT,                                   \
+                .fixed_rate = 216000000,                                        \
+                .reg = 0x1a8,                                           \
+                .u.periph = {                                           \
+                        .clk_num = (_index - 1) * 8 + 2,                \
+                },                                                      \
+        };                                                              \
+        static struct clk tegra_##_name = {                             \
+                .name = #_name,                                         \
+                .ops = &tegra_clk_out_ops,                              \
+                .hw = &tegra_##_name##_hw.hw,                           \
+                .parent_names = mux_clkm_clkm2_clkm4_extern##_index,    \
+                .parents = mux_clkm_clkm2_clkm4_extern##_index##_p,     \
+                .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
+        };
+
+CLK_OUT_CLK(clk_out_1, 1);
+CLK_OUT_CLK(clk_out_2, 2);
+CLK_OUT_CLK(clk_out_3, 3);
+
+static struct clk *tegra_clk_out_list[] = {
+        &tegra_clk_out_1,
+        &tegra_clk_out_2,
+        &tegra_clk_out_3,
+};
+
+static const char *mux_sclk[] = {
+        "clk_m",
+        "pll_c_out1",
+        "pll_p_out4",
+        "pll_p_out3",
+        "pll_p_out2",
+        "dummy",
+        "clk_32k",
+        "pll_m_out1",
+};
+
+static struct clk *mux_sclk_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c_out1,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out2,
+        NULL,
+        &tegra_clk_32k,
+        &tegra_pll_m_out1,
+};
+
+static struct clk tegra_clk_sclk;
+static struct clk_tegra tegra_clk_sclk_hw = {
+        .hw = {
+                .clk = &tegra_clk_sclk,
+        },
+        .reg = 0x28,
+        .max_rate = 334000000,
+        .min_rate = 40000000,
+};
+
+static struct clk tegra_clk_sclk = {
+        .name = "sclk",
+        .ops = &tegra30_super_ops,
+        .hw = &tegra_clk_sclk_hw.hw,
+        .parent_names = mux_sclk,
+        .parents = mux_sclk_p,
+        .num_parents = ARRAY_SIZE(mux_sclk),
+};
+
+static const char *mux_blink[] = {
+        "clk_32k",
+};
+
+static struct clk *mux_blink_p[] = {
+        &tegra_clk_32k,
+};
+
+static struct clk tegra_clk_blink;
+static struct clk_tegra tegra_clk_blink_hw = {
+        .hw = {
+                .clk = &tegra_clk_blink,
+        },
+        .reg = 0x40,
+        .max_rate = 32768,
+};
+static struct clk tegra_clk_blink = {
+        .name = "blink",
+        .ops = &tegra30_blink_clk_ops,
+        .hw = &tegra_clk_blink_hw.hw,
+        .parent = &tegra_clk_32k,
+        .parent_names = mux_blink,
+        .parents = mux_blink_p,
+        .num_parents = ARRAY_SIZE(mux_blink),
+};
+
+static const char *mux_pllm_pllc_pllp_plla[] = {
+        "pll_m",
+        "pll_c",
+        "pll_p",
+        "pll_a_out0",
+};
+
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m",
+        "clk_m",
+};
+
+static const char *mux_pllp_clkm[] = {
+        "pll_p",
+        "dummy",
+        "dummy",
+        "clk_m",
+};
+
+static const char *mux_pllp_plld_pllc_clkm[] = {
+        "pll_p",
+        "pll_d_out0",
+        "pll_c",
+        "clk_m",
+};
+
+static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+        "pll_p",
+        "pll_m",
+        "pll_d_out0",
+        "pll_a_out0",
+        "pll_c",
+        "pll_d2_out0",
+        "clk_m",
+};
+
+static const char *mux_plla_pllc_pllp_clkm[] = {
+        "pll_a_out0",
+        "dummy",
+        "pll_p",
+        "clk_m"
+};
+
+static const char *mux_pllp_pllc_clk32_clkm[] = {
+        "pll_p",
+        "pll_c",
+        "clk_32k",
+        "clk_m",
+};
+
+static const char *mux_pllp_pllc_clkm_clk32[] = {
+        "pll_p",
+        "pll_c",
+        "clk_m",
+        "clk_32k",
+};
+
+static const char *mux_pllp_pllc_pllm[] = {
+        "pll_p",
+        "pll_c",
+        "pll_m",
+};
+
+static const char *mux_clk_m[] = {
+        "clk_m",
+};
+
+static const char *mux_pllp_out3[] = {
+        "pll_p_out3",
+};
+
+static const char *mux_plld_out0[] = {
+        "pll_d_out0",
+};
+
+static const char *mux_plld_out0_plld2_out0[] = {
+        "pll_d_out0",
+        "pll_d2_out0",
+};
+
+static const char *mux_clk_32k[] = {
+        "clk_32k",
+};
+
+static const char *mux_plla_clk32_pllp_clkm_plle[] = {
+        "pll_a_out0",
+        "clk_32k",
+        "pll_p",
+        "clk_m",
+        "pll_e",
+};
+
+static const char *mux_cclk_g[] = {
+        "clk_m",
+        "pll_c",
+        "clk_32k",
+        "pll_m",
+        "pll_p",
+        "pll_p_out4",
+        "pll_p_out3",
+        "dummy",
+        "pll_x",
+};
+
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+        &tegra_pll_m,
+        &tegra_pll_c,
+        &tegra_pll_p,
+        &tegra_pll_a_out0,
+};
+
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_clkm_p[] = {
+        &tegra_pll_p,
+        NULL,
+        NULL,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_d_out0,
+        &tegra_pll_c,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_m,
+        &tegra_pll_d_out0,
+        &tegra_pll_a_out0,
+        &tegra_pll_c,
+        &tegra_pll_d2_out0,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
+        &tegra_pll_a_out0,
+        NULL,
+        &tegra_pll_p,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_clk_32k,
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_clk_m,
+        &tegra_clk_32k,
+};
+
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+        &tegra_pll_p,
+        &tegra_pll_c,
+        &tegra_pll_m,
+};
+
+static struct clk *mux_clk_m_p[] = {
+        &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_out3_p[] = {
+        &tegra_pll_p_out3,
+};
+
+static struct clk *mux_plld_out0_p[] = {
+        &tegra_pll_d_out0,
+};
+
+static struct clk *mux_plld_out0_plld2_out0_p[] = {
+        &tegra_pll_d_out0,
+        &tegra_pll_d2_out0,
+};
+
+static struct clk *mux_clk_32k_p[] = {
+        &tegra_clk_32k,
+};
+
+static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
+        &tegra_pll_a_out0,
+        &tegra_clk_32k,
+        &tegra_pll_p,
+        &tegra_clk_m,
+        &tegra_pll_e,
+};
+
+static struct clk *mux_cclk_g_p[] = {
+        &tegra_clk_m,
+        &tegra_pll_c,
+        &tegra_clk_32k,
+        &tegra_pll_m,
+        &tegra_pll_p,
+        &tegra_pll_p_out4,
+        &tegra_pll_p_out3,
+        NULL,
+        &tegra_pll_x,
+};
+
+static struct clk tegra_clk_cclk_g;
+static struct clk_tegra tegra_clk_cclk_g_hw = {
+        .hw = {
+                .clk = &tegra_clk_cclk_g,
+        },
+        .flags = DIV_U71 | DIV_U71_INT,
+        .reg = 0x368,
+        .max_rate = 1700000000,
+};
+static struct clk tegra_clk_cclk_g = {
+        .name = "cclk_g",
+        .ops = &tegra30_super_ops,
+        .hw = &tegra_clk_cclk_g_hw.hw,
+        .parent_names = mux_cclk_g,
+        .parents = mux_cclk_g_p,
+        .num_parents = ARRAY_SIZE(mux_cclk_g),
+};
+
+static const char *mux_twd[] = {
+        "cclk_g",
+};
+
+static struct clk *mux_twd_p[] = {
+        &tegra_clk_cclk_g,
+};
+
+static struct clk tegra30_clk_twd;
+static struct clk_tegra tegra30_clk_twd_hw = {
+        .hw = {
+                .clk = &tegra30_clk_twd,
+        },
+        .max_rate = 1400000000,
+        .mul = 1,
+        .div = 2,
+};
+
+static struct clk tegra30_clk_twd = {
+        .name = "twd",
+        .ops = &tegra30_twd_ops,
+        .hw = &tegra30_clk_twd_hw.hw,
+        .parent = &tegra_clk_cclk_g,
+        .parent_names = mux_twd,
+        .parents = mux_twd_p,
+        .num_parents = ARRAY_SIZE(mux_twd),
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,   \
+                _max, _inputs, _flags)                  \
+        static struct clk tegra_##_name;                \
+        static struct clk_tegra tegra_##_name##_hw = {  \
+                .hw = {                                 \
+                        .clk = &tegra_##_name,          \
+                },                                      \
+                .lookup = {                             \
+                        .dev_id = _dev,                 \
+                        .con_id = _con,                 \
+                },                                      \
+                .reg = _reg,                            \
+                .flags = _flags,                        \
+                .max_rate = _max,                       \
+                .u.periph = {                           \
+                        .clk_num = _clk_num,            \
+                },                                      \
+                .reset = &tegra30_periph_clk_reset,     \
+        };                                              \
+        static struct clk tegra_##_name = {             \
+                .name = #_name,                         \
+                .ops = &tegra30_periph_clk_ops,         \
+                .hw = &tegra_##_name##_hw.hw,           \
+                .parent_names = _inputs,                \
+                .parents = _inputs##_p,                 \
+                .num_parents = ARRAY_SIZE(_inputs),     \
+        };
+
+PERIPH_CLK(apbdma,      "tegra-apbdma",         NULL,   34,     0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(rtc,         "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(kbc,         "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(timer,       "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(kfuse,       "kfuse-tegra",          NULL,   40,     0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(fuse,        "fuse-tegra",           "fuse", 39,     0,      26000000,  mux_clk_m,                   PERIPH_ON_APB);
+PERIPH_CLK(fuse_burn,   "fuse-tegra",           "fuse_burn",    39,     0,      26000000,  mux_clk_m,           PERIPH_ON_APB);
+PERIPH_CLK(apbif,       "tegra30-ahub",         "apbif", 107,   0,      26000000,  mux_clk_m,                   0);
+PERIPH_CLK(i2s0,        "tegra30-i2s.0",        NULL,   30,     0x1d8,  26000000,  mux_pllaout0_audio0_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s1,        "tegra30-i2s.1",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio1_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s2,        "tegra30-i2s.2",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s3,        "tegra30-i2s.3",        NULL,   101,    0x3bc,  26000000,  mux_pllaout0_audio3_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s4,        "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_out,   "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio5_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_in,    "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pwm,         "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(d_audio,     "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(dam0,        "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(dam1,        "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(dam2,        "tegra30-dam.2",        NULL,   110,    0x3e0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
+PERIPH_CLK(hda,         "tegra30-hda",          "hda",  125,    0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(hda2codec_2x,        "tegra30-hda",  "hda2codec",    111,    0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(hda2hdmi,    "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0);
+PERIPH_CLK(sbc1,        "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc2,        "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc3,        "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc4,        "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc5,        "spi_tegra.4",          NULL,   104,    0x3c8,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc6,        "spi_tegra.5",          NULL,   105,    0x3cc,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sata_oob,    "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sata,        "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(sata_cold,   "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0);
+PERIPH_CLK(ndflash,     "tegra_nand",           NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(ndspeed,     "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(vfir,        "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sdmmc1,      "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2,      "sdhci-tegra.1",        NULL,   9,      0x154,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3,      "sdhci-tegra.2",        NULL,   69,     0x1bc,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4,      "sdhci-tegra.3",        NULL,   15,     0x164,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp,         "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsea,        "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(bsev,        "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(vde,         "vde",                  NULL,   61,     0x1c8,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(csite,       "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* max rate ??? */
+PERIPH_CLK(la,          "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
+PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
+PERIPH_CLK(i2c1,        "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c2,        "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c3,        "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c4,        "tegra-i2c.3",          NULL,   103,    0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c5,        "tegra-i2c.4",          NULL,   47,     0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartd,       "tegra-uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uarte,       "tegra-uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(vi,          "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(3d,          "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(3d2,         "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(2d,          "2d",                   NULL,   21,     0x15c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
+PERIPH_CLK(vi_sensor,   "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET);
+PERIPH_CLK(epp,         "epp",                  NULL,   19,     0x16c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(mpe,         "mpe",                  NULL,   60,     0x170,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(host1x,      "host1x",               NULL,   28,     0x180,  260000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(cve,         "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo,         "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(dtv,         "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   0);
+PERIPH_CLK(hdmi,        "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71);
+PERIPH_CLK(tvdac,       "tvdac",                NULL,   53,     0x194,  220000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1,       "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8);
+PERIPH_CLK(disp2,       "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8);
+PERIPH_CLK(usbd,        "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb2,        "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(usb3,        "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
+PERIPH_CLK(dsia,        "tegradc.0",            "dsia", 48,     0,      500000000, mux_plld_out0,               0);
+PERIPH_CLK(csi,         "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0);
+PERIPH_CLK(isp,         "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0); /* same frequency as VI */
+PERIPH_CLK(csus,        "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET);
+PERIPH_CLK(tsensor,     "tegra-tsensor",        NULL,   100,    0x3b8,  216000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71);
+PERIPH_CLK(actmon,      "actmon",               NULL,   119,    0x3e8,  216000000, mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71);
+PERIPH_CLK(extern1,     "extern1",              NULL,   120,    0x3ec,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern2,     "extern2",              NULL,   121,    0x3f0,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern3,     "extern3",              NULL,   122,    0x3f4,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
+PERIPH_CLK(i2cslow,     "i2cslow",              NULL,   81,     0x3fc,  26000000,  mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pcie,        "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(afi,         "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0);
+PERIPH_CLK(se,          "se",                   NULL,   127,    0x42c,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT);
+
+static struct clk tegra_dsib;
+static struct clk_tegra tegra_dsib_hw = {
+        .hw = {
+                .clk = &tegra_dsib,
+        },
+        .lookup = {
+                .dev_id = "tegradc.1",
+                .con_id = "dsib",
+        },
+        .reg = 0xd0,
+        .flags = MUX | PLLD,
+        .max_rate = 500000000,
+        .u.periph = {
+                .clk_num = 82,
+        },
+        .reset = &tegra30_periph_clk_reset,
+};
+static struct clk tegra_dsib = {
+        .name = "dsib",
+        .ops = &tegra30_dsib_clk_ops,
+        .hw = &tegra_dsib_hw.hw,
+        .parent_names = mux_plld_out0_plld2_out0,
+        .parents = mux_plld_out0_plld2_out0_p,
+        .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
+};
+
+struct clk *tegra_list_clks[] = {
+        &tegra_apbdma,
+        &tegra_rtc,
+        &tegra_kbc,
+        &tegra_kfuse,
+        &tegra_fuse,
+        &tegra_fuse_burn,
+        &tegra_apbif,
+        &tegra_i2s0,
+        &tegra_i2s1,
+        &tegra_i2s2,
+        &tegra_i2s3,
+        &tegra_i2s4,
+        &tegra_spdif_out,
+        &tegra_spdif_in,
+        &tegra_pwm,
+        &tegra_d_audio,
+        &tegra_dam0,
+        &tegra_dam1,
+        &tegra_dam2,
+        &tegra_hda,
+        &tegra_hda2codec_2x,
+        &tegra_hda2hdmi,
+        &tegra_sbc1,
+        &tegra_sbc2,
+        &tegra_sbc3,
+        &tegra_sbc4,
+        &tegra_sbc5,
+        &tegra_sbc6,
+        &tegra_sata_oob,
+        &tegra_sata,
+        &tegra_sata_cold,
+        &tegra_ndflash,
+        &tegra_ndspeed,
+        &tegra_vfir,
+        &tegra_sdmmc1,
+        &tegra_sdmmc2,
+        &tegra_sdmmc3,
+        &tegra_sdmmc4,
+        &tegra_vcp,
+        &tegra_bsea,
+        &tegra_bsev,
+        &tegra_vde,
+        &tegra_csite,
+        &tegra_la,
+        &tegra_owr,
+        &tegra_nor,
+        &tegra_mipi,
+        &tegra_i2c1,
+        &tegra_i2c2,
+        &tegra_i2c3,
+        &tegra_i2c4,
+        &tegra_i2c5,
+        &tegra_uarta,
+        &tegra_uartb,
+        &tegra_uartc,
+        &tegra_uartd,
+        &tegra_uarte,
+        &tegra_vi,
+        &tegra_3d,
+        &tegra_3d2,
+        &tegra_2d,
+        &tegra_vi_sensor,
+        &tegra_epp,
+        &tegra_mpe,
+        &tegra_host1x,
+        &tegra_cve,
+        &tegra_tvo,
+        &tegra_dtv,
+        &tegra_hdmi,
+        &tegra_tvdac,
+        &tegra_disp1,
+        &tegra_disp2,
+        &tegra_usbd,
+        &tegra_usb2,
+        &tegra_usb3,
+        &tegra_dsia,
+        &tegra_dsib,
+        &tegra_csi,
+        &tegra_isp,
+        &tegra_csus,
+        &tegra_tsensor,
+        &tegra_actmon,
+        &tegra_extern1,
+        &tegra_extern2,
+        &tegra_extern3,
+        &tegra_i2cslow,
+        &tegra_pcie,
+        &tegra_afi,
+        &tegra_se,
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con)        \
+        {                                       \
+                .name   = _name,                \
+                .lookup = {                     \
+                        .dev_id = _dev,         \
+                        .con_id = _con,         \
+                },                              \
+        }
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+struct clk_duplicate tegra_clk_duplicates[] = {
+        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
+        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
+        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
+        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
+        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
+        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
+        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
+        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
+        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
+        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
+        CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
+        CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
+        CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
+        CLK_DUPLICATE("bsev", "nvavp", "bsev"),
+        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
+        CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
+        CLK_DUPLICATE("bsea", "nvavp", "bsea"),
+        CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
+        CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
+        CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
+        CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
+        CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
+        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
+        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
+        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+        CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
+        CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
+        CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
+        CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
+        CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
+        CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
+        CLK_DUPLICATE("twd", "smp_twd", NULL),
+        CLK_DUPLICATE("vcp", "nvavp", "vcp"),
+        CLK_DUPLICATE("i2s0", NULL, "i2s0"),
+        CLK_DUPLICATE("i2s1", NULL, "i2s1"),
+        CLK_DUPLICATE("i2s2", NULL, "i2s2"),
+        CLK_DUPLICATE("i2s3", NULL, "i2s3"),
+        CLK_DUPLICATE("i2s4", NULL, "i2s4"),
+        CLK_DUPLICATE("dam0", NULL, "dam0"),
+        CLK_DUPLICATE("dam1", NULL, "dam1"),
+        CLK_DUPLICATE("dam2", NULL, "dam2"),
+        CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
+};
+
+struct clk *tegra_ptr_clks[] = {
+        &tegra_clk_32k,
+        &tegra_clk_m,
+        &tegra_clk_m_div2,
+        &tegra_clk_m_div4,
+        &tegra_pll_ref,
+        &tegra_pll_m,
+        &tegra_pll_m_out1,
+        &tegra_pll_c,
+        &tegra_pll_c_out1,
+        &tegra_pll_p,
+        &tegra_pll_p_out1,
+        &tegra_pll_p_out2,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out4,
+        &tegra_pll_a,
+        &tegra_pll_a_out0,
+        &tegra_pll_d,
+        &tegra_pll_d_out0,
+        &tegra_pll_d2,
+        &tegra_pll_d2_out0,
+        &tegra_pll_u,
+        &tegra_pll_x,
+        &tegra_pll_x_out0,
+        &tegra_pll_e,
+        &tegra_clk_cclk_g,
+        &tegra_cml0,
+        &tegra_cml1,
+        &tegra_pciex,
+        &tegra_clk_sclk,
+        &tegra_clk_blink,
+        &tegra30_clk_twd,
+};
+
+static void tegra30_init_one_clock(struct clk *c)
+{
+        struct clk_tegra *clk = to_clk_tegra(c->hw);
+        __clk_init(NULL, c);
+        INIT_LIST_HEAD(&clk->shared_bus_list);
+        if (!clk->lookup.dev_id && !clk->lookup.con_id)
+                clk->lookup.con_id = c->name;
+        clk->lookup.clk = c;
+        clkdev_add(&clk->lookup);
+        tegra_clk_add(c);
+}
+
+void __init tegra30_init_clocks(void)
+{
+        int i;
+        struct clk *c;
+
+        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+                tegra30_init_one_clock(tegra_ptr_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+                tegra30_init_one_clock(tegra_list_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+                if (!c) {
+                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                                tegra_clk_duplicates[i].name);
+                        continue;
+                }
+
+                tegra_clk_duplicates[i].lookup.clk = c;
+                clkdev_add(&tegra_clk_duplicates[i].lookup);
+        }
+
+        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
+                tegra30_init_one_clock(tegra_sync_source_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
+                tegra30_init_one_clock(tegra_clk_audio_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
+                tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
+                tegra30_init_one_clock(tegra_clk_out_list[i]);
+
+        tegra30_cpu_car_ops_init();
+}
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
new file mode 100644
index 000000000000..30d063ad2bef
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_CPU_CAR_H
+#define __MACH_TEGRA_CPU_CAR_H
+
+/*
+ * Tegra CPU clock and reset control ops
+ *
+ * wait_for_reset:
+ *      keep waiting until the CPU in reset state
+ * put_in_reset:
+ *      put the CPU in reset state
+ * out_of_reset:
+ *      release the CPU from reset state
+ * enable_clock:
+ *      CPU clock un-gate
+ * disable_clock:
+ *      CPU clock gate
+ */
+struct tegra_cpu_car_ops {
+        void (*wait_for_reset)(u32 cpu);
+        void (*put_in_reset)(u32 cpu);
+        void (*out_of_reset)(u32 cpu);
+        void (*enable_clock)(u32 cpu);
+        void (*disable_clock)(u32 cpu);
+};
+
+extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
+
+static inline void tegra_wait_cpu_in_reset(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
+                return;
+
+        tegra_cpu_car_ops->wait_for_reset(cpu);
+}
+
+static inline void tegra_put_cpu_in_reset(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
+                return;
+
+        tegra_cpu_car_ops->put_in_reset(cpu);
+}
+
+static inline void tegra_cpu_out_of_reset(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
+                return;
+
+        tegra_cpu_car_ops->out_of_reset(cpu);
+}
+
+static inline void tegra_enable_cpu_clock(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
+                return;
+
+        tegra_cpu_car_ops->enable_clock(cpu);
+}
+
+static inline void tegra_disable_cpu_clock(u32 cpu)
+{
+        if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
+                return;
+
+        tegra_cpu_car_ops->disable_clock(cpu);
+}
+
+void tegra20_cpu_car_ops_init(void);
+void tegra30_cpu_car_ops_init(void);
+
+#endif /* __MACH_TEGRA_CPU_CAR_H */
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index dc12394295d5..75d5b512a3d5 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -38,7 +38,7 @@ static int __init ux500_l2x0_init(void)
 {
         u32 aux_val = 0x3e000000;
 
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                 l2x0_base = __io_address(U8500_L2CC_BASE);
         else
                 ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 7e6c384881a6..3ce7d940fc3c 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -80,7 +80,7 @@ void __init u8500_map_io(void)
 
         iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
 
-        if (cpu_is_u9540())
+        if (cpu_is_ux540_family())
                 iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
         else
                 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 8e755638aa76..2236cbd03cd7 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -51,7 +51,7 @@ void __init ux500_init_irq(void)
 
         gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
 
-        if (cpu_is_u8500_family()) {
+        if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
                 dist_base = __io_address(U8500_GIC_DIST_BASE);
                 cpu_base = __io_address(U8500_GIC_CPU_BASE);
         } else
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index c6e2db9e9e51..9c42642ab168 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -41,43 +41,29 @@ static inline bool __attribute_const__ cpu_is_u8500(void)
         return dbx500_partnumber() == 0x8500;
 }
 
-static inline bool __attribute_const__ cpu_is_u9540(void)
+static inline bool __attribute_const__ cpu_is_u8520(void)
 {
-        return dbx500_partnumber() == 0x9540;
+        return dbx500_partnumber() == 0x8520;
 }
 
 static inline bool cpu_is_u8500_family(void)
 {
-        return cpu_is_u8500() || cpu_is_u9540();
-}
-
-static inline bool __attribute_const__ cpu_is_u5500(void)
-{
-        return dbx500_partnumber() == 0x5500;
-}
-
-/*
- * 5500 revisions
- */
-
-static inline bool __attribute_const__ cpu_is_u5500v1(void)
-{
-        return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0;
+        return cpu_is_u8500() || cpu_is_u8520();
 }
 
-static inline bool __attribute_const__ cpu_is_u5500v2(void)
+static inline bool __attribute_const__ cpu_is_u9540(void)
 {
-        return (dbx500_id.revision & 0xf0) == 0xB0;
+        return dbx500_partnumber() == 0x9540;
 }
 
-static inline bool __attribute_const__ cpu_is_u5500v20(void)
+static inline bool __attribute_const__ cpu_is_u8540(void)
 {
-        return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0);
+        return dbx500_partnumber() == 0x8540;
 }
 
-static inline bool __attribute_const__ cpu_is_u5500v21(void)
+static inline bool cpu_is_ux540_family(void)
 {
-        return cpu_is_u5500() && (dbx500_revision() == 0xB1);
+        return cpu_is_u9540() || cpu_is_u8540();
 }
 
 /*
@@ -119,14 +105,14 @@ static inline bool cpu_is_u8500v21(void)
         return cpu_is_u8500() && (dbx500_revision() == 0xB1);
 }
 
+static inline bool cpu_is_u8500v22(void)
+{
+        return cpu_is_u8500() && (dbx500_revision() == 0xB2);
+}
+
 static inline bool cpu_is_u8500v20_or_later(void)
 {
-        /*
-         * U9540 has so much in common with U8500 that is is considered a
-         * U8500 variant.
-         */
-        return cpu_is_u9540() ||
-                (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
+        return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
 }
 
 static inline bool ux500_is_svp(void)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index da1d5ad5bd45..a5dda68444db 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -48,7 +48,7 @@ static void write_pen_release(int val)
 
 static void __iomem *scu_base_addr(void)
 {
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                 return __io_address(U8500_SCU_BASE);
         else
                 ux500_unknown_soc();
@@ -118,7 +118,7 @@ static void __init wakeup_secondary(void)
 {
         void __iomem *backupram;
 
-        if (cpu_is_u8500_family())
+        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                 backupram = __io_address(U8500_BACKUPRAM0_BASE);
         else
                 ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 66e7f00884ab..6f39731951b0 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -54,7 +54,7 @@ static void __init ux500_timer_init(void)
         void __iomem *tmp_base;
         struct device_node *np;
 
-        if (cpu_is_u8500_family()) {
+        if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
                 mtu_timer_base = __io_address(U8500_MTU0_BASE);
                 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
         } else {
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index d8b65b51f2a9..f79f78a1c0ed 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -512,12 +512,16 @@ enum iomux_pins {
 #define MX31_PIN_CSPI3_SPI_RDY__CTS3    IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
 #define MX31_PIN_CTS1__CTS1             IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RTS1__RTS1             IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RTS1__SFS              IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_TXD1__TXD1             IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_TXD1__SCK              IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_RXD1__RXD1             IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RXD1__STXDA            IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_DCD_DCE1__DCD_DCE1     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RI_DCE1__RI_DCE1       IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_DSR_DCE1__DSR_DCE1     IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_DTR_DCE1__DTR_DCE1     IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DTR_DCE1__SRXDA        IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
 #define MX31_PIN_CTS2__CTS2             IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_RTS2__RTS2             IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_TXD2__TXD2             IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
@@ -721,6 +725,7 @@ enum iomux_pins {
 #define MX31_PIN_KEY_ROW2_KEY_ROW2      IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW3_KEY_ROW3      IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW4_KEY_ROW4      IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW4_GPIO          IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_KEY_ROW5_KEY_ROW5      IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW6_KEY_ROW6      IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_KEY_ROW7_KEY_ROW7      IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
index 8397a2dd19f2..a8b93c5f29b5 100644
--- a/arch/arm/plat-mxc/ssi-fiq.S
+++ b/arch/arm/plat-mxc/ssi-fiq.S
@@ -34,91 +34,98 @@
                 .global imx_ssi_fiq_rx_buffer
                 .global imx_ssi_fiq_tx_buffer
 
+/*
+ * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol
+ * using ENDPROC().  imx_ssi_fiq_start and imx_ssi_fiq_end are used to
+ * mark the function body so that it can be copied to the FIQ vector in
+ * the vectors page.  imx_ssi_fiq_start should only be called as the result
+ * of an FIQ: calling it directly will not work.
+ */
 imx_ssi_fiq_start:
-                ldr r12, imx_ssi_fiq_base
+                ldr r12, .L_imx_ssi_fiq_base
 
                 /* TX */
-                ldr r11, imx_ssi_fiq_tx_buffer
+                ldr r13, .L_imx_ssi_fiq_tx_buffer
 
                 /* shall we send? */
-                ldr r13, [r12, #SSI_SIER]
-                tst r13, #SSI_SIER_TFE0_EN
+                ldr r11, [r12, #SSI_SIER]
+                tst r11, #SSI_SIER_TFE0_EN
                 beq 1f
 
                 /* TX FIFO empty? */
-                ldr r13, [r12, #SSI_SISR]
-                tst r13, #SSI_SISR_TFE0
+                ldr r11, [r12, #SSI_SISR]
+                tst r11, #SSI_SISR_TFE0
                 beq 1f
 
                 mov r10, #0x10000
                 sub r10, #1
                 and r10, r10, r8        /* r10: current buffer offset */
 
-                add r11, r11, r10
+                add r13, r13, r10
 
-                ldrh r13, [r11]
-                strh r13, [r12, #SSI_STX0]
+                ldrh r11, [r13]
+                strh r11, [r12, #SSI_STX0]
 
-                ldrh r13, [r11, #2]
-                strh r13, [r12, #SSI_STX0]
+                ldrh r11, [r13, #2]
+                strh r11, [r12, #SSI_STX0]
 
-                ldrh r13, [r11, #4]
-                strh r13, [r12, #SSI_STX0]
+                ldrh r11, [r13, #4]
+                strh r11, [r12, #SSI_STX0]
 
-                ldrh r13, [r11, #6]
-                strh r13, [r12, #SSI_STX0]
+                ldrh r11, [r13, #6]
+                strh r11, [r12, #SSI_STX0]
 
                 add r10, #8
-                lsr r13, r8, #16        /* r13: buffer size */
-                cmp r10, r13
-                lslgt r8, r13, #16
+                lsr r11, r8, #16        /* r11: buffer size */
+                cmp r10, r11
+                lslgt r8, r11, #16
                 addle r8, #8
 1:
                 /* RX */
 
                 /* shall we receive? */
-                ldr r13, [r12, #SSI_SIER]
-                tst r13, #SSI_SIER_RFF0_EN
+                ldr r11, [r12, #SSI_SIER]
+                tst r11, #SSI_SIER_RFF0_EN
                 beq 1f
 
                 /* RX FIFO full? */
-                ldr r13, [r12, #SSI_SISR]
-                tst r13, #SSI_SISR_RFF0
+                ldr r11, [r12, #SSI_SISR]
+                tst r11, #SSI_SISR_RFF0
                 beq 1f
 
-                ldr r11, imx_ssi_fiq_rx_buffer
+                ldr r13, .L_imx_ssi_fiq_rx_buffer
 
                 mov r10, #0x10000
                 sub r10, #1
                 and r10, r10, r9        /* r10: current buffer offset */
 
-                add r11, r11, r10
+                add r13, r13, r10
 
-                ldr r13, [r12, #SSI_SACNT]
-                tst r13, #SSI_SACNT_AC97EN
+                ldr r11, [r12, #SSI_SACNT]
+                tst r11, #SSI_SACNT_AC97EN
 
-                ldr r13, [r12, #SSI_SRX0]
-                strh r13, [r11]
+                ldr r11, [r12, #SSI_SRX0]
+                strh r11, [r13]
 
-                ldr r13, [r12, #SSI_SRX0]
-                strh r13, [r11, #2]
+                ldr r11, [r12, #SSI_SRX0]
+                strh r11, [r13, #2]
 
                 /* dummy read to skip slot 12 */
-                ldrne r13, [r12, #SSI_SRX0]
+                ldrne r11, [r12, #SSI_SRX0]
 
-                ldr r13, [r12, #SSI_SRX0]
-                strh r13, [r11, #4]
+                ldr r11, [r12, #SSI_SRX0]
+                strh r11, [r13, #4]
 
-                ldr r13, [r12, #SSI_SRX0]
-                strh r13, [r11, #6]
+                ldr r11, [r12, #SSI_SRX0]
+                strh r11, [r13, #6]
 
                 /* dummy read to skip slot 12 */
-                ldrne r13, [r12, #SSI_SRX0]
+                ldrne r11, [r12, #SSI_SRX0]
 
                 add r10, #8
-                lsr r13, r9, #16        /* r13: buffer size */
-                cmp r10, r13
-                lslgt r9, r13, #16
+                lsr r11, r9, #16        /* r11: buffer size */
+                cmp r10, r11
+                lslgt r9, r11, #16
                 addle r9, #8
 
 1:
@@ -126,11 +133,15 @@ imx_ssi_fiq_start:
                 subs    pc, lr, #4
 
                 .align
+.L_imx_ssi_fiq_base:
 imx_ssi_fiq_base:
                 .word 0x0
+.L_imx_ssi_fiq_rx_buffer:
 imx_ssi_fiq_rx_buffer:
                 .word 0x0
+.L_imx_ssi_fiq_tx_buffer:
 imx_ssi_fiq_tx_buffer:
                 .word 0x0
+.L_imx_ssi_fiq_end:
 imx_ssi_fiq_end:
 
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 4327b2c90c3d..e7259c0d33ec 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -60,6 +60,7 @@ extern struct dev_pm_domain omap_device_pm_domain;
  * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
  * @_state: one of OMAP_DEVICE_STATE_* (see above)
  * @flags: device flags
+ * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
  *
  * Integrates omap_hwmod data into Linux platform_device.
  *
@@ -73,6 +74,7 @@ struct omap_device {
         struct omap_device_pm_latency   *pm_lats;
         u32                             dev_wakeup_lat;
         u32                             _dev_wakeup_lat_limit;
+        unsigned long                   _driver_status;
         u8                              pm_lats_cnt;
         s8                              pm_lat_level;
         u8                              hwmods_cnt;
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 6132972aff37..9b9646c3673d 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -658,6 +658,7 @@ extern int omap2420_hwmod_init(void);
 extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
 extern int omap44xx_hwmod_init(void);
+extern int am33xx_hwmod_init(void);
 
 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
 
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index b59edb065c70..5c93c09a80c2 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -380,17 +380,21 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
                                       unsigned long event, void *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *od;
 
         switch (event) {
-        case BUS_NOTIFY_ADD_DEVICE:
-                if (pdev->dev.of_node)
-                        omap_device_build_from_dt(pdev);
-                break;
-
         case BUS_NOTIFY_DEL_DEVICE:
                 if (pdev->archdata.od)
                         omap_device_delete(pdev->archdata.od);
                 break;
+        case BUS_NOTIFY_ADD_DEVICE:
+                if (pdev->dev.of_node)
+                        omap_device_build_from_dt(pdev);
+                /* fall through */
+        default:
+                od = to_omap_device(pdev);
+                if (od)
+                        od->_driver_status = event;
         }
 
         return NOTIFY_DONE;
@@ -747,6 +751,10 @@ static int _od_suspend_noirq(struct device *dev)
         struct omap_device *od = to_omap_device(pdev);
         int ret;
 
+        /* Don't attempt late suspend on a driver that is not bound */
+        if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER)
+                return 0;
+
         ret = pm_generic_suspend_noirq(dev);
 
         if (!ret && !pm_runtime_status_suspended(dev)) {
@@ -1120,3 +1128,41 @@ static int __init omap_device_init(void)
         return 0;
 }
 core_initcall(omap_device_init);
+
+/**
+ * omap_device_late_idle - idle devices without drivers
+ * @dev: struct device * associated with omap_device
+ * @data: unused
+ *
+ * Check the driver bound status of this device, and idle it
+ * if there is no driver attached.
+ */
+static int __init omap_device_late_idle(struct device *dev, void *data)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *od = to_omap_device(pdev);
+
+        if (!od)
+                return 0;
+
+        /*
+         * If omap_device state is enabled, but has no driver bound,
+         * idle it.
+         */
+        if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
+                if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
+                        dev_warn(dev, "%s: enabled but no driver.  Idling\n",
+                                 __func__);
+                        omap_device_idle(pdev);
+                }
+        }
+
+        return 0;
+}
+
+static int __init omap_device_late_init(void)
+{
+        bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
+        return 0;
+}
+late_initcall(omap_device_late_init);
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index d1116e2dfbea..012bbd0b8d81 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -119,7 +119,7 @@ void clk_disable(struct clk *clk)
 
 unsigned long clk_get_rate(struct clk *clk)
 {
-        if (IS_ERR(clk))
+        if (IS_ERR_OR_NULL(clk))
                 return 0;
 
         if (clk->rate != 0)
@@ -136,7 +136,7 @@ unsigned long clk_get_rate(struct clk *clk)
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
-        if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)
+        if (!IS_ERR_OR_NULL(clk) && clk->ops && clk->ops->round_rate)
                 return (clk->ops->round_rate)(clk, rate);
 
         return rate;
@@ -147,7 +147,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         unsigned long flags;
         int ret;
 
-        if (IS_ERR(clk))
+        if (IS_ERR_OR_NULL(clk))
                 return -EINVAL;
 
         /* We do not default just do a clk->rate = rate as
@@ -177,7 +177,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
         unsigned long flags;
         int ret = 0;
 
-        if (IS_ERR(clk))
+        if (IS_ERR_OR_NULL(clk) || IS_ERR_OR_NULL(parent))
                 return -EINVAL;
 
         spin_lock_irqsave(&clocks_lock, flags);
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index fed07d27e0c9..8d26ce6813bb 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -51,6 +51,7 @@
 #include <plat/ehci.h>
 #include <plat/fb.h>
 #include <plat/fb-s3c2410.h>
+#include <plat/hdmi.h>
 #include <plat/hwmon.h>
 #include <plat/iic.h>
 #include <plat/keypad.h>
@@ -762,7 +763,7 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
                                &s5p_device_i2c_hdmiphy);
 }
 
-struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
+static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
 
 void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
                                   struct i2c_board_info *mhl_info, int mhl_bus)
diff --git a/drivers/Kconfig b/drivers/Kconfig
index ece958d3762e..36d3daa19a74 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -152,4 +152,6 @@ source "drivers/vme/Kconfig"
 
 source "drivers/pwm/Kconfig"
 
+source "drivers/irqchip/Kconfig"
+
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 5b421840c48d..8c30e73cd94c 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -5,6 +5,8 @@
 # Rewritten to use lists instead of if-statements.
 #
 
+obj-y                           += irqchip/
+
 # GPIO must come after pinctrl as gpios may need to mux pins etc
 obj-y                           += pinctrl/
 obj-y                           += gpio/
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b7b862077d88..2b861625bdae 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_CLKDEV_LOOKUP)	+= clkdev.o
 obj-$(CONFIG_COMMON_CLK)        += clk.o clk-fixed-rate.o clk-gate.o \
                                    clk-mux.o clk-divider.o clk-fixed-factor.o
 # SoCs specific
+obj-$(CONFIG_ARCH_BCM2835)      += clk-bcm2835.o
 obj-$(CONFIG_ARCH_NOMADIK)      += clk-nomadik.o
 obj-$(CONFIG_ARCH_HIGHBANK)     += clk-highbank.o
 obj-$(CONFIG_ARCH_MXS)          += mxs/
diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c
new file mode 100644
index 000000000000..67ad16b20b81
--- /dev/null
+++ b/drivers/clk/clk-bcm2835.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ * Copyright (C) 2012 Stephen Warren
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk/bcm2835.h>
+
+/*
+ * These are fixed clocks. They're probably not all root clocks and it may
+ * be possible to turn them on and off but until this is mapped out better
+ * it's the only way they can be used.
+ */
+void __init bcm2835_init_clocks(void)
+{
+        struct clk *clk;
+        int ret;
+
+        clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT,
+                                        250000000);
+        if (!clk)
+                pr_err("sys_pclk not registered\n");
+
+        clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT,
+                                        126000000);
+        if (!clk)
+                pr_err("apb_pclk not registered\n");
+
+        clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT,
+                                        3000000);
+        if (!clk)
+                pr_err("uart0_pclk not registered\n");
+        ret = clk_register_clkdev(clk, NULL, "20201000.uart");
+        if (ret)
+                pr_err("uart0_pclk alias not registered\n");
+
+        clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT,
+                                        125000000);
+        if (!clk)
+                pr_err("uart1_pclk not registered\n");
+        ret = clk_register_clkdev(clk, NULL, "20215000.uart");
+        if (ret)
+                pr_err("uart0_pclk alias not registered\n");
+}
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 65919901a301..603be366f762 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -13,4 +13,6 @@ obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
 obj-$(CONFIG_DW_APB_TIMER_OF)   += dw_apb_timer_of.o
 obj-$(CONFIG_CLKSRC_DBX500_PRCMU)       += clksrc-dbx500-prcmu.o
 obj-$(CONFIG_ARMADA_370_XP_TIMER)       += time-armada-370-xp.o
+obj-$(CONFIG_ARCH_BCM2835)      += bcm2835_timer.o
+
 obj-$(CONFIG_CLKSRC_ARM_GENERIC)        += arm_generic.o
diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c
new file mode 100644
index 000000000000..bc19f12c20ce
--- /dev/null
+++ b/drivers/clocksource/bcm2835_timer.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2012 Simon Arlott
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/bcm2835_timer.h>
+#include <linux/bitops.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include <asm/sched_clock.h>
+#include <asm/irq.h>
+
+#define REG_CONTROL     0x00
+#define REG_COUNTER_LO  0x04
+#define REG_COUNTER_HI  0x08
+#define REG_COMPARE(n)  (0x0c + (n) * 4)
+#define MAX_TIMER       3
+#define DEFAULT_TIMER   3
+
+struct bcm2835_timer {
+        void __iomem *control;
+        void __iomem *compare;
+        int match_mask;
+        struct clock_event_device evt;
+        struct irqaction act;
+};
+
+static void __iomem *system_clock __read_mostly;
+
+static u32 notrace bcm2835_sched_read(void)
+{
+        return readl_relaxed(system_clock);
+}
+
+static void bcm2835_time_set_mode(enum clock_event_mode mode,
+        struct clock_event_device *evt_dev)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        default:
+                WARN(1, "%s: unhandled event mode %d\n", __func__, mode);
+                break;
+        }
+}
+
+static int bcm2835_time_set_next_event(unsigned long event,
+        struct clock_event_device *evt_dev)
+{
+        struct bcm2835_timer *timer = container_of(evt_dev,
+                struct bcm2835_timer, evt);
+        writel_relaxed(readl_relaxed(system_clock) + event,
+                timer->compare);
+        return 0;
+}
+
+static irqreturn_t bcm2835_time_interrupt(int irq, void *dev_id)
+{
+        struct bcm2835_timer *timer = dev_id;
+        void (*event_handler)(struct clock_event_device *);
+        if (readl_relaxed(timer->control) & timer->match_mask) {
+                writel_relaxed(timer->match_mask, timer->control);
+
+                event_handler = ACCESS_ONCE(timer->evt.event_handler);
+                if (event_handler)
+                        event_handler(&timer->evt);
+                return IRQ_HANDLED;
+        } else {
+                return IRQ_NONE;
+        }
+}
+
+static struct of_device_id bcm2835_time_match[] __initconst = {
+        { .compatible = "brcm,bcm2835-system-timer" },
+        {}
+};
+
+static void __init bcm2835_time_init(void)
+{
+        struct device_node *node;
+        void __iomem *base;
+        u32 freq;
+        int irq;
+        struct bcm2835_timer *timer;
+
+        node = of_find_matching_node(NULL, bcm2835_time_match);
+        if (!node)
+                panic("No bcm2835 timer node");
+
+        base = of_iomap(node, 0);
+        if (!base)
+                panic("Can't remap registers");
+
+        if (of_property_read_u32(node, "clock-frequency", &freq))
+                panic("Can't read clock-frequency");
+
+        system_clock = base + REG_COUNTER_LO;
+        setup_sched_clock(bcm2835_sched_read, 32, freq);
+
+        clocksource_mmio_init(base + REG_COUNTER_LO, node->name,
+                freq, 300, 32, clocksource_mmio_readl_up);
+
+        irq = irq_of_parse_and_map(node, DEFAULT_TIMER);
+        if (irq <= 0)
+                panic("Can't parse IRQ");
+
+        timer = kzalloc(sizeof(*timer), GFP_KERNEL);
+        if (!timer)
+                panic("Can't allocate timer struct\n");
+
+        timer->control = base + REG_CONTROL;
+        timer->compare = base + REG_COMPARE(DEFAULT_TIMER);
+        timer->match_mask = BIT(DEFAULT_TIMER);
+        timer->evt.name = node->name;
+        timer->evt.rating = 300;
+        timer->evt.features = CLOCK_EVT_FEAT_ONESHOT;
+        timer->evt.set_mode = bcm2835_time_set_mode;
+        timer->evt.set_next_event = bcm2835_time_set_next_event;
+        timer->evt.cpumask = cpumask_of(0);
+        timer->act.name = node->name;
+        timer->act.flags = IRQF_TIMER | IRQF_SHARED;
+        timer->act.dev_id = timer;
+        timer->act.handler = bcm2835_time_interrupt;
+
+        if (setup_irq(irq, &timer->act))
+                panic("Can't set up timer IRQ\n");
+
+        clockevents_config_and_register(&timer->evt, freq, 0xf, 0xffffffff);
+
+        pr_info("bcm2835: system timer (irq = %d)\n", irq);
+}
+
+struct sys_timer bcm2835_timer = {
+        .init = bcm2835_time_init,
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
new file mode 100644
index 000000000000..1bb8bf6d7fd4
--- /dev/null
+++ b/drivers/irqchip/Kconfig
@@ -0,0 +1 @@
+# empty
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
new file mode 100644
index 000000000000..054321db4350
--- /dev/null
+++ b/drivers/irqchip/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c
new file mode 100644
index 000000000000..dc670ccc6978
--- /dev/null
+++ b/drivers/irqchip/irq-bcm2835.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2010 Broadcom
+ * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
+ *
+ * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
+ * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
+ * to look in the bank 1 status register for more information.
+ *
+ * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
+ * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
+ * status register, but bank 0 bit 8 is _not_ set.
+ *
+ * Quirk 2: You can't mask the register 1/2 pending interrupts
+ *
+ * In a proper cascaded interrupt controller, the interrupt lines with
+ * cascaded interrupt controllers on them are just normal interrupt lines.
+ * You can mask the interrupts and get on with things. With this controller
+ * you can't do that.
+ *
+ * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
+ *
+ * Those interrupts that have shortcuts can only be masked/unmasked in
+ * their respective banks' enable/disable registers. Doing so in the bank 0
+ * enable/disable registers has no effect.
+ *
+ * The FIQ control register:
+ *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
+ *  Bit    7: Enable FIQ generation
+ *  Bits  8+: Unused
+ *
+ * An interrupt must be disabled before configuring it for FIQ generation
+ * otherwise both handlers will fire at the same time!
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip/bcm2835.h>
+
+#include <asm/exception.h>
+
+/* Put the bank and irq (32 bits) into the hwirq */
+#define MAKE_HWIRQ(b, n)        ((b << 5) | (n))
+#define HWIRQ_BANK(i)           (i >> 5)
+#define HWIRQ_BIT(i)            BIT(i & 0x1f)
+
+#define NR_IRQS_BANK0           8
+#define BANK0_HWIRQ_MASK        0xff
+/* Shortcuts can't be disabled so any unknown new ones need to be masked */
+#define SHORTCUT1_MASK          0x00007c00
+#define SHORTCUT2_MASK          0x001f8000
+#define SHORTCUT_SHIFT          10
+#define BANK1_HWIRQ             BIT(8)
+#define BANK2_HWIRQ             BIT(9)
+#define BANK0_VALID_MASK        (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
+                                        | SHORTCUT1_MASK | SHORTCUT2_MASK)
+
+#define REG_FIQ_CONTROL         0x0c
+
+#define NR_BANKS                3
+#define IRQS_PER_BANK           32
+
+static int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
+static int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
+static int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
+static int bank_irqs[] __initconst = { 8, 32, 32 };
+
+static const int shortcuts[] = {
+        7, 9, 10, 18, 19,               /* Bank 1 */
+        21, 22, 23, 24, 25, 30          /* Bank 2 */
+};
+
+struct armctrl_ic {
+        void __iomem *base;
+        void __iomem *pending[NR_BANKS];
+        void __iomem *enable[NR_BANKS];
+        void __iomem *disable[NR_BANKS];
+        struct irq_domain *domain;
+};
+
+static struct armctrl_ic intc __read_mostly;
+
+static void armctrl_mask_irq(struct irq_data *d)
+{
+        writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
+}
+
+static void armctrl_unmask_irq(struct irq_data *d)
+{
+        writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
+}
+
+static struct irq_chip armctrl_chip = {
+        .name = "ARMCTRL-level",
+        .irq_mask = armctrl_mask_irq,
+        .irq_unmask = armctrl_unmask_irq
+};
+
+static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
+        const u32 *intspec, unsigned int intsize,
+        unsigned long *out_hwirq, unsigned int *out_type)
+{
+        if (WARN_ON(intsize != 2))
+                return -EINVAL;
+
+        if (WARN_ON(intspec[0] >= NR_BANKS))
+                return -EINVAL;
+
+        if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
+                return -EINVAL;
+
+        if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
+                return -EINVAL;
+
+        *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
+        *out_type = IRQ_TYPE_NONE;
+        return 0;
+}
+
+static struct irq_domain_ops armctrl_ops = {
+        .xlate = armctrl_xlate
+};
+
+static int __init armctrl_of_init(struct device_node *node,
+        struct device_node *parent)
+{
+        void __iomem *base;
+        int irq, b, i;
+
+        base = of_iomap(node, 0);
+        if (!base)
+                panic("%s: unable to map IC registers\n",
+                        node->full_name);
+
+        intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
+                        &armctrl_ops, NULL);
+        if (!intc.domain)
+                panic("%s: unable to create IRQ domain\n", node->full_name);
+
+        for (b = 0; b < NR_BANKS; b++) {
+                intc.pending[b] = base + reg_pending[b];
+                intc.enable[b] = base + reg_enable[b];
+                intc.disable[b] = base + reg_disable[b];
+
+                for (i = 0; i < bank_irqs[b]; i++) {
+                        irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
+                        BUG_ON(irq <= 0);
+                        irq_set_chip_and_handler(irq, &armctrl_chip,
+                                handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
+        }
+        return 0;
+}
+
+static struct of_device_id irq_of_match[] __initconst = {
+        { .compatible = "brcm,bcm2835-armctrl-ic", .data = armctrl_of_init }
+};
+
+void __init bcm2835_init_irq(void)
+{
+        of_irq_init(irq_of_match);
+}
+
+/*
+ * Handle each interrupt across the entire interrupt controller.  This reads the
+ * status register before handling each interrupt, which is necessary given that
+ * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
+ */
+
+static void armctrl_handle_bank(int bank, struct pt_regs *regs)
+{
+        u32 stat, irq;
+
+        while ((stat = readl_relaxed(intc.pending[bank]))) {
+                irq = MAKE_HWIRQ(bank, ffs(stat) - 1);
+                handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
+        }
+}
+
+static void armctrl_handle_shortcut(int bank, struct pt_regs *regs,
+        u32 stat)
+{
+        u32 irq = MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
+        handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
+}
+
+asmlinkage void __exception_irq_entry bcm2835_handle_irq(
+        struct pt_regs *regs)
+{
+        u32 stat, irq;
+
+        while ((stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK)) {
+                if (stat & BANK0_HWIRQ_MASK) {
+                        irq = MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
+                        handle_IRQ(irq_linear_revmap(intc.domain, irq), regs);
+                } else if (stat & SHORTCUT1_MASK) {
+                        armctrl_handle_shortcut(1, regs, stat & SHORTCUT1_MASK);
+                } else if (stat & SHORTCUT2_MASK) {
+                        armctrl_handle_shortcut(2, regs, stat & SHORTCUT2_MASK);
+                } else if (stat & BANK1_HWIRQ) {
+                        armctrl_handle_bank(1, regs);
+                } else if (stat & BANK2_HWIRQ) {
+                        armctrl_handle_bank(2, regs);
+                } else {
+                        BUG();
+                }
+        }
+}
diff --git a/include/linux/bcm2835_timer.h b/include/linux/bcm2835_timer.h
new file mode 100644
index 000000000000..25680fe0903c
--- /dev/null
+++ b/include/linux/bcm2835_timer.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2012 Simon Arlott
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BCM2835_TIMER_H
+#define __BCM2835_TIMER_H
+
+#include <asm/mach/time.h>
+
+extern struct sys_timer bcm2835_timer;
+
+#endif
diff --git a/include/linux/clk/bcm2835.h b/include/linux/clk/bcm2835.h
new file mode 100644
index 000000000000..aa937f6c17da
--- /dev/null
+++ b/include/linux/clk/bcm2835.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_CLK_BCM2835_H_
+#define __LINUX_CLK_BCM2835_H_
+
+void __init bcm2835_init_clocks(void);
+
+#endif
diff --git a/include/linux/irqchip/bcm2835.h b/include/linux/irqchip/bcm2835.h
new file mode 100644
index 000000000000..48a859bc9dca
--- /dev/null
+++ b/include/linux/irqchip/bcm2835.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2010 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __LINUX_IRQCHIP_BCM2835_H_
+#define __LINUX_IRQCHIP_BCM2835_H_
+
+#include <asm/exception.h>
+
+extern void bcm2835_init_irq(void);
+
+extern asmlinkage void __exception_irq_entry bcm2835_handle_irq(
+        struct pt_regs *regs);
+
+#endif