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-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/mach-ux500/board-mop500.c19
-rw-r--r--drivers/pinctrl/Kconfig7
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/pinctrl-abx500.c1233
-rw-r--r--drivers/pinctrl/pinctrl-abx500.h180
-rw-r--r--include/linux/mfd/abx500/ab8500-gpio.h15
-rw-r--r--include/linux/mfd/abx500/ab8500.h2
8 files changed, 1437 insertions, 21 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 1d7dbe61a958..018bf681659d 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
11 select COMMON_CLK 11 select COMMON_CLK
12 select PINCTRL 12 select PINCTRL
13 select PINCTRL_NOMADIK 13 select PINCTRL_NOMADIK
14 select PINCTRL_ABX500
14 select PL310_ERRATA_753970 if CACHE_PL310 15 select PL310_ERRATA_753970 if CACHE_PL310
15 16
16config UX500_SOC_DB8500 17config UX500_SOC_DB8500
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index d453522edb0d..b6f14ee507ca 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -90,26 +90,9 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
90 }, 90 },
91}; 91};
92 92
93static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { 93static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
94 .gpio_base = MOP500_AB8500_PIN_GPIO(1), 94 .gpio_base = MOP500_AB8500_PIN_GPIO(1),
95 .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE, 95 .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
96 /* config_reg is the initial configuration of ab8500 pins.
97 * The pins can be configured as GPIO or alt functions based
98 * on value present in GpioSel1 to GpioSel6 and AlternatFunction
99 * register. This is the array of 7 configuration settings.
100 * One has to compile time decide these settings. Below is the
101 * explanation of these setting
102 * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
103 * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
104 * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
105 * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO
106 * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO
107 * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO
108 * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured
109 * as GPIO then this register selectes the alternate fucntions
110 */
111 .config_reg = {0x00, 0x1E, 0x80, 0x01,
112 0x7A, 0x00, 0x00},
113}; 96};
114 97
115/* ab8500-codec */ 98/* ab8500-codec */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 881ddcd00236..ba3038c827c6 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -26,6 +26,13 @@ config DEBUG_PINCTRL
26 help 26 help
27 Say Y here to add some extra checks and diagnostics to PINCTRL calls. 27 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
28 28
29config PINCTRL_ABX500
30 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions"
31 depends on AB8500_CORE
32 select GENERIC_PINCONF
33 help
34 Select this to enable the ABx500 family IC GPIO driver
35
29config PINCTRL_AT91 36config PINCTRL_AT91
30 bool "AT91 pinctrl driver" 37 bool "AT91 pinctrl driver"
31 depends on OF 38 depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index e9ad8c3851be..ead4fa7dfd1f 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,6 +9,7 @@ ifeq ($(CONFIG_OF),y)
9obj-$(CONFIG_PINCTRL) += devicetree.o 9obj-$(CONFIG_PINCTRL) += devicetree.o
10endif 10endif
11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o 11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o
12obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o 13obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
13obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 14obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
14obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o 15obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
new file mode 100644
index 000000000000..9eed9887da2a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -0,0 +1,1233 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2013
3 *
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/gpio.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/bitops.h>
22#include <linux/mfd/abx500.h>
23#include <linux/mfd/abx500/ab8500.h>
24#include <linux/mfd/abx500/ab8500-gpio.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/consumer.h>
27#include <linux/pinctrl/pinmux.h>
28#include <linux/pinctrl/pinconf.h>
29#include <linux/pinctrl/pinconf-generic.h>
30
31#include "pinctrl-abx500.h"
32
33/*
34 * The AB9540 and AB8540 GPIO support are extended versions
35 * of the AB8500 GPIO support.
36 * The AB9540 supports an additional (7th) register so that
37 * more GPIO may be configured and used.
38 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
39 * internal pull-up and pull-down capabilities.
40 */
41
42/*
43 * GPIO registers offset
44 * Bank: 0x10
45 */
46#define AB8500_GPIO_SEL1_REG 0x00
47#define AB8500_GPIO_SEL2_REG 0x01
48#define AB8500_GPIO_SEL3_REG 0x02
49#define AB8500_GPIO_SEL4_REG 0x03
50#define AB8500_GPIO_SEL5_REG 0x04
51#define AB8500_GPIO_SEL6_REG 0x05
52#define AB9540_GPIO_SEL7_REG 0x06
53
54#define AB8500_GPIO_DIR1_REG 0x10
55#define AB8500_GPIO_DIR2_REG 0x11
56#define AB8500_GPIO_DIR3_REG 0x12
57#define AB8500_GPIO_DIR4_REG 0x13
58#define AB8500_GPIO_DIR5_REG 0x14
59#define AB8500_GPIO_DIR6_REG 0x15
60#define AB9540_GPIO_DIR7_REG 0x16
61
62#define AB8500_GPIO_OUT1_REG 0x20
63#define AB8500_GPIO_OUT2_REG 0x21
64#define AB8500_GPIO_OUT3_REG 0x22
65#define AB8500_GPIO_OUT4_REG 0x23
66#define AB8500_GPIO_OUT5_REG 0x24
67#define AB8500_GPIO_OUT6_REG 0x25
68#define AB9540_GPIO_OUT7_REG 0x26
69
70#define AB8500_GPIO_PUD1_REG 0x30
71#define AB8500_GPIO_PUD2_REG 0x31
72#define AB8500_GPIO_PUD3_REG 0x32
73#define AB8500_GPIO_PUD4_REG 0x33
74#define AB8500_GPIO_PUD5_REG 0x34
75#define AB8500_GPIO_PUD6_REG 0x35
76#define AB9540_GPIO_PUD7_REG 0x36
77
78#define AB8500_GPIO_IN1_REG 0x40
79#define AB8500_GPIO_IN2_REG 0x41
80#define AB8500_GPIO_IN3_REG 0x42
81#define AB8500_GPIO_IN4_REG 0x43
82#define AB8500_GPIO_IN5_REG 0x44
83#define AB8500_GPIO_IN6_REG 0x45
84#define AB9540_GPIO_IN7_REG 0x46
85#define AB8540_GPIO_VINSEL_REG 0x47
86#define AB8540_GPIO_PULL_UPDOWN_REG 0x48
87#define AB8500_GPIO_ALTFUN_REG 0x50
88#define AB8500_NUM_VIR_GPIO_IRQ 16
89#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
90#define AB8540_GPIO_VINSEL_MASK 0x03
91#define AB8540_GPIOX_VBAT_START 51
92#define AB8540_GPIOX_VBAT_END 54
93
94enum abx500_gpio_action {
95 NONE,
96 STARTUP,
97 SHUTDOWN,
98 MASK,
99 UNMASK
100};
101
102struct abx500_pinctrl {
103 struct device *dev;
104 struct pinctrl_dev *pctldev;
105 struct abx500_pinctrl_soc_data *soc;
106 struct gpio_chip chip;
107 struct ab8500 *parent;
108 struct mutex lock;
109 u32 irq_base;
110 enum abx500_gpio_action irq_action;
111 u16 rising;
112 u16 falling;
113 struct abx500_gpio_irq_cluster *irq_cluster;
114 int irq_cluster_size;
115 int irq_gpio_rising_offset;
116 int irq_gpio_falling_offset;
117 int irq_gpio_factor;
118};
119
120/**
121 * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
122 * @chip: Member of the structure abx500_pinctrl
123 */
124static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
125{
126 return container_of(chip, struct abx500_pinctrl, chip);
127}
128
129static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
130 unsigned offset, bool *bit)
131{
132 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
133 u8 pos = offset % 8;
134 u8 val;
135 int ret;
136
137 reg += offset / 8;
138 ret = abx500_get_register_interruptible(pct->dev,
139 AB8500_MISC, reg, &val);
140
141 *bit = !!(val & BIT(pos));
142
143 if (ret < 0)
144 dev_err(pct->dev,
145 "%s read reg =%x, offset=%x failed\n",
146 __func__, reg, offset);
147
148 return ret;
149}
150
151static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
152 unsigned offset, int val)
153{
154 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
155 u8 pos = offset % 8;
156 int ret;
157
158 reg += offset / 8;
159 ret = abx500_mask_and_set_register_interruptible(pct->dev,
160 AB8500_MISC, reg, 1 << pos, val << pos);
161 if (ret < 0)
162 dev_err(pct->dev, "%s write failed\n", __func__);
163 return ret;
164}
165/**
166 * abx500_gpio_get() - Get the particular GPIO value
167 * @chip: Gpio device
168 * @offset: GPIO number to read
169 */
170static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
171{
172 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
173 bool bit;
174 int ret;
175
176 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
177 offset, &bit);
178 if (ret < 0) {
179 dev_err(pct->dev, "%s failed\n", __func__);
180 return ret;
181 }
182 return bit;
183}
184
185static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
186{
187 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
188 int ret;
189
190 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
191 if (ret < 0)
192 dev_err(pct->dev, "%s write failed\n", __func__);
193}
194
195static int abx500_config_pull_updown(struct abx500_pinctrl *pct,
196 int offset, enum abx500_gpio_pull_updown val)
197{
198 u8 pos;
199 int ret;
200 struct pullud *pullud;
201
202 if (!pct->soc->pullud) {
203 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
204 __func__);
205 ret = -EPERM;
206 goto out;
207 }
208
209 pullud = pct->soc->pullud;
210
211 if ((offset < pullud->first_pin)
212 || (offset > pullud->last_pin)) {
213 ret = -EINVAL;
214 goto out;
215 }
216
217 pos = offset << 1;
218
219 ret = abx500_mask_and_set_register_interruptible(pct->dev,
220 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
221 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
222
223out:
224 if (ret < 0)
225 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
226 return ret;
227}
228
229static int abx500_gpio_direction_output(struct gpio_chip *chip,
230 unsigned offset,
231 int val)
232{
233 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
234 struct pullud *pullud = pct->soc->pullud;
235 unsigned gpio;
236 int ret;
237 /* set direction as output */
238 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
239 if (ret < 0)
240 return ret;
241
242 /* disable pull down */
243 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
244 if (ret < 0)
245 return ret;
246
247 /* if supported, disable both pull down and pull up */
248 gpio = offset + 1;
249 if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) {
250 ret = abx500_config_pull_updown(pct,
251 gpio,
252 ABX500_GPIO_PULL_NONE);
253 if (ret < 0)
254 return ret;
255 }
256 /* set the output as 1 or 0 */
257 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
258}
259
260static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
261{
262 /* set the register as input */
263 return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
264}
265
266static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
267{
268 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
269 int base = pct->irq_base;
270 int i;
271
272 for (i = 0; i < pct->irq_cluster_size; i++) {
273 struct abx500_gpio_irq_cluster *cluster =
274 &pct->irq_cluster[i];
275
276 if (offset >= cluster->start && offset <= cluster->end)
277 return base + offset - cluster->start;
278
279 /* Advance by the number of gpios in this cluster */
280 base += cluster->end + cluster->offset - cluster->start + 1;
281 }
282
283 return -EINVAL;
284}
285
286static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
287 unsigned gpio, int alt_setting)
288{
289 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
290 struct alternate_functions af = pct->soc->alternate_functions[gpio];
291 int ret;
292 int val;
293 unsigned offset;
294 const char *modes[] = {
295 [ABX500_DEFAULT] = "default",
296 [ABX500_ALT_A] = "altA",
297 [ABX500_ALT_B] = "altB",
298 [ABX500_ALT_C] = "altC",
299 };
300
301 /* sanity check */
302 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
303 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
304 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
305 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
306 modes[alt_setting]);
307 return -EINVAL;
308 }
309
310 /* on ABx5xx, there is no GPIO0, so adjust the offset */
311 offset = gpio - 1;
312 switch (alt_setting) {
313 case ABX500_DEFAULT:
314 /*
315 * for ABx5xx family, default mode is always selected by
316 * writing 0 to GPIOSELx register, except for pins which
317 * support at least ALT_B mode, default mode is selected
318 * by writing 1 to GPIOSELx register
319 */
320 val = 0;
321 if (af.alt_bit1 != UNUSED)
322 val++;
323
324 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
325 offset, val);
326 break;
327 case ABX500_ALT_A:
328 /*
329 * for ABx5xx family, alt_a mode is always selected by
330 * writing 1 to GPIOSELx register, except for pins which
331 * support at least ALT_B mode, alt_a mode is selected
332 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
333 * register
334 */
335 if (af.alt_bit1 != UNUSED) {
336 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
337 offset, 0);
338 ret = abx500_gpio_set_bits(chip,
339 AB8500_GPIO_ALTFUN_REG,
340 af.alt_bit1,
341 !!(af.alta_val && BIT(0)));
342 if (af.alt_bit2 != UNUSED)
343 ret = abx500_gpio_set_bits(chip,
344 AB8500_GPIO_ALTFUN_REG,
345 af.alt_bit2,
346 !!(af.alta_val && BIT(1)));
347 } else
348 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
349 offset, 1);
350 break;
351 case ABX500_ALT_B:
352 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
353 offset, 0);
354 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
355 af.alt_bit1, !!(af.altb_val && BIT(0)));
356 if (af.alt_bit2 != UNUSED)
357 ret = abx500_gpio_set_bits(chip,
358 AB8500_GPIO_ALTFUN_REG,
359 af.alt_bit2,
360 !!(af.altb_val && BIT(1)));
361 break;
362 case ABX500_ALT_C:
363 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
364 offset, 0);
365 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
366 af.alt_bit2, !!(af.altc_val && BIT(0)));
367 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
368 af.alt_bit2, !!(af.altc_val && BIT(1)));
369 break;
370
371 default:
372 dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting);
373 return -EINVAL;
374 }
375 return ret;
376}
377
378static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
379 unsigned gpio)
380{
381 u8 mode;
382 bool bit_mode;
383 bool alt_bit1;
384 bool alt_bit2;
385 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
386 struct alternate_functions af = pct->soc->alternate_functions[gpio];
387
388 /*
389 * if gpiosel_bit is set to unused,
390 * it means no GPIO or special case
391 */
392 if (af.gpiosel_bit == UNUSED)
393 return ABX500_DEFAULT;
394
395 /* read GpioSelx register */
396 abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (gpio / 8),
397 af.gpiosel_bit, &bit_mode);
398 mode = bit_mode;
399
400 /* sanity check */
401 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
402 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
403 dev_err(pct->dev,
404 "alt_bitX value not in correct range (-1 to 7)\n");
405 return -EINVAL;
406 }
407 /* if alt_bit2 is used, alt_bit1 must be used too */
408 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
409 dev_err(pct->dev,
410 "if alt_bit2 is used, alt_bit1 can't be unused\n");
411 return -EINVAL;
412 }
413
414 /* check if pin use AlternateFunction register */
415 if ((af.alt_bit1 == UNUSED) && (af.alt_bit1 == UNUSED))
416 return mode;
417 /*
418 * if pin GPIOSEL bit is set and pin supports alternate function,
419 * it means DEFAULT mode
420 */
421 if (mode)
422 return ABX500_DEFAULT;
423 /*
424 * pin use the AlternatFunction register
425 * read alt_bit1 value
426 */
427 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
428 af.alt_bit1, &alt_bit1);
429
430 if (af.alt_bit2 != UNUSED)
431 /* read alt_bit2 value */
432 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2,
433 &alt_bit2);
434 else
435 alt_bit2 = 0;
436
437 mode = (alt_bit2 << 1) + alt_bit1;
438 if (mode == af.alta_val)
439 return ABX500_ALT_A;
440 else if (mode == af.altb_val)
441 return ABX500_ALT_B;
442 else
443 return ABX500_ALT_C;
444}
445
446#ifdef CONFIG_DEBUG_FS
447
448#include <linux/seq_file.h>
449
450static void abx500_gpio_dbg_show_one(struct seq_file *s,
451 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
452 unsigned offset, unsigned gpio)
453{
454 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
455 const char *label = gpiochip_is_requested(chip, offset - 1);
456 u8 gpio_offset = offset - 1;
457 int mode = -1;
458 bool is_out;
459 bool pull;
460 const char *modes[] = {
461 [ABX500_DEFAULT] = "default",
462 [ABX500_ALT_A] = "altA",
463 [ABX500_ALT_B] = "altB",
464 [ABX500_ALT_C] = "altC",
465 };
466
467 abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out);
468 abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull);
469
470 if (pctldev)
471 mode = abx500_get_mode(pctldev, chip, offset);
472
473 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s",
474 gpio, label ?: "(none)",
475 is_out ? "out" : "in ",
476 is_out ?
477 (chip->get
478 ? (chip->get(chip, offset) ? "hi" : "lo")
479 : "? ")
480 : (pull ? "pull up" : "pull down"),
481 (mode < 0) ? "unknown" : modes[mode]);
482
483 if (label && !is_out) {
484 int irq = gpio_to_irq(gpio);
485 struct irq_desc *desc = irq_to_desc(irq);
486
487 if (irq >= 0 && desc->action) {
488 char *trigger;
489 int irq_offset = irq - pct->irq_base;
490
491 if (pct->rising & BIT(irq_offset))
492 trigger = "edge-rising";
493 else if (pct->falling & BIT(irq_offset))
494 trigger = "edge-falling";
495 else
496 trigger = "edge-undefined";
497
498 seq_printf(s, " irq-%d %s", irq, trigger);
499 }
500 }
501}
502
503static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
504{
505 unsigned i;
506 unsigned gpio = chip->base;
507 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
508 struct pinctrl_dev *pctldev = pct->pctldev;
509
510 for (i = 0; i < chip->ngpio; i++, gpio++) {
511 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
512 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
513 seq_printf(s, "\n");
514 }
515}
516
517#else
518static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
519 struct pinctrl_dev *pctldev,
520 struct gpio_chip *chip,
521 unsigned offset, unsigned gpio)
522{
523}
524#define abx500_gpio_dbg_show NULL
525#endif
526
527int abx500_gpio_request(struct gpio_chip *chip, unsigned offset)
528{
529 int gpio = chip->base + offset;
530
531 return pinctrl_request_gpio(gpio);
532}
533
534void abx500_gpio_free(struct gpio_chip *chip, unsigned offset)
535{
536 int gpio = chip->base + offset;
537
538 pinctrl_free_gpio(gpio);
539}
540
541static struct gpio_chip abx500gpio_chip = {
542 .label = "abx500-gpio",
543 .owner = THIS_MODULE,
544 .request = abx500_gpio_request,
545 .free = abx500_gpio_free,
546 .direction_input = abx500_gpio_direction_input,
547 .get = abx500_gpio_get,
548 .direction_output = abx500_gpio_direction_output,
549 .set = abx500_gpio_set,
550 .to_irq = abx500_gpio_to_irq,
551 .dbg_show = abx500_gpio_dbg_show,
552};
553
554static unsigned int irq_to_rising(unsigned int irq)
555{
556 struct abx500_pinctrl *pct = irq_get_chip_data(irq);
557 int offset = irq - pct->irq_base;
558 int new_irq;
559
560 new_irq = offset * pct->irq_gpio_factor
561 + pct->irq_gpio_rising_offset
562 + pct->parent->irq_base;
563
564 return new_irq;
565}
566
567static unsigned int irq_to_falling(unsigned int irq)
568{
569 struct abx500_pinctrl *pct = irq_get_chip_data(irq);
570 int offset = irq - pct->irq_base;
571 int new_irq;
572
573 new_irq = offset * pct->irq_gpio_factor
574 + pct->irq_gpio_falling_offset
575 + pct->parent->irq_base;
576 return new_irq;
577
578}
579
580static unsigned int rising_to_irq(unsigned int irq, void *dev)
581{
582 struct abx500_pinctrl *pct = dev;
583 int offset, new_irq;
584
585 offset = irq - pct->irq_gpio_rising_offset
586 - pct->parent->irq_base;
587 new_irq = (offset / pct->irq_gpio_factor)
588 + pct->irq_base;
589
590 return new_irq;
591}
592
593static unsigned int falling_to_irq(unsigned int irq, void *dev)
594{
595 struct abx500_pinctrl *pct = dev;
596 int offset, new_irq;
597
598 offset = irq - pct->irq_gpio_falling_offset
599 - pct->parent->irq_base;
600 new_irq = (offset / pct->irq_gpio_factor)
601 + pct->irq_base;
602
603 return new_irq;
604}
605
606/*
607 * IRQ handler
608 */
609
610static irqreturn_t handle_rising(int irq, void *dev)
611{
612
613 handle_nested_irq(rising_to_irq(irq , dev));
614 return IRQ_HANDLED;
615}
616
617static irqreturn_t handle_falling(int irq, void *dev)
618{
619
620 handle_nested_irq(falling_to_irq(irq, dev));
621 return IRQ_HANDLED;
622}
623
624static void abx500_gpio_irq_lock(struct irq_data *data)
625{
626 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
627 mutex_lock(&pct->lock);
628}
629
630static void abx500_gpio_irq_sync_unlock(struct irq_data *data)
631{
632 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
633 unsigned int irq = data->irq;
634 int offset = irq - pct->irq_base;
635 bool rising = pct->rising & BIT(offset);
636 bool falling = pct->falling & BIT(offset);
637 int ret;
638
639 switch (pct->irq_action) {
640 case STARTUP:
641 if (rising)
642 ret = request_threaded_irq(irq_to_rising(irq),
643 NULL, handle_rising,
644 IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND,
645 "abx500-gpio-r", pct);
646 if (falling)
647 ret = request_threaded_irq(irq_to_falling(irq),
648 NULL, handle_falling,
649 IRQF_TRIGGER_FALLING | IRQF_NO_SUSPEND,
650 "abx500-gpio-f", pct);
651 break;
652 case SHUTDOWN:
653 if (rising)
654 free_irq(irq_to_rising(irq), pct);
655 if (falling)
656 free_irq(irq_to_falling(irq), pct);
657 break;
658 case MASK:
659 if (rising)
660 disable_irq(irq_to_rising(irq));
661 if (falling)
662 disable_irq(irq_to_falling(irq));
663 break;
664 case UNMASK:
665 if (rising)
666 enable_irq(irq_to_rising(irq));
667 if (falling)
668 enable_irq(irq_to_falling(irq));
669 break;
670 case NONE:
671 break;
672 }
673 pct->irq_action = NONE;
674 pct->rising &= ~(BIT(offset));
675 pct->falling &= ~(BIT(offset));
676 mutex_unlock(&pct->lock);
677}
678
679
680static void abx500_gpio_irq_mask(struct irq_data *data)
681{
682 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
683 pct->irq_action = MASK;
684}
685
686static void abx500_gpio_irq_unmask(struct irq_data *data)
687{
688 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
689 pct->irq_action = UNMASK;
690}
691
692static int abx500_gpio_irq_set_type(struct irq_data *data, unsigned int type)
693{
694 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
695 unsigned int irq = data->irq;
696 int offset = irq - pct->irq_base;
697
698 if (type == IRQ_TYPE_EDGE_BOTH) {
699 pct->rising = BIT(offset);
700 pct->falling = BIT(offset);
701 } else if (type == IRQ_TYPE_EDGE_RISING) {
702 pct->rising = BIT(offset);
703 } else {
704 pct->falling = BIT(offset);
705 }
706 return 0;
707}
708
709static unsigned int abx500_gpio_irq_startup(struct irq_data *data)
710{
711 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
712 pct->irq_action = STARTUP;
713 return 0;
714}
715
716static void abx500_gpio_irq_shutdown(struct irq_data *data)
717{
718 struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data);
719 pct->irq_action = SHUTDOWN;
720}
721
722static struct irq_chip abx500_gpio_irq_chip = {
723 .name = "abx500-gpio",
724 .irq_startup = abx500_gpio_irq_startup,
725 .irq_shutdown = abx500_gpio_irq_shutdown,
726 .irq_bus_lock = abx500_gpio_irq_lock,
727 .irq_bus_sync_unlock = abx500_gpio_irq_sync_unlock,
728 .irq_mask = abx500_gpio_irq_mask,
729 .irq_unmask = abx500_gpio_irq_unmask,
730 .irq_set_type = abx500_gpio_irq_set_type,
731};
732
733static int abx500_gpio_irq_init(struct abx500_pinctrl *pct)
734{
735 u32 base = pct->irq_base;
736 int irq;
737
738 for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ ; irq++) {
739 irq_set_chip_data(irq, pct);
740 irq_set_chip_and_handler(irq, &abx500_gpio_irq_chip,
741 handle_simple_irq);
742 irq_set_nested_thread(irq, 1);
743#ifdef CONFIG_ARM
744 set_irq_flags(irq, IRQF_VALID);
745#else
746 irq_set_noprobe(irq);
747#endif
748 }
749
750 return 0;
751}
752
753static void abx500_gpio_irq_remove(struct abx500_pinctrl *pct)
754{
755 int base = pct->irq_base;
756 int irq;
757
758 for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ; irq++) {
759#ifdef CONFIG_ARM
760 set_irq_flags(irq, 0);
761#endif
762 irq_set_chip_and_handler(irq, NULL, NULL);
763 irq_set_chip_data(irq, NULL);
764 }
765}
766
767static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
768{
769 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
770
771 return pct->soc->nfunctions;
772}
773
774static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
775 unsigned function)
776{
777 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
778
779 return pct->soc->functions[function].name;
780}
781
782static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
783 unsigned function,
784 const char * const **groups,
785 unsigned * const num_groups)
786{
787 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
788
789 *groups = pct->soc->functions[function].groups;
790 *num_groups = pct->soc->functions[function].ngroups;
791
792 return 0;
793}
794
795static void abx500_disable_lazy_irq(struct gpio_chip *chip, unsigned gpio)
796{
797 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
798 int irq;
799 int offset;
800 bool rising;
801 bool falling;
802
803 /*
804 * check if gpio has interrupt capability and convert
805 * gpio number to irq
806 * On ABx5xx, there is no GPIO0, GPIO1 is the
807 * first one, so adjust gpio number
808 */
809 gpio--;
810 irq = gpio_to_irq(gpio + chip->base);
811 if (irq < 0)
812 return;
813
814 offset = irq - pct->irq_base;
815 rising = pct->rising & BIT(offset);
816 falling = pct->falling & BIT(offset);
817
818 /* nothing to do ?*/
819 if (!rising && !falling)
820 return;
821
822 if (rising) {
823 disable_irq(irq_to_rising(irq));
824 free_irq(irq_to_rising(irq), pct);
825 }
826 if (falling) {
827 disable_irq(irq_to_falling(irq));
828 free_irq(irq_to_falling(irq), pct);
829 }
830}
831
832static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
833 unsigned group)
834{
835 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
836 struct gpio_chip *chip = &pct->chip;
837 const struct abx500_pingroup *g;
838 int i;
839 int ret = 0;
840
841 g = &pct->soc->groups[group];
842 if (g->altsetting < 0)
843 return -EINVAL;
844
845 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
846
847 for (i = 0; i < g->npins; i++) {
848 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
849 g->pins[i], g->altsetting);
850
851 abx500_disable_lazy_irq(chip, g->pins[i]);
852 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
853 }
854 return ret;
855}
856
857static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
858 unsigned function, unsigned group)
859{
860 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
861 const struct abx500_pingroup *g;
862
863 g = &pct->soc->groups[group];
864 if (g->altsetting < 0)
865 return;
866
867 /* FIXME: poke out the mux, set the pin to some default state? */
868 dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
869}
870
871int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
872 struct pinctrl_gpio_range *range,
873 unsigned offset)
874{
875 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
876 const struct abx500_pinrange *p;
877 int ret;
878 int i;
879
880 /*
881 * Different ranges have different ways to enable GPIO function on a
882 * pin, so refer back to our local range type, where we handily define
883 * what altfunc enables GPIO for a certain pin.
884 */
885 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
886 p = &pct->soc->gpio_ranges[i];
887 if ((offset >= p->offset) &&
888 (offset < (p->offset + p->npins)))
889 break;
890 }
891
892 if (i == pct->soc->gpio_num_ranges) {
893 dev_err(pct->dev, "%s failed to locate range\n", __func__);
894 return -ENODEV;
895 }
896
897 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
898 p->altfunc, offset);
899
900 ret = abx500_set_mode(pct->pctldev, &pct->chip,
901 offset, p->altfunc);
902 if (ret < 0) {
903 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
904 return ret;
905 }
906
907 return ret;
908}
909
910static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
911 struct pinctrl_gpio_range *range,
912 unsigned offset)
913{
914}
915
916static struct pinmux_ops abx500_pinmux_ops = {
917 .get_functions_count = abx500_pmx_get_funcs_cnt,
918 .get_function_name = abx500_pmx_get_func_name,
919 .get_function_groups = abx500_pmx_get_func_groups,
920 .enable = abx500_pmx_enable,
921 .disable = abx500_pmx_disable,
922 .gpio_request_enable = abx500_gpio_request_enable,
923 .gpio_disable_free = abx500_gpio_disable_free,
924};
925
926static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
927{
928 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
929
930 return pct->soc->ngroups;
931}
932
933static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
934 unsigned selector)
935{
936 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
937
938 return pct->soc->groups[selector].name;
939}
940
941static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
942 unsigned selector,
943 const unsigned **pins,
944 unsigned *num_pins)
945{
946 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
947
948 *pins = pct->soc->groups[selector].pins;
949 *num_pins = pct->soc->groups[selector].npins;
950 return 0;
951}
952
953static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
954 struct seq_file *s, unsigned offset)
955{
956 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
957 struct gpio_chip *chip = &pct->chip;
958
959 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
960 chip->base + offset - 1);
961}
962
963static struct pinctrl_ops abx500_pinctrl_ops = {
964 .get_groups_count = abx500_get_groups_cnt,
965 .get_group_name = abx500_get_group_name,
966 .get_group_pins = abx500_get_group_pins,
967 .pin_dbg_show = abx500_pin_dbg_show,
968};
969
970int abx500_pin_config_get(struct pinctrl_dev *pctldev,
971 unsigned pin,
972 unsigned long *config)
973{
974 /* Not implemented */
975 return -EINVAL;
976}
977
978int abx500_pin_config_set(struct pinctrl_dev *pctldev,
979 unsigned pin,
980 unsigned long config)
981{
982 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
983 struct pullud *pullud = pct->soc->pullud;
984 struct gpio_chip *chip = &pct->chip;
985 unsigned offset;
986 int ret;
987 enum pin_config_param param = pinconf_to_config_param(config);
988 enum pin_config_param argument = pinconf_to_config_argument(config);
989
990 dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
991 pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
992 (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") :
993 (argument ? "pull up" : "pull down"));
994 /* on ABx500, there is no GPIO0, so adjust the offset */
995 offset = pin - 1;
996
997 switch (param) {
998 case PIN_CONFIG_BIAS_PULL_DOWN:
999 /*
1000 * if argument = 1 set the pull down
1001 * else clear the pull down
1002 */
1003 ret = abx500_gpio_direction_input(chip, offset);
1004 /*
1005 * Some chips only support pull down, while some actually
1006 * support both pull up and pull down. Such chips have
1007 * a "pullud" range specified for the pins that support
1008 * both features. If the pin is not within that range, we
1009 * fall back to the old bit set that only support pull down.
1010 */
1011 if (pullud &&
1012 pin >= pullud->first_pin &&
1013 pin <= pullud->last_pin)
1014 ret = abx500_config_pull_updown(pct,
1015 pin,
1016 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
1017 else
1018 /* Chip only supports pull down */
1019 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
1020 offset, argument ? 0 : 1);
1021 break;
1022 case PIN_CONFIG_OUTPUT:
1023 ret = abx500_gpio_direction_output(chip, offset, argument);
1024 break;
1025 default:
1026 dev_err(chip->dev, "illegal configuration requested\n");
1027 return -EINVAL;
1028 }
1029 return ret;
1030}
1031
1032static struct pinconf_ops abx500_pinconf_ops = {
1033 .pin_config_get = abx500_pin_config_get,
1034 .pin_config_set = abx500_pin_config_set,
1035};
1036
1037static struct pinctrl_desc abx500_pinctrl_desc = {
1038 .name = "pinctrl-abx500",
1039 .pctlops = &abx500_pinctrl_ops,
1040 .pmxops = &abx500_pinmux_ops,
1041 .confops = &abx500_pinconf_ops,
1042 .owner = THIS_MODULE,
1043};
1044
1045static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
1046{
1047 unsigned int lowest = 0;
1048 unsigned int highest = 0;
1049 unsigned int npins = 0;
1050 int i;
1051
1052 /*
1053 * Compute number of GPIOs from the last SoC gpio range descriptors
1054 * These ranges may include "holes" but the GPIO number space shall
1055 * still be homogeneous, so we need to detect and account for any
1056 * such holes so that these are included in the number of GPIO pins.
1057 */
1058 for (i = 0; i < soc->gpio_num_ranges; i++) {
1059 unsigned gstart;
1060 unsigned gend;
1061 const struct abx500_pinrange *p;
1062
1063 p = &soc->gpio_ranges[i];
1064 gstart = p->offset;
1065 gend = p->offset + p->npins - 1;
1066
1067 if (i == 0) {
1068 /* First iteration, set start values */
1069 lowest = gstart;
1070 highest = gend;
1071 } else {
1072 if (gstart < lowest)
1073 lowest = gstart;
1074 if (gend > highest)
1075 highest = gend;
1076 }
1077 }
1078 /* this gives the absolute number of pins */
1079 npins = highest - lowest + 1;
1080 return npins;
1081}
1082
1083static int abx500_gpio_probe(struct platform_device *pdev)
1084{
1085 struct ab8500_platform_data *abx500_pdata =
1086 dev_get_platdata(pdev->dev.parent);
1087 struct abx500_gpio_platform_data *pdata;
1088 struct abx500_pinctrl *pct;
1089 const struct platform_device_id *platid = platform_get_device_id(pdev);
1090 int ret;
1091 int i;
1092
1093 pdata = abx500_pdata->gpio;
1094 if (!pdata) {
1095 dev_err(&pdev->dev, "gpio platform data missing\n");
1096 return -ENODEV;
1097 }
1098
1099 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
1100 GFP_KERNEL);
1101 if (pct == NULL) {
1102 dev_err(&pdev->dev,
1103 "failed to allocate memory for pct\n");
1104 return -ENOMEM;
1105 }
1106
1107 pct->dev = &pdev->dev;
1108 pct->parent = dev_get_drvdata(pdev->dev.parent);
1109 pct->chip = abx500gpio_chip;
1110 pct->chip.dev = &pdev->dev;
1111 pct->chip.base = pdata->gpio_base;
1112 pct->irq_base = pdata->irq_base;
1113
1114 /* initialize the lock */
1115 mutex_init(&pct->lock);
1116
1117 /* Poke in other ASIC variants here */
1118 switch (platid->driver_data) {
1119 default:
1120 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n",
1121 (int) platid->driver_data);
1122 return -EINVAL;
1123 }
1124
1125 if (!pct->soc) {
1126 dev_err(&pdev->dev, "Invalid SOC data\n");
1127 return -EINVAL;
1128 }
1129
1130 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
1131 pct->irq_cluster = pct->soc->gpio_irq_cluster;
1132 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
1133 pct->irq_gpio_rising_offset = pct->soc->irq_gpio_rising_offset;
1134 pct->irq_gpio_falling_offset = pct->soc->irq_gpio_falling_offset;
1135 pct->irq_gpio_factor = pct->soc->irq_gpio_factor;
1136
1137 ret = abx500_gpio_irq_init(pct);
1138 if (ret)
1139 goto out_free;
1140 ret = gpiochip_add(&pct->chip);
1141 if (ret) {
1142 dev_err(&pdev->dev, "unable to add gpiochip: %d\n",
1143 ret);
1144 goto out_rem_irq;
1145 }
1146 dev_info(&pdev->dev, "added gpiochip\n");
1147
1148 abx500_pinctrl_desc.pins = pct->soc->pins;
1149 abx500_pinctrl_desc.npins = pct->soc->npins;
1150 pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
1151 if (!pct->pctldev) {
1152 dev_err(&pdev->dev,
1153 "could not register abx500 pinctrl driver\n");
1154 goto out_rem_chip;
1155 }
1156 dev_info(&pdev->dev, "registered pin controller\n");
1157
1158 /* We will handle a range of GPIO pins */
1159 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
1160 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
1161
1162 ret = gpiochip_add_pin_range(&pct->chip,
1163 dev_name(&pdev->dev),
1164 p->offset - 1, p->offset, p->npins);
1165 if (ret < 0)
1166 return ret;
1167 }
1168
1169 platform_set_drvdata(pdev, pct);
1170 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
1171
1172 return 0;
1173
1174out_rem_chip:
1175 ret = gpiochip_remove(&pct->chip);
1176 if (ret)
1177 dev_info(&pdev->dev, "failed to remove gpiochip\n");
1178out_rem_irq:
1179 abx500_gpio_irq_remove(pct);
1180out_free:
1181 mutex_destroy(&pct->lock);
1182 return ret;
1183}
1184
1185/*
1186 * abx500_gpio_remove() - remove Ab8500-gpio driver
1187 * @pdev : Platform device registered
1188 */
1189static int abx500_gpio_remove(struct platform_device *pdev)
1190{
1191 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
1192 int ret;
1193
1194 ret = gpiochip_remove(&pct->chip);
1195 if (ret < 0) {
1196 dev_err(pct->dev, "unable to remove gpiochip: %d\n",
1197 ret);
1198 return ret;
1199 }
1200
1201 mutex_destroy(&pct->lock);
1202
1203 return 0;
1204}
1205
1206static const struct platform_device_id abx500_pinctrl_id[] = {
1207 { "pinctrl-ab8500", PINCTRL_AB8500 },
1208 { "pinctrl-ab8540", PINCTRL_AB8540 },
1209 { "pinctrl-ab9540", PINCTRL_AB9540 },
1210 { "pinctrl-ab8505", PINCTRL_AB8505 },
1211 { },
1212};
1213
1214static struct platform_driver abx500_gpio_driver = {
1215 .driver = {
1216 .name = "abx500-gpio",
1217 .owner = THIS_MODULE,
1218 },
1219 .probe = abx500_gpio_probe,
1220 .remove = abx500_gpio_remove,
1221 .id_table = abx500_pinctrl_id,
1222};
1223
1224static int __init abx500_gpio_init(void)
1225{
1226 return platform_driver_register(&abx500_gpio_driver);
1227}
1228core_initcall(abx500_gpio_init);
1229
1230MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
1231MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
1232MODULE_ALIAS("platform:abx500-gpio");
1233MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-abx500.h b/drivers/pinctrl/pinctrl-abx500.h
new file mode 100644
index 000000000000..436ace356175
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-abx500.h
@@ -0,0 +1,180 @@
1#ifndef PINCTRL_PINCTRL_ABx5O0_H
2#define PINCTRL_PINCTRL_ABx500_H
3
4/* Package definitions */
5#define PINCTRL_AB8500 0
6#define PINCTRL_AB8540 1
7#define PINCTRL_AB9540 2
8#define PINCTRL_AB8505 3
9
10/* pins alternate function */
11enum abx500_pin_func {
12 ABX500_DEFAULT,
13 ABX500_ALT_A,
14 ABX500_ALT_B,
15 ABX500_ALT_C,
16};
17
18/**
19 * struct abx500_function - ABx500 pinctrl mux function
20 * @name: The name of the function, exported to pinctrl core.
21 * @groups: An array of pin groups that may select this function.
22 * @ngroups: The number of entries in @groups.
23 */
24struct abx500_function {
25 const char *name;
26 const char * const *groups;
27 unsigned ngroups;
28};
29
30/**
31 * struct abx500_pingroup - describes a ABx500 pin group
32 * @name: the name of this specific pin group
33 * @pins: an array of discrete physical pins used in this group, taken
34 * from the driver-local pin enumeration space
35 * @num_pins: the number of pins in this group array, i.e. the number of
36 * elements in .pins so we can iterate over that array
37 * @altsetting: the altsetting to apply to all pins in this group to
38 * configure them to be used by a function
39 */
40struct abx500_pingroup {
41 const char *name;
42 const unsigned int *pins;
43 const unsigned npins;
44 int altsetting;
45};
46
47#define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \
48{ \
49 .pin_number = pin, \
50 .gpiosel_bit = sel_bit, \
51 .alt_bit1 = alt1, \
52 .alt_bit2 = alt2, \
53 .alta_val = alta, \
54 .altb_val = altb, \
55 .altc_val = altc, \
56}
57
58#define UNUSED -1
59/**
60 * struct alternate_functions
61 * @pin_number: The pin number
62 * @gpiosel_bit: Control bit in GPIOSEL register,
63 * @alt_bit1: First AlternateFunction bit used to select the
64 * alternate function
65 * @alt_bit2: Second AlternateFunction bit used to select the
66 * alternate function
67 *
68 * these 3 following fields are necessary due to none
69 * coherency on how to select the altA, altB and altC
70 * function between the ABx500 SOC family when using
71 * alternatfunc register.
72 * @alta_val: value to write in alternatfunc to select altA function
73 * @altb_val: value to write in alternatfunc to select altB function
74 * @altc_val: value to write in alternatfunc to select altC function
75 */
76struct alternate_functions {
77 unsigned pin_number;
78 s8 gpiosel_bit;
79 s8 alt_bit1;
80 s8 alt_bit2;
81 u8 alta_val;
82 u8 altb_val;
83 u8 altc_val;
84};
85
86/**
87 * struct pullud - specific pull up/down feature
88 * @first_pin: The pin number of the first pins which support
89 * specific pull up/down
90 * @last_pin: The pin number of the last pins
91 */
92struct pullud {
93 unsigned first_pin;
94 unsigned last_pin;
95};
96
97#define GPIO_IRQ_CLUSTER(a, b, c) \
98{ \
99 .start = a, \
100 .end = b, \
101 .offset = c, \
102}
103
104/**
105 * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
106 * capable
107 * @start: The pin number of the first pin interrupt capable
108 * @end: The pin number of the last pin interrupt capable
109 * @offset: offset used to compute specific setting strategy of
110 * the interrupt line
111 */
112
113struct abx500_gpio_irq_cluster {
114 int start;
115 int end;
116 int offset;
117};
118
119/**
120 * struct abx500_pinrange - map pin numbers to GPIO offsets
121 * @offset: offset into the GPIO local numberspace, incidentally
122 * identical to the offset into the local pin numberspace
123 * @npins: number of pins to map from both offsets
124 * @altfunc: altfunc setting to be used to enable GPIO on a pin in
125 * this range (may vary)
126 */
127struct abx500_pinrange {
128 unsigned int offset;
129 unsigned int npins;
130 int altfunc;
131};
132
133#define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c }
134
135/**
136 * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration
137 * @gpio_ranges: An array of GPIO ranges for this SoC
138 * @gpio_num_ranges: The number of GPIO ranges for this SoC
139 * @pins: An array describing all pins the pin controller affects.
140 * All pins which are also GPIOs must be listed first within the
141 * array, and be numbered identically to the GPIO controller's
142 * numbering.
143 * @npins: The number of entries in @pins.
144 * @functions: The functions supported on this SoC.
145 * @nfunction: The number of entries in @functions.
146 * @groups: An array describing all pin groups the pin SoC supports.
147 * @ngroups: The number of entries in @groups.
148 * @alternate_functions: array describing pins which supports alternate and
149 * how to set it.
150 * @pullud: array describing pins which supports pull up/down
151 * specific registers.
152 * @gpio_irq_cluster: An array of GPIO interrupt capable for this SoC
153 * @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC
154 * @irq_gpio_rising_offset: Interrupt offset used as base to compute specific
155 * setting strategy of the rising interrupt line
156 * @irq_gpio_falling_offset: Interrupt offset used as base to compute specific
157 * setting strategy of the falling interrupt line
158 * @irq_gpio_factor: Factor used to compute specific setting strategy of
159 * the interrupt line
160 */
161
162struct abx500_pinctrl_soc_data {
163 const struct abx500_pinrange *gpio_ranges;
164 unsigned gpio_num_ranges;
165 const struct pinctrl_pin_desc *pins;
166 unsigned npins;
167 const struct abx500_function *functions;
168 unsigned nfunctions;
169 const struct abx500_pingroup *groups;
170 unsigned ngroups;
171 struct alternate_functions *alternate_functions;
172 struct pullud *pullud;
173 struct abx500_gpio_irq_cluster *gpio_irq_cluster;
174 unsigned ngpio_irq_cluster;
175 int irq_gpio_rising_offset;
176 int irq_gpio_falling_offset;
177 int irq_gpio_factor;
178};
179
180#endif /* PINCTRL_PINCTRL_ABx500_H */
diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h
index 2387c207ea86..e8c8281e194a 100644
--- a/include/linux/mfd/abx500/ab8500-gpio.h
+++ b/include/linux/mfd/abx500/ab8500-gpio.h
@@ -14,10 +14,21 @@
14 * registers. 14 * registers.
15 */ 15 */
16 16
17struct ab8500_gpio_platform_data { 17struct abx500_gpio_platform_data {
18 int gpio_base; 18 int gpio_base;
19 u32 irq_base; 19 u32 irq_base;
20 u8 config_reg[8]; 20};
21
22enum abx500_gpio_pull_updown {
23 ABX500_GPIO_PULL_DOWN = 0x0,
24 ABX500_GPIO_PULL_NONE = 0x1,
25 ABX500_GPIO_PULL_UP = 0x3,
26};
27
28enum abx500_gpio_vinsel {
29 ABX500_GPIO_VINSEL_VBAT = 0x0,
30 ABX500_GPIO_VINSEL_VIN_1V8 = 0x1,
31 ABX500_GPIO_VINSEL_VDD_BIF = 0x2,
21}; 32};
22 33
23#endif /* _AB8500_GPIO_H */ 34#endif /* _AB8500_GPIO_H */
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index e640ea059be2..fc0534483c72 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -385,7 +385,7 @@ struct ab8500_platform_data {
385 struct ab8500_regulator_reg_init *regulator_reg_init; 385 struct ab8500_regulator_reg_init *regulator_reg_init;
386 int num_regulator; 386 int num_regulator;
387 struct regulator_init_data *regulator; 387 struct regulator_init_data *regulator;
388 struct ab8500_gpio_platform_data *gpio; 388 struct abx500_gpio_platform_data *gpio;
389 struct ab8500_codec_platform_data *codec; 389 struct ab8500_codec_platform_data *codec;
390}; 390};
391 391
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 09:36:34 -0500