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-rw-r--r--arch/arm/mach-highbank/highbank.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 38e1dc3b4c6e..4712aed3d9f6 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -51,11 +51,13 @@ static void __init highbank_scu_map_io(void)
51} 51}
52 52
53 53
54static void highbank_l2x0_disable(void) 54static void highbank_l2c310_write_sec(unsigned long val, unsigned reg)
55{ 55{
56 outer_flush_all(); 56 if (reg == L2X0_CTRL)
57 /* Disable PL310 L2 Cache controller */ 57 highbank_smc1(0x102, val);
58 highbank_smc1(0x102, 0x0); 58 else
59 WARN_ONCE(1, "Highbank L2C310: ignoring write to reg 0x%x\n",
60 reg);
59} 61}
60 62
61static void __init highbank_init_irq(void) 63static void __init highbank_init_irq(void)
@@ -69,8 +71,8 @@ static void __init highbank_init_irq(void)
69 if (IS_ENABLED(CONFIG_CACHE_L2X0) && 71 if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
70 of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) { 72 of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
71 highbank_smc1(0x102, 0x1); 73 highbank_smc1(0x102, 0x1);
74 outer_cache.write_sec = highbank_l2c310_write_sec;
72 l2x0_of_init(0, ~0); 75 l2x0_of_init(0, ~0);
73 outer_cache.disable = highbank_l2x0_disable;
74 } 76 }
75} 77}
76 78