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-rw-r--r--drivers/staging/et131x/et1310_address_map.h35
-rw-r--r--drivers/staging/et131x/et131x_isr.c6
2 files changed, 10 insertions, 31 deletions
diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h
index 39ba922bd2b6..6c69a15dbbe5 100644
--- a/drivers/staging/et131x/et1310_address_map.h
+++ b/drivers/staging/et131x/et1310_address_map.h
@@ -261,35 +261,14 @@ extern inline void add_10bit(u32 *v, int n)
261 * txdma tx descriptor cache write index reg in txdma address map at 0x1030 261 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
262 * 262 *
263 * txdma error reg in txdma address map at address 0x1034 263 * txdma error reg in txdma address map at address 0x1034
264 * 0: PyldResend
265 * 1: PyldRewind
266 * 4: DescrResend
267 * 5: DescrRewind
268 * 8: WrbkResend
269 * 9: WrbkRewind
264 */ 270 */
265 271
266typedef union _TXDMA_ERROR_t {
267 u32 value;
268 struct {
269#ifdef _BIT_FIELDS_HTOL
270 u32 unused3:22; /* bits 10-31 */
271 u32 WrbkRewind:1; /* bit 9 */
272 u32 WrbkResend:1; /* bit 8 */
273 u32 unused2:2; /* bits 6-7 */
274 u32 DescrRewind:1; /* bit 5 */
275 u32 DescrResend:1; /* bit 4 */
276 u32 unused1:2; /* bits 2-3 */
277 u32 PyldRewind:1; /* bit 1 */
278 u32 PyldResend:1; /* bit 0 */
279#else
280 u32 PyldResend:1; /* bit 0 */
281 u32 PyldRewind:1; /* bit 1 */
282 u32 unused1:2; /* bits 2-3 */
283 u32 DescrResend:1; /* bit 4 */
284 u32 DescrRewind:1; /* bit 5 */
285 u32 unused2:2; /* bits 6-7 */
286 u32 WrbkResend:1; /* bit 8 */
287 u32 WrbkRewind:1; /* bit 9 */
288 u32 unused3:22; /* bits 10-31 */
289#endif
290 } bits;
291} TXDMA_ERROR_t, *PTXDMA_ERROR_t;
292
293/* 272/*
294 * Tx DMA Module of JAGCore Address Mapping 273 * Tx DMA Module of JAGCore Address Mapping
295 * Located at address 0x1000 274 * Located at address 0x1000
@@ -308,7 +287,7 @@ typedef struct _TXDMA_t { /* Location: */
308 u32 service_complete; /* 0x1028 */ 287 u32 service_complete; /* 0x1028 */
309 u32 cache_rd_index; /* 0x102C */ 288 u32 cache_rd_index; /* 0x102C */
310 u32 cache_wr_index; /* 0x1030 */ 289 u32 cache_wr_index; /* 0x1030 */
311 TXDMA_ERROR_t TxDmaError; /* 0x1034 */ 290 u32 TxDmaError; /* 0x1034 */
312 u32 DescAbortCount; /* 0x1038 */ 291 u32 DescAbortCount; /* 0x1038 */
313 u32 PayloadAbortCnt; /* 0x103c */ 292 u32 PayloadAbortCnt; /* 0x103c */
314 u32 WriteBackAbortCnt; /* 0x1040 */ 293 u32 WriteBackAbortCnt; /* 0x1040 */
diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c
index 2943178a7a36..f80189d7cb6d 100644
--- a/drivers/staging/et131x/et131x_isr.c
+++ b/drivers/staging/et131x/et131x_isr.c
@@ -255,14 +255,14 @@ void et131x_isr_handler(struct work_struct *work)
255 if (status) { 255 if (status) {
256 /* Handle the TXDMA Error interrupt */ 256 /* Handle the TXDMA Error interrupt */
257 if (status & ET_INTR_TXDMA_ERR) { 257 if (status & ET_INTR_TXDMA_ERR) {
258 TXDMA_ERROR_t TxDmaErr; 258 u32 txdma_err;
259 259
260 /* Following read also clears the register (COR) */ 260 /* Following read also clears the register (COR) */
261 TxDmaErr.value = readl(&iomem->txdma.TxDmaError.value); 261 txdma_err = readl(&iomem->txdma.TxDmaError);
262 262
263 dev_warn(&etdev->pdev->dev, 263 dev_warn(&etdev->pdev->dev,
264 "TXDMA_ERR interrupt, error = %d\n", 264 "TXDMA_ERR interrupt, error = %d\n",
265 TxDmaErr.value); 265 txdma_err);
266 } 266 }
267 267
268 /* Handle Free Buffer Ring 0 and 1 Low interrupt */ 268 /* Handle Free Buffer Ring 0 and 1 Low interrupt */