3 files changed, 24 insertions, 17 deletions

diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 7e600c1962db..5866b28eede1 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -143,6 +143,7 @@ void clflush_cache_range(void *vaddr, unsigned int size)
 
         mb();
 }
+EXPORT_SYMBOL_GPL(clflush_cache_range);
 
 static void __cpa_flush_all(void *arg)
 {
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index c17291715031..e8dc75fc33cc 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -682,23 +682,39 @@ static void intel_i830_setup_flush(void)
         if (!intel_private.i8xx_page)
                 return;
 
-        /* make page uncached */
-        map_page_into_agp(intel_private.i8xx_page);
-
         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
         if (!intel_private.i8xx_flush_page)
                 intel_i830_fini_flush();
 }
 
+static void
+do_wbinvd(void *null)
+{
+        wbinvd();
+}
+
+/* The chipset_flush interface needs to get data that has already been
+ * flushed out of the CPU all the way out to main memory, because the GPU
+ * doesn't snoop those buffers.
+ *
+ * The 8xx series doesn't have the same lovely interface for flushing the
+ * chipset write buffers that the later chips do. According to the 865
+ * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
+ * that buffer out, we just fill 1KB and clflush it out, on the assumption
+ * that it'll push whatever was in there out.  It appears to work.
+ */
 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 {
         unsigned int *pg = intel_private.i8xx_flush_page;
-        int i;
 
-        for (i = 0; i < 256; i += 2)
-                *(pg + i) = i;
+        memset(pg, 0, 1024);
 
-        wmb();
+        if (cpu_has_clflush) {
+                clflush_cache_range(pg, 1024);
+        } else {
+                if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
+                        printk(KERN_ERR "Timed out waiting for cache flush.\n");
+        }
 }
 
 /* The intel i830 automatically initializes the agp aperture during POST.
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f3758f9fc979..30ea4b6b0219 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2511,16 +2511,6 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
         if (obj_priv->pages == NULL)
                 return;
 
-        /* XXX: The 865 in particular appears to be weird in how it handles
-         * cache flushing.  We haven't figured it out, but the
-         * clflush+agp_chipset_flush doesn't appear to successfully get the
-         * data visible to the PGU, while wbinvd + agp_chipset_flush does.
-         */
-        if (IS_I865G(obj->dev)) {
-                wbinvd();
-                return;
-        }
-
         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
 }