aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--include/asm-m68knommu/bitops.h2
-rw-r--r--include/asm-m68knommu/commproc.h2
-rw-r--r--include/asm-m68knommu/delay.h2
-rw-r--r--include/asm-m68knommu/m5249sim.h4
-rw-r--r--include/asm-m68knommu/m5307sim.h12
-rw-r--r--include/asm-m68knommu/m5407sim.h12
-rw-r--r--include/asm-m68knommu/m68360_regs.h2
-rw-r--r--include/asm-m68knommu/mcfuart.h2
8 files changed, 19 insertions, 19 deletions
diff --git a/include/asm-m68knommu/bitops.h b/include/asm-m68knommu/bitops.h
index f43afe1fc3b3..c142fbf2f376 100644
--- a/include/asm-m68knommu/bitops.h
+++ b/include/asm-m68knommu/bitops.h
@@ -262,7 +262,7 @@ static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned lon
262 * tmp = __swab32(*(p++)); 262 * tmp = __swab32(*(p++));
263 * tmp |= ~0UL >> (32-offset); 263 * tmp |= ~0UL >> (32-offset);
264 * 264 *
265 * but this would decrease preformance, so we change the 265 * but this would decrease performance, so we change the
266 * shift: 266 * shift:
267 */ 267 */
268 tmp = *(p++); 268 tmp = *(p++);
diff --git a/include/asm-m68knommu/commproc.h b/include/asm-m68knommu/commproc.h
index 0161ebb5d883..36e870b468ef 100644
--- a/include/asm-m68knommu/commproc.h
+++ b/include/asm-m68knommu/commproc.h
@@ -715,7 +715,7 @@ extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
715#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 715#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
716#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 716#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
717#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 717#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
718#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ 718#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
719#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 719#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
720#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 720#define CICR_IEN ((uint)0x00000080) /* Int. enable */
721#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 721#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
diff --git a/include/asm-m68knommu/delay.h b/include/asm-m68knommu/delay.h
index 04a20fd051cf..55cbd6294ab6 100644
--- a/include/asm-m68knommu/delay.h
+++ b/include/asm-m68knommu/delay.h
@@ -68,7 +68,7 @@ static inline void _udelay(unsigned long usecs)
68/* 68/*
69 * Moved the udelay() function into library code, no longer inlined. 69 * Moved the udelay() function into library code, no longer inlined.
70 * I had to change the algorithm because we are overflowing now on 70 * I had to change the algorithm because we are overflowing now on
71 * the faster ColdFire parts. The code is a little biger, so it makes 71 * the faster ColdFire parts. The code is a little bigger, so it makes
72 * sense to library it. 72 * sense to library it.
73 */ 73 */
74extern void udelay(unsigned long usecs); 74extern void udelay(unsigned long usecs);
diff --git a/include/asm-m68knommu/m5249sim.h b/include/asm-m68knommu/m5249sim.h
index 399814f0b219..366eb8602d2f 100644
--- a/include/asm-m68knommu/m5249sim.h
+++ b/include/asm-m68knommu/m5249sim.h
@@ -43,10 +43,10 @@
43#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ 43#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
44#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ 44#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
45#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ 45#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
46#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */ 46#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
47#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ 47#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
48#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 48#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
49#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */ 49#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
50#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 50#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
51#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 51#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
52 52
diff --git a/include/asm-m68knommu/m5307sim.h b/include/asm-m68knommu/m5307sim.h
index d3ce550f6ef4..5886728409c0 100644
--- a/include/asm-m68knommu/m5307sim.h
+++ b/include/asm-m68knommu/m5307sim.h
@@ -64,22 +64,22 @@
64#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ 64#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */
65#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 65#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
66#else 66#else
67#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */ 67#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
68#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ 68#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
69#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 69#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
70#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */ 70#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
71#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 71#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
72#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 72#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
73#define MCFSIM_CSAR4 0xb0 /* CS 4 Adress reg (r/w) */ 73#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
74#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ 74#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
75#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ 75#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
76#define MCFSIM_CSAR5 0xbc /* CS 5 Adress reg (r/w) */ 76#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
77#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ 77#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
78#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ 78#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
79#define MCFSIM_CSAR6 0xc8 /* CS 6 Adress reg (r/w) */ 79#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
80#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ 80#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
81#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ 81#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
82#define MCFSIM_CSAR7 0xd4 /* CS 7 Adress reg (r/w) */ 82#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
83#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ 83#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
84#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 84#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
85#endif /* CONFIG_OLDMASK */ 85#endif /* CONFIG_OLDMASK */
diff --git a/include/asm-m68knommu/m5407sim.h b/include/asm-m68knommu/m5407sim.h
index 75dcdacdb298..cc22c4a53005 100644
--- a/include/asm-m68knommu/m5407sim.h
+++ b/include/asm-m68knommu/m5407sim.h
@@ -48,22 +48,22 @@
48#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ 48#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
49#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ 49#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
50 50
51#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */ 51#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
52#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ 52#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
53#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ 53#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
54#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */ 54#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
55#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ 55#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
56#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ 56#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
57#define MCFSIM_CSAR4 0xb0 /* CS 4 Adress reg (r/w) */ 57#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
58#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ 58#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
59#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ 59#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
60#define MCFSIM_CSAR5 0xbc /* CS 5 Adress reg (r/w) */ 60#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
61#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ 61#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
62#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ 62#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
63#define MCFSIM_CSAR6 0xc8 /* CS 6 Adress reg (r/w) */ 63#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
64#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ 64#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
65#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ 65#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
66#define MCFSIM_CSAR7 0xd4 /* CS 7 Adress reg (r/w) */ 66#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
67#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ 67#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
68#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ 68#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
69 69
diff --git a/include/asm-m68knommu/m68360_regs.h b/include/asm-m68knommu/m68360_regs.h
index a3f8cc8a4a84..d57217ca4f27 100644
--- a/include/asm-m68knommu/m68360_regs.h
+++ b/include/asm-m68knommu/m68360_regs.h
@@ -138,7 +138,7 @@
138#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 138#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
139#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ 139#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
140 140
141#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ 141#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
142#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 142#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
143#define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */ 143#define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */
144#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 144#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
diff --git a/include/asm-m68knommu/mcfuart.h b/include/asm-m68knommu/mcfuart.h
index 1319a81814b1..8a7a67703ac3 100644
--- a/include/asm-m68knommu/mcfuart.h
+++ b/include/asm-m68knommu/mcfuart.h
@@ -71,7 +71,7 @@ struct mcf_platform_uart {
71#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ 71#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
72#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ 72#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
73#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ 73#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
74#define MCFUART_UISR 0x14 /* Interrup Status (r) */ 74#define MCFUART_UISR 0x14 /* Interrupt Status (r) */
75#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ 75#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
76#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ 76#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
77#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ 77#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 10:31:48 -0500