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-rw-r--r--drivers/net/forcedeth.c212
1 files changed, 178 insertions, 34 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 8c4214b0ee1f..73d85b31fbdc 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -96,6 +96,7 @@
96#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */ 96#define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
97#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */ 97#define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
98#define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */ 98#define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
99#define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */
99 100
100enum { 101enum {
101 NvRegIrqStatus = 0x000, 102 NvRegIrqStatus = 0x000,
@@ -174,11 +175,13 @@ enum {
174 NvRegReceiverStatus = 0x98, 175 NvRegReceiverStatus = 0x98,
175#define NVREG_RCVSTAT_BUSY 0x01 176#define NVREG_RCVSTAT_BUSY 0x01
176 177
177 NvRegRandomSeed = 0x9c, 178 NvRegSlotTime = 0x9c,
178#define NVREG_RNDSEED_MASK 0x00ff 179#define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
179#define NVREG_RNDSEED_FORCE 0x7f00 180#define NVREG_SLOTTIME_10_100_FULL 0x00007f00
180#define NVREG_RNDSEED_FORCE2 0x2d00 181#define NVREG_SLOTTIME_1000_FULL 0x0003ff00
181#define NVREG_RNDSEED_FORCE3 0x7400 182#define NVREG_SLOTTIME_HALF 0x0000ff00
183#define NVREG_SLOTTIME_DEFAULT 0x00007f00
184#define NVREG_SLOTTIME_MASK 0x000000ff
182 185
183 NvRegTxDeferral = 0xA0, 186 NvRegTxDeferral = 0xA0,
184#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f 187#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
@@ -201,6 +204,11 @@ enum {
201 204
202 NvRegPhyInterface = 0xC0, 205 NvRegPhyInterface = 0xC0,
203#define PHY_RGMII 0x10000000 206#define PHY_RGMII 0x10000000
207 NvRegBackOffControl = 0xC4,
208#define NVREG_BKOFFCTRL_DEFAULT 0x70000000
209#define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
210#define NVREG_BKOFFCTRL_SELECT 24
211#define NVREG_BKOFFCTRL_GEAR 12
204 212
205 NvRegTxRingPhysAddr = 0x100, 213 NvRegTxRingPhysAddr = 0x100,
206 NvRegRxRingPhysAddr = 0x104, 214 NvRegRxRingPhysAddr = 0x104,
@@ -352,6 +360,7 @@ union ring_type {
352 360
353#define NV_TX_LASTPACKET (1<<16) 361#define NV_TX_LASTPACKET (1<<16)
354#define NV_TX_RETRYERROR (1<<19) 362#define NV_TX_RETRYERROR (1<<19)
363#define NV_TX_RETRYCOUNT_MASK (0xF<<20)
355#define NV_TX_FORCED_INTERRUPT (1<<24) 364#define NV_TX_FORCED_INTERRUPT (1<<24)
356#define NV_TX_DEFERRED (1<<26) 365#define NV_TX_DEFERRED (1<<26)
357#define NV_TX_CARRIERLOST (1<<27) 366#define NV_TX_CARRIERLOST (1<<27)
@@ -362,6 +371,7 @@ union ring_type {
362 371
363#define NV_TX2_LASTPACKET (1<<29) 372#define NV_TX2_LASTPACKET (1<<29)
364#define NV_TX2_RETRYERROR (1<<18) 373#define NV_TX2_RETRYERROR (1<<18)
374#define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
365#define NV_TX2_FORCED_INTERRUPT (1<<30) 375#define NV_TX2_FORCED_INTERRUPT (1<<30)
366#define NV_TX2_DEFERRED (1<<25) 376#define NV_TX2_DEFERRED (1<<25)
367#define NV_TX2_CARRIERLOST (1<<26) 377#define NV_TX2_CARRIERLOST (1<<26)
@@ -1769,6 +1779,115 @@ static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1769 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); 1779 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1770} 1780}
1771 1781
1782static void nv_legacybackoff_reseed(struct net_device *dev)
1783{
1784 u8 __iomem *base = get_hwbase(dev);
1785 u32 reg;
1786 u32 low;
1787 int tx_status = 0;
1788
1789 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1790 get_random_bytes(&low, sizeof(low));
1791 reg |= low & NVREG_SLOTTIME_MASK;
1792
1793 /* Need to stop tx before change takes effect.
1794 * Caller has already gained np->lock.
1795 */
1796 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1797 if (tx_status)
1798 nv_stop_tx(dev);
1799 nv_stop_rx(dev);
1800 writel(reg, base + NvRegSlotTime);
1801 if (tx_status)
1802 nv_start_tx(dev);
1803 nv_start_rx(dev);
1804}
1805
1806/* Gear Backoff Seeds */
1807#define BACKOFF_SEEDSET_ROWS 8
1808#define BACKOFF_SEEDSET_LFSRS 15
1809
1810/* Known Good seed sets */
1811static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1812 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1813 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1814 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1815 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1816 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1817 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1818 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
1819 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
1820
1821static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
1822 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1823 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1824 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
1825 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1826 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1827 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1828 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1829 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
1830
1831static void nv_gear_backoff_reseed(struct net_device *dev)
1832{
1833 u8 __iomem *base = get_hwbase(dev);
1834 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
1835 u32 temp, seedset, combinedSeed;
1836 int i;
1837
1838 /* Setup seed for free running LFSR */
1839 /* We are going to read the time stamp counter 3 times
1840 and swizzle bits around to increase randomness */
1841 get_random_bytes(&miniseed1, sizeof(miniseed1));
1842 miniseed1 &= 0x0fff;
1843 if (miniseed1 == 0)
1844 miniseed1 = 0xabc;
1845
1846 get_random_bytes(&miniseed2, sizeof(miniseed2));
1847 miniseed2 &= 0x0fff;
1848 if (miniseed2 == 0)
1849 miniseed2 = 0xabc;
1850 miniseed2_reversed =
1851 ((miniseed2 & 0xF00) >> 8) |
1852 (miniseed2 & 0x0F0) |
1853 ((miniseed2 & 0x00F) << 8);
1854
1855 get_random_bytes(&miniseed3, sizeof(miniseed3));
1856 miniseed3 &= 0x0fff;
1857 if (miniseed3 == 0)
1858 miniseed3 = 0xabc;
1859 miniseed3_reversed =
1860 ((miniseed3 & 0xF00) >> 8) |
1861 (miniseed3 & 0x0F0) |
1862 ((miniseed3 & 0x00F) << 8);
1863
1864 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
1865 (miniseed2 ^ miniseed3_reversed);
1866
1867 /* Seeds can not be zero */
1868 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
1869 combinedSeed |= 0x08;
1870 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
1871 combinedSeed |= 0x8000;
1872
1873 /* No need to disable tx here */
1874 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
1875 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
1876 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
1877 writel(temp,base + NvRegBackOffControl);
1878
1879 /* Setup seeds for all gear LFSRs. */
1880 get_random_bytes(&seedset, sizeof(seedset));
1881 seedset = seedset % BACKOFF_SEEDSET_ROWS;
1882 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
1883 {
1884 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
1885 temp |= main_seedset[seedset][i-1] & 0x3ff;
1886 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
1887 writel(temp, base + NvRegBackOffControl);
1888 }
1889}
1890
1772/* 1891/*
1773 * nv_start_xmit: dev->hard_start_xmit function 1892 * nv_start_xmit: dev->hard_start_xmit function
1774 * Called with netif_tx_lock held. 1893 * Called with netif_tx_lock held.
@@ -2088,6 +2207,8 @@ static void nv_tx_done(struct net_device *dev)
2088 dev->stats.tx_fifo_errors++; 2207 dev->stats.tx_fifo_errors++;
2089 if (flags & NV_TX_CARRIERLOST) 2208 if (flags & NV_TX_CARRIERLOST)
2090 dev->stats.tx_carrier_errors++; 2209 dev->stats.tx_carrier_errors++;
2210 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2211 nv_legacybackoff_reseed(dev);
2091 dev->stats.tx_errors++; 2212 dev->stats.tx_errors++;
2092 } else { 2213 } else {
2093 dev->stats.tx_packets++; 2214 dev->stats.tx_packets++;
@@ -2103,6 +2224,8 @@ static void nv_tx_done(struct net_device *dev)
2103 dev->stats.tx_fifo_errors++; 2224 dev->stats.tx_fifo_errors++;
2104 if (flags & NV_TX2_CARRIERLOST) 2225 if (flags & NV_TX2_CARRIERLOST)
2105 dev->stats.tx_carrier_errors++; 2226 dev->stats.tx_carrier_errors++;
2227 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2228 nv_legacybackoff_reseed(dev);
2106 dev->stats.tx_errors++; 2229 dev->stats.tx_errors++;
2107 } else { 2230 } else {
2108 dev->stats.tx_packets++; 2231 dev->stats.tx_packets++;
@@ -2144,6 +2267,15 @@ static void nv_tx_done_optimized(struct net_device *dev, int limit)
2144 if (flags & NV_TX2_LASTPACKET) { 2267 if (flags & NV_TX2_LASTPACKET) {
2145 if (!(flags & NV_TX2_ERROR)) 2268 if (!(flags & NV_TX2_ERROR))
2146 dev->stats.tx_packets++; 2269 dev->stats.tx_packets++;
2270 else {
2271 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2272 if (np->driver_data & DEV_HAS_GEAR_MODE)
2273 nv_gear_backoff_reseed(dev);
2274 else
2275 nv_legacybackoff_reseed(dev);
2276 }
2277 }
2278
2147 dev_kfree_skb_any(np->get_tx_ctx->skb); 2279 dev_kfree_skb_any(np->get_tx_ctx->skb);
2148 np->get_tx_ctx->skb = NULL; 2280 np->get_tx_ctx->skb = NULL;
2149 2281
@@ -2905,15 +3037,14 @@ set_speed:
2905 } 3037 }
2906 3038
2907 if (np->gigabit == PHY_GIGABIT) { 3039 if (np->gigabit == PHY_GIGABIT) {
2908 phyreg = readl(base + NvRegRandomSeed); 3040 phyreg = readl(base + NvRegSlotTime);
2909 phyreg &= ~(0x3FF00); 3041 phyreg &= ~(0x3FF00);
2910 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) 3042 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
2911 phyreg |= NVREG_RNDSEED_FORCE3; 3043 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
2912 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) 3044 phyreg |= NVREG_SLOTTIME_10_100_FULL;
2913 phyreg |= NVREG_RNDSEED_FORCE2;
2914 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) 3045 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2915 phyreg |= NVREG_RNDSEED_FORCE; 3046 phyreg |= NVREG_SLOTTIME_1000_FULL;
2916 writel(phyreg, base + NvRegRandomSeed); 3047 writel(phyreg, base + NvRegSlotTime);
2917 } 3048 }
2918 3049
2919 phyreg = readl(base + NvRegPhyInterface); 3050 phyreg = readl(base + NvRegPhyInterface);
@@ -4843,6 +4974,7 @@ static int nv_open(struct net_device *dev)
4843 u8 __iomem *base = get_hwbase(dev); 4974 u8 __iomem *base = get_hwbase(dev);
4844 int ret = 1; 4975 int ret = 1;
4845 int oom, i; 4976 int oom, i;
4977 u32 low;
4846 4978
4847 dprintk(KERN_DEBUG "nv_open: begin\n"); 4979 dprintk(KERN_DEBUG "nv_open: begin\n");
4848 4980
@@ -4902,8 +5034,20 @@ static int nv_open(struct net_device *dev)
4902 writel(np->rx_buf_sz, base + NvRegOffloadConfig); 5034 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4903 5035
4904 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); 5036 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4905 get_random_bytes(&i, sizeof(i)); 5037
4906 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); 5038 get_random_bytes(&low, sizeof(low));
5039 low &= NVREG_SLOTTIME_MASK;
5040 if (np->desc_ver == DESC_VER_1) {
5041 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5042 } else {
5043 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5044 /* setup legacy backoff */
5045 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5046 } else {
5047 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5048 nv_gear_backoff_reseed(dev);
5049 }
5050 }
4907 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); 5051 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4908 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); 5052 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4909 if (poll_interval == -1) { 5053 if (poll_interval == -1) {
@@ -5632,83 +5776,83 @@ static struct pci_device_id pci_tbl[] = {
5632 }, 5776 },
5633 { /* MCP65 Ethernet Controller */ 5777 { /* MCP65 Ethernet Controller */
5634 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20), 5778 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5635 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT, 5779 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5636 }, 5780 },
5637 { /* MCP65 Ethernet Controller */ 5781 { /* MCP65 Ethernet Controller */
5638 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21), 5782 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5639 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT, 5783 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5640 }, 5784 },
5641 { /* MCP65 Ethernet Controller */ 5785 { /* MCP65 Ethernet Controller */
5642 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22), 5786 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5643 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT, 5787 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5644 }, 5788 },
5645 { /* MCP65 Ethernet Controller */ 5789 { /* MCP65 Ethernet Controller */
5646 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23), 5790 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5647 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT, 5791 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5648 }, 5792 },
5649 { /* MCP67 Ethernet Controller */ 5793 { /* MCP67 Ethernet Controller */
5650 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24), 5794 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5651 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 5795 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
5652 }, 5796 },
5653 { /* MCP67 Ethernet Controller */ 5797 { /* MCP67 Ethernet Controller */
5654 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25), 5798 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5655 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 5799 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
5656 }, 5800 },
5657 { /* MCP67 Ethernet Controller */ 5801 { /* MCP67 Ethernet Controller */
5658 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26), 5802 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5659 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 5803 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
5660 }, 5804 },
5661 { /* MCP67 Ethernet Controller */ 5805 { /* MCP67 Ethernet Controller */
5662 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27), 5806 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5663 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR, 5807 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE,
5664 }, 5808 },
5665 { /* MCP73 Ethernet Controller */ 5809 { /* MCP73 Ethernet Controller */
5666 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28), 5810 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
5667 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX, 5811 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
5668 }, 5812 },
5669 { /* MCP73 Ethernet Controller */ 5813 { /* MCP73 Ethernet Controller */
5670 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29), 5814 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
5671 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX, 5815 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
5672 }, 5816 },
5673 { /* MCP73 Ethernet Controller */ 5817 { /* MCP73 Ethernet Controller */
5674 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30), 5818 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
5675 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX, 5819 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
5676 }, 5820 },
5677 { /* MCP73 Ethernet Controller */ 5821 { /* MCP73 Ethernet Controller */
5678 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31), 5822 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
5679 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX, 5823 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE,
5680 }, 5824 },
5681 { /* MCP77 Ethernet Controller */ 5825 { /* MCP77 Ethernet Controller */
5682 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32), 5826 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
5683 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5827 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5684 }, 5828 },
5685 { /* MCP77 Ethernet Controller */ 5829 { /* MCP77 Ethernet Controller */
5686 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33), 5830 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
5687 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5831 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5688 }, 5832 },
5689 { /* MCP77 Ethernet Controller */ 5833 { /* MCP77 Ethernet Controller */
5690 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34), 5834 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
5691 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5835 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5692 }, 5836 },
5693 { /* MCP77 Ethernet Controller */ 5837 { /* MCP77 Ethernet Controller */
5694 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35), 5838 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
5695 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5839 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5696 }, 5840 },
5697 { /* MCP79 Ethernet Controller */ 5841 { /* MCP79 Ethernet Controller */
5698 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36), 5842 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
5699 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5843 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5700 }, 5844 },
5701 { /* MCP79 Ethernet Controller */ 5845 { /* MCP79 Ethernet Controller */
5702 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37), 5846 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
5703 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5847 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5704 }, 5848 },
5705 { /* MCP79 Ethernet Controller */ 5849 { /* MCP79 Ethernet Controller */
5706 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38), 5850 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
5707 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5851 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5708 }, 5852 },
5709 { /* MCP79 Ethernet Controller */ 5853 { /* MCP79 Ethernet Controller */
5710 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39), 5854 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
5711 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT, 5855 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE,
5712 }, 5856 },
5713 {0,}, 5857 {0,},
5714}; 5858};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 20:32:16 -0500