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-rw-r--r--drivers/char/drm/radeon_cp.c9
-rw-r--r--drivers/char/drm/radeon_drv.h1
2 files changed, 8 insertions, 2 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 9f2b4efd0c7a..95ae9e0892ac 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -1312,6 +1312,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1312static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) 1312static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1313{ 1313{
1314 drm_radeon_private_t *dev_priv = dev->dev_private;; 1314 drm_radeon_private_t *dev_priv = dev->dev_private;;
1315 unsigned int mem_size;
1316
1315 DRM_DEBUG("\n"); 1317 DRM_DEBUG("\n");
1316 1318
1317 dev_priv->is_pci = init->is_pci; 1319 dev_priv->is_pci = init->is_pci;
@@ -1521,8 +1523,11 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1521 + dev_priv->fb_location) >> 10)); 1523 + dev_priv->fb_location) >> 10));
1522 1524
1523 dev_priv->gart_size = init->gart_size; 1525 dev_priv->gart_size = init->gart_size;
1524 dev_priv->gart_vm_start = dev_priv->fb_location 1526
1525 + RADEON_READ(RADEON_CONFIG_APER_SIZE) * 2; 1527 mem_size = RADEON_READ(RADEON_CONFIG_MEMSIZE);
1528 if (mem_size == 0)
1529 mem_size = 0x800000;
1530 dev_priv->gart_vm_start = dev_priv->fb_location + mem_size;
1526 1531
1527#if __OS_HAS_AGP 1532#if __OS_HAS_AGP
1528 if (!dev_priv->is_pci) 1533 if (!dev_priv->is_pci)
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 7bda7e33d2bd..d92ccee3e54c 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -379,6 +379,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
379# define RADEON_PLL_WR_EN (1 << 7) 379# define RADEON_PLL_WR_EN (1 << 7)
380#define RADEON_CLOCK_CNTL_INDEX 0x0008 380#define RADEON_CLOCK_CNTL_INDEX 0x0008
381#define RADEON_CONFIG_APER_SIZE 0x0108 381#define RADEON_CONFIG_APER_SIZE 0x0108
382#define RADEON_CONFIG_MEMSIZE 0x00f8
382#define RADEON_CRTC_OFFSET 0x0224 383#define RADEON_CRTC_OFFSET 0x0224
383#define RADEON_CRTC_OFFSET_CNTL 0x0228 384#define RADEON_CRTC_OFFSET_CNTL 0x0228
384# define RADEON_CRTC_TILE_EN (1 << 15) 385# define RADEON_CRTC_TILE_EN (1 << 15)