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-rw-r--r--MAINTAINERS6
-rw-r--r--drivers/net/Kconfig14
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/phy/smsc.c28
-rw-r--r--drivers/net/smsc911x.c2091
-rw-r--r--drivers/net/smsc911x.h394
-rw-r--r--include/linux/smsc911x.h42
7 files changed, 2576 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 129117fe6490..5d951f3db018 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3853,6 +3853,12 @@ M: mhoffman@lightlink.com
3853L: lm-sensors@lm-sensors.org 3853L: lm-sensors@lm-sensors.org
3854S: Maintained 3854S: Maintained
3855 3855
3856SMSC911x ETHERNET DRIVER
3857P: Steve Glendinning
3858M: steve.glendinning@smsc.com
3859L: netdev@vger.kernel.org
3860S: Supported
3861
3856SMX UIO Interface 3862SMX UIO Interface
3857P: Ben Nizette 3863P: Ben Nizette
3858M: bn@niasdigital.com 3864M: bn@niasdigital.com
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index f1d0a1371695..74a18a7f8f40 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -979,6 +979,20 @@ config SMC911X
979 called smc911x. If you want to compile it as a module, say M 979 called smc911x. If you want to compile it as a module, say M
980 here and read <file:Documentation/kbuild/modules.txt> 980 here and read <file:Documentation/kbuild/modules.txt>
981 981
982config SMSC911X
983 tristate "SMSC LAN911x/LAN921x families embedded ethernet support"
984 depends on ARM || SUPERH
985 select CRC32
986 select MII
987 select PHYLIB
988 ---help---
989 Say Y here if you want support for SMSC LAN911x and LAN921x families
990 of ethernet controllers.
991
992 To compile this driver as a module, choose M here and read
993 <file:Documentation/networking/net-modules.txt>. The module
994 will be called smsc911x.
995
982config NET_VENDOR_RACAL 996config NET_VENDOR_RACAL
983 bool "Racal-Interlan (Micom) NI cards" 997 bool "Racal-Interlan (Micom) NI cards"
984 depends on ISA 998 depends on ISA
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 657c47b1a6b6..e06829aa75b0 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -219,6 +219,7 @@ obj-$(CONFIG_S2IO) += s2io.o
219obj-$(CONFIG_MYRI10GE) += myri10ge/ 219obj-$(CONFIG_MYRI10GE) += myri10ge/
220obj-$(CONFIG_SMC91X) += smc91x.o 220obj-$(CONFIG_SMC91X) += smc91x.o
221obj-$(CONFIG_SMC911X) += smc911x.o 221obj-$(CONFIG_SMC911X) += smc911x.o
222obj-$(CONFIG_SMSC911X) += smsc911x.o
222obj-$(CONFIG_BFIN_MAC) += bfin_mac.o 223obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
223obj-$(CONFIG_DM9000) += dm9000.o 224obj-$(CONFIG_DM9000) += dm9000.o
224obj-$(CONFIG_PASEMI_MAC) += pasemi_mac_driver.o 225obj-$(CONFIG_PASEMI_MAC) += pasemi_mac_driver.o
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 73baa7a3bb0e..c05d38d46350 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -126,6 +126,27 @@ static struct phy_driver lan8700_driver = {
126 .driver = { .owner = THIS_MODULE, } 126 .driver = { .owner = THIS_MODULE, }
127}; 127};
128 128
129static struct phy_driver lan911x_int_driver = {
130 .phy_id = 0x0007c0d0, /* OUI=0x00800f, Model#=0x0d */
131 .phy_id_mask = 0xfffffff0,
132 .name = "SMSC LAN911x Internal PHY",
133
134 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
135 | SUPPORTED_Asym_Pause),
136 .flags = PHY_HAS_INTERRUPT | PHY_HAS_MAGICANEG,
137
138 /* basic functions */
139 .config_aneg = genphy_config_aneg,
140 .read_status = genphy_read_status,
141 .config_init = smsc_phy_config_init,
142
143 /* IRQ related */
144 .ack_interrupt = smsc_phy_ack_interrupt,
145 .config_intr = smsc_phy_config_intr,
146
147 .driver = { .owner = THIS_MODULE, }
148};
149
129static int __init smsc_init(void) 150static int __init smsc_init(void)
130{ 151{
131 int ret; 152 int ret;
@@ -142,8 +163,14 @@ static int __init smsc_init(void)
142 if (ret) 163 if (ret)
143 goto err3; 164 goto err3;
144 165
166 ret = phy_driver_register (&lan911x_int_driver);
167 if (ret)
168 goto err4;
169
145 return 0; 170 return 0;
146 171
172err4:
173 phy_driver_unregister (&lan8700_driver);
147err3: 174err3:
148 phy_driver_unregister (&lan8187_driver); 175 phy_driver_unregister (&lan8187_driver);
149err2: 176err2:
@@ -154,6 +181,7 @@ err1:
154 181
155static void __exit smsc_exit(void) 182static void __exit smsc_exit(void)
156{ 183{
184 phy_driver_unregister (&lan911x_int_driver);
157 phy_driver_unregister (&lan8700_driver); 185 phy_driver_unregister (&lan8700_driver);
158 phy_driver_unregister (&lan8187_driver); 186 phy_driver_unregister (&lan8187_driver);
159 phy_driver_unregister (&lan83c185_driver); 187 phy_driver_unregister (&lan83c185_driver);
diff --git a/drivers/net/smsc911x.c b/drivers/net/smsc911x.c
new file mode 100644
index 000000000000..fe517880fc97
--- /dev/null
+++ b/drivers/net/smsc911x.c
@@ -0,0 +1,2091 @@
1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************
21 * Rewritten, heavily based on smsc911x simple driver by SMSC.
22 * Partly uses io macros from smc91x.c by Nicolas Pitre
23 *
24 * Supported devices:
25 * LAN9115, LAN9116, LAN9117, LAN9118
26 * LAN9215, LAN9216, LAN9217, LAN9218
27 * LAN9210, LAN9211
28 * LAN9220, LAN9221
29 *
30 */
31
32#include <linux/crc32.h>
33#include <linux/delay.h>
34#include <linux/errno.h>
35#include <linux/etherdevice.h>
36#include <linux/ethtool.h>
37#include <linux/init.h>
38#include <linux/ioport.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/netdevice.h>
42#include <linux/platform_device.h>
43#include <linux/sched.h>
44#include <linux/slab.h>
45#include <linux/timer.h>
46#include <linux/version.h>
47#include <linux/bug.h>
48#include <linux/bitops.h>
49#include <linux/irq.h>
50#include <linux/io.h>
51#include <linux/phy.h>
52#include <linux/smsc911x.h>
53#include "smsc911x.h"
54
55#define SMSC_CHIPNAME "smsc911x"
56#define SMSC_MDIONAME "smsc911x-mdio"
57#define SMSC_DRV_VERSION "2008-10-21"
58
59MODULE_LICENSE("GPL");
60MODULE_VERSION(SMSC_DRV_VERSION);
61
62#if USE_DEBUG > 0
63static int debug = 16;
64#else
65static int debug = 3;
66#endif
67
68module_param(debug, int, 0);
69MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71struct smsc911x_data {
72 void __iomem *ioaddr;
73
74 unsigned int idrev;
75
76 /* used to decide which workarounds apply */
77 unsigned int generation;
78
79 /* device configuration (copied from platform_data during probe) */
80 unsigned int irq_polarity;
81 unsigned int irq_type;
82 phy_interface_t phy_interface;
83
84 /* This needs to be acquired before calling any of below:
85 * smsc911x_mac_read(), smsc911x_mac_write()
86 */
87 spinlock_t mac_lock;
88
89#if (!SMSC_CAN_USE_32BIT)
90 /* spinlock to ensure 16-bit accesses are serialised */
91 spinlock_t dev_lock;
92#endif
93
94 struct phy_device *phy_dev;
95 struct mii_bus *mii_bus;
96 int phy_irq[PHY_MAX_ADDR];
97 unsigned int using_extphy;
98 int last_duplex;
99 int last_carrier;
100
101 u32 msg_enable;
102 unsigned int gpio_setting;
103 unsigned int gpio_orig_setting;
104 struct net_device *dev;
105 struct napi_struct napi;
106
107 unsigned int software_irq_signal;
108
109#ifdef USE_PHY_WORK_AROUND
110#define MIN_PACKET_SIZE (64)
111 char loopback_tx_pkt[MIN_PACKET_SIZE];
112 char loopback_rx_pkt[MIN_PACKET_SIZE];
113 unsigned int resetcount;
114#endif
115
116 /* Members for Multicast filter workaround */
117 unsigned int multicast_update_pending;
118 unsigned int set_bits_mask;
119 unsigned int clear_bits_mask;
120 unsigned int hashhi;
121 unsigned int hashlo;
122};
123
124#if SMSC_CAN_USE_32BIT
125
126static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
127{
128 return readl(pdata->ioaddr + reg);
129}
130
131static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
132 u32 val)
133{
134 writel(val, pdata->ioaddr + reg);
135}
136
137/* Writes a packet to the TX_DATA_FIFO */
138static inline void
139smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
140 unsigned int wordcount)
141{
142 writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
143}
144
145/* Reads a packet out of the RX_DATA_FIFO */
146static inline void
147smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
148 unsigned int wordcount)
149{
150 readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
151}
152
153#else /* SMSC_CAN_USE_32BIT */
154
155/* These 16-bit access functions are significantly slower, due to the locking
156 * necessary. If your bus hardware can be configured to do this for you
157 * (in response to a single 32-bit operation from software), you should use
158 * the 32-bit access functions instead. */
159
160static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
161{
162 unsigned long flags;
163 u32 data;
164
165 /* these two 16-bit reads must be performed consecutively, so must
166 * not be interrupted by our own ISR (which would start another
167 * read operation) */
168 spin_lock_irqsave(&pdata->dev_lock, flags);
169 data = ((readw(pdata->ioaddr + reg) & 0xFFFF) |
170 ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
171 spin_unlock_irqrestore(&pdata->dev_lock, flags);
172
173 return data;
174}
175
176static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
177 u32 val)
178{
179 unsigned long flags;
180
181 /* these two 16-bit writes must be performed consecutively, so must
182 * not be interrupted by our own ISR (which would start another
183 * read operation) */
184 spin_lock_irqsave(&pdata->dev_lock, flags);
185 writew(val & 0xFFFF, pdata->ioaddr + reg);
186 writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
187 spin_unlock_irqrestore(&pdata->dev_lock, flags);
188}
189
190/* Writes a packet to the TX_DATA_FIFO */
191static inline void
192smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
193 unsigned int wordcount)
194{
195 while (wordcount--)
196 smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
197}
198
199/* Reads a packet out of the RX_DATA_FIFO */
200static inline void
201smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
202 unsigned int wordcount)
203{
204 while (wordcount--)
205 *buf++ = smsc911x_reg_read(pdata, RX_DATA_FIFO);
206}
207
208#endif /* SMSC_CAN_USE_32BIT */
209
210/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
211 * and smsc911x_mac_write, so assumes mac_lock is held */
212static int smsc911x_mac_complete(struct smsc911x_data *pdata)
213{
214 int i;
215 u32 val;
216
217 SMSC_ASSERT_MAC_LOCK(pdata);
218
219 for (i = 0; i < 40; i++) {
220 val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
221 if (!(val & MAC_CSR_CMD_CSR_BUSY_))
222 return 0;
223 }
224 SMSC_WARNING(HW, "Timed out waiting for MAC not BUSY. "
225 "MAC_CSR_CMD: 0x%08X", val);
226 return -EIO;
227}
228
229/* Fetches a MAC register value. Assumes mac_lock is acquired */
230static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
231{
232 unsigned int temp;
233
234 SMSC_ASSERT_MAC_LOCK(pdata);
235
236 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
237 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
238 SMSC_WARNING(HW, "MAC busy at entry");
239 return 0xFFFFFFFF;
240 }
241
242 /* Send the MAC cmd */
243 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
244 MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
245
246 /* Workaround for hardware read-after-write restriction */
247 temp = smsc911x_reg_read(pdata, BYTE_TEST);
248
249 /* Wait for the read to complete */
250 if (likely(smsc911x_mac_complete(pdata) == 0))
251 return smsc911x_reg_read(pdata, MAC_CSR_DATA);
252
253 SMSC_WARNING(HW, "MAC busy after read");
254 return 0xFFFFFFFF;
255}
256
257/* Set a mac register, mac_lock must be acquired before calling */
258static void smsc911x_mac_write(struct smsc911x_data *pdata,
259 unsigned int offset, u32 val)
260{
261 unsigned int temp;
262
263 SMSC_ASSERT_MAC_LOCK(pdata);
264
265 temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
266 if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
267 SMSC_WARNING(HW,
268 "smsc911x_mac_write failed, MAC busy at entry");
269 return;
270 }
271
272 /* Send data to write */
273 smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
274
275 /* Write the actual data */
276 smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
277 MAC_CSR_CMD_CSR_BUSY_));
278
279 /* Workaround for hardware read-after-write restriction */
280 temp = smsc911x_reg_read(pdata, BYTE_TEST);
281
282 /* Wait for the write to complete */
283 if (likely(smsc911x_mac_complete(pdata) == 0))
284 return;
285
286 SMSC_WARNING(HW,
287 "smsc911x_mac_write failed, MAC busy after write");
288}
289
290/* Get a phy register */
291static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
292{
293 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
294 unsigned long flags;
295 unsigned int addr;
296 int i, reg;
297
298 spin_lock_irqsave(&pdata->mac_lock, flags);
299
300 /* Confirm MII not busy */
301 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
302 SMSC_WARNING(HW,
303 "MII is busy in smsc911x_mii_read???");
304 reg = -EIO;
305 goto out;
306 }
307
308 /* Set the address, index & direction (read from PHY) */
309 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
310 smsc911x_mac_write(pdata, MII_ACC, addr);
311
312 /* Wait for read to complete w/ timeout */
313 for (i = 0; i < 100; i++)
314 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
315 reg = smsc911x_mac_read(pdata, MII_DATA);
316 goto out;
317 }
318
319 SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
320 reg = -EIO;
321
322out:
323 spin_unlock_irqrestore(&pdata->mac_lock, flags);
324 return reg;
325}
326
327/* Set a phy register */
328static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
329 u16 val)
330{
331 struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
332 unsigned long flags;
333 unsigned int addr;
334 int i, reg;
335
336 spin_lock_irqsave(&pdata->mac_lock, flags);
337
338 /* Confirm MII not busy */
339 if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
340 SMSC_WARNING(HW,
341 "MII is busy in smsc911x_mii_write???");
342 reg = -EIO;
343 goto out;
344 }
345
346 /* Put the data to write in the MAC */
347 smsc911x_mac_write(pdata, MII_DATA, val);
348
349 /* Set the address, index & direction (write to PHY) */
350 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
351 MII_ACC_MII_WRITE_;
352 smsc911x_mac_write(pdata, MII_ACC, addr);
353
354 /* Wait for write to complete w/ timeout */
355 for (i = 0; i < 100; i++)
356 if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
357 reg = 0;
358 goto out;
359 }
360
361 SMSC_WARNING(HW, "Timed out waiting for MII write to finish");
362 reg = -EIO;
363
364out:
365 spin_unlock_irqrestore(&pdata->mac_lock, flags);
366 return reg;
367}
368
369/* Autodetects and initialises external phy for SMSC9115 and SMSC9117 flavors.
370 * If something goes wrong, returns -ENODEV to revert back to internal phy.
371 * Performed at initialisation only, so interrupts are enabled */
372static int smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
373{
374 unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
375
376 /* External phy is requested, supported, and detected */
377 if (hwcfg & HW_CFG_EXT_PHY_DET_) {
378
379 /* Switch to external phy. Assuming tx and rx are stopped
380 * because smsc911x_phy_initialise is called before
381 * smsc911x_rx_initialise and tx_initialise. */
382
383 /* Disable phy clocks to the MAC */
384 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
385 hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
386 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
387 udelay(10); /* Enough time for clocks to stop */
388
389 /* Switch to external phy */
390 hwcfg |= HW_CFG_EXT_PHY_EN_;
391 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
392
393 /* Enable phy clocks to the MAC */
394 hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
395 hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
396 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
397 udelay(10); /* Enough time for clocks to restart */
398
399 hwcfg |= HW_CFG_SMI_SEL_;
400 smsc911x_reg_write(pdata, HW_CFG, hwcfg);
401
402 SMSC_TRACE(HW, "Successfully switched to external PHY");
403 pdata->using_extphy = 1;
404 } else {
405 SMSC_WARNING(HW, "No external PHY detected, "
406 "Using internal PHY instead.");
407 /* Use internal phy */
408 return -ENODEV;
409 }
410 return 0;
411}
412
413/* Fetches a tx status out of the status fifo */
414static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
415{
416 unsigned int result =
417 smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
418
419 if (result != 0)
420 result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
421
422 return result;
423}
424
425/* Fetches the next rx status */
426static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
427{
428 unsigned int result =
429 smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
430
431 if (result != 0)
432 result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
433
434 return result;
435}
436
437#ifdef USE_PHY_WORK_AROUND
438static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
439{
440 unsigned int tries;
441 u32 wrsz;
442 u32 rdsz;
443 ulong bufp;
444
445 for (tries = 0; tries < 10; tries++) {
446 unsigned int txcmd_a;
447 unsigned int txcmd_b;
448 unsigned int status;
449 unsigned int pktlength;
450 unsigned int i;
451
452 /* Zero-out rx packet memory */
453 memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
454
455 /* Write tx packet to 118 */
456 txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
457 txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
458 txcmd_a |= MIN_PACKET_SIZE;
459
460 txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
461
462 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
463 smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
464
465 bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
466 wrsz = MIN_PACKET_SIZE + 3;
467 wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
468 wrsz >>= 2;
469
470 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
471
472 /* Wait till transmit is done */
473 i = 60;
474 do {
475 udelay(5);
476 status = smsc911x_tx_get_txstatus(pdata);
477 } while ((i--) && (!status));
478
479 if (!status) {
480 SMSC_WARNING(HW, "Failed to transmit "
481 "during loopback test");
482 continue;
483 }
484 if (status & TX_STS_ES_) {
485 SMSC_WARNING(HW, "Transmit encountered "
486 "errors during loopback test");
487 continue;
488 }
489
490 /* Wait till receive is done */
491 i = 60;
492 do {
493 udelay(5);
494 status = smsc911x_rx_get_rxstatus(pdata);
495 } while ((i--) && (!status));
496
497 if (!status) {
498 SMSC_WARNING(HW,
499 "Failed to receive during loopback test");
500 continue;
501 }
502 if (status & RX_STS_ES_) {
503 SMSC_WARNING(HW, "Receive encountered "
504 "errors during loopback test");
505 continue;
506 }
507
508 pktlength = ((status & 0x3FFF0000UL) >> 16);
509 bufp = (ulong)pdata->loopback_rx_pkt;
510 rdsz = pktlength + 3;
511 rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
512 rdsz >>= 2;
513
514 smsc911x_rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
515
516 if (pktlength != (MIN_PACKET_SIZE + 4)) {
517 SMSC_WARNING(HW, "Unexpected packet size "
518 "during loop back test, size=%d, will retry",
519 pktlength);
520 } else {
521 unsigned int j;
522 int mismatch = 0;
523 for (j = 0; j < MIN_PACKET_SIZE; j++) {
524 if (pdata->loopback_tx_pkt[j]
525 != pdata->loopback_rx_pkt[j]) {
526 mismatch = 1;
527 break;
528 }
529 }
530 if (!mismatch) {
531 SMSC_TRACE(HW, "Successfully verified "
532 "loopback packet");
533 return 0;
534 } else {
535 SMSC_WARNING(HW, "Data mismatch "
536 "during loop back test, will retry");
537 }
538 }
539 }
540
541 return -EIO;
542}
543
544static int smsc911x_phy_reset(struct smsc911x_data *pdata)
545{
546 struct phy_device *phy_dev = pdata->phy_dev;
547 unsigned int temp;
548 unsigned int i = 100000;
549
550 BUG_ON(!phy_dev);
551 BUG_ON(!phy_dev->bus);
552
553 SMSC_TRACE(HW, "Performing PHY BCR Reset");
554 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
555 do {
556 msleep(1);
557 temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
558 MII_BMCR);
559 } while ((i--) && (temp & BMCR_RESET));
560
561 if (temp & BMCR_RESET) {
562 SMSC_WARNING(HW, "PHY reset failed to complete.");
563 return -EIO;
564 }
565 /* Extra delay required because the phy may not be completed with
566 * its reset when BMCR_RESET is cleared. Specs say 256 uS is
567 * enough delay but using 1ms here to be safe */
568 msleep(1);
569
570 return 0;
571}
572
573static int smsc911x_phy_loopbacktest(struct net_device *dev)
574{
575 struct smsc911x_data *pdata = netdev_priv(dev);
576 struct phy_device *phy_dev = pdata->phy_dev;
577 int result = -EIO;
578 unsigned int i, val;
579 unsigned long flags;
580
581 /* Initialise tx packet using broadcast destination address */
582 memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
583
584 /* Use incrementing source address */
585 for (i = 6; i < 12; i++)
586 pdata->loopback_tx_pkt[i] = (char)i;
587
588 /* Set length type field */
589 pdata->loopback_tx_pkt[12] = 0x00;
590 pdata->loopback_tx_pkt[13] = 0x00;
591
592 for (i = 14; i < MIN_PACKET_SIZE; i++)
593 pdata->loopback_tx_pkt[i] = (char)i;
594
595 val = smsc911x_reg_read(pdata, HW_CFG);
596 val &= HW_CFG_TX_FIF_SZ_;
597 val |= HW_CFG_SF_;
598 smsc911x_reg_write(pdata, HW_CFG, val);
599
600 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
601 smsc911x_reg_write(pdata, RX_CFG,
602 (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
603
604 for (i = 0; i < 10; i++) {
605 /* Set PHY to 10/FD, no ANEG, and loopback mode */
606 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
607 BMCR_LOOPBACK | BMCR_FULLDPLX);
608
609 /* Enable MAC tx/rx, FD */
610 spin_lock_irqsave(&pdata->mac_lock, flags);
611 smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
612 | MAC_CR_TXEN_ | MAC_CR_RXEN_);
613 spin_unlock_irqrestore(&pdata->mac_lock, flags);
614
615 if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
616 result = 0;
617 break;
618 }
619 pdata->resetcount++;
620
621 /* Disable MAC rx */
622 spin_lock_irqsave(&pdata->mac_lock, flags);
623 smsc911x_mac_write(pdata, MAC_CR, 0);
624 spin_unlock_irqrestore(&pdata->mac_lock, flags);
625
626 smsc911x_phy_reset(pdata);
627 }
628
629 /* Disable MAC */
630 spin_lock_irqsave(&pdata->mac_lock, flags);
631 smsc911x_mac_write(pdata, MAC_CR, 0);
632 spin_unlock_irqrestore(&pdata->mac_lock, flags);
633
634 /* Cancel PHY loopback mode */
635 smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
636
637 smsc911x_reg_write(pdata, TX_CFG, 0);
638 smsc911x_reg_write(pdata, RX_CFG, 0);
639
640 return result;
641}
642#endif /* USE_PHY_WORK_AROUND */
643
644static u8 smsc95xx_resolve_flowctrl_fulldplx(u16 lcladv, u16 rmtadv)
645{
646 u8 cap = 0;
647
648 if (lcladv & ADVERTISE_PAUSE_CAP) {
649 if (lcladv & ADVERTISE_PAUSE_ASYM) {
650 if (rmtadv & LPA_PAUSE_CAP)
651 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
652 else if (rmtadv & LPA_PAUSE_ASYM)
653 cap = FLOW_CTRL_RX;
654 } else {
655 if (rmtadv & LPA_PAUSE_CAP)
656 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
657 }
658 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
659 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
660 cap = FLOW_CTRL_TX;
661 }
662
663 return cap;
664}
665
666static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
667{
668 struct phy_device *phy_dev = pdata->phy_dev;
669 u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
670 u32 flow;
671 unsigned long flags;
672
673 if (phy_dev->duplex == DUPLEX_FULL) {
674 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
675 u16 rmtadv = phy_read(phy_dev, MII_LPA);
676 u8 cap = smsc95xx_resolve_flowctrl_fulldplx(lcladv, rmtadv);
677
678 if (cap & FLOW_CTRL_RX)
679 flow = 0xFFFF0002;
680 else
681 flow = 0;
682
683 if (cap & FLOW_CTRL_TX)
684 afc |= 0xF;
685 else
686 afc &= ~0xF;
687
688 SMSC_TRACE(HW, "rx pause %s, tx pause %s",
689 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
690 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
691 } else {
692 SMSC_TRACE(HW, "half duplex");
693 flow = 0;
694 afc |= 0xF;
695 }
696
697 spin_lock_irqsave(&pdata->mac_lock, flags);
698 smsc911x_mac_write(pdata, FLOW, flow);
699 spin_unlock_irqrestore(&pdata->mac_lock, flags);
700
701 smsc911x_reg_write(pdata, AFC_CFG, afc);
702}
703
704/* Update link mode if anything has changed. Called periodically when the
705 * PHY is in polling mode, even if nothing has changed. */
706static void smsc911x_phy_adjust_link(struct net_device *dev)
707{
708 struct smsc911x_data *pdata = netdev_priv(dev);
709 struct phy_device *phy_dev = pdata->phy_dev;
710 unsigned long flags;
711 int carrier;
712
713 if (phy_dev->duplex != pdata->last_duplex) {
714 unsigned int mac_cr;
715 SMSC_TRACE(HW, "duplex state has changed");
716
717 spin_lock_irqsave(&pdata->mac_lock, flags);
718 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
719 if (phy_dev->duplex) {
720 SMSC_TRACE(HW,
721 "configuring for full duplex mode");
722 mac_cr |= MAC_CR_FDPX_;
723 } else {
724 SMSC_TRACE(HW,
725 "configuring for half duplex mode");
726 mac_cr &= ~MAC_CR_FDPX_;
727 }
728 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
729 spin_unlock_irqrestore(&pdata->mac_lock, flags);
730
731 smsc911x_phy_update_flowcontrol(pdata);
732 pdata->last_duplex = phy_dev->duplex;
733 }
734
735 carrier = netif_carrier_ok(dev);
736 if (carrier != pdata->last_carrier) {
737 SMSC_TRACE(HW, "carrier state has changed");
738 if (carrier) {
739 SMSC_TRACE(HW, "configuring for carrier OK");
740 if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
741 (!pdata->using_extphy)) {
742 /* Restore orginal GPIO configuration */
743 pdata->gpio_setting = pdata->gpio_orig_setting;
744 smsc911x_reg_write(pdata, GPIO_CFG,
745 pdata->gpio_setting);
746 }
747 } else {
748 SMSC_TRACE(HW, "configuring for no carrier");
749 /* Check global setting that LED1
750 * usage is 10/100 indicator */
751 pdata->gpio_setting = smsc911x_reg_read(pdata,
752 GPIO_CFG);
753 if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_)
754 && (!pdata->using_extphy)) {
755 /* Force 10/100 LED off, after saving
756 * orginal GPIO configuration */
757 pdata->gpio_orig_setting = pdata->gpio_setting;
758
759 pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
760 pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
761 | GPIO_CFG_GPIODIR0_
762 | GPIO_CFG_GPIOD0_);
763 smsc911x_reg_write(pdata, GPIO_CFG,
764 pdata->gpio_setting);
765 }
766 }
767 pdata->last_carrier = carrier;
768 }
769}
770
771static int smsc911x_mii_probe(struct net_device *dev)
772{
773 struct smsc911x_data *pdata = netdev_priv(dev);
774 struct phy_device *phydev = NULL;
775 int phy_addr;
776
777 /* find the first phy */
778 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
779 if (pdata->mii_bus->phy_map[phy_addr]) {
780 phydev = pdata->mii_bus->phy_map[phy_addr];
781 SMSC_TRACE(PROBE, "PHY %d: addr %d, phy_id 0x%08X",
782 phy_addr, phydev->addr, phydev->phy_id);
783 break;
784 }
785 }
786
787 if (!phydev) {
788 pr_err("%s: no PHY found\n", dev->name);
789 return -ENODEV;
790 }
791
792 phydev = phy_connect(dev, phydev->dev.bus_id,
793 &smsc911x_phy_adjust_link, 0, pdata->phy_interface);
794
795 if (IS_ERR(phydev)) {
796 pr_err("%s: Could not attach to PHY\n", dev->name);
797 return PTR_ERR(phydev);
798 }
799
800 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
801 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
802
803 /* mask with MAC supported features */
804 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
805 SUPPORTED_Asym_Pause);
806 phydev->advertising = phydev->supported;
807
808 pdata->phy_dev = phydev;
809 pdata->last_duplex = -1;
810 pdata->last_carrier = -1;
811
812#ifdef USE_PHY_WORK_AROUND
813 if (smsc911x_phy_loopbacktest(dev) < 0) {
814 SMSC_WARNING(HW, "Failed Loop Back Test");
815 return -ENODEV;
816 }
817 SMSC_TRACE(HW, "Passed Loop Back Test");
818#endif /* USE_PHY_WORK_AROUND */
819
820 SMSC_TRACE(HW, "phy initialised succesfully");
821 return 0;
822}
823
824static int __devinit smsc911x_mii_init(struct platform_device *pdev,
825 struct net_device *dev)
826{
827 struct smsc911x_data *pdata = netdev_priv(dev);
828 int err = -ENXIO, i;
829
830 pdata->mii_bus = mdiobus_alloc();
831 if (!pdata->mii_bus) {
832 err = -ENOMEM;
833 goto err_out_1;
834 }
835
836 pdata->mii_bus->name = SMSC_MDIONAME;
837 snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
838 pdata->mii_bus->priv = pdata;
839 pdata->mii_bus->read = smsc911x_mii_read;
840 pdata->mii_bus->write = smsc911x_mii_write;
841 pdata->mii_bus->irq = pdata->phy_irq;
842 for (i = 0; i < PHY_MAX_ADDR; ++i)
843 pdata->mii_bus->irq[i] = PHY_POLL;
844
845 pdata->mii_bus->parent = &pdev->dev;
846 dev_set_drvdata(&pdev->dev, &pdata->mii_bus);
847
848 pdata->using_extphy = 0;
849
850 switch (pdata->idrev & 0xFFFF0000) {
851 case 0x01170000:
852 case 0x01150000:
853 case 0x117A0000:
854 case 0x115A0000:
855 /* External PHY supported, try to autodetect */
856 if (smsc911x_phy_initialise_external(pdata) < 0) {
857 SMSC_TRACE(HW, "No external PHY detected, "
858 "using internal PHY");
859 }
860 break;
861 default:
862 SMSC_TRACE(HW, "External PHY is not supported, "
863 "using internal PHY");
864 break;
865 }
866
867 if (!pdata->using_extphy) {
868 /* Mask all PHYs except ID 1 (internal) */
869 pdata->mii_bus->phy_mask = ~(1 << 1);
870 }
871
872 if (mdiobus_register(pdata->mii_bus)) {
873 SMSC_WARNING(PROBE, "Error registering mii bus");
874 goto err_out_free_bus_2;
875 }
876
877 if (smsc911x_mii_probe(dev) < 0) {
878 SMSC_WARNING(PROBE, "Error registering mii bus");
879 goto err_out_unregister_bus_3;
880 }
881
882 return 0;
883
884err_out_unregister_bus_3:
885 mdiobus_unregister(pdata->mii_bus);
886err_out_free_bus_2:
887 mdiobus_free(pdata->mii_bus);
888err_out_1:
889 return err;
890}
891
892/* Gets the number of tx statuses in the fifo */
893static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
894{
895 return (smsc911x_reg_read(pdata, TX_FIFO_INF)
896 & TX_FIFO_INF_TSUSED_) >> 16;
897}
898
899/* Reads tx statuses and increments counters where necessary */
900static void smsc911x_tx_update_txcounters(struct net_device *dev)
901{
902 struct smsc911x_data *pdata = netdev_priv(dev);
903 unsigned int tx_stat;
904
905 while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
906 if (unlikely(tx_stat & 0x80000000)) {
907 /* In this driver the packet tag is used as the packet
908 * length. Since a packet length can never reach the
909 * size of 0x8000, this bit is reserved. It is worth
910 * noting that the "reserved bit" in the warning above
911 * does not reference a hardware defined reserved bit
912 * but rather a driver defined one.
913 */
914 SMSC_WARNING(HW,
915 "Packet tag reserved bit is high");
916 } else {
917 if (unlikely(tx_stat & 0x00008000)) {
918 dev->stats.tx_errors++;
919 } else {
920 dev->stats.tx_packets++;
921 dev->stats.tx_bytes += (tx_stat >> 16);
922 }
923 if (unlikely(tx_stat & 0x00000100)) {
924 dev->stats.collisions += 16;
925 dev->stats.tx_aborted_errors += 1;
926 } else {
927 dev->stats.collisions +=
928 ((tx_stat >> 3) & 0xF);
929 }
930 if (unlikely(tx_stat & 0x00000800))
931 dev->stats.tx_carrier_errors += 1;
932 if (unlikely(tx_stat & 0x00000200)) {
933 dev->stats.collisions++;
934 dev->stats.tx_aborted_errors++;
935 }
936 }
937 }
938}
939
940/* Increments the Rx error counters */
941static void
942smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
943{
944 int crc_err = 0;
945
946 if (unlikely(rxstat & 0x00008000)) {
947 dev->stats.rx_errors++;
948 if (unlikely(rxstat & 0x00000002)) {
949 dev->stats.rx_crc_errors++;
950 crc_err = 1;
951 }
952 }
953 if (likely(!crc_err)) {
954 if (unlikely((rxstat & 0x00001020) == 0x00001020)) {
955 /* Frame type indicates length,
956 * and length error is set */
957 dev->stats.rx_length_errors++;
958 }
959 if (rxstat & RX_STS_MCAST_)
960 dev->stats.multicast++;
961 }
962}
963
964/* Quickly dumps bad packets */
965static void
966smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
967{
968 unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
969
970 if (likely(pktwords >= 4)) {
971 unsigned int timeout = 500;
972 unsigned int val;
973 smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
974 do {
975 udelay(1);
976 val = smsc911x_reg_read(pdata, RX_DP_CTRL);
977 } while (timeout-- && (val & RX_DP_CTRL_RX_FFWD_));
978
979 if (unlikely(timeout == 0))
980 SMSC_WARNING(HW, "Timed out waiting for "
981 "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
982 } else {
983 unsigned int temp;
984 while (pktwords--)
985 temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
986 }
987}
988
989/* NAPI poll function */
990static int smsc911x_poll(struct napi_struct *napi, int budget)
991{
992 struct smsc911x_data *pdata =
993 container_of(napi, struct smsc911x_data, napi);
994 struct net_device *dev = pdata->dev;
995 int npackets = 0;
996
997 while (likely(netif_running(dev)) && (npackets < budget)) {
998 unsigned int pktlength;
999 unsigned int pktwords;
1000 struct sk_buff *skb;
1001 unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
1002
1003 if (!rxstat) {
1004 unsigned int temp;
1005 /* We processed all packets available. Tell NAPI it can
1006 * stop polling then re-enable rx interrupts */
1007 smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
1008 netif_rx_complete(dev, napi);
1009 temp = smsc911x_reg_read(pdata, INT_EN);
1010 temp |= INT_EN_RSFL_EN_;
1011 smsc911x_reg_write(pdata, INT_EN, temp);
1012 break;
1013 }
1014
1015 /* Count packet for NAPI scheduling, even if it has an error.
1016 * Error packets still require cycles to discard */
1017 npackets++;
1018
1019 pktlength = ((rxstat & 0x3FFF0000) >> 16);
1020 pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
1021 smsc911x_rx_counterrors(dev, rxstat);
1022
1023 if (unlikely(rxstat & RX_STS_ES_)) {
1024 SMSC_WARNING(RX_ERR,
1025 "Discarding packet with error bit set");
1026 /* Packet has an error, discard it and continue with
1027 * the next */
1028 smsc911x_rx_fastforward(pdata, pktwords);
1029 dev->stats.rx_dropped++;
1030 continue;
1031 }
1032
1033 skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
1034 if (unlikely(!skb)) {
1035 SMSC_WARNING(RX_ERR,
1036 "Unable to allocate skb for rx packet");
1037 /* Drop the packet and stop this polling iteration */
1038 smsc911x_rx_fastforward(pdata, pktwords);
1039 dev->stats.rx_dropped++;
1040 break;
1041 }
1042
1043 skb->data = skb->head;
1044 skb_reset_tail_pointer(skb);
1045
1046 /* Align IP on 16B boundary */
1047 skb_reserve(skb, NET_IP_ALIGN);
1048 skb_put(skb, pktlength - 4);
1049 smsc911x_rx_readfifo(pdata, (unsigned int *)skb->head,
1050 pktwords);
1051 skb->protocol = eth_type_trans(skb, dev);
1052 skb->ip_summed = CHECKSUM_NONE;
1053 netif_receive_skb(skb);
1054
1055 /* Update counters */
1056 dev->stats.rx_packets++;
1057 dev->stats.rx_bytes += (pktlength - 4);
1058 dev->last_rx = jiffies;
1059 }
1060
1061 /* Return total received packets */
1062 return npackets;
1063}
1064
1065/* Returns hash bit number for given MAC address
1066 * Example:
1067 * 01 00 5E 00 00 01 -> returns bit number 31 */
1068static unsigned int smsc911x_hash(char addr[ETH_ALEN])
1069{
1070 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
1071}
1072
1073static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
1074{
1075 /* Performs the multicast & mac_cr update. This is called when
1076 * safe on the current hardware, and with the mac_lock held */
1077 unsigned int mac_cr;
1078
1079 SMSC_ASSERT_MAC_LOCK(pdata);
1080
1081 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1082 mac_cr |= pdata->set_bits_mask;
1083 mac_cr &= ~(pdata->clear_bits_mask);
1084 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1085 smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
1086 smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
1087 SMSC_TRACE(HW, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
1088 mac_cr, pdata->hashhi, pdata->hashlo);
1089}
1090
1091static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
1092{
1093 unsigned int mac_cr;
1094
1095 /* This function is only called for older LAN911x devices
1096 * (revA or revB), where MAC_CR, HASHH and HASHL should not
1097 * be modified during Rx - newer devices immediately update the
1098 * registers.
1099 *
1100 * This is called from interrupt context */
1101
1102 spin_lock(&pdata->mac_lock);
1103
1104 /* Check Rx has stopped */
1105 if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
1106 SMSC_WARNING(DRV, "Rx not stopped");
1107
1108 /* Perform the update - safe to do now Rx has stopped */
1109 smsc911x_rx_multicast_update(pdata);
1110
1111 /* Re-enable Rx */
1112 mac_cr = smsc911x_mac_read(pdata, MAC_CR);
1113 mac_cr |= MAC_CR_RXEN_;
1114 smsc911x_mac_write(pdata, MAC_CR, mac_cr);
1115
1116 pdata->multicast_update_pending = 0;
1117
1118 spin_unlock(&pdata->mac_lock);
1119}
1120
1121static int smsc911x_soft_reset(struct smsc911x_data *pdata)
1122{
1123 unsigned int timeout;
1124 unsigned int temp;
1125
1126 /* Reset the LAN911x */
1127 smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
1128 timeout = 10;
1129 do {
1130 udelay(10);
1131 temp = smsc911x_reg_read(pdata, HW_CFG);
1132 } while ((--timeout) && (temp & HW_CFG_SRST_));
1133
1134 if (unlikely(temp & HW_CFG_SRST_)) {
1135 SMSC_WARNING(DRV, "Failed to complete reset");
1136 return -EIO;
1137 }
1138 return 0;
1139}
1140
1141/* Sets the device MAC address to dev_addr, called with mac_lock held */
1142static void
1143smsc911x_set_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
1144{
1145 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
1146 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
1147 (dev_addr[1] << 8) | dev_addr[0];
1148
1149 SMSC_ASSERT_MAC_LOCK(pdata);
1150
1151 smsc911x_mac_write(pdata, ADDRH, mac_high16);
1152 smsc911x_mac_write(pdata, ADDRL, mac_low32);
1153}
1154
1155static int smsc911x_open(struct net_device *dev)
1156{
1157 struct smsc911x_data *pdata = netdev_priv(dev);
1158 unsigned int timeout;
1159 unsigned int temp;
1160 unsigned int intcfg;
1161
1162 /* if the phy is not yet registered, retry later*/
1163 if (!pdata->phy_dev) {
1164 SMSC_WARNING(HW, "phy_dev is NULL");
1165 return -EAGAIN;
1166 }
1167
1168 if (!is_valid_ether_addr(dev->dev_addr)) {
1169 SMSC_WARNING(HW, "dev_addr is not a valid MAC address");
1170 return -EADDRNOTAVAIL;
1171 }
1172
1173 /* Reset the LAN911x */
1174 if (smsc911x_soft_reset(pdata)) {
1175 SMSC_WARNING(HW, "soft reset failed");
1176 return -EIO;
1177 }
1178
1179 smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
1180 smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
1181
1182 /* Make sure EEPROM has finished loading before setting GPIO_CFG */
1183 timeout = 50;
1184 while ((timeout--) &&
1185 (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
1186 udelay(10);
1187 }
1188
1189 if (unlikely(timeout == 0))
1190 SMSC_WARNING(IFUP,
1191 "Timed out waiting for EEPROM busy bit to clear");
1192
1193 smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
1194
1195 /* The soft reset above cleared the device's MAC address,
1196 * restore it from local copy (set in probe) */
1197 spin_lock_irq(&pdata->mac_lock);
1198 smsc911x_set_mac_address(pdata, dev->dev_addr);
1199 spin_unlock_irq(&pdata->mac_lock);
1200
1201 /* Initialise irqs, but leave all sources disabled */
1202 smsc911x_reg_write(pdata, INT_EN, 0);
1203 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1204
1205 /* Set interrupt deassertion to 100uS */
1206 intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
1207
1208 if (pdata->irq_polarity) {
1209 SMSC_TRACE(IFUP, "irq polarity: active high");
1210 intcfg |= INT_CFG_IRQ_POL_;
1211 } else {
1212 SMSC_TRACE(IFUP, "irq polarity: active low");
1213 }
1214
1215 if (pdata->irq_type) {
1216 SMSC_TRACE(IFUP, "irq type: push-pull");
1217 intcfg |= INT_CFG_IRQ_TYPE_;
1218 } else {
1219 SMSC_TRACE(IFUP, "irq type: open drain");
1220 }
1221
1222 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1223
1224 SMSC_TRACE(IFUP, "Testing irq handler using IRQ %d", dev->irq);
1225 pdata->software_irq_signal = 0;
1226 smp_wmb();
1227
1228 temp = smsc911x_reg_read(pdata, INT_EN);
1229 temp |= INT_EN_SW_INT_EN_;
1230 smsc911x_reg_write(pdata, INT_EN, temp);
1231
1232 timeout = 1000;
1233 while (timeout--) {
1234 if (pdata->software_irq_signal)
1235 break;
1236 msleep(1);
1237 }
1238
1239 if (!pdata->software_irq_signal) {
1240 dev_warn(&dev->dev, "ISR failed signaling test (IRQ %d)\n",
1241 dev->irq);
1242 return -ENODEV;
1243 }
1244 SMSC_TRACE(IFUP, "IRQ handler passed test using IRQ %d", dev->irq);
1245
1246 dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
1247 (unsigned long)pdata->ioaddr, dev->irq);
1248
1249 /* Bring the PHY up */
1250 phy_start(pdata->phy_dev);
1251
1252 temp = smsc911x_reg_read(pdata, HW_CFG);
1253 /* Preserve TX FIFO size and external PHY configuration */
1254 temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
1255 temp |= HW_CFG_SF_;
1256 smsc911x_reg_write(pdata, HW_CFG, temp);
1257
1258 temp = smsc911x_reg_read(pdata, FIFO_INT);
1259 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1260 temp &= ~(FIFO_INT_RX_STS_LEVEL_);
1261 smsc911x_reg_write(pdata, FIFO_INT, temp);
1262
1263 /* set RX Data offset to 2 bytes for alignment */
1264 smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
1265
1266 /* enable NAPI polling before enabling RX interrupts */
1267 napi_enable(&pdata->napi);
1268
1269 temp = smsc911x_reg_read(pdata, INT_EN);
1270 temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_);
1271 smsc911x_reg_write(pdata, INT_EN, temp);
1272
1273 spin_lock_irq(&pdata->mac_lock);
1274 temp = smsc911x_mac_read(pdata, MAC_CR);
1275 temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
1276 smsc911x_mac_write(pdata, MAC_CR, temp);
1277 spin_unlock_irq(&pdata->mac_lock);
1278
1279 smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
1280
1281 netif_start_queue(dev);
1282 return 0;
1283}
1284
1285/* Entry point for stopping the interface */
1286static int smsc911x_stop(struct net_device *dev)
1287{
1288 struct smsc911x_data *pdata = netdev_priv(dev);
1289 unsigned int temp;
1290
1291 BUG_ON(!pdata->phy_dev);
1292
1293 /* Disable all device interrupts */
1294 temp = smsc911x_reg_read(pdata, INT_CFG);
1295 temp &= ~INT_CFG_IRQ_EN_;
1296 smsc911x_reg_write(pdata, INT_CFG, temp);
1297
1298 /* Stop Tx and Rx polling */
1299 netif_stop_queue(dev);
1300 napi_disable(&pdata->napi);
1301
1302 /* At this point all Rx and Tx activity is stopped */
1303 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1304 smsc911x_tx_update_txcounters(dev);
1305
1306 /* Bring the PHY down */
1307 phy_stop(pdata->phy_dev);
1308
1309 SMSC_TRACE(IFDOWN, "Interface stopped");
1310 return 0;
1311}
1312
1313/* Entry point for transmitting a packet */
1314static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1315{
1316 struct smsc911x_data *pdata = netdev_priv(dev);
1317 unsigned int freespace;
1318 unsigned int tx_cmd_a;
1319 unsigned int tx_cmd_b;
1320 unsigned int temp;
1321 u32 wrsz;
1322 ulong bufp;
1323
1324 freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
1325
1326 if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
1327 SMSC_WARNING(TX_ERR,
1328 "Tx data fifo low, space available: %d", freespace);
1329
1330 /* Word alignment adjustment */
1331 tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
1332 tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
1333 tx_cmd_a |= (unsigned int)skb->len;
1334
1335 tx_cmd_b = ((unsigned int)skb->len) << 16;
1336 tx_cmd_b |= (unsigned int)skb->len;
1337
1338 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
1339 smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
1340
1341 bufp = (ulong)skb->data & (~0x3);
1342 wrsz = (u32)skb->len + 3;
1343 wrsz += (u32)((ulong)skb->data & 0x3);
1344 wrsz >>= 2;
1345
1346 smsc911x_tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
1347 freespace -= (skb->len + 32);
1348 dev_kfree_skb(skb);
1349 dev->trans_start = jiffies;
1350
1351 if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
1352 smsc911x_tx_update_txcounters(dev);
1353
1354 if (freespace < TX_FIFO_LOW_THRESHOLD) {
1355 netif_stop_queue(dev);
1356 temp = smsc911x_reg_read(pdata, FIFO_INT);
1357 temp &= 0x00FFFFFF;
1358 temp |= 0x32000000;
1359 smsc911x_reg_write(pdata, FIFO_INT, temp);
1360 }
1361
1362 return NETDEV_TX_OK;
1363}
1364
1365/* Entry point for getting status counters */
1366static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
1367{
1368 struct smsc911x_data *pdata = netdev_priv(dev);
1369 smsc911x_tx_update_txcounters(dev);
1370 dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
1371 return &dev->stats;
1372}
1373
1374/* Entry point for setting addressing modes */
1375static void smsc911x_set_multicast_list(struct net_device *dev)
1376{
1377 struct smsc911x_data *pdata = netdev_priv(dev);
1378 unsigned long flags;
1379
1380 if (dev->flags & IFF_PROMISC) {
1381 /* Enabling promiscuous mode */
1382 pdata->set_bits_mask = MAC_CR_PRMS_;
1383 pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1384 pdata->hashhi = 0;
1385 pdata->hashlo = 0;
1386 } else if (dev->flags & IFF_ALLMULTI) {
1387 /* Enabling all multicast mode */
1388 pdata->set_bits_mask = MAC_CR_MCPAS_;
1389 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
1390 pdata->hashhi = 0;
1391 pdata->hashlo = 0;
1392 } else if (dev->mc_count > 0) {
1393 /* Enabling specific multicast addresses */
1394 unsigned int hash_high = 0;
1395 unsigned int hash_low = 0;
1396 unsigned int count = 0;
1397 struct dev_mc_list *mc_list = dev->mc_list;
1398
1399 pdata->set_bits_mask = MAC_CR_HPFILT_;
1400 pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
1401
1402 while (mc_list) {
1403 count++;
1404 if ((mc_list->dmi_addrlen) == ETH_ALEN) {
1405 unsigned int bitnum =
1406 smsc911x_hash(mc_list->dmi_addr);
1407 unsigned int mask = 0x01 << (bitnum & 0x1F);
1408 if (bitnum & 0x20)
1409 hash_high |= mask;
1410 else
1411 hash_low |= mask;
1412 } else {
1413 SMSC_WARNING(DRV, "dmi_addrlen != 6");
1414 }
1415 mc_list = mc_list->next;
1416 }
1417 if (count != (unsigned int)dev->mc_count)
1418 SMSC_WARNING(DRV, "mc_count != dev->mc_count");
1419
1420 pdata->hashhi = hash_high;
1421 pdata->hashlo = hash_low;
1422 } else {
1423 /* Enabling local MAC address only */
1424 pdata->set_bits_mask = 0;
1425 pdata->clear_bits_mask =
1426 (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
1427 pdata->hashhi = 0;
1428 pdata->hashlo = 0;
1429 }
1430
1431 spin_lock_irqsave(&pdata->mac_lock, flags);
1432
1433 if (pdata->generation <= 1) {
1434 /* Older hardware revision - cannot change these flags while
1435 * receiving data */
1436 if (!pdata->multicast_update_pending) {
1437 unsigned int temp;
1438 SMSC_TRACE(HW, "scheduling mcast update");
1439 pdata->multicast_update_pending = 1;
1440
1441 /* Request the hardware to stop, then perform the
1442 * update when we get an RX_STOP interrupt */
1443 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1444 temp = smsc911x_reg_read(pdata, INT_EN);
1445 temp |= INT_EN_RXSTOP_INT_EN_;
1446 smsc911x_reg_write(pdata, INT_EN, temp);
1447
1448 temp = smsc911x_mac_read(pdata, MAC_CR);
1449 temp &= ~(MAC_CR_RXEN_);
1450 smsc911x_mac_write(pdata, MAC_CR, temp);
1451 } else {
1452 /* There is another update pending, this should now
1453 * use the newer values */
1454 }
1455 } else {
1456 /* Newer hardware revision - can write immediately */
1457 smsc911x_rx_multicast_update(pdata);
1458 }
1459
1460 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1461}
1462
1463static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
1464{
1465 struct net_device *dev = dev_id;
1466 struct smsc911x_data *pdata = netdev_priv(dev);
1467 u32 intsts = smsc911x_reg_read(pdata, INT_STS);
1468 u32 inten = smsc911x_reg_read(pdata, INT_EN);
1469 int serviced = IRQ_NONE;
1470 u32 temp;
1471
1472 if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
1473 temp = smsc911x_reg_read(pdata, INT_EN);
1474 temp &= (~INT_EN_SW_INT_EN_);
1475 smsc911x_reg_write(pdata, INT_EN, temp);
1476 smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
1477 pdata->software_irq_signal = 1;
1478 smp_wmb();
1479 serviced = IRQ_HANDLED;
1480 }
1481
1482 if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
1483 /* Called when there is a multicast update scheduled and
1484 * it is now safe to complete the update */
1485 SMSC_TRACE(INTR, "RX Stop interrupt");
1486 temp = smsc911x_reg_read(pdata, INT_EN);
1487 temp &= (~INT_EN_RXSTOP_INT_EN_);
1488 smsc911x_reg_write(pdata, INT_EN, temp);
1489 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
1490 smsc911x_rx_multicast_update_workaround(pdata);
1491 serviced = IRQ_HANDLED;
1492 }
1493
1494 if (intsts & inten & INT_STS_TDFA_) {
1495 temp = smsc911x_reg_read(pdata, FIFO_INT);
1496 temp |= FIFO_INT_TX_AVAIL_LEVEL_;
1497 smsc911x_reg_write(pdata, FIFO_INT, temp);
1498 smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
1499 netif_wake_queue(dev);
1500 serviced = IRQ_HANDLED;
1501 }
1502
1503 if (unlikely(intsts & inten & INT_STS_RXE_)) {
1504 SMSC_TRACE(INTR, "RX Error interrupt");
1505 smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
1506 serviced = IRQ_HANDLED;
1507 }
1508
1509 if (likely(intsts & inten & INT_STS_RSFL_)) {
1510 if (likely(netif_rx_schedule_prep(dev, &pdata->napi))) {
1511 /* Disable Rx interrupts */
1512 temp = smsc911x_reg_read(pdata, INT_EN);
1513 temp &= (~INT_EN_RSFL_EN_);
1514 smsc911x_reg_write(pdata, INT_EN, temp);
1515 /* Schedule a NAPI poll */
1516 __netif_rx_schedule(dev, &pdata->napi);
1517 } else {
1518 SMSC_WARNING(RX_ERR,
1519 "netif_rx_schedule_prep failed");
1520 }
1521 serviced = IRQ_HANDLED;
1522 }
1523
1524 return serviced;
1525}
1526
1527#ifdef CONFIG_NET_POLL_CONTROLLER
1528void smsc911x_poll_controller(struct net_device *dev)
1529{
1530 disable_irq(dev->irq);
1531 smsc911x_irqhandler(0, dev);
1532 enable_irq(dev->irq);
1533}
1534#endif /* CONFIG_NET_POLL_CONTROLLER */
1535
1536/* Standard ioctls for mii-tool */
1537static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1538{
1539 struct smsc911x_data *pdata = netdev_priv(dev);
1540
1541 if (!netif_running(dev) || !pdata->phy_dev)
1542 return -EINVAL;
1543
1544 return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd);
1545}
1546
1547static int
1548smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1549{
1550 struct smsc911x_data *pdata = netdev_priv(dev);
1551
1552 cmd->maxtxpkt = 1;
1553 cmd->maxrxpkt = 1;
1554 return phy_ethtool_gset(pdata->phy_dev, cmd);
1555}
1556
1557static int
1558smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1559{
1560 struct smsc911x_data *pdata = netdev_priv(dev);
1561
1562 return phy_ethtool_sset(pdata->phy_dev, cmd);
1563}
1564
1565static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
1566 struct ethtool_drvinfo *info)
1567{
1568 strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
1569 strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
1570 strlcpy(info->bus_info, dev->dev.parent->bus_id,
1571 sizeof(info->bus_info));
1572}
1573
1574static int smsc911x_ethtool_nwayreset(struct net_device *dev)
1575{
1576 struct smsc911x_data *pdata = netdev_priv(dev);
1577
1578 return phy_start_aneg(pdata->phy_dev);
1579}
1580
1581static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
1582{
1583 struct smsc911x_data *pdata = netdev_priv(dev);
1584 return pdata->msg_enable;
1585}
1586
1587static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
1588{
1589 struct smsc911x_data *pdata = netdev_priv(dev);
1590 pdata->msg_enable = level;
1591}
1592
1593static int smsc911x_ethtool_getregslen(struct net_device *dev)
1594{
1595 return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
1596 sizeof(u32);
1597}
1598
1599static void
1600smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
1601 void *buf)
1602{
1603 struct smsc911x_data *pdata = netdev_priv(dev);
1604 struct phy_device *phy_dev = pdata->phy_dev;
1605 unsigned long flags;
1606 unsigned int i;
1607 unsigned int j = 0;
1608 u32 *data = buf;
1609
1610 regs->version = pdata->idrev;
1611 for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
1612 data[j++] = smsc911x_reg_read(pdata, i);
1613
1614 for (i = MAC_CR; i <= WUCSR; i++) {
1615 spin_lock_irqsave(&pdata->mac_lock, flags);
1616 data[j++] = smsc911x_mac_read(pdata, i);
1617 spin_unlock_irqrestore(&pdata->mac_lock, flags);
1618 }
1619
1620 for (i = 0; i <= 31; i++)
1621 data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
1622}
1623
1624static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
1625{
1626 unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
1627 temp &= ~GPIO_CFG_EEPR_EN_;
1628 smsc911x_reg_write(pdata, GPIO_CFG, temp);
1629 msleep(1);
1630}
1631
1632static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
1633{
1634 int timeout = 100;
1635 u32 e2cmd;
1636
1637 SMSC_TRACE(DRV, "op 0x%08x", op);
1638 if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
1639 SMSC_WARNING(DRV, "Busy at start");
1640 return -EBUSY;
1641 }
1642
1643 e2cmd = op | E2P_CMD_EPC_BUSY_;
1644 smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
1645
1646 do {
1647 msleep(1);
1648 e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
1649 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (timeout--));
1650
1651 if (!timeout) {
1652 SMSC_TRACE(DRV, "TIMED OUT");
1653 return -EAGAIN;
1654 }
1655
1656 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
1657 SMSC_TRACE(DRV, "Error occured during eeprom operation");
1658 return -EINVAL;
1659 }
1660
1661 return 0;
1662}
1663
1664static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
1665 u8 address, u8 *data)
1666{
1667 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
1668 int ret;
1669
1670 SMSC_TRACE(DRV, "address 0x%x", address);
1671 ret = smsc911x_eeprom_send_cmd(pdata, op);
1672
1673 if (!ret)
1674 data[address] = smsc911x_reg_read(pdata, E2P_DATA);
1675
1676 return ret;
1677}
1678
1679static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
1680 u8 address, u8 data)
1681{
1682 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
1683 int ret;
1684
1685 SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
1686 ret = smsc911x_eeprom_send_cmd(pdata, op);
1687
1688 if (!ret) {
1689 op = E2P_CMD_EPC_CMD_WRITE_ | address;
1690 smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
1691 ret = smsc911x_eeprom_send_cmd(pdata, op);
1692 }
1693
1694 return ret;
1695}
1696
1697static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
1698{
1699 return SMSC911X_EEPROM_SIZE;
1700}
1701
1702static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
1703 struct ethtool_eeprom *eeprom, u8 *data)
1704{
1705 struct smsc911x_data *pdata = netdev_priv(dev);
1706 u8 eeprom_data[SMSC911X_EEPROM_SIZE];
1707 int len;
1708 int i;
1709
1710 smsc911x_eeprom_enable_access(pdata);
1711
1712 len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
1713 for (i = 0; i < len; i++) {
1714 int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
1715 if (ret < 0) {
1716 eeprom->len = 0;
1717 return ret;
1718 }
1719 }
1720
1721 memcpy(data, &eeprom_data[eeprom->offset], len);
1722 eeprom->len = len;
1723 return 0;
1724}
1725
1726static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
1727 struct ethtool_eeprom *eeprom, u8 *data)
1728{
1729 int ret;
1730 struct smsc911x_data *pdata = netdev_priv(dev);
1731
1732 smsc911x_eeprom_enable_access(pdata);
1733 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
1734 ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
1735 smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
1736
1737 /* Single byte write, according to man page */
1738 eeprom->len = 1;
1739
1740 return ret;
1741}
1742
1743static struct ethtool_ops smsc911x_ethtool_ops = {
1744 .get_settings = smsc911x_ethtool_getsettings,
1745 .set_settings = smsc911x_ethtool_setsettings,
1746 .get_link = ethtool_op_get_link,
1747 .get_drvinfo = smsc911x_ethtool_getdrvinfo,
1748 .nway_reset = smsc911x_ethtool_nwayreset,
1749 .get_msglevel = smsc911x_ethtool_getmsglevel,
1750 .set_msglevel = smsc911x_ethtool_setmsglevel,
1751 .get_regs_len = smsc911x_ethtool_getregslen,
1752 .get_regs = smsc911x_ethtool_getregs,
1753 .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
1754 .get_eeprom = smsc911x_ethtool_get_eeprom,
1755 .set_eeprom = smsc911x_ethtool_set_eeprom,
1756};
1757
1758/* Initializing private device structures, only called from probe */
1759static int __devinit smsc911x_init(struct net_device *dev)
1760{
1761 struct smsc911x_data *pdata = netdev_priv(dev);
1762 unsigned int byte_test;
1763
1764 SMSC_TRACE(PROBE, "Driver Parameters:");
1765 SMSC_TRACE(PROBE, "LAN base: 0x%08lX",
1766 (unsigned long)pdata->ioaddr);
1767 SMSC_TRACE(PROBE, "IRQ: %d", dev->irq);
1768 SMSC_TRACE(PROBE, "PHY will be autodetected.");
1769
1770#if (!SMSC_CAN_USE_32BIT)
1771 spin_lock_init(&pdata->dev_lock);
1772#endif
1773
1774 if (pdata->ioaddr == 0) {
1775 SMSC_WARNING(PROBE, "pdata->ioaddr: 0x00000000");
1776 return -ENODEV;
1777 }
1778
1779 /* Check byte ordering */
1780 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1781 SMSC_TRACE(PROBE, "BYTE_TEST: 0x%08X", byte_test);
1782 if (byte_test == 0x43218765) {
1783 SMSC_TRACE(PROBE, "BYTE_TEST looks swapped, "
1784 "applying WORD_SWAP");
1785 smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
1786
1787 /* 1 dummy read of BYTE_TEST is needed after a write to
1788 * WORD_SWAP before its contents are valid */
1789 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1790
1791 byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
1792 }
1793
1794 if (byte_test != 0x87654321) {
1795 SMSC_WARNING(DRV, "BYTE_TEST: 0x%08X", byte_test);
1796 if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
1797 SMSC_WARNING(PROBE,
1798 "top 16 bits equal to bottom 16 bits");
1799 SMSC_TRACE(PROBE, "This may mean the chip is set "
1800 "for 32 bit while the bus is reading 16 bit");
1801 }
1802 return -ENODEV;
1803 }
1804
1805 /* Default generation to zero (all workarounds apply) */
1806 pdata->generation = 0;
1807
1808 pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
1809 switch (pdata->idrev & 0xFFFF0000) {
1810 case 0x01180000:
1811 case 0x01170000:
1812 case 0x01160000:
1813 case 0x01150000:
1814 /* LAN911[5678] family */
1815 pdata->generation = pdata->idrev & 0x0000FFFF;
1816 break;
1817
1818 case 0x118A0000:
1819 case 0x117A0000:
1820 case 0x116A0000:
1821 case 0x115A0000:
1822 /* LAN921[5678] family */
1823 pdata->generation = 3;
1824 break;
1825
1826 case 0x92100000:
1827 case 0x92110000:
1828 case 0x92200000:
1829 case 0x92210000:
1830 /* LAN9210/LAN9211/LAN9220/LAN9221 */
1831 pdata->generation = 4;
1832 break;
1833
1834 default:
1835 SMSC_WARNING(PROBE, "LAN911x not identified, idrev: 0x%08X",
1836 pdata->idrev);
1837 return -ENODEV;
1838 }
1839
1840 SMSC_TRACE(PROBE, "LAN911x identified, idrev: 0x%08X, generation: %d",
1841 pdata->idrev, pdata->generation);
1842
1843 if (pdata->generation == 0)
1844 SMSC_WARNING(PROBE,
1845 "This driver is not intended for this chip revision");
1846
1847 /* Reset the LAN911x */
1848 if (smsc911x_soft_reset(pdata))
1849 return -ENODEV;
1850
1851 /* Disable all interrupt sources until we bring the device up */
1852 smsc911x_reg_write(pdata, INT_EN, 0);
1853
1854 ether_setup(dev);
1855 dev->open = smsc911x_open;
1856 dev->stop = smsc911x_stop;
1857 dev->hard_start_xmit = smsc911x_hard_start_xmit;
1858 dev->get_stats = smsc911x_get_stats;
1859 dev->set_multicast_list = smsc911x_set_multicast_list;
1860 dev->flags |= IFF_MULTICAST;
1861 dev->do_ioctl = smsc911x_do_ioctl;
1862 netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
1863 dev->ethtool_ops = &smsc911x_ethtool_ops;
1864
1865#ifdef CONFIG_NET_POLL_CONTROLLER
1866 dev->poll_controller = smsc911x_poll_controller;
1867#endif /* CONFIG_NET_POLL_CONTROLLER */
1868
1869 return 0;
1870}
1871
1872static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
1873{
1874 struct net_device *dev;
1875 struct smsc911x_data *pdata;
1876 struct resource *res;
1877
1878 dev = platform_get_drvdata(pdev);
1879 BUG_ON(!dev);
1880 pdata = netdev_priv(dev);
1881 BUG_ON(!pdata);
1882 BUG_ON(!pdata->ioaddr);
1883 BUG_ON(!pdata->phy_dev);
1884
1885 SMSC_TRACE(IFDOWN, "Stopping driver.");
1886
1887 phy_disconnect(pdata->phy_dev);
1888 pdata->phy_dev = NULL;
1889 mdiobus_unregister(pdata->mii_bus);
1890 mdiobus_free(pdata->mii_bus);
1891
1892 platform_set_drvdata(pdev, NULL);
1893 unregister_netdev(dev);
1894 free_irq(dev->irq, dev);
1895 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1896 "smsc911x-memory");
1897 if (!res)
1898 platform_get_resource(pdev, IORESOURCE_MEM, 0);
1899
1900 release_mem_region(res->start, res->end - res->start);
1901
1902 iounmap(pdata->ioaddr);
1903
1904 free_netdev(dev);
1905
1906 return 0;
1907}
1908
1909static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
1910{
1911 struct net_device *dev;
1912 struct smsc911x_data *pdata;
1913 struct resource *res;
1914 unsigned int intcfg = 0;
1915 int res_size;
1916 int retval;
1917 DECLARE_MAC_BUF(mac);
1918
1919 pr_info("%s: Driver version %s.\n", SMSC_CHIPNAME, SMSC_DRV_VERSION);
1920
1921 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1922 "smsc911x-memory");
1923 if (!res)
1924 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1925 if (!res) {
1926 pr_warning("%s: Could not allocate resource.\n",
1927 SMSC_CHIPNAME);
1928 retval = -ENODEV;
1929 goto out_0;
1930 }
1931 res_size = res->end - res->start;
1932
1933 if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
1934 retval = -EBUSY;
1935 goto out_0;
1936 }
1937
1938 dev = alloc_etherdev(sizeof(struct smsc911x_data));
1939 if (!dev) {
1940 pr_warning("%s: Could not allocate device.\n", SMSC_CHIPNAME);
1941 retval = -ENOMEM;
1942 goto out_release_io_1;
1943 }
1944
1945 SET_NETDEV_DEV(dev, &pdev->dev);
1946
1947 pdata = netdev_priv(dev);
1948
1949 dev->irq = platform_get_irq(pdev, 0);
1950 pdata->ioaddr = ioremap_nocache(res->start, res_size);
1951
1952 /* copy config parameters across if present, otherwise pdata
1953 * defaults to zeros */
1954 if (pdev->dev.platform_data) {
1955 struct smsc911x_platform_config *config =
1956 pdev->dev.platform_data;
1957 pdata->irq_polarity = config->irq_polarity;
1958 pdata->irq_type = config->irq_type;
1959 pdata->phy_interface = config->phy_interface;
1960 }
1961
1962 pdata->dev = dev;
1963 pdata->msg_enable = ((1 << debug) - 1);
1964
1965 if (pdata->ioaddr == NULL) {
1966 SMSC_WARNING(PROBE,
1967 "Error smsc911x base address invalid");
1968 retval = -ENOMEM;
1969 goto out_free_netdev_2;
1970 }
1971
1972 retval = smsc911x_init(dev);
1973 if (retval < 0)
1974 goto out_unmap_io_3;
1975
1976 /* configure irq polarity and type before connecting isr */
1977 if (pdata->irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
1978 intcfg |= INT_CFG_IRQ_POL_;
1979
1980 if (pdata->irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
1981 intcfg |= INT_CFG_IRQ_TYPE_;
1982
1983 smsc911x_reg_write(pdata, INT_CFG, intcfg);
1984
1985 /* Ensure interrupts are globally disabled before connecting ISR */
1986 smsc911x_reg_write(pdata, INT_EN, 0);
1987 smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
1988
1989 retval = request_irq(dev->irq, smsc911x_irqhandler, IRQF_DISABLED,
1990 SMSC_CHIPNAME, dev);
1991 if (retval) {
1992 SMSC_WARNING(PROBE,
1993 "Unable to claim requested irq: %d", dev->irq);
1994 goto out_unmap_io_3;
1995 }
1996
1997 platform_set_drvdata(pdev, dev);
1998
1999 retval = register_netdev(dev);
2000 if (retval) {
2001 SMSC_WARNING(PROBE,
2002 "Error %i registering device", retval);
2003 goto out_unset_drvdata_4;
2004 } else {
2005 SMSC_TRACE(PROBE, "Network interface: \"%s\"", dev->name);
2006 }
2007
2008 spin_lock_init(&pdata->mac_lock);
2009
2010 retval = smsc911x_mii_init(pdev, dev);
2011 if (retval) {
2012 SMSC_WARNING(PROBE,
2013 "Error %i initialising mii", retval);
2014 goto out_unregister_netdev_5;
2015 }
2016
2017 spin_lock_irq(&pdata->mac_lock);
2018
2019 /* Check if mac address has been specified when bringing interface up */
2020 if (is_valid_ether_addr(dev->dev_addr)) {
2021 smsc911x_set_mac_address(pdata, dev->dev_addr);
2022 SMSC_TRACE(PROBE, "MAC Address is specified by configuration");
2023 } else {
2024 /* Try reading mac address from device. if EEPROM is present
2025 * it will already have been set */
2026 u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
2027 u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
2028 dev->dev_addr[0] = (u8)(mac_low32);
2029 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
2030 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
2031 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
2032 dev->dev_addr[4] = (u8)(mac_high16);
2033 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
2034
2035 if (is_valid_ether_addr(dev->dev_addr)) {
2036 /* eeprom values are valid so use them */
2037 SMSC_TRACE(PROBE,
2038 "Mac Address is read from LAN911x EEPROM");
2039 } else {
2040 /* eeprom values are invalid, generate random MAC */
2041 random_ether_addr(dev->dev_addr);
2042 smsc911x_set_mac_address(pdata, dev->dev_addr);
2043 SMSC_TRACE(PROBE,
2044 "MAC Address is set to random_ether_addr");
2045 }
2046 }
2047
2048 spin_unlock_irq(&pdata->mac_lock);
2049
2050 dev_info(&dev->dev, "MAC Address: %s\n",
2051 print_mac(mac, dev->dev_addr));
2052
2053 return 0;
2054
2055out_unregister_netdev_5:
2056 unregister_netdev(dev);
2057out_unset_drvdata_4:
2058 platform_set_drvdata(pdev, NULL);
2059 free_irq(dev->irq, dev);
2060out_unmap_io_3:
2061 iounmap(pdata->ioaddr);
2062out_free_netdev_2:
2063 free_netdev(dev);
2064out_release_io_1:
2065 release_mem_region(res->start, res->end - res->start);
2066out_0:
2067 return retval;
2068}
2069
2070static struct platform_driver smsc911x_driver = {
2071 .probe = smsc911x_drv_probe,
2072 .remove = smsc911x_drv_remove,
2073 .driver = {
2074 .name = SMSC_CHIPNAME,
2075 },
2076};
2077
2078/* Entry point for loading the module */
2079static int __init smsc911x_init_module(void)
2080{
2081 return platform_driver_register(&smsc911x_driver);
2082}
2083
2084/* entry point for unloading the module */
2085static void __exit smsc911x_cleanup_module(void)
2086{
2087 platform_driver_unregister(&smsc911x_driver);
2088}
2089
2090module_init(smsc911x_init_module);
2091module_exit(smsc911x_cleanup_module);
diff --git a/drivers/net/smsc911x.h b/drivers/net/smsc911x.h
new file mode 100644
index 000000000000..feb36de274ca
--- /dev/null
+++ b/drivers/net/smsc911x.h
@@ -0,0 +1,394 @@
1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************/
21#ifndef __SMSC911X_H__
22#define __SMSC911X_H__
23
24#define SMSC_CAN_USE_32BIT 1
25#define TX_FIFO_LOW_THRESHOLD ((u32)1600)
26#define SMSC911X_EEPROM_SIZE ((u32)7)
27#define USE_DEBUG 0
28
29/* This is the maximum number of packets to be received every
30 * NAPI poll */
31#define SMSC_NAPI_WEIGHT 16
32
33/* implements a PHY loopback test at initialisation time, to ensure a packet
34 * can be succesfully looped back */
35#define USE_PHY_WORK_AROUND
36
37#define DPRINTK(nlevel, klevel, fmt, args...) \
38 ((void)((NETIF_MSG_##nlevel & pdata->msg_enable) && \
39 printk(KERN_##klevel "%s: %s: " fmt "\n", \
40 pdata->dev->name, __func__, ## args)))
41
42#if USE_DEBUG >= 1
43#define SMSC_WARNING(nlevel, fmt, args...) \
44 DPRINTK(nlevel, WARNING, fmt, ## args)
45#else
46#define SMSC_WARNING(nlevel, fmt, args...) \
47 ({ do {} while (0); 0; })
48#endif
49
50#if USE_DEBUG >= 2
51#define SMSC_TRACE(nlevel, fmt, args...) \
52 DPRINTK(nlevel, INFO, fmt, ## args)
53#else
54#define SMSC_TRACE(nlevel, fmt, args...) \
55 ({ do {} while (0); 0; })
56#endif
57
58#ifdef CONFIG_DEBUG_SPINLOCK
59#define SMSC_ASSERT_MAC_LOCK(pdata) \
60 WARN_ON(!spin_is_locked(&pdata->mac_lock))
61#else
62#define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)
63#endif /* CONFIG_DEBUG_SPINLOCK */
64
65#define FLOW_CTRL_TX (1)
66#define FLOW_CTRL_RX (2)
67
68/* SMSC911x registers and bitfields */
69#define RX_DATA_FIFO 0x00
70
71#define TX_DATA_FIFO 0x20
72#define TX_CMD_A_ON_COMP_ 0x80000000
73#define TX_CMD_A_BUF_END_ALGN_ 0x03000000
74#define TX_CMD_A_4_BYTE_ALGN_ 0x00000000
75#define TX_CMD_A_16_BYTE_ALGN_ 0x01000000
76#define TX_CMD_A_32_BYTE_ALGN_ 0x02000000
77#define TX_CMD_A_DATA_OFFSET_ 0x001F0000
78#define TX_CMD_A_FIRST_SEG_ 0x00002000
79#define TX_CMD_A_LAST_SEG_ 0x00001000
80#define TX_CMD_A_BUF_SIZE_ 0x000007FF
81#define TX_CMD_B_PKT_TAG_ 0xFFFF0000
82#define TX_CMD_B_ADD_CRC_DISABLE_ 0x00002000
83#define TX_CMD_B_DISABLE_PADDING_ 0x00001000
84#define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF
85
86#define RX_STATUS_FIFO 0x40
87#define RX_STS_ES_ 0x00008000
88#define RX_STS_MCAST_ 0x00000400
89
90#define RX_STATUS_FIFO_PEEK 0x44
91
92#define TX_STATUS_FIFO 0x48
93#define TX_STS_ES_ 0x00008000
94
95#define TX_STATUS_FIFO_PEEK 0x4C
96
97#define ID_REV 0x50
98#define ID_REV_CHIP_ID_ 0xFFFF0000
99#define ID_REV_REV_ID_ 0x0000FFFF
100
101#define INT_CFG 0x54
102#define INT_CFG_INT_DEAS_ 0xFF000000
103#define INT_CFG_INT_DEAS_CLR_ 0x00004000
104#define INT_CFG_INT_DEAS_STS_ 0x00002000
105#define INT_CFG_IRQ_INT_ 0x00001000
106#define INT_CFG_IRQ_EN_ 0x00000100
107#define INT_CFG_IRQ_POL_ 0x00000010
108#define INT_CFG_IRQ_TYPE_ 0x00000001
109
110#define INT_STS 0x58
111#define INT_STS_SW_INT_ 0x80000000
112#define INT_STS_TXSTOP_INT_ 0x02000000
113#define INT_STS_RXSTOP_INT_ 0x01000000
114#define INT_STS_RXDFH_INT_ 0x00800000
115#define INT_STS_RXDF_INT_ 0x00400000
116#define INT_STS_TX_IOC_ 0x00200000
117#define INT_STS_RXD_INT_ 0x00100000
118#define INT_STS_GPT_INT_ 0x00080000
119#define INT_STS_PHY_INT_ 0x00040000
120#define INT_STS_PME_INT_ 0x00020000
121#define INT_STS_TXSO_ 0x00010000
122#define INT_STS_RWT_ 0x00008000
123#define INT_STS_RXE_ 0x00004000
124#define INT_STS_TXE_ 0x00002000
125#define INT_STS_TDFU_ 0x00000800
126#define INT_STS_TDFO_ 0x00000400
127#define INT_STS_TDFA_ 0x00000200
128#define INT_STS_TSFF_ 0x00000100
129#define INT_STS_TSFL_ 0x00000080
130#define INT_STS_RXDF_ 0x00000040
131#define INT_STS_RDFL_ 0x00000020
132#define INT_STS_RSFF_ 0x00000010
133#define INT_STS_RSFL_ 0x00000008
134#define INT_STS_GPIO2_INT_ 0x00000004
135#define INT_STS_GPIO1_INT_ 0x00000002
136#define INT_STS_GPIO0_INT_ 0x00000001
137
138#define INT_EN 0x5C
139#define INT_EN_SW_INT_EN_ 0x80000000
140#define INT_EN_TXSTOP_INT_EN_ 0x02000000
141#define INT_EN_RXSTOP_INT_EN_ 0x01000000
142#define INT_EN_RXDFH_INT_EN_ 0x00800000
143#define INT_EN_TIOC_INT_EN_ 0x00200000
144#define INT_EN_RXD_INT_EN_ 0x00100000
145#define INT_EN_GPT_INT_EN_ 0x00080000
146#define INT_EN_PHY_INT_EN_ 0x00040000
147#define INT_EN_PME_INT_EN_ 0x00020000
148#define INT_EN_TXSO_EN_ 0x00010000
149#define INT_EN_RWT_EN_ 0x00008000
150#define INT_EN_RXE_EN_ 0x00004000
151#define INT_EN_TXE_EN_ 0x00002000
152#define INT_EN_TDFU_EN_ 0x00000800
153#define INT_EN_TDFO_EN_ 0x00000400
154#define INT_EN_TDFA_EN_ 0x00000200
155#define INT_EN_TSFF_EN_ 0x00000100
156#define INT_EN_TSFL_EN_ 0x00000080
157#define INT_EN_RXDF_EN_ 0x00000040
158#define INT_EN_RDFL_EN_ 0x00000020
159#define INT_EN_RSFF_EN_ 0x00000010
160#define INT_EN_RSFL_EN_ 0x00000008
161#define INT_EN_GPIO2_INT_ 0x00000004
162#define INT_EN_GPIO1_INT_ 0x00000002
163#define INT_EN_GPIO0_INT_ 0x00000001
164
165#define BYTE_TEST 0x64
166
167#define FIFO_INT 0x68
168#define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000
169#define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000
170#define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00
171#define FIFO_INT_RX_STS_LEVEL_ 0x000000FF
172
173#define RX_CFG 0x6C
174#define RX_CFG_RX_END_ALGN_ 0xC0000000
175#define RX_CFG_RX_END_ALGN4_ 0x00000000
176#define RX_CFG_RX_END_ALGN16_ 0x40000000
177#define RX_CFG_RX_END_ALGN32_ 0x80000000
178#define RX_CFG_RX_DMA_CNT_ 0x0FFF0000
179#define RX_CFG_RX_DUMP_ 0x00008000
180#define RX_CFG_RXDOFF_ 0x00001F00
181
182#define TX_CFG 0x70
183#define TX_CFG_TXS_DUMP_ 0x00008000
184#define TX_CFG_TXD_DUMP_ 0x00004000
185#define TX_CFG_TXSAO_ 0x00000004
186#define TX_CFG_TX_ON_ 0x00000002
187#define TX_CFG_STOP_TX_ 0x00000001
188
189#define HW_CFG 0x74
190#define HW_CFG_TTM_ 0x00200000
191#define HW_CFG_SF_ 0x00100000
192#define HW_CFG_TX_FIF_SZ_ 0x000F0000
193#define HW_CFG_TR_ 0x00003000
194#define HW_CFG_SRST_ 0x00000001
195
196/* only available on 115/117 */
197#define HW_CFG_PHY_CLK_SEL_ 0x00000060
198#define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000
199#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020
200#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040
201#define HW_CFG_SMI_SEL_ 0x00000010
202#define HW_CFG_EXT_PHY_DET_ 0x00000008
203#define HW_CFG_EXT_PHY_EN_ 0x00000004
204#define HW_CFG_SRST_TO_ 0x00000002
205
206/* only available on 116/118 */
207#define HW_CFG_32_16_BIT_MODE_ 0x00000004
208
209#define RX_DP_CTRL 0x78
210#define RX_DP_CTRL_RX_FFWD_ 0x80000000
211
212#define RX_FIFO_INF 0x7C
213#define RX_FIFO_INF_RXSUSED_ 0x00FF0000
214#define RX_FIFO_INF_RXDUSED_ 0x0000FFFF
215
216#define TX_FIFO_INF 0x80
217#define TX_FIFO_INF_TSUSED_ 0x00FF0000
218#define TX_FIFO_INF_TDFREE_ 0x0000FFFF
219
220#define PMT_CTRL 0x84
221#define PMT_CTRL_PM_MODE_ 0x00003000
222#define PMT_CTRL_PM_MODE_D0_ 0x00000000
223#define PMT_CTRL_PM_MODE_D1_ 0x00001000
224#define PMT_CTRL_PM_MODE_D2_ 0x00002000
225#define PMT_CTRL_PM_MODE_D3_ 0x00003000
226#define PMT_CTRL_PHY_RST_ 0x00000400
227#define PMT_CTRL_WOL_EN_ 0x00000200
228#define PMT_CTRL_ED_EN_ 0x00000100
229#define PMT_CTRL_PME_TYPE_ 0x00000040
230#define PMT_CTRL_WUPS_ 0x00000030
231#define PMT_CTRL_WUPS_NOWAKE_ 0x00000000
232#define PMT_CTRL_WUPS_ED_ 0x00000010
233#define PMT_CTRL_WUPS_WOL_ 0x00000020
234#define PMT_CTRL_WUPS_MULTI_ 0x00000030
235#define PMT_CTRL_PME_IND_ 0x00000008
236#define PMT_CTRL_PME_POL_ 0x00000004
237#define PMT_CTRL_PME_EN_ 0x00000002
238#define PMT_CTRL_READY_ 0x00000001
239
240#define GPIO_CFG 0x88
241#define GPIO_CFG_LED3_EN_ 0x40000000
242#define GPIO_CFG_LED2_EN_ 0x20000000
243#define GPIO_CFG_LED1_EN_ 0x10000000
244#define GPIO_CFG_GPIO2_INT_POL_ 0x04000000
245#define GPIO_CFG_GPIO1_INT_POL_ 0x02000000
246#define GPIO_CFG_GPIO0_INT_POL_ 0x01000000
247#define GPIO_CFG_EEPR_EN_ 0x00700000
248#define GPIO_CFG_GPIOBUF2_ 0x00040000
249#define GPIO_CFG_GPIOBUF1_ 0x00020000
250#define GPIO_CFG_GPIOBUF0_ 0x00010000
251#define GPIO_CFG_GPIODIR2_ 0x00000400
252#define GPIO_CFG_GPIODIR1_ 0x00000200
253#define GPIO_CFG_GPIODIR0_ 0x00000100
254#define GPIO_CFG_GPIOD4_ 0x00000020
255#define GPIO_CFG_GPIOD3_ 0x00000010
256#define GPIO_CFG_GPIOD2_ 0x00000004
257#define GPIO_CFG_GPIOD1_ 0x00000002
258#define GPIO_CFG_GPIOD0_ 0x00000001
259
260#define GPT_CFG 0x8C
261#define GPT_CFG_TIMER_EN_ 0x20000000
262#define GPT_CFG_GPT_LOAD_ 0x0000FFFF
263
264#define GPT_CNT 0x90
265#define GPT_CNT_GPT_CNT_ 0x0000FFFF
266
267#define WORD_SWAP 0x98
268
269#define FREE_RUN 0x9C
270
271#define RX_DROP 0xA0
272
273#define MAC_CSR_CMD 0xA4
274#define MAC_CSR_CMD_CSR_BUSY_ 0x80000000
275#define MAC_CSR_CMD_R_NOT_W_ 0x40000000
276#define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF
277
278#define MAC_CSR_DATA 0xA8
279
280#define AFC_CFG 0xAC
281#define AFC_CFG_AFC_HI_ 0x00FF0000
282#define AFC_CFG_AFC_LO_ 0x0000FF00
283#define AFC_CFG_BACK_DUR_ 0x000000F0
284#define AFC_CFG_FCMULT_ 0x00000008
285#define AFC_CFG_FCBRD_ 0x00000004
286#define AFC_CFG_FCADD_ 0x00000002
287#define AFC_CFG_FCANY_ 0x00000001
288
289#define E2P_CMD 0xB0
290#define E2P_CMD_EPC_BUSY_ 0x80000000
291#define E2P_CMD_EPC_CMD_ 0x70000000
292#define E2P_CMD_EPC_CMD_READ_ 0x00000000
293#define E2P_CMD_EPC_CMD_EWDS_ 0x10000000
294#define E2P_CMD_EPC_CMD_EWEN_ 0x20000000
295#define E2P_CMD_EPC_CMD_WRITE_ 0x30000000
296#define E2P_CMD_EPC_CMD_WRAL_ 0x40000000
297#define E2P_CMD_EPC_CMD_ERASE_ 0x50000000
298#define E2P_CMD_EPC_CMD_ERAL_ 0x60000000
299#define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000
300#define E2P_CMD_EPC_TIMEOUT_ 0x00000200
301#define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100
302#define E2P_CMD_EPC_ADDR_ 0x000000FF
303
304#define E2P_DATA 0xB4
305#define E2P_DATA_EEPROM_DATA_ 0x000000FF
306#define LAN_REGISTER_EXTENT 0x00000100
307
308/*
309 * MAC Control and Status Register (Indirect Address)
310 * Offset (through the MAC_CSR CMD and DATA port)
311 */
312#define MAC_CR 0x01
313#define MAC_CR_RXALL_ 0x80000000
314#define MAC_CR_HBDIS_ 0x10000000
315#define MAC_CR_RCVOWN_ 0x00800000
316#define MAC_CR_LOOPBK_ 0x00200000
317#define MAC_CR_FDPX_ 0x00100000
318#define MAC_CR_MCPAS_ 0x00080000
319#define MAC_CR_PRMS_ 0x00040000
320#define MAC_CR_INVFILT_ 0x00020000
321#define MAC_CR_PASSBAD_ 0x00010000
322#define MAC_CR_HFILT_ 0x00008000
323#define MAC_CR_HPFILT_ 0x00002000
324#define MAC_CR_LCOLL_ 0x00001000
325#define MAC_CR_BCAST_ 0x00000800
326#define MAC_CR_DISRTY_ 0x00000400
327#define MAC_CR_PADSTR_ 0x00000100
328#define MAC_CR_BOLMT_MASK_ 0x000000C0
329#define MAC_CR_DFCHK_ 0x00000020
330#define MAC_CR_TXEN_ 0x00000008
331#define MAC_CR_RXEN_ 0x00000004
332
333#define ADDRH 0x02
334
335#define ADDRL 0x03
336
337#define HASHH 0x04
338
339#define HASHL 0x05
340
341#define MII_ACC 0x06
342#define MII_ACC_PHY_ADDR_ 0x0000F800
343#define MII_ACC_MIIRINDA_ 0x000007C0
344#define MII_ACC_MII_WRITE_ 0x00000002
345#define MII_ACC_MII_BUSY_ 0x00000001
346
347#define MII_DATA 0x07
348
349#define FLOW 0x08
350#define FLOW_FCPT_ 0xFFFF0000
351#define FLOW_FCPASS_ 0x00000004
352#define FLOW_FCEN_ 0x00000002
353#define FLOW_FCBSY_ 0x00000001
354
355#define VLAN1 0x09
356
357#define VLAN2 0x0A
358
359#define WUFF 0x0B
360
361#define WUCSR 0x0C
362#define WUCSR_GUE_ 0x00000200
363#define WUCSR_WUFR_ 0x00000040
364#define WUCSR_MPR_ 0x00000020
365#define WUCSR_WAKE_EN_ 0x00000004
366#define WUCSR_MPEN_ 0x00000002
367
368/*
369 * Phy definitions (vendor-specific)
370 */
371#define LAN9118_PHY_ID 0x00C0001C
372
373#define MII_INTSTS 0x1D
374
375#define MII_INTMSK 0x1E
376#define PHY_INTMSK_AN_RCV_ (1 << 1)
377#define PHY_INTMSK_PDFAULT_ (1 << 2)
378#define PHY_INTMSK_AN_ACK_ (1 << 3)
379#define PHY_INTMSK_LNKDOWN_ (1 << 4)
380#define PHY_INTMSK_RFAULT_ (1 << 5)
381#define PHY_INTMSK_AN_COMP_ (1 << 6)
382#define PHY_INTMSK_ENERGYON_ (1 << 7)
383#define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ | \
384 PHY_INTMSK_AN_COMP_ | \
385 PHY_INTMSK_RFAULT_ | \
386 PHY_INTMSK_LNKDOWN_)
387
388#define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP | \
389 ADVERTISE_PAUSE_ASYM)
390
391#define LPA_PAUSE_ALL (LPA_PAUSE_CAP | \
392 LPA_PAUSE_ASYM)
393
394#endif /* __SMSC911X_H__ */
diff --git a/include/linux/smsc911x.h b/include/linux/smsc911x.h
new file mode 100644
index 000000000000..47c4ffd10dbb
--- /dev/null
+++ b/include/linux/smsc911x.h
@@ -0,0 +1,42 @@
1/***************************************************************************
2 *
3 * Copyright (C) 2004-2008 SMSC
4 * Copyright (C) 2005-2008 ARM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 ***************************************************************************/
21#ifndef __LINUX_SMSC911X_H__
22#define __LINUX_SMSC911X_H__
23
24#include <linux/phy.h>
25
26/* platform_device configuration data, should be assigned to
27 * the platform_device's dev.platform_data */
28struct smsc911x_platform_config {
29 unsigned int irq_polarity;
30 unsigned int irq_type;
31 phy_interface_t phy_interface;
32};
33
34/* Constants for platform_device irq polarity configuration */
35#define SMSC911X_IRQ_POLARITY_ACTIVE_LOW 0
36#define SMSC911X_IRQ_POLARITY_ACTIVE_HIGH 1
37
38/* Constants for platform_device irq type configuration */
39#define SMSC911X_IRQ_TYPE_OPEN_DRAIN 0
40#define SMSC911X_IRQ_TYPE_PUSH_PULL 1
41
42#endif /* __LINUX_SMSC911X_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 12:49:02 -0500