diff options
| -rw-r--r-- | Documentation/arm/IXP4xx | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp4xx/io.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/arm/IXP4xx b/Documentation/arm/IXP4xx index d4c6d3aa0c25..43edb4ecf27d 100644 --- a/Documentation/arm/IXP4xx +++ b/Documentation/arm/IXP4xx | |||
| @@ -85,7 +85,7 @@ IXP4xx provides two methods of accessing PCI memory space: | |||
| 85 | 2) If > 64MB of memory space is required, the IXP4xx can be | 85 | 2) If > 64MB of memory space is required, the IXP4xx can be |
| 86 | configured to use indirect registers to access PCI This allows | 86 | configured to use indirect registers to access PCI This allows |
| 87 | for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. | 87 | for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. |
| 88 | The disadvantadge of this is that every PCI access requires | 88 | The disadvantage of this is that every PCI access requires |
| 89 | three local register accesses plus a spinlock, but in some | 89 | three local register accesses plus a spinlock, but in some |
| 90 | cases the performance hit is acceptable. In addition, you cannot | 90 | cases the performance hit is acceptable. In addition, you cannot |
| 91 | mmap() PCI devices in this case due to the indirect nature | 91 | mmap() PCI devices in this case due to the indirect nature |
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h index b59520e56fc7..0d517267fb63 100644 --- a/include/asm-arm/arch-ixp4xx/io.h +++ b/include/asm-arm/arch-ixp4xx/io.h | |||
| @@ -38,7 +38,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | |||
| 38 | * 2) If > 64MB of memory space is required, the IXP4xx can be configured | 38 | * 2) If > 64MB of memory space is required, the IXP4xx can be configured |
| 39 | * to use indirect registers to access PCI (as we do below for I/O | 39 | * to use indirect registers to access PCI (as we do below for I/O |
| 40 | * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) | 40 | * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) |
| 41 | * of memory on the bus. The disadvantadge of this is that every | 41 | * of memory on the bus. The disadvantage of this is that every |
| 42 | * PCI access requires three local register accesses plus a spinlock, | 42 | * PCI access requires three local register accesses plus a spinlock, |
| 43 | * but in some cases the performance hit is acceptable. In addition, | 43 | * but in some cases the performance hit is acceptable. In addition, |
| 44 | * you cannot mmap() PCI devices in this case. | 44 | * you cannot mmap() PCI devices in this case. |