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-rw-r--r--drivers/net/bnx2x_fw_defs.h9
-rw-r--r--drivers/net/bnx2x_hsi.h2
-rw-r--r--drivers/net/bnx2x_init.h94
-rw-r--r--drivers/net/bnx2x_link.c5
-rw-r--r--drivers/net/bnx2x_main.c43
5 files changed, 78 insertions, 75 deletions
diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h
index f6dacb03bdd6..0683e542e942 100644
--- a/drivers/net/bnx2x_fw_defs.h
+++ b/drivers/net/bnx2x_fw_defs.h
@@ -194,7 +194,7 @@
194#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0 194#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
195 195
196/** 196/**
197* This file defines HSI constatnts for the ETH flow 197* This file defines HSI constants for the ETH flow
198*/ 198*/
199#ifdef _EVEREST_MICROCODE 199#ifdef _EVEREST_MICROCODE
200#include "microcode_constants.h" 200#include "microcode_constants.h"
@@ -212,7 +212,8 @@
212#define IPV6_HASH_TYPE 3 212#define IPV6_HASH_TYPE 3
213#define TCP_IPV6_HASH_TYPE 4 213#define TCP_IPV6_HASH_TYPE 4
214 214
215/* Ethernet Ring parmaters */ 215
216/* Ethernet Ring parameters */
216#define X_ETH_LOCAL_RING_SIZE 13 217#define X_ETH_LOCAL_RING_SIZE 13
217#define FIRST_BD_IN_PKT 0 218#define FIRST_BD_IN_PKT 0
218#define PARSE_BD_INDEX 1 219#define PARSE_BD_INDEX 1
@@ -279,7 +280,7 @@
279 280
280 281
281/** 282/**
282* This file defines HSI constatnts common to all microcode flows 283* This file defines HSI constants common to all microcode flows
283*/ 284*/
284 285
285/* Connection types */ 286/* Connection types */
@@ -313,7 +314,7 @@
313#define HC_USTORM_SB_NUM_INDICES 4 314#define HC_USTORM_SB_NUM_INDICES 4
314#define HC_CSTORM_SB_NUM_INDICES 4 315#define HC_CSTORM_SB_NUM_INDICES 4
315 316
316/* index values - which counterto update */ 317/* index values - which counter to update */
317 318
318#define HC_INDEX_U_TOE_RX_CQ_CONS 0 319#define HC_INDEX_U_TOE_RX_CQ_CONS 0
319#define HC_INDEX_U_ETH_RX_CQ_CONS 1 320#define HC_INDEX_U_ETH_RX_CQ_CONS 1
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
index 51c5fe16e2dd..966b4a2de962 100644
--- a/drivers/net/bnx2x_hsi.h
+++ b/drivers/net/bnx2x_hsi.h
@@ -1671,7 +1671,7 @@ struct xstorm_eth_ag_context {
1671}; 1671};
1672 1672
1673/* 1673/*
1674 * The eth aggregative context section of Tstorm 1674 * The eth extra aggregative context section of Tstorm
1675 */ 1675 */
1676struct tstorm_eth_extra_ag_context_section { 1676struct tstorm_eth_extra_ag_context_section {
1677 u32 __agg_val1; 1677 u32 __agg_val1;
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 6fcd1dc51d97..ba370f713b2d 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -429,57 +429,57 @@ struct arb_line {
429 429
430/* derived configuration for each read queue for each max request size */ 430/* derived configuration for each read queue for each max request size */
431static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = { 431static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
432 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} }, 432/* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
433 {{4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4} }, 433 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
434 {{4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3} }, 434 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
435 {{8 , 3 , 6}, {16 , 3 , 11}, {16 , 3 , 11}, {16 , 3 , 11} }, 435 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
436 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} }, 436 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
437 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, 437 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
438 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, 438 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
439 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, 439 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
440 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} }, 440 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
441 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 441/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
442 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 442 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
443 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 443 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
444 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 444 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
445 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 445 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
446 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 446 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
447 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 447 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
448 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 448 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
449 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 449 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
450 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 450 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
451 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 451/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
452 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 452 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
453 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 453 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
454 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 454 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
455 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 455 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
456 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 456 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
457 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 457 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
458 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 458 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
459 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} }, 459 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
460 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81}, {64 , 64 , 120} } 460 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
461}; 461};
462 462
463/* derived configuration for each write queue for each max request size */ 463/* derived configuration for each write queue for each max request size */
464static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = { 464static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
465 {{4 , 6 , 3}, {4 , 6 , 3}, {4 , 6 , 3} }, 465/* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
466 {{4 , 2 , 3}, {4 , 2 , 3}, {4 , 2 , 3} }, 466 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
467 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, 467 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
468 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, 468 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
469 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, 469 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
470 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} }, 470 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
471 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25} }, 471 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
472 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, 472 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
473 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} }, 473 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
474 {{8 , 9 , 6}, {16 , 9 , 11}, {32 , 9 , 21} }, 474/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
475 {{8 , 47 , 19}, {16 , 47 , 19}, {32 , 47 , 21} }, 475 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
476 {{8 , 9 , 6}, {16 , 9 , 11}, {16 , 9 , 11} }, 476 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
477 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} } 477 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
478}; 478};
479 479
480/* register addresses for read queues */ 480/* register addresses for read queues */
481static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { 481static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
482 {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, 482/* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
483 PXP2_REG_RQ_BW_RD_UBOUND0}, 483 PXP2_REG_RQ_BW_RD_UBOUND0},
484 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, 484 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
485 PXP2_REG_PSWRQ_BW_UB1}, 485 PXP2_REG_PSWRQ_BW_UB1},
@@ -497,7 +497,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
497 PXP2_REG_PSWRQ_BW_UB7}, 497 PXP2_REG_PSWRQ_BW_UB7},
498 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, 498 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
499 PXP2_REG_PSWRQ_BW_UB8}, 499 PXP2_REG_PSWRQ_BW_UB8},
500 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, 500/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
501 PXP2_REG_PSWRQ_BW_UB9}, 501 PXP2_REG_PSWRQ_BW_UB9},
502 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, 502 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
503 PXP2_REG_PSWRQ_BW_UB10}, 503 PXP2_REG_PSWRQ_BW_UB10},
@@ -517,7 +517,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
517 PXP2_REG_RQ_BW_RD_UBOUND17}, 517 PXP2_REG_RQ_BW_RD_UBOUND17},
518 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18, 518 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
519 PXP2_REG_RQ_BW_RD_UBOUND18}, 519 PXP2_REG_RQ_BW_RD_UBOUND18},
520 {PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19, 520/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
521 PXP2_REG_RQ_BW_RD_UBOUND19}, 521 PXP2_REG_RQ_BW_RD_UBOUND19},
522 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20, 522 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
523 PXP2_REG_RQ_BW_RD_UBOUND20}, 523 PXP2_REG_RQ_BW_RD_UBOUND20},
@@ -539,7 +539,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
539 539
540/* register addresses for write queues */ 540/* register addresses for write queues */
541static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { 541static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
542 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, 542/* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
543 PXP2_REG_PSWRQ_BW_UB1}, 543 PXP2_REG_PSWRQ_BW_UB1},
544 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, 544 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
545 PXP2_REG_PSWRQ_BW_UB2}, 545 PXP2_REG_PSWRQ_BW_UB2},
@@ -557,7 +557,7 @@ static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
557 PXP2_REG_PSWRQ_BW_UB10}, 557 PXP2_REG_PSWRQ_BW_UB10},
558 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, 558 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
559 PXP2_REG_PSWRQ_BW_UB11}, 559 PXP2_REG_PSWRQ_BW_UB11},
560 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, 560/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
561 PXP2_REG_PSWRQ_BW_UB28}, 561 PXP2_REG_PSWRQ_BW_UB28},
562 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29, 562 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
563 PXP2_REG_RQ_BW_WR_UBOUND29}, 563 PXP2_REG_RQ_BW_WR_UBOUND29},
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index 5a17c7c90286..e1a4e39fc0e3 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -4823,6 +4823,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
4823 return -EINVAL; 4823 return -EINVAL;
4824 break; 4824 break;
4825 } 4825 }
4826 DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
4826 4827
4827 bnx2x_link_initialize(params, vars); 4828 bnx2x_link_initialize(params, vars);
4828 msleep(30); 4829 msleep(30);
@@ -5179,7 +5180,7 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
5179 5180
5180 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 5181 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
5181 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 5182 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
5182 /* Phase2 of POWER_DOWN_RESET*/ 5183 /* Phase2 of POWER_DOWN_RESET */
5183 /* Release bit 10 (Release Tx power down) */ 5184 /* Release bit 10 (Release Tx power down) */
5184 bnx2x_cl45_read(bp, port, 5185 bnx2x_cl45_read(bp, port,
5185 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 5186 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
@@ -5258,7 +5259,7 @@ u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
5258 u8 rc = 0; 5259 u8 rc = 0;
5259 u32 ext_phy_type; 5260 u32 ext_phy_type;
5260 5261
5261 DP(NETIF_MSG_LINK, "bnx2x_common_init_phy\n"); 5262 DP(NETIF_MSG_LINK, "Begin common phy init\n");
5262 5263
5263 /* Read the ext_phy_type for arbitrary port(0) */ 5264 /* Read the ext_phy_type for arbitrary port(0) */
5264 ext_phy_type = XGXS_EXT_PHY_TYPE( 5265 ext_phy_type = XGXS_EXT_PHY_TYPE(
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 0d6015f2af37..ae36bc7b0276 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -1704,7 +1704,7 @@ static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1704 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1704 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1705 return IRQ_NONE; 1705 return IRQ_NONE;
1706 } 1706 }
1707 DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status); 1707 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1708 1708
1709 /* Return here if interrupt is disabled */ 1709 /* Return here if interrupt is disabled */
1710 if (unlikely(atomic_read(&bp->intr_sem) != 0)) { 1710 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
@@ -2115,7 +2115,7 @@ static u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2115 2115
2116 return rc; 2116 return rc;
2117 } 2117 }
2118 BNX2X_ERR("Bootcode is missing -not initializing link\n"); 2118 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2119 return -EINVAL; 2119 return -EINVAL;
2120} 2120}
2121 2121
@@ -2128,7 +2128,7 @@ static void bnx2x_link_set(struct bnx2x *bp)
2128 2128
2129 bnx2x_calc_fc_adv(bp); 2129 bnx2x_calc_fc_adv(bp);
2130 } else 2130 } else
2131 BNX2X_ERR("Bootcode is missing -not setting link\n"); 2131 BNX2X_ERR("Bootcode is missing - can not set link\n");
2132} 2132}
2133 2133
2134static void bnx2x__link_reset(struct bnx2x *bp) 2134static void bnx2x__link_reset(struct bnx2x *bp)
@@ -2138,7 +2138,7 @@ static void bnx2x__link_reset(struct bnx2x *bp)
2138 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2138 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2139 bnx2x_release_phy_lock(bp); 2139 bnx2x_release_phy_lock(bp);
2140 } else 2140 } else
2141 BNX2X_ERR("Bootcode is missing -not resetting link\n"); 2141 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2142} 2142}
2143 2143
2144static u8 bnx2x_link_test(struct bnx2x *bp) 2144static u8 bnx2x_link_test(struct bnx2x *bp)
@@ -5139,8 +5139,8 @@ static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5139 fp->cl_id = BP_L_ID(bp) + i; 5139 fp->cl_id = BP_L_ID(bp) + i;
5140 fp->sb_id = fp->cl_id; 5140 fp->sb_id = fp->cl_id;
5141 DP(NETIF_MSG_IFUP, 5141 DP(NETIF_MSG_IFUP,
5142 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n", 5142 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d sb %d\n",
5143 bp, fp->status_blk, i, fp->cl_id, fp->sb_id); 5143 i, bp, fp->status_blk, fp->cl_id, fp->sb_id);
5144 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping, 5144 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
5145 fp->sb_id); 5145 fp->sb_id);
5146 bnx2x_update_fpsb_idx(fp); 5146 bnx2x_update_fpsb_idx(fp);
@@ -6904,11 +6904,11 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6904 } else { 6904 } else {
6905 int port = BP_PORT(bp); 6905 int port = BP_PORT(bp);
6906 6906
6907 DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n", 6907 DP(NETIF_MSG_IFUP, "NO MCP - load counts %d, %d, %d\n",
6908 load_count[0], load_count[1], load_count[2]); 6908 load_count[0], load_count[1], load_count[2]);
6909 load_count[0]++; 6909 load_count[0]++;
6910 load_count[1 + port]++; 6910 load_count[1 + port]++;
6911 DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n", 6911 DP(NETIF_MSG_IFUP, "NO MCP - new load counts %d, %d, %d\n",
6912 load_count[0], load_count[1], load_count[2]); 6912 load_count[0], load_count[1], load_count[2]);
6913 if (load_count[0] == 1) 6913 if (load_count[0] == 1)
6914 load_code = FW_MSG_CODE_DRV_LOAD_COMMON; 6914 load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
@@ -6955,7 +6955,7 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6955 6955
6956 if (CHIP_IS_E1H(bp)) 6956 if (CHIP_IS_E1H(bp))
6957 if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) { 6957 if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
6958 BNX2X_ERR("!!! mf_cfg function disabled\n"); 6958 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
6959 bp->state = BNX2X_STATE_DISABLED; 6959 bp->state = BNX2X_STATE_DISABLED;
6960 } 6960 }
6961 6961
@@ -7028,8 +7028,6 @@ load_error1:
7028 netif_napi_del(&bnx2x_fp(bp, i, napi)); 7028 netif_napi_del(&bnx2x_fp(bp, i, napi));
7029 bnx2x_free_mem(bp); 7029 bnx2x_free_mem(bp);
7030 7030
7031 /* TBD we really need to reset the chip
7032 if we want to recover from this */
7033 return rc; 7031 return rc;
7034} 7032}
7035 7033
@@ -7303,11 +7301,11 @@ unload_error:
7303 if (!BP_NOMCP(bp)) 7301 if (!BP_NOMCP(bp))
7304 reset_code = bnx2x_fw_command(bp, reset_code); 7302 reset_code = bnx2x_fw_command(bp, reset_code);
7305 else { 7303 else {
7306 DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n", 7304 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts %d, %d, %d\n",
7307 load_count[0], load_count[1], load_count[2]); 7305 load_count[0], load_count[1], load_count[2]);
7308 load_count[0]--; 7306 load_count[0]--;
7309 load_count[1 + port]--; 7307 load_count[1 + port]--;
7310 DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n", 7308 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts %d, %d, %d\n",
7311 load_count[0], load_count[1], load_count[2]); 7309 load_count[0], load_count[1], load_count[2]);
7312 if (load_count[0] == 0) 7310 if (load_count[0] == 0)
7313 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 7311 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
@@ -7615,7 +7613,7 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7615 bp->flags |= NO_WOL_FLAG; 7613 bp->flags |= NO_WOL_FLAG;
7616 } 7614 }
7617 BNX2X_DEV_INFO("%sWoL capable\n", 7615 BNX2X_DEV_INFO("%sWoL capable\n",
7618 (bp->flags & NO_WOL_FLAG) ? "Not " : ""); 7616 (bp->flags & NO_WOL_FLAG) ? "not " : "");
7619 7617
7620 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 7618 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7621 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 7619 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
@@ -8111,7 +8109,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8111 "(0x%04x)\n", 8109 "(0x%04x)\n",
8112 func, bp->e1hov, bp->e1hov); 8110 func, bp->e1hov, bp->e1hov);
8113 } else { 8111 } else {
8114 BNX2X_DEV_INFO("Single function mode\n"); 8112 BNX2X_DEV_INFO("single function mode\n");
8115 if (BP_E1HVN(bp)) { 8113 if (BP_E1HVN(bp)) {
8116 BNX2X_ERR("!!! No valid E1HOV for func %d," 8114 BNX2X_ERR("!!! No valid E1HOV for func %d,"
8117 " aborting\n", func); 8115 " aborting\n", func);
@@ -9519,7 +9517,7 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
9519 9517
9520 rc = bnx2x_nvram_read(bp, 0, data, 4); 9518 rc = bnx2x_nvram_read(bp, 0, data, 4);
9521 if (rc) { 9519 if (rc) {
9522 DP(NETIF_MSG_PROBE, "magic value read (rc -%d)\n", -rc); 9520 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
9523 goto test_nvram_exit; 9521 goto test_nvram_exit;
9524 } 9522 }
9525 9523
@@ -9536,7 +9534,7 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
9536 nvram_tbl[i].size); 9534 nvram_tbl[i].size);
9537 if (rc) { 9535 if (rc) {
9538 DP(NETIF_MSG_PROBE, 9536 DP(NETIF_MSG_PROBE,
9539 "nvram_tbl[%d] read data (rc -%d)\n", i, -rc); 9537 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
9540 goto test_nvram_exit; 9538 goto test_nvram_exit;
9541 } 9539 }
9542 9540
@@ -10173,7 +10171,9 @@ static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
10173} 10171}
10174 10172
10175#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3) 10173#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
10176/* check if packet requires linearization (packet is too fragmented) */ 10174/* check if packet requires linearization (packet is too fragmented)
10175 no need to check fragmentation if page size > 8K (there will be no
10176 violation to FW restrictions) */
10177static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb, 10177static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
10178 u32 xmit_type) 10178 u32 xmit_type)
10179{ 10179{
@@ -10295,8 +10295,9 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
10295 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type); 10295 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
10296 10296
10297#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3) 10297#if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
10298 /* First, check if we need to linearize the skb 10298 /* First, check if we need to linearize the skb (due to FW
10299 (due to FW restrictions) */ 10299 restrictions). No need to check fragmentation if page size > 8K
10300 (there will be no violation to FW restrictions) */
10300 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) { 10301 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
10301 /* Statistics of linearization */ 10302 /* Statistics of linearization */
10302 bp->lin_cnt++; 10303 bp->lin_cnt++;
@@ -10557,7 +10558,7 @@ static int bnx2x_close(struct net_device *dev)
10557 return 0; 10558 return 0;
10558} 10559}
10559 10560
10560/* called with netif_tx_lock from set_multicast */ 10561/* called with netif_tx_lock from dev_mcast.c */
10561static void bnx2x_set_rx_mode(struct net_device *dev) 10562static void bnx2x_set_rx_mode(struct net_device *dev)
10562{ 10563{
10563 struct bnx2x *bp = netdev_priv(dev); 10564 struct bnx2x *bp = netdev_priv(dev);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 02:54:30 -0500