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-rw-r--r--MAINTAINERS7
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/qmgr.h35
-rw-r--r--arch/arm/mach-ixp4xx/ixp4xx_qmgr.c44
-rw-r--r--drivers/net/arm/Kconfig2
-rw-r--r--drivers/net/arm/ixp4xx_eth.c337
-rw-r--r--drivers/net/wan/Kconfig7
-rw-r--r--drivers/net/wan/Makefile1
-rw-r--r--drivers/net/wan/hdlc_ppp.c11
-rw-r--r--drivers/net/wan/ixp4xx_hss.c1325
9 files changed, 1585 insertions, 184 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 4b54fda5ac72..7f73db02c53e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1844,7 +1844,7 @@ P: Haavard Skinnemoen
1844M: hskinnemoen@atmel.com 1844M: hskinnemoen@atmel.com
1845S: Supported 1845S: Supported
1846 1846
1847GENERIC HDLC DRIVER, N2, C101, PCI200SYN and WANXL DRIVERS 1847GENERIC HDLC (WAN) DRIVERS
1848P: Krzysztof Halasa 1848P: Krzysztof Halasa
1849M: khc@pm.waw.pl 1849M: khc@pm.waw.pl
1850W: http://www.kernel.org/pub/linux/utils/net/hdlc/ 1850W: http://www.kernel.org/pub/linux/utils/net/hdlc/
@@ -2243,6 +2243,11 @@ M: dan.j.williams@intel.com
2243L: linux-kernel@vger.kernel.org 2243L: linux-kernel@vger.kernel.org
2244S: Supported 2244S: Supported
2245 2245
2246INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT
2247P: Krzysztof Halasa
2248M: khc@pm.waw.pl
2249S: Maintained
2250
2246INTEL IXP4XX RANDOM NUMBER GENERATOR SUPPORT 2251INTEL IXP4XX RANDOM NUMBER GENERATOR SUPPORT
2247P: Deepak Saxena 2252P: Deepak Saxena
2248M: dsaxena@plexity.net 2253M: dsaxena@plexity.net
diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
index 1e52b95cede5..0cbe6ceb67c5 100644
--- a/arch/arm/mach-ixp4xx/include/mach/qmgr.h
+++ b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
@@ -12,6 +12,8 @@
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14 14
15#define DEBUG_QMGR 0
16
15#define HALF_QUEUES 32 17#define HALF_QUEUES 32
16#define QUEUES 64 /* only 32 lower queues currently supported */ 18#define QUEUES 64 /* only 32 lower queues currently supported */
17#define MAX_QUEUE_LENGTH 4 /* in dwords */ 19#define MAX_QUEUE_LENGTH 4 /* in dwords */
@@ -61,22 +63,51 @@ void qmgr_enable_irq(unsigned int queue);
61void qmgr_disable_irq(unsigned int queue); 63void qmgr_disable_irq(unsigned int queue);
62 64
63/* request_ and release_queue() must be called from non-IRQ context */ 65/* request_ and release_queue() must be called from non-IRQ context */
66
67#if DEBUG_QMGR
68extern char qmgr_queue_descs[QUEUES][32];
69
64int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, 70int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
65 unsigned int nearly_empty_watermark, 71 unsigned int nearly_empty_watermark,
66 unsigned int nearly_full_watermark); 72 unsigned int nearly_full_watermark,
73 const char *desc_format, const char* name);
74#else
75int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
76 unsigned int nearly_empty_watermark,
77 unsigned int nearly_full_watermark);
78#define qmgr_request_queue(queue, len, nearly_empty_watermark, \
79 nearly_full_watermark, desc_format, name) \
80 __qmgr_request_queue(queue, len, nearly_empty_watermark, \
81 nearly_full_watermark)
82#endif
83
67void qmgr_release_queue(unsigned int queue); 84void qmgr_release_queue(unsigned int queue);
68 85
69 86
70static inline void qmgr_put_entry(unsigned int queue, u32 val) 87static inline void qmgr_put_entry(unsigned int queue, u32 val)
71{ 88{
72 extern struct qmgr_regs __iomem *qmgr_regs; 89 extern struct qmgr_regs __iomem *qmgr_regs;
90#if DEBUG_QMGR
91 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
92
93 printk(KERN_DEBUG "Queue %s(%i) put %X\n",
94 qmgr_queue_descs[queue], queue, val);
95#endif
73 __raw_writel(val, &qmgr_regs->acc[queue][0]); 96 __raw_writel(val, &qmgr_regs->acc[queue][0]);
74} 97}
75 98
76static inline u32 qmgr_get_entry(unsigned int queue) 99static inline u32 qmgr_get_entry(unsigned int queue)
77{ 100{
101 u32 val;
78 extern struct qmgr_regs __iomem *qmgr_regs; 102 extern struct qmgr_regs __iomem *qmgr_regs;
79 return __raw_readl(&qmgr_regs->acc[queue][0]); 103 val = __raw_readl(&qmgr_regs->acc[queue][0]);
104#if DEBUG_QMGR
105 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
106
107 printk(KERN_DEBUG "Queue %s(%i) get %X\n",
108 qmgr_queue_descs[queue], queue, val);
109#endif
110 return val;
80} 111}
81 112
82static inline int qmgr_get_stat1(unsigned int queue) 113static inline int qmgr_get_stat1(unsigned int queue)
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
index c6cb069a5a83..bfddc73d0a20 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
@@ -14,8 +14,6 @@
14#include <linux/module.h> 14#include <linux/module.h>
15#include <mach/qmgr.h> 15#include <mach/qmgr.h>
16 16
17#define DEBUG 0
18
19struct qmgr_regs __iomem *qmgr_regs; 17struct qmgr_regs __iomem *qmgr_regs;
20static struct resource *mem_res; 18static struct resource *mem_res;
21static spinlock_t qmgr_lock; 19static spinlock_t qmgr_lock;
@@ -23,6 +21,10 @@ static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
23static void (*irq_handlers[HALF_QUEUES])(void *pdev); 21static void (*irq_handlers[HALF_QUEUES])(void *pdev);
24static void *irq_pdevs[HALF_QUEUES]; 22static void *irq_pdevs[HALF_QUEUES];
25 23
24#if DEBUG_QMGR
25char qmgr_queue_descs[QUEUES][32];
26#endif
27
26void qmgr_set_irq(unsigned int queue, int src, 28void qmgr_set_irq(unsigned int queue, int src,
27 void (*handler)(void *pdev), void *pdev) 29 void (*handler)(void *pdev), void *pdev)
28{ 30{
@@ -70,6 +72,7 @@ void qmgr_disable_irq(unsigned int queue)
70 spin_lock_irqsave(&qmgr_lock, flags); 72 spin_lock_irqsave(&qmgr_lock, flags);
71 __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue), 73 __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
72 &qmgr_regs->irqen[0]); 74 &qmgr_regs->irqen[0]);
75 __raw_writel(1 << queue, &qmgr_regs->irqstat[0]); /* clear */
73 spin_unlock_irqrestore(&qmgr_lock, flags); 76 spin_unlock_irqrestore(&qmgr_lock, flags);
74} 77}
75 78
@@ -81,9 +84,16 @@ static inline void shift_mask(u32 *mask)
81 mask[0] <<= 1; 84 mask[0] <<= 1;
82} 85}
83 86
87#if DEBUG_QMGR
84int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */, 88int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
85 unsigned int nearly_empty_watermark, 89 unsigned int nearly_empty_watermark,
86 unsigned int nearly_full_watermark) 90 unsigned int nearly_full_watermark,
91 const char *desc_format, const char* name)
92#else
93int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
94 unsigned int nearly_empty_watermark,
95 unsigned int nearly_full_watermark)
96#endif
87{ 97{
88 u32 cfg, addr = 0, mask[4]; /* in 16-dwords */ 98 u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
89 int err; 99 int err;
@@ -151,12 +161,13 @@ int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
151 used_sram_bitmap[2] |= mask[2]; 161 used_sram_bitmap[2] |= mask[2];
152 used_sram_bitmap[3] |= mask[3]; 162 used_sram_bitmap[3] |= mask[3];
153 __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]); 163 __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
154 spin_unlock_irq(&qmgr_lock); 164#if DEBUG_QMGR
155 165 snprintf(qmgr_queue_descs[queue], sizeof(qmgr_queue_descs[0]),
156#if DEBUG 166 desc_format, name);
157 printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n", 167 printk(KERN_DEBUG "qmgr: requested queue %s(%i) addr = 0x%02X\n",
158 queue, addr); 168 qmgr_queue_descs[queue], queue, addr);
159#endif 169#endif
170 spin_unlock_irq(&qmgr_lock);
160 return 0; 171 return 0;
161 172
162err: 173err:
@@ -189,6 +200,11 @@ void qmgr_release_queue(unsigned int queue)
189 while (addr--) 200 while (addr--)
190 shift_mask(mask); 201 shift_mask(mask);
191 202
203#if DEBUG_QMGR
204 printk(KERN_DEBUG "qmgr: releasing queue %s(%i)\n",
205 qmgr_queue_descs[queue], queue);
206 qmgr_queue_descs[queue][0] = '\x0';
207#endif
192 __raw_writel(0, &qmgr_regs->sram[queue]); 208 __raw_writel(0, &qmgr_regs->sram[queue]);
193 209
194 used_sram_bitmap[0] &= ~mask[0]; 210 used_sram_bitmap[0] &= ~mask[0];
@@ -199,9 +215,10 @@ void qmgr_release_queue(unsigned int queue)
199 spin_unlock_irq(&qmgr_lock); 215 spin_unlock_irq(&qmgr_lock);
200 216
201 module_put(THIS_MODULE); 217 module_put(THIS_MODULE);
202#if DEBUG 218
203 printk(KERN_DEBUG "qmgr: released queue %i\n", queue); 219 while ((addr = qmgr_get_entry(queue)))
204#endif 220 printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
221 queue, addr);
205} 222}
206 223
207static int qmgr_init(void) 224static int qmgr_init(void)
@@ -272,5 +289,10 @@ EXPORT_SYMBOL(qmgr_regs);
272EXPORT_SYMBOL(qmgr_set_irq); 289EXPORT_SYMBOL(qmgr_set_irq);
273EXPORT_SYMBOL(qmgr_enable_irq); 290EXPORT_SYMBOL(qmgr_enable_irq);
274EXPORT_SYMBOL(qmgr_disable_irq); 291EXPORT_SYMBOL(qmgr_disable_irq);
292#if DEBUG_QMGR
293EXPORT_SYMBOL(qmgr_queue_descs);
275EXPORT_SYMBOL(qmgr_request_queue); 294EXPORT_SYMBOL(qmgr_request_queue);
295#else
296EXPORT_SYMBOL(__qmgr_request_queue);
297#endif
276EXPORT_SYMBOL(qmgr_release_queue); 298EXPORT_SYMBOL(qmgr_release_queue);
diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
index abe17762e6f5..2895db13bfa4 100644
--- a/drivers/net/arm/Kconfig
+++ b/drivers/net/arm/Kconfig
@@ -59,7 +59,7 @@ config EP93XX_ETH
59config IXP4XX_ETH 59config IXP4XX_ETH
60 tristate "Intel IXP4xx Ethernet support" 60 tristate "Intel IXP4xx Ethernet support"
61 depends on ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR 61 depends on ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR
62 select MII 62 select PHYLIB
63 help 63 help
64 Say Y here if you want to use built-in Ethernet ports 64 Say Y here if you want to use built-in Ethernet ports
65 on IXP4xx processor. 65 on IXP4xx processor.
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index b03609f2e90f..26af411fc428 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -30,12 +30,11 @@
30#include <linux/etherdevice.h> 30#include <linux/etherdevice.h>
31#include <linux/io.h> 31#include <linux/io.h>
32#include <linux/kernel.h> 32#include <linux/kernel.h>
33#include <linux/mii.h> 33#include <linux/phy.h>
34#include <linux/platform_device.h> 34#include <linux/platform_device.h>
35#include <mach/npe.h> 35#include <mach/npe.h>
36#include <mach/qmgr.h> 36#include <mach/qmgr.h>
37 37
38#define DEBUG_QUEUES 0
39#define DEBUG_DESC 0 38#define DEBUG_DESC 0
40#define DEBUG_RX 0 39#define DEBUG_RX 0
41#define DEBUG_TX 0 40#define DEBUG_TX 0
@@ -59,7 +58,6 @@
59#define NAPI_WEIGHT 16 58#define NAPI_WEIGHT 16
60#define MDIO_INTERVAL (3 * HZ) 59#define MDIO_INTERVAL (3 * HZ)
61#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ 60#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
62#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */
63#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ 61#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
64 62
65#define NPE_ID(port_id) ((port_id) >> 4) 63#define NPE_ID(port_id) ((port_id) >> 4)
@@ -164,15 +162,14 @@ struct port {
164 struct npe *npe; 162 struct npe *npe;
165 struct net_device *netdev; 163 struct net_device *netdev;
166 struct napi_struct napi; 164 struct napi_struct napi;
167 struct net_device_stats stat; 165 struct phy_device *phydev;
168 struct mii_if_info mii;
169 struct delayed_work mdio_thread;
170 struct eth_plat_info *plat; 166 struct eth_plat_info *plat;
171 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; 167 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
172 struct desc *desc_tab; /* coherent */ 168 struct desc *desc_tab; /* coherent */
173 u32 desc_tab_phys; 169 u32 desc_tab_phys;
174 int id; /* logical port ID */ 170 int id; /* logical port ID */
175 u16 mii_bmcr; 171 int speed, duplex;
172 u8 firmware[4];
176}; 173};
177 174
178/* NPE message structure */ 175/* NPE message structure */
@@ -243,19 +240,20 @@ static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
243 240
244static spinlock_t mdio_lock; 241static spinlock_t mdio_lock;
245static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ 242static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
243struct mii_bus *mdio_bus;
246static int ports_open; 244static int ports_open;
247static struct port *npe_port_tab[MAX_NPES]; 245static struct port *npe_port_tab[MAX_NPES];
248static struct dma_pool *dma_pool; 246static struct dma_pool *dma_pool;
249 247
250 248
251static u16 mdio_cmd(struct net_device *dev, int phy_id, int location, 249static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
252 int write, u16 cmd) 250 int write, u16 cmd)
253{ 251{
254 int cycles = 0; 252 int cycles = 0;
255 253
256 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { 254 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
257 printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name); 255 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
258 return 0; 256 return -1;
259 } 257 }
260 258
261 if (write) { 259 if (write) {
@@ -274,107 +272,119 @@ static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
274 } 272 }
275 273
276 if (cycles == MAX_MDIO_RETRIES) { 274 if (cycles == MAX_MDIO_RETRIES) {
277 printk(KERN_ERR "%s: MII write failed\n", dev->name); 275 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
278 return 0; 276 phy_id);
277 return -1;
279 } 278 }
280 279
281#if DEBUG_MDIO 280#if DEBUG_MDIO
282 printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name, 281 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
283 cycles); 282 phy_id, write ? "write" : "read", cycles);
284#endif 283#endif
285 284
286 if (write) 285 if (write)
287 return 0; 286 return 0;
288 287
289 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { 288 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
290 printk(KERN_ERR "%s: MII read failed\n", dev->name); 289#if DEBUG_MDIO
291 return 0; 290 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
291 phy_id);
292#endif
293 return 0xFFFF; /* don't return error */
292 } 294 }
293 295
294 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | 296 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
295 (__raw_readl(&mdio_regs->mdio_status[1]) << 8); 297 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
296} 298}
297 299
298static int mdio_read(struct net_device *dev, int phy_id, int location) 300static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
299{ 301{
300 unsigned long flags; 302 unsigned long flags;
301 u16 val; 303 int ret;
302 304
303 spin_lock_irqsave(&mdio_lock, flags); 305 spin_lock_irqsave(&mdio_lock, flags);
304 val = mdio_cmd(dev, phy_id, location, 0, 0); 306 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
305 spin_unlock_irqrestore(&mdio_lock, flags); 307 spin_unlock_irqrestore(&mdio_lock, flags);
306 return val; 308#if DEBUG_MDIO
309 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
310 phy_id, location, ret);
311#endif
312 return ret;
307} 313}
308 314
309static void mdio_write(struct net_device *dev, int phy_id, int location, 315static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
310 int val) 316 u16 val)
311{ 317{
312 unsigned long flags; 318 unsigned long flags;
319 int ret;
313 320
314 spin_lock_irqsave(&mdio_lock, flags); 321 spin_lock_irqsave(&mdio_lock, flags);
315 mdio_cmd(dev, phy_id, location, 1, val); 322 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
316 spin_unlock_irqrestore(&mdio_lock, flags); 323 spin_unlock_irqrestore(&mdio_lock, flags);
324#if DEBUG_MDIO
325 printk(KERN_DEBUG "%s #%i: MII read [%i] <- 0x%X, err = %i\n",
326 bus->name, phy_id, location, val, ret);
327#endif
328 return ret;
317} 329}
318 330
319static void phy_reset(struct net_device *dev, int phy_id) 331static int ixp4xx_mdio_register(void)
320{ 332{
321 struct port *port = netdev_priv(dev); 333 int err;
322 int cycles = 0;
323 334
324 mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET); 335 if (!(mdio_bus = mdiobus_alloc()))
336 return -ENOMEM;
325 337
326 while (cycles < MAX_MII_RESET_RETRIES) { 338 /* All MII PHY accesses use NPE-B Ethernet registers */
327 if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) { 339 spin_lock_init(&mdio_lock);
328#if DEBUG_MDIO 340 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
329 printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n", 341 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
330 dev->name, cycles); 342
331#endif 343 mdio_bus->name = "IXP4xx MII Bus";
332 return; 344 mdio_bus->read = &ixp4xx_mdio_read;
333 } 345 mdio_bus->write = &ixp4xx_mdio_write;
334 udelay(1); 346 strcpy(mdio_bus->id, "0");
335 cycles++;
336 }
337 347
338 printk(KERN_ERR "%s: MII reset failed\n", dev->name); 348 if ((err = mdiobus_register(mdio_bus)))
349 mdiobus_free(mdio_bus);
350 return err;
339} 351}
340 352
341static void eth_set_duplex(struct port *port) 353static void ixp4xx_mdio_remove(void)
342{ 354{
343 if (port->mii.full_duplex) 355 mdiobus_unregister(mdio_bus);
344 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, 356 mdiobus_free(mdio_bus);
345 &port->regs->tx_control[0]);
346 else
347 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
348 &port->regs->tx_control[0]);
349} 357}
350 358
351 359
352static void phy_check_media(struct port *port, int init) 360static void ixp4xx_adjust_link(struct net_device *dev)
353{ 361{
354 if (mii_check_media(&port->mii, 1, init)) 362 struct port *port = netdev_priv(dev);
355 eth_set_duplex(port); 363 struct phy_device *phydev = port->phydev;
356 if (port->mii.force_media) { /* mii_check_media() doesn't work */ 364
357 struct net_device *dev = port->netdev; 365 if (!phydev->link) {
358 int cur_link = mii_link_ok(&port->mii); 366 if (port->speed) {
359 int prev_link = netif_carrier_ok(dev); 367 port->speed = 0;
360
361 if (!prev_link && cur_link) {
362 printk(KERN_INFO "%s: link up\n", dev->name);
363 netif_carrier_on(dev);
364 } else if (prev_link && !cur_link) {
365 printk(KERN_INFO "%s: link down\n", dev->name); 368 printk(KERN_INFO "%s: link down\n", dev->name);
366 netif_carrier_off(dev);
367 } 369 }
370 return;
368 } 371 }
369}
370 372
373 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
374 return;
371 375
372static void mdio_thread(struct work_struct *work) 376 port->speed = phydev->speed;
373{ 377 port->duplex = phydev->duplex;
374 struct port *port = container_of(work, struct port, mdio_thread.work); 378
379 if (port->duplex)
380 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
381 &port->regs->tx_control[0]);
382 else
383 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
384 &port->regs->tx_control[0]);
375 385
376 phy_check_media(port, 0); 386 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
377 schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL); 387 dev->name, port->speed, port->duplex ? "full" : "half");
378} 388}
379 389
380 390
@@ -412,47 +422,13 @@ static inline void debug_desc(u32 phys, struct desc *desc)
412#endif 422#endif
413} 423}
414 424
415static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
416{
417#if DEBUG_QUEUES
418 static struct {
419 int queue;
420 char *name;
421 } names[] = {
422 { TX_QUEUE(0x10), "TX#0 " },
423 { TX_QUEUE(0x20), "TX#1 " },
424 { TX_QUEUE(0x00), "TX#2 " },
425 { RXFREE_QUEUE(0x10), "RX-free#0 " },
426 { RXFREE_QUEUE(0x20), "RX-free#1 " },
427 { RXFREE_QUEUE(0x00), "RX-free#2 " },
428 { TXDONE_QUEUE, "TX-done " },
429 };
430 int i;
431
432 for (i = 0; i < ARRAY_SIZE(names); i++)
433 if (names[i].queue == queue)
434 break;
435
436 printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
437 i < ARRAY_SIZE(names) ? names[i].name : "",
438 is_get ? "->" : "<-", phys);
439#endif
440}
441
442static inline u32 queue_get_entry(unsigned int queue)
443{
444 u32 phys = qmgr_get_entry(queue);
445 debug_queue(queue, 1, phys);
446 return phys;
447}
448
449static inline int queue_get_desc(unsigned int queue, struct port *port, 425static inline int queue_get_desc(unsigned int queue, struct port *port,
450 int is_tx) 426 int is_tx)
451{ 427{
452 u32 phys, tab_phys, n_desc; 428 u32 phys, tab_phys, n_desc;
453 struct desc *tab; 429 struct desc *tab;
454 430
455 if (!(phys = queue_get_entry(queue))) 431 if (!(phys = qmgr_get_entry(queue)))
456 return -1; 432 return -1;
457 433
458 phys &= ~0x1F; /* mask out non-address bits */ 434 phys &= ~0x1F; /* mask out non-address bits */
@@ -468,7 +444,6 @@ static inline int queue_get_desc(unsigned int queue, struct port *port,
468static inline void queue_put_desc(unsigned int queue, u32 phys, 444static inline void queue_put_desc(unsigned int queue, u32 phys,
469 struct desc *desc) 445 struct desc *desc)
470{ 446{
471 debug_queue(queue, 0, phys);
472 debug_desc(phys, desc); 447 debug_desc(phys, desc);
473 BUG_ON(phys & 0x1F); 448 BUG_ON(phys & 0x1F);
474 qmgr_put_entry(queue, phys); 449 qmgr_put_entry(queue, phys);
@@ -562,7 +537,7 @@ static int eth_poll(struct napi_struct *napi, int budget)
562#endif 537#endif
563 538
564 if (!skb) { 539 if (!skb) {
565 port->stat.rx_dropped++; 540 dev->stats.rx_dropped++;
566 /* put the desc back on RX-ready queue */ 541 /* put the desc back on RX-ready queue */
567 desc->buf_len = MAX_MRU; 542 desc->buf_len = MAX_MRU;
568 desc->pkt_len = 0; 543 desc->pkt_len = 0;
@@ -588,8 +563,8 @@ static int eth_poll(struct napi_struct *napi, int budget)
588 debug_pkt(dev, "eth_poll", skb->data, skb->len); 563 debug_pkt(dev, "eth_poll", skb->data, skb->len);
589 564
590 skb->protocol = eth_type_trans(skb, dev); 565 skb->protocol = eth_type_trans(skb, dev);
591 port->stat.rx_packets++; 566 dev->stats.rx_packets++;
592 port->stat.rx_bytes += skb->len; 567 dev->stats.rx_bytes += skb->len;
593 netif_receive_skb(skb); 568 netif_receive_skb(skb);
594 569
595 /* put the new buffer on RX-free queue */ 570 /* put the new buffer on RX-free queue */
@@ -617,7 +592,7 @@ static void eth_txdone_irq(void *unused)
617#if DEBUG_TX 592#if DEBUG_TX
618 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); 593 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
619#endif 594#endif
620 while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) { 595 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
621 u32 npe_id, n_desc; 596 u32 npe_id, n_desc;
622 struct port *port; 597 struct port *port;
623 struct desc *desc; 598 struct desc *desc;
@@ -634,8 +609,8 @@ static void eth_txdone_irq(void *unused)
634 debug_desc(phys, desc); 609 debug_desc(phys, desc);
635 610
636 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ 611 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
637 port->stat.tx_packets++; 612 port->netdev->stats.tx_packets++;
638 port->stat.tx_bytes += desc->pkt_len; 613 port->netdev->stats.tx_bytes += desc->pkt_len;
639 614
640 dma_unmap_tx(port, desc); 615 dma_unmap_tx(port, desc);
641#if DEBUG_TX 616#if DEBUG_TX
@@ -673,7 +648,7 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
673 648
674 if (unlikely(skb->len > MAX_MRU)) { 649 if (unlikely(skb->len > MAX_MRU)) {
675 dev_kfree_skb(skb); 650 dev_kfree_skb(skb);
676 port->stat.tx_errors++; 651 dev->stats.tx_errors++;
677 return NETDEV_TX_OK; 652 return NETDEV_TX_OK;
678 } 653 }
679 654
@@ -689,7 +664,7 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
689 bytes = ALIGN(offset + len, 4); 664 bytes = ALIGN(offset + len, 4);
690 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { 665 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
691 dev_kfree_skb(skb); 666 dev_kfree_skb(skb);
692 port->stat.tx_dropped++; 667 dev->stats.tx_dropped++;
693 return NETDEV_TX_OK; 668 return NETDEV_TX_OK;
694 } 669 }
695 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); 670 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
@@ -703,7 +678,7 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
703#else 678#else
704 kfree(mem); 679 kfree(mem);
705#endif 680#endif
706 port->stat.tx_dropped++; 681 dev->stats.tx_dropped++;
707 return NETDEV_TX_OK; 682 return NETDEV_TX_OK;
708 } 683 }
709 684
@@ -746,12 +721,6 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
746} 721}
747 722
748 723
749static struct net_device_stats *eth_stats(struct net_device *dev)
750{
751 struct port *port = netdev_priv(dev);
752 return &port->stat;
753}
754
755static void eth_set_mcast_list(struct net_device *dev) 724static void eth_set_mcast_list(struct net_device *dev)
756{ 725{
757 struct port *port = netdev_priv(dev); 726 struct port *port = netdev_priv(dev);
@@ -785,41 +754,80 @@ static void eth_set_mcast_list(struct net_device *dev)
785static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 754static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
786{ 755{
787 struct port *port = netdev_priv(dev); 756 struct port *port = netdev_priv(dev);
788 unsigned int duplex_chg;
789 int err;
790 757
791 if (!netif_running(dev)) 758 if (!netif_running(dev))
792 return -EINVAL; 759 return -EINVAL;
793 err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg); 760 return phy_mii_ioctl(port->phydev, if_mii(req), cmd);
794 if (duplex_chg) 761}
795 eth_set_duplex(port); 762
796 return err; 763/* ethtool support */
764
765static void ixp4xx_get_drvinfo(struct net_device *dev,
766 struct ethtool_drvinfo *info)
767{
768 struct port *port = netdev_priv(dev);
769 strcpy(info->driver, DRV_NAME);
770 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
771 port->firmware[0], port->firmware[1],
772 port->firmware[2], port->firmware[3]);
773 strcpy(info->bus_info, "internal");
797} 774}
798 775
776static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
777{
778 struct port *port = netdev_priv(dev);
779 return phy_ethtool_gset(port->phydev, cmd);
780}
781
782static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
783{
784 struct port *port = netdev_priv(dev);
785 return phy_ethtool_sset(port->phydev, cmd);
786}
787
788static int ixp4xx_nway_reset(struct net_device *dev)
789{
790 struct port *port = netdev_priv(dev);
791 return phy_start_aneg(port->phydev);
792}
793
794static struct ethtool_ops ixp4xx_ethtool_ops = {
795 .get_drvinfo = ixp4xx_get_drvinfo,
796 .get_settings = ixp4xx_get_settings,
797 .set_settings = ixp4xx_set_settings,
798 .nway_reset = ixp4xx_nway_reset,
799 .get_link = ethtool_op_get_link,
800};
801
799 802
800static int request_queues(struct port *port) 803static int request_queues(struct port *port)
801{ 804{
802 int err; 805 int err;
803 806
804 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0); 807 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
808 "%s:RX-free", port->netdev->name);
805 if (err) 809 if (err)
806 return err; 810 return err;
807 811
808 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0); 812 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
813 "%s:RX", port->netdev->name);
809 if (err) 814 if (err)
810 goto rel_rxfree; 815 goto rel_rxfree;
811 816
812 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0); 817 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
818 "%s:TX", port->netdev->name);
813 if (err) 819 if (err)
814 goto rel_rx; 820 goto rel_rx;
815 821
816 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0); 822 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
823 "%s:TX-ready", port->netdev->name);
817 if (err) 824 if (err)
818 goto rel_tx; 825 goto rel_tx;
819 826
820 /* TX-done queue handles skbs sent out by the NPEs */ 827 /* TX-done queue handles skbs sent out by the NPEs */
821 if (!ports_open) { 828 if (!ports_open) {
822 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0); 829 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
830 "%s:TX-done", DRV_NAME);
823 if (err) 831 if (err)
824 goto rel_txready; 832 goto rel_txready;
825 } 833 }
@@ -943,10 +951,12 @@ static int eth_open(struct net_device *dev)
943 npe_name(npe)); 951 npe_name(npe));
944 return -EIO; 952 return -EIO;
945 } 953 }
954 port->firmware[0] = msg.byte4;
955 port->firmware[1] = msg.byte5;
956 port->firmware[2] = msg.byte6;
957 port->firmware[3] = msg.byte7;
946 } 958 }
947 959
948 mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
949
950 memset(&msg, 0, sizeof(msg)); 960 memset(&msg, 0, sizeof(msg));
951 msg.cmd = NPE_VLAN_SETRXQOSENTRY; 961 msg.cmd = NPE_VLAN_SETRXQOSENTRY;
952 msg.eth_id = port->id; 962 msg.eth_id = port->id;
@@ -984,6 +994,9 @@ static int eth_open(struct net_device *dev)
984 return err; 994 return err;
985 } 995 }
986 996
997 port->speed = 0; /* force "link up" message */
998 phy_start(port->phydev);
999
987 for (i = 0; i < ETH_ALEN; i++) 1000 for (i = 0; i < ETH_ALEN; i++)
988 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); 1001 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
989 __raw_writel(0x08, &port->regs->random_seed); 1002 __raw_writel(0x08, &port->regs->random_seed);
@@ -1011,10 +1024,8 @@ static int eth_open(struct net_device *dev)
1011 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); 1024 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1012 1025
1013 napi_enable(&port->napi); 1026 napi_enable(&port->napi);
1014 phy_check_media(port, 1);
1015 eth_set_mcast_list(dev); 1027 eth_set_mcast_list(dev);
1016 netif_start_queue(dev); 1028 netif_start_queue(dev);
1017 schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
1018 1029
1019 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, 1030 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1020 eth_rx_irq, dev); 1031 eth_rx_irq, dev);
@@ -1105,25 +1116,31 @@ static int eth_close(struct net_device *dev)
1105 printk(KERN_CRIT "%s: unable to disable loopback\n", 1116 printk(KERN_CRIT "%s: unable to disable loopback\n",
1106 dev->name); 1117 dev->name);
1107 1118
1108 port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) & 1119 phy_stop(port->phydev);
1109 ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
1110 mdio_write(dev, port->plat->phy, MII_BMCR,
1111 port->mii_bmcr | BMCR_PDOWN);
1112 1120
1113 if (!ports_open) 1121 if (!ports_open)
1114 qmgr_disable_irq(TXDONE_QUEUE); 1122 qmgr_disable_irq(TXDONE_QUEUE);
1115 cancel_rearming_delayed_work(&port->mdio_thread);
1116 destroy_queues(port); 1123 destroy_queues(port);
1117 release_queues(port); 1124 release_queues(port);
1118 return 0; 1125 return 0;
1119} 1126}
1120 1127
1128static const struct net_device_ops ixp4xx_netdev_ops = {
1129 .ndo_open = eth_open,
1130 .ndo_stop = eth_close,
1131 .ndo_start_xmit = eth_xmit,
1132 .ndo_set_multicast_list = eth_set_mcast_list,
1133 .ndo_do_ioctl = eth_ioctl,
1134
1135};
1136
1121static int __devinit eth_init_one(struct platform_device *pdev) 1137static int __devinit eth_init_one(struct platform_device *pdev)
1122{ 1138{
1123 struct port *port; 1139 struct port *port;
1124 struct net_device *dev; 1140 struct net_device *dev;
1125 struct eth_plat_info *plat = pdev->dev.platform_data; 1141 struct eth_plat_info *plat = pdev->dev.platform_data;
1126 u32 regs_phys; 1142 u32 regs_phys;
1143 char phy_id[BUS_ID_SIZE];
1127 int err; 1144 int err;
1128 1145
1129 if (!(dev = alloc_etherdev(sizeof(struct port)))) 1146 if (!(dev = alloc_etherdev(sizeof(struct port))))
@@ -1152,12 +1169,8 @@ static int __devinit eth_init_one(struct platform_device *pdev)
1152 goto err_free; 1169 goto err_free;
1153 } 1170 }
1154 1171
1155 dev->open = eth_open; 1172 dev->netdev_ops = &ixp4xx_netdev_ops;
1156 dev->hard_start_xmit = eth_xmit; 1173 dev->ethtool_ops = &ixp4xx_ethtool_ops;
1157 dev->stop = eth_close;
1158 dev->get_stats = eth_stats;
1159 dev->do_ioctl = eth_ioctl;
1160 dev->set_multicast_list = eth_set_mcast_list;
1161 dev->tx_queue_len = 100; 1174 dev->tx_queue_len = 100;
1162 1175
1163 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT); 1176 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
@@ -1190,22 +1203,19 @@ static int __devinit eth_init_one(struct platform_device *pdev)
1190 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); 1203 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1191 udelay(50); 1204 udelay(50);
1192 1205
1193 port->mii.dev = dev; 1206 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, "0", plat->phy);
1194 port->mii.mdio_read = mdio_read; 1207 port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0,
1195 port->mii.mdio_write = mdio_write; 1208 PHY_INTERFACE_MODE_MII);
1196 port->mii.phy_id = plat->phy; 1209 if (IS_ERR(port->phydev)) {
1197 port->mii.phy_id_mask = 0x1F; 1210 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1198 port->mii.reg_num_mask = 0x1F; 1211 return PTR_ERR(port->phydev);
1212 }
1213
1214 port->phydev->irq = PHY_POLL;
1199 1215
1200 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy, 1216 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1201 npe_name(port->npe)); 1217 npe_name(port->npe));
1202 1218
1203 phy_reset(dev, plat->phy);
1204 port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
1205 ~(BMCR_RESET | BMCR_PDOWN);
1206 mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
1207
1208 INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
1209 return 0; 1219 return 0;
1210 1220
1211err_unreg: 1221err_unreg:
@@ -1231,7 +1241,7 @@ static int __devexit eth_remove_one(struct platform_device *pdev)
1231 return 0; 1241 return 0;
1232} 1242}
1233 1243
1234static struct platform_driver drv = { 1244static struct platform_driver ixp4xx_eth_driver = {
1235 .driver.name = DRV_NAME, 1245 .driver.name = DRV_NAME,
1236 .probe = eth_init_one, 1246 .probe = eth_init_one,
1237 .remove = eth_remove_one, 1247 .remove = eth_remove_one,
@@ -1239,20 +1249,19 @@ static struct platform_driver drv = {
1239 1249
1240static int __init eth_init_module(void) 1250static int __init eth_init_module(void)
1241{ 1251{
1252 int err;
1242 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) 1253 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
1243 return -ENOSYS; 1254 return -ENOSYS;
1244 1255
1245 /* All MII PHY accesses use NPE-B Ethernet registers */ 1256 if ((err = ixp4xx_mdio_register()))
1246 spin_lock_init(&mdio_lock); 1257 return err;
1247 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; 1258 return platform_driver_register(&ixp4xx_eth_driver);
1248 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
1249
1250 return platform_driver_register(&drv);
1251} 1259}
1252 1260
1253static void __exit eth_cleanup_module(void) 1261static void __exit eth_cleanup_module(void)
1254{ 1262{
1255 platform_driver_unregister(&drv); 1263 platform_driver_unregister(&ixp4xx_eth_driver);
1264 ixp4xx_mdio_remove();
1256} 1265}
1257 1266
1258MODULE_AUTHOR("Krzysztof Halasa"); 1267MODULE_AUTHOR("Krzysztof Halasa");
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index 0725161aa27c..d08ce6a264cb 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -335,6 +335,13 @@ config DSCC4_PCI_RST
335 335
336 Say Y if your card supports this feature. 336 Say Y if your card supports this feature.
337 337
338config IXP4XX_HSS
339 tristate "Intel IXP4xx HSS (synchronous serial port) support"
340 depends on HDLC && ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR
341 help
342 Say Y here if you want to use built-in HSS ports
343 on IXP4xx processor.
344
338config DLCI 345config DLCI
339 tristate "Frame Relay DLCI support" 346 tristate "Frame Relay DLCI support"
340 ---help--- 347 ---help---
diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
index cec16818a130..19d14bc28356 100644
--- a/drivers/net/wan/Makefile
+++ b/drivers/net/wan/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_C101) += c101.o
41obj-$(CONFIG_WANXL) += wanxl.o 41obj-$(CONFIG_WANXL) += wanxl.o
42obj-$(CONFIG_PCI200SYN) += pci200syn.o 42obj-$(CONFIG_PCI200SYN) += pci200syn.o
43obj-$(CONFIG_PC300TOO) += pc300too.o 43obj-$(CONFIG_PC300TOO) += pc300too.o
44obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
44 45
45clean-files := wanxlfw.inc 46clean-files := wanxlfw.inc
46$(obj)/wanxl.o: $(obj)/wanxlfw.inc 47$(obj)/wanxl.o: $(obj)/wanxlfw.inc
diff --git a/drivers/net/wan/hdlc_ppp.c b/drivers/net/wan/hdlc_ppp.c
index 72fae217f1c4..57fe714c1c7f 100644
--- a/drivers/net/wan/hdlc_ppp.c
+++ b/drivers/net/wan/hdlc_ppp.c
@@ -303,7 +303,7 @@ static int cp_table[EVENTS][STATES] = {
303 STA: RTR must supply id 303 STA: RTR must supply id
304 SCJ: RUC must supply CP packet len and data */ 304 SCJ: RUC must supply CP packet len and data */
305static void ppp_cp_event(struct net_device *dev, u16 pid, u16 event, u8 code, 305static void ppp_cp_event(struct net_device *dev, u16 pid, u16 event, u8 code,
306 u8 id, unsigned int len, void *data) 306 u8 id, unsigned int len, const void *data)
307{ 307{
308 int old_state, action; 308 int old_state, action;
309 struct ppp *ppp = get_ppp(dev); 309 struct ppp *ppp = get_ppp(dev);
@@ -374,11 +374,12 @@ static void ppp_cp_event(struct net_device *dev, u16 pid, u16 event, u8 code,
374 374
375 375
376static void ppp_cp_parse_cr(struct net_device *dev, u16 pid, u8 id, 376static void ppp_cp_parse_cr(struct net_device *dev, u16 pid, u8 id,
377 unsigned int len, u8 *data) 377 unsigned int req_len, const u8 *data)
378{ 378{
379 static u8 const valid_accm[6] = { LCP_OPTION_ACCM, 6, 0, 0, 0, 0 }; 379 static u8 const valid_accm[6] = { LCP_OPTION_ACCM, 6, 0, 0, 0, 0 };
380 u8 *opt, *out; 380 const u8 *opt;
381 unsigned int nak_len = 0, rej_len = 0; 381 u8 *out;
382 unsigned int len = req_len, nak_len = 0, rej_len = 0;
382 383
383 if (!(out = kmalloc(len, GFP_ATOMIC))) { 384 if (!(out = kmalloc(len, GFP_ATOMIC))) {
384 dev->stats.rx_dropped++; 385 dev->stats.rx_dropped++;
@@ -423,7 +424,7 @@ static void ppp_cp_parse_cr(struct net_device *dev, u16 pid, u8 id,
423 else if (nak_len) 424 else if (nak_len)
424 ppp_cp_event(dev, pid, RCR_BAD, CP_CONF_NAK, id, nak_len, out); 425 ppp_cp_event(dev, pid, RCR_BAD, CP_CONF_NAK, id, nak_len, out);
425 else 426 else
426 ppp_cp_event(dev, pid, RCR_GOOD, CP_CONF_ACK, id, len, data); 427 ppp_cp_event(dev, pid, RCR_GOOD, CP_CONF_ACK, id, req_len, data);
427 428
428 kfree(out); 429 kfree(out);
429} 430}
diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
new file mode 100644
index 000000000000..0c6802507a79
--- /dev/null
+++ b/drivers/net/wan/ixp4xx_hss.c
@@ -0,0 +1,1325 @@
1/*
2 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
3 *
4 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 */
10
11#include <linux/bitops.h>
12#include <linux/cdev.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmapool.h>
15#include <linux/fs.h>
16#include <linux/hdlc.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/poll.h>
21#include <mach/npe.h>
22#include <mach/qmgr.h>
23
24#define DEBUG_DESC 0
25#define DEBUG_RX 0
26#define DEBUG_TX 0
27#define DEBUG_PKT_BYTES 0
28#define DEBUG_CLOSE 0
29
30#define DRV_NAME "ixp4xx_hss"
31
32#define PKT_EXTRA_FLAGS 0 /* orig 1 */
33#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
34#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
35
36#define RX_DESCS 16 /* also length of all RX queues */
37#define TX_DESCS 16 /* also length of all TX queues */
38
39#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
40#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
41#define MAX_CLOSE_WAIT 1000 /* microseconds */
42#define HSS_COUNT 2
43#define FRAME_SIZE 256 /* doesn't matter at this point */
44#define FRAME_OFFSET 0
45#define MAX_CHANNELS (FRAME_SIZE / 8)
46
47#define NAPI_WEIGHT 16
48
49/* Queue IDs */
50#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
51#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
52#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
53#define HSS0_PKT_TX1_QUEUE 15
54#define HSS0_PKT_TX2_QUEUE 16
55#define HSS0_PKT_TX3_QUEUE 17
56#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
57#define HSS0_PKT_RXFREE1_QUEUE 19
58#define HSS0_PKT_RXFREE2_QUEUE 20
59#define HSS0_PKT_RXFREE3_QUEUE 21
60#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
61
62#define HSS1_CHL_RXTRIG_QUEUE 10
63#define HSS1_PKT_RX_QUEUE 0
64#define HSS1_PKT_TX0_QUEUE 5
65#define HSS1_PKT_TX1_QUEUE 6
66#define HSS1_PKT_TX2_QUEUE 7
67#define HSS1_PKT_TX3_QUEUE 8
68#define HSS1_PKT_RXFREE0_QUEUE 1
69#define HSS1_PKT_RXFREE1_QUEUE 2
70#define HSS1_PKT_RXFREE2_QUEUE 3
71#define HSS1_PKT_RXFREE3_QUEUE 4
72#define HSS1_PKT_TXDONE_QUEUE 9
73
74#define NPE_PKT_MODE_HDLC 0
75#define NPE_PKT_MODE_RAW 1
76#define NPE_PKT_MODE_56KMODE 2
77#define NPE_PKT_MODE_56KENDIAN_MSB 4
78
79/* PKT_PIPE_HDLC_CFG_WRITE flags */
80#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
81#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
82#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
83
84
85/* hss_config, PCRs */
86/* Frame sync sampling, default = active low */
87#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
88#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
89#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
90
91/* Frame sync pin: input (default) or output generated off a given clk edge */
92#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
93#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
94
95/* Frame and data clock sampling on edge, default = falling */
96#define PCR_FCLK_EDGE_RISING 0x08000000
97#define PCR_DCLK_EDGE_RISING 0x04000000
98
99/* Clock direction, default = input */
100#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
101
102/* Generate/Receive frame pulses, default = enabled */
103#define PCR_FRM_PULSE_DISABLED 0x01000000
104
105 /* Data rate is full (default) or half the configured clk speed */
106#define PCR_HALF_CLK_RATE 0x00200000
107
108/* Invert data between NPE and HSS FIFOs? (default = no) */
109#define PCR_DATA_POLARITY_INVERT 0x00100000
110
111/* TX/RX endianness, default = LSB */
112#define PCR_MSB_ENDIAN 0x00080000
113
114/* Normal (default) / open drain mode (TX only) */
115#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
116
117/* No framing bit transmitted and expected on RX? (default = framing bit) */
118#define PCR_SOF_NO_FBIT 0x00020000
119
120/* Drive data pins? */
121#define PCR_TX_DATA_ENABLE 0x00010000
122
123/* Voice 56k type: drive the data pins low (default), high, high Z */
124#define PCR_TX_V56K_HIGH 0x00002000
125#define PCR_TX_V56K_HIGH_IMP 0x00004000
126
127/* Unassigned type: drive the data pins low (default), high, high Z */
128#define PCR_TX_UNASS_HIGH 0x00000800
129#define PCR_TX_UNASS_HIGH_IMP 0x00001000
130
131/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
132#define PCR_TX_FB_HIGH_IMP 0x00000400
133
134/* 56k data endiannes - which bit unused: high (default) or low */
135#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
136
137/* 56k data transmission type: 32/8 bit data (default) or 56K data */
138#define PCR_TX_56KS_56K_DATA 0x00000100
139
140/* hss_config, cCR */
141/* Number of packetized clients, default = 1 */
142#define CCR_NPE_HFIFO_2_HDLC 0x04000000
143#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
144
145/* default = no loopback */
146#define CCR_LOOPBACK 0x02000000
147
148/* HSS number, default = 0 (first) */
149#define CCR_SECOND_HSS 0x01000000
150
151
152/* hss_config, clkCR: main:10, num:10, denom:12 */
153#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
154
155#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
156#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
157#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
158#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
159#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
160#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
161
162#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
163#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
164#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
165#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
166#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
167#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
168
169
170/* hss_config, LUT entries */
171#define TDMMAP_UNASSIGNED 0
172#define TDMMAP_HDLC 1 /* HDLC - packetized */
173#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
174#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
175
176/* offsets into HSS config */
177#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
178#define HSS_CONFIG_RX_PCR 0x04
179#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
180#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
181#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
182#define HSS_CONFIG_RX_FCR 0x14
183#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
184#define HSS_CONFIG_RX_LUT 0x38
185
186
187/* NPE command codes */
188/* writes the ConfigWord value to the location specified by offset */
189#define PORT_CONFIG_WRITE 0x40
190
191/* triggers the NPE to load the contents of the configuration table */
192#define PORT_CONFIG_LOAD 0x41
193
194/* triggers the NPE to return an HssErrorReadResponse message */
195#define PORT_ERROR_READ 0x42
196
197/* triggers the NPE to reset internal status and enable the HssPacketized
198 operation for the flow specified by pPipe */
199#define PKT_PIPE_FLOW_ENABLE 0x50
200#define PKT_PIPE_FLOW_DISABLE 0x51
201#define PKT_NUM_PIPES_WRITE 0x52
202#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
203#define PKT_PIPE_HDLC_CFG_WRITE 0x54
204#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
205#define PKT_PIPE_RX_SIZE_WRITE 0x56
206#define PKT_PIPE_MODE_WRITE 0x57
207
208/* HDLC packet status values - desc->status */
209#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
210#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
211#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
212#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
213 this packet (if buf_len < pkt_len) */
214#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
215#define ERR_HDLC_ABORT 6 /* abort sequence received */
216#define ERR_DISCONNECTING 7 /* disconnect is in progress */
217
218
219#ifdef __ARMEB__
220typedef struct sk_buff buffer_t;
221#define free_buffer dev_kfree_skb
222#define free_buffer_irq dev_kfree_skb_irq
223#else
224typedef void buffer_t;
225#define free_buffer kfree
226#define free_buffer_irq kfree
227#endif
228
229struct port {
230 struct device *dev;
231 struct npe *npe;
232 struct net_device *netdev;
233 struct napi_struct napi;
234 struct hss_plat_info *plat;
235 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
236 struct desc *desc_tab; /* coherent */
237 u32 desc_tab_phys;
238 unsigned int id;
239 unsigned int clock_type, clock_rate, loopback;
240 unsigned int initialized, carrier;
241 u8 hdlc_cfg;
242};
243
244/* NPE message structure */
245struct msg {
246#ifdef __ARMEB__
247 u8 cmd, unused, hss_port, index;
248 union {
249 struct { u8 data8a, data8b, data8c, data8d; };
250 struct { u16 data16a, data16b; };
251 struct { u32 data32; };
252 };
253#else
254 u8 index, hss_port, unused, cmd;
255 union {
256 struct { u8 data8d, data8c, data8b, data8a; };
257 struct { u16 data16b, data16a; };
258 struct { u32 data32; };
259 };
260#endif
261};
262
263/* HDLC packet descriptor */
264struct desc {
265 u32 next; /* pointer to next buffer, unused */
266
267#ifdef __ARMEB__
268 u16 buf_len; /* buffer length */
269 u16 pkt_len; /* packet length */
270 u32 data; /* pointer to data buffer in RAM */
271 u8 status;
272 u8 error_count;
273 u16 __reserved;
274#else
275 u16 pkt_len; /* packet length */
276 u16 buf_len; /* buffer length */
277 u32 data; /* pointer to data buffer in RAM */
278 u16 __reserved;
279 u8 error_count;
280 u8 status;
281#endif
282 u32 __reserved1[4];
283};
284
285
286#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
287 (n) * sizeof(struct desc))
288#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
289
290#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
291 ((n) + RX_DESCS) * sizeof(struct desc))
292#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
293
294/*****************************************************************************
295 * global variables
296 ****************************************************************************/
297
298static int ports_open;
299static struct dma_pool *dma_pool;
300static spinlock_t npe_lock;
301
302static const struct {
303 int tx, txdone, rx, rxfree;
304}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
305 HSS0_PKT_RXFREE0_QUEUE},
306 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
307 HSS1_PKT_RXFREE0_QUEUE},
308};
309
310/*****************************************************************************
311 * utility functions
312 ****************************************************************************/
313
314static inline struct port* dev_to_port(struct net_device *dev)
315{
316 return dev_to_hdlc(dev)->priv;
317}
318
319#ifndef __ARMEB__
320static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
321{
322 int i;
323 for (i = 0; i < cnt; i++)
324 dest[i] = swab32(src[i]);
325}
326#endif
327
328/*****************************************************************************
329 * HSS access
330 ****************************************************************************/
331
332static void hss_npe_send(struct port *port, struct msg *msg, const char* what)
333{
334 u32 *val = (u32*)msg;
335 if (npe_send_message(port->npe, msg, what)) {
336 printk(KERN_CRIT "HSS-%i: unable to send command [%08X:%08X]"
337 " to %s\n", port->id, val[0], val[1],
338 npe_name(port->npe));
339 BUG();
340 }
341}
342
343static void hss_config_set_lut(struct port *port)
344{
345 struct msg msg;
346 int ch;
347
348 memset(&msg, 0, sizeof(msg));
349 msg.cmd = PORT_CONFIG_WRITE;
350 msg.hss_port = port->id;
351
352 for (ch = 0; ch < MAX_CHANNELS; ch++) {
353 msg.data32 >>= 2;
354 msg.data32 |= TDMMAP_HDLC << 30;
355
356 if (ch % 16 == 15) {
357 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
358 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
359
360 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
361 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
362 }
363 }
364}
365
366static void hss_config(struct port *port)
367{
368 struct msg msg;
369
370 memset(&msg, 0, sizeof(msg));
371 msg.cmd = PORT_CONFIG_WRITE;
372 msg.hss_port = port->id;
373 msg.index = HSS_CONFIG_TX_PCR;
374 msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN |
375 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
376 if (port->clock_type == CLOCK_INT)
377 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
378 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
379
380 msg.index = HSS_CONFIG_RX_PCR;
381 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
382 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
383
384 memset(&msg, 0, sizeof(msg));
385 msg.cmd = PORT_CONFIG_WRITE;
386 msg.hss_port = port->id;
387 msg.index = HSS_CONFIG_CORE_CR;
388 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
389 (port->id ? CCR_SECOND_HSS : 0);
390 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
391
392 memset(&msg, 0, sizeof(msg));
393 msg.cmd = PORT_CONFIG_WRITE;
394 msg.hss_port = port->id;
395 msg.index = HSS_CONFIG_CLOCK_CR;
396 msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
397 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
398
399 memset(&msg, 0, sizeof(msg));
400 msg.cmd = PORT_CONFIG_WRITE;
401 msg.hss_port = port->id;
402 msg.index = HSS_CONFIG_TX_FCR;
403 msg.data16a = FRAME_OFFSET;
404 msg.data16b = FRAME_SIZE - 1;
405 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
406
407 memset(&msg, 0, sizeof(msg));
408 msg.cmd = PORT_CONFIG_WRITE;
409 msg.hss_port = port->id;
410 msg.index = HSS_CONFIG_RX_FCR;
411 msg.data16a = FRAME_OFFSET;
412 msg.data16b = FRAME_SIZE - 1;
413 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
414
415 hss_config_set_lut(port);
416
417 memset(&msg, 0, sizeof(msg));
418 msg.cmd = PORT_CONFIG_LOAD;
419 msg.hss_port = port->id;
420 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
421
422 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
423 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
424 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
425 printk(KERN_CRIT "HSS-%i: HSS_LOAD_CONFIG failed\n",
426 port->id);
427 BUG();
428 }
429
430 /* HDLC may stop working without this - check FIXME */
431 npe_recv_message(port->npe, &msg, "FLUSH_IT");
432}
433
434static void hss_set_hdlc_cfg(struct port *port)
435{
436 struct msg msg;
437
438 memset(&msg, 0, sizeof(msg));
439 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
440 msg.hss_port = port->id;
441 msg.data8a = port->hdlc_cfg; /* rx_cfg */
442 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
443 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
444}
445
446static u32 hss_get_status(struct port *port)
447{
448 struct msg msg;
449
450 memset(&msg, 0, sizeof(msg));
451 msg.cmd = PORT_ERROR_READ;
452 msg.hss_port = port->id;
453 hss_npe_send(port, &msg, "PORT_ERROR_READ");
454 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
455 printk(KERN_CRIT "HSS-%i: unable to read HSS status\n",
456 port->id);
457 BUG();
458 }
459
460 return msg.data32;
461}
462
463static void hss_start_hdlc(struct port *port)
464{
465 struct msg msg;
466
467 memset(&msg, 0, sizeof(msg));
468 msg.cmd = PKT_PIPE_FLOW_ENABLE;
469 msg.hss_port = port->id;
470 msg.data32 = 0;
471 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
472}
473
474static void hss_stop_hdlc(struct port *port)
475{
476 struct msg msg;
477
478 memset(&msg, 0, sizeof(msg));
479 msg.cmd = PKT_PIPE_FLOW_DISABLE;
480 msg.hss_port = port->id;
481 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
482 hss_get_status(port); /* make sure it's halted */
483}
484
485static int hss_load_firmware(struct port *port)
486{
487 struct msg msg;
488 int err;
489
490 if (port->initialized)
491 return 0;
492
493 if (!npe_running(port->npe) &&
494 (err = npe_load_firmware(port->npe, npe_name(port->npe),
495 port->dev)))
496 return err;
497
498 /* HDLC mode configuration */
499 memset(&msg, 0, sizeof(msg));
500 msg.cmd = PKT_NUM_PIPES_WRITE;
501 msg.hss_port = port->id;
502 msg.data8a = PKT_NUM_PIPES;
503 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
504
505 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
506 msg.data8a = PKT_PIPE_FIFO_SIZEW;
507 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
508
509 msg.cmd = PKT_PIPE_MODE_WRITE;
510 msg.data8a = NPE_PKT_MODE_HDLC;
511 /* msg.data8b = inv_mask */
512 /* msg.data8c = or_mask */
513 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
514
515 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
516 msg.data16a = HDLC_MAX_MRU; /* including CRC */
517 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
518
519 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
520 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
521 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
522
523 port->initialized = 1;
524 return 0;
525}
526
527/*****************************************************************************
528 * packetized (HDLC) operation
529 ****************************************************************************/
530
531static inline void debug_pkt(struct net_device *dev, const char *func,
532 u8 *data, int len)
533{
534#if DEBUG_PKT_BYTES
535 int i;
536
537 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
538 for (i = 0; i < len; i++) {
539 if (i >= DEBUG_PKT_BYTES)
540 break;
541 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
542 }
543 printk("\n");
544#endif
545}
546
547
548static inline void debug_desc(u32 phys, struct desc *desc)
549{
550#if DEBUG_DESC
551 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
552 phys, desc->next, desc->buf_len, desc->pkt_len,
553 desc->data, desc->status, desc->error_count);
554#endif
555}
556
557static inline int queue_get_desc(unsigned int queue, struct port *port,
558 int is_tx)
559{
560 u32 phys, tab_phys, n_desc;
561 struct desc *tab;
562
563 if (!(phys = qmgr_get_entry(queue)))
564 return -1;
565
566 BUG_ON(phys & 0x1F);
567 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
568 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
569 n_desc = (phys - tab_phys) / sizeof(struct desc);
570 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
571 debug_desc(phys, &tab[n_desc]);
572 BUG_ON(tab[n_desc].next);
573 return n_desc;
574}
575
576static inline void queue_put_desc(unsigned int queue, u32 phys,
577 struct desc *desc)
578{
579 debug_desc(phys, desc);
580 BUG_ON(phys & 0x1F);
581 qmgr_put_entry(queue, phys);
582 BUG_ON(qmgr_stat_overflow(queue));
583}
584
585
586static inline void dma_unmap_tx(struct port *port, struct desc *desc)
587{
588#ifdef __ARMEB__
589 dma_unmap_single(&port->netdev->dev, desc->data,
590 desc->buf_len, DMA_TO_DEVICE);
591#else
592 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
593 ALIGN((desc->data & 3) + desc->buf_len, 4),
594 DMA_TO_DEVICE);
595#endif
596}
597
598
599static void hss_hdlc_set_carrier(void *pdev, int carrier)
600{
601 struct net_device *netdev = pdev;
602 struct port *port = dev_to_port(netdev);
603 unsigned long flags;
604
605 spin_lock_irqsave(&npe_lock, flags);
606 port->carrier = carrier;
607 if (!port->loopback) {
608 if (carrier)
609 netif_carrier_on(netdev);
610 else
611 netif_carrier_off(netdev);
612 }
613 spin_unlock_irqrestore(&npe_lock, flags);
614}
615
616static void hss_hdlc_rx_irq(void *pdev)
617{
618 struct net_device *dev = pdev;
619 struct port *port = dev_to_port(dev);
620
621#if DEBUG_RX
622 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
623#endif
624 qmgr_disable_irq(queue_ids[port->id].rx);
625 netif_rx_schedule(dev, &port->napi);
626}
627
628static int hss_hdlc_poll(struct napi_struct *napi, int budget)
629{
630 struct port *port = container_of(napi, struct port, napi);
631 struct net_device *dev = port->netdev;
632 unsigned int rxq = queue_ids[port->id].rx;
633 unsigned int rxfreeq = queue_ids[port->id].rxfree;
634 int received = 0;
635
636#if DEBUG_RX
637 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
638#endif
639
640 while (received < budget) {
641 struct sk_buff *skb;
642 struct desc *desc;
643 int n;
644#ifdef __ARMEB__
645 struct sk_buff *temp;
646 u32 phys;
647#endif
648
649 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
650#if DEBUG_RX
651 printk(KERN_DEBUG "%s: hss_hdlc_poll"
652 " netif_rx_complete\n", dev->name);
653#endif
654 netif_rx_complete(dev, napi);
655 qmgr_enable_irq(rxq);
656 if (!qmgr_stat_empty(rxq) &&
657 netif_rx_reschedule(dev, napi)) {
658#if DEBUG_RX
659 printk(KERN_DEBUG "%s: hss_hdlc_poll"
660 " netif_rx_reschedule succeeded\n",
661 dev->name);
662#endif
663 qmgr_disable_irq(rxq);
664 continue;
665 }
666#if DEBUG_RX
667 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
668 dev->name);
669#endif
670 return received; /* all work done */
671 }
672
673 desc = rx_desc_ptr(port, n);
674#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
675 if (desc->error_count)
676 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
677 " errors %u\n", dev->name, desc->status,
678 desc->error_count);
679#endif
680 skb = NULL;
681 switch (desc->status) {
682 case 0:
683#ifdef __ARMEB__
684 if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
685 phys = dma_map_single(&dev->dev, skb->data,
686 RX_SIZE,
687 DMA_FROM_DEVICE);
688 if (dma_mapping_error(&dev->dev, phys)) {
689 dev_kfree_skb(skb);
690 skb = NULL;
691 }
692 }
693#else
694 skb = netdev_alloc_skb(dev, desc->pkt_len);
695#endif
696 if (!skb)
697 dev->stats.rx_dropped++;
698 break;
699 case ERR_HDLC_ALIGN:
700 case ERR_HDLC_ABORT:
701 dev->stats.rx_frame_errors++;
702 dev->stats.rx_errors++;
703 break;
704 case ERR_HDLC_FCS:
705 dev->stats.rx_crc_errors++;
706 dev->stats.rx_errors++;
707 break;
708 case ERR_HDLC_TOO_LONG:
709 dev->stats.rx_length_errors++;
710 dev->stats.rx_errors++;
711 break;
712 default: /* FIXME - remove printk */
713 printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
714 " errors %u\n", dev->name, desc->status,
715 desc->error_count);
716 dev->stats.rx_errors++;
717 }
718
719 if (!skb) {
720 /* put the desc back on RX-ready queue */
721 desc->buf_len = RX_SIZE;
722 desc->pkt_len = desc->status = 0;
723 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
724 continue;
725 }
726
727 /* process received frame */
728#ifdef __ARMEB__
729 temp = skb;
730 skb = port->rx_buff_tab[n];
731 dma_unmap_single(&dev->dev, desc->data,
732 RX_SIZE, DMA_FROM_DEVICE);
733#else
734 dma_sync_single(&dev->dev, desc->data,
735 RX_SIZE, DMA_FROM_DEVICE);
736 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
737 ALIGN(desc->pkt_len, 4) / 4);
738#endif
739 skb_put(skb, desc->pkt_len);
740
741 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
742
743 skb->protocol = hdlc_type_trans(skb, dev);
744 dev->stats.rx_packets++;
745 dev->stats.rx_bytes += skb->len;
746 netif_receive_skb(skb);
747
748 /* put the new buffer on RX-free queue */
749#ifdef __ARMEB__
750 port->rx_buff_tab[n] = temp;
751 desc->data = phys;
752#endif
753 desc->buf_len = RX_SIZE;
754 desc->pkt_len = 0;
755 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
756 received++;
757 }
758#if DEBUG_RX
759 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
760#endif
761 return received; /* not all work done */
762}
763
764
765static void hss_hdlc_txdone_irq(void *pdev)
766{
767 struct net_device *dev = pdev;
768 struct port *port = dev_to_port(dev);
769 int n_desc;
770
771#if DEBUG_TX
772 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
773#endif
774 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
775 port, 1)) >= 0) {
776 struct desc *desc;
777 int start;
778
779 desc = tx_desc_ptr(port, n_desc);
780
781 dev->stats.tx_packets++;
782 dev->stats.tx_bytes += desc->pkt_len;
783
784 dma_unmap_tx(port, desc);
785#if DEBUG_TX
786 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
787 dev->name, port->tx_buff_tab[n_desc]);
788#endif
789 free_buffer_irq(port->tx_buff_tab[n_desc]);
790 port->tx_buff_tab[n_desc] = NULL;
791
792 start = qmgr_stat_empty(port->plat->txreadyq);
793 queue_put_desc(port->plat->txreadyq,
794 tx_desc_phys(port, n_desc), desc);
795 if (start) {
796#if DEBUG_TX
797 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
798 " ready\n", dev->name);
799#endif
800 netif_wake_queue(dev);
801 }
802 }
803}
804
805static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
806{
807 struct port *port = dev_to_port(dev);
808 unsigned int txreadyq = port->plat->txreadyq;
809 int len, offset, bytes, n;
810 void *mem;
811 u32 phys;
812 struct desc *desc;
813
814#if DEBUG_TX
815 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
816#endif
817
818 if (unlikely(skb->len > HDLC_MAX_MRU)) {
819 dev_kfree_skb(skb);
820 dev->stats.tx_errors++;
821 return NETDEV_TX_OK;
822 }
823
824 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
825
826 len = skb->len;
827#ifdef __ARMEB__
828 offset = 0; /* no need to keep alignment */
829 bytes = len;
830 mem = skb->data;
831#else
832 offset = (int)skb->data & 3; /* keep 32-bit alignment */
833 bytes = ALIGN(offset + len, 4);
834 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
835 dev_kfree_skb(skb);
836 dev->stats.tx_dropped++;
837 return NETDEV_TX_OK;
838 }
839 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
840 dev_kfree_skb(skb);
841#endif
842
843 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
844 if (dma_mapping_error(&dev->dev, phys)) {
845#ifdef __ARMEB__
846 dev_kfree_skb(skb);
847#else
848 kfree(mem);
849#endif
850 dev->stats.tx_dropped++;
851 return NETDEV_TX_OK;
852 }
853
854 n = queue_get_desc(txreadyq, port, 1);
855 BUG_ON(n < 0);
856 desc = tx_desc_ptr(port, n);
857
858#ifdef __ARMEB__
859 port->tx_buff_tab[n] = skb;
860#else
861 port->tx_buff_tab[n] = mem;
862#endif
863 desc->data = phys + offset;
864 desc->buf_len = desc->pkt_len = len;
865
866 wmb();
867 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
868 dev->trans_start = jiffies;
869
870 if (qmgr_stat_empty(txreadyq)) {
871#if DEBUG_TX
872 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
873#endif
874 netif_stop_queue(dev);
875 /* we could miss TX ready interrupt */
876 if (!qmgr_stat_empty(txreadyq)) {
877#if DEBUG_TX
878 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
879 dev->name);
880#endif
881 netif_wake_queue(dev);
882 }
883 }
884
885#if DEBUG_TX
886 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
887#endif
888 return NETDEV_TX_OK;
889}
890
891
892static int request_hdlc_queues(struct port *port)
893{
894 int err;
895
896 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
897 "%s:RX-free", port->netdev->name);
898 if (err)
899 return err;
900
901 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
902 "%s:RX", port->netdev->name);
903 if (err)
904 goto rel_rxfree;
905
906 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
907 "%s:TX", port->netdev->name);
908 if (err)
909 goto rel_rx;
910
911 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
912 "%s:TX-ready", port->netdev->name);
913 if (err)
914 goto rel_tx;
915
916 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
917 "%s:TX-done", port->netdev->name);
918 if (err)
919 goto rel_txready;
920 return 0;
921
922rel_txready:
923 qmgr_release_queue(port->plat->txreadyq);
924rel_tx:
925 qmgr_release_queue(queue_ids[port->id].tx);
926rel_rx:
927 qmgr_release_queue(queue_ids[port->id].rx);
928rel_rxfree:
929 qmgr_release_queue(queue_ids[port->id].rxfree);
930 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
931 port->netdev->name);
932 return err;
933}
934
935static void release_hdlc_queues(struct port *port)
936{
937 qmgr_release_queue(queue_ids[port->id].rxfree);
938 qmgr_release_queue(queue_ids[port->id].rx);
939 qmgr_release_queue(queue_ids[port->id].txdone);
940 qmgr_release_queue(queue_ids[port->id].tx);
941 qmgr_release_queue(port->plat->txreadyq);
942}
943
944static int init_hdlc_queues(struct port *port)
945{
946 int i;
947
948 if (!ports_open)
949 if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
950 POOL_ALLOC_SIZE, 32, 0)))
951 return -ENOMEM;
952
953 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
954 &port->desc_tab_phys)))
955 return -ENOMEM;
956 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
957 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
958 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
959
960 /* Setup RX buffers */
961 for (i = 0; i < RX_DESCS; i++) {
962 struct desc *desc = rx_desc_ptr(port, i);
963 buffer_t *buff;
964 void *data;
965#ifdef __ARMEB__
966 if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
967 return -ENOMEM;
968 data = buff->data;
969#else
970 if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
971 return -ENOMEM;
972 data = buff;
973#endif
974 desc->buf_len = RX_SIZE;
975 desc->data = dma_map_single(&port->netdev->dev, data,
976 RX_SIZE, DMA_FROM_DEVICE);
977 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
978 free_buffer(buff);
979 return -EIO;
980 }
981 port->rx_buff_tab[i] = buff;
982 }
983
984 return 0;
985}
986
987static void destroy_hdlc_queues(struct port *port)
988{
989 int i;
990
991 if (port->desc_tab) {
992 for (i = 0; i < RX_DESCS; i++) {
993 struct desc *desc = rx_desc_ptr(port, i);
994 buffer_t *buff = port->rx_buff_tab[i];
995 if (buff) {
996 dma_unmap_single(&port->netdev->dev,
997 desc->data, RX_SIZE,
998 DMA_FROM_DEVICE);
999 free_buffer(buff);
1000 }
1001 }
1002 for (i = 0; i < TX_DESCS; i++) {
1003 struct desc *desc = tx_desc_ptr(port, i);
1004 buffer_t *buff = port->tx_buff_tab[i];
1005 if (buff) {
1006 dma_unmap_tx(port, desc);
1007 free_buffer(buff);
1008 }
1009 }
1010 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1011 port->desc_tab = NULL;
1012 }
1013
1014 if (!ports_open && dma_pool) {
1015 dma_pool_destroy(dma_pool);
1016 dma_pool = NULL;
1017 }
1018}
1019
1020static int hss_hdlc_open(struct net_device *dev)
1021{
1022 struct port *port = dev_to_port(dev);
1023 unsigned long flags;
1024 int i, err = 0;
1025
1026 if ((err = hdlc_open(dev)))
1027 return err;
1028
1029 if ((err = hss_load_firmware(port)))
1030 goto err_hdlc_close;
1031
1032 if ((err = request_hdlc_queues(port)))
1033 goto err_hdlc_close;
1034
1035 if ((err = init_hdlc_queues(port)))
1036 goto err_destroy_queues;
1037
1038 spin_lock_irqsave(&npe_lock, flags);
1039 if (port->plat->open)
1040 if ((err = port->plat->open(port->id, dev,
1041 hss_hdlc_set_carrier)))
1042 goto err_unlock;
1043 spin_unlock_irqrestore(&npe_lock, flags);
1044
1045 /* Populate queues with buffers, no failure after this point */
1046 for (i = 0; i < TX_DESCS; i++)
1047 queue_put_desc(port->plat->txreadyq,
1048 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1049
1050 for (i = 0; i < RX_DESCS; i++)
1051 queue_put_desc(queue_ids[port->id].rxfree,
1052 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1053
1054 napi_enable(&port->napi);
1055 netif_start_queue(dev);
1056
1057 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1058 hss_hdlc_rx_irq, dev);
1059
1060 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1061 hss_hdlc_txdone_irq, dev);
1062 qmgr_enable_irq(queue_ids[port->id].txdone);
1063
1064 ports_open++;
1065
1066 hss_set_hdlc_cfg(port);
1067 hss_config(port);
1068
1069 hss_start_hdlc(port);
1070
1071 /* we may already have RX data, enables IRQ */
1072 netif_rx_schedule(dev, &port->napi);
1073 return 0;
1074
1075err_unlock:
1076 spin_unlock_irqrestore(&npe_lock, flags);
1077err_destroy_queues:
1078 destroy_hdlc_queues(port);
1079 release_hdlc_queues(port);
1080err_hdlc_close:
1081 hdlc_close(dev);
1082 return err;
1083}
1084
1085static int hss_hdlc_close(struct net_device *dev)
1086{
1087 struct port *port = dev_to_port(dev);
1088 unsigned long flags;
1089 int i, buffs = RX_DESCS; /* allocated RX buffers */
1090
1091 spin_lock_irqsave(&npe_lock, flags);
1092 ports_open--;
1093 qmgr_disable_irq(queue_ids[port->id].rx);
1094 netif_stop_queue(dev);
1095 napi_disable(&port->napi);
1096
1097 hss_stop_hdlc(port);
1098
1099 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1100 buffs--;
1101 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1102 buffs--;
1103
1104 if (buffs)
1105 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1106 " left in NPE\n", dev->name, buffs);
1107
1108 buffs = TX_DESCS;
1109 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1110 buffs--; /* cancel TX */
1111
1112 i = 0;
1113 do {
1114 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1115 buffs--;
1116 if (!buffs)
1117 break;
1118 } while (++i < MAX_CLOSE_WAIT);
1119
1120 if (buffs)
1121 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1122 "left in NPE\n", dev->name, buffs);
1123#if DEBUG_CLOSE
1124 if (!buffs)
1125 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1126#endif
1127 qmgr_disable_irq(queue_ids[port->id].txdone);
1128
1129 if (port->plat->close)
1130 port->plat->close(port->id, dev);
1131 spin_unlock_irqrestore(&npe_lock, flags);
1132
1133 destroy_hdlc_queues(port);
1134 release_hdlc_queues(port);
1135 hdlc_close(dev);
1136 return 0;
1137}
1138
1139
1140static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1141 unsigned short parity)
1142{
1143 struct port *port = dev_to_port(dev);
1144
1145 if (encoding != ENCODING_NRZ)
1146 return -EINVAL;
1147
1148 switch(parity) {
1149 case PARITY_CRC16_PR1_CCITT:
1150 port->hdlc_cfg = 0;
1151 return 0;
1152
1153 case PARITY_CRC32_PR1_CCITT:
1154 port->hdlc_cfg = PKT_HDLC_CRC_32;
1155 return 0;
1156
1157 default:
1158 return -EINVAL;
1159 }
1160}
1161
1162
1163static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1164{
1165 const size_t size = sizeof(sync_serial_settings);
1166 sync_serial_settings new_line;
1167 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1168 struct port *port = dev_to_port(dev);
1169 unsigned long flags;
1170 int clk;
1171
1172 if (cmd != SIOCWANDEV)
1173 return hdlc_ioctl(dev, ifr, cmd);
1174
1175 switch(ifr->ifr_settings.type) {
1176 case IF_GET_IFACE:
1177 ifr->ifr_settings.type = IF_IFACE_V35;
1178 if (ifr->ifr_settings.size < size) {
1179 ifr->ifr_settings.size = size; /* data size wanted */
1180 return -ENOBUFS;
1181 }
1182 memset(&new_line, 0, sizeof(new_line));
1183 new_line.clock_type = port->clock_type;
1184 new_line.clock_rate = 2048000; /* FIXME */
1185 new_line.loopback = port->loopback;
1186 if (copy_to_user(line, &new_line, size))
1187 return -EFAULT;
1188 return 0;
1189
1190 case IF_IFACE_SYNC_SERIAL:
1191 case IF_IFACE_V35:
1192 if(!capable(CAP_NET_ADMIN))
1193 return -EPERM;
1194 if (copy_from_user(&new_line, line, size))
1195 return -EFAULT;
1196
1197 clk = new_line.clock_type;
1198 if (port->plat->set_clock)
1199 clk = port->plat->set_clock(port->id, clk);
1200
1201 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1202 return -EINVAL; /* No such clock setting */
1203
1204 if (new_line.loopback != 0 && new_line.loopback != 1)
1205 return -EINVAL;
1206
1207 port->clock_type = clk; /* Update settings */
1208 /* FIXME port->clock_rate = new_line.clock_rate */;
1209 port->loopback = new_line.loopback;
1210
1211 spin_lock_irqsave(&npe_lock, flags);
1212
1213 if (dev->flags & IFF_UP)
1214 hss_config(port);
1215
1216 if (port->loopback || port->carrier)
1217 netif_carrier_on(port->netdev);
1218 else
1219 netif_carrier_off(port->netdev);
1220 spin_unlock_irqrestore(&npe_lock, flags);
1221
1222 return 0;
1223
1224 default:
1225 return hdlc_ioctl(dev, ifr, cmd);
1226 }
1227}
1228
1229/*****************************************************************************
1230 * initialization
1231 ****************************************************************************/
1232
1233static int __devinit hss_init_one(struct platform_device *pdev)
1234{
1235 struct port *port;
1236 struct net_device *dev;
1237 hdlc_device *hdlc;
1238 int err;
1239
1240 if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
1241 return -ENOMEM;
1242
1243 if ((port->npe = npe_request(0)) == NULL) {
1244 err = -ENOSYS;
1245 goto err_free;
1246 }
1247
1248 if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
1249 err = -ENOMEM;
1250 goto err_plat;
1251 }
1252
1253 SET_NETDEV_DEV(dev, &pdev->dev);
1254 hdlc = dev_to_hdlc(dev);
1255 hdlc->attach = hss_hdlc_attach;
1256 hdlc->xmit = hss_hdlc_xmit;
1257 dev->open = hss_hdlc_open;
1258 dev->stop = hss_hdlc_close;
1259 dev->do_ioctl = hss_hdlc_ioctl;
1260 dev->tx_queue_len = 100;
1261 port->clock_type = CLOCK_EXT;
1262 port->clock_rate = 2048000;
1263 port->id = pdev->id;
1264 port->dev = &pdev->dev;
1265 port->plat = pdev->dev.platform_data;
1266 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1267
1268 if ((err = register_hdlc_device(dev)))
1269 goto err_free_netdev;
1270
1271 platform_set_drvdata(pdev, port);
1272
1273 printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
1274 return 0;
1275
1276err_free_netdev:
1277 free_netdev(dev);
1278err_plat:
1279 npe_release(port->npe);
1280err_free:
1281 kfree(port);
1282 return err;
1283}
1284
1285static int __devexit hss_remove_one(struct platform_device *pdev)
1286{
1287 struct port *port = platform_get_drvdata(pdev);
1288
1289 unregister_hdlc_device(port->netdev);
1290 free_netdev(port->netdev);
1291 npe_release(port->npe);
1292 platform_set_drvdata(pdev, NULL);
1293 kfree(port);
1294 return 0;
1295}
1296
1297static struct platform_driver ixp4xx_hss_driver = {
1298 .driver.name = DRV_NAME,
1299 .probe = hss_init_one,
1300 .remove = hss_remove_one,
1301};
1302
1303static int __init hss_init_module(void)
1304{
1305 if ((ixp4xx_read_feature_bits() &
1306 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1307 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
1308 return -ENOSYS;
1309
1310 spin_lock_init(&npe_lock);
1311
1312 return platform_driver_register(&ixp4xx_hss_driver);
1313}
1314
1315static void __exit hss_cleanup_module(void)
1316{
1317 platform_driver_unregister(&ixp4xx_hss_driver);
1318}
1319
1320MODULE_AUTHOR("Krzysztof Halasa");
1321MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1322MODULE_LICENSE("GPL v2");
1323MODULE_ALIAS("platform:ixp4xx_hss");
1324module_init(hss_init_module);
1325module_exit(hss_cleanup_module);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 08:08:17 -0500