diff options
-rw-r--r-- | arch/ppc/Kconfig | 46 | ||||
-rw-r--r-- | arch/ppc/Makefile | 1 | ||||
-rw-r--r-- | arch/ppc/configs/mpc834x_sys_defconfig | 844 | ||||
-rw-r--r-- | arch/ppc/kernel/ppc_ksyms.c | 3 | ||||
-rw-r--r-- | arch/ppc/kernel/setup.c | 2 | ||||
-rw-r--r-- | arch/ppc/mm/mmu_context.c | 2 | ||||
-rw-r--r-- | arch/ppc/mm/ppc_mmu.c | 2 | ||||
-rw-r--r-- | arch/ppc/platforms/83xx/Makefile | 4 | ||||
-rw-r--r-- | arch/ppc/platforms/83xx/mpc834x_sys.c | 346 | ||||
-rw-r--r-- | arch/ppc/platforms/83xx/mpc834x_sys.h | 54 | ||||
-rw-r--r-- | arch/ppc/syslib/Makefile | 5 | ||||
-rw-r--r-- | arch/ppc/syslib/ipic.c | 646 | ||||
-rw-r--r-- | arch/ppc/syslib/ipic.h | 47 | ||||
-rw-r--r-- | arch/ppc/syslib/mpc83xx_devices.c | 251 | ||||
-rw-r--r-- | arch/ppc/syslib/mpc83xx_sys.c | 122 | ||||
-rw-r--r-- | arch/ppc/syslib/ppc83xx_pci.h | 151 | ||||
-rw-r--r-- | arch/ppc/syslib/ppc83xx_setup.c | 410 | ||||
-rw-r--r-- | arch/ppc/syslib/ppc83xx_setup.h | 55 | ||||
-rw-r--r-- | include/asm-powerpc/irq.h | 5 | ||||
-rw-r--r-- | include/asm-ppc/mpc83xx.h | 107 | ||||
-rw-r--r-- | include/asm-ppc/ppc_sys.h | 2 | ||||
-rw-r--r-- | include/asm-ppc/ppcboot.h | 5 | ||||
-rw-r--r-- | include/asm-ppc/serial.h | 2 |
23 files changed, 15 insertions, 3097 deletions
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index 6473fa7cb4b9..08e083d30dc6 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig | |||
@@ -78,18 +78,18 @@ choice | |||
78 | default 6xx | 78 | default 6xx |
79 | 79 | ||
80 | config 6xx | 80 | config 6xx |
81 | bool "6xx/7xx/74xx/52xx/82xx/83xx" | 81 | bool "6xx/7xx/74xx/52xx/82xx" |
82 | select PPC_FPU | 82 | select PPC_FPU |
83 | help | 83 | help |
84 | There are four types of PowerPC chips supported. The more common | 84 | There are four types of PowerPC chips supported. The more common |
85 | types (601, 603, 604, 740, 750, 7400), the older Freescale | 85 | types (601, 603, 604, 740, 750, 7400), the older Freescale |
86 | (formerly Motorola) embedded versions (821, 823, 850, 855, 860, | 86 | (formerly Motorola) embedded versions (821, 823, 850, 855, 860, |
87 | 52xx, 82xx, 83xx), the IBM embedded versions (403 and 405) and | 87 | 52xx, 82xx), the IBM embedded versions (403 and 405) and |
88 | the Book E embedded processors from IBM (44x) and Freescale (85xx). | 88 | the Book E embedded processors from IBM (44x) and Freescale (85xx). |
89 | For support for 64-bit processors, set ARCH=powerpc. | 89 | For support for 64-bit processors, set ARCH=powerpc. |
90 | Unless you are building a kernel for one of the embedded processor | 90 | Unless you are building a kernel for one of the embedded processor |
91 | systems, choose 6xx. | 91 | systems, choose 6xx. |
92 | Also note that because the 52xx, 82xx, & 83xx family have a 603e | 92 | Also note that because the 52xx, 82xx family have a 603e |
93 | core, specific support for that chipset is asked later on. | 93 | core, specific support for that chipset is asked later on. |
94 | 94 | ||
95 | config 40x | 95 | config 40x |
@@ -153,7 +153,7 @@ config PHYS_64BIT | |||
153 | config ALTIVEC | 153 | config ALTIVEC |
154 | bool "AltiVec Support" | 154 | bool "AltiVec Support" |
155 | depends on 6xx | 155 | depends on 6xx |
156 | depends on !8260 && !83xx | 156 | depends on !8260 |
157 | ---help--- | 157 | ---help--- |
158 | This option enables kernel support for the Altivec extensions to the | 158 | This option enables kernel support for the Altivec extensions to the |
159 | PowerPC processor. The kernel currently supports saving and restoring | 159 | PowerPC processor. The kernel currently supports saving and restoring |
@@ -184,7 +184,7 @@ config SPE | |||
184 | 184 | ||
185 | config TAU | 185 | config TAU |
186 | bool "Thermal Management Support" | 186 | bool "Thermal Management Support" |
187 | depends on 6xx && !8260 && !83xx | 187 | depends on 6xx && !8260 |
188 | help | 188 | help |
189 | G3 and G4 processors have an on-chip temperature sensor called the | 189 | G3 and G4 processors have an on-chip temperature sensor called the |
190 | 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die | 190 | 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die |
@@ -721,16 +721,6 @@ config LITE5200B | |||
721 | Support for the LITE5200B dev board for the MPC5200 from Freescale. | 721 | Support for the LITE5200B dev board for the MPC5200 from Freescale. |
722 | This is the new board with 2 PCI slots. | 722 | This is the new board with 2 PCI slots. |
723 | 723 | ||
724 | config MPC834x_SYS | ||
725 | bool "Freescale MPC834x SYS" | ||
726 | help | ||
727 | This option enables support for the MPC 834x SYS evaluation board. | ||
728 | |||
729 | Be aware that PCI buses can only function when SYS board is plugged | ||
730 | into the PIB (Platform IO Board) board from Freescale which provide | ||
731 | 3 PCI slots. The PIBs PCI initialization is the bootloader's | ||
732 | responsibility. | ||
733 | |||
734 | config EV64360 | 724 | config EV64360 |
735 | bool "Marvell-EV64360BP" | 725 | bool "Marvell-EV64360BP" |
736 | help | 726 | help |
@@ -774,18 +764,6 @@ config 8272 | |||
774 | The MPC8272 CPM has a different internal dpram setup than other CPM2 | 764 | The MPC8272 CPM has a different internal dpram setup than other CPM2 |
775 | devices | 765 | devices |
776 | 766 | ||
777 | config 83xx | ||
778 | bool | ||
779 | default y if MPC834x_SYS | ||
780 | |||
781 | config MPC834x | ||
782 | bool | ||
783 | default y if MPC834x_SYS | ||
784 | |||
785 | config PPC_83xx | ||
786 | bool | ||
787 | default y if 83xx | ||
788 | |||
789 | config CPM1 | 767 | config CPM1 |
790 | bool | 768 | bool |
791 | depends on 8xx | 769 | depends on 8xx |
@@ -811,8 +789,7 @@ config PPC_GEN550 | |||
811 | bool | 789 | bool |
812 | depends on SANDPOINT || SPRUCE || PPLUS || \ | 790 | depends on SANDPOINT || SPRUCE || PPLUS || \ |
813 | PRPMC750 || PRPMC800 || LOPEC || \ | 791 | PRPMC750 || PRPMC800 || LOPEC || \ |
814 | (EV64260 && !SERIAL_MPSC) || CHESTNUT || RADSTONE_PPC7D || \ | 792 | (EV64260 && !SERIAL_MPSC) || CHESTNUT || RADSTONE_PPC7D |
815 | 83xx | ||
816 | default y | 793 | default y |
817 | 794 | ||
818 | config FORCE | 795 | config FORCE |
@@ -1074,7 +1051,7 @@ config PPC_I8259 | |||
1074 | config PPC_INDIRECT_PCI | 1051 | config PPC_INDIRECT_PCI |
1075 | bool | 1052 | bool |
1076 | depends on PCI | 1053 | depends on PCI |
1077 | default y if 40x || 44x || 85xx || 83xx || PPC_PREP | 1054 | default y if 40x || 44x || 85xx || PPC_PREP |
1078 | default n | 1055 | default n |
1079 | 1056 | ||
1080 | config EISA | 1057 | config EISA |
@@ -1091,8 +1068,8 @@ config MCA | |||
1091 | bool | 1068 | bool |
1092 | 1069 | ||
1093 | config PCI | 1070 | config PCI |
1094 | bool "PCI support" if 40x || CPM2 || 83xx || 85xx || PPC_MPC52xx | 1071 | bool "PCI support" if 40x || CPM2 || 85xx || PPC_MPC52xx |
1095 | default y if !40x && !CPM2 && !8xx && !83xx && !85xx | 1072 | default y if !40x && !CPM2 && !8xx && !85xx |
1096 | default PCI_QSPAN if !4xx && !CPM2 && 8xx | 1073 | default PCI_QSPAN if !4xx && !CPM2 && 8xx |
1097 | help | 1074 | help |
1098 | Find out whether your system includes a PCI bus. PCI is the name of | 1075 | Find out whether your system includes a PCI bus. PCI is the name of |
@@ -1106,11 +1083,6 @@ config PCI_DOMAINS | |||
1106 | config PCI_SYSCALL | 1083 | config PCI_SYSCALL |
1107 | def_bool PCI | 1084 | def_bool PCI |
1108 | 1085 | ||
1109 | config MPC83xx_PCI2 | ||
1110 | bool "Support for 2nd PCI host controller" | ||
1111 | depends on PCI && MPC834x | ||
1112 | default y if MPC834x_SYS | ||
1113 | |||
1114 | config PCI_QSPAN | 1086 | config PCI_QSPAN |
1115 | bool "QSpan PCI" | 1087 | bool "QSpan PCI" |
1116 | depends on !4xx && !CPM2 && 8xx | 1088 | depends on !4xx && !CPM2 && 8xx |
diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile index 95894ef7beaa..a4fef18075ff 100644 --- a/arch/ppc/Makefile +++ b/arch/ppc/Makefile | |||
@@ -65,7 +65,6 @@ core-y += arch/ppc/kernel/ arch/powerpc/kernel/ \ | |||
65 | arch/ppc/syslib/ arch/powerpc/sysdev/ \ | 65 | arch/ppc/syslib/ arch/powerpc/sysdev/ \ |
66 | arch/powerpc/lib/ | 66 | arch/powerpc/lib/ |
67 | core-$(CONFIG_4xx) += arch/ppc/platforms/4xx/ | 67 | core-$(CONFIG_4xx) += arch/ppc/platforms/4xx/ |
68 | core-$(CONFIG_83xx) += arch/ppc/platforms/83xx/ | ||
69 | core-$(CONFIG_85xx) += arch/ppc/platforms/85xx/ | 68 | core-$(CONFIG_85xx) += arch/ppc/platforms/85xx/ |
70 | core-$(CONFIG_MATH_EMULATION) += arch/powerpc/math-emu/ | 69 | core-$(CONFIG_MATH_EMULATION) += arch/powerpc/math-emu/ |
71 | core-$(CONFIG_XMON) += arch/ppc/xmon/ | 70 | core-$(CONFIG_XMON) += arch/ppc/xmon/ |
diff --git a/arch/ppc/configs/mpc834x_sys_defconfig b/arch/ppc/configs/mpc834x_sys_defconfig deleted file mode 100644 index d90c8a7e060c..000000000000 --- a/arch/ppc/configs/mpc834x_sys_defconfig +++ /dev/null | |||
@@ -1,844 +0,0 @@ | |||
1 | # | ||
2 | # Automatically generated make config: don't edit | ||
3 | # Linux kernel version: 2.6.14 | ||
4 | # Mon Nov 7 15:38:29 2005 | ||
5 | # | ||
6 | CONFIG_MMU=y | ||
7 | CONFIG_GENERIC_HARDIRQS=y | ||
8 | CONFIG_RWSEM_XCHGADD_ALGORITHM=y | ||
9 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
10 | CONFIG_PPC=y | ||
11 | CONFIG_PPC32=y | ||
12 | CONFIG_GENERIC_NVRAM=y | ||
13 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y | ||
14 | CONFIG_ARCH_MAY_HAVE_PC_FDC=y | ||
15 | |||
16 | # | ||
17 | # Code maturity level options | ||
18 | # | ||
19 | CONFIG_EXPERIMENTAL=y | ||
20 | CONFIG_CLEAN_COMPILE=y | ||
21 | CONFIG_BROKEN_ON_SMP=y | ||
22 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
23 | |||
24 | # | ||
25 | # General setup | ||
26 | # | ||
27 | CONFIG_LOCALVERSION="" | ||
28 | CONFIG_LOCALVERSION_AUTO=y | ||
29 | CONFIG_SWAP=y | ||
30 | CONFIG_SYSVIPC=y | ||
31 | # CONFIG_POSIX_MQUEUE is not set | ||
32 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
33 | CONFIG_SYSCTL=y | ||
34 | # CONFIG_AUDIT is not set | ||
35 | # CONFIG_HOTPLUG is not set | ||
36 | CONFIG_KOBJECT_UEVENT=y | ||
37 | # CONFIG_IKCONFIG is not set | ||
38 | CONFIG_INITRAMFS_SOURCE="" | ||
39 | CONFIG_EMBEDDED=y | ||
40 | # CONFIG_KALLSYMS is not set | ||
41 | CONFIG_PRINTK=y | ||
42 | CONFIG_BUG=y | ||
43 | CONFIG_BASE_FULL=y | ||
44 | CONFIG_FUTEX=y | ||
45 | # CONFIG_EPOLL is not set | ||
46 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
47 | CONFIG_SHMEM=y | ||
48 | CONFIG_CC_ALIGN_FUNCTIONS=0 | ||
49 | CONFIG_CC_ALIGN_LABELS=0 | ||
50 | CONFIG_CC_ALIGN_LOOPS=0 | ||
51 | CONFIG_CC_ALIGN_JUMPS=0 | ||
52 | # CONFIG_TINY_SHMEM is not set | ||
53 | CONFIG_BASE_SMALL=0 | ||
54 | |||
55 | # | ||
56 | # Loadable module support | ||
57 | # | ||
58 | # CONFIG_MODULES is not set | ||
59 | |||
60 | # | ||
61 | # Processor | ||
62 | # | ||
63 | CONFIG_6xx=y | ||
64 | # CONFIG_40x is not set | ||
65 | # CONFIG_44x is not set | ||
66 | # CONFIG_POWER3 is not set | ||
67 | # CONFIG_POWER4 is not set | ||
68 | # CONFIG_8xx is not set | ||
69 | # CONFIG_E200 is not set | ||
70 | # CONFIG_E500 is not set | ||
71 | CONFIG_PPC_FPU=y | ||
72 | # CONFIG_KEXEC is not set | ||
73 | # CONFIG_CPU_FREQ is not set | ||
74 | # CONFIG_WANT_EARLY_SERIAL is not set | ||
75 | CONFIG_PPC_GEN550=y | ||
76 | CONFIG_PPC_STD_MMU=y | ||
77 | |||
78 | # | ||
79 | # Platform options | ||
80 | # | ||
81 | # CONFIG_PPC_MULTIPLATFORM is not set | ||
82 | # CONFIG_APUS is not set | ||
83 | # CONFIG_KATANA is not set | ||
84 | # CONFIG_WILLOW is not set | ||
85 | # CONFIG_CPCI690 is not set | ||
86 | # CONFIG_POWERPMC250 is not set | ||
87 | # CONFIG_CHESTNUT is not set | ||
88 | # CONFIG_SPRUCE is not set | ||
89 | # CONFIG_HDPU is not set | ||
90 | # CONFIG_EV64260 is not set | ||
91 | # CONFIG_LOPEC is not set | ||
92 | # CONFIG_MVME5100 is not set | ||
93 | # CONFIG_PPLUS is not set | ||
94 | # CONFIG_PRPMC750 is not set | ||
95 | # CONFIG_PRPMC800 is not set | ||
96 | # CONFIG_SANDPOINT is not set | ||
97 | # CONFIG_RADSTONE_PPC7D is not set | ||
98 | # CONFIG_PAL4 is not set | ||
99 | # CONFIG_GEMINI is not set | ||
100 | # CONFIG_EST8260 is not set | ||
101 | # CONFIG_SBC82xx is not set | ||
102 | # CONFIG_SBS8260 is not set | ||
103 | # CONFIG_RPX8260 is not set | ||
104 | # CONFIG_TQM8260 is not set | ||
105 | # CONFIG_ADS8272 is not set | ||
106 | # CONFIG_PQ2FADS is not set | ||
107 | # CONFIG_LITE5200 is not set | ||
108 | CONFIG_MPC834x_SYS=y | ||
109 | # CONFIG_EV64360 is not set | ||
110 | CONFIG_83xx=y | ||
111 | CONFIG_MPC834x=y | ||
112 | # CONFIG_SMP is not set | ||
113 | # CONFIG_HIGHMEM is not set | ||
114 | # CONFIG_HZ_100 is not set | ||
115 | CONFIG_HZ_250=y | ||
116 | # CONFIG_HZ_1000 is not set | ||
117 | CONFIG_HZ=250 | ||
118 | CONFIG_PREEMPT_NONE=y | ||
119 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
120 | # CONFIG_PREEMPT is not set | ||
121 | CONFIG_SELECT_MEMORY_MODEL=y | ||
122 | CONFIG_FLATMEM_MANUAL=y | ||
123 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
124 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
125 | CONFIG_FLATMEM=y | ||
126 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
127 | # CONFIG_SPARSEMEM_STATIC is not set | ||
128 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
129 | CONFIG_BINFMT_ELF=y | ||
130 | # CONFIG_BINFMT_MISC is not set | ||
131 | # CONFIG_CMDLINE_BOOL is not set | ||
132 | # CONFIG_PM is not set | ||
133 | # CONFIG_HIBERNATION is not set | ||
134 | CONFIG_SECCOMP=y | ||
135 | CONFIG_ISA_DMA_API=y | ||
136 | |||
137 | # | ||
138 | # Bus options | ||
139 | # | ||
140 | CONFIG_GENERIC_ISA_DMA=y | ||
141 | # CONFIG_PPC_I8259 is not set | ||
142 | CONFIG_PPC_INDIRECT_PCI=y | ||
143 | CONFIG_PCI=y | ||
144 | CONFIG_PCI_DOMAINS=y | ||
145 | # CONFIG_MPC83xx_PCI2 is not set | ||
146 | CONFIG_PCI_LEGACY_PROC=y | ||
147 | |||
148 | # | ||
149 | # PCCARD (PCMCIA/CardBus) support | ||
150 | # | ||
151 | # CONFIG_PCCARD is not set | ||
152 | |||
153 | # | ||
154 | # Advanced setup | ||
155 | # | ||
156 | # CONFIG_ADVANCED_OPTIONS is not set | ||
157 | |||
158 | # | ||
159 | # Default settings for advanced configuration options are used | ||
160 | # | ||
161 | CONFIG_HIGHMEM_START=0xfe000000 | ||
162 | CONFIG_LOWMEM_SIZE=0x30000000 | ||
163 | CONFIG_KERNEL_START=0xc0000000 | ||
164 | CONFIG_TASK_SIZE=0x80000000 | ||
165 | CONFIG_BOOT_LOAD=0x00800000 | ||
166 | |||
167 | # | ||
168 | # Networking | ||
169 | # | ||
170 | CONFIG_NET=y | ||
171 | |||
172 | # | ||
173 | # Networking options | ||
174 | # | ||
175 | CONFIG_PACKET=y | ||
176 | # CONFIG_PACKET_MMAP is not set | ||
177 | CONFIG_UNIX=y | ||
178 | # CONFIG_NET_KEY is not set | ||
179 | CONFIG_INET=y | ||
180 | CONFIG_IP_MULTICAST=y | ||
181 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
182 | CONFIG_IP_FIB_HASH=y | ||
183 | CONFIG_IP_PNP=y | ||
184 | CONFIG_IP_PNP_DHCP=y | ||
185 | CONFIG_IP_PNP_BOOTP=y | ||
186 | # CONFIG_IP_PNP_RARP is not set | ||
187 | # CONFIG_NET_IPIP is not set | ||
188 | # CONFIG_NET_IPGRE is not set | ||
189 | # CONFIG_IP_MROUTE is not set | ||
190 | # CONFIG_ARPD is not set | ||
191 | CONFIG_SYN_COOKIES=y | ||
192 | # CONFIG_INET_AH is not set | ||
193 | # CONFIG_INET_ESP is not set | ||
194 | # CONFIG_INET_IPCOMP is not set | ||
195 | # CONFIG_INET_TUNNEL is not set | ||
196 | CONFIG_INET_DIAG=y | ||
197 | CONFIG_INET_TCP_DIAG=y | ||
198 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
199 | CONFIG_TCP_CONG_BIC=y | ||
200 | # CONFIG_IPV6 is not set | ||
201 | # CONFIG_NETFILTER is not set | ||
202 | |||
203 | # | ||
204 | # DCCP Configuration (EXPERIMENTAL) | ||
205 | # | ||
206 | # CONFIG_IP_DCCP is not set | ||
207 | |||
208 | # | ||
209 | # SCTP Configuration (EXPERIMENTAL) | ||
210 | # | ||
211 | # CONFIG_IP_SCTP is not set | ||
212 | # CONFIG_ATM is not set | ||
213 | # CONFIG_BRIDGE is not set | ||
214 | # CONFIG_VLAN_8021Q is not set | ||
215 | # CONFIG_DECNET is not set | ||
216 | # CONFIG_LLC2 is not set | ||
217 | # CONFIG_IPX is not set | ||
218 | # CONFIG_ATALK is not set | ||
219 | # CONFIG_X25 is not set | ||
220 | # CONFIG_LAPB is not set | ||
221 | # CONFIG_NET_DIVERT is not set | ||
222 | # CONFIG_ECONET is not set | ||
223 | # CONFIG_WAN_ROUTER is not set | ||
224 | # CONFIG_NET_SCHED is not set | ||
225 | # CONFIG_NET_CLS_ROUTE is not set | ||
226 | |||
227 | # | ||
228 | # Network testing | ||
229 | # | ||
230 | # CONFIG_NET_PKTGEN is not set | ||
231 | # CONFIG_HAMRADIO is not set | ||
232 | # CONFIG_IRDA is not set | ||
233 | # CONFIG_BT is not set | ||
234 | # CONFIG_IEEE80211 is not set | ||
235 | |||
236 | # | ||
237 | # Device Drivers | ||
238 | # | ||
239 | |||
240 | # | ||
241 | # Generic Driver Options | ||
242 | # | ||
243 | CONFIG_STANDALONE=y | ||
244 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
245 | # CONFIG_FW_LOADER is not set | ||
246 | |||
247 | # | ||
248 | # Connector - unified userspace <-> kernelspace linker | ||
249 | # | ||
250 | # CONFIG_CONNECTOR is not set | ||
251 | |||
252 | # | ||
253 | # Memory Technology Devices (MTD) | ||
254 | # | ||
255 | # CONFIG_MTD is not set | ||
256 | |||
257 | # | ||
258 | # Parallel port support | ||
259 | # | ||
260 | # CONFIG_PARPORT is not set | ||
261 | |||
262 | # | ||
263 | # Plug and Play support | ||
264 | # | ||
265 | |||
266 | # | ||
267 | # Block devices | ||
268 | # | ||
269 | # CONFIG_BLK_DEV_FD is not set | ||
270 | # CONFIG_BLK_CPQ_DA is not set | ||
271 | # CONFIG_BLK_CPQ_CISS_DA is not set | ||
272 | # CONFIG_BLK_DEV_DAC960 is not set | ||
273 | # CONFIG_BLK_DEV_UMEM is not set | ||
274 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
275 | CONFIG_BLK_DEV_LOOP=y | ||
276 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
277 | # CONFIG_BLK_DEV_NBD is not set | ||
278 | # CONFIG_BLK_DEV_SX8 is not set | ||
279 | CONFIG_BLK_DEV_RAM=y | ||
280 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
281 | CONFIG_BLK_DEV_RAM_SIZE=32768 | ||
282 | CONFIG_BLK_DEV_INITRD=y | ||
283 | # CONFIG_LBD is not set | ||
284 | # CONFIG_CDROM_PKTCDVD is not set | ||
285 | |||
286 | # | ||
287 | # IO Schedulers | ||
288 | # | ||
289 | CONFIG_IOSCHED_NOOP=y | ||
290 | CONFIG_IOSCHED_AS=y | ||
291 | CONFIG_IOSCHED_DEADLINE=y | ||
292 | CONFIG_IOSCHED_CFQ=y | ||
293 | CONFIG_DEFAULT_AS=y | ||
294 | # CONFIG_DEFAULT_DEADLINE is not set | ||
295 | # CONFIG_DEFAULT_CFQ is not set | ||
296 | # CONFIG_DEFAULT_NOOP is not set | ||
297 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
298 | # CONFIG_ATA_OVER_ETH is not set | ||
299 | |||
300 | # | ||
301 | # ATA/ATAPI/MFM/RLL support | ||
302 | # | ||
303 | # CONFIG_IDE is not set | ||
304 | |||
305 | # | ||
306 | # SCSI device support | ||
307 | # | ||
308 | # CONFIG_RAID_ATTRS is not set | ||
309 | # CONFIG_SCSI is not set | ||
310 | |||
311 | # | ||
312 | # Multi-device support (RAID and LVM) | ||
313 | # | ||
314 | # CONFIG_MD is not set | ||
315 | |||
316 | # | ||
317 | # Fusion MPT device support | ||
318 | # | ||
319 | # CONFIG_FUSION is not set | ||
320 | |||
321 | # | ||
322 | # IEEE 1394 (FireWire) support | ||
323 | # | ||
324 | # CONFIG_IEEE1394 is not set | ||
325 | |||
326 | # | ||
327 | # I2O device support | ||
328 | # | ||
329 | # CONFIG_I2O is not set | ||
330 | |||
331 | # | ||
332 | # Macintosh device drivers | ||
333 | # | ||
334 | |||
335 | # | ||
336 | # Network device support | ||
337 | # | ||
338 | CONFIG_NETDEVICES=y | ||
339 | # CONFIG_DUMMY is not set | ||
340 | # CONFIG_BONDING is not set | ||
341 | # CONFIG_EQUALIZER is not set | ||
342 | # CONFIG_TUN is not set | ||
343 | |||
344 | # | ||
345 | # ARCnet devices | ||
346 | # | ||
347 | # CONFIG_ARCNET is not set | ||
348 | |||
349 | # | ||
350 | # PHY device support | ||
351 | # | ||
352 | CONFIG_PHYLIB=y | ||
353 | |||
354 | # | ||
355 | # MII PHY device drivers | ||
356 | # | ||
357 | CONFIG_MARVELL_PHY=y | ||
358 | # CONFIG_DAVICOM_PHY is not set | ||
359 | # CONFIG_QSEMI_PHY is not set | ||
360 | # CONFIG_LXT_PHY is not set | ||
361 | # CONFIG_CICADA_PHY is not set | ||
362 | |||
363 | # | ||
364 | # Ethernet (10 or 100Mbit) | ||
365 | # | ||
366 | CONFIG_NET_ETHERNET=y | ||
367 | CONFIG_MII=y | ||
368 | # CONFIG_HAPPYMEAL is not set | ||
369 | # CONFIG_SUNGEM is not set | ||
370 | # CONFIG_CASSINI is not set | ||
371 | # CONFIG_NET_VENDOR_3COM is not set | ||
372 | |||
373 | # | ||
374 | # Tulip family network device support | ||
375 | # | ||
376 | # CONFIG_NET_TULIP is not set | ||
377 | # CONFIG_HP100 is not set | ||
378 | CONFIG_NET_PCI=y | ||
379 | # CONFIG_PCNET32 is not set | ||
380 | # CONFIG_AMD8111_ETH is not set | ||
381 | # CONFIG_ADAPTEC_STARFIRE is not set | ||
382 | # CONFIG_B44 is not set | ||
383 | # CONFIG_FORCEDETH is not set | ||
384 | # CONFIG_DGRS is not set | ||
385 | # CONFIG_EEPRO100 is not set | ||
386 | CONFIG_E100=y | ||
387 | # CONFIG_FEALNX is not set | ||
388 | # CONFIG_NATSEMI is not set | ||
389 | # CONFIG_NE2K_PCI is not set | ||
390 | # CONFIG_8139CP is not set | ||
391 | # CONFIG_8139TOO is not set | ||
392 | # CONFIG_SIS900 is not set | ||
393 | # CONFIG_EPIC100 is not set | ||
394 | # CONFIG_SUNDANCE is not set | ||
395 | # CONFIG_TLAN is not set | ||
396 | # CONFIG_VIA_RHINE is not set | ||
397 | |||
398 | # | ||
399 | # Ethernet (1000 Mbit) | ||
400 | # | ||
401 | # CONFIG_ACENIC is not set | ||
402 | # CONFIG_DL2K is not set | ||
403 | CONFIG_E1000=y | ||
404 | # CONFIG_E1000_NAPI is not set | ||
405 | # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set | ||
406 | # CONFIG_NS83820 is not set | ||
407 | # CONFIG_HAMACHI is not set | ||
408 | # CONFIG_YELLOWFIN is not set | ||
409 | # CONFIG_R8169 is not set | ||
410 | # CONFIG_SIS190 is not set | ||
411 | # CONFIG_SKGE is not set | ||
412 | # CONFIG_SK98LIN is not set | ||
413 | # CONFIG_VIA_VELOCITY is not set | ||
414 | # CONFIG_TIGON3 is not set | ||
415 | # CONFIG_BNX2 is not set | ||
416 | CONFIG_GIANFAR=y | ||
417 | # CONFIG_GFAR_NAPI is not set | ||
418 | |||
419 | # | ||
420 | # Ethernet (10000 Mbit) | ||
421 | # | ||
422 | # CONFIG_CHELSIO_T1 is not set | ||
423 | # CONFIG_IXGB is not set | ||
424 | # CONFIG_S2IO is not set | ||
425 | |||
426 | # | ||
427 | # Token Ring devices | ||
428 | # | ||
429 | # CONFIG_TR is not set | ||
430 | |||
431 | # | ||
432 | # Wireless LAN (non-hamradio) | ||
433 | # | ||
434 | # CONFIG_NET_RADIO is not set | ||
435 | |||
436 | # | ||
437 | # Wan interfaces | ||
438 | # | ||
439 | # CONFIG_WAN is not set | ||
440 | # CONFIG_FDDI is not set | ||
441 | # CONFIG_HIPPI is not set | ||
442 | # CONFIG_PPP is not set | ||
443 | # CONFIG_SLIP is not set | ||
444 | # CONFIG_SHAPER is not set | ||
445 | # CONFIG_NETCONSOLE is not set | ||
446 | # CONFIG_NETPOLL is not set | ||
447 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
448 | |||
449 | # | ||
450 | # ISDN subsystem | ||
451 | # | ||
452 | # CONFIG_ISDN is not set | ||
453 | |||
454 | # | ||
455 | # Telephony Support | ||
456 | # | ||
457 | # CONFIG_PHONE is not set | ||
458 | |||
459 | # | ||
460 | # Input device support | ||
461 | # | ||
462 | CONFIG_INPUT=y | ||
463 | |||
464 | # | ||
465 | # Userland interfaces | ||
466 | # | ||
467 | # CONFIG_INPUT_MOUSEDEV is not set | ||
468 | # CONFIG_INPUT_JOYDEV is not set | ||
469 | # CONFIG_INPUT_TSDEV is not set | ||
470 | # CONFIG_INPUT_EVDEV is not set | ||
471 | # CONFIG_INPUT_EVBUG is not set | ||
472 | |||
473 | # | ||
474 | # Input Device Drivers | ||
475 | # | ||
476 | # CONFIG_INPUT_KEYBOARD is not set | ||
477 | # CONFIG_INPUT_MOUSE is not set | ||
478 | # CONFIG_INPUT_JOYSTICK is not set | ||
479 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
480 | # CONFIG_INPUT_MISC is not set | ||
481 | |||
482 | # | ||
483 | # Hardware I/O ports | ||
484 | # | ||
485 | # CONFIG_SERIO is not set | ||
486 | # CONFIG_GAMEPORT is not set | ||
487 | |||
488 | # | ||
489 | # Character devices | ||
490 | # | ||
491 | # CONFIG_VT is not set | ||
492 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
493 | |||
494 | # | ||
495 | # Serial drivers | ||
496 | # | ||
497 | CONFIG_SERIAL_8250=y | ||
498 | CONFIG_SERIAL_8250_CONSOLE=y | ||
499 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
500 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
501 | |||
502 | # | ||
503 | # Non-8250 serial port support | ||
504 | # | ||
505 | CONFIG_SERIAL_CORE=y | ||
506 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
507 | # CONFIG_SERIAL_JSM is not set | ||
508 | CONFIG_UNIX98_PTYS=y | ||
509 | CONFIG_LEGACY_PTYS=y | ||
510 | CONFIG_LEGACY_PTY_COUNT=256 | ||
511 | |||
512 | # | ||
513 | # IPMI | ||
514 | # | ||
515 | # CONFIG_IPMI_HANDLER is not set | ||
516 | |||
517 | # | ||
518 | # Watchdog Cards | ||
519 | # | ||
520 | # CONFIG_WATCHDOG is not set | ||
521 | # CONFIG_NVRAM is not set | ||
522 | CONFIG_GEN_RTC=y | ||
523 | # CONFIG_GEN_RTC_X is not set | ||
524 | # CONFIG_DTLK is not set | ||
525 | # CONFIG_R3964 is not set | ||
526 | # CONFIG_APPLICOM is not set | ||
527 | |||
528 | # | ||
529 | # Ftape, the floppy tape device driver | ||
530 | # | ||
531 | # CONFIG_AGP is not set | ||
532 | # CONFIG_DRM is not set | ||
533 | # CONFIG_RAW_DRIVER is not set | ||
534 | |||
535 | # | ||
536 | # TPM devices | ||
537 | # | ||
538 | # CONFIG_TCG_TPM is not set | ||
539 | # CONFIG_TELCLOCK is not set | ||
540 | |||
541 | # | ||
542 | # I2C support | ||
543 | # | ||
544 | CONFIG_I2C=y | ||
545 | CONFIG_I2C_CHARDEV=y | ||
546 | |||
547 | # | ||
548 | # I2C Algorithms | ||
549 | # | ||
550 | # CONFIG_I2C_ALGOBIT is not set | ||
551 | # CONFIG_I2C_ALGOPCF is not set | ||
552 | # CONFIG_I2C_ALGOPCA is not set | ||
553 | |||
554 | # | ||
555 | # I2C Hardware Bus support | ||
556 | # | ||
557 | # CONFIG_I2C_ALI1535 is not set | ||
558 | # CONFIG_I2C_ALI1563 is not set | ||
559 | # CONFIG_I2C_ALI15X3 is not set | ||
560 | # CONFIG_I2C_AMD756 is not set | ||
561 | # CONFIG_I2C_AMD8111 is not set | ||
562 | # CONFIG_I2C_I801 is not set | ||
563 | # CONFIG_I2C_I810 is not set | ||
564 | # CONFIG_I2C_PIIX4 is not set | ||
565 | CONFIG_I2C_MPC=y | ||
566 | # CONFIG_I2C_NFORCE2 is not set | ||
567 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
568 | # CONFIG_I2C_PROSAVAGE is not set | ||
569 | # CONFIG_I2C_SAVAGE4 is not set | ||
570 | # CONFIG_SCx200_ACB is not set | ||
571 | # CONFIG_I2C_SIS5595 is not set | ||
572 | # CONFIG_I2C_SIS630 is not set | ||
573 | # CONFIG_I2C_SIS96X is not set | ||
574 | # CONFIG_I2C_VIA is not set | ||
575 | # CONFIG_I2C_VIAPRO is not set | ||
576 | # CONFIG_I2C_VOODOO3 is not set | ||
577 | # CONFIG_I2C_PCA_ISA is not set | ||
578 | |||
579 | # | ||
580 | # Miscellaneous I2C Chip support | ||
581 | # | ||
582 | # CONFIG_SENSORS_DS1337 is not set | ||
583 | # CONFIG_SENSORS_DS1374 is not set | ||
584 | # CONFIG_SENSORS_EEPROM is not set | ||
585 | # CONFIG_SENSORS_PCF8574 is not set | ||
586 | # CONFIG_SENSORS_PCA9539 is not set | ||
587 | # CONFIG_SENSORS_PCF8591 is not set | ||
588 | # CONFIG_SENSORS_RTC8564 is not set | ||
589 | # CONFIG_SENSORS_M41T00 is not set | ||
590 | # CONFIG_SENSORS_MAX6875 is not set | ||
591 | # CONFIG_RTC_X1205_I2C is not set | ||
592 | # CONFIG_I2C_DEBUG_CORE is not set | ||
593 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
594 | # CONFIG_I2C_DEBUG_BUS is not set | ||
595 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
596 | |||
597 | # | ||
598 | # Dallas's 1-wire bus | ||
599 | # | ||
600 | # CONFIG_W1 is not set | ||
601 | |||
602 | # | ||
603 | # Hardware Monitoring support | ||
604 | # | ||
605 | CONFIG_HWMON=y | ||
606 | # CONFIG_HWMON_VID is not set | ||
607 | # CONFIG_SENSORS_ADM1021 is not set | ||
608 | # CONFIG_SENSORS_ADM1025 is not set | ||
609 | # CONFIG_SENSORS_ADM1026 is not set | ||
610 | # CONFIG_SENSORS_ADM1031 is not set | ||
611 | # CONFIG_SENSORS_ADM9240 is not set | ||
612 | # CONFIG_SENSORS_ASB100 is not set | ||
613 | # CONFIG_SENSORS_ATXP1 is not set | ||
614 | # CONFIG_SENSORS_DS1621 is not set | ||
615 | # CONFIG_SENSORS_FSCHER is not set | ||
616 | # CONFIG_SENSORS_FSCPOS is not set | ||
617 | # CONFIG_SENSORS_GL518SM is not set | ||
618 | # CONFIG_SENSORS_GL520SM is not set | ||
619 | # CONFIG_SENSORS_IT87 is not set | ||
620 | # CONFIG_SENSORS_LM63 is not set | ||
621 | # CONFIG_SENSORS_LM75 is not set | ||
622 | # CONFIG_SENSORS_LM77 is not set | ||
623 | # CONFIG_SENSORS_LM78 is not set | ||
624 | # CONFIG_SENSORS_LM80 is not set | ||
625 | # CONFIG_SENSORS_LM83 is not set | ||
626 | # CONFIG_SENSORS_LM85 is not set | ||
627 | # CONFIG_SENSORS_LM87 is not set | ||
628 | # CONFIG_SENSORS_LM90 is not set | ||
629 | # CONFIG_SENSORS_LM92 is not set | ||
630 | # CONFIG_SENSORS_MAX1619 is not set | ||
631 | # CONFIG_SENSORS_PC87360 is not set | ||
632 | # CONFIG_SENSORS_SIS5595 is not set | ||
633 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
634 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
635 | # CONFIG_SENSORS_VIA686A is not set | ||
636 | # CONFIG_SENSORS_W83781D is not set | ||
637 | # CONFIG_SENSORS_W83792D is not set | ||
638 | # CONFIG_SENSORS_W83L785TS is not set | ||
639 | # CONFIG_SENSORS_W83627HF is not set | ||
640 | # CONFIG_SENSORS_W83627EHF is not set | ||
641 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
642 | |||
643 | # | ||
644 | # Misc devices | ||
645 | # | ||
646 | |||
647 | # | ||
648 | # Multimedia Capabilities Port drivers | ||
649 | # | ||
650 | |||
651 | # | ||
652 | # Multimedia devices | ||
653 | # | ||
654 | # CONFIG_VIDEO_DEV is not set | ||
655 | |||
656 | # | ||
657 | # Digital Video Broadcasting Devices | ||
658 | # | ||
659 | # CONFIG_DVB is not set | ||
660 | |||
661 | # | ||
662 | # Graphics support | ||
663 | # | ||
664 | # CONFIG_FB is not set | ||
665 | |||
666 | # | ||
667 | # Sound | ||
668 | # | ||
669 | # CONFIG_SOUND is not set | ||
670 | |||
671 | # | ||
672 | # USB support | ||
673 | # | ||
674 | CONFIG_USB_ARCH_HAS_HCD=y | ||
675 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
676 | # CONFIG_USB is not set | ||
677 | |||
678 | # | ||
679 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
680 | # | ||
681 | |||
682 | # | ||
683 | # USB Gadget Support | ||
684 | # | ||
685 | # CONFIG_USB_GADGET is not set | ||
686 | |||
687 | # | ||
688 | # MMC/SD Card support | ||
689 | # | ||
690 | # CONFIG_MMC is not set | ||
691 | |||
692 | # | ||
693 | # InfiniBand support | ||
694 | # | ||
695 | # CONFIG_INFINIBAND is not set | ||
696 | |||
697 | # | ||
698 | # SN Devices | ||
699 | # | ||
700 | |||
701 | # | ||
702 | # File systems | ||
703 | # | ||
704 | CONFIG_EXT2_FS=y | ||
705 | # CONFIG_EXT2_FS_XATTR is not set | ||
706 | # CONFIG_EXT2_FS_XIP is not set | ||
707 | CONFIG_EXT3_FS=y | ||
708 | CONFIG_EXT3_FS_XATTR=y | ||
709 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
710 | # CONFIG_EXT3_FS_SECURITY is not set | ||
711 | CONFIG_JBD=y | ||
712 | # CONFIG_JBD_DEBUG is not set | ||
713 | CONFIG_FS_MBCACHE=y | ||
714 | # CONFIG_REISERFS_FS is not set | ||
715 | # CONFIG_JFS_FS is not set | ||
716 | # CONFIG_FS_POSIX_ACL is not set | ||
717 | # CONFIG_XFS_FS is not set | ||
718 | # CONFIG_MINIX_FS is not set | ||
719 | # CONFIG_ROMFS_FS is not set | ||
720 | CONFIG_INOTIFY=y | ||
721 | # CONFIG_QUOTA is not set | ||
722 | CONFIG_DNOTIFY=y | ||
723 | # CONFIG_AUTOFS_FS is not set | ||
724 | # CONFIG_AUTOFS4_FS is not set | ||
725 | # CONFIG_FUSE_FS is not set | ||
726 | |||
727 | # | ||
728 | # CD-ROM/DVD Filesystems | ||
729 | # | ||
730 | # CONFIG_ISO9660_FS is not set | ||
731 | # CONFIG_UDF_FS is not set | ||
732 | |||
733 | # | ||
734 | # DOS/FAT/NT Filesystems | ||
735 | # | ||
736 | # CONFIG_MSDOS_FS is not set | ||
737 | # CONFIG_VFAT_FS is not set | ||
738 | # CONFIG_NTFS_FS is not set | ||
739 | |||
740 | # | ||
741 | # Pseudo filesystems | ||
742 | # | ||
743 | CONFIG_PROC_FS=y | ||
744 | CONFIG_PROC_KCORE=y | ||
745 | CONFIG_SYSFS=y | ||
746 | CONFIG_TMPFS=y | ||
747 | # CONFIG_HUGETLB_PAGE is not set | ||
748 | CONFIG_RAMFS=y | ||
749 | # CONFIG_RELAYFS_FS is not set | ||
750 | |||
751 | # | ||
752 | # Miscellaneous filesystems | ||
753 | # | ||
754 | # CONFIG_ADFS_FS is not set | ||
755 | # CONFIG_AFFS_FS is not set | ||
756 | # CONFIG_HFS_FS is not set | ||
757 | # CONFIG_HFSPLUS_FS is not set | ||
758 | # CONFIG_BEFS_FS is not set | ||
759 | # CONFIG_BFS_FS is not set | ||
760 | # CONFIG_EFS_FS is not set | ||
761 | # CONFIG_CRAMFS is not set | ||
762 | # CONFIG_VXFS_FS is not set | ||
763 | # CONFIG_HPFS_FS is not set | ||
764 | # CONFIG_QNX4FS_FS is not set | ||
765 | # CONFIG_SYSV_FS is not set | ||
766 | # CONFIG_UFS_FS is not set | ||
767 | |||
768 | # | ||
769 | # Network File Systems | ||
770 | # | ||
771 | CONFIG_NFS_FS=y | ||
772 | # CONFIG_NFS_V3 is not set | ||
773 | # CONFIG_NFS_V4 is not set | ||
774 | # CONFIG_NFS_DIRECTIO is not set | ||
775 | # CONFIG_NFSD is not set | ||
776 | CONFIG_ROOT_NFS=y | ||
777 | CONFIG_LOCKD=y | ||
778 | CONFIG_NFS_COMMON=y | ||
779 | CONFIG_SUNRPC=y | ||
780 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
781 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
782 | # CONFIG_SMB_FS is not set | ||
783 | # CONFIG_CIFS is not set | ||
784 | # CONFIG_NCP_FS is not set | ||
785 | # CONFIG_CODA_FS is not set | ||
786 | # CONFIG_AFS_FS is not set | ||
787 | # CONFIG_9P_FS is not set | ||
788 | |||
789 | # | ||
790 | # Partition Types | ||
791 | # | ||
792 | CONFIG_PARTITION_ADVANCED=y | ||
793 | # CONFIG_ACORN_PARTITION is not set | ||
794 | # CONFIG_OSF_PARTITION is not set | ||
795 | # CONFIG_AMIGA_PARTITION is not set | ||
796 | # CONFIG_ATARI_PARTITION is not set | ||
797 | # CONFIG_MAC_PARTITION is not set | ||
798 | # CONFIG_MSDOS_PARTITION is not set | ||
799 | # CONFIG_LDM_PARTITION is not set | ||
800 | # CONFIG_SGI_PARTITION is not set | ||
801 | # CONFIG_ULTRIX_PARTITION is not set | ||
802 | # CONFIG_SUN_PARTITION is not set | ||
803 | # CONFIG_EFI_PARTITION is not set | ||
804 | |||
805 | # | ||
806 | # Native Language Support | ||
807 | # | ||
808 | # CONFIG_NLS is not set | ||
809 | |||
810 | # | ||
811 | # Library routines | ||
812 | # | ||
813 | # CONFIG_CRC_CCITT is not set | ||
814 | # CONFIG_CRC16 is not set | ||
815 | CONFIG_CRC32=y | ||
816 | # CONFIG_LIBCRC32C is not set | ||
817 | |||
818 | # | ||
819 | # Profiling support | ||
820 | # | ||
821 | # CONFIG_PROFILING is not set | ||
822 | |||
823 | # | ||
824 | # Kernel hacking | ||
825 | # | ||
826 | # CONFIG_PRINTK_TIME is not set | ||
827 | # CONFIG_DEBUG_KERNEL is not set | ||
828 | CONFIG_LOG_BUF_SHIFT=14 | ||
829 | # CONFIG_SERIAL_TEXT_DEBUG is not set | ||
830 | |||
831 | # | ||
832 | # Security options | ||
833 | # | ||
834 | # CONFIG_KEYS is not set | ||
835 | # CONFIG_SECURITY is not set | ||
836 | |||
837 | # | ||
838 | # Cryptographic options | ||
839 | # | ||
840 | # CONFIG_CRYPTO is not set | ||
841 | |||
842 | # | ||
843 | # Hardware crypto devices | ||
844 | # | ||
diff --git a/arch/ppc/kernel/ppc_ksyms.c b/arch/ppc/kernel/ppc_ksyms.c index 0d53dc378c7d..ba729ce2071c 100644 --- a/arch/ppc/kernel/ppc_ksyms.c +++ b/arch/ppc/kernel/ppc_ksyms.c | |||
@@ -244,8 +244,7 @@ EXPORT_SYMBOL(debugger_fault_handler); | |||
244 | EXPORT_SYMBOL(cpm_install_handler); | 244 | EXPORT_SYMBOL(cpm_install_handler); |
245 | EXPORT_SYMBOL(cpm_free_handler); | 245 | EXPORT_SYMBOL(cpm_free_handler); |
246 | #endif /* CONFIG_8xx */ | 246 | #endif /* CONFIG_8xx */ |
247 | #if defined(CONFIG_8xx) || defined(CONFIG_40x) || defined(CONFIG_85xx) ||\ | 247 | #if defined(CONFIG_8xx) || defined(CONFIG_40x) || defined(CONFIG_85xx) |
248 | defined(CONFIG_83xx) | ||
249 | EXPORT_SYMBOL(__res); | 248 | EXPORT_SYMBOL(__res); |
250 | #endif | 249 | #endif |
251 | 250 | ||
diff --git a/arch/ppc/kernel/setup.c b/arch/ppc/kernel/setup.c index 3c453029f1c5..5888ae6a4ac8 100644 --- a/arch/ppc/kernel/setup.c +++ b/arch/ppc/kernel/setup.c | |||
@@ -38,7 +38,7 @@ | |||
38 | #include <asm/xmon.h> | 38 | #include <asm/xmon.h> |
39 | #include <asm/ocp.h> | 39 | #include <asm/ocp.h> |
40 | 40 | ||
41 | #define USES_PPC_SYS (defined(CONFIG_85xx) || defined(CONFIG_83xx) || \ | 41 | #define USES_PPC_SYS (defined(CONFIG_85xx) || \ |
42 | defined(CONFIG_MPC10X_BRIDGE) || defined(CONFIG_8260) || \ | 42 | defined(CONFIG_MPC10X_BRIDGE) || defined(CONFIG_8260) || \ |
43 | defined(CONFIG_PPC_MPC52xx)) | 43 | defined(CONFIG_PPC_MPC52xx)) |
44 | 44 | ||
diff --git a/arch/ppc/mm/mmu_context.c b/arch/ppc/mm/mmu_context.c index 85afa7f8aa78..dacf45ced473 100644 --- a/arch/ppc/mm/mmu_context.c +++ b/arch/ppc/mm/mmu_context.c | |||
@@ -2,7 +2,7 @@ | |||
2 | * This file contains the routines for handling the MMU on those | 2 | * This file contains the routines for handling the MMU on those |
3 | * PowerPC implementations where the MMU substantially follows the | 3 | * PowerPC implementations where the MMU substantially follows the |
4 | * architecture specification. This includes the 6xx, 7xx, 7xxx, | 4 | * architecture specification. This includes the 6xx, 7xx, 7xxx, |
5 | * 8260, and 83xx implementations but excludes the 8xx and 4xx. | 5 | * and 8260 implementations but excludes the 8xx and 4xx. |
6 | * -- paulus | 6 | * -- paulus |
7 | * | 7 | * |
8 | * Derived from arch/ppc/mm/init.c: | 8 | * Derived from arch/ppc/mm/init.c: |
diff --git a/arch/ppc/mm/ppc_mmu.c b/arch/ppc/mm/ppc_mmu.c index 973f1e6afa53..0c1dc155996a 100644 --- a/arch/ppc/mm/ppc_mmu.c +++ b/arch/ppc/mm/ppc_mmu.c | |||
@@ -2,7 +2,7 @@ | |||
2 | * This file contains the routines for handling the MMU on those | 2 | * This file contains the routines for handling the MMU on those |
3 | * PowerPC implementations where the MMU substantially follows the | 3 | * PowerPC implementations where the MMU substantially follows the |
4 | * architecture specification. This includes the 6xx, 7xx, 7xxx, | 4 | * architecture specification. This includes the 6xx, 7xx, 7xxx, |
5 | * 8260, and 83xx implementations but excludes the 8xx and 4xx. | 5 | * and 8260 implementations but excludes the 8xx and 4xx. |
6 | * -- paulus | 6 | * -- paulus |
7 | * | 7 | * |
8 | * Derived from arch/ppc/mm/init.c: | 8 | * Derived from arch/ppc/mm/init.c: |
diff --git a/arch/ppc/platforms/83xx/Makefile b/arch/ppc/platforms/83xx/Makefile deleted file mode 100644 index eb55341d6a17..000000000000 --- a/arch/ppc/platforms/83xx/Makefile +++ /dev/null | |||
@@ -1,4 +0,0 @@ | |||
1 | # | ||
2 | # Makefile for the PowerPC 83xx linux kernel. | ||
3 | # | ||
4 | obj-$(CONFIG_MPC834x_SYS) += mpc834x_sys.o | ||
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.c b/arch/ppc/platforms/83xx/mpc834x_sys.c deleted file mode 100644 index b84f8df325c4..000000000000 --- a/arch/ppc/platforms/83xx/mpc834x_sys.c +++ /dev/null | |||
@@ -1,346 +0,0 @@ | |||
1 | /* | ||
2 | * MPC834x SYS board specific routines | ||
3 | * | ||
4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | ||
5 | * | ||
6 | * Copyright 2005 Freescale Semiconductor Inc. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | */ | ||
13 | |||
14 | #include <linux/stddef.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <linux/errno.h> | ||
18 | #include <linux/reboot.h> | ||
19 | #include <linux/pci.h> | ||
20 | #include <linux/kdev_t.h> | ||
21 | #include <linux/major.h> | ||
22 | #include <linux/console.h> | ||
23 | #include <linux/delay.h> | ||
24 | #include <linux/seq_file.h> | ||
25 | #include <linux/root_dev.h> | ||
26 | #include <linux/serial.h> | ||
27 | #include <linux/tty.h> /* for linux/serial_core.h */ | ||
28 | #include <linux/serial_core.h> | ||
29 | #include <linux/initrd.h> | ||
30 | #include <linux/module.h> | ||
31 | #include <linux/fsl_devices.h> | ||
32 | |||
33 | #include <asm/system.h> | ||
34 | #include <asm/pgtable.h> | ||
35 | #include <asm/page.h> | ||
36 | #include <asm/atomic.h> | ||
37 | #include <asm/time.h> | ||
38 | #include <asm/io.h> | ||
39 | #include <asm/machdep.h> | ||
40 | #include <asm/ipic.h> | ||
41 | #include <asm/bootinfo.h> | ||
42 | #include <asm/pci-bridge.h> | ||
43 | #include <asm/mpc83xx.h> | ||
44 | #include <asm/irq.h> | ||
45 | #include <asm/kgdb.h> | ||
46 | #include <asm/ppc_sys.h> | ||
47 | #include <mm/mmu_decl.h> | ||
48 | |||
49 | #include <syslib/ppc83xx_setup.h> | ||
50 | |||
51 | #ifndef CONFIG_PCI | ||
52 | unsigned long isa_io_base = 0; | ||
53 | unsigned long isa_mem_base = 0; | ||
54 | #endif | ||
55 | |||
56 | extern unsigned long total_memory; /* in mm/init */ | ||
57 | |||
58 | unsigned char __res[sizeof (bd_t)]; | ||
59 | |||
60 | #ifdef CONFIG_PCI | ||
61 | int | ||
62 | mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | ||
63 | { | ||
64 | static char pci_irq_table[][4] = | ||
65 | /* | ||
66 | * PCI IDSEL/INTPIN->INTLINE | ||
67 | * A B C D | ||
68 | */ | ||
69 | { | ||
70 | {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */ | ||
71 | {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */ | ||
72 | {PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x13 */ | ||
73 | {0, 0, 0, 0}, | ||
74 | {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x15 */ | ||
75 | {PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x16 */ | ||
76 | {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x17 */ | ||
77 | {PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x18 */ | ||
78 | {0, 0, 0, 0}, /* idsel 0x19 */ | ||
79 | {0, 0, 0, 0}, /* idsel 0x20 */ | ||
80 | }; | ||
81 | |||
82 | const long min_idsel = 0x11, max_idsel = 0x20, irqs_per_slot = 4; | ||
83 | return PCI_IRQ_TABLE_LOOKUP; | ||
84 | } | ||
85 | |||
86 | int | ||
87 | mpc83xx_exclude_device(u_char bus, u_char devfn) | ||
88 | { | ||
89 | return PCIBIOS_SUCCESSFUL; | ||
90 | } | ||
91 | #endif /* CONFIG_PCI */ | ||
92 | |||
93 | /* ************************************************************************ | ||
94 | * | ||
95 | * Setup the architecture | ||
96 | * | ||
97 | */ | ||
98 | static void __init | ||
99 | mpc834x_sys_setup_arch(void) | ||
100 | { | ||
101 | bd_t *binfo = (bd_t *) __res; | ||
102 | unsigned int freq; | ||
103 | struct gianfar_platform_data *pdata; | ||
104 | struct gianfar_mdio_data *mdata; | ||
105 | |||
106 | /* get the core frequency */ | ||
107 | freq = binfo->bi_intfreq; | ||
108 | |||
109 | /* Set loops_per_jiffy to a half-way reasonable value, | ||
110 | for use until calibrate_delay gets called. */ | ||
111 | loops_per_jiffy = freq / HZ; | ||
112 | |||
113 | #ifdef CONFIG_PCI | ||
114 | /* setup PCI host bridges */ | ||
115 | mpc83xx_setup_hose(); | ||
116 | #endif | ||
117 | mpc83xx_early_serial_map(); | ||
118 | |||
119 | /* setup the board related info for the MDIO bus */ | ||
120 | mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC83xx_MDIO); | ||
121 | |||
122 | mdata->irq[0] = MPC83xx_IRQ_EXT1; | ||
123 | mdata->irq[1] = MPC83xx_IRQ_EXT2; | ||
124 | mdata->irq[2] = PHY_POLL; | ||
125 | mdata->irq[31] = PHY_POLL; | ||
126 | |||
127 | /* setup the board related information for the enet controllers */ | ||
128 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1); | ||
129 | if (pdata) { | ||
130 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; | ||
131 | pdata->bus_id = 0; | ||
132 | pdata->phy_id = 0; | ||
133 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); | ||
134 | } | ||
135 | |||
136 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2); | ||
137 | if (pdata) { | ||
138 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; | ||
139 | pdata->bus_id = 0; | ||
140 | pdata->phy_id = 1; | ||
141 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); | ||
142 | } | ||
143 | |||
144 | #ifdef CONFIG_BLK_DEV_INITRD | ||
145 | if (initrd_start) | ||
146 | ROOT_DEV = Root_RAM0; | ||
147 | else | ||
148 | #endif | ||
149 | #ifdef CONFIG_ROOT_NFS | ||
150 | ROOT_DEV = Root_NFS; | ||
151 | #else | ||
152 | ROOT_DEV = Root_HDA1; | ||
153 | #endif | ||
154 | } | ||
155 | |||
156 | static void __init | ||
157 | mpc834x_sys_map_io(void) | ||
158 | { | ||
159 | /* we steal the lowest ioremap addr for virt space */ | ||
160 | io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO); | ||
161 | } | ||
162 | |||
163 | int | ||
164 | mpc834x_sys_show_cpuinfo(struct seq_file *m) | ||
165 | { | ||
166 | uint pvid, svid, phid1; | ||
167 | bd_t *binfo = (bd_t *) __res; | ||
168 | unsigned int freq; | ||
169 | |||
170 | /* get the core frequency */ | ||
171 | freq = binfo->bi_intfreq; | ||
172 | |||
173 | pvid = mfspr(SPRN_PVR); | ||
174 | svid = mfspr(SPRN_SVR); | ||
175 | |||
176 | seq_printf(m, "Vendor\t\t: Freescale Inc.\n"); | ||
177 | seq_printf(m, "Machine\t\t: mpc%s sys\n", cur_ppc_sys_spec->ppc_sys_name); | ||
178 | seq_printf(m, "core clock\t: %d MHz\n" | ||
179 | "bus clock\t: %d MHz\n", | ||
180 | (int)(binfo->bi_intfreq / 1000000), | ||
181 | (int)(binfo->bi_busfreq / 1000000)); | ||
182 | seq_printf(m, "PVR\t\t: 0x%x\n", pvid); | ||
183 | seq_printf(m, "SVR\t\t: 0x%x\n", svid); | ||
184 | |||
185 | /* Display cpu Pll setting */ | ||
186 | phid1 = mfspr(SPRN_HID1); | ||
187 | seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); | ||
188 | |||
189 | /* Display the amount of memory */ | ||
190 | seq_printf(m, "Memory\t\t: %d MB\n", (int)(binfo->bi_memsize / (1024 * 1024))); | ||
191 | |||
192 | return 0; | ||
193 | } | ||
194 | |||
195 | |||
196 | void __init | ||
197 | mpc834x_sys_init_IRQ(void) | ||
198 | { | ||
199 | bd_t *binfo = (bd_t *) __res; | ||
200 | |||
201 | u8 senses[8] = { | ||
202 | 0, /* EXT 0 */ | ||
203 | IRQ_SENSE_LEVEL, /* EXT 1 */ | ||
204 | IRQ_SENSE_LEVEL, /* EXT 2 */ | ||
205 | 0, /* EXT 3 */ | ||
206 | #ifdef CONFIG_PCI | ||
207 | IRQ_SENSE_LEVEL, /* EXT 4 */ | ||
208 | IRQ_SENSE_LEVEL, /* EXT 5 */ | ||
209 | IRQ_SENSE_LEVEL, /* EXT 6 */ | ||
210 | IRQ_SENSE_LEVEL, /* EXT 7 */ | ||
211 | #else | ||
212 | 0, /* EXT 4 */ | ||
213 | 0, /* EXT 5 */ | ||
214 | 0, /* EXT 6 */ | ||
215 | 0, /* EXT 7 */ | ||
216 | #endif | ||
217 | }; | ||
218 | |||
219 | ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8); | ||
220 | |||
221 | /* Initialize the default interrupt mapping priorities, | ||
222 | * in case the boot rom changed something on us. | ||
223 | */ | ||
224 | ipic_set_default_priority(); | ||
225 | } | ||
226 | |||
227 | #if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374) | ||
228 | extern ulong ds1374_get_rtc_time(void); | ||
229 | extern int ds1374_set_rtc_time(ulong); | ||
230 | |||
231 | static int __init | ||
232 | mpc834x_rtc_hookup(void) | ||
233 | { | ||
234 | struct timespec tv; | ||
235 | |||
236 | ppc_md.get_rtc_time = ds1374_get_rtc_time; | ||
237 | ppc_md.set_rtc_time = ds1374_set_rtc_time; | ||
238 | |||
239 | tv.tv_nsec = 0; | ||
240 | tv.tv_sec = (ppc_md.get_rtc_time)(); | ||
241 | do_settimeofday(&tv); | ||
242 | |||
243 | return 0; | ||
244 | } | ||
245 | late_initcall(mpc834x_rtc_hookup); | ||
246 | #endif | ||
247 | static __inline__ void | ||
248 | mpc834x_sys_set_bat(void) | ||
249 | { | ||
250 | /* we steal the lowest ioremap addr for virt space */ | ||
251 | mb(); | ||
252 | mtspr(SPRN_DBAT1U, VIRT_IMMRBAR | 0x1e); | ||
253 | mtspr(SPRN_DBAT1L, immrbar | 0x2a); | ||
254 | mb(); | ||
255 | } | ||
256 | |||
257 | void __init | ||
258 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, | ||
259 | unsigned long r6, unsigned long r7) | ||
260 | { | ||
261 | bd_t *binfo = (bd_t *) __res; | ||
262 | |||
263 | /* parse_bootinfo must always be called first */ | ||
264 | parse_bootinfo(find_bootinfo()); | ||
265 | |||
266 | /* | ||
267 | * If we were passed in a board information, copy it into the | ||
268 | * residual data area. | ||
269 | */ | ||
270 | if (r3) { | ||
271 | memcpy((void *) __res, (void *) (r3 + KERNELBASE), | ||
272 | sizeof (bd_t)); | ||
273 | } | ||
274 | |||
275 | #if defined(CONFIG_BLK_DEV_INITRD) | ||
276 | /* | ||
277 | * If the init RAM disk has been configured in, and there's a valid | ||
278 | * starting address for it, set it up. | ||
279 | */ | ||
280 | if (r4) { | ||
281 | initrd_start = r4 + KERNELBASE; | ||
282 | initrd_end = r5 + KERNELBASE; | ||
283 | } | ||
284 | #endif /* CONFIG_BLK_DEV_INITRD */ | ||
285 | |||
286 | /* Copy the kernel command line arguments to a safe place. */ | ||
287 | if (r6) { | ||
288 | *(char *) (r7 + KERNELBASE) = 0; | ||
289 | strcpy(cmd_line, (char *) (r6 + KERNELBASE)); | ||
290 | } | ||
291 | |||
292 | immrbar = binfo->bi_immr_base; | ||
293 | |||
294 | mpc834x_sys_set_bat(); | ||
295 | |||
296 | #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG) | ||
297 | { | ||
298 | struct uart_port p; | ||
299 | |||
300 | memset(&p, 0, sizeof (p)); | ||
301 | p.iotype = UPIO_MEM; | ||
302 | p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4500); | ||
303 | p.uartclk = binfo->bi_busfreq; | ||
304 | |||
305 | gen550_init(0, &p); | ||
306 | |||
307 | memset(&p, 0, sizeof (p)); | ||
308 | p.iotype = UPIO_MEM; | ||
309 | p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4600); | ||
310 | p.uartclk = binfo->bi_busfreq; | ||
311 | |||
312 | gen550_init(1, &p); | ||
313 | } | ||
314 | #endif | ||
315 | |||
316 | identify_ppc_sys_by_id(mfspr(SPRN_SVR)); | ||
317 | |||
318 | /* setup the PowerPC module struct */ | ||
319 | ppc_md.setup_arch = mpc834x_sys_setup_arch; | ||
320 | ppc_md.show_cpuinfo = mpc834x_sys_show_cpuinfo; | ||
321 | |||
322 | ppc_md.init_IRQ = mpc834x_sys_init_IRQ; | ||
323 | ppc_md.get_irq = ipic_get_irq; | ||
324 | |||
325 | ppc_md.restart = mpc83xx_restart; | ||
326 | ppc_md.power_off = mpc83xx_power_off; | ||
327 | ppc_md.halt = mpc83xx_halt; | ||
328 | |||
329 | ppc_md.find_end_of_memory = mpc83xx_find_end_of_memory; | ||
330 | ppc_md.setup_io_mappings = mpc834x_sys_map_io; | ||
331 | |||
332 | ppc_md.time_init = mpc83xx_time_init; | ||
333 | ppc_md.set_rtc_time = NULL; | ||
334 | ppc_md.get_rtc_time = NULL; | ||
335 | ppc_md.calibrate_decr = mpc83xx_calibrate_decr; | ||
336 | |||
337 | ppc_md.early_serial_map = mpc83xx_early_serial_map; | ||
338 | #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG) | ||
339 | ppc_md.progress = gen550_progress; | ||
340 | #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */ | ||
341 | |||
342 | if (ppc_md.progress) | ||
343 | ppc_md.progress("mpc834x_sys_init(): exit", 0); | ||
344 | |||
345 | return; | ||
346 | } | ||
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h deleted file mode 100644 index d2e06c95b083..000000000000 --- a/arch/ppc/platforms/83xx/mpc834x_sys.h +++ /dev/null | |||
@@ -1,54 +0,0 @@ | |||
1 | /* | ||
2 | * MPC834X SYS common board definitions | ||
3 | * | ||
4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | ||
5 | * | ||
6 | * Copyright 2005 Freescale Semiconductor, Inc. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | * | ||
13 | */ | ||
14 | |||
15 | #ifndef __MACH_MPC83XX_SYS_H__ | ||
16 | #define __MACH_MPC83XX_SYS_H__ | ||
17 | |||
18 | #include <linux/init.h> | ||
19 | #include <syslib/ppc83xx_setup.h> | ||
20 | #include <asm/ppcboot.h> | ||
21 | |||
22 | #define VIRT_IMMRBAR ((uint)0xfe000000) | ||
23 | |||
24 | #define BCSR_PHYS_ADDR ((uint)0xf8000000) | ||
25 | #define BCSR_SIZE ((uint)(32 * 1024)) | ||
26 | |||
27 | #define BCSR_MISC_REG2_OFF 0x07 | ||
28 | #define BCSR_MISC_REG2_PORESET 0x01 | ||
29 | |||
30 | #define BCSR_MISC_REG3_OFF 0x08 | ||
31 | #define BCSR_MISC_REG3_CNFLOCK 0x80 | ||
32 | |||
33 | #define PIRQA MPC83xx_IRQ_EXT4 | ||
34 | #define PIRQB MPC83xx_IRQ_EXT5 | ||
35 | #define PIRQC MPC83xx_IRQ_EXT6 | ||
36 | #define PIRQD MPC83xx_IRQ_EXT7 | ||
37 | |||
38 | #define MPC83xx_PCI1_LOWER_IO 0x00000000 | ||
39 | #define MPC83xx_PCI1_UPPER_IO 0x00ffffff | ||
40 | #define MPC83xx_PCI1_LOWER_MEM 0x80000000 | ||
41 | #define MPC83xx_PCI1_UPPER_MEM 0x9fffffff | ||
42 | #define MPC83xx_PCI1_IO_BASE 0xe2000000 | ||
43 | #define MPC83xx_PCI1_MEM_OFFSET 0x00000000 | ||
44 | #define MPC83xx_PCI1_IO_SIZE 0x01000000 | ||
45 | |||
46 | #define MPC83xx_PCI2_LOWER_IO 0x00000000 | ||
47 | #define MPC83xx_PCI2_UPPER_IO 0x00ffffff | ||
48 | #define MPC83xx_PCI2_LOWER_MEM 0xa0000000 | ||
49 | #define MPC83xx_PCI2_UPPER_MEM 0xbfffffff | ||
50 | #define MPC83xx_PCI2_IO_BASE 0xe3000000 | ||
51 | #define MPC83xx_PCI2_MEM_OFFSET 0x00000000 | ||
52 | #define MPC83xx_PCI2_IO_SIZE 0x01000000 | ||
53 | |||
54 | #endif /* __MACH_MPC83XX_SYS_H__ */ | ||
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index 5e16228f7645..4d158f3bd474 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile | |||
@@ -93,11 +93,6 @@ obj-$(CONFIG_85xx) += open_pic.o ppc85xx_common.o ppc85xx_setup.o \ | |||
93 | ifeq ($(CONFIG_85xx),y) | 93 | ifeq ($(CONFIG_85xx),y) |
94 | obj-$(CONFIG_PCI) += pci_auto.o | 94 | obj-$(CONFIG_PCI) += pci_auto.o |
95 | endif | 95 | endif |
96 | obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \ | ||
97 | mpc83xx_sys.o mpc83xx_devices.o ipic.o | ||
98 | ifeq ($(CONFIG_83xx),y) | ||
99 | obj-$(CONFIG_PCI) += pci_auto.o | ||
100 | endif | ||
101 | obj-$(CONFIG_MPC8548_CDS) += todc_time.o | 96 | obj-$(CONFIG_MPC8548_CDS) += todc_time.o |
102 | obj-$(CONFIG_MPC8555_CDS) += todc_time.o | 97 | obj-$(CONFIG_MPC8555_CDS) += todc_time.o |
103 | obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ | 98 | obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ |
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c deleted file mode 100644 index 9192777d0f78..000000000000 --- a/arch/ppc/syslib/ipic.c +++ /dev/null | |||
@@ -1,646 +0,0 @@ | |||
1 | /* | ||
2 | * arch/ppc/syslib/ipic.c | ||
3 | * | ||
4 | * IPIC routines implementations. | ||
5 | * | ||
6 | * Copyright 2005 Freescale Semiconductor, Inc. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | */ | ||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/init.h> | ||
15 | #include <linux/errno.h> | ||
16 | #include <linux/reboot.h> | ||
17 | #include <linux/slab.h> | ||
18 | #include <linux/stddef.h> | ||
19 | #include <linux/sched.h> | ||
20 | #include <linux/signal.h> | ||
21 | #include <linux/sysdev.h> | ||
22 | #include <asm/irq.h> | ||
23 | #include <asm/io.h> | ||
24 | #include <asm/ipic.h> | ||
25 | #include <asm/mpc83xx.h> | ||
26 | |||
27 | #include "ipic.h" | ||
28 | |||
29 | static struct ipic p_ipic; | ||
30 | static struct ipic * primary_ipic; | ||
31 | |||
32 | static struct ipic_info ipic_info[] = { | ||
33 | [9] = { | ||
34 | .pend = IPIC_SIPNR_H, | ||
35 | .mask = IPIC_SIMSR_H, | ||
36 | .prio = IPIC_SIPRR_D, | ||
37 | .force = IPIC_SIFCR_H, | ||
38 | .bit = 24, | ||
39 | .prio_mask = 0, | ||
40 | }, | ||
41 | [10] = { | ||
42 | .pend = IPIC_SIPNR_H, | ||
43 | .mask = IPIC_SIMSR_H, | ||
44 | .prio = IPIC_SIPRR_D, | ||
45 | .force = IPIC_SIFCR_H, | ||
46 | .bit = 25, | ||
47 | .prio_mask = 1, | ||
48 | }, | ||
49 | [11] = { | ||
50 | .pend = IPIC_SIPNR_H, | ||
51 | .mask = IPIC_SIMSR_H, | ||
52 | .prio = IPIC_SIPRR_D, | ||
53 | .force = IPIC_SIFCR_H, | ||
54 | .bit = 26, | ||
55 | .prio_mask = 2, | ||
56 | }, | ||
57 | [14] = { | ||
58 | .pend = IPIC_SIPNR_H, | ||
59 | .mask = IPIC_SIMSR_H, | ||
60 | .prio = IPIC_SIPRR_D, | ||
61 | .force = IPIC_SIFCR_H, | ||
62 | .bit = 29, | ||
63 | .prio_mask = 5, | ||
64 | }, | ||
65 | [15] = { | ||
66 | .pend = IPIC_SIPNR_H, | ||
67 | .mask = IPIC_SIMSR_H, | ||
68 | .prio = IPIC_SIPRR_D, | ||
69 | .force = IPIC_SIFCR_H, | ||
70 | .bit = 30, | ||
71 | .prio_mask = 6, | ||
72 | }, | ||
73 | [16] = { | ||
74 | .pend = IPIC_SIPNR_H, | ||
75 | .mask = IPIC_SIMSR_H, | ||
76 | .prio = IPIC_SIPRR_D, | ||
77 | .force = IPIC_SIFCR_H, | ||
78 | .bit = 31, | ||
79 | .prio_mask = 7, | ||
80 | }, | ||
81 | [17] = { | ||
82 | .pend = IPIC_SEPNR, | ||
83 | .mask = IPIC_SEMSR, | ||
84 | .prio = IPIC_SMPRR_A, | ||
85 | .force = IPIC_SEFCR, | ||
86 | .bit = 1, | ||
87 | .prio_mask = 5, | ||
88 | }, | ||
89 | [18] = { | ||
90 | .pend = IPIC_SEPNR, | ||
91 | .mask = IPIC_SEMSR, | ||
92 | .prio = IPIC_SMPRR_A, | ||
93 | .force = IPIC_SEFCR, | ||
94 | .bit = 2, | ||
95 | .prio_mask = 6, | ||
96 | }, | ||
97 | [19] = { | ||
98 | .pend = IPIC_SEPNR, | ||
99 | .mask = IPIC_SEMSR, | ||
100 | .prio = IPIC_SMPRR_A, | ||
101 | .force = IPIC_SEFCR, | ||
102 | .bit = 3, | ||
103 | .prio_mask = 7, | ||
104 | }, | ||
105 | [20] = { | ||
106 | .pend = IPIC_SEPNR, | ||
107 | .mask = IPIC_SEMSR, | ||
108 | .prio = IPIC_SMPRR_B, | ||
109 | .force = IPIC_SEFCR, | ||
110 | .bit = 4, | ||
111 | .prio_mask = 4, | ||
112 | }, | ||
113 | [21] = { | ||
114 | .pend = IPIC_SEPNR, | ||
115 | .mask = IPIC_SEMSR, | ||
116 | .prio = IPIC_SMPRR_B, | ||
117 | .force = IPIC_SEFCR, | ||
118 | .bit = 5, | ||
119 | .prio_mask = 5, | ||
120 | }, | ||
121 | [22] = { | ||
122 | .pend = IPIC_SEPNR, | ||
123 | .mask = IPIC_SEMSR, | ||
124 | .prio = IPIC_SMPRR_B, | ||
125 | .force = IPIC_SEFCR, | ||
126 | .bit = 6, | ||
127 | .prio_mask = 6, | ||
128 | }, | ||
129 | [23] = { | ||
130 | .pend = IPIC_SEPNR, | ||
131 | .mask = IPIC_SEMSR, | ||
132 | .prio = IPIC_SMPRR_B, | ||
133 | .force = IPIC_SEFCR, | ||
134 | .bit = 7, | ||
135 | .prio_mask = 7, | ||
136 | }, | ||
137 | [32] = { | ||
138 | .pend = IPIC_SIPNR_H, | ||
139 | .mask = IPIC_SIMSR_H, | ||
140 | .prio = IPIC_SIPRR_A, | ||
141 | .force = IPIC_SIFCR_H, | ||
142 | .bit = 0, | ||
143 | .prio_mask = 0, | ||
144 | }, | ||
145 | [33] = { | ||
146 | .pend = IPIC_SIPNR_H, | ||
147 | .mask = IPIC_SIMSR_H, | ||
148 | .prio = IPIC_SIPRR_A, | ||
149 | .force = IPIC_SIFCR_H, | ||
150 | .bit = 1, | ||
151 | .prio_mask = 1, | ||
152 | }, | ||
153 | [34] = { | ||
154 | .pend = IPIC_SIPNR_H, | ||
155 | .mask = IPIC_SIMSR_H, | ||
156 | .prio = IPIC_SIPRR_A, | ||
157 | .force = IPIC_SIFCR_H, | ||
158 | .bit = 2, | ||
159 | .prio_mask = 2, | ||
160 | }, | ||
161 | [35] = { | ||
162 | .pend = IPIC_SIPNR_H, | ||
163 | .mask = IPIC_SIMSR_H, | ||
164 | .prio = IPIC_SIPRR_A, | ||
165 | .force = IPIC_SIFCR_H, | ||
166 | .bit = 3, | ||
167 | .prio_mask = 3, | ||
168 | }, | ||
169 | [36] = { | ||
170 | .pend = IPIC_SIPNR_H, | ||
171 | .mask = IPIC_SIMSR_H, | ||
172 | .prio = IPIC_SIPRR_A, | ||
173 | .force = IPIC_SIFCR_H, | ||
174 | .bit = 4, | ||
175 | .prio_mask = 4, | ||
176 | }, | ||
177 | [37] = { | ||
178 | .pend = IPIC_SIPNR_H, | ||
179 | .mask = IPIC_SIMSR_H, | ||
180 | .prio = IPIC_SIPRR_A, | ||
181 | .force = IPIC_SIFCR_H, | ||
182 | .bit = 5, | ||
183 | .prio_mask = 5, | ||
184 | }, | ||
185 | [38] = { | ||
186 | .pend = IPIC_SIPNR_H, | ||
187 | .mask = IPIC_SIMSR_H, | ||
188 | .prio = IPIC_SIPRR_A, | ||
189 | .force = IPIC_SIFCR_H, | ||
190 | .bit = 6, | ||
191 | .prio_mask = 6, | ||
192 | }, | ||
193 | [39] = { | ||
194 | .pend = IPIC_SIPNR_H, | ||
195 | .mask = IPIC_SIMSR_H, | ||
196 | .prio = IPIC_SIPRR_A, | ||
197 | .force = IPIC_SIFCR_H, | ||
198 | .bit = 7, | ||
199 | .prio_mask = 7, | ||
200 | }, | ||
201 | [48] = { | ||
202 | .pend = IPIC_SEPNR, | ||
203 | .mask = IPIC_SEMSR, | ||
204 | .prio = IPIC_SMPRR_A, | ||
205 | .force = IPIC_SEFCR, | ||
206 | .bit = 0, | ||
207 | .prio_mask = 4, | ||
208 | }, | ||
209 | [64] = { | ||
210 | .pend = IPIC_SIPNR_H, | ||
211 | .mask = IPIC_SIMSR_L, | ||
212 | .prio = IPIC_SMPRR_A, | ||
213 | .force = IPIC_SIFCR_L, | ||
214 | .bit = 0, | ||
215 | .prio_mask = 0, | ||
216 | }, | ||
217 | [65] = { | ||
218 | .pend = IPIC_SIPNR_H, | ||
219 | .mask = IPIC_SIMSR_L, | ||
220 | .prio = IPIC_SMPRR_A, | ||
221 | .force = IPIC_SIFCR_L, | ||
222 | .bit = 1, | ||
223 | .prio_mask = 1, | ||
224 | }, | ||
225 | [66] = { | ||
226 | .pend = IPIC_SIPNR_H, | ||
227 | .mask = IPIC_SIMSR_L, | ||
228 | .prio = IPIC_SMPRR_A, | ||
229 | .force = IPIC_SIFCR_L, | ||
230 | .bit = 2, | ||
231 | .prio_mask = 2, | ||
232 | }, | ||
233 | [67] = { | ||
234 | .pend = IPIC_SIPNR_H, | ||
235 | .mask = IPIC_SIMSR_L, | ||
236 | .prio = IPIC_SMPRR_A, | ||
237 | .force = IPIC_SIFCR_L, | ||
238 | .bit = 3, | ||
239 | .prio_mask = 3, | ||
240 | }, | ||
241 | [68] = { | ||
242 | .pend = IPIC_SIPNR_H, | ||
243 | .mask = IPIC_SIMSR_L, | ||
244 | .prio = IPIC_SMPRR_B, | ||
245 | .force = IPIC_SIFCR_L, | ||
246 | .bit = 4, | ||
247 | .prio_mask = 0, | ||
248 | }, | ||
249 | [69] = { | ||
250 | .pend = IPIC_SIPNR_H, | ||
251 | .mask = IPIC_SIMSR_L, | ||
252 | .prio = IPIC_SMPRR_B, | ||
253 | .force = IPIC_SIFCR_L, | ||
254 | .bit = 5, | ||
255 | .prio_mask = 1, | ||
256 | }, | ||
257 | [70] = { | ||
258 | .pend = IPIC_SIPNR_H, | ||
259 | .mask = IPIC_SIMSR_L, | ||
260 | .prio = IPIC_SMPRR_B, | ||
261 | .force = IPIC_SIFCR_L, | ||
262 | .bit = 6, | ||
263 | .prio_mask = 2, | ||
264 | }, | ||
265 | [71] = { | ||
266 | .pend = IPIC_SIPNR_H, | ||
267 | .mask = IPIC_SIMSR_L, | ||
268 | .prio = IPIC_SMPRR_B, | ||
269 | .force = IPIC_SIFCR_L, | ||
270 | .bit = 7, | ||
271 | .prio_mask = 3, | ||
272 | }, | ||
273 | [72] = { | ||
274 | .pend = IPIC_SIPNR_H, | ||
275 | .mask = IPIC_SIMSR_L, | ||
276 | .prio = 0, | ||
277 | .force = IPIC_SIFCR_L, | ||
278 | .bit = 8, | ||
279 | }, | ||
280 | [73] = { | ||
281 | .pend = IPIC_SIPNR_H, | ||
282 | .mask = IPIC_SIMSR_L, | ||
283 | .prio = 0, | ||
284 | .force = IPIC_SIFCR_L, | ||
285 | .bit = 9, | ||
286 | }, | ||
287 | [74] = { | ||
288 | .pend = IPIC_SIPNR_H, | ||
289 | .mask = IPIC_SIMSR_L, | ||
290 | .prio = 0, | ||
291 | .force = IPIC_SIFCR_L, | ||
292 | .bit = 10, | ||
293 | }, | ||
294 | [75] = { | ||
295 | .pend = IPIC_SIPNR_H, | ||
296 | .mask = IPIC_SIMSR_L, | ||
297 | .prio = 0, | ||
298 | .force = IPIC_SIFCR_L, | ||
299 | .bit = 11, | ||
300 | }, | ||
301 | [76] = { | ||
302 | .pend = IPIC_SIPNR_H, | ||
303 | .mask = IPIC_SIMSR_L, | ||
304 | .prio = 0, | ||
305 | .force = IPIC_SIFCR_L, | ||
306 | .bit = 12, | ||
307 | }, | ||
308 | [77] = { | ||
309 | .pend = IPIC_SIPNR_H, | ||
310 | .mask = IPIC_SIMSR_L, | ||
311 | .prio = 0, | ||
312 | .force = IPIC_SIFCR_L, | ||
313 | .bit = 13, | ||
314 | }, | ||
315 | [78] = { | ||
316 | .pend = IPIC_SIPNR_H, | ||
317 | .mask = IPIC_SIMSR_L, | ||
318 | .prio = 0, | ||
319 | .force = IPIC_SIFCR_L, | ||
320 | .bit = 14, | ||
321 | }, | ||
322 | [79] = { | ||
323 | .pend = IPIC_SIPNR_H, | ||
324 | .mask = IPIC_SIMSR_L, | ||
325 | .prio = 0, | ||
326 | .force = IPIC_SIFCR_L, | ||
327 | .bit = 15, | ||
328 | }, | ||
329 | [80] = { | ||
330 | .pend = IPIC_SIPNR_H, | ||
331 | .mask = IPIC_SIMSR_L, | ||
332 | .prio = 0, | ||
333 | .force = IPIC_SIFCR_L, | ||
334 | .bit = 16, | ||
335 | }, | ||
336 | [84] = { | ||
337 | .pend = IPIC_SIPNR_H, | ||
338 | .mask = IPIC_SIMSR_L, | ||
339 | .prio = 0, | ||
340 | .force = IPIC_SIFCR_L, | ||
341 | .bit = 20, | ||
342 | }, | ||
343 | [85] = { | ||
344 | .pend = IPIC_SIPNR_H, | ||
345 | .mask = IPIC_SIMSR_L, | ||
346 | .prio = 0, | ||
347 | .force = IPIC_SIFCR_L, | ||
348 | .bit = 21, | ||
349 | }, | ||
350 | [90] = { | ||
351 | .pend = IPIC_SIPNR_H, | ||
352 | .mask = IPIC_SIMSR_L, | ||
353 | .prio = 0, | ||
354 | .force = IPIC_SIFCR_L, | ||
355 | .bit = 26, | ||
356 | }, | ||
357 | [91] = { | ||
358 | .pend = IPIC_SIPNR_H, | ||
359 | .mask = IPIC_SIMSR_L, | ||
360 | .prio = 0, | ||
361 | .force = IPIC_SIFCR_L, | ||
362 | .bit = 27, | ||
363 | }, | ||
364 | }; | ||
365 | |||
366 | static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg) | ||
367 | { | ||
368 | return in_be32(base + (reg >> 2)); | ||
369 | } | ||
370 | |||
371 | static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value) | ||
372 | { | ||
373 | out_be32(base + (reg >> 2), value); | ||
374 | } | ||
375 | |||
376 | static inline struct ipic * ipic_from_irq(unsigned int irq) | ||
377 | { | ||
378 | return primary_ipic; | ||
379 | } | ||
380 | |||
381 | static void ipic_enable_irq(unsigned int irq) | ||
382 | { | ||
383 | struct ipic *ipic = ipic_from_irq(irq); | ||
384 | unsigned int src = irq - ipic->irq_offset; | ||
385 | u32 temp; | ||
386 | |||
387 | temp = ipic_read(ipic->regs, ipic_info[src].mask); | ||
388 | temp |= (1 << (31 - ipic_info[src].bit)); | ||
389 | ipic_write(ipic->regs, ipic_info[src].mask, temp); | ||
390 | } | ||
391 | |||
392 | static void ipic_disable_irq(unsigned int irq) | ||
393 | { | ||
394 | struct ipic *ipic = ipic_from_irq(irq); | ||
395 | unsigned int src = irq - ipic->irq_offset; | ||
396 | u32 temp; | ||
397 | |||
398 | temp = ipic_read(ipic->regs, ipic_info[src].mask); | ||
399 | temp &= ~(1 << (31 - ipic_info[src].bit)); | ||
400 | ipic_write(ipic->regs, ipic_info[src].mask, temp); | ||
401 | } | ||
402 | |||
403 | static void ipic_disable_irq_and_ack(unsigned int irq) | ||
404 | { | ||
405 | struct ipic *ipic = ipic_from_irq(irq); | ||
406 | unsigned int src = irq - ipic->irq_offset; | ||
407 | u32 temp; | ||
408 | |||
409 | ipic_disable_irq(irq); | ||
410 | |||
411 | temp = ipic_read(ipic->regs, ipic_info[src].pend); | ||
412 | temp |= (1 << (31 - ipic_info[src].bit)); | ||
413 | ipic_write(ipic->regs, ipic_info[src].pend, temp); | ||
414 | } | ||
415 | |||
416 | static void ipic_end_irq(unsigned int irq) | ||
417 | { | ||
418 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
419 | ipic_enable_irq(irq); | ||
420 | } | ||
421 | |||
422 | struct hw_interrupt_type ipic = { | ||
423 | .typename = " IPIC ", | ||
424 | .enable = ipic_enable_irq, | ||
425 | .disable = ipic_disable_irq, | ||
426 | .ack = ipic_disable_irq_and_ack, | ||
427 | .end = ipic_end_irq, | ||
428 | }; | ||
429 | |||
430 | void __init ipic_init(phys_addr_t phys_addr, | ||
431 | unsigned int flags, | ||
432 | unsigned int irq_offset, | ||
433 | unsigned char *senses, | ||
434 | unsigned int senses_count) | ||
435 | { | ||
436 | u32 i, temp = 0; | ||
437 | |||
438 | primary_ipic = &p_ipic; | ||
439 | primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE); | ||
440 | |||
441 | primary_ipic->irq_offset = irq_offset; | ||
442 | |||
443 | ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0); | ||
444 | |||
445 | /* default priority scheme is grouped. If spread mode is required | ||
446 | * configure SICFR accordingly */ | ||
447 | if (flags & IPIC_SPREADMODE_GRP_A) | ||
448 | temp |= SICFR_IPSA; | ||
449 | if (flags & IPIC_SPREADMODE_GRP_D) | ||
450 | temp |= SICFR_IPSD; | ||
451 | if (flags & IPIC_SPREADMODE_MIX_A) | ||
452 | temp |= SICFR_MPSA; | ||
453 | if (flags & IPIC_SPREADMODE_MIX_B) | ||
454 | temp |= SICFR_MPSB; | ||
455 | |||
456 | ipic_write(primary_ipic->regs, IPIC_SICNR, temp); | ||
457 | |||
458 | /* handle MCP route */ | ||
459 | temp = 0; | ||
460 | if (flags & IPIC_DISABLE_MCP_OUT) | ||
461 | temp = SERCR_MCPR; | ||
462 | ipic_write(primary_ipic->regs, IPIC_SERCR, temp); | ||
463 | |||
464 | /* handle routing of IRQ0 to MCP */ | ||
465 | temp = ipic_read(primary_ipic->regs, IPIC_SEMSR); | ||
466 | |||
467 | if (flags & IPIC_IRQ0_MCP) | ||
468 | temp |= SEMSR_SIRQ0; | ||
469 | else | ||
470 | temp &= ~SEMSR_SIRQ0; | ||
471 | |||
472 | ipic_write(primary_ipic->regs, IPIC_SEMSR, temp); | ||
473 | |||
474 | for (i = 0 ; i < NR_IPIC_INTS ; i++) { | ||
475 | irq_desc[i+irq_offset].chip = &ipic; | ||
476 | irq_desc[i+irq_offset].status = IRQ_LEVEL; | ||
477 | } | ||
478 | |||
479 | temp = 0; | ||
480 | for (i = 0 ; i < senses_count ; i++) { | ||
481 | if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) { | ||
482 | temp |= 1 << (15 - i); | ||
483 | if (i != 0) | ||
484 | irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0; | ||
485 | else | ||
486 | irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0; | ||
487 | } | ||
488 | } | ||
489 | ipic_write(primary_ipic->regs, IPIC_SECNR, temp); | ||
490 | |||
491 | printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS, | ||
492 | senses_count, primary_ipic->regs); | ||
493 | } | ||
494 | |||
495 | int ipic_set_priority(unsigned int irq, unsigned int priority) | ||
496 | { | ||
497 | struct ipic *ipic = ipic_from_irq(irq); | ||
498 | unsigned int src = irq - ipic->irq_offset; | ||
499 | u32 temp; | ||
500 | |||
501 | if (priority > 7) | ||
502 | return -EINVAL; | ||
503 | if (src > 127) | ||
504 | return -EINVAL; | ||
505 | if (ipic_info[src].prio == 0) | ||
506 | return -EINVAL; | ||
507 | |||
508 | temp = ipic_read(ipic->regs, ipic_info[src].prio); | ||
509 | |||
510 | if (priority < 4) { | ||
511 | temp &= ~(0x7 << (20 + (3 - priority) * 3)); | ||
512 | temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3); | ||
513 | } else { | ||
514 | temp &= ~(0x7 << (4 + (7 - priority) * 3)); | ||
515 | temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3); | ||
516 | } | ||
517 | |||
518 | ipic_write(ipic->regs, ipic_info[src].prio, temp); | ||
519 | |||
520 | return 0; | ||
521 | } | ||
522 | |||
523 | void ipic_set_highest_priority(unsigned int irq) | ||
524 | { | ||
525 | struct ipic *ipic = ipic_from_irq(irq); | ||
526 | unsigned int src = irq - ipic->irq_offset; | ||
527 | u32 temp; | ||
528 | |||
529 | temp = ipic_read(ipic->regs, IPIC_SICFR); | ||
530 | |||
531 | /* clear and set HPI */ | ||
532 | temp &= 0x7f000000; | ||
533 | temp |= (src & 0x7f) << 24; | ||
534 | |||
535 | ipic_write(ipic->regs, IPIC_SICFR, temp); | ||
536 | } | ||
537 | |||
538 | void ipic_set_default_priority(void) | ||
539 | { | ||
540 | ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0); | ||
541 | ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1); | ||
542 | ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2); | ||
543 | ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3); | ||
544 | ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4); | ||
545 | ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5); | ||
546 | ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6); | ||
547 | ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7); | ||
548 | |||
549 | ipic_set_priority(MPC83xx_IRQ_UART1, 0); | ||
550 | ipic_set_priority(MPC83xx_IRQ_UART2, 1); | ||
551 | ipic_set_priority(MPC83xx_IRQ_SEC2, 2); | ||
552 | ipic_set_priority(MPC83xx_IRQ_IIC1, 5); | ||
553 | ipic_set_priority(MPC83xx_IRQ_IIC2, 6); | ||
554 | ipic_set_priority(MPC83xx_IRQ_SPI, 7); | ||
555 | ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0); | ||
556 | ipic_set_priority(MPC83xx_IRQ_PIT, 1); | ||
557 | ipic_set_priority(MPC83xx_IRQ_PCI1, 2); | ||
558 | ipic_set_priority(MPC83xx_IRQ_PCI2, 3); | ||
559 | ipic_set_priority(MPC83xx_IRQ_EXT0, 4); | ||
560 | ipic_set_priority(MPC83xx_IRQ_EXT1, 5); | ||
561 | ipic_set_priority(MPC83xx_IRQ_EXT2, 6); | ||
562 | ipic_set_priority(MPC83xx_IRQ_EXT3, 7); | ||
563 | ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0); | ||
564 | ipic_set_priority(MPC83xx_IRQ_MU, 1); | ||
565 | ipic_set_priority(MPC83xx_IRQ_SBA, 2); | ||
566 | ipic_set_priority(MPC83xx_IRQ_DMA, 3); | ||
567 | ipic_set_priority(MPC83xx_IRQ_EXT4, 4); | ||
568 | ipic_set_priority(MPC83xx_IRQ_EXT5, 5); | ||
569 | ipic_set_priority(MPC83xx_IRQ_EXT6, 6); | ||
570 | ipic_set_priority(MPC83xx_IRQ_EXT7, 7); | ||
571 | } | ||
572 | |||
573 | void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq) | ||
574 | { | ||
575 | struct ipic *ipic = primary_ipic; | ||
576 | u32 temp; | ||
577 | |||
578 | temp = ipic_read(ipic->regs, IPIC_SERMR); | ||
579 | temp |= (1 << (31 - mcp_irq)); | ||
580 | ipic_write(ipic->regs, IPIC_SERMR, temp); | ||
581 | } | ||
582 | |||
583 | void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq) | ||
584 | { | ||
585 | struct ipic *ipic = primary_ipic; | ||
586 | u32 temp; | ||
587 | |||
588 | temp = ipic_read(ipic->regs, IPIC_SERMR); | ||
589 | temp &= (1 << (31 - mcp_irq)); | ||
590 | ipic_write(ipic->regs, IPIC_SERMR, temp); | ||
591 | } | ||
592 | |||
593 | u32 ipic_get_mcp_status(void) | ||
594 | { | ||
595 | return ipic_read(primary_ipic->regs, IPIC_SERMR); | ||
596 | } | ||
597 | |||
598 | void ipic_clear_mcp_status(u32 mask) | ||
599 | { | ||
600 | ipic_write(primary_ipic->regs, IPIC_SERMR, mask); | ||
601 | } | ||
602 | |||
603 | /* Return an interrupt vector or -1 if no interrupt is pending. */ | ||
604 | int ipic_get_irq(void) | ||
605 | { | ||
606 | int irq; | ||
607 | |||
608 | irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f; | ||
609 | |||
610 | if (irq == 0) /* 0 --> no irq is pending */ | ||
611 | irq = -1; | ||
612 | |||
613 | return irq; | ||
614 | } | ||
615 | |||
616 | static struct sysdev_class ipic_sysclass = { | ||
617 | set_kset_name("ipic"), | ||
618 | }; | ||
619 | |||
620 | static struct sys_device device_ipic = { | ||
621 | .id = 0, | ||
622 | .cls = &ipic_sysclass, | ||
623 | }; | ||
624 | |||
625 | static int __init init_ipic_sysfs(void) | ||
626 | { | ||
627 | int rc; | ||
628 | |||
629 | if (!primary_ipic->regs) | ||
630 | return -ENODEV; | ||
631 | printk(KERN_DEBUG "Registering ipic with sysfs...\n"); | ||
632 | |||
633 | rc = sysdev_class_register(&ipic_sysclass); | ||
634 | if (rc) { | ||
635 | printk(KERN_ERR "Failed registering ipic sys class\n"); | ||
636 | return -ENODEV; | ||
637 | } | ||
638 | rc = sysdev_register(&device_ipic); | ||
639 | if (rc) { | ||
640 | printk(KERN_ERR "Failed registering ipic sys device\n"); | ||
641 | return -ENODEV; | ||
642 | } | ||
643 | return 0; | ||
644 | } | ||
645 | |||
646 | subsys_initcall(init_ipic_sysfs); | ||
diff --git a/arch/ppc/syslib/ipic.h b/arch/ppc/syslib/ipic.h deleted file mode 100644 index a60c9d18bb7f..000000000000 --- a/arch/ppc/syslib/ipic.h +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | /* | ||
2 | * IPIC private definitions and structure. | ||
3 | * | ||
4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | ||
5 | * | ||
6 | * Copyright 2005 Freescale Semiconductor, Inc | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | */ | ||
13 | #ifndef __IPIC_H__ | ||
14 | #define __IPIC_H__ | ||
15 | |||
16 | #include <asm/ipic.h> | ||
17 | |||
18 | #define MPC83xx_IPIC_SIZE (0x00100) | ||
19 | |||
20 | /* System Global Interrupt Configuration Register */ | ||
21 | #define SICFR_IPSA 0x00010000 | ||
22 | #define SICFR_IPSD 0x00080000 | ||
23 | #define SICFR_MPSA 0x00200000 | ||
24 | #define SICFR_MPSB 0x00400000 | ||
25 | |||
26 | /* System External Interrupt Mask Register */ | ||
27 | #define SEMSR_SIRQ0 0x00008000 | ||
28 | |||
29 | /* System Error Control Register */ | ||
30 | #define SERCR_MCPR 0x00000001 | ||
31 | |||
32 | struct ipic { | ||
33 | volatile u32 __iomem *regs; | ||
34 | unsigned int irq_offset; | ||
35 | }; | ||
36 | |||
37 | struct ipic_info { | ||
38 | u8 pend; /* pending register offset from base */ | ||
39 | u8 mask; /* mask register offset from base */ | ||
40 | u8 prio; /* priority register offset from base */ | ||
41 | u8 force; /* force register offset from base */ | ||
42 | u8 bit; /* register bit position (as per doc) | ||
43 | bit mask = 1 << (31 - bit) */ | ||
44 | u8 prio_mask; /* priority mask value */ | ||
45 | }; | ||
46 | |||
47 | #endif /* __IPIC_H__ */ | ||
diff --git a/arch/ppc/syslib/mpc83xx_devices.c b/arch/ppc/syslib/mpc83xx_devices.c deleted file mode 100644 index 5c4932ca8e9b..000000000000 --- a/arch/ppc/syslib/mpc83xx_devices.c +++ /dev/null | |||
@@ -1,251 +0,0 @@ | |||
1 | /* | ||
2 | * MPC83xx Device descriptions | ||
3 | * | ||
4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | ||
5 | * | ||
6 | * Copyright 2005 Freescale Semiconductor Inc. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/device.h> | ||
17 | #include <linux/serial_8250.h> | ||
18 | #include <linux/fsl_devices.h> | ||
19 | #include <asm/mpc83xx.h> | ||
20 | #include <asm/irq.h> | ||
21 | #include <asm/ppc_sys.h> | ||
22 | #include <asm/machdep.h> | ||
23 | |||
24 | /* We use offsets for IORESOURCE_MEM since we do not know at compile time | ||
25 | * what IMMRBAR is, will get fixed up by mach_mpc83xx_fixup | ||
26 | */ | ||
27 | |||
28 | struct gianfar_mdio_data mpc83xx_mdio_pdata = { | ||
29 | }; | ||
30 | |||
31 | static struct gianfar_platform_data mpc83xx_tsec1_pdata = { | ||
32 | .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | | ||
33 | FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | | ||
34 | FSL_GIANFAR_DEV_HAS_MULTI_INTR, | ||
35 | }; | ||
36 | |||
37 | static struct gianfar_platform_data mpc83xx_tsec2_pdata = { | ||
38 | .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | | ||
39 | FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON | | ||
40 | FSL_GIANFAR_DEV_HAS_MULTI_INTR, | ||
41 | }; | ||
42 | |||
43 | static struct fsl_i2c_platform_data mpc83xx_fsl_i2c1_pdata = { | ||
44 | .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, | ||
45 | }; | ||
46 | |||
47 | static struct fsl_i2c_platform_data mpc83xx_fsl_i2c2_pdata = { | ||
48 | .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR, | ||
49 | }; | ||
50 | |||
51 | static struct plat_serial8250_port serial_platform_data[] = { | ||
52 | [0] = { | ||
53 | .mapbase = 0x4500, | ||
54 | .irq = MPC83xx_IRQ_UART1, | ||
55 | .iotype = UPIO_MEM, | ||
56 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
57 | }, | ||
58 | [1] = { | ||
59 | .mapbase = 0x4600, | ||
60 | .irq = MPC83xx_IRQ_UART2, | ||
61 | .iotype = UPIO_MEM, | ||
62 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | ||
63 | }, | ||
64 | { }, | ||
65 | }; | ||
66 | |||
67 | struct platform_device ppc_sys_platform_devices[] = { | ||
68 | [MPC83xx_TSEC1] = { | ||
69 | .name = "fsl-gianfar", | ||
70 | .id = 1, | ||
71 | .dev.platform_data = &mpc83xx_tsec1_pdata, | ||
72 | .num_resources = 4, | ||
73 | .resource = (struct resource[]) { | ||
74 | { | ||
75 | .start = 0x24000, | ||
76 | .end = 0x24fff, | ||
77 | .flags = IORESOURCE_MEM, | ||
78 | }, | ||
79 | { | ||
80 | .name = "tx", | ||
81 | .start = MPC83xx_IRQ_TSEC1_TX, | ||
82 | .end = MPC83xx_IRQ_TSEC1_TX, | ||
83 | .flags = IORESOURCE_IRQ, | ||
84 | }, | ||
85 | { | ||
86 | .name = "rx", | ||
87 | .start = MPC83xx_IRQ_TSEC1_RX, | ||
88 | .end = MPC83xx_IRQ_TSEC1_RX, | ||
89 | .flags = IORESOURCE_IRQ, | ||
90 | }, | ||
91 | { | ||
92 | .name = "error", | ||
93 | .start = MPC83xx_IRQ_TSEC1_ERROR, | ||
94 | .end = MPC83xx_IRQ_TSEC1_ERROR, | ||
95 | .flags = IORESOURCE_IRQ, | ||
96 | }, | ||
97 | }, | ||
98 | }, | ||
99 | [MPC83xx_TSEC2] = { | ||
100 | .name = "fsl-gianfar", | ||
101 | .id = 2, | ||
102 | .dev.platform_data = &mpc83xx_tsec2_pdata, | ||
103 | .num_resources = 4, | ||
104 | .resource = (struct resource[]) { | ||
105 | { | ||
106 | .start = 0x25000, | ||
107 | .end = 0x25fff, | ||
108 | .flags = IORESOURCE_MEM, | ||
109 | }, | ||
110 | { | ||
111 | .name = "tx", | ||
112 | .start = MPC83xx_IRQ_TSEC2_TX, | ||
113 | .end = MPC83xx_IRQ_TSEC2_TX, | ||
114 | .flags = IORESOURCE_IRQ, | ||
115 | }, | ||
116 | { | ||
117 | .name = "rx", | ||
118 | .start = MPC83xx_IRQ_TSEC2_RX, | ||
119 | .end = MPC83xx_IRQ_TSEC2_RX, | ||
120 | .flags = IORESOURCE_IRQ, | ||
121 | }, | ||
122 | { | ||
123 | .name = "error", | ||
124 | .start = MPC83xx_IRQ_TSEC2_ERROR, | ||
125 | .end = MPC83xx_IRQ_TSEC2_ERROR, | ||
126 | .flags = IORESOURCE_IRQ, | ||
127 | }, | ||
128 | }, | ||
129 | }, | ||
130 | [MPC83xx_IIC1] = { | ||
131 | .name = "fsl-i2c", | ||
132 | .id = 1, | ||
133 | .dev.platform_data = &mpc83xx_fsl_i2c1_pdata, | ||
134 | .num_resources = 2, | ||
135 | .resource = (struct resource[]) { | ||
136 | { | ||
137 | .start = 0x3000, | ||
138 | .end = 0x30ff, | ||
139 | .flags = IORESOURCE_MEM, | ||
140 | }, | ||
141 | { | ||
142 | .start = MPC83xx_IRQ_IIC1, | ||
143 | .end = MPC83xx_IRQ_IIC1, | ||
144 | .flags = IORESOURCE_IRQ, | ||
145 | }, | ||
146 | }, | ||
147 | }, | ||
148 | [MPC83xx_IIC2] = { | ||
149 | .name = "fsl-i2c", | ||
150 | .id = 2, | ||
151 | .dev.platform_data = &mpc83xx_fsl_i2c2_pdata, | ||
152 | .num_resources = 2, | ||
153 | .resource = (struct resource[]) { | ||
154 | { | ||
155 | .start = 0x3100, | ||
156 | .end = 0x31ff, | ||
157 | .flags = IORESOURCE_MEM, | ||
158 | }, | ||
159 | { | ||
160 | .start = MPC83xx_IRQ_IIC2, | ||
161 | .end = MPC83xx_IRQ_IIC2, | ||
162 | .flags = IORESOURCE_IRQ, | ||
163 | }, | ||
164 | }, | ||
165 | }, | ||
166 | [MPC83xx_DUART] = { | ||
167 | .name = "serial8250", | ||
168 | .id = PLAT8250_DEV_PLATFORM, | ||
169 | .dev.platform_data = serial_platform_data, | ||
170 | }, | ||
171 | [MPC83xx_SEC2] = { | ||
172 | .name = "fsl-sec2", | ||
173 | .id = 1, | ||
174 | .num_resources = 2, | ||
175 | .resource = (struct resource[]) { | ||
176 | { | ||
177 | .start = 0x30000, | ||
178 | .end = 0x3ffff, | ||
179 | .flags = IORESOURCE_MEM, | ||
180 | }, | ||
181 | { | ||
182 | .start = MPC83xx_IRQ_SEC2, | ||
183 | .end = MPC83xx_IRQ_SEC2, | ||
184 | .flags = IORESOURCE_IRQ, | ||
185 | }, | ||
186 | }, | ||
187 | }, | ||
188 | [MPC83xx_USB2_DR] = { | ||
189 | .name = "fsl-ehci", | ||
190 | .id = 1, | ||
191 | .num_resources = 2, | ||
192 | .resource = (struct resource[]) { | ||
193 | { | ||
194 | .start = 0x23000, | ||
195 | .end = 0x23fff, | ||
196 | .flags = IORESOURCE_MEM, | ||
197 | }, | ||
198 | { | ||
199 | .start = MPC83xx_IRQ_USB2_DR, | ||
200 | .end = MPC83xx_IRQ_USB2_DR, | ||
201 | .flags = IORESOURCE_IRQ, | ||
202 | }, | ||
203 | }, | ||
204 | }, | ||
205 | [MPC83xx_USB2_MPH] = { | ||
206 | .name = "fsl-ehci", | ||
207 | .id = 2, | ||
208 | .num_resources = 2, | ||
209 | .resource = (struct resource[]) { | ||
210 | { | ||
211 | .start = 0x22000, | ||
212 | .end = 0x22fff, | ||
213 | .flags = IORESOURCE_MEM, | ||
214 | }, | ||
215 | { | ||
216 | .start = MPC83xx_IRQ_USB2_MPH, | ||
217 | .end = MPC83xx_IRQ_USB2_MPH, | ||
218 | .flags = IORESOURCE_IRQ, | ||
219 | }, | ||
220 | }, | ||
221 | }, | ||
222 | [MPC83xx_MDIO] = { | ||
223 | .name = "fsl-gianfar_mdio", | ||
224 | .id = 0, | ||
225 | .dev.platform_data = &mpc83xx_mdio_pdata, | ||
226 | .num_resources = 1, | ||
227 | .resource = (struct resource[]) { | ||
228 | { | ||
229 | .start = 0x24520, | ||
230 | .end = 0x2453f, | ||
231 | .flags = IORESOURCE_MEM, | ||
232 | }, | ||
233 | }, | ||
234 | }, | ||
235 | }; | ||
236 | |||
237 | static int __init mach_mpc83xx_fixup(struct platform_device *pdev) | ||
238 | { | ||
239 | ppc_sys_fixup_mem_resource(pdev, immrbar); | ||
240 | return 0; | ||
241 | } | ||
242 | |||
243 | static int __init mach_mpc83xx_init(void) | ||
244 | { | ||
245 | if (ppc_md.progress) | ||
246 | ppc_md.progress("mach_mpc83xx_init:enter", 0); | ||
247 | ppc_sys_device_fixup = mach_mpc83xx_fixup; | ||
248 | return 0; | ||
249 | } | ||
250 | |||
251 | postcore_initcall(mach_mpc83xx_init); | ||
diff --git a/arch/ppc/syslib/mpc83xx_sys.c b/arch/ppc/syslib/mpc83xx_sys.c deleted file mode 100644 index 0498ae7e01e3..000000000000 --- a/arch/ppc/syslib/mpc83xx_sys.c +++ /dev/null | |||
@@ -1,122 +0,0 @@ | |||
1 | /* | ||
2 | * MPC83xx System descriptions | ||
3 | * | ||
4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | ||
5 | * | ||
6 | * Copyright 2005 Freescale Semiconductor Inc. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/device.h> | ||
17 | #include <asm/ppc_sys.h> | ||
18 | |||
19 | struct ppc_sys_spec *cur_ppc_sys_spec; | ||
20 | struct ppc_sys_spec ppc_sys_specs[] = { | ||
21 | { | ||
22 | .ppc_sys_name = "8349E", | ||
23 | .mask = 0xFFFF0000, | ||
24 | .value = 0x80500000, | ||
25 | .num_devices = 9, | ||
26 | .device_list = (enum ppc_sys_devices[]) | ||
27 | { | ||
28 | MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, | ||
29 | MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, | ||
30 | MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO | ||
31 | }, | ||
32 | }, | ||
33 | { | ||
34 | .ppc_sys_name = "8349", | ||
35 | .mask = 0xFFFF0000, | ||
36 | .value = 0x80510000, | ||
37 | .num_devices = 8, | ||
38 | .device_list = (enum ppc_sys_devices[]) | ||
39 | { | ||
40 | MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, | ||
41 | MPC83xx_IIC2, MPC83xx_DUART, | ||
42 | MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO | ||
43 | }, | ||
44 | }, | ||
45 | { | ||
46 | .ppc_sys_name = "8347E", | ||
47 | .mask = 0xFFFF0000, | ||
48 | .value = 0x80520000, | ||
49 | .num_devices = 9, | ||
50 | .device_list = (enum ppc_sys_devices[]) | ||
51 | { | ||
52 | MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, | ||
53 | MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, | ||
54 | MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO | ||
55 | }, | ||
56 | }, | ||
57 | { | ||
58 | .ppc_sys_name = "8347", | ||
59 | .mask = 0xFFFF0000, | ||
60 | .value = 0x80530000, | ||
61 | .num_devices = 8, | ||
62 | .device_list = (enum ppc_sys_devices[]) | ||
63 | { | ||
64 | MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, | ||
65 | MPC83xx_IIC2, MPC83xx_DUART, | ||
66 | MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO | ||
67 | }, | ||
68 | }, | ||
69 | { | ||
70 | .ppc_sys_name = "8347E", | ||
71 | .mask = 0xFFFF0000, | ||
72 | .value = 0x80540000, | ||
73 | .num_devices = 9, | ||
74 | .device_list = (enum ppc_sys_devices[]) | ||
75 | { | ||
76 | MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, | ||
77 | MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, | ||
78 | MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO | ||
79 | }, | ||
80 | }, | ||
81 | { | ||
82 | .ppc_sys_name = "8347", | ||
83 | .mask = 0xFFFF0000, | ||
84 | .value = 0x80550000, | ||
85 | .num_devices = 8, | ||
86 | .device_list = (enum ppc_sys_devices[]) | ||
87 | { | ||
88 | MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, | ||
89 | MPC83xx_IIC2, MPC83xx_DUART, | ||
90 | MPC83xx_USB2_DR, MPC83xx_USB2_MPH, MPC83xx_MDIO | ||
91 | }, | ||
92 | }, | ||
93 | { | ||
94 | .ppc_sys_name = "8343E", | ||
95 | .mask = 0xFFFF0000, | ||
96 | .value = 0x80560000, | ||
97 | .num_devices = 8, | ||
98 | .device_list = (enum ppc_sys_devices[]) | ||
99 | { | ||
100 | MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, | ||
101 | MPC83xx_IIC2, MPC83xx_DUART, MPC83xx_SEC2, | ||
102 | MPC83xx_USB2_DR, MPC83xx_MDIO | ||
103 | }, | ||
104 | }, | ||
105 | { | ||
106 | .ppc_sys_name = "8343", | ||
107 | .mask = 0xFFFF0000, | ||
108 | .value = 0x80570000, | ||
109 | .num_devices = 7, | ||
110 | .device_list = (enum ppc_sys_devices[]) | ||
111 | { | ||
112 | MPC83xx_TSEC1, MPC83xx_TSEC2, MPC83xx_IIC1, | ||
113 | MPC83xx_IIC2, MPC83xx_DUART, | ||
114 | MPC83xx_USB2_DR, MPC83xx_MDIO | ||
115 | }, | ||
116 | }, | ||
117 | { /* default match */ | ||
118 | .ppc_sys_name = "", | ||
119 | .mask = 0x00000000, | ||
120 | .value = 0x00000000, | ||
121 | }, | ||
122 | }; | ||
diff --git a/arch/ppc/syslib/ppc83xx_pci.h b/arch/ppc/syslib/ppc83xx_pci.h deleted file mode 100644 index ec691640f6be..000000000000 --- a/arch/ppc/syslib/ppc83xx_pci.h +++ /dev/null | |||
@@ -1,151 +0,0 @@ | |||
1 | /* Created by Tony Li <tony.li@freescale.com> | ||
2 | * Copyright (c) 2005 freescale semiconductor | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms of the GNU General Public License as published by the | ||
6 | * Free Software Foundation; either version 2 of the License, or (at your | ||
7 | * option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but | ||
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
12 | * General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along | ||
15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
16 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
17 | */ | ||
18 | |||
19 | #ifndef __PPC_SYSLIB_PPC83XX_PCI_H | ||
20 | #define __PPC_SYSLIB_PPC83XX_PCI_H | ||
21 | |||
22 | typedef struct immr_clk { | ||
23 | u32 spmr; /* system PLL mode Register */ | ||
24 | u32 occr; /* output clock control Register */ | ||
25 | u32 sccr; /* system clock control Register */ | ||
26 | u8 res0[0xF4]; | ||
27 | } immr_clk_t; | ||
28 | |||
29 | /* | ||
30 | * Sequencer | ||
31 | */ | ||
32 | typedef struct immr_ios { | ||
33 | u32 potar0; | ||
34 | u8 res0[4]; | ||
35 | u32 pobar0; | ||
36 | u8 res1[4]; | ||
37 | u32 pocmr0; | ||
38 | u8 res2[4]; | ||
39 | u32 potar1; | ||
40 | u8 res3[4]; | ||
41 | u32 pobar1; | ||
42 | u8 res4[4]; | ||
43 | u32 pocmr1; | ||
44 | u8 res5[4]; | ||
45 | u32 potar2; | ||
46 | u8 res6[4]; | ||
47 | u32 pobar2; | ||
48 | u8 res7[4]; | ||
49 | u32 pocmr2; | ||
50 | u8 res8[4]; | ||
51 | u32 potar3; | ||
52 | u8 res9[4]; | ||
53 | u32 pobar3; | ||
54 | u8 res10[4]; | ||
55 | u32 pocmr3; | ||
56 | u8 res11[4]; | ||
57 | u32 potar4; | ||
58 | u8 res12[4]; | ||
59 | u32 pobar4; | ||
60 | u8 res13[4]; | ||
61 | u32 pocmr4; | ||
62 | u8 res14[4]; | ||
63 | u32 potar5; | ||
64 | u8 res15[4]; | ||
65 | u32 pobar5; | ||
66 | u8 res16[4]; | ||
67 | u32 pocmr5; | ||
68 | u8 res17[4]; | ||
69 | u8 res18[0x60]; | ||
70 | u32 pmcr; | ||
71 | u8 res19[4]; | ||
72 | u32 dtcr; | ||
73 | u8 res20[4]; | ||
74 | } immr_ios_t; | ||
75 | #define POTAR_TA_MASK 0x000fffff | ||
76 | #define POBAR_BA_MASK 0x000fffff | ||
77 | #define POCMR_EN 0x80000000 | ||
78 | #define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ | ||
79 | #define POCMR_SE 0x20000000 /* streaming enable */ | ||
80 | #define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2 */ | ||
81 | #define POCMR_CM_MASK 0x000fffff | ||
82 | |||
83 | /* | ||
84 | * PCI Controller Control and Status Registers | ||
85 | */ | ||
86 | typedef struct immr_pcictrl { | ||
87 | u32 esr; | ||
88 | u32 ecdr; | ||
89 | u32 eer; | ||
90 | u32 eatcr; | ||
91 | u32 eacr; | ||
92 | u32 eeacr; | ||
93 | u32 edlcr; | ||
94 | u32 edhcr; | ||
95 | u32 gcr; | ||
96 | u32 ecr; | ||
97 | u32 gsr; | ||
98 | u8 res0[12]; | ||
99 | u32 pitar2; | ||
100 | u8 res1[4]; | ||
101 | u32 pibar2; | ||
102 | u32 piebar2; | ||
103 | u32 piwar2; | ||
104 | u8 res2[4]; | ||
105 | u32 pitar1; | ||
106 | u8 res3[4]; | ||
107 | u32 pibar1; | ||
108 | u32 piebar1; | ||
109 | u32 piwar1; | ||
110 | u8 res4[4]; | ||
111 | u32 pitar0; | ||
112 | u8 res5[4]; | ||
113 | u32 pibar0; | ||
114 | u8 res6[4]; | ||
115 | u32 piwar0; | ||
116 | u8 res7[132]; | ||
117 | } immr_pcictrl_t; | ||
118 | #define PITAR_TA_MASK 0x000fffff | ||
119 | #define PIBAR_MASK 0xffffffff | ||
120 | #define PIEBAR_EBA_MASK 0x000fffff | ||
121 | #define PIWAR_EN 0x80000000 | ||
122 | #define PIWAR_PF 0x20000000 | ||
123 | #define PIWAR_RTT_MASK 0x000f0000 | ||
124 | #define PIWAR_RTT_NO_SNOOP 0x00040000 | ||
125 | #define PIWAR_RTT_SNOOP 0x00050000 | ||
126 | #define PIWAR_WTT_MASK 0x0000f000 | ||
127 | #define PIWAR_WTT_NO_SNOOP 0x00004000 | ||
128 | #define PIWAR_WTT_SNOOP 0x00005000 | ||
129 | #define PIWAR_IWS_MASK 0x0000003F | ||
130 | #define PIWAR_IWS_4K 0x0000000B | ||
131 | #define PIWAR_IWS_8K 0x0000000C | ||
132 | #define PIWAR_IWS_16K 0x0000000D | ||
133 | #define PIWAR_IWS_32K 0x0000000E | ||
134 | #define PIWAR_IWS_64K 0x0000000F | ||
135 | #define PIWAR_IWS_128K 0x00000010 | ||
136 | #define PIWAR_IWS_256K 0x00000011 | ||
137 | #define PIWAR_IWS_512K 0x00000012 | ||
138 | #define PIWAR_IWS_1M 0x00000013 | ||
139 | #define PIWAR_IWS_2M 0x00000014 | ||
140 | #define PIWAR_IWS_4M 0x00000015 | ||
141 | #define PIWAR_IWS_8M 0x00000016 | ||
142 | #define PIWAR_IWS_16M 0x00000017 | ||
143 | #define PIWAR_IWS_32M 0x00000018 | ||
144 | #define PIWAR_IWS_64M 0x00000019 | ||
145 | #define PIWAR_IWS_128M 0x0000001A | ||
146 | #define PIWAR_IWS_256M 0x0000001B | ||
147 | #define PIWAR_IWS_512M 0x0000001C | ||
148 | #define PIWAR_IWS_1G 0x0000001D | ||
149 | #define PIWAR_IWS_2G 0x0000001E | ||
150 | |||
151 | #endif /* __PPC_SYSLIB_PPC83XX_PCI_H */ | ||
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c deleted file mode 100644 index ea372914dd6e..000000000000 --- a/arch/ppc/syslib/ppc83xx_setup.c +++ /dev/null | |||
@@ -1,410 +0,0 @@ | |||
1 | /* | ||
2 | * MPC83XX common board code | ||
3 | * | ||
4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | ||
5 | * | ||
6 | * Copyright 2005 Freescale Semiconductor Inc. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, but | ||
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
16 | * General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along | ||
19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
20 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
21 | * | ||
22 | * Added PCI support -- Tony Li <tony.li@freescale.com> | ||
23 | */ | ||
24 | |||
25 | #include <linux/types.h> | ||
26 | #include <linux/module.h> | ||
27 | #include <linux/init.h> | ||
28 | #include <linux/pci.h> | ||
29 | #include <linux/serial.h> | ||
30 | #include <linux/tty.h> /* for linux/serial_core.h */ | ||
31 | #include <linux/serial_core.h> | ||
32 | #include <linux/serial_8250.h> | ||
33 | |||
34 | #include <asm/time.h> | ||
35 | #include <asm/mpc83xx.h> | ||
36 | #include <asm/mmu.h> | ||
37 | #include <asm/ppc_sys.h> | ||
38 | #include <asm/kgdb.h> | ||
39 | #include <asm/delay.h> | ||
40 | #include <asm/machdep.h> | ||
41 | |||
42 | #include <syslib/ppc83xx_setup.h> | ||
43 | #if defined(CONFIG_PCI) | ||
44 | #include <syslib/ppc83xx_pci.h> | ||
45 | #endif | ||
46 | |||
47 | phys_addr_t immrbar; | ||
48 | |||
49 | /* Return the amount of memory */ | ||
50 | unsigned long __init | ||
51 | mpc83xx_find_end_of_memory(void) | ||
52 | { | ||
53 | bd_t *binfo; | ||
54 | |||
55 | binfo = (bd_t *) __res; | ||
56 | |||
57 | return binfo->bi_memsize; | ||
58 | } | ||
59 | |||
60 | long __init | ||
61 | mpc83xx_time_init(void) | ||
62 | { | ||
63 | #define SPCR_OFFS 0x00000110 | ||
64 | #define SPCR_TBEN 0x00400000 | ||
65 | |||
66 | bd_t *binfo = (bd_t *)__res; | ||
67 | u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4); | ||
68 | |||
69 | *spcr |= SPCR_TBEN; | ||
70 | |||
71 | iounmap(spcr); | ||
72 | |||
73 | return 0; | ||
74 | } | ||
75 | |||
76 | /* The decrementer counts at the system (internal) clock freq divided by 4 */ | ||
77 | void __init | ||
78 | mpc83xx_calibrate_decr(void) | ||
79 | { | ||
80 | bd_t *binfo = (bd_t *) __res; | ||
81 | unsigned int freq, divisor; | ||
82 | |||
83 | freq = binfo->bi_busfreq; | ||
84 | divisor = 4; | ||
85 | tb_ticks_per_jiffy = freq / HZ / divisor; | ||
86 | tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); | ||
87 | } | ||
88 | |||
89 | #ifdef CONFIG_SERIAL_8250 | ||
90 | void __init | ||
91 | mpc83xx_early_serial_map(void) | ||
92 | { | ||
93 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) | ||
94 | struct uart_port serial_req; | ||
95 | #endif | ||
96 | struct plat_serial8250_port *pdata; | ||
97 | bd_t *binfo = (bd_t *) __res; | ||
98 | pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART); | ||
99 | |||
100 | /* Setup serial port access */ | ||
101 | pdata[0].uartclk = binfo->bi_busfreq; | ||
102 | pdata[0].mapbase += binfo->bi_immr_base; | ||
103 | pdata[0].membase = ioremap(pdata[0].mapbase, 0x100); | ||
104 | |||
105 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) | ||
106 | memset(&serial_req, 0, sizeof (serial_req)); | ||
107 | serial_req.iotype = UPIO_MEM; | ||
108 | serial_req.mapbase = pdata[0].mapbase; | ||
109 | serial_req.membase = pdata[0].membase; | ||
110 | serial_req.regshift = 0; | ||
111 | |||
112 | gen550_init(0, &serial_req); | ||
113 | #endif | ||
114 | |||
115 | pdata[1].uartclk = binfo->bi_busfreq; | ||
116 | pdata[1].mapbase += binfo->bi_immr_base; | ||
117 | pdata[1].membase = ioremap(pdata[1].mapbase, 0x100); | ||
118 | |||
119 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) | ||
120 | /* Assume gen550_init() doesn't modify serial_req */ | ||
121 | serial_req.mapbase = pdata[1].mapbase; | ||
122 | serial_req.membase = pdata[1].membase; | ||
123 | |||
124 | gen550_init(1, &serial_req); | ||
125 | #endif | ||
126 | } | ||
127 | #endif | ||
128 | |||
129 | void | ||
130 | mpc83xx_restart(char *cmd) | ||
131 | { | ||
132 | volatile unsigned char __iomem *reg; | ||
133 | unsigned char tmp; | ||
134 | |||
135 | reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE); | ||
136 | |||
137 | local_irq_disable(); | ||
138 | |||
139 | /* | ||
140 | * Unlock the BCSR bits so a PRST will update the contents. | ||
141 | * Otherwise the reset asserts but doesn't clear. | ||
142 | */ | ||
143 | tmp = in_8(reg + BCSR_MISC_REG3_OFF); | ||
144 | tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */ | ||
145 | out_8(reg + BCSR_MISC_REG3_OFF, tmp); | ||
146 | |||
147 | /* | ||
148 | * Trigger a reset via a low->high transition of the | ||
149 | * PORESET bit. | ||
150 | */ | ||
151 | tmp = in_8(reg + BCSR_MISC_REG2_OFF); | ||
152 | tmp &= ~BCSR_MISC_REG2_PORESET; | ||
153 | out_8(reg + BCSR_MISC_REG2_OFF, tmp); | ||
154 | |||
155 | udelay(1); | ||
156 | |||
157 | tmp |= BCSR_MISC_REG2_PORESET; | ||
158 | out_8(reg + BCSR_MISC_REG2_OFF, tmp); | ||
159 | |||
160 | for(;;); | ||
161 | } | ||
162 | |||
163 | void | ||
164 | mpc83xx_power_off(void) | ||
165 | { | ||
166 | local_irq_disable(); | ||
167 | for(;;); | ||
168 | } | ||
169 | |||
170 | void | ||
171 | mpc83xx_halt(void) | ||
172 | { | ||
173 | local_irq_disable(); | ||
174 | for(;;); | ||
175 | } | ||
176 | |||
177 | #if defined(CONFIG_PCI) | ||
178 | void __init | ||
179 | mpc83xx_setup_pci1(struct pci_controller *hose) | ||
180 | { | ||
181 | u16 reg16; | ||
182 | volatile immr_pcictrl_t * pci_ctrl; | ||
183 | volatile immr_ios_t * ios; | ||
184 | bd_t *binfo = (bd_t *) __res; | ||
185 | |||
186 | pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t)); | ||
187 | ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); | ||
188 | |||
189 | /* | ||
190 | * Configure PCI Outbound Translation Windows | ||
191 | */ | ||
192 | ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK; | ||
193 | ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK; | ||
194 | ios->pocmr0 = POCMR_EN | | ||
195 | (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM - | ||
196 | MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK); | ||
197 | |||
198 | /* mapped to PCI1 IO space */ | ||
199 | ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK; | ||
200 | ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK; | ||
201 | ios->pocmr1 = POCMR_EN | POCMR_IO | | ||
202 | (((0xffffffff - (MPC83xx_PCI1_UPPER_IO - | ||
203 | MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK); | ||
204 | |||
205 | /* | ||
206 | * Configure PCI Inbound Translation Windows | ||
207 | */ | ||
208 | pci_ctrl->pitar1 = 0x0; | ||
209 | pci_ctrl->pibar1 = 0x0; | ||
210 | pci_ctrl->piebar1 = 0x0; | ||
211 | pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; | ||
212 | |||
213 | /* | ||
214 | * Release PCI RST signal | ||
215 | */ | ||
216 | pci_ctrl->gcr = 0; | ||
217 | udelay(2000); | ||
218 | pci_ctrl->gcr = 1; | ||
219 | udelay(2000); | ||
220 | |||
221 | reg16 = 0xff; | ||
222 | early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); | ||
223 | reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; | ||
224 | early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); | ||
225 | |||
226 | /* | ||
227 | * Clear non-reserved bits in status register. | ||
228 | */ | ||
229 | early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); | ||
230 | early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); | ||
231 | |||
232 | iounmap(pci_ctrl); | ||
233 | iounmap(ios); | ||
234 | } | ||
235 | |||
236 | void __init | ||
237 | mpc83xx_setup_pci2(struct pci_controller *hose) | ||
238 | { | ||
239 | u16 reg16; | ||
240 | volatile immr_pcictrl_t * pci_ctrl; | ||
241 | volatile immr_ios_t * ios; | ||
242 | bd_t *binfo = (bd_t *) __res; | ||
243 | |||
244 | pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t)); | ||
245 | ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t)); | ||
246 | |||
247 | /* | ||
248 | * Configure PCI Outbound Translation Windows | ||
249 | */ | ||
250 | ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK; | ||
251 | ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK; | ||
252 | ios->pocmr3 = POCMR_EN | POCMR_DST | | ||
253 | (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM - | ||
254 | MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK); | ||
255 | |||
256 | /* mapped to PCI2 IO space */ | ||
257 | ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK; | ||
258 | ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK; | ||
259 | ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO | | ||
260 | (((0xffffffff - (MPC83xx_PCI2_UPPER_IO - | ||
261 | MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK); | ||
262 | |||
263 | /* | ||
264 | * Configure PCI Inbound Translation Windows | ||
265 | */ | ||
266 | pci_ctrl->pitar1 = 0x0; | ||
267 | pci_ctrl->pibar1 = 0x0; | ||
268 | pci_ctrl->piebar1 = 0x0; | ||
269 | pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; | ||
270 | |||
271 | /* | ||
272 | * Release PCI RST signal | ||
273 | */ | ||
274 | pci_ctrl->gcr = 0; | ||
275 | udelay(2000); | ||
276 | pci_ctrl->gcr = 1; | ||
277 | udelay(2000); | ||
278 | |||
279 | reg16 = 0xff; | ||
280 | early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16); | ||
281 | reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; | ||
282 | early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16); | ||
283 | |||
284 | /* | ||
285 | * Clear non-reserved bits in status register. | ||
286 | */ | ||
287 | early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff); | ||
288 | early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80); | ||
289 | |||
290 | iounmap(pci_ctrl); | ||
291 | iounmap(ios); | ||
292 | } | ||
293 | |||
294 | /* | ||
295 | * PCI buses can be enabled only if SYS board combinates with PIB | ||
296 | * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses | ||
297 | * and 3 PCI slots, so people must configure the routes between them before | ||
298 | * enable PCI bus. This routes are under the control of PCA9555PW device which | ||
299 | * can be accessed via I2C bus 2 and are configured by firmware. Refer to | ||
300 | * Freescale to get more information about firmware configuration. | ||
301 | */ | ||
302 | |||
303 | extern int mpc83xx_exclude_device(u_char bus, u_char devfn); | ||
304 | extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, | ||
305 | unsigned char pin); | ||
306 | void __init | ||
307 | mpc83xx_setup_hose(void) | ||
308 | { | ||
309 | u32 val32; | ||
310 | volatile immr_clk_t * clk; | ||
311 | struct pci_controller * hose1; | ||
312 | #ifdef CONFIG_MPC83xx_PCI2 | ||
313 | struct pci_controller * hose2; | ||
314 | #endif | ||
315 | bd_t * binfo = (bd_t *)__res; | ||
316 | |||
317 | clk = ioremap(binfo->bi_immr_base + 0xA00, | ||
318 | sizeof(immr_clk_t)); | ||
319 | |||
320 | /* | ||
321 | * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode | ||
322 | */ | ||
323 | val32 = clk->occr; | ||
324 | udelay(2000); | ||
325 | clk->occr = 0xff000000; | ||
326 | udelay(2000); | ||
327 | |||
328 | iounmap(clk); | ||
329 | |||
330 | hose1 = pcibios_alloc_controller(); | ||
331 | if(!hose1) | ||
332 | return; | ||
333 | |||
334 | ppc_md.pci_swizzle = common_swizzle; | ||
335 | ppc_md.pci_map_irq = mpc83xx_map_irq; | ||
336 | |||
337 | hose1->bus_offset = 0; | ||
338 | hose1->first_busno = 0; | ||
339 | hose1->last_busno = 0xff; | ||
340 | |||
341 | setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, | ||
342 | binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); | ||
343 | hose1->set_cfg_type = 1; | ||
344 | |||
345 | mpc83xx_setup_pci1(hose1); | ||
346 | |||
347 | hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET; | ||
348 | hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM; | ||
349 | hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM; | ||
350 | |||
351 | hose1->io_base_phys = MPC83xx_PCI1_IO_BASE; | ||
352 | hose1->io_space.start = MPC83xx_PCI1_LOWER_IO; | ||
353 | hose1->io_space.end = MPC83xx_PCI1_UPPER_IO; | ||
354 | #ifdef CONFIG_MPC83xx_PCI2 | ||
355 | isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, | ||
356 | MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE); | ||
357 | #else | ||
358 | isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, | ||
359 | MPC83xx_PCI1_IO_SIZE); | ||
360 | #endif /* CONFIG_MPC83xx_PCI2 */ | ||
361 | hose1->io_base_virt = (void *)isa_io_base; | ||
362 | /* setup resources */ | ||
363 | pci_init_resource(&hose1->io_resource, | ||
364 | MPC83xx_PCI1_LOWER_IO, | ||
365 | MPC83xx_PCI1_UPPER_IO, | ||
366 | IORESOURCE_IO, "PCI host bridge 1"); | ||
367 | pci_init_resource(&hose1->mem_resources[0], | ||
368 | MPC83xx_PCI1_LOWER_MEM, | ||
369 | MPC83xx_PCI1_UPPER_MEM, | ||
370 | IORESOURCE_MEM, "PCI host bridge 1"); | ||
371 | |||
372 | ppc_md.pci_exclude_device = mpc83xx_exclude_device; | ||
373 | hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); | ||
374 | |||
375 | #ifdef CONFIG_MPC83xx_PCI2 | ||
376 | hose2 = pcibios_alloc_controller(); | ||
377 | if(!hose2) | ||
378 | return; | ||
379 | |||
380 | hose2->bus_offset = hose1->last_busno + 1; | ||
381 | hose2->first_busno = hose1->last_busno + 1; | ||
382 | hose2->last_busno = 0xff; | ||
383 | setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, | ||
384 | binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); | ||
385 | hose2->set_cfg_type = 1; | ||
386 | |||
387 | mpc83xx_setup_pci2(hose2); | ||
388 | |||
389 | hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET; | ||
390 | hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM; | ||
391 | hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM; | ||
392 | |||
393 | hose2->io_base_phys = MPC83xx_PCI2_IO_BASE; | ||
394 | hose2->io_space.start = MPC83xx_PCI2_LOWER_IO; | ||
395 | hose2->io_space.end = MPC83xx_PCI2_UPPER_IO; | ||
396 | hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE); | ||
397 | /* setup resources */ | ||
398 | pci_init_resource(&hose2->io_resource, | ||
399 | MPC83xx_PCI2_LOWER_IO, | ||
400 | MPC83xx_PCI2_UPPER_IO, | ||
401 | IORESOURCE_IO, "PCI host bridge 2"); | ||
402 | pci_init_resource(&hose2->mem_resources[0], | ||
403 | MPC83xx_PCI2_LOWER_MEM, | ||
404 | MPC83xx_PCI2_UPPER_MEM, | ||
405 | IORESOURCE_MEM, "PCI host bridge 2"); | ||
406 | |||
407 | hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); | ||
408 | #endif /* CONFIG_MPC83xx_PCI2 */ | ||
409 | } | ||
410 | #endif /*CONFIG_PCI*/ | ||
diff --git a/arch/ppc/syslib/ppc83xx_setup.h b/arch/ppc/syslib/ppc83xx_setup.h deleted file mode 100644 index b918a2d245ea..000000000000 --- a/arch/ppc/syslib/ppc83xx_setup.h +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | /* | ||
2 | * MPC83XX common board definitions | ||
3 | * | ||
4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | ||
5 | * | ||
6 | * Copyright 2005 Freescale Semiconductor Inc. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License as published by the | ||
10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
11 | * option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, but | ||
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
16 | * General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License along | ||
19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
20 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
21 | */ | ||
22 | |||
23 | #ifndef __PPC_SYSLIB_PPC83XX_SETUP_H | ||
24 | #define __PPC_SYSLIB_PPC83XX_SETUP_H | ||
25 | |||
26 | #include <linux/init.h> | ||
27 | |||
28 | extern unsigned long mpc83xx_find_end_of_memory(void) __init; | ||
29 | extern long mpc83xx_time_init(void) __init; | ||
30 | extern void mpc83xx_calibrate_decr(void) __init; | ||
31 | extern void mpc83xx_early_serial_map(void) __init; | ||
32 | extern void mpc83xx_restart(char *cmd); | ||
33 | extern void mpc83xx_power_off(void); | ||
34 | extern void mpc83xx_halt(void); | ||
35 | extern void mpc83xx_setup_hose(void) __init; | ||
36 | |||
37 | /* PCI config */ | ||
38 | #define PCI1_CFG_ADDR_OFFSET (0x8300) | ||
39 | #define PCI1_CFG_DATA_OFFSET (0x8304) | ||
40 | |||
41 | #define PCI2_CFG_ADDR_OFFSET (0x8380) | ||
42 | #define PCI2_CFG_DATA_OFFSET (0x8384) | ||
43 | |||
44 | /* Serial Config */ | ||
45 | #ifdef CONFIG_SERIAL_MANY_PORTS | ||
46 | #define RS_TABLE_SIZE 64 | ||
47 | #else | ||
48 | #define RS_TABLE_SIZE 2 | ||
49 | #endif | ||
50 | |||
51 | #ifndef BASE_BAUD | ||
52 | #define BASE_BAUD 115200 | ||
53 | #endif | ||
54 | |||
55 | #endif /* __PPC_SYSLIB_PPC83XX_SETUP_H */ | ||
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 1392db456523..4a015da9fb1e 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h | |||
@@ -483,11 +483,6 @@ static __inline__ int irq_canonicalize(int irq) | |||
483 | */ | 483 | */ |
484 | #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) | 484 | #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) |
485 | 485 | ||
486 | #elif defined(CONFIG_83xx) | ||
487 | #include <asm/mpc83xx.h> | ||
488 | |||
489 | #define NR_IRQS (NR_IPIC_INTS) | ||
490 | |||
491 | #elif defined(CONFIG_85xx) | 486 | #elif defined(CONFIG_85xx) |
492 | /* Now include the board configuration specific associations. | 487 | /* Now include the board configuration specific associations. |
493 | */ | 488 | */ |
diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h deleted file mode 100644 index c3061972309b..000000000000 --- a/include/asm-ppc/mpc83xx.h +++ /dev/null | |||
@@ -1,107 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-ppc/mpc83xx.h | ||
3 | * | ||
4 | * MPC83xx definitions | ||
5 | * | ||
6 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> | ||
7 | * | ||
8 | * Copyright 2005 Freescale Semiconductor, Inc | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify it | ||
11 | * under the terms of the GNU General Public License as published by the | ||
12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
13 | * option) any later version. | ||
14 | */ | ||
15 | |||
16 | #ifdef __KERNEL__ | ||
17 | #ifndef __ASM_MPC83xx_H__ | ||
18 | #define __ASM_MPC83xx_H__ | ||
19 | |||
20 | #include <asm/mmu.h> | ||
21 | |||
22 | #ifdef CONFIG_83xx | ||
23 | |||
24 | #ifdef CONFIG_MPC834x_SYS | ||
25 | #include <platforms/83xx/mpc834x_sys.h> | ||
26 | #endif | ||
27 | |||
28 | /* | ||
29 | * The "residual" board information structure the boot loader passes | ||
30 | * into the kernel. | ||
31 | */ | ||
32 | extern unsigned char __res[]; | ||
33 | |||
34 | /* Internal IRQs on MPC83xx OpenPIC */ | ||
35 | /* Not all of these exist on all MPC83xx implementations */ | ||
36 | |||
37 | #ifndef MPC83xx_IPIC_IRQ_OFFSET | ||
38 | #define MPC83xx_IPIC_IRQ_OFFSET 0 | ||
39 | #endif | ||
40 | |||
41 | #define NR_IPIC_INTS 128 | ||
42 | |||
43 | #define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET) | ||
44 | #define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET) | ||
45 | #define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET) | ||
46 | #define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET) | ||
47 | #define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET) | ||
48 | #define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET) | ||
49 | #define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET) | ||
50 | #define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET) | ||
51 | #define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET) | ||
52 | #define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET) | ||
53 | #define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET) | ||
54 | #define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET) | ||
55 | #define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET) | ||
56 | #define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET) | ||
57 | #define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET) | ||
58 | #define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET) | ||
59 | #define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET) | ||
60 | #define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET) | ||
61 | #define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET) | ||
62 | #define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET) | ||
63 | #define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET) | ||
64 | #define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET) | ||
65 | #define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET) | ||
66 | #define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET) | ||
67 | #define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET) | ||
68 | #define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET) | ||
69 | #define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET) | ||
70 | #define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET) | ||
71 | #define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET) | ||
72 | #define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET) | ||
73 | #define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET) | ||
74 | #define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET) | ||
75 | #define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET) | ||
76 | #define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET) | ||
77 | #define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET) | ||
78 | #define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET) | ||
79 | #define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET) | ||
80 | #define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET) | ||
81 | #define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET) | ||
82 | #define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET) | ||
83 | #define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET) | ||
84 | #define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET) | ||
85 | #define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET) | ||
86 | |||
87 | #define MPC83xx_CCSRBAR_SIZE (1024*1024) | ||
88 | |||
89 | /* Let modules/drivers get at immrbar (physical) */ | ||
90 | extern phys_addr_t immrbar; | ||
91 | |||
92 | enum ppc_sys_devices { | ||
93 | MPC83xx_TSEC1, | ||
94 | MPC83xx_TSEC2, | ||
95 | MPC83xx_IIC1, | ||
96 | MPC83xx_IIC2, | ||
97 | MPC83xx_DUART, | ||
98 | MPC83xx_SEC2, | ||
99 | MPC83xx_USB2_DR, | ||
100 | MPC83xx_USB2_MPH, | ||
101 | MPC83xx_MDIO, | ||
102 | NUM_PPC_SYS_DEVS, | ||
103 | }; | ||
104 | |||
105 | #endif /* CONFIG_83xx */ | ||
106 | #endif /* __ASM_MPC83xx_H__ */ | ||
107 | #endif /* __KERNEL__ */ | ||
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h index de99e92d627b..80c5851972f5 100644 --- a/include/asm-ppc/ppc_sys.h +++ b/include/asm-ppc/ppc_sys.h | |||
@@ -23,8 +23,6 @@ | |||
23 | 23 | ||
24 | #if defined(CONFIG_8260) | 24 | #if defined(CONFIG_8260) |
25 | #include <asm/mpc8260.h> | 25 | #include <asm/mpc8260.h> |
26 | #elif defined(CONFIG_83xx) | ||
27 | #include <asm/mpc83xx.h> | ||
28 | #elif defined(CONFIG_85xx) | 26 | #elif defined(CONFIG_85xx) |
29 | #include <asm/mpc85xx.h> | 27 | #include <asm/mpc85xx.h> |
30 | #elif defined(CONFIG_8xx) | 28 | #elif defined(CONFIG_8xx) |
diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h index 6b7b63f71daa..18d04e8164ca 100644 --- a/include/asm-ppc/ppcboot.h +++ b/include/asm-ppc/ppcboot.h | |||
@@ -38,8 +38,7 @@ typedef struct bd_info { | |||
38 | unsigned long bi_flashoffset; /* reserved area for startup monitor */ | 38 | unsigned long bi_flashoffset; /* reserved area for startup monitor */ |
39 | unsigned long bi_sramstart; /* start of SRAM memory */ | 39 | unsigned long bi_sramstart; /* start of SRAM memory */ |
40 | unsigned long bi_sramsize; /* size of SRAM memory */ | 40 | unsigned long bi_sramsize; /* size of SRAM memory */ |
41 | #if defined(CONFIG_8xx) || defined(CONFIG_CPM2) || defined(CONFIG_85xx) ||\ | 41 | #if defined(CONFIG_8xx) || defined(CONFIG_CPM2) || defined(CONFIG_85xx) |
42 | defined(CONFIG_83xx) | ||
43 | unsigned long bi_immr_base; /* base of IMMR register */ | 42 | unsigned long bi_immr_base; /* base of IMMR register */ |
44 | #endif | 43 | #endif |
45 | #if defined(CONFIG_PPC_MPC52xx) | 44 | #if defined(CONFIG_PPC_MPC52xx) |
@@ -74,7 +73,7 @@ typedef struct bd_info { | |||
74 | hymod_conf_t bi_hymod_conf; /* hymod configuration information */ | 73 | hymod_conf_t bi_hymod_conf; /* hymod configuration information */ |
75 | #endif | 74 | #endif |
76 | #if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) || \ | 75 | #if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) || \ |
77 | defined(CONFIG_85xx) || defined(CONFIG_83xx) | 76 | defined(CONFIG_85xx) |
78 | /* second onboard ethernet port */ | 77 | /* second onboard ethernet port */ |
79 | unsigned char bi_enet1addr[6]; | 78 | unsigned char bi_enet1addr[6]; |
80 | #endif | 79 | #endif |
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h index 8fc1b546613d..6220ef9ab8bc 100644 --- a/include/asm-ppc/serial.h +++ b/include/asm-ppc/serial.h | |||
@@ -29,8 +29,6 @@ | |||
29 | #include <platforms/spruce.h> | 29 | #include <platforms/spruce.h> |
30 | #elif defined(CONFIG_4xx) | 30 | #elif defined(CONFIG_4xx) |
31 | #include <asm/ibm4xx.h> | 31 | #include <asm/ibm4xx.h> |
32 | #elif defined(CONFIG_83xx) | ||
33 | #include <asm/mpc83xx.h> | ||
34 | #elif defined(CONFIG_85xx) | 32 | #elif defined(CONFIG_85xx) |
35 | #include <asm/mpc85xx.h> | 33 | #include <asm/mpc85xx.h> |
36 | #elif defined(CONFIG_RADSTONE_PPC7D) | 34 | #elif defined(CONFIG_RADSTONE_PPC7D) |