aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/net/e1000/e1000.h26
-rw-r--r--drivers/net/e1000/e1000_hw.c1984
-rw-r--r--drivers/net/e1000/e1000_hw.h568
-rw-r--r--drivers/net/e1000/e1000_main.c804
-rw-r--r--drivers/net/e1000/e1000_osdep.h23
5 files changed, 2882 insertions, 523 deletions
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index da055520daa0..19858c267532 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -112,6 +112,8 @@ struct e1000_adapter;
112#define E1000_MAX_82544_RXD 4096 112#define E1000_MAX_82544_RXD 4096
113 113
114/* Supported Rx Buffer Sizes */ 114/* Supported Rx Buffer Sizes */
115#define E1000_RXBUFFER_128 128 /* Used for packet split */
116#define E1000_RXBUFFER_256 256 /* Used for packet split */
115#define E1000_RXBUFFER_2048 2048 117#define E1000_RXBUFFER_2048 2048
116#define E1000_RXBUFFER_4096 4096 118#define E1000_RXBUFFER_4096 4096
117#define E1000_RXBUFFER_8192 8192 119#define E1000_RXBUFFER_8192 8192
@@ -146,6 +148,10 @@ struct e1000_adapter;
146#define E1000_MASTER_SLAVE e1000_ms_hw_default 148#define E1000_MASTER_SLAVE e1000_ms_hw_default
147#endif 149#endif
148 150
151#define E1000_MNG_VLAN_NONE -1
152/* Number of packet split data buffers (not including the header buffer) */
153#define PS_PAGE_BUFFERS MAX_PS_BUFFERS-1
154
149/* only works for sizes that are powers of 2 */ 155/* only works for sizes that are powers of 2 */
150#define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1))) 156#define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
151 157
@@ -159,6 +165,9 @@ struct e1000_buffer {
159 uint16_t next_to_watch; 165 uint16_t next_to_watch;
160}; 166};
161 167
168struct e1000_ps_page { struct page *ps_page[MAX_PS_BUFFERS]; };
169struct e1000_ps_page_dma { uint64_t ps_page_dma[MAX_PS_BUFFERS]; };
170
162struct e1000_desc_ring { 171struct e1000_desc_ring {
163 /* pointer to the descriptor ring memory */ 172 /* pointer to the descriptor ring memory */
164 void *desc; 173 void *desc;
@@ -174,12 +183,19 @@ struct e1000_desc_ring {
174 unsigned int next_to_clean; 183 unsigned int next_to_clean;
175 /* array of buffer information structs */ 184 /* array of buffer information structs */
176 struct e1000_buffer *buffer_info; 185 struct e1000_buffer *buffer_info;
186 /* arrays of page information for packet split */
187 struct e1000_ps_page *ps_page;
188 struct e1000_ps_page_dma *ps_page_dma;
177}; 189};
178 190
179#define E1000_DESC_UNUSED(R) \ 191#define E1000_DESC_UNUSED(R) \
180 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 192 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
181 (R)->next_to_clean - (R)->next_to_use - 1) 193 (R)->next_to_clean - (R)->next_to_use - 1)
182 194
195#define E1000_RX_DESC_PS(R, i) \
196 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
197#define E1000_RX_DESC_EXT(R, i) \
198 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
183#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 199#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
184#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) 200#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
185#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 201#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
@@ -192,6 +208,7 @@ struct e1000_adapter {
192 struct timer_list watchdog_timer; 208 struct timer_list watchdog_timer;
193 struct timer_list phy_info_timer; 209 struct timer_list phy_info_timer;
194 struct vlan_group *vlgrp; 210 struct vlan_group *vlgrp;
211 uint16_t mng_vlan_id;
195 uint32_t bd_number; 212 uint32_t bd_number;
196 uint32_t rx_buffer_len; 213 uint32_t rx_buffer_len;
197 uint32_t part_num; 214 uint32_t part_num;
@@ -228,14 +245,23 @@ struct e1000_adapter {
228 boolean_t detect_tx_hung; 245 boolean_t detect_tx_hung;
229 246
230 /* RX */ 247 /* RX */
248#ifdef CONFIG_E1000_NAPI
249 boolean_t (*clean_rx) (struct e1000_adapter *adapter, int *work_done,
250 int work_to_do);
251#else
252 boolean_t (*clean_rx) (struct e1000_adapter *adapter);
253#endif
254 void (*alloc_rx_buf) (struct e1000_adapter *adapter);
231 struct e1000_desc_ring rx_ring; 255 struct e1000_desc_ring rx_ring;
232 uint64_t hw_csum_err; 256 uint64_t hw_csum_err;
233 uint64_t hw_csum_good; 257 uint64_t hw_csum_good;
234 uint32_t rx_int_delay; 258 uint32_t rx_int_delay;
235 uint32_t rx_abs_int_delay; 259 uint32_t rx_abs_int_delay;
236 boolean_t rx_csum; 260 boolean_t rx_csum;
261 boolean_t rx_ps;
237 uint32_t gorcl; 262 uint32_t gorcl;
238 uint64_t gorcl_old; 263 uint64_t gorcl_old;
264 uint16_t rx_ps_bsize0;
239 265
240 /* Interrupt Throttle Rate */ 266 /* Interrupt Throttle Rate */
241 uint32_t itr; 267 uint32_t itr;
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 786a9b935659..b7a7ceb67f47 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -63,10 +63,11 @@ static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); 63static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64static void e1000_release_eeprom(struct e1000_hw *hw); 64static void e1000_release_eeprom(struct e1000_hw *hw);
65static void e1000_standby_eeprom(struct e1000_hw *hw); 65static void e1000_standby_eeprom(struct e1000_hw *hw);
66static int32_t e1000_id_led_init(struct e1000_hw * hw);
67static int32_t e1000_set_vco_speed(struct e1000_hw *hw); 66static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); 67static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69static int32_t e1000_set_phy_mode(struct e1000_hw *hw); 68static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
69static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
70static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
70 71
71/* IGP cable length table */ 72/* IGP cable length table */
72static const 73static const
@@ -80,6 +81,17 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
80 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 81 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
81 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 82 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
82 83
84static const
85uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
86 { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43,
87 22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58,
88 32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74,
89 43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90,
90 57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108,
91 73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124,
92 91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128,
93 108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128};
94
83 95
84/****************************************************************************** 96/******************************************************************************
85 * Set the phy type member in the hw struct. 97 * Set the phy type member in the hw struct.
@@ -91,10 +103,14 @@ e1000_set_phy_type(struct e1000_hw *hw)
91{ 103{
92 DEBUGFUNC("e1000_set_phy_type"); 104 DEBUGFUNC("e1000_set_phy_type");
93 105
106 if(hw->mac_type == e1000_undefined)
107 return -E1000_ERR_PHY_TYPE;
108
94 switch(hw->phy_id) { 109 switch(hw->phy_id) {
95 case M88E1000_E_PHY_ID: 110 case M88E1000_E_PHY_ID:
96 case M88E1000_I_PHY_ID: 111 case M88E1000_I_PHY_ID:
97 case M88E1011_I_PHY_ID: 112 case M88E1011_I_PHY_ID:
113 case M88E1111_I_PHY_ID:
98 hw->phy_type = e1000_phy_m88; 114 hw->phy_type = e1000_phy_m88;
99 break; 115 break;
100 case IGP01E1000_I_PHY_ID: 116 case IGP01E1000_I_PHY_ID:
@@ -271,6 +287,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
271 case E1000_DEV_ID_82546GB_FIBER: 287 case E1000_DEV_ID_82546GB_FIBER:
272 case E1000_DEV_ID_82546GB_SERDES: 288 case E1000_DEV_ID_82546GB_SERDES:
273 case E1000_DEV_ID_82546GB_PCIE: 289 case E1000_DEV_ID_82546GB_PCIE:
290 case E1000_DEV_ID_82546GB_QUAD_COPPER:
274 hw->mac_type = e1000_82546_rev_3; 291 hw->mac_type = e1000_82546_rev_3;
275 break; 292 break;
276 case E1000_DEV_ID_82541EI: 293 case E1000_DEV_ID_82541EI:
@@ -289,12 +306,19 @@ e1000_set_mac_type(struct e1000_hw *hw)
289 case E1000_DEV_ID_82547GI: 306 case E1000_DEV_ID_82547GI:
290 hw->mac_type = e1000_82547_rev_2; 307 hw->mac_type = e1000_82547_rev_2;
291 break; 308 break;
309 case E1000_DEV_ID_82573E:
310 case E1000_DEV_ID_82573E_IAMT:
311 hw->mac_type = e1000_82573;
312 break;
292 default: 313 default:
293 /* Should never have loaded on this device */ 314 /* Should never have loaded on this device */
294 return -E1000_ERR_MAC_TYPE; 315 return -E1000_ERR_MAC_TYPE;
295 } 316 }
296 317
297 switch(hw->mac_type) { 318 switch(hw->mac_type) {
319 case e1000_82573:
320 hw->eeprom_semaphore_present = TRUE;
321 /* fall through */
298 case e1000_82541: 322 case e1000_82541:
299 case e1000_82547: 323 case e1000_82547:
300 case e1000_82541_rev_2: 324 case e1000_82541_rev_2:
@@ -360,6 +384,9 @@ e1000_reset_hw(struct e1000_hw *hw)
360 uint32_t icr; 384 uint32_t icr;
361 uint32_t manc; 385 uint32_t manc;
362 uint32_t led_ctrl; 386 uint32_t led_ctrl;
387 uint32_t timeout;
388 uint32_t extcnf_ctrl;
389 int32_t ret_val;
363 390
364 DEBUGFUNC("e1000_reset_hw"); 391 DEBUGFUNC("e1000_reset_hw");
365 392
@@ -369,6 +396,15 @@ e1000_reset_hw(struct e1000_hw *hw)
369 e1000_pci_clear_mwi(hw); 396 e1000_pci_clear_mwi(hw);
370 } 397 }
371 398
399 if(hw->bus_type == e1000_bus_type_pci_express) {
400 /* Prevent the PCI-E bus from sticking if there is no TLP connection
401 * on the last TLP read/write transaction when MAC is reset.
402 */
403 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
404 DEBUGOUT("PCI-E Master disable polling has failed.\n");
405 }
406 }
407
372 /* Clear interrupt mask to stop board from generating interrupts */ 408 /* Clear interrupt mask to stop board from generating interrupts */
373 DEBUGOUT("Masking off all interrupts\n"); 409 DEBUGOUT("Masking off all interrupts\n");
374 E1000_WRITE_REG(hw, IMC, 0xffffffff); 410 E1000_WRITE_REG(hw, IMC, 0xffffffff);
@@ -393,10 +429,32 @@ e1000_reset_hw(struct e1000_hw *hw)
393 429
394 /* Must reset the PHY before resetting the MAC */ 430 /* Must reset the PHY before resetting the MAC */
395 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 431 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
396 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 432 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
397 msec_delay(5); 433 msec_delay(5);
398 } 434 }
399 435
436 /* Must acquire the MDIO ownership before MAC reset.
437 * Ownership defaults to firmware after a reset. */
438 if(hw->mac_type == e1000_82573) {
439 timeout = 10;
440
441 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
442 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
443
444 do {
445 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
446 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
447
448 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
449 break;
450 else
451 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
452
453 msec_delay(2);
454 timeout--;
455 } while(timeout);
456 }
457
400 /* Issue a global reset to the MAC. This will reset the chip's 458 /* Issue a global reset to the MAC. This will reset the chip's
401 * transmit, receive, DMA, and link units. It will not effect 459 * transmit, receive, DMA, and link units. It will not effect
402 * the current PCI configuration. The global reset bit is self- 460 * the current PCI configuration. The global reset bit is self-
@@ -450,6 +508,18 @@ e1000_reset_hw(struct e1000_hw *hw)
450 /* Wait for EEPROM reload */ 508 /* Wait for EEPROM reload */
451 msec_delay(20); 509 msec_delay(20);
452 break; 510 break;
511 case e1000_82573:
512 udelay(10);
513 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
514 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
515 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
516 E1000_WRITE_FLUSH(hw);
517 /* fall through */
518 ret_val = e1000_get_auto_rd_done(hw);
519 if(ret_val)
520 /* We don't want to continue accessing MAC registers. */
521 return ret_val;
522 break;
453 default: 523 default:
454 /* Wait for EEPROM reload (it happens automatically) */ 524 /* Wait for EEPROM reload (it happens automatically) */
455 msec_delay(5); 525 msec_delay(5);
@@ -457,7 +527,7 @@ e1000_reset_hw(struct e1000_hw *hw)
457 } 527 }
458 528
459 /* Disable HW ARPs on ASF enabled adapters */ 529 /* Disable HW ARPs on ASF enabled adapters */
460 if(hw->mac_type >= e1000_82540) { 530 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
461 manc = E1000_READ_REG(hw, MANC); 531 manc = E1000_READ_REG(hw, MANC);
462 manc &= ~(E1000_MANC_ARP_EN); 532 manc &= ~(E1000_MANC_ARP_EN);
463 E1000_WRITE_REG(hw, MANC, manc); 533 E1000_WRITE_REG(hw, MANC, manc);
@@ -510,6 +580,8 @@ e1000_init_hw(struct e1000_hw *hw)
510 uint16_t pcix_stat_hi_word; 580 uint16_t pcix_stat_hi_word;
511 uint16_t cmd_mmrbc; 581 uint16_t cmd_mmrbc;
512 uint16_t stat_mmrbc; 582 uint16_t stat_mmrbc;
583 uint32_t mta_size;
584
513 DEBUGFUNC("e1000_init_hw"); 585 DEBUGFUNC("e1000_init_hw");
514 586
515 /* Initialize Identification LED */ 587 /* Initialize Identification LED */
@@ -524,8 +596,8 @@ e1000_init_hw(struct e1000_hw *hw)
524 596
525 /* Disabling VLAN filtering. */ 597 /* Disabling VLAN filtering. */
526 DEBUGOUT("Initializing the IEEE VLAN\n"); 598 DEBUGOUT("Initializing the IEEE VLAN\n");
527 E1000_WRITE_REG(hw, VET, 0); 599 if (hw->mac_type < e1000_82545_rev_3)
528 600 E1000_WRITE_REG(hw, VET, 0);
529 e1000_clear_vfta(hw); 601 e1000_clear_vfta(hw);
530 602
531 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 603 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
@@ -553,14 +625,16 @@ e1000_init_hw(struct e1000_hw *hw)
553 625
554 /* Zero out the Multicast HASH table */ 626 /* Zero out the Multicast HASH table */
555 DEBUGOUT("Zeroing the MTA\n"); 627 DEBUGOUT("Zeroing the MTA\n");
556 for(i = 0; i < E1000_MC_TBL_SIZE; i++) 628 mta_size = E1000_MC_TBL_SIZE;
629 for(i = 0; i < mta_size; i++)
557 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 630 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
558 631
559 /* Set the PCI priority bit correctly in the CTRL register. This 632 /* Set the PCI priority bit correctly in the CTRL register. This
560 * determines if the adapter gives priority to receives, or if it 633 * determines if the adapter gives priority to receives, or if it
561 * gives equal priority to transmits and receives. 634 * gives equal priority to transmits and receives. Valid only on
635 * 82542 and 82543 silicon.
562 */ 636 */
563 if(hw->dma_fairness) { 637 if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
564 ctrl = E1000_READ_REG(hw, CTRL); 638 ctrl = E1000_READ_REG(hw, CTRL);
565 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 639 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
566 } 640 }
@@ -598,9 +672,21 @@ e1000_init_hw(struct e1000_hw *hw)
598 if(hw->mac_type > e1000_82544) { 672 if(hw->mac_type > e1000_82544) {
599 ctrl = E1000_READ_REG(hw, TXDCTL); 673 ctrl = E1000_READ_REG(hw, TXDCTL);
600 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 674 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
675 switch (hw->mac_type) {
676 default:
677 break;
678 case e1000_82573:
679 ctrl |= E1000_TXDCTL_COUNT_DESC;
680 break;
681 }
601 E1000_WRITE_REG(hw, TXDCTL, ctrl); 682 E1000_WRITE_REG(hw, TXDCTL, ctrl);
602 } 683 }
603 684
685 if (hw->mac_type == e1000_82573) {
686 e1000_enable_tx_pkt_filtering(hw);
687 }
688
689
604 /* Clear all of the statistics registers (clear on read). It is 690 /* Clear all of the statistics registers (clear on read). It is
605 * important that we do this after we have tried to establish link 691 * important that we do this after we have tried to establish link
606 * because the symbol error count will increment wildly if there 692 * because the symbol error count will increment wildly if there
@@ -679,7 +765,7 @@ e1000_setup_link(struct e1000_hw *hw)
679 * control setting, then the variable hw->fc will 765 * control setting, then the variable hw->fc will
680 * be initialized based on a value in the EEPROM. 766 * be initialized based on a value in the EEPROM.
681 */ 767 */
682 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) { 768 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) {
683 DEBUGOUT("EEPROM Read Error\n"); 769 DEBUGOUT("EEPROM Read Error\n");
684 return -E1000_ERR_EEPROM; 770 return -E1000_ERR_EEPROM;
685 } 771 }
@@ -736,6 +822,7 @@ e1000_setup_link(struct e1000_hw *hw)
736 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 822 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
737 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 823 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
738 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 824 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
825
739 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 826 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
740 827
741 /* Set the flow control receive threshold registers. Normally, 828 /* Set the flow control receive threshold registers. Normally,
@@ -906,20 +993,18 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
906} 993}
907 994
908/****************************************************************************** 995/******************************************************************************
909* Detects which PHY is present and the speed and duplex 996* Make sure we have a valid PHY and change PHY mode before link setup.
910* 997*
911* hw - Struct containing variables accessed by shared code 998* hw - Struct containing variables accessed by shared code
912******************************************************************************/ 999******************************************************************************/
913static int32_t 1000static int32_t
914e1000_setup_copper_link(struct e1000_hw *hw) 1001e1000_copper_link_preconfig(struct e1000_hw *hw)
915{ 1002{
916 uint32_t ctrl; 1003 uint32_t ctrl;
917 uint32_t led_ctrl;
918 int32_t ret_val; 1004 int32_t ret_val;
919 uint16_t i;
920 uint16_t phy_data; 1005 uint16_t phy_data;
921 1006
922 DEBUGFUNC("e1000_setup_copper_link"); 1007 DEBUGFUNC("e1000_copper_link_preconfig");
923 1008
924 ctrl = E1000_READ_REG(hw, CTRL); 1009 ctrl = E1000_READ_REG(hw, CTRL);
925 /* With 82543, we need to force speed and duplex on the MAC equal to what 1010 /* With 82543, we need to force speed and duplex on the MAC equal to what
@@ -933,7 +1018,9 @@ e1000_setup_copper_link(struct e1000_hw *hw)
933 } else { 1018 } else {
934 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1019 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
935 E1000_WRITE_REG(hw, CTRL, ctrl); 1020 E1000_WRITE_REG(hw, CTRL, ctrl);
936 e1000_phy_hw_reset(hw); 1021 ret_val = e1000_phy_hw_reset(hw);
1022 if(ret_val)
1023 return ret_val;
937 } 1024 }
938 1025
939 /* Make sure we have a valid PHY */ 1026 /* Make sure we have a valid PHY */
@@ -961,274 +1048,398 @@ e1000_setup_copper_link(struct e1000_hw *hw)
961 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) 1048 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
962 hw->phy_reset_disable = FALSE; 1049 hw->phy_reset_disable = FALSE;
963 1050
964 if(!hw->phy_reset_disable) { 1051 return E1000_SUCCESS;
965 if (hw->phy_type == e1000_phy_igp) { 1052}
966 1053
967 ret_val = e1000_phy_reset(hw);
968 if(ret_val) {
969 DEBUGOUT("Error Resetting the PHY\n");
970 return ret_val;
971 }
972 1054
973 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1055/********************************************************************
974 msec_delay(15); 1056* Copper link setup for e1000_phy_igp series.
1057*
1058* hw - Struct containing variables accessed by shared code
1059*********************************************************************/
1060static int32_t
1061e1000_copper_link_igp_setup(struct e1000_hw *hw)
1062{
1063 uint32_t led_ctrl;
1064 int32_t ret_val;
1065 uint16_t phy_data;
975 1066
976 /* Configure activity LED after PHY reset */ 1067 DEBUGFUNC("e1000_copper_link_igp_setup");
977 led_ctrl = E1000_READ_REG(hw, LEDCTL);
978 led_ctrl &= IGP_ACTIVITY_LED_MASK;
979 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
980 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
981 1068
982 /* disable lplu d3 during driver init */ 1069 if (hw->phy_reset_disable)
983 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1070 return E1000_SUCCESS;
984 if(ret_val) { 1071
985 DEBUGOUT("Error Disabling LPLU D3\n"); 1072 ret_val = e1000_phy_reset(hw);
986 return ret_val; 1073 if (ret_val) {
987 } 1074 DEBUGOUT("Error Resetting the PHY\n");
1075 return ret_val;
1076 }
988 1077
989 /* Configure mdi-mdix settings */ 1078 /* Wait 10ms for MAC to configure PHY from eeprom settings */
990 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 1079 msec_delay(15);
991 &phy_data);
992 if(ret_val)
993 return ret_val;
994 1080
995 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1081 /* Configure activity LED after PHY reset */
996 hw->dsp_config_state = e1000_dsp_config_disabled; 1082 led_ctrl = E1000_READ_REG(hw, LEDCTL);
997 /* Force MDI for earlier revs of the IGP PHY */ 1083 led_ctrl &= IGP_ACTIVITY_LED_MASK;
998 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 1084 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
999 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1085 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1000 hw->mdix = 1;
1001 1086
1002 } else { 1087 /* disable lplu d3 during driver init */
1003 hw->dsp_config_state = e1000_dsp_config_enabled; 1088 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1004 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1089 if (ret_val) {
1005 1090 DEBUGOUT("Error Disabling LPLU D3\n");
1006 switch (hw->mdix) { 1091 return ret_val;
1007 case 1: 1092 }
1008 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1009 break;
1010 case 2:
1011 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1012 break;
1013 case 0:
1014 default:
1015 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1016 break;
1017 }
1018 }
1019 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1020 phy_data);
1021 if(ret_val)
1022 return ret_val;
1023 1093
1024 /* set auto-master slave resolution settings */ 1094 /* disable lplu d0 during driver init */
1025 if(hw->autoneg) { 1095 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1026 e1000_ms_type phy_ms_setting = hw->master_slave; 1096 if (ret_val) {
1097 DEBUGOUT("Error Disabling LPLU D0\n");
1098 return ret_val;
1099 }
1100 /* Configure mdi-mdix settings */
1101 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1102 if (ret_val)
1103 return ret_val;
1027 1104
1028 if(hw->ffe_config_state == e1000_ffe_config_active) 1105 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1029 hw->ffe_config_state = e1000_ffe_config_enabled; 1106 hw->dsp_config_state = e1000_dsp_config_disabled;
1107 /* Force MDI for earlier revs of the IGP PHY */
1108 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1109 hw->mdix = 1;
1030 1110
1031 if(hw->dsp_config_state == e1000_dsp_config_activated) 1111 } else {
1032 hw->dsp_config_state = e1000_dsp_config_enabled; 1112 hw->dsp_config_state = e1000_dsp_config_enabled;
1113 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1033 1114
1034 /* when autonegotiation advertisment is only 1000Mbps then we 1115 switch (hw->mdix) {
1035 * should disable SmartSpeed and enable Auto MasterSlave 1116 case 1:
1036 * resolution as hardware default. */ 1117 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1037 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1118 break;
1038 /* Disable SmartSpeed */ 1119 case 2:
1039 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1120 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1040 &phy_data); 1121 break;
1041 if(ret_val) 1122 case 0:
1042 return ret_val; 1123 default:
1043 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1124 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1044 ret_val = e1000_write_phy_reg(hw, 1125 break;
1045 IGP01E1000_PHY_PORT_CONFIG, 1126 }
1046 phy_data); 1127 }
1047 if(ret_val) 1128 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1048 return ret_val; 1129 if(ret_val)
1049 /* Set auto Master/Slave resolution process */ 1130 return ret_val;
1050 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1051 if(ret_val)
1052 return ret_val;
1053 phy_data &= ~CR_1000T_MS_ENABLE;
1054 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1055 if(ret_val)
1056 return ret_val;
1057 }
1058 1131
1059 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1132 /* set auto-master slave resolution settings */
1060 if(ret_val) 1133 if(hw->autoneg) {
1061 return ret_val; 1134 e1000_ms_type phy_ms_setting = hw->master_slave;
1062 1135
1063 /* load defaults for future use */ 1136 if(hw->ffe_config_state == e1000_ffe_config_active)
1064 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1137 hw->ffe_config_state = e1000_ffe_config_enabled;
1065 ((phy_data & CR_1000T_MS_VALUE) ? 1138
1066 e1000_ms_force_master : 1139 if(hw->dsp_config_state == e1000_dsp_config_activated)
1067 e1000_ms_force_slave) : 1140 hw->dsp_config_state = e1000_dsp_config_enabled;
1068 e1000_ms_auto; 1141
1069 1142 /* when autonegotiation advertisment is only 1000Mbps then we
1070 switch (phy_ms_setting) { 1143 * should disable SmartSpeed and enable Auto MasterSlave
1071 case e1000_ms_force_master: 1144 * resolution as hardware default. */
1072 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1145 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1073 break; 1146 /* Disable SmartSpeed */
1074 case e1000_ms_force_slave: 1147 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1075 phy_data |= CR_1000T_MS_ENABLE;
1076 phy_data &= ~(CR_1000T_MS_VALUE);
1077 break;
1078 case e1000_ms_auto:
1079 phy_data &= ~CR_1000T_MS_ENABLE;
1080 default:
1081 break;
1082 }
1083 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1084 if(ret_val)
1085 return ret_val;
1086 }
1087 } else {
1088 /* Enable CRS on TX. This must be set for half-duplex operation. */
1089 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1090 &phy_data);
1091 if(ret_val) 1148 if(ret_val)
1092 return ret_val; 1149 return ret_val;
1150 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1151 ret_val = e1000_write_phy_reg(hw,
1152 IGP01E1000_PHY_PORT_CONFIG,
1153 phy_data);
1154 if(ret_val)
1155 return ret_val;
1156 /* Set auto Master/Slave resolution process */
1157 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1158 if(ret_val)
1159 return ret_val;
1160 phy_data &= ~CR_1000T_MS_ENABLE;
1161 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1162 if(ret_val)
1163 return ret_val;
1164 }
1093 1165
1094 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1166 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1167 if(ret_val)
1168 return ret_val;
1095 1169
1096 /* Options: 1170 /* load defaults for future use */
1097 * MDI/MDI-X = 0 (default) 1171 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1098 * 0 - Auto for all speeds 1172 ((phy_data & CR_1000T_MS_VALUE) ?
1099 * 1 - MDI mode 1173 e1000_ms_force_master :
1100 * 2 - MDI-X mode 1174 e1000_ms_force_slave) :
1101 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1175 e1000_ms_auto;
1102 */
1103 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1104 1176
1105 switch (hw->mdix) { 1177 switch (phy_ms_setting) {
1106 case 1: 1178 case e1000_ms_force_master:
1107 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1179 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1108 break; 1180 break;
1109 case 2: 1181 case e1000_ms_force_slave:
1110 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1182 phy_data |= CR_1000T_MS_ENABLE;
1111 break; 1183 phy_data &= ~(CR_1000T_MS_VALUE);
1112 case 3: 1184 break;
1113 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1185 case e1000_ms_auto:
1114 break; 1186 phy_data &= ~CR_1000T_MS_ENABLE;
1115 case 0:
1116 default: 1187 default:
1117 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1188 break;
1118 break; 1189 }
1119 } 1190 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1191 if(ret_val)
1192 return ret_val;
1193 }
1120 1194
1121 /* Options: 1195 return E1000_SUCCESS;
1122 * disable_polarity_correction = 0 (default) 1196}
1123 * Automatic Correction for Reversed Cable Polarity
1124 * 0 - Disabled
1125 * 1 - Enabled
1126 */
1127 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1128 if(hw->disable_polarity_correction == 1)
1129 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1130 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1131 phy_data);
1132 if(ret_val)
1133 return ret_val;
1134 1197
1135 /* Force TX_CLK in the Extended PHY Specific Control Register
1136 * to 25MHz clock.
1137 */
1138 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1139 &phy_data);
1140 if(ret_val)
1141 return ret_val;
1142 1198
1143 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1199/********************************************************************
1200* Copper link setup for e1000_phy_m88 series.
1201*
1202* hw - Struct containing variables accessed by shared code
1203*********************************************************************/
1204static int32_t
1205e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1206{
1207 int32_t ret_val;
1208 uint16_t phy_data;
1209
1210 DEBUGFUNC("e1000_copper_link_mgp_setup");
1211
1212 if(hw->phy_reset_disable)
1213 return E1000_SUCCESS;
1214
1215 /* Enable CRS on TX. This must be set for half-duplex operation. */
1216 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1217 if(ret_val)
1218 return ret_val;
1219
1220 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1221
1222 /* Options:
1223 * MDI/MDI-X = 0 (default)
1224 * 0 - Auto for all speeds
1225 * 1 - MDI mode
1226 * 2 - MDI-X mode
1227 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1228 */
1229 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1230
1231 switch (hw->mdix) {
1232 case 1:
1233 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1234 break;
1235 case 2:
1236 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1237 break;
1238 case 3:
1239 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1240 break;
1241 case 0:
1242 default:
1243 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1244 break;
1245 }
1144 1246
1145 if (hw->phy_revision < M88E1011_I_REV_4) { 1247 /* Options:
1146 /* Configure Master and Slave downshift values */ 1248 * disable_polarity_correction = 0 (default)
1147 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1249 * Automatic Correction for Reversed Cable Polarity
1250 * 0 - Disabled
1251 * 1 - Enabled
1252 */
1253 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1254 if(hw->disable_polarity_correction == 1)
1255 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1256 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1257 if(ret_val)
1258 return ret_val;
1259
1260 /* Force TX_CLK in the Extended PHY Specific Control Register
1261 * to 25MHz clock.
1262 */
1263 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1264 if(ret_val)
1265 return ret_val;
1266
1267 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1268
1269 if (hw->phy_revision < M88E1011_I_REV_4) {
1270 /* Configure Master and Slave downshift values */
1271 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1148 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1272 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1149 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1273 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1150 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1274 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1151 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1275 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1152 phy_data); 1276 if(ret_val)
1153 if(ret_val) 1277 return ret_val;
1154 return ret_val; 1278 }
1155 }
1156 1279
1157 /* SW Reset the PHY so all changes take effect */ 1280 /* SW Reset the PHY so all changes take effect */
1158 ret_val = e1000_phy_reset(hw); 1281 ret_val = e1000_phy_reset(hw);
1159 if(ret_val) { 1282 if(ret_val) {
1160 DEBUGOUT("Error Resetting the PHY\n"); 1283 DEBUGOUT("Error Resetting the PHY\n");
1161 return ret_val; 1284 return ret_val;
1162 } 1285 }
1286
1287 return E1000_SUCCESS;
1288}
1289
1290/********************************************************************
1291* Setup auto-negotiation and flow control advertisements,
1292* and then perform auto-negotiation.
1293*
1294* hw - Struct containing variables accessed by shared code
1295*********************************************************************/
1296static int32_t
1297e1000_copper_link_autoneg(struct e1000_hw *hw)
1298{
1299 int32_t ret_val;
1300 uint16_t phy_data;
1301
1302 DEBUGFUNC("e1000_copper_link_autoneg");
1303
1304 /* Perform some bounds checking on the hw->autoneg_advertised
1305 * parameter. If this variable is zero, then set it to the default.
1306 */
1307 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1308
1309 /* If autoneg_advertised is zero, we assume it was not defaulted
1310 * by the calling code so we set to advertise full capability.
1311 */
1312 if(hw->autoneg_advertised == 0)
1313 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1314
1315 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1316 ret_val = e1000_phy_setup_autoneg(hw);
1317 if(ret_val) {
1318 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1319 return ret_val;
1320 }
1321 DEBUGOUT("Restarting Auto-Neg\n");
1322
1323 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1324 * the Auto Neg Restart bit in the PHY control register.
1325 */
1326 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1327 if(ret_val)
1328 return ret_val;
1329
1330 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1331 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1332 if(ret_val)
1333 return ret_val;
1334
1335 /* Does the user want to wait for Auto-Neg to complete here, or
1336 * check at a later time (for example, callback routine).
1337 */
1338 if(hw->wait_autoneg_complete) {
1339 ret_val = e1000_wait_autoneg(hw);
1340 if(ret_val) {
1341 DEBUGOUT("Error while waiting for autoneg to complete\n");
1342 return ret_val;
1163 } 1343 }
1344 }
1164 1345
1165 /* Options: 1346 hw->get_link_status = TRUE;
1166 * autoneg = 1 (default)
1167 * PHY will advertise value(s) parsed from
1168 * autoneg_advertised and fc
1169 * autoneg = 0
1170 * PHY will be set to 10H, 10F, 100H, or 100F
1171 * depending on value parsed from forced_speed_duplex.
1172 */
1173 1347
1174 /* Is autoneg enabled? This is enabled by default or by software 1348 return E1000_SUCCESS;
1175 * override. If so, call e1000_phy_setup_autoneg routine to parse the 1349}
1176 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1177 * the user should have provided a speed/duplex override. If so, then
1178 * call e1000_phy_force_speed_duplex to parse and set this up.
1179 */
1180 if(hw->autoneg) {
1181 /* Perform some bounds checking on the hw->autoneg_advertised
1182 * parameter. If this variable is zero, then set it to the default.
1183 */
1184 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1185 1350
1186 /* If autoneg_advertised is zero, we assume it was not defaulted
1187 * by the calling code so we set to advertise full capability.
1188 */
1189 if(hw->autoneg_advertised == 0)
1190 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1191 1351
1192 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1352/******************************************************************************
1193 ret_val = e1000_phy_setup_autoneg(hw); 1353* Config the MAC and the PHY after link is up.
1194 if(ret_val) { 1354* 1) Set up the MAC to the current PHY speed/duplex
1195 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1355* if we are on 82543. If we
1196 return ret_val; 1356* are on newer silicon, we only need to configure
1197 } 1357* collision distance in the Transmit Control Register.
1198 DEBUGOUT("Restarting Auto-Neg\n"); 1358* 2) Set up flow control on the MAC to that established with
1359* the link partner.
1360* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1361*
1362* hw - Struct containing variables accessed by shared code
1363******************************************************************************/
1364static int32_t
1365e1000_copper_link_postconfig(struct e1000_hw *hw)
1366{
1367 int32_t ret_val;
1368 DEBUGFUNC("e1000_copper_link_postconfig");
1369
1370 if(hw->mac_type >= e1000_82544) {
1371 e1000_config_collision_dist(hw);
1372 } else {
1373 ret_val = e1000_config_mac_to_phy(hw);
1374 if(ret_val) {
1375 DEBUGOUT("Error configuring MAC to PHY settings\n");
1376 return ret_val;
1377 }
1378 }
1379 ret_val = e1000_config_fc_after_link_up(hw);
1380 if(ret_val) {
1381 DEBUGOUT("Error Configuring Flow Control\n");
1382 return ret_val;
1383 }
1199 1384
1200 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1385 /* Config DSP to improve Giga link quality */
1201 * the Auto Neg Restart bit in the PHY control register. 1386 if(hw->phy_type == e1000_phy_igp) {
1202 */ 1387 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1203 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1388 if(ret_val) {
1204 if(ret_val) 1389 DEBUGOUT("Error Configuring DSP after link up\n");
1205 return ret_val; 1390 return ret_val;
1391 }
1392 }
1393
1394 return E1000_SUCCESS;
1395}
1206 1396
1207 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1397/******************************************************************************
1208 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1398* Detects which PHY is present and setup the speed and duplex
1209 if(ret_val) 1399*
1210 return ret_val; 1400* hw - Struct containing variables accessed by shared code
1401******************************************************************************/
1402static int32_t
1403e1000_setup_copper_link(struct e1000_hw *hw)
1404{
1405 int32_t ret_val;
1406 uint16_t i;
1407 uint16_t phy_data;
1211 1408
1212 /* Does the user want to wait for Auto-Neg to complete here, or 1409 DEBUGFUNC("e1000_setup_copper_link");
1213 * check at a later time (for example, callback routine). 1410
1214 */ 1411 /* Check if it is a valid PHY and set PHY mode if necessary. */
1215 if(hw->wait_autoneg_complete) { 1412 ret_val = e1000_copper_link_preconfig(hw);
1216 ret_val = e1000_wait_autoneg(hw); 1413 if(ret_val)
1217 if(ret_val) { 1414 return ret_val;
1218 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1415
1219 return ret_val; 1416 if (hw->phy_type == e1000_phy_igp ||
1220 } 1417 hw->phy_type == e1000_phy_igp_2) {
1221 } 1418 ret_val = e1000_copper_link_igp_setup(hw);
1222 hw->get_link_status = TRUE; 1419 if(ret_val)
1223 } else { 1420 return ret_val;
1224 DEBUGOUT("Forcing speed and duplex\n"); 1421 } else if (hw->phy_type == e1000_phy_m88) {
1225 ret_val = e1000_phy_force_speed_duplex(hw); 1422 ret_val = e1000_copper_link_mgp_setup(hw);
1226 if(ret_val) { 1423 if(ret_val)
1227 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1424 return ret_val;
1228 return ret_val; 1425 }
1229 } 1426
1427 if(hw->autoneg) {
1428 /* Setup autoneg and flow control advertisement
1429 * and perform autonegotiation */
1430 ret_val = e1000_copper_link_autoneg(hw);
1431 if(ret_val)
1432 return ret_val;
1433 } else {
1434 /* PHY will be set to 10H, 10F, 100H,or 100F
1435 * depending on value from forced_speed_duplex. */
1436 DEBUGOUT("Forcing speed and duplex\n");
1437 ret_val = e1000_phy_force_speed_duplex(hw);
1438 if(ret_val) {
1439 DEBUGOUT("Error Forcing Speed and Duplex\n");
1440 return ret_val;
1230 } 1441 }
1231 } /* !hw->phy_reset_disable */ 1442 }
1232 1443
1233 /* Check link status. Wait up to 100 microseconds for link to become 1444 /* Check link status. Wait up to 100 microseconds for link to become
1234 * valid. 1445 * valid.
@@ -1242,37 +1453,11 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1242 return ret_val; 1453 return ret_val;
1243 1454
1244 if(phy_data & MII_SR_LINK_STATUS) { 1455 if(phy_data & MII_SR_LINK_STATUS) {
1245 /* We have link, so we need to finish the config process: 1456 /* Config the MAC and PHY after link is up */
1246 * 1) Set up the MAC to the current PHY speed/duplex 1457 ret_val = e1000_copper_link_postconfig(hw);
1247 * if we are on 82543. If we 1458 if(ret_val)
1248 * are on newer silicon, we only need to configure
1249 * collision distance in the Transmit Control Register.
1250 * 2) Set up flow control on the MAC to that established with
1251 * the link partner.
1252 */
1253 if(hw->mac_type >= e1000_82544) {
1254 e1000_config_collision_dist(hw);
1255 } else {
1256 ret_val = e1000_config_mac_to_phy(hw);
1257 if(ret_val) {
1258 DEBUGOUT("Error configuring MAC to PHY settings\n");
1259 return ret_val;
1260 }
1261 }
1262 ret_val = e1000_config_fc_after_link_up(hw);
1263 if(ret_val) {
1264 DEBUGOUT("Error Configuring Flow Control\n");
1265 return ret_val; 1459 return ret_val;
1266 } 1460
1267 DEBUGOUT("Valid link established!!!\n");
1268
1269 if(hw->phy_type == e1000_phy_igp) {
1270 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1271 if(ret_val) {
1272 DEBUGOUT("Error Configuring DSP after link up\n");
1273 return ret_val;
1274 }
1275 }
1276 DEBUGOUT("Valid link established!!!\n"); 1461 DEBUGOUT("Valid link established!!!\n");
1277 return E1000_SUCCESS; 1462 return E1000_SUCCESS;
1278 } 1463 }
@@ -1302,10 +1487,10 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1302 if(ret_val) 1487 if(ret_val)
1303 return ret_val; 1488 return ret_val;
1304 1489
1305 /* Read the MII 1000Base-T Control Register (Address 9). */ 1490 /* Read the MII 1000Base-T Control Register (Address 9). */
1306 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1491 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1307 if(ret_val) 1492 if(ret_val)
1308 return ret_val; 1493 return ret_val;
1309 1494
1310 /* Need to parse both autoneg_advertised and fc and set up 1495 /* Need to parse both autoneg_advertised and fc and set up
1311 * the appropriate PHY registers. First we will parse for 1496 * the appropriate PHY registers. First we will parse for
@@ -1417,7 +1602,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1417 1602
1418 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1603 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1419 1604
1420 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1605 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1421 if(ret_val) 1606 if(ret_val)
1422 return ret_val; 1607 return ret_val;
1423 1608
@@ -1678,6 +1863,11 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
1678 1863
1679 DEBUGFUNC("e1000_config_mac_to_phy"); 1864 DEBUGFUNC("e1000_config_mac_to_phy");
1680 1865
1866 /* 82544 or newer MAC, Auto Speed Detection takes care of
1867 * MAC speed/duplex configuration.*/
1868 if (hw->mac_type >= e1000_82544)
1869 return E1000_SUCCESS;
1870
1681 /* Read the Device Control Register and set the bits to Force Speed 1871 /* Read the Device Control Register and set the bits to Force Speed
1682 * and Duplex. 1872 * and Duplex.
1683 */ 1873 */
@@ -1688,45 +1878,25 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
1688 /* Set up duplex in the Device Control and Transmit Control 1878 /* Set up duplex in the Device Control and Transmit Control
1689 * registers depending on negotiated values. 1879 * registers depending on negotiated values.
1690 */ 1880 */
1691 if (hw->phy_type == e1000_phy_igp) { 1881 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1692 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 1882 if(ret_val)
1693 &phy_data); 1883 return ret_val;
1694 if(ret_val)
1695 return ret_val;
1696
1697 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1698 else ctrl &= ~E1000_CTRL_FD;
1699
1700 e1000_config_collision_dist(hw);
1701 1884
1702 /* Set up speed in the Device Control register depending on 1885 if(phy_data & M88E1000_PSSR_DPLX)
1703 * negotiated values. 1886 ctrl |= E1000_CTRL_FD;
1704 */ 1887 else
1705 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 1888 ctrl &= ~E1000_CTRL_FD;
1706 IGP01E1000_PSSR_SPEED_1000MBPS)
1707 ctrl |= E1000_CTRL_SPD_1000;
1708 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1709 IGP01E1000_PSSR_SPEED_100MBPS)
1710 ctrl |= E1000_CTRL_SPD_100;
1711 } else {
1712 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1713 &phy_data);
1714 if(ret_val)
1715 return ret_val;
1716 1889
1717 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD; 1890 e1000_config_collision_dist(hw);
1718 else ctrl &= ~E1000_CTRL_FD;
1719 1891
1720 e1000_config_collision_dist(hw); 1892 /* Set up speed in the Device Control register depending on
1893 * negotiated values.
1894 */
1895 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1896 ctrl |= E1000_CTRL_SPD_1000;
1897 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1898 ctrl |= E1000_CTRL_SPD_100;
1721 1899
1722 /* Set up speed in the Device Control register depending on
1723 * negotiated values.
1724 */
1725 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1726 ctrl |= E1000_CTRL_SPD_1000;
1727 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1728 ctrl |= E1000_CTRL_SPD_100;
1729 }
1730 /* Write the configured values back to the Device Control Reg. */ 1900 /* Write the configured values back to the Device Control Reg. */
1731 E1000_WRITE_REG(hw, CTRL, ctrl); 1901 E1000_WRITE_REG(hw, CTRL, ctrl);
1732 return E1000_SUCCESS; 1902 return E1000_SUCCESS;
@@ -2494,8 +2664,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
2494 2664
2495 DEBUGFUNC("e1000_read_phy_reg"); 2665 DEBUGFUNC("e1000_read_phy_reg");
2496 2666
2497 2667 if((hw->phy_type == e1000_phy_igp ||
2498 if(hw->phy_type == e1000_phy_igp && 2668 hw->phy_type == e1000_phy_igp_2) &&
2499 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2669 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2500 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2670 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2501 (uint16_t)reg_addr); 2671 (uint16_t)reg_addr);
@@ -2600,8 +2770,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
2600 2770
2601 DEBUGFUNC("e1000_write_phy_reg"); 2771 DEBUGFUNC("e1000_write_phy_reg");
2602 2772
2603 2773 if((hw->phy_type == e1000_phy_igp ||
2604 if(hw->phy_type == e1000_phy_igp && 2774 hw->phy_type == e1000_phy_igp_2) &&
2605 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2775 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2606 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2776 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2607 (uint16_t)reg_addr); 2777 (uint16_t)reg_addr);
@@ -2679,19 +2849,27 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
2679 return E1000_SUCCESS; 2849 return E1000_SUCCESS;
2680} 2850}
2681 2851
2852
2682/****************************************************************************** 2853/******************************************************************************
2683* Returns the PHY to the power-on reset state 2854* Returns the PHY to the power-on reset state
2684* 2855*
2685* hw - Struct containing variables accessed by shared code 2856* hw - Struct containing variables accessed by shared code
2686******************************************************************************/ 2857******************************************************************************/
2687void 2858int32_t
2688e1000_phy_hw_reset(struct e1000_hw *hw) 2859e1000_phy_hw_reset(struct e1000_hw *hw)
2689{ 2860{
2690 uint32_t ctrl, ctrl_ext; 2861 uint32_t ctrl, ctrl_ext;
2691 uint32_t led_ctrl; 2862 uint32_t led_ctrl;
2863 int32_t ret_val;
2692 2864
2693 DEBUGFUNC("e1000_phy_hw_reset"); 2865 DEBUGFUNC("e1000_phy_hw_reset");
2694 2866
2867 /* In the case of the phy reset being blocked, it's not an error, we
2868 * simply return success without performing the reset. */
2869 ret_val = e1000_check_phy_reset_block(hw);
2870 if (ret_val)
2871 return E1000_SUCCESS;
2872
2695 DEBUGOUT("Resetting Phy...\n"); 2873 DEBUGOUT("Resetting Phy...\n");
2696 2874
2697 if(hw->mac_type > e1000_82543) { 2875 if(hw->mac_type > e1000_82543) {
@@ -2727,6 +2905,11 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
2727 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2905 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2728 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2906 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2729 } 2907 }
2908
2909 /* Wait for FW to finish PHY configuration. */
2910 ret_val = e1000_get_phy_cfg_done(hw);
2911
2912 return ret_val;
2730} 2913}
2731 2914
2732/****************************************************************************** 2915/******************************************************************************
@@ -2744,7 +2927,19 @@ e1000_phy_reset(struct e1000_hw *hw)
2744 2927
2745 DEBUGFUNC("e1000_phy_reset"); 2928 DEBUGFUNC("e1000_phy_reset");
2746 2929
2747 if(hw->mac_type != e1000_82541_rev_2) { 2930 /* In the case of the phy reset being blocked, it's not an error, we
2931 * simply return success without performing the reset. */
2932 ret_val = e1000_check_phy_reset_block(hw);
2933 if (ret_val)
2934 return E1000_SUCCESS;
2935
2936 switch (hw->mac_type) {
2937 case e1000_82541_rev_2:
2938 ret_val = e1000_phy_hw_reset(hw);
2939 if(ret_val)
2940 return ret_val;
2941 break;
2942 default:
2748 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2943 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2749 if(ret_val) 2944 if(ret_val)
2750 return ret_val; 2945 return ret_val;
@@ -2755,9 +2950,10 @@ e1000_phy_reset(struct e1000_hw *hw)
2755 return ret_val; 2950 return ret_val;
2756 2951
2757 udelay(1); 2952 udelay(1);
2758 } else e1000_phy_hw_reset(hw); 2953 break;
2954 }
2759 2955
2760 if(hw->phy_type == e1000_phy_igp) 2956 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
2761 e1000_phy_init_script(hw); 2957 e1000_phy_init_script(hw);
2762 2958
2763 return E1000_SUCCESS; 2959 return E1000_SUCCESS;
@@ -2811,6 +3007,9 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
2811 case e1000_82547_rev_2: 3007 case e1000_82547_rev_2:
2812 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 3008 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2813 break; 3009 break;
3010 case e1000_82573:
3011 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3012 break;
2814 default: 3013 default:
2815 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3014 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2816 return -E1000_ERR_CONFIG; 3015 return -E1000_ERR_CONFIG;
@@ -2866,7 +3065,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
2866 3065
2867 /* The downshift status is checked only once, after link is established, 3066 /* The downshift status is checked only once, after link is established,
2868 * and it stored in the hw->speed_downgraded parameter. */ 3067 * and it stored in the hw->speed_downgraded parameter. */
2869 phy_info->downshift = hw->speed_downgraded; 3068 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
2870 3069
2871 /* IGP01E1000 does not need to support it. */ 3070 /* IGP01E1000 does not need to support it. */
2872 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3071 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
@@ -2905,7 +3104,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
2905 if(ret_val) 3104 if(ret_val)
2906 return ret_val; 3105 return ret_val;
2907 3106
2908 /* transalte to old method */ 3107 /* Translate to old method */
2909 average = (max_length + min_length) / 2; 3108 average = (max_length + min_length) / 2;
2910 3109
2911 if(average <= e1000_igp_cable_length_50) 3110 if(average <= e1000_igp_cable_length_50)
@@ -2940,7 +3139,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
2940 3139
2941 /* The downshift status is checked only once, after link is established, 3140 /* The downshift status is checked only once, after link is established,
2942 * and it stored in the hw->speed_downgraded parameter. */ 3141 * and it stored in the hw->speed_downgraded parameter. */
2943 phy_info->downshift = hw->speed_downgraded; 3142 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
2944 3143
2945 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3144 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2946 if(ret_val) 3145 if(ret_val)
@@ -3029,7 +3228,8 @@ e1000_phy_get_info(struct e1000_hw *hw,
3029 return -E1000_ERR_CONFIG; 3228 return -E1000_ERR_CONFIG;
3030 } 3229 }
3031 3230
3032 if(hw->phy_type == e1000_phy_igp) 3231 if(hw->phy_type == e1000_phy_igp ||
3232 hw->phy_type == e1000_phy_igp_2)
3033 return e1000_phy_igp_get_info(hw, phy_info); 3233 return e1000_phy_igp_get_info(hw, phy_info);
3034 else 3234 else
3035 return e1000_phy_m88_get_info(hw, phy_info); 3235 return e1000_phy_m88_get_info(hw, phy_info);
@@ -3055,11 +3255,12 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
3055 * 3255 *
3056 * hw - Struct containing variables accessed by shared code 3256 * hw - Struct containing variables accessed by shared code
3057 *****************************************************************************/ 3257 *****************************************************************************/
3058void 3258int32_t
3059e1000_init_eeprom_params(struct e1000_hw *hw) 3259e1000_init_eeprom_params(struct e1000_hw *hw)
3060{ 3260{
3061 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3261 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3062 uint32_t eecd = E1000_READ_REG(hw, EECD); 3262 uint32_t eecd = E1000_READ_REG(hw, EECD);
3263 int32_t ret_val = E1000_SUCCESS;
3063 uint16_t eeprom_size; 3264 uint16_t eeprom_size;
3064 3265
3065 DEBUGFUNC("e1000_init_eeprom_params"); 3266 DEBUGFUNC("e1000_init_eeprom_params");
@@ -3074,6 +3275,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3074 eeprom->opcode_bits = 3; 3275 eeprom->opcode_bits = 3;
3075 eeprom->address_bits = 6; 3276 eeprom->address_bits = 6;
3076 eeprom->delay_usec = 50; 3277 eeprom->delay_usec = 50;
3278 eeprom->use_eerd = FALSE;
3279 eeprom->use_eewr = FALSE;
3077 break; 3280 break;
3078 case e1000_82540: 3281 case e1000_82540:
3079 case e1000_82545: 3282 case e1000_82545:
@@ -3090,6 +3293,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3090 eeprom->word_size = 64; 3293 eeprom->word_size = 64;
3091 eeprom->address_bits = 6; 3294 eeprom->address_bits = 6;
3092 } 3295 }
3296 eeprom->use_eerd = FALSE;
3297 eeprom->use_eewr = FALSE;
3093 break; 3298 break;
3094 case e1000_82541: 3299 case e1000_82541:
3095 case e1000_82541_rev_2: 3300 case e1000_82541_rev_2:
@@ -3118,42 +3323,60 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3118 eeprom->address_bits = 6; 3323 eeprom->address_bits = 6;
3119 } 3324 }
3120 } 3325 }
3326 eeprom->use_eerd = FALSE;
3327 eeprom->use_eewr = FALSE;
3328 break;
3329 case e1000_82573:
3330 eeprom->type = e1000_eeprom_spi;
3331 eeprom->opcode_bits = 8;
3332 eeprom->delay_usec = 1;
3333 if (eecd & E1000_EECD_ADDR_BITS) {
3334 eeprom->page_size = 32;
3335 eeprom->address_bits = 16;
3336 } else {
3337 eeprom->page_size = 8;
3338 eeprom->address_bits = 8;
3339 }
3340 eeprom->use_eerd = TRUE;
3341 eeprom->use_eewr = TRUE;
3342 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
3343 eeprom->type = e1000_eeprom_flash;
3344 eeprom->word_size = 2048;
3345
3346 /* Ensure that the Autonomous FLASH update bit is cleared due to
3347 * Flash update issue on parts which use a FLASH for NVM. */
3348 eecd &= ~E1000_EECD_AUPDEN;
3349 E1000_WRITE_REG(hw, EECD, eecd);
3350 }
3121 break; 3351 break;
3122 default: 3352 default:
3123 break; 3353 break;
3124 } 3354 }
3125 3355
3126 if (eeprom->type == e1000_eeprom_spi) { 3356 if (eeprom->type == e1000_eeprom_spi) {
3127 eeprom->word_size = 64; 3357 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3128 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) { 3358 * 32KB (incremented by powers of 2).
3129 eeprom_size &= EEPROM_SIZE_MASK; 3359 */
3130 3360 if(hw->mac_type <= e1000_82547_rev_2) {
3131 switch (eeprom_size) { 3361 /* Set to default value for initial eeprom read. */
3132 case EEPROM_SIZE_16KB: 3362 eeprom->word_size = 64;
3133 eeprom->word_size = 8192; 3363 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3134 break; 3364 if(ret_val)
3135 case EEPROM_SIZE_8KB: 3365 return ret_val;
3136 eeprom->word_size = 4096; 3366 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3137 break; 3367 /* 256B eeprom size was not supported in earlier hardware, so we
3138 case EEPROM_SIZE_4KB: 3368 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3139 eeprom->word_size = 2048; 3369 * is never the result used in the shifting logic below. */
3140 break; 3370 if(eeprom_size)
3141 case EEPROM_SIZE_2KB: 3371 eeprom_size++;
3142 eeprom->word_size = 1024; 3372 } else {
3143 break; 3373 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
3144 case EEPROM_SIZE_1KB: 3374 E1000_EECD_SIZE_EX_SHIFT);
3145 eeprom->word_size = 512;
3146 break;
3147 case EEPROM_SIZE_512B:
3148 eeprom->word_size = 256;
3149 break;
3150 case EEPROM_SIZE_128B:
3151 default:
3152 eeprom->word_size = 64;
3153 break;
3154 }
3155 } 3375 }
3376
3377 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3156 } 3378 }
3379 return ret_val;
3157} 3380}
3158 3381
3159/****************************************************************************** 3382/******************************************************************************
@@ -3306,8 +3529,12 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3306 3529
3307 DEBUGFUNC("e1000_acquire_eeprom"); 3530 DEBUGFUNC("e1000_acquire_eeprom");
3308 3531
3532 if(e1000_get_hw_eeprom_semaphore(hw))
3533 return -E1000_ERR_EEPROM;
3534
3309 eecd = E1000_READ_REG(hw, EECD); 3535 eecd = E1000_READ_REG(hw, EECD);
3310 3536
3537 if (hw->mac_type != e1000_82573) {
3311 /* Request EEPROM Access */ 3538 /* Request EEPROM Access */
3312 if(hw->mac_type > e1000_82544) { 3539 if(hw->mac_type > e1000_82544) {
3313 eecd |= E1000_EECD_REQ; 3540 eecd |= E1000_EECD_REQ;
@@ -3326,6 +3553,7 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3326 return -E1000_ERR_EEPROM; 3553 return -E1000_ERR_EEPROM;
3327 } 3554 }
3328 } 3555 }
3556 }
3329 3557
3330 /* Setup EEPROM for Read/Write */ 3558 /* Setup EEPROM for Read/Write */
3331 3559
@@ -3443,6 +3671,8 @@ e1000_release_eeprom(struct e1000_hw *hw)
3443 eecd &= ~E1000_EECD_REQ; 3671 eecd &= ~E1000_EECD_REQ;
3444 E1000_WRITE_REG(hw, EECD, eecd); 3672 E1000_WRITE_REG(hw, EECD, eecd);
3445 } 3673 }
3674
3675 e1000_put_hw_eeprom_semaphore(hw);
3446} 3676}
3447 3677
3448/****************************************************************************** 3678/******************************************************************************
@@ -3504,8 +3734,10 @@ e1000_read_eeprom(struct e1000_hw *hw,
3504{ 3734{
3505 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3735 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3506 uint32_t i = 0; 3736 uint32_t i = 0;
3737 int32_t ret_val;
3507 3738
3508 DEBUGFUNC("e1000_read_eeprom"); 3739 DEBUGFUNC("e1000_read_eeprom");
3740
3509 /* A check for invalid values: offset too large, too many words, and not 3741 /* A check for invalid values: offset too large, too many words, and not
3510 * enough words. 3742 * enough words.
3511 */ 3743 */
@@ -3515,9 +3747,23 @@ e1000_read_eeprom(struct e1000_hw *hw,
3515 return -E1000_ERR_EEPROM; 3747 return -E1000_ERR_EEPROM;
3516 } 3748 }
3517 3749
3518 /* Prepare the EEPROM for reading */ 3750 /* FLASH reads without acquiring the semaphore are safe in 82573-based
3519 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3751 * controllers.
3520 return -E1000_ERR_EEPROM; 3752 */
3753 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3754 (hw->mac_type != e1000_82573)) {
3755 /* Prepare the EEPROM for reading */
3756 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3757 return -E1000_ERR_EEPROM;
3758 }
3759
3760 if(eeprom->use_eerd == TRUE) {
3761 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
3762 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3763 (hw->mac_type != e1000_82573))
3764 e1000_release_eeprom(hw);
3765 return ret_val;
3766 }
3521 3767
3522 if(eeprom->type == e1000_eeprom_spi) { 3768 if(eeprom->type == e1000_eeprom_spi) {
3523 uint16_t word_in; 3769 uint16_t word_in;
@@ -3569,6 +3815,132 @@ e1000_read_eeprom(struct e1000_hw *hw,
3569} 3815}
3570 3816
3571/****************************************************************************** 3817/******************************************************************************
3818 * Reads a 16 bit word from the EEPROM using the EERD register.
3819 *
3820 * hw - Struct containing variables accessed by shared code
3821 * offset - offset of word in the EEPROM to read
3822 * data - word read from the EEPROM
3823 * words - number of words to read
3824 *****************************************************************************/
3825int32_t
3826e1000_read_eeprom_eerd(struct e1000_hw *hw,
3827 uint16_t offset,
3828 uint16_t words,
3829 uint16_t *data)
3830{
3831 uint32_t i, eerd = 0;
3832 int32_t error = 0;
3833
3834 for (i = 0; i < words; i++) {
3835 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
3836 E1000_EEPROM_RW_REG_START;
3837
3838 E1000_WRITE_REG(hw, EERD, eerd);
3839 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
3840
3841 if(error) {
3842 break;
3843 }
3844 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
3845
3846 }
3847
3848 return error;
3849}
3850
3851/******************************************************************************
3852 * Writes a 16 bit word from the EEPROM using the EEWR register.
3853 *
3854 * hw - Struct containing variables accessed by shared code
3855 * offset - offset of word in the EEPROM to read
3856 * data - word read from the EEPROM
3857 * words - number of words to read
3858 *****************************************************************************/
3859int32_t
3860e1000_write_eeprom_eewr(struct e1000_hw *hw,
3861 uint16_t offset,
3862 uint16_t words,
3863 uint16_t *data)
3864{
3865 uint32_t register_value = 0;
3866 uint32_t i = 0;
3867 int32_t error = 0;
3868
3869 for (i = 0; i < words; i++) {
3870 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
3871 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
3872 E1000_EEPROM_RW_REG_START;
3873
3874 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3875 if(error) {
3876 break;
3877 }
3878
3879 E1000_WRITE_REG(hw, EEWR, register_value);
3880
3881 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3882
3883 if(error) {
3884 break;
3885 }
3886 }
3887
3888 return error;
3889}
3890
3891/******************************************************************************
3892 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
3893 *
3894 * hw - Struct containing variables accessed by shared code
3895 *****************************************************************************/
3896int32_t
3897e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
3898{
3899 uint32_t attempts = 100000;
3900 uint32_t i, reg = 0;
3901 int32_t done = E1000_ERR_EEPROM;
3902
3903 for(i = 0; i < attempts; i++) {
3904 if(eerd == E1000_EEPROM_POLL_READ)
3905 reg = E1000_READ_REG(hw, EERD);
3906 else
3907 reg = E1000_READ_REG(hw, EEWR);
3908
3909 if(reg & E1000_EEPROM_RW_REG_DONE) {
3910 done = E1000_SUCCESS;
3911 break;
3912 }
3913 udelay(5);
3914 }
3915
3916 return done;
3917}
3918
3919/***************************************************************************
3920* Description: Determines if the onboard NVM is FLASH or EEPROM.
3921*
3922* hw - Struct containing variables accessed by shared code
3923****************************************************************************/
3924boolean_t
3925e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
3926{
3927 uint32_t eecd = 0;
3928
3929 if(hw->mac_type == e1000_82573) {
3930 eecd = E1000_READ_REG(hw, EECD);
3931
3932 /* Isolate bits 15 & 16 */
3933 eecd = ((eecd >> 15) & 0x03);
3934
3935 /* If both bits are set, device is Flash type */
3936 if(eecd == 0x03) {
3937 return FALSE;
3938 }
3939 }
3940 return TRUE;
3941}
3942
3943/******************************************************************************
3572 * Verifies that the EEPROM has a valid checksum 3944 * Verifies that the EEPROM has a valid checksum
3573 * 3945 *
3574 * hw - Struct containing variables accessed by shared code 3946 * hw - Struct containing variables accessed by shared code
@@ -3585,6 +3957,25 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3585 3957
3586 DEBUGFUNC("e1000_validate_eeprom_checksum"); 3958 DEBUGFUNC("e1000_validate_eeprom_checksum");
3587 3959
3960 if ((hw->mac_type == e1000_82573) &&
3961 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
3962 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
3963 * 10h-12h. Checksum may need to be fixed. */
3964 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
3965 if ((eeprom_data & 0x10) == 0) {
3966 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
3967 * has already been fixed. If the checksum is still wrong and this
3968 * bit is a 1, we need to return bad checksum. Otherwise, we need
3969 * to set this bit to a 1 and update the checksum. */
3970 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
3971 if ((eeprom_data & 0x8000) == 0) {
3972 eeprom_data |= 0x8000;
3973 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
3974 e1000_update_eeprom_checksum(hw);
3975 }
3976 }
3977 }
3978
3588 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3979 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3589 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3980 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3590 DEBUGOUT("EEPROM Read Error\n"); 3981 DEBUGOUT("EEPROM Read Error\n");
@@ -3628,6 +4019,8 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
3628 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 4019 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3629 DEBUGOUT("EEPROM Write Error\n"); 4020 DEBUGOUT("EEPROM Write Error\n");
3630 return -E1000_ERR_EEPROM; 4021 return -E1000_ERR_EEPROM;
4022 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4023 e1000_commit_shadow_ram(hw);
3631 } 4024 }
3632 return E1000_SUCCESS; 4025 return E1000_SUCCESS;
3633} 4026}
@@ -3663,6 +4056,10 @@ e1000_write_eeprom(struct e1000_hw *hw,
3663 return -E1000_ERR_EEPROM; 4056 return -E1000_ERR_EEPROM;
3664 } 4057 }
3665 4058
4059 /* 82573 reads only through eerd */
4060 if(eeprom->use_eewr == TRUE)
4061 return e1000_write_eeprom_eewr(hw, offset, words, data);
4062
3666 /* Prepare the EEPROM for writing */ 4063 /* Prepare the EEPROM for writing */
3667 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4064 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3668 return -E1000_ERR_EEPROM; 4065 return -E1000_ERR_EEPROM;
@@ -3833,6 +4230,65 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
3833} 4230}
3834 4231
3835/****************************************************************************** 4232/******************************************************************************
4233 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4234 * in the eeprom cache and the non modified values in the currently active bank
4235 * to the new bank.
4236 *
4237 * hw - Struct containing variables accessed by shared code
4238 * offset - offset of word in the EEPROM to read
4239 * data - word read from the EEPROM
4240 * words - number of words to read
4241 *****************************************************************************/
4242int32_t
4243e1000_commit_shadow_ram(struct e1000_hw *hw)
4244{
4245 uint32_t attempts = 100000;
4246 uint32_t eecd = 0;
4247 uint32_t flop = 0;
4248 uint32_t i = 0;
4249 int32_t error = E1000_SUCCESS;
4250
4251 /* The flop register will be used to determine if flash type is STM */
4252 flop = E1000_READ_REG(hw, FLOP);
4253
4254 if (hw->mac_type == e1000_82573) {
4255 for (i=0; i < attempts; i++) {
4256 eecd = E1000_READ_REG(hw, EECD);
4257 if ((eecd & E1000_EECD_FLUPD) == 0) {
4258 break;
4259 }
4260 udelay(5);
4261 }
4262
4263 if (i == attempts) {
4264 return -E1000_ERR_EEPROM;
4265 }
4266
4267 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4268 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
4269 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
4270 }
4271
4272 /* Perform the flash update */
4273 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
4274
4275 for (i=0; i < attempts; i++) {
4276 eecd = E1000_READ_REG(hw, EECD);
4277 if ((eecd & E1000_EECD_FLUPD) == 0) {
4278 break;
4279 }
4280 udelay(5);
4281 }
4282
4283 if (i == attempts) {
4284 return -E1000_ERR_EEPROM;
4285 }
4286 }
4287
4288 return error;
4289}
4290
4291/******************************************************************************
3836 * Reads the adapter's part number from the EEPROM 4292 * Reads the adapter's part number from the EEPROM
3837 * 4293 *
3838 * hw - Struct containing variables accessed by shared code 4294 * hw - Struct containing variables accessed by shared code
@@ -3911,6 +4367,7 @@ void
3911e1000_init_rx_addrs(struct e1000_hw *hw) 4367e1000_init_rx_addrs(struct e1000_hw *hw)
3912{ 4368{
3913 uint32_t i; 4369 uint32_t i;
4370 uint32_t rar_num;
3914 4371
3915 DEBUGFUNC("e1000_init_rx_addrs"); 4372 DEBUGFUNC("e1000_init_rx_addrs");
3916 4373
@@ -3919,9 +4376,10 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
3919 4376
3920 e1000_rar_set(hw, hw->mac_addr, 0); 4377 e1000_rar_set(hw, hw->mac_addr, 0);
3921 4378
4379 rar_num = E1000_RAR_ENTRIES;
3922 /* Zero out the other 15 receive addresses. */ 4380 /* Zero out the other 15 receive addresses. */
3923 DEBUGOUT("Clearing RAR[1-15]\n"); 4381 DEBUGOUT("Clearing RAR[1-15]\n");
3924 for(i = 1; i < E1000_RAR_ENTRIES; i++) { 4382 for(i = 1; i < rar_num; i++) {
3925 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4383 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3926 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4384 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3927 } 4385 }
@@ -3950,7 +4408,9 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3950{ 4408{
3951 uint32_t hash_value; 4409 uint32_t hash_value;
3952 uint32_t i; 4410 uint32_t i;
3953 4411 uint32_t num_rar_entry;
4412 uint32_t num_mta_entry;
4413
3954 DEBUGFUNC("e1000_mc_addr_list_update"); 4414 DEBUGFUNC("e1000_mc_addr_list_update");
3955 4415
3956 /* Set the new number of MC addresses that we are being requested to use. */ 4416 /* Set the new number of MC addresses that we are being requested to use. */
@@ -3958,14 +4418,16 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3958 4418
3959 /* Clear RAR[1-15] */ 4419 /* Clear RAR[1-15] */
3960 DEBUGOUT(" Clearing RAR[1-15]\n"); 4420 DEBUGOUT(" Clearing RAR[1-15]\n");
3961 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) { 4421 num_rar_entry = E1000_RAR_ENTRIES;
4422 for(i = rar_used_count; i < num_rar_entry; i++) {
3962 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4423 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3963 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4424 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3964 } 4425 }
3965 4426
3966 /* Clear the MTA */ 4427 /* Clear the MTA */
3967 DEBUGOUT(" Clearing MTA\n"); 4428 DEBUGOUT(" Clearing MTA\n");
3968 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) { 4429 num_mta_entry = E1000_NUM_MTA_REGISTERS;
4430 for(i = 0; i < num_mta_entry; i++) {
3969 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 4431 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3970 } 4432 }
3971 4433
@@ -3989,7 +4451,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3989 /* Place this multicast address in the RAR if there is room, * 4451 /* Place this multicast address in the RAR if there is room, *
3990 * else put it in the MTA 4452 * else put it in the MTA
3991 */ 4453 */
3992 if(rar_used_count < E1000_RAR_ENTRIES) { 4454 if (rar_used_count < num_rar_entry) {
3993 e1000_rar_set(hw, 4455 e1000_rar_set(hw,
3994 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), 4456 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3995 rar_used_count); 4457 rar_used_count);
@@ -4040,6 +4502,7 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
4040 } 4502 }
4041 4503
4042 hash_value &= 0xFFF; 4504 hash_value &= 0xFFF;
4505
4043 return hash_value; 4506 return hash_value;
4044} 4507}
4045 4508
@@ -4144,12 +4607,33 @@ void
4144e1000_clear_vfta(struct e1000_hw *hw) 4607e1000_clear_vfta(struct e1000_hw *hw)
4145{ 4608{
4146 uint32_t offset; 4609 uint32_t offset;
4147 4610 uint32_t vfta_value = 0;
4148 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 4611 uint32_t vfta_offset = 0;
4149 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 4612 uint32_t vfta_bit_in_reg = 0;
4613
4614 if (hw->mac_type == e1000_82573) {
4615 if (hw->mng_cookie.vlan_id != 0) {
4616 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4617 * ID. The following operations determine which 32b entry
4618 * (i.e. offset) into the array we want to set the VLAN ID
4619 * (i.e. bit) of the manageability unit. */
4620 vfta_offset = (hw->mng_cookie.vlan_id >>
4621 E1000_VFTA_ENTRY_SHIFT) &
4622 E1000_VFTA_ENTRY_MASK;
4623 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
4624 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
4625 }
4626 }
4627 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4628 /* If the offset we want to clear is the same offset of the
4629 * manageability VLAN ID, then clear all bits except that of the
4630 * manageability unit */
4631 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4632 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4633 }
4150} 4634}
4151 4635
4152static int32_t 4636int32_t
4153e1000_id_led_init(struct e1000_hw * hw) 4637e1000_id_led_init(struct e1000_hw * hw)
4154{ 4638{
4155 uint32_t ledctl; 4639 uint32_t ledctl;
@@ -4480,6 +4964,19 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
4480 temp = E1000_READ_REG(hw, MGTPRC); 4964 temp = E1000_READ_REG(hw, MGTPRC);
4481 temp = E1000_READ_REG(hw, MGTPDC); 4965 temp = E1000_READ_REG(hw, MGTPDC);
4482 temp = E1000_READ_REG(hw, MGTPTC); 4966 temp = E1000_READ_REG(hw, MGTPTC);
4967
4968 if(hw->mac_type <= e1000_82547_rev_2) return;
4969
4970 temp = E1000_READ_REG(hw, IAC);
4971 temp = E1000_READ_REG(hw, ICRXOC);
4972 temp = E1000_READ_REG(hw, ICRXPTC);
4973 temp = E1000_READ_REG(hw, ICRXATC);
4974 temp = E1000_READ_REG(hw, ICTXPTC);
4975 temp = E1000_READ_REG(hw, ICTXATC);
4976 temp = E1000_READ_REG(hw, ICTXQEC);
4977 temp = E1000_READ_REG(hw, ICTXQMTC);
4978 temp = E1000_READ_REG(hw, ICRXDMTC);
4979
4483} 4980}
4484 4981
4485/****************************************************************************** 4982/******************************************************************************
@@ -4646,6 +5143,11 @@ e1000_get_bus_info(struct e1000_hw *hw)
4646 hw->bus_speed = e1000_bus_speed_unknown; 5143 hw->bus_speed = e1000_bus_speed_unknown;
4647 hw->bus_width = e1000_bus_width_unknown; 5144 hw->bus_width = e1000_bus_width_unknown;
4648 break; 5145 break;
5146 case e1000_82573:
5147 hw->bus_type = e1000_bus_type_pci_express;
5148 hw->bus_speed = e1000_bus_speed_2500;
5149 hw->bus_width = e1000_bus_width_pciex_4;
5150 break;
4649 default: 5151 default:
4650 status = E1000_READ_REG(hw, STATUS); 5152 status = E1000_READ_REG(hw, STATUS);
4651 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5153 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
@@ -4749,6 +5251,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
4749 5251
4750 /* Use old method for Phy older than IGP */ 5252 /* Use old method for Phy older than IGP */
4751 if(hw->phy_type == e1000_phy_m88) { 5253 if(hw->phy_type == e1000_phy_m88) {
5254
4752 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5255 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4753 &phy_data); 5256 &phy_data);
4754 if(ret_val) 5257 if(ret_val)
@@ -4865,7 +5368,8 @@ e1000_check_polarity(struct e1000_hw *hw,
4865 return ret_val; 5368 return ret_val;
4866 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 5369 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4867 M88E1000_PSSR_REV_POLARITY_SHIFT; 5370 M88E1000_PSSR_REV_POLARITY_SHIFT;
4868 } else if(hw->phy_type == e1000_phy_igp) { 5371 } else if(hw->phy_type == e1000_phy_igp ||
5372 hw->phy_type == e1000_phy_igp_2) {
4869 /* Read the Status register to check the speed */ 5373 /* Read the Status register to check the speed */
4870 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 5374 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4871 &phy_data); 5375 &phy_data);
@@ -4917,7 +5421,8 @@ e1000_check_downshift(struct e1000_hw *hw)
4917 5421
4918 DEBUGFUNC("e1000_check_downshift"); 5422 DEBUGFUNC("e1000_check_downshift");
4919 5423
4920 if(hw->phy_type == e1000_phy_igp) { 5424 if(hw->phy_type == e1000_phy_igp ||
5425 hw->phy_type == e1000_phy_igp_2) {
4921 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5426 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4922 &phy_data); 5427 &phy_data);
4923 if(ret_val) 5428 if(ret_val)
@@ -4933,6 +5438,7 @@ e1000_check_downshift(struct e1000_hw *hw)
4933 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5438 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4934 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5439 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4935 } 5440 }
5441
4936 return E1000_SUCCESS; 5442 return E1000_SUCCESS;
4937} 5443}
4938 5444
@@ -5047,7 +5553,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5047 if(ret_val) 5553 if(ret_val)
5048 return ret_val; 5554 return ret_val;
5049 5555
5050 msec_delay(20); 5556 msec_delay_irq(20);
5051 5557
5052 ret_val = e1000_write_phy_reg(hw, 0x0000, 5558 ret_val = e1000_write_phy_reg(hw, 0x0000,
5053 IGP01E1000_IEEE_FORCE_GIGA); 5559 IGP01E1000_IEEE_FORCE_GIGA);
@@ -5071,7 +5577,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5071 if(ret_val) 5577 if(ret_val)
5072 return ret_val; 5578 return ret_val;
5073 5579
5074 msec_delay(20); 5580 msec_delay_irq(20);
5075 5581
5076 /* Now enable the transmitter */ 5582 /* Now enable the transmitter */
5077 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5583 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
@@ -5096,7 +5602,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5096 if(ret_val) 5602 if(ret_val)
5097 return ret_val; 5603 return ret_val;
5098 5604
5099 msec_delay(20); 5605 msec_delay_irq(20);
5100 5606
5101 ret_val = e1000_write_phy_reg(hw, 0x0000, 5607 ret_val = e1000_write_phy_reg(hw, 0x0000,
5102 IGP01E1000_IEEE_FORCE_GIGA); 5608 IGP01E1000_IEEE_FORCE_GIGA);
@@ -5112,7 +5618,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5112 if(ret_val) 5618 if(ret_val)
5113 return ret_val; 5619 return ret_val;
5114 5620
5115 msec_delay(20); 5621 msec_delay_irq(20);
5116 5622
5117 /* Now enable the transmitter */ 5623 /* Now enable the transmitter */
5118 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5624 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
@@ -5187,22 +5693,36 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
5187 uint16_t phy_data; 5693 uint16_t phy_data;
5188 DEBUGFUNC("e1000_set_d3_lplu_state"); 5694 DEBUGFUNC("e1000_set_d3_lplu_state");
5189 5695
5190 if(!((hw->mac_type == e1000_82541_rev_2) || 5696 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2)
5191 (hw->mac_type == e1000_82547_rev_2)))
5192 return E1000_SUCCESS; 5697 return E1000_SUCCESS;
5193 5698
5194 /* During driver activity LPLU should not be used or it will attain link 5699 /* During driver activity LPLU should not be used or it will attain link
5195 * from the lowest speeds starting from 10Mbps. The capability is used for 5700 * from the lowest speeds starting from 10Mbps. The capability is used for
5196 * Dx transitions and states */ 5701 * Dx transitions and states */
5197 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5702 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
5198 if(ret_val) 5703 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5199 return ret_val;
5200
5201 if(!active) {
5202 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5203 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5204 if(ret_val) 5704 if(ret_val)
5205 return ret_val; 5705 return ret_val;
5706 } else {
5707 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5708 if(ret_val)
5709 return ret_val;
5710 }
5711
5712 if(!active) {
5713 if(hw->mac_type == e1000_82541_rev_2 ||
5714 hw->mac_type == e1000_82547_rev_2) {
5715 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5716 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5717 if(ret_val)
5718 return ret_val;
5719 } else {
5720 phy_data &= ~IGP02E1000_PM_D3_LPLU;
5721 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5722 phy_data);
5723 if (ret_val)
5724 return ret_val;
5725 }
5206 5726
5207 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 5727 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5208 * Dx states where the power conservation is most important. During 5728 * Dx states where the power conservation is most important. During
@@ -5236,11 +5756,105 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
5236 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || 5756 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5237 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 5757 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5238 5758
5239 phy_data |= IGP01E1000_GMII_FLEX_SPD; 5759 if(hw->mac_type == e1000_82541_rev_2 ||
5240 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 5760 hw->mac_type == e1000_82547_rev_2) {
5761 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5762 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5763 if(ret_val)
5764 return ret_val;
5765 } else {
5766 phy_data |= IGP02E1000_PM_D3_LPLU;
5767 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5768 phy_data);
5769 if (ret_val)
5770 return ret_val;
5771 }
5772
5773 /* When LPLU is enabled we should disable SmartSpeed */
5774 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5775 if(ret_val)
5776 return ret_val;
5777
5778 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5779 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5241 if(ret_val) 5780 if(ret_val)
5242 return ret_val; 5781 return ret_val;
5243 5782
5783 }
5784 return E1000_SUCCESS;
5785}
5786
5787/*****************************************************************************
5788 *
5789 * This function sets the lplu d0 state according to the active flag. When
5790 * activating lplu this function also disables smart speed and vise versa.
5791 * lplu will not be activated unless the device autonegotiation advertisment
5792 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5793 * hw: Struct containing variables accessed by shared code
5794 * active - true to enable lplu false to disable lplu.
5795 *
5796 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5797 * E1000_SUCCESS at any other case.
5798 *
5799 ****************************************************************************/
5800
5801int32_t
5802e1000_set_d0_lplu_state(struct e1000_hw *hw,
5803 boolean_t active)
5804{
5805 int32_t ret_val;
5806 uint16_t phy_data;
5807 DEBUGFUNC("e1000_set_d0_lplu_state");
5808
5809 if(hw->mac_type <= e1000_82547_rev_2)
5810 return E1000_SUCCESS;
5811
5812 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5813 if(ret_val)
5814 return ret_val;
5815
5816 if (!active) {
5817 phy_data &= ~IGP02E1000_PM_D0_LPLU;
5818 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5819 if (ret_val)
5820 return ret_val;
5821
5822 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5823 * Dx states where the power conservation is most important. During
5824 * driver activity we should enable SmartSpeed, so performance is
5825 * maintained. */
5826 if (hw->smart_speed == e1000_smart_speed_on) {
5827 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5828 &phy_data);
5829 if(ret_val)
5830 return ret_val;
5831
5832 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5833 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5834 phy_data);
5835 if(ret_val)
5836 return ret_val;
5837 } else if (hw->smart_speed == e1000_smart_speed_off) {
5838 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5839 &phy_data);
5840 if (ret_val)
5841 return ret_val;
5842
5843 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5844 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5845 phy_data);
5846 if(ret_val)
5847 return ret_val;
5848 }
5849
5850
5851 } else {
5852
5853 phy_data |= IGP02E1000_PM_D0_LPLU;
5854 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5855 if (ret_val)
5856 return ret_val;
5857
5244 /* When LPLU is enabled we should disable SmartSpeed */ 5858 /* When LPLU is enabled we should disable SmartSpeed */
5245 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 5859 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5246 if(ret_val) 5860 if(ret_val)
@@ -5318,6 +5932,338 @@ e1000_set_vco_speed(struct e1000_hw *hw)
5318 return E1000_SUCCESS; 5932 return E1000_SUCCESS;
5319} 5933}
5320 5934
5935
5936/*****************************************************************************
5937 * This function reads the cookie from ARC ram.
5938 *
5939 * returns: - E1000_SUCCESS .
5940 ****************************************************************************/
5941int32_t
5942e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
5943{
5944 uint8_t i;
5945 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
5946 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
5947
5948 length = (length >> 2);
5949 offset = (offset >> 2);
5950
5951 for (i = 0; i < length; i++) {
5952 *((uint32_t *) buffer + i) =
5953 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
5954 }
5955 return E1000_SUCCESS;
5956}
5957
5958
5959/*****************************************************************************
5960 * This function checks whether the HOST IF is enabled for command operaton
5961 * and also checks whether the previous command is completed.
5962 * It busy waits in case of previous command is not completed.
5963 *
5964 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
5965 * timeout
5966 * - E1000_SUCCESS for success.
5967 ****************************************************************************/
5968int32_t
5969e1000_mng_enable_host_if(struct e1000_hw * hw)
5970{
5971 uint32_t hicr;
5972 uint8_t i;
5973
5974 /* Check that the host interface is enabled. */
5975 hicr = E1000_READ_REG(hw, HICR);
5976 if ((hicr & E1000_HICR_EN) == 0) {
5977 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
5978 return -E1000_ERR_HOST_INTERFACE_COMMAND;
5979 }
5980 /* check the previous command is completed */
5981 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
5982 hicr = E1000_READ_REG(hw, HICR);
5983 if (!(hicr & E1000_HICR_C))
5984 break;
5985 msec_delay_irq(1);
5986 }
5987
5988 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
5989 DEBUGOUT("Previous command timeout failed .\n");
5990 return -E1000_ERR_HOST_INTERFACE_COMMAND;
5991 }
5992 return E1000_SUCCESS;
5993}
5994
5995/*****************************************************************************
5996 * This function writes the buffer content at the offset given on the host if.
5997 * It also does alignment considerations to do the writes in most efficient way.
5998 * Also fills up the sum of the buffer in *buffer parameter.
5999 *
6000 * returns - E1000_SUCCESS for success.
6001 ****************************************************************************/
6002int32_t
6003e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
6004 uint16_t length, uint16_t offset, uint8_t *sum)
6005{
6006 uint8_t *tmp;
6007 uint8_t *bufptr = buffer;
6008 uint32_t data;
6009 uint16_t remaining, i, j, prev_bytes;
6010
6011 /* sum = only sum of the data and it is not checksum */
6012
6013 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
6014 return -E1000_ERR_PARAM;
6015 }
6016
6017 tmp = (uint8_t *)&data;
6018 prev_bytes = offset & 0x3;
6019 offset &= 0xFFFC;
6020 offset >>= 2;
6021
6022 if (prev_bytes) {
6023 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
6024 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
6025 *(tmp + j) = *bufptr++;
6026 *sum += *(tmp + j);
6027 }
6028 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
6029 length -= j - prev_bytes;
6030 offset++;
6031 }
6032
6033 remaining = length & 0x3;
6034 length -= remaining;
6035
6036 /* Calculate length in DWORDs */
6037 length >>= 2;
6038
6039 /* The device driver writes the relevant command block into the
6040 * ram area. */
6041 for (i = 0; i < length; i++) {
6042 for (j = 0; j < sizeof(uint32_t); j++) {
6043 *(tmp + j) = *bufptr++;
6044 *sum += *(tmp + j);
6045 }
6046
6047 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6048 }
6049 if (remaining) {
6050 for (j = 0; j < sizeof(uint32_t); j++) {
6051 if (j < remaining)
6052 *(tmp + j) = *bufptr++;
6053 else
6054 *(tmp + j) = 0;
6055
6056 *sum += *(tmp + j);
6057 }
6058 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6059 }
6060
6061 return E1000_SUCCESS;
6062}
6063
6064
6065/*****************************************************************************
6066 * This function writes the command header after does the checksum calculation.
6067 *
6068 * returns - E1000_SUCCESS for success.
6069 ****************************************************************************/
6070int32_t
6071e1000_mng_write_cmd_header(struct e1000_hw * hw,
6072 struct e1000_host_mng_command_header * hdr)
6073{
6074 uint16_t i;
6075 uint8_t sum;
6076 uint8_t *buffer;
6077
6078 /* Write the whole command header structure which includes sum of
6079 * the buffer */
6080
6081 uint16_t length = sizeof(struct e1000_host_mng_command_header);
6082
6083 sum = hdr->checksum;
6084 hdr->checksum = 0;
6085
6086 buffer = (uint8_t *) hdr;
6087 i = length;
6088 while(i--)
6089 sum += buffer[i];
6090
6091 hdr->checksum = 0 - sum;
6092
6093 length >>= 2;
6094 /* The device driver writes the relevant command block into the ram area. */
6095 for (i = 0; i < length; i++)
6096 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
6097
6098 return E1000_SUCCESS;
6099}
6100
6101
6102/*****************************************************************************
6103 * This function indicates to ARC that a new command is pending which completes
6104 * one write operation by the driver.
6105 *
6106 * returns - E1000_SUCCESS for success.
6107 ****************************************************************************/
6108int32_t
6109e1000_mng_write_commit(
6110 struct e1000_hw * hw)
6111{
6112 uint32_t hicr;
6113
6114 hicr = E1000_READ_REG(hw, HICR);
6115 /* Setting this bit tells the ARC that a new command is pending. */
6116 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
6117
6118 return E1000_SUCCESS;
6119}
6120
6121
6122/*****************************************************************************
6123 * This function checks the mode of the firmware.
6124 *
6125 * returns - TRUE when the mode is IAMT or FALSE.
6126 ****************************************************************************/
6127boolean_t
6128e1000_check_mng_mode(
6129 struct e1000_hw *hw)
6130{
6131 uint32_t fwsm;
6132
6133 fwsm = E1000_READ_REG(hw, FWSM);
6134
6135 if((fwsm & E1000_FWSM_MODE_MASK) ==
6136 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6137 return TRUE;
6138
6139 return FALSE;
6140}
6141
6142
6143/*****************************************************************************
6144 * This function writes the dhcp info .
6145 ****************************************************************************/
6146int32_t
6147e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
6148 uint16_t length)
6149{
6150 int32_t ret_val;
6151 struct e1000_host_mng_command_header hdr;
6152
6153 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
6154 hdr.command_length = length;
6155 hdr.reserved1 = 0;
6156 hdr.reserved2 = 0;
6157 hdr.checksum = 0;
6158
6159 ret_val = e1000_mng_enable_host_if(hw);
6160 if (ret_val == E1000_SUCCESS) {
6161 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
6162 &(hdr.checksum));
6163 if (ret_val == E1000_SUCCESS) {
6164 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
6165 if (ret_val == E1000_SUCCESS)
6166 ret_val = e1000_mng_write_commit(hw);
6167 }
6168 }
6169 return ret_val;
6170}
6171
6172
6173/*****************************************************************************
6174 * This function calculates the checksum.
6175 *
6176 * returns - checksum of buffer contents.
6177 ****************************************************************************/
6178uint8_t
6179e1000_calculate_mng_checksum(char *buffer, uint32_t length)
6180{
6181 uint8_t sum = 0;
6182 uint32_t i;
6183
6184 if (!buffer)
6185 return 0;
6186
6187 for (i=0; i < length; i++)
6188 sum += buffer[i];
6189
6190 return (uint8_t) (0 - sum);
6191}
6192
6193/*****************************************************************************
6194 * This function checks whether tx pkt filtering needs to be enabled or not.
6195 *
6196 * returns - TRUE for packet filtering or FALSE.
6197 ****************************************************************************/
6198boolean_t
6199e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
6200{
6201 /* called in init as well as watchdog timer functions */
6202
6203 int32_t ret_val, checksum;
6204 boolean_t tx_filter = FALSE;
6205 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
6206 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
6207
6208 if (e1000_check_mng_mode(hw)) {
6209 ret_val = e1000_mng_enable_host_if(hw);
6210 if (ret_val == E1000_SUCCESS) {
6211 ret_val = e1000_host_if_read_cookie(hw, buffer);
6212 if (ret_val == E1000_SUCCESS) {
6213 checksum = hdr->checksum;
6214 hdr->checksum = 0;
6215 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
6216 checksum == e1000_calculate_mng_checksum((char *)buffer,
6217 E1000_MNG_DHCP_COOKIE_LENGTH)) {
6218 if (hdr->status &
6219 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
6220 tx_filter = TRUE;
6221 } else
6222 tx_filter = TRUE;
6223 } else
6224 tx_filter = TRUE;
6225 }
6226 }
6227
6228 hw->tx_pkt_filtering = tx_filter;
6229 return tx_filter;
6230}
6231
6232/******************************************************************************
6233 * Verifies the hardware needs to allow ARPs to be processed by the host
6234 *
6235 * hw - Struct containing variables accessed by shared code
6236 *
6237 * returns: - TRUE/FALSE
6238 *
6239 *****************************************************************************/
6240uint32_t
6241e1000_enable_mng_pass_thru(struct e1000_hw *hw)
6242{
6243 uint32_t manc;
6244 uint32_t fwsm, factps;
6245
6246 if (hw->asf_firmware_present) {
6247 manc = E1000_READ_REG(hw, MANC);
6248
6249 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
6250 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
6251 return FALSE;
6252 if (e1000_arc_subsystem_valid(hw) == TRUE) {
6253 fwsm = E1000_READ_REG(hw, FWSM);
6254 factps = E1000_READ_REG(hw, FACTPS);
6255
6256 if (((fwsm & E1000_FWSM_MODE_MASK) ==
6257 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
6258 (factps & E1000_FACTPS_MNGCG))
6259 return TRUE;
6260 } else
6261 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
6262 return TRUE;
6263 }
6264 return FALSE;
6265}
6266
5321static int32_t 6267static int32_t
5322e1000_polarity_reversal_workaround(struct e1000_hw *hw) 6268e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5323{ 6269{
@@ -5403,3 +6349,265 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5403 return E1000_SUCCESS; 6349 return E1000_SUCCESS;
5404} 6350}
5405 6351
6352/***************************************************************************
6353 *
6354 * Disables PCI-Express master access.
6355 *
6356 * hw: Struct containing variables accessed by shared code
6357 *
6358 * returns: - none.
6359 *
6360 ***************************************************************************/
6361void
6362e1000_set_pci_express_master_disable(struct e1000_hw *hw)
6363{
6364 uint32_t ctrl;
6365
6366 DEBUGFUNC("e1000_set_pci_express_master_disable");
6367
6368 if (hw->bus_type != e1000_bus_type_pci_express)
6369 return;
6370
6371 ctrl = E1000_READ_REG(hw, CTRL);
6372 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
6373 E1000_WRITE_REG(hw, CTRL, ctrl);
6374}
6375
6376/***************************************************************************
6377 *
6378 * Enables PCI-Express master access.
6379 *
6380 * hw: Struct containing variables accessed by shared code
6381 *
6382 * returns: - none.
6383 *
6384 ***************************************************************************/
6385void
6386e1000_enable_pciex_master(struct e1000_hw *hw)
6387{
6388 uint32_t ctrl;
6389
6390 DEBUGFUNC("e1000_enable_pciex_master");
6391
6392 if (hw->bus_type != e1000_bus_type_pci_express)
6393 return;
6394
6395 ctrl = E1000_READ_REG(hw, CTRL);
6396 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
6397 E1000_WRITE_REG(hw, CTRL, ctrl);
6398}
6399
6400/*******************************************************************************
6401 *
6402 * Disables PCI-Express master access and verifies there are no pending requests
6403 *
6404 * hw: Struct containing variables accessed by shared code
6405 *
6406 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6407 * caused the master requests to be disabled.
6408 * E1000_SUCCESS master requests disabled.
6409 *
6410 ******************************************************************************/
6411int32_t
6412e1000_disable_pciex_master(struct e1000_hw *hw)
6413{
6414 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
6415
6416 DEBUGFUNC("e1000_disable_pciex_master");
6417
6418 if (hw->bus_type != e1000_bus_type_pci_express)
6419 return E1000_SUCCESS;
6420
6421 e1000_set_pci_express_master_disable(hw);
6422
6423 while(timeout) {
6424 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
6425 break;
6426 else
6427 udelay(100);
6428 timeout--;
6429 }
6430
6431 if(!timeout) {
6432 DEBUGOUT("Master requests are pending.\n");
6433 return -E1000_ERR_MASTER_REQUESTS_PENDING;
6434 }
6435
6436 return E1000_SUCCESS;
6437}
6438
6439/*******************************************************************************
6440 *
6441 * Check for EEPROM Auto Read bit done.
6442 *
6443 * hw: Struct containing variables accessed by shared code
6444 *
6445 * returns: - E1000_ERR_RESET if fail to reset MAC
6446 * E1000_SUCCESS at any other case.
6447 *
6448 ******************************************************************************/
6449int32_t
6450e1000_get_auto_rd_done(struct e1000_hw *hw)
6451{
6452 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
6453
6454 DEBUGFUNC("e1000_get_auto_rd_done");
6455
6456 switch (hw->mac_type) {
6457 default:
6458 msec_delay(5);
6459 break;
6460 case e1000_82573:
6461 while(timeout) {
6462 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
6463 else msec_delay(1);
6464 timeout--;
6465 }
6466
6467 if(!timeout) {
6468 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6469 return -E1000_ERR_RESET;
6470 }
6471 break;
6472 }
6473
6474 return E1000_SUCCESS;
6475}
6476
6477/***************************************************************************
6478 * Checks if the PHY configuration is done
6479 *
6480 * hw: Struct containing variables accessed by shared code
6481 *
6482 * returns: - E1000_ERR_RESET if fail to reset MAC
6483 * E1000_SUCCESS at any other case.
6484 *
6485 ***************************************************************************/
6486int32_t
6487e1000_get_phy_cfg_done(struct e1000_hw *hw)
6488{
6489 DEBUGFUNC("e1000_get_phy_cfg_done");
6490
6491 /* Simply wait for 10ms */
6492 msec_delay(10);
6493
6494 return E1000_SUCCESS;
6495}
6496
6497/***************************************************************************
6498 *
6499 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6500 * adapter or Eeprom access.
6501 *
6502 * hw: Struct containing variables accessed by shared code
6503 *
6504 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6505 * E1000_SUCCESS at any other case.
6506 *
6507 ***************************************************************************/
6508int32_t
6509e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
6510{
6511 int32_t timeout;
6512 uint32_t swsm;
6513
6514 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
6515
6516 if(!hw->eeprom_semaphore_present)
6517 return E1000_SUCCESS;
6518
6519
6520 /* Get the FW semaphore. */
6521 timeout = hw->eeprom.word_size + 1;
6522 while(timeout) {
6523 swsm = E1000_READ_REG(hw, SWSM);
6524 swsm |= E1000_SWSM_SWESMBI;
6525 E1000_WRITE_REG(hw, SWSM, swsm);
6526 /* if we managed to set the bit we got the semaphore. */
6527 swsm = E1000_READ_REG(hw, SWSM);
6528 if(swsm & E1000_SWSM_SWESMBI)
6529 break;
6530
6531 udelay(50);
6532 timeout--;
6533 }
6534
6535 if(!timeout) {
6536 /* Release semaphores */
6537 e1000_put_hw_eeprom_semaphore(hw);
6538 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6539 return -E1000_ERR_EEPROM;
6540 }
6541
6542 return E1000_SUCCESS;
6543}
6544
6545/***************************************************************************
6546 * This function clears HW semaphore bits.
6547 *
6548 * hw: Struct containing variables accessed by shared code
6549 *
6550 * returns: - None.
6551 *
6552 ***************************************************************************/
6553void
6554e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
6555{
6556 uint32_t swsm;
6557
6558 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
6559
6560 if(!hw->eeprom_semaphore_present)
6561 return;
6562
6563 swsm = E1000_READ_REG(hw, SWSM);
6564 /* Release both semaphores. */
6565 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
6566 E1000_WRITE_REG(hw, SWSM, swsm);
6567}
6568
6569/******************************************************************************
6570 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6571 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
6572 * the caller to figure out how to deal with it.
6573 *
6574 * hw - Struct containing variables accessed by shared code
6575 *
6576 * returns: - E1000_BLK_PHY_RESET
6577 * E1000_SUCCESS
6578 *
6579 *****************************************************************************/
6580int32_t
6581e1000_check_phy_reset_block(struct e1000_hw *hw)
6582{
6583 uint32_t manc = 0;
6584 if(hw->mac_type > e1000_82547_rev_2)
6585 manc = E1000_READ_REG(hw, MANC);
6586 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
6587 E1000_BLK_PHY_RESET : E1000_SUCCESS;
6588}
6589
6590uint8_t
6591e1000_arc_subsystem_valid(struct e1000_hw *hw)
6592{
6593 uint32_t fwsm;
6594
6595 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6596 * may not be provided a DMA clock when no manageability features are
6597 * enabled. We do not want to perform any reads/writes to these registers
6598 * if this is the case. We read FWSM to determine the manageability mode.
6599 */
6600 switch (hw->mac_type) {
6601 case e1000_82573:
6602 fwsm = E1000_READ_REG(hw, FWSM);
6603 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
6604 return TRUE;
6605 break;
6606 default:
6607 break;
6608 }
6609 return FALSE;
6610}
6611
6612
6613
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index f397e637a3c5..1573f608fb68 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -57,6 +57,7 @@ typedef enum {
57 e1000_82541_rev_2, 57 e1000_82541_rev_2,
58 e1000_82547, 58 e1000_82547,
59 e1000_82547_rev_2, 59 e1000_82547_rev_2,
60 e1000_82573,
60 e1000_num_macs 61 e1000_num_macs
61} e1000_mac_type; 62} e1000_mac_type;
62 63
@@ -64,6 +65,7 @@ typedef enum {
64 e1000_eeprom_uninitialized = 0, 65 e1000_eeprom_uninitialized = 0,
65 e1000_eeprom_spi, 66 e1000_eeprom_spi,
66 e1000_eeprom_microwire, 67 e1000_eeprom_microwire,
68 e1000_eeprom_flash,
67 e1000_num_eeprom_types 69 e1000_num_eeprom_types
68} e1000_eeprom_type; 70} e1000_eeprom_type;
69 71
@@ -96,6 +98,7 @@ typedef enum {
96 e1000_bus_type_unknown = 0, 98 e1000_bus_type_unknown = 0,
97 e1000_bus_type_pci, 99 e1000_bus_type_pci,
98 e1000_bus_type_pcix, 100 e1000_bus_type_pcix,
101 e1000_bus_type_pci_express,
99 e1000_bus_type_reserved 102 e1000_bus_type_reserved
100} e1000_bus_type; 103} e1000_bus_type;
101 104
@@ -107,6 +110,7 @@ typedef enum {
107 e1000_bus_speed_100, 110 e1000_bus_speed_100,
108 e1000_bus_speed_120, 111 e1000_bus_speed_120,
109 e1000_bus_speed_133, 112 e1000_bus_speed_133,
113 e1000_bus_speed_2500,
110 e1000_bus_speed_reserved 114 e1000_bus_speed_reserved
111} e1000_bus_speed; 115} e1000_bus_speed;
112 116
@@ -115,6 +119,8 @@ typedef enum {
115 e1000_bus_width_unknown = 0, 119 e1000_bus_width_unknown = 0,
116 e1000_bus_width_32, 120 e1000_bus_width_32,
117 e1000_bus_width_64, 121 e1000_bus_width_64,
122 e1000_bus_width_pciex_1,
123 e1000_bus_width_pciex_4,
118 e1000_bus_width_reserved 124 e1000_bus_width_reserved
119} e1000_bus_width; 125} e1000_bus_width;
120 126
@@ -196,6 +202,7 @@ typedef enum {
196typedef enum { 202typedef enum {
197 e1000_phy_m88 = 0, 203 e1000_phy_m88 = 0,
198 e1000_phy_igp, 204 e1000_phy_igp,
205 e1000_phy_igp_2,
199 e1000_phy_undefined = 0xFF 206 e1000_phy_undefined = 0xFF
200} e1000_phy_type; 207} e1000_phy_type;
201 208
@@ -242,8 +249,19 @@ struct e1000_eeprom_info {
242 uint16_t address_bits; 249 uint16_t address_bits;
243 uint16_t delay_usec; 250 uint16_t delay_usec;
244 uint16_t page_size; 251 uint16_t page_size;
252 boolean_t use_eerd;
253 boolean_t use_eewr;
245}; 254};
246 255
256/* Flex ASF Information */
257#define E1000_HOST_IF_MAX_SIZE 2048
258
259typedef enum {
260 e1000_byte_align = 0,
261 e1000_word_align = 1,
262 e1000_dword_align = 2
263} e1000_align_type;
264
247 265
248 266
249/* Error Codes */ 267/* Error Codes */
@@ -254,11 +272,16 @@ struct e1000_eeprom_info {
254#define E1000_ERR_PARAM 4 272#define E1000_ERR_PARAM 4
255#define E1000_ERR_MAC_TYPE 5 273#define E1000_ERR_MAC_TYPE 5
256#define E1000_ERR_PHY_TYPE 6 274#define E1000_ERR_PHY_TYPE 6
275#define E1000_ERR_RESET 9
276#define E1000_ERR_MASTER_REQUESTS_PENDING 10
277#define E1000_ERR_HOST_INTERFACE_COMMAND 11
278#define E1000_BLK_PHY_RESET 12
257 279
258/* Function prototypes */ 280/* Function prototypes */
259/* Initialization */ 281/* Initialization */
260int32_t e1000_reset_hw(struct e1000_hw *hw); 282int32_t e1000_reset_hw(struct e1000_hw *hw);
261int32_t e1000_init_hw(struct e1000_hw *hw); 283int32_t e1000_init_hw(struct e1000_hw *hw);
284int32_t e1000_id_led_init(struct e1000_hw * hw);
262int32_t e1000_set_mac_type(struct e1000_hw *hw); 285int32_t e1000_set_mac_type(struct e1000_hw *hw);
263void e1000_set_media_type(struct e1000_hw *hw); 286void e1000_set_media_type(struct e1000_hw *hw);
264 287
@@ -275,7 +298,7 @@ int32_t e1000_force_mac_fc(struct e1000_hw *hw);
275/* PHY */ 298/* PHY */
276int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data); 299int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
277int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 300int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
278void e1000_phy_hw_reset(struct e1000_hw *hw); 301int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
279int32_t e1000_phy_reset(struct e1000_hw *hw); 302int32_t e1000_phy_reset(struct e1000_hw *hw);
280int32_t e1000_detect_gig_phy(struct e1000_hw *hw); 303int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
281int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 304int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
@@ -287,13 +310,86 @@ int32_t e1000_check_downshift(struct e1000_hw *hw);
287int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 310int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
288 311
289/* EEPROM Functions */ 312/* EEPROM Functions */
290void e1000_init_eeprom_params(struct e1000_hw *hw); 313int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
314boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
315int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
316int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
317int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
318
319/* MNG HOST IF functions */
320uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
321
322#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
323#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
324
325#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
326#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
327#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
328#define E1000_MNG_IAMT_MODE 0x3
329#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
330
331#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
332#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
333#define E1000_VFTA_ENTRY_SHIFT 0x5
334#define E1000_VFTA_ENTRY_MASK 0x7F
335#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
336
337struct e1000_host_mng_command_header {
338 uint8_t command_id;
339 uint8_t checksum;
340 uint16_t reserved1;
341 uint16_t reserved2;
342 uint16_t command_length;
343};
344
345struct e1000_host_mng_command_info {
346 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
347 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
348};
349#ifdef __BIG_ENDIAN
350struct e1000_host_mng_dhcp_cookie{
351 uint32_t signature;
352 uint16_t vlan_id;
353 uint8_t reserved0;
354 uint8_t status;
355 uint32_t reserved1;
356 uint8_t checksum;
357 uint8_t reserved3;
358 uint16_t reserved2;
359};
360#else
361struct e1000_host_mng_dhcp_cookie{
362 uint32_t signature;
363 uint8_t status;
364 uint8_t reserved0;
365 uint16_t vlan_id;
366 uint32_t reserved1;
367 uint16_t reserved2;
368 uint8_t reserved3;
369 uint8_t checksum;
370};
371#endif
372
373int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
374 uint16_t length);
375boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
376boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
377int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
378int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer,
379 uint16_t length, uint16_t offset, uint8_t *sum);
380int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw,
381 struct e1000_host_mng_command_header* hdr);
382
383int32_t e1000_mng_write_commit(struct e1000_hw *hw);
384
291int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 385int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
292int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw); 386int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
293int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw); 387int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
294int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 388int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
295int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num); 389int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
296int32_t e1000_read_mac_addr(struct e1000_hw * hw); 390int32_t e1000_read_mac_addr(struct e1000_hw * hw);
391int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
392void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
297 393
298/* Filters (multicast, vlan, receive) */ 394/* Filters (multicast, vlan, receive) */
299void e1000_init_rx_addrs(struct e1000_hw *hw); 395void e1000_init_rx_addrs(struct e1000_hw *hw);
@@ -313,7 +409,6 @@ int32_t e1000_led_off(struct e1000_hw *hw);
313/* Adaptive IFS Functions */ 409/* Adaptive IFS Functions */
314 410
315/* Everything else */ 411/* Everything else */
316uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
317void e1000_clear_hw_cntrs(struct e1000_hw *hw); 412void e1000_clear_hw_cntrs(struct e1000_hw *hw);
318void e1000_reset_adaptive(struct e1000_hw *hw); 413void e1000_reset_adaptive(struct e1000_hw *hw);
319void e1000_update_adaptive(struct e1000_hw *hw); 414void e1000_update_adaptive(struct e1000_hw *hw);
@@ -330,6 +425,19 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
330void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); 425void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
331int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); 426int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
332int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); 427int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
428int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
429void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
430void e1000_enable_pciex_master(struct e1000_hw *hw);
431int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
432int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
433int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
434int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
435void e1000_release_software_semaphore(struct e1000_hw *hw);
436int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
437int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
438void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
439int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
440uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
333 441
334#define E1000_READ_REG_IO(a, reg) \ 442#define E1000_READ_REG_IO(a, reg) \
335 e1000_read_reg_io((a), E1000_##reg) 443 e1000_read_reg_io((a), E1000_##reg)
@@ -369,6 +477,10 @@ int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
369#define E1000_DEV_ID_82546GB_SERDES 0x107B 477#define E1000_DEV_ID_82546GB_SERDES 0x107B
370#define E1000_DEV_ID_82546GB_PCIE 0x108A 478#define E1000_DEV_ID_82546GB_PCIE 0x108A
371#define E1000_DEV_ID_82547EI 0x1019 479#define E1000_DEV_ID_82547EI 0x1019
480#define E1000_DEV_ID_82573E 0x108B
481#define E1000_DEV_ID_82573E_IAMT 0x108C
482
483#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
372 484
373#define NODE_ADDRESS_SIZE 6 485#define NODE_ADDRESS_SIZE 6
374#define ETH_LENGTH_OF_ADDRESS 6 486#define ETH_LENGTH_OF_ADDRESS 6
@@ -381,6 +493,7 @@ int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
381#define E1000_REVISION_0 0 493#define E1000_REVISION_0 0
382#define E1000_REVISION_1 1 494#define E1000_REVISION_1 1
383#define E1000_REVISION_2 2 495#define E1000_REVISION_2 2
496#define E1000_REVISION_3 3
384 497
385#define SPEED_10 10 498#define SPEED_10 10
386#define SPEED_100 100 499#define SPEED_100 100
@@ -437,6 +550,7 @@ int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
437 E1000_IMS_RXSEQ | \ 550 E1000_IMS_RXSEQ | \
438 E1000_IMS_LSC) 551 E1000_IMS_LSC)
439 552
553
440/* Number of high/low register pairs in the RAR. The RAR (Receive Address 554/* Number of high/low register pairs in the RAR. The RAR (Receive Address
441 * Registers) holds the directed and multicast addresses that we monitor. We 555 * Registers) holds the directed and multicast addresses that we monitor. We
442 * reserve one of these spots for our directed address, allowing us room for 556 * reserve one of these spots for our directed address, allowing us room for
@@ -457,14 +571,74 @@ struct e1000_rx_desc {
457 uint16_t special; 571 uint16_t special;
458}; 572};
459 573
574/* Receive Descriptor - Extended */
575union e1000_rx_desc_extended {
576 struct {
577 uint64_t buffer_addr;
578 uint64_t reserved;
579 } read;
580 struct {
581 struct {
582 uint32_t mrq; /* Multiple Rx Queues */
583 union {
584 uint32_t rss; /* RSS Hash */
585 struct {
586 uint16_t ip_id; /* IP id */
587 uint16_t csum; /* Packet Checksum */
588 } csum_ip;
589 } hi_dword;
590 } lower;
591 struct {
592 uint32_t status_error; /* ext status/error */
593 uint16_t length;
594 uint16_t vlan; /* VLAN tag */
595 } upper;
596 } wb; /* writeback */
597};
598
599#define MAX_PS_BUFFERS 4
600/* Receive Descriptor - Packet Split */
601union e1000_rx_desc_packet_split {
602 struct {
603 /* one buffer for protocol header(s), three data buffers */
604 uint64_t buffer_addr[MAX_PS_BUFFERS];
605 } read;
606 struct {
607 struct {
608 uint32_t mrq; /* Multiple Rx Queues */
609 union {
610 uint32_t rss; /* RSS Hash */
611 struct {
612 uint16_t ip_id; /* IP id */
613 uint16_t csum; /* Packet Checksum */
614 } csum_ip;
615 } hi_dword;
616 } lower;
617 struct {
618 uint32_t status_error; /* ext status/error */
619 uint16_t length0; /* length of buffer 0 */
620 uint16_t vlan; /* VLAN tag */
621 } middle;
622 struct {
623 uint16_t header_status;
624 uint16_t length[3]; /* length of buffers 1-3 */
625 } upper;
626 uint64_t reserved;
627 } wb; /* writeback */
628};
629
460/* Receive Decriptor bit definitions */ 630/* Receive Decriptor bit definitions */
461#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 631#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
462#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 632#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
463#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 633#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
464#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 634#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
635#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
465#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 636#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
466#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 637#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
467#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 638#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
639#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
640#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
641#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
468#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 642#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
469#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 643#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
470#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 644#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
@@ -474,9 +648,20 @@ struct e1000_rx_desc {
474#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 648#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
475#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 649#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
476#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 650#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
477#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ 651#define E1000_RXD_SPC_PRI_SHIFT 13
478#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 652#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
479#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ 653#define E1000_RXD_SPC_CFI_SHIFT 12
654
655#define E1000_RXDEXT_STATERR_CE 0x01000000
656#define E1000_RXDEXT_STATERR_SE 0x02000000
657#define E1000_RXDEXT_STATERR_SEQ 0x04000000
658#define E1000_RXDEXT_STATERR_CXE 0x10000000
659#define E1000_RXDEXT_STATERR_TCPE 0x20000000
660#define E1000_RXDEXT_STATERR_IPE 0x40000000
661#define E1000_RXDEXT_STATERR_RXE 0x80000000
662
663#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
664#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
480 665
481/* mask to determine if packets should be dropped due to frame errors */ 666/* mask to determine if packets should be dropped due to frame errors */
482#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 667#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
@@ -486,6 +671,15 @@ struct e1000_rx_desc {
486 E1000_RXD_ERR_CXE | \ 671 E1000_RXD_ERR_CXE | \
487 E1000_RXD_ERR_RXE) 672 E1000_RXD_ERR_RXE)
488 673
674
675/* Same mask, but for extended and packet split descriptors */
676#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
677 E1000_RXDEXT_STATERR_CE | \
678 E1000_RXDEXT_STATERR_SE | \
679 E1000_RXDEXT_STATERR_SEQ | \
680 E1000_RXDEXT_STATERR_CXE | \
681 E1000_RXDEXT_STATERR_RXE)
682
489/* Transmit Descriptor */ 683/* Transmit Descriptor */
490struct e1000_tx_desc { 684struct e1000_tx_desc {
491 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 685 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
@@ -667,6 +861,7 @@ struct e1000_ffvt_entry {
667#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 861#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
668#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 862#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
669#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 863#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
864#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
670#define E1000_RCTL 0x00100 /* RX Control - RW */ 865#define E1000_RCTL 0x00100 /* RX Control - RW */
671#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 866#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
672#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 867#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
@@ -676,9 +871,23 @@ struct e1000_ffvt_entry {
676#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 871#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
677#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 872#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
678#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 873#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
874#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
875#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
679#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 876#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
877#define E1000_PBS 0x01008 /* Packet Buffer Size */
878#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
879#define E1000_FLASH_UPDATES 1000
880#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
881#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
882#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
883#define E1000_FLSWCTL 0x01030 /* FLASH control register */
884#define E1000_FLSWDATA 0x01034 /* FLASH data register */
885#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
886#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
887#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
680#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 888#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
681#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 889#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
890#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
682#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 891#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
683#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 892#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
684#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 893#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
@@ -688,6 +897,7 @@ struct e1000_ffvt_entry {
688#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ 897#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
689#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 898#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
690#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 899#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
900#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
691#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 901#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
692#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 902#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
693#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 903#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
@@ -703,6 +913,14 @@ struct e1000_ffvt_entry {
703#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 913#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
704#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 914#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
705#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 915#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
916#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
917#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
918#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
919#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
920#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
921#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
922#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
923#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
706#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 924#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
707#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 925#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
708#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 926#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
@@ -761,7 +979,17 @@ struct e1000_ffvt_entry {
761#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 979#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
762#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 980#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
763#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 981#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
982#define E1000_IAC 0x4100 /* Interrupt Assertion Count */
983#define E1000_ICRXPTC 0x4104 /* Interrupt Cause Rx Packet Timer Expire Count */
984#define E1000_ICRXATC 0x4108 /* Interrupt Cause Rx Absolute Timer Expire Count */
985#define E1000_ICTXPTC 0x410C /* Interrupt Cause Tx Packet Timer Expire Count */
986#define E1000_ICTXATC 0x4110 /* Interrupt Cause Tx Absolute Timer Expire Count */
987#define E1000_ICTXQEC 0x4118 /* Interrupt Cause Tx Queue Empty Count */
988#define E1000_ICTXQMTC 0x411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
989#define E1000_ICRXDMTC 0x4120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
990#define E1000_ICRXOC 0x4124 /* Interrupt Cause Receiver Overrun Count */
764#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 991#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
992#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
765#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 993#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
766#define E1000_RA 0x05400 /* Receive Address - RW Array */ 994#define E1000_RA 0x05400 /* Receive Address - RW Array */
767#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 995#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
@@ -779,6 +1007,16 @@ struct e1000_ffvt_entry {
779#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 1007#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
780#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 1008#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
781 1009
1010#define E1000_GCR 0x05B00 /* PCI-Ex Control */
1011#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1012#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1013#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1014#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1015#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1016#define E1000_SWSM 0x05B50 /* SW Semaphore */
1017#define E1000_FWSM 0x05B54 /* FW Semaphore */
1018#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1019#define E1000_HICR 0x08F00 /* Host Inteface Control */
782/* Register Set (82542) 1020/* Register Set (82542)
783 * 1021 *
784 * Some of the 82542 registers are located at different offsets than they are 1022 * Some of the 82542 registers are located at different offsets than they are
@@ -829,6 +1067,18 @@ struct e1000_ffvt_entry {
829#define E1000_82542_VFTA 0x00600 1067#define E1000_82542_VFTA 0x00600
830#define E1000_82542_LEDCTL E1000_LEDCTL 1068#define E1000_82542_LEDCTL E1000_LEDCTL
831#define E1000_82542_PBA E1000_PBA 1069#define E1000_82542_PBA E1000_PBA
1070#define E1000_82542_PBS E1000_PBS
1071#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1072#define E1000_82542_EEARBC E1000_EEARBC
1073#define E1000_82542_FLASHT E1000_FLASHT
1074#define E1000_82542_EEWR E1000_EEWR
1075#define E1000_82542_FLSWCTL E1000_FLSWCTL
1076#define E1000_82542_FLSWDATA E1000_FLSWDATA
1077#define E1000_82542_FLSWCNT E1000_FLSWCNT
1078#define E1000_82542_FLOP E1000_FLOP
1079#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1080#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1081#define E1000_82542_ERT E1000_ERT
832#define E1000_82542_RXDCTL E1000_RXDCTL 1082#define E1000_82542_RXDCTL E1000_RXDCTL
833#define E1000_82542_RADV E1000_RADV 1083#define E1000_82542_RADV E1000_RADV
834#define E1000_82542_RSRPD E1000_RSRPD 1084#define E1000_82542_RSRPD E1000_RSRPD
@@ -913,6 +1163,38 @@ struct e1000_ffvt_entry {
913#define E1000_82542_FFMT E1000_FFMT 1163#define E1000_82542_FFMT E1000_FFMT
914#define E1000_82542_FFVT E1000_FFVT 1164#define E1000_82542_FFVT E1000_FFVT
915#define E1000_82542_HOST_IF E1000_HOST_IF 1165#define E1000_82542_HOST_IF E1000_HOST_IF
1166#define E1000_82542_IAM E1000_IAM
1167#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1168#define E1000_82542_PSRCTL E1000_PSRCTL
1169#define E1000_82542_RAID E1000_RAID
1170#define E1000_82542_TARC0 E1000_TARC0
1171#define E1000_82542_TDBAL1 E1000_TDBAL1
1172#define E1000_82542_TDBAH1 E1000_TDBAH1
1173#define E1000_82542_TDLEN1 E1000_TDLEN1
1174#define E1000_82542_TDH1 E1000_TDH1
1175#define E1000_82542_TDT1 E1000_TDT1
1176#define E1000_82542_TXDCTL1 E1000_TXDCTL1
1177#define E1000_82542_TARC1 E1000_TARC1
1178#define E1000_82542_RFCTL E1000_RFCTL
1179#define E1000_82542_GCR E1000_GCR
1180#define E1000_82542_GSCL_1 E1000_GSCL_1
1181#define E1000_82542_GSCL_2 E1000_GSCL_2
1182#define E1000_82542_GSCL_3 E1000_GSCL_3
1183#define E1000_82542_GSCL_4 E1000_GSCL_4
1184#define E1000_82542_FACTPS E1000_FACTPS
1185#define E1000_82542_SWSM E1000_SWSM
1186#define E1000_82542_FWSM E1000_FWSM
1187#define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1188#define E1000_82542_IAC E1000_IAC
1189#define E1000_82542_ICRXPTC E1000_ICRXPTC
1190#define E1000_82542_ICRXATC E1000_ICRXATC
1191#define E1000_82542_ICTXPTC E1000_ICTXPTC
1192#define E1000_82542_ICTXATC E1000_ICTXATC
1193#define E1000_82542_ICTXQEC E1000_ICTXQEC
1194#define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1195#define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1196#define E1000_82542_ICRXOC E1000_ICRXOC
1197#define E1000_82542_HICR E1000_HICR
916 1198
917/* Statistics counters collected by the MAC */ 1199/* Statistics counters collected by the MAC */
918struct e1000_hw_stats { 1200struct e1000_hw_stats {
@@ -974,11 +1256,21 @@ struct e1000_hw_stats {
974 uint64_t bptc; 1256 uint64_t bptc;
975 uint64_t tsctc; 1257 uint64_t tsctc;
976 uint64_t tsctfc; 1258 uint64_t tsctfc;
1259 uint64_t iac;
1260 uint64_t icrxptc;
1261 uint64_t icrxatc;
1262 uint64_t ictxptc;
1263 uint64_t ictxatc;
1264 uint64_t ictxqec;
1265 uint64_t ictxqmtc;
1266 uint64_t icrxdmtc;
1267 uint64_t icrxoc;
977}; 1268};
978 1269
979/* Structure containing variables used by the shared code (e1000_hw.c) */ 1270/* Structure containing variables used by the shared code (e1000_hw.c) */
980struct e1000_hw { 1271struct e1000_hw {
981 uint8_t __iomem *hw_addr; 1272 uint8_t *hw_addr;
1273 uint8_t *flash_address;
982 e1000_mac_type mac_type; 1274 e1000_mac_type mac_type;
983 e1000_phy_type phy_type; 1275 e1000_phy_type phy_type;
984 uint32_t phy_init_script; 1276 uint32_t phy_init_script;
@@ -993,6 +1285,7 @@ struct e1000_hw {
993 e1000_ms_type original_master_slave; 1285 e1000_ms_type original_master_slave;
994 e1000_ffe_config ffe_config_state; 1286 e1000_ffe_config ffe_config_state;
995 uint32_t asf_firmware_present; 1287 uint32_t asf_firmware_present;
1288 uint32_t eeprom_semaphore_present;
996 unsigned long io_base; 1289 unsigned long io_base;
997 uint32_t phy_id; 1290 uint32_t phy_id;
998 uint32_t phy_revision; 1291 uint32_t phy_revision;
@@ -1009,6 +1302,8 @@ struct e1000_hw {
1009 uint32_t ledctl_default; 1302 uint32_t ledctl_default;
1010 uint32_t ledctl_mode1; 1303 uint32_t ledctl_mode1;
1011 uint32_t ledctl_mode2; 1304 uint32_t ledctl_mode2;
1305 boolean_t tx_pkt_filtering;
1306 struct e1000_host_mng_dhcp_cookie mng_cookie;
1012 uint16_t phy_spd_default; 1307 uint16_t phy_spd_default;
1013 uint16_t autoneg_advertised; 1308 uint16_t autoneg_advertised;
1014 uint16_t pci_cmd_word; 1309 uint16_t pci_cmd_word;
@@ -1047,16 +1342,24 @@ struct e1000_hw {
1047 boolean_t adaptive_ifs; 1342 boolean_t adaptive_ifs;
1048 boolean_t ifs_params_forced; 1343 boolean_t ifs_params_forced;
1049 boolean_t in_ifs_mode; 1344 boolean_t in_ifs_mode;
1345 boolean_t mng_reg_access_disabled;
1050}; 1346};
1051 1347
1052 1348
1053#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 1349#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1054#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 1350#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1351#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1352#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1353#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1354#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1355#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1356#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1055/* Register Bit Masks */ 1357/* Register Bit Masks */
1056/* Device Control */ 1358/* Device Control */
1057#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 1359#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1058#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 1360#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1059#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 1361#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1362#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1060#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 1363#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1061#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 1364#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1062#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 1365#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
@@ -1070,6 +1373,7 @@ struct e1000_hw {
1070#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 1373#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1071#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 1374#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1072#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 1375#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1376#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1073#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 1377#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1074#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1378#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1075#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 1379#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
@@ -1089,6 +1393,7 @@ struct e1000_hw {
1089#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1393#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1090#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 1394#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1091#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 1395#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1396#define E1000_STATUS_FUNC_SHIFT 2
1092#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 1397#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1093#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 1398#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1094#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 1399#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
@@ -1098,6 +1403,8 @@ struct e1000_hw {
1098#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1403#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1099#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1404#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1100#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1405#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1406#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1407#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1101#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 1408#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1102#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 1409#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1103#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 1410#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
@@ -1128,6 +1435,18 @@ struct e1000_hw {
1128#ifndef E1000_EEPROM_GRANT_ATTEMPTS 1435#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1129#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1436#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1130#endif 1437#endif
1438#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1439#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1440#define E1000_EECD_SIZE_EX_SHIFT 11
1441#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1442#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1443#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1444#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1445#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1446#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1447#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1448#define E1000_STM_OPCODE 0xDB00
1449#define E1000_HICR_FW_RESET 0xC0
1131 1450
1132/* EEPROM Read */ 1451/* EEPROM Read */
1133#define E1000_EERD_START 0x00000001 /* Start Read */ 1452#define E1000_EERD_START 0x00000001 /* Start Read */
@@ -1171,6 +1490,8 @@ struct e1000_hw {
1171#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1490#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1172#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1491#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1173#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1492#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1493#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1494#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1174 1495
1175/* MDI Control */ 1496/* MDI Control */
1176#define E1000_MDIC_DATA_MASK 0x0000FFFF 1497#define E1000_MDIC_DATA_MASK 0x0000FFFF
@@ -1187,14 +1508,17 @@ struct e1000_hw {
1187/* LED Control */ 1508/* LED Control */
1188#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1509#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1189#define E1000_LEDCTL_LED0_MODE_SHIFT 0 1510#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1511#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1190#define E1000_LEDCTL_LED0_IVRT 0x00000040 1512#define E1000_LEDCTL_LED0_IVRT 0x00000040
1191#define E1000_LEDCTL_LED0_BLINK 0x00000080 1513#define E1000_LEDCTL_LED0_BLINK 0x00000080
1192#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 1514#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1193#define E1000_LEDCTL_LED1_MODE_SHIFT 8 1515#define E1000_LEDCTL_LED1_MODE_SHIFT 8
1516#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1194#define E1000_LEDCTL_LED1_IVRT 0x00004000 1517#define E1000_LEDCTL_LED1_IVRT 0x00004000
1195#define E1000_LEDCTL_LED1_BLINK 0x00008000 1518#define E1000_LEDCTL_LED1_BLINK 0x00008000
1196#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 1519#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1197#define E1000_LEDCTL_LED2_MODE_SHIFT 16 1520#define E1000_LEDCTL_LED2_MODE_SHIFT 16
1521#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1198#define E1000_LEDCTL_LED2_IVRT 0x00400000 1522#define E1000_LEDCTL_LED2_IVRT 0x00400000
1199#define E1000_LEDCTL_LED2_BLINK 0x00800000 1523#define E1000_LEDCTL_LED2_BLINK 0x00800000
1200#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 1524#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
@@ -1238,6 +1562,10 @@ struct e1000_hw {
1238#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1562#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1239#define E1000_ICR_TXD_LOW 0x00008000 1563#define E1000_ICR_TXD_LOW 0x00008000
1240#define E1000_ICR_SRPD 0x00010000 1564#define E1000_ICR_SRPD 0x00010000
1565#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1566#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1567#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1568#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1241 1569
1242/* Interrupt Cause Set */ 1570/* Interrupt Cause Set */
1243#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1571#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1255,6 +1583,9 @@ struct e1000_hw {
1255#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1583#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1256#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1584#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1257#define E1000_ICS_SRPD E1000_ICR_SRPD 1585#define E1000_ICS_SRPD E1000_ICR_SRPD
1586#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1587#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1588#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1258 1589
1259/* Interrupt Mask Set */ 1590/* Interrupt Mask Set */
1260#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1591#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1272,6 +1603,9 @@ struct e1000_hw {
1272#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1603#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1273#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1604#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1274#define E1000_IMS_SRPD E1000_ICR_SRPD 1605#define E1000_IMS_SRPD E1000_ICR_SRPD
1606#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1607#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1608#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1275 1609
1276/* Interrupt Mask Clear */ 1610/* Interrupt Mask Clear */
1277#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1611#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1289,6 +1623,9 @@ struct e1000_hw {
1289#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1623#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1290#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1624#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1291#define E1000_IMC_SRPD E1000_ICR_SRPD 1625#define E1000_IMC_SRPD E1000_ICR_SRPD
1626#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1627#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1628#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1292 1629
1293/* Receive Control */ 1630/* Receive Control */
1294#define E1000_RCTL_RST 0x00000001 /* Software reset */ 1631#define E1000_RCTL_RST 0x00000001 /* Software reset */
@@ -1301,6 +1638,8 @@ struct e1000_hw {
1301#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1638#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1302#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1639#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1303#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1640#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1641#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1642#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1304#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1643#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1305#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1644#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1306#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1645#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
@@ -1327,6 +1666,34 @@ struct e1000_hw {
1327#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1666#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1328#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1667#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1329#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 1668#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1669#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1670#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1671
1672/* Use byte values for the following shift parameters
1673 * Usage:
1674 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1675 * E1000_PSRCTL_BSIZE0_MASK) |
1676 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1677 * E1000_PSRCTL_BSIZE1_MASK) |
1678 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1679 * E1000_PSRCTL_BSIZE2_MASK) |
1680 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1681 * E1000_PSRCTL_BSIZE3_MASK))
1682 * where value0 = [128..16256], default=256
1683 * value1 = [1024..64512], default=4096
1684 * value2 = [0..64512], default=4096
1685 * value3 = [0..64512], default=0
1686 */
1687
1688#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1689#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1690#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1691#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1692
1693#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1694#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1695#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1696#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1330 1697
1331/* Receive Descriptor */ 1698/* Receive Descriptor */
1332#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 1699#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
@@ -1341,6 +1708,23 @@ struct e1000_hw {
1341#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1708#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1342#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1709#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1343 1710
1711/* Header split receive */
1712#define E1000_RFCTL_ISCSI_DIS 0x00000001
1713#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1714#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1715#define E1000_RFCTL_NFSW_DIS 0x00000040
1716#define E1000_RFCTL_NFSR_DIS 0x00000080
1717#define E1000_RFCTL_NFS_VER_MASK 0x00000300
1718#define E1000_RFCTL_NFS_VER_SHIFT 8
1719#define E1000_RFCTL_IPV6_DIS 0x00000400
1720#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1721#define E1000_RFCTL_ACK_DIS 0x00001000
1722#define E1000_RFCTL_ACKD_DIS 0x00002000
1723#define E1000_RFCTL_IPFRSP_DIS 0x00004000
1724#define E1000_RFCTL_EXTEN 0x00008000
1725#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1726#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1727
1344/* Receive Descriptor Control */ 1728/* Receive Descriptor Control */
1345#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 1729#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1346#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 1730#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
@@ -1354,6 +1738,8 @@ struct e1000_hw {
1354#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1738#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1355#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1739#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1356#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1740#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1741#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1742 still to be processed. */
1357 1743
1358/* Transmit Configuration Word */ 1744/* Transmit Configuration Word */
1359#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1745#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
@@ -1387,12 +1773,16 @@ struct e1000_hw {
1387#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 1773#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1388#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 1774#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1389#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 1775#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1776#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1390 1777
1391/* Receive Checksum Control */ 1778/* Receive Checksum Control */
1392#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 1779#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1393#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 1780#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1394#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 1781#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1395#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 1782#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1783#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1784#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1785
1396 1786
1397/* Definitions for power management and wakeup registers */ 1787/* Definitions for power management and wakeup registers */
1398/* Wake Up Control */ 1788/* Wake Up Control */
@@ -1411,6 +1801,7 @@ struct e1000_hw {
1411#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 1801#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1412#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 1802#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1413#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 1803#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1804#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1414#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 1805#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1415#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 1806#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1416#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 1807#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
@@ -1446,13 +1837,19 @@ struct e1000_hw {
1446#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 1837#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1447#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 1838#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1448 * Filtering */ 1839 * Filtering */
1840#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
1449#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 1841#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1450#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 1842#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1451#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 1843#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
1844#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
1452#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 1845#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
1453 * filtering */ 1846 * filtering */
1454#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 1847#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
1455 * memory */ 1848 * memory */
1849#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
1850 * filtering */
1851#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
1852#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
1456#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 1853#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1457#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 1854#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1458#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 1855#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
@@ -1463,11 +1860,97 @@ struct e1000_hw {
1463#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 1860#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1464#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 1861#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1465 1862
1863/* SW Semaphore Register */
1864#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1865#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1866#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1867#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
1868
1869/* FW Semaphore Register */
1870#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
1871#define E1000_FWSM_MODE_SHIFT 1
1872#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
1873
1874/* FFLT Debug Register */
1875#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
1876
1877typedef enum {
1878 e1000_mng_mode_none = 0,
1879 e1000_mng_mode_asf,
1880 e1000_mng_mode_pt,
1881 e1000_mng_mode_ipmi,
1882 e1000_mng_mode_host_interface_only
1883} e1000_mng_mode;
1884
1885/* Host Inteface Control Register */
1886#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
1887#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
1888 * to put command in RAM */
1889#define E1000_HICR_SV 0x00000004 /* Status Validity */
1890#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
1891
1892/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
1893#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
1894#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
1895#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
1896#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
1897
1898struct e1000_host_command_header {
1899 uint8_t command_id;
1900 uint8_t command_length;
1901 uint8_t command_options; /* I/F bits for command, status for return */
1902 uint8_t checksum;
1903};
1904struct e1000_host_command_info {
1905 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
1906 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
1907};
1908
1909/* Host SMB register #0 */
1910#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
1911#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
1912#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
1913#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
1914
1915/* Host SMB register #1 */
1916#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
1917#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
1918#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
1919#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
1920
1921/* FW Status Register */
1922#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
1923
1466/* Wake Up Packet Length */ 1924/* Wake Up Packet Length */
1467#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 1925#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1468 1926
1469#define E1000_MDALIGN 4096 1927#define E1000_MDALIGN 4096
1470 1928
1929#define E1000_GCR_BEM32 0x00400000
1930/* Function Active and Power State to MNG */
1931#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
1932#define E1000_FACTPS_LAN0_VALID 0x00000004
1933#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
1934#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
1935#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
1936#define E1000_FACTPS_LAN1_VALID 0x00000100
1937#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
1938#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
1939#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
1940#define E1000_FACTPS_IDE_ENABLE 0x00004000
1941#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
1942#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
1943#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
1944#define E1000_FACTPS_SP_ENABLE 0x00100000
1945#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
1946#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
1947#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
1948#define E1000_FACTPS_IPMI_ENABLE 0x04000000
1949#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
1950#define E1000_FACTPS_MNGCG 0x20000000
1951#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
1952#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
1953
1471/* EEPROM Commands - Microwire */ 1954/* EEPROM Commands - Microwire */
1472#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 1955#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
1473#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 1956#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
@@ -1477,22 +1960,20 @@ struct e1000_hw {
1477 1960
1478/* EEPROM Commands - SPI */ 1961/* EEPROM Commands - SPI */
1479#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1962#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1480#define EEPROM_READ_OPCODE_SPI 0x3 /* EEPROM read opcode */ 1963#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1481#define EEPROM_WRITE_OPCODE_SPI 0x2 /* EEPROM write opcode */ 1964#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1482#define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */ 1965#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1483#define EEPROM_WREN_OPCODE_SPI 0x6 /* EEPROM set Write Enable latch */ 1966#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
1484#define EEPROM_WRDI_OPCODE_SPI 0x4 /* EEPROM reset Write Enable latch */ 1967#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
1485#define EEPROM_RDSR_OPCODE_SPI 0x5 /* EEPROM read Status register */ 1968#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
1486#define EEPROM_WRSR_OPCODE_SPI 0x1 /* EEPROM write Status register */ 1969#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
1970#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1971#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1972#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1487 1973
1488/* EEPROM Size definitions */ 1974/* EEPROM Size definitions */
1489#define EEPROM_SIZE_16KB 0x1800 1975#define EEPROM_WORD_SIZE_SHIFT 6
1490#define EEPROM_SIZE_8KB 0x1400 1976#define EEPROM_SIZE_SHIFT 10
1491#define EEPROM_SIZE_4KB 0x1000
1492#define EEPROM_SIZE_2KB 0x0C00
1493#define EEPROM_SIZE_1KB 0x0800
1494#define EEPROM_SIZE_512B 0x0400
1495#define EEPROM_SIZE_128B 0x0000
1496#define EEPROM_SIZE_MASK 0x1C00 1977#define EEPROM_SIZE_MASK 0x1C00
1497 1978
1498/* EEPROM Word Offsets */ 1979/* EEPROM Word Offsets */
@@ -1606,7 +2087,22 @@ struct e1000_hw {
1606#define IFS_MIN 40 2087#define IFS_MIN 40
1607#define IFS_RATIO 4 2088#define IFS_RATIO 4
1608 2089
2090/* Extended Configuration Control and Size */
2091#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2092#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2093#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2094#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2095#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2096#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2097#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2098#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000
2099
2100#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2101#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2102#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2103
1609/* PBA constants */ 2104/* PBA constants */
2105#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
1610#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2106#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
1611#define E1000_PBA_22K 0x0016 2107#define E1000_PBA_22K 0x0016
1612#define E1000_PBA_24K 0x0018 2108#define E1000_PBA_24K 0x0018
@@ -1663,6 +2159,13 @@ struct e1000_hw {
1663/* Number of milliseconds we wait for auto-negotiation to complete */ 2159/* Number of milliseconds we wait for auto-negotiation to complete */
1664#define LINK_UP_TIMEOUT 500 2160#define LINK_UP_TIMEOUT 500
1665 2161
2162/* Number of 100 microseconds we wait for PCI Express master disable */
2163#define MASTER_DISABLE_TIMEOUT 800
2164/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2165#define AUTO_READ_DONE_TIMEOUT 10
2166/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2167#define PHY_CFG_TIMEOUT 40
2168
1666#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 2169#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1667 2170
1668/* The carrier extension symbol, as received by the NIC. */ 2171/* The carrier extension symbol, as received by the NIC. */
@@ -1763,6 +2266,7 @@ struct e1000_hw {
1763#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 2266#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
1764#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 2267#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
1765#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 2268#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2269#define IGP02E1000_PHY_POWER_MGMT 0x19
1766#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 2270#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
1767 2271
1768/* IGP01E1000 AGC Registers - stores the cable length values*/ 2272/* IGP01E1000 AGC Registers - stores the cable length values*/
@@ -1771,12 +2275,20 @@ struct e1000_hw {
1771#define IGP01E1000_PHY_AGC_C 0x1472 2275#define IGP01E1000_PHY_AGC_C 0x1472
1772#define IGP01E1000_PHY_AGC_D 0x1872 2276#define IGP01E1000_PHY_AGC_D 0x1872
1773 2277
2278/* IGP02E1000 AGC Registers for cable length values */
2279#define IGP02E1000_PHY_AGC_A 0x11B1
2280#define IGP02E1000_PHY_AGC_B 0x12B1
2281#define IGP02E1000_PHY_AGC_C 0x14B1
2282#define IGP02E1000_PHY_AGC_D 0x18B1
2283
1774/* IGP01E1000 DSP Reset Register */ 2284/* IGP01E1000 DSP Reset Register */
1775#define IGP01E1000_PHY_DSP_RESET 0x1F33 2285#define IGP01E1000_PHY_DSP_RESET 0x1F33
1776#define IGP01E1000_PHY_DSP_SET 0x1F71 2286#define IGP01E1000_PHY_DSP_SET 0x1F71
1777#define IGP01E1000_PHY_DSP_FFE 0x1F35 2287#define IGP01E1000_PHY_DSP_FFE 0x1F35
1778 2288
1779#define IGP01E1000_PHY_CHANNEL_NUM 4 2289#define IGP01E1000_PHY_CHANNEL_NUM 4
2290#define IGP02E1000_PHY_CHANNEL_NUM 4
2291
1780#define IGP01E1000_PHY_AGC_PARAM_A 0x1171 2292#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
1781#define IGP01E1000_PHY_AGC_PARAM_B 0x1271 2293#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
1782#define IGP01E1000_PHY_AGC_PARAM_C 0x1471 2294#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
@@ -2060,20 +2572,30 @@ struct e1000_hw {
2060#define IGP01E1000_MSE_CHANNEL_B 0x0F00 2572#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2061#define IGP01E1000_MSE_CHANNEL_A 0xF000 2573#define IGP01E1000_MSE_CHANNEL_A 0xF000
2062 2574
2575#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2576#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2577#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2578
2063/* IGP01E1000 DSP reset macros */ 2579/* IGP01E1000 DSP reset macros */
2064#define DSP_RESET_ENABLE 0x0 2580#define DSP_RESET_ENABLE 0x0
2065#define DSP_RESET_DISABLE 0x2 2581#define DSP_RESET_DISABLE 0x2
2066#define E1000_MAX_DSP_RESETS 10 2582#define E1000_MAX_DSP_RESETS 10
2067 2583
2068/* IGP01E1000 AGC Registers */ 2584/* IGP01E1000 & IGP02E1000 AGC Registers */
2069 2585
2070#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 2586#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2587#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2588
2589/* IGP02E1000 AGC Register Length 9-bit mask */
2590#define IGP02E1000_AGC_LENGTH_MASK 0x7F
2071 2591
2072/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ 2592/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2073#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 2593#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
2594#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 128
2074 2595
2075/* The precision of the length is +/- 10 meters */ 2596/* The precision error of the cable length is +/- 10 meters */
2076#define IGP01E1000_AGC_RANGE 10 2597#define IGP01E1000_AGC_RANGE 10
2598#define IGP02E1000_AGC_RANGE 10
2077 2599
2078/* IGP01E1000 PCS Initialization register */ 2600/* IGP01E1000 PCS Initialization register */
2079/* bits 3:6 in the PCS registers stores the channels polarity */ 2601/* bits 3:6 in the PCS registers stores the channels polarity */
@@ -2113,6 +2635,8 @@ struct e1000_hw {
2113#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID 2635#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2114#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID 2636#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2115#define M88E1011_I_REV_4 0x04 2637#define M88E1011_I_REV_4 0x04
2638#define M88E1111_I_PHY_ID 0x01410CC0
2639#define L1LXT971A_PHY_ID 0x001378E0
2116 2640
2117/* Miscellaneous PHY bit definitions. */ 2641/* Miscellaneous PHY bit definitions. */
2118#define PHY_PREAMBLE 0xFFFFFFFF 2642#define PHY_PREAMBLE 0xFFFFFFFF
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 4cdf371961eb..5e6e1f7fd777 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -155,10 +155,14 @@ static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter);
155static int e1000_clean(struct net_device *netdev, int *budget); 155static int e1000_clean(struct net_device *netdev, int *budget);
156static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter, 156static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
157 int *work_done, int work_to_do); 157 int *work_done, int work_to_do);
158static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
159 int *work_done, int work_to_do);
158#else 160#else
159static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter); 161static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter);
162static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter);
160#endif 163#endif
161static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter); 164static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter);
165static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter);
162static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 166static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
163static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 167static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
164 int cmd); 168 int cmd);
@@ -286,7 +290,29 @@ e1000_irq_enable(struct e1000_adapter *adapter)
286 E1000_WRITE_FLUSH(&adapter->hw); 290 E1000_WRITE_FLUSH(&adapter->hw);
287 } 291 }
288} 292}
289 293void
294e1000_update_mng_vlan(struct e1000_adapter *adapter)
295{
296 struct net_device *netdev = adapter->netdev;
297 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
298 uint16_t old_vid = adapter->mng_vlan_id;
299 if(adapter->vlgrp) {
300 if(!adapter->vlgrp->vlan_devices[vid]) {
301 if(adapter->hw.mng_cookie.status &
302 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
303 e1000_vlan_rx_add_vid(netdev, vid);
304 adapter->mng_vlan_id = vid;
305 } else
306 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
307
308 if((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
309 (vid != old_vid) &&
310 !adapter->vlgrp->vlan_devices[old_vid])
311 e1000_vlan_rx_kill_vid(netdev, old_vid);
312 }
313 }
314}
315
290int 316int
291e1000_up(struct e1000_adapter *adapter) 317e1000_up(struct e1000_adapter *adapter)
292{ 318{
@@ -310,7 +336,7 @@ e1000_up(struct e1000_adapter *adapter)
310 e1000_configure_tx(adapter); 336 e1000_configure_tx(adapter);
311 e1000_setup_rctl(adapter); 337 e1000_setup_rctl(adapter);
312 e1000_configure_rx(adapter); 338 e1000_configure_rx(adapter);
313 e1000_alloc_rx_buffers(adapter); 339 adapter->alloc_rx_buf(adapter);
314 340
315#ifdef CONFIG_PCI_MSI 341#ifdef CONFIG_PCI_MSI
316 if(adapter->hw.mac_type > e1000_82547_rev_2) { 342 if(adapter->hw.mac_type > e1000_82547_rev_2) {
@@ -366,8 +392,12 @@ e1000_down(struct e1000_adapter *adapter)
366 e1000_clean_rx_ring(adapter); 392 e1000_clean_rx_ring(adapter);
367 393
368 /* If WoL is not enabled 394 /* If WoL is not enabled
395 * and management mode is not IAMT
369 * Power down the PHY so no link is implied when interface is down */ 396 * Power down the PHY so no link is implied when interface is down */
370 if(!adapter->wol && adapter->hw.media_type == e1000_media_type_copper) { 397 if(!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
398 adapter->hw.media_type == e1000_media_type_copper &&
399 !e1000_check_mng_mode(&adapter->hw) &&
400 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN)) {
371 uint16_t mii_reg; 401 uint16_t mii_reg;
372 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg); 402 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
373 mii_reg |= MII_CR_POWER_DOWN; 403 mii_reg |= MII_CR_POWER_DOWN;
@@ -379,28 +409,34 @@ e1000_down(struct e1000_adapter *adapter)
379void 409void
380e1000_reset(struct e1000_adapter *adapter) 410e1000_reset(struct e1000_adapter *adapter)
381{ 411{
382 uint32_t pba; 412 uint32_t pba, manc;
383 413
384 /* Repartition Pba for greater than 9k mtu 414 /* Repartition Pba for greater than 9k mtu
385 * To take effect CTRL.RST is required. 415 * To take effect CTRL.RST is required.
386 */ 416 */
387 417
388 if(adapter->hw.mac_type < e1000_82547) { 418 switch (adapter->hw.mac_type) {
389 if(adapter->rx_buffer_len > E1000_RXBUFFER_8192) 419 case e1000_82547:
390 pba = E1000_PBA_40K; 420 pba = E1000_PBA_30K;
391 else 421 break;
392 pba = E1000_PBA_48K; 422 case e1000_82573:
393 } else { 423 pba = E1000_PBA_12K;
394 if(adapter->rx_buffer_len > E1000_RXBUFFER_8192) 424 break;
395 pba = E1000_PBA_22K; 425 default:
396 else 426 pba = E1000_PBA_48K;
397 pba = E1000_PBA_30K; 427 break;
428 }
429
430
431
432 if(adapter->hw.mac_type == e1000_82547) {
398 adapter->tx_fifo_head = 0; 433 adapter->tx_fifo_head = 0;
399 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT; 434 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
400 adapter->tx_fifo_size = 435 adapter->tx_fifo_size =
401 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT; 436 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
402 atomic_set(&adapter->tx_fifo_stall, 0); 437 atomic_set(&adapter->tx_fifo_stall, 0);
403 } 438 }
439
404 E1000_WRITE_REG(&adapter->hw, PBA, pba); 440 E1000_WRITE_REG(&adapter->hw, PBA, pba);
405 441
406 /* flow control settings */ 442 /* flow control settings */
@@ -412,17 +448,23 @@ e1000_reset(struct e1000_adapter *adapter)
412 adapter->hw.fc_send_xon = 1; 448 adapter->hw.fc_send_xon = 1;
413 adapter->hw.fc = adapter->hw.original_fc; 449 adapter->hw.fc = adapter->hw.original_fc;
414 450
451 /* Allow time for pending master requests to run */
415 e1000_reset_hw(&adapter->hw); 452 e1000_reset_hw(&adapter->hw);
416 if(adapter->hw.mac_type >= e1000_82544) 453 if(adapter->hw.mac_type >= e1000_82544)
417 E1000_WRITE_REG(&adapter->hw, WUC, 0); 454 E1000_WRITE_REG(&adapter->hw, WUC, 0);
418 if(e1000_init_hw(&adapter->hw)) 455 if(e1000_init_hw(&adapter->hw))
419 DPRINTK(PROBE, ERR, "Hardware Error\n"); 456 DPRINTK(PROBE, ERR, "Hardware Error\n");
420 457 e1000_update_mng_vlan(adapter);
421 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 458 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
422 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE); 459 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
423 460
424 e1000_reset_adaptive(&adapter->hw); 461 e1000_reset_adaptive(&adapter->hw);
425 e1000_phy_get_info(&adapter->hw, &adapter->phy_info); 462 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
463 if (adapter->en_mng_pt) {
464 manc = E1000_READ_REG(&adapter->hw, MANC);
465 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
466 E1000_WRITE_REG(&adapter->hw, MANC, manc);
467 }
426} 468}
427 469
428/** 470/**
@@ -443,15 +485,13 @@ e1000_probe(struct pci_dev *pdev,
443{ 485{
444 struct net_device *netdev; 486 struct net_device *netdev;
445 struct e1000_adapter *adapter; 487 struct e1000_adapter *adapter;
488 unsigned long mmio_start, mmio_len;
489 uint32_t swsm;
490
446 static int cards_found = 0; 491 static int cards_found = 0;
447 unsigned long mmio_start; 492 int i, err, pci_using_dac;
448 int mmio_len;
449 int pci_using_dac;
450 int i;
451 int err;
452 uint16_t eeprom_data; 493 uint16_t eeprom_data;
453 uint16_t eeprom_apme_mask = E1000_EEPROM_APME; 494 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
454
455 if((err = pci_enable_device(pdev))) 495 if((err = pci_enable_device(pdev)))
456 return err; 496 return err;
457 497
@@ -538,6 +578,9 @@ e1000_probe(struct pci_dev *pdev,
538 if((err = e1000_sw_init(adapter))) 578 if((err = e1000_sw_init(adapter)))
539 goto err_sw_init; 579 goto err_sw_init;
540 580
581 if((err = e1000_check_phy_reset_block(&adapter->hw)))
582 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
583
541 if(adapter->hw.mac_type >= e1000_82543) { 584 if(adapter->hw.mac_type >= e1000_82543) {
542 netdev->features = NETIF_F_SG | 585 netdev->features = NETIF_F_SG |
543 NETIF_F_HW_CSUM | 586 NETIF_F_HW_CSUM |
@@ -550,6 +593,11 @@ e1000_probe(struct pci_dev *pdev,
550 if((adapter->hw.mac_type >= e1000_82544) && 593 if((adapter->hw.mac_type >= e1000_82544) &&
551 (adapter->hw.mac_type != e1000_82547)) 594 (adapter->hw.mac_type != e1000_82547))
552 netdev->features |= NETIF_F_TSO; 595 netdev->features |= NETIF_F_TSO;
596
597#ifdef NETIF_F_TSO_IPV6
598 if(adapter->hw.mac_type > e1000_82547_rev_2)
599 netdev->features |= NETIF_F_TSO_IPV6;
600#endif
553#endif 601#endif
554 if(pci_using_dac) 602 if(pci_using_dac)
555 netdev->features |= NETIF_F_HIGHDMA; 603 netdev->features |= NETIF_F_HIGHDMA;
@@ -557,6 +605,8 @@ e1000_probe(struct pci_dev *pdev,
557 /* hard_start_xmit is safe against parallel locking */ 605 /* hard_start_xmit is safe against parallel locking */
558 netdev->features |= NETIF_F_LLTX; 606 netdev->features |= NETIF_F_LLTX;
559 607
608 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
609
560 /* before reading the EEPROM, reset the controller to 610 /* before reading the EEPROM, reset the controller to
561 * put the device in a known good starting state */ 611 * put the device in a known good starting state */
562 612
@@ -646,6 +696,17 @@ e1000_probe(struct pci_dev *pdev,
646 /* reset the hardware with the new settings */ 696 /* reset the hardware with the new settings */
647 e1000_reset(adapter); 697 e1000_reset(adapter);
648 698
699 /* Let firmware know the driver has taken over */
700 switch(adapter->hw.mac_type) {
701 case e1000_82573:
702 swsm = E1000_READ_REG(&adapter->hw, SWSM);
703 E1000_WRITE_REG(&adapter->hw, SWSM,
704 swsm | E1000_SWSM_DRV_LOAD);
705 break;
706 default:
707 break;
708 }
709
649 strcpy(netdev->name, "eth%d"); 710 strcpy(netdev->name, "eth%d");
650 if((err = register_netdev(netdev))) 711 if((err = register_netdev(netdev)))
651 goto err_register; 712 goto err_register;
@@ -681,7 +742,7 @@ e1000_remove(struct pci_dev *pdev)
681{ 742{
682 struct net_device *netdev = pci_get_drvdata(pdev); 743 struct net_device *netdev = pci_get_drvdata(pdev);
683 struct e1000_adapter *adapter = netdev->priv; 744 struct e1000_adapter *adapter = netdev->priv;
684 uint32_t manc; 745 uint32_t manc, swsm;
685 746
686 flush_scheduled_work(); 747 flush_scheduled_work();
687 748
@@ -694,9 +755,21 @@ e1000_remove(struct pci_dev *pdev)
694 } 755 }
695 } 756 }
696 757
758 switch(adapter->hw.mac_type) {
759 case e1000_82573:
760 swsm = E1000_READ_REG(&adapter->hw, SWSM);
761 E1000_WRITE_REG(&adapter->hw, SWSM,
762 swsm & ~E1000_SWSM_DRV_LOAD);
763 break;
764
765 default:
766 break;
767 }
768
697 unregister_netdev(netdev); 769 unregister_netdev(netdev);
698 770
699 e1000_phy_hw_reset(&adapter->hw); 771 if(!e1000_check_phy_reset_block(&adapter->hw))
772 e1000_phy_hw_reset(&adapter->hw);
700 773
701 iounmap(adapter->hw.hw_addr); 774 iounmap(adapter->hw.hw_addr);
702 pci_release_regions(pdev); 775 pci_release_regions(pdev);
@@ -734,6 +807,7 @@ e1000_sw_init(struct e1000_adapter *adapter)
734 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 807 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
735 808
736 adapter->rx_buffer_len = E1000_RXBUFFER_2048; 809 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
810 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
737 hw->max_frame_size = netdev->mtu + 811 hw->max_frame_size = netdev->mtu +
738 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; 812 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
739 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE; 813 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
@@ -747,7 +821,10 @@ e1000_sw_init(struct e1000_adapter *adapter)
747 821
748 /* initialize eeprom parameters */ 822 /* initialize eeprom parameters */
749 823
750 e1000_init_eeprom_params(hw); 824 if(e1000_init_eeprom_params(hw)) {
825 E1000_ERR("EEPROM initialization failed\n");
826 return -EIO;
827 }
751 828
752 switch(hw->mac_type) { 829 switch(hw->mac_type) {
753 default: 830 default:
@@ -812,6 +889,11 @@ e1000_open(struct net_device *netdev)
812 889
813 if((err = e1000_up(adapter))) 890 if((err = e1000_up(adapter)))
814 goto err_up; 891 goto err_up;
892 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
893 if((adapter->hw.mng_cookie.status &
894 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
895 e1000_update_mng_vlan(adapter);
896 }
815 897
816 return E1000_SUCCESS; 898 return E1000_SUCCESS;
817 899
@@ -847,14 +929,18 @@ e1000_close(struct net_device *netdev)
847 e1000_free_tx_resources(adapter); 929 e1000_free_tx_resources(adapter);
848 e1000_free_rx_resources(adapter); 930 e1000_free_rx_resources(adapter);
849 931
932 if((adapter->hw.mng_cookie.status &
933 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
934 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
935 }
850 return 0; 936 return 0;
851} 937}
852 938
853/** 939/**
854 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary 940 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
855 * @adapter: address of board private structure 941 * @adapter: address of board private structure
856 * @begin: address of beginning of memory 942 * @start: address of beginning of memory
857 * @end: address of end of memory 943 * @len: length of memory
858 **/ 944 **/
859static inline boolean_t 945static inline boolean_t
860e1000_check_64k_bound(struct e1000_adapter *adapter, 946e1000_check_64k_bound(struct e1000_adapter *adapter,
@@ -1039,7 +1125,7 @@ e1000_setup_rx_resources(struct e1000_adapter *adapter)
1039{ 1125{
1040 struct e1000_desc_ring *rxdr = &adapter->rx_ring; 1126 struct e1000_desc_ring *rxdr = &adapter->rx_ring;
1041 struct pci_dev *pdev = adapter->pdev; 1127 struct pci_dev *pdev = adapter->pdev;
1042 int size; 1128 int size, desc_len;
1043 1129
1044 size = sizeof(struct e1000_buffer) * rxdr->count; 1130 size = sizeof(struct e1000_buffer) * rxdr->count;
1045 rxdr->buffer_info = vmalloc(size); 1131 rxdr->buffer_info = vmalloc(size);
@@ -1050,9 +1136,35 @@ e1000_setup_rx_resources(struct e1000_adapter *adapter)
1050 } 1136 }
1051 memset(rxdr->buffer_info, 0, size); 1137 memset(rxdr->buffer_info, 0, size);
1052 1138
1139 size = sizeof(struct e1000_ps_page) * rxdr->count;
1140 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
1141 if(!rxdr->ps_page) {
1142 vfree(rxdr->buffer_info);
1143 DPRINTK(PROBE, ERR,
1144 "Unable to allocate memory for the receive descriptor ring\n");
1145 return -ENOMEM;
1146 }
1147 memset(rxdr->ps_page, 0, size);
1148
1149 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1150 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
1151 if(!rxdr->ps_page_dma) {
1152 vfree(rxdr->buffer_info);
1153 kfree(rxdr->ps_page);
1154 DPRINTK(PROBE, ERR,
1155 "Unable to allocate memory for the receive descriptor ring\n");
1156 return -ENOMEM;
1157 }
1158 memset(rxdr->ps_page_dma, 0, size);
1159
1160 if(adapter->hw.mac_type <= e1000_82547_rev_2)
1161 desc_len = sizeof(struct e1000_rx_desc);
1162 else
1163 desc_len = sizeof(union e1000_rx_desc_packet_split);
1164
1053 /* Round up to nearest 4K */ 1165 /* Round up to nearest 4K */
1054 1166
1055 rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc); 1167 rxdr->size = rxdr->count * desc_len;
1056 E1000_ROUNDUP(rxdr->size, 4096); 1168 E1000_ROUNDUP(rxdr->size, 4096);
1057 1169
1058 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); 1170 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
@@ -1062,6 +1174,8 @@ setup_rx_desc_die:
1062 DPRINTK(PROBE, ERR, 1174 DPRINTK(PROBE, ERR,
1063 "Unble to Allocate Memory for the Recieve descriptor ring\n"); 1175 "Unble to Allocate Memory for the Recieve descriptor ring\n");
1064 vfree(rxdr->buffer_info); 1176 vfree(rxdr->buffer_info);
1177 kfree(rxdr->ps_page);
1178 kfree(rxdr->ps_page_dma);
1065 return -ENOMEM; 1179 return -ENOMEM;
1066 } 1180 }
1067 1181
@@ -1089,6 +1203,8 @@ setup_rx_desc_die:
1089 "Unable to Allocate aligned Memory for the" 1203 "Unable to Allocate aligned Memory for the"
1090 " Receive descriptor ring\n"); 1204 " Receive descriptor ring\n");
1091 vfree(rxdr->buffer_info); 1205 vfree(rxdr->buffer_info);
1206 kfree(rxdr->ps_page);
1207 kfree(rxdr->ps_page_dma);
1092 return -ENOMEM; 1208 return -ENOMEM;
1093 } else { 1209 } else {
1094 /* free old, move on with the new one since its okay */ 1210 /* free old, move on with the new one since its okay */
@@ -1111,7 +1227,8 @@ setup_rx_desc_die:
1111static void 1227static void
1112e1000_setup_rctl(struct e1000_adapter *adapter) 1228e1000_setup_rctl(struct e1000_adapter *adapter)
1113{ 1229{
1114 uint32_t rctl; 1230 uint32_t rctl, rfctl;
1231 uint32_t psrctl = 0;
1115 1232
1116 rctl = E1000_READ_REG(&adapter->hw, RCTL); 1233 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1117 1234
@@ -1126,24 +1243,69 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
1126 else 1243 else
1127 rctl &= ~E1000_RCTL_SBP; 1244 rctl &= ~E1000_RCTL_SBP;
1128 1245
1246 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1247 rctl &= ~E1000_RCTL_LPE;
1248 else
1249 rctl |= E1000_RCTL_LPE;
1250
1129 /* Setup buffer sizes */ 1251 /* Setup buffer sizes */
1130 rctl &= ~(E1000_RCTL_SZ_4096); 1252 if(adapter->hw.mac_type == e1000_82573) {
1131 rctl |= (E1000_RCTL_BSEX | E1000_RCTL_LPE); 1253 /* We can now specify buffers in 1K increments.
1132 switch (adapter->rx_buffer_len) { 1254 * BSIZE and BSEX are ignored in this case. */
1133 case E1000_RXBUFFER_2048: 1255 rctl |= adapter->rx_buffer_len << 0x11;
1134 default: 1256 } else {
1135 rctl |= E1000_RCTL_SZ_2048; 1257 rctl &= ~E1000_RCTL_SZ_4096;
1136 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 1258 rctl |= E1000_RCTL_BSEX;
1137 break; 1259 switch (adapter->rx_buffer_len) {
1138 case E1000_RXBUFFER_4096: 1260 case E1000_RXBUFFER_2048:
1139 rctl |= E1000_RCTL_SZ_4096; 1261 default:
1140 break; 1262 rctl |= E1000_RCTL_SZ_2048;
1141 case E1000_RXBUFFER_8192: 1263 rctl &= ~E1000_RCTL_BSEX;
1142 rctl |= E1000_RCTL_SZ_8192; 1264 break;
1143 break; 1265 case E1000_RXBUFFER_4096:
1144 case E1000_RXBUFFER_16384: 1266 rctl |= E1000_RCTL_SZ_4096;
1145 rctl |= E1000_RCTL_SZ_16384; 1267 break;
1146 break; 1268 case E1000_RXBUFFER_8192:
1269 rctl |= E1000_RCTL_SZ_8192;
1270 break;
1271 case E1000_RXBUFFER_16384:
1272 rctl |= E1000_RCTL_SZ_16384;
1273 break;
1274 }
1275 }
1276
1277#ifdef CONFIG_E1000_PACKET_SPLIT
1278 /* 82571 and greater support packet-split where the protocol
1279 * header is placed in skb->data and the packet data is
1280 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1281 * In the case of a non-split, skb->data is linearly filled,
1282 * followed by the page buffers. Therefore, skb->data is
1283 * sized to hold the largest protocol header.
1284 */
1285 adapter->rx_ps = (adapter->hw.mac_type > e1000_82547_rev_2)
1286 && (adapter->netdev->mtu
1287 < ((3 * PAGE_SIZE) + adapter->rx_ps_bsize0));
1288#endif
1289 if(adapter->rx_ps) {
1290 /* Configure extra packet-split registers */
1291 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1292 rfctl |= E1000_RFCTL_EXTEN;
1293 /* disable IPv6 packet split support */
1294 rfctl |= E1000_RFCTL_IPV6_DIS;
1295 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1296
1297 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
1298
1299 psrctl |= adapter->rx_ps_bsize0 >>
1300 E1000_PSRCTL_BSIZE0_SHIFT;
1301 psrctl |= PAGE_SIZE >>
1302 E1000_PSRCTL_BSIZE1_SHIFT;
1303 psrctl |= PAGE_SIZE <<
1304 E1000_PSRCTL_BSIZE2_SHIFT;
1305 psrctl |= PAGE_SIZE <<
1306 E1000_PSRCTL_BSIZE3_SHIFT;
1307
1308 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1147 } 1309 }
1148 1310
1149 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 1311 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
@@ -1160,9 +1322,18 @@ static void
1160e1000_configure_rx(struct e1000_adapter *adapter) 1322e1000_configure_rx(struct e1000_adapter *adapter)
1161{ 1323{
1162 uint64_t rdba = adapter->rx_ring.dma; 1324 uint64_t rdba = adapter->rx_ring.dma;
1163 uint32_t rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc); 1325 uint32_t rdlen, rctl, rxcsum;
1164 uint32_t rctl; 1326
1165 uint32_t rxcsum; 1327 if(adapter->rx_ps) {
1328 rdlen = adapter->rx_ring.count *
1329 sizeof(union e1000_rx_desc_packet_split);
1330 adapter->clean_rx = e1000_clean_rx_irq_ps;
1331 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1332 } else {
1333 rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc);
1334 adapter->clean_rx = e1000_clean_rx_irq;
1335 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1336 }
1166 1337
1167 /* disable receives while setting up the descriptors */ 1338 /* disable receives while setting up the descriptors */
1168 rctl = E1000_READ_REG(&adapter->hw, RCTL); 1339 rctl = E1000_READ_REG(&adapter->hw, RCTL);
@@ -1189,13 +1360,27 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1189 E1000_WRITE_REG(&adapter->hw, RDT, 0); 1360 E1000_WRITE_REG(&adapter->hw, RDT, 0);
1190 1361
1191 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 1362 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
1192 if((adapter->hw.mac_type >= e1000_82543) && 1363 if(adapter->hw.mac_type >= e1000_82543) {
1193 (adapter->rx_csum == TRUE)) {
1194 rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM); 1364 rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
1195 rxcsum |= E1000_RXCSUM_TUOFL; 1365 if(adapter->rx_csum == TRUE) {
1366 rxcsum |= E1000_RXCSUM_TUOFL;
1367
1368 /* Enable 82573 IPv4 payload checksum for UDP fragments
1369 * Must be used in conjunction with packet-split. */
1370 if((adapter->hw.mac_type > e1000_82547_rev_2) &&
1371 (adapter->rx_ps)) {
1372 rxcsum |= E1000_RXCSUM_IPPCSE;
1373 }
1374 } else {
1375 rxcsum &= ~E1000_RXCSUM_TUOFL;
1376 /* don't need to clear IPPCSE as it defaults to 0 */
1377 }
1196 E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum); 1378 E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum);
1197 } 1379 }
1198 1380
1381 if (adapter->hw.mac_type == e1000_82573)
1382 E1000_WRITE_REG(&adapter->hw, ERT, 0x0100);
1383
1199 /* Enable Receives */ 1384 /* Enable Receives */
1200 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 1385 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1201} 1386}
@@ -1298,6 +1483,10 @@ e1000_free_rx_resources(struct e1000_adapter *adapter)
1298 1483
1299 vfree(rx_ring->buffer_info); 1484 vfree(rx_ring->buffer_info);
1300 rx_ring->buffer_info = NULL; 1485 rx_ring->buffer_info = NULL;
1486 kfree(rx_ring->ps_page);
1487 rx_ring->ps_page = NULL;
1488 kfree(rx_ring->ps_page_dma);
1489 rx_ring->ps_page_dma = NULL;
1301 1490
1302 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); 1491 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1303 1492
@@ -1314,16 +1503,19 @@ e1000_clean_rx_ring(struct e1000_adapter *adapter)
1314{ 1503{
1315 struct e1000_desc_ring *rx_ring = &adapter->rx_ring; 1504 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
1316 struct e1000_buffer *buffer_info; 1505 struct e1000_buffer *buffer_info;
1506 struct e1000_ps_page *ps_page;
1507 struct e1000_ps_page_dma *ps_page_dma;
1317 struct pci_dev *pdev = adapter->pdev; 1508 struct pci_dev *pdev = adapter->pdev;
1318 unsigned long size; 1509 unsigned long size;
1319 unsigned int i; 1510 unsigned int i, j;
1320 1511
1321 /* Free all the Rx ring sk_buffs */ 1512 /* Free all the Rx ring sk_buffs */
1322 1513
1323 for(i = 0; i < rx_ring->count; i++) { 1514 for(i = 0; i < rx_ring->count; i++) {
1324 buffer_info = &rx_ring->buffer_info[i]; 1515 buffer_info = &rx_ring->buffer_info[i];
1325 if(buffer_info->skb) { 1516 if(buffer_info->skb) {
1326 1517 ps_page = &rx_ring->ps_page[i];
1518 ps_page_dma = &rx_ring->ps_page_dma[i];
1327 pci_unmap_single(pdev, 1519 pci_unmap_single(pdev,
1328 buffer_info->dma, 1520 buffer_info->dma,
1329 buffer_info->length, 1521 buffer_info->length,
@@ -1331,11 +1523,25 @@ e1000_clean_rx_ring(struct e1000_adapter *adapter)
1331 1523
1332 dev_kfree_skb(buffer_info->skb); 1524 dev_kfree_skb(buffer_info->skb);
1333 buffer_info->skb = NULL; 1525 buffer_info->skb = NULL;
1526
1527 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
1528 if(!ps_page->ps_page[j]) break;
1529 pci_unmap_single(pdev,
1530 ps_page_dma->ps_page_dma[j],
1531 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1532 ps_page_dma->ps_page_dma[j] = 0;
1533 put_page(ps_page->ps_page[j]);
1534 ps_page->ps_page[j] = NULL;
1535 }
1334 } 1536 }
1335 } 1537 }
1336 1538
1337 size = sizeof(struct e1000_buffer) * rx_ring->count; 1539 size = sizeof(struct e1000_buffer) * rx_ring->count;
1338 memset(rx_ring->buffer_info, 0, size); 1540 memset(rx_ring->buffer_info, 0, size);
1541 size = sizeof(struct e1000_ps_page) * rx_ring->count;
1542 memset(rx_ring->ps_page, 0, size);
1543 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
1544 memset(rx_ring->ps_page_dma, 0, size);
1339 1545
1340 /* Zero out the descriptor ring */ 1546 /* Zero out the descriptor ring */
1341 1547
@@ -1573,6 +1779,11 @@ e1000_watchdog_task(struct e1000_adapter *adapter)
1573 uint32_t link; 1779 uint32_t link;
1574 1780
1575 e1000_check_for_link(&adapter->hw); 1781 e1000_check_for_link(&adapter->hw);
1782 if (adapter->hw.mac_type == e1000_82573) {
1783 e1000_enable_tx_pkt_filtering(&adapter->hw);
1784 if(adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
1785 e1000_update_mng_vlan(adapter);
1786 }
1576 1787
1577 if((adapter->hw.media_type == e1000_media_type_internal_serdes) && 1788 if((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1578 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE)) 1789 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
@@ -1659,6 +1870,7 @@ e1000_watchdog_task(struct e1000_adapter *adapter)
1659#define E1000_TX_FLAGS_CSUM 0x00000001 1870#define E1000_TX_FLAGS_CSUM 0x00000001
1660#define E1000_TX_FLAGS_VLAN 0x00000002 1871#define E1000_TX_FLAGS_VLAN 0x00000002
1661#define E1000_TX_FLAGS_TSO 0x00000004 1872#define E1000_TX_FLAGS_TSO 0x00000004
1873#define E1000_TX_FLAGS_IPV4 0x00000008
1662#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 1874#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
1663#define E1000_TX_FLAGS_VLAN_SHIFT 16 1875#define E1000_TX_FLAGS_VLAN_SHIFT 16
1664 1876
@@ -1669,7 +1881,7 @@ e1000_tso(struct e1000_adapter *adapter, struct sk_buff *skb)
1669 struct e1000_context_desc *context_desc; 1881 struct e1000_context_desc *context_desc;
1670 unsigned int i; 1882 unsigned int i;
1671 uint32_t cmd_length = 0; 1883 uint32_t cmd_length = 0;
1672 uint16_t ipcse, tucse, mss; 1884 uint16_t ipcse = 0, tucse, mss;
1673 uint8_t ipcss, ipcso, tucss, tucso, hdr_len; 1885 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
1674 int err; 1886 int err;
1675 1887
@@ -1682,23 +1894,37 @@ e1000_tso(struct e1000_adapter *adapter, struct sk_buff *skb)
1682 1894
1683 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2)); 1895 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
1684 mss = skb_shinfo(skb)->tso_size; 1896 mss = skb_shinfo(skb)->tso_size;
1685 skb->nh.iph->tot_len = 0; 1897 if(skb->protocol == ntohs(ETH_P_IP)) {
1686 skb->nh.iph->check = 0; 1898 skb->nh.iph->tot_len = 0;
1687 skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr, 1899 skb->nh.iph->check = 0;
1688 skb->nh.iph->daddr, 1900 skb->h.th->check =
1689 0, 1901 ~csum_tcpudp_magic(skb->nh.iph->saddr,
1690 IPPROTO_TCP, 1902 skb->nh.iph->daddr,
1691 0); 1903 0,
1904 IPPROTO_TCP,
1905 0);
1906 cmd_length = E1000_TXD_CMD_IP;
1907 ipcse = skb->h.raw - skb->data - 1;
1908#ifdef NETIF_F_TSO_IPV6
1909 } else if(skb->protocol == ntohs(ETH_P_IPV6)) {
1910 skb->nh.ipv6h->payload_len = 0;
1911 skb->h.th->check =
1912 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
1913 &skb->nh.ipv6h->daddr,
1914 0,
1915 IPPROTO_TCP,
1916 0);
1917 ipcse = 0;
1918#endif
1919 }
1692 ipcss = skb->nh.raw - skb->data; 1920 ipcss = skb->nh.raw - skb->data;
1693 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data; 1921 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1694 ipcse = skb->h.raw - skb->data - 1;
1695 tucss = skb->h.raw - skb->data; 1922 tucss = skb->h.raw - skb->data;
1696 tucso = (void *)&(skb->h.th->check) - (void *)skb->data; 1923 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
1697 tucse = 0; 1924 tucse = 0;
1698 1925
1699 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 1926 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
1700 E1000_TXD_CMD_IP | E1000_TXD_CMD_TCP | 1927 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1701 (skb->len - (hdr_len)));
1702 1928
1703 i = adapter->tx_ring.next_to_use; 1929 i = adapter->tx_ring.next_to_use;
1704 context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i); 1930 context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i);
@@ -1866,7 +2092,10 @@ e1000_tx_queue(struct e1000_adapter *adapter, int count, int tx_flags)
1866 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) { 2092 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1867 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 2093 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
1868 E1000_TXD_CMD_TSE; 2094 E1000_TXD_CMD_TSE;
1869 txd_upper |= (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 2095 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2096
2097 if(likely(tx_flags & E1000_TX_FLAGS_IPV4))
2098 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1870 } 2099 }
1871 2100
1872 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) { 2101 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
@@ -1941,6 +2170,53 @@ no_fifo_stall_required:
1941 return 0; 2170 return 0;
1942} 2171}
1943 2172
2173#define MINIMUM_DHCP_PACKET_SIZE 282
2174static inline int
2175e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2176{
2177 struct e1000_hw *hw = &adapter->hw;
2178 uint16_t length, offset;
2179 if(vlan_tx_tag_present(skb)) {
2180 if(!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2181 ( adapter->hw.mng_cookie.status &
2182 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2183 return 0;
2184 }
2185 if(htons(ETH_P_IP) == skb->protocol) {
2186 const struct iphdr *ip = skb->nh.iph;
2187 if(IPPROTO_UDP == ip->protocol) {
2188 struct udphdr *udp = (struct udphdr *)(skb->h.uh);
2189 if(ntohs(udp->dest) == 67) {
2190 offset = (uint8_t *)udp + 8 - skb->data;
2191 length = skb->len - offset;
2192
2193 return e1000_mng_write_dhcp_info(hw,
2194 (uint8_t *)udp + 8, length);
2195 }
2196 }
2197 } else if((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
2198 struct ethhdr *eth = (struct ethhdr *) skb->data;
2199 if((htons(ETH_P_IP) == eth->h_proto)) {
2200 const struct iphdr *ip =
2201 (struct iphdr *)((uint8_t *)skb->data+14);
2202 if(IPPROTO_UDP == ip->protocol) {
2203 struct udphdr *udp =
2204 (struct udphdr *)((uint8_t *)ip +
2205 (ip->ihl << 2));
2206 if(ntohs(udp->dest) == 67) {
2207 offset = (uint8_t *)udp + 8 - skb->data;
2208 length = skb->len - offset;
2209
2210 return e1000_mng_write_dhcp_info(hw,
2211 (uint8_t *)udp + 8,
2212 length);
2213 }
2214 }
2215 }
2216 }
2217 return 0;
2218}
2219
1944#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 ) 2220#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
1945static int 2221static int
1946e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2222e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
@@ -2008,6 +2284,9 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2008 local_irq_restore(flags); 2284 local_irq_restore(flags);
2009 return NETDEV_TX_LOCKED; 2285 return NETDEV_TX_LOCKED;
2010 } 2286 }
2287 if(adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
2288 e1000_transfer_dhcp_info(adapter, skb);
2289
2011 2290
2012 /* need: count + 2 desc gap to keep tail from touching 2291 /* need: count + 2 desc gap to keep tail from touching
2013 * head, otherwise try next time */ 2292 * head, otherwise try next time */
@@ -2044,6 +2323,12 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2044 else if(likely(e1000_tx_csum(adapter, skb))) 2323 else if(likely(e1000_tx_csum(adapter, skb)))
2045 tx_flags |= E1000_TX_FLAGS_CSUM; 2324 tx_flags |= E1000_TX_FLAGS_CSUM;
2046 2325
2326 /* Old method was to assume IPv4 packet by default if TSO was enabled.
2327 * 82573 hardware supports TSO capabilities for IPv6 as well...
2328 * no longer assume, we must. */
2329 if(likely(skb->protocol == ntohs(ETH_P_IP)))
2330 tx_flags |= E1000_TX_FLAGS_IPV4;
2331
2047 e1000_tx_queue(adapter, 2332 e1000_tx_queue(adapter,
2048 e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss), 2333 e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss),
2049 tx_flags); 2334 tx_flags);
@@ -2110,7 +2395,6 @@ static int
2110e1000_change_mtu(struct net_device *netdev, int new_mtu) 2395e1000_change_mtu(struct net_device *netdev, int new_mtu)
2111{ 2396{
2112 struct e1000_adapter *adapter = netdev->priv; 2397 struct e1000_adapter *adapter = netdev->priv;
2113 int old_mtu = adapter->rx_buffer_len;
2114 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; 2398 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
2115 2399
2116 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) || 2400 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
@@ -2119,29 +2403,45 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
2119 return -EINVAL; 2403 return -EINVAL;
2120 } 2404 }
2121 2405
2122 if(max_frame <= MAXIMUM_ETHERNET_FRAME_SIZE) { 2406#define MAX_STD_JUMBO_FRAME_SIZE 9216
2123 adapter->rx_buffer_len = E1000_RXBUFFER_2048; 2407 /* might want this to be bigger enum check... */
2124 2408 if (adapter->hw.mac_type == e1000_82573 &&
2125 } else if(adapter->hw.mac_type < e1000_82543) { 2409 max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2126 DPRINTK(PROBE, ERR, "Jumbo Frames not supported on 82542\n"); 2410 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2411 "on 82573\n");
2127 return -EINVAL; 2412 return -EINVAL;
2413 }
2128 2414
2129 } else if(max_frame <= E1000_RXBUFFER_4096) { 2415 if(adapter->hw.mac_type > e1000_82547_rev_2) {
2130 adapter->rx_buffer_len = E1000_RXBUFFER_4096; 2416 adapter->rx_buffer_len = max_frame;
2131 2417 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
2132 } else if(max_frame <= E1000_RXBUFFER_8192) {
2133 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
2134
2135 } else { 2418 } else {
2136 adapter->rx_buffer_len = E1000_RXBUFFER_16384; 2419 if(unlikely((adapter->hw.mac_type < e1000_82543) &&
2420 (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE))) {
2421 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2422 "on 82542\n");
2423 return -EINVAL;
2424
2425 } else {
2426 if(max_frame <= E1000_RXBUFFER_2048) {
2427 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2428 } else if(max_frame <= E1000_RXBUFFER_4096) {
2429 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
2430 } else if(max_frame <= E1000_RXBUFFER_8192) {
2431 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
2432 } else if(max_frame <= E1000_RXBUFFER_16384) {
2433 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
2434 }
2435 }
2137 } 2436 }
2138 2437
2139 if(old_mtu != adapter->rx_buffer_len && netif_running(netdev)) { 2438 netdev->mtu = new_mtu;
2439
2440 if(netif_running(netdev)) {
2140 e1000_down(adapter); 2441 e1000_down(adapter);
2141 e1000_up(adapter); 2442 e1000_up(adapter);
2142 } 2443 }
2143 2444
2144 netdev->mtu = new_mtu;
2145 adapter->hw.max_frame_size = max_frame; 2445 adapter->hw.max_frame_size = max_frame;
2146 2446
2147 return 0; 2447 return 0;
@@ -2232,6 +2532,17 @@ e1000_update_stats(struct e1000_adapter *adapter)
2232 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC); 2532 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
2233 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC); 2533 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
2234 } 2534 }
2535 if(hw->mac_type > e1000_82547_rev_2) {
2536 adapter->stats.iac += E1000_READ_REG(hw, IAC);
2537 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
2538 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
2539 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
2540 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
2541 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
2542 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
2543 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
2544 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
2545 }
2235 2546
2236 /* Fill out the OS statistics structure */ 2547 /* Fill out the OS statistics structure */
2237 2548
@@ -2337,7 +2648,7 @@ e1000_intr(int irq, void *data, struct pt_regs *regs)
2337 } 2648 }
2338 2649
2339 for(i = 0; i < E1000_MAX_INTR; i++) 2650 for(i = 0; i < E1000_MAX_INTR; i++)
2340 if(unlikely(!e1000_clean_rx_irq(adapter) & 2651 if(unlikely(!adapter->clean_rx(adapter) &
2341 !e1000_clean_tx_irq(adapter))) 2652 !e1000_clean_tx_irq(adapter)))
2342 break; 2653 break;
2343 2654
@@ -2363,7 +2674,7 @@ e1000_clean(struct net_device *netdev, int *budget)
2363 int work_done = 0; 2674 int work_done = 0;
2364 2675
2365 tx_cleaned = e1000_clean_tx_irq(adapter); 2676 tx_cleaned = e1000_clean_tx_irq(adapter);
2366 e1000_clean_rx_irq(adapter, &work_done, work_to_do); 2677 adapter->clean_rx(adapter, &work_done, work_to_do);
2367 2678
2368 *budget -= work_done; 2679 *budget -= work_done;
2369 netdev->quota -= work_done; 2680 netdev->quota -= work_done;
@@ -2501,41 +2812,57 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter)
2501 2812
2502/** 2813/**
2503 * e1000_rx_checksum - Receive Checksum Offload for 82543 2814 * e1000_rx_checksum - Receive Checksum Offload for 82543
2504 * @adapter: board private structure 2815 * @adapter: board private structure
2505 * @rx_desc: receive descriptor 2816 * @status_err: receive descriptor status and error fields
2506 * @sk_buff: socket buffer with received data 2817 * @csum: receive descriptor csum field
2818 * @sk_buff: socket buffer with received data
2507 **/ 2819 **/
2508 2820
2509static inline void 2821static inline void
2510e1000_rx_checksum(struct e1000_adapter *adapter, 2822e1000_rx_checksum(struct e1000_adapter *adapter,
2511 struct e1000_rx_desc *rx_desc, 2823 uint32_t status_err, uint32_t csum,
2512 struct sk_buff *skb) 2824 struct sk_buff *skb)
2513{ 2825{
2826 uint16_t status = (uint16_t)status_err;
2827 uint8_t errors = (uint8_t)(status_err >> 24);
2828 skb->ip_summed = CHECKSUM_NONE;
2829
2514 /* 82543 or newer only */ 2830 /* 82543 or newer only */
2515 if(unlikely((adapter->hw.mac_type < e1000_82543) || 2831 if(unlikely(adapter->hw.mac_type < e1000_82543)) return;
2516 /* Ignore Checksum bit is set */ 2832 /* Ignore Checksum bit is set */
2517 (rx_desc->status & E1000_RXD_STAT_IXSM) || 2833 if(unlikely(status & E1000_RXD_STAT_IXSM)) return;
2518 /* TCP Checksum has not been calculated */ 2834 /* TCP/UDP checksum error bit is set */
2519 (!(rx_desc->status & E1000_RXD_STAT_TCPCS)))) { 2835 if(unlikely(errors & E1000_RXD_ERR_TCPE)) {
2520 skb->ip_summed = CHECKSUM_NONE;
2521 return;
2522 }
2523
2524 /* At this point we know the hardware did the TCP checksum */
2525 /* now look at the TCP checksum error bit */
2526 if(rx_desc->errors & E1000_RXD_ERR_TCPE) {
2527 /* let the stack verify checksum errors */ 2836 /* let the stack verify checksum errors */
2528 skb->ip_summed = CHECKSUM_NONE;
2529 adapter->hw_csum_err++; 2837 adapter->hw_csum_err++;
2838 return;
2839 }
2840 /* TCP/UDP Checksum has not been calculated */
2841 if(adapter->hw.mac_type <= e1000_82547_rev_2) {
2842 if(!(status & E1000_RXD_STAT_TCPCS))
2843 return;
2530 } else { 2844 } else {
2845 if(!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2846 return;
2847 }
2848 /* It must be a TCP or UDP packet with a valid checksum */
2849 if (likely(status & E1000_RXD_STAT_TCPCS)) {
2531 /* TCP checksum is good */ 2850 /* TCP checksum is good */
2532 skb->ip_summed = CHECKSUM_UNNECESSARY; 2851 skb->ip_summed = CHECKSUM_UNNECESSARY;
2533 adapter->hw_csum_good++; 2852 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
2853 /* IP fragment with UDP payload */
2854 /* Hardware complements the payload checksum, so we undo it
2855 * and then put the value in host order for further stack use.
2856 */
2857 csum = ntohl(csum ^ 0xFFFF);
2858 skb->csum = csum;
2859 skb->ip_summed = CHECKSUM_HW;
2534 } 2860 }
2861 adapter->hw_csum_good++;
2535} 2862}
2536 2863
2537/** 2864/**
2538 * e1000_clean_rx_irq - Send received data up the network stack 2865 * e1000_clean_rx_irq - Send received data up the network stack; legacy
2539 * @adapter: board private structure 2866 * @adapter: board private structure
2540 **/ 2867 **/
2541 2868
@@ -2608,15 +2935,17 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter)
2608 skb_put(skb, length - ETHERNET_FCS_SIZE); 2935 skb_put(skb, length - ETHERNET_FCS_SIZE);
2609 2936
2610 /* Receive Checksum Offload */ 2937 /* Receive Checksum Offload */
2611 e1000_rx_checksum(adapter, rx_desc, skb); 2938 e1000_rx_checksum(adapter,
2612 2939 (uint32_t)(rx_desc->status) |
2940 ((uint32_t)(rx_desc->errors) << 24),
2941 rx_desc->csum, skb);
2613 skb->protocol = eth_type_trans(skb, netdev); 2942 skb->protocol = eth_type_trans(skb, netdev);
2614#ifdef CONFIG_E1000_NAPI 2943#ifdef CONFIG_E1000_NAPI
2615 if(unlikely(adapter->vlgrp && 2944 if(unlikely(adapter->vlgrp &&
2616 (rx_desc->status & E1000_RXD_STAT_VP))) { 2945 (rx_desc->status & E1000_RXD_STAT_VP))) {
2617 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 2946 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2618 le16_to_cpu(rx_desc->special) & 2947 le16_to_cpu(rx_desc->special) &
2619 E1000_RXD_SPC_VLAN_MASK); 2948 E1000_RXD_SPC_VLAN_MASK);
2620 } else { 2949 } else {
2621 netif_receive_skb(skb); 2950 netif_receive_skb(skb);
2622 } 2951 }
@@ -2639,16 +2968,142 @@ next_desc:
2639 2968
2640 rx_desc = E1000_RX_DESC(*rx_ring, i); 2969 rx_desc = E1000_RX_DESC(*rx_ring, i);
2641 } 2970 }
2642
2643 rx_ring->next_to_clean = i; 2971 rx_ring->next_to_clean = i;
2972 adapter->alloc_rx_buf(adapter);
2973
2974 return cleaned;
2975}
2976
2977/**
2978 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
2979 * @adapter: board private structure
2980 **/
2981
2982static boolean_t
2983#ifdef CONFIG_E1000_NAPI
2984e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, int *work_done,
2985 int work_to_do)
2986#else
2987e1000_clean_rx_irq_ps(struct e1000_adapter *adapter)
2988#endif
2989{
2990 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
2991 union e1000_rx_desc_packet_split *rx_desc;
2992 struct net_device *netdev = adapter->netdev;
2993 struct pci_dev *pdev = adapter->pdev;
2994 struct e1000_buffer *buffer_info;
2995 struct e1000_ps_page *ps_page;
2996 struct e1000_ps_page_dma *ps_page_dma;
2997 struct sk_buff *skb;
2998 unsigned int i, j;
2999 uint32_t length, staterr;
3000 boolean_t cleaned = FALSE;
3001
3002 i = rx_ring->next_to_clean;
3003 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3004 staterr = rx_desc->wb.middle.status_error;
3005
3006 while(staterr & E1000_RXD_STAT_DD) {
3007 buffer_info = &rx_ring->buffer_info[i];
3008 ps_page = &rx_ring->ps_page[i];
3009 ps_page_dma = &rx_ring->ps_page_dma[i];
3010#ifdef CONFIG_E1000_NAPI
3011 if(unlikely(*work_done >= work_to_do))
3012 break;
3013 (*work_done)++;
3014#endif
3015 cleaned = TRUE;
3016 pci_unmap_single(pdev, buffer_info->dma,
3017 buffer_info->length,
3018 PCI_DMA_FROMDEVICE);
3019
3020 skb = buffer_info->skb;
3021
3022 if(unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
3023 E1000_DBG("%s: Packet Split buffers didn't pick up"
3024 " the full packet\n", netdev->name);
3025 dev_kfree_skb_irq(skb);
3026 goto next_desc;
3027 }
2644 3028
2645 e1000_alloc_rx_buffers(adapter); 3029 if(unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3030 dev_kfree_skb_irq(skb);
3031 goto next_desc;
3032 }
3033
3034 length = le16_to_cpu(rx_desc->wb.middle.length0);
3035
3036 if(unlikely(!length)) {
3037 E1000_DBG("%s: Last part of the packet spanning"
3038 " multiple descriptors\n", netdev->name);
3039 dev_kfree_skb_irq(skb);
3040 goto next_desc;
3041 }
3042
3043 /* Good Receive */
3044 skb_put(skb, length);
3045
3046 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
3047 if(!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
3048 break;
3049
3050 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3051 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3052 ps_page_dma->ps_page_dma[j] = 0;
3053 skb_shinfo(skb)->frags[j].page =
3054 ps_page->ps_page[j];
3055 ps_page->ps_page[j] = NULL;
3056 skb_shinfo(skb)->frags[j].page_offset = 0;
3057 skb_shinfo(skb)->frags[j].size = length;
3058 skb_shinfo(skb)->nr_frags++;
3059 skb->len += length;
3060 skb->data_len += length;
3061 }
3062
3063 e1000_rx_checksum(adapter, staterr,
3064 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
3065 skb->protocol = eth_type_trans(skb, netdev);
3066
3067#ifdef HAVE_RX_ZERO_COPY
3068 if(likely(rx_desc->wb.upper.header_status &
3069 E1000_RXDPS_HDRSTAT_HDRSP))
3070 skb_shinfo(skb)->zero_copy = TRUE;
3071#endif
3072#ifdef CONFIG_E1000_NAPI
3073 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3074 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3075 le16_to_cpu(rx_desc->wb.middle.vlan &
3076 E1000_RXD_SPC_VLAN_MASK));
3077 } else {
3078 netif_receive_skb(skb);
3079 }
3080#else /* CONFIG_E1000_NAPI */
3081 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3082 vlan_hwaccel_rx(skb, adapter->vlgrp,
3083 le16_to_cpu(rx_desc->wb.middle.vlan &
3084 E1000_RXD_SPC_VLAN_MASK));
3085 } else {
3086 netif_rx(skb);
3087 }
3088#endif /* CONFIG_E1000_NAPI */
3089 netdev->last_rx = jiffies;
3090
3091next_desc:
3092 rx_desc->wb.middle.status_error &= ~0xFF;
3093 buffer_info->skb = NULL;
3094 if(unlikely(++i == rx_ring->count)) i = 0;
3095
3096 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3097 staterr = rx_desc->wb.middle.status_error;
3098 }
3099 rx_ring->next_to_clean = i;
3100 adapter->alloc_rx_buf(adapter);
2646 3101
2647 return cleaned; 3102 return cleaned;
2648} 3103}
2649 3104
2650/** 3105/**
2651 * e1000_alloc_rx_buffers - Replace used receive buffers 3106 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
2652 * @adapter: address of board private structure 3107 * @adapter: address of board private structure
2653 **/ 3108 **/
2654 3109
@@ -2753,6 +3208,95 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter)
2753} 3208}
2754 3209
2755/** 3210/**
3211 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3212 * @adapter: address of board private structure
3213 **/
3214
3215static void
3216e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter)
3217{
3218 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
3219 struct net_device *netdev = adapter->netdev;
3220 struct pci_dev *pdev = adapter->pdev;
3221 union e1000_rx_desc_packet_split *rx_desc;
3222 struct e1000_buffer *buffer_info;
3223 struct e1000_ps_page *ps_page;
3224 struct e1000_ps_page_dma *ps_page_dma;
3225 struct sk_buff *skb;
3226 unsigned int i, j;
3227
3228 i = rx_ring->next_to_use;
3229 buffer_info = &rx_ring->buffer_info[i];
3230 ps_page = &rx_ring->ps_page[i];
3231 ps_page_dma = &rx_ring->ps_page_dma[i];
3232
3233 while(!buffer_info->skb) {
3234 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3235
3236 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
3237 if(unlikely(!ps_page->ps_page[j])) {
3238 ps_page->ps_page[j] =
3239 alloc_page(GFP_ATOMIC);
3240 if(unlikely(!ps_page->ps_page[j]))
3241 goto no_buffers;
3242 ps_page_dma->ps_page_dma[j] =
3243 pci_map_page(pdev,
3244 ps_page->ps_page[j],
3245 0, PAGE_SIZE,
3246 PCI_DMA_FROMDEVICE);
3247 }
3248 /* Refresh the desc even if buffer_addrs didn't
3249 * change because each write-back erases this info.
3250 */
3251 rx_desc->read.buffer_addr[j+1] =
3252 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
3253 }
3254
3255 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3256
3257 if(unlikely(!skb))
3258 break;
3259
3260 /* Make buffer alignment 2 beyond a 16 byte boundary
3261 * this will result in a 16 byte aligned IP header after
3262 * the 14 byte MAC header is removed
3263 */
3264 skb_reserve(skb, NET_IP_ALIGN);
3265
3266 skb->dev = netdev;
3267
3268 buffer_info->skb = skb;
3269 buffer_info->length = adapter->rx_ps_bsize0;
3270 buffer_info->dma = pci_map_single(pdev, skb->data,
3271 adapter->rx_ps_bsize0,
3272 PCI_DMA_FROMDEVICE);
3273
3274 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
3275
3276 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3277 /* Force memory writes to complete before letting h/w
3278 * know there are new descriptors to fetch. (Only
3279 * applicable for weak-ordered memory model archs,
3280 * such as IA-64). */
3281 wmb();
3282 /* Hardware increments by 16 bytes, but packet split
3283 * descriptors are 32 bytes...so we increment tail
3284 * twice as much.
3285 */
3286 E1000_WRITE_REG(&adapter->hw, RDT, i<<1);
3287 }
3288
3289 if(unlikely(++i == rx_ring->count)) i = 0;
3290 buffer_info = &rx_ring->buffer_info[i];
3291 ps_page = &rx_ring->ps_page[i];
3292 ps_page_dma = &rx_ring->ps_page_dma[i];
3293 }
3294
3295no_buffers:
3296 rx_ring->next_to_use = i;
3297}
3298
3299/**
2756 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers. 3300 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
2757 * @adapter: 3301 * @adapter:
2758 **/ 3302 **/
@@ -2986,6 +3530,7 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2986 rctl |= E1000_RCTL_VFE; 3530 rctl |= E1000_RCTL_VFE;
2987 rctl &= ~E1000_RCTL_CFIEN; 3531 rctl &= ~E1000_RCTL_CFIEN;
2988 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 3532 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
3533 e1000_update_mng_vlan(adapter);
2989 } else { 3534 } else {
2990 /* disable VLAN tag insert/strip */ 3535 /* disable VLAN tag insert/strip */
2991 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 3536 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
@@ -2996,6 +3541,10 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2996 rctl = E1000_READ_REG(&adapter->hw, RCTL); 3541 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2997 rctl &= ~E1000_RCTL_VFE; 3542 rctl &= ~E1000_RCTL_VFE;
2998 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 3543 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
3544 if(adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
3545 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3546 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3547 }
2999 } 3548 }
3000 3549
3001 e1000_irq_enable(adapter); 3550 e1000_irq_enable(adapter);
@@ -3006,7 +3555,10 @@ e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
3006{ 3555{
3007 struct e1000_adapter *adapter = netdev->priv; 3556 struct e1000_adapter *adapter = netdev->priv;
3008 uint32_t vfta, index; 3557 uint32_t vfta, index;
3009 3558 if((adapter->hw.mng_cookie.status &
3559 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
3560 (vid == adapter->mng_vlan_id))
3561 return;
3010 /* add VID to filter table */ 3562 /* add VID to filter table */
3011 index = (vid >> 5) & 0x7F; 3563 index = (vid >> 5) & 0x7F;
3012 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index); 3564 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
@@ -3027,6 +3579,10 @@ e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
3027 3579
3028 e1000_irq_enable(adapter); 3580 e1000_irq_enable(adapter);
3029 3581
3582 if((adapter->hw.mng_cookie.status &
3583 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
3584 (vid == adapter->mng_vlan_id))
3585 return;
3030 /* remove VID from filter table */ 3586 /* remove VID from filter table */
3031 index = (vid >> 5) & 0x7F; 3587 index = (vid >> 5) & 0x7F;
3032 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index); 3588 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
@@ -3102,7 +3658,7 @@ e1000_suspend(struct pci_dev *pdev, uint32_t state)
3102{ 3658{
3103 struct net_device *netdev = pci_get_drvdata(pdev); 3659 struct net_device *netdev = pci_get_drvdata(pdev);
3104 struct e1000_adapter *adapter = netdev->priv; 3660 struct e1000_adapter *adapter = netdev->priv;
3105 uint32_t ctrl, ctrl_ext, rctl, manc, status; 3661 uint32_t ctrl, ctrl_ext, rctl, manc, status, swsm;
3106 uint32_t wufc = adapter->wol; 3662 uint32_t wufc = adapter->wol;
3107 3663
3108 netif_device_detach(netdev); 3664 netif_device_detach(netdev);
@@ -3144,6 +3700,9 @@ e1000_suspend(struct pci_dev *pdev, uint32_t state)
3144 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext); 3700 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
3145 } 3701 }
3146 3702
3703 /* Allow time for pending master requests to run */
3704 e1000_disable_pciex_master(&adapter->hw);
3705
3147 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN); 3706 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
3148 E1000_WRITE_REG(&adapter->hw, WUFC, wufc); 3707 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
3149 pci_enable_wake(pdev, 3, 1); 3708 pci_enable_wake(pdev, 3, 1);
@@ -3168,6 +3727,16 @@ e1000_suspend(struct pci_dev *pdev, uint32_t state)
3168 } 3727 }
3169 } 3728 }
3170 3729
3730 switch(adapter->hw.mac_type) {
3731 case e1000_82573:
3732 swsm = E1000_READ_REG(&adapter->hw, SWSM);
3733 E1000_WRITE_REG(&adapter->hw, SWSM,
3734 swsm & ~E1000_SWSM_DRV_LOAD);
3735 break;
3736 default:
3737 break;
3738 }
3739
3171 pci_disable_device(pdev); 3740 pci_disable_device(pdev);
3172 3741
3173 state = (state > 0) ? 3 : 0; 3742 state = (state > 0) ? 3 : 0;
@@ -3182,7 +3751,7 @@ e1000_resume(struct pci_dev *pdev)
3182{ 3751{
3183 struct net_device *netdev = pci_get_drvdata(pdev); 3752 struct net_device *netdev = pci_get_drvdata(pdev);
3184 struct e1000_adapter *adapter = netdev->priv; 3753 struct e1000_adapter *adapter = netdev->priv;
3185 uint32_t manc, ret; 3754 uint32_t manc, ret, swsm;
3186 3755
3187 pci_set_power_state(pdev, 0); 3756 pci_set_power_state(pdev, 0);
3188 pci_restore_state(pdev); 3757 pci_restore_state(pdev);
@@ -3207,10 +3776,19 @@ e1000_resume(struct pci_dev *pdev)
3207 E1000_WRITE_REG(&adapter->hw, MANC, manc); 3776 E1000_WRITE_REG(&adapter->hw, MANC, manc);
3208 } 3777 }
3209 3778
3779 switch(adapter->hw.mac_type) {
3780 case e1000_82573:
3781 swsm = E1000_READ_REG(&adapter->hw, SWSM);
3782 E1000_WRITE_REG(&adapter->hw, SWSM,
3783 swsm | E1000_SWSM_DRV_LOAD);
3784 break;
3785 default:
3786 break;
3787 }
3788
3210 return 0; 3789 return 0;
3211} 3790}
3212#endif 3791#endif
3213
3214#ifdef CONFIG_NET_POLL_CONTROLLER 3792#ifdef CONFIG_NET_POLL_CONTROLLER
3215/* 3793/*
3216 * Polling 'interrupt' - used by things like netconsole to send skbs 3794 * Polling 'interrupt' - used by things like netconsole to send skbs
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index 2efa3b1b64dc..b1915e8eb564 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -101,6 +101,29 @@ typedef enum {
101 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 101 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
102 ((offset) << 2))) 102 ((offset) << 2)))
103 103
104#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
105#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
106
107#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
108 writew((value), ((a)->hw_addr + \
109 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
110 ((offset) << 1))))
111
112#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
113 readw((a)->hw_addr + \
114 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
115 ((offset) << 1)))
116
117#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
118 writeb((value), ((a)->hw_addr + \
119 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
120 (offset))))
121
122#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
123 readb((a)->hw_addr + \
124 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
125 (offset)))
126
104#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) 127#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
105 128
106#endif /* _E1000_OSDEP_H_ */ 129#endif /* _E1000_OSDEP_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 13:07:19 -0500