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-rw-r--r--drivers/scsi/ahci.c660
-rw-r--r--drivers/scsi/libata-core.c12
-rw-r--r--drivers/scsi/libata-scsi.c8
-rw-r--r--include/linux/libata.h6
4 files changed, 449 insertions, 237 deletions
diff --git a/drivers/scsi/ahci.c b/drivers/scsi/ahci.c
index 904c25fb4ba4..f5734a97580a 100644
--- a/drivers/scsi/ahci.c
+++ b/drivers/scsi/ahci.c
@@ -92,7 +92,9 @@ enum {
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ 92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
93 93
94 /* HOST_CAP bits */ 94 /* HOST_CAP bits */
95 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
95 HOST_CAP_CLO = (1 << 24), /* Command List Override support */ 96 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
97 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
96 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ 98 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
97 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ 99 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
98 100
@@ -155,6 +157,7 @@ enum {
155 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ 157 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
156 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ 158 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
157 159
160 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
158 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ 161 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
159 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ 162 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
160 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ 163 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
@@ -212,6 +215,10 @@ static void ahci_freeze(struct ata_port *ap);
212static void ahci_thaw(struct ata_port *ap); 215static void ahci_thaw(struct ata_port *ap);
213static void ahci_error_handler(struct ata_port *ap); 216static void ahci_error_handler(struct ata_port *ap);
214static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 217static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
218static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
219static int ahci_port_resume(struct ata_port *ap);
220static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
221static int ahci_pci_device_resume(struct pci_dev *pdev);
215static void ahci_remove_one (struct pci_dev *pdev); 222static void ahci_remove_one (struct pci_dev *pdev);
216 223
217static struct scsi_host_template ahci_sht = { 224static struct scsi_host_template ahci_sht = {
@@ -231,6 +238,8 @@ static struct scsi_host_template ahci_sht = {
231 .slave_configure = ata_scsi_slave_config, 238 .slave_configure = ata_scsi_slave_config,
232 .slave_destroy = ata_scsi_slave_destroy, 239 .slave_destroy = ata_scsi_slave_destroy,
233 .bios_param = ata_std_bios_param, 240 .bios_param = ata_std_bios_param,
241 .suspend = ata_scsi_device_suspend,
242 .resume = ata_scsi_device_resume,
234}; 243};
235 244
236static const struct ata_port_operations ahci_ops = { 245static const struct ata_port_operations ahci_ops = {
@@ -257,6 +266,9 @@ static const struct ata_port_operations ahci_ops = {
257 .error_handler = ahci_error_handler, 266 .error_handler = ahci_error_handler,
258 .post_internal_cmd = ahci_post_internal_cmd, 267 .post_internal_cmd = ahci_post_internal_cmd,
259 268
269 .port_suspend = ahci_port_suspend,
270 .port_resume = ahci_port_resume,
271
260 .port_start = ahci_port_start, 272 .port_start = ahci_port_start,
261 .port_stop = ahci_port_stop, 273 .port_stop = ahci_port_stop,
262}; 274};
@@ -350,6 +362,14 @@ static const struct pci_device_id ahci_pci_tbl[] = {
350 { PCI_VENDOR_ID_NVIDIA, 0x044f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 362 { PCI_VENDOR_ID_NVIDIA, 0x044f, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
351 board_ahci }, /* MCP65 */ 363 board_ahci }, /* MCP65 */
352 364
365 /* SiS */
366 { PCI_VENDOR_ID_SI, 0x1184, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
367 board_ahci }, /* SiS 966 */
368 { PCI_VENDOR_ID_SI, 0x1185, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
369 board_ahci }, /* SiS 966 */
370 { PCI_VENDOR_ID_SI, 0x0186, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
371 board_ahci }, /* SiS 968 */
372
353 { } /* terminate list */ 373 { } /* terminate list */
354}; 374};
355 375
@@ -358,6 +378,8 @@ static struct pci_driver ahci_pci_driver = {
358 .name = DRV_NAME, 378 .name = DRV_NAME,
359 .id_table = ahci_pci_tbl, 379 .id_table = ahci_pci_tbl,
360 .probe = ahci_init_one, 380 .probe = ahci_init_one,
381 .suspend = ahci_pci_device_suspend,
382 .resume = ahci_pci_device_resume,
361 .remove = ahci_remove_one, 383 .remove = ahci_remove_one,
362}; 384};
363 385
@@ -372,177 +394,289 @@ static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int por
372 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port); 394 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
373} 395}
374 396
375static int ahci_port_start(struct ata_port *ap) 397static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
376{ 398{
377 struct device *dev = ap->host_set->dev; 399 unsigned int sc_reg;
378 struct ahci_host_priv *hpriv = ap->host_set->private_data;
379 struct ahci_port_priv *pp;
380 void __iomem *mmio = ap->host_set->mmio_base;
381 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
382 void *mem;
383 dma_addr_t mem_dma;
384 int rc;
385
386 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
387 if (!pp)
388 return -ENOMEM;
389 memset(pp, 0, sizeof(*pp));
390 400
391 rc = ata_pad_alloc(ap, dev); 401 switch (sc_reg_in) {
392 if (rc) { 402 case SCR_STATUS: sc_reg = 0; break;
393 kfree(pp); 403 case SCR_CONTROL: sc_reg = 1; break;
394 return rc; 404 case SCR_ERROR: sc_reg = 2; break;
405 case SCR_ACTIVE: sc_reg = 3; break;
406 default:
407 return 0xffffffffU;
395 } 408 }
396 409
397 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL); 410 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
398 if (!mem) { 411}
399 ata_pad_free(ap, dev);
400 kfree(pp);
401 return -ENOMEM;
402 }
403 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
404 412
405 /*
406 * First item in chunk of DMA memory: 32-slot command table,
407 * 32 bytes each in size
408 */
409 pp->cmd_slot = mem;
410 pp->cmd_slot_dma = mem_dma;
411 413
412 mem += AHCI_CMD_SLOT_SZ; 414static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
413 mem_dma += AHCI_CMD_SLOT_SZ; 415 u32 val)
416{
417 unsigned int sc_reg;
414 418
415 /* 419 switch (sc_reg_in) {
416 * Second item: Received-FIS area 420 case SCR_STATUS: sc_reg = 0; break;
417 */ 421 case SCR_CONTROL: sc_reg = 1; break;
418 pp->rx_fis = mem; 422 case SCR_ERROR: sc_reg = 2; break;
419 pp->rx_fis_dma = mem_dma; 423 case SCR_ACTIVE: sc_reg = 3; break;
424 default:
425 return;
426 }
420 427
421 mem += AHCI_RX_FIS_SZ; 428 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
422 mem_dma += AHCI_RX_FIS_SZ; 429}
423 430
424 /* 431static void ahci_start_engine(void __iomem *port_mmio)
425 * Third item: data area for storing a single command 432{
426 * and its scatter-gather table 433 u32 tmp;
427 */
428 pp->cmd_tbl = mem;
429 pp->cmd_tbl_dma = mem_dma;
430 434
431 ap->private_data = pp; 435 /* start DMA */
436 tmp = readl(port_mmio + PORT_CMD);
437 tmp |= PORT_CMD_START;
438 writel(tmp, port_mmio + PORT_CMD);
439 readl(port_mmio + PORT_CMD); /* flush */
440}
432 441
433 if (hpriv->cap & HOST_CAP_64) 442static int ahci_stop_engine(void __iomem *port_mmio)
434 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); 443{
435 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 444 u32 tmp;
436 readl(port_mmio + PORT_LST_ADDR); /* flush */
437 445
438 if (hpriv->cap & HOST_CAP_64) 446 tmp = readl(port_mmio + PORT_CMD);
439 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
440 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
441 readl(port_mmio + PORT_FIS_ADDR); /* flush */
442 447
443 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 448 /* check if the HBA is idle */
444 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 449 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
445 PORT_CMD_START, port_mmio + PORT_CMD); 450 return 0;
446 readl(port_mmio + PORT_CMD); /* flush */ 451
452 /* setting HBA to idle */
453 tmp &= ~PORT_CMD_START;
454 writel(tmp, port_mmio + PORT_CMD);
455
456 /* wait for engine to stop. This could be as long as 500 msec */
457 tmp = ata_wait_register(port_mmio + PORT_CMD,
458 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
459 if (tmp & PORT_CMD_LIST_ON)
460 return -EIO;
447 461
448 return 0; 462 return 0;
449} 463}
450 464
465static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
466 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
467{
468 u32 tmp;
469
470 /* set FIS registers */
471 if (cap & HOST_CAP_64)
472 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
473 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
451 474
452static void ahci_port_stop(struct ata_port *ap) 475 if (cap & HOST_CAP_64)
476 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
477 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
478
479 /* enable FIS reception */
480 tmp = readl(port_mmio + PORT_CMD);
481 tmp |= PORT_CMD_FIS_RX;
482 writel(tmp, port_mmio + PORT_CMD);
483
484 /* flush */
485 readl(port_mmio + PORT_CMD);
486}
487
488static int ahci_stop_fis_rx(void __iomem *port_mmio)
453{ 489{
454 struct device *dev = ap->host_set->dev;
455 struct ahci_port_priv *pp = ap->private_data;
456 void __iomem *mmio = ap->host_set->mmio_base;
457 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
458 u32 tmp; 490 u32 tmp;
459 491
492 /* disable FIS reception */
460 tmp = readl(port_mmio + PORT_CMD); 493 tmp = readl(port_mmio + PORT_CMD);
461 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX); 494 tmp &= ~PORT_CMD_FIS_RX;
462 writel(tmp, port_mmio + PORT_CMD); 495 writel(tmp, port_mmio + PORT_CMD);
463 readl(port_mmio + PORT_CMD); /* flush */
464 496
465 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so 497 /* wait for completion, spec says 500ms, give it 1000 */
466 * this is slightly incorrect. 498 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
467 */ 499 PORT_CMD_FIS_ON, 10, 1000);
468 msleep(500); 500 if (tmp & PORT_CMD_FIS_ON)
501 return -EBUSY;
469 502
470 ap->private_data = NULL; 503 return 0;
471 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
472 pp->cmd_slot, pp->cmd_slot_dma);
473 ata_pad_free(ap, dev);
474 kfree(pp);
475} 504}
476 505
477static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) 506static void ahci_power_up(void __iomem *port_mmio, u32 cap)
478{ 507{
479 unsigned int sc_reg; 508 u32 cmd;
480 509
481 switch (sc_reg_in) { 510 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
482 case SCR_STATUS: sc_reg = 0; break; 511
483 case SCR_CONTROL: sc_reg = 1; break; 512 /* spin up device */
484 case SCR_ERROR: sc_reg = 2; break; 513 if (cap & HOST_CAP_SSS) {
485 case SCR_ACTIVE: sc_reg = 3; break; 514 cmd |= PORT_CMD_SPIN_UP;
486 default: 515 writel(cmd, port_mmio + PORT_CMD);
487 return 0xffffffffU;
488 } 516 }
489 517
490 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); 518 /* wake up link */
519 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
491} 520}
492 521
522static void ahci_power_down(void __iomem *port_mmio, u32 cap)
523{
524 u32 cmd, scontrol;
493 525
494static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, 526 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
495 u32 val) 527
528 if (cap & HOST_CAP_SSC) {
529 /* enable transitions to slumber mode */
530 scontrol = readl(port_mmio + PORT_SCR_CTL);
531 if ((scontrol & 0x0f00) > 0x100) {
532 scontrol &= ~0xf00;
533 writel(scontrol, port_mmio + PORT_SCR_CTL);
534 }
535
536 /* put device into slumber mode */
537 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
538
539 /* wait for the transition to complete */
540 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
541 PORT_CMD_ICC_SLUMBER, 1, 50);
542 }
543
544 /* put device into listen mode */
545 if (cap & HOST_CAP_SSS) {
546 /* first set PxSCTL.DET to 0 */
547 scontrol = readl(port_mmio + PORT_SCR_CTL);
548 scontrol &= ~0xf;
549 writel(scontrol, port_mmio + PORT_SCR_CTL);
550
551 /* then set PxCMD.SUD to 0 */
552 cmd &= ~PORT_CMD_SPIN_UP;
553 writel(cmd, port_mmio + PORT_CMD);
554 }
555}
556
557static void ahci_init_port(void __iomem *port_mmio, u32 cap,
558 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
496{ 559{
497 unsigned int sc_reg; 560 /* power up */
561 ahci_power_up(port_mmio, cap);
498 562
499 switch (sc_reg_in) { 563 /* enable FIS reception */
500 case SCR_STATUS: sc_reg = 0; break; 564 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
501 case SCR_CONTROL: sc_reg = 1; break; 565
502 case SCR_ERROR: sc_reg = 2; break; 566 /* enable DMA */
503 case SCR_ACTIVE: sc_reg = 3; break; 567 ahci_start_engine(port_mmio);
504 default: 568}
505 return; 569
570static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
571{
572 int rc;
573
574 /* disable DMA */
575 rc = ahci_stop_engine(port_mmio);
576 if (rc) {
577 *emsg = "failed to stop engine";
578 return rc;
506 } 579 }
507 580
508 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); 581 /* disable FIS reception */
582 rc = ahci_stop_fis_rx(port_mmio);
583 if (rc) {
584 *emsg = "failed stop FIS RX";
585 return rc;
586 }
587
588 /* put device into slumber mode */
589 ahci_power_down(port_mmio, cap);
590
591 return 0;
509} 592}
510 593
511static int ahci_stop_engine(struct ata_port *ap) 594static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
512{ 595{
513 void __iomem *mmio = ap->host_set->mmio_base; 596 u32 cap_save, tmp;
514 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
515 int work;
516 u32 tmp;
517 597
518 tmp = readl(port_mmio + PORT_CMD); 598 cap_save = readl(mmio + HOST_CAP);
519 tmp &= ~PORT_CMD_START; 599 cap_save &= ( (1<<28) | (1<<17) );
520 writel(tmp, port_mmio + PORT_CMD); 600 cap_save |= (1 << 27);
521 601
522 /* wait for engine to stop. TODO: this could be 602 /* global controller reset */
523 * as long as 500 msec 603 tmp = readl(mmio + HOST_CTL);
604 if ((tmp & HOST_RESET) == 0) {
605 writel(tmp | HOST_RESET, mmio + HOST_CTL);
606 readl(mmio + HOST_CTL); /* flush */
607 }
608
609 /* reset must complete within 1 second, or
610 * the hardware should be considered fried.
524 */ 611 */
525 work = 1000; 612 ssleep(1);
526 while (work-- > 0) { 613
527 tmp = readl(port_mmio + PORT_CMD); 614 tmp = readl(mmio + HOST_CTL);
528 if ((tmp & PORT_CMD_LIST_ON) == 0) 615 if (tmp & HOST_RESET) {
529 return 0; 616 dev_printk(KERN_ERR, &pdev->dev,
530 udelay(10); 617 "controller reset failed (0x%x)\n", tmp);
618 return -EIO;
531 } 619 }
532 620
533 return -EIO; 621 writel(HOST_AHCI_EN, mmio + HOST_CTL);
622 (void) readl(mmio + HOST_CTL); /* flush */
623 writel(cap_save, mmio + HOST_CAP);
624 writel(0xf, mmio + HOST_PORTS_IMPL);
625 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
626
627 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
628 u16 tmp16;
629
630 /* configure PCS */
631 pci_read_config_word(pdev, 0x92, &tmp16);
632 tmp16 |= 0xf;
633 pci_write_config_word(pdev, 0x92, tmp16);
634 }
635
636 return 0;
534} 637}
535 638
536static void ahci_start_engine(struct ata_port *ap) 639static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
640 int n_ports, u32 cap)
537{ 641{
538 void __iomem *mmio = ap->host_set->mmio_base; 642 int i, rc;
539 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
540 u32 tmp; 643 u32 tmp;
541 644
542 tmp = readl(port_mmio + PORT_CMD); 645 for (i = 0; i < n_ports; i++) {
543 tmp |= PORT_CMD_START; 646 void __iomem *port_mmio = ahci_port_base(mmio, i);
544 writel(tmp, port_mmio + PORT_CMD); 647 const char *emsg = NULL;
545 readl(port_mmio + PORT_CMD); /* flush */ 648
649#if 0 /* BIOSen initialize this incorrectly */
650 if (!(hpriv->port_map & (1 << i)))
651 continue;
652#endif
653
654 /* make sure port is not active */
655 rc = ahci_deinit_port(port_mmio, cap, &emsg);
656 if (rc)
657 dev_printk(KERN_WARNING, &pdev->dev,
658 "%s (%d)\n", emsg, rc);
659
660 /* clear SError */
661 tmp = readl(port_mmio + PORT_SCR_ERR);
662 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
663 writel(tmp, port_mmio + PORT_SCR_ERR);
664
665 /* clear & turn off port IRQ */
666 tmp = readl(port_mmio + PORT_IRQ_STAT);
667 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
668 if (tmp)
669 writel(tmp, port_mmio + PORT_IRQ_STAT);
670
671 writel(1 << i, mmio + HOST_IRQ_STAT);
672 writel(0, port_mmio + PORT_IRQ_MASK);
673 }
674
675 tmp = readl(mmio + HOST_CTL);
676 VPRINTK("HOST_CTL 0x%x\n", tmp);
677 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
678 tmp = readl(mmio + HOST_CTL);
679 VPRINTK("HOST_CTL 0x%x\n", tmp);
546} 680}
547 681
548static unsigned int ahci_dev_classify(struct ata_port *ap) 682static unsigned int ahci_dev_classify(struct ata_port *ap)
@@ -626,7 +760,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
626 } 760 }
627 761
628 /* prepare for SRST (AHCI-1.1 10.4.1) */ 762 /* prepare for SRST (AHCI-1.1 10.4.1) */
629 rc = ahci_stop_engine(ap); 763 rc = ahci_stop_engine(port_mmio);
630 if (rc) { 764 if (rc) {
631 reason = "failed to stop engine"; 765 reason = "failed to stop engine";
632 goto fail_restart; 766 goto fail_restart;
@@ -647,7 +781,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
647 } 781 }
648 782
649 /* restart engine */ 783 /* restart engine */
650 ahci_start_engine(ap); 784 ahci_start_engine(port_mmio);
651 785
652 ata_tf_init(ap->device, &tf); 786 ata_tf_init(ap->device, &tf);
653 fis = pp->cmd_tbl; 787 fis = pp->cmd_tbl;
@@ -706,7 +840,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
706 return 0; 840 return 0;
707 841
708 fail_restart: 842 fail_restart:
709 ahci_start_engine(ap); 843 ahci_start_engine(port_mmio);
710 fail: 844 fail:
711 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); 845 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
712 return rc; 846 return rc;
@@ -717,11 +851,13 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
717 struct ahci_port_priv *pp = ap->private_data; 851 struct ahci_port_priv *pp = ap->private_data;
718 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 852 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
719 struct ata_taskfile tf; 853 struct ata_taskfile tf;
854 void __iomem *mmio = ap->host_set->mmio_base;
855 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
720 int rc; 856 int rc;
721 857
722 DPRINTK("ENTER\n"); 858 DPRINTK("ENTER\n");
723 859
724 ahci_stop_engine(ap); 860 ahci_stop_engine(port_mmio);
725 861
726 /* clear D2H reception area to properly wait for D2H FIS */ 862 /* clear D2H reception area to properly wait for D2H FIS */
727 ata_tf_init(ap->device, &tf); 863 ata_tf_init(ap->device, &tf);
@@ -730,7 +866,7 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
730 866
731 rc = sata_std_hardreset(ap, class); 867 rc = sata_std_hardreset(ap, class);
732 868
733 ahci_start_engine(ap); 869 ahci_start_engine(port_mmio);
734 870
735 if (rc == 0 && ata_port_online(ap)) 871 if (rc == 0 && ata_port_online(ap))
736 *class = ahci_dev_classify(ap); 872 *class = ahci_dev_classify(ap);
@@ -1046,10 +1182,13 @@ static void ahci_thaw(struct ata_port *ap)
1046 1182
1047static void ahci_error_handler(struct ata_port *ap) 1183static void ahci_error_handler(struct ata_port *ap)
1048{ 1184{
1185 void __iomem *mmio = ap->host_set->mmio_base;
1186 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1187
1049 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1188 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1050 /* restart engine */ 1189 /* restart engine */
1051 ahci_stop_engine(ap); 1190 ahci_stop_engine(port_mmio);
1052 ahci_start_engine(ap); 1191 ahci_start_engine(port_mmio);
1053 } 1192 }
1054 1193
1055 /* perform recovery */ 1194 /* perform recovery */
@@ -1060,15 +1199,176 @@ static void ahci_error_handler(struct ata_port *ap)
1060static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1199static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1061{ 1200{
1062 struct ata_port *ap = qc->ap; 1201 struct ata_port *ap = qc->ap;
1202 void __iomem *mmio = ap->host_set->mmio_base;
1203 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1063 1204
1064 if (qc->flags & ATA_QCFLAG_FAILED) 1205 if (qc->flags & ATA_QCFLAG_FAILED)
1065 qc->err_mask |= AC_ERR_OTHER; 1206 qc->err_mask |= AC_ERR_OTHER;
1066 1207
1067 if (qc->err_mask) { 1208 if (qc->err_mask) {
1068 /* make DMA engine forget about the failed command */ 1209 /* make DMA engine forget about the failed command */
1069 ahci_stop_engine(ap); 1210 ahci_stop_engine(port_mmio);
1070 ahci_start_engine(ap); 1211 ahci_start_engine(port_mmio);
1212 }
1213}
1214
1215static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1216{
1217 struct ahci_host_priv *hpriv = ap->host_set->private_data;
1218 struct ahci_port_priv *pp = ap->private_data;
1219 void __iomem *mmio = ap->host_set->mmio_base;
1220 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1221 const char *emsg = NULL;
1222 int rc;
1223
1224 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1225 if (rc) {
1226 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1227 ahci_init_port(port_mmio, hpriv->cap,
1228 pp->cmd_slot_dma, pp->rx_fis_dma);
1071 } 1229 }
1230
1231 return rc;
1232}
1233
1234static int ahci_port_resume(struct ata_port *ap)
1235{
1236 struct ahci_port_priv *pp = ap->private_data;
1237 struct ahci_host_priv *hpriv = ap->host_set->private_data;
1238 void __iomem *mmio = ap->host_set->mmio_base;
1239 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1240
1241 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1242
1243 return 0;
1244}
1245
1246static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1247{
1248 struct ata_host_set *host_set = dev_get_drvdata(&pdev->dev);
1249 void __iomem *mmio = host_set->mmio_base;
1250 u32 ctl;
1251
1252 if (mesg.event == PM_EVENT_SUSPEND) {
1253 /* AHCI spec rev1.1 section 8.3.3:
1254 * Software must disable interrupts prior to requesting a
1255 * transition of the HBA to D3 state.
1256 */
1257 ctl = readl(mmio + HOST_CTL);
1258 ctl &= ~HOST_IRQ_EN;
1259 writel(ctl, mmio + HOST_CTL);
1260 readl(mmio + HOST_CTL); /* flush */
1261 }
1262
1263 return ata_pci_device_suspend(pdev, mesg);
1264}
1265
1266static int ahci_pci_device_resume(struct pci_dev *pdev)
1267{
1268 struct ata_host_set *host_set = dev_get_drvdata(&pdev->dev);
1269 struct ahci_host_priv *hpriv = host_set->private_data;
1270 void __iomem *mmio = host_set->mmio_base;
1271 int rc;
1272
1273 ata_pci_device_do_resume(pdev);
1274
1275 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1276 rc = ahci_reset_controller(mmio, pdev);
1277 if (rc)
1278 return rc;
1279
1280 ahci_init_controller(mmio, pdev, host_set->n_ports, hpriv->cap);
1281 }
1282
1283 ata_host_set_resume(host_set);
1284
1285 return 0;
1286}
1287
1288static int ahci_port_start(struct ata_port *ap)
1289{
1290 struct device *dev = ap->host_set->dev;
1291 struct ahci_host_priv *hpriv = ap->host_set->private_data;
1292 struct ahci_port_priv *pp;
1293 void __iomem *mmio = ap->host_set->mmio_base;
1294 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1295 void *mem;
1296 dma_addr_t mem_dma;
1297 int rc;
1298
1299 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1300 if (!pp)
1301 return -ENOMEM;
1302 memset(pp, 0, sizeof(*pp));
1303
1304 rc = ata_pad_alloc(ap, dev);
1305 if (rc) {
1306 kfree(pp);
1307 return rc;
1308 }
1309
1310 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1311 if (!mem) {
1312 ata_pad_free(ap, dev);
1313 kfree(pp);
1314 return -ENOMEM;
1315 }
1316 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1317
1318 /*
1319 * First item in chunk of DMA memory: 32-slot command table,
1320 * 32 bytes each in size
1321 */
1322 pp->cmd_slot = mem;
1323 pp->cmd_slot_dma = mem_dma;
1324
1325 mem += AHCI_CMD_SLOT_SZ;
1326 mem_dma += AHCI_CMD_SLOT_SZ;
1327
1328 /*
1329 * Second item: Received-FIS area
1330 */
1331 pp->rx_fis = mem;
1332 pp->rx_fis_dma = mem_dma;
1333
1334 mem += AHCI_RX_FIS_SZ;
1335 mem_dma += AHCI_RX_FIS_SZ;
1336
1337 /*
1338 * Third item: data area for storing a single command
1339 * and its scatter-gather table
1340 */
1341 pp->cmd_tbl = mem;
1342 pp->cmd_tbl_dma = mem_dma;
1343
1344 ap->private_data = pp;
1345
1346 /* initialize port */
1347 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1348
1349 return 0;
1350}
1351
1352static void ahci_port_stop(struct ata_port *ap)
1353{
1354 struct device *dev = ap->host_set->dev;
1355 struct ahci_host_priv *hpriv = ap->host_set->private_data;
1356 struct ahci_port_priv *pp = ap->private_data;
1357 void __iomem *mmio = ap->host_set->mmio_base;
1358 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1359 const char *emsg = NULL;
1360 int rc;
1361
1362 /* de-initialize port */
1363 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1364 if (rc)
1365 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1366
1367 ap->private_data = NULL;
1368 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1369 pp->cmd_slot, pp->cmd_slot_dma);
1370 ata_pad_free(ap, dev);
1371 kfree(pp);
1072} 1372}
1073 1373
1074static void ahci_setup_port(struct ata_ioports *port, unsigned long base, 1374static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
@@ -1089,47 +1389,12 @@ static int ahci_host_init(struct ata_probe_ent *probe_ent)
1089 struct ahci_host_priv *hpriv = probe_ent->private_data; 1389 struct ahci_host_priv *hpriv = probe_ent->private_data;
1090 struct pci_dev *pdev = to_pci_dev(probe_ent->dev); 1390 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1091 void __iomem *mmio = probe_ent->mmio_base; 1391 void __iomem *mmio = probe_ent->mmio_base;
1092 u32 tmp, cap_save; 1392 unsigned int i, using_dac;
1093 unsigned int i, j, using_dac;
1094 int rc; 1393 int rc;
1095 void __iomem *port_mmio;
1096 1394
1097 cap_save = readl(mmio + HOST_CAP); 1395 rc = ahci_reset_controller(mmio, pdev);
1098 cap_save &= ( (1<<28) | (1<<17) ); 1396 if (rc)
1099 cap_save |= (1 << 27); 1397 return rc;
1100
1101 /* global controller reset */
1102 tmp = readl(mmio + HOST_CTL);
1103 if ((tmp & HOST_RESET) == 0) {
1104 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1105 readl(mmio + HOST_CTL); /* flush */
1106 }
1107
1108 /* reset must complete within 1 second, or
1109 * the hardware should be considered fried.
1110 */
1111 ssleep(1);
1112
1113 tmp = readl(mmio + HOST_CTL);
1114 if (tmp & HOST_RESET) {
1115 dev_printk(KERN_ERR, &pdev->dev,
1116 "controller reset failed (0x%x)\n", tmp);
1117 return -EIO;
1118 }
1119
1120 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1121 (void) readl(mmio + HOST_CTL); /* flush */
1122 writel(cap_save, mmio + HOST_CAP);
1123 writel(0xf, mmio + HOST_PORTS_IMPL);
1124 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1125
1126 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1127 u16 tmp16;
1128
1129 pci_read_config_word(pdev, 0x92, &tmp16);
1130 tmp16 |= 0xf;
1131 pci_write_config_word(pdev, 0x92, tmp16);
1132 }
1133 1398
1134 hpriv->cap = readl(mmio + HOST_CAP); 1399 hpriv->cap = readl(mmio + HOST_CAP);
1135 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); 1400 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
@@ -1165,63 +1430,10 @@ static int ahci_host_init(struct ata_probe_ent *probe_ent)
1165 } 1430 }
1166 } 1431 }
1167 1432
1168 for (i = 0; i < probe_ent->n_ports; i++) { 1433 for (i = 0; i < probe_ent->n_ports; i++)
1169#if 0 /* BIOSen initialize this incorrectly */ 1434 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1170 if (!(hpriv->port_map & (1 << i)))
1171 continue;
1172#endif
1173
1174 port_mmio = ahci_port_base(mmio, i);
1175 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1176
1177 ahci_setup_port(&probe_ent->port[i],
1178 (unsigned long) mmio, i);
1179
1180 /* make sure port is not active */
1181 tmp = readl(port_mmio + PORT_CMD);
1182 VPRINTK("PORT_CMD 0x%x\n", tmp);
1183 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1184 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1185 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1186 PORT_CMD_FIS_RX | PORT_CMD_START);
1187 writel(tmp, port_mmio + PORT_CMD);
1188 readl(port_mmio + PORT_CMD); /* flush */
1189
1190 /* spec says 500 msecs for each bit, so
1191 * this is slightly incorrect.
1192 */
1193 msleep(500);
1194 }
1195
1196 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1197
1198 j = 0;
1199 while (j < 100) {
1200 msleep(10);
1201 tmp = readl(port_mmio + PORT_SCR_STAT);
1202 if ((tmp & 0xf) == 0x3)
1203 break;
1204 j++;
1205 }
1206
1207 tmp = readl(port_mmio + PORT_SCR_ERR);
1208 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1209 writel(tmp, port_mmio + PORT_SCR_ERR);
1210 1435
1211 /* ack any pending irq events for this port */ 1436 ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap);
1212 tmp = readl(port_mmio + PORT_IRQ_STAT);
1213 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1214 if (tmp)
1215 writel(tmp, port_mmio + PORT_IRQ_STAT);
1216
1217 writel(1 << i, mmio + HOST_IRQ_STAT);
1218 }
1219
1220 tmp = readl(mmio + HOST_CTL);
1221 VPRINTK("HOST_CTL 0x%x\n", tmp);
1222 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1223 tmp = readl(mmio + HOST_CTL);
1224 VPRINTK("HOST_CTL 0x%x\n", tmp);
1225 1437
1226 pci_set_master(pdev); 1438 pci_set_master(pdev);
1227 1439
diff --git a/drivers/scsi/libata-core.c b/drivers/scsi/libata-core.c
index 386e5f21e191..66feebdb01c3 100644
--- a/drivers/scsi/libata-core.c
+++ b/drivers/scsi/libata-core.c
@@ -5767,11 +5767,11 @@ int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
5767 return (tmp == bits->val) ? 1 : 0; 5767 return (tmp == bits->val) ? 1 : 0;
5768} 5768}
5769 5769
5770void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t state) 5770void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t mesg)
5771{ 5771{
5772 pci_save_state(pdev); 5772 pci_save_state(pdev);
5773 5773
5774 if (state.event == PM_EVENT_SUSPEND) { 5774 if (mesg.event == PM_EVENT_SUSPEND) {
5775 pci_disable_device(pdev); 5775 pci_disable_device(pdev);
5776 pci_set_power_state(pdev, PCI_D3hot); 5776 pci_set_power_state(pdev, PCI_D3hot);
5777 } 5777 }
@@ -5785,24 +5785,24 @@ void ata_pci_device_do_resume(struct pci_dev *pdev)
5785 pci_set_master(pdev); 5785 pci_set_master(pdev);
5786} 5786}
5787 5787
5788int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t state) 5788int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
5789{ 5789{
5790 struct ata_host_set *host_set = dev_get_drvdata(&pdev->dev); 5790 struct ata_host_set *host_set = dev_get_drvdata(&pdev->dev);
5791 int rc = 0; 5791 int rc = 0;
5792 5792
5793 rc = ata_host_set_suspend(host_set, state); 5793 rc = ata_host_set_suspend(host_set, mesg);
5794 if (rc) 5794 if (rc)
5795 return rc; 5795 return rc;
5796 5796
5797 if (host_set->next) { 5797 if (host_set->next) {
5798 rc = ata_host_set_suspend(host_set->next, state); 5798 rc = ata_host_set_suspend(host_set->next, mesg);
5799 if (rc) { 5799 if (rc) {
5800 ata_host_set_resume(host_set); 5800 ata_host_set_resume(host_set);
5801 return rc; 5801 return rc;
5802 } 5802 }
5803 } 5803 }
5804 5804
5805 ata_pci_device_do_suspend(pdev, state); 5805 ata_pci_device_do_suspend(pdev, mesg);
5806 5806
5807 return 0; 5807 return 0;
5808} 5808}
diff --git a/drivers/scsi/libata-scsi.c b/drivers/scsi/libata-scsi.c
index 7ced41ecde86..1638e57028cb 100644
--- a/drivers/scsi/libata-scsi.c
+++ b/drivers/scsi/libata-scsi.c
@@ -400,7 +400,7 @@ void ata_dump_status(unsigned id, struct ata_taskfile *tf)
400/** 400/**
401 * ata_scsi_device_suspend - suspend ATA device associated with sdev 401 * ata_scsi_device_suspend - suspend ATA device associated with sdev
402 * @sdev: the SCSI device to suspend 402 * @sdev: the SCSI device to suspend
403 * @state: target power management state 403 * @mesg: target power management message
404 * 404 *
405 * Request suspend EH action on the ATA device associated with 405 * Request suspend EH action on the ATA device associated with
406 * @sdev and wait for the operation to complete. 406 * @sdev and wait for the operation to complete.
@@ -411,7 +411,7 @@ void ata_dump_status(unsigned id, struct ata_taskfile *tf)
411 * RETURNS: 411 * RETURNS:
412 * 0 on success, -errno otherwise. 412 * 0 on success, -errno otherwise.
413 */ 413 */
414int ata_scsi_device_suspend(struct scsi_device *sdev, pm_message_t state) 414int ata_scsi_device_suspend(struct scsi_device *sdev, pm_message_t mesg)
415{ 415{
416 struct ata_port *ap = ata_shost_to_port(sdev->host); 416 struct ata_port *ap = ata_shost_to_port(sdev->host);
417 struct ata_device *dev = ata_scsi_find_dev(ap, sdev); 417 struct ata_device *dev = ata_scsi_find_dev(ap, sdev);
@@ -438,7 +438,7 @@ int ata_scsi_device_suspend(struct scsi_device *sdev, pm_message_t state)
438 438
439 /* request suspend */ 439 /* request suspend */
440 action = ATA_EH_SUSPEND; 440 action = ATA_EH_SUSPEND;
441 if (state.event != PM_EVENT_SUSPEND) 441 if (mesg.event != PM_EVENT_SUSPEND)
442 action |= ATA_EH_PM_FREEZE; 442 action |= ATA_EH_PM_FREEZE;
443 ap->eh_info.dev_action[dev->devno] |= action; 443 ap->eh_info.dev_action[dev->devno] |= action;
444 ap->eh_info.flags |= ATA_EHI_QUIET; 444 ap->eh_info.flags |= ATA_EHI_QUIET;
@@ -463,7 +463,7 @@ int ata_scsi_device_suspend(struct scsi_device *sdev, pm_message_t state)
463 spin_unlock_irqrestore(ap->lock, flags); 463 spin_unlock_irqrestore(ap->lock, flags);
464 out: 464 out:
465 if (rc == 0) 465 if (rc == 0)
466 sdev->sdev_gendev.power.power_state = state; 466 sdev->sdev_gendev.power.power_state = mesg;
467 return rc; 467 return rc;
468} 468}
469 469
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 66c3100c2b94..b9416708bba2 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -676,9 +676,9 @@ extern void ata_std_ports(struct ata_ioports *ioaddr);
676extern int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info, 676extern int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info,
677 unsigned int n_ports); 677 unsigned int n_ports);
678extern void ata_pci_remove_one (struct pci_dev *pdev); 678extern void ata_pci_remove_one (struct pci_dev *pdev);
679extern void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t state); 679extern void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t mesg);
680extern void ata_pci_device_do_resume(struct pci_dev *pdev); 680extern void ata_pci_device_do_resume(struct pci_dev *pdev);
681extern int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t state); 681extern int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
682extern int ata_pci_device_resume(struct pci_dev *pdev); 682extern int ata_pci_device_resume(struct pci_dev *pdev);
683extern int ata_pci_clear_simplex(struct pci_dev *pdev); 683extern int ata_pci_clear_simplex(struct pci_dev *pdev);
684#endif /* CONFIG_PCI */ 684#endif /* CONFIG_PCI */
@@ -697,7 +697,7 @@ extern int sata_scr_write_flush(struct ata_port *ap, int reg, u32 val);
697extern int ata_port_online(struct ata_port *ap); 697extern int ata_port_online(struct ata_port *ap);
698extern int ata_port_offline(struct ata_port *ap); 698extern int ata_port_offline(struct ata_port *ap);
699extern int ata_scsi_device_resume(struct scsi_device *); 699extern int ata_scsi_device_resume(struct scsi_device *);
700extern int ata_scsi_device_suspend(struct scsi_device *, pm_message_t state); 700extern int ata_scsi_device_suspend(struct scsi_device *, pm_message_t mesg);
701extern int ata_host_set_suspend(struct ata_host_set *host_set, 701extern int ata_host_set_suspend(struct ata_host_set *host_set,
702 pm_message_t mesg); 702 pm_message_t mesg);
703extern void ata_host_set_resume(struct ata_host_set *host_set); 703extern void ata_host_set_resume(struct ata_host_set *host_set);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 20:35:32 -0500