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-rw-r--r--arch/blackfin/Kconfig68
-rw-r--r--arch/blackfin/boot/Makefile2
-rw-r--r--arch/blackfin/configs/BF518F-EZBRD_defconfig24
-rw-r--r--arch/blackfin/configs/BF526-EZBRD_defconfig22
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig22
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig25
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig22
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig22
-rw-r--r--arch/blackfin/configs/BF538-EZKIT_defconfig22
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig27
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig27
-rw-r--r--arch/blackfin/configs/BlackStamp_defconfig12
-rw-r--r--arch/blackfin/configs/CM-BF527_defconfig22
-rw-r--r--arch/blackfin/configs/CM-BF533_defconfig23
-rw-r--r--arch/blackfin/configs/CM-BF537E_defconfig22
-rw-r--r--arch/blackfin/configs/CM-BF537U_defconfig23
-rw-r--r--arch/blackfin/configs/CM-BF548_defconfig25
-rw-r--r--arch/blackfin/configs/CM-BF561_defconfig25
-rw-r--r--arch/blackfin/configs/H8606_defconfig14
-rw-r--r--arch/blackfin/configs/PNAV-10_defconfig20
-rw-r--r--arch/blackfin/configs/SRV1_defconfig14
-rw-r--r--arch/blackfin/configs/TCM-BF537_defconfig14
-rw-r--r--arch/blackfin/include/asm/blackfin.h1
-rw-r--r--arch/blackfin/include/asm/cache.h4
-rw-r--r--arch/blackfin/include/asm/cacheflush.h10
-rw-r--r--arch/blackfin/include/asm/cplb.h32
-rw-r--r--arch/blackfin/include/asm/dma-mapping.h13
-rw-r--r--arch/blackfin/include/asm/ipipe.h11
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h30
-rw-r--r--arch/blackfin/include/asm/irq.h7
-rw-r--r--arch/blackfin/include/asm/irqflags.h164
-rw-r--r--arch/blackfin/include/asm/mem_init.h88
-rw-r--r--arch/blackfin/include/asm/mem_map.h97
-rw-r--r--arch/blackfin/include/asm/system.h4
-rw-r--r--arch/blackfin/include/asm/traps.h4
-rw-r--r--arch/blackfin/include/asm/uaccess.h22
-rw-r--r--arch/blackfin/include/asm/unistd.h3
-rw-r--r--arch/blackfin/kernel/Makefile1
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbinit.c10
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbmgr.c36
-rw-r--r--arch/blackfin/kernel/ipipe.c7
-rw-r--r--arch/blackfin/kernel/irqchip.c114
-rw-r--r--arch/blackfin/kernel/kgdb.c297
-rw-r--r--arch/blackfin/kernel/mcount.S70
-rw-r--r--arch/blackfin/kernel/process.c151
-rw-r--r--arch/blackfin/kernel/setup.c122
-rw-r--r--arch/blackfin/kernel/traps.c60
-rw-r--r--arch/blackfin/mach-bf518/boards/ezbrd.c16
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h37
-rw-r--r--arch/blackfin/mach-bf518/include/mach/blackfin.h1
-rw-r--r--arch/blackfin/mach-bf518/include/mach/mem_map.h56
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c1
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c4
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c1
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h15
-rw-r--r--arch/blackfin/mach-bf527/include/mach/blackfin.h1
-rw-r--r--arch/blackfin/mach-bf527/include/mach/mem_map.h56
-rw-r--r--arch/blackfin/mach-bf533/boards/ezkit.c106
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h77
-rw-r--r--arch/blackfin/mach-bf533/include/mach/blackfin.h1
-rw-r--r--arch/blackfin/mach-bf533/include/mach/mem_map.h56
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c1
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h41
-rw-r--r--arch/blackfin/mach-bf537/include/mach/blackfin.h1
-rw-r--r--arch/blackfin/mach-bf537/include/mach/mem_map.h56
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h24
-rw-r--r--arch/blackfin/mach-bf538/include/mach/blackfin.h1
-rw-r--r--arch/blackfin/mach-bf538/include/mach/mem_map.h57
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c1
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h20
-rw-r--r--arch/blackfin/mach-bf548/include/mach/blackfin.h1
-rw-r--r--arch/blackfin/mach-bf548/include/mach/mem_map.h51
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c1
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h89
-rw-r--r--arch/blackfin/mach-bf561/include/mach/blackfin.h1
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_map.h58
-rw-r--r--arch/blackfin/mach-common/arch_checks.c4
-rw-r--r--arch/blackfin/mach-common/cpufreq.c2
-rw-r--r--arch/blackfin/mach-common/entry.S1
-rw-r--r--arch/blackfin/mach-common/ints-priority.c47
-rw-r--r--arch/blackfin/mach-common/pm.c4
-rw-r--r--arch/blackfin/mm/init.c2
82 files changed, 1530 insertions, 1216 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 8ea0d942cdea..7faa2f554ab1 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -274,7 +274,7 @@ config BF_REV_0_0
274 274
275config BF_REV_0_1 275config BF_REV_0_1
276 bool "0.1" 276 bool "0.1"
277 depends on (BF52x || (BF54x && !BF54xM)) 277 depends on (BF51x || BF52x || (BF54x && !BF54xM))
278 278
279config BF_REV_0_2 279config BF_REV_0_2
280 bool "0.2" 280 bool "0.2"
@@ -358,7 +358,7 @@ config MEM_MT48LC8M32B2B5_7
358 358
359config MEM_MT48LC32M16A2TG_75 359config MEM_MT48LC32M16A2TG_75
360 bool 360 bool
361 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) 361 depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
362 default y 362 default y
363 363
364config MEM_MT48LC32M8A2_75 364config MEM_MT48LC32M8A2_75
@@ -366,6 +366,11 @@ config MEM_MT48LC32M8A2_75
366 depends on (BFIN518F_EZBRD) 366 depends on (BFIN518F_EZBRD)
367 default y 367 default y
368 368
369config MEM_MT48H32M16LFCJ_75
370 bool
371 depends on (BFIN526_EZBRD)
372 default y
373
369source "arch/blackfin/mach-bf518/Kconfig" 374source "arch/blackfin/mach-bf518/Kconfig"
370source "arch/blackfin/mach-bf527/Kconfig" 375source "arch/blackfin/mach-bf527/Kconfig"
371source "arch/blackfin/mach-bf533/Kconfig" 376source "arch/blackfin/mach-bf533/Kconfig"
@@ -623,7 +628,6 @@ choice
623config TICKSOURCE_GPTMR0 628config TICKSOURCE_GPTMR0
624 bool "Gptimer0 (SCLK domain)" 629 bool "Gptimer0 (SCLK domain)"
625 select BFIN_GPTIMERS 630 select BFIN_GPTIMERS
626 depends on !IPIPE
627 631
628config TICKSOURCE_CORETMR 632config TICKSOURCE_CORETMR
629 bool "Core timer (CCLK domain)" 633 bool "Core timer (CCLK domain)"
@@ -644,6 +648,7 @@ config CYCLES_CLOCKSOURCE
644 648
645config GPTMR0_CLOCKSOURCE 649config GPTMR0_CLOCKSOURCE
646 bool "Use GPTimer0 as a clocksource (higher rating)" 650 bool "Use GPTimer0 as a clocksource (higher rating)"
651 select BFIN_GPTIMERS
647 depends on GENERIC_CLOCKEVENTS 652 depends on GENERIC_CLOCKEVENTS
648 depends on !TICKSOURCE_GPTMR0 653 depends on !TICKSOURCE_GPTMR0
649 654
@@ -908,23 +913,41 @@ endchoice
908 913
909 914
910comment "Cache Support" 915comment "Cache Support"
916
911config BFIN_ICACHE 917config BFIN_ICACHE
912 bool "Enable ICACHE" 918 bool "Enable ICACHE"
919 default y
920config BFIN_ICACHE_LOCK
921 bool "Enable Instruction Cache Locking"
922 depends on BFIN_ICACHE
923 default n
924config BFIN_EXTMEM_ICACHEABLE
925 bool "Enable ICACHE for external memory"
926 depends on BFIN_ICACHE
927 default y
928config BFIN_L2_ICACHEABLE
929 bool "Enable ICACHE for L2 SRAM"
930 depends on BFIN_ICACHE
931 depends on BF54x || BF561
932 default n
933
913config BFIN_DCACHE 934config BFIN_DCACHE
914 bool "Enable DCACHE" 935 bool "Enable DCACHE"
936 default y
915config BFIN_DCACHE_BANKA 937config BFIN_DCACHE_BANKA
916 bool "Enable only 16k BankA DCACHE - BankB is SRAM" 938 bool "Enable only 16k BankA DCACHE - BankB is SRAM"
917 depends on BFIN_DCACHE && !BF531 939 depends on BFIN_DCACHE && !BF531
918 default n 940 default n
919config BFIN_ICACHE_LOCK 941config BFIN_EXTMEM_DCACHEABLE
920 bool "Enable Instruction Cache Locking" 942 bool "Enable DCACHE for external memory"
921
922choice
923 prompt "External memory cache policy"
924 depends on BFIN_DCACHE 943 depends on BFIN_DCACHE
925 default BFIN_WB if !SMP 944 default y
926 default BFIN_WT if SMP 945choice
927config BFIN_WB 946 prompt "External memory DCACHE policy"
947 depends on BFIN_EXTMEM_DCACHEABLE
948 default BFIN_EXTMEM_WRITEBACK if !SMP
949 default BFIN_EXTMEM_WRITETHROUGH if SMP
950config BFIN_EXTMEM_WRITEBACK
928 bool "Write back" 951 bool "Write back"
929 depends on !SMP 952 depends on !SMP
930 help 953 help
@@ -942,7 +965,7 @@ config BFIN_WB
942 If you are unsure of the options and you want to be safe, 965 If you are unsure of the options and you want to be safe,
943 then go with Write Through. 966 then go with Write Through.
944 967
945config BFIN_WT 968config BFIN_EXTMEM_WRITETHROUGH
946 bool "Write through" 969 bool "Write through"
947 help 970 help
948 Write Back Policy: 971 Write Back Policy:
@@ -961,23 +984,26 @@ config BFIN_WT
961 984
962endchoice 985endchoice
963 986
987config BFIN_L2_DCACHEABLE
988 bool "Enable DCACHE for L2 SRAM"
989 depends on BFIN_DCACHE
990 depends on BF54x || BF561
991 default n
964choice 992choice
965 prompt "L2 SRAM cache policy" 993 prompt "L2 SRAM DCACHE policy"
966 depends on (BF54x || BF561) 994 depends on BFIN_L2_DCACHEABLE
967 default BFIN_L2_WT 995 default BFIN_L2_WRITEBACK
968config BFIN_L2_WB 996config BFIN_L2_WRITEBACK
969 bool "Write back" 997 bool "Write back"
970 depends on !SMP 998 depends on !SMP
971 999
972config BFIN_L2_WT 1000config BFIN_L2_WRITETHROUGH
973 bool "Write through" 1001 bool "Write through"
974 depends on !SMP 1002 depends on !SMP
975
976config BFIN_L2_NOT_CACHED
977 bool "Not cached"
978
979endchoice 1003endchoice
980 1004
1005
1006comment "Memory Protection Unit"
981config MPU 1007config MPU
982 bool "Enable the memory protection unit (EXPERIMENTAL)" 1008 bool "Enable the memory protection unit (EXPERIMENTAL)"
983 default n 1009 default n
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index 3ab6f23561dd..fd9ccc5fea10 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -13,7 +13,7 @@ extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma
13 13
14quiet_cmd_uimage = UIMAGE $@ 14quiet_cmd_uimage = UIMAGE $@
15 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ 15 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
16 -C $(2) -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \ 16 -C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \
17 -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \ 17 -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
18 -d $< $@ 18 -d $< $@
19 19
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index baec1337f282..dcfb4889559a 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -326,11 +326,17 @@ CONFIG_DMA_UNCACHED_1M=y
326# Cache Support 326# Cache Support
327# 327#
328CONFIG_BFIN_ICACHE=y 328CONFIG_BFIN_ICACHE=y
329# CONFIG_BFIN_ICACHE_LOCK is not set
329CONFIG_BFIN_DCACHE=y 330CONFIG_BFIN_DCACHE=y
330# CONFIG_BFIN_DCACHE_BANKA is not set 331# CONFIG_BFIN_DCACHE_BANKA is not set
331# CONFIG_BFIN_ICACHE_LOCK is not set 332CONFIG_BFIN_EXTMEM_ICACHEABLE=y
332CONFIG_BFIN_WB=y 333CONFIG_BFIN_EXTMEM_DCACHEABLE=y
333# CONFIG_BFIN_WT is not set 334CONFIG_BFIN_EXTMEM_WRITEBACK=y
335# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
336
337#
338# Memory Protection Unit
339#
334# CONFIG_MPU is not set 340# CONFIG_MPU is not set
335 341
336# 342#
@@ -413,11 +419,11 @@ CONFIG_IP_PNP=y
413# CONFIG_INET_IPCOMP is not set 419# CONFIG_INET_IPCOMP is not set
414# CONFIG_INET_XFRM_TUNNEL is not set 420# CONFIG_INET_XFRM_TUNNEL is not set
415# CONFIG_INET_TUNNEL is not set 421# CONFIG_INET_TUNNEL is not set
416CONFIG_INET_XFRM_MODE_TRANSPORT=y 422# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
417CONFIG_INET_XFRM_MODE_TUNNEL=y 423# CONFIG_INET_XFRM_MODE_TUNNEL is not set
418CONFIG_INET_XFRM_MODE_BEET=y 424# CONFIG_INET_XFRM_MODE_BEET is not set
419# CONFIG_INET_LRO is not set 425# CONFIG_INET_LRO is not set
420CONFIG_INET_DIAG=y 426# CONFIG_INET_DIAG is not set
421CONFIG_INET_TCP_DIAG=y 427CONFIG_INET_TCP_DIAG=y
422# CONFIG_TCP_CONG_ADVANCED is not set 428# CONFIG_TCP_CONG_ADVANCED is not set
423CONFIG_TCP_CONG_CUBIC=y 429CONFIG_TCP_CONG_CUBIC=y
@@ -916,7 +922,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
916# CONFIG_MMC_SDHCI is not set 922# CONFIG_MMC_SDHCI is not set
917CONFIG_SDH_BFIN=m 923CONFIG_SDH_BFIN=m
918CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y 924CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
919CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ=y 925# CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ is not set
920# CONFIG_MMC_SPI is not set 926# CONFIG_MMC_SPI is not set
921# CONFIG_MEMSTICK is not set 927# CONFIG_MEMSTICK is not set
922# CONFIG_NEW_LEDS is not set 928# CONFIG_NEW_LEDS is not set
@@ -1147,7 +1153,7 @@ CONFIG_SCHED_DEBUG=y
1147# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1153# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1148# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1154# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1149# CONFIG_DEBUG_KOBJECT is not set 1155# CONFIG_DEBUG_KOBJECT is not set
1150# CONFIG_DEBUG_BUGVERBOSE is not set 1156CONFIG_DEBUG_BUGVERBOSE=y
1151CONFIG_DEBUG_INFO=y 1157CONFIG_DEBUG_INFO=y
1152# CONFIG_DEBUG_VM is not set 1158# CONFIG_DEBUG_VM is not set
1153# CONFIG_DEBUG_WRITECOUNT is not set 1159# CONFIG_DEBUG_WRITECOUNT is not set
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
index c06262e41f7c..48a3a7a9099c 100644
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@@ -331,16 +331,18 @@ CONFIG_DMA_UNCACHED_1M=y
331# Cache Support 331# Cache Support
332# 332#
333CONFIG_BFIN_ICACHE=y 333CONFIG_BFIN_ICACHE=y
334# CONFIG_BFIN_ICACHE_LOCK is not set
334CONFIG_BFIN_DCACHE=y 335CONFIG_BFIN_DCACHE=y
335# CONFIG_BFIN_DCACHE_BANKA is not set 336# CONFIG_BFIN_DCACHE_BANKA is not set
336# CONFIG_BFIN_ICACHE_LOCK is not set 337CONFIG_BFIN_EXTMEM_ICACHEABLE=y
337CONFIG_BFIN_WB=y 338CONFIG_BFIN_EXTMEM_DCACHEABLE=y
338# CONFIG_BFIN_WT is not set 339CONFIG_BFIN_EXTMEM_WRITEBACK=y
339# CONFIG_MPU is not set 340# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
340 341
341# 342#
342# Asynchonous Memory Configuration 343# Memory Protection Unit
343# 344#
345# CONFIG_MPU is not set
344 346
345# 347#
346# EBIU_AMGCTL Global Control 348# EBIU_AMGCTL Global Control
@@ -418,11 +420,11 @@ CONFIG_IP_PNP=y
418# CONFIG_INET_IPCOMP is not set 420# CONFIG_INET_IPCOMP is not set
419# CONFIG_INET_XFRM_TUNNEL is not set 421# CONFIG_INET_XFRM_TUNNEL is not set
420# CONFIG_INET_TUNNEL is not set 422# CONFIG_INET_TUNNEL is not set
421CONFIG_INET_XFRM_MODE_TRANSPORT=y 423# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
422CONFIG_INET_XFRM_MODE_TUNNEL=y 424# CONFIG_INET_XFRM_MODE_TUNNEL is not set
423CONFIG_INET_XFRM_MODE_BEET=y 425# CONFIG_INET_XFRM_MODE_BEET is not set
424# CONFIG_INET_LRO is not set 426# CONFIG_INET_LRO is not set
425CONFIG_INET_DIAG=y 427# CONFIG_INET_DIAG is not set
426CONFIG_INET_TCP_DIAG=y 428CONFIG_INET_TCP_DIAG=y
427# CONFIG_TCP_CONG_ADVANCED is not set 429# CONFIG_TCP_CONG_ADVANCED is not set
428CONFIG_TCP_CONG_CUBIC=y 430CONFIG_TCP_CONG_CUBIC=y
@@ -1424,7 +1426,7 @@ CONFIG_SCHED_DEBUG=y
1424# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1426# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1425# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1427# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1426# CONFIG_DEBUG_KOBJECT is not set 1428# CONFIG_DEBUG_KOBJECT is not set
1427# CONFIG_DEBUG_BUGVERBOSE is not set 1429CONFIG_DEBUG_BUGVERBOSE=y
1428CONFIG_DEBUG_INFO=y 1430CONFIG_DEBUG_INFO=y
1429# CONFIG_DEBUG_VM is not set 1431# CONFIG_DEBUG_VM is not set
1430# CONFIG_DEBUG_WRITECOUNT is not set 1432# CONFIG_DEBUG_WRITECOUNT is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index e9175c608aa7..dd8352791daf 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -331,11 +331,17 @@ CONFIG_DMA_UNCACHED_1M=y
331# Cache Support 331# Cache Support
332# 332#
333CONFIG_BFIN_ICACHE=y 333CONFIG_BFIN_ICACHE=y
334# CONFIG_BFIN_ICACHE_LOCK is not set
334CONFIG_BFIN_DCACHE=y 335CONFIG_BFIN_DCACHE=y
335# CONFIG_BFIN_DCACHE_BANKA is not set 336# CONFIG_BFIN_DCACHE_BANKA is not set
336# CONFIG_BFIN_ICACHE_LOCK is not set 337CONFIG_BFIN_EXTMEM_ICACHEABLE=y
337CONFIG_BFIN_WB=y 338CONFIG_BFIN_EXTMEM_DCACHEABLE=y
338# CONFIG_BFIN_WT is not set 339CONFIG_BFIN_EXTMEM_WRITEBACK=y
340# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
341
342#
343# Memory Protection Unit
344#
339# CONFIG_MPU is not set 345# CONFIG_MPU is not set
340 346
341# 347#
@@ -418,11 +424,11 @@ CONFIG_IP_PNP=y
418# CONFIG_INET_IPCOMP is not set 424# CONFIG_INET_IPCOMP is not set
419# CONFIG_INET_XFRM_TUNNEL is not set 425# CONFIG_INET_XFRM_TUNNEL is not set
420# CONFIG_INET_TUNNEL is not set 426# CONFIG_INET_TUNNEL is not set
421CONFIG_INET_XFRM_MODE_TRANSPORT=y 427# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
422CONFIG_INET_XFRM_MODE_TUNNEL=y 428# CONFIG_INET_XFRM_MODE_TUNNEL is not set
423CONFIG_INET_XFRM_MODE_BEET=y 429# CONFIG_INET_XFRM_MODE_BEET is not set
424# CONFIG_INET_LRO is not set 430# CONFIG_INET_LRO is not set
425CONFIG_INET_DIAG=y 431# CONFIG_INET_DIAG is not set
426CONFIG_INET_TCP_DIAG=y 432CONFIG_INET_TCP_DIAG=y
427# CONFIG_TCP_CONG_ADVANCED is not set 433# CONFIG_TCP_CONG_ADVANCED is not set
428CONFIG_TCP_CONG_CUBIC=y 434CONFIG_TCP_CONG_CUBIC=y
@@ -1505,7 +1511,7 @@ CONFIG_SCHED_DEBUG=y
1505# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1511# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1506# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1512# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1507# CONFIG_DEBUG_KOBJECT is not set 1513# CONFIG_DEBUG_KOBJECT is not set
1508# CONFIG_DEBUG_BUGVERBOSE is not set 1514CONFIG_DEBUG_BUGVERBOSE=y
1509CONFIG_DEBUG_INFO=y 1515CONFIG_DEBUG_INFO=y
1510# CONFIG_DEBUG_VM is not set 1516# CONFIG_DEBUG_VM is not set
1511# CONFIG_DEBUG_WRITECOUNT is not set 1517# CONFIG_DEBUG_WRITECOUNT is not set
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 5aa63bafdd62..4c044805cb5c 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -292,12 +292,21 @@ CONFIG_DMA_UNCACHED_1M=y
292# 292#
293# Cache Support 293# Cache Support
294# 294#
295#
296# Cache Support
297#
295CONFIG_BFIN_ICACHE=y 298CONFIG_BFIN_ICACHE=y
299# CONFIG_BFIN_ICACHE_LOCK is not set
296CONFIG_BFIN_DCACHE=y 300CONFIG_BFIN_DCACHE=y
297# CONFIG_BFIN_DCACHE_BANKA is not set 301# CONFIG_BFIN_DCACHE_BANKA is not set
298# CONFIG_BFIN_ICACHE_LOCK is not set 302CONFIG_BFIN_EXTMEM_ICACHEABLE=y
299CONFIG_BFIN_WB=y 303CONFIG_BFIN_EXTMEM_DCACHEABLE=y
300# CONFIG_BFIN_WT is not set 304CONFIG_BFIN_EXTMEM_WRITEBACK=y
305# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
306
307#
308# Memory Protection Unit
309#
301# CONFIG_MPU is not set 310# CONFIG_MPU is not set
302 311
303# 312#
@@ -391,11 +400,11 @@ CONFIG_IP_PNP=y
391# CONFIG_INET_IPCOMP is not set 400# CONFIG_INET_IPCOMP is not set
392# CONFIG_INET_XFRM_TUNNEL is not set 401# CONFIG_INET_XFRM_TUNNEL is not set
393# CONFIG_INET_TUNNEL is not set 402# CONFIG_INET_TUNNEL is not set
394CONFIG_INET_XFRM_MODE_TRANSPORT=y 403# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
395CONFIG_INET_XFRM_MODE_TUNNEL=y 404# CONFIG_INET_XFRM_MODE_TUNNEL is not set
396CONFIG_INET_XFRM_MODE_BEET=y 405# CONFIG_INET_XFRM_MODE_BEET is not set
397# CONFIG_INET_LRO is not set 406# CONFIG_INET_LRO is not set
398CONFIG_INET_DIAG=y 407# CONFIG_INET_DIAG is not set
399CONFIG_INET_TCP_DIAG=y 408CONFIG_INET_TCP_DIAG=y
400# CONFIG_TCP_CONG_ADVANCED is not set 409# CONFIG_TCP_CONG_ADVANCED is not set
401CONFIG_TCP_CONG_CUBIC=y 410CONFIG_TCP_CONG_CUBIC=y
@@ -1052,7 +1061,7 @@ CONFIG_SCHED_DEBUG=y
1052# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1061# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1053# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1062# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1054# CONFIG_DEBUG_KOBJECT is not set 1063# CONFIG_DEBUG_KOBJECT is not set
1055# CONFIG_DEBUG_BUGVERBOSE is not set 1064CONFIG_DEBUG_BUGVERBOSE=y
1056CONFIG_DEBUG_INFO=y 1065CONFIG_DEBUG_INFO=y
1057# CONFIG_DEBUG_VM is not set 1066# CONFIG_DEBUG_VM is not set
1058# CONFIG_DEBUG_WRITECOUNT is not set 1067# CONFIG_DEBUG_WRITECOUNT is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index fed25329e13c..c99bbcd09a68 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -293,11 +293,17 @@ CONFIG_DMA_UNCACHED_1M=y
293# Cache Support 293# Cache Support
294# 294#
295CONFIG_BFIN_ICACHE=y 295CONFIG_BFIN_ICACHE=y
296# CONFIG_BFIN_ICACHE_LOCK is not set
296CONFIG_BFIN_DCACHE=y 297CONFIG_BFIN_DCACHE=y
297# CONFIG_BFIN_DCACHE_BANKA is not set 298# CONFIG_BFIN_DCACHE_BANKA is not set
298# CONFIG_BFIN_ICACHE_LOCK is not set 299CONFIG_BFIN_EXTMEM_ICACHEABLE=y
299CONFIG_BFIN_WB=y 300CONFIG_BFIN_EXTMEM_DCACHEABLE=y
300# CONFIG_BFIN_WT is not set 301CONFIG_BFIN_EXTMEM_WRITEBACK=y
302# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
303
304#
305# Memory Protection Unit
306#
301# CONFIG_MPU is not set 307# CONFIG_MPU is not set
302 308
303# 309#
@@ -391,11 +397,11 @@ CONFIG_IP_PNP=y
391# CONFIG_INET_IPCOMP is not set 397# CONFIG_INET_IPCOMP is not set
392# CONFIG_INET_XFRM_TUNNEL is not set 398# CONFIG_INET_XFRM_TUNNEL is not set
393# CONFIG_INET_TUNNEL is not set 399# CONFIG_INET_TUNNEL is not set
394CONFIG_INET_XFRM_MODE_TRANSPORT=y 400# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
395CONFIG_INET_XFRM_MODE_TUNNEL=y 401# CONFIG_INET_XFRM_MODE_TUNNEL is not set
396CONFIG_INET_XFRM_MODE_BEET=y 402# CONFIG_INET_XFRM_MODE_BEET is not set
397# CONFIG_INET_LRO is not set 403# CONFIG_INET_LRO is not set
398CONFIG_INET_DIAG=y 404# CONFIG_INET_DIAG is not set
399CONFIG_INET_TCP_DIAG=y 405CONFIG_INET_TCP_DIAG=y
400# CONFIG_TCP_CONG_ADVANCED is not set 406# CONFIG_TCP_CONG_ADVANCED is not set
401CONFIG_TCP_CONG_CUBIC=y 407CONFIG_TCP_CONG_CUBIC=y
@@ -1216,7 +1222,7 @@ CONFIG_SCHED_DEBUG=y
1216# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1222# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1217# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1223# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1218# CONFIG_DEBUG_KOBJECT is not set 1224# CONFIG_DEBUG_KOBJECT is not set
1219# CONFIG_DEBUG_BUGVERBOSE is not set 1225CONFIG_DEBUG_BUGVERBOSE=y
1220CONFIG_DEBUG_INFO=y 1226CONFIG_DEBUG_INFO=y
1221# CONFIG_DEBUG_VM is not set 1227# CONFIG_DEBUG_VM is not set
1222# CONFIG_DEBUG_WRITECOUNT is not set 1228# CONFIG_DEBUG_WRITECOUNT is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index f9ac20d55799..092ffda80e68 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -300,11 +300,17 @@ CONFIG_DMA_UNCACHED_1M=y
300# Cache Support 300# Cache Support
301# 301#
302CONFIG_BFIN_ICACHE=y 302CONFIG_BFIN_ICACHE=y
303# CONFIG_BFIN_ICACHE_LOCK is not set
303CONFIG_BFIN_DCACHE=y 304CONFIG_BFIN_DCACHE=y
304# CONFIG_BFIN_DCACHE_BANKA is not set 305# CONFIG_BFIN_DCACHE_BANKA is not set
305# CONFIG_BFIN_ICACHE_LOCK is not set 306CONFIG_BFIN_EXTMEM_ICACHEABLE=y
306CONFIG_BFIN_WB=y 307CONFIG_BFIN_EXTMEM_DCACHEABLE=y
307# CONFIG_BFIN_WT is not set 308CONFIG_BFIN_EXTMEM_WRITEBACK=y
309# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
310
311#
312# Memory Protection Unit
313#
308# CONFIG_MPU is not set 314# CONFIG_MPU is not set
309 315
310# 316#
@@ -399,11 +405,11 @@ CONFIG_IP_PNP=y
399# CONFIG_INET_IPCOMP is not set 405# CONFIG_INET_IPCOMP is not set
400# CONFIG_INET_XFRM_TUNNEL is not set 406# CONFIG_INET_XFRM_TUNNEL is not set
401# CONFIG_INET_TUNNEL is not set 407# CONFIG_INET_TUNNEL is not set
402CONFIG_INET_XFRM_MODE_TRANSPORT=y 408# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
403CONFIG_INET_XFRM_MODE_TUNNEL=y 409# CONFIG_INET_XFRM_MODE_TUNNEL is not set
404CONFIG_INET_XFRM_MODE_BEET=y 410# CONFIG_INET_XFRM_MODE_BEET is not set
405# CONFIG_INET_LRO is not set 411# CONFIG_INET_LRO is not set
406CONFIG_INET_DIAG=y 412# CONFIG_INET_DIAG is not set
407CONFIG_INET_TCP_DIAG=y 413CONFIG_INET_TCP_DIAG=y
408# CONFIG_TCP_CONG_ADVANCED is not set 414# CONFIG_TCP_CONG_ADVANCED is not set
409CONFIG_TCP_CONG_CUBIC=y 415CONFIG_TCP_CONG_CUBIC=y
@@ -1269,7 +1275,7 @@ CONFIG_SCHED_DEBUG=y
1269# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1275# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1270# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1276# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1271# CONFIG_DEBUG_KOBJECT is not set 1277# CONFIG_DEBUG_KOBJECT is not set
1272# CONFIG_DEBUG_BUGVERBOSE is not set 1278CONFIG_DEBUG_BUGVERBOSE=y
1273CONFIG_DEBUG_INFO=y 1279CONFIG_DEBUG_INFO=y
1274# CONFIG_DEBUG_VM is not set 1280# CONFIG_DEBUG_VM is not set
1275# CONFIG_DEBUG_WRITECOUNT is not set 1281# CONFIG_DEBUG_WRITECOUNT is not set
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index ee98e227b887..fa698a89f6fe 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -311,11 +311,17 @@ CONFIG_DMA_UNCACHED_1M=y
311# Cache Support 311# Cache Support
312# 312#
313CONFIG_BFIN_ICACHE=y 313CONFIG_BFIN_ICACHE=y
314# CONFIG_BFIN_ICACHE_LOCK is not set
314CONFIG_BFIN_DCACHE=y 315CONFIG_BFIN_DCACHE=y
315# CONFIG_BFIN_DCACHE_BANKA is not set 316# CONFIG_BFIN_DCACHE_BANKA is not set
316# CONFIG_BFIN_ICACHE_LOCK is not set 317CONFIG_BFIN_EXTMEM_ICACHEABLE=y
317CONFIG_BFIN_WB=y 318CONFIG_BFIN_EXTMEM_DCACHEABLE=y
318# CONFIG_BFIN_WT is not set 319CONFIG_BFIN_EXTMEM_WRITEBACK=y
320# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
321
322#
323# Memory Protection Unit
324#
319# CONFIG_MPU is not set 325# CONFIG_MPU is not set
320 326
321# 327#
@@ -398,11 +404,11 @@ CONFIG_IP_PNP=y
398# CONFIG_INET_IPCOMP is not set 404# CONFIG_INET_IPCOMP is not set
399# CONFIG_INET_XFRM_TUNNEL is not set 405# CONFIG_INET_XFRM_TUNNEL is not set
400# CONFIG_INET_TUNNEL is not set 406# CONFIG_INET_TUNNEL is not set
401CONFIG_INET_XFRM_MODE_TRANSPORT=y 407# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
402CONFIG_INET_XFRM_MODE_TUNNEL=y 408# CONFIG_INET_XFRM_MODE_TUNNEL is not set
403CONFIG_INET_XFRM_MODE_BEET=y 409# CONFIG_INET_XFRM_MODE_BEET is not set
404# CONFIG_INET_LRO is not set 410# CONFIG_INET_LRO is not set
405CONFIG_INET_DIAG=y 411# CONFIG_INET_DIAG is not set
406CONFIG_INET_TCP_DIAG=y 412CONFIG_INET_TCP_DIAG=y
407# CONFIG_TCP_CONG_ADVANCED is not set 413# CONFIG_TCP_CONG_ADVANCED is not set
408CONFIG_TCP_CONG_CUBIC=y 414CONFIG_TCP_CONG_CUBIC=y
@@ -1203,7 +1209,7 @@ CONFIG_SCHED_DEBUG=y
1203# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1209# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1204# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1210# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1205# CONFIG_DEBUG_KOBJECT is not set 1211# CONFIG_DEBUG_KOBJECT is not set
1206# CONFIG_DEBUG_BUGVERBOSE is not set 1212CONFIG_DEBUG_BUGVERBOSE=y
1207CONFIG_DEBUG_INFO=y 1213CONFIG_DEBUG_INFO=y
1208# CONFIG_DEBUG_VM is not set 1214# CONFIG_DEBUG_VM is not set
1209# CONFIG_DEBUG_WRITECOUNT is not set 1215# CONFIG_DEBUG_WRITECOUNT is not set
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index deeabef8ab80..b3d3cab81cfe 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -366,14 +366,19 @@ CONFIG_DMA_UNCACHED_2M=y
366# Cache Support 366# Cache Support
367# 367#
368CONFIG_BFIN_ICACHE=y 368CONFIG_BFIN_ICACHE=y
369# CONFIG_BFIN_ICACHE_LOCK is not set
369CONFIG_BFIN_DCACHE=y 370CONFIG_BFIN_DCACHE=y
370# CONFIG_BFIN_DCACHE_BANKA is not set 371# CONFIG_BFIN_DCACHE_BANKA is not set
371# CONFIG_BFIN_ICACHE_LOCK is not set 372CONFIG_BFIN_EXTMEM_ICACHEABLE=y
372CONFIG_BFIN_WB=y 373CONFIG_BFIN_EXTMEM_DCACHEABLE=y
373# CONFIG_BFIN_WT is not set 374CONFIG_BFIN_EXTMEM_WRITEBACK=y
374# CONFIG_BFIN_L2_WB is not set 375# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
375CONFIG_BFIN_L2_WT=y 376# CONFIG_BFIN_L2_ICACHEABLE is not set
376# CONFIG_BFIN_L2_NOT_CACHED is not set 377# CONFIG_BFIN_L2_DCACHEABLE is not set
378
379#
380# Memory Protection Unit
381#
377# CONFIG_MPU is not set 382# CONFIG_MPU is not set
378 383
379# 384#
@@ -459,11 +464,11 @@ CONFIG_IP_PNP=y
459# CONFIG_INET_IPCOMP is not set 464# CONFIG_INET_IPCOMP is not set
460# CONFIG_INET_XFRM_TUNNEL is not set 465# CONFIG_INET_XFRM_TUNNEL is not set
461# CONFIG_INET_TUNNEL is not set 466# CONFIG_INET_TUNNEL is not set
462CONFIG_INET_XFRM_MODE_TRANSPORT=y 467# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
463CONFIG_INET_XFRM_MODE_TUNNEL=y 468# CONFIG_INET_XFRM_MODE_TUNNEL is not set
464CONFIG_INET_XFRM_MODE_BEET=y 469# CONFIG_INET_XFRM_MODE_BEET is not set
465# CONFIG_INET_LRO is not set 470# CONFIG_INET_LRO is not set
466CONFIG_INET_DIAG=y 471# CONFIG_INET_DIAG is not set
467CONFIG_INET_TCP_DIAG=y 472CONFIG_INET_TCP_DIAG=y
468# CONFIG_TCP_CONG_ADVANCED is not set 473# CONFIG_TCP_CONG_ADVANCED is not set
469CONFIG_TCP_CONG_CUBIC=y 474CONFIG_TCP_CONG_CUBIC=y
@@ -1606,7 +1611,7 @@ CONFIG_SCHED_DEBUG=y
1606# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1611# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1607# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1612# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1608# CONFIG_DEBUG_KOBJECT is not set 1613# CONFIG_DEBUG_KOBJECT is not set
1609# CONFIG_DEBUG_BUGVERBOSE is not set 1614CONFIG_DEBUG_BUGVERBOSE=y
1610CONFIG_DEBUG_INFO=y 1615CONFIG_DEBUG_INFO=y
1611# CONFIG_DEBUG_VM is not set 1616# CONFIG_DEBUG_VM is not set
1612# CONFIG_DEBUG_WRITECOUNT is not set 1617# CONFIG_DEBUG_WRITECOUNT is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index dcfbe2e2931e..0313cd1d9824 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -331,14 +331,19 @@ CONFIG_DMA_UNCACHED_1M=y
331# Cache Support 331# Cache Support
332# 332#
333CONFIG_BFIN_ICACHE=y 333CONFIG_BFIN_ICACHE=y
334# CONFIG_BFIN_ICACHE_LOCK is not set
334CONFIG_BFIN_DCACHE=y 335CONFIG_BFIN_DCACHE=y
335# CONFIG_BFIN_DCACHE_BANKA is not set 336# CONFIG_BFIN_DCACHE_BANKA is not set
336# CONFIG_BFIN_ICACHE_LOCK is not set 337CONFIG_BFIN_EXTMEM_ICACHEABLE=y
337CONFIG_BFIN_WB=y 338CONFIG_BFIN_EXTMEM_DCACHEABLE=y
338# CONFIG_BFIN_WT is not set 339CONFIG_BFIN_EXTMEM_WRITEBACK=y
339# CONFIG_BFIN_L2_WB is not set 340# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
340CONFIG_BFIN_L2_WT=y 341# CONFIG_BFIN_L2_ICACHEABLE is not set
341# CONFIG_BFIN_L2_NOT_CACHED is not set 342# CONFIG_BFIN_L2_DCACHEABLE is not set
343
344#
345# Memory Protection Unit
346#
342# CONFIG_MPU is not set 347# CONFIG_MPU is not set
343 348
344# 349#
@@ -425,11 +430,11 @@ CONFIG_IP_PNP=y
425# CONFIG_INET_IPCOMP is not set 430# CONFIG_INET_IPCOMP is not set
426# CONFIG_INET_XFRM_TUNNEL is not set 431# CONFIG_INET_XFRM_TUNNEL is not set
427# CONFIG_INET_TUNNEL is not set 432# CONFIG_INET_TUNNEL is not set
428CONFIG_INET_XFRM_MODE_TRANSPORT=y 433# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
429CONFIG_INET_XFRM_MODE_TUNNEL=y 434# CONFIG_INET_XFRM_MODE_TUNNEL is not set
430CONFIG_INET_XFRM_MODE_BEET=y 435# CONFIG_INET_XFRM_MODE_BEET is not set
431# CONFIG_INET_LRO is not set 436# CONFIG_INET_LRO is not set
432CONFIG_INET_DIAG=y 437# CONFIG_INET_DIAG is not set
433CONFIG_INET_TCP_DIAG=y 438CONFIG_INET_TCP_DIAG=y
434# CONFIG_TCP_CONG_ADVANCED is not set 439# CONFIG_TCP_CONG_ADVANCED is not set
435CONFIG_TCP_CONG_CUBIC=y 440CONFIG_TCP_CONG_CUBIC=y
@@ -1044,7 +1049,7 @@ CONFIG_SCHED_DEBUG=y
1044# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1049# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1045# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1050# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1046# CONFIG_DEBUG_KOBJECT is not set 1051# CONFIG_DEBUG_KOBJECT is not set
1047# CONFIG_DEBUG_BUGVERBOSE is not set 1052CONFIG_DEBUG_BUGVERBOSE=y
1048CONFIG_DEBUG_INFO=y 1053CONFIG_DEBUG_INFO=y
1049# CONFIG_DEBUG_VM is not set 1054# CONFIG_DEBUG_VM is not set
1050# CONFIG_DEBUG_WRITECOUNT is not set 1055# CONFIG_DEBUG_WRITECOUNT is not set
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
index 174c578b8ec4..5d944ffd4ab0 100644
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ b/arch/blackfin/configs/BlackStamp_defconfig
@@ -285,11 +285,17 @@ CONFIG_DMA_UNCACHED_1M=y
285# Cache Support 285# Cache Support
286# 286#
287CONFIG_BFIN_ICACHE=y 287CONFIG_BFIN_ICACHE=y
288# CONFIG_BFIN_ICACHE_LOCK is not set
288CONFIG_BFIN_DCACHE=y 289CONFIG_BFIN_DCACHE=y
289# CONFIG_BFIN_DCACHE_BANKA is not set 290# CONFIG_BFIN_DCACHE_BANKA is not set
290# CONFIG_BFIN_ICACHE_LOCK is not set 291CONFIG_BFIN_EXTMEM_ICACHEABLE=y
291CONFIG_BFIN_WB=y 292CONFIG_BFIN_EXTMEM_DCACHEABLE=y
292# CONFIG_BFIN_WT is not set 293CONFIG_BFIN_EXTMEM_WRITEBACK=y
294# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
295
296#
297# Memory Protection Unit
298#
293# CONFIG_MPU is not set 299# CONFIG_MPU is not set
294 300
295# 301#
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index e17875e8abe8..648a31d01bf4 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -329,11 +329,17 @@ CONFIG_DMA_UNCACHED_1M=y
329# Cache Support 329# Cache Support
330# 330#
331CONFIG_BFIN_ICACHE=y 331CONFIG_BFIN_ICACHE=y
332# CONFIG_BFIN_ICACHE_LOCK is not set
332CONFIG_BFIN_DCACHE=y 333CONFIG_BFIN_DCACHE=y
333# CONFIG_BFIN_DCACHE_BANKA is not set 334# CONFIG_BFIN_DCACHE_BANKA is not set
334# CONFIG_BFIN_ICACHE_LOCK is not set 335CONFIG_BFIN_EXTMEM_ICACHEABLE=y
335CONFIG_BFIN_WB=y 336CONFIG_BFIN_EXTMEM_DCACHEABLE=y
336# CONFIG_BFIN_WT is not set 337CONFIG_BFIN_EXTMEM_WRITEBACK=y
338# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
339
340#
341# Memory Protection Unit
342#
337# CONFIG_MPU is not set 343# CONFIG_MPU is not set
338 344
339# 345#
@@ -417,11 +423,11 @@ CONFIG_IP_PNP=y
417# CONFIG_INET_IPCOMP is not set 423# CONFIG_INET_IPCOMP is not set
418# CONFIG_INET_XFRM_TUNNEL is not set 424# CONFIG_INET_XFRM_TUNNEL is not set
419# CONFIG_INET_TUNNEL is not set 425# CONFIG_INET_TUNNEL is not set
420CONFIG_INET_XFRM_MODE_TRANSPORT=y 426# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
421CONFIG_INET_XFRM_MODE_TUNNEL=y 427# CONFIG_INET_XFRM_MODE_TUNNEL is not set
422CONFIG_INET_XFRM_MODE_BEET=y 428# CONFIG_INET_XFRM_MODE_BEET is not set
423# CONFIG_INET_LRO is not set 429# CONFIG_INET_LRO is not set
424CONFIG_INET_DIAG=y 430# CONFIG_INET_DIAG is not set
425CONFIG_INET_TCP_DIAG=y 431CONFIG_INET_TCP_DIAG=y
426# CONFIG_TCP_CONG_ADVANCED is not set 432# CONFIG_TCP_CONG_ADVANCED is not set
427CONFIG_TCP_CONG_CUBIC=y 433CONFIG_TCP_CONG_CUBIC=y
@@ -1246,7 +1252,7 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1246# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1252# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1247# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1253# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1248# CONFIG_DEBUG_KOBJECT is not set 1254# CONFIG_DEBUG_KOBJECT is not set
1249# CONFIG_DEBUG_BUGVERBOSE is not set 1255CONFIG_DEBUG_BUGVERBOSE=y
1250# CONFIG_DEBUG_INFO is not set 1256# CONFIG_DEBUG_INFO is not set
1251# CONFIG_DEBUG_VM is not set 1257# CONFIG_DEBUG_VM is not set
1252# CONFIG_DEBUG_WRITECOUNT is not set 1258# CONFIG_DEBUG_WRITECOUNT is not set
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig
index fafd95e84b28..ae665b93b875 100644
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ b/arch/blackfin/configs/CM-BF533_defconfig
@@ -262,12 +262,17 @@ CONFIG_DMA_UNCACHED_1M=y
262# Cache Support 262# Cache Support
263# 263#
264CONFIG_BFIN_ICACHE=y 264CONFIG_BFIN_ICACHE=y
265# CONFIG_BFIN_ICACHE_LOCK is not set
265CONFIG_BFIN_DCACHE=y 266CONFIG_BFIN_DCACHE=y
266# CONFIG_BFIN_DCACHE_BANKA is not set 267# CONFIG_BFIN_DCACHE_BANKA is not set
267# CONFIG_BFIN_ICACHE_LOCK is not set 268CONFIG_BFIN_EXTMEM_ICACHEABLE=y
268CONFIG_BFIN_WB=y 269CONFIG_BFIN_EXTMEM_DCACHEABLE=y
269# CONFIG_BFIN_WT is not set 270CONFIG_BFIN_EXTMEM_WRITEBACK=y
270CONFIG_L1_MAX_PIECE=16 271# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
272
273#
274# Memory Protection Unit
275#
271# CONFIG_MPU is not set 276# CONFIG_MPU is not set
272 277
273# 278#
@@ -353,10 +358,10 @@ CONFIG_IP_FIB_HASH=y
353# CONFIG_INET_IPCOMP is not set 358# CONFIG_INET_IPCOMP is not set
354# CONFIG_INET_XFRM_TUNNEL is not set 359# CONFIG_INET_XFRM_TUNNEL is not set
355# CONFIG_INET_TUNNEL is not set 360# CONFIG_INET_TUNNEL is not set
356CONFIG_INET_XFRM_MODE_TRANSPORT=y 361# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
357CONFIG_INET_XFRM_MODE_TUNNEL=y 362# CONFIG_INET_XFRM_MODE_TUNNEL is not set
358CONFIG_INET_XFRM_MODE_BEET=y 363# CONFIG_INET_XFRM_MODE_BEET is not set
359CONFIG_INET_DIAG=y 364# CONFIG_INET_DIAG is not set
360CONFIG_INET_TCP_DIAG=y 365CONFIG_INET_TCP_DIAG=y
361# CONFIG_TCP_CONG_ADVANCED is not set 366# CONFIG_TCP_CONG_ADVANCED is not set
362CONFIG_TCP_CONG_CUBIC=y 367CONFIG_TCP_CONG_CUBIC=y
@@ -873,7 +878,7 @@ CONFIG_ENABLE_MUST_CHECK=y
873CONFIG_DEBUG_FS=y 878CONFIG_DEBUG_FS=y
874# CONFIG_HEADERS_CHECK is not set 879# CONFIG_HEADERS_CHECK is not set
875# CONFIG_DEBUG_KERNEL is not set 880# CONFIG_DEBUG_KERNEL is not set
876# CONFIG_DEBUG_BUGVERBOSE is not set 881CONFIG_DEBUG_BUGVERBOSE=y
877CONFIG_DEBUG_MMRS=y 882CONFIG_DEBUG_MMRS=y
878CONFIG_DEBUG_HUNT_FOR_ZERO=y 883CONFIG_DEBUG_HUNT_FOR_ZERO=y
879CONFIG_DEBUG_BFIN_HWTRACE_ON=y 884CONFIG_DEBUG_BFIN_HWTRACE_ON=y
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig
index e73aa5af58b9..d74b6f4db35d 100644
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ b/arch/blackfin/configs/CM-BF537E_defconfig
@@ -297,11 +297,17 @@ CONFIG_DMA_UNCACHED_1M=y
297# Cache Support 297# Cache Support
298# 298#
299CONFIG_BFIN_ICACHE=y 299CONFIG_BFIN_ICACHE=y
300# CONFIG_BFIN_ICACHE_LOCK is not set
300CONFIG_BFIN_DCACHE=y 301CONFIG_BFIN_DCACHE=y
301# CONFIG_BFIN_DCACHE_BANKA is not set 302# CONFIG_BFIN_DCACHE_BANKA is not set
302# CONFIG_BFIN_ICACHE_LOCK is not set 303CONFIG_BFIN_EXTMEM_ICACHEABLE=y
303CONFIG_BFIN_WB=y 304CONFIG_BFIN_EXTMEM_DCACHEABLE=y
304# CONFIG_BFIN_WT is not set 305CONFIG_BFIN_EXTMEM_WRITEBACK=y
306# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
307
308#
309# Memory Protection Unit
310#
305# CONFIG_MPU is not set 311# CONFIG_MPU is not set
306 312
307# 313#
@@ -383,11 +389,11 @@ CONFIG_IP_PNP=y
383# CONFIG_INET_IPCOMP is not set 389# CONFIG_INET_IPCOMP is not set
384# CONFIG_INET_XFRM_TUNNEL is not set 390# CONFIG_INET_XFRM_TUNNEL is not set
385# CONFIG_INET_TUNNEL is not set 391# CONFIG_INET_TUNNEL is not set
386CONFIG_INET_XFRM_MODE_TRANSPORT=y 392# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
387CONFIG_INET_XFRM_MODE_TUNNEL=y 393# CONFIG_INET_XFRM_MODE_TUNNEL is not set
388CONFIG_INET_XFRM_MODE_BEET=y 394# CONFIG_INET_XFRM_MODE_BEET is not set
389# CONFIG_INET_LRO is not set 395# CONFIG_INET_LRO is not set
390CONFIG_INET_DIAG=y 396# CONFIG_INET_DIAG is not set
391CONFIG_INET_TCP_DIAG=y 397CONFIG_INET_TCP_DIAG=y
392# CONFIG_TCP_CONG_ADVANCED is not set 398# CONFIG_TCP_CONG_ADVANCED is not set
393CONFIG_TCP_CONG_CUBIC=y 399CONFIG_TCP_CONG_CUBIC=y
@@ -861,7 +867,7 @@ CONFIG_DEBUG_FS=y
861# CONFIG_HEADERS_CHECK is not set 867# CONFIG_HEADERS_CHECK is not set
862CONFIG_DEBUG_SECTION_MISMATCH=y 868CONFIG_DEBUG_SECTION_MISMATCH=y
863# CONFIG_DEBUG_KERNEL is not set 869# CONFIG_DEBUG_KERNEL is not set
864# CONFIG_DEBUG_BUGVERBOSE is not set 870CONFIG_DEBUG_BUGVERBOSE=y
865# CONFIG_DEBUG_MEMORY_INIT is not set 871# CONFIG_DEBUG_MEMORY_INIT is not set
866# CONFIG_RCU_CPU_STALL_DETECTOR is not set 872# CONFIG_RCU_CPU_STALL_DETECTOR is not set
867 873
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig
index 80211303f6b9..7fc8dfa1719f 100644
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ b/arch/blackfin/configs/CM-BF537U_defconfig
@@ -270,12 +270,17 @@ CONFIG_DMA_UNCACHED_1M=y
270# Cache Support 270# Cache Support
271# 271#
272CONFIG_BFIN_ICACHE=y 272CONFIG_BFIN_ICACHE=y
273# CONFIG_BFIN_ICACHE_LOCK is not set
273CONFIG_BFIN_DCACHE=y 274CONFIG_BFIN_DCACHE=y
274# CONFIG_BFIN_DCACHE_BANKA is not set 275# CONFIG_BFIN_DCACHE_BANKA is not set
275# CONFIG_BFIN_ICACHE_LOCK is not set 276CONFIG_BFIN_EXTMEM_ICACHEABLE=y
276CONFIG_BFIN_WB=y 277CONFIG_BFIN_EXTMEM_DCACHEABLE=y
277# CONFIG_BFIN_WT is not set 278CONFIG_BFIN_EXTMEM_WRITEBACK=y
278CONFIG_L1_MAX_PIECE=16 279# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
280
281#
282# Memory Protection Unit
283#
279# CONFIG_MPU is not set 284# CONFIG_MPU is not set
280 285
281# 286#
@@ -361,10 +366,10 @@ CONFIG_IP_FIB_HASH=y
361# CONFIG_INET_IPCOMP is not set 366# CONFIG_INET_IPCOMP is not set
362# CONFIG_INET_XFRM_TUNNEL is not set 367# CONFIG_INET_XFRM_TUNNEL is not set
363# CONFIG_INET_TUNNEL is not set 368# CONFIG_INET_TUNNEL is not set
364CONFIG_INET_XFRM_MODE_TRANSPORT=y 369# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
365CONFIG_INET_XFRM_MODE_TUNNEL=y 370# CONFIG_INET_XFRM_MODE_TUNNEL is not set
366CONFIG_INET_XFRM_MODE_BEET=y 371# CONFIG_INET_XFRM_MODE_BEET is not set
367CONFIG_INET_DIAG=y 372# CONFIG_INET_DIAG is not set
368CONFIG_INET_TCP_DIAG=y 373CONFIG_INET_TCP_DIAG=y
369# CONFIG_TCP_CONG_ADVANCED is not set 374# CONFIG_TCP_CONG_ADVANCED is not set
370CONFIG_TCP_CONG_CUBIC=y 375CONFIG_TCP_CONG_CUBIC=y
@@ -901,7 +906,7 @@ CONFIG_ENABLE_MUST_CHECK=y
901CONFIG_DEBUG_FS=y 906CONFIG_DEBUG_FS=y
902# CONFIG_HEADERS_CHECK is not set 907# CONFIG_HEADERS_CHECK is not set
903# CONFIG_DEBUG_KERNEL is not set 908# CONFIG_DEBUG_KERNEL is not set
904# CONFIG_DEBUG_BUGVERBOSE is not set 909CONFIG_DEBUG_BUGVERBOSE=y
905CONFIG_DEBUG_MMRS=y 910CONFIG_DEBUG_MMRS=y
906CONFIG_DEBUG_HUNT_FOR_ZERO=y 911CONFIG_DEBUG_HUNT_FOR_ZERO=y
907CONFIG_DEBUG_BFIN_HWTRACE_ON=y 912CONFIG_DEBUG_BFIN_HWTRACE_ON=y
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index dd815f0d1517..acca4e51a45a 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -333,12 +333,19 @@ CONFIG_DMA_UNCACHED_1M=y
333# Cache Support 333# Cache Support
334# 334#
335CONFIG_BFIN_ICACHE=y 335CONFIG_BFIN_ICACHE=y
336# CONFIG_BFIN_ICACHE_LOCK is not set
336CONFIG_BFIN_DCACHE=y 337CONFIG_BFIN_DCACHE=y
337# CONFIG_BFIN_DCACHE_BANKA is not set 338# CONFIG_BFIN_DCACHE_BANKA is not set
338# CONFIG_BFIN_ICACHE_LOCK is not set 339CONFIG_BFIN_EXTMEM_ICACHEABLE=y
339CONFIG_BFIN_WB=y 340CONFIG_BFIN_EXTMEM_DCACHEABLE=y
340# CONFIG_BFIN_WT is not set 341CONFIG_BFIN_EXTMEM_WRITEBACK=y
341CONFIG_L1_MAX_PIECE=16 342# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
343# CONFIG_BFIN_L2_ICACHEABLE is not set
344# CONFIG_BFIN_L2_DCACHEABLE is not set
345
346#
347# Memory Protection Unit
348#
342# CONFIG_MPU is not set 349# CONFIG_MPU is not set
343 350
344# 351#
@@ -428,11 +435,11 @@ CONFIG_IP_PNP=y
428# CONFIG_INET_IPCOMP is not set 435# CONFIG_INET_IPCOMP is not set
429# CONFIG_INET_XFRM_TUNNEL is not set 436# CONFIG_INET_XFRM_TUNNEL is not set
430# CONFIG_INET_TUNNEL is not set 437# CONFIG_INET_TUNNEL is not set
431CONFIG_INET_XFRM_MODE_TRANSPORT=y 438# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
432CONFIG_INET_XFRM_MODE_TUNNEL=y 439# CONFIG_INET_XFRM_MODE_TUNNEL is not set
433CONFIG_INET_XFRM_MODE_BEET=y 440# CONFIG_INET_XFRM_MODE_BEET is not set
434# CONFIG_INET_LRO is not set 441# CONFIG_INET_LRO is not set
435CONFIG_INET_DIAG=y 442# CONFIG_INET_DIAG is not set
436CONFIG_INET_TCP_DIAG=y 443CONFIG_INET_TCP_DIAG=y
437# CONFIG_TCP_CONG_ADVANCED is not set 444# CONFIG_TCP_CONG_ADVANCED is not set
438CONFIG_TCP_CONG_CUBIC=y 445CONFIG_TCP_CONG_CUBIC=y
@@ -1334,7 +1341,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1334CONFIG_DEBUG_FS=y 1341CONFIG_DEBUG_FS=y
1335# CONFIG_HEADERS_CHECK is not set 1342# CONFIG_HEADERS_CHECK is not set
1336# CONFIG_DEBUG_KERNEL is not set 1343# CONFIG_DEBUG_KERNEL is not set
1337# CONFIG_DEBUG_BUGVERBOSE is not set 1344CONFIG_DEBUG_BUGVERBOSE=y
1338# CONFIG_SAMPLES is not set 1345# CONFIG_SAMPLES is not set
1339CONFIG_DEBUG_MMRS=y 1346CONFIG_DEBUG_MMRS=y
1340CONFIG_DEBUG_HUNT_FOR_ZERO=y 1347CONFIG_DEBUG_HUNT_FOR_ZERO=y
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
index 16c198bd40c5..bae4ee6e68bb 100644
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ b/arch/blackfin/configs/CM-BF561_defconfig
@@ -308,12 +308,19 @@ CONFIG_DMA_UNCACHED_1M=y
308# Cache Support 308# Cache Support
309# 309#
310CONFIG_BFIN_ICACHE=y 310CONFIG_BFIN_ICACHE=y
311# CONFIG_BFIN_ICACHE_LOCK is not set
311CONFIG_BFIN_DCACHE=y 312CONFIG_BFIN_DCACHE=y
312# CONFIG_BFIN_DCACHE_BANKA is not set 313# CONFIG_BFIN_DCACHE_BANKA is not set
313# CONFIG_BFIN_ICACHE_LOCK is not set 314CONFIG_BFIN_EXTMEM_ICACHEABLE=y
314CONFIG_BFIN_WB=y 315CONFIG_BFIN_EXTMEM_DCACHEABLE=y
315# CONFIG_BFIN_WT is not set 316CONFIG_BFIN_EXTMEM_WRITEBACK=y
316CONFIG_L1_MAX_PIECE=16 317# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
318# CONFIG_BFIN_L2_ICACHEABLE is not set
319# CONFIG_BFIN_L2_DCACHEABLE is not set
320
321#
322# Memory Protection Unit
323#
317# CONFIG_MPU is not set 324# CONFIG_MPU is not set
318 325
319# 326#
@@ -395,11 +402,11 @@ CONFIG_IP_FIB_HASH=y
395# CONFIG_INET_IPCOMP is not set 402# CONFIG_INET_IPCOMP is not set
396# CONFIG_INET_XFRM_TUNNEL is not set 403# CONFIG_INET_XFRM_TUNNEL is not set
397# CONFIG_INET_TUNNEL is not set 404# CONFIG_INET_TUNNEL is not set
398CONFIG_INET_XFRM_MODE_TRANSPORT=y 405# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
399CONFIG_INET_XFRM_MODE_TUNNEL=y 406# CONFIG_INET_XFRM_MODE_TUNNEL is not set
400CONFIG_INET_XFRM_MODE_BEET=y 407# CONFIG_INET_XFRM_MODE_BEET is not set
401# CONFIG_INET_LRO is not set 408# CONFIG_INET_LRO is not set
402CONFIG_INET_DIAG=y 409# CONFIG_INET_DIAG is not set
403CONFIG_INET_TCP_DIAG=y 410CONFIG_INET_TCP_DIAG=y
404# CONFIG_TCP_CONG_ADVANCED is not set 411# CONFIG_TCP_CONG_ADVANCED is not set
405CONFIG_TCP_CONG_CUBIC=y 412CONFIG_TCP_CONG_CUBIC=y
@@ -837,7 +844,7 @@ CONFIG_ENABLE_MUST_CHECK=y
837CONFIG_DEBUG_FS=y 844CONFIG_DEBUG_FS=y
838# CONFIG_HEADERS_CHECK is not set 845# CONFIG_HEADERS_CHECK is not set
839# CONFIG_DEBUG_KERNEL is not set 846# CONFIG_DEBUG_KERNEL is not set
840# CONFIG_DEBUG_BUGVERBOSE is not set 847CONFIG_DEBUG_BUGVERBOSE=y
841# CONFIG_SAMPLES is not set 848# CONFIG_SAMPLES is not set
842CONFIG_DEBUG_MMRS=y 849CONFIG_DEBUG_MMRS=y
843CONFIG_DEBUG_HUNT_FOR_ZERO=y 850CONFIG_DEBUG_HUNT_FOR_ZERO=y
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig
index 6b4c1a982383..a6a7c8ede705 100644
--- a/arch/blackfin/configs/H8606_defconfig
+++ b/arch/blackfin/configs/H8606_defconfig
@@ -258,12 +258,18 @@ CONFIG_DMA_UNCACHED_1M=y
258# Cache Support 258# Cache Support
259# 259#
260CONFIG_BFIN_ICACHE=y 260CONFIG_BFIN_ICACHE=y
261# CONFIG_BFIN_ICACHE_LOCK is not set
261CONFIG_BFIN_DCACHE=y 262CONFIG_BFIN_DCACHE=y
262# CONFIG_BFIN_DCACHE_BANKA is not set 263# CONFIG_BFIN_DCACHE_BANKA is not set
263CONFIG_BFIN_ICACHE_LOCK=y 264CONFIG_BFIN_EXTMEM_ICACHEABLE=y
264CONFIG_BFIN_WB=y 265CONFIG_BFIN_EXTMEM_DCACHEABLE=y
265# CONFIG_BFIN_WT is not set 266CONFIG_BFIN_EXTMEM_WRITEBACK=y
266CONFIG_L1_MAX_PIECE=16 267# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
268
269#
270# Memory Protection Unit
271#
272# CONFIG_MPU is not set
267 273
268# 274#
269# Asynchonous Memory Configuration 275# Asynchonous Memory Configuration
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
index 09701f907e9b..ff377fae061b 100644
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ b/arch/blackfin/configs/PNAV-10_defconfig
@@ -295,11 +295,17 @@ CONFIG_DMA_UNCACHED_1M=y
295# Cache Support 295# Cache Support
296# 296#
297CONFIG_BFIN_ICACHE=y 297CONFIG_BFIN_ICACHE=y
298# CONFIG_BFIN_ICACHE_LOCK is not set
298CONFIG_BFIN_DCACHE=y 299CONFIG_BFIN_DCACHE=y
299# CONFIG_BFIN_DCACHE_BANKA is not set 300# CONFIG_BFIN_DCACHE_BANKA is not set
300# CONFIG_BFIN_ICACHE_LOCK is not set 301CONFIG_BFIN_EXTMEM_ICACHEABLE=y
301CONFIG_BFIN_WB=y 302CONFIG_BFIN_EXTMEM_DCACHEABLE=y
302# CONFIG_BFIN_WT is not set 303CONFIG_BFIN_EXTMEM_WRITEBACK=y
304# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
305
306#
307# Memory Protection Unit
308#
303# CONFIG_MPU is not set 309# CONFIG_MPU is not set
304 310
305# 311#
@@ -382,11 +388,11 @@ CONFIG_IP_PNP=y
382# CONFIG_INET_IPCOMP is not set 388# CONFIG_INET_IPCOMP is not set
383# CONFIG_INET_XFRM_TUNNEL is not set 389# CONFIG_INET_XFRM_TUNNEL is not set
384# CONFIG_INET_TUNNEL is not set 390# CONFIG_INET_TUNNEL is not set
385CONFIG_INET_XFRM_MODE_TRANSPORT=y 391# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
386CONFIG_INET_XFRM_MODE_TUNNEL=y 392# CONFIG_INET_XFRM_MODE_TUNNEL is not set
387CONFIG_INET_XFRM_MODE_BEET=y 393# CONFIG_INET_XFRM_MODE_BEET is not set
388# CONFIG_INET_LRO is not set 394# CONFIG_INET_LRO is not set
389CONFIG_INET_DIAG=y 395# CONFIG_INET_DIAG is not set
390CONFIG_INET_TCP_DIAG=y 396CONFIG_INET_TCP_DIAG=y
391# CONFIG_TCP_CONG_ADVANCED is not set 397# CONFIG_TCP_CONG_ADVANCED is not set
392CONFIG_TCP_CONG_CUBIC=y 398CONFIG_TCP_CONG_CUBIC=y
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
index ec84a53daae9..814f9cacf407 100644
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@@ -279,12 +279,18 @@ CONFIG_DMA_UNCACHED_2M=y
279# Cache Support 279# Cache Support
280# 280#
281CONFIG_BFIN_ICACHE=y 281CONFIG_BFIN_ICACHE=y
282# CONFIG_BFIN_ICACHE_LOCK is not set
282CONFIG_BFIN_DCACHE=y 283CONFIG_BFIN_DCACHE=y
283# CONFIG_BFIN_DCACHE_BANKA is not set 284# CONFIG_BFIN_DCACHE_BANKA is not set
284# CONFIG_BFIN_ICACHE_LOCK is not set 285CONFIG_BFIN_EXTMEM_ICACHEABLE=y
285CONFIG_BFIN_WB=y 286CONFIG_BFIN_EXTMEM_DCACHEABLE=y
286# CONFIG_BFIN_WT is not set 287CONFIG_BFIN_EXTMEM_WRITEBACK=y
287CONFIG_L1_MAX_PIECE=16 288# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
289
290#
291# Memory Protection Unit
292#
293# CONFIG_MPU is not set
288 294
289# 295#
290# Asynchonous Memory Configuration 296# Asynchonous Memory Configuration
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig
index 6e2796240fdc..375e75a27abc 100644
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ b/arch/blackfin/configs/TCM-BF537_defconfig
@@ -287,11 +287,17 @@ CONFIG_DMA_UNCACHED_1M=y
287# Cache Support 287# Cache Support
288# 288#
289CONFIG_BFIN_ICACHE=y 289CONFIG_BFIN_ICACHE=y
290# CONFIG_BFIN_ICACHE_LOCK is not set
290CONFIG_BFIN_DCACHE=y 291CONFIG_BFIN_DCACHE=y
291# CONFIG_BFIN_DCACHE_BANKA is not set 292# CONFIG_BFIN_DCACHE_BANKA is not set
292# CONFIG_BFIN_ICACHE_LOCK is not set 293CONFIG_BFIN_EXTMEM_ICACHEABLE=y
293CONFIG_BFIN_WB=y 294CONFIG_BFIN_EXTMEM_DCACHEABLE=y
294# CONFIG_BFIN_WT is not set 295CONFIG_BFIN_EXTMEM_WRITEBACK=y
296# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set
297
298#
299# Memory Protection Unit
300#
295# CONFIG_MPU is not set 301# CONFIG_MPU is not set
296 302
297# 303#
@@ -709,7 +715,7 @@ CONFIG_FRAME_WARN=1024
709CONFIG_DEBUG_FS=y 715CONFIG_DEBUG_FS=y
710# CONFIG_HEADERS_CHECK is not set 716# CONFIG_HEADERS_CHECK is not set
711# CONFIG_DEBUG_KERNEL is not set 717# CONFIG_DEBUG_KERNEL is not set
712# CONFIG_DEBUG_BUGVERBOSE is not set 718CONFIG_DEBUG_BUGVERBOSE=y
713# CONFIG_DEBUG_MEMORY_INIT is not set 719# CONFIG_DEBUG_MEMORY_INIT is not set
714# CONFIG_RCU_CPU_STALL_DETECTOR is not set 720# CONFIG_RCU_CPU_STALL_DETECTOR is not set
715# CONFIG_SYSCTL_SYSCALL_CHECK is not set 721# CONFIG_SYSCTL_SYSCALL_CHECK is not set
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
index 8bb2cb139756..4d4439583396 100644
--- a/arch/blackfin/include/asm/blackfin.h
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -86,6 +86,7 @@ static inline void CSYNC(void)
86 86
87#endif /* __ASSEMBLY__ */ 87#endif /* __ASSEMBLY__ */
88 88
89#include <asm/mem_map.h>
89#include <mach/blackfin.h> 90#include <mach/blackfin.h>
90#include <asm/bfin-global.h> 91#include <asm/bfin-global.h>
91 92
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index 2ef669ed9222..477050ad5c53 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -35,10 +35,10 @@
35 35
36#if defined(CONFIG_SMP) && \ 36#if defined(CONFIG_SMP) && \
37 !defined(CONFIG_BFIN_CACHE_COHERENT) 37 !defined(CONFIG_BFIN_CACHE_COHERENT)
38# if defined(CONFIG_BFIN_ICACHE) 38# if defined(CONFIG_BFIN_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
39# define __ARCH_SYNC_CORE_ICACHE 39# define __ARCH_SYNC_CORE_ICACHE
40# endif 40# endif
41# if defined(CONFIG_BFIN_DCACHE) 41# if defined(CONFIG_BFIN_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
42# define __ARCH_SYNC_CORE_DCACHE 42# define __ARCH_SYNC_CORE_DCACHE
43# endif 43# endif
44#ifndef __ASSEMBLY__ 44#ifndef __ASSEMBLY__
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 5c17dee53b5d..7e55549e180f 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -56,7 +56,7 @@ extern void blackfin_invalidate_entire_icache(void);
56 56
57static inline void flush_icache_range(unsigned start, unsigned end) 57static inline void flush_icache_range(unsigned start, unsigned end)
58{ 58{
59#if defined(CONFIG_BFIN_WB) 59#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
60 blackfin_dcache_flush_range(start, end); 60 blackfin_dcache_flush_range(start, end);
61#endif 61#endif
62 62
@@ -87,9 +87,9 @@ do { memcpy(dst, src, len); \
87#else 87#else
88# define invalidate_dcache_range(start,end) do { } while (0) 88# define invalidate_dcache_range(start,end) do { } while (0)
89#endif 89#endif
90#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB) 90#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
91# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) 91# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
92# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) 92# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
93#else 93#else
94# define flush_dcache_range(start,end) do { } while (0) 94# define flush_dcache_range(start,end) do { } while (0)
95# define flush_dcache_page(page) do { } while (0) 95# define flush_dcache_page(page) do { } while (0)
@@ -100,7 +100,7 @@ extern unsigned long reserved_mem_icache_on;
100 100
101static inline int bfin_addr_dcacheable(unsigned long addr) 101static inline int bfin_addr_dcacheable(unsigned long addr)
102{ 102{
103#ifdef CONFIG_BFIN_DCACHE 103#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
104 if (addr < (_ramend - DMA_UNCACHED_REGION)) 104 if (addr < (_ramend - DMA_UNCACHED_REGION))
105 return 1; 105 return 1;
106#endif 106#endif
@@ -109,7 +109,7 @@ static inline int bfin_addr_dcacheable(unsigned long addr)
109 addr >= _ramend && addr < physical_mem_end) 109 addr >= _ramend && addr < physical_mem_end)
110 return 1; 110 return 1;
111 111
112#ifndef CONFIG_BFIN_L2_NOT_CACHED 112#ifdef CONFIG_BFIN_L2_DCACHEABLE
113 if (addr >= L2_START && addr < L2_START + L2_LENGTH) 113 if (addr >= L2_START && addr < L2_START + L2_LENGTH)
114 return 1; 114 return 1;
115#endif 115#endif
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index a75a6a9f0949..c5dacf8f8cf9 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -37,8 +37,6 @@
37#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) 37#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
38#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) 38#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
39 39
40/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
41
42#if ANOMALY_05000158 40#if ANOMALY_05000158
43#define ANOMALY_05000158_WORKAROUND 0x200 41#define ANOMALY_05000158_WORKAROUND 0x200
44#else 42#else
@@ -47,10 +45,12 @@
47 45
48#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) 46#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
49 47
50#ifdef CONFIG_BFIN_WB /*Write Back Policy */ 48#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
51#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON) 49#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
52#else /*Write Through */ 50#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
53#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) 51#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
52#else
53#define SDRAM_DGENERIC (CPLB_COMMON)
54#endif 54#endif
55 55
56#define SDRAM_DNON_CHBL (CPLB_COMMON) 56#define SDRAM_DNON_CHBL (CPLB_COMMON)
@@ -61,21 +61,23 @@
61 61
62#ifdef CONFIG_SMP 62#ifdef CONFIG_SMP
63#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) 63#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
64#define L2_IMEMORY (CPLB_COMMON) 64#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
65#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON) 65#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
66 66
67#else 67#else
68#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) 68#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
69#define L2_IMEMORY (SDRAM_IGENERIC) 69# if defined(CONFIG_BFIN_L2_ICACHEABLE)
70 70# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
71# if defined(CONFIG_BFIN_L2_WB) 71# else
72# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON) 72# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
73# elif defined(CONFIG_BFIN_L2_WT) 73# endif
74# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) 74
75# elif defined(CONFIG_BFIN_L2_NOT_CACHED) 75# if defined(CONFIG_BFIN_L2_WRITEBACK)
76# define L2_DMEMORY (CPLB_COMMON) 76# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
77# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
78# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
77# else 79# else
78# define L2_DMEMORY (0) 80# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
79# endif 81# endif
80#endif /* CONFIG_SMP */ 82#endif /* CONFIG_SMP */
81 83
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
index d7d9148e433c..ed6b1f3cccce 100644
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -95,4 +95,17 @@ static inline void dma_sync_single_for_device(struct device *dev,
95 enum dma_data_direction dir) 95 enum dma_data_direction dir)
96{ 96{
97} 97}
98
99static inline void dma_sync_sg_for_cpu(struct device *dev,
100 struct scatterlist *sg,
101 int nents, enum dma_data_direction dir)
102{
103}
104
105static inline void dma_sync_sg_for_device(struct device *dev,
106 struct scatterlist *sg,
107 int nents, enum dma_data_direction dir)
108{
109}
110
98#endif /* _BLACKFIN_DMA_MAPPING_H */ 111#endif /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index bbe1c3726b69..87ba9ad399cb 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -35,9 +35,9 @@
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/traps.h> 36#include <asm/traps.h>
37 37
38#define IPIPE_ARCH_STRING "1.10-00" 38#define IPIPE_ARCH_STRING "1.11-00"
39#define IPIPE_MAJOR_NUMBER 1 39#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 10 40#define IPIPE_MINOR_NUMBER 11
41#define IPIPE_PATCH_NUMBER 0 41#define IPIPE_PATCH_NUMBER 0
42 42
43#ifdef CONFIG_SMP 43#ifdef CONFIG_SMP
@@ -207,7 +207,7 @@ void ipipe_init_irq_threads(void);
207 207
208int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); 208int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
209 209
210#ifdef CONFIG_GENERIC_CLOCKEVENTS 210#ifdef CONFIG_TICKSOURCE_CORETMR
211#define IRQ_SYSTMR IRQ_CORETMR 211#define IRQ_SYSTMR IRQ_CORETMR
212#define IRQ_PRIOTMR IRQ_CORETMR 212#define IRQ_PRIOTMR IRQ_CORETMR
213#else 213#else
@@ -240,8 +240,13 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
240#define ipipe_init_irq_threads() do { } while (0) 240#define ipipe_init_irq_threads() do { } while (0)
241#define ipipe_start_irq_thread(irq, desc) 0 241#define ipipe_start_irq_thread(irq, desc) 0
242 242
243#ifndef CONFIG_TICKSOURCE_GPTMR0
243#define IRQ_SYSTMR IRQ_CORETMR 244#define IRQ_SYSTMR IRQ_CORETMR
244#define IRQ_PRIOTMR IRQ_CORETMR 245#define IRQ_PRIOTMR IRQ_CORETMR
246#else
247#define IRQ_SYSTMR IRQ_TIMER0
248#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
249#endif
245 250
246#define __ipipe_root_tick_p(regs) 1 251#define __ipipe_root_tick_p(regs) 1
247 252
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
index 3e8acbd1a3be..490098f532a7 100644
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -51,23 +51,23 @@
51 51
52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ 52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
53 53
54static inline void __ipipe_stall_root(void) 54#define __ipipe_stall_root() \
55{ 55 do { \
56 volatile unsigned long *p = &__ipipe_root_status; 56 volatile unsigned long *p = &__ipipe_root_status; \
57 set_bit(0, p); 57 set_bit(0, p); \
58} 58 } while (0)
59 59
60static inline unsigned long __ipipe_test_and_stall_root(void) 60#define __ipipe_test_and_stall_root() \
61{ 61 ({ \
62 volatile unsigned long *p = &__ipipe_root_status; 62 volatile unsigned long *p = &__ipipe_root_status; \
63 return test_and_set_bit(0, p); 63 test_and_set_bit(0, p); \
64} 64 })
65 65
66static inline unsigned long __ipipe_test_root(void) 66#define __ipipe_test_root() \
67{ 67 ({ \
68 const unsigned long *p = &__ipipe_root_status; 68 const unsigned long *p = &__ipipe_root_status; \
69 return test_bit(0, p); 69 test_bit(0, p); \
70} 70 })
71 71
72#endif /* !__ASSEMBLY__ */ 72#endif /* !__ASSEMBLY__ */
73 73
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 9a7f63a83c47..42a15f5ce0d0 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -22,13 +22,6 @@
22/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */ 22/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
23#include <mach/irq.h> 23#include <mach/irq.h>
24 24
25/* Xenomai IPIPE helpers */
26#define local_irq_restore_hw(x) local_irq_restore(x)
27#define local_irq_save_hw(x) local_irq_save(x)
28#define local_irq_enable_hw(x) local_irq_enable(x)
29#define local_irq_disable_hw(x) local_irq_disable(x)
30#define irqs_disabled_hw(x) irqs_disabled(x)
31
32#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE) 25#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
33# define NOP_PAD_ANOMALY_05000244 "nop; nop;" 26# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
34#else 27#else
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 139cba4651b1..9b19a19d9ae9 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -31,6 +31,150 @@ static inline unsigned long bfin_cli(void)
31 return flags; 31 return flags;
32} 32}
33 33
34#ifdef CONFIG_IPIPE
35
36#include <linux/ipipe_base.h>
37#include <linux/ipipe_trace.h>
38
39#ifdef CONFIG_DEBUG_HWERR
40# define bfin_no_irqs 0x3f
41#else
42# define bfin_no_irqs 0x1f
43#endif
44
45#define raw_local_irq_disable() \
46 do { \
47 ipipe_check_context(ipipe_root_domain); \
48 __ipipe_stall_root(); \
49 barrier(); \
50 } while (0)
51
52static inline void raw_local_irq_enable(void)
53{
54 barrier();
55 ipipe_check_context(ipipe_root_domain);
56 __ipipe_unstall_root();
57}
58
59#define raw_local_save_flags_ptr(x) \
60 do { \
61 *(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \
62 } while (0)
63
64#define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x))
65
66#define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs)
67
68#define raw_local_irq_save_ptr(x) \
69 do { \
70 *(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \
71 barrier(); \
72 } while (0)
73
74#define raw_local_irq_save(x) \
75 do { \
76 ipipe_check_context(ipipe_root_domain); \
77 raw_local_irq_save_ptr(&(x)); \
78 } while (0)
79
80static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real)
81{
82 /*
83 * Merge virtual and real interrupt mask bits into a single
84 * 32bit word.
85 */
86 return (real & ~(1 << 31)) | ((virt != 0) << 31);
87}
88
89static inline int raw_demangle_irq_bits(unsigned long *x)
90{
91 int virt = (*x & (1 << 31)) != 0;
92 *x &= ~(1L << 31);
93 return virt;
94}
95
96static inline void local_irq_disable_hw_notrace(void)
97{
98 bfin_cli();
99}
100
101static inline void local_irq_enable_hw_notrace(void)
102{
103 bfin_sti(bfin_irq_flags);
104}
105
106#define local_save_flags_hw(flags) \
107 do { \
108 (flags) = bfin_read_IMASK(); \
109 } while (0)
110
111#define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0)
112
113#define irqs_disabled_hw() \
114 ({ \
115 unsigned long flags; \
116 local_save_flags_hw(flags); \
117 irqs_disabled_flags_hw(flags); \
118 })
119
120static inline void local_irq_save_ptr_hw(unsigned long *flags)
121{
122 *flags = bfin_cli();
123#ifdef CONFIG_DEBUG_HWERR
124 bfin_sti(0x3f);
125#endif
126}
127
128#define local_irq_save_hw_notrace(flags) \
129 do { \
130 local_irq_save_ptr_hw(&(flags)); \
131 } while (0)
132
133static inline void local_irq_restore_hw_notrace(unsigned long flags)
134{
135 if (!irqs_disabled_flags_hw(flags))
136 local_irq_enable_hw_notrace();
137}
138
139#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
140# define local_irq_disable_hw() \
141 do { \
142 if (!irqs_disabled_hw()) { \
143 local_irq_disable_hw_notrace(); \
144 ipipe_trace_begin(0x80000000); \
145 } \
146 } while (0)
147# define local_irq_enable_hw() \
148 do { \
149 if (irqs_disabled_hw()) { \
150 ipipe_trace_end(0x80000000); \
151 local_irq_enable_hw_notrace(); \
152 } \
153 } while (0)
154# define local_irq_save_hw(flags) \
155 do { \
156 local_save_flags_hw(flags); \
157 if (!irqs_disabled_flags_hw(flags)) { \
158 local_irq_disable_hw_notrace(); \
159 ipipe_trace_begin(0x80000001); \
160 } \
161 } while (0)
162# define local_irq_restore_hw(flags) \
163 do { \
164 if (!irqs_disabled_flags_hw(flags)) { \
165 ipipe_trace_end(0x80000001); \
166 local_irq_enable_hw_notrace(); \
167 } \
168 } while (0)
169#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
170# define local_irq_disable_hw() local_irq_disable_hw_notrace()
171# define local_irq_enable_hw() local_irq_enable_hw_notrace()
172# define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags)
173# define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags)
174#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
175
176#else /* CONFIG_IPIPE */
177
34static inline void raw_local_irq_disable(void) 178static inline void raw_local_irq_disable(void)
35{ 179{
36 bfin_cli(); 180 bfin_cli();
@@ -44,12 +188,6 @@ static inline void raw_local_irq_enable(void)
44 188
45#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0) 189#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0)
46 190
47static inline void raw_local_irq_restore(unsigned long flags)
48{
49 if (!raw_irqs_disabled_flags(flags))
50 raw_local_irq_enable();
51}
52
53static inline unsigned long __raw_local_irq_save(void) 191static inline unsigned long __raw_local_irq_save(void)
54{ 192{
55 unsigned long flags = bfin_cli(); 193 unsigned long flags = bfin_cli();
@@ -60,4 +198,18 @@ static inline unsigned long __raw_local_irq_save(void)
60} 198}
61#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0) 199#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0)
62 200
201#define local_irq_save_hw(flags) raw_local_irq_save(flags)
202#define local_irq_restore_hw(flags) raw_local_irq_restore(flags)
203#define local_irq_enable_hw() raw_local_irq_enable()
204#define local_irq_disable_hw() raw_local_irq_disable()
205#define irqs_disabled_hw() irqs_disabled()
206
207#endif /* !CONFIG_IPIPE */
208
209static inline void raw_local_irq_restore(unsigned long flags)
210{
211 if (!raw_irqs_disabled_flags(flags))
212 raw_local_irq_enable();
213}
214
63#endif 215#endif
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 61f7487fbf12..4179e329b9c9 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -59,7 +59,7 @@
59#define SDRAM_tRP TRP_1 59#define SDRAM_tRP TRP_1
60#define SDRAM_tRP_num 1 60#define SDRAM_tRP_num 1
61#define SDRAM_tRAS TRAS_4 61#define SDRAM_tRAS TRAS_4
62#define SDRAM_tRAS_num 3 62#define SDRAM_tRAS_num 4
63#define SDRAM_tRCD TRCD_1 63#define SDRAM_tRCD TRCD_1
64#define SDRAM_tWR TWR_2 64#define SDRAM_tWR TWR_2
65#endif 65#endif
@@ -89,6 +89,85 @@
89#endif 89#endif
90#endif 90#endif
91 91
92/*
93 * The BF526-EZ-Board changed SDRAM chips between revisions,
94 * so we use below timings to accommodate both.
95 */
96#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
97#if (CONFIG_SCLK_HZ > 119402985)
98#define SDRAM_tRP TRP_2
99#define SDRAM_tRP_num 2
100#define SDRAM_tRAS TRAS_8
101#define SDRAM_tRAS_num 8
102#define SDRAM_tRCD TRCD_2
103#define SDRAM_tWR TWR_2
104#endif
105#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
106#define SDRAM_tRP TRP_2
107#define SDRAM_tRP_num 2
108#define SDRAM_tRAS TRAS_7
109#define SDRAM_tRAS_num 7
110#define SDRAM_tRCD TRCD_2
111#define SDRAM_tWR TWR_2
112#endif
113#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
114#define SDRAM_tRP TRP_2
115#define SDRAM_tRP_num 2
116#define SDRAM_tRAS TRAS_6
117#define SDRAM_tRAS_num 6
118#define SDRAM_tRCD TRCD_2
119#define SDRAM_tWR TWR_2
120#endif
121#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
122#define SDRAM_tRP TRP_2
123#define SDRAM_tRP_num 2
124#define SDRAM_tRAS TRAS_5
125#define SDRAM_tRAS_num 5
126#define SDRAM_tRCD TRCD_2
127#define SDRAM_tWR TWR_2
128#endif
129#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
130#define SDRAM_tRP TRP_2
131#define SDRAM_tRP_num 2
132#define SDRAM_tRAS TRAS_4
133#define SDRAM_tRAS_num 4
134#define SDRAM_tRCD TRCD_2
135#define SDRAM_tWR TWR_2
136#endif
137#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
138#define SDRAM_tRP TRP_2
139#define SDRAM_tRP_num 2
140#define SDRAM_tRAS TRAS_4
141#define SDRAM_tRAS_num 4
142#define SDRAM_tRCD TRCD_1
143#define SDRAM_tWR TWR_2
144#endif
145#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
146#define SDRAM_tRP TRP_2
147#define SDRAM_tRP_num 2
148#define SDRAM_tRAS TRAS_3
149#define SDRAM_tRAS_num 3
150#define SDRAM_tRCD TRCD_1
151#define SDRAM_tWR TWR_2
152#endif
153#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
154#define SDRAM_tRP TRP_1
155#define SDRAM_tRP_num 1
156#define SDRAM_tRAS TRAS_3
157#define SDRAM_tRAS_num 3
158#define SDRAM_tRCD TRCD_1
159#define SDRAM_tWR TWR_2
160#endif
161#if (CONFIG_SCLK_HZ <= 29850746)
162#define SDRAM_tRP TRP_1
163#define SDRAM_tRP_num 1
164#define SDRAM_tRAS TRAS_2
165#define SDRAM_tRAS_num 2
166#define SDRAM_tRCD TRCD_1
167#define SDRAM_tWR TWR_2
168#endif
169#endif
170
92#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ 171#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
93 defined(CONFIG_MEM_MT48LC8M32B2B5_7) 172 defined(CONFIG_MEM_MT48LC8M32B2B5_7)
94 /*SDRAM INFORMATION: */ 173 /*SDRAM INFORMATION: */
@@ -109,6 +188,13 @@
109#define SDRAM_CL CL_3 188#define SDRAM_CL CL_3
110#endif 189#endif
111 190
191#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
192 /*SDRAM INFORMATION: */
193#define SDRAM_Tref 64 /* Refresh period in milliseconds */
194#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
195#define SDRAM_CL CL_2
196#endif
197
112 198
113#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC 199#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
114/* Equation from section 17 (p17-46) of BF533 HRM */ 200/* Equation from section 17 (p17-46) of BF533 HRM */
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
index e92b31051bb7..5e21627c9ba2 100644
--- a/arch/blackfin/include/asm/mem_map.h
+++ b/arch/blackfin/include/asm/mem_map.h
@@ -1,87 +1,84 @@
1/* 1/*
2 * mem_map.h 2 * Common Blackfin memory map
3 * Common header file for blackfin family of processors.
4 * 3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 * Licensed under the GPL-2 or later.
5 */ 6 */
6 7
7#ifndef _MEM_MAP_H_ 8#ifndef __BFIN_MEM_MAP_H__
8#define _MEM_MAP_H_ 9#define __BFIN_MEM_MAP_H__
9 10
10#include <mach/mem_map.h> 11#include <mach/mem_map.h>
11 12
12#ifndef __ASSEMBLY__ 13/* Every Blackfin so far has MMRs like this */
14#ifndef COREMMR_BASE
15# define COREMMR_BASE 0xFFE00000
16#endif
17#ifndef SYSMMR_BASE
18# define SYSMMR_BASE 0xFFC00000
19#endif
13 20
14#ifdef CONFIG_SMP 21/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
15static inline ulong get_l1_scratch_start_cpu(int cpu) 22#ifndef L1_SCRATCH_START
16{ 23# define L1_SCRATCH_START 0xFFB00000
17 return (cpu) ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START; 24# define L1_SCRATCH_LENGTH 0x1000
18} 25#endif
19static inline ulong get_l1_code_start_cpu(int cpu)
20{
21 return (cpu) ? COREB_L1_CODE_START : COREA_L1_CODE_START;
22}
23static inline ulong get_l1_data_a_start_cpu(int cpu)
24{
25 return (cpu) ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
26}
27static inline ulong get_l1_data_b_start_cpu(int cpu)
28{
29 return (cpu) ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
30}
31 26
32static inline ulong get_l1_scratch_start(void) 27/* Most parts lack on-chip L2 SRAM */
33{ 28#ifndef L2_START
34 return get_l1_scratch_start_cpu(blackfin_core_id()); 29# define L2_START 0
35} 30# define L2_LENGTH 0
36static inline ulong get_l1_code_start(void) 31#endif
37{ 32
38 return get_l1_code_start_cpu(blackfin_core_id()); 33/* Most parts lack on-chip L1 ROM */
39} 34#ifndef L1_ROM_START
40static inline ulong get_l1_data_a_start(void) 35# define L1_ROM_START 0
41{ 36# define L1_ROM_LENGTH 0
42 return get_l1_data_a_start_cpu(blackfin_core_id()); 37#endif
43} 38
44static inline ulong get_l1_data_b_start(void) 39/* Allow wonky SMP ports to override this */
45{ 40#ifndef GET_PDA_SAFE
46 return get_l1_data_b_start_cpu(blackfin_core_id()); 41# define GET_PDA_SAFE(preg) \
47} 42 preg.l = _cpu_pda; \
43 preg.h = _cpu_pda;
44# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
48 45
49#else /* !CONFIG_SMP */ 46# ifndef __ASSEMBLY__
50 47
51static inline ulong get_l1_scratch_start_cpu(int cpu) 48static inline unsigned long get_l1_scratch_start_cpu(int cpu)
52{ 49{
53 return L1_SCRATCH_START; 50 return L1_SCRATCH_START;
54} 51}
55static inline ulong get_l1_code_start_cpu(int cpu) 52static inline unsigned long get_l1_code_start_cpu(int cpu)
56{ 53{
57 return L1_CODE_START; 54 return L1_CODE_START;
58} 55}
59static inline ulong get_l1_data_a_start_cpu(int cpu) 56static inline unsigned long get_l1_data_a_start_cpu(int cpu)
60{ 57{
61 return L1_DATA_A_START; 58 return L1_DATA_A_START;
62} 59}
63static inline ulong get_l1_data_b_start_cpu(int cpu) 60static inline unsigned long get_l1_data_b_start_cpu(int cpu)
64{ 61{
65 return L1_DATA_B_START; 62 return L1_DATA_B_START;
66} 63}
67static inline ulong get_l1_scratch_start(void) 64static inline unsigned long get_l1_scratch_start(void)
68{ 65{
69 return get_l1_scratch_start_cpu(0); 66 return get_l1_scratch_start_cpu(0);
70} 67}
71static inline ulong get_l1_code_start(void) 68static inline unsigned long get_l1_code_start(void)
72{ 69{
73 return get_l1_code_start_cpu(0); 70 return get_l1_code_start_cpu(0);
74} 71}
75static inline ulong get_l1_data_a_start(void) 72static inline unsigned long get_l1_data_a_start(void)
76{ 73{
77 return get_l1_data_a_start_cpu(0); 74 return get_l1_data_a_start_cpu(0);
78} 75}
79static inline ulong get_l1_data_b_start(void) 76static inline unsigned long get_l1_data_b_start(void)
80{ 77{
81 return get_l1_data_b_start_cpu(0); 78 return get_l1_data_b_start_cpu(0);
82} 79}
83 80
84#endif /* CONFIG_SMP */ 81# endif /* __ASSEMBLY__ */
85#endif /* __ASSEMBLY__ */ 82#endif /* !GET_PDA_SAFE */
86 83
87#endif /* _MEM_MAP_H_ */ 84#endif
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
index 294dbda24164..85e8f16cf8c2 100644
--- a/arch/blackfin/include/asm/system.h
+++ b/arch/blackfin/include/asm/system.h
@@ -135,11 +135,13 @@ struct __xchg_dummy {
135}; 135};
136#define __xg(x) ((volatile struct __xchg_dummy *)(x)) 136#define __xg(x) ((volatile struct __xchg_dummy *)(x))
137 137
138#include <mach/blackfin.h>
139
138static inline unsigned long __xchg(unsigned long x, volatile void *ptr, 140static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
139 int size) 141 int size)
140{ 142{
141 unsigned long tmp = 0; 143 unsigned long tmp = 0;
142 unsigned long flags = 0; 144 unsigned long flags;
143 145
144 local_irq_save_hw(flags); 146 local_irq_save_hw(flags);
145 147
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
index 34f7295fb070..3cdc454cde23 100644
--- a/arch/blackfin/include/asm/traps.h
+++ b/arch/blackfin/include/asm/traps.h
@@ -111,9 +111,7 @@
111 level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" 111 level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
112#define EXC_0x2A(level) \ 112#define EXC_0x2A(level) \
113 "Instruction fetch misaligned address violation\n" \ 113 "Instruction fetch misaligned address violation\n" \
114 level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ 114 level " - Attempted misaligned instruction cache fetch.\n"
115 level " exception, the return address provided in RETX is the destination address which is\n" \
116 level " misaligned, rather than the address of the offending instruction.\n"
117#define EXC_0x2B(level) \ 115#define EXC_0x2B(level) \
118 "CPLB protection violation\n" \ 116 "CPLB protection violation\n" \
119 level " - Illegal instruction fetch access (memory protection violation).\n" 117 level " - Illegal instruction fetch access (memory protection violation).\n"
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
index 8894e9ffbb57..2f469a1f80fb 100644
--- a/arch/blackfin/include/asm/uaccess.h
+++ b/arch/blackfin/include/asm/uaccess.h
@@ -265,4 +265,26 @@ __clear_user(void *to, unsigned long n)
265 265
266#define clear_user(to, n) __clear_user(to, n) 266#define clear_user(to, n) __clear_user(to, n)
267 267
268/* How to interpret these return values:
269 * CORE: can be accessed by core load or dma memcpy
270 * CORE_ONLY: can only be accessed by core load
271 * DMA: can only be accessed by dma memcpy
272 * IDMA: can only be accessed by interprocessor dma memcpy (BF561)
273 * ITEST: can be accessed by isram memcpy or dma memcpy
274 */
275enum {
276 BFIN_MEM_ACCESS_CORE = 0,
277 BFIN_MEM_ACCESS_CORE_ONLY,
278 BFIN_MEM_ACCESS_DMA,
279 BFIN_MEM_ACCESS_IDMA,
280 BFIN_MEM_ACCESS_ITEST,
281};
282/**
283 * bfin_mem_access_type() - what kind of memory access is required
284 * @addr: the address to check
285 * @size: number of bytes needed
286 * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above)
287 */
288int bfin_mem_access_type(unsigned long addr, unsigned long size);
289
268#endif /* _BLACKFIN_UACCESS_H */ 290#endif /* _BLACKFIN_UACCESS_H */
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index da35133c171d..c8e7ee4768cd 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -381,8 +381,9 @@
381#define __NR_preadv 366 381#define __NR_preadv 366
382#define __NR_pwritev 367 382#define __NR_pwritev 367
383#define __NR_rt_tgsigqueueinfo 368 383#define __NR_rt_tgsigqueueinfo 368
384#define __NR_perf_counter_open 369
384 385
385#define __NR_syscall 369 386#define __NR_syscall 370
386#define NR_syscalls __NR_syscall 387#define NR_syscalls __NR_syscall
387 388
388/* Old optional stuff no one actually uses */ 389/* Old optional stuff no one actually uses */
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 3731088e181b..141d9281e4b0 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -20,7 +20,6 @@ obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
20CFLAGS_REMOVE_ftrace.o = -pg 20CFLAGS_REMOVE_ftrace.o = -pg
21 21
22obj-$(CONFIG_IPIPE) += ipipe.o 22obj-$(CONFIG_IPIPE) += ipipe.o
23obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o
24obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o 23obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
25obj-$(CONFIG_CPLB_INFO) += cplbinfo.o 24obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
26obj-$(CONFIG_MODULES) += module.o 25obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
index c006a44527bf..36193eed9a1f 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -46,13 +46,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
46 46
47 printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n"); 47 printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
48 48
49#ifdef CONFIG_BFIN_ICACHE 49#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
50 i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; 50 i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
51#endif 51#endif
52 52
53#ifdef CONFIG_BFIN_DCACHE 53#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
54 d_cache = CPLB_L1_CHBL; 54 d_cache = CPLB_L1_CHBL;
55#ifdef CONFIG_BFIN_WT 55#ifdef CONFIG_BFIN_EXTMEM_WRITETROUGH
56 d_cache |= CPLB_L1_AOW | CPLB_WT; 56 d_cache |= CPLB_L1_AOW | CPLB_WT;
57#endif 57#endif
58#endif 58#endif
@@ -91,9 +91,9 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
91 /* Cover L2 memory */ 91 /* Cover L2 memory */
92#if L2_LENGTH > 0 92#if L2_LENGTH > 0
93 dcplb_tbl[cpu][i_d].addr = L2_START; 93 dcplb_tbl[cpu][i_d].addr = L2_START;
94 dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB; 94 dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
95 icplb_tbl[cpu][i_i].addr = L2_START; 95 icplb_tbl[cpu][i_i].addr = L2_START;
96 icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB; 96 icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
97#endif 97#endif
98 98
99 first_mask_dcplb = i_d; 99 first_mask_dcplb = i_d;
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index 784923e52a9a..bcdfe9b0b71f 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -150,15 +150,19 @@ static noinline int dcplb_miss(unsigned int cpu)
150 nr_dcplb_miss[cpu]++; 150 nr_dcplb_miss[cpu]++;
151 151
152 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; 152 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
153#ifdef CONFIG_BFIN_DCACHE 153#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
154 if (bfin_addr_dcacheable(addr)) { 154 if (bfin_addr_dcacheable(addr)) {
155 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; 155 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
156#ifdef CONFIG_BFIN_WT 156# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
157 d_data |= CPLB_L1_AOW | CPLB_WT; 157 d_data |= CPLB_L1_AOW | CPLB_WT;
158#endif 158# endif
159 } 159 }
160#endif 160#endif
161 if (addr >= physical_mem_end) { 161
162 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
163 addr = L2_START;
164 d_data = L2_DMEMORY;
165 } else if (addr >= physical_mem_end) {
162 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE 166 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE
163 && (status & FAULT_USERSUPV)) { 167 && (status & FAULT_USERSUPV)) {
164 addr &= ~0x3fffff; 168 addr &= ~0x3fffff;
@@ -235,7 +239,7 @@ static noinline int icplb_miss(unsigned int cpu)
235 239
236 i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB; 240 i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
237 241
238#ifdef CONFIG_BFIN_ICACHE 242#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
239 /* 243 /*
240 * Normal RAM, and possibly the reserved memory area, are 244 * Normal RAM, and possibly the reserved memory area, are
241 * cacheable. 245 * cacheable.
@@ -245,7 +249,10 @@ static noinline int icplb_miss(unsigned int cpu)
245 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; 249 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
246#endif 250#endif
247 251
248 if (addr >= physical_mem_end) { 252 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
253 addr = L2_START;
254 i_data = L2_IMEMORY;
255 } else if (addr >= physical_mem_end) {
249 if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH 256 if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
250 && (status & FAULT_USERSUPV)) { 257 && (status & FAULT_USERSUPV)) {
251 addr &= ~(1 * 1024 * 1024 - 1); 258 addr &= ~(1 * 1024 * 1024 - 1);
@@ -365,13 +372,18 @@ void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
365 local_irq_save_hw(flags); 372 local_irq_save_hw(flags);
366 current_rwx_mask[cpu] = masks; 373 current_rwx_mask[cpu] = masks;
367 374
368 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; 375 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
369#ifdef CONFIG_BFIN_DCACHE 376 addr = L2_START;
370 d_data |= CPLB_L1_CHBL; 377 d_data = L2_DMEMORY;
371#ifdef CONFIG_BFIN_WT 378 } else {
372 d_data |= CPLB_L1_AOW | CPLB_WT; 379 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
373#endif 380#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
381 d_data |= CPLB_L1_CHBL;
382# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
383 d_data |= CPLB_L1_AOW | CPLB_WT;
384# endif
374#endif 385#endif
386 }
375 387
376 disable_dcplb(); 388 disable_dcplb();
377 for (i = first_mask_dcplb; i < first_switched_dcplb; i++) { 389 for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index d8cde1fc5cb9..b8d22034b9a6 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -52,7 +52,7 @@ EXPORT_SYMBOL(__ipipe_freq_scale);
52 52
53atomic_t __ipipe_irq_lvdepth[IVG15 + 1]; 53atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
54 54
55unsigned long __ipipe_irq_lvmask = __all_masked_irq_flags; 55unsigned long __ipipe_irq_lvmask = bfin_no_irqs;
56EXPORT_SYMBOL(__ipipe_irq_lvmask); 56EXPORT_SYMBOL(__ipipe_irq_lvmask);
57 57
58static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc) 58static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc)
@@ -342,8 +342,3 @@ void ___ipipe_sync_pipeline(unsigned long syncmask)
342} 342}
343 343
344EXPORT_SYMBOL(show_stack); 344EXPORT_SYMBOL(show_stack);
345
346#ifdef CONFIG_IPIPE_TRACE_MCOUNT
347void notrace _mcount(void);
348EXPORT_SYMBOL(_mcount);
349#endif /* CONFIG_IPIPE_TRACE_MCOUNT */
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 6e31e935bb31..4b5fd36187d9 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -38,38 +38,15 @@
38#include <asm/pda.h> 38#include <asm/pda.h>
39 39
40static atomic_t irq_err_count; 40static atomic_t irq_err_count;
41static spinlock_t irq_controller_lock;
42
43/*
44 * Dummy mask/unmask handler
45 */
46void dummy_mask_unmask_irq(unsigned int irq)
47{
48}
49
50void ack_bad_irq(unsigned int irq) 41void ack_bad_irq(unsigned int irq)
51{ 42{
52 atomic_inc(&irq_err_count); 43 atomic_inc(&irq_err_count);
53 printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq); 44 printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
54} 45}
55 46
56static struct irq_chip bad_chip = {
57 .ack = dummy_mask_unmask_irq,
58 .mask = dummy_mask_unmask_irq,
59 .unmask = dummy_mask_unmask_irq,
60};
61
62static int bad_stats;
63static struct irq_desc bad_irq_desc = { 47static struct irq_desc bad_irq_desc = {
64 .status = IRQ_DISABLED,
65 .chip = &bad_chip,
66 .handle_irq = handle_bad_irq, 48 .handle_irq = handle_bad_irq,
67 .depth = 1,
68 .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock), 49 .lock = __SPIN_LOCK_UNLOCKED(irq_desc->lock),
69 .kstat_irqs = &bad_stats,
70#ifdef CONFIG_SMP
71 .affinity = CPU_MASK_ALL
72#endif
73}; 50};
74 51
75#ifdef CONFIG_CPUMASK_OFFSTACK 52#ifdef CONFIG_CPUMASK_OFFSTACK
@@ -77,6 +54,7 @@ static struct irq_desc bad_irq_desc = {
77#error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK." 54#error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK."
78#endif 55#endif
79 56
57#ifdef CONFIG_PROC_FS
80int show_interrupts(struct seq_file *p, void *v) 58int show_interrupts(struct seq_file *p, void *v)
81{ 59{
82 int i = *(loff_t *) v, j; 60 int i = *(loff_t *) v, j;
@@ -108,50 +86,29 @@ int show_interrupts(struct seq_file *p, void *v)
108 } 86 }
109 return 0; 87 return 0;
110} 88}
111
112/*
113 * do_IRQ handles all hardware IRQs. Decoded IRQs should not
114 * come via this function. Instead, they should provide their
115 * own 'handler'
116 */
117#ifdef CONFIG_DO_IRQ_L1
118__attribute__((l1_text))
119#endif
120asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
121{
122 struct pt_regs *old_regs;
123 struct irq_desc *desc = irq_desc + irq;
124#ifndef CONFIG_IPIPE
125 unsigned short pending, other_ints;
126#endif 89#endif
127 old_regs = set_irq_regs(regs);
128 90
129 /*
130 * Some hardware gives randomly wrong interrupts. Rather
131 * than crashing, do something sensible.
132 */
133 if (irq >= NR_IRQS)
134 desc = &bad_irq_desc;
135
136 irq_enter();
137#ifdef CONFIG_DEBUG_STACKOVERFLOW 91#ifdef CONFIG_DEBUG_STACKOVERFLOW
92static void check_stack_overflow(int irq)
93{
138 /* Debugging check for stack overflow: is there less than STACK_WARN free? */ 94 /* Debugging check for stack overflow: is there less than STACK_WARN free? */
139 { 95 long sp = __get_SP() & (THREAD_SIZE - 1);
140 long sp;
141
142 sp = __get_SP() & (THREAD_SIZE-1);
143 96
144 if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) { 97 if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
145 dump_stack(); 98 dump_stack();
146 printk(KERN_EMERG "%s: possible stack overflow while handling irq %i " 99 pr_emerg("irq%i: possible stack overflow only %ld bytes free\n",
147 " only %ld bytes free\n", 100 irq, sp - sizeof(struct thread_info));
148 __func__, irq, sp - sizeof(struct thread_info));
149 }
150 } 101 }
102}
103#else
104static inline void check_stack_overflow(int irq) { }
151#endif 105#endif
152 generic_handle_irq(irq);
153 106
154#ifndef CONFIG_IPIPE 107#ifndef CONFIG_IPIPE
108static void maybe_lower_to_irq14(void)
109{
110 unsigned short pending, other_ints;
111
155 /* 112 /*
156 * If we're the only interrupt running (ignoring IRQ15 which 113 * If we're the only interrupt running (ignoring IRQ15 which
157 * is for syscalls), lower our priority to IRQ14 so that 114 * is for syscalls), lower our priority to IRQ14 so that
@@ -165,7 +122,38 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
165 other_ints = pending & (pending - 1); 122 other_ints = pending & (pending - 1);
166 if (other_ints == 0) 123 if (other_ints == 0)
167 lower_to_irq14(); 124 lower_to_irq14();
168#endif /* !CONFIG_IPIPE */ 125}
126#else
127static inline void maybe_lower_to_irq14(void) { }
128#endif
129
130/*
131 * do_IRQ handles all hardware IRQs. Decoded IRQs should not
132 * come via this function. Instead, they should provide their
133 * own 'handler'
134 */
135#ifdef CONFIG_DO_IRQ_L1
136__attribute__((l1_text))
137#endif
138asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
139{
140 struct pt_regs *old_regs = set_irq_regs(regs);
141
142 irq_enter();
143
144 check_stack_overflow(irq);
145
146 /*
147 * Some hardware gives randomly wrong interrupts. Rather
148 * than crashing, do something sensible.
149 */
150 if (irq >= NR_IRQS)
151 handle_bad_irq(irq, &bad_irq_desc);
152 else
153 generic_handle_irq(irq);
154
155 maybe_lower_to_irq14();
156
169 irq_exit(); 157 irq_exit();
170 158
171 set_irq_regs(old_regs); 159 set_irq_regs(old_regs);
@@ -173,14 +161,6 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
173 161
174void __init init_IRQ(void) 162void __init init_IRQ(void)
175{ 163{
176 struct irq_desc *desc;
177 int irq;
178
179 spin_lock_init(&irq_controller_lock);
180 for (irq = 0, desc = irq_desc; irq < NR_IRQS; irq++, desc++) {
181 *desc = bad_irq_desc;
182 }
183
184 init_arch_irq(); 164 init_arch_irq();
185 165
186#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND 166#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index da28f796ad78..cce79d05b90b 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -34,15 +34,6 @@ int gdb_bfin_vector = -1;
34#error change the definition of slavecpulocks 34#error change the definition of slavecpulocks
35#endif 35#endif
36 36
37#define IN_MEM(addr, size, l1_addr, l1_size) \
38({ \
39 unsigned long __addr = (unsigned long)(addr); \
40 (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
41})
42#define ASYNC_BANK_SIZE \
43 (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
44 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
45
46void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) 37void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
47{ 38{
48 gdb_regs[BFIN_R0] = regs->r0; 39 gdb_regs[BFIN_R0] = regs->r0;
@@ -463,41 +454,88 @@ static int hex(char ch)
463 454
464static int validate_memory_access_address(unsigned long addr, int size) 455static int validate_memory_access_address(unsigned long addr, int size)
465{ 456{
466 int cpu = raw_smp_processor_id(); 457 if (size < 0 || addr == 0)
467
468 if (size < 0)
469 return -EFAULT; 458 return -EFAULT;
470 if (addr >= 0x1000 && (addr + size) <= physical_mem_end) 459 return bfin_mem_access_type(addr, size);
471 return 0; 460}
472 if (addr >= SYSMMR_BASE) 461
473 return 0; 462static int bfin_probe_kernel_read(char *dst, char *src, int size)
474 if (IN_MEM(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE)) 463{
475 return 0; 464 unsigned long lsrc = (unsigned long)src;
476 if (cpu == 0) { 465 int mem_type;
477 if (IN_MEM(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH)) 466
478 return 0; 467 mem_type = validate_memory_access_address(lsrc, size);
479 if (IN_MEM(addr, size, L1_CODE_START, L1_CODE_LENGTH)) 468 if (mem_type < 0)
480 return 0; 469 return mem_type;
481 if (IN_MEM(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH)) 470
482 return 0; 471 if (lsrc >= SYSMMR_BASE) {
483 if (IN_MEM(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH)) 472 if (size == 2 && lsrc % 2 == 0) {
484 return 0; 473 u16 mmr = bfin_read16(src);
485#ifdef CONFIG_SMP 474 memcpy(dst, &mmr, sizeof(mmr));
486 } else if (cpu == 1) {
487 if (IN_MEM(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
488 return 0; 475 return 0;
489 if (IN_MEM(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH)) 476 } else if (size == 4 && lsrc % 4 == 0) {
477 u32 mmr = bfin_read32(src);
478 memcpy(dst, &mmr, sizeof(mmr));
490 return 0; 479 return 0;
491 if (IN_MEM(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH)) 480 }
481 } else {
482 switch (mem_type) {
483 case BFIN_MEM_ACCESS_CORE:
484 case BFIN_MEM_ACCESS_CORE_ONLY:
485 return probe_kernel_read(dst, src, size);
486 /* XXX: should support IDMA here with SMP */
487 case BFIN_MEM_ACCESS_DMA:
488 if (dma_memcpy(dst, src, size))
489 return 0;
490 break;
491 case BFIN_MEM_ACCESS_ITEST:
492 if (isram_memcpy(dst, src, size))
493 return 0;
494 break;
495 }
496 }
497
498 return -EFAULT;
499}
500
501static int bfin_probe_kernel_write(char *dst, char *src, int size)
502{
503 unsigned long ldst = (unsigned long)dst;
504 int mem_type;
505
506 mem_type = validate_memory_access_address(ldst, size);
507 if (mem_type < 0)
508 return mem_type;
509
510 if (ldst >= SYSMMR_BASE) {
511 if (size == 2 && ldst % 2 == 0) {
512 u16 mmr;
513 memcpy(&mmr, src, sizeof(mmr));
514 bfin_write16(dst, mmr);
492 return 0; 515 return 0;
493 if (IN_MEM(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH)) 516 } else if (size == 4 && ldst % 4 == 0) {
517 u32 mmr;
518 memcpy(&mmr, src, sizeof(mmr));
519 bfin_write32(dst, mmr);
494 return 0; 520 return 0;
495#endif 521 }
522 } else {
523 switch (mem_type) {
524 case BFIN_MEM_ACCESS_CORE:
525 case BFIN_MEM_ACCESS_CORE_ONLY:
526 return probe_kernel_write(dst, src, size);
527 /* XXX: should support IDMA here with SMP */
528 case BFIN_MEM_ACCESS_DMA:
529 if (dma_memcpy(dst, src, size))
530 return 0;
531 break;
532 case BFIN_MEM_ACCESS_ITEST:
533 if (isram_memcpy(dst, src, size))
534 return 0;
535 break;
536 }
496 } 537 }
497 538
498 if (IN_MEM(addr, size, L2_START, L2_LENGTH))
499 return 0;
500
501 return -EFAULT; 539 return -EFAULT;
502} 540}
503 541
@@ -509,14 +547,6 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
509{ 547{
510 char *tmp; 548 char *tmp;
511 int err; 549 int err;
512 unsigned char *pch;
513 unsigned short mmr16;
514 unsigned long mmr32;
515 int cpu = raw_smp_processor_id();
516
517 err = validate_memory_access_address((unsigned long)mem, count);
518 if (err)
519 return err;
520 550
521 /* 551 /*
522 * We use the upper half of buf as an intermediate buffer for the 552 * We use the upper half of buf as an intermediate buffer for the
@@ -524,44 +554,7 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
524 */ 554 */
525 tmp = buf + count; 555 tmp = buf + count;
526 556
527 if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ 557 err = bfin_probe_kernel_read(tmp, mem, count);
528 switch (count) {
529 case 2:
530 if ((unsigned int)mem % 2 == 0) {
531 mmr16 = *(unsigned short *)mem;
532 pch = (unsigned char *)&mmr16;
533 *tmp++ = *pch++;
534 *tmp++ = *pch++;
535 tmp -= 2;
536 } else
537 err = -EFAULT;
538 break;
539 case 4:
540 if ((unsigned int)mem % 4 == 0) {
541 mmr32 = *(unsigned long *)mem;
542 pch = (unsigned char *)&mmr32;
543 *tmp++ = *pch++;
544 *tmp++ = *pch++;
545 *tmp++ = *pch++;
546 *tmp++ = *pch++;
547 tmp -= 4;
548 } else
549 err = -EFAULT;
550 break;
551 default:
552 err = -EFAULT;
553 }
554 } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
555#ifdef CONFIG_SMP
556 || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
557#endif
558 ) {
559 /* access L1 instruction SRAM*/
560 if (dma_memcpy(tmp, mem, count) == NULL)
561 err = -EFAULT;
562 } else
563 err = probe_kernel_read(tmp, mem, count);
564
565 if (!err) { 558 if (!err) {
566 while (count > 0) { 559 while (count > 0) {
567 buf = pack_hex_byte(buf, *tmp); 560 buf = pack_hex_byte(buf, *tmp);
@@ -582,13 +575,8 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
582 */ 575 */
583int kgdb_ebin2mem(char *buf, char *mem, int count) 576int kgdb_ebin2mem(char *buf, char *mem, int count)
584{ 577{
585 char *tmp_old; 578 char *tmp_old, *tmp_new;
586 char *tmp_new;
587 unsigned short *mmr16;
588 unsigned long *mmr32;
589 int err;
590 int size; 579 int size;
591 int cpu = raw_smp_processor_id();
592 580
593 tmp_old = tmp_new = buf; 581 tmp_old = tmp_new = buf;
594 582
@@ -601,41 +589,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count)
601 tmp_old++; 589 tmp_old++;
602 } 590 }
603 591
604 err = validate_memory_access_address((unsigned long)mem, size); 592 return bfin_probe_kernel_write(mem, buf, count);
605 if (err)
606 return err;
607
608 if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
609 switch (size) {
610 case 2:
611 if ((unsigned int)mem % 2 == 0) {
612 mmr16 = (unsigned short *)buf;
613 *(unsigned short *)mem = *mmr16;
614 } else
615 err = -EFAULT;
616 break;
617 case 4:
618 if ((unsigned int)mem % 4 == 0) {
619 mmr32 = (unsigned long *)buf;
620 *(unsigned long *)mem = *mmr32;
621 } else
622 err = -EFAULT;
623 break;
624 default:
625 err = -EFAULT;
626 }
627 } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
628#ifdef CONFIG_SMP
629 || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
630#endif
631 ) {
632 /* access L1 instruction SRAM */
633 if (dma_memcpy(mem, buf, size) == NULL)
634 err = -EFAULT;
635 } else
636 err = probe_kernel_write(mem, buf, size);
637
638 return err;
639} 593}
640 594
641/* 595/*
@@ -645,16 +599,7 @@ int kgdb_ebin2mem(char *buf, char *mem, int count)
645 */ 599 */
646int kgdb_hex2mem(char *buf, char *mem, int count) 600int kgdb_hex2mem(char *buf, char *mem, int count)
647{ 601{
648 char *tmp_raw; 602 char *tmp_raw, *tmp_hex;
649 char *tmp_hex;
650 unsigned short *mmr16;
651 unsigned long *mmr32;
652 int err;
653 int cpu = raw_smp_processor_id();
654
655 err = validate_memory_access_address((unsigned long)mem, count);
656 if (err)
657 return err;
658 603
659 /* 604 /*
660 * We use the upper half of buf as an intermediate buffer for the 605 * We use the upper half of buf as an intermediate buffer for the
@@ -669,39 +614,18 @@ int kgdb_hex2mem(char *buf, char *mem, int count)
669 *tmp_raw |= hex(*tmp_hex--) << 4; 614 *tmp_raw |= hex(*tmp_hex--) << 4;
670 } 615 }
671 616
672 if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/ 617 return bfin_probe_kernel_write(mem, tmp_raw, count);
673 switch (count) {
674 case 2:
675 if ((unsigned int)mem % 2 == 0) {
676 mmr16 = (unsigned short *)tmp_raw;
677 *(unsigned short *)mem = *mmr16;
678 } else
679 err = -EFAULT;
680 break;
681 case 4:
682 if ((unsigned int)mem % 4 == 0) {
683 mmr32 = (unsigned long *)tmp_raw;
684 *(unsigned long *)mem = *mmr32;
685 } else
686 err = -EFAULT;
687 break;
688 default:
689 err = -EFAULT;
690 }
691 } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
692#ifdef CONFIG_SMP
693 || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
694#endif
695 ) {
696 /* access L1 instruction SRAM */
697 if (dma_memcpy(mem, tmp_raw, count) == NULL)
698 err = -EFAULT;
699 } else
700 err = probe_kernel_write(mem, tmp_raw, count);
701
702 return err;
703} 618}
704 619
620#define IN_MEM(addr, size, l1_addr, l1_size) \
621({ \
622 unsigned long __addr = (unsigned long)(addr); \
623 (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
624})
625#define ASYNC_BANK_SIZE \
626 (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
627 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
628
705int kgdb_validate_break_address(unsigned long addr) 629int kgdb_validate_break_address(unsigned long addr)
706{ 630{
707 int cpu = raw_smp_processor_id(); 631 int cpu = raw_smp_processor_id();
@@ -724,46 +648,17 @@ int kgdb_validate_break_address(unsigned long addr)
724 648
725int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr) 649int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
726{ 650{
727 int err; 651 int err = bfin_probe_kernel_read(saved_instr, (char *)addr,
728 int cpu = raw_smp_processor_id(); 652 BREAK_INSTR_SIZE);
729 653 if (err)
730 if ((cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) 654 return err;
731#ifdef CONFIG_SMP 655 return bfin_probe_kernel_write((char *)addr, arch_kgdb_ops.gdb_bpt_instr,
732 || (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH)) 656 BREAK_INSTR_SIZE);
733#endif
734 ) {
735 /* access L1 instruction SRAM */
736 if (dma_memcpy(saved_instr, (void *)addr, BREAK_INSTR_SIZE)
737 == NULL)
738 return -EFAULT;
739
740 if (dma_memcpy((void *)addr, arch_kgdb_ops.gdb_bpt_instr,
741 BREAK_INSTR_SIZE) == NULL)
742 return -EFAULT;
743
744 return 0;
745 } else {
746 err = probe_kernel_read(saved_instr, (char *)addr,
747 BREAK_INSTR_SIZE);
748 if (err)
749 return err;
750
751 return probe_kernel_write((char *)addr,
752 arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE);
753 }
754} 657}
755 658
756int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle) 659int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
757{ 660{
758 if (IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) { 661 return bfin_probe_kernel_write((char *)addr, bundle, BREAK_INSTR_SIZE);
759 /* access L1 instruction SRAM */
760 if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL)
761 return -EFAULT;
762
763 return 0;
764 } else
765 return probe_kernel_write((char *)addr,
766 (char *)bundle, BREAK_INSTR_SIZE);
767} 662}
768 663
769int kgdb_arch_init(void) 664int kgdb_arch_init(void)
diff --git a/arch/blackfin/kernel/mcount.S b/arch/blackfin/kernel/mcount.S
deleted file mode 100644
index edcfb3865f46..000000000000
--- a/arch/blackfin/kernel/mcount.S
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * linux/arch/blackfin/mcount.S
3 *
4 * Copyright (C) 2006 Analog Devices Inc.
5 *
6 * 2007/04/12 Save index, length, modify and base registers. --rpm
7 */
8
9#include <linux/linkage.h>
10#include <asm/blackfin.h>
11
12.text
13
14.align 4 /* just in case */
15
16ENTRY(__mcount)
17 [--sp] = i0;
18 [--sp] = i1;
19 [--sp] = i2;
20 [--sp] = i3;
21 [--sp] = l0;
22 [--sp] = l1;
23 [--sp] = l2;
24 [--sp] = l3;
25 [--sp] = m0;
26 [--sp] = m1;
27 [--sp] = m2;
28 [--sp] = m3;
29 [--sp] = b0;
30 [--sp] = b1;
31 [--sp] = b2;
32 [--sp] = b3;
33 [--sp] = ( r7:0, p5:0 );
34 [--sp] = ASTAT;
35
36 p1.L = _ipipe_trace_enable;
37 p1.H = _ipipe_trace_enable;
38 r7 = [p1];
39 CC = r7 == 0;
40 if CC jump out;
41 link 0x10;
42 r0 = 0x0;
43 [sp + 0xc] = r0; /* v */
44 r0 = 0x0; /* type: IPIPE_TRACE_FN */
45 r1 = rets;
46 p0 = [fp]; /* p0: Prior FP */
47 r2 = [p0 + 4]; /* r2: Prior RETS */
48 call ___ipipe_trace;
49 unlink;
50out:
51 ASTAT = [sp++];
52 ( r7:0, p5:0 ) = [sp++];
53 b3 = [sp++];
54 b2 = [sp++];
55 b1 = [sp++];
56 b0 = [sp++];
57 m3 = [sp++];
58 m2 = [sp++];
59 m1 = [sp++];
60 m0 = [sp++];
61 l3 = [sp++];
62 l2 = [sp++];
63 l1 = [sp++];
64 l0 = [sp++];
65 i3 = [sp++];
66 i2 = [sp++];
67 i1 = [sp++];
68 i0 = [sp++];
69 rts;
70ENDPROC(__mcount)
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 3e1d86e456f6..79cad0ac5892 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -344,6 +344,87 @@ void finish_atomic_sections (struct pt_regs *regs)
344 } 344 }
345} 345}
346 346
347static inline
348int in_mem(unsigned long addr, unsigned long size,
349 unsigned long start, unsigned long end)
350{
351 return addr >= start && addr + size <= end;
352}
353static inline
354int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
355 unsigned long const_addr, unsigned long const_size)
356{
357 return const_size &&
358 in_mem(addr, size, const_addr + off, const_addr + const_size);
359}
360static inline
361int in_mem_const(unsigned long addr, unsigned long size,
362 unsigned long const_addr, unsigned long const_size)
363{
364 return in_mem_const_off(addr, 0, size, const_addr, const_size);
365}
366#define IN_ASYNC(bnum, bctlnum) \
367({ \
368 (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \
369 bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \
370 BFIN_MEM_ACCESS_CORE; \
371})
372
373int bfin_mem_access_type(unsigned long addr, unsigned long size)
374{
375 int cpu = raw_smp_processor_id();
376
377 /* Check that things do not wrap around */
378 if (addr > ULONG_MAX - size)
379 return -EFAULT;
380
381 if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
382 return BFIN_MEM_ACCESS_CORE;
383
384 if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
385 return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
386 if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
387 return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
388 if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
389 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
390 if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
391 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
392#ifdef COREB_L1_CODE_START
393 if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
394 return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
395 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
396 return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
397 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
398 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
399 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
400 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
401#endif
402 if (in_mem_const(addr, size, L2_START, L2_LENGTH))
403 return BFIN_MEM_ACCESS_CORE;
404
405 if (addr >= SYSMMR_BASE)
406 return BFIN_MEM_ACCESS_CORE_ONLY;
407
408 /* We can't read EBIU banks that aren't enabled or we end up hanging
409 * on the access to the async space.
410 */
411 if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE))
412 return IN_ASYNC(0, 0);
413 if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE))
414 return IN_ASYNC(1, 0);
415 if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE))
416 return IN_ASYNC(2, 1);
417 if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE))
418 return IN_ASYNC(3, 1);
419
420 if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
421 return BFIN_MEM_ACCESS_CORE;
422 if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
423 return BFIN_MEM_ACCESS_DMA;
424
425 return -EFAULT;
426}
427
347#if defined(CONFIG_ACCESS_CHECK) 428#if defined(CONFIG_ACCESS_CHECK)
348#ifdef CONFIG_ACCESS_OK_L1 429#ifdef CONFIG_ACCESS_OK_L1
349__attribute__((l1_text)) 430__attribute__((l1_text))
@@ -353,51 +434,61 @@ int _access_ok(unsigned long addr, unsigned long size)
353{ 434{
354 if (size == 0) 435 if (size == 0)
355 return 1; 436 return 1;
356 if (addr > (addr + size)) 437 /* Check that things do not wrap around */
438 if (addr > ULONG_MAX - size)
357 return 0; 439 return 0;
358 if (segment_eq(get_fs(), KERNEL_DS)) 440 if (segment_eq(get_fs(), KERNEL_DS))
359 return 1; 441 return 1;
360#ifdef CONFIG_MTD_UCLINUX 442#ifdef CONFIG_MTD_UCLINUX
361 if (addr >= memory_start && (addr + size) <= memory_end) 443 if (1)
362 return 1; 444#else
363 if (addr >= memory_mtd_end && (addr + size) <= physical_mem_end) 445 if (0)
446#endif
447 {
448 if (in_mem(addr, size, memory_start, memory_end))
449 return 1;
450 if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
451 return 1;
452# ifndef CONFIG_ROMFS_ON_MTD
453 if (0)
454# endif
455 /* For XIP, allow user space to use pointers within the ROMFS. */
456 if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
457 return 1;
458 } else {
459 if (in_mem(addr, size, memory_start, physical_mem_end))
460 return 1;
461 }
462
463 if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
364 return 1; 464 return 1;
365 465
366#ifdef CONFIG_ROMFS_ON_MTD 466 if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
367 /* For XIP, allow user space to use pointers within the ROMFS. */
368 if (addr >= memory_mtd_start && (addr + size) <= memory_mtd_end)
369 return 1; 467 return 1;
370#endif 468 if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
371#else
372 if (addr >= memory_start && (addr + size) <= physical_mem_end)
373 return 1; 469 return 1;
374#endif 470 if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
375 if (addr >= (unsigned long)__init_begin &&
376 addr + size <= (unsigned long)__init_end)
377 return 1; 471 return 1;
378 if (addr >= get_l1_scratch_start() 472 if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
379 && addr + size <= get_l1_scratch_start() + L1_SCRATCH_LENGTH)
380 return 1; 473 return 1;
381#if L1_CODE_LENGTH != 0 474#ifdef COREB_L1_CODE_START
382 if (addr >= get_l1_code_start() + (_etext_l1 - _stext_l1) 475 if (in_mem_const(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
383 && addr + size <= get_l1_code_start() + L1_CODE_LENGTH)
384 return 1; 476 return 1;
385#endif 477 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
386#if L1_DATA_A_LENGTH != 0
387 if (addr >= get_l1_data_a_start() + (_ebss_l1 - _sdata_l1)
388 && addr + size <= get_l1_data_a_start() + L1_DATA_A_LENGTH)
389 return 1; 478 return 1;
390#endif 479 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
391#if L1_DATA_B_LENGTH != 0
392 if (addr >= get_l1_data_b_start() + (_ebss_b_l1 - _sdata_b_l1)
393 && addr + size <= get_l1_data_b_start() + L1_DATA_B_LENGTH)
394 return 1; 480 return 1;
395#endif 481 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
396#if L2_LENGTH != 0
397 if (addr >= L2_START + (_ebss_l2 - _stext_l2)
398 && addr + size <= L2_START + L2_LENGTH)
399 return 1; 482 return 1;
400#endif 483#endif
484 if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
485 return 1;
486
487 if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
488 return 1;
489 if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
490 return 1;
491
401 return 0; 492 return 0;
402} 493}
403EXPORT_SYMBOL(_access_ok); 494EXPORT_SYMBOL(_access_ok);
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 6454babdfaff..298f023bcc09 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -117,15 +117,49 @@ void __cpuinit bfin_setup_caches(unsigned int cpu)
117 */ 117 */
118#ifdef CONFIG_BFIN_ICACHE 118#ifdef CONFIG_BFIN_ICACHE
119 printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu); 119 printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
120 printk(KERN_INFO " External memory:"
121# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
122 " cacheable"
123# else
124 " uncacheable"
125# endif
126 " in instruction cache\n");
127 if (L2_LENGTH)
128 printk(KERN_INFO " L2 SRAM :"
129# ifdef CONFIG_BFIN_L2_ICACHEABLE
130 " cacheable"
131# else
132 " uncacheable"
133# endif
134 " in instruction cache\n");
135
136#else
137 printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
120#endif 138#endif
139
121#ifdef CONFIG_BFIN_DCACHE 140#ifdef CONFIG_BFIN_DCACHE
122 printk(KERN_INFO "Data Cache Enabled for CPU%u" 141 printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
123# if defined CONFIG_BFIN_WB 142 printk(KERN_INFO " External memory:"
124 " (write-back)" 143# if defined CONFIG_BFIN_EXTMEM_WRITEBACK
125# elif defined CONFIG_BFIN_WT 144 " cacheable (write-back)"
126 " (write-through)" 145# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
146 " cacheable (write-through)"
147# else
148 " uncacheable"
127# endif 149# endif
128 "\n", cpu); 150 " in data cache\n");
151 if (L2_LENGTH)
152 printk(KERN_INFO " L2 SRAM :"
153# if defined CONFIG_BFIN_L2_WRITEBACK
154 " cacheable (write-back)"
155# elif defined CONFIG_BFIN_L2_WRITETHROUGH
156 " cacheable (write-through)"
157# else
158 " uncacheable"
159# endif
160 " in data cache\n");
161#else
162 printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
129#endif 163#endif
130} 164}
131 165
@@ -443,9 +477,11 @@ static __init void parse_cmdline_early(char *cmdline_p)
443 } else if (!memcmp(to, "clkin_hz=", 9)) { 477 } else if (!memcmp(to, "clkin_hz=", 9)) {
444 to += 9; 478 to += 9;
445 early_init_clkin_hz(to); 479 early_init_clkin_hz(to);
480#ifdef CONFIG_EARLY_PRINTK
446 } else if (!memcmp(to, "earlyprintk=", 12)) { 481 } else if (!memcmp(to, "earlyprintk=", 12)) {
447 to += 12; 482 to += 12;
448 setup_early_printk(to); 483 setup_early_printk(to);
484#endif
449 } else if (!memcmp(to, "memmap=", 7)) { 485 } else if (!memcmp(to, "memmap=", 7)) {
450 to += 7; 486 to += 7;
451 parse_memmap(to); 487 parse_memmap(to);
@@ -516,7 +552,7 @@ static __init void memory_setup(void)
516 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) 552 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
517 mtd_size = 553 mtd_size =
518 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2])); 554 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
519# if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) 555# if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
520 /* Due to a Hardware Anomaly we need to limit the size of usable 556 /* Due to a Hardware Anomaly we need to limit the size of usable
521 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on 557 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
522 * 05000263 - Hardware loop corrupted when taking an ICPLB exception 558 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
@@ -544,7 +580,7 @@ static __init void memory_setup(void)
544 dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size); 580 dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
545#endif /* CONFIG_MTD_UCLINUX */ 581#endif /* CONFIG_MTD_UCLINUX */
546 582
547#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) 583#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
548 /* Due to a Hardware Anomaly we need to limit the size of usable 584 /* Due to a Hardware Anomaly we need to limit the size of usable
549 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on 585 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
550 * 05000263 - Hardware loop corrupted when taking an ICPLB exception 586 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
@@ -764,6 +800,11 @@ void __init setup_arch(char **cmdline_p)
764{ 800{
765 unsigned long sclk, cclk; 801 unsigned long sclk, cclk;
766 802
803 /* Check to make sure we are running on the right processor */
804 if (unlikely(CPUID != bfin_cpuid()))
805 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
806 CPU, bfin_cpuid(), bfin_revid());
807
767#ifdef CONFIG_DUMMY_CONSOLE 808#ifdef CONFIG_DUMMY_CONSOLE
768 conswitchp = &dummy_con; 809 conswitchp = &dummy_con;
769#endif 810#endif
@@ -778,14 +819,17 @@ void __init setup_arch(char **cmdline_p)
778 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); 819 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
779 boot_command_line[COMMAND_LINE_SIZE - 1] = '\0'; 820 boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
780 821
781 /* setup memory defaults from the user config */
782 physical_mem_end = 0;
783 _ramend = get_mem_size() * 1024 * 1024;
784
785 memset(&bfin_memmap, 0, sizeof(bfin_memmap)); 822 memset(&bfin_memmap, 0, sizeof(bfin_memmap));
786 823
824 /* If the user does not specify things on the command line, use
825 * what the bootloader set things up as
826 */
827 physical_mem_end = 0;
787 parse_cmdline_early(&command_line[0]); 828 parse_cmdline_early(&command_line[0]);
788 829
830 if (_ramend == 0)
831 _ramend = get_mem_size() * 1024 * 1024;
832
789 if (physical_mem_end == 0) 833 if (physical_mem_end == 0)
790 physical_mem_end = _ramend; 834 physical_mem_end = _ramend;
791 835
@@ -837,7 +881,8 @@ void __init setup_arch(char **cmdline_p)
837 defined(CONFIG_BF538) || defined(CONFIG_BF539) 881 defined(CONFIG_BF538) || defined(CONFIG_BF539)
838 _bfin_swrst = bfin_read_SWRST(); 882 _bfin_swrst = bfin_read_SWRST();
839#else 883#else
840 _bfin_swrst = bfin_read_SYSCR(); 884 /* Clear boot mode field */
885 _bfin_swrst = bfin_read_SYSCR() & ~0xf;
841#endif 886#endif
842 887
843#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT 888#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
@@ -875,10 +920,7 @@ void __init setup_arch(char **cmdline_p)
875 else 920 else
876 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid()); 921 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
877 922
878 if (unlikely(CPUID != bfin_cpuid())) 923 if (likely(CPUID == bfin_cpuid())) {
879 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
880 CPU, bfin_cpuid(), bfin_revid());
881 else {
882 if (bfin_revid() != bfin_compiled_revid()) { 924 if (bfin_revid() != bfin_compiled_revid()) {
883 if (bfin_compiled_revid() == -1) 925 if (bfin_compiled_revid() == -1)
884 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n", 926 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
@@ -1157,16 +1199,25 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1157 icache_size = 0; 1199 icache_size = 0;
1158 1200
1159 seq_printf(m, "cache size\t: %d KB(L1 icache) " 1201 seq_printf(m, "cache size\t: %d KB(L1 icache) "
1160 "%d KB(L1 dcache%s) %d KB(L2 cache)\n", 1202 "%d KB(L1 dcache) %d KB(L2 cache)\n",
1161 icache_size, dcache_size, 1203 icache_size, dcache_size, 0);
1162#if defined CONFIG_BFIN_WB
1163 "-wb"
1164#elif defined CONFIG_BFIN_WT
1165 "-wt"
1166#endif
1167 "", 0);
1168
1169 seq_printf(m, "%s\n", cache); 1204 seq_printf(m, "%s\n", cache);
1205 seq_printf(m, "external memory\t: "
1206#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
1207 "cacheable"
1208#else
1209 "uncacheable"
1210#endif
1211 " in instruction cache\n");
1212 seq_printf(m, "external memory\t: "
1213#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
1214 "cacheable (write-back)"
1215#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
1216 "cacheable (write-through)"
1217#else
1218 "uncacheable"
1219#endif
1220 " in data cache\n");
1170 1221
1171 if (icache_size) 1222 if (icache_size)
1172 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n", 1223 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
@@ -1239,8 +1290,25 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1239 if (cpu_num != num_possible_cpus() - 1) 1290 if (cpu_num != num_possible_cpus() - 1)
1240 return 0; 1291 return 0;
1241 1292
1242 if (L2_LENGTH) 1293 if (L2_LENGTH) {
1243 seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400); 1294 seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
1295 seq_printf(m, "L2 SRAM\t\t: "
1296#if defined(CONFIG_BFIN_L2_ICACHEABLE)
1297 "cacheable"
1298#else
1299 "uncacheable"
1300#endif
1301 " in instruction cache\n");
1302 seq_printf(m, "L2 SRAM\t\t: "
1303#if defined(CONFIG_BFIN_L2_WRITEBACK)
1304 "cacheable (write-back)"
1305#elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
1306 "cacheable (write-through)"
1307#else
1308 "uncacheable"
1309#endif
1310 " in data cache\n");
1311 }
1244 seq_printf(m, "board name\t: %s\n", bfin_board_name); 1312 seq_printf(m, "board name\t: %s\n", bfin_board_name);
1245 seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n", 1313 seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
1246 physical_mem_end >> 10, (void *)0, (void *)physical_mem_end); 1314 physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index d279552fe9b0..8eeb457ce5d5 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -37,6 +37,7 @@
37#include <asm/traps.h> 37#include <asm/traps.h>
38#include <asm/cacheflush.h> 38#include <asm/cacheflush.h>
39#include <asm/cplb.h> 39#include <asm/cplb.h>
40#include <asm/dma.h>
40#include <asm/blackfin.h> 41#include <asm/blackfin.h>
41#include <asm/irq_handler.h> 42#include <asm/irq_handler.h>
42#include <linux/irq.h> 43#include <linux/irq.h>
@@ -636,57 +637,30 @@ asmlinkage void trap_c(struct pt_regs *fp)
636 */ 637 */
637static bool get_instruction(unsigned short *val, unsigned short *address) 638static bool get_instruction(unsigned short *val, unsigned short *address)
638{ 639{
639 640 unsigned long addr = (unsigned long)address;
640 unsigned long addr;
641
642 addr = (unsigned long)address;
643 641
644 /* Check for odd addresses */ 642 /* Check for odd addresses */
645 if (addr & 0x1) 643 if (addr & 0x1)
646 return false; 644 return false;
647 645
648 /* Check that things do not wrap around */ 646 /* MMR region will never have instructions */
649 if (addr > (addr + 2)) 647 if (addr >= SYSMMR_BASE)
650 return false; 648 return false;
651 649
652 /* 650 switch (bfin_mem_access_type(addr, 2)) {
653 * Since we are in exception context, we need to do a little address checking 651 case BFIN_MEM_ACCESS_CORE:
654 * We need to make sure we are only accessing valid memory, and 652 case BFIN_MEM_ACCESS_CORE_ONLY:
655 * we don't read something in the async space that can hang forever 653 *val = *address;
656 */ 654 return true;
657 if ((addr >= FIXED_CODE_START && (addr + 2) <= physical_mem_end) || 655 case BFIN_MEM_ACCESS_DMA:
658#if L2_LENGTH != 0 656 dma_memcpy(val, address, 2);
659 (addr >= L2_START && (addr + 2) <= (L2_START + L2_LENGTH)) || 657 return true;
660#endif 658 case BFIN_MEM_ACCESS_ITEST:
661 (addr >= BOOT_ROM_START && (addr + 2) <= (BOOT_ROM_START + BOOT_ROM_LENGTH)) || 659 isram_memcpy(val, address, 2);
662#if L1_DATA_A_LENGTH != 0 660 return true;
663 (addr >= L1_DATA_A_START && (addr + 2) <= (L1_DATA_A_START + L1_DATA_A_LENGTH)) || 661 default: /* invalid access */
664#endif 662 return false;
665#if L1_DATA_B_LENGTH != 0
666 (addr >= L1_DATA_B_START && (addr + 2) <= (L1_DATA_B_START + L1_DATA_B_LENGTH)) ||
667#endif
668 (addr >= L1_SCRATCH_START && (addr + 2) <= (L1_SCRATCH_START + L1_SCRATCH_LENGTH)) ||
669 (!(bfin_read_EBIU_AMBCTL0() & B0RDYEN) &&
670 addr >= ASYNC_BANK0_BASE && (addr + 2) <= (ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)) ||
671 (!(bfin_read_EBIU_AMBCTL0() & B1RDYEN) &&
672 addr >= ASYNC_BANK1_BASE && (addr + 2) <= (ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)) ||
673 (!(bfin_read_EBIU_AMBCTL1() & B2RDYEN) &&
674 addr >= ASYNC_BANK2_BASE && (addr + 2) <= (ASYNC_BANK2_BASE + ASYNC_BANK1_SIZE)) ||
675 (!(bfin_read_EBIU_AMBCTL1() & B3RDYEN) &&
676 addr >= ASYNC_BANK3_BASE && (addr + 2) <= (ASYNC_BANK3_BASE + ASYNC_BANK1_SIZE))) {
677 *val = *address;
678 return true;
679 } 663 }
680
681#if L1_CODE_LENGTH != 0
682 if (addr >= L1_CODE_START && (addr + 2) <= (L1_CODE_START + L1_CODE_LENGTH)) {
683 isram_memcpy(val, address, 2);
684 return true;
685 }
686#endif
687
688
689 return false;
690} 664}
691 665
692/* 666/*
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index 1382f0382359..d9791106be9f 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -119,13 +119,19 @@ static struct platform_device bfin_mac_device = {
119}; 119};
120 120
121#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 121#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
122static struct dsa_platform_data ksz8893m_switch_data = { 122static struct dsa_chip_data ksz8893m_switch_chip_data = {
123 .mii_bus = &bfin_mii_bus.dev, 123 .mii_bus = &bfin_mii_bus.dev,
124 .port_names = {
125 NULL,
126 "eth%d",
127 "eth%d",
128 "cpu",
129 },
130};
131static struct dsa_platform_data ksz8893m_switch_data = {
132 .nr_chips = 1,
124 .netdev = &bfin_mac_device.dev, 133 .netdev = &bfin_mac_device.dev,
125 .port_names[0] = NULL, 134 .chip = &ksz8893m_switch_chip_data,
126 .port_names[1] = "eth%d",
127 .port_names[2] = "eth%d",
128 .port_names[3] = "cpu",
129}; 135};
130 136
131static struct platform_device ksz8893m_switch_device = { 137static struct platform_device ksz8893m_switch_device = {
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index b69bd9af38dd..426e064062a0 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file should be up to date with: 9/* This file should be up to date with:
10 * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List 10 * - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ 13/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
@@ -18,7 +18,7 @@
18#ifndef _MACH_ANOMALY_H_ 18#ifndef _MACH_ANOMALY_H_
19#define _MACH_ANOMALY_H_ 19#define _MACH_ANOMALY_H_
20 20
21/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ 21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
22#define ANOMALY_05000074 (1) 22#define ANOMALY_05000074 (1)
23/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 23/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
24#define ANOMALY_05000122 (1) 24#define ANOMALY_05000122 (1)
@@ -45,29 +45,31 @@
45/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ 45/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
46#define ANOMALY_05000426 (1) 46#define ANOMALY_05000426 (1)
47/* Software System Reset Corrupts PLL_LOCKCNT Register */ 47/* Software System Reset Corrupts PLL_LOCKCNT Register */
48#define ANOMALY_05000430 (1) 48#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
49/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ 49/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
50#define ANOMALY_05000431 (1) 50#define ANOMALY_05000431 (1)
51/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ 51/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
52#define ANOMALY_05000435 (1) 52#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
53/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ 53/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
54#define ANOMALY_05000438 (1) 54#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
55/* Preboot Cannot be Used to Alter the PLL_DIV Register */ 55/* Preboot Cannot be Used to Alter the PLL_DIV Register */
56#define ANOMALY_05000439 (1) 56#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
57/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ 57/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
58#define ANOMALY_05000440 (1) 58#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
59/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 59/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
60#define ANOMALY_05000443 (1) 60#define ANOMALY_05000443 (1)
61/* Incorrect L1 Instruction Bank B Memory Map Location */ 61/* Incorrect L1 Instruction Bank B Memory Map Location */
62#define ANOMALY_05000444 (1) 62#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
63/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ 63/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
64#define ANOMALY_05000452 (1) 64#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
65/* PWM_TRIPB Signal Not Available on PG10 */ 65/* PWM_TRIPB Signal Not Available on PG10 */
66#define ANOMALY_05000453 (1) 66#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
67/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ 67/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
68#define ANOMALY_05000455 (1) 68#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
69/* False Hardware Error when RETI points to invalid memory */ 69/* False Hardware Error when RETI Points to Invalid Memory */
70#define ANOMALY_05000461 (1) 70#define ANOMALY_05000461 (1)
71/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
72#define ANOMALY_05000462 (1)
71 73
72/* Anomalies that don't exist on this proc */ 74/* Anomalies that don't exist on this proc */
73#define ANOMALY_05000099 (0) 75#define ANOMALY_05000099 (0)
@@ -78,24 +80,30 @@
78#define ANOMALY_05000158 (0) 80#define ANOMALY_05000158 (0)
79#define ANOMALY_05000171 (0) 81#define ANOMALY_05000171 (0)
80#define ANOMALY_05000179 (0) 82#define ANOMALY_05000179 (0)
83#define ANOMALY_05000182 (0)
81#define ANOMALY_05000183 (0) 84#define ANOMALY_05000183 (0)
82#define ANOMALY_05000198 (0) 85#define ANOMALY_05000198 (0)
86#define ANOMALY_05000202 (0)
83#define ANOMALY_05000215 (0) 87#define ANOMALY_05000215 (0)
84#define ANOMALY_05000220 (0) 88#define ANOMALY_05000220 (0)
85#define ANOMALY_05000227 (0) 89#define ANOMALY_05000227 (0)
86#define ANOMALY_05000230 (0) 90#define ANOMALY_05000230 (0)
87#define ANOMALY_05000231 (0) 91#define ANOMALY_05000231 (0)
88#define ANOMALY_05000233 (0) 92#define ANOMALY_05000233 (0)
93#define ANOMALY_05000234 (0)
89#define ANOMALY_05000242 (0) 94#define ANOMALY_05000242 (0)
90#define ANOMALY_05000244 (0) 95#define ANOMALY_05000244 (0)
91#define ANOMALY_05000248 (0) 96#define ANOMALY_05000248 (0)
92#define ANOMALY_05000250 (0) 97#define ANOMALY_05000250 (0)
98#define ANOMALY_05000257 (0)
93#define ANOMALY_05000261 (0) 99#define ANOMALY_05000261 (0)
94#define ANOMALY_05000263 (0) 100#define ANOMALY_05000263 (0)
95#define ANOMALY_05000266 (0) 101#define ANOMALY_05000266 (0)
96#define ANOMALY_05000273 (0) 102#define ANOMALY_05000273 (0)
97#define ANOMALY_05000274 (0) 103#define ANOMALY_05000274 (0)
98#define ANOMALY_05000278 (0) 104#define ANOMALY_05000278 (0)
105#define ANOMALY_05000281 (0)
106#define ANOMALY_05000283 (0)
99#define ANOMALY_05000285 (0) 107#define ANOMALY_05000285 (0)
100#define ANOMALY_05000287 (0) 108#define ANOMALY_05000287 (0)
101#define ANOMALY_05000301 (0) 109#define ANOMALY_05000301 (0)
@@ -103,10 +111,13 @@
103#define ANOMALY_05000307 (0) 111#define ANOMALY_05000307 (0)
104#define ANOMALY_05000311 (0) 112#define ANOMALY_05000311 (0)
105#define ANOMALY_05000312 (0) 113#define ANOMALY_05000312 (0)
114#define ANOMALY_05000315 (0)
106#define ANOMALY_05000323 (0) 115#define ANOMALY_05000323 (0)
107#define ANOMALY_05000353 (0) 116#define ANOMALY_05000353 (0)
117#define ANOMALY_05000357 (0)
108#define ANOMALY_05000362 (1) 118#define ANOMALY_05000362 (1)
109#define ANOMALY_05000363 (0) 119#define ANOMALY_05000363 (0)
120#define ANOMALY_05000371 (0)
110#define ANOMALY_05000380 (0) 121#define ANOMALY_05000380 (0)
111#define ANOMALY_05000386 (0) 122#define ANOMALY_05000386 (0)
112#define ANOMALY_05000389 (0) 123#define ANOMALY_05000389 (0)
@@ -117,5 +128,7 @@
117#define ANOMALY_05000448 (0) 128#define ANOMALY_05000448 (0)
118#define ANOMALY_05000456 (0) 129#define ANOMALY_05000456 (0)
119#define ANOMALY_05000450 (0) 130#define ANOMALY_05000450 (0)
131#define ANOMALY_05000465 (0)
132#define ANOMALY_05000467 (0)
120 133
121#endif 134#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
index 267bb7c8bfb5..e8e14c2769ed 100644
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -33,7 +33,6 @@
33#define _MACH_BLACKFIN_H_ 33#define _MACH_BLACKFIN_H_
34 34
35#include "bf518.h" 35#include "bf518.h"
36#include "mem_map.h"
37#include "defBF512.h" 36#include "defBF512.h"
38#include "anomaly.h" 37#include "anomaly.h"
39 38
diff --git a/arch/blackfin/mach-bf518/include/mach/mem_map.h b/arch/blackfin/mach-bf518/include/mach/mem_map.h
index 62bcc781bfaa..3c6777cb3532 100644
--- a/arch/blackfin/mach-bf518/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf518/include/mach/mem_map.h
@@ -1,38 +1,16 @@
1/* 1/*
2 * file: include/asm-blackfin/mach-bf518/mem_map.h 2 * BF51x memory map
3 * based on: include/asm-blackfin/mach-bf527/mem_map.h
4 * author: Bryan Wu <cooloney@kernel.org>
5 * 3 *
6 * created: 4 * Copyright 2004-2009 Analog Devices Inc.
7 * description: 5 * Licensed under the GPL-2 or later.
8 * Memory MAP Common header file for blackfin BF518/6/4/2 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */ 6 */
30 7
31#ifndef _MEM_MAP_518_H_ 8#ifndef __BFIN_MACH_MEM_MAP_H__
32#define _MEM_MAP_518_H_ 9#define __BFIN_MACH_MEM_MAP_H__
33 10
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ 11#ifndef __BFIN_MEM_MAP_H__
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ 12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13#endif
36 14
37/* Async Memory Banks */ 15/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ 16#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
@@ -89,20 +67,4 @@
89#define BFIN_DSUPBANKS 0 67#define BFIN_DSUPBANKS 0
90#endif /*CONFIG_BFIN_DCACHE */ 68#endif /*CONFIG_BFIN_DCACHE */
91 69
92/* Level 2 Memory - none */ 70#endif
93
94#define L2_START 0
95#define L2_LENGTH 0
96
97/* Scratch Pad Memory */
98
99#define L1_SCRATCH_START 0xFFB00000
100#define L1_SCRATCH_LENGTH 0x1000
101
102#define GET_PDA_SAFE(preg) \
103 preg.l = _cpu_pda; \
104 preg.h = _cpu_pda;
105
106#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
107
108#endif /* _MEM_MAP_518_H_ */
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 1eaf27ff722e..f4867ce0c618 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -78,7 +78,6 @@ static struct resource bfin_isp1760_resources[] = {
78 78
79static struct isp1760_platform_data isp1760_priv = { 79static struct isp1760_platform_data isp1760_priv = {
80 .is_isp1761 = 0, 80 .is_isp1761 = 0,
81 .port1_disable = 0,
82 .bus_width_16 = 1, 81 .bus_width_16 = 1,
83 .port1_otg = 0, 82 .port1_otg = 0,
84 .analog_oc = 0, 83 .analog_oc = 0,
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 9f9c0005dcf1..b2f30f06b73e 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -237,10 +237,10 @@ static struct flash_platform_data bfin_spi_flash_data = {
237 .name = "m25p80", 237 .name = "m25p80",
238 .parts = bfin_spi_flash_partitions, 238 .parts = bfin_spi_flash_partitions,
239 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), 239 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
240 .type = "m25p16", 240 .type = "sst25wf040",
241}; 241};
242 242
243/* SPI flash chip (m25p64) */ 243/* SPI flash chip (sst25wf040) */
244static struct bfin5xx_spi_chip spi_flash_chip_info = { 244static struct bfin5xx_spi_chip spi_flash_chip_info = {
245 .enable_dma = 0, /* use dma transfer with this chip*/ 245 .enable_dma = 0, /* use dma transfer with this chip*/
246 .bits_per_word = 8, 246 .bits_per_word = 8,
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 3e5b7db6b065..799a1d1fa890 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -77,7 +77,6 @@ static struct resource bfin_isp1760_resources[] = {
77 77
78static struct isp1760_platform_data isp1760_priv = { 78static struct isp1760_platform_data isp1760_priv = {
79 .is_isp1761 = 0, 79 .is_isp1761 = 0,
80 .port1_disable = 0,
81 .bus_width_16 = 1, 80 .bus_width_16 = 1,
82 .port1_otg = 0, 81 .port1_otg = 0,
83 .analog_oc = 0, 82 .analog_oc = 0,
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index c84ddea95749..0d63f7406168 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -34,7 +34,7 @@
34#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527) 34#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
35#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527)) 35#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
36 36
37/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ 37/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
38#define ANOMALY_05000074 (1) 38#define ANOMALY_05000074 (1)
39/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 39/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
40#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ 40#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
@@ -184,8 +184,12 @@
184#define ANOMALY_05000456 (1) 184#define ANOMALY_05000456 (1)
185/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ 185/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
186#define ANOMALY_05000457 (1) 186#define ANOMALY_05000457 (1)
187/* False Hardware Error when RETI points to invalid memory */ 187/* False Hardware Error when RETI Points to Invalid Memory */
188#define ANOMALY_05000461 (1) 188#define ANOMALY_05000461 (1)
189/* USB Rx DMA hang */
190#define ANOMALY_05000465 (1)
191/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
192#define ANOMALY_05000467 (1)
189 193
190/* Anomalies that don't exist on this proc */ 194/* Anomalies that don't exist on this proc */
191#define ANOMALY_05000099 (0) 195#define ANOMALY_05000099 (0)
@@ -195,24 +199,30 @@
195#define ANOMALY_05000158 (0) 199#define ANOMALY_05000158 (0)
196#define ANOMALY_05000171 (0) 200#define ANOMALY_05000171 (0)
197#define ANOMALY_05000179 (0) 201#define ANOMALY_05000179 (0)
202#define ANOMALY_05000182 (0)
198#define ANOMALY_05000183 (0) 203#define ANOMALY_05000183 (0)
199#define ANOMALY_05000198 (0) 204#define ANOMALY_05000198 (0)
205#define ANOMALY_05000202 (0)
200#define ANOMALY_05000215 (0) 206#define ANOMALY_05000215 (0)
201#define ANOMALY_05000220 (0) 207#define ANOMALY_05000220 (0)
202#define ANOMALY_05000227 (0) 208#define ANOMALY_05000227 (0)
203#define ANOMALY_05000230 (0) 209#define ANOMALY_05000230 (0)
204#define ANOMALY_05000231 (0) 210#define ANOMALY_05000231 (0)
205#define ANOMALY_05000233 (0) 211#define ANOMALY_05000233 (0)
212#define ANOMALY_05000234 (0)
206#define ANOMALY_05000242 (0) 213#define ANOMALY_05000242 (0)
207#define ANOMALY_05000244 (0) 214#define ANOMALY_05000244 (0)
208#define ANOMALY_05000248 (0) 215#define ANOMALY_05000248 (0)
209#define ANOMALY_05000250 (0) 216#define ANOMALY_05000250 (0)
217#define ANOMALY_05000257 (0)
210#define ANOMALY_05000261 (0) 218#define ANOMALY_05000261 (0)
211#define ANOMALY_05000263 (0) 219#define ANOMALY_05000263 (0)
212#define ANOMALY_05000266 (0) 220#define ANOMALY_05000266 (0)
213#define ANOMALY_05000273 (0) 221#define ANOMALY_05000273 (0)
214#define ANOMALY_05000274 (0) 222#define ANOMALY_05000274 (0)
215#define ANOMALY_05000278 (0) 223#define ANOMALY_05000278 (0)
224#define ANOMALY_05000281 (0)
225#define ANOMALY_05000283 (0)
216#define ANOMALY_05000285 (0) 226#define ANOMALY_05000285 (0)
217#define ANOMALY_05000287 (0) 227#define ANOMALY_05000287 (0)
218#define ANOMALY_05000301 (0) 228#define ANOMALY_05000301 (0)
@@ -220,6 +230,7 @@
220#define ANOMALY_05000307 (0) 230#define ANOMALY_05000307 (0)
221#define ANOMALY_05000311 (0) 231#define ANOMALY_05000311 (0)
222#define ANOMALY_05000312 (0) 232#define ANOMALY_05000312 (0)
233#define ANOMALY_05000315 (0)
223#define ANOMALY_05000323 (0) 234#define ANOMALY_05000323 (0)
224#define ANOMALY_05000362 (1) 235#define ANOMALY_05000362 (1)
225#define ANOMALY_05000363 (0) 236#define ANOMALY_05000363 (0)
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
index 417abcd61f4d..03665a8e16be 100644
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -33,7 +33,6 @@
33#define _MACH_BLACKFIN_H_ 33#define _MACH_BLACKFIN_H_
34 34
35#include "bf527.h" 35#include "bf527.h"
36#include "mem_map.h"
37#include "defBF522.h" 36#include "defBF522.h"
38#include "anomaly.h" 37#include "anomaly.h"
39 38
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h
index 019e0017ad81..d96e894afd2c 100644
--- a/arch/blackfin/mach-bf527/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf527/include/mach/mem_map.h
@@ -1,38 +1,16 @@
1/* 1/*
2 * file: include/asm-blackfin/mach-bf527/mem_map.h 2 * BF52x memory map
3 * based on: include/asm-blackfin/mach-bf537/mem_map.h
4 * author: Michael Hennerich (michael.hennerich@analog.com)
5 * 3 *
6 * created: 4 * Copyright 2004-2009 Analog Devices Inc.
7 * description: 5 * Licensed under the GPL-2 or later.
8 * Memory MAP Common header file for blackfin BF527/5/2 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */ 6 */
30 7
31#ifndef _MEM_MAP_527_H_ 8#ifndef __BFIN_MACH_MEM_MAP_H__
32#define _MEM_MAP_527_H_ 9#define __BFIN_MACH_MEM_MAP_H__
33 10
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ 11#ifndef __BFIN_MEM_MAP_H__
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ 12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13#endif
36 14
37/* Async Memory Banks */ 15/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ 16#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
@@ -89,20 +67,4 @@
89#define BFIN_DSUPBANKS 0 67#define BFIN_DSUPBANKS 0
90#endif /*CONFIG_BFIN_DCACHE */ 68#endif /*CONFIG_BFIN_DCACHE */
91 69
92/* Level 2 Memory - none */ 70#endif
93
94#define L2_START 0
95#define L2_LENGTH 0
96
97/* Scratch Pad Memory */
98
99#define L1_SCRATCH_START 0xFFB00000
100#define L1_SCRATCH_LENGTH 0x1000
101
102#define GET_PDA_SAFE(preg) \
103 preg.l = _cpu_pda; \
104 preg.h = _cpu_pda;
105
106#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
107
108#endif /* _MEM_MAP_527_H_ */
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 89a5ec4ca048..4e3e511bf146 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -32,6 +32,7 @@
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h> 33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h> 34#include <linux/mtd/partitions.h>
35#include <linux/mtd/plat-ram.h>
35#include <linux/spi/spi.h> 36#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 37#include <linux/spi/flash.h>
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 38#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
@@ -86,6 +87,101 @@ static struct platform_device smc91x_device = {
86}; 87};
87#endif 88#endif
88 89
90#if defined(CONFIG_MTD_PSD4256G) || defined(CONFIG_MTD_PSD4256G_MODULE)
91static const char *map_probes[] = {
92 "stm_flash",
93 NULL,
94};
95
96static struct platdata_mtd_ram stm_pri_data_a = {
97 .mapname = "Flash A Primary",
98 .map_probes = map_probes,
99 .bankwidth = 2,
100};
101
102static struct resource stm_pri_resource_a = {
103 .start = 0x20000000,
104 .end = 0x200fffff,
105 .flags = IORESOURCE_MEM,
106};
107
108static struct platform_device stm_pri_device_a = {
109 .name = "mtd-ram",
110 .id = 0,
111 .dev = {
112 .platform_data = &stm_pri_data_a,
113 },
114 .num_resources = 1,
115 .resource = &stm_pri_resource_a,
116};
117
118static struct platdata_mtd_ram stm_pri_data_b = {
119 .mapname = "Flash B Primary",
120 .map_probes = map_probes,
121 .bankwidth = 2,
122};
123
124static struct resource stm_pri_resource_b = {
125 .start = 0x20100000,
126 .end = 0x201fffff,
127 .flags = IORESOURCE_MEM,
128};
129
130static struct platform_device stm_pri_device_b = {
131 .name = "mtd-ram",
132 .id = 4,
133 .dev = {
134 .platform_data = &stm_pri_data_b,
135 },
136 .num_resources = 1,
137 .resource = &stm_pri_resource_b,
138};
139#endif
140
141#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
142static struct platdata_mtd_ram sram_data_a = {
143 .mapname = "Flash A SRAM",
144 .bankwidth = 2,
145};
146
147static struct resource sram_resource_a = {
148 .start = 0x20240000,
149 .end = 0x2024ffff,
150 .flags = IORESOURCE_MEM,
151};
152
153static struct platform_device sram_device_a = {
154 .name = "mtd-ram",
155 .id = 8,
156 .dev = {
157 .platform_data = &sram_data_a,
158 },
159 .num_resources = 1,
160 .resource = &sram_resource_a,
161};
162
163static struct platdata_mtd_ram sram_data_b = {
164 .mapname = "Flash B SRAM",
165 .bankwidth = 2,
166};
167
168static struct resource sram_resource_b = {
169 .start = 0x202c0000,
170 .end = 0x202cffff,
171 .flags = IORESOURCE_MEM,
172};
173
174static struct platform_device sram_device_b = {
175 .name = "mtd-ram",
176 .id = 9,
177 .dev = {
178 .platform_data = &sram_data_b,
179 },
180 .num_resources = 1,
181 .resource = &sram_resource_b,
182};
183#endif
184
89#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) 185#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
90static struct mtd_partition bfin_spi_flash_partitions[] = { 186static struct mtd_partition bfin_spi_flash_partitions[] = {
91 { 187 {
@@ -357,6 +453,16 @@ static struct platform_device *ezkit_devices[] __initdata = {
357 453
358 &bfin_dpmc, 454 &bfin_dpmc,
359 455
456#if defined(CONFIG_MTD_PSD4256G) || defined(CONFIG_MTD_PSD4256G_MODULE)
457 &stm_pri_device_a,
458 &stm_pri_device_b,
459#endif
460
461#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
462 &sram_device_a,
463 &sram_device_b,
464#endif
465
360#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 466#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
361 &smc91x_device, 467 &smc91x_device,
362#endif 468#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 31145b509e20..70a0ad69c610 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -34,7 +34,7 @@
34# define ANOMALY_BF533 0 34# define ANOMALY_BF533 0
35#endif 35#endif
36 36
37/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ 37/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
38#define ANOMALY_05000074 (1) 38#define ANOMALY_05000074 (1)
39/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ 39/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
40#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) 40#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
@@ -46,7 +46,7 @@
46#define ANOMALY_05000122 (1) 46#define ANOMALY_05000122 (1)
47/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */ 47/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
48#define ANOMALY_05000158 (__SILICON_REVISION__ < 5) 48#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
49/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ 49/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
50#define ANOMALY_05000166 (1) 50#define ANOMALY_05000166 (1)
51/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ 51/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
52#define ANOMALY_05000167 (1) 52#define ANOMALY_05000167 (1)
@@ -56,13 +56,13 @@
56#define ANOMALY_05000180 (1) 56#define ANOMALY_05000180 (1)
57/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ 57/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
58#define ANOMALY_05000183 (__SILICON_REVISION__ < 4) 58#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
59/* False Protection Exceptions */ 59/* False Protection Exceptions when Speculative Fetch Is Cancelled */
60#define ANOMALY_05000189 (__SILICON_REVISION__ < 4) 60#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
61/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ 61/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
62#define ANOMALY_05000193 (__SILICON_REVISION__ < 4) 62#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
63/* Restarting SPORT in Specific Modes May Cause Data Corruption */ 63/* Restarting SPORT in Specific Modes May Cause Data Corruption */
64#define ANOMALY_05000194 (__SILICON_REVISION__ < 4) 64#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
65/* Failing MMR Accesses When Stalled by Preceding Memory Read */ 65/* Failing MMR Accesses when Preceding Memory Read Stalls */
66#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) 66#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
67/* Current DMA Address Shows Wrong Value During Carry Fix */ 67/* Current DMA Address Shows Wrong Value During Carry Fix */
68#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) 68#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
@@ -74,7 +74,7 @@
74#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) 74#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
75/* Specific Sequence That Can Cause DMA Error or DMA Stopping */ 75/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
76#define ANOMALY_05000203 (__SILICON_REVISION__ < 4) 76#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
77/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ 77/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
78#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533) 78#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
79/* Recovery from "Brown-Out" Condition */ 79/* Recovery from "Brown-Out" Condition */
80#define ANOMALY_05000207 (__SILICON_REVISION__ < 4) 80#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
@@ -106,7 +106,7 @@
106#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) 106#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
107/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 107/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
108#define ANOMALY_05000245 (1) 108#define ANOMALY_05000245 (1)
109/* Data CPLBs Should Prevent Spurious Hardware Errors */ 109/* Data CPLBs Should Prevent False Hardware Errors */
110#define ANOMALY_05000246 (__SILICON_REVISION__ < 5) 110#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
111/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ 111/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
112#define ANOMALY_05000250 (__SILICON_REVISION__ == 4) 112#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
@@ -148,21 +148,21 @@
148#define ANOMALY_05000277 (__SILICON_REVISION__ < 6) 148#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
149/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 149/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
150#define ANOMALY_05000278 (__SILICON_REVISION__ < 6) 150#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
151/* False Hardware Error Exception When ISR Context Is Not Restored */ 151/* False Hardware Error Exception when ISR Context Is Not Restored */
152#define ANOMALY_05000281 (__SILICON_REVISION__ < 6) 152#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
153/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 153/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
154#define ANOMALY_05000282 (__SILICON_REVISION__ < 6) 154#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
155/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ 155/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
156#define ANOMALY_05000283 (__SILICON_REVISION__ < 6) 156#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
157/* SPORTs May Receive Bad Data If FIFOs Fill Up */ 157/* SPORTs May Receive Bad Data If FIFOs Fill Up */
158#define ANOMALY_05000288 (__SILICON_REVISION__ < 6) 158#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
159/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ 159/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) 160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 161/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) 162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
163/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ 163/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ 165/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
167/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 167/* SCKELOW Bit Does Not Maintain State Through Hibernate */
168#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ 168#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
@@ -170,11 +170,11 @@
170#define ANOMALY_05000310 (1) 170#define ANOMALY_05000310 (1)
171/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ 171/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
172#define ANOMALY_05000311 (__SILICON_REVISION__ < 6) 172#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
173/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 173/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
174#define ANOMALY_05000312 (__SILICON_REVISION__ < 6) 174#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
175/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ 175/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
176#define ANOMALY_05000313 (__SILICON_REVISION__ < 6) 176#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
177/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ 177/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
178#define ANOMALY_05000315 (__SILICON_REVISION__ < 6) 178#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
179/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ 179/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
180#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) 180#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
@@ -200,7 +200,7 @@
200#define ANOMALY_05000426 (1) 200#define ANOMALY_05000426 (1)
201/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 201/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
202#define ANOMALY_05000443 (1) 202#define ANOMALY_05000443 (1)
203/* False Hardware Error when RETI points to invalid memory */ 203/* False Hardware Error when RETI Points to Invalid Memory */
204#define ANOMALY_05000461 (1) 204#define ANOMALY_05000461 (1)
205 205
206/* These anomalies have been "phased" out of analog.com anomaly sheets and are 206/* These anomalies have been "phased" out of analog.com anomaly sheets and are
@@ -215,17 +215,17 @@
215#define ANOMALY_05000070 (__SILICON_REVISION__ < 2) 215#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
216/* Writing FIO_DIR can corrupt a programmable flag's data */ 216/* Writing FIO_DIR can corrupt a programmable flag's data */
217#define ANOMALY_05000079 (__SILICON_REVISION__ < 2) 217#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
218/* Timer Auto-Baud Mode requires the UART clock to be enabled */ 218/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
219#define ANOMALY_05000086 (__SILICON_REVISION__ < 2) 219#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
220/* Internal Clocking Modes on SPORT0 not supported */ 220/* Internal Clocking Modes on SPORT0 not supported */
221#define ANOMALY_05000088 (__SILICON_REVISION__ < 2) 221#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
222/* Internal voltage regulator does not wake up from an RTC wakeup */ 222/* Internal voltage regulator does not wake up from an RTC wakeup */
223#define ANOMALY_05000092 (__SILICON_REVISION__ < 2) 223#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
224/* The IFLUSH instruction must be preceded by a CSYNC instruction */ 224/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
225#define ANOMALY_05000093 (__SILICON_REVISION__ < 2) 225#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
226/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */ 226/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
227#define ANOMALY_05000095 (__SILICON_REVISION__ < 2) 227#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
228/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */ 228/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
229#define ANOMALY_05000096 (__SILICON_REVISION__ < 2) 229#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
230/* Performance Monitor 0 and 1 are swapped when monitoring memory events */ 230/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
231#define ANOMALY_05000097 (__SILICON_REVISION__ < 2) 231#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
@@ -235,45 +235,45 @@
235#define ANOMALY_05000100 (__SILICON_REVISION__ < 2) 235#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
236/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ 236/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
237#define ANOMALY_05000101 (__SILICON_REVISION__ < 2) 237#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
238/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ 238/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
239#define ANOMALY_05000102 (__SILICON_REVISION__ < 2) 239#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
240/* Incorrect value written to the cycle counters */ 240/* Incorrect Value Written to the Cycle Counters */
241#define ANOMALY_05000103 (__SILICON_REVISION__ < 2) 241#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
242/* Stores to L1 Data memory incorrect when a specific sequence is followed */ 242/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
243#define ANOMALY_05000104 (__SILICON_REVISION__ < 2) 243#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
244/* Programmable Flag (PF3) functionality not supported in all PPI modes */ 244/* Programmable Flag (PF3) functionality not supported in all PPI modes */
245#define ANOMALY_05000106 (__SILICON_REVISION__ < 2) 245#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
246/* Data store can be lost when targeting a cache line fill */ 246/* Data store can be lost when targeting a cache line fill */
247#define ANOMALY_05000107 (__SILICON_REVISION__ < 2) 247#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
248/* Reserved bits in SYSCFG register not set at power on */ 248/* Reserved Bits in SYSCFG Register Not Set at Power-On */
249#define ANOMALY_05000109 (__SILICON_REVISION__ < 3) 249#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
250/* Infinite Core Stall */ 250/* Infinite Core Stall */
251#define ANOMALY_05000114 (__SILICON_REVISION__ < 2) 251#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
252/* PPI_FSx may glitch when generated by the on chip Timers */ 252/* PPI_FSx may glitch when generated by the on chip Timers. */
253#define ANOMALY_05000115 (__SILICON_REVISION__ < 2) 253#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
254/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ 254/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
255#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) 255#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
256/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ 256/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
257#define ANOMALY_05000117 (__SILICON_REVISION__ < 2) 257#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
258/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ 258/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
259#define ANOMALY_05000118 (__SILICON_REVISION__ < 2) 259#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
260/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ 260/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
261#define ANOMALY_05000123 (__SILICON_REVISION__ < 3) 261#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
262/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ 262/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
263#define ANOMALY_05000124 (__SILICON_REVISION__ < 3) 263#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
264/* Erroneous exception when enabling cache */ 264/* Erroneous Exception when Enabling Cache */
265#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) 265#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
266/* SPI clock polarity and phase bits incorrect during booting */ 266/* SPI clock polarity and phase bits incorrect during booting */
267#define ANOMALY_05000126 (__SILICON_REVISION__ < 3) 267#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
268/* DMEM_CONTROL is not set on Reset */ 268/* DMEM_CONTROL<12> Is Not Set on Reset */
269#define ANOMALY_05000137 (__SILICON_REVISION__ < 3) 269#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
270/* SPI boot will not complete if there is a zero fill block in the loader file */ 270/* SPI boot will not complete if there is a zero fill block in the loader file */
271#define ANOMALY_05000138 (__SILICON_REVISION__ == 2) 271#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
272/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */ 272/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
273#define ANOMALY_05000139 (__SILICON_REVISION__ < 2) 273#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
274/* Allowing the SPORT RX FIFO to fill will cause an overflow */ 274/* Allowing the SPORT RX FIFO to fill will cause an overflow */
275#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) 275#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
276/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ 276/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
277#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) 277#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
278/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ 278/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
279#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) 279#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
@@ -287,7 +287,7 @@
287#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) 287#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
288/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ 288/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
289#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) 289#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
290/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ 290/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
291#define ANOMALY_05000148 (__SILICON_REVISION__ < 3) 291#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
292/* Frame Delay in SPORT Multichannel Mode */ 292/* Frame Delay in SPORT Multichannel Mode */
293#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) 293#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
@@ -295,13 +295,13 @@
295#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) 295#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
296/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ 296/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
297#define ANOMALY_05000155 (__SILICON_REVISION__ < 3) 297#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
298/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ 298/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
299#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) 299#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
300/* SPORT transmit data is not gated by external frame sync in certain conditions */ 300/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
301#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) 301#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
302/* SDRAM auto-refresh and subsequent Power Ups */ 302/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
303#define ANOMALY_05000168 (__SILICON_REVISION__ < 3) 303#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
304/* DATA CPLB page miss can result in lost write-through cache data writes */ 304/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
305#define ANOMALY_05000169 (__SILICON_REVISION__ < 3) 305#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
306/* DMA vs Core accesses to external memory */ 306/* DMA vs Core accesses to external memory */
307#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) 307#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
@@ -309,15 +309,15 @@
309#define ANOMALY_05000174 (__SILICON_REVISION__ < 3) 309#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
310/* Overlapping Sequencer and Memory Stalls */ 310/* Overlapping Sequencer and Memory Stalls */
311#define ANOMALY_05000175 (__SILICON_REVISION__ < 3) 311#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
312/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ 312/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
313#define ANOMALY_05000176 (__SILICON_REVISION__ < 3) 313#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
314/* Disabling the PPI resets the PPI configuration registers */ 314/* Disabling the PPI Resets the PPI Configuration Registers */
315#define ANOMALY_05000181 (__SILICON_REVISION__ < 3) 315#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
316/* PPI TX Mode with 2 External Frame Syncs */ 316/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
317#define ANOMALY_05000185 (__SILICON_REVISION__ < 3) 317#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
318/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ 318/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
319#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) 319#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
320/* In PPI Transmit Modes with External Frame Syncs POLC */ 320/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
321#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) 321#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
322/* Internal Voltage Regulator may not start up */ 322/* Internal Voltage Regulator may not start up */
323#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) 323#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
@@ -326,6 +326,7 @@
326#define ANOMALY_05000120 (0) 326#define ANOMALY_05000120 (0)
327#define ANOMALY_05000149 (0) 327#define ANOMALY_05000149 (0)
328#define ANOMALY_05000171 (0) 328#define ANOMALY_05000171 (0)
329#define ANOMALY_05000182 (0)
329#define ANOMALY_05000220 (0) 330#define ANOMALY_05000220 (0)
330#define ANOMALY_05000248 (0) 331#define ANOMALY_05000248 (0)
331#define ANOMALY_05000266 (0) 332#define ANOMALY_05000266 (0)
@@ -345,5 +346,7 @@
345#define ANOMALY_05000448 (0) 346#define ANOMALY_05000448 (0)
346#define ANOMALY_05000456 (0) 347#define ANOMALY_05000456 (0)
347#define ANOMALY_05000450 (0) 348#define ANOMALY_05000450 (0)
349#define ANOMALY_05000465 (0)
350#define ANOMALY_05000467 (0)
348 351
349#endif 352#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
index 045184f81a29..39aa175f19f5 100644
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -34,7 +34,6 @@
34#define BF533_FAMILY 34#define BF533_FAMILY
35 35
36#include "bf533.h" 36#include "bf533.h"
37#include "mem_map.h"
38#include "defBF532.h" 37#include "defBF532.h"
39#include "anomaly.h" 38#include "anomaly.h"
40 39
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h
index fc33b7cb9937..197af1a398ac 100644
--- a/arch/blackfin/mach-bf533/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf533/include/mach/mem_map.h
@@ -1,38 +1,16 @@
1/* 1/*
2 * File: include/asm-blackfin/mach-bf533/mem_map.h 2 * BF533 memory map
3 * Based on:
4 * Author:
5 * 3 *
6 * Created: 4 * Copyright 2004-2009 Analog Devices Inc.
7 * Description: 5 * Licensed under the GPL-2 or later.
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */ 6 */
30 7
31#ifndef _MEM_MAP_533_H_ 8#ifndef __BFIN_MACH_MEM_MAP_H__
32#define _MEM_MAP_533_H_ 9#define __BFIN_MACH_MEM_MAP_H__
33 10
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ 11#ifndef __BFIN_MEM_MAP_H__
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ 12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13#endif
36 14
37/* Async Memory Banks */ 15/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ 16#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
@@ -158,20 +136,4 @@
158 136
159#endif 137#endif
160 138
161/* Level 2 Memory - none */ 139#endif
162
163#define L2_START 0
164#define L2_LENGTH 0
165
166/* Scratch Pad Memory */
167
168#define L1_SCRATCH_START 0xFFB00000
169#define L1_SCRATCH_LENGTH 0x1000
170
171#define GET_PDA_SAFE(preg) \
172 preg.l = _cpu_pda; \
173 preg.h = _cpu_pda;
174
175#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
176
177#endif /* _MEM_MAP_533_H_ */
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index ff7228caa7da..c1f76dd2c4ed 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -79,7 +79,6 @@ static struct resource bfin_isp1760_resources[] = {
79 79
80static struct isp1760_platform_data isp1760_priv = { 80static struct isp1760_platform_data isp1760_priv = {
81 .is_isp1761 = 0, 81 .is_isp1761 = 0,
82 .port1_disable = 0,
83 .bus_width_16 = 1, 82 .bus_width_16 = 1,
84 .port1_otg = 0, 83 .port1_otg = 0,
85 .analog_oc = 0, 84 .analog_oc = 0,
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index fc9663425465..57c128cc3b64 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -34,13 +34,13 @@
34# define ANOMALY_BF537 0 34# define ANOMALY_BF537 0
35#endif 35#endif
36 36
37/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ 37/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
38#define ANOMALY_05000074 (1) 38#define ANOMALY_05000074 (1)
39/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 39/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
40#define ANOMALY_05000119 (1) 40#define ANOMALY_05000119 (1)
41/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 41/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
42#define ANOMALY_05000122 (1) 42#define ANOMALY_05000122 (1)
43/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ 43/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
44#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) 44#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
45/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ 45/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
46#define ANOMALY_05000180 (1) 46#define ANOMALY_05000180 (1)
@@ -50,11 +50,11 @@
50#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) 50#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
51/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 51/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
52#define ANOMALY_05000245 (1) 52#define ANOMALY_05000245 (1)
53/* CLKIN Buffer Output Enable Reset Behavior Is Changed */ 53/* Buffered CLKIN Output Is Disabled by Default */
54#define ANOMALY_05000247 (1) 54#define ANOMALY_05000247 (1)
55/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ 55/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
56#define ANOMALY_05000250 (__SILICON_REVISION__ < 3) 56#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
57/* EMAC Tx DMA error after an early frame abort */ 57/* EMAC TX DMA Error After an Early Frame Abort */
58#define ANOMALY_05000252 (__SILICON_REVISION__ < 3) 58#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
59/* Maximum External Clock Speed for Timers */ 59/* Maximum External Clock Speed for Timers */
60#define ANOMALY_05000253 (__SILICON_REVISION__ < 3) 60#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
@@ -62,7 +62,7 @@
62#define ANOMALY_05000254 (__SILICON_REVISION__ > 2) 62#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
63/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */ 63/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
64#define ANOMALY_05000255 (__SILICON_REVISION__ < 3) 64#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
65/* EMAC MDIO input latched on wrong MDC edge */ 65/* EMAC MDIO Input Latched on Wrong MDC Edge */
66#define ANOMALY_05000256 (__SILICON_REVISION__ < 3) 66#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
67/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ 67/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
68#define ANOMALY_05000257 (__SILICON_REVISION__ < 3) 68#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
@@ -80,7 +80,7 @@
80#define ANOMALY_05000264 (__SILICON_REVISION__ < 3) 80#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
81/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 81/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
82#define ANOMALY_05000265 (1) 82#define ANOMALY_05000265 (1)
83/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */ 83/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
84#define ANOMALY_05000268 (__SILICON_REVISION__ < 3) 84#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
85/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ 85/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
86#define ANOMALY_05000270 (__SILICON_REVISION__ < 3) 86#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
@@ -92,15 +92,15 @@
92#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) 92#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
93/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 93/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
94#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) 94#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
95/* SPI Master boot mode does not work well with Atmel Data flash devices */ 95/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
96#define ANOMALY_05000280 (1) 96#define ANOMALY_05000280 (1)
97/* False Hardware Error Exception When ISR Context Is Not Restored */ 97/* False Hardware Error Exception when ISR Context Is Not Restored */
98#define ANOMALY_05000281 (__SILICON_REVISION__ < 3) 98#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
99/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 99/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
100#define ANOMALY_05000282 (__SILICON_REVISION__ < 3) 100#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
101/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ 101/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
102#define ANOMALY_05000283 (__SILICON_REVISION__ < 3) 102#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
103/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */ 103/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
104#define ANOMALY_05000285 (__SILICON_REVISION__ < 3) 104#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
105/* SPORTs May Receive Bad Data If FIFOs Fill Up */ 105/* SPORTs May Receive Bad Data If FIFOs Fill Up */
106#define ANOMALY_05000288 (__SILICON_REVISION__ < 3) 106#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
@@ -112,25 +112,25 @@
112#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) 112#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
113/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 113/* SCKELOW Bit Does Not Maintain State Through Hibernate */
114#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) 114#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
115/* Writing UART_THR while UART clock is disabled sends erroneous start bit */ 115/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
116#define ANOMALY_05000309 (__SILICON_REVISION__ < 3) 116#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
117/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 117/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
118#define ANOMALY_05000310 (1) 118#define ANOMALY_05000310 (1)
119/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 119/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
120#define ANOMALY_05000312 (1) 120#define ANOMALY_05000312 (1)
121/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ 121/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
122#define ANOMALY_05000313 (1) 122#define ANOMALY_05000313 (1)
123/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ 123/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
124#define ANOMALY_05000315 (__SILICON_REVISION__ < 3) 124#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
125/* EMAC RMII mode: collisions occur in Full Duplex mode */ 125/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
126#define ANOMALY_05000316 (__SILICON_REVISION__ < 3) 126#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
127/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */ 127/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
128#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) 128#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
129/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ 129/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
130#define ANOMALY_05000322 (1) 130#define ANOMALY_05000322 (1)
131/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ 131/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
132#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) 132#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
133/* New Feature: UART Remains Enabled after UART Boot */ 133/* UART Gets Disabled after UART Boot */
134#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) 134#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
135/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ 135/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
136#define ANOMALY_05000355 (1) 136#define ANOMALY_05000355 (1)
@@ -154,7 +154,7 @@
154#define ANOMALY_05000426 (1) 154#define ANOMALY_05000426 (1)
155/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 155/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
156#define ANOMALY_05000443 (1) 156#define ANOMALY_05000443 (1)
157/* False Hardware Error when RETI points to invalid memory */ 157/* False Hardware Error when RETI Points to Invalid Memory */
158#define ANOMALY_05000461 (1) 158#define ANOMALY_05000461 (1)
159 159
160/* Anomalies that don't exist on this proc */ 160/* Anomalies that don't exist on this proc */
@@ -165,14 +165,17 @@
165#define ANOMALY_05000158 (0) 165#define ANOMALY_05000158 (0)
166#define ANOMALY_05000171 (0) 166#define ANOMALY_05000171 (0)
167#define ANOMALY_05000179 (0) 167#define ANOMALY_05000179 (0)
168#define ANOMALY_05000182 (0)
168#define ANOMALY_05000183 (0) 169#define ANOMALY_05000183 (0)
169#define ANOMALY_05000198 (0) 170#define ANOMALY_05000198 (0)
171#define ANOMALY_05000202 (0)
170#define ANOMALY_05000215 (0) 172#define ANOMALY_05000215 (0)
171#define ANOMALY_05000220 (0) 173#define ANOMALY_05000220 (0)
172#define ANOMALY_05000227 (0) 174#define ANOMALY_05000227 (0)
173#define ANOMALY_05000230 (0) 175#define ANOMALY_05000230 (0)
174#define ANOMALY_05000231 (0) 176#define ANOMALY_05000231 (0)
175#define ANOMALY_05000233 (0) 177#define ANOMALY_05000233 (0)
178#define ANOMALY_05000234 (0)
176#define ANOMALY_05000242 (0) 179#define ANOMALY_05000242 (0)
177#define ANOMALY_05000248 (0) 180#define ANOMALY_05000248 (0)
178#define ANOMALY_05000266 (0) 181#define ANOMALY_05000266 (0)
@@ -195,5 +198,7 @@
195#define ANOMALY_05000448 (0) 198#define ANOMALY_05000448 (0)
196#define ANOMALY_05000456 (0) 199#define ANOMALY_05000456 (0)
197#define ANOMALY_05000450 (0) 200#define ANOMALY_05000450 (0)
201#define ANOMALY_05000465 (0)
202#define ANOMALY_05000467 (0)
198 203
199#endif 204#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index 7d6069c886f1..f5e5015ad831 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -35,7 +35,6 @@
35#define BF537_FAMILY 35#define BF537_FAMILY
36 36
37#include "bf537.h" 37#include "bf537.h"
38#include "mem_map.h"
39#include "defBF534.h" 38#include "defBF534.h"
40#include "anomaly.h" 39#include "anomaly.h"
41 40
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h
index f9010c4b4bf3..942f08de306b 100644
--- a/arch/blackfin/mach-bf537/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf537/include/mach/mem_map.h
@@ -1,38 +1,16 @@
1/* 1/*
2 * file: include/asm-blackfin/mach-bf537/mem_map.h 2 * BF537 memory map
3 * based on:
4 * author:
5 * 3 *
6 * created: 4 * Copyright 2004-2009 Analog Devices Inc.
7 * description: 5 * Licensed under the GPL-2 or later.
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */ 6 */
30 7
31#ifndef _MEM_MAP_537_H_ 8#ifndef __BFIN_MACH_MEM_MAP_H__
32#define _MEM_MAP_537_H_ 9#define __BFIN_MACH_MEM_MAP_H__
33 10
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ 11#ifndef __BFIN_MEM_MAP_H__
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ 12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13#endif
36 14
37/* Async Memory Banks */ 15/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ 16#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
@@ -166,20 +144,4 @@
166 144
167#endif 145#endif
168 146
169/* Level 2 Memory - none */ 147#endif
170
171#define L2_START 0
172#define L2_LENGTH 0
173
174/* Scratch Pad Memory */
175
176#define L1_SCRATCH_START 0xFFB00000
177#define L1_SCRATCH_LENGTH 0x1000
178
179#define GET_PDA_SAFE(preg) \
180 preg.l = _cpu_pda; \
181 preg.h = _cpu_pda;
182
183#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
184
185#endif /* _MEM_MAP_537_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index 175ca9ef7232..c97acdf85cd3 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -30,13 +30,13 @@
30# define ANOMALY_BF539 0 30# define ANOMALY_BF539 0
31#endif 31#endif
32 32
33/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ 33/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
34#define ANOMALY_05000074 (1) 34#define ANOMALY_05000074 (1)
35/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 35/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
36#define ANOMALY_05000119 (1) 36#define ANOMALY_05000119 (1)
37/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 37/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
38#define ANOMALY_05000122 (1) 38#define ANOMALY_05000122 (1)
39/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ 39/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
40#define ANOMALY_05000166 (1) 40#define ANOMALY_05000166 (1)
41/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ 41/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
42#define ANOMALY_05000179 (1) 42#define ANOMALY_05000179 (1)
@@ -70,11 +70,11 @@
70#define ANOMALY_05000277 (__SILICON_REVISION__ < 4) 70#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
71/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 71/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
72#define ANOMALY_05000278 (__SILICON_REVISION__ < 4) 72#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
73/* False Hardware Error Exception When ISR Context Is Not Restored */ 73/* False Hardware Error Exception when ISR Context Is Not Restored */
74#define ANOMALY_05000281 (__SILICON_REVISION__ < 4) 74#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
75/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ 75/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
76#define ANOMALY_05000282 (__SILICON_REVISION__ < 4) 76#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
77/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ 77/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
78#define ANOMALY_05000283 (__SILICON_REVISION__ < 4) 78#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
79/* SPORTs May Receive Bad Data If FIFOs Fill Up */ 79/* SPORTs May Receive Bad Data If FIFOs Fill Up */
80#define ANOMALY_05000288 (__SILICON_REVISION__ < 4) 80#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
@@ -92,11 +92,11 @@
92#define ANOMALY_05000307 (__SILICON_REVISION__ < 4) 92#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
93/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 93/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
94#define ANOMALY_05000310 (1) 94#define ANOMALY_05000310 (1)
95/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 95/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
96#define ANOMALY_05000312 (__SILICON_REVISION__ < 5) 96#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
97/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ 97/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
98#define ANOMALY_05000313 (__SILICON_REVISION__ < 4) 98#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
99/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ 99/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
100#define ANOMALY_05000315 (__SILICON_REVISION__ < 4) 100#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
101/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ 101/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
102#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) 102#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
@@ -110,7 +110,7 @@
110#define ANOMALY_05000371 (__SILICON_REVISION__ < 5) 110#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
111/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */ 111/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
112#define ANOMALY_05000374 (__SILICON_REVISION__ == 4) 112#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
113/* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */ 113/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
114#define ANOMALY_05000375 (__SILICON_REVISION__ < 4) 114#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
115/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ 115/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
116#define ANOMALY_05000402 (__SILICON_REVISION__ < 4) 116#define ANOMALY_05000402 (__SILICON_REVISION__ < 4)
@@ -126,26 +126,32 @@
126#define ANOMALY_05000436 (__SILICON_REVISION__ > 3) 126#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
127/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 127/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
128#define ANOMALY_05000443 (1) 128#define ANOMALY_05000443 (1)
129/* False Hardware Error when RETI points to invalid memory */ 129/* False Hardware Error when RETI Points to Invalid Memory */
130#define ANOMALY_05000461 (1) 130#define ANOMALY_05000461 (1)
131 131
132/* Anomalies that don't exist on this proc */ 132/* Anomalies that don't exist on this proc */
133#define ANOMALY_05000099 (0) 133#define ANOMALY_05000099 (0)
134#define ANOMALY_05000120 (0) 134#define ANOMALY_05000120 (0)
135#define ANOMALY_05000125 (0)
135#define ANOMALY_05000149 (0) 136#define ANOMALY_05000149 (0)
136#define ANOMALY_05000158 (0) 137#define ANOMALY_05000158 (0)
137#define ANOMALY_05000171 (0) 138#define ANOMALY_05000171 (0)
139#define ANOMALY_05000182 (0)
138#define ANOMALY_05000198 (0) 140#define ANOMALY_05000198 (0)
141#define ANOMALY_05000202 (0)
139#define ANOMALY_05000215 (0) 142#define ANOMALY_05000215 (0)
140#define ANOMALY_05000220 (0) 143#define ANOMALY_05000220 (0)
141#define ANOMALY_05000227 (0) 144#define ANOMALY_05000227 (0)
142#define ANOMALY_05000230 (0) 145#define ANOMALY_05000230 (0)
143#define ANOMALY_05000231 (0) 146#define ANOMALY_05000231 (0)
147#define ANOMALY_05000234 (0)
144#define ANOMALY_05000242 (0) 148#define ANOMALY_05000242 (0)
145#define ANOMALY_05000248 (0) 149#define ANOMALY_05000248 (0)
146#define ANOMALY_05000250 (0) 150#define ANOMALY_05000250 (0)
147#define ANOMALY_05000254 (0) 151#define ANOMALY_05000254 (0)
152#define ANOMALY_05000257 (0)
148#define ANOMALY_05000263 (0) 153#define ANOMALY_05000263 (0)
154#define ANOMALY_05000266 (0)
149#define ANOMALY_05000274 (0) 155#define ANOMALY_05000274 (0)
150#define ANOMALY_05000287 (0) 156#define ANOMALY_05000287 (0)
151#define ANOMALY_05000305 (0) 157#define ANOMALY_05000305 (0)
@@ -166,5 +172,7 @@
166#define ANOMALY_05000448 (0) 172#define ANOMALY_05000448 (0)
167#define ANOMALY_05000456 (0) 173#define ANOMALY_05000456 (0)
168#define ANOMALY_05000450 (0) 174#define ANOMALY_05000450 (0)
175#define ANOMALY_05000465 (0)
176#define ANOMALY_05000467 (0)
169 177
170#endif 178#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 6f628353dde3..9496196ac164 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -35,7 +35,6 @@
35#define BF538_FAMILY 35#define BF538_FAMILY
36 36
37#include "bf538.h" 37#include "bf538.h"
38#include "mem_map.h"
39#include "defBF539.h" 38#include "defBF539.h"
40#include "anomaly.h" 39#include "anomaly.h"
41 40
diff --git a/arch/blackfin/mach-bf538/include/mach/mem_map.h b/arch/blackfin/mach-bf538/include/mach/mem_map.h
index 76811966690e..aff00f453e9e 100644
--- a/arch/blackfin/mach-bf538/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf538/include/mach/mem_map.h
@@ -1,38 +1,16 @@
1/* 1/*
2 * File: include/asm-blackfin/mach-bf538/mem_map.h 2 * BF538 memory map
3 * Based on:
4 * Author:
5 * 3 *
6 * Created: 4 * Copyright 2004-2009 Analog Devices Inc.
7 * Description: 5 * Licensed under the GPL-2 or later.
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */ 6 */
30 7
31#ifndef _MEM_MAP_538_H_ 8#ifndef __BFIN_MACH_MEM_MAP_H__
32#define _MEM_MAP_538_H_ 9#define __BFIN_MACH_MEM_MAP_H__
33 10
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ 11#ifndef __BFIN_MEM_MAP_H__
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ 12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13#endif
36 14
37/* Async Memory Banks */ 15/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ 16#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
@@ -93,21 +71,4 @@
93#define BFIN_DSUPBANKS 0 71#define BFIN_DSUPBANKS 0
94#endif /*CONFIG_BFIN_DCACHE*/ 72#endif /*CONFIG_BFIN_DCACHE*/
95 73
96 74#endif
97/* Level 2 Memory - none */
98
99#define L2_START 0
100#define L2_LENGTH 0
101
102/* Scratch Pad Memory */
103
104#define L1_SCRATCH_START 0xFFB00000
105#define L1_SCRATCH_LENGTH 0x1000
106
107#define GET_PDA_SAFE(preg) \
108 preg.l = _cpu_pda; \
109 preg.h = _cpu_pda;
110
111#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
112
113#endif /* _MEM_MAP_538_H_ */
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 805a57b5e650..81f5b95cc361 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -76,7 +76,6 @@ static struct resource bfin_isp1760_resources[] = {
76 76
77static struct isp1760_platform_data isp1760_priv = { 77static struct isp1760_platform_data isp1760_priv = {
78 .is_isp1761 = 0, 78 .is_isp1761 = 0,
79 .port1_disable = 0,
80 .bus_width_16 = 1, 79 .bus_width_16 = 1,
81 .port1_otg = 0, 80 .port1_otg = 0,
82 .analog_oc = 0, 81 .analog_oc = 0,
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index c510ae688e28..18a4cd24f673 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -18,7 +18,7 @@
18# error will not work on BF548 silicon version 0.0, or 0.1 18# error will not work on BF548 silicon version 0.0, or 0.1
19#endif 19#endif
20 20
21/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ 21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
22#define ANOMALY_05000074 (1) 22#define ANOMALY_05000074 (1)
23/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ 23/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
24#define ANOMALY_05000119 (1) 24#define ANOMALY_05000119 (1)
@@ -30,17 +30,17 @@
30#define ANOMALY_05000265 (1) 30#define ANOMALY_05000265 (1)
31/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 31/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
32#define ANOMALY_05000272 (1) 32#define ANOMALY_05000272 (1)
33/* False Hardware Error Exception When ISR Context Is Not Restored */ 33/* False Hardware Error Exception when ISR Context Is Not Restored */
34#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) 34#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
35/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 35/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
36#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) 36#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
37/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 37/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
38#define ANOMALY_05000310 (1) 38#define ANOMALY_05000310 (1)
39/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 39/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
40#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) 40#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
41/* TWI Slave Boot Mode Is Not Functional */ 41/* TWI Slave Boot Mode Is Not Functional */
42#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) 42#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
43/* External FIFO Boot Mode Is Not Functional */ 43/* FIFO Boot Mode Not Functional */
44#define ANOMALY_05000325 (__SILICON_REVISION__ < 2) 44#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
45/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ 45/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
46#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) 46#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
@@ -178,8 +178,12 @@
178#define ANOMALY_05000450 (1) 178#define ANOMALY_05000450 (1)
179/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ 179/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
180#define ANOMALY_05000456 (__SILICON_REVISION__ < 3) 180#define ANOMALY_05000456 (__SILICON_REVISION__ < 3)
181/* False Hardware Error when RETI points to invalid memory */ 181/* False Hardware Error when RETI Points to Invalid Memory */
182#define ANOMALY_05000461 (1) 182#define ANOMALY_05000461 (1)
183/* USB Rx DMA hang */
184#define ANOMALY_05000465 (1)
185/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
186#define ANOMALY_05000467 (1)
183 187
184/* Anomalies that don't exist on this proc */ 188/* Anomalies that don't exist on this proc */
185#define ANOMALY_05000099 (0) 189#define ANOMALY_05000099 (0)
@@ -189,30 +193,36 @@
189#define ANOMALY_05000158 (0) 193#define ANOMALY_05000158 (0)
190#define ANOMALY_05000171 (0) 194#define ANOMALY_05000171 (0)
191#define ANOMALY_05000179 (0) 195#define ANOMALY_05000179 (0)
196#define ANOMALY_05000182 (0)
192#define ANOMALY_05000183 (0) 197#define ANOMALY_05000183 (0)
193#define ANOMALY_05000198 (0) 198#define ANOMALY_05000198 (0)
199#define ANOMALY_05000202 (0)
194#define ANOMALY_05000215 (0) 200#define ANOMALY_05000215 (0)
195#define ANOMALY_05000220 (0) 201#define ANOMALY_05000220 (0)
196#define ANOMALY_05000227 (0) 202#define ANOMALY_05000227 (0)
197#define ANOMALY_05000230 (0) 203#define ANOMALY_05000230 (0)
198#define ANOMALY_05000231 (0) 204#define ANOMALY_05000231 (0)
199#define ANOMALY_05000233 (0) 205#define ANOMALY_05000233 (0)
206#define ANOMALY_05000234 (0)
200#define ANOMALY_05000242 (0) 207#define ANOMALY_05000242 (0)
201#define ANOMALY_05000244 (0) 208#define ANOMALY_05000244 (0)
202#define ANOMALY_05000248 (0) 209#define ANOMALY_05000248 (0)
203#define ANOMALY_05000250 (0) 210#define ANOMALY_05000250 (0)
204#define ANOMALY_05000254 (0) 211#define ANOMALY_05000254 (0)
212#define ANOMALY_05000257 (0)
205#define ANOMALY_05000261 (0) 213#define ANOMALY_05000261 (0)
206#define ANOMALY_05000263 (0) 214#define ANOMALY_05000263 (0)
207#define ANOMALY_05000266 (0) 215#define ANOMALY_05000266 (0)
208#define ANOMALY_05000273 (0) 216#define ANOMALY_05000273 (0)
209#define ANOMALY_05000274 (0) 217#define ANOMALY_05000274 (0)
210#define ANOMALY_05000278 (0) 218#define ANOMALY_05000278 (0)
219#define ANOMALY_05000283 (0)
211#define ANOMALY_05000287 (0) 220#define ANOMALY_05000287 (0)
212#define ANOMALY_05000301 (0) 221#define ANOMALY_05000301 (0)
213#define ANOMALY_05000305 (0) 222#define ANOMALY_05000305 (0)
214#define ANOMALY_05000307 (0) 223#define ANOMALY_05000307 (0)
215#define ANOMALY_05000311 (0) 224#define ANOMALY_05000311 (0)
225#define ANOMALY_05000315 (0)
216#define ANOMALY_05000323 (0) 226#define ANOMALY_05000323 (0)
217#define ANOMALY_05000362 (1) 227#define ANOMALY_05000362 (1)
218#define ANOMALY_05000363 (0) 228#define ANOMALY_05000363 (0)
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index cf6c1500222a..6b97396d817f 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -33,7 +33,6 @@
33#define _MACH_BLACKFIN_H_ 33#define _MACH_BLACKFIN_H_
34 34
35#include "bf548.h" 35#include "bf548.h"
36#include "mem_map.h"
37#include "anomaly.h" 36#include "anomaly.h"
38 37
39#ifdef CONFIG_BF542 38#ifdef CONFIG_BF542
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h
index 70b9c1194024..caac2dfb41eb 100644
--- a/arch/blackfin/mach-bf548/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf548/include/mach/mem_map.h
@@ -1,38 +1,16 @@
1/* 1/*
2 * file: include/asm-blackfin/mach-bf548/mem_map.h 2 * BF548 memory map
3 * based on:
4 * author:
5 * 3 *
6 * created: 4 * Copyright 2004-2009 Analog Devices Inc.
7 * description: 5 * Licensed under the GPL-2 or later.
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */ 6 */
30 7
31#ifndef _MEM_MAP_548_H_ 8#ifndef __BFIN_MACH_MEM_MAP_H__
32#define _MEM_MAP_548_H_ 9#define __BFIN_MACH_MEM_MAP_H__
33 10
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ 11#ifndef __BFIN_MEM_MAP_H__
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ 12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13#endif
36 14
37/* Async Memory Banks */ 15/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ 16#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
@@ -103,15 +81,4 @@
103# define L2_LENGTH 0x20000 81# define L2_LENGTH 0x20000
104#endif 82#endif
105 83
106/* Scratch Pad Memory */ 84#endif
107
108#define L1_SCRATCH_START 0xFFB00000
109#define L1_SCRATCH_LENGTH 0x1000
110
111#define GET_PDA_SAFE(preg) \
112 preg.l = _cpu_pda; \
113 preg.h = _cpu_pda;
114
115#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
116
117#endif/* _MEM_MAP_548_H_ */
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index b5ef7ff7b7bd..4df904f9e90a 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -62,7 +62,6 @@ static struct resource bfin_isp1760_resources[] = {
62 62
63static struct isp1760_platform_data isp1760_priv = { 63static struct isp1760_platform_data isp1760_priv = {
64 .is_isp1761 = 0, 64 .is_isp1761 = 0,
65 .port1_disable = 0,
66 .bus_width_16 = 1, 65 .bus_width_16 = 1,
67 .port1_otg = 0, 66 .port1_otg = 0,
68 .analog_oc = 0, 67 .analog_oc = 0,
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index dccd396cd931..94b8e277f09d 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -18,19 +18,19 @@
18# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 18# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
19#endif 19#endif
20 20
21/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ 21/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
22#define ANOMALY_05000074 (1) 22#define ANOMALY_05000074 (1)
23/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ 23/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
24#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) 24#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
25/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ 25/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
26#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) 26#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
27/* Testset instructions restricted to 32-bit aligned memory locations */ 27/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
28#define ANOMALY_05000120 (1) 28#define ANOMALY_05000120 (1)
29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ 29/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
30#define ANOMALY_05000122 (1) 30#define ANOMALY_05000122 (1)
31/* Erroneous exception when enabling cache */ 31/* Erroneous Exception when Enabling Cache */
32#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) 32#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
33/* Signbits instruction not functional under certain conditions */ 33/* SIGNBITS Instruction Not Functional under Certain Conditions */
34#define ANOMALY_05000127 (1) 34#define ANOMALY_05000127 (1)
35/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ 35/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
36#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) 36#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
@@ -40,7 +40,7 @@
40#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) 40#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
41/* Allowing the SPORT RX FIFO to fill will cause an overflow */ 41/* Allowing the SPORT RX FIFO to fill will cause an overflow */
42#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) 42#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
43/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ 43/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
44#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) 44#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
45/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ 45/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
46#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) 46#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
@@ -52,7 +52,7 @@
52#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) 52#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
53/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ 53/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
54#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) 54#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
55/* IMDMA S1/D1 channel may stall */ 55/* IMDMA S1/D1 Channel May Stall */
56#define ANOMALY_05000149 (1) 56#define ANOMALY_05000149 (1)
57/* DMA engine may lose data due to incorrect handshaking */ 57/* DMA engine may lose data due to incorrect handshaking */
58#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) 58#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
@@ -66,7 +66,7 @@
66#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) 66#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
67/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ 67/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
68#define ANOMALY_05000156 (__SILICON_REVISION__ < 4) 68#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
69/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ 69/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
70#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) 70#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
71/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ 71/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
72#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) 72#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
@@ -76,17 +76,17 @@
76#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) 76#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
77/* DMEM_CONTROL<12> is not set on Reset */ 77/* DMEM_CONTROL<12> is not set on Reset */
78#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) 78#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
79/* SPORT transmit data is not gated by external frame sync in certain conditions */ 79/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
80#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) 80#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
81/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ 81/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
82#define ANOMALY_05000166 (1) 82#define ANOMALY_05000166 (1)
83/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ 83/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
84#define ANOMALY_05000167 (1) 84#define ANOMALY_05000167 (1)
85/* SDRAM auto-refresh and subsequent Power Ups */ 85/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
86#define ANOMALY_05000168 (__SILICON_REVISION__ < 5) 86#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
87/* DATA CPLB page miss can result in lost write-through cache data writes */ 87/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
88#define ANOMALY_05000169 (__SILICON_REVISION__ < 5) 88#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
89/* Boot-ROM code modifies SICA_IWRx wakeup registers */ 89/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
90#define ANOMALY_05000171 (__SILICON_REVISION__ < 5) 90#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
91/* DSPID register values incorrect */ 91/* DSPID register values incorrect */
92#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) 92#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
@@ -96,29 +96,29 @@
96#define ANOMALY_05000174 (__SILICON_REVISION__ < 5) 96#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
97/* Overlapping Sequencer and Memory Stalls */ 97/* Overlapping Sequencer and Memory Stalls */
98#define ANOMALY_05000175 (__SILICON_REVISION__ < 5) 98#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
99/* Multiplication of (-1) by (-1) followed by an accumulator saturation */ 99/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
100#define ANOMALY_05000176 (__SILICON_REVISION__ < 5) 100#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
101/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ 101/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
102#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) 102#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
103/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ 103/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
104#define ANOMALY_05000180 (1) 104#define ANOMALY_05000180 (1)
105/* Disabling the PPI resets the PPI configuration registers */ 105/* Disabling the PPI Resets the PPI Configuration Registers */
106#define ANOMALY_05000181 (__SILICON_REVISION__ < 5) 106#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
107/* IMDMA does not operate to full speed for 600MHz and higher devices */ 107/* Internal Memory DMA Does Not Operate at Full Speed */
108#define ANOMALY_05000182 (1) 108#define ANOMALY_05000182 (1)
109/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */ 109/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
110#define ANOMALY_05000184 (__SILICON_REVISION__ < 5) 110#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
111/* PPI TX Mode with 2 External Frame Syncs */ 111/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
112#define ANOMALY_05000185 (__SILICON_REVISION__ < 5) 112#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
113/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */ 113/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
114#define ANOMALY_05000186 (__SILICON_REVISION__ < 5) 114#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
115/* IMDMA Corrupted Data after a Halt */ 115/* IMDMA Corrupted Data after a Halt */
116#define ANOMALY_05000187 (1) 116#define ANOMALY_05000187 (1)
117/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */ 117/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
118#define ANOMALY_05000188 (__SILICON_REVISION__ < 5) 118#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
119/* False Protection Exceptions */ 119/* False Protection Exceptions when Speculative Fetch Is Cancelled */
120#define ANOMALY_05000189 (__SILICON_REVISION__ < 5) 120#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
121/* PPI not functional at core voltage < 1Volt */ 121/* PPI Not Functional at Core Voltage < 1Volt */
122#define ANOMALY_05000190 (1) 122#define ANOMALY_05000190 (1)
123/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ 123/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
124#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) 124#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
@@ -126,7 +126,7 @@
126#define ANOMALY_05000193 (__SILICON_REVISION__ < 5) 126#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
127/* Restarting SPORT in Specific Modes May Cause Data Corruption */ 127/* Restarting SPORT in Specific Modes May Cause Data Corruption */
128#define ANOMALY_05000194 (__SILICON_REVISION__ < 5) 128#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
129/* Failing MMR Accesses When Stalled by Preceding Memory Read */ 129/* Failing MMR Accesses when Preceding Memory Read Stalls */
130#define ANOMALY_05000198 (__SILICON_REVISION__ < 5) 130#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
131/* Current DMA Address Shows Wrong Value During Carry Fix */ 131/* Current DMA Address Shows Wrong Value During Carry Fix */
132#define ANOMALY_05000199 (__SILICON_REVISION__ < 5) 132#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
@@ -134,9 +134,9 @@
134#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) 134#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
135/* Possible Infinite Stall with Specific Dual-DAG Situation */ 135/* Possible Infinite Stall with Specific Dual-DAG Situation */
136#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) 136#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
137/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */ 137/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
138#define ANOMALY_05000204 (__SILICON_REVISION__ < 5) 138#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
139/* Specific sequence that can cause DMA error or DMA stopping */ 139/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
140#define ANOMALY_05000205 (__SILICON_REVISION__ < 5) 140#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
141/* Recovery from "Brown-Out" Condition */ 141/* Recovery from "Brown-Out" Condition */
142#define ANOMALY_05000207 (__SILICON_REVISION__ < 5) 142#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
@@ -158,7 +158,7 @@
158#define ANOMALY_05000230 (__SILICON_REVISION__ < 5) 158#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
159/* UART STB Bit Incorrectly Affects Receiver Setting */ 159/* UART STB Bit Incorrectly Affects Receiver Setting */
160#define ANOMALY_05000231 (__SILICON_REVISION__ < 5) 160#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
161/* SPORT data transmit lines are incorrectly driven in multichannel mode */ 161/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
162#define ANOMALY_05000232 (__SILICON_REVISION__ < 5) 162#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
163/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ 163/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
164#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) 164#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
@@ -166,7 +166,7 @@
166#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
167/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 167/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
168#define ANOMALY_05000245 (__SILICON_REVISION__ < 5) 168#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
169/* TESTSET operation forces stall on the other core */ 169/* TESTSET Operation Forces Stall on the Other Core */
170#define ANOMALY_05000248 (__SILICON_REVISION__ < 5) 170#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
171/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ 171/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
172#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5) 172#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
@@ -192,9 +192,9 @@
192#define ANOMALY_05000264 (__SILICON_REVISION__ < 5) 192#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
193/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 193/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
194#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) 194#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
195/* IMDMA destination IRQ status must be read prior to using IMDMA */ 195/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
196#define ANOMALY_05000266 (__SILICON_REVISION__ > 3) 196#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
197/* IMDMA may corrupt data under certain conditions */ 197/* IMDMA May Corrupt Data under Certain Conditions */
198#define ANOMALY_05000267 (1) 198#define ANOMALY_05000267 (1)
199/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ 199/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
200#define ANOMALY_05000269 (1) 200#define ANOMALY_05000269 (1)
@@ -202,7 +202,7 @@
202#define ANOMALY_05000270 (1) 202#define ANOMALY_05000270 (1)
203/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ 203/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
204#define ANOMALY_05000272 (1) 204#define ANOMALY_05000272 (1)
205/* Data cache write back to external synchronous memory may be lost */ 205/* Data Cache Write Back to External Synchronous Memory May Be Lost */
206#define ANOMALY_05000274 (1) 206#define ANOMALY_05000274 (1)
207/* PPI Timing and Sampling Information Updates */ 207/* PPI Timing and Sampling Information Updates */
208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) 208#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
@@ -212,17 +212,17 @@
212#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) 212#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
213/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ 213/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
214#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) 214#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
215/* False Hardware Error Exception When ISR Context Is Not Restored */ 215/* False Hardware Error Exception when ISR Context Is Not Restored */
216#define ANOMALY_05000281 (__SILICON_REVISION__ < 5) 216#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
217/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ 217/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
218#define ANOMALY_05000283 (1) 218#define ANOMALY_05000283 (1)
219/* A read will receive incorrect data under certain conditions */ 219/* Reads Will Receive Incorrect Data under Certain Conditions */
220#define ANOMALY_05000287 (__SILICON_REVISION__ < 5) 220#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
221/* SPORTs May Receive Bad Data If FIFOs Fill Up */ 221/* SPORTs May Receive Bad Data If FIFOs Fill Up */
222#define ANOMALY_05000288 (__SILICON_REVISION__ < 5) 222#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
223/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ 223/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
224#define ANOMALY_05000301 (1) 224#define ANOMALY_05000301 (1)
225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 225/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
226#define ANOMALY_05000302 (1) 226#define ANOMALY_05000302 (1)
227/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ 227/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
@@ -230,25 +230,25 @@
230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) 230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
231/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 231/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
232#define ANOMALY_05000310 (1) 232#define ANOMALY_05000310 (1)
233/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ 233/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
234#define ANOMALY_05000312 (1) 234#define ANOMALY_05000312 (1)
235/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ 235/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
236#define ANOMALY_05000313 (1) 236#define ANOMALY_05000313 (1)
237/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ 237/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
238#define ANOMALY_05000315 (1) 238#define ANOMALY_05000315 (1)
239/* PF2 Output Remains Asserted After SPI Master Boot */ 239/* PF2 Output Remains Asserted after SPI Master Boot */
240#define ANOMALY_05000320 (__SILICON_REVISION__ > 3) 240#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
241/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */ 241/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
242#define ANOMALY_05000323 (1) 242#define ANOMALY_05000323 (1)
243/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */ 243/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
244#define ANOMALY_05000326 (__SILICON_REVISION__ > 3) 244#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
245/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */ 245/* 24-Bit SPI Boot Mode Is Not Functional */
246#define ANOMALY_05000331 (__SILICON_REVISION__ < 5) 246#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
247/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */ 247/* Slave SPI Boot Mode Is Not Functional */
248#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) 248#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
249/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ 249/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
250#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) 250#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
251/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */ 251/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
252#define ANOMALY_05000339 (__SILICON_REVISION__ < 5) 252#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
253/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */ 253/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
254#define ANOMALY_05000343 (__SILICON_REVISION__ < 5) 254#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
@@ -276,7 +276,7 @@
276#define ANOMALY_05000428 (__SILICON_REVISION__ > 3) 276#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
277/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 277/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
278#define ANOMALY_05000443 (1) 278#define ANOMALY_05000443 (1)
279/* False Hardware Error when RETI points to invalid memory */ 279/* False Hardware Error when RETI Points to Invalid Memory */
280#define ANOMALY_05000461 (1) 280#define ANOMALY_05000461 (1)
281 281
282/* Anomalies that don't exist on this proc */ 282/* Anomalies that don't exist on this proc */
@@ -284,6 +284,7 @@
284#define ANOMALY_05000158 (0) 284#define ANOMALY_05000158 (0)
285#define ANOMALY_05000183 (0) 285#define ANOMALY_05000183 (0)
286#define ANOMALY_05000233 (0) 286#define ANOMALY_05000233 (0)
287#define ANOMALY_05000234 (0)
287#define ANOMALY_05000273 (0) 288#define ANOMALY_05000273 (0)
288#define ANOMALY_05000311 (0) 289#define ANOMALY_05000311 (0)
289#define ANOMALY_05000353 (1) 290#define ANOMALY_05000353 (1)
@@ -298,5 +299,7 @@
298#define ANOMALY_05000448 (0) 299#define ANOMALY_05000448 (0)
299#define ANOMALY_05000456 (0) 300#define ANOMALY_05000456 (0)
300#define ANOMALY_05000450 (0) 301#define ANOMALY_05000450 (0)
302#define ANOMALY_05000465 (0)
303#define ANOMALY_05000467 (0)
301 304
302#endif 305#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index f79f6626b7ec..8be31358ef88 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -34,7 +34,6 @@
34#define BF561_FAMILY 34#define BF561_FAMILY
35 35
36#include "bf561.h" 36#include "bf561.h"
37#include "mem_map.h"
38#include "defBF561.h" 37#include "defBF561.h"
39#include "anomaly.h" 38#include "anomaly.h"
40 39
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index 419dffdc96eb..a63e15c86d90 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -1,13 +1,16 @@
1/* 1/*
2 * Memory MAP 2 * BF561 memory map
3 * Common header file for blackfin BF561 of processors. 3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 * Licensed under the GPL-2 or later.
4 */ 6 */
5 7
6#ifndef _MEM_MAP_561_H_ 8#ifndef __BFIN_MACH_MEM_MAP_H__
7#define _MEM_MAP_561_H_ 9#define __BFIN_MACH_MEM_MAP_H__
8 10
9#define COREMMR_BASE 0xFFE00000 /* Core MMRs */ 11#ifndef __BFIN_MEM_MAP_H__
10#define SYSMMR_BASE 0xFFC00000 /* System MMRs */ 12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13#endif
11 14
12/* Async Memory Banks */ 15/* Async Memory Banks */
13#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ 16#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
@@ -82,9 +85,6 @@
82#define COREA_L1_SCRATCH_START 0xFFB00000 85#define COREA_L1_SCRATCH_START 0xFFB00000
83#define COREB_L1_SCRATCH_START 0xFF700000 86#define COREB_L1_SCRATCH_START 0xFF700000
84 87
85#define L1_SCRATCH_START COREA_L1_SCRATCH_START
86#define L1_SCRATCH_LENGTH 0x1000
87
88#ifdef __ASSEMBLY__ 88#ifdef __ASSEMBLY__
89 89
90/* 90/*
@@ -155,14 +155,42 @@
155 dreg = ROT dreg BY -1; \ 155 dreg = ROT dreg BY -1; \
156 dreg = CC; 156 dreg = CC;
157 157
158#else 158static inline unsigned long get_l1_scratch_start_cpu(int cpu)
159#define GET_PDA_SAFE(preg) \ 159{
160 preg.l = _cpu_pda; \ 160 return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
161 preg.h = _cpu_pda; 161}
162static inline unsigned long get_l1_code_start_cpu(int cpu)
163{
164 return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
165}
166static inline unsigned long get_l1_data_a_start_cpu(int cpu)
167{
168 return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
169}
170static inline unsigned long get_l1_data_b_start_cpu(int cpu)
171{
172 return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
173}
174
175static inline unsigned long get_l1_scratch_start(void)
176{
177 return get_l1_scratch_start_cpu(blackfin_core_id());
178}
179static inline unsigned long get_l1_code_start(void)
180{
181 return get_l1_code_start_cpu(blackfin_core_id());
182}
183static inline unsigned long get_l1_data_a_start(void)
184{
185 return get_l1_data_a_start_cpu(blackfin_core_id());
186}
187static inline unsigned long get_l1_data_b_start(void)
188{
189 return get_l1_data_b_start_cpu(blackfin_core_id());
190}
162 191
163#define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
164#endif /* CONFIG_SMP */ 192#endif /* CONFIG_SMP */
165 193
166#endif /* __ASSEMBLY__ */ 194#endif /* __ASSEMBLY__ */
167 195
168#endif /* _MEM_MAP_533_H_ */ 196#endif
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
index da93d9207165..5998d8632a73 100644
--- a/arch/blackfin/mach-common/arch_checks.c
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -74,7 +74,7 @@
74 74
75/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ 75/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
76#if ANOMALY_05000220 && \ 76#if ANOMALY_05000220 && \
77 ((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \ 77 ((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \
78 (!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB))) 78 (!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK)))
79# error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. 79# error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB.
80#endif 80#endif
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 70e3411f558c..85c658083279 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -141,7 +141,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
141 sclk = get_sclk() / 1000; 141 sclk = get_sclk() / 1000;
142 142
143#if ANOMALY_05000273 || ANOMALY_05000274 || \ 143#if ANOMALY_05000273 || ANOMALY_05000274 || \
144 (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE)) 144 (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
145 min_cclk = sclk * 2; 145 min_cclk = sclk * 2;
146#else 146#else
147 min_cclk = sclk; 147 min_cclk = sclk;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 31fa313e81cf..5a4e7c7fd92c 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -1609,6 +1609,7 @@ ENTRY(_sys_call_table)
1609 .long _sys_preadv 1609 .long _sys_preadv
1610 .long _sys_pwritev 1610 .long _sys_pwritev
1611 .long _sys_rt_tgsigqueueinfo 1611 .long _sys_rt_tgsigqueueinfo
1612 .long _sys_perf_counter_open
1612 1613
1613 .rept NR_syscalls-(.-_sys_call_table)/4 1614 .rept NR_syscalls-(.-_sys_call_table)/4
1614 .long _sys_ni_syscall 1615 .long _sys_ni_syscall
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index af70f09acd55..b42150190d0e 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -1052,35 +1052,34 @@ int __init init_arch_irq(void)
1052 set_irq_chained_handler(irq, bfin_demux_error_irq); 1052 set_irq_chained_handler(irq, bfin_demux_error_irq);
1053 break; 1053 break;
1054#endif 1054#endif
1055#if defined(CONFIG_TICKSOURCE_GPTMR0)
1056 case IRQ_TIMER0:
1057 set_irq_handler(irq, handle_percpu_irq);
1058 break;
1059#endif
1060#ifdef CONFIG_SMP 1055#ifdef CONFIG_SMP
1061 case IRQ_SUPPLE_0: 1056 case IRQ_SUPPLE_0:
1062 case IRQ_SUPPLE_1: 1057 case IRQ_SUPPLE_1:
1063 set_irq_handler(irq, handle_percpu_irq); 1058 set_irq_handler(irq, handle_percpu_irq);
1064 break; 1059 break;
1065#endif 1060#endif
1066 default:
1067#ifdef CONFIG_IPIPE 1061#ifdef CONFIG_IPIPE
1068 /* 1062#ifndef CONFIG_TICKSOURCE_CORETMR
1069 * We want internal interrupt sources to be 1063 case IRQ_TIMER0:
1070 * masked, because ISRs may trigger interrupts 1064 set_irq_handler(irq, handle_simple_irq);
1071 * recursively (e.g. DMA), but interrupts are 1065 break;
1072 * _not_ masked at CPU level. So let's handle 1066#endif /* !CONFIG_TICKSOURCE_CORETMR */
1073 * most of them as level interrupts, except 1067 case IRQ_CORETMR:
1074 * the timer interrupt which is special. 1068 set_irq_handler(irq, handle_simple_irq);
1075 */ 1069 break;
1076 if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR) 1070 default:
1077 set_irq_handler(irq, handle_simple_irq); 1071 set_irq_handler(irq, handle_level_irq);
1078 else 1072 break;
1079 set_irq_handler(irq, handle_level_irq);
1080#else /* !CONFIG_IPIPE */ 1073#else /* !CONFIG_IPIPE */
1074#ifdef CONFIG_TICKSOURCE_GPTMR0
1075 case IRQ_TIMER0:
1076 set_irq_handler(irq, handle_percpu_irq);
1077 break;
1078#endif /* CONFIG_TICKSOURCE_GPTMR0 */
1079 default:
1081 set_irq_handler(irq, handle_simple_irq); 1080 set_irq_handler(irq, handle_simple_irq);
1082#endif /* !CONFIG_IPIPE */
1083 break; 1081 break;
1082#endif /* !CONFIG_IPIPE */
1084 } 1083 }
1085 } 1084 }
1086 1085
@@ -1224,15 +1223,14 @@ __attribute__((l1_text))
1224asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) 1223asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1225{ 1224{
1226 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); 1225 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1227 struct ipipe_domain *this_domain = ipipe_current_domain; 1226 struct ipipe_domain *this_domain = __ipipe_current_domain;
1228 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; 1227 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1229 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; 1228 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1230 int irq, s; 1229 int irq, s;
1231 1230
1232 if (likely(vec == EVT_IVTMR_P)) { 1231 if (likely(vec == EVT_IVTMR_P))
1233 irq = IRQ_CORETMR; 1232 irq = IRQ_CORETMR;
1234 1233 else {
1235 } else {
1236#if defined(SIC_ISR0) || defined(SICA_ISR0) 1234#if defined(SIC_ISR0) || defined(SICA_ISR0)
1237 unsigned long sic_status[3]; 1235 unsigned long sic_status[3];
1238 1236
@@ -1262,12 +1260,11 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1262 break; 1260 break;
1263 } 1261 }
1264#endif 1262#endif
1265
1266 irq = ivg->irqno; 1263 irq = ivg->irqno;
1267 } 1264 }
1268 1265
1269 if (irq == IRQ_SYSTMR) { 1266 if (irq == IRQ_SYSTMR) {
1270#ifndef CONFIG_GENERIC_CLOCKEVENTS 1267#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1271 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ 1268 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1272#endif 1269#endif
1273 /* This is basically what we need from the register frame. */ 1270 /* This is basically what we need from the register frame. */
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index bce5a84be49f..9e7e27b7fc8d 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -132,7 +132,7 @@ int bf53x_resume_l1_mem(unsigned char *memptr)
132 return 0; 132 return 0;
133} 133}
134 134
135#ifdef CONFIG_BFIN_WB 135#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
136static void flushinv_all_dcache(void) 136static void flushinv_all_dcache(void)
137{ 137{
138 u32 way, bank, subbank, set; 138 u32 way, bank, subbank, set;
@@ -175,7 +175,7 @@ static inline void dcache_disable(void)
175#ifdef CONFIG_BFIN_DCACHE 175#ifdef CONFIG_BFIN_DCACHE
176 unsigned long ctrl; 176 unsigned long ctrl;
177 177
178#ifdef CONFIG_BFIN_WB 178#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
179 flushinv_all_dcache(); 179 flushinv_all_dcache();
180#endif 180#endif
181 SSYNC(); 181 SSYNC();
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 014a55abd09a..68bd0bd680cd 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -160,7 +160,7 @@ void __init mem_init(void)
160 160
161 /* do not count in kernel image between _rambase and _ramstart */ 161 /* do not count in kernel image between _rambase and _ramstart */
162 reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; 162 reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
163#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263) 163#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
164 reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT; 164 reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT;
165#endif 165#endif
166 166
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