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-rw-r--r--drivers/net/wireless/ath/ath5k/ath5k.h8
-rw-r--r--drivers/net/wireless/ath/ath5k/base.c2
-rw-r--r--drivers/net/wireless/ath/ath5k/dma.c245
-rw-r--r--drivers/net/wireless/ath/ath5k/reg.h27
4 files changed, 189 insertions, 93 deletions
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h
index fecbcd9a4259..0f42a5792ca0 100644
--- a/drivers/net/wireless/ath/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath/ath5k/ath5k.h
@@ -1187,7 +1187,13 @@ struct ath5k_hw {
1187 u32 ah_txq_imr_cbrurn; 1187 u32 ah_txq_imr_cbrurn;
1188 u32 ah_txq_imr_qtrig; 1188 u32 ah_txq_imr_qtrig;
1189 u32 ah_txq_imr_nofrm; 1189 u32 ah_txq_imr_nofrm;
1190 u32 ah_txq_isr; 1190
1191 u32 ah_txq_isr_txok_all;
1192 u32 ah_txq_isr_txurn;
1193 u32 ah_txq_isr_qcborn;
1194 u32 ah_txq_isr_qcburn;
1195 u32 ah_txq_isr_qtrig;
1196
1191 u32 *ah_rf_banks; 1197 u32 *ah_rf_banks;
1192 size_t ah_rf_banks_size; 1198 size_t ah_rf_banks_size;
1193 size_t ah_rf_regs_count; 1199 size_t ah_rf_regs_count;
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index b346d0492001..c18d31008978 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -1689,7 +1689,7 @@ ath5k_tasklet_tx(unsigned long data)
1689 struct ath5k_hw *ah = (void *)data; 1689 struct ath5k_hw *ah = (void *)data;
1690 1690
1691 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) 1691 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1692 if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i))) 1692 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
1693 ath5k_tx_processq(ah, &ah->txqs[i]); 1693 ath5k_tx_processq(ah, &ah->txqs[i]);
1694 1694
1695 ah->tx_pending = false; 1695 ah->tx_pending = false;
diff --git a/drivers/net/wireless/ath/ath5k/dma.c b/drivers/net/wireless/ath/ath5k/dma.c
index 2481f9c7f4b6..b5db6e78f88e 100644
--- a/drivers/net/wireless/ath/ath5k/dma.c
+++ b/drivers/net/wireless/ath/ath5k/dma.c
@@ -450,7 +450,6 @@ int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
450 * 450 *
451 * XXX: Link this with tx DMA size ? 451 * XXX: Link this with tx DMA size ?
452 * XXX: Use it to save interrupts ? 452 * XXX: Use it to save interrupts ?
453 * TODO: Needs testing, i think it's related to bmiss...
454 */ 453 */
455int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase) 454int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
456{ 455{
@@ -523,62 +522,161 @@ bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
523 * being mapped on some standard non hw-specific positions 522 * being mapped on some standard non hw-specific positions
524 * (check out &ath5k_int). 523 * (check out &ath5k_int).
525 * 524 *
526 * NOTE: We use read-and-clear register, so after this function is called ISR 525 * NOTE: We do write-to-clear, so the active PISR/SISR bits at the time this
527 * is zeroed. 526 * function gets called are cleared on return.
528 */ 527 */
529int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) 528int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
530{ 529{
531 u32 data; 530 u32 data = 0;
532 531
533 /* 532 /*
534 * Read interrupt status from the Interrupt Status register 533 * Read interrupt status from Primary Interrupt
535 * on 5210 534 * Register.
535 *
536 * Note: PISR/SISR Not available on 5210
536 */ 537 */
537 if (ah->ah_version == AR5K_AR5210) { 538 if (ah->ah_version == AR5K_AR5210) {
538 data = ath5k_hw_reg_read(ah, AR5K_ISR); 539 u32 isr = 0;
539 if (unlikely(data == AR5K_INT_NOCARD)) { 540 isr = ath5k_hw_reg_read(ah, AR5K_ISR);
540 *interrupt_mask = data; 541 if (unlikely(isr == AR5K_INT_NOCARD)) {
542 *interrupt_mask = isr;
541 return -ENODEV; 543 return -ENODEV;
542 } 544 }
543 } else { 545
544 /* 546 /*
545 * Read interrupt status from Interrupt 547 * Filter out the non-common bits from the interrupt
546 * Status Register shadow copy (Read And Clear) 548 * status.
547 *
548 * Note: PISR/SISR Not available on 5210
549 */ 549 */
550 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR); 550 *interrupt_mask = (isr & AR5K_INT_COMMON) & ah->ah_imr;
551 if (unlikely(data == AR5K_INT_NOCARD)) { 551
552 *interrupt_mask = data; 552 /* Hanlde INT_FATAL */
553 if (unlikely(isr & (AR5K_ISR_SSERR | AR5K_ISR_MCABT
554 | AR5K_ISR_DPERR)))
555 *interrupt_mask |= AR5K_INT_FATAL;
556
557 /*
558 * XXX: BMISS interrupts may occur after association.
559 * I found this on 5210 code but it needs testing. If this is
560 * true we should disable them before assoc and re-enable them
561 * after a successful assoc + some jiffies.
562 interrupt_mask &= ~AR5K_INT_BMISS;
563 */
564
565 data = isr;
566 } else {
567 u32 pisr = 0;
568 u32 pisr_clear = 0;
569 u32 sisr0 = 0;
570 u32 sisr1 = 0;
571 u32 sisr2 = 0;
572 u32 sisr3 = 0;
573 u32 sisr4 = 0;
574
575 /* Read PISR and SISRs... */
576 pisr = ath5k_hw_reg_read(ah, AR5K_PISR);
577 if (unlikely(pisr == AR5K_INT_NOCARD)) {
578 *interrupt_mask = pisr;
553 return -ENODEV; 579 return -ENODEV;
554 } 580 }
555 }
556 581
557 /* 582 sisr0 = ath5k_hw_reg_read(ah, AR5K_SISR0);
558 * Get abstract interrupt mask (driver-compatible) 583 sisr1 = ath5k_hw_reg_read(ah, AR5K_SISR1);
559 */ 584 sisr2 = ath5k_hw_reg_read(ah, AR5K_SISR2);
560 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr; 585 sisr3 = ath5k_hw_reg_read(ah, AR5K_SISR3);
586 sisr4 = ath5k_hw_reg_read(ah, AR5K_SISR4);
561 587
562 if (ah->ah_version != AR5K_AR5210) { 588 /*
563 u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2); 589 * PISR holds the logical OR of interrupt bits
590 * from SISR registers:
591 *
592 * TXOK and TXDESC -> Logical OR of TXOK and TXDESC
593 * per-queue bits on SISR0
594 *
595 * TXERR and TXEOL -> Logical OR of TXERR and TXEOL
596 * per-queue bits on SISR1
597 *
598 * TXURN -> Logical OR of TXURN per-queue bits on SISR2
599 *
600 * HIUERR -> Logical OR of MCABT, SSERR and DPER bits on SISR2
601 *
602 * BCNMISC -> Logical OR of TIM, CAB_END, DTIM_SYNC
603 * BCN_TIMEOUT, CAB_TIMEOUT and DTIM
604 * (and TSFOOR ?) bits on SISR2
605 *
606 * QCBRORN and QCBRURN -> Logical OR of QCBRORN and
607 * QCBRURN per-queue bits on SISR3
608 * QTRIG -> Logical OR of QTRIG per-queue bits on SISR4
609 *
610 * If we clean these bits on PISR we 'll also clear all
611 * related bits from SISRs, e.g. if we write the TXOK bit on
612 * PISR we 'll clean all TXOK bits from SISR0 so if a new TXOK
613 * interrupt got fired for another queue while we were reading
614 * the interrupt registers and we write back the TXOK bit on
615 * PISR we 'll lose it. So make sure that we don't write back
616 * on PISR any bits that come from SISRs. Clearing them from
617 * SISRs will also clear PISR so no need to worry here.
618 */
564 619
565 /*HIU = Host Interface Unit (PCI etc)*/ 620 pisr_clear = pisr & ~AR5K_ISR_BITS_FROM_SISRS;
566 if (unlikely(data & (AR5K_ISR_HIUERR)))
567 *interrupt_mask |= AR5K_INT_FATAL;
568 621
569 /*Beacon Not Ready*/ 622 /*
570 if (unlikely(data & (AR5K_ISR_BNR))) 623 * Write to clear them...
571 *interrupt_mask |= AR5K_INT_BNR; 624 * Note: This means that each bit we write back
625 * to the registers will get cleared, leaving the
626 * rest unaffected. So this won't affect new interrupts
627 * we didn't catch while reading/processing, we 'll get
628 * them next time get_isr gets called.
629 */
630 ath5k_hw_reg_write(ah, sisr0, AR5K_SISR0);
631 ath5k_hw_reg_write(ah, sisr1, AR5K_SISR1);
632 ath5k_hw_reg_write(ah, sisr2, AR5K_SISR2);
633 ath5k_hw_reg_write(ah, sisr3, AR5K_SISR3);
634 ath5k_hw_reg_write(ah, sisr4, AR5K_SISR4);
635 ath5k_hw_reg_write(ah, pisr_clear, AR5K_PISR);
636 /* Flush previous write */
637 ath5k_hw_reg_read(ah, AR5K_PISR);
572 638
573 if (unlikely(sisr2 & (AR5K_SISR2_SSERR | 639 /*
574 AR5K_SISR2_DPERR | 640 * Filter out the non-common bits from the interrupt
575 AR5K_SISR2_MCABT))) 641 * status.
576 *interrupt_mask |= AR5K_INT_FATAL; 642 */
643 *interrupt_mask = (pisr & AR5K_INT_COMMON) & ah->ah_imr;
644
645
646 /* We treat TXOK,TXDESC, TXERR and TXEOL
647 * the same way (schedule the tx tasklet)
648 * so we track them all together per queue */
649 if (pisr & AR5K_ISR_TXOK)
650 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0,
651 AR5K_SISR0_QCU_TXOK);
652
653 if (pisr & AR5K_ISR_TXDESC)
654 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0,
655 AR5K_SISR0_QCU_TXDESC);
577 656
578 if (data & AR5K_ISR_TIM) 657 if (pisr & AR5K_ISR_TXERR)
658 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1,
659 AR5K_SISR1_QCU_TXERR);
660
661 if (pisr & AR5K_ISR_TXEOL)
662 ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1,
663 AR5K_SISR1_QCU_TXEOL);
664
665 /* Currently this is not much usefull since we treat
666 * all queues the same way if we get a TXURN (update
667 * tx trigger level) but we might need it later on*/
668 if (pisr & AR5K_ISR_TXURN)
669 ah->ah_txq_isr_txurn |= AR5K_REG_MS(sisr2,
670 AR5K_SISR2_QCU_TXURN);
671
672 /* Misc Beacon related interrupts */
673
674 /* For AR5211 */
675 if (pisr & AR5K_ISR_TIM)
579 *interrupt_mask |= AR5K_INT_TIM; 676 *interrupt_mask |= AR5K_INT_TIM;
580 677
581 if (data & AR5K_ISR_BCNMISC) { 678 /* For AR5212+ */
679 if (pisr & AR5K_ISR_BCNMISC) {
582 if (sisr2 & AR5K_SISR2_TIM) 680 if (sisr2 & AR5K_SISR2_TIM)
583 *interrupt_mask |= AR5K_INT_TIM; 681 *interrupt_mask |= AR5K_INT_TIM;
584 if (sisr2 & AR5K_SISR2_DTIM) 682 if (sisr2 & AR5K_SISR2_DTIM)
@@ -591,63 +689,40 @@ int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
591 *interrupt_mask |= AR5K_INT_CAB_TIMEOUT; 689 *interrupt_mask |= AR5K_INT_CAB_TIMEOUT;
592 } 690 }
593 691
594 if (data & AR5K_ISR_RXDOPPLER) 692 /* Below interrupts are unlikely to happen */
693
694 /* HIU = Host Interface Unit (PCI etc)
695 * Can be one of MCABT, SSERR, DPERR from SISR2 */
696 if (unlikely(pisr & (AR5K_ISR_HIUERR)))
697 *interrupt_mask |= AR5K_INT_FATAL;
698
699
700 /*Beacon Not Ready*/
701 if (unlikely(pisr & (AR5K_ISR_BNR)))
702 *interrupt_mask |= AR5K_INT_BNR;
703
704 if (unlikely(pisr & (AR5K_ISR_RXDOPPLER)))
595 *interrupt_mask |= AR5K_INT_RX_DOPPLER; 705 *interrupt_mask |= AR5K_INT_RX_DOPPLER;
596 if (data & AR5K_ISR_QCBRORN) { 706
707 if (unlikely(pisr & (AR5K_ISR_QCBRORN))) {
597 *interrupt_mask |= AR5K_INT_QCBRORN; 708 *interrupt_mask |= AR5K_INT_QCBRORN;
598 ah->ah_txq_isr |= AR5K_REG_MS( 709 ah->ah_txq_isr_qcborn |= AR5K_REG_MS(sisr3,
599 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), 710 AR5K_SISR3_QCBRORN);
600 AR5K_SISR3_QCBRORN);
601 } 711 }
602 if (data & AR5K_ISR_QCBRURN) { 712
713 if (unlikely(pisr & (AR5K_ISR_QCBRURN))) {
603 *interrupt_mask |= AR5K_INT_QCBRURN; 714 *interrupt_mask |= AR5K_INT_QCBRURN;
604 ah->ah_txq_isr |= AR5K_REG_MS( 715 ah->ah_txq_isr_qcburn |= AR5K_REG_MS(sisr3,
605 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), 716 AR5K_SISR3_QCBRURN);
606 AR5K_SISR3_QCBRURN);
607 } 717 }
608 if (data & AR5K_ISR_QTRIG) { 718
719 if (unlikely(pisr & (AR5K_ISR_QTRIG))) {
609 *interrupt_mask |= AR5K_INT_QTRIG; 720 *interrupt_mask |= AR5K_INT_QTRIG;
610 ah->ah_txq_isr |= AR5K_REG_MS( 721 ah->ah_txq_isr_qtrig |= AR5K_REG_MS(sisr4,
611 ath5k_hw_reg_read(ah, AR5K_RAC_SISR4), 722 AR5K_SISR4_QTRIG);
612 AR5K_SISR4_QTRIG);
613 } 723 }
614 724
615 if (data & AR5K_ISR_TXOK) 725 data = pisr;
616 ah->ah_txq_isr |= AR5K_REG_MS(
617 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
618 AR5K_SISR0_QCU_TXOK);
619
620 if (data & AR5K_ISR_TXDESC)
621 ah->ah_txq_isr |= AR5K_REG_MS(
622 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0),
623 AR5K_SISR0_QCU_TXDESC);
624
625 if (data & AR5K_ISR_TXERR)
626 ah->ah_txq_isr |= AR5K_REG_MS(
627 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
628 AR5K_SISR1_QCU_TXERR);
629
630 if (data & AR5K_ISR_TXEOL)
631 ah->ah_txq_isr |= AR5K_REG_MS(
632 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1),
633 AR5K_SISR1_QCU_TXEOL);
634
635 if (data & AR5K_ISR_TXURN)
636 ah->ah_txq_isr |= AR5K_REG_MS(
637 ath5k_hw_reg_read(ah, AR5K_RAC_SISR2),
638 AR5K_SISR2_QCU_TXURN);
639 } else {
640 if (unlikely(data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT
641 | AR5K_ISR_HIUERR | AR5K_ISR_DPERR)))
642 *interrupt_mask |= AR5K_INT_FATAL;
643
644 /*
645 * XXX: BMISS interrupts may occur after association.
646 * I found this on 5210 code but it needs testing. If this is
647 * true we should disable them before assoc and re-enable them
648 * after a successful assoc + some jiffies.
649 interrupt_mask &= ~AR5K_INT_BMISS;
650 */
651 } 726 }
652 727
653 /* 728 /*
diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h
index f5c1000045d3..0ea1608b47fd 100644
--- a/drivers/net/wireless/ath/ath5k/reg.h
+++ b/drivers/net/wireless/ath/ath5k/reg.h
@@ -280,6 +280,10 @@
280 * 5211/5212 we have one primary and 4 secondary registers. 280 * 5211/5212 we have one primary and 4 secondary registers.
281 * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. 281 * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212.
282 * Most of these bits are common for all chipsets. 282 * Most of these bits are common for all chipsets.
283 *
284 * NOTE: On 5211+ TXOK, TXDESC, TXERR, TXEOL and TXURN contain
285 * the logical OR from per-queue interrupt bits found on SISR registers
286 * (see below).
283 */ 287 */
284#define AR5K_ISR 0x001c /* Register Address [5210] */ 288#define AR5K_ISR 0x001c /* Register Address [5210] */
285#define AR5K_PISR 0x0080 /* Register Address [5211+] */ 289#define AR5K_PISR 0x0080 /* Register Address [5211+] */
@@ -292,7 +296,10 @@
292#define AR5K_ISR_TXOK 0x00000040 /* Frame successfully transmitted */ 296#define AR5K_ISR_TXOK 0x00000040 /* Frame successfully transmitted */
293#define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ 297#define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */
294#define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ 298#define AR5K_ISR_TXERR 0x00000100 /* Transmit error */
295#define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout) */ 299#define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout)
300 * NOTE: We don't have per-queue info for this
301 * one, but we can enable it per-queue through
302 * TXNOFRM_QCU field on TXNOFRM register */
296#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ 303#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */
297#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ 304#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */
298#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ 305#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */
@@ -302,21 +309,29 @@
302#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ 309#define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */
303#define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ 310#define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
304#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ 311#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */
305#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 312#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+]
313 * 'or' of MCABT, SSERR, DPERR from SISR2 */
306#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ 314#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */
307#define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ 315#define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
308#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ 316#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */
309#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ 317#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */
310#define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */ 318#define AR5K_ISR_DPERR 0x00400000 /* Bus parity error [5210] */
311#define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ 319#define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */
312#define AR5K_ISR_TIM 0x00800000 /* [5211+] */ 320#define AR5K_ISR_TIM 0x00800000 /* [5211+] */
313#define AR5K_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, 321#define AR5K_ISR_BCNMISC 0x00800000 /* Misc beacon related interrupt
314 CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ 322 * 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
323 * CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */
315#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */ 324#define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */
316#define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */ 325#define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */
317#define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */ 326#define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */
318#define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ 327#define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */
319 328
329#define AR5K_ISR_BITS_FROM_SISRS (AR5K_ISR_TXOK | AR5K_ISR_TXDESC |\
330 AR5K_ISR_TXERR | AR5K_ISR_TXEOL |\
331 AR5K_ISR_TXURN | AR5K_ISR_HIUERR |\
332 AR5K_ISR_BCNMISC | AR5K_ISR_QCBRORN |\
333 AR5K_ISR_QCBRURN | AR5K_ISR_QTRIG)
334
320/* 335/*
321 * Secondary status registers [5211+] (0 - 4) 336 * Secondary status registers [5211+] (0 - 4)
322 * 337 *
@@ -347,7 +362,7 @@
347#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ 362#define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */
348#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ 363#define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */
349#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ 364#define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */
350#define AR5K_SISR2_TSFOOR 0x80000000 /* TSF OOR (?) */ 365#define AR5K_SISR2_TSFOOR 0x80000000 /* TSF Out of range */
351 366
352#define AR5K_SISR3 0x0090 /* Register Address [5211+] */ 367#define AR5K_SISR3 0x0090 /* Register Address [5211+] */
353#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ 368#define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */