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-rw-r--r--arch/arm/Kconfig8
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/mach-iop13xx/Kconfig20
-rw-r--r--arch/arm/mach-iop13xx/Makefile12
-rw-r--r--arch/arm/mach-iop13xx/Makefile.boot3
-rw-r--r--arch/arm/mach-iop13xx/io.c93
-rw-r--r--arch/arm/mach-iop13xx/iq81340mc.c98
-rw-r--r--arch/arm/mach-iop13xx/iq81340sc.c100
-rw-r--r--arch/arm/mach-iop13xx/irq.c286
-rw-r--r--arch/arm/mach-iop13xx/pci.c1113
-rw-r--r--arch/arm/mach-iop13xx/setup.c406
-rw-r--r--arch/arm/mach-iop13xx/time.c102
-rw-r--r--arch/arm/mm/Kconfig2
-rw-r--r--drivers/i2c/busses/Kconfig6
-rw-r--r--include/asm-arm/arch-iop13xx/debug-macro.S26
-rw-r--r--include/asm-arm/arch-iop13xx/dma.h3
-rw-r--r--include/asm-arm/arch-iop13xx/entry-macro.S39
-rw-r--r--include/asm-arm/arch-iop13xx/hardware.h28
-rw-r--r--include/asm-arm/arch-iop13xx/io.h41
-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h492
-rw-r--r--include/asm-arm/arch-iop13xx/iq81340.h31
-rw-r--r--include/asm-arm/arch-iop13xx/irqs.h207
-rw-r--r--include/asm-arm/arch-iop13xx/memory.h64
-rw-r--r--include/asm-arm/arch-iop13xx/pci.h57
-rw-r--r--include/asm-arm/arch-iop13xx/system.h59
-rw-r--r--include/asm-arm/arch-iop13xx/timex.h3
-rw-r--r--include/asm-arm/arch-iop13xx/uncompress.h24
-rw-r--r--include/asm-arm/arch-iop13xx/vmalloc.h4
28 files changed, 3324 insertions, 4 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ce00c570459d..d654c4f87d0f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -223,6 +223,12 @@ config ARCH_IOP33X
223 help 223 help
224 Support for Intel's IOP33X (XScale) family of processors. 224 Support for Intel's IOP33X (XScale) family of processors.
225 225
226config ARCH_IOP13XX
227 bool "IOP13xx-based"
228 select PCI
229 help
230 Support for Intel's IOP13XX (XScale) family of processors.
231
226config ARCH_IXP4XX 232config ARCH_IXP4XX
227 bool "IXP4xx-based" 233 bool "IXP4xx-based"
228 depends on MMU 234 depends on MMU
@@ -331,6 +337,8 @@ source "arch/arm/mach-iop32x/Kconfig"
331 337
332source "arch/arm/mach-iop33x/Kconfig" 338source "arch/arm/mach-iop33x/Kconfig"
333 339
340source "arch/arm/mach-iop13xx/Kconfig"
341
334source "arch/arm/mach-ixp4xx/Kconfig" 342source "arch/arm/mach-ixp4xx/Kconfig"
335 343
336source "arch/arm/mach-ixp2000/Kconfig" 344source "arch/arm/mach-ixp2000/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f4f8bf36071..5f6f9a585709 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -108,6 +108,7 @@ endif
108 machine-$(CONFIG_ARCH_CLPS711X) := clps711x 108 machine-$(CONFIG_ARCH_CLPS711X) := clps711x
109 machine-$(CONFIG_ARCH_IOP32X) := iop32x 109 machine-$(CONFIG_ARCH_IOP32X) := iop32x
110 machine-$(CONFIG_ARCH_IOP33X) := iop33x 110 machine-$(CONFIG_ARCH_IOP33X) := iop33x
111 machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
111 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx 112 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
112 machine-$(CONFIG_ARCH_IXP2000) := ixp2000 113 machine-$(CONFIG_ARCH_IXP2000) := ixp2000
113 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx 114 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
diff --git a/arch/arm/mach-iop13xx/Kconfig b/arch/arm/mach-iop13xx/Kconfig
new file mode 100644
index 000000000000..40c2d689f2eb
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Kconfig
@@ -0,0 +1,20 @@
1if ARCH_IOP13XX
2
3menu "IOP13XX Implementation Options"
4
5comment "IOP13XX Platform Support"
6
7config MACH_IQ81340SC
8 bool "Enable IQ81340SC Hardware Support"
9 help
10 Say Y here if you want to support running on the Intel IQ81340SC
11 evaluation kit.
12
13config MACH_IQ81340MC
14 bool "Enable IQ81340MC Hardware Support"
15 help
16 Say Y here if you want to support running on the Intel IQ81340MC
17 evaluation kit.
18
19endmenu
20endif
diff --git a/arch/arm/mach-iop13xx/Makefile b/arch/arm/mach-iop13xx/Makefile
new file mode 100644
index 000000000000..c3d6c08f2d4c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Makefile
@@ -0,0 +1,12 @@
1obj-y :=
2obj-m :=
3obj-n :=
4obj- :=
5
6obj-$(CONFIG_ARCH_IOP13XX) += setup.o
7obj-$(CONFIG_ARCH_IOP13XX) += irq.o
8obj-$(CONFIG_ARCH_IOP13XX) += time.o
9obj-$(CONFIG_ARCH_IOP13XX) += pci.o
10obj-$(CONFIG_ARCH_IOP13XX) += io.o
11obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
12obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
diff --git a/arch/arm/mach-iop13xx/Makefile.boot b/arch/arm/mach-iop13xx/Makefile.boot
new file mode 100644
index 000000000000..0b0e19fdfe6c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
new file mode 100644
index 000000000000..fbf9f88e46ea
--- /dev/null
+++ b/arch/arm/mach-iop13xx/io.c
@@ -0,0 +1,93 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <asm/hardware.h>
22#include <asm/io.h>
23
24void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
25 unsigned long flags)
26{
27 void __iomem * retval;
28
29 switch (cookie) {
30 case IOP13XX_PCIX_LOWER_MEM_RA ... IOP13XX_PCIX_UPPER_MEM_RA:
31 if (unlikely(!iop13xx_atux_mem_base))
32 retval = NULL;
33 else
34 retval = (void *)(iop13xx_atux_mem_base +
35 (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
36 break;
37 case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
38 if (unlikely(!iop13xx_atue_mem_base))
39 retval = NULL;
40 else
41 retval = (void *)(iop13xx_atue_mem_base +
42 (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
43 break;
44 case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
45 retval = __ioremap(IOP13XX_PBI_LOWER_MEM_PA +
46 (cookie - IOP13XX_PBI_LOWER_MEM_RA),
47 size, flags);
48 break;
49 case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
50 retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
51 break;
52 case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
53 retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
54 break;
55 case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
56 retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
57 break;
58 default:
59 retval = __ioremap(cookie, size, flags);
60 }
61
62 return retval;
63}
64EXPORT_SYMBOL(__iop13xx_ioremap);
65
66void __iop13xx_iounmap(void __iomem *addr)
67{
68 extern void __iounmap(volatile void __iomem *addr);
69
70 if (iop13xx_atue_mem_base)
71 if (addr >= (void __iomem *) iop13xx_atue_mem_base &&
72 addr < (void __iomem *) (iop13xx_atue_mem_base +
73 iop13xx_atue_mem_size))
74 goto skip;
75
76 if (iop13xx_atux_mem_base)
77 if (addr >= (void __iomem *) iop13xx_atux_mem_base &&
78 addr < (void __iomem *) (iop13xx_atux_mem_base +
79 iop13xx_atux_mem_size))
80 goto skip;
81
82 switch ((u32) addr) {
83 case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
84 case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
85 case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
86 goto skip;
87 }
88 __iounmap(addr);
89
90skip:
91 return;
92}
93EXPORT_SYMBOL(__iop13xx_iounmap);
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
new file mode 100644
index 000000000000..ee595786cd22
--- /dev/null
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -0,0 +1,98 @@
1/*
2 * iq81340mc board support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/pci.h>
20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23#include <asm/mach/pci.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/arch/pci.h>
27#include <asm/mach/time.h>
28
29extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
30
31static int __init
32iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
33{
34 switch (idsel) {
35 case 1:
36 switch (pin) {
37 case 1: return ATUX_INTB;
38 case 2: return ATUX_INTC;
39 case 3: return ATUX_INTD;
40 case 4: return ATUX_INTA;
41 default: return -1;
42 }
43 case 2:
44 switch (pin) {
45 case 1: return ATUX_INTC;
46 case 2: return ATUX_INTD;
47 case 3: return ATUX_INTC;
48 case 4: return ATUX_INTD;
49 default: return -1;
50 }
51 default: return -1;
52 }
53}
54
55static struct hw_pci iq81340mc_pci __initdata = {
56 .swizzle = pci_std_swizzle,
57 .nr_controllers = 0,
58 .setup = iop13xx_pci_setup,
59 .map_irq = iq81340mc_pcix_map_irq,
60 .scan = iop13xx_scan_bus,
61 .preinit = iop13xx_pci_init,
62};
63
64static int __init iq81340mc_pci_init(void)
65{
66 iop13xx_atu_select(&iq81340mc_pci);
67 pci_common_init(&iq81340mc_pci);
68 iop13xx_map_pci_memory();
69
70 return 0;
71}
72
73static void __init iq81340mc_init(void)
74{
75 iop13xx_platform_init();
76 iq81340mc_pci_init();
77}
78
79static void __init iq81340mc_timer_init(void)
80{
81 iop13xx_init_time(400000000);
82}
83
84static struct sys_timer iq81340mc_timer = {
85 .init = iq81340mc_timer_init,
86 .offset = iop13xx_gettimeoffset,
87};
88
89MACHINE_START(IQ81340MC, "Intel IQ81340MC")
90 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
91 .phys_io = PHYS_IO,
92 .io_pg_offst = IO_PG_OFFSET,
93 .map_io = iop13xx_map_io,
94 .init_irq = iop13xx_init_irq,
95 .timer = &iq81340mc_timer,
96 .boot_params = BOOT_PARAM_OFFSET,
97 .init_machine = iq81340mc_init,
98MACHINE_END
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
new file mode 100644
index 000000000000..6677e14b61bf
--- /dev/null
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -0,0 +1,100 @@
1/*
2 * iq81340sc board support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/pci.h>
20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23#include <asm/mach/pci.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/arch/pci.h>
27#include <asm/mach/time.h>
28
29extern int init_atu;
30
31static int __init
32iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
33{
34 WARN_ON(idsel < 1 || idsel > 2);
35
36 switch (idsel) {
37 case 1:
38 switch (pin) {
39 case 1: return ATUX_INTB;
40 case 2: return ATUX_INTC;
41 case 3: return ATUX_INTD;
42 case 4: return ATUX_INTA;
43 default: return -1;
44 }
45 case 2:
46 switch (pin) {
47 case 1: return ATUX_INTC;
48 case 2: return ATUX_INTC;
49 case 3: return ATUX_INTC;
50 case 4: return ATUX_INTC;
51 default: return -1;
52 }
53 default: return -1;
54 }
55}
56
57static struct hw_pci iq81340sc_pci __initdata = {
58 .swizzle = pci_std_swizzle,
59 .nr_controllers = 0,
60 .setup = iop13xx_pci_setup,
61 .scan = iop13xx_scan_bus,
62 .map_irq = iq81340sc_atux_map_irq,
63 .preinit = iop13xx_pci_init
64};
65
66static int __init iq81340sc_pci_init(void)
67{
68 iop13xx_atu_select(&iq81340sc_pci);
69 pci_common_init(&iq81340sc_pci);
70 iop13xx_map_pci_memory();
71
72 return 0;
73}
74
75static void __init iq81340sc_init(void)
76{
77 iop13xx_platform_init();
78 iq81340sc_pci_init();
79}
80
81static void __init iq81340sc_timer_init(void)
82{
83 iop13xx_init_time(400000000);
84}
85
86static struct sys_timer iq81340sc_timer = {
87 .init = iq81340sc_timer_init,
88 .offset = iop13xx_gettimeoffset,
89};
90
91MACHINE_START(IQ81340SC, "Intel IQ81340SC")
92 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
93 .phys_io = PHYS_IO,
94 .io_pg_offst = IO_PG_OFFSET,
95 .map_io = iop13xx_map_io,
96 .init_irq = iop13xx_init_irq,
97 .timer = &iq81340sc_timer,
98 .boot_params = BOOT_PARAM_OFFSET,
99 .init_machine = iq81340sc_init,
100MACHINE_END
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
new file mode 100644
index 000000000000..c4d9c8c5579c
--- /dev/null
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -0,0 +1,286 @@
1/*
2 * iop13xx IRQ handling / support functions
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/sysctl.h>
23#include <asm/uaccess.h>
24#include <asm/mach/irq.h>
25#include <asm/irq.h>
26#include <asm/hardware.h>
27#include <asm/mach-types.h>
28#include <asm/arch/irqs.h>
29
30/* INTCTL0 CP6 R0 Page 4
31 */
32static inline u32 read_intctl_0(void)
33{
34 u32 val;
35 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
36 return val;
37}
38static inline void write_intctl_0(u32 val)
39{
40 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
41}
42
43/* INTCTL1 CP6 R1 Page 4
44 */
45static inline u32 read_intctl_1(void)
46{
47 u32 val;
48 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
49 return val;
50}
51static inline void write_intctl_1(u32 val)
52{
53 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
54}
55
56/* INTCTL2 CP6 R2 Page 4
57 */
58static inline u32 read_intctl_2(void)
59{
60 u32 val;
61 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
62 return val;
63}
64static inline void write_intctl_2(u32 val)
65{
66 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
67}
68
69/* INTCTL3 CP6 R3 Page 4
70 */
71static inline u32 read_intctl_3(void)
72{
73 u32 val;
74 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
75 return val;
76}
77static inline void write_intctl_3(u32 val)
78{
79 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
80}
81
82/* INTSTR0 CP6 R0 Page 5
83 */
84static inline u32 read_intstr_0(void)
85{
86 u32 val;
87 asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
88 return val;
89}
90static inline void write_intstr_0(u32 val)
91{
92 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
93}
94
95/* INTSTR1 CP6 R1 Page 5
96 */
97static inline u32 read_intstr_1(void)
98{
99 u32 val;
100 asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
101 return val;
102}
103static void write_intstr_1(u32 val)
104{
105 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
106}
107
108/* INTSTR2 CP6 R2 Page 5
109 */
110static inline u32 read_intstr_2(void)
111{
112 u32 val;
113 asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
114 return val;
115}
116static void write_intstr_2(u32 val)
117{
118 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
119}
120
121/* INTSTR3 CP6 R3 Page 5
122 */
123static inline u32 read_intstr_3(void)
124{
125 u32 val;
126 asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
127 return val;
128}
129static void write_intstr_3(u32 val)
130{
131 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
132}
133
134/* INTBASE CP6 R0 Page 2
135 */
136static inline u32 read_intbase(void)
137{
138 u32 val;
139 asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
140 return val;
141}
142static void write_intbase(u32 val)
143{
144 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
145}
146
147/* INTSIZE CP6 R2 Page 2
148 */
149static inline u32 read_intsize(void)
150{
151 u32 val;
152 asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
153 return val;
154}
155static void write_intsize(u32 val)
156{
157 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
158}
159
160/* 0 = Interrupt Masked and 1 = Interrupt not masked */
161static void
162iop13xx_irq_mask0 (unsigned int irq)
163{
164 u32 cp_flags = iop13xx_cp6_save();
165 write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
166 iop13xx_cp6_restore(cp_flags);
167}
168
169static void
170iop13xx_irq_mask1 (unsigned int irq)
171{
172 u32 cp_flags = iop13xx_cp6_save();
173 write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
174 iop13xx_cp6_restore(cp_flags);
175}
176
177static void
178iop13xx_irq_mask2 (unsigned int irq)
179{
180 u32 cp_flags = iop13xx_cp6_save();
181 write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
182 iop13xx_cp6_restore(cp_flags);
183}
184
185static void
186iop13xx_irq_mask3 (unsigned int irq)
187{
188 u32 cp_flags = iop13xx_cp6_save();
189 write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
190 iop13xx_cp6_restore(cp_flags);
191}
192
193static void
194iop13xx_irq_unmask0(unsigned int irq)
195{
196 u32 cp_flags = iop13xx_cp6_save();
197 write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
198 iop13xx_cp6_restore(cp_flags);
199}
200
201static void
202iop13xx_irq_unmask1(unsigned int irq)
203{
204 u32 cp_flags = iop13xx_cp6_save();
205 write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
206 iop13xx_cp6_restore(cp_flags);
207}
208
209static void
210iop13xx_irq_unmask2(unsigned int irq)
211{
212 u32 cp_flags = iop13xx_cp6_save();
213 write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
214 iop13xx_cp6_restore(cp_flags);
215}
216
217static void
218iop13xx_irq_unmask3(unsigned int irq)
219{
220 u32 cp_flags = iop13xx_cp6_save();
221 write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
222 iop13xx_cp6_restore(cp_flags);
223}
224
225static struct irqchip iop13xx_irqchip0 = {
226 .ack = iop13xx_irq_mask0,
227 .mask = iop13xx_irq_mask0,
228 .unmask = iop13xx_irq_unmask0,
229};
230
231static struct irqchip iop13xx_irqchip1 = {
232 .ack = iop13xx_irq_mask1,
233 .mask = iop13xx_irq_mask1,
234 .unmask = iop13xx_irq_unmask1,
235};
236
237static struct irqchip iop13xx_irqchip2 = {
238 .ack = iop13xx_irq_mask2,
239 .mask = iop13xx_irq_mask2,
240 .unmask = iop13xx_irq_unmask2,
241};
242
243static struct irqchip iop13xx_irqchip3 = {
244 .ack = iop13xx_irq_mask3,
245 .mask = iop13xx_irq_mask3,
246 .unmask = iop13xx_irq_unmask3,
247};
248
249void __init iop13xx_init_irq(void)
250{
251 unsigned int i;
252
253 u32 cp_flags = iop13xx_cp6_save();
254
255 /* disable all interrupts */
256 write_intctl_0(0);
257 write_intctl_1(0);
258 write_intctl_2(0);
259 write_intctl_3(0);
260
261 /* treat all as IRQ */
262 write_intstr_0(0);
263 write_intstr_1(0);
264 write_intstr_2(0);
265 write_intstr_3(0);
266
267 /* initialize the interrupt vector generator */
268 write_intbase(INTBASE);
269 write_intsize(INTSIZE_4);
270
271 for(i = 0; i < NR_IOP13XX_IRQS; i++) {
272 if (i < 32)
273 set_irq_chip(i, &iop13xx_irqchip0);
274 else if (i < 64)
275 set_irq_chip(i, &iop13xx_irqchip1);
276 else if (i < 96)
277 set_irq_chip(i, &iop13xx_irqchip2);
278 else
279 set_irq_chip(i, &iop13xx_irqchip3);
280
281 set_irq_handler(i, do_level_IRQ);
282 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
283 }
284
285 iop13xx_cp6_restore(cp_flags);
286}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
new file mode 100644
index 000000000000..89ec70ea3187
--- /dev/null
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -0,0 +1,1113 @@
1/*
2 * iop13xx PCI support
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19
20#include <linux/pci.h>
21#include <linux/delay.h>
22
23#include <asm/irq.h>
24#include <asm/hardware.h>
25#include <asm/sizes.h>
26#include <asm/mach/pci.h>
27#include <asm/arch/pci.h>
28
29#define IOP13XX_PCI_DEBUG 0
30#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
31
32u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
33u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
34static struct pci_bus *pci_bus_atux = 0;
35static struct pci_bus *pci_bus_atue = 0;
36u32 iop13xx_atue_mem_base;
37u32 iop13xx_atux_mem_base;
38size_t iop13xx_atue_mem_size;
39size_t iop13xx_atux_mem_size;
40unsigned long iop13xx_pcibios_min_io = 0;
41unsigned long iop13xx_pcibios_min_mem = 0;
42
43EXPORT_SYMBOL(iop13xx_atue_mem_base);
44EXPORT_SYMBOL(iop13xx_atux_mem_base);
45EXPORT_SYMBOL(iop13xx_atue_mem_size);
46EXPORT_SYMBOL(iop13xx_atux_mem_size);
47
48int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
49static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
50 access */
51
52/* Scan the initialized busses and ioremap the requested memory range
53 */
54void iop13xx_map_pci_memory(void)
55{
56 int atu;
57 struct pci_bus *bus;
58 struct pci_dev *dev;
59 resource_size_t end = 0;
60
61 for (atu = 0; atu < 2; atu++) {
62 bus = atu ? pci_bus_atue : pci_bus_atux;
63 if (bus) {
64 list_for_each_entry(dev, &bus->devices, bus_list) {
65 int i;
66 int max = 7;
67
68 if (dev->subordinate)
69 max = DEVICE_COUNT_RESOURCE;
70
71 for (i = 0; i < max; i++) {
72 struct resource *res = &dev->resource[i];
73 if (res->flags & IORESOURCE_MEM)
74 end = max(res->end, end);
75 }
76 }
77
78 switch(atu) {
79 case 0:
80 iop13xx_atux_mem_size =
81 (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
82
83 /* 16MB align the request */
84 if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
85 iop13xx_atux_mem_size &= ~(SZ_16M - 1);
86 iop13xx_atux_mem_size += SZ_16M;
87 }
88
89 if (end) {
90 iop13xx_atux_mem_base =
91 (u32) __ioremap_pfn(
92 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
93 , 0, iop13xx_atux_mem_size, 0);
94 if (!iop13xx_atux_mem_base) {
95 printk("%s: atux allocation "
96 "failed\n", __FUNCTION__);
97 BUG();
98 }
99 } else
100 iop13xx_atux_mem_size = 0;
101 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
102 __FUNCTION__, atu, iop13xx_atux_mem_size,
103 iop13xx_atux_mem_base);
104 break;
105 case 1:
106 iop13xx_atue_mem_size =
107 (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
108
109 /* 16MB align the request */
110 if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
111 iop13xx_atue_mem_size &= ~(SZ_16M - 1);
112 iop13xx_atue_mem_size += SZ_16M;
113 }
114
115 if (end) {
116 iop13xx_atue_mem_base =
117 (u32) __ioremap_pfn(
118 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
119 , 0, iop13xx_atue_mem_size, 0);
120 if (!iop13xx_atue_mem_base) {
121 printk("%s: atue allocation "
122 "failed\n", __FUNCTION__);
123 BUG();
124 }
125 } else
126 iop13xx_atue_mem_size = 0;
127 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
128 __FUNCTION__, atu, iop13xx_atue_mem_size,
129 iop13xx_atue_mem_base);
130 break;
131 }
132
133 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
134 atu ? "ATUE" : "ATUX",
135 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
136 SZ_1M,
137 atu ? IOP13XX_PCIE_LOWER_MEM_RA :
138 IOP13XX_PCIX_LOWER_MEM_RA,
139 atu ? iop13xx_atue_mem_base :
140 iop13xx_atux_mem_base);
141 end = 0;
142 }
143
144 }
145}
146
147static inline int iop13xx_atu_function(int atu)
148{
149 int func = 0;
150 /* the function number depends on the value of the
151 * IOP13XX_INTERFACE_SEL_PCIX reset strap
152 * see C-Spec section 3.17
153 */
154 switch(atu) {
155 case IOP13XX_INIT_ATU_ATUX:
156 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
157 func = 5;
158 else
159 func = 0;
160 break;
161 case IOP13XX_INIT_ATU_ATUE:
162 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
163 func = 0;
164 else
165 func = 5;
166 break;
167 default:
168 BUG();
169 }
170
171 return func;
172}
173
174/* iop13xx_atux_cfg_address - format a configuration address for atux
175 * @bus: Target bus to access
176 * @devfn: Combined device number and function number
177 * @where: Desired register's address offset
178 *
179 * Convert the parameters to a configuration address formatted
180 * according the PCI-X 2.0 specification
181 */
182static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
183{
184 struct pci_sys_data *sys = bus->sysdata;
185 u32 addr;
186
187 if (sys->busnr == bus->number)
188 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
189 else
190 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
191
192 addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
193 addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
194
195 return addr;
196}
197
198/* iop13xx_atue_cfg_address - format a configuration address for atue
199 * @bus: Target bus to access
200 * @devfn: Combined device number and function number
201 * @where: Desired register's address offset
202 *
203 * Convert the parameters to an address usable by the ATUE_OCCAR
204 */
205static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
206{
207 struct pci_sys_data *sys = bus->sysdata;
208 u32 addr;
209
210 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
211 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
212 addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM |
213 ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
214 ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
215 (where & ~0x3);
216
217 if (sys->busnr != bus->number)
218 addr |= 1; /* type 1 access */
219
220 return addr;
221}
222
223/* This routine checks the status of the last configuration cycle. If an error
224 * was detected it returns >0, else it returns a 0. The errors being checked
225 * are parity, master abort, target abort (master and target). These types of
226 * errors occure during a config cycle where there is no device, like during
227 * the discovery stage.
228 */
229static int iop13xx_atux_pci_status(int clear)
230{
231 unsigned int status;
232 int err = 0;
233
234 /*
235 * Check the status registers.
236 */
237 status = __raw_readw(IOP13XX_ATUX_ATUSR);
238 if (status & IOP_PCI_STATUS_ERROR)
239 {
240 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
241 if(clear)
242 __raw_writew(status & IOP_PCI_STATUS_ERROR,
243 IOP13XX_ATUX_ATUSR);
244 err = 1;
245 }
246 status = __raw_readl(IOP13XX_ATUX_ATUISR);
247 if (status & IOP13XX_ATUX_ATUISR_ERROR)
248 {
249 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status);
250 if(clear)
251 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
252 IOP13XX_ATUX_ATUISR);
253 err = 1;
254 }
255 return err;
256}
257
258/* Simply write the address register and read the configuration
259 * data. Note that the data dependency on %0 encourages an abort
260 * to be detected before we return.
261 */
262static inline u32 iop13xx_atux_read(unsigned long addr)
263{
264 u32 val;
265
266 __asm__ __volatile__(
267 "str %1, [%2]\n\t"
268 "ldr %0, [%3]\n\t"
269 "mov %0, %0\n\t"
270 : "=r" (val)
271 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
272
273 return val;
274}
275
276/* The read routines must check the error status of the last configuration
277 * cycle. If there was an error, the routine returns all hex f's.
278 */
279static int
280iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
281 int size, u32 *value)
282{
283 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
284 u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
285
286 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
287 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
288 IOP13XX_XBG_BECSR);
289 val = 0xffffffff;
290 }
291
292 *value = val;
293
294 return PCIBIOS_SUCCESSFUL;
295}
296
297static int
298iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
299 int size, u32 value)
300{
301 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
302 u32 val;
303
304 if (size != 4) {
305 val = iop13xx_atux_read(addr);
306 if (!iop13xx_atux_pci_status(1) == 0)
307 return PCIBIOS_SUCCESSFUL;
308
309 where = (where & 3) * 8;
310
311 if (size == 1)
312 val &= ~(0xff << where);
313 else
314 val &= ~(0xffff << where);
315
316 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
317 } else {
318 __raw_writel(addr, IOP13XX_ATUX_OCCAR);
319 __raw_writel(value, IOP13XX_ATUX_OCCDR);
320 }
321
322 return PCIBIOS_SUCCESSFUL;
323}
324
325static struct pci_ops iop13xx_atux_ops = {
326 .read = iop13xx_atux_read_config,
327 .write = iop13xx_atux_write_config,
328};
329
330/* This routine checks the status of the last configuration cycle. If an error
331 * was detected it returns >0, else it returns a 0. The errors being checked
332 * are parity, master abort, target abort (master and target). These types of
333 * errors occure during a config cycle where there is no device, like during
334 * the discovery stage.
335 */
336static int iop13xx_atue_pci_status(int clear)
337{
338 unsigned int status;
339 int err = 0;
340
341 /*
342 * Check the status registers.
343 */
344
345 /* standard pci status register */
346 status = __raw_readw(IOP13XX_ATUE_ATUSR);
347 if (status & IOP_PCI_STATUS_ERROR) {
348 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
349 if(clear)
350 __raw_writew(status & IOP_PCI_STATUS_ERROR,
351 IOP13XX_ATUE_ATUSR);
352 err++;
353 }
354
355 /* check the normal status bits in the ATUISR */
356 status = __raw_readl(IOP13XX_ATUE_ATUISR);
357 if (status & IOP13XX_ATUE_ATUISR_ERROR) {
358 PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
359 if (clear)
360 __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
361 IOP13XX_ATUE_ATUISR);
362 err++;
363
364 /* check the PCI-E status if the ATUISR reports an interface error */
365 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
366 /* get the unmasked errors */
367 status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
368 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
369
370 if (status) {
371 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
372 __raw_readl(IOP13XX_ATUE_PIE_STS));
373 err++;
374 } else {
375 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
376 __raw_readl(IOP13XX_ATUE_PIE_STS));
377 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
378 __raw_readl(IOP13XX_ATUE_PIE_MSK));
379 BUG();
380 }
381
382 if(clear)
383 __raw_writel(status, IOP13XX_ATUE_PIE_STS);
384 }
385 }
386
387 return err;
388}
389
390static inline int __init
391iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
392{
393 WARN_ON(idsel != 0);
394
395 switch (pin) {
396 case 1: return ATUE_INTA;
397 case 2: return ATUE_INTB;
398 case 3: return ATUE_INTC;
399 case 4: return ATUE_INTD;
400 default: return -1;
401 }
402}
403
404static inline u32 iop13xx_atue_read(unsigned long addr)
405{
406 u32 val;
407
408 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
409 val = __raw_readl(IOP13XX_ATUE_OCCDR);
410
411 rmb();
412
413 return val;
414}
415
416/* The read routines must check the error status of the last configuration
417 * cycle. If there was an error, the routine returns all hex f's.
418 */
419static int
420iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
421 int size, u32 *value)
422{
423 u32 val;
424 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
425
426 /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
427 if (!PCI_SLOT(devfn) || (addr & 1)) {
428 val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
429 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
430 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
431 IOP13XX_XBG_BECSR);
432 val = 0xffffffff;
433 }
434
435 PRINTK("addr=%#0lx, val=%#010x", addr, val);
436 } else
437 val = 0xffffffff;
438
439 *value = val;
440
441 return PCIBIOS_SUCCESSFUL;
442}
443
444static int
445iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
446 int size, u32 value)
447{
448 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
449 u32 val;
450
451 if (size != 4) {
452 val = iop13xx_atue_read(addr);
453 if (!iop13xx_atue_pci_status(1) == 0)
454 return PCIBIOS_SUCCESSFUL;
455
456 where = (where & 3) * 8;
457
458 if (size == 1)
459 val &= ~(0xff << where);
460 else
461 val &= ~(0xffff << where);
462
463 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
464 } else {
465 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
466 __raw_writel(value, IOP13XX_ATUE_OCCDR);
467 }
468
469 return PCIBIOS_SUCCESSFUL;
470}
471
472static struct pci_ops iop13xx_atue_ops = {
473 .read = iop13xx_atue_read_config,
474 .write = iop13xx_atue_write_config,
475};
476
477/* When a PCI device does not exist during config cycles, the XScale gets a
478 * bus error instead of returning 0xffffffff. We can't rely on the ATU status
479 * bits to tell us that it was indeed a configuration cycle that caused this
480 * error especially in the case when the ATUE link is down. Instead we rely
481 * on data from the south XSI bridge to validate the abort
482 */
483int
484iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
485{
486 PRINTK("Data abort: address = 0x%08lx "
487 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
488 addr, fsr, regs->ARM_pc, regs->ARM_lr);
489
490 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
491 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
492 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
493
494 /* If it was an imprecise abort, then we need to correct the
495 * return address to be _after_ the instruction.
496 */
497 if (fsr & (1 << 10))
498 regs->ARM_pc += 4;
499
500 if (is_atue_occdr_error() || is_atux_occdr_error())
501 return 0;
502 else
503 return 1;
504}
505
506/* Scan an IOP13XX PCI bus. nr selects which ATU we use.
507 */
508struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
509{
510 int which_atu;
511 struct pci_bus *bus = NULL;
512
513 switch (init_atu) {
514 case IOP13XX_INIT_ATU_ATUX:
515 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
516 break;
517 case IOP13XX_INIT_ATU_ATUE:
518 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
519 break;
520 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
521 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
522 break;
523 default:
524 which_atu = 0;
525 }
526
527 if (!which_atu) {
528 BUG();
529 return NULL;
530 }
531
532 switch (which_atu) {
533 case IOP13XX_INIT_ATU_ATUX:
534 if (time_after_eq(jiffies + msecs_to_jiffies(1000),
535 atux_trhfa_timeout)) /* ensure not wrap */
536 while(time_before(jiffies, atux_trhfa_timeout))
537 udelay(100);
538
539 bus = pci_bus_atux = pci_scan_bus(sys->busnr,
540 &iop13xx_atux_ops,
541 sys);
542 break;
543 case IOP13XX_INIT_ATU_ATUE:
544 bus = pci_bus_atue = pci_scan_bus(sys->busnr,
545 &iop13xx_atue_ops,
546 sys);
547 break;
548 }
549
550 return bus;
551}
552
553/* This function is called from iop13xx_pci_init() after assigning valid
554 * values to iop13xx_atue_pmmr_offset. This is the location for common
555 * setup of ATUE for all IOP13XX implementations.
556 */
557void __init iop13xx_atue_setup(void)
558{
559 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
560 u32 reg_val;
561
562 /* BAR 1 (1:1 mapping with Physical RAM) */
563 /* Set limit and enable */
564 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
565 IOP13XX_ATUE_IALR1);
566 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
567
568 /* Set base at the top of the reserved address space */
569 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
570 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
571
572 /* 1:1 mapping with physical ram
573 * (leave big endian byte swap disabled)
574 */
575 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
576 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
577
578 /* Outbound window 1 (PCIX/PCIE memory window) */
579 /* 32 bit Address Space */
580 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
581 /* PA[35:32] */
582 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
583 (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
584 IOP13XX_ATUE_OUMBAR1);
585
586 /* Setup the I/O Bar
587 * A[35-16] in 31-12
588 */
589 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
590 IOP13XX_ATUE_OIOBAR);
591 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
592
593 /* clear startup errors */
594 iop13xx_atue_pci_status(1);
595
596 /* OIOBAR function number
597 */
598 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
599 reg_val &= ~0x7;
600 reg_val |= func;
601 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
602
603 /* OUMBAR function numbers
604 */
605 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
606 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
607 IOP13XX_ATU_OUMBAR_FUNC_NUM);
608 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
609 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
610
611 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
612 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
613 IOP13XX_ATU_OUMBAR_FUNC_NUM);
614 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
615 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
616
617 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
618 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
619 IOP13XX_ATU_OUMBAR_FUNC_NUM);
620 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
621 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
622
623 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
624 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
625 IOP13XX_ATU_OUMBAR_FUNC_NUM);
626 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
627 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
628
629 /* Enable inbound and outbound cycles
630 */
631 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
632 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
633 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
634 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
635
636 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
637 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
638 IOP13XX_ATUE_ATUCR_IVM;
639 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
640}
641
642void __init iop13xx_atue_disable(void)
643{
644 u32 reg_val;
645
646 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
647 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
648
649 /* wait for cycles to quiesce */
650 while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
651 IOP13XX_ATUE_PCSR_IN_Q_BUSY |
652 IOP13XX_ATUE_PCSR_LLRB_BUSY))
653 cpu_relax();
654
655 /* BAR 0 ( Disabled ) */
656 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
657 __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
658 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
659 __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
660 __raw_writel(0x0, IOP13XX_ATUE_IALR0);
661 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
662 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
663 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
664
665 /* BAR 1 ( Disabled ) */
666 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
667 __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
668 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
669 __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
670 __raw_writel(0x0, IOP13XX_ATUE_IALR1);
671 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
672 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
673 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
674
675 /* BAR 2 ( Disabled ) */
676 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
677 __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
678 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
679 __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
680 __raw_writel(0x0, IOP13XX_ATUE_IALR2);
681 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
682 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
683 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
684
685 /* BAR 3 ( Disabled ) */
686 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
687 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
688 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
689
690 /* Setup the I/O Bar
691 * A[35-16] in 31-12
692 */
693 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
694 IOP13XX_ATUE_OIOBAR);
695 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
696}
697
698/* This function is called from iop13xx_pci_init() after assigning valid
699 * values to iop13xx_atux_pmmr_offset. This is the location for common
700 * setup of ATUX for all IOP13XX implementations.
701 */
702void __init iop13xx_atux_setup(void)
703{
704 u32 reg_val;
705 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
706
707 /* Take PCI-X bus out of reset if bootloader hasn't already.
708 * According to spec, we should wait for 2^25 PCI clocks to meet
709 * the PCI timing parameter Trhfa (RST# high to first access).
710 * This is rarely necessary and often ignored.
711 */
712 reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
713 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
714 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
715 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
716 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
717 IOP13XX_ATUX_PCSR);
718 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
719 }
720 else
721 atux_trhfa_timeout = jiffies;
722
723 /* BAR 1 (1:1 mapping with Physical RAM) */
724 /* Set limit and enable */
725 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
726 IOP13XX_ATUX_IALR1);
727 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
728
729 /* Set base at the top of the reserved address space */
730 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
731 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
732
733 /* 1:1 mapping with physical ram
734 * (leave big endian byte swap disabled)
735 */
736 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
737 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
738
739 /* Outbound window 1 (PCIX/PCIE memory window) */
740 /* 32 bit Address Space */
741 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
742 /* PA[35:32] */
743 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
744 IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
745 IOP13XX_ATUX_OUMBAR1);
746
747 /* Setup the I/O Bar
748 * A[35-16] in 31-12
749 */
750 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
751 IOP13XX_ATUX_OIOBAR);
752 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
753
754 /* clear startup errors */
755 iop13xx_atux_pci_status(1);
756
757 /* OIOBAR function number
758 */
759 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
760 reg_val &= ~0x7;
761 reg_val |= func;
762 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
763
764 /* OUMBAR function numbers
765 */
766 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
767 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
768 IOP13XX_ATU_OUMBAR_FUNC_NUM);
769 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
770 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
771
772 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
773 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
774 IOP13XX_ATU_OUMBAR_FUNC_NUM);
775 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
776 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
777
778 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
779 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
780 IOP13XX_ATU_OUMBAR_FUNC_NUM);
781 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
782 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
783
784 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
785 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
786 IOP13XX_ATU_OUMBAR_FUNC_NUM);
787 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
788 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
789
790 /* Enable inbound and outbound cycles
791 */
792 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
793 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
794 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
795 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
796
797 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
798 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
799 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
800}
801
802void __init iop13xx_atux_disable(void)
803{
804 u32 reg_val;
805
806 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
807 __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
808
809 /* wait for cycles to quiesce */
810 while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
811 IOP13XX_ATUX_PCSR_IN_Q_BUSY))
812 cpu_relax();
813
814 /* BAR 0 ( Disabled ) */
815 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
816 __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
817 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
818 __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
819 __raw_writel(0x0, IOP13XX_ATUX_IALR0);
820 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
821 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
822 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
823
824 /* BAR 1 ( Disabled ) */
825 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
826 __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
827 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
828 __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
829 __raw_writel(0x0, IOP13XX_ATUX_IALR1);
830 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
831 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
832 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
833
834 /* BAR 2 ( Disabled ) */
835 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
836 __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
837 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
838 __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
839 __raw_writel(0x0, IOP13XX_ATUX_IALR2);
840 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
841 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
842 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
843
844 /* BAR 3 ( Disabled ) */
845 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
846 __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
847 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
848 __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
849 __raw_writel(0x0, IOP13XX_ATUX_IALR3);
850 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
851 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
852 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
853
854 /* Setup the I/O Bar
855 * A[35-16] in 31-12
856 */
857 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
858 IOP13XX_ATUX_OIOBAR);
859 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
860}
861
862void __init iop13xx_set_atu_mmr_bases(void)
863{
864 /* Based on ESSR0, determine the ATU X/E offsets */
865 switch(__raw_readl(IOP13XX_ESSR0) &
866 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
867 /* both asserted */
868 case 0:
869 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
870 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
871 break;
872 /* IOP13XX_CONTROLLER_ONLY = deasserted
873 * IOP13XX_INTERFACE_SEL_PCIX = asserted
874 */
875 case IOP13XX_CONTROLLER_ONLY:
876 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
877 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
878 break;
879 /* IOP13XX_CONTROLLER_ONLY = asserted
880 * IOP13XX_INTERFACE_SEL_PCIX = deasserted
881 */
882 case IOP13XX_INTERFACE_SEL_PCIX:
883 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
884 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
885 break;
886 /* both deasserted */
887 case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
888 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
889 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
890 break;
891 default:
892 BUG();
893 }
894}
895
896void __init iop13xx_atu_select(struct hw_pci *plat_pci)
897{
898 int i;
899
900 /* set system defaults
901 * note: if "iop13xx_init_atu=" is specified this autodetect
902 * sequence will be bypassed
903 */
904 if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
905 /* check for single/dual interface */
906 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
907 /* ATUE must be present check the device id
908 * to see if ATUX is present.
909 */
910 init_atu |= IOP13XX_INIT_ATU_ATUE;
911 switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
912 case 0x70:
913 case 0x80:
914 case 0xc0:
915 init_atu |= IOP13XX_INIT_ATU_ATUX;
916 break;
917 }
918 } else {
919 /* ATUX must be present check the device id
920 * to see if ATUE is present.
921 */
922 init_atu |= IOP13XX_INIT_ATU_ATUX;
923 switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
924 case 0x70:
925 case 0x80:
926 case 0xc0:
927 init_atu |= IOP13XX_INIT_ATU_ATUE;
928 break;
929 }
930 }
931
932 /* check central resource and root complex capability */
933 if (init_atu & IOP13XX_INIT_ATU_ATUX)
934 if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
935 IOP13XX_ATUX_PCSR_CENTRAL_RES))
936 init_atu &= ~IOP13XX_INIT_ATU_ATUX;
937
938 if (init_atu & IOP13XX_INIT_ATU_ATUE)
939 if (__raw_readl(IOP13XX_ATUE_PCSR) &
940 IOP13XX_ATUE_PCSR_END_POINT)
941 init_atu &= ~IOP13XX_INIT_ATU_ATUE;
942 }
943
944 for (i = 0; i < 2; i++) {
945 if((init_atu & (1 << i)) == (1 << i))
946 plat_pci->nr_controllers++;
947 }
948}
949
950void __init iop13xx_pci_init(void)
951{
952 /* clear pre-existing south bridge errors */
953 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
954
955 /* Setup the Min Address for PCI memory... */
956 iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
957
958 /* if Linux is given control of an ATU
959 * clear out its prior configuration,
960 * otherwise do not touch the registers
961 */
962 if (init_atu & IOP13XX_INIT_ATU_ATUE) {
963 iop13xx_atue_disable();
964 iop13xx_atue_setup();
965 }
966
967 if (init_atu & IOP13XX_INIT_ATU_ATUX) {
968 iop13xx_atux_disable();
969 iop13xx_atux_setup();
970 }
971
972 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS,
973 "imprecise external abort");
974}
975
976/* intialize the pci memory space. handle any combination of
977 * atue and atux enabled/disabled
978 */
979int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
980{
981 struct resource *res;
982 int which_atu;
983 u32 pcixsr, pcsr;
984
985 if (nr > 1)
986 return 0;
987
988 res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
989 if (!res)
990 panic("PCI: unable to alloc resources");
991
992 memset(res, 0, sizeof(struct resource) * 2);
993
994 /* 'nr' assumptions:
995 * ATUX is always 0
996 * ATUE is 1 when ATUX is also enabled
997 * ATUE is 0 when ATUX is disabled
998 */
999 switch(init_atu) {
1000 case IOP13XX_INIT_ATU_ATUX:
1001 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
1002 break;
1003 case IOP13XX_INIT_ATU_ATUE:
1004 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
1005 break;
1006 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
1007 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
1008 break;
1009 default:
1010 which_atu = 0;
1011 }
1012
1013 if (!which_atu)
1014 return 0;
1015
1016 switch(which_atu) {
1017 case IOP13XX_INIT_ATU_ATUX:
1018 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
1019 pcixsr &= ~0xffff;
1020 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
1021 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
1022 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
1023 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1024 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1025
1026 res[0].start = IOP13XX_PCIX_LOWER_IO_PA;
1027 res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
1028 res[0].name = "IQ81340 ATUX PCI I/O Space";
1029 res[0].flags = IORESOURCE_IO;
1030
1031 res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
1032 res[1].end = IOP13XX_PCIX_UPPER_MEM_RA;
1033 res[1].name = "IQ81340 ATUX PCI Memory Space";
1034 res[1].flags = IORESOURCE_MEM;
1035 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1036 sys->io_offset = IOP13XX_PCIX_IO_OFFSET;
1037 break;
1038 case IOP13XX_INIT_ATU_ATUE:
1039 /* Note: the function number field in the PCSR is ro */
1040 pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
1041 pcsr &= ~(0xfff8 << 16);
1042 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
1043 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
1044
1045 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1046
1047 res[0].start = IOP13XX_PCIE_LOWER_IO_PA;
1048 res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
1049 res[0].name = "IQ81340 ATUE PCI I/O Space";
1050 res[0].flags = IORESOURCE_IO;
1051
1052 res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
1053 res[1].end = IOP13XX_PCIE_UPPER_MEM_RA;
1054 res[1].name = "IQ81340 ATUE PCI Memory Space";
1055 res[1].flags = IORESOURCE_MEM;
1056 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1057 sys->io_offset = IOP13XX_PCIE_IO_OFFSET;
1058 sys->map_irq = iop13xx_pcie_map_irq;
1059 break;
1060 default:
1061 return 0;
1062 }
1063
1064 request_resource(&ioport_resource, &res[0]);
1065 request_resource(&iomem_resource, &res[1]);
1066
1067 sys->resource[0] = &res[0];
1068 sys->resource[1] = &res[1];
1069 sys->resource[2] = NULL;
1070
1071 return 1;
1072}
1073
1074u16 iop13xx_dev_id(void)
1075{
1076 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
1077 return __raw_readw(IOP13XX_ATUE_DID);
1078 else
1079 return __raw_readw(IOP13XX_ATUX_DID);
1080}
1081
1082static int __init iop13xx_init_atu_setup(char *str)
1083{
1084 init_atu = IOP13XX_INIT_ATU_NONE;
1085 if (str) {
1086 while (*str != '\0') {
1087 switch (*str) {
1088 case 'x':
1089 case 'X':
1090 init_atu |= IOP13XX_INIT_ATU_ATUX;
1091 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1092 break;
1093 case 'e':
1094 case 'E':
1095 init_atu |= IOP13XX_INIT_ATU_ATUE;
1096 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1097 break;
1098 case ',':
1099 case '=':
1100 break;
1101 default:
1102 PRINTK("\"iop13xx_init_atu\" malformed at "
1103 "character: \'%c\'", *str);
1104 *(str + 1) = '\0';
1105 init_atu = IOP13XX_INIT_ATU_DEFAULT;
1106 }
1107 str++;
1108 }
1109 }
1110 return 1;
1111}
1112
1113__setup("iop13xx_init_atu", iop13xx_init_atu_setup);
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
new file mode 100644
index 000000000000..3756d2ccb1a7
--- /dev/null
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -0,0 +1,406 @@
1/*
2 * iop13xx platform Initialization
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19
20#include <linux/serial_8250.h>
21#ifdef CONFIG_MTD_PHYSMAP
22#include <linux/mtd/physmap.h>
23#endif
24#include <asm/mach/map.h>
25#include <asm/hardware.h>
26#include <asm/irq.h>
27
28#define IOP13XX_UART_XTAL 33334000
29#define IOP13XX_SETUP_DEBUG 0
30#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
31
32/* Standard IO mapping for all IOP13XX based systems
33 */
34static struct map_desc iop13xx_std_desc[] __initdata = {
35 { /* mem mapped registers */
36 .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
37 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
38 .length = IOP13XX_PMMR_SIZE,
39 .type = MT_DEVICE,
40 }, { /* PCIE IO space */
41 .virtual = IOP13XX_PCIE_LOWER_IO_VA,
42 .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
43 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
44 .type = MT_DEVICE,
45 }, { /* PCIX IO space */
46 .virtual = IOP13XX_PCIX_LOWER_IO_VA,
47 .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
48 .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
49 .type = MT_DEVICE,
50 },
51};
52
53static struct resource iop13xx_uart0_resources[] = {
54 [0] = {
55 .start = IOP13XX_UART0_PHYS,
56 .end = IOP13XX_UART0_PHYS + 0x3f,
57 .flags = IORESOURCE_MEM,
58 },
59 [1] = {
60 .start = IRQ_IOP13XX_UART0,
61 .end = IRQ_IOP13XX_UART0,
62 .flags = IORESOURCE_IRQ
63 }
64};
65
66static struct resource iop13xx_uart1_resources[] = {
67 [0] = {
68 .start = IOP13XX_UART1_PHYS,
69 .end = IOP13XX_UART1_PHYS + 0x3f,
70 .flags = IORESOURCE_MEM,
71 },
72 [1] = {
73 .start = IRQ_IOP13XX_UART1,
74 .end = IRQ_IOP13XX_UART1,
75 .flags = IORESOURCE_IRQ
76 }
77};
78
79static struct plat_serial8250_port iop13xx_uart0_data[] = {
80 {
81 .membase = (char*)(IOP13XX_UART0_VIRT),
82 .mapbase = (IOP13XX_UART0_PHYS),
83 .irq = IRQ_IOP13XX_UART0,
84 .uartclk = IOP13XX_UART_XTAL,
85 .regshift = 2,
86 .iotype = UPIO_MEM,
87 .flags = UPF_SKIP_TEST,
88 },
89 { },
90};
91
92static struct plat_serial8250_port iop13xx_uart1_data[] = {
93 {
94 .membase = (char*)(IOP13XX_UART1_VIRT),
95 .mapbase = (IOP13XX_UART1_PHYS),
96 .irq = IRQ_IOP13XX_UART1,
97 .uartclk = IOP13XX_UART_XTAL,
98 .regshift = 2,
99 .iotype = UPIO_MEM,
100 .flags = UPF_SKIP_TEST,
101 },
102 { },
103};
104
105/* The ids are fixed up later in iop13xx_platform_init */
106static struct platform_device iop13xx_uart0 = {
107 .name = "serial8250",
108 .id = 0,
109 .dev.platform_data = iop13xx_uart0_data,
110 .num_resources = 2,
111 .resource = iop13xx_uart0_resources,
112};
113
114static struct platform_device iop13xx_uart1 = {
115 .name = "serial8250",
116 .id = 0,
117 .dev.platform_data = iop13xx_uart1_data,
118 .num_resources = 2,
119 .resource = iop13xx_uart1_resources
120};
121
122static struct resource iop13xx_i2c_0_resources[] = {
123 [0] = {
124 .start = IOP13XX_I2C0_PHYS,
125 .end = IOP13XX_I2C0_PHYS + 0x18,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = IRQ_IOP13XX_I2C_0,
130 .end = IRQ_IOP13XX_I2C_0,
131 .flags = IORESOURCE_IRQ
132 }
133};
134
135static struct resource iop13xx_i2c_1_resources[] = {
136 [0] = {
137 .start = IOP13XX_I2C1_PHYS,
138 .end = IOP13XX_I2C1_PHYS + 0x18,
139 .flags = IORESOURCE_MEM,
140 },
141 [1] = {
142 .start = IRQ_IOP13XX_I2C_1,
143 .end = IRQ_IOP13XX_I2C_1,
144 .flags = IORESOURCE_IRQ
145 }
146};
147
148static struct resource iop13xx_i2c_2_resources[] = {
149 [0] = {
150 .start = IOP13XX_I2C2_PHYS,
151 .end = IOP13XX_I2C2_PHYS + 0x18,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = IRQ_IOP13XX_I2C_2,
156 .end = IRQ_IOP13XX_I2C_2,
157 .flags = IORESOURCE_IRQ
158 }
159};
160
161/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
162 * we just use the same device name.
163 */
164
165/* The ids are fixed up later in iop13xx_platform_init */
166static struct platform_device iop13xx_i2c_0_controller = {
167 .name = "IOP3xx-I2C",
168 .id = 0,
169 .num_resources = 2,
170 .resource = iop13xx_i2c_0_resources
171};
172
173static struct platform_device iop13xx_i2c_1_controller = {
174 .name = "IOP3xx-I2C",
175 .id = 0,
176 .num_resources = 2,
177 .resource = iop13xx_i2c_1_resources
178};
179
180static struct platform_device iop13xx_i2c_2_controller = {
181 .name = "IOP3xx-I2C",
182 .id = 0,
183 .num_resources = 2,
184 .resource = iop13xx_i2c_2_resources
185};
186
187#ifdef CONFIG_MTD_PHYSMAP
188/* PBI Flash Device
189 */
190static struct physmap_flash_data iq8134x_flash_data = {
191 .width = 2,
192};
193
194static struct resource iq8134x_flash_resource = {
195 .start = IQ81340_FLASHBASE,
196 .end = 0,
197 .flags = IORESOURCE_MEM,
198};
199
200static struct platform_device iq8134x_flash = {
201 .name = "physmap-flash",
202 .id = 0,
203 .dev = { .platform_data = &iq8134x_flash_data, },
204 .num_resources = 1,
205 .resource = &iq8134x_flash_resource,
206};
207
208static unsigned long iq8134x_probe_flash_size(void)
209{
210 uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
211 int i;
212 char query[3];
213 unsigned long size = 0;
214 int width = iq8134x_flash_data.width;
215
216 if (flash_addr) {
217 /* send CFI 'query' command */
218 writew(0x98, flash_addr);
219
220 /* check for CFI compliance */
221 for (i = 0; i < 3 * width; i += width)
222 query[i / width] = readb(flash_addr + (0x10 * width) + i);
223
224 /* read the size */
225 if (memcmp(query, "QRY", 3) == 0)
226 size = 1 << readb(flash_addr + (0x27 * width));
227
228 /* send CFI 'read array' command */
229 writew(0xff, flash_addr);
230
231 iounmap(flash_addr);
232 }
233
234 return size;
235}
236#endif
237
238void __init iop13xx_map_io(void)
239{
240 /* Initialize the Static Page Table maps */
241 iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
242}
243
244static int init_uart = 0;
245static int init_i2c = 0;
246
247void __init iop13xx_platform_init(void)
248{
249 int i;
250 u32 uart_idx, i2c_idx, plat_idx;
251 struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
252
253 /* set the bases so we can read the device id */
254 iop13xx_set_atu_mmr_bases();
255
256 memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
257
258 if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
259 switch (iop13xx_dev_id()) {
260 /* enable both uarts on iop341 and iop342 */
261 case 0x3380:
262 case 0x3384:
263 case 0x3388:
264 case 0x338c:
265 case 0x3382:
266 case 0x3386:
267 case 0x338a:
268 case 0x338e:
269 init_uart |= IOP13XX_INIT_UART_0;
270 init_uart |= IOP13XX_INIT_UART_1;
271 break;
272 /* only enable uart 1 */
273 default:
274 init_uart |= IOP13XX_INIT_UART_1;
275 }
276 }
277
278 if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
279 switch (iop13xx_dev_id()) {
280 /* enable all i2c units on iop341 and iop342 */
281 case 0x3380:
282 case 0x3384:
283 case 0x3388:
284 case 0x338c:
285 case 0x3382:
286 case 0x3386:
287 case 0x338a:
288 case 0x338e:
289 init_i2c |= IOP13XX_INIT_I2C_0;
290 init_i2c |= IOP13XX_INIT_I2C_1;
291 init_i2c |= IOP13XX_INIT_I2C_2;
292 break;
293 /* only enable i2c 1 and 2 */
294 default:
295 init_i2c |= IOP13XX_INIT_I2C_1;
296 init_i2c |= IOP13XX_INIT_I2C_2;
297 }
298 }
299
300 plat_idx = 0;
301 uart_idx = 0;
302 i2c_idx = 0;
303
304 /* uart 1 (if enabled) is ttyS0 */
305 if (init_uart & IOP13XX_INIT_UART_1) {
306 PRINTK("Adding uart1 to platform device list\n");
307 iop13xx_uart1.id = uart_idx++;
308 iop13xx_devices[plat_idx++] = &iop13xx_uart1;
309 }
310 if (init_uart & IOP13XX_INIT_UART_0) {
311 PRINTK("Adding uart0 to platform device list\n");
312 iop13xx_uart0.id = uart_idx++;
313 iop13xx_devices[plat_idx++] = &iop13xx_uart0;
314 }
315
316 for(i = 0; i < IQ81340_NUM_I2C; i++) {
317 if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
318 printk("Adding i2c%d to platform device list\n", i);
319 switch(init_i2c & (1 << i)) {
320 case IOP13XX_INIT_I2C_0:
321 iop13xx_i2c_0_controller.id = i2c_idx++;
322 iop13xx_devices[plat_idx++] =
323 &iop13xx_i2c_0_controller;
324 break;
325 case IOP13XX_INIT_I2C_1:
326 iop13xx_i2c_1_controller.id = i2c_idx++;
327 iop13xx_devices[plat_idx++] =
328 &iop13xx_i2c_1_controller;
329 break;
330 case IOP13XX_INIT_I2C_2:
331 iop13xx_i2c_2_controller.id = i2c_idx++;
332 iop13xx_devices[plat_idx++] =
333 &iop13xx_i2c_2_controller;
334 break;
335 }
336 }
337
338#ifdef CONFIG_MTD_PHYSMAP
339 iq8134x_flash_resource.end = iq8134x_flash_resource.start +
340 iq8134x_probe_flash_size();
341 if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
342 iop13xx_devices[plat_idx++] = &iq8134x_flash;
343 else
344 printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
345#endif
346
347 platform_add_devices(iop13xx_devices, plat_idx);
348}
349
350static int __init iop13xx_init_uart_setup(char *str)
351{
352 if (str) {
353 while (*str != '\0') {
354 switch(*str) {
355 case '0':
356 init_uart |= IOP13XX_INIT_UART_0;
357 break;
358 case '1':
359 init_uart |= IOP13XX_INIT_UART_1;
360 break;
361 case ',':
362 case '=':
363 break;
364 default:
365 PRINTK("\"iop13xx_init_uart\" malformed"
366 " at character: \'%c\'", *str);
367 *(str + 1) = '\0';
368 init_uart = IOP13XX_INIT_UART_DEFAULT;
369 }
370 str++;
371 }
372 }
373 return 1;
374}
375
376static int __init iop13xx_init_i2c_setup(char *str)
377{
378 if (str) {
379 while (*str != '\0') {
380 switch(*str) {
381 case '0':
382 init_i2c |= IOP13XX_INIT_I2C_0;
383 break;
384 case '1':
385 init_i2c |= IOP13XX_INIT_I2C_1;
386 break;
387 case '2':
388 init_i2c |= IOP13XX_INIT_I2C_2;
389 break;
390 case ',':
391 case '=':
392 break;
393 default:
394 PRINTK("\"iop13xx_init_i2c\" malformed"
395 " at character: \'%c\'", *str);
396 *(str + 1) = '\0';
397 init_i2c = IOP13XX_INIT_I2C_DEFAULT;
398 }
399 str++;
400 }
401 }
402 return 1;
403}
404
405__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
406__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
diff --git a/arch/arm/mach-iop13xx/time.c b/arch/arm/mach-iop13xx/time.c
new file mode 100644
index 000000000000..8b21365f653f
--- /dev/null
+++ b/arch/arm/mach-iop13xx/time.c
@@ -0,0 +1,102 @@
1/*
2 * arch/arm/mach-iop13xx/time.c
3 *
4 * Timer code for IOP13xx (copied from IOP32x/IOP33x implementation)
5 *
6 * Author: Deepak Saxena <dsaxena@mvista.com>
7 *
8 * Copyright 2002-2003 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/time.h>
19#include <linux/init.h>
20#include <linux/timex.h>
21#include <asm/io.h>
22#include <asm/irq.h>
23#include <asm/uaccess.h>
24#include <asm/mach/irq.h>
25#include <asm/mach/time.h>
26
27static unsigned long ticks_per_jiffy;
28static unsigned long ticks_per_usec;
29static unsigned long next_jiffy_time;
30
31static inline u32 read_tcr1(void)
32{
33 u32 val;
34 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
35 return val;
36}
37
38unsigned long iop13xx_gettimeoffset(void)
39{
40 unsigned long offset;
41 u32 cp_flags;
42
43 cp_flags = iop13xx_cp6_save();
44 offset = next_jiffy_time - read_tcr1();
45 iop13xx_cp6_restore(cp_flags);
46
47 return offset / ticks_per_usec;
48}
49
50static irqreturn_t
51iop13xx_timer_interrupt(int irq, void *dev_id)
52{
53 u32 cp_flags = iop13xx_cp6_save();
54
55 write_seqlock(&xtime_lock);
56
57 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
58
59 while ((signed long)(next_jiffy_time - read_tcr1())
60 >= ticks_per_jiffy) {
61 timer_tick();
62 next_jiffy_time -= ticks_per_jiffy;
63 }
64
65 write_sequnlock(&xtime_lock);
66
67 iop13xx_cp6_restore(cp_flags);
68
69 return IRQ_HANDLED;
70}
71
72static struct irqaction iop13xx_timer_irq = {
73 .name = "IOP13XX Timer Tick",
74 .handler = iop13xx_timer_interrupt,
75 .flags = IRQF_DISABLED | IRQF_TIMER,
76};
77
78void __init iop13xx_init_time(unsigned long tick_rate)
79{
80 u32 timer_ctl;
81 u32 cp_flags;
82
83 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
84 ticks_per_usec = tick_rate / 1000000;
85 next_jiffy_time = 0xffffffff;
86
87 timer_ctl = IOP13XX_TMR_EN | IOP13XX_TMR_PRIVILEGED |
88 IOP13XX_TMR_RELOAD | IOP13XX_TMR_RATIO_1_1;
89
90 /*
91 * We use timer 0 for our timer interrupt, and timer 1 as
92 * monotonic counter for tracking missed jiffies.
93 */
94 cp_flags = iop13xx_cp6_save();
95 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
96 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
97 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
98 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
99 iop13xx_cp6_restore(cp_flags);
100
101 setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
102}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c0bfb8212b77..4c4dae6901fc 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -333,7 +333,7 @@ config CPU_XSCALE
333# XScale Core Version 3 333# XScale Core Version 3
334config CPU_XSC3 334config CPU_XSC3
335 bool 335 bool
336 depends on ARCH_IXP23XX 336 depends on ARCH_IXP23XX || ARCH_IOP13XX
337 default y 337 default y
338 select CPU_32v5 338 select CPU_32v5
339 select CPU_ABRT_EV5T 339 select CPU_ABRT_EV5T
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 510816c16da3..5cbf8b9d5141 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -195,11 +195,11 @@ config I2C_IBM_IIC
195 will be called i2c-ibm_iic. 195 will be called i2c-ibm_iic.
196 196
197config I2C_IOP3XX 197config I2C_IOP3XX
198 tristate "Intel IOP3xx and IXP4xx on-chip I2C interface" 198 tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface"
199 depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX) && I2C 199 depends on (ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX) && I2C
200 help 200 help
201 Say Y here if you want to use the IIC bus controller on 201 Say Y here if you want to use the IIC bus controller on
202 the Intel IOP3xx I/O Processors or IXP4xx Network Processors. 202 the Intel IOPx3xx I/O Processors or IXP4xx Network Processors.
203 203
204 This driver can also be built as a module. If so, the module 204 This driver can also be built as a module. If so, the module
205 will be called i2c-iop3xx. 205 will be called i2c-iop3xx.
diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S
new file mode 100644
index 000000000000..788b4e386c16
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/debug-macro.S
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-iop13xx/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 .macro addruart, rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ mmu enabled?
17 moveq \rx, #0xff000000 @ physical
18 orreq \rx, \rx, #0x00d80000
19 movne \rx, #0xfe000000 @ virtual
20 orrne \rx, \rx, #0x00e80000
21 orr \rx, \rx, #0x00002300
22 orr \rx, \rx, #0x00000040
23 .endm
24
25#define UART_SHIFT 2
26#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
new file mode 100644
index 000000000000..2e15da53ff79
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -0,0 +1,3 @@
1#ifndef _IOP13XX_DMA_H
2#define _IOP13XX_DMA_H_
3#endif
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S
new file mode 100644
index 000000000000..94c50283dc56
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * iop13xx low level irq macros
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 .macro disable_fiq
20 .endm
21
22 /*
23 * Note: a 1-cycle window exists where iintvec will return the value
24 * of iintbase, so we explicitly check for "bad zeros"
25 */
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 mrc p15, 0, \tmp, c15, c1, 0
28 orr \tmp, \tmp, #(1 << 6)
29 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
30
31 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
32 cmp \irqnr, #0
33 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
34 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
35 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
36
37 biceq \tmp, \tmp, #(1 << 6)
38 mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts
39 .endm
diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h
new file mode 100644
index 000000000000..8e1d56289846
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/hardware.h
@@ -0,0 +1,28 @@
1#ifndef __ASM_ARCH_HARDWARE_H
2#define __ASM_ARCH_HARDWARE_H
3#include <asm/types.h>
4
5#define pcibios_assign_all_busses() 1
6
7#ifndef __ASSEMBLY__
8extern unsigned long iop13xx_pcibios_min_io;
9extern unsigned long iop13xx_pcibios_min_mem;
10extern u16 iop13xx_dev_id(void);
11extern void iop13xx_set_atu_mmr_bases(void);
12#endif
13
14#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io)
15#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem)
16
17/*
18 * Generic chipset bits
19 *
20 */
21#include "iop13xx.h"
22
23/*
24 * Board specific bits
25 */
26#include "iq81340.h"
27
28#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h
new file mode 100644
index 000000000000..db6de2480a24
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/io.h
@@ -0,0 +1,41 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARM_ARCH_IO_H
21
22#define IO_SPACE_LIMIT 0xffffffff
23
24#define __io(a) (a)
25#define __mem_pci(a) (a)
26#define __mem_isa(a) (a)
27
28extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
29extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
30 unsigned long flags);
31extern void __iop13xx_iounmap(void __iomem *addr);
32
33extern u32 iop13xx_atue_mem_base;
34extern u32 iop13xx_atux_mem_base;
35extern size_t iop13xx_atue_mem_size;
36extern size_t iop13xx_atux_mem_size;
37
38#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
39#define __arch_iounmap(a) __iop13xx_iounmap(a)
40
41#endif
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
new file mode 100644
index 000000000000..a88522a0ff8e
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -0,0 +1,492 @@
1#ifndef _IOP13XX_HW_H_
2#define _IOP13XX_HW_H_
3
4#ifndef __ASSEMBLY__
5/* The ATU offsets can change based on the strapping */
6extern u32 iop13xx_atux_pmmr_offset;
7extern u32 iop13xx_atue_pmmr_offset;
8void iop13xx_init_irq(void);
9void iop13xx_map_io(void);
10void iop13xx_platform_init(void);
11void iop13xx_init_irq(void);
12void iop13xx_init_time(unsigned long tickrate);
13unsigned long iop13xx_gettimeoffset(void);
14
15/* handle cp6 access
16 * to do: handle access in entry-armv5.S and unify with
17 * the iop3xx implementation
18 * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
19 * when interrupts are enabled
20 */
21static inline unsigned long iop13xx_cp6_save(void)
22{
23 u32 temp, cp_flags;
24
25 asm volatile (
26 "mrc p15, 0, %1, c15, c1, 0\n\t"
27 "orr %0, %1, #(1 << 6)\n\t"
28 "mcr p15, 0, %0, c15, c1, 0\n\t"
29 : "=r" (temp), "=r"(cp_flags));
30
31 return cp_flags;
32}
33
34static inline void iop13xx_cp6_restore(unsigned long cp_flags)
35{
36 asm volatile (
37 "mcr p15, 0, %0, c15, c1, 0\n\t"
38 : : "r" (cp_flags) );
39}
40
41/* CPUID CP6 R0 Page 0 */
42static inline int iop13xx_cpu_id(void)
43{
44 int id;
45 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
46 return id;
47}
48
49#endif
50
51/*
52 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
53 */
54#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
55#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
56
57/* PCI MAP
58 * 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM
59 * 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB)
60*/
61#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
62#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
63#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
64#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL
65#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
66 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
67#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
68 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
69#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\
70 IOP13XX_PCIX_LOWER_IO_BA)
71#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
72 (IOP13XX_PCIX_LOWER_IO_PA\
73 - IOP13XX_PCIX_LOWER_IO_VA))
74
75#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
76#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
77#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
78#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
79 IOP13XX_PCIX_LOWER_MEM_BA)
80#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
81 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
82#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
83 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
84
85#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
86#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
87#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
88 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
89#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
90 IOP13XX_PCIX_LOWER_MEM_BA)
91
92/* PCI-E ranges */
93#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
94#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
95#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
96#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL
97#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
98 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
99#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
100 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
101#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
102 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
103#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\
104 IOP13XX_PCIE_LOWER_IO_BA)
105#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
106 (IOP13XX_PCIE_LOWER_IO_PA\
107 - IOP13XX_PCIE_LOWER_IO_VA))
108
109#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
110#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
111#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
112#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
113 IOP13XX_PCIE_LOWER_MEM_BA)
114#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
115 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
116#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
117 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
118
119/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
120#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
121#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
122#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
123 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
124#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
125 IOP13XX_PCIE_LOWER_MEM_BA)
126
127/* PBI Ranges */
128#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
129#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
130#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
131#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
132#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
133 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
134
135/*
136 * IOP13XX chipset registers
137 */
138#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
139#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
140#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
141#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
142 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
143#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
144 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
145#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
146 (IOP13XX_PMMR_PHYS_MEM_BASE\
147 - IOP13XX_PMMR_VIRT_MEM_BASE))
148#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
149 (IOP13XX_PMMR_PHYS_MEM_BASE\
150 - IOP13XX_PMMR_VIRT_MEM_BASE))
151#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
152#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
153#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
154#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
155#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
156#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
157#define IOP13XX_PMMR_SIZE 0x00080000
158
159/*=================== Defines for Platform Devices =====================*/
160#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
161#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
162#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
163#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
164
165#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
166#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
167#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
168#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
169#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
170#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
171
172/* ATU selection flags */
173/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
174#define IOP13XX_INIT_ATU_DEFAULT (0)
175#define IOP13XX_INIT_ATU_ATUX (1 << 0)
176#define IOP13XX_INIT_ATU_ATUE (1 << 1)
177#define IOP13XX_INIT_ATU_NONE (1 << 2)
178
179/* UART selection flags */
180/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
181#define IOP13XX_INIT_UART_DEFAULT (0)
182#define IOP13XX_INIT_UART_0 (1 << 0)
183#define IOP13XX_INIT_UART_1 (1 << 1)
184
185/* I2C selection flags */
186/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
187#define IOP13XX_INIT_I2C_DEFAULT (0)
188#define IOP13XX_INIT_I2C_0 (1 << 0)
189#define IOP13XX_INIT_I2C_1 (1 << 1)
190#define IOP13XX_INIT_I2C_2 (1 << 2)
191
192#define IQ81340_NUM_UART 2
193#define IQ81340_NUM_I2C 3
194#define IQ81340_NUM_PHYS_MAP_FLASH 1
195#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
196 IQ81340_NUM_I2C +\
197 IQ81340_NUM_PHYS_MAP_FLASH)
198
199/*========================== PMMR offsets for key registers ============*/
200#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
201#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
202#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
203#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
204#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
205#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
206#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
207#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
208#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
209
210#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
211#define IOP13XX_CONTROLLER_ONLY (1 << 14)
212#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
213
214#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
215#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
216 IOP13XX_PMON_PMMR_OFFSET)
217#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
218 IOP13XX_PMON_PMMR_OFFSET)
219
220#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
221#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
222#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
223#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
224
225#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
226#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
227#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
228#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
229
230#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
231#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
232#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
233#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
234
235#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
236#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
237
238/*================================ATU===================================*/
239#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
240 iop13xx_atux_pmmr_offset + (ofs))
241
242#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
243 iop13xx_atux_pmmr_offset + 0x2)
244
245#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
246 iop13xx_atux_pmmr_offset + 0x4)
247#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
248 iop13xx_atux_pmmr_offset + 0x6)
249
250#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
251#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
252#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
253#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
254#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
255#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
256#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
257#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
258#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
259#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
260#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
261#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
262#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
263#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
264#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
265#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
266#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
267#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
268#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
269#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
270#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
271#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
272#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
273#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
274
275#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
276#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
277#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
278#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
279#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
280#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
281#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
282#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
283#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
284#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
285#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
286#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
287#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
288#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
289
290#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
291#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
292#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
293#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
294#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
295#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
296
297#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
298#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
299#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
300#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
301#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
302#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
303#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
304#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
305#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
306#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
307#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
308#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
309#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
310#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
311#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
312#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
313#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
314
315#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
316#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
317#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
318
319#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
320#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
321
322#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
323 iop13xx_atue_pmmr_offset + (ofs))
324
325#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
326 iop13xx_atue_pmmr_offset + 0x2)
327#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
328 iop13xx_atue_pmmr_offset + 0x4)
329#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
330 iop13xx_atue_pmmr_offset + 0x6)
331
332#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
333#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
334#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
335#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
336#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
337#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
338#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
339#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
340#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
341#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
342#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
343#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
344#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
345#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
346#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
347#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
348 iop13xx_atue_pmmr_offset + 0xe2)
349#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
350#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
351#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
352#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
353#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
354#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
355#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
356#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
357#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
358
359#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
360#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
361#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
362#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
363#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
364#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
365
366#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
367#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
368
369#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
370#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
371#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
372#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
373#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
374#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
375#define IOP13XX_ATUE_OCCAR_REG (2)
376
377#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
378#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
379#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
380#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
381#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
382#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
383#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
384
385#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
386#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
387#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
388
389#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
390#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
391
392#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
393#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
394#define IOP13XX_ATUE_STAT_PME (1 << 27)
395#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
396#define IOP13XX_ATUE_STAT_IVM (1 << 25)
397#define IOP13XX_ATUE_STAT_BIST (1 << 24)
398#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
399#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
400#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
401#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
402#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
403#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
404#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
405#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
406#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
407#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
408#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
409#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
410#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
411#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
412#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
413#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
414#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
415
416#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
417#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
418#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
419#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
420#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
421#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
422#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
423#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
424#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
425#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
426#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
427#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
428#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
429#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
430#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
431
432#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
433#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
434#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
435#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
436/*=======================================================================*/
437
438/*==============================ADMA UNITS===============================*/
439#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
440#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
441#define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs))
442
443#define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0)
444#define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4)
445#define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8)
446#define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18)
447#define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c)
448#define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20)
449#define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24)
450#define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28)
451#define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c)
452#define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30)
453#define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34)
454#define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38)
455#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
456#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
457
458/*==============================XSI BRIDGE===============================*/
459#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
460#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
461#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
462#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
463 IOP13XX_PMMR_VIRT_TO_PHYS(\
464 IOP13XX_ATUE_OCCDR))\
465 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
466#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
467 IOP13XX_PMMR_VIRT_TO_PHYS(\
468 IOP13XX_ATUX_OCCDR))\
469 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
470/*=======================================================================*/
471
472#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
473 (ofs))
474
475#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
476#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
477#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
478#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
479#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
480#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
481
482#define IOP13XX_TMR_TC 0x01
483#define IOP13XX_TMR_EN 0x02
484#define IOP13XX_TMR_RELOAD 0x04
485#define IOP13XX_TMR_PRIVILEGED 0x08
486
487#define IOP13XX_TMR_RATIO_1_1 0x00
488#define IOP13XX_TMR_RATIO_4_1 0x10
489#define IOP13XX_TMR_RATIO_8_1 0x20
490#define IOP13XX_TMR_RATIO_16_1 0x30
491
492#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h
new file mode 100644
index 000000000000..b98f8f109c22
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iq81340.h
@@ -0,0 +1,31 @@
1#ifndef _IQ81340_H_
2#define _IQ81340_H_
3
4#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA
5#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000)
6
7#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */
8
9#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
10
11#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0)
12#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000)
13#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000)
14#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000)
15#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000)
16#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000)
17#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000)
18#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000)
19#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000)
20#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000)
21#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000)
22#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
23
24#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH)
25#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1)
26
27/* These are the values used in the Machine description */
28#define PHYS_IO 0xfeffff00
29#define IO_PG_OFFSET 0xffffff00
30#define BOOT_PARAM_OFFSET 0x00000100
31#endif /* _IQ81340_H_ */
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h
new file mode 100644
index 000000000000..442e35a40359
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/irqs.h
@@ -0,0 +1,207 @@
1#ifndef _IOP13XX_IRQS_H_
2#define _IOP13XX_IRQS_H_
3
4#ifndef __ASSEMBLER__
5#include <linux/types.h>
6#include <asm/system.h> /* local_irq_save */
7#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
8
9/* INTPND0 CP6 R0 Page 3
10 */
11static inline u32 read_intpnd_0(void)
12{
13 u32 val;
14 asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
15 return val;
16}
17
18/* INTPND1 CP6 R1 Page 3
19 */
20static inline u32 read_intpnd_1(void)
21{
22 u32 val;
23 asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
24 return val;
25}
26
27/* INTPND2 CP6 R2 Page 3
28 */
29static inline u32 read_intpnd_2(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
33 return val;
34}
35
36/* INTPND3 CP6 R3 Page 3
37 */
38static inline u32 read_intpnd_3(void)
39{
40 u32 val;
41 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
42 return val;
43}
44
45static inline void
46iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
47{
48 local_irq_save(*irq_flags);
49 *cp_flags = iop13xx_cp6_save();
50}
51
52static inline void
53iop13xx_cp6_irq_restore(unsigned long *cp_flags,
54 unsigned long *irq_flags)
55{
56 iop13xx_cp6_restore(*cp_flags);
57 local_irq_restore(*irq_flags);
58}
59#endif
60
61#define INTBASE 0
62#define INTSIZE_4 1
63
64/*
65 * iop34x chipset interrupts
66 */
67#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x))
68
69/*
70 * On IRQ or FIQ register
71 */
72#define IRQ_IOP13XX_ADMA0_EOT (0)
73#define IRQ_IOP13XX_ADMA0_EOC (1)
74#define IRQ_IOP13XX_ADMA1_EOT (2)
75#define IRQ_IOP13XX_ADMA1_EOC (3)
76#define IRQ_IOP13XX_ADMA2_EOT (4)
77#define IRQ_IOP13XX_ADMA2_EOC (5)
78#define IRQ_IOP134_WATCHDOG (6)
79#define IRQ_IOP13XX_RSVD_7 (7)
80#define IRQ_IOP13XX_TIMER0 (8)
81#define IRQ_IOP13XX_TIMER1 (9)
82#define IRQ_IOP13XX_I2C_0 (10)
83#define IRQ_IOP13XX_I2C_1 (11)
84#define IRQ_IOP13XX_MSG (12)
85#define IRQ_IOP13XX_MSGIBQ (13)
86#define IRQ_IOP13XX_ATU_IM (14)
87#define IRQ_IOP13XX_ATU_BIST (15)
88#define IRQ_IOP13XX_PPMU (16)
89#define IRQ_IOP13XX_COREPMU (17)
90#define IRQ_IOP13XX_CORECACHE (18)
91#define IRQ_IOP13XX_RSVD_19 (19)
92#define IRQ_IOP13XX_RSVD_20 (20)
93#define IRQ_IOP13XX_RSVD_21 (21)
94#define IRQ_IOP13XX_RSVD_22 (22)
95#define IRQ_IOP13XX_RSVD_23 (23)
96#define IRQ_IOP13XX_XINT0 (24)
97#define IRQ_IOP13XX_XINT1 (25)
98#define IRQ_IOP13XX_XINT2 (26)
99#define IRQ_IOP13XX_XINT3 (27)
100#define IRQ_IOP13XX_XINT4 (28)
101#define IRQ_IOP13XX_XINT5 (29)
102#define IRQ_IOP13XX_XINT6 (30)
103#define IRQ_IOP13XX_XINT7 (31)
104 /* IINTSRC1 bit */
105#define IRQ_IOP13XX_XINT8 (32) /* 0 */
106#define IRQ_IOP13XX_XINT9 (33) /* 1 */
107#define IRQ_IOP13XX_XINT10 (34) /* 2 */
108#define IRQ_IOP13XX_XINT11 (35) /* 3 */
109#define IRQ_IOP13XX_XINT12 (36) /* 4 */
110#define IRQ_IOP13XX_XINT13 (37) /* 5 */
111#define IRQ_IOP13XX_XINT14 (38) /* 6 */
112#define IRQ_IOP13XX_XINT15 (39) /* 7 */
113#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */
114#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */
115#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */
116#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */
117#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */
118#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */
119#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */
120#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */
121#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */
122#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */
123#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */
124#define IRQ_IOP13XX_UART0 (51) /* 19 */
125#define IRQ_IOP13XX_UART1 (52) /* 20 */
126#define IRQ_IOP13XX_PBIE (53) /* 21 */
127#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */
128#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */
129#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */
130#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */
131#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */
132#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */
133#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */
134#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */
135#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */
136#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */
137 /* IINTSRC2 bit */
138#define IRQ_IOP13XX_INTERPROC (64) /* 0 */
139#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */
140#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */
141#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */
142#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */
143#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */
144#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */
145#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */
146#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */
147#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */
148#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */
149#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */
150#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */
151#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */
152#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */
153#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */
154#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */
155#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */
156#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */
157#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */
158#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */
159#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */
160#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */
161#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */
162#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */
163#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */
164#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */
165#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */
166#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */
167#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */
168#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */
169#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */
170 /* IINTSRC3 bit */
171#define IRQ_IOP13XX_I2C_2 (96) /* 0 */
172#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */
173#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */
174#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */
175#define IRQ_IOP13XX_IMU (100) /* 4 */
176#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */
177#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */
178#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */
179#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */
180#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */
181#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */
182#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */
183#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */
184#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */
185#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
186#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
187#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
188#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */
189#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
190#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
191#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
192#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */
193#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */
194#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */
195#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */
196#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */
197#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */
198#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */
199#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */
200#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */
201#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
202#define IRQ_IOP13XX_HPI (127) /* 31 */
203
204#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
205#define NR_IRQS NR_IOP13XX_IRQS
206
207#endif /* _IOP13XX_IRQ_H_ */
diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h
new file mode 100644
index 000000000000..031a0fa78eff
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/memory.h
@@ -0,0 +1,64 @@
1#ifndef __ASM_ARCH_MEMORY_H
2#define __ASM_ARCH_MEMORY_H
3
4#include <asm/arch/hardware.h>
5
6/*
7 * Physical DRAM offset.
8 */
9#define PHYS_OFFSET UL(0x00000000)
10#define TASK_SIZE UL(0x3f000000)
11#define PAGE_OFFSET UL(0x40000000)
12#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
13
14#ifndef __ASSEMBLY__
15
16#if defined(CONFIG_ARCH_IOP13XX)
17#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
18#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
19#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
20#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
21
22/*
23 * Virtual view <-> PCI DMA view memory address translations
24 * virt_to_bus: Used to translate the virtual address to an
25 * address suitable to be passed to set_dma_addr
26 * bus_to_virt: Used to convert an address for DMA operations
27 * to an address that the kernel can use.
28 */
29
30/* RAM has 1:1 mapping on the PCIe/x Busses */
31#define __virt_to_bus(x) (__virt_to_phys(x))
32#define __bus_to_virt(x) (__phys_to_virt(x))
33
34#define virt_to_lbus(x) \
35(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \
36((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \
37((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
38((x) - PAGE_OFFSET + PHYS_OFFSET))
39
40#define lbus_to_virt(x) \
41(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
42((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
43((x) - PHYS_OFFSET + PAGE_OFFSET))
44
45/* Device is an lbus device if it is on the platform bus of the IOP13XX */
46#define is_lbus_device(dev) (dev &&\
47 (strncmp(dev->bus->name, "platform", 8) == 0))
48
49#define __arch_page_to_dma(dev, page) \
50({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
51(dma_addr_t)__virt_to_bus(page_address(page));})
52
53#define __arch_dma_to_virt(dev, addr) \
54({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
55
56#define __arch_virt_to_dma(dev, addr) \
57({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
58
59#endif /* CONFIG_ARCH_IOP13XX */
60#endif /* !ASSEMBLY */
61
62#define PFN_TO_NID(addr) (0)
63
64#endif
diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h
new file mode 100644
index 000000000000..4041f30d4cd3
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/pci.h
@@ -0,0 +1,57 @@
1#ifndef _IOP13XX_PCI_H_
2#define _IOP13XX_PCI_H_
3#include <asm/arch/irqs.h>
4#include <asm/io.h>
5
6struct pci_sys_data;
7struct hw_pci;
8int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
9struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
10void iop13xx_atu_select(struct hw_pci *plat_pci);
11void iop13xx_pci_init(void);
12void iop13xx_map_pci_memory(void);
13
14#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \
15 PCI_STATUS_SIG_TARGET_ABORT | \
16 PCI_STATUS_REC_TARGET_ABORT | \
17 PCI_STATUS_REC_TARGET_ABORT | \
18 PCI_STATUS_REC_MASTER_ABORT | \
19 PCI_STATUS_SIG_SYSTEM_ERROR | \
20 PCI_STATUS_DETECTED_PARITY)
21
22#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \
23 IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \
24 IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \
25 IOP13XX_ATUE_STAT_ERR_COR | \
26 IOP13XX_ATUE_STAT_ERR_UNCOR | \
27 IOP13XX_ATUE_STAT_CRS | \
28 IOP13XX_ATUE_STAT_DET_PAR_ERR | \
29 IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
30 IOP13XX_ATUE_STAT_SIG_TABORT | \
31 IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
32 IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
33
34#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \
35 IOP13XX_ATUX_STAT_REC_SCEM | \
36 IOP13XX_ATUX_STAT_TX_SERR | \
37 IOP13XX_ATUX_STAT_DET_PAR_ERR | \
38 IOP13XX_ATUX_STAT_INT_REC_MABORT | \
39 IOP13XX_ATUX_STAT_REC_SERR | \
40 IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
41 IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
42 IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
43 IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
44
45/* PCI interrupts
46 */
47#define ATUX_INTA IRQ_IOP13XX_XINT0
48#define ATUX_INTB IRQ_IOP13XX_XINT1
49#define ATUX_INTC IRQ_IOP13XX_XINT2
50#define ATUX_INTD IRQ_IOP13XX_XINT3
51
52#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
53#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
54#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
55#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
56
57#endif /* _IOP13XX_PCI_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
new file mode 100644
index 000000000000..ee3a62530af2
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -0,0 +1,59 @@
1/*
2 * linux/include/asm-arm/arch-iop13xx/system.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <asm/arch/iop13xx.h>
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
15
16/* WDTCR CP6 R7 Page 9 */
17static inline u32 read_wdtcr(void)
18{
19 u32 val;
20 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
21 return val;
22}
23static inline void write_wdtcr(u32 val)
24{
25 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
26}
27
28/* WDTSR CP6 R8 Page 9 */
29static inline u32 read_wdtsr(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
33 return val;
34}
35static inline void write_wdtsr(u32 val)
36{
37 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
38}
39
40#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e
41#define IOP13XX_WDTCR_EN 0xe1e1e1e1
42#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f
43#define IOP13XX_WDTCR_DIS 0xf1f1f1f1
44#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
45#define IOP13XX_WDTCR_IB_RESET (1 << 0)
46static inline void arch_reset(char mode)
47{
48 /*
49 * Reset the internal bus (warning both cores are reset)
50 */
51 u32 cp_flags = iop13xx_cp6_save();
52 write_wdtcr(IOP13XX_WDTCR_EN_ARM);
53 write_wdtcr(IOP13XX_WDTCR_EN);
54 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
55 write_wdtcr(0x1000);
56 iop13xx_cp6_restore(cp_flags);
57
58 for(;;);
59}
diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h
new file mode 100644
index 000000000000..f0c51dd97ed8
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/timex.h
@@ -0,0 +1,3 @@
1#include <asm/hardware.h>
2
3#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
new file mode 100644
index 000000000000..b9525d59b7ad
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -0,0 +1,24 @@
1#include <asm/types.h>
2#include <linux/serial_reg.h>
3#include <asm/hardware.h>
4#include <asm/processor.h>
5
6#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
7#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
8
9static inline void putc(char c)
10{
11 while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
12 cpu_relax();
13 UART_BASE[UART_TX] = c;
14}
15
16static inline void flush(void)
17{
18}
19
20/*
21 * nothing to do
22 */
23#define arch_decomp_setup()
24#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h
new file mode 100644
index 000000000000..c53456740345
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/vmalloc.h
@@ -0,0 +1,4 @@
1#ifndef _VMALLOC_H_
2#define _VMALLOC_H_
3#define VMALLOC_END 0xfa000000UL
4#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 11:44:20 -0500